1 /**************************************************************************
2 *
3 * Copyright 2022 Advanced Micro Devices, Inc.
4 *
5 * SPDX-License-Identifier: MIT
6 *
7 **************************************************************************/
8
9 #include <stdio.h>
10
11 #include "pipe/p_video_codec.h"
12
13 #include "util/u_video.h"
14
15 #include "si_pipe.h"
16 #include "radeon_vcn_enc.h"
17
18 #define RENCODE_FW_INTERFACE_MAJOR_VERSION 1
19 #define RENCODE_FW_INTERFACE_MINOR_VERSION 11
20
21 #define RENCODE_IB_PARAM_CDF_DEFAULT_TABLE_BUFFER 0x00000019
22 #define RENCODE_IB_PARAM_ENCODE_STATISTICS 0x0000001a
23
24 #define RENCODE_AV1_IB_PARAM_SPEC_MISC 0x00300001
25 #define RENCODE_AV1_IB_PARAM_BITSTREAM_INSTRUCTION 0x00300002
26
27 #define RENCODE_AV1_BITSTREAM_INSTRUCTION_END RENCODE_HEADER_INSTRUCTION_END
28 #define RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY RENCODE_HEADER_INSTRUCTION_COPY
29 #define RENCODE_AV1_BITSTREAM_INSTRUCTION_ALLOW_HIGH_PRECISION_MV 0x00000005
30 #define RENCODE_AV1_BITSTREAM_INSTRUCTION_DELTA_LF_PARAMS 0x00000006
31 #define RENCODE_AV1_BITSTREAM_INSTRUCTION_READ_INTERPOLATION_FILTER 0x00000007
32 #define RENCODE_AV1_BITSTREAM_INSTRUCTION_LOOP_FILTER_PARAMS 0x00000008
33 #define RENCODE_AV1_BITSTREAM_INSTRUCTION_TILE_INFO 0x00000009
34 #define RENCODE_AV1_BITSTREAM_INSTRUCTION_QUANTIZATION_PARAMS 0x0000000a
35 #define RENCODE_AV1_BITSTREAM_INSTRUCTION_DELTA_Q_PARAMS 0x0000000b
36 #define RENCODE_AV1_BITSTREAM_INSTRUCTION_CDEF_PARAMS 0x0000000c
37 #define RENCODE_AV1_BITSTREAM_INSTRUCTION_READ_TX_MODE 0x0000000d
38 #define RENCODE_AV1_BITSTREAM_INSTRUCTION_TILE_GROUP_OBU 0x0000000e
39
radeon_enc_sq_begin(struct radeon_encoder * enc)40 static void radeon_enc_sq_begin(struct radeon_encoder *enc)
41 {
42 rvcn_sq_header(&enc->cs, &enc->sq, true);
43 enc->mq_begin(enc);
44 rvcn_sq_tail(&enc->cs, &enc->sq);
45 }
46
radeon_enc_sq_encode(struct radeon_encoder * enc)47 static void radeon_enc_sq_encode(struct radeon_encoder *enc)
48 {
49 rvcn_sq_header(&enc->cs, &enc->sq, true);
50 enc->mq_encode(enc);
51 rvcn_sq_tail(&enc->cs, &enc->sq);
52 }
53
radeon_enc_sq_destroy(struct radeon_encoder * enc)54 static void radeon_enc_sq_destroy(struct radeon_encoder *enc)
55 {
56 rvcn_sq_header(&enc->cs, &enc->sq, true);
57 enc->mq_destroy(enc);
58 rvcn_sq_tail(&enc->cs, &enc->sq);
59 }
60
radeon_enc_op_preset(struct radeon_encoder * enc)61 static void radeon_enc_op_preset(struct radeon_encoder *enc)
62 {
63 uint32_t preset_mode;
64
65 if (enc->enc_pic.quality_modes.preset_mode == RENCODE_PRESET_MODE_SPEED &&
66 (enc->enc_pic.sample_adaptive_offset_enabled_flag &&
67 (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_HEVC)))
68 preset_mode = RENCODE_IB_OP_SET_BALANCE_ENCODING_MODE;
69 else if (enc->enc_pic.quality_modes.preset_mode == RENCODE_PRESET_MODE_QUALITY)
70 preset_mode = RENCODE_IB_OP_SET_QUALITY_ENCODING_MODE;
71 else if (enc->enc_pic.quality_modes.preset_mode == RENCODE_PRESET_MODE_HIGH_QUALITY)
72 preset_mode = RENCODE_IB_OP_SET_HIGH_QUALITY_ENCODING_MODE;
73 else if (enc->enc_pic.quality_modes.preset_mode == RENCODE_PRESET_MODE_BALANCE)
74 preset_mode = RENCODE_IB_OP_SET_BALANCE_ENCODING_MODE;
75 else
76 preset_mode = RENCODE_IB_OP_SET_SPEED_ENCODING_MODE;
77
78 RADEON_ENC_BEGIN(preset_mode);
79 RADEON_ENC_END();
80 }
81
radeon_enc_session_init(struct radeon_encoder * enc)82 static void radeon_enc_session_init(struct radeon_encoder *enc)
83 {
84 bool av1_encoding = false;
85 uint32_t av1_height = enc->enc_pic.pic_height_in_luma_samples;
86
87 switch (u_reduce_video_profile(enc->base.profile)) {
88 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
89 enc->enc_pic.session_init.encode_standard = RENCODE_ENCODE_STANDARD_H264;
90 enc->enc_pic.session_init.aligned_picture_width = align(enc->base.width, 16);
91 enc->enc_pic.session_init.aligned_picture_height = align(enc->base.height, 16);
92 break;
93 case PIPE_VIDEO_FORMAT_HEVC:
94 enc->enc_pic.session_init.encode_standard = RENCODE_ENCODE_STANDARD_HEVC;
95 enc->enc_pic.session_init.aligned_picture_width = align(enc->base.width, 64);
96 enc->enc_pic.session_init.aligned_picture_height = align(enc->base.height, 16);
97 break;
98 case PIPE_VIDEO_FORMAT_AV1:
99 enc->enc_pic.session_init.encode_standard = RENCODE_ENCODE_STANDARD_AV1;
100 enc->enc_pic.session_init.aligned_picture_width =
101 align(enc->enc_pic.pic_width_in_luma_samples, 64);
102 enc->enc_pic.session_init.aligned_picture_height =
103 align(enc->enc_pic.pic_height_in_luma_samples, 16);
104 if (!(av1_height % 8) && (av1_height % 16) && !(enc->enc_pic.enable_render_size))
105 enc->enc_pic.session_init.aligned_picture_height = av1_height + 2;
106
107 av1_encoding = true;
108 break;
109 default:
110 assert(0);
111 break;
112 }
113
114 enc->enc_pic.session_init.padding_width =
115 enc->enc_pic.session_init.aligned_picture_width - enc->base.width;
116 enc->enc_pic.session_init.padding_height =
117 enc->enc_pic.session_init.aligned_picture_height - enc->base.height;
118
119 if (av1_encoding) {
120 enc->enc_pic.session_init.padding_width =
121 enc->enc_pic.session_init.aligned_picture_width -
122 enc->enc_pic.pic_width_in_luma_samples;
123 enc->enc_pic.session_init.padding_height =
124 enc->enc_pic.session_init.aligned_picture_height - av1_height;
125
126 if (enc->enc_pic.enable_render_size)
127 enc->enc_pic.enable_render_size =
128 (enc->enc_pic.session_init.aligned_picture_width !=
129 enc->enc_pic.render_width) ||
130 (enc->enc_pic.session_init.aligned_picture_height !=
131 enc->enc_pic.render_height);
132 }
133
134 enc->enc_pic.session_init.slice_output_enabled = 0;
135 enc->enc_pic.session_init.display_remote = 0;
136 enc->enc_pic.session_init.pre_encode_mode = enc->enc_pic.quality_modes.pre_encode_mode;
137 enc->enc_pic.session_init.pre_encode_chroma_enabled = !!(enc->enc_pic.quality_modes.pre_encode_mode);
138
139 RADEON_ENC_BEGIN(enc->cmd.session_init);
140 RADEON_ENC_CS(enc->enc_pic.session_init.encode_standard);
141 RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_width);
142 RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_height);
143 RADEON_ENC_CS(enc->enc_pic.session_init.padding_width);
144 RADEON_ENC_CS(enc->enc_pic.session_init.padding_height);
145 RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_mode);
146 RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_chroma_enabled);
147 RADEON_ENC_CS(enc->enc_pic.session_init.slice_output_enabled);
148 RADEON_ENC_CS(enc->enc_pic.session_init.display_remote);
149 RADEON_ENC_CS(0);
150 RADEON_ENC_END();
151 }
152
153 /* for new temporal_id, sequence_num has to be incremented ahead. */
radeon_enc_av1_calculate_temporal_id(uint32_t sequence_num,uint32_t max_layer)154 static uint32_t radeon_enc_av1_calculate_temporal_id(uint32_t sequence_num,
155 uint32_t max_layer)
156 {
157 for (uint32_t i = 0; i <= max_layer; i++)
158 if (!(sequence_num % (1 << (max_layer - i))))
159 return i;
160
161 /* never come here */
162 assert(0);
163 return 0;
164 }
165
radeon_enc_av1_alloc_recon_slot(struct radeon_encoder * enc)166 static uint32_t radeon_enc_av1_alloc_recon_slot(struct radeon_encoder *enc)
167 {
168 uint32_t i;
169 for (i = 0; i < ARRAY_SIZE(enc->enc_pic.recon_slots); i++) {
170 if(!enc->enc_pic.recon_slots[i].in_use) {
171 enc->enc_pic.recon_slots[i].in_use = true;
172 break;
173 }
174 }
175 return i;
176 }
177
redeon_enc_av1_release_recon_slot(struct radeon_encoder * enc,uint32_t index,bool is_orphaned)178 static void redeon_enc_av1_release_recon_slot(struct radeon_encoder *enc,
179 uint32_t index,
180 bool is_orphaned)
181 {
182 assert(index < (ARRAY_SIZE(enc->enc_pic.recon_slots) - 1));
183 assert(enc->enc_pic.recon_slots[index].in_use);
184
185 if (is_orphaned)
186 enc->enc_pic.recon_slots[index].is_orphaned = true;
187 else
188 enc->enc_pic.recon_slots[index].in_use = false;
189 }
190
radeon_enc_av1_alloc_curr_frame(struct radeon_encoder * enc,uint32_t frame_id,uint32_t temporal_id,uint32_t mark_long_term,void * frame_signature,enum pipe_av1_enc_frame_type frame_type)191 static uint32_t radeon_enc_av1_alloc_curr_frame(struct radeon_encoder *enc,
192 uint32_t frame_id,
193 uint32_t temporal_id,
194 uint32_t mark_long_term, /* mark it as long term reference */
195 void *frame_signature,
196 enum pipe_av1_enc_frame_type frame_type)
197 {
198 uint32_t i = 0;
199
200 assert(frame_signature);
201
202 for (i = 0; i < ARRAY_SIZE(enc->enc_pic.frames); i++) {
203 rvcn_enc_av1_ref_frame_t *frame = &enc->enc_pic.frames[i];
204 if (!frame->in_use) {
205 frame->in_use = true;
206 frame->frame_id = frame_id;
207 frame->temporal_id = temporal_id;
208 frame->slot_id = radeon_enc_av1_alloc_recon_slot(enc);
209 frame->frame_type = frame_type;
210 frame->frame_signature = frame_signature;
211 frame->is_ltr = !!(mark_long_term);
212 if (frame->is_ltr)
213 frame->ltr_seq = enc->enc_pic.av1_ltr_seq++;
214 break;
215 }
216 }
217
218 return i;
219 }
220
radeon_enc_av1_release_ref_frame(struct radeon_encoder * enc,uint32_t index,bool is_recon_orphan)221 static void radeon_enc_av1_release_ref_frame(struct radeon_encoder *enc,
222 uint32_t index,
223 bool is_recon_orphan)
224 {
225 assert(index < (ARRAY_SIZE(enc->enc_pic.frames) - 1));
226
227 redeon_enc_av1_release_recon_slot(enc,
228 enc->enc_pic.frames[index].slot_id,
229 is_recon_orphan);
230 enc->enc_pic.frames[index].in_use = false;
231 }
232
233 /* save 1 recon slot in max temporal layer = 4 case */
radeon_enc_av1_temporal_4_extra_release(struct radeon_encoder * enc,uint32_t temporal_id)234 static void radeon_enc_av1_temporal_4_extra_release(struct radeon_encoder *enc,
235 uint32_t temporal_id)
236 {
237 uint32_t i = 0;
238
239 if (temporal_id == 0)
240 enc->enc_pic.count_last_layer = 0;
241 else if (temporal_id == 3)
242 enc->enc_pic.count_last_layer++;
243
244 /* since temporal ID = 1 picture will not be used in this
245 * temporal period, that can be released */
246 if (enc->enc_pic.count_last_layer == 4) {
247 for (i = 0; i < ARRAY_SIZE(enc->enc_pic.frames); i++) {
248 rvcn_enc_av1_ref_frame_t *frame = &enc->enc_pic.frames[i];
249 if (frame->in_use && (frame->temporal_id == 1)) {
250 radeon_enc_av1_release_ref_frame(enc, i, false);
251 break;
252 }
253 }
254 }
255 }
256
radeon_enc_av1_pre_scan_frames(struct radeon_encoder * enc,uint32_t temporal_id)257 static void radeon_enc_av1_pre_scan_frames(struct radeon_encoder *enc,
258 uint32_t temporal_id)
259 {
260 uint32_t i = 0;
261
262 /* checking long term frames if it reached the limit, it needs to
263 * release the oldest. */
264 if (enc->enc_pic.av1_mark_long_term_reference) {
265 int cnt = 0;
266 uint32_t min_seq = (uint32_t)-1;
267 uint32_t min_seq_idx = 0;
268 for (i = 0; i < ARRAY_SIZE(enc->enc_pic.frames); i++) {
269 rvcn_enc_av1_ref_frame_t *frame = &enc->enc_pic.frames[i];
270 if (frame->in_use && frame->is_ltr) {
271 if (frame->ltr_seq < min_seq) {
272 min_seq = frame->ltr_seq;
273 min_seq_idx = i;
274 }
275 cnt++;
276
277 /* this means some LTR ref buffer has been re-used. */
278 if (enc->enc_pic.av1_recon_frame == frame->frame_signature)
279 RVID_ERR("recon duplicated! it could refer to a wrong frame!\n");
280 }
281 }
282 /* release the frame with minimum ltr seq number (oldest),
283 * this check is happening on each frame, the total number
284 * of LTR is limited by RENCODE_VCN4_AV1_MAX_NUM_LTR.*/
285 if (cnt > RENCODE_VCN4_AV1_MAX_NUM_LTR)
286 radeon_enc_av1_release_ref_frame(enc, min_seq_idx, false);
287 }
288
289 for (i = 0; i < ARRAY_SIZE(enc->enc_pic.recon_slots); i++) {
290 rvcn_enc_av1_recon_slot_t *slot = &enc->enc_pic.recon_slots[i];
291 if (slot->in_use && slot->is_orphaned) {
292 slot->in_use = false;
293 slot->is_orphaned = false;
294 }
295 }
296
297 for (i = 0; i < ARRAY_SIZE(enc->enc_pic.frames); i++) {
298 rvcn_enc_av1_ref_frame_t *frame = &enc->enc_pic.frames[i];
299 if (frame->in_use) {
300 if (temporal_id < frame->temporal_id)
301 radeon_enc_av1_release_ref_frame(enc, i, false);
302 else if (temporal_id == frame->temporal_id && (!frame->is_ltr))
303 radeon_enc_av1_release_ref_frame(enc, i, true);
304 }
305 }
306 }
307
radeon_enc_av1_search_requested_reference(struct radeon_encoder * enc,uint32_t * idx)308 static bool radeon_enc_av1_search_requested_reference(
309 struct radeon_encoder *enc,
310 uint32_t *idx)
311 {
312 bool find = false;
313 /* Here is the assumption, the 3rd item of ref_frame_ctrl_l0
314 indicates which slot it needs to find in ref_frame_idx[], and
315 from ref_frame_idx to find the requested reference frame
316 in ref_list[] */
317 #define RENCODE_AV1_REF_CTRL_L0_THIRD_ITEM (0x1c0) /* 111 000 000 */
318 uint32_t marked_ref_frame_idx = (RENCODE_AV1_REF_CTRL_L0_THIRD_ITEM &
319 enc->enc_pic.av1_ref_frame_ctrl_l0) >> 6;
320 /* valid marked_ref_frame_idx > 0 */
321 if (marked_ref_frame_idx) {
322 uint32_t requested_frame_idx =
323 enc->enc_pic.av1_ref_frame_idx[marked_ref_frame_idx - 1];
324 void *request_signature = NULL;
325
326 if (requested_frame_idx >= RENCDOE_AV1_NUM_REF_FRAMES)
327 goto end;
328
329 request_signature = enc->enc_pic.av1_ref_list[requested_frame_idx];
330 for (uint32_t i = 0; i < ARRAY_SIZE((enc->enc_pic.frames)); i++) {
331 rvcn_enc_av1_ref_frame_t *frame = &enc->enc_pic.frames[i];
332 if (frame->in_use &&
333 frame->is_ltr &&
334 (request_signature == frame->frame_signature)) {
335 find = true;
336 /* increase the frame seq number after found, when it
337 * reaches the maximum limit, this found one will not
338 * be released. */
339 frame->ltr_seq = enc->enc_pic.av1_ltr_seq++;
340 *idx = i;
341 break;
342 }
343 }
344 }
345 end:
346 return find;
347 }
348
radeon_enc_av1_obtain_ref0_frame(struct radeon_encoder * enc,uint32_t temporal_id)349 static uint32_t radeon_enc_av1_obtain_ref0_frame(struct radeon_encoder *enc,
350 uint32_t temporal_id)
351 {
352 /* when only ltr frames in DPB, it needs to use the biggest ltr_seq
353 * one (latest) for reference, instead of the first one met. */
354 uint32_t i = 0;
355 uint32_t ret_idx = 0;
356 uint32_t max_seq = 0;
357 uint32_t max_seq_idx = 0;
358 for (i = 0; i < ARRAY_SIZE(enc->enc_pic.frames); i++) {
359 rvcn_enc_av1_ref_frame_t *frame = &enc->enc_pic.frames[i];
360 if (frame->in_use && frame->is_ltr && (frame->ltr_seq >= max_seq)) {
361 max_seq = frame->ltr_seq;
362 max_seq_idx = i;
363 }
364 }
365 for (i = ARRAY_SIZE(enc->enc_pic.frames); i > 0; i--) {
366 rvcn_enc_av1_ref_frame_t *frame = &enc->enc_pic.frames[i - 1];
367 if (frame->in_use && frame->temporal_id <= temporal_id) {
368 if (frame->is_ltr)
369 ret_idx = max_seq_idx;
370 else
371 ret_idx = i - 1;
372
373 break;
374 }
375 }
376 return ret_idx;
377 }
378
radeon_enc_reset_av1_dpb_frames(struct radeon_encoder * enc)379 static void radeon_enc_reset_av1_dpb_frames(struct radeon_encoder *enc)
380 {
381 for (int i = 0; i < ARRAY_SIZE(enc->enc_pic.frames); i++)
382 enc->enc_pic.frames[i] = (rvcn_enc_av1_ref_frame_t) {
383 .in_use = false,
384 .is_ltr = false,
385 .ltr_seq = 0,
386 .frame_id = 0,
387 .temporal_id = 0,
388 .slot_id = 0,
389 .frame_type = 0,
390 .frame_signature = NULL,
391 };
392
393 for (int i = 0; i < ARRAY_SIZE(enc->enc_pic.recon_slots); i++)
394 enc->enc_pic.recon_slots[i] = (rvcn_enc_av1_recon_slot_t) {
395 .in_use = false,
396 .is_orphaned = false,
397 };
398 }
399
radeon_enc_av1_dpb_management(struct radeon_encoder * enc)400 static void radeon_enc_av1_dpb_management(struct radeon_encoder *enc)
401 {
402 struct radeon_enc_pic *pic = &enc->enc_pic;
403 uint32_t current_slot;
404 uint32_t ref_slot;
405 uint32_t request_idx;
406 bool find = false;
407
408 if (pic->frame_type == PIPE_AV1_ENC_FRAME_TYPE_KEY) {
409 pic->frame_id = 0;
410 pic->temporal_seq_num = 0;
411 pic->temporal_id = 0;
412 pic->reference_delta_frame_id = 0;
413 pic->reference_frame_index = 0;
414 pic->last_frame_type = PIPE_AV1_ENC_FRAME_TYPE_KEY;
415 pic->av1_ltr_seq = 0;
416 current_slot = 0;
417 ref_slot = 0;
418 request_idx = 0;
419 radeon_enc_reset_av1_dpb_frames(enc);
420 } else {
421 find = radeon_enc_av1_search_requested_reference(enc, &request_idx);
422 if (pic->av1_mark_long_term_reference || find)
423 pic->temporal_seq_num = 0; /*for ltr, always temporal_id = 0 */
424 else
425 pic->temporal_seq_num++;
426
427 pic->temporal_id = radeon_enc_av1_calculate_temporal_id(pic->temporal_seq_num,
428 pic->num_temporal_layers - 1);
429 if (find)
430 pic->reference_frame_index = request_idx;
431 else
432 pic->reference_frame_index =
433 radeon_enc_av1_obtain_ref0_frame(enc, pic->temporal_id);
434 ref_slot = pic->frames[pic->reference_frame_index].slot_id;
435 pic->last_frame_type = pic->frames[pic->reference_frame_index].frame_type;
436 radeon_enc_av1_pre_scan_frames(enc, pic->temporal_id);
437 }
438
439 if (pic->num_temporal_layers == 4)
440 radeon_enc_av1_temporal_4_extra_release(enc, pic->temporal_id);
441
442 pic->frame_to_show_map_index = pic->reference_frame_index;
443
444 for (int i = 0; i < ARRAY_SIZE(pic->frames); i++)
445 pic->reference_order_hint[i] = pic->frames[i].frame_id;
446
447 pic->reference_delta_frame_id = pic->frame_id -
448 pic->frames[pic->reference_frame_index].frame_id;
449 current_slot = radeon_enc_av1_alloc_curr_frame(enc, pic->frame_id,
450 pic->temporal_id,
451 pic->av1_mark_long_term_reference,
452 pic->av1_recon_frame,
453 pic->frame_type);
454 if (pic->frame_type == PIPE_AV1_ENC_FRAME_TYPE_KEY ||
455 pic->frame_type == PIPE_AV1_ENC_FRAME_TYPE_SWITCH ||
456 ((pic->frame_type == PIPE_AV1_ENC_FRAME_TYPE_SHOW_EXISTING) &&
457 pic->last_frame_type == PIPE_AV1_ENC_FRAME_TYPE_KEY))
458 pic->refresh_frame_flags = 255;
459 else
460 pic->refresh_frame_flags = 1 << current_slot;
461
462 pic->enc_params.reference_picture_index = ref_slot;
463 pic->enc_params.reconstructed_picture_index = pic->frames[current_slot].slot_id;
464 pic->display_frame_id = pic->frame_id;
465 pic->order_hint = pic->frame_id;
466 }
467
radeon_enc_spec_misc_av1(struct radeon_encoder * enc)468 static void radeon_enc_spec_misc_av1(struct radeon_encoder *enc)
469 {
470 uint32_t num_of_tiles = enc->enc_pic.av1_spec_misc.num_tiles_per_picture;
471 uint32_t threshold_low, threshold_high;
472 uint32_t num_rows;
473 uint32_t num_columns;
474
475 num_rows = PIPE_ALIGN_IN_BLOCK_SIZE(enc->enc_pic.session_init.aligned_picture_height,
476 PIPE_AV1_ENC_SB_SIZE);
477 num_columns = PIPE_ALIGN_IN_BLOCK_SIZE(enc->enc_pic.session_init.aligned_picture_width,
478 PIPE_AV1_ENC_SB_SIZE);
479
480 if (num_rows > 64) {
481 /* max tile size 4096 x 2304 */
482 threshold_low = ((num_rows + 63) / 64) * ((num_columns + 35) / 36);
483 num_of_tiles = (num_of_tiles & 1) ? num_of_tiles - 1 : num_of_tiles;
484 } else
485 threshold_low = 1;
486
487 threshold_high = num_rows > 16 ? 16 : num_rows;
488 threshold_high = num_columns > 64 ? threshold_high * 2 : threshold_high;
489
490 num_of_tiles = CLAMP(num_of_tiles, threshold_low, threshold_high);
491
492 /* in case of multiple tiles, it should be an obu frame */
493 if (num_of_tiles > 1)
494 enc->enc_pic.stream_obu_frame = 1;
495 else
496 enc->enc_pic.stream_obu_frame = enc->enc_pic.is_obu_frame;
497
498 enc->enc_pic.av1_spec_misc.num_tiles_per_picture = num_of_tiles;
499
500 RADEON_ENC_BEGIN(enc->cmd.spec_misc_av1);
501 RADEON_ENC_CS(enc->enc_pic.av1_spec_misc.palette_mode_enable);
502 RADEON_ENC_CS(enc->enc_pic.av1_spec_misc.mv_precision);
503 RADEON_ENC_CS(enc->enc_pic.av1_spec_misc.cdef_mode);
504 RADEON_ENC_CS(enc->enc_pic.av1_spec_misc.disable_cdf_update);
505 RADEON_ENC_CS(enc->enc_pic.av1_spec_misc.disable_frame_end_update_cdf);
506 RADEON_ENC_CS(enc->enc_pic.av1_spec_misc.num_tiles_per_picture);
507 RADEON_ENC_CS(0);
508 RADEON_ENC_CS(0);
509 RADEON_ENC_END();
510 }
511
radeon_enc_cdf_default_table(struct radeon_encoder * enc)512 static void radeon_enc_cdf_default_table(struct radeon_encoder *enc)
513 {
514 bool use_cdf_default = enc->enc_pic.frame_type == PIPE_AV1_ENC_FRAME_TYPE_KEY ||
515 enc->enc_pic.frame_type == PIPE_AV1_ENC_FRAME_TYPE_INTRA_ONLY ||
516 enc->enc_pic.frame_type == PIPE_AV1_ENC_FRAME_TYPE_SWITCH;
517
518 enc->enc_pic.av1_cdf_default_table.use_cdf_default = use_cdf_default ? 1 : 0;
519
520 RADEON_ENC_BEGIN(enc->cmd.cdf_default_table_av1);
521 RADEON_ENC_CS(enc->enc_pic.av1_cdf_default_table.use_cdf_default);
522 RADEON_ENC_READWRITE(enc->cdf->res->buf, enc->cdf->res->domains, 0);
523 RADEON_ENC_ADDR_SWAP();
524 RADEON_ENC_END();
525 }
526
radeon_enc_av1_header_size_offset(struct radeon_encoder * enc)527 uint8_t *radeon_enc_av1_header_size_offset(struct radeon_encoder *enc)
528 {
529 uint32_t *bits_start = enc->enc_pic.copy_start + 3;
530 assert(enc->bits_output % 8 == 0); /* should be always byte aligned */
531 return (uint8_t *)(bits_start) + (enc->bits_output >> 3);
532 }
533
radeon_enc_av1_temporal_delimiter(struct radeon_encoder * enc)534 static void radeon_enc_av1_temporal_delimiter(struct radeon_encoder *enc)
535 {
536 bool use_extension_flag;
537
538 /* obu header () */
539 /* obu_forbidden_bit */
540 radeon_enc_code_fixed_bits(enc, 0, 1);
541 /* obu_type */
542 radeon_enc_code_fixed_bits(enc, RENCODE_OBU_TYPE_TEMPORAL_DELIMITER, 4);
543 /* obu_extension_flag */
544 use_extension_flag = (enc->enc_pic.num_temporal_layers) > 1 &&
545 (enc->enc_pic.temporal_id) > 0 ? 1 : 0;
546 radeon_enc_code_fixed_bits(enc, use_extension_flag ? 1 : 0, 1);
547 /* obu_has_size_field */
548 radeon_enc_code_fixed_bits(enc, 1, 1);
549 /* obu_reserved_1bit */
550 radeon_enc_code_fixed_bits(enc, 0, 1);
551
552 if (use_extension_flag) {
553 radeon_enc_code_fixed_bits(enc, enc->enc_pic.temporal_id, 3);
554 radeon_enc_code_fixed_bits(enc, 0, 2); /* spatial_id should always be zero */
555 radeon_enc_code_fixed_bits(enc, 0, 3); /* reserved 3 bits */
556 }
557
558 radeon_enc_code_fixed_bits(enc, 0, 8); /* obu has size */
559 }
560
radeon_enc_av1_sequence_header(struct radeon_encoder * enc)561 static void radeon_enc_av1_sequence_header(struct radeon_encoder *enc)
562 {
563 uint8_t *size_offset;
564 uint8_t obu_size_bin[2];
565 uint32_t obu_size;
566 uint32_t width_bits;
567 uint32_t height_bits;
568 uint32_t max_temporal_layers = enc->enc_pic.num_temporal_layers;
569
570 /* obu_header() */
571 /* obu_forbidden_bit */
572 radeon_enc_code_fixed_bits(enc, 0, 1);
573 /* obu_type */
574 radeon_enc_code_fixed_bits(enc, RENCODE_OBU_TYPE_SEQUENCE_HEADER, 4);
575 /* obu_extension_flag */
576 radeon_enc_code_fixed_bits(enc, 0, 1);
577 /* obu_has_size_field */
578 radeon_enc_code_fixed_bits(enc, 1, 1);
579 /* obu_reserved_1bit */
580 radeon_enc_code_fixed_bits(enc, 0, 1);
581
582 /* obu_size, use two bytes for header, the size will be written in afterwards */
583 size_offset = radeon_enc_av1_header_size_offset(enc);
584 radeon_enc_code_fixed_bits(enc, 0, 2 * 8);
585
586 /* sequence_header_obu() */
587 /* seq_profile, only seq_profile = 0 is supported */
588 radeon_enc_code_fixed_bits(enc, 0, 3);
589 /* still_picture */
590 radeon_enc_code_fixed_bits(enc, 0, 1);
591 /* reduced_still_picture_header */
592 radeon_enc_code_fixed_bits(enc, 0, 1);
593 /* timing_info_present_flag */
594 radeon_enc_code_fixed_bits(enc, enc->enc_pic.timing_info_present ? 1 : 0, 1);
595
596 if (enc->enc_pic.timing_info_present) {
597 /* num_units_in_display_tick */
598 radeon_enc_code_fixed_bits(enc, enc->enc_pic.av1_timing_info.num_units_in_display_tick, 32);
599 /* time_scale */
600 radeon_enc_code_fixed_bits(enc, enc->enc_pic.av1_timing_info.time_scale, 32);
601 /* equal_picture_interval */
602 radeon_enc_code_fixed_bits(enc, enc->enc_pic.timing_info_equal_picture_interval, 1);
603 /* num_ticks_per_picture_minus_1 */
604 if (enc->enc_pic.timing_info_equal_picture_interval)
605 radeon_enc_code_uvlc(enc, enc->enc_pic.av1_timing_info.num_tick_per_picture_minus1);
606 /* decoder_model_info_present_flag */
607 radeon_enc_code_fixed_bits(enc, 0, 1);
608 }
609
610 /* initial_display_delay_present_flag */
611 radeon_enc_code_fixed_bits(enc, 0, 1);
612 /* operating_points_cnt_minus_1 */
613 radeon_enc_code_fixed_bits(enc, max_temporal_layers - 1, 5);
614
615 for (uint32_t i = 0; i < max_temporal_layers; i++) {
616 uint32_t operating_point_idc = 0;
617 if (max_temporal_layers > 1) {
618 operating_point_idc = (1 << (max_temporal_layers - i)) - 1;
619 operating_point_idc |= 0x100; /* spatial layer not supported */
620 }
621 radeon_enc_code_fixed_bits(enc, operating_point_idc, 12);
622 radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_level_idc, 5);
623 if (enc->enc_pic.general_level_idc > 7)
624 radeon_enc_code_fixed_bits(enc, 0, 1); /* tier */
625 }
626
627 /* frame_width_bits_minus_1 */
628 width_bits = radeon_enc_value_bits(enc->enc_pic.session_init.aligned_picture_width - 1);
629 radeon_enc_code_fixed_bits(enc, width_bits - 1, 4);
630 /* frame_height_bits_minus_1 */
631 height_bits = radeon_enc_value_bits(enc->enc_pic.session_init.aligned_picture_height - 1);
632 radeon_enc_code_fixed_bits(enc, height_bits - 1, 4);
633 /* max_frame_width_minus_1 */
634 radeon_enc_code_fixed_bits(enc, enc->enc_pic.session_init.aligned_picture_width - 1,
635 width_bits);
636 /* max_frame_height_minus_1 */
637 radeon_enc_code_fixed_bits(enc, enc->enc_pic.session_init.aligned_picture_height - 1,
638 height_bits);
639
640 /* frame_id_numbers_present_flag */
641 radeon_enc_code_fixed_bits(enc, enc->enc_pic.frame_id_numbers_present, 1);
642 if (enc->enc_pic.frame_id_numbers_present) {
643 /* delta_frame_id_length_minus_2 */
644 radeon_enc_code_fixed_bits(enc, RENCODE_AV1_DELTA_FRAME_ID_LENGTH - 2, 4);
645 /* additional_frame_id_length_minus_1 */
646 radeon_enc_code_fixed_bits(enc, RENCODE_AV1_ADDITIONAL_FRAME_ID_LENGTH - 1, 3);
647 }
648
649 /* use_128x128_superblock */
650 radeon_enc_code_fixed_bits(enc, 0, 1);
651 /* enable_filter_intra */
652 radeon_enc_code_fixed_bits(enc, 0, 1);
653 /* enable_intra_edge_filter */
654 radeon_enc_code_fixed_bits(enc, 0, 1);
655 /* enable_interintra_compound */
656 radeon_enc_code_fixed_bits(enc, 0, 1);
657 /* enable_masked_compound */
658 radeon_enc_code_fixed_bits(enc, 0, 1);
659 /* enable_warped_motion */
660 radeon_enc_code_fixed_bits(enc, 0, 1);
661 /* enable_dual_filter */
662 radeon_enc_code_fixed_bits(enc, 0, 1);
663 /* enable_order_hint */
664 radeon_enc_code_fixed_bits(enc, enc->enc_pic.enable_order_hint ? 1 : 0, 1);
665
666 if (enc->enc_pic.enable_order_hint) {
667 /* enable_jnt_comp */
668 radeon_enc_code_fixed_bits(enc, 0, 1);
669 /* enable_ref_frame_mvs */
670 radeon_enc_code_fixed_bits(enc, 0, 1);
671 }
672
673 /* seq_choose_screen_content_tools */
674 radeon_enc_code_fixed_bits(enc, enc->enc_pic.disable_screen_content_tools ? 0 : 1, 1);
675 if (enc->enc_pic.disable_screen_content_tools)
676 /* seq_force_screen_content_tools */
677 radeon_enc_code_fixed_bits(enc, 0, 1);
678 else
679 /* seq_choose_integer_mv */
680 radeon_enc_code_fixed_bits(enc, 1, 1);
681
682 if(enc->enc_pic.enable_order_hint)
683 /* order_hint_bits_minus_1 */
684 radeon_enc_code_fixed_bits(enc, enc->enc_pic.order_hint_bits - 1, 3);
685
686 /* enable_superres */
687 radeon_enc_code_fixed_bits(enc, 0, 1);
688 /* enable_cdef */
689 radeon_enc_code_fixed_bits(enc, enc->enc_pic.av1_spec_misc.cdef_mode ? 1 : 0, 1);
690 /* enable_restoration */
691 radeon_enc_code_fixed_bits(enc, 0, 1);
692 /* high_bitdepth */
693 radeon_enc_code_fixed_bits(enc, enc->enc_pic.enc_output_format.output_color_bit_depth, 1);
694 /* mono_chrome */
695 radeon_enc_code_fixed_bits(enc, 0, 1);
696 /* color_description_present_flag */
697 radeon_enc_code_fixed_bits(enc, enc->enc_pic.enable_color_description ? 1 : 0, 1);
698
699 if(enc->enc_pic.enable_color_description) {
700 /* color_primaries */
701 radeon_enc_code_fixed_bits(enc, enc->enc_pic.av1_color_description.color_primaries, 8);
702 /* transfer_characteristics */
703 radeon_enc_code_fixed_bits(enc, enc->enc_pic.av1_color_description.transfer_characteristics, 8);
704 /* matrix_coefficients */
705 radeon_enc_code_fixed_bits(enc, enc->enc_pic.av1_color_description.maxtrix_coefficients, 8);
706 }
707 /* color_range */
708 radeon_enc_code_fixed_bits(enc, enc->enc_pic.av1_color_description.color_range, 1);
709 /* chroma_sample_position */
710 radeon_enc_code_fixed_bits(enc, enc->enc_pic.av1_color_description.chroma_sample_position, 2);
711 /* separate_uv_delta_q */
712 radeon_enc_code_fixed_bits(enc, 0, 1);
713 /* film_grain_params_present */
714 radeon_enc_code_fixed_bits(enc, 0, 1);
715
716 /* trailing_one_bit */
717 radeon_enc_code_fixed_bits(enc, 1, 1);
718 radeon_enc_byte_align(enc);
719
720 /* obu_size doesn't include the bytes within obu_header
721 * or obu_size syntax element (6.2.1), here we use 2 bytes for obu_size syntax
722 * which needs to be removed from the size.
723 */
724 obu_size = (uint32_t)(radeon_enc_av1_header_size_offset(enc) - size_offset - 2);
725 radeon_enc_code_leb128(obu_size_bin, obu_size, 2);
726
727 /* update obu_size */
728 for (int i = 0; i < sizeof(obu_size_bin); i++) {
729 uint8_t *p = (uint8_t *)((((uintptr_t)size_offset & 3) ^ 3) | ((uintptr_t)size_offset & ~3));
730 *p = obu_size_bin[i];
731 size_offset++;
732 }
733 }
734
radeon_enc_av1_frame_header(struct radeon_encoder * enc,bool frame_header)735 static void radeon_enc_av1_frame_header(struct radeon_encoder *enc, bool frame_header)
736 {
737 uint32_t i;
738 uint32_t extension_flag = enc->enc_pic.num_temporal_layers > 1 ? 1 : 0;
739 bool show_existing = false;
740 bool frame_is_intra = enc->enc_pic.frame_type == PIPE_AV1_ENC_FRAME_TYPE_KEY ||
741 enc->enc_pic.frame_type == PIPE_AV1_ENC_FRAME_TYPE_INTRA_ONLY;
742
743 radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY, 0);
744 /* obu_header() */
745 /* obu_forbidden_bit */
746 radeon_enc_code_fixed_bits(enc, 0, 1);
747 /* obu_type */
748 radeon_enc_code_fixed_bits(enc, frame_header ? RENCODE_OBU_TYPE_FRAME_HEADER
749 : RENCODE_OBU_TYPE_FRAME, 4);
750 /* obu_extension_flag */
751 radeon_enc_code_fixed_bits(enc, extension_flag, 1);
752 /* obu_has_size_field */
753 radeon_enc_code_fixed_bits(enc, 1, 1);
754 /* obu_reserved_1bit */
755 radeon_enc_code_fixed_bits(enc, 0, 1);
756 if (extension_flag) {
757 radeon_enc_code_fixed_bits(enc, enc->enc_pic.temporal_id, 3);
758 radeon_enc_code_fixed_bits(enc, 0, 2);
759 radeon_enc_code_fixed_bits(enc, 0, 3);
760 }
761
762 radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_OBU_SIZE, 0);
763
764 /* uncompressed_header() */
765 radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY, 0);
766 /* show_existing_frame */
767 show_existing = enc->enc_pic.frame_type == PIPE_AV1_ENC_FRAME_TYPE_SHOW_EXISTING;
768 radeon_enc_code_fixed_bits(enc, show_existing ? 1 : 0, 1);
769 /* if (show_existing_frame == 1) */
770 if(show_existing) {
771 /* frame_to_show_map_idx */
772 radeon_enc_code_fixed_bits(enc, enc->enc_pic.frame_to_show_map_index, 3);
773 /* display_frame_id */
774 if (enc->enc_pic.frame_id_numbers_present)
775 radeon_enc_code_fixed_bits(enc, enc->enc_pic.display_frame_id,
776 RENCODE_AV1_DELTA_FRAME_ID_LENGTH +
777 RENCODE_AV1_ADDITIONAL_FRAME_ID_LENGTH);
778 } else {
779 /* frame_type */
780 radeon_enc_code_fixed_bits(enc, enc->enc_pic.frame_type, 2);
781 /* show_frame */
782 radeon_enc_code_fixed_bits(enc, 1, 1);
783 bool error_resilient_mode = false;
784 if ((enc->enc_pic.frame_type == PIPE_AV1_ENC_FRAME_TYPE_SWITCH) ||
785 (enc->enc_pic.frame_type == PIPE_AV1_ENC_FRAME_TYPE_KEY))
786 error_resilient_mode = true;
787 else {
788 /* error_resilient_mode */
789 radeon_enc_code_fixed_bits(enc, enc->enc_pic.enable_error_resilient_mode ? 1 : 0, 1);
790 error_resilient_mode = enc->enc_pic.enable_error_resilient_mode;
791 }
792 /* disable_cdf_update */
793 radeon_enc_code_fixed_bits(enc, enc->enc_pic.av1_spec_misc.disable_cdf_update ? 1 : 0, 1);
794
795 bool allow_screen_content_tools = false;
796 if (!enc->enc_pic.disable_screen_content_tools) {
797 /* allow_screen_content_tools */
798 allow_screen_content_tools = enc->enc_pic.av1_spec_misc.palette_mode_enable ||
799 enc->enc_pic.force_integer_mv;
800 radeon_enc_code_fixed_bits(enc, allow_screen_content_tools ? 1 : 0, 1);
801 }
802
803 if (allow_screen_content_tools)
804 /* force_integer_mv */
805 radeon_enc_code_fixed_bits(enc, enc->enc_pic.force_integer_mv ? 1 : 0, 1);
806
807 if (enc->enc_pic.frame_id_numbers_present)
808 /* current_frame_id */
809 radeon_enc_code_fixed_bits(enc, enc->enc_pic.frame_id,
810 RENCODE_AV1_DELTA_FRAME_ID_LENGTH +
811 RENCODE_AV1_ADDITIONAL_FRAME_ID_LENGTH);
812
813 bool frame_size_override = false;
814 if (enc->enc_pic.frame_type == PIPE_AV1_ENC_FRAME_TYPE_SWITCH)
815 frame_size_override = true;
816 else {
817 /* frame_size_override_flag */
818 frame_size_override = false;
819 radeon_enc_code_fixed_bits(enc, 0, 1);
820 }
821
822 if (enc->enc_pic.enable_order_hint)
823 radeon_enc_code_fixed_bits(enc, enc->enc_pic.order_hint, enc->enc_pic.order_hint_bits);
824
825 if (!frame_is_intra && !error_resilient_mode)
826 /* primary_ref_frame */
827 radeon_enc_code_fixed_bits(enc, 0, 3); /* always LAST_FRAME(1) */
828
829 if ((enc->enc_pic.frame_type != PIPE_AV1_ENC_FRAME_TYPE_SWITCH) &&
830 (enc->enc_pic.frame_type != PIPE_AV1_ENC_FRAME_TYPE_KEY))
831 /* refresh_frame_flags */
832 radeon_enc_code_fixed_bits(enc, enc->enc_pic.refresh_frame_flags, 8);
833
834 if ((!frame_is_intra || enc->enc_pic.refresh_frame_flags != 0xff) &&
835 error_resilient_mode && enc->enc_pic.enable_order_hint)
836 for (i = 0; i < RENCDOE_AV1_NUM_REF_FRAMES; i++)
837 /* ref_order_hint */
838 radeon_enc_code_fixed_bits(enc, enc->enc_pic.reference_order_hint[i], enc->enc_pic.order_hint_bits);
839
840 if (frame_is_intra) {
841 /* render_and_frame_size_different */
842 radeon_enc_code_fixed_bits(enc, enc->enc_pic.enable_render_size ? 1 : 0, 1);
843 if (enc->enc_pic.enable_render_size) {
844 /* render_width_minus_1 */
845 radeon_enc_code_fixed_bits(enc, enc->enc_pic.render_width - 1, 16);
846 /* render_height_minus_1 */
847 radeon_enc_code_fixed_bits(enc, enc->enc_pic.render_height - 1, 16);
848 }
849 if (!enc->enc_pic.disable_screen_content_tools &&
850 (enc->enc_pic.av1_spec_misc.palette_mode_enable || enc->enc_pic.force_integer_mv))
851 /* allow_intrabc */
852 radeon_enc_code_fixed_bits(enc, 0, 1);
853 } else {
854 if (enc->enc_pic.enable_order_hint)
855 /* frame_refs_short_signaling */
856 radeon_enc_code_fixed_bits(enc, 0, 1);
857 for (i = 0; i < RENCDOE_AV1_REFS_PER_FRAME; i++) {
858 /* ref_frame_idx */
859 radeon_enc_code_fixed_bits(enc, enc->enc_pic.reference_frame_index, 3);
860 if (enc->enc_pic.frame_id_numbers_present)
861 radeon_enc_code_fixed_bits(enc,
862 enc->enc_pic.reference_delta_frame_id - 1,
863 RENCODE_AV1_DELTA_FRAME_ID_LENGTH);
864 }
865
866 if (frame_size_override && !error_resilient_mode)
867 /* found_ref */
868 radeon_enc_code_fixed_bits(enc, 1, 1);
869 else {
870 if(frame_size_override) {
871 /* frame_width_minus_1 */
872 uint32_t used_bits =
873 radeon_enc_value_bits(enc->enc_pic.session_init.aligned_picture_width - 1);
874 radeon_enc_code_fixed_bits(enc, enc->enc_pic.session_init.aligned_picture_width - 1,
875 used_bits);
876 /* frame_height_minus_1 */
877 used_bits = radeon_enc_value_bits(enc->enc_pic.session_init.aligned_picture_height - 1);
878 radeon_enc_code_fixed_bits(enc, enc->enc_pic.session_init.aligned_picture_height - 1,
879 used_bits);
880 }
881 /* render_and_frame_size_different */
882 radeon_enc_code_fixed_bits(enc, enc->enc_pic.enable_render_size ? 1 : 0, 1);
883 if (enc->enc_pic.enable_render_size) {
884 /* render_width_minus_1 */
885 radeon_enc_code_fixed_bits(enc, enc->enc_pic.render_width - 1, 16);
886 /* render_height_minus_1 */
887 radeon_enc_code_fixed_bits(enc, enc->enc_pic.render_height - 1, 16);
888 }
889 }
890
891 if (enc->enc_pic.disable_screen_content_tools || !enc->enc_pic.force_integer_mv)
892 /* allow_high_precision_mv */
893 radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_ALLOW_HIGH_PRECISION_MV, 0);
894
895 /* read_interpolation_filter */
896 radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_READ_INTERPOLATION_FILTER, 0);
897
898 radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY, 0);
899 /* is_motion_mode_switchable */
900 radeon_enc_code_fixed_bits(enc, 0, 1);
901 }
902
903 if (!enc->enc_pic.av1_spec_misc.disable_cdf_update)
904 /* disable_frame_end_update_cdf */
905 radeon_enc_code_fixed_bits(enc, enc->enc_pic.av1_spec_misc.disable_frame_end_update_cdf ? 1 : 0, 1);
906
907 /* tile_info */
908 radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_TILE_INFO, 0);
909 /* quantization_params */
910 radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_QUANTIZATION_PARAMS, 0);
911 /* segmentation_enable */
912 radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY, 0);
913 radeon_enc_code_fixed_bits(enc, 0, 1);
914 /* delta_q_params */
915 radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_DELTA_Q_PARAMS, 0);
916 /* delta_lf_params */
917 radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_DELTA_LF_PARAMS, 0);
918 /* loop_filter_params */
919 radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_LOOP_FILTER_PARAMS, 0);
920 /* cdef_params */
921 radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_CDEF_PARAMS, 0);
922 /* lr_params */
923 /* read_tx_mode */
924 radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_READ_TX_MODE, 0);
925
926 radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY, 0);
927 if (!frame_is_intra)
928 /* reference_select */
929 radeon_enc_code_fixed_bits(enc, 0, 1);
930
931 radeon_enc_code_fixed_bits(enc, 0, 1);
932 if (!frame_is_intra)
933 for (uint32_t ref = 1 /*LAST_FRAME*/; ref <= 7 /*ALTREF_FRAME*/; ref++)
934 /* is_global */
935 radeon_enc_code_fixed_bits(enc, 0, 1);
936 /* film_grain_params() */
937 }
938 }
939
radeon_enc_av1_tile_group(struct radeon_encoder * enc)940 static void radeon_enc_av1_tile_group(struct radeon_encoder *enc)
941 {
942 uint32_t extension_flag = enc->enc_pic.num_temporal_layers > 1 ? 1 : 0;
943
944 radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_OBU_START,
945 RENCODE_OBU_START_TYPE_TILE_GROUP);
946 radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY, 0);
947
948 /* obu_header() */
949 /* obu_forbidden_bit */
950 radeon_enc_code_fixed_bits(enc, 0, 1);
951 /* obu_type */
952 radeon_enc_code_fixed_bits(enc, RENCODE_OBU_TYPE_TILE_GROUP, 4);
953 /* obu_extension_flag */
954 radeon_enc_code_fixed_bits(enc, extension_flag, 1);
955 /* obu_has_size_field */
956 radeon_enc_code_fixed_bits(enc, 1, 1);
957 /* obu_reserved_1bit */
958 radeon_enc_code_fixed_bits(enc, 0, 1);
959
960 if (extension_flag) {
961 radeon_enc_code_fixed_bits(enc, enc->enc_pic.temporal_id, 3);
962 radeon_enc_code_fixed_bits(enc, 0, 2);
963 radeon_enc_code_fixed_bits(enc, 0, 3);
964 }
965
966 radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_OBU_SIZE, 0);
967 radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_TILE_GROUP_OBU, 0);
968 radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_OBU_END, 0);
969 }
970
radeon_enc_obu_instruction(struct radeon_encoder * enc)971 static void radeon_enc_obu_instruction(struct radeon_encoder *enc)
972 {
973 bool frame_header = !enc->enc_pic.stream_obu_frame ||
974 (enc->enc_pic.frame_type == PIPE_AV1_ENC_FRAME_TYPE_SHOW_EXISTING);
975 radeon_enc_reset(enc);
976 RADEON_ENC_BEGIN(enc->cmd.bitstream_instruction_av1);
977 radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY, 0);
978
979 radeon_enc_av1_temporal_delimiter(enc);
980 if (enc->enc_pic.need_av1_seq || enc->enc_pic.need_sequence_header)
981 radeon_enc_av1_sequence_header(enc);
982
983 /* if others OBU types are needed such as meta data, then they need to be byte aligned and added here
984 *
985 * if (others)
986 * radeon_enc_av1_others(enc); */
987
988 radeon_enc_av1_bs_instruction_type(enc,
989 RENCODE_AV1_BITSTREAM_INSTRUCTION_OBU_START,
990 frame_header ? RENCODE_OBU_START_TYPE_FRAME_HEADER
991 : RENCODE_OBU_START_TYPE_FRAME);
992
993 radeon_enc_av1_frame_header(enc, frame_header);
994
995 if (!frame_header && (enc->enc_pic.frame_type != PIPE_AV1_ENC_FRAME_TYPE_SHOW_EXISTING))
996 radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_TILE_GROUP_OBU, 0);
997
998 radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_OBU_END, 0);
999
1000 if (frame_header && (enc->enc_pic.frame_type != PIPE_AV1_ENC_FRAME_TYPE_SHOW_EXISTING))
1001 radeon_enc_av1_tile_group(enc);
1002
1003 radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_END, 0);
1004 RADEON_ENC_END();
1005 }
1006
1007 /* av1 encode params */
radeon_enc_av1_encode_params(struct radeon_encoder * enc)1008 static void radeon_enc_av1_encode_params(struct radeon_encoder *enc)
1009 {
1010 switch (enc->enc_pic.frame_type) {
1011 case PIPE_AV1_ENC_FRAME_TYPE_KEY:
1012 enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I;
1013 break;
1014 case PIPE_AV1_ENC_FRAME_TYPE_INTRA_ONLY:
1015 enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I;
1016 break;
1017 case PIPE_AV1_ENC_FRAME_TYPE_INTER:
1018 case PIPE_AV1_ENC_FRAME_TYPE_SWITCH:
1019 case PIPE_AV1_ENC_FRAME_TYPE_SHOW_EXISTING:
1020 enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_P;
1021 break;
1022 default:
1023 assert(0); /* never come to this condition */
1024 }
1025
1026 if (enc->luma->meta_offset) {
1027 RVID_ERR("DCC surfaces not supported.\n");
1028 assert(false);
1029 }
1030
1031 enc->enc_pic.enc_params.allowed_max_bitstream_size = enc->bs_size;
1032 enc->enc_pic.enc_params.input_pic_luma_pitch = enc->luma->u.gfx9.surf_pitch;
1033 enc->enc_pic.enc_params.input_pic_chroma_pitch = enc->chroma ?
1034 enc->chroma->u.gfx9.surf_pitch : enc->luma->u.gfx9.surf_pitch;
1035 enc->enc_pic.enc_params.input_pic_swizzle_mode = enc->luma->u.gfx9.swizzle_mode;
1036
1037 RADEON_ENC_BEGIN(enc->cmd.enc_params);
1038 RADEON_ENC_CS(enc->enc_pic.enc_params.pic_type);
1039 RADEON_ENC_CS(enc->enc_pic.enc_params.allowed_max_bitstream_size);
1040
1041 /* show existing type doesn't need input picture */
1042 if (enc->enc_pic.frame_type == PIPE_AV1_ENC_FRAME_TYPE_SHOW_EXISTING) {
1043 RADEON_ENC_CS(0);
1044 RADEON_ENC_CS(0);
1045 RADEON_ENC_CS(0);
1046 RADEON_ENC_CS(0);
1047 } else {
1048 RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->luma->u.gfx9.surf_offset);
1049 RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->chroma ?
1050 enc->chroma->u.gfx9.surf_offset : enc->luma->u.gfx9.surf_pitch);
1051 }
1052
1053 RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_luma_pitch);
1054 RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_chroma_pitch);
1055 RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_swizzle_mode);
1056 RADEON_ENC_CS(enc->enc_pic.enc_params.reference_picture_index);
1057 RADEON_ENC_CS(enc->enc_pic.enc_params.reconstructed_picture_index);
1058 RADEON_ENC_END();
1059 }
1060
radeon_enc_ref_swizzle_mode(struct radeon_encoder * enc)1061 static uint32_t radeon_enc_ref_swizzle_mode(struct radeon_encoder *enc)
1062 {
1063 /* return RENCODE_REC_SWIZZLE_MODE_LINEAR; for debugging purpose */
1064 if (enc->enc_pic.bit_depth_luma_minus8 != 0)
1065 return RENCODE_REC_SWIZZLE_MODE_8x8_1D_THIN_12_24BPP;
1066 else
1067 return RENCODE_REC_SWIZZLE_MODE_256B_D;
1068 }
1069
radeon_enc_ctx(struct radeon_encoder * enc)1070 static void radeon_enc_ctx(struct radeon_encoder *enc)
1071 {
1072
1073 bool is_av1 = u_reduce_video_profile(enc->base.profile)
1074 == PIPE_VIDEO_FORMAT_AV1;
1075 enc->enc_pic.ctx_buf.swizzle_mode = radeon_enc_ref_swizzle_mode(enc);
1076 enc->enc_pic.ctx_buf.two_pass_search_center_map_offset = 0;
1077
1078 RADEON_ENC_BEGIN(enc->cmd.ctx);
1079 RADEON_ENC_READWRITE(enc->dpb->res->buf, enc->dpb->res->domains, 0);
1080 RADEON_ENC_CS(enc->enc_pic.ctx_buf.swizzle_mode);
1081 RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_luma_pitch);
1082 RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_chroma_pitch);
1083 RADEON_ENC_CS(enc->enc_pic.ctx_buf.num_reconstructed_pictures);
1084
1085 for (int i = 0; i < RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES; i++) {
1086 rvcn_enc_reconstructed_picture_t *pic =
1087 &enc->enc_pic.ctx_buf.reconstructed_pictures[i];
1088 RADEON_ENC_CS(pic->luma_offset);
1089 RADEON_ENC_CS(pic->chroma_offset);
1090 if (is_av1) {
1091 RADEON_ENC_CS(pic->av1.av1_cdf_frame_context_offset);
1092 RADEON_ENC_CS(pic->av1.av1_cdef_algorithm_context_offset);
1093 } else {
1094 RADEON_ENC_CS(0x00000000); /* unused offset 1 */
1095 RADEON_ENC_CS(0x00000000); /* unused offset 2 */
1096 }
1097 }
1098
1099 RADEON_ENC_CS(enc->enc_pic.ctx_buf.pre_encode_picture_luma_pitch);
1100 RADEON_ENC_CS(enc->enc_pic.ctx_buf.pre_encode_picture_chroma_pitch);
1101
1102 for (int i = 0; i < RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES; i++) {
1103 rvcn_enc_reconstructed_picture_t *pic =
1104 &enc->enc_pic.ctx_buf.pre_encode_reconstructed_pictures[i];
1105 RADEON_ENC_CS(pic->luma_offset);
1106 RADEON_ENC_CS(pic->chroma_offset);
1107 if (is_av1) {
1108 RADEON_ENC_CS(pic->av1.av1_cdf_frame_context_offset);
1109 RADEON_ENC_CS(pic->av1.av1_cdef_algorithm_context_offset);
1110 } else {
1111 RADEON_ENC_CS(0x00000000); /* unused offset 1 */
1112 RADEON_ENC_CS(0x00000000); /* unused offset 2 */
1113 }
1114 }
1115
1116 RADEON_ENC_CS(enc->enc_pic.ctx_buf.pre_encode_input_picture.rgb.red_offset);
1117 RADEON_ENC_CS(enc->enc_pic.ctx_buf.pre_encode_input_picture.rgb.green_offset);
1118 RADEON_ENC_CS(enc->enc_pic.ctx_buf.pre_encode_input_picture.rgb.blue_offset);
1119
1120 RADEON_ENC_CS(enc->enc_pic.ctx_buf.two_pass_search_center_map_offset);
1121 if (is_av1)
1122 RADEON_ENC_CS(enc->enc_pic.ctx_buf.av1.av1_sdb_intermedidate_context_offset);
1123 else
1124 RADEON_ENC_CS(enc->enc_pic.ctx_buf.colloc_buffer_offset);
1125 RADEON_ENC_END();
1126 }
1127
radeon_enc_header_av1(struct radeon_encoder * enc)1128 static void radeon_enc_header_av1(struct radeon_encoder *enc)
1129 {
1130 enc->obu_instructions(enc);
1131 enc->encode_params(enc);
1132 enc->cdf_default_table(enc);
1133
1134 enc->enc_pic.frame_id++;
1135 if (enc->enc_pic.frame_id > (1 << (RENCODE_AV1_DELTA_FRAME_ID_LENGTH - 2)))
1136 enc->enc_pic.frame_id = 0;
1137 }
1138
radeon_enc_4_0_init(struct radeon_encoder * enc)1139 void radeon_enc_4_0_init(struct radeon_encoder *enc)
1140 {
1141 radeon_enc_3_0_init(enc);
1142
1143 enc->session_init = radeon_enc_session_init;
1144 enc->ctx = radeon_enc_ctx;
1145 enc->mq_begin = enc->begin;
1146 enc->mq_encode = enc->encode;
1147 enc->mq_destroy = enc->destroy;
1148 enc->begin = radeon_enc_sq_begin;
1149 enc->encode = radeon_enc_sq_encode;
1150 enc->destroy = radeon_enc_sq_destroy;
1151 enc->op_preset = radeon_enc_op_preset;
1152
1153 if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_AV1) {
1154 enc->before_encode = radeon_enc_av1_dpb_management;
1155 /* begin function need to set these two functions to dummy */
1156 enc->slice_control = radeon_enc_dummy;
1157 enc->deblocking_filter = radeon_enc_dummy;
1158 enc->cmd.cdf_default_table_av1 = RENCODE_IB_PARAM_CDF_DEFAULT_TABLE_BUFFER;
1159 enc->cmd.bitstream_instruction_av1 = RENCODE_AV1_IB_PARAM_BITSTREAM_INSTRUCTION;
1160 enc->cmd.spec_misc_av1 = RENCODE_AV1_IB_PARAM_SPEC_MISC;
1161 enc->spec_misc = radeon_enc_spec_misc_av1;
1162 enc->encode_headers = radeon_enc_header_av1;
1163 enc->obu_instructions = radeon_enc_obu_instruction;
1164 enc->cdf_default_table = radeon_enc_cdf_default_table;
1165 enc->encode_params = radeon_enc_av1_encode_params;
1166 }
1167
1168 enc->cmd.enc_statistics = RENCODE_IB_PARAM_ENCODE_STATISTICS;
1169
1170 enc->enc_pic.session_info.interface_version =
1171 ((RENCODE_FW_INTERFACE_MAJOR_VERSION << RENCODE_IF_MAJOR_VERSION_SHIFT) |
1172 (RENCODE_FW_INTERFACE_MINOR_VERSION << RENCODE_IF_MINOR_VERSION_SHIFT));
1173 }
1174