1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * SPDX-License-Identifier: MIT
5 */
6
7 #include "compiler/nir/nir.h"
8 #include "ac_shader_util.h"
9 #include "radeon_uvd_enc.h"
10 #include "radeon_vce.h"
11 #include "radeon_video.h"
12 #include "si_pipe.h"
13 #include "util/u_cpu_detect.h"
14 #include "util/u_screen.h"
15 #include "util/u_video.h"
16 #include "vl/vl_decoder.h"
17 #include "vl/vl_video_buffer.h"
18 #include <sys/utsname.h>
19
20 /* The capabilities reported by the kernel has priority
21 over the existing logic in si_get_video_param */
22 #define QUERYABLE_KERNEL (sscreen->info.is_amdgpu && \
23 !!(sscreen->info.drm_minor >= 41))
24 #define KERNEL_DEC_CAP(codec, attrib) \
25 (codec > PIPE_VIDEO_FORMAT_UNKNOWN && codec <= PIPE_VIDEO_FORMAT_AV1) ? \
26 (sscreen->info.dec_caps.codec_info[codec - 1].valid ? \
27 sscreen->info.dec_caps.codec_info[codec - 1].attrib : 0) : 0
28 #define KERNEL_ENC_CAP(codec, attrib) \
29 (codec > PIPE_VIDEO_FORMAT_UNKNOWN && codec <= PIPE_VIDEO_FORMAT_AV1) ? \
30 (sscreen->info.enc_caps.codec_info[codec - 1].valid ? \
31 sscreen->info.enc_caps.codec_info[codec - 1].attrib : 0) : 0
32
si_get_vendor(struct pipe_screen * pscreen)33 static const char *si_get_vendor(struct pipe_screen *pscreen)
34 {
35 return "AMD";
36 }
37
si_get_device_vendor(struct pipe_screen * pscreen)38 static const char *si_get_device_vendor(struct pipe_screen *pscreen)
39 {
40 return "AMD";
41 }
42
si_get_param(struct pipe_screen * pscreen,enum pipe_cap param)43 static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
44 {
45 struct si_screen *sscreen = (struct si_screen *)pscreen;
46
47 /* Gfx8 (Polaris11) hangs, so don't enable this on Gfx8 and older chips. */
48 bool enable_sparse = sscreen->info.gfx_level >= GFX9 &&
49 sscreen->info.has_sparse_vm_mappings;
50
51 switch (param) {
52 /* Supported features (boolean caps). */
53 case PIPE_CAP_ACCELERATED:
54 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
55 case PIPE_CAP_ANISOTROPIC_FILTER:
56 case PIPE_CAP_OCCLUSION_QUERY:
57 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
58 case PIPE_CAP_TEXTURE_SHADOW_LOD:
59 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
60 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
61 case PIPE_CAP_TEXTURE_SWIZZLE:
62 case PIPE_CAP_DEPTH_CLIP_DISABLE:
63 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
64 case PIPE_CAP_SHADER_STENCIL_EXPORT:
65 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
66 case PIPE_CAP_FS_COORD_ORIGIN_UPPER_LEFT:
67 case PIPE_CAP_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
68 case PIPE_CAP_FS_COORD_PIXEL_CENTER_INTEGER:
69 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
70 case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
71 case PIPE_CAP_PRIMITIVE_RESTART:
72 case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX:
73 case PIPE_CAP_CONDITIONAL_RENDER:
74 case PIPE_CAP_TEXTURE_BARRIER:
75 case PIPE_CAP_INDEP_BLEND_ENABLE:
76 case PIPE_CAP_INDEP_BLEND_FUNC:
77 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
78 case PIPE_CAP_START_INSTANCE:
79 case PIPE_CAP_NPOT_TEXTURES:
80 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
81 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
82 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
83 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
84 case PIPE_CAP_VS_INSTANCEID:
85 case PIPE_CAP_COMPUTE:
86 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
87 case PIPE_CAP_VS_LAYER_VIEWPORT:
88 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
89 case PIPE_CAP_SAMPLE_SHADING:
90 case PIPE_CAP_DRAW_INDIRECT:
91 case PIPE_CAP_CLIP_HALFZ:
92 case PIPE_CAP_VS_WINDOW_SPACE_POSITION:
93 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
94 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
95 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
96 case PIPE_CAP_TGSI_TEXCOORD:
97 case PIPE_CAP_FS_FINE_DERIVATIVE:
98 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
99 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
100 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
101 case PIPE_CAP_DEPTH_BOUNDS_TEST:
102 case PIPE_CAP_SAMPLER_VIEW_TARGET:
103 case PIPE_CAP_TEXTURE_QUERY_LOD:
104 case PIPE_CAP_TEXTURE_GATHER_SM5:
105 case PIPE_CAP_TEXTURE_QUERY_SAMPLES:
106 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
107 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
108 case PIPE_CAP_FS_POSITION_IS_SYSVAL:
109 case PIPE_CAP_FS_FACE_IS_INTEGER_SYSVAL:
110 case PIPE_CAP_INVALIDATE_BUFFER:
111 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
112 case PIPE_CAP_QUERY_BUFFER_OBJECT:
113 case PIPE_CAP_QUERY_MEMORY_INFO:
114 case PIPE_CAP_SHADER_PACK_HALF_FLOAT:
115 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
116 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
117 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
118 case PIPE_CAP_STRING_MARKER:
119 case PIPE_CAP_CULL_DISTANCE:
120 case PIPE_CAP_SHADER_ARRAY_COMPONENTS:
121 case PIPE_CAP_SHADER_CAN_READ_OUTPUTS:
122 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
123 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
124 case PIPE_CAP_DOUBLES:
125 case PIPE_CAP_TGSI_TEX_TXF_LZ:
126 case PIPE_CAP_TES_LAYER_VIEWPORT:
127 case PIPE_CAP_BINDLESS_TEXTURE:
128 case PIPE_CAP_QUERY_TIMESTAMP:
129 case PIPE_CAP_QUERY_TIME_ELAPSED:
130 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
131 case PIPE_CAP_MEMOBJ:
132 case PIPE_CAP_LOAD_CONSTBUF:
133 case PIPE_CAP_INT64:
134 case PIPE_CAP_SHADER_CLOCK:
135 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
136 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
137 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
138 case PIPE_CAP_SHADER_BALLOT:
139 case PIPE_CAP_SHADER_GROUP_VOTE:
140 case PIPE_CAP_FBFETCH:
141 case PIPE_CAP_COMPUTE_GRID_INFO_LAST_BLOCK:
142 case PIPE_CAP_IMAGE_LOAD_FORMATTED:
143 case PIPE_CAP_PREFER_COMPUTE_FOR_MULTIMEDIA:
144 case PIPE_CAP_TGSI_DIV:
145 case PIPE_CAP_PACKED_UNIFORMS:
146 case PIPE_CAP_GL_SPIRV:
147 case PIPE_CAP_ALPHA_TO_COVERAGE_DITHER_CONTROL:
148 case PIPE_CAP_MAP_UNSYNCHRONIZED_THREAD_SAFE:
149 case PIPE_CAP_NO_CLIP_ON_COPY_TEX:
150 case PIPE_CAP_SHADER_ATOMIC_INT64:
151 case PIPE_CAP_FRONTEND_NOOP:
152 case PIPE_CAP_DEMOTE_TO_HELPER_INVOCATION:
153 case PIPE_CAP_PREFER_REAL_BUFFER_IN_CONSTBUF0:
154 case PIPE_CAP_COMPUTE_SHADER_DERIVATIVES:
155 case PIPE_CAP_IMAGE_ATOMIC_INC_WRAP:
156 case PIPE_CAP_IMAGE_STORE_FORMATTED:
157 case PIPE_CAP_ALLOW_DRAW_OUT_OF_ORDER:
158 case PIPE_CAP_QUERY_SO_OVERFLOW:
159 case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS:
160 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
161 case PIPE_CAP_TEXTURE_MULTISAMPLE:
162 case PIPE_CAP_ALLOW_GLTHREAD_BUFFER_SUBDATA_OPT: /* TODO: remove if it's slow */
163 case PIPE_CAP_NULL_TEXTURES:
164 case PIPE_CAP_HAS_CONST_BW:
165 case PIPE_CAP_FENCE_SIGNAL:
166 case PIPE_CAP_NATIVE_FENCE_FD:
167 case PIPE_CAP_CL_GL_SHARING:
168 return 1;
169
170 case PIPE_CAP_TEXTURE_TRANSFER_MODES:
171 return PIPE_TEXTURE_TRANSFER_BLIT;
172
173 case PIPE_CAP_DRAW_VERTEX_STATE:
174 return !(sscreen->debug_flags & DBG(NO_FAST_DISPLAY_LIST));
175
176 case PIPE_CAP_SHADER_SAMPLES_IDENTICAL:
177 return sscreen->info.gfx_level < GFX11;
178
179 case PIPE_CAP_GLSL_ZERO_INIT:
180 return 2;
181
182 case PIPE_CAP_GENERATE_MIPMAP:
183 case PIPE_CAP_SEAMLESS_CUBE_MAP:
184 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
185 case PIPE_CAP_CUBE_MAP_ARRAY:
186 return sscreen->info.has_3d_cube_border_color_mipmap;
187
188 case PIPE_CAP_POST_DEPTH_COVERAGE:
189 return sscreen->info.gfx_level >= GFX10;
190
191 case PIPE_CAP_GRAPHICS:
192 return sscreen->info.has_graphics;
193
194 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
195 return !UTIL_ARCH_BIG_ENDIAN && sscreen->info.has_userptr;
196
197 case PIPE_CAP_DEVICE_PROTECTED_SURFACE:
198 return sscreen->info.has_tmz_support;
199
200 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
201 return SI_MAP_BUFFER_ALIGNMENT;
202
203 case PIPE_CAP_MAX_VERTEX_BUFFERS:
204 return SI_MAX_ATTRIBS;
205
206 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
207 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
208 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
209 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
210 case PIPE_CAP_MAX_VERTEX_STREAMS:
211 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
212 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
213 return 4;
214
215 case PIPE_CAP_GLSL_FEATURE_LEVEL:
216 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
217 return 460;
218
219 case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
220 /* Optimal number for good TexSubImage performance on Polaris10. */
221 return 64 * 1024 * 1024;
222
223 case PIPE_CAP_GL_BEGIN_END_BUFFER_SIZE:
224 return 4096 * 1024;
225
226 case PIPE_CAP_MAX_TEXEL_BUFFER_ELEMENTS_UINT: {
227 unsigned max_texels =
228 pscreen->get_param(pscreen, PIPE_CAP_MAX_SHADER_BUFFER_SIZE_UINT);
229
230 /* FYI, BUF_RSRC_WORD2.NUM_RECORDS field limit is UINT32_MAX. */
231
232 /* Gfx8 and older use the size in bytes for bounds checking, and the max element size
233 * is 16B. Gfx9 and newer use the VGPR index for bounds checking.
234 */
235 if (sscreen->info.gfx_level <= GFX8)
236 max_texels = MIN2(max_texels, UINT32_MAX / 16);
237 else
238 /* Gallium has a limitation that it can only bind UINT32_MAX bytes, not texels.
239 * TODO: Remove this after the gallium interface is changed. */
240 max_texels = MIN2(max_texels, UINT32_MAX / 16);
241
242 return max_texels;
243 }
244
245 case PIPE_CAP_MAX_CONSTANT_BUFFER_SIZE_UINT:
246 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE_UINT: {
247 /* Return 1/4th of the heap size as the maximum because the max size is not practically
248 * allocatable. Also, this can only return UINT32_MAX at most.
249 */
250 unsigned max_size = MIN2((sscreen->info.max_heap_size_kb * 1024ull) / 4, UINT32_MAX);
251
252 /* Allow max 512 MB to pass CTS with a 32-bit build. */
253 if (sizeof(void*) == 4)
254 max_size = MIN2(max_size, 512 * 1024 * 1024);
255
256 return max_size;
257 }
258
259 case PIPE_CAP_MAX_TEXTURE_MB:
260 /* Allow 1/4th of the heap size. */
261 return sscreen->info.max_heap_size_kb / 1024 / 4;
262
263 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
264 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
265 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
266 case PIPE_CAP_PREFER_BACK_BUFFER_REUSE:
267 case PIPE_CAP_UMA:
268 case PIPE_CAP_PREFER_IMM_ARRAYS_AS_CONSTBUF:
269 return 0;
270
271 case PIPE_CAP_PERFORMANCE_MONITOR:
272 return sscreen->info.gfx_level >= GFX7 && sscreen->info.gfx_level <= GFX10_3;
273
274 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
275 return enable_sparse ? RADEON_SPARSE_PAGE_SIZE : 0;
276
277 case PIPE_CAP_CONTEXT_PRIORITY_MASK:
278 if (!sscreen->info.is_amdgpu)
279 return 0;
280 return PIPE_CONTEXT_PRIORITY_LOW |
281 PIPE_CONTEXT_PRIORITY_MEDIUM |
282 PIPE_CONTEXT_PRIORITY_HIGH;
283
284 case PIPE_CAP_CONSTBUF0_FLAGS:
285 return SI_RESOURCE_FLAG_32BIT;
286
287 case PIPE_CAP_DRAW_PARAMETERS:
288 case PIPE_CAP_MULTI_DRAW_INDIRECT:
289 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
290 return sscreen->has_draw_indirect_multi;
291
292 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
293 return 30;
294
295 case PIPE_CAP_MAX_VARYINGS:
296 case PIPE_CAP_MAX_GS_INVOCATIONS:
297 return 32;
298
299 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
300 return sscreen->info.gfx_level <= GFX8 ? PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
301
302 /* Stream output. */
303 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
304 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
305 return 32 * 4;
306
307 /* Geometry shader output. */
308 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
309 /* gfx9 has to report 256 to make piglit/gs-max-output pass.
310 * gfx8 and earlier can do 1024.
311 */
312 return 256;
313 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
314 return 4095;
315
316 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
317 return 2048;
318
319 /* Texturing. */
320 case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
321 return 16384;
322 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
323 if (!sscreen->info.has_3d_cube_border_color_mipmap)
324 return 0;
325 return 15; /* 16384 */
326 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
327 if (!sscreen->info.has_3d_cube_border_color_mipmap)
328 return 0;
329 if (sscreen->info.gfx_level >= GFX10)
330 return 14;
331 /* textures support 8192, but layered rendering supports 2048 */
332 return 12;
333 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
334 if (sscreen->info.gfx_level >= GFX10)
335 return 8192;
336 /* textures support 8192, but layered rendering supports 2048 */
337 return 2048;
338
339 /* Sparse texture */
340 case PIPE_CAP_MAX_SPARSE_TEXTURE_SIZE:
341 return enable_sparse ?
342 si_get_param(pscreen, PIPE_CAP_MAX_TEXTURE_2D_SIZE) : 0;
343 case PIPE_CAP_MAX_SPARSE_3D_TEXTURE_SIZE:
344 return enable_sparse ?
345 (1 << (si_get_param(pscreen, PIPE_CAP_MAX_TEXTURE_3D_LEVELS) - 1)) : 0;
346 case PIPE_CAP_MAX_SPARSE_ARRAY_TEXTURE_LAYERS:
347 return enable_sparse ?
348 si_get_param(pscreen, PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS) : 0;
349 case PIPE_CAP_SPARSE_TEXTURE_FULL_ARRAY_CUBE_MIPMAPS:
350 case PIPE_CAP_QUERY_SPARSE_TEXTURE_RESIDENCY:
351 case PIPE_CAP_CLAMP_SPARSE_TEXTURE_LOD:
352 return enable_sparse;
353
354 /* Viewports and render targets. */
355 case PIPE_CAP_MAX_VIEWPORTS:
356 return SI_MAX_VIEWPORTS;
357 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
358 case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS:
359 case PIPE_CAP_MAX_RENDER_TARGETS:
360 return 8;
361 case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
362 return sscreen->info.has_eqaa_surface_allocator ? 2 : 0;
363
364 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
365 case PIPE_CAP_MIN_TEXEL_OFFSET:
366 return -32;
367
368 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
369 case PIPE_CAP_MAX_TEXEL_OFFSET:
370 return 31;
371
372 case PIPE_CAP_ENDIANNESS:
373 return PIPE_ENDIAN_LITTLE;
374
375 case PIPE_CAP_VENDOR_ID:
376 return ATI_VENDOR_ID;
377 case PIPE_CAP_DEVICE_ID:
378 return sscreen->info.pci_id;
379 case PIPE_CAP_VIDEO_MEMORY:
380 return sscreen->info.vram_size_kb >> 10;
381 case PIPE_CAP_PCI_GROUP:
382 return sscreen->info.pci.domain;
383 case PIPE_CAP_PCI_BUS:
384 return sscreen->info.pci.bus;
385 case PIPE_CAP_PCI_DEVICE:
386 return sscreen->info.pci.dev;
387 case PIPE_CAP_PCI_FUNCTION:
388 return sscreen->info.pci.func;
389
390 case PIPE_CAP_TIMER_RESOLUTION:
391 /* Conversion to nanos from cycles per millisecond */
392 return DIV_ROUND_UP(1000000, sscreen->info.clock_crystal_freq);
393
394 default:
395 return u_pipe_screen_get_param_defaults(pscreen, param);
396 }
397 }
398
si_get_paramf(struct pipe_screen * pscreen,enum pipe_capf param)399 static float si_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
400 {
401 struct si_screen *sscreen = (struct si_screen *)pscreen;
402
403 switch (param) {
404 case PIPE_CAPF_MIN_LINE_WIDTH:
405 case PIPE_CAPF_MIN_LINE_WIDTH_AA:
406 return 1; /* due to axis-aligned end caps at line width 1 */
407 case PIPE_CAPF_MIN_POINT_SIZE:
408 case PIPE_CAPF_MIN_POINT_SIZE_AA:
409 case PIPE_CAPF_POINT_SIZE_GRANULARITY:
410 case PIPE_CAPF_LINE_WIDTH_GRANULARITY:
411 return 1.0 / 8.0; /* due to the register field precision */
412 case PIPE_CAPF_MAX_LINE_WIDTH:
413 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
414 /* This depends on the quant mode, though the precise interactions
415 * are unknown. */
416 return 2048;
417 case PIPE_CAPF_MAX_POINT_SIZE:
418 case PIPE_CAPF_MAX_POINT_SIZE_AA:
419 return SI_MAX_POINT_SIZE;
420 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
421 return 16.0f;
422 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
423 /* This is the maximum value of the LOD_BIAS sampler field. */
424 return sscreen->info.gfx_level >= GFX10 ? 31 : 16;
425 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
426 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
427 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
428 return 0.0f;
429 }
430 return 0.0f;
431 }
432
si_get_shader_param(struct pipe_screen * pscreen,enum pipe_shader_type shader,enum pipe_shader_cap param)433 static int si_get_shader_param(struct pipe_screen *pscreen, enum pipe_shader_type shader,
434 enum pipe_shader_cap param)
435 {
436 struct si_screen *sscreen = (struct si_screen *)pscreen;
437
438 if (shader == PIPE_SHADER_MESH ||
439 shader == PIPE_SHADER_TASK)
440 return 0;
441
442 switch (param) {
443 /* Shader limits. */
444 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
445 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
446 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
447 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
448 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
449 return 16384;
450 case PIPE_SHADER_CAP_MAX_INPUTS:
451 return shader == PIPE_SHADER_VERTEX ? SI_MAX_ATTRIBS : 32;
452 case PIPE_SHADER_CAP_MAX_OUTPUTS:
453 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
454 case PIPE_SHADER_CAP_MAX_TEMPS:
455 return 256; /* Max native temporaries. */
456 case PIPE_SHADER_CAP_MAX_CONST_BUFFER0_SIZE:
457 return 1 << 26; /* 64 MB */
458 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
459 return SI_NUM_CONST_BUFFERS;
460 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
461 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
462 return SI_NUM_SAMPLERS;
463 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
464 return SI_NUM_SHADER_BUFFERS;
465 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
466 return SI_NUM_IMAGES;
467
468 case PIPE_SHADER_CAP_SUPPORTED_IRS:
469 if (shader == PIPE_SHADER_COMPUTE) {
470 return (1 << PIPE_SHADER_IR_NATIVE) |
471 (1 << PIPE_SHADER_IR_NIR) |
472 (1 << PIPE_SHADER_IR_TGSI);
473 }
474 return (1 << PIPE_SHADER_IR_TGSI) |
475 (1 << PIPE_SHADER_IR_NIR);
476
477 /* Supported boolean features. */
478 case PIPE_SHADER_CAP_CONT_SUPPORTED:
479 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
480 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
481 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
482 case PIPE_SHADER_CAP_INTEGERS:
483 case PIPE_SHADER_CAP_INT64_ATOMICS:
484 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
485 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR: /* lowered in finalize_nir */
486 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR: /* lowered in finalize_nir */
487 return 1;
488
489 case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:
490 /* We need f16c for fast FP16 conversions in glUniform. */
491 if (!util_get_cpu_caps()->has_f16c)
492 return 0;
493 FALLTHROUGH;
494 case PIPE_SHADER_CAP_FP16:
495 case PIPE_SHADER_CAP_FP16_DERIVATIVES:
496 case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
497 case PIPE_SHADER_CAP_INT16:
498 return sscreen->info.gfx_level >= GFX8 && sscreen->options.fp16;
499
500 /* Unsupported boolean features. */
501 case PIPE_SHADER_CAP_SUBROUTINES:
502 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
503 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
504 return 0;
505 }
506 return 0;
507 }
508
si_get_compiler_options(struct pipe_screen * screen,enum pipe_shader_ir ir,enum pipe_shader_type shader)509 static const void *si_get_compiler_options(struct pipe_screen *screen, enum pipe_shader_ir ir,
510 enum pipe_shader_type shader)
511 {
512 struct si_screen *sscreen = (struct si_screen *)screen;
513
514 assert(ir == PIPE_SHADER_IR_NIR);
515 return sscreen->nir_options;
516 }
517
si_get_driver_uuid(struct pipe_screen * pscreen,char * uuid)518 static void si_get_driver_uuid(struct pipe_screen *pscreen, char *uuid)
519 {
520 ac_compute_driver_uuid(uuid, PIPE_UUID_SIZE);
521 }
522
si_get_device_uuid(struct pipe_screen * pscreen,char * uuid)523 static void si_get_device_uuid(struct pipe_screen *pscreen, char *uuid)
524 {
525 struct si_screen *sscreen = (struct si_screen *)pscreen;
526
527 ac_compute_device_uuid(&sscreen->info, uuid, PIPE_UUID_SIZE);
528 }
529
si_get_name(struct pipe_screen * pscreen)530 static const char *si_get_name(struct pipe_screen *pscreen)
531 {
532 struct si_screen *sscreen = (struct si_screen *)pscreen;
533
534 return sscreen->renderer_string;
535 }
536
si_get_video_param_no_video_hw(struct pipe_screen * screen,enum pipe_video_profile profile,enum pipe_video_entrypoint entrypoint,enum pipe_video_cap param)537 static int si_get_video_param_no_video_hw(struct pipe_screen *screen, enum pipe_video_profile profile,
538 enum pipe_video_entrypoint entrypoint,
539 enum pipe_video_cap param)
540 {
541 switch (param) {
542 case PIPE_VIDEO_CAP_SUPPORTED:
543 return vl_profile_supported(screen, profile, entrypoint);
544 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
545 return 1;
546 case PIPE_VIDEO_CAP_MAX_WIDTH:
547 case PIPE_VIDEO_CAP_MAX_HEIGHT:
548 return vl_video_buffer_max_size(screen);
549 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
550 return PIPE_FORMAT_NV12;
551 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
552 return false;
553 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
554 return false;
555 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
556 return true;
557 case PIPE_VIDEO_CAP_MAX_LEVEL:
558 return vl_level_supported(screen, profile);
559 default:
560 return 0;
561 }
562 }
563
si_get_video_param(struct pipe_screen * screen,enum pipe_video_profile profile,enum pipe_video_entrypoint entrypoint,enum pipe_video_cap param)564 static int si_get_video_param(struct pipe_screen *screen, enum pipe_video_profile profile,
565 enum pipe_video_entrypoint entrypoint, enum pipe_video_cap param)
566 {
567 struct si_screen *sscreen = (struct si_screen *)screen;
568 enum pipe_video_format codec = u_reduce_video_profile(profile);
569 bool fully_supported_profile = ((profile >= PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE) &&
570 (profile <= PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH)) ||
571 (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN) ||
572 (profile == PIPE_VIDEO_PROFILE_AV1_MAIN);
573
574 /* Return the capability of Video Post Processor.
575 * Have to determine the HW version of VPE.
576 * Have to check the HW limitation and
577 * Check if the VPE exists and is valid
578 */
579 if (sscreen->info.ip[AMD_IP_VPE].num_queues && entrypoint == PIPE_VIDEO_ENTRYPOINT_PROCESSING) {
580
581 switch(param) {
582 case PIPE_VIDEO_CAP_SUPPORTED:
583 return true;
584 case PIPE_VIDEO_CAP_MAX_WIDTH:
585 return 10240;
586 case PIPE_VIDEO_CAP_MAX_HEIGHT:
587 return 10240;
588 case PIPE_VIDEO_CAP_VPP_MAX_INPUT_WIDTH:
589 return 10240;
590 case PIPE_VIDEO_CAP_VPP_MAX_INPUT_HEIGHT:
591 return 10240;
592 case PIPE_VIDEO_CAP_VPP_MIN_INPUT_WIDTH:
593 return 16;
594 case PIPE_VIDEO_CAP_VPP_MIN_INPUT_HEIGHT:
595 return 16;
596 case PIPE_VIDEO_CAP_VPP_MAX_OUTPUT_WIDTH:
597 return 10240;
598 case PIPE_VIDEO_CAP_VPP_MAX_OUTPUT_HEIGHT:
599 return 10240;
600 case PIPE_VIDEO_CAP_VPP_MIN_OUTPUT_WIDTH:
601 return 16;
602 case PIPE_VIDEO_CAP_VPP_MIN_OUTPUT_HEIGHT:
603 return 16;
604 case PIPE_VIDEO_CAP_VPP_ORIENTATION_MODES:
605 /* VPE 1st generation does not support orientation
606 * Have to determine the version and features of VPE in future.
607 */
608 return PIPE_VIDEO_VPP_ORIENTATION_DEFAULT;
609 case PIPE_VIDEO_CAP_VPP_BLEND_MODES:
610 /* VPE 1st generation does not support blending.
611 * Have to determine the version and features of VPE in future.
612 */
613 return PIPE_VIDEO_VPP_BLEND_MODE_NONE;
614 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
615 return PIPE_FORMAT_NV12;
616 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
617 return false;
618 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
619 return true;
620 case PIPE_VIDEO_CAP_REQUIRES_FLUSH_ON_END_FRAME:
621 /* true: VPP flush function will be called within vaEndPicture() */
622 /* false: VPP flush function will be skipped */
623 return false;
624 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
625 /* for VPE we prefer non-interlaced buffer */
626 return false;
627 default:
628 return 0;
629 }
630 }
631
632 if (entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
633 if (!(sscreen->info.ip[AMD_IP_VCE].num_queues ||
634 sscreen->info.ip[AMD_IP_UVD_ENC].num_queues ||
635 sscreen->info.ip[AMD_IP_VCN_ENC].num_queues))
636 return 0;
637
638 if (sscreen->info.vcn_ip_version == VCN_4_0_3)
639 return 0;
640
641 switch (param) {
642 case PIPE_VIDEO_CAP_SUPPORTED:
643 return (
644 /* in case it is explicitly marked as not supported by the kernel */
645 ((QUERYABLE_KERNEL && fully_supported_profile) ? KERNEL_ENC_CAP(codec, valid) : 1) &&
646 ((codec == PIPE_VIDEO_FORMAT_MPEG4_AVC && profile != PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH10 &&
647 (sscreen->info.vcn_ip_version >= VCN_1_0_0 || si_vce_is_fw_version_supported(sscreen))) ||
648 (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN &&
649 (sscreen->info.vcn_ip_version >= VCN_1_0_0 || si_radeon_uvd_enc_supported(sscreen))) ||
650 (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10 && sscreen->info.vcn_ip_version >= VCN_2_0_0) ||
651 (profile == PIPE_VIDEO_PROFILE_AV1_MAIN &&
652 (sscreen->info.vcn_ip_version >= VCN_4_0_0 && sscreen->info.vcn_ip_version != VCN_4_0_3))));
653 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
654 return 1;
655 case PIPE_VIDEO_CAP_MIN_WIDTH:
656 return 256;
657 case PIPE_VIDEO_CAP_MIN_HEIGHT:
658 return 128;
659 case PIPE_VIDEO_CAP_MAX_WIDTH:
660 if (codec != PIPE_VIDEO_FORMAT_UNKNOWN && QUERYABLE_KERNEL)
661 return KERNEL_ENC_CAP(codec, max_width);
662 else
663 return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
664 case PIPE_VIDEO_CAP_MAX_HEIGHT:
665 if (codec != PIPE_VIDEO_FORMAT_UNKNOWN && QUERYABLE_KERNEL)
666 return KERNEL_ENC_CAP(codec, max_height);
667 else
668 return (sscreen->info.family < CHIP_TONGA) ? 1152 : 2304;
669 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
670 if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
671 return PIPE_FORMAT_P010;
672 else
673 return PIPE_FORMAT_NV12;
674 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
675 return false;
676 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
677 return false;
678 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
679 return true;
680 case PIPE_VIDEO_CAP_STACKED_FRAMES:
681 return (sscreen->info.family < CHIP_TONGA) ? 1 : 2;
682 case PIPE_VIDEO_CAP_MAX_TEMPORAL_LAYERS:
683 return (codec == PIPE_VIDEO_FORMAT_MPEG4_AVC &&
684 sscreen->info.vcn_ip_version >= VCN_1_0_0) ? 4 : 0;
685 case PIPE_VIDEO_CAP_ENC_QUALITY_LEVEL:
686 return (sscreen->info.vcn_ip_version >= VCN_1_0_0) ? 32 : 0;
687 case PIPE_VIDEO_CAP_ENC_SUPPORTS_MAX_FRAME_SIZE:
688 return (sscreen->info.vcn_ip_version >= VCN_1_0_0) ? 1 : 0;
689
690 case PIPE_VIDEO_CAP_ENC_HEVC_FEATURE_FLAGS:
691 if ((sscreen->info.vcn_ip_version >= VCN_1_0_0) &&
692 (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN ||
693 profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)) {
694 union pipe_h265_enc_cap_features pipe_features;
695 pipe_features.value = 0;
696
697 pipe_features.bits.amp = PIPE_ENC_FEATURE_SUPPORTED;
698 pipe_features.bits.strong_intra_smoothing = PIPE_ENC_FEATURE_SUPPORTED;
699 pipe_features.bits.constrained_intra_pred = PIPE_ENC_FEATURE_SUPPORTED;
700 pipe_features.bits.deblocking_filter_disable
701 = PIPE_ENC_FEATURE_SUPPORTED;
702 if (sscreen->info.vcn_ip_version >= VCN_2_0_0)
703 pipe_features.bits.sao = PIPE_ENC_FEATURE_SUPPORTED;
704
705 return pipe_features.value;
706 } else
707 return 0;
708
709 case PIPE_VIDEO_CAP_ENC_HEVC_BLOCK_SIZES:
710 if (sscreen->info.vcn_ip_version >= VCN_1_0_0 &&
711 (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN ||
712 profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)) {
713 union pipe_h265_enc_cap_block_sizes pipe_block_sizes;
714 pipe_block_sizes.value = 0;
715
716 pipe_block_sizes.bits.log2_max_coding_tree_block_size_minus3 = 3;
717 pipe_block_sizes.bits.log2_min_coding_tree_block_size_minus3 = 3;
718 pipe_block_sizes.bits.log2_min_luma_coding_block_size_minus3 = 0;
719 pipe_block_sizes.bits.log2_max_luma_transform_block_size_minus2 = 3;
720 pipe_block_sizes.bits.log2_min_luma_transform_block_size_minus2 = 0;
721
722 return pipe_block_sizes.value;
723 } else
724 return 0;
725
726 case PIPE_VIDEO_CAP_ENC_SUPPORTS_ASYNC_OPERATION:
727 return (sscreen->info.vcn_ip_version >= VCN_1_0_0) ? 1 : 0;
728
729 case PIPE_VIDEO_CAP_ENC_MAX_SLICES_PER_FRAME:
730 return (sscreen->info.vcn_ip_version >= VCN_1_0_0) ? 128 : 1;
731
732 case PIPE_VIDEO_CAP_ENC_SLICES_STRUCTURE:
733 if (sscreen->info.vcn_ip_version >= VCN_2_0_0) {
734 int value = (PIPE_VIDEO_CAP_SLICE_STRUCTURE_POWER_OF_TWO_ROWS |
735 PIPE_VIDEO_CAP_SLICE_STRUCTURE_EQUAL_ROWS |
736 PIPE_VIDEO_CAP_SLICE_STRUCTURE_EQUAL_MULTI_ROWS);
737 return value;
738 } else
739 return 0;
740
741 case PIPE_VIDEO_CAP_ENC_AV1_FEATURE:
742 if (sscreen->info.vcn_ip_version >= VCN_4_0_0 && sscreen->info.vcn_ip_version != VCN_4_0_3) {
743 union pipe_av1_enc_cap_features attrib;
744 attrib.value = 0;
745
746 attrib.bits.support_128x128_superblock = PIPE_ENC_FEATURE_NOT_SUPPORTED;
747 attrib.bits.support_filter_intra = PIPE_ENC_FEATURE_NOT_SUPPORTED;
748 attrib.bits.support_intra_edge_filter = PIPE_ENC_FEATURE_NOT_SUPPORTED;
749 attrib.bits.support_interintra_compound = PIPE_ENC_FEATURE_NOT_SUPPORTED;
750 attrib.bits.support_masked_compound = PIPE_ENC_FEATURE_NOT_SUPPORTED;
751 attrib.bits.support_warped_motion = PIPE_ENC_FEATURE_NOT_SUPPORTED;
752 attrib.bits.support_palette_mode = PIPE_ENC_FEATURE_SUPPORTED;
753 attrib.bits.support_dual_filter = PIPE_ENC_FEATURE_NOT_SUPPORTED;
754 attrib.bits.support_jnt_comp = PIPE_ENC_FEATURE_NOT_SUPPORTED;
755 attrib.bits.support_ref_frame_mvs = PIPE_ENC_FEATURE_NOT_SUPPORTED;
756 attrib.bits.support_superres = PIPE_ENC_FEATURE_NOT_SUPPORTED;
757 attrib.bits.support_restoration = PIPE_ENC_FEATURE_NOT_SUPPORTED;
758 attrib.bits.support_allow_intrabc = PIPE_ENC_FEATURE_NOT_SUPPORTED;
759 attrib.bits.support_cdef_channel_strength = PIPE_ENC_FEATURE_SUPPORTED;
760
761 return attrib.value;
762 } else
763 return 0;
764
765 case PIPE_VIDEO_CAP_ENC_AV1_FEATURE_EXT1:
766 if (sscreen->info.vcn_ip_version >= VCN_4_0_0 && sscreen->info.vcn_ip_version != VCN_4_0_3) {
767 union pipe_av1_enc_cap_features_ext1 attrib_ext1;
768 attrib_ext1.value = 0;
769 attrib_ext1.bits.interpolation_filter = PIPE_VIDEO_CAP_ENC_AV1_INTERPOLATION_FILTER_EIGHT_TAP |
770 PIPE_VIDEO_CAP_ENC_AV1_INTERPOLATION_FILTER_EIGHT_TAP_SMOOTH |
771 PIPE_VIDEO_CAP_ENC_AV1_INTERPOLATION_FILTER_EIGHT_TAP_SHARP |
772 PIPE_VIDEO_CAP_ENC_AV1_INTERPOLATION_FILTER_BILINEAR |
773 PIPE_VIDEO_CAP_ENC_AV1_INTERPOLATION_FILTER_SWITCHABLE;
774 attrib_ext1.bits.min_segid_block_size_accepted = 0;
775 attrib_ext1.bits.segment_feature_support = 0;
776
777 return attrib_ext1.value;
778 } else
779 return 0;
780
781 case PIPE_VIDEO_CAP_ENC_AV1_FEATURE_EXT2:
782 if (sscreen->info.vcn_ip_version >= VCN_4_0_0 && sscreen->info.vcn_ip_version != VCN_4_0_3) {
783 union pipe_av1_enc_cap_features_ext2 attrib_ext2;
784 attrib_ext2.value = 0;
785
786 attrib_ext2.bits.tile_size_bytes_minus1 = 1;
787 attrib_ext2.bits.obu_size_bytes_minus1 = 1;
788 /**
789 * tx_mode supported.
790 * (tx_mode_support & 0x01) == 1: ONLY_4X4 is supported, 0: not.
791 * (tx_mode_support & 0x02) == 1: TX_MODE_LARGEST is supported, 0: not.
792 * (tx_mode_support & 0x04) == 1: TX_MODE_SELECT is supported, 0: not.
793 */
794 attrib_ext2.bits.tx_mode_support = PIPE_VIDEO_CAP_ENC_AV1_TX_MODE_SELECT;
795 attrib_ext2.bits.max_tile_num_minus1 = 31;
796
797 return attrib_ext2.value;
798 } else
799 return 0;
800 case PIPE_VIDEO_CAP_ENC_SUPPORTS_TILE:
801 if ((sscreen->info.vcn_ip_version >= VCN_4_0_0 && sscreen->info.vcn_ip_version != VCN_4_0_3) &&
802 profile == PIPE_VIDEO_PROFILE_AV1_MAIN)
803 return 1;
804 else
805 return 0;
806 case PIPE_VIDEO_CAP_EFC_SUPPORTED:
807 return ((sscreen->info.family > CHIP_RENOIR) &&
808 !(sscreen->debug_flags & DBG(NO_EFC)));
809
810 case PIPE_VIDEO_CAP_ENC_MAX_REFERENCES_PER_FRAME:
811 if (sscreen->info.vcn_ip_version >= VCN_3_0_0) {
812 int refPicList0 = 1;
813 int refPicList1 = codec == PIPE_VIDEO_FORMAT_MPEG4_AVC ? 1 : 0;
814 return refPicList0 | (refPicList1 << 16);
815 } else
816 return 1;
817
818 case PIPE_VIDEO_CAP_ENC_INTRA_REFRESH:
819 if (sscreen->info.vcn_ip_version >= VCN_1_0_0) {
820 int value = PIPE_VIDEO_ENC_INTRA_REFRESH_ROW |
821 PIPE_VIDEO_ENC_INTRA_REFRESH_COLUMN |
822 PIPE_VIDEO_ENC_INTRA_REFRESH_P_FRAME;
823 return value;
824 }
825 else
826 return 0;
827
828 case PIPE_VIDEO_CAP_ENC_ROI:
829 if (sscreen->info.vcn_ip_version >= VCN_1_0_0) {
830 union pipe_enc_cap_roi attrib;
831 attrib.value = 0;
832
833 attrib.bits.num_roi_regions = PIPE_ENC_ROI_REGION_NUM_MAX;
834 attrib.bits.roi_rc_priority_support = PIPE_ENC_FEATURE_NOT_SUPPORTED;
835 attrib.bits.roi_rc_qp_delta_support = PIPE_ENC_FEATURE_SUPPORTED;
836 return attrib.value;
837 }
838 else
839 return 0;
840
841 default:
842 return 0;
843 }
844 }
845
846 switch (param) {
847 case PIPE_VIDEO_CAP_SUPPORTED:
848 if (codec != PIPE_VIDEO_FORMAT_JPEG &&
849 !(sscreen->info.ip[AMD_IP_UVD].num_queues ||
850 ((sscreen->info.vcn_ip_version >= VCN_4_0_0) ?
851 sscreen->info.ip[AMD_IP_VCN_UNIFIED].num_queues :
852 sscreen->info.ip[AMD_IP_VCN_DEC].num_queues)))
853 return false;
854 if (QUERYABLE_KERNEL && fully_supported_profile &&
855 sscreen->info.vcn_ip_version >= VCN_1_0_0)
856 return KERNEL_DEC_CAP(codec, valid);
857 if (codec < PIPE_VIDEO_FORMAT_MPEG4_AVC &&
858 sscreen->info.vcn_ip_version >= VCN_3_0_33)
859 return false;
860
861 switch (codec) {
862 case PIPE_VIDEO_FORMAT_MPEG12:
863 return !(sscreen->info.vcn_ip_version >= VCN_3_0_33 || profile == PIPE_VIDEO_PROFILE_MPEG1);
864 case PIPE_VIDEO_FORMAT_MPEG4:
865 return !(sscreen->info.vcn_ip_version >= VCN_3_0_33);
866 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
867 if ((sscreen->info.family == CHIP_POLARIS10 || sscreen->info.family == CHIP_POLARIS11) &&
868 sscreen->info.uvd_fw_version < UVD_FW_1_66_16) {
869 RVID_ERR("POLARIS10/11 firmware version need to be updated.\n");
870 return false;
871 }
872 return (profile != PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH10);
873 case PIPE_VIDEO_FORMAT_VC1:
874 return !(sscreen->info.vcn_ip_version >= VCN_3_0_33);
875 case PIPE_VIDEO_FORMAT_HEVC:
876 /* Carrizo only supports HEVC Main */
877 if (sscreen->info.family >= CHIP_STONEY)
878 return (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN ||
879 profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10);
880 else if (sscreen->info.family >= CHIP_CARRIZO)
881 return profile == PIPE_VIDEO_PROFILE_HEVC_MAIN;
882 return false;
883 case PIPE_VIDEO_FORMAT_JPEG:
884 if (sscreen->info.vcn_ip_version >= VCN_1_0_0) {
885 if (!sscreen->info.ip[AMD_IP_VCN_JPEG].num_queues)
886 return false;
887 else
888 return true;
889 }
890 if (sscreen->info.family < CHIP_CARRIZO || sscreen->info.family >= CHIP_VEGA10)
891 return false;
892 if (!sscreen->info.is_amdgpu) {
893 RVID_ERR("No MJPEG support for the kernel version\n");
894 return false;
895 }
896 return true;
897 case PIPE_VIDEO_FORMAT_VP9:
898 return sscreen->info.vcn_ip_version >= VCN_1_0_0;
899 case PIPE_VIDEO_FORMAT_AV1:
900 return sscreen->info.vcn_ip_version >= VCN_3_0_0 && sscreen->info.vcn_ip_version != VCN_3_0_33;
901 default:
902 return false;
903 }
904 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
905 return 1;
906 case PIPE_VIDEO_CAP_MIN_WIDTH:
907 case PIPE_VIDEO_CAP_MIN_HEIGHT:
908 return (codec == PIPE_VIDEO_FORMAT_AV1) ? 16 : 64;
909 case PIPE_VIDEO_CAP_MAX_WIDTH:
910 if (codec != PIPE_VIDEO_FORMAT_UNKNOWN && QUERYABLE_KERNEL)
911 return KERNEL_DEC_CAP(codec, max_width);
912 else {
913 switch (codec) {
914 case PIPE_VIDEO_FORMAT_HEVC:
915 case PIPE_VIDEO_FORMAT_VP9:
916 case PIPE_VIDEO_FORMAT_AV1:
917 return (sscreen->info.vcn_ip_version < VCN_2_0_0) ?
918 ((sscreen->info.family < CHIP_TONGA) ? 2048 : 4096) : 8192;
919 default:
920 return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
921 }
922 }
923 case PIPE_VIDEO_CAP_MAX_HEIGHT:
924 if (codec != PIPE_VIDEO_FORMAT_UNKNOWN && QUERYABLE_KERNEL)
925 return KERNEL_DEC_CAP(codec, max_height);
926 else {
927 switch (codec) {
928 case PIPE_VIDEO_FORMAT_HEVC:
929 case PIPE_VIDEO_FORMAT_VP9:
930 case PIPE_VIDEO_FORMAT_AV1:
931 return (sscreen->info.vcn_ip_version < VCN_2_0_0) ?
932 ((sscreen->info.family < CHIP_TONGA) ? 1152 : 4096) : 4352;
933 default:
934 return (sscreen->info.family < CHIP_TONGA) ? 1152 : 4096;
935 }
936 }
937 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
938 if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
939 return PIPE_FORMAT_P010;
940 else if (profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2)
941 return PIPE_FORMAT_P010;
942 else
943 return PIPE_FORMAT_NV12;
944
945 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
946 return false;
947 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED: {
948 enum pipe_video_format format = u_reduce_video_profile(profile);
949
950 if (format >= PIPE_VIDEO_FORMAT_HEVC)
951 return false;
952
953 return true;
954 }
955 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
956 return true;
957 case PIPE_VIDEO_CAP_MAX_LEVEL:
958 if ((profile == PIPE_VIDEO_PROFILE_MPEG2_SIMPLE ||
959 profile == PIPE_VIDEO_PROFILE_MPEG2_MAIN ||
960 profile == PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE ||
961 profile == PIPE_VIDEO_PROFILE_VC1_ADVANCED) &&
962 sscreen->info.dec_caps.codec_info[codec - 1].valid) {
963 return sscreen->info.dec_caps.codec_info[codec - 1].max_level;
964 } else {
965 switch (profile) {
966 case PIPE_VIDEO_PROFILE_MPEG1:
967 return 0;
968 case PIPE_VIDEO_PROFILE_MPEG2_SIMPLE:
969 case PIPE_VIDEO_PROFILE_MPEG2_MAIN:
970 return 3;
971 case PIPE_VIDEO_PROFILE_MPEG4_SIMPLE:
972 return 3;
973 case PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE:
974 return 5;
975 case PIPE_VIDEO_PROFILE_VC1_SIMPLE:
976 return 1;
977 case PIPE_VIDEO_PROFILE_VC1_MAIN:
978 return 2;
979 case PIPE_VIDEO_PROFILE_VC1_ADVANCED:
980 return 4;
981 case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
982 case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
983 case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
984 return (sscreen->info.family < CHIP_TONGA) ? 41 : 52;
985 case PIPE_VIDEO_PROFILE_HEVC_MAIN:
986 case PIPE_VIDEO_PROFILE_HEVC_MAIN_10:
987 return 186;
988 default:
989 return 0;
990 }
991 }
992 case PIPE_VIDEO_CAP_SUPPORTS_CONTIGUOUS_PLANES_MAP:
993 return true;
994 case PIPE_VIDEO_CAP_ROI_CROP_DEC:
995 if (codec == PIPE_VIDEO_FORMAT_JPEG &&
996 sscreen->info.vcn_ip_version == VCN_4_0_3)
997 return true;
998 return false;
999 default:
1000 return 0;
1001 }
1002 }
1003
si_vid_is_format_supported(struct pipe_screen * screen,enum pipe_format format,enum pipe_video_profile profile,enum pipe_video_entrypoint entrypoint)1004 static bool si_vid_is_format_supported(struct pipe_screen *screen, enum pipe_format format,
1005 enum pipe_video_profile profile,
1006 enum pipe_video_entrypoint entrypoint)
1007 {
1008 struct si_screen *sscreen = (struct si_screen *)screen;
1009
1010 if (sscreen->info.ip[AMD_IP_VPE].num_queues && entrypoint == PIPE_VIDEO_ENTRYPOINT_PROCESSING) {
1011 /* Todo:
1012 * Unable to confirm whether it is asking for an input or output type
1013 * Have to modify va frontend for solving this problem
1014 */
1015 /* VPE Supported input type */
1016 if ((format == PIPE_FORMAT_NV12) || (format == PIPE_FORMAT_NV21) || (format == PIPE_FORMAT_P010))
1017 return true;
1018
1019 /* VPE Supported output type */
1020 if ((format == PIPE_FORMAT_A8R8G8B8_UNORM) || (format == PIPE_FORMAT_A8B8G8R8_UNORM) || (format == PIPE_FORMAT_R8G8B8A8_UNORM) ||
1021 (format == PIPE_FORMAT_B8G8R8A8_UNORM) || (format == PIPE_FORMAT_X8R8G8B8_UNORM) || (format == PIPE_FORMAT_X8B8G8R8_UNORM) ||
1022 (format == PIPE_FORMAT_R8G8B8X8_UNORM) || (format == PIPE_FORMAT_B8G8R8X8_UNORM) || (format == PIPE_FORMAT_A2R10G10B10_UNORM) ||
1023 (format == PIPE_FORMAT_A2B10G10R10_UNORM) || (format == PIPE_FORMAT_B10G10R10A2_UNORM) || (format == PIPE_FORMAT_R10G10B10A2_UNORM))
1024 return true;
1025 }
1026
1027 /* HEVC 10 bit decoding should use P010 instead of NV12 if possible */
1028 if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
1029 return (format == PIPE_FORMAT_NV12) || (format == PIPE_FORMAT_P010) ||
1030 (format == PIPE_FORMAT_P016);
1031
1032 /* Vp9 profile 2 supports 10 bit decoding using P016 */
1033 if (profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2)
1034 return (format == PIPE_FORMAT_P010) || (format == PIPE_FORMAT_P016);
1035
1036 if (profile == PIPE_VIDEO_PROFILE_AV1_MAIN && entrypoint == PIPE_VIDEO_ENTRYPOINT_BITSTREAM)
1037 return (format == PIPE_FORMAT_P010) || (format == PIPE_FORMAT_P016) ||
1038 (format == PIPE_FORMAT_NV12);
1039
1040 /* JPEG supports YUV400 and YUV444 */
1041 if (profile == PIPE_VIDEO_PROFILE_JPEG_BASELINE) {
1042 switch (format) {
1043 case PIPE_FORMAT_NV12:
1044 case PIPE_FORMAT_YUYV:
1045 case PIPE_FORMAT_L8_UNORM:
1046 case PIPE_FORMAT_Y8_400_UNORM:
1047 return true;
1048 case PIPE_FORMAT_Y8_U8_V8_444_UNORM:
1049 if (sscreen->info.vcn_ip_version >= VCN_2_0_0)
1050 return true;
1051 else
1052 return false;
1053 case PIPE_FORMAT_R8G8B8A8_UNORM:
1054 case PIPE_FORMAT_A8R8G8B8_UNORM:
1055 case PIPE_FORMAT_R8_G8_B8_UNORM:
1056 if (sscreen->info.vcn_ip_version == VCN_4_0_3)
1057 return true;
1058 else
1059 return false;
1060 default:
1061 return false;
1062 }
1063 }
1064
1065 if ((entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) &&
1066 (((profile == PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH) &&
1067 (sscreen->info.vcn_ip_version >= VCN_2_0_0)) ||
1068 ((profile == PIPE_VIDEO_PROFILE_AV1_MAIN) &&
1069 (sscreen->info.vcn_ip_version >= VCN_4_0_0 &&
1070 sscreen->info.vcn_ip_version != VCN_4_0_3))))
1071 return (format == PIPE_FORMAT_P010 || format == PIPE_FORMAT_NV12);
1072
1073
1074 /* we can only handle this one with UVD */
1075 if (profile != PIPE_VIDEO_PROFILE_UNKNOWN)
1076 return format == PIPE_FORMAT_NV12;
1077
1078 return vl_video_buffer_is_format_supported(screen, format, profile, entrypoint);
1079 }
1080
get_max_threads_per_block(struct si_screen * screen,enum pipe_shader_ir ir_type)1081 static unsigned get_max_threads_per_block(struct si_screen *screen, enum pipe_shader_ir ir_type)
1082 {
1083 if (ir_type == PIPE_SHADER_IR_NATIVE)
1084 return 256;
1085
1086 /* LLVM only supports 1024 threads per block. */
1087 return 1024;
1088 }
1089
si_get_compute_param(struct pipe_screen * screen,enum pipe_shader_ir ir_type,enum pipe_compute_cap param,void * ret)1090 static int si_get_compute_param(struct pipe_screen *screen, enum pipe_shader_ir ir_type,
1091 enum pipe_compute_cap param, void *ret)
1092 {
1093 struct si_screen *sscreen = (struct si_screen *)screen;
1094
1095 // TODO: select these params by asic
1096 switch (param) {
1097 case PIPE_COMPUTE_CAP_IR_TARGET: {
1098 const char *gpu, *triple;
1099
1100 triple = "amdgcn-mesa-mesa3d";
1101 gpu = ac_get_llvm_processor_name(sscreen->info.family);
1102 if (ret) {
1103 sprintf(ret, "%s-%s", gpu, triple);
1104 }
1105 /* +2 for dash and terminating NIL byte */
1106 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
1107 }
1108 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
1109 if (ret) {
1110 uint64_t *grid_dimension = ret;
1111 grid_dimension[0] = 3;
1112 }
1113 return 1 * sizeof(uint64_t);
1114
1115 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
1116 if (ret) {
1117 uint64_t *grid_size = ret;
1118 /* Use this size, so that internal counters don't overflow 64 bits. */
1119 grid_size[0] = UINT32_MAX;
1120 grid_size[1] = UINT16_MAX;
1121 grid_size[2] = UINT16_MAX;
1122 }
1123 return 3 * sizeof(uint64_t);
1124
1125 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
1126 if (ret) {
1127 uint64_t *block_size = ret;
1128 unsigned threads_per_block = get_max_threads_per_block(sscreen, ir_type);
1129 block_size[0] = threads_per_block;
1130 block_size[1] = threads_per_block;
1131 block_size[2] = threads_per_block;
1132 }
1133 return 3 * sizeof(uint64_t);
1134
1135 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
1136 if (ret) {
1137 uint64_t *max_threads_per_block = ret;
1138 *max_threads_per_block = get_max_threads_per_block(sscreen, ir_type);
1139 }
1140 return sizeof(uint64_t);
1141 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
1142 if (ret) {
1143 uint32_t *address_bits = ret;
1144 address_bits[0] = 64;
1145 }
1146 return 1 * sizeof(uint32_t);
1147
1148 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
1149 if (ret) {
1150 uint64_t *max_global_size = ret;
1151 uint64_t max_mem_alloc_size;
1152
1153 si_get_compute_param(screen, ir_type, PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
1154 &max_mem_alloc_size);
1155
1156 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
1157 * 1/4 of the MAX_GLOBAL_SIZE. Since the
1158 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
1159 * make sure we never report more than
1160 * 4 * MAX_MEM_ALLOC_SIZE.
1161 */
1162 *max_global_size =
1163 MIN2(4 * max_mem_alloc_size, sscreen->info.max_heap_size_kb * 1024ull);
1164 }
1165 return sizeof(uint64_t);
1166
1167 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
1168 if (ret) {
1169 uint64_t *max_local_size = ret;
1170 /* Value reported by the closed source driver. */
1171 if (sscreen->info.gfx_level == GFX6)
1172 *max_local_size = 32 * 1024;
1173 else
1174 *max_local_size = 64 * 1024;
1175 }
1176 return sizeof(uint64_t);
1177
1178 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
1179 if (ret) {
1180 uint64_t *max_input_size = ret;
1181 /* Value reported by the closed source driver. */
1182 *max_input_size = 1024;
1183 }
1184 return sizeof(uint64_t);
1185
1186 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
1187 if (ret) {
1188 uint64_t *max_mem_alloc_size = ret;
1189
1190 /* Return 1/4 of the heap size as the maximum because the max size is not practically
1191 * allocatable.
1192 */
1193 *max_mem_alloc_size = (sscreen->info.max_heap_size_kb / 4) * 1024ull;
1194 }
1195 return sizeof(uint64_t);
1196
1197 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
1198 if (ret) {
1199 uint32_t *max_clock_frequency = ret;
1200 *max_clock_frequency = sscreen->info.max_gpu_freq_mhz;
1201 }
1202 return sizeof(uint32_t);
1203
1204 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
1205 if (ret) {
1206 uint32_t *max_compute_units = ret;
1207 *max_compute_units = sscreen->info.num_cu;
1208 }
1209 return sizeof(uint32_t);
1210
1211 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
1212 if (ret) {
1213 uint32_t *images_supported = ret;
1214 *images_supported = 0;
1215 }
1216 return sizeof(uint32_t);
1217 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
1218 break; /* unused */
1219 case PIPE_COMPUTE_CAP_MAX_SUBGROUPS: {
1220 if (ret) {
1221 uint32_t *max_subgroups = ret;
1222 unsigned threads = get_max_threads_per_block(sscreen, ir_type);
1223 unsigned subgroup_size;
1224
1225 if (sscreen->debug_flags & DBG(W64_CS) || sscreen->info.gfx_level < GFX10)
1226 subgroup_size = 64;
1227 else
1228 subgroup_size = 32;
1229
1230 *max_subgroups = threads / subgroup_size;
1231 }
1232 return sizeof(uint32_t);
1233 }
1234 case PIPE_COMPUTE_CAP_SUBGROUP_SIZES:
1235 if (ret) {
1236 uint32_t *subgroup_size = ret;
1237 if (sscreen->debug_flags & DBG(W32_CS))
1238 *subgroup_size = 32;
1239 else if (sscreen->debug_flags & DBG(W64_CS))
1240 *subgroup_size = 64;
1241 else
1242 *subgroup_size = sscreen->info.gfx_level < GFX10 ? 64 : 64 | 32;
1243 }
1244 return sizeof(uint32_t);
1245 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
1246 if (ret) {
1247 uint64_t *max_variable_threads_per_block = ret;
1248 if (ir_type == PIPE_SHADER_IR_NATIVE)
1249 *max_variable_threads_per_block = 0;
1250 else
1251 *max_variable_threads_per_block = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
1252 }
1253 return sizeof(uint64_t);
1254 }
1255
1256 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
1257 return 0;
1258 }
1259
si_get_timestamp(struct pipe_screen * screen)1260 static uint64_t si_get_timestamp(struct pipe_screen *screen)
1261 {
1262 struct si_screen *sscreen = (struct si_screen *)screen;
1263
1264 return 1000000 * sscreen->ws->query_value(sscreen->ws, RADEON_TIMESTAMP) /
1265 sscreen->info.clock_crystal_freq;
1266 }
1267
si_query_memory_info(struct pipe_screen * screen,struct pipe_memory_info * info)1268 static void si_query_memory_info(struct pipe_screen *screen, struct pipe_memory_info *info)
1269 {
1270 struct si_screen *sscreen = (struct si_screen *)screen;
1271 struct radeon_winsys *ws = sscreen->ws;
1272 unsigned vram_usage, gtt_usage;
1273
1274 info->total_device_memory = sscreen->info.vram_size_kb;
1275 info->total_staging_memory = sscreen->info.gart_size_kb;
1276
1277 /* The real TTM memory usage is somewhat random, because:
1278 *
1279 * 1) TTM delays freeing memory, because it can only free it after
1280 * fences expire.
1281 *
1282 * 2) The memory usage can be really low if big VRAM evictions are
1283 * taking place, but the real usage is well above the size of VRAM.
1284 *
1285 * Instead, return statistics of this process.
1286 */
1287 vram_usage = ws->query_value(ws, RADEON_VRAM_USAGE) / 1024;
1288 gtt_usage = ws->query_value(ws, RADEON_GTT_USAGE) / 1024;
1289
1290 info->avail_device_memory =
1291 vram_usage <= info->total_device_memory ? info->total_device_memory - vram_usage : 0;
1292 info->avail_staging_memory =
1293 gtt_usage <= info->total_staging_memory ? info->total_staging_memory - gtt_usage : 0;
1294
1295 info->device_memory_evicted = ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
1296
1297 if (sscreen->info.is_amdgpu)
1298 info->nr_device_memory_evictions = ws->query_value(ws, RADEON_NUM_EVICTIONS);
1299 else
1300 /* Just return the number of evicted 64KB pages. */
1301 info->nr_device_memory_evictions = info->device_memory_evicted / 64;
1302 }
1303
si_get_disk_shader_cache(struct pipe_screen * pscreen)1304 static struct disk_cache *si_get_disk_shader_cache(struct pipe_screen *pscreen)
1305 {
1306 struct si_screen *sscreen = (struct si_screen *)pscreen;
1307
1308 return sscreen->disk_shader_cache;
1309 }
1310
si_init_renderer_string(struct si_screen * sscreen)1311 static void si_init_renderer_string(struct si_screen *sscreen)
1312 {
1313 char first_name[256], second_name[32] = {}, kernel_version[128] = {};
1314 struct utsname uname_data;
1315
1316 snprintf(first_name, sizeof(first_name), "%s",
1317 sscreen->info.marketing_name ? sscreen->info.marketing_name : sscreen->info.name);
1318 snprintf(second_name, sizeof(second_name), "%s, ", sscreen->info.lowercase_name);
1319
1320 if (uname(&uname_data) == 0)
1321 snprintf(kernel_version, sizeof(kernel_version), ", %s", uname_data.release);
1322
1323 const char *compiler_name =
1324 #if LLVM_AVAILABLE
1325 !sscreen->use_aco ? "LLVM " MESA_LLVM_VERSION_STRING :
1326 #endif
1327 "ACO";
1328
1329 snprintf(sscreen->renderer_string, sizeof(sscreen->renderer_string),
1330 "%s (radeonsi, %s%s, DRM %i.%i%s)", first_name, second_name, compiler_name,
1331 sscreen->info.drm_major, sscreen->info.drm_minor, kernel_version);
1332 }
1333
si_get_screen_fd(struct pipe_screen * screen)1334 static int si_get_screen_fd(struct pipe_screen *screen)
1335 {
1336 struct si_screen *sscreen = (struct si_screen *)screen;
1337 struct radeon_winsys *ws = sscreen->ws;
1338
1339 return ws->get_fd(ws);
1340 }
1341
si_init_screen_get_functions(struct si_screen * sscreen)1342 void si_init_screen_get_functions(struct si_screen *sscreen)
1343 {
1344 sscreen->b.get_name = si_get_name;
1345 sscreen->b.get_vendor = si_get_vendor;
1346 sscreen->b.get_device_vendor = si_get_device_vendor;
1347 sscreen->b.get_screen_fd = si_get_screen_fd;
1348 sscreen->b.get_param = si_get_param;
1349 sscreen->b.get_paramf = si_get_paramf;
1350 sscreen->b.get_compute_param = si_get_compute_param;
1351 sscreen->b.get_timestamp = si_get_timestamp;
1352 sscreen->b.get_shader_param = si_get_shader_param;
1353 sscreen->b.get_compiler_options = si_get_compiler_options;
1354 sscreen->b.get_device_uuid = si_get_device_uuid;
1355 sscreen->b.get_driver_uuid = si_get_driver_uuid;
1356 sscreen->b.query_memory_info = si_query_memory_info;
1357 sscreen->b.get_disk_shader_cache = si_get_disk_shader_cache;
1358
1359 if (sscreen->info.ip[AMD_IP_UVD].num_queues ||
1360 ((sscreen->info.vcn_ip_version >= VCN_4_0_0) ?
1361 sscreen->info.ip[AMD_IP_VCN_UNIFIED].num_queues : sscreen->info.ip[AMD_IP_VCN_DEC].num_queues) ||
1362 sscreen->info.ip[AMD_IP_VCN_JPEG].num_queues || sscreen->info.ip[AMD_IP_VCE].num_queues ||
1363 sscreen->info.ip[AMD_IP_UVD_ENC].num_queues || sscreen->info.ip[AMD_IP_VCN_ENC].num_queues ||
1364 sscreen->info.ip[AMD_IP_VPE].num_queues) {
1365 sscreen->b.get_video_param = si_get_video_param;
1366 sscreen->b.is_video_format_supported = si_vid_is_format_supported;
1367 } else {
1368 sscreen->b.get_video_param = si_get_video_param_no_video_hw;
1369 sscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
1370 }
1371
1372 si_init_renderer_string(sscreen);
1373
1374 /* |---------------------------------- Performance & Availability --------------------------------|
1375 * |MAD/MAC/MADAK/MADMK|MAD_LEGACY|MAC_LEGACY| FMA |FMAC/FMAAK/FMAMK|FMA_LEGACY|PK_FMA_F16,|Best choice
1376 * Arch | F32,F16,F64 | F32,F16 | F32,F16 |F32,F16,F64 | F32,F16 | F32 |PK_FMAC_F16|F16,F32,F64
1377 * ------------------------------------------------------------------------------------------------------------------
1378 * gfx6,7 | 1 , - , - | 1 , - | 1 , - |1/4, - ,1/16| - , - | - | - , - | - ,MAD,FMA
1379 * gfx8 | 1 , 1 , - | 1 , - | - , - |1/4, 1 ,1/16| - , - | - | - , - |MAD,MAD,FMA
1380 * gfx9 | 1 ,1|0, - | 1 , - | - , - | 1 , 1 ,1/16| 0|1, - | - | 2 , - |FMA,MAD,FMA
1381 * gfx10 | 1 , - , - | 1 , - | 1 , - | 1 , 1 ,1/16| 1 , 1 | - | 2 , 2 |FMA,MAD,FMA
1382 * gfx10.3| - , - , - | - , - | - , - | 1 , 1 ,1/16| 1 , 1 | 1 | 2 , 2 | all FMA
1383 * gfx11 | - , - , - | - , - | - , - | 2 , 2 ,1/16| 2 , 2 | 2 | 2 , 2 | all FMA
1384 *
1385 * Tahiti, Hawaii, Carrizo, Vega20: FMA_F32 is full rate, FMA_F64 is 1/4
1386 * gfx9 supports MAD_F16 only on Vega10, Raven, Raven2, Renoir.
1387 * gfx9 supports FMAC_F32 only on Vega20, but doesn't support FMAAK and FMAMK.
1388 *
1389 * gfx8 prefers MAD for F16 because of MAC/MADAK/MADMK.
1390 * gfx9 and newer prefer FMA for F16 because of the packed instruction.
1391 * gfx10 and older prefer MAD for F32 because of the legacy instruction.
1392 */
1393 bool use_fma32 =
1394 sscreen->info.gfx_level >= GFX10_3 ||
1395 (sscreen->info.family >= CHIP_GFX940 && !sscreen->info.has_graphics) ||
1396 /* fma32 is too slow for gpu < gfx9, so apply the option only for gpu >= gfx9 */
1397 (sscreen->info.gfx_level >= GFX9 && sscreen->options.force_use_fma32);
1398
1399 nir_shader_compiler_options *options = sscreen->nir_options;
1400 ac_set_nir_options(&sscreen->info, !sscreen->use_aco, options);
1401
1402 options->lower_ffma16 = sscreen->info.gfx_level < GFX9;
1403 options->lower_ffma32 = !use_fma32;
1404 options->lower_ffma64 = false;
1405 options->fuse_ffma16 = sscreen->info.gfx_level >= GFX9;
1406 options->fuse_ffma32 = use_fma32;
1407 options->fuse_ffma64 = true;
1408 options->lower_uniforms_to_ubo = true;
1409 options->lower_layer_fs_input_to_sysval = true;
1410 options->optimize_sample_mask_in = true;
1411 options->lower_to_scalar = true;
1412 options->lower_to_scalar_filter =
1413 sscreen->info.has_packed_math_16bit ? si_alu_to_scalar_packed_math_filter : NULL;
1414 options->max_unroll_iterations = 128;
1415 options->max_unroll_iterations_aggressive = 128;
1416 /* For OpenGL, rounding mode is undefined. We want fast packing with v_cvt_pkrtz_f16,
1417 * but if we use it, all f32->f16 conversions have to round towards zero,
1418 * because both scalar and vec2 down-conversions have to round equally.
1419 *
1420 * For OpenCL, rounding mode is explicit. This will only lower f2f16 to f2f16_rtz
1421 * when execution mode is rtz instead of rtne.
1422 */
1423 options->force_f2f16_rtz = true;
1424 options->io_options = nir_io_has_flexible_input_interpolation_except_flat |
1425 nir_io_glsl_lower_derefs;
1426 /* HW supports indirect indexing for: | Enabled in driver
1427 * -------------------------------------------------------
1428 * TCS inputs | Yes
1429 * TES inputs | Yes
1430 * GS inputs | No
1431 * -------------------------------------------------------
1432 * VS outputs before TCS | No
1433 * TCS outputs | Yes
1434 * VS/TES outputs before GS | No
1435 */
1436 options->support_indirect_inputs = BITFIELD_BIT(MESA_SHADER_TESS_CTRL) |
1437 BITFIELD_BIT(MESA_SHADER_TESS_EVAL);
1438 options->support_indirect_outputs = BITFIELD_BIT(MESA_SHADER_TESS_CTRL);
1439 }
1440