1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
4 *
5 * SPDX-License-Identifier: MIT
6 */
7 #ifndef SI_PIPE_H
8 #define SI_PIPE_H
9
10 #include "si_shader.h"
11 #include "si_state.h"
12 #include "winsys/radeon_winsys.h"
13 #include "util/u_blitter.h"
14 #include "util/u_idalloc.h"
15 #include "util/u_suballoc.h"
16 #include "util/u_threaded_context.h"
17 #include "util/u_vertex_state_cache.h"
18 #include "util/perf/u_trace.h"
19 #include "ac_sqtt.h"
20 #include "ac_spm.h"
21 #include "si_perfetto.h"
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 struct ac_llvm_compiler;
28
29 #define ATI_VENDOR_ID 0x1002
30 #define SI_NOT_QUERY 0xffffffff
31
32 /* special primitive types */
33 #define SI_PRIM_RECTANGLE_LIST MESA_PRIM_COUNT
34
35 /* The primitive restart can be any number, but we must pick one which will
36 * mean "unknown" for the purpose of state tracking and the number shouldn't
37 * be a commonly-used one.
38 */
39 #define SI_RESTART_INDEX_UNKNOWN ((unsigned)INT_MIN)
40 #define SI_INSTANCE_COUNT_UNKNOWN ((unsigned)INT_MIN)
41 #define SI_NUM_SMOOTH_AA_SAMPLES 4
42 #define SI_MAX_POINT_SIZE 2048
43 #define SI_GS_PER_ES 128
44 /* Alignment for optimal CP DMA performance. */
45 #define SI_CPDMA_ALIGNMENT 32
46
47 /* Tunables for compute-based clear_buffer and copy_buffer: */
48 #define SI_COMPUTE_CLEAR_DW_PER_THREAD 4
49 #define SI_COMPUTE_COPY_DW_PER_THREAD 4
50 /* L2 LRU is recommended because the compute shader can finish sooner due to fewer L2 evictions. */
51 #define SI_COMPUTE_DST_CACHE_POLICY L2_LRU
52
53 /* Pipeline & streamout query controls. */
54 #define SI_CONTEXT_START_PIPELINE_STATS (1 << 0)
55 #define SI_CONTEXT_STOP_PIPELINE_STATS (1 << 1)
56 /* gap */
57 /* Instruction cache. */
58 #define SI_CONTEXT_INV_ICACHE (1 << 3)
59 /* Scalar cache. (GFX6-9: scalar L1; GFX10: scalar L0)
60 * GFX10: This also invalidates the L1 shader array cache. */
61 #define SI_CONTEXT_INV_SCACHE (1 << 4)
62 /* Vector cache. (GFX6-9: vector L1; GFX10: vector L0)
63 * GFX10: This also invalidates the L1 shader array cache. */
64 #define SI_CONTEXT_INV_VCACHE (1 << 5)
65 /* L2 cache + L2 metadata cache writeback & invalidate.
66 * GFX6-8: Used by shaders only. GFX9-10: Used by everything. */
67 #define SI_CONTEXT_INV_L2 (1 << 6)
68 /* L2 writeback (write dirty L2 lines to memory for non-L2 clients).
69 * Only used for coherency with non-L2 clients like CB, DB, CP on GFX6-8.
70 * GFX6-7 will do complete invalidation, because the writeback is unsupported. */
71 #define SI_CONTEXT_WB_L2 (1 << 7)
72 /* Writeback & invalidate the L2 metadata cache only. It can only be coupled with
73 * a CB or DB flush. */
74 #define SI_CONTEXT_INV_L2_METADATA (1 << 8)
75 /* Framebuffer caches. */
76 #define SI_CONTEXT_FLUSH_AND_INV_DB (1 << 9)
77 #define SI_CONTEXT_FLUSH_AND_INV_DB_META (1 << 10)
78 #define SI_CONTEXT_FLUSH_AND_INV_CB (1 << 11)
79 /* Engine synchronization. */
80 #define SI_CONTEXT_VS_PARTIAL_FLUSH (1 << 12)
81 #define SI_CONTEXT_PS_PARTIAL_FLUSH (1 << 13)
82 #define SI_CONTEXT_CS_PARTIAL_FLUSH (1 << 14)
83 #define SI_CONTEXT_VGT_FLUSH (1 << 15)
84 #define SI_CONTEXT_VGT_STREAMOUT_SYNC (1 << 16)
85 /* PFP waits for ME to finish. Used to sync for index and indirect buffers and render
86 * condition. It's typically set when doing a VS/PS/CS partial flush for buffers. */
87 #define SI_CONTEXT_PFP_SYNC_ME (1 << 17)
88
89 #define SI_PREFETCH_LS (1 << 1)
90 #define SI_PREFETCH_HS (1 << 2)
91 #define SI_PREFETCH_ES (1 << 3)
92 #define SI_PREFETCH_GS (1 << 4)
93 #define SI_PREFETCH_VS (1 << 5)
94 #define SI_PREFETCH_PS (1 << 6)
95
96 #define SI_MAX_BORDER_COLORS 4096
97 #define SI_MAX_VIEWPORTS 16
98 #define SI_MAP_BUFFER_ALIGNMENT 64
99 /* We only support the minimum allowed value (512), so that we can pack a 3D block size
100 * in 1 SGPR. */
101 #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 512
102
103 #define SI_CONTEXT_FLAG_AUX (1u << 31)
104
105 #define SI_RESOURCE_FLAG_FORCE_LINEAR (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
106 #define SI_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
107 #define SI_RESOURCE_FLAG_FORCE_MSAA_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
108 #define SI_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
109 #define SI_RESOURCE_FLAG_DRIVER_INTERNAL (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
110 #define SI_RESOURCE_FLAG_READ_ONLY (PIPE_RESOURCE_FLAG_DRV_PRIV << 5)
111 #define SI_RESOURCE_FLAG_32BIT (PIPE_RESOURCE_FLAG_DRV_PRIV << 6)
112 #define SI_RESOURCE_FLAG_CLEAR (PIPE_RESOURCE_FLAG_DRV_PRIV << 7)
113 #define SI_RESOURCE_AUX_PLANE (PIPE_RESOURCE_FLAG_DRV_PRIV << 8)
114 /* Set a micro tile mode: */
115 #define SI_RESOURCE_FLAG_FORCE_MICRO_TILE_MODE (PIPE_RESOURCE_FLAG_DRV_PRIV << 9)
116 #define SI_RESOURCE_FLAG_MICRO_TILE_MODE_SHIFT (util_logbase2(PIPE_RESOURCE_FLAG_DRV_PRIV) + 10)
117 #define SI_RESOURCE_FLAG_MICRO_TILE_MODE_SET(x) \
118 (((x)&0x3) << SI_RESOURCE_FLAG_MICRO_TILE_MODE_SHIFT)
119 #define SI_RESOURCE_FLAG_MICRO_TILE_MODE_GET(x) \
120 (((x) >> SI_RESOURCE_FLAG_MICRO_TILE_MODE_SHIFT) & 0x3)
121 #define SI_RESOURCE_FLAG_GL2_BYPASS (PIPE_RESOURCE_FLAG_DRV_PRIV << 12)
122 /* Discard instead of evict. */
123 #define SI_RESOURCE_FLAG_DISCARDABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 13)
124
125 enum si_has_gs {
126 GS_OFF,
127 GS_ON,
128 };
129
130 enum si_has_tess {
131 TESS_OFF,
132 TESS_ON,
133 };
134
135 enum si_has_ngg {
136 NGG_OFF,
137 NGG_ON,
138 };
139
140 #define DCC_CODE(x) (((x) << 24) | ((x) << 16) | ((x) << 8) | (x))
141
142 enum si_clear_code
143 {
144 /* Common clear codes. */
145 DCC_CLEAR_0000 = DCC_CODE(0x00), /* all bits are 0 */
146 DCC_UNCOMPRESSED = DCC_CODE(0xFF),
147
148 GFX8_DCC_CLEAR_0000 = DCC_CLEAR_0000,
149 GFX8_DCC_CLEAR_0001 = DCC_CODE(0x40),
150 GFX8_DCC_CLEAR_1110 = DCC_CODE(0x80),
151 GFX8_DCC_CLEAR_1111 = DCC_CODE(0xC0),
152 GFX8_DCC_CLEAR_REG = DCC_CODE(0x20),
153 GFX9_DCC_CLEAR_SINGLE = DCC_CODE(0x10),
154
155 GFX11_DCC_CLEAR_SINGLE = DCC_CODE(0x01),
156 GFX11_DCC_CLEAR_0000 = DCC_CLEAR_0000, /* all bits are 0 */
157 GFX11_DCC_CLEAR_1111_UNORM = DCC_CODE(0x02), /* all bits are 1 */
158 GFX11_DCC_CLEAR_1111_FP16 = DCC_CODE(0x04), /* all 16-bit words are 0x3c00, max 64bpp */
159 GFX11_DCC_CLEAR_1111_FP32 = DCC_CODE(0x06), /* all 32-bit words are 0x3f800000 */
160 /* Color bits are 0, alpha bits are 1; only 88, 8888, 16161616 */
161 GFX11_DCC_CLEAR_0001_UNORM = DCC_CODE(0x08),
162 /* Color bits are 1, alpha bits are 0, only 88, 8888, 16161616 */
163 GFX11_DCC_CLEAR_1110_UNORM = DCC_CODE(0x0A),
164 };
165
166 #define SI_IMAGE_ACCESS_DCC_OFF (1 << 8)
167 #define SI_IMAGE_ACCESS_ALLOW_DCC_STORE (1 << 9)
168 #define SI_IMAGE_ACCESS_BLOCK_FORMAT_AS_UINT (1 << 10) /* for compressed/subsampled images */
169
170 enum si_occlusion_query_mode {
171 SI_OCCLUSION_QUERY_MODE_DISABLE,
172 SI_OCCLUSION_QUERY_MODE_PRECISE_INTEGER,
173 SI_OCCLUSION_QUERY_MODE_PRECISE_BOOLEAN,
174 SI_OCCLUSION_QUERY_MODE_CONSERVATIVE_BOOLEAN,
175 };
176
177 /* Debug flags. */
178 enum
179 {
180 /* Shader logging options: */
181 DBG_VS = MESA_SHADER_VERTEX,
182 DBG_TCS = MESA_SHADER_TESS_CTRL,
183 DBG_TES = MESA_SHADER_TESS_EVAL,
184 DBG_GS = MESA_SHADER_GEOMETRY,
185 DBG_PS = MESA_SHADER_FRAGMENT,
186 DBG_CS = MESA_SHADER_COMPUTE,
187 DBG_INIT_NIR,
188 DBG_NIR,
189 DBG_INIT_LLVM,
190 DBG_LLVM,
191 DBG_INIT_ACO,
192 DBG_ACO,
193 DBG_ASM,
194 DBG_STATS,
195
196 /* Shader compiler options the shader cache should be aware of: */
197 DBG_W32_GE,
198 DBG_W32_PS,
199 DBG_W32_CS,
200 DBG_W64_GE,
201 DBG_W64_PS,
202 DBG_W64_CS,
203
204 /* Shader compiler options (with no effect on the shader cache): */
205 DBG_CHECK_IR,
206 DBG_MONOLITHIC_SHADERS,
207 DBG_NO_OPT_VARIANT,
208
209 /* Information logging options: */
210 DBG_INFO,
211 DBG_TEX,
212 DBG_COMPUTE,
213 DBG_VM,
214 DBG_CACHE_STATS,
215 DBG_IB,
216 DBG_VERTEX_ELEMENTS,
217
218 /* Driver options: */
219 DBG_NO_WC,
220 DBG_NO_WC_STREAM,
221 DBG_CHECK_VM,
222 DBG_RESERVE_VMID,
223 DBG_SHADOW_REGS,
224 DBG_NO_FAST_DISPLAY_LIST,
225 DBG_NO_DMA_SHADERS,
226
227 /* Multimedia options: */
228 DBG_NO_EFC,
229
230 /* 3D engine options: */
231 DBG_NO_NGG,
232 DBG_ALWAYS_NGG_CULLING_ALL,
233 DBG_NO_NGG_CULLING,
234 DBG_SWITCH_ON_EOP,
235 DBG_NO_OUT_OF_ORDER,
236 DBG_NO_DPBB,
237 DBG_DPBB,
238 DBG_NO_HYPERZ,
239 DBG_NO_2D_TILING,
240 DBG_NO_TILING,
241 DBG_NO_DISPLAY_TILING,
242 DBG_NO_DISPLAY_DCC,
243 DBG_NO_EXPORTED_DCC,
244 DBG_NO_DCC,
245 DBG_NO_DCC_CLEAR,
246 DBG_NO_DCC_STORE,
247 DBG_DCC_STORE,
248 DBG_NO_DCC_MSAA,
249 DBG_NO_FMASK,
250 DBG_NO_DMA,
251
252 DBG_EXTRA_METADATA,
253
254 DBG_TMZ,
255 DBG_SQTT,
256 DBG_USE_ACO,
257
258 DBG_COUNT
259 };
260
261 enum
262 {
263 /* Tests: */
264 DBG_TEST_IMAGE_COPY,
265 DBG_TEST_CB_RESOLVE,
266 DBG_TEST_COMPUTE_BLIT,
267 DBG_TEST_VMFAULT_CP,
268 DBG_TEST_VMFAULT_SHADER,
269 DBG_TEST_DMA_PERF,
270 DBG_TEST_GDS,
271 DBG_TEST_GDS_MM,
272 DBG_TEST_GDS_OA_MM,
273 };
274
275 #define DBG_ALL_SHADERS (((1 << (DBG_CS + 1)) - 1))
276 #define DBG(name) (1ull << DBG_##name)
277
278 enum si_cache_policy
279 {
280 L2_BYPASS,
281 L2_STREAM, /* same as SLC=1 */
282 L2_LRU, /* same as SLC=0 */
283 };
284
285 enum si_coherency
286 {
287 SI_COHERENCY_NONE, /* no cache flushes needed */
288 SI_COHERENCY_SHADER,
289 SI_COHERENCY_CB_META,
290 SI_COHERENCY_DB_META,
291 SI_COHERENCY_CP,
292 };
293
294 #define SI_BIND_CONSTANT_BUFFER_SHIFT 0
295 #define SI_BIND_SHADER_BUFFER_SHIFT 6
296 #define SI_BIND_IMAGE_BUFFER_SHIFT 12
297 #define SI_BIND_SAMPLER_BUFFER_SHIFT 18
298 #define SI_BIND_OTHER_BUFFER_SHIFT 24
299
300 /* Bind masks for all 6 shader stages. */
301 #define SI_BIND_CONSTANT_BUFFER_ALL (0x3f << SI_BIND_CONSTANT_BUFFER_SHIFT)
302 #define SI_BIND_SHADER_BUFFER_ALL (0x3f << SI_BIND_SHADER_BUFFER_SHIFT)
303 #define SI_BIND_IMAGE_BUFFER_ALL (0x3f << SI_BIND_IMAGE_BUFFER_SHIFT)
304 #define SI_BIND_SAMPLER_BUFFER_ALL (0x3f << SI_BIND_SAMPLER_BUFFER_SHIFT)
305
306 #define SI_BIND_CONSTANT_BUFFER(shader) ((1 << (shader)) << SI_BIND_CONSTANT_BUFFER_SHIFT)
307 #define SI_BIND_SHADER_BUFFER(shader) ((1 << (shader)) << SI_BIND_SHADER_BUFFER_SHIFT)
308 #define SI_BIND_IMAGE_BUFFER(shader) ((1 << (shader)) << SI_BIND_IMAGE_BUFFER_SHIFT)
309 #define SI_BIND_SAMPLER_BUFFER(shader) ((1 << (shader)) << SI_BIND_SAMPLER_BUFFER_SHIFT)
310 #define SI_BIND_VERTEX_BUFFER (1 << (SI_BIND_OTHER_BUFFER_SHIFT + 0))
311 #define SI_BIND_STREAMOUT_BUFFER (1 << (SI_BIND_OTHER_BUFFER_SHIFT + 1))
312
313 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
314 * at the moment.
315 */
316 struct si_resource {
317 struct threaded_resource b;
318
319 /* If we remove this seemingly useless padding, performance in Viewperf2020/catiav5test1
320 * decreases by 8%.
321 */
322 uint32_t _pad;
323
324 /* Winsys objects. */
325 struct pb_buffer_lean *buf;
326 uint64_t gpu_address;
327
328 /* Resource properties. */
329 uint64_t bo_size;
330 uint8_t bo_alignment_log2;
331 enum radeon_bo_domain domains:8;
332 enum radeon_bo_flag flags:16;
333 unsigned bind_history; /* bitmask of SI_BIND_xxx_BUFFER */
334
335 /* The buffer range which is initialized (with a write transfer,
336 * streamout, DMA, or as a random access target). The rest of
337 * the buffer is considered invalid and can be mapped unsynchronized.
338 *
339 * This allows unsynchronized mapping of a buffer range which hasn't
340 * been used yet. It's for applications which forget to use
341 * the unsynchronized map flag and expect the driver to figure it out.
342 */
343 struct util_range valid_buffer_range;
344
345 /* For buffers only. This indicates that a write operation has been
346 * performed by TC L2, but the cache hasn't been flushed.
347 * Any hw block which doesn't use or bypasses TC L2 should check this
348 * flag and flush the cache before using the buffer.
349 *
350 * For example, TC L2 must be flushed if a buffer which has been
351 * modified by a shader store instruction is about to be used as
352 * an index buffer. The reason is that VGT DMA index fetching doesn't
353 * use TC L2.
354 */
355 bool TC_L2_dirty;
356
357 /* Whether this resource is referenced by bindless handles. */
358 bool texture_handle_allocated;
359 bool image_handle_allocated;
360
361 /* Whether the resource has been exported via resource_get_handle. */
362 uint8_t external_usage; /* PIPE_HANDLE_USAGE_* */
363 };
364
365 struct si_transfer {
366 struct threaded_transfer b;
367 struct si_resource *staging;
368 };
369
370 struct si_texture {
371 struct si_resource buffer;
372
373 struct radeon_surf surface;
374 struct si_texture *flushed_depth_texture;
375
376 /* One texture allocation can contain these buffers:
377 * - image (pixel data)
378 * - FMASK buffer (MSAA compression)
379 * - CMASK buffer (MSAA compression and/or legacy fast color clear)
380 * - HTILE buffer (Z/S compression and fast Z/S clear)
381 * - DCC buffer (color compression and new fast color clear)
382 * - displayable DCC buffer (if the DCC buffer is not displayable)
383 */
384 uint64_t cmask_base_address_reg;
385 struct si_resource *cmask_buffer;
386 unsigned cb_color_info; /* fast clear enable bit */
387 unsigned color_clear_value[2]; /* not on gfx11 */
388 unsigned last_msaa_resolve_target_micro_mode;
389 bool swap_rgb_to_bgr_on_next_clear;
390 bool swap_rgb_to_bgr;
391 unsigned num_level0_transfers;
392 unsigned plane_index; /* other planes are different pipe_resources */
393 unsigned num_planes;
394 enum pipe_format multi_plane_format;
395
396 /* Depth buffer compression and fast clear. */
397 float depth_clear_value[RADEON_SURF_MAX_LEVELS];
398 uint8_t stencil_clear_value[RADEON_SURF_MAX_LEVELS];
399 uint16_t depth_cleared_level_mask_once; /* if it was cleared at least once */
400 uint16_t depth_cleared_level_mask; /* track if it's cleared (can be false negative) */
401 uint16_t stencil_cleared_level_mask_once; /* if it was cleared at least once */
402 uint16_t dirty_level_mask; /* each bit says if that mipmap is compressed */
403 uint16_t stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */
404 enum pipe_format db_render_format : 16;
405 bool fmask_is_identity : 1;
406 bool tc_compatible_htile : 1;
407 bool enable_tc_compatible_htile_next_clear : 1;
408 bool htile_stencil_disabled : 1;
409 bool upgraded_depth : 1; /* upgraded from unorm to Z32_FLOAT */
410 bool is_depth : 1;
411 bool db_compatible : 1;
412 bool can_sample_z : 1;
413 bool can_sample_s : 1;
414 bool need_flush_after_depth_decompression: 1;
415
416 /* We need to track DCC dirtiness, because st/dri usually calls
417 * flush_resource twice per frame (not a bug) and we don't wanna
418 * decompress DCC twice.
419 */
420 bool displayable_dcc_dirty : 1;
421
422 /* Counter that should be non-zero if the texture is bound to a
423 * framebuffer.
424 */
425 unsigned framebuffers_bound;
426 };
427
428 /* State trackers create separate textures in a next-chain for extra planes
429 * even if those are planes created purely for modifiers. Because the linking
430 * of the chain happens outside of the driver, and NULL is interpreted as
431 * failure, let's create some dummy texture structs. We could use these
432 * later to use the offsets for linking if we really wanted to.
433 *
434 * For now just create a dummy struct and completely ignore it.
435 *
436 * Potentially in the future we could store stride/offset and use it during
437 * creation, though we might want to change how linking is done first.
438 */
439 struct si_auxiliary_texture {
440 struct threaded_resource b;
441 struct pb_buffer_lean *buffer;
442 uint32_t offset;
443 uint32_t stride;
444 };
445
446 struct si_surface {
447 struct pipe_surface base;
448
449 /* These can vary with block-compressed textures. */
450 uint16_t width0;
451 uint16_t height0;
452
453 bool color_initialized : 1;
454 bool depth_initialized : 1;
455
456 /* Misc. color flags. */
457 bool color_is_int8 : 1;
458 bool color_is_int10 : 1;
459 bool dcc_incompatible : 1;
460 uint8_t db_format_index : 3;
461
462 /* Color registers. */
463 unsigned cb_color_info;
464 unsigned cb_color_view;
465 unsigned cb_color_attrib;
466 unsigned cb_color_attrib2; /* GFX9 and later */
467 unsigned cb_color_attrib3; /* GFX10 and later */
468 unsigned cb_dcc_control; /* GFX8 and later */
469 unsigned spi_shader_col_format : 8; /* no blending, no alpha-to-coverage. */
470 unsigned spi_shader_col_format_alpha : 8; /* alpha-to-coverage */
471 unsigned spi_shader_col_format_blend : 8; /* blending without alpha. */
472 unsigned spi_shader_col_format_blend_alpha : 8; /* blending with alpha. */
473
474 /* DB registers. */
475 uint64_t db_depth_base; /* DB_Z_READ/WRITE_BASE */
476 uint64_t db_stencil_base;
477 uint64_t db_htile_data_base;
478 unsigned db_depth_info;
479 unsigned db_z_info;
480 unsigned db_z_info2; /* GFX9 only */
481 unsigned db_depth_view;
482 unsigned db_depth_size;
483 unsigned db_depth_slice;
484 unsigned db_stencil_info;
485 unsigned db_stencil_info2; /* GFX9 only */
486 unsigned db_htile_surface;
487 };
488
489 struct si_mmio_counter {
490 unsigned busy;
491 unsigned idle;
492 };
493
494 union si_mmio_counters {
495 struct si_mmio_counters_named {
496 /* For global GPU load including SDMA. */
497 struct si_mmio_counter gpu;
498
499 /* GRBM_STATUS */
500 struct si_mmio_counter spi;
501 struct si_mmio_counter gui;
502 struct si_mmio_counter ta;
503 struct si_mmio_counter gds;
504 struct si_mmio_counter vgt;
505 struct si_mmio_counter ia;
506 struct si_mmio_counter sx;
507 struct si_mmio_counter wd;
508 struct si_mmio_counter bci;
509 struct si_mmio_counter sc;
510 struct si_mmio_counter pa;
511 struct si_mmio_counter db;
512 struct si_mmio_counter cp;
513 struct si_mmio_counter cb;
514
515 /* SRBM_STATUS2 */
516 struct si_mmio_counter sdma;
517
518 /* CP_STAT */
519 struct si_mmio_counter pfp;
520 struct si_mmio_counter meq;
521 struct si_mmio_counter me;
522 struct si_mmio_counter surf_sync;
523 struct si_mmio_counter cp_dma;
524 struct si_mmio_counter scratch_ram;
525 } named;
526
527 unsigned array[sizeof(struct si_mmio_counters_named) / sizeof(unsigned)];
528 };
529
530 struct si_memory_object {
531 struct pipe_memory_object b;
532 struct pb_buffer_lean *buf;
533 uint32_t stride;
534 };
535
536 /* Saved CS data for debugging features. */
537 struct radeon_saved_cs {
538 uint32_t *ib;
539 unsigned num_dw;
540
541 struct radeon_bo_list_item *bo_list;
542 unsigned bo_count;
543 };
544
545 struct si_aux_context {
546 struct pipe_context *ctx;
547 mtx_t lock;
548 };
549
550 struct si_screen {
551 struct pipe_screen b;
552 struct radeon_winsys *ws;
553 struct disk_cache *disk_shader_cache;
554
555 struct radeon_info info;
556 struct nir_shader_compiler_options *nir_options;
557 uint64_t debug_flags;
558 char renderer_string[183];
559
560 void (*make_texture_descriptor)(struct si_screen *screen, struct si_texture *tex, bool sampler,
561 enum pipe_texture_target target, enum pipe_format pipe_format,
562 const unsigned char state_swizzle[4], unsigned first_level,
563 unsigned last_level, unsigned first_layer, unsigned last_layer,
564 unsigned width, unsigned height, unsigned depth,
565 bool get_bo_metadata, uint32_t *state, uint32_t *fmask_state);
566
567 unsigned pa_sc_raster_config;
568 unsigned pa_sc_raster_config_1;
569 unsigned se_tile_repeat;
570 unsigned gs_table_depth;
571 struct ac_hs_info hs;
572 unsigned eqaa_force_coverage_samples;
573 unsigned eqaa_force_z_samples;
574 unsigned eqaa_force_color_samples;
575 unsigned pbb_context_states_per_bin;
576 unsigned pbb_persistent_states_per_bin;
577 bool has_draw_indirect_multi;
578 bool dpbb_allowed;
579 bool use_ngg;
580 bool use_ngg_culling;
581 bool allow_dcc_msaa_clear_to_reg_for_bpp[5]; /* indexed by log2(Bpp) */
582 bool always_allow_dcc_stores;
583 bool use_aco;
584
585 struct {
586 #define OPT_BOOL(name, dflt, description) bool name : 1;
587 #define OPT_INT(name, dflt, description) int name;
588 #include "si_debug_options.h"
589 } options;
590
591 /* Whether shaders are monolithic (1-part) or separate (3-part). */
592 bool use_monolithic_shaders;
593 bool record_llvm_ir;
594 const char *context_roll_log_filename;
595
596 struct slab_parent_pool pool_transfers;
597
598 /* Texture filter settings. */
599 int force_aniso; /* -1 = disabled */
600
601 unsigned max_texel_buffer_elements;
602
603 /* Auxiliary context. Used to initialize resources and upload shaders. */
604 union {
605 struct {
606 struct si_aux_context general;
607
608 /* Second auxiliary context for uploading shaders. When the first auxiliary context is
609 * locked and wants to compile and upload shaders, we need to use a second auxiliary
610 * context because the first one is locked.
611 */
612 struct si_aux_context shader_upload;
613 } aux_context;
614 struct si_aux_context aux_contexts[2];
615 };
616
617 /* Async compute context for DRI_PRIME copies. */
618 struct pipe_context *async_compute_context;
619 simple_mtx_t async_compute_context_lock;
620
621 /* This must be in the screen, because UE4 uses one context for
622 * compilation and another one for rendering.
623 */
624 unsigned num_compilations;
625 /* Along with ST_DEBUG=precompile, this should show if applications
626 * are loading shaders on demand. This is a monotonic counter.
627 */
628 unsigned num_shaders_created;
629 unsigned num_memory_shader_cache_hits;
630 unsigned num_memory_shader_cache_misses;
631 unsigned num_disk_shader_cache_hits;
632 unsigned num_disk_shader_cache_misses;
633
634 /* GPU load thread. */
635 simple_mtx_t gpu_load_mutex;
636 thrd_t gpu_load_thread;
637 bool gpu_load_thread_created;
638 union si_mmio_counters mmio_counters;
639 volatile unsigned gpu_load_stop_thread; /* bool */
640
641 /* Performance counters. */
642 struct si_perfcounters *perfcounters;
643
644 /* If pipe_screen wants to recompute and re-emit the framebuffer,
645 * sampler, and image states of all contexts, it should atomically
646 * increment this.
647 *
648 * Each context will compare this with its own last known value of
649 * the counter before drawing and re-emit the states accordingly.
650 */
651 unsigned dirty_tex_counter;
652 unsigned dirty_buf_counter;
653
654 /* Atomically increment this counter when an existing texture's
655 * metadata is enabled or disabled in a way that requires changing
656 * contexts' compressed texture binding masks.
657 */
658 unsigned compressed_colortex_counter;
659
660 struct {
661 /* Context flags to set so that all writes from earlier jobs
662 * in the CP are seen by L2 clients.
663 */
664 unsigned cp_to_L2;
665
666 /* Context flags to set so that all writes from earlier jobs
667 * that end in L2 are seen by CP.
668 */
669 unsigned L2_to_cp;
670 } barrier_flags;
671
672 simple_mtx_t shader_parts_mutex;
673 struct si_shader_part *tcs_epilogs;
674 struct si_shader_part *ps_prologs;
675 struct si_shader_part *ps_epilogs;
676
677 /* Shader cache in memory.
678 *
679 * Design & limitations:
680 * - The shader cache is per screen (= per process), never saved to
681 * disk, and skips redundant shader compilations from NIR to bytecode.
682 * - It can only be used with one-variant-per-shader support, in which
683 * case only the main (typically middle) part of shaders is cached.
684 * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
685 * variants of VS and TES are cached, so LS and ES aren't.
686 * - GS and CS aren't cached, but it's certainly possible to cache
687 * those as well.
688 */
689 simple_mtx_t shader_cache_mutex;
690 struct hash_table *shader_cache;
691 /* Maximum and current size */
692 uint32_t shader_cache_size;
693 uint32_t shader_cache_max_size;
694
695 /* Shader cache of live shaders. */
696 struct util_live_shader_cache live_shader_cache;
697
698 /* Shader compiler queue for multithreaded compilation. */
699 struct util_queue shader_compiler_queue;
700 /* Compiler instances for asynchronous shader compilation of new shader CSOs,
701 * one for each thread of the shader compiler queue.
702 */
703 struct ac_llvm_compiler *compiler[24]; /* used by the queue only */
704
705 struct util_queue shader_compiler_queue_opt_variants;
706 /* Compiler instances for asynchronous shader compilation of optimized shader variants,
707 * one for each thread of the low-priority shader compiler queue. */
708 struct ac_llvm_compiler *compiler_lowp[10];
709
710 struct util_idalloc_mt buffer_ids;
711 struct util_vertex_state_cache vertex_state_cache;
712
713 struct si_resource *attribute_ring;
714
715 /* NGG streamout. */
716 simple_mtx_t gds_mutex;
717 struct pb_buffer_lean *gds_oa;
718 };
719
720 struct si_compute {
721 struct si_shader_selector sel;
722 struct si_shader shader;
723
724 unsigned ir_type;
725 unsigned input_size;
726
727 int max_global_buffers;
728 struct pipe_resource **global_buffers;
729 };
730
731 struct si_sampler_view {
732 struct pipe_sampler_view base;
733 /* [0..7] = image descriptor
734 * [4..7] = buffer descriptor */
735 uint32_t state[8];
736 uint32_t fmask_state[8];
737 const struct legacy_surf_level *base_level_info;
738 uint8_t block_width;
739 bool is_stencil_sampler;
740 bool dcc_incompatible;
741 };
742
743 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
744
745 struct si_sampler_state {
746 #ifndef NDEBUG
747 unsigned magic;
748 #endif
749 uint32_t val[4];
750 uint32_t upgraded_depth_val[4];
751 };
752
753 struct si_cs_shader_state {
754 struct si_compute *program;
755 struct si_compute *emitted_program;
756 unsigned offset;
757 uint32_t variable_shared_size;
758 };
759
760 struct si_samplers {
761 struct pipe_sampler_view *views[SI_NUM_SAMPLERS];
762 struct si_sampler_state *sampler_states[SI_NUM_SAMPLERS];
763
764 /* The i-th bit is set if that element is enabled (non-NULL resource). */
765 unsigned enabled_mask;
766 uint32_t has_depth_tex_mask;
767 uint32_t needs_depth_decompress_mask;
768 uint32_t needs_color_decompress_mask;
769 };
770
771 struct si_images {
772 struct pipe_image_view views[SI_NUM_IMAGES];
773 uint32_t needs_color_decompress_mask;
774 unsigned enabled_mask;
775 unsigned display_dcc_store_mask;
776 };
777
778 struct si_framebuffer {
779 struct pipe_framebuffer_state state;
780 unsigned colorbuf_enabled_4bit;
781 unsigned spi_shader_col_format;
782 unsigned spi_shader_col_format_alpha;
783 unsigned spi_shader_col_format_blend;
784 unsigned spi_shader_col_format_blend_alpha;
785 uint8_t nr_samples : 5; /* at most 16xAA */
786 uint8_t log_samples : 3; /* at most 4 = 16xAA */
787 uint8_t nr_color_samples; /* at most 8xAA */
788 uint8_t compressed_cb_mask;
789 uint8_t uncompressed_cb_mask;
790 uint8_t color_is_int8;
791 uint8_t color_is_int10;
792 uint8_t dirty_cbufs;
793 uint8_t min_bytes_per_pixel;
794 bool dirty_zsbuf;
795 bool any_dst_linear;
796 bool CB_has_shader_readable_metadata;
797 bool DB_has_shader_readable_metadata;
798 bool all_DCC_pipe_aligned;
799 bool has_dcc_msaa;
800 };
801
802 enum si_quant_mode
803 {
804 /* This is the list we want to support. */
805 SI_QUANT_MODE_16_8_FIXED_POINT_1_256TH,
806 SI_QUANT_MODE_14_10_FIXED_POINT_1_1024TH,
807 SI_QUANT_MODE_12_12_FIXED_POINT_1_4096TH,
808 };
809
810 struct si_signed_scissor {
811 int minx;
812 int miny;
813 int maxx;
814 int maxy;
815 enum si_quant_mode quant_mode;
816 };
817
818 struct si_viewports {
819 struct pipe_viewport_state states[SI_MAX_VIEWPORTS];
820 struct si_signed_scissor as_scissor[SI_MAX_VIEWPORTS];
821 };
822
823 struct si_streamout_target {
824 struct pipe_stream_output_target b;
825
826 /* The buffer where BUFFER_FILLED_SIZE is stored. */
827 struct si_resource *buf_filled_size;
828 unsigned buf_filled_size_offset;
829 bool buf_filled_size_valid;
830
831 unsigned stride_in_dw;
832 };
833
834 struct si_streamout {
835 bool begin_emitted;
836
837 unsigned enabled_mask;
838 unsigned num_targets;
839 struct si_streamout_target *targets[PIPE_MAX_SO_BUFFERS];
840
841 unsigned append_bitmask;
842 bool suspended;
843
844 /* External state which comes from the vertex shader,
845 * it must be set explicitly when binding a shader. */
846 uint8_t *stride_in_dw;
847 unsigned enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
848
849 /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
850 unsigned hw_enabled_mask;
851
852 /* The state of VGT_STRMOUT_(CONFIG|EN). */
853 bool streamout_enabled;
854 bool prims_gen_query_enabled;
855 int num_prims_gen_queries;
856 };
857
858 /* A shader state consists of the shader selector, which is a constant state
859 * object shared by multiple contexts and shouldn't be modified, and
860 * the current shader variant selected for this context.
861 */
862 struct si_shader_ctx_state {
863 struct si_shader_selector *cso;
864 struct si_shader *current;
865 /* The shader variant key representing the current state. */
866 union si_shader_key key;
867 };
868
869 #define SI_NUM_VGT_PARAM_KEY_BITS 12
870 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
871
872 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
873 * Some fields are set by state-change calls, most are set by draw_vbo.
874 */
875 union si_vgt_param_key {
876 struct {
877 #if UTIL_ARCH_LITTLE_ENDIAN
878 uint16_t prim : 4;
879 uint16_t uses_instancing : 1;
880 uint16_t multi_instances_smaller_than_primgroup : 1;
881 uint16_t primitive_restart : 1;
882 uint16_t count_from_stream_output : 1;
883 uint16_t line_stipple_enabled : 1;
884 uint16_t uses_tess : 1;
885 uint16_t tess_uses_prim_id : 1;
886 uint16_t uses_gs : 1;
887 uint16_t _pad : 16 - SI_NUM_VGT_PARAM_KEY_BITS;
888 #else /* UTIL_ARCH_BIG_ENDIAN */
889 uint16_t _pad : 16 - SI_NUM_VGT_PARAM_KEY_BITS;
890 uint16_t uses_gs : 1;
891 uint16_t tess_uses_prim_id : 1;
892 uint16_t uses_tess : 1;
893 uint16_t line_stipple_enabled : 1;
894 uint16_t count_from_stream_output : 1;
895 uint16_t primitive_restart : 1;
896 uint16_t multi_instances_smaller_than_primgroup : 1;
897 uint16_t uses_instancing : 1;
898 uint16_t prim : 4;
899 #endif
900 } u;
901 uint16_t index;
902 };
903
904 struct si_texture_handle {
905 unsigned desc_slot;
906 bool desc_dirty;
907 struct pipe_sampler_view *view;
908 struct si_sampler_state sstate;
909 };
910
911 struct si_image_handle {
912 unsigned desc_slot;
913 bool desc_dirty;
914 struct pipe_image_view view;
915 };
916
917 struct si_saved_cs {
918 struct pipe_reference reference;
919 struct si_context *ctx;
920 struct radeon_saved_cs gfx;
921 struct radeon_saved_cs compute;
922 struct si_resource *trace_buf;
923 unsigned trace_id;
924
925 unsigned gfx_last_dw;
926 bool flushed;
927 int64_t time_flush;
928 };
929
930 struct si_sqtt_fake_pipeline {
931 struct si_pm4_state pm4; /* base class */
932 uint64_t code_hash;
933 struct si_resource *bo;
934 uint32_t offset[SI_NUM_GRAPHICS_SHADERS];
935 };
936
937 struct si_small_prim_cull_info {
938 float scale[2], translate[2];
939 float scale_no_aa[2], translate_no_aa[2];
940 float clip_half_line_width[2]; /* line_width * 0.5 in clip space in X and Y directions */
941 };
942
943 struct si_vertex_state {
944 struct pipe_vertex_state b;
945 struct si_vertex_elements velems;
946 uint32_t descriptors[4 * SI_MAX_ATTRIBS];
947 };
948
949 /* The structure layout is identical to a pair of registers in SET_*_REG_PAIRS_PACKED. */
950 struct gfx11_reg_pair {
951 union {
952 /* A pair of register offsets. */
953 struct {
954 uint16_t reg_offset[2];
955 };
956 /* The same pair of register offsets as a dword. */
957 uint32_t reg_offsets;
958 };
959 /* A pair of register values for the register offsets above. */
960 uint32_t reg_value[2];
961 };
962
963 typedef void (*pipe_draw_vertex_state_func)(struct pipe_context *ctx,
964 struct pipe_vertex_state *vstate,
965 uint32_t partial_velem_mask,
966 struct pipe_draw_vertex_state_info info,
967 const struct pipe_draw_start_count_bias *draws,
968 unsigned num_draws);
969
970 struct si_context {
971 struct pipe_context b; /* base class */
972
973 enum radeon_family family;
974 enum amd_gfx_level gfx_level;
975
976 struct radeon_winsys *ws;
977 struct radeon_winsys_ctx *ctx;
978 struct radeon_cmdbuf gfx_cs; /* compute IB if graphics is disabled */
979 struct radeon_cmdbuf *sdma_cs;
980 struct pipe_fence_handle *last_gfx_fence;
981 struct si_resource *eop_bug_scratch;
982 struct si_resource *eop_bug_scratch_tmz;
983 struct u_upload_mgr *cached_gtt_allocator;
984 struct threaded_context *tc;
985 struct u_suballocator allocator_zeroed_memory;
986 struct slab_child_pool pool_transfers;
987 struct slab_child_pool pool_transfers_unsync; /* for threaded_context */
988 struct pipe_device_reset_callback device_reset_callback;
989 struct u_log_context *log;
990 void *query_result_shader;
991 void *sh_query_result_shader;
992 struct {
993 /* Memory where the shadowed registers will be saved and loaded from. */
994 struct si_resource *registers;
995 /* Context Save Area: scratch area to save other required data. Only
996 * used if info->has_fw_based_mcbp is true.
997 */
998 struct si_resource *csa;
999 } shadowing;
1000
1001 void (*emit_cache_flush)(struct si_context *ctx, struct radeon_cmdbuf *cs);
1002
1003 struct blitter_context *blitter;
1004 void *noop_blend;
1005 void *noop_dsa;
1006 void *no_velems_state;
1007 void *discard_rasterizer_state;
1008 void *custom_dsa_flush;
1009 void *custom_blend_resolve;
1010 void *custom_blend_fmask_decompress;
1011 void *custom_blend_eliminate_fastclear;
1012 void *custom_blend_dcc_decompress;
1013 void *vs_blit_pos;
1014 void *vs_blit_pos_layered;
1015 void *vs_blit_color;
1016 void *vs_blit_color_layered;
1017 void *vs_blit_texcoord;
1018 void *cs_clear_buffer;
1019 void *cs_clear_buffer_rmw;
1020 void *cs_copy_buffer;
1021 void *cs_ubyte_to_ushort;
1022 void *cs_copy_image[3][2][2]; /* [wg_dim-1][src_is_1d][dst_is_1d] */
1023 void *cs_clear_render_target;
1024 void *cs_clear_render_target_1d_array;
1025 void *cs_clear_12bytes_buffer;
1026 void *cs_dcc_retile[32];
1027 void *cs_fmask_expand[3][2]; /* [log2(samples)-1][is_array] */
1028 struct hash_table *cs_blit_shaders;
1029 struct si_screen *screen;
1030 struct util_debug_callback debug;
1031 struct ac_llvm_compiler *compiler; /* only non-threaded compilation */
1032 struct hash_table *fixed_func_tcs_shader_cache;
1033 struct si_resource *wait_mem_scratch;
1034 struct si_resource *wait_mem_scratch_tmz;
1035 unsigned wait_mem_number;
1036 uint16_t prefetch_L2_mask;
1037
1038 bool blitter_running:1;
1039 bool suppress_update_ps_colorbuf0_slot:1;
1040 bool is_noop:1;
1041 bool has_graphics:1;
1042 bool gfx_flush_in_progress : 1;
1043 bool gfx_last_ib_is_busy : 1;
1044 bool compute_is_busy : 1;
1045 bool gfx11_force_msaa_num_samples_zero:1;
1046 int8_t pipeline_stats_enabled; /* -1 = unknown, 0 = disabled, 1 = enabled */
1047
1048 unsigned num_gfx_cs_flushes;
1049 unsigned initial_gfx_cs_size;
1050 unsigned last_dirty_tex_counter;
1051 unsigned last_dirty_buf_counter;
1052 unsigned last_compressed_colortex_counter;
1053 unsigned last_num_draw_calls;
1054 unsigned flags; /* flush flags */
1055
1056 /* Atoms (state emit functions). */
1057 union si_state_atoms atoms;
1058 uint64_t dirty_atoms; /* mask */
1059 union si_state queued;
1060 union si_state emitted;
1061
1062 /* Gfx11+: Buffered SH registers for SET_SH_REG_PAIRS_*. */
1063 unsigned num_buffered_gfx_sh_regs;
1064 unsigned num_buffered_compute_sh_regs;
1065 struct {
1066 struct gfx11_reg_pair buffered_gfx_sh_regs[32];
1067 struct gfx11_reg_pair buffered_compute_sh_regs[32];
1068 } gfx11;
1069
1070 /* Atom declarations. */
1071 struct si_framebuffer framebuffer;
1072 unsigned sample_locs_num_samples;
1073 uint16_t sample_mask;
1074 unsigned last_cb_target_mask;
1075 struct pipe_blend_color blend_color;
1076 struct pipe_clip_state clip_state;
1077 struct si_shader_data shader_pointers;
1078 struct si_stencil_ref stencil_ref;
1079 bool blend_color_any_nonzeros:1;
1080 bool clip_state_any_nonzeros:1;
1081 bool viewport0_y_inverted;
1082 struct pipe_scissor_state scissors[SI_MAX_VIEWPORTS];
1083 struct si_streamout streamout;
1084 struct si_viewports viewports;
1085 unsigned num_window_rectangles;
1086 bool window_rectangles_include;
1087 struct pipe_scissor_state window_rectangles[4];
1088
1089 /* Precomputed states. */
1090 struct si_pm4_state *cs_preamble_state;
1091 struct si_pm4_state *cs_preamble_state_tmz;
1092 uint16_t gs_ring_state_dw_offset;
1093 uint16_t gs_ring_state_dw_offset_tmz;
1094 bool cs_preamble_has_vgt_flush;
1095 bool cs_preamble_has_vgt_flush_tmz;
1096 uint32_t vgt_shader_stages_en;
1097 uint32_t ge_cntl;
1098
1099 /* shaders */
1100 union {
1101 struct {
1102 struct si_shader_ctx_state vs;
1103 struct si_shader_ctx_state tcs;
1104 struct si_shader_ctx_state tes;
1105 struct si_shader_ctx_state gs;
1106 struct si_shader_ctx_state ps;
1107 } shader;
1108 /* indexed access using pipe_shader_type (not by MESA_SHADER_*) */
1109 struct si_shader_ctx_state shaders[SI_NUM_GRAPHICS_SHADERS];
1110 };
1111 struct si_cs_shader_state cs_shader_state;
1112 /* if current tcs set by user */
1113 bool is_user_tcs;
1114
1115 /* video context */
1116 bool vcn_has_ctx;
1117 enum vcn_version vcn_ip_ver;
1118
1119 /* shader information */
1120 uint64_t ps_inputs_read_or_disabled;
1121 struct si_vertex_elements *vertex_elements;
1122 unsigned num_vertex_elements;
1123 unsigned cs_max_waves_per_sh;
1124 bool uses_nontrivial_vs_inputs;
1125 bool force_trivial_vs_inputs;
1126 bool do_update_shaders;
1127 bool compute_shaderbuf_sgprs_dirty;
1128 bool compute_image_sgprs_dirty;
1129 bool vs_uses_base_instance;
1130 bool vs_uses_draw_id;
1131 uint8_t patch_vertices;
1132
1133 /* shader descriptors */
1134 struct si_descriptors descriptors[SI_NUM_DESCS];
1135 unsigned descriptors_dirty;
1136 unsigned shader_pointers_dirty;
1137 unsigned shader_needs_decompress_mask;
1138 unsigned shader_has_depth_tex;
1139 struct si_buffer_resources internal_bindings;
1140 struct si_buffer_resources const_and_shader_buffers[SI_NUM_SHADERS];
1141 struct si_samplers samplers[SI_NUM_SHADERS];
1142 struct si_images images[SI_NUM_SHADERS];
1143 bool bo_list_add_all_resident_resources;
1144 bool bo_list_add_all_compute_resources;
1145
1146 /* other shader resources */
1147 struct pipe_constant_buffer null_const_buf; /* used for set_constant_buffer(NULL) on GFX7 */
1148 struct pipe_resource *esgs_ring;
1149 struct pipe_resource *gsvs_ring;
1150 struct pipe_resource *tess_rings;
1151 struct pipe_resource *tess_rings_tmz;
1152 union pipe_color_union *border_color_table; /* in CPU memory, any endian */
1153 struct si_resource *border_color_buffer;
1154 union pipe_color_union *border_color_map; /* in VRAM (slow access), little endian */
1155 unsigned border_color_count;
1156 unsigned num_vs_blit_sgprs;
1157 uint32_t vs_blit_sh_data[MAX_SI_VS_BLIT_SGPRS];
1158 uint32_t cs_user_data[4];
1159
1160 /* Vertex buffers. */
1161 bool vertex_buffers_dirty;
1162 uint8_t num_vertex_buffers;
1163 uint16_t vertex_buffer_unaligned; /* bitmask of not dword-aligned buffers */
1164 struct pipe_vertex_buffer vertex_buffer[SI_NUM_VERTEX_BUFFERS];
1165
1166 /* Even though we don't need this variable, u_upload_alloc has an optimization that skips
1167 * reference counting when the new upload buffer is the same as the last one. So keep
1168 * the last upload buffer here and always pass &last_const_upload_buffer to u_upload_alloc.
1169 */
1170 struct si_resource *last_const_upload_buffer;
1171
1172 /* MSAA config state. */
1173 int ps_iter_samples;
1174 bool ps_uses_fbfetch;
1175 bool smoothing_enabled;
1176
1177 /* point smoothing state.*/
1178 bool point_smoothing_enabled;
1179
1180 /* DB render state. */
1181 unsigned ps_db_shader_control;
1182 unsigned dbcb_copy_sample;
1183 bool dbcb_depth_copy_enabled : 1;
1184 bool dbcb_stencil_copy_enabled : 1;
1185 bool db_flush_depth_inplace : 1;
1186 bool db_flush_stencil_inplace : 1;
1187 bool db_depth_clear : 1;
1188 bool db_depth_disable_expclear : 1;
1189 bool db_stencil_clear : 1;
1190 bool db_stencil_disable_expclear : 1;
1191 bool occlusion_queries_disabled : 1;
1192 bool generate_mipmap_for_depth : 1;
1193 bool allow_flat_shading : 1;
1194
1195 /* Emitted draw state. */
1196 bool ngg : 1;
1197 bool disable_instance_packing : 1;
1198 uint16_t ngg_culling;
1199 unsigned last_index_size;
1200 unsigned last_instance_count;
1201 int last_primitive_restart_en;
1202 unsigned last_restart_index;
1203 unsigned last_prim;
1204 unsigned current_vs_state; /* all VS bits including LS bits */
1205 unsigned current_gs_state; /* only GS and NGG bits */
1206 unsigned last_vs_state;
1207 unsigned last_gs_state;
1208 enum mesa_prim current_rast_prim; /* primitive type after TES, GS */
1209 unsigned gs_out_prim;
1210
1211 struct si_small_prim_cull_info last_small_prim_cull_info;
1212 struct si_resource *small_prim_cull_info_buf;
1213 uint64_t small_prim_cull_info_address;
1214
1215 /* Scratch buffer */
1216 struct si_resource *scratch_buffer;
1217 unsigned spi_tmpring_size;
1218 unsigned max_seen_scratch_bytes_per_wave;
1219 unsigned max_seen_compute_scratch_bytes_per_wave;
1220
1221 struct si_resource *compute_scratch_buffer;
1222
1223 /* Emitted derived tessellation state. */
1224 /* Local shader (VS), or HS if LS-HS are merged. */
1225 struct si_shader *last_ls;
1226 struct si_shader_selector *last_tcs;
1227 unsigned last_num_tcs_input_cp;
1228 unsigned last_tes_sh_base;
1229 bool last_tess_uses_primid;
1230 unsigned num_patches_per_workgroup;
1231 unsigned tcs_offchip_layout;
1232 unsigned tes_offchip_ring_va_sgpr;
1233 unsigned ls_hs_rsrc2;
1234 unsigned ls_hs_config;
1235
1236 /* Debug state. */
1237 bool is_debug;
1238 struct si_saved_cs *current_saved_cs;
1239 uint64_t dmesg_timestamp;
1240 unsigned apitrace_call_number;
1241
1242 /* Other state */
1243 bool need_check_render_feedback;
1244 bool decompression_enabled;
1245 bool dpbb_force_off;
1246 bool dpbb_force_off_profile_vs;
1247 bool dpbb_force_off_profile_ps;
1248 bool vs_writes_viewport_index;
1249 bool vs_disables_clipping_viewport;
1250 bool has_reset_been_notified;
1251
1252 /* The number of pixels outside the viewport that are not culled by the clipper.
1253 * Normally, the clipper clips everything outside the viewport, however, points and lines
1254 * can have vertices outside the viewport, but their edges can be inside the viewport. Those
1255 * shouldn't be culled. The problem is that the register setting (PA_CL_GB_*_DISC_ADJ) that
1256 * controls the discard distance, which depends on the point size and line width, applies to
1257 * all primitive types, and we would have to set 0 distance for triangles and non-zero for
1258 * points and lines whenever the primitive type changes, which would add overhead and cause
1259 * context rolls.
1260 *
1261 * To reduce that, whenever the discard distance changes for points and lines, we keep it
1262 * at that higher value up to a certain small number for all primitive types including all
1263 * points and lines within a specific size. This is slightly inefficient, but it eliminates
1264 * a lot of guardband state updates and context register changes.
1265 */
1266 float min_clip_discard_distance_watermark;
1267 float current_clip_discard_distance;
1268
1269 /* Precomputed IA_MULTI_VGT_PARAM */
1270 union si_vgt_param_key ia_multi_vgt_param_key;
1271 unsigned ia_multi_vgt_param[SI_NUM_VGT_PARAM_STATES];
1272
1273 /* Bindless descriptors. */
1274 struct si_descriptors bindless_descriptors;
1275 struct util_idalloc bindless_used_slots;
1276 unsigned num_bindless_descriptors;
1277 bool bindless_descriptors_dirty;
1278 bool graphics_bindless_pointer_dirty;
1279 bool compute_bindless_pointer_dirty;
1280 bool gs_attribute_ring_pointer_dirty;
1281
1282 /* Allocated bindless handles */
1283 struct hash_table *tex_handles;
1284 struct hash_table *img_handles;
1285
1286 /* Resident bindless handles */
1287 struct util_dynarray resident_tex_handles;
1288 struct util_dynarray resident_img_handles;
1289
1290 /* Resident bindless handles which need decompression */
1291 struct util_dynarray resident_tex_needs_color_decompress;
1292 struct util_dynarray resident_img_needs_color_decompress;
1293 struct util_dynarray resident_tex_needs_depth_decompress;
1294
1295 /* Bindless state */
1296 bool uses_bindless_samplers;
1297 bool uses_bindless_images;
1298
1299 /* MSAA sample locations.
1300 * The first index is the sample index.
1301 * The second index is the coordinate: X, Y. */
1302 struct {
1303 float x1[1][2];
1304 float x2[2][2];
1305 float x4[4][2];
1306 float x8[8][2];
1307 float x16[16][2];
1308 } sample_positions;
1309 struct pipe_resource *sample_pos_buffer;
1310
1311 /* Misc stats. */
1312 unsigned num_draw_calls;
1313 unsigned num_decompress_calls;
1314 unsigned num_compute_calls;
1315 unsigned num_cp_dma_calls;
1316 unsigned num_vs_flushes;
1317 unsigned num_ps_flushes;
1318 unsigned num_cs_flushes;
1319 unsigned num_cb_cache_flushes;
1320 unsigned num_db_cache_flushes;
1321 unsigned num_L2_invalidates;
1322 unsigned num_L2_writebacks;
1323 unsigned num_resident_handles;
1324 uint64_t num_alloc_tex_transfer_bytes;
1325 unsigned last_tex_ps_draw_ratio; /* for query */
1326 unsigned context_roll;
1327
1328 /* Queries. */
1329 /* Maintain the list of active queries for pausing between IBs. */
1330 enum si_occlusion_query_mode occlusion_query_mode;
1331 int num_integer_occlusion_queries;
1332 int num_boolean_occlusion_queries;
1333 int num_conservative_occlusion_queries;
1334 int num_pipeline_stat_queries;
1335 int num_pipeline_stat_emulated_queries;
1336 int num_hw_pipestat_streamout_queries;
1337 struct list_head active_queries;
1338 unsigned num_cs_dw_queries_suspend;
1339 /* Shared buffer for pipeline stats queries implemented with an atomic op */
1340 struct si_resource *pipeline_stats_query_buf;
1341
1342 /* Render condition. */
1343 struct pipe_query *render_cond;
1344 unsigned render_cond_mode;
1345 bool render_cond_invert;
1346 bool render_cond_enabled; /* for u_blitter */
1347
1348 /* Shader-based queries. */
1349 struct list_head shader_query_buffers;
1350 unsigned num_active_shader_queries;
1351
1352 bool force_cb_shader_coherent;
1353
1354 struct si_tracked_regs tracked_regs;
1355
1356 /* Resources that need to be flushed, but will not get an explicit
1357 * flush_resource from the frontend and that will need to get flushed during
1358 * a context flush.
1359 */
1360 struct hash_table *dirty_implicit_resources;
1361
1362 pipe_draw_func draw_vbo[2][2][2];
1363 pipe_draw_vertex_state_func draw_vertex_state[2][2][2];
1364 /* When b.draw_vbo is a wrapper, real_draw_vbo is the real draw_vbo function */
1365 pipe_draw_func real_draw_vbo;
1366 pipe_draw_vertex_state_func real_draw_vertex_state;
1367 void (*emit_spi_map[33])(struct si_context *sctx, unsigned index);
1368
1369 /* SQTT */
1370 struct ac_sqtt *sqtt;
1371 struct ac_spm spm;
1372 struct pipe_fence_handle *last_sqtt_fence;
1373 enum rgp_sqtt_marker_event_type sqtt_next_event;
1374 bool sqtt_enabled;
1375
1376 unsigned context_flags;
1377
1378 /* Shaders. */
1379 /* TODO: move other shaders here too */
1380 /* Only used for DCC MSAA clears with 4-8 fragments and 4-16 samples. */
1381 void *cs_clear_dcc_msaa[32][5][2][3][2]; /* [swizzle_mode][log2(bpe)][fragments == 8][log2(samples)-2][is_array] */
1382
1383 /* u_trace logging*/
1384 struct si_ds_device ds;
1385 /** Where tracepoints are recorded */
1386 struct u_trace trace;
1387 struct si_ds_queue ds_queue;
1388 uint32_t *last_timestamp_cmd;
1389 unsigned int last_timestamp_cmd_cdw;
1390 };
1391
1392 /* si_blit.c */
1393 enum si_blitter_op /* bitmask */
1394 {
1395 SI_SAVE_TEXTURES = 1,
1396 SI_SAVE_FRAMEBUFFER = 2,
1397 SI_SAVE_FRAGMENT_STATE = 4,
1398 SI_SAVE_FRAGMENT_CONSTANT = 8,
1399 SI_DISABLE_RENDER_COND = 16,
1400 };
1401
1402 void si_blitter_begin(struct si_context *sctx, enum si_blitter_op op);
1403 void si_blitter_end(struct si_context *sctx);
1404 void si_init_blit_functions(struct si_context *sctx);
1405 void gfx6_decompress_textures(struct si_context *sctx, unsigned shader_mask);
1406 void gfx11_decompress_textures(struct si_context *sctx, unsigned shader_mask);
1407 void si_decompress_subresource(struct pipe_context *ctx, struct pipe_resource *tex, unsigned planes,
1408 unsigned level, unsigned first_layer, unsigned last_layer,
1409 bool need_fmask_expand);
1410 void si_resource_copy_region(struct pipe_context *ctx, struct pipe_resource *dst,
1411 unsigned dst_level, unsigned dstx, unsigned dsty, unsigned dstz,
1412 struct pipe_resource *src, unsigned src_level,
1413 const struct pipe_box *src_box);
1414 void si_decompress_dcc(struct si_context *sctx, struct si_texture *tex);
1415 void si_flush_implicit_resources(struct si_context *sctx);
1416 bool si_msaa_resolve_blit_via_CB(struct pipe_context *ctx, const struct pipe_blit_info *info);
1417 void si_gfx_blit(struct pipe_context *ctx, const struct pipe_blit_info *info);
1418
1419 /* si_nir_optim.c */
1420 bool si_nir_is_output_const_if_tex_is_const(struct nir_shader *shader, float *in, float *out, int *texunit);
1421
1422 /* si_buffer.c */
1423 bool si_cs_is_buffer_referenced(struct si_context *sctx, struct pb_buffer_lean *buf,
1424 unsigned usage);
1425 void *si_buffer_map(struct si_context *sctx, struct si_resource *resource,
1426 unsigned usage);
1427 void si_init_resource_fields(struct si_screen *sscreen, struct si_resource *res, uint64_t size,
1428 unsigned alignment);
1429 bool si_alloc_resource(struct si_screen *sscreen, struct si_resource *res);
1430 struct pipe_resource *pipe_aligned_buffer_create(struct pipe_screen *screen, unsigned flags,
1431 unsigned usage, unsigned size, unsigned alignment);
1432 struct si_resource *si_aligned_buffer_create(struct pipe_screen *screen, unsigned flags,
1433 unsigned usage, unsigned size, unsigned alignment);
1434 struct pipe_resource *si_buffer_from_winsys_buffer(struct pipe_screen *screen,
1435 const struct pipe_resource *templ,
1436 struct pb_buffer_lean *imported_buf,
1437 uint64_t offset);
1438 void si_replace_buffer_storage(struct pipe_context *ctx, struct pipe_resource *dst,
1439 struct pipe_resource *src, unsigned num_rebinds,
1440 uint32_t rebind_mask, uint32_t delete_buffer_id);
1441 void si_init_screen_buffer_functions(struct si_screen *sscreen);
1442 void si_init_buffer_functions(struct si_context *sctx);
1443
1444 /* si_clear.c */
1445 #define SI_CLEAR_TYPE_CMASK (1 << 0)
1446 #define SI_CLEAR_TYPE_DCC (1 << 1)
1447 #define SI_CLEAR_TYPE_HTILE (1 << 2)
1448
1449 struct si_clear_info {
1450 struct pipe_resource *resource;
1451 uint64_t offset;
1452 uint32_t size;
1453 uint32_t clear_value;
1454 uint32_t writemask;
1455 bool is_dcc_msaa; /* Clear it as a DCC MSAA image. */
1456 };
1457
1458 enum pipe_format si_simplify_cb_format(enum pipe_format format);
1459 bool vi_alpha_is_on_msb(struct si_screen *sscreen, enum pipe_format format);
1460 bool vi_dcc_get_clear_info(struct si_context *sctx, struct si_texture *tex, unsigned level,
1461 unsigned clear_value, struct si_clear_info *out);
1462 void si_init_buffer_clear(struct si_clear_info *info,
1463 struct pipe_resource *resource, uint64_t offset,
1464 uint32_t size, uint32_t clear_value);
1465 void si_execute_clears(struct si_context *sctx, struct si_clear_info *info,
1466 unsigned num_clears, unsigned types);
1467 void si_init_clear_functions(struct si_context *sctx);
1468
1469 /* si_compute.c */
1470 void si_destroy_compute(struct si_compute *program);
1471
1472 /* si_compute_blit.c */
1473 #define SI_OP_SYNC_CS_BEFORE (1 << 0)
1474 #define SI_OP_SYNC_PS_BEFORE (1 << 1)
1475 #define SI_OP_SYNC_CPDMA_BEFORE (1 << 2) /* only affects CP DMA calls */
1476 #define SI_OP_SYNC_BEFORE (SI_OP_SYNC_CS_BEFORE | SI_OP_SYNC_PS_BEFORE | SI_OP_SYNC_CPDMA_BEFORE)
1477 #define SI_OP_SYNC_AFTER (1 << 3)
1478 #define SI_OP_SYNC_BEFORE_AFTER (SI_OP_SYNC_BEFORE | SI_OP_SYNC_AFTER)
1479 #define SI_OP_SKIP_CACHE_INV_BEFORE (1 << 4) /* don't invalidate caches */
1480 #define SI_OP_CS_IMAGE (1 << 5)
1481 #define SI_OP_CS_RENDER_COND_ENABLE (1 << 6)
1482 #define SI_OP_CPDMA_SKIP_CHECK_CS_SPACE (1 << 7) /* don't call need_cs_space */
1483 #define SI_OP_SYNC_GE_BEFORE (1 << 8) /* only sync VS, TCS, TES, GS */
1484
1485 unsigned si_get_flush_flags(struct si_context *sctx, enum si_coherency coher,
1486 enum si_cache_policy cache_policy);
1487 void si_launch_grid_internal_ssbos(struct si_context *sctx, struct pipe_grid_info *info,
1488 void *shader, unsigned flags, enum si_coherency coher,
1489 unsigned num_buffers, const struct pipe_shader_buffer *buffers,
1490 unsigned writeable_bitmask);
1491 enum si_clear_method {
1492 SI_CP_DMA_CLEAR_METHOD,
1493 SI_COMPUTE_CLEAR_METHOD,
1494 SI_AUTO_SELECT_CLEAR_METHOD
1495 };
1496 void si_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
1497 uint64_t offset, uint64_t size, uint32_t *clear_value,
1498 uint32_t clear_value_size, unsigned flags,
1499 enum si_coherency coher, enum si_clear_method method);
1500 void si_compute_clear_buffer_rmw(struct si_context *sctx, struct pipe_resource *dst,
1501 unsigned dst_offset, unsigned size,
1502 uint32_t clear_value, uint32_t writebitmask,
1503 unsigned flags, enum si_coherency coher);
1504 void si_copy_buffer(struct si_context *sctx, struct pipe_resource *dst, struct pipe_resource *src,
1505 uint64_t dst_offset, uint64_t src_offset, unsigned size, unsigned flags);
1506 void si_compute_shorten_ubyte_buffer(struct si_context *sctx, struct pipe_resource *dst, struct pipe_resource *src,
1507 uint64_t dst_offset, uint64_t src_offset, unsigned size, unsigned flags);
1508 bool si_compute_copy_image(struct si_context *sctx, struct pipe_resource *dst, unsigned dst_level,
1509 struct pipe_resource *src, unsigned src_level, unsigned dstx,
1510 unsigned dsty, unsigned dstz, const struct pipe_box *src_box,
1511 unsigned flags);
1512 void si_compute_clear_render_target(struct pipe_context *ctx, struct pipe_surface *dstsurf,
1513 const union pipe_color_union *color, unsigned dstx,
1514 unsigned dsty, unsigned width, unsigned height,
1515 bool render_condition_enabled);
1516 void si_retile_dcc(struct si_context *sctx, struct si_texture *tex);
1517 void gfx9_clear_dcc_msaa(struct si_context *sctx, struct pipe_resource *res, uint32_t clear_value,
1518 unsigned flags, enum si_coherency coher);
1519 void si_compute_expand_fmask(struct pipe_context *ctx, struct pipe_resource *tex);
1520 bool si_compute_blit(struct si_context *sctx, const struct pipe_blit_info *info, bool testing);
1521 void si_init_compute_blit_functions(struct si_context *sctx);
1522
1523 /* si_cp_dma.c */
1524 void si_cp_dma_wait_for_idle(struct si_context *sctx, struct radeon_cmdbuf *cs);
1525 void si_cp_dma_clear_buffer(struct si_context *sctx, struct radeon_cmdbuf *cs,
1526 struct pipe_resource *dst, uint64_t offset, uint64_t size,
1527 unsigned value, unsigned user_flags, enum si_coherency coher,
1528 enum si_cache_policy cache_policy);
1529 void si_cp_dma_copy_buffer(struct si_context *sctx, struct pipe_resource *dst,
1530 struct pipe_resource *src, uint64_t dst_offset, uint64_t src_offset,
1531 unsigned size, unsigned user_flags, enum si_coherency coher,
1532 enum si_cache_policy cache_policy);
1533 void si_test_gds(struct si_context *sctx);
1534 void si_cp_write_data(struct si_context *sctx, struct si_resource *buf, unsigned offset,
1535 unsigned size, unsigned dst_sel, unsigned engine, const void *data);
1536 void si_cp_copy_data(struct si_context *sctx, struct radeon_cmdbuf *cs, unsigned dst_sel,
1537 struct si_resource *dst, unsigned dst_offset, unsigned src_sel,
1538 struct si_resource *src, unsigned src_offset);
1539
1540 /* si_cp_reg_shadowing.c */
1541 void si_init_cp_reg_shadowing(struct si_context *sctx);
1542
1543 /* si_debug.c */
1544 void si_gather_context_rolls(struct si_context *sctx);
1545 void si_save_cs(struct radeon_winsys *ws, struct radeon_cmdbuf *cs, struct radeon_saved_cs *saved,
1546 bool get_buffer_list);
1547 void si_clear_saved_cs(struct radeon_saved_cs *saved);
1548 void si_destroy_saved_cs(struct si_saved_cs *scs);
1549 void si_auto_log_cs(void *data, struct u_log_context *log);
1550 void si_log_hw_flush(struct si_context *sctx);
1551 void si_log_draw_state(struct si_context *sctx, struct u_log_context *log);
1552 void si_log_compute_state(struct si_context *sctx, struct u_log_context *log);
1553 void si_init_debug_functions(struct si_context *sctx);
1554 void si_check_vm_faults(struct si_context *sctx, struct radeon_saved_cs *saved,
1555 enum amd_ip_type ring);
1556 bool si_replace_shader(unsigned num, struct si_shader_binary *binary);
1557 void si_print_current_ib(struct si_context *sctx, FILE *f);
1558
1559 /* si_fence.c */
1560 void si_cp_release_mem(struct si_context *ctx, struct radeon_cmdbuf *cs, unsigned event,
1561 unsigned event_flags, unsigned dst_sel, unsigned int_sel, unsigned data_sel,
1562 struct si_resource *buf, uint64_t va, uint32_t new_fence,
1563 unsigned query_type);
1564 unsigned si_cp_write_fence_dwords(struct si_screen *screen);
1565 void si_cp_wait_mem(struct si_context *ctx, struct radeon_cmdbuf *cs, uint64_t va, uint32_t ref,
1566 uint32_t mask, unsigned flags);
1567 void si_init_fence_functions(struct si_context *ctx);
1568 void si_init_screen_fence_functions(struct si_screen *screen);
1569 struct pipe_fence_handle *si_create_fence(struct pipe_context *ctx,
1570 struct tc_unflushed_batch_token *tc_token);
1571
1572 /* si_get.c */
1573 void si_init_screen_get_functions(struct si_screen *sscreen);
1574
1575 bool si_sdma_copy_image(struct si_context *ctx, struct si_texture *dst, struct si_texture *src);
1576
1577 /* si_gfx_cs.c */
1578 void si_flush_gfx_cs(struct si_context *ctx, unsigned flags, struct pipe_fence_handle **fence);
1579 void si_allocate_gds(struct si_context *ctx);
1580 void si_set_tracked_regs_to_clear_state(struct si_context *ctx);
1581 void si_begin_new_gfx_cs(struct si_context *ctx, bool first_cs);
1582 void si_trace_emit(struct si_context *sctx);
1583 void si_emit_ts(struct si_context *sctx, struct si_resource* buffer, unsigned int offset);
1584 void si_emit_surface_sync(struct si_context *sctx, struct radeon_cmdbuf *cs,
1585 unsigned cp_coher_cntl);
1586 void gfx10_emit_cache_flush(struct si_context *sctx, struct radeon_cmdbuf *cs);
1587 void gfx6_emit_cache_flush(struct si_context *sctx, struct radeon_cmdbuf *cs);
1588 /* Replace the sctx->b.draw_vbo function with a wrapper. This can be use to implement
1589 * optimizations without affecting the normal draw_vbo functions perf.
1590 */
1591 void si_install_draw_wrapper(struct si_context *sctx, pipe_draw_func wrapper,
1592 pipe_draw_vertex_state_func vstate_wrapper);
1593
1594 /* si_gpu_load.c */
1595 void si_gpu_load_kill_thread(struct si_screen *sscreen);
1596 uint64_t si_begin_counter(struct si_screen *sscreen, unsigned type);
1597 unsigned si_end_counter(struct si_screen *sscreen, unsigned type, uint64_t begin);
1598
1599 /* si_compute.c */
1600 void si_emit_initial_compute_regs(struct si_context *sctx, struct radeon_cmdbuf *cs);
1601 void si_init_compute_functions(struct si_context *sctx);
1602
1603 /* si_pipe.c */
1604 struct ac_llvm_compiler *si_create_llvm_compiler(struct si_screen *sscreen);
1605 void si_init_aux_async_compute_ctx(struct si_screen *sscreen);
1606 struct si_context *si_get_aux_context(struct si_aux_context *ctx);
1607 void si_put_aux_context_flush(struct si_aux_context *ctx);
1608 void si_put_aux_shader_upload_context_flush(struct si_screen *sscreen);
1609
1610 /* si_perfcounters.c */
1611 void si_init_perfcounters(struct si_screen *screen);
1612 void si_destroy_perfcounters(struct si_screen *screen);
1613 void si_inhibit_clockgating(struct si_context *sctx, struct radeon_cmdbuf *cs, bool inhibit);
1614 void si_pc_emit_shaders(struct radeon_cmdbuf *cs, unsigned shaders);
1615 void si_pc_emit_spm_start(struct radeon_cmdbuf *cs);
1616 void si_pc_emit_spm_stop(struct radeon_cmdbuf *cs, bool never_stop_sq_perf_counters,
1617 bool never_send_perfcounter_stop);
1618 void si_pc_emit_spm_reset(struct radeon_cmdbuf *cs);
1619 void si_emit_spm_setup(struct si_context *sctx, struct radeon_cmdbuf *cs);
1620 bool si_spm_init(struct si_context *sctx);
1621 void si_spm_finish(struct si_context *sctx);
1622
1623 /* si_query.c */
1624 void si_init_screen_query_functions(struct si_screen *sscreen);
1625 void si_init_query_functions(struct si_context *sctx);
1626 void si_suspend_queries(struct si_context *sctx);
1627 void si_resume_queries(struct si_context *sctx);
1628
1629 /* si_shaderlib_nir.c */
1630 void *si_create_copy_image_cs(struct si_context *sctx, unsigned wg_dim,
1631 bool src_is_1d_array, bool dst_is_1d_array);
1632 void *si_create_dcc_retile_cs(struct si_context *sctx, struct radeon_surf *surf);
1633 void *gfx9_create_clear_dcc_msaa_cs(struct si_context *sctx, struct si_texture *tex);
1634 void *si_create_passthrough_tcs(struct si_context *sctx);
1635
1636 union si_compute_blit_shader_key {
1637 struct {
1638 /* The key saved in _mesa_hash_table_create_u32_keys() can't be 0. */
1639 bool always_true:1;
1640 /* Declaration modifiers. */
1641 uint8_t wg_dim:2; /* 1, 2, or 3 */
1642 bool src_is_1d:1;
1643 bool dst_is_1d:1;
1644 bool src_is_msaa:1;
1645 bool dst_is_msaa:1;
1646 uint8_t log2_samples:4;
1647 bool sample0_only:1; /* src is MSAA, dst is not MSAA, log2_samples is ignored */
1648 /* Source coordinate modifiers. */
1649 bool xy_clamp_to_edge:1;
1650 bool flip_x:1;
1651 bool flip_y:1;
1652 /* Output modifiers. */
1653 bool sint_to_uint:1;
1654 bool uint_to_sint:1;
1655 bool dst_is_srgb:1;
1656 bool use_integer_one:1;
1657 uint8_t last_src_channel:2;
1658 uint8_t last_dst_channel:2;
1659 bool fp16_rtz:1; /* only for equality with pixel shaders, not necessary otherwise */
1660 };
1661 uint32_t key;
1662 };
1663
1664 void *si_create_blit_cs(struct si_context *sctx, const union si_compute_blit_shader_key *options);
1665
1666 /* si_shaderlib_nir.c */
1667 void *si_get_blitter_vs(struct si_context *sctx, enum blitter_attrib_type type,
1668 unsigned num_layers);
1669 void *si_create_dma_compute_shader(struct si_context *sctx, unsigned num_dwords_per_thread,
1670 bool dst_stream_cache_policy, bool is_copy);
1671 void *si_create_ubyte_to_ushort_compute_shader(struct si_context *sctx);
1672 void *si_create_clear_buffer_rmw_cs(struct si_context *sctx);
1673 void *si_clear_render_target_shader(struct si_context *sctx, enum pipe_texture_target type);
1674 void *si_clear_12bytes_buffer_shader(struct si_context *sctx);
1675 void *si_create_fmask_expand_cs(struct si_context *sctx, unsigned num_samples, bool is_array);
1676 void *si_create_query_result_cs(struct si_context *sctx);
1677 void *gfx11_create_sh_query_result_cs(struct si_context *sctx);
1678
1679 /* gfx11_query.c */
1680 void si_gfx11_init_query(struct si_context *sctx);
1681 void si_gfx11_destroy_query(struct si_context *sctx);
1682
1683 /* si_test_image_copy_region.c */
1684 void si_test_image_copy_region(struct si_screen *sscreen);
1685 void si_test_blit(struct si_screen *sscreen, unsigned test_flags);
1686
1687 /* si_test_clearbuffer.c */
1688 void si_test_dma_perf(struct si_screen *sscreen);
1689
1690 /* si_uvd.c */
1691 struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
1692 const struct pipe_video_codec *templ);
1693
1694 struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
1695 const struct pipe_video_buffer *tmpl);
1696 struct pipe_video_buffer *si_video_buffer_create_with_modifiers(struct pipe_context *pipe,
1697 const struct pipe_video_buffer *tmpl,
1698 const uint64_t *modifiers,
1699 unsigned int modifiers_count);
1700
1701 /* si_state_viewport.c */
1702 void si_update_vs_viewport_state(struct si_context *ctx);
1703 void si_init_viewport_functions(struct si_context *ctx);
1704
1705 /* si_texture.c */
1706 void si_eliminate_fast_color_clear(struct si_context *sctx, struct si_texture *tex,
1707 bool *ctx_flushed);
1708 void si_texture_discard_cmask(struct si_screen *sscreen, struct si_texture *tex);
1709 bool si_init_flushed_depth_texture(struct pipe_context *ctx, struct pipe_resource *texture);
1710 void si_print_texture_info(struct si_screen *sscreen, struct si_texture *tex,
1711 struct u_log_context *log);
1712 struct pipe_resource *si_texture_create(struct pipe_screen *screen,
1713 const struct pipe_resource *templ);
1714 bool si_texture_commit(struct si_context *ctx, struct si_resource *res, unsigned level,
1715 struct pipe_box *box, bool commit);
1716 bool vi_dcc_formats_compatible(struct si_screen *sscreen, enum pipe_format format1,
1717 enum pipe_format format2);
1718 bool vi_dcc_formats_are_incompatible(struct pipe_resource *tex, unsigned level,
1719 enum pipe_format view_format);
1720 void vi_disable_dcc_if_incompatible_format(struct si_context *sctx, struct pipe_resource *tex,
1721 unsigned level, enum pipe_format view_format);
1722 unsigned si_translate_colorswap(enum amd_gfx_level gfx_level, enum pipe_format format,
1723 bool do_endian_swap);
1724 bool si_texture_disable_dcc(struct si_context *sctx, struct si_texture *tex);
1725 void si_init_screen_texture_functions(struct si_screen *sscreen);
1726 void si_init_context_texture_functions(struct si_context *sctx);
1727
1728 /* si_sqtt.c */
1729 void si_sqtt_write_event_marker(struct si_context* sctx, struct radeon_cmdbuf *rcs,
1730 enum rgp_sqtt_marker_event_type api_type,
1731 uint32_t vertex_offset_user_data,
1732 uint32_t instance_offset_user_data,
1733 uint32_t draw_index_user_data);
1734 bool si_sqtt_register_pipeline(struct si_context* sctx, struct si_sqtt_fake_pipeline *pipeline, bool is_compute);
1735 bool si_sqtt_pipeline_is_registered(struct ac_sqtt *sqtt,
1736 uint64_t pipeline_hash);
1737 void si_sqtt_describe_pipeline_bind(struct si_context* sctx, uint64_t pipeline_hash, int bind_point);
1738 void
1739 si_write_event_with_dims_marker(struct si_context* sctx, struct radeon_cmdbuf *rcs,
1740 enum rgp_sqtt_marker_event_type api_type,
1741 uint32_t x, uint32_t y, uint32_t z);
1742 void
1743 si_write_user_event(struct si_context* sctx, struct radeon_cmdbuf *rcs,
1744 enum rgp_sqtt_marker_user_event_type type,
1745 const char *str, int len);
1746 void
1747 si_sqtt_describe_barrier_start(struct si_context* sctx, struct radeon_cmdbuf *rcs);
1748 void
1749 si_sqtt_describe_barrier_end(struct si_context* sctx, struct radeon_cmdbuf *rcs, unsigned flags);
1750 bool si_init_sqtt(struct si_context *sctx);
1751 void si_destroy_sqtt(struct si_context *sctx);
1752 void si_handle_sqtt(struct si_context *sctx, struct radeon_cmdbuf *rcs);
1753
1754 /*
1755 * common helpers
1756 */
1757
si_compute_reference(struct si_compute ** dst,struct si_compute * src)1758 static inline void si_compute_reference(struct si_compute **dst, struct si_compute *src)
1759 {
1760 if (pipe_reference(&(*dst)->sel.base.reference, &src->sel.base.reference))
1761 si_destroy_compute(*dst);
1762
1763 *dst = src;
1764 }
1765
si_resource(struct pipe_resource * r)1766 static inline struct si_resource *si_resource(struct pipe_resource *r)
1767 {
1768 return (struct si_resource *)r;
1769 }
1770
si_resource_reference(struct si_resource ** ptr,struct si_resource * res)1771 static inline void si_resource_reference(struct si_resource **ptr, struct si_resource *res)
1772 {
1773 pipe_resource_reference((struct pipe_resource **)ptr, (struct pipe_resource *)res);
1774 }
1775
si_texture_reference(struct si_texture ** ptr,struct si_texture * res)1776 static inline void si_texture_reference(struct si_texture **ptr, struct si_texture *res)
1777 {
1778 pipe_resource_reference((struct pipe_resource **)ptr, &res->buffer.b.b);
1779 }
1780
1781 static inline void
si_shader_selector_reference(struct si_context * sctx,struct si_shader_selector ** dst,struct si_shader_selector * src)1782 si_shader_selector_reference(struct si_context *sctx, /* sctx can optionally be NULL */
1783 struct si_shader_selector **dst, struct si_shader_selector *src)
1784 {
1785 if (*dst == src)
1786 return;
1787
1788 struct si_screen *sscreen = src ? src->screen : (*dst)->screen;
1789 util_shader_reference(&sctx->b, &sscreen->live_shader_cache, (void **)dst, src);
1790 }
1791
vi_dcc_enabled(struct si_texture * tex,unsigned level)1792 static inline bool vi_dcc_enabled(struct si_texture *tex, unsigned level)
1793 {
1794 return !tex->is_depth && tex->surface.meta_offset && level < tex->surface.num_meta_levels;
1795 }
1796
si_tile_mode_index(struct si_texture * tex,unsigned level,bool stencil)1797 static inline unsigned si_tile_mode_index(struct si_texture *tex, unsigned level, bool stencil)
1798 {
1799 if (stencil)
1800 return tex->surface.u.legacy.zs.stencil_tiling_index[level];
1801 else
1802 return tex->surface.u.legacy.tiling_index[level];
1803 }
1804
si_get_minimum_num_gfx_cs_dwords(struct si_context * sctx,unsigned num_draws)1805 static inline unsigned si_get_minimum_num_gfx_cs_dwords(struct si_context *sctx,
1806 unsigned num_draws)
1807 {
1808 /* Don't count the needed CS space exactly and just use an upper bound.
1809 *
1810 * Also reserve space for stopping queries at the end of IB, because
1811 * the number of active queries is unlimited in theory.
1812 */
1813 return 2048 + sctx->num_cs_dw_queries_suspend + num_draws * 10;
1814 }
1815
si_get_atom_bit(struct si_context * sctx,struct si_atom * atom)1816 static inline uint64_t si_get_atom_bit(struct si_context *sctx, struct si_atom *atom)
1817 {
1818 return 1ull << (atom - sctx->atoms.array);
1819 }
1820
si_set_atom_dirty(struct si_context * sctx,struct si_atom * atom,bool dirty)1821 static inline void si_set_atom_dirty(struct si_context *sctx, struct si_atom *atom, bool dirty)
1822 {
1823 uint64_t bit = si_get_atom_bit(sctx, atom);
1824
1825 if (dirty)
1826 sctx->dirty_atoms |= bit;
1827 else
1828 sctx->dirty_atoms &= ~bit;
1829 }
1830
si_is_atom_dirty(struct si_context * sctx,struct si_atom * atom)1831 static inline bool si_is_atom_dirty(struct si_context *sctx, struct si_atom *atom)
1832 {
1833 return (sctx->dirty_atoms & si_get_atom_bit(sctx, atom)) != 0;
1834 }
1835
si_mark_atom_dirty(struct si_context * sctx,struct si_atom * atom)1836 static inline void si_mark_atom_dirty(struct si_context *sctx, struct si_atom *atom)
1837 {
1838 si_set_atom_dirty(sctx, atom, true);
1839 }
1840
1841 /* This should be evaluated at compile time if all parameters except sctx are constants. */
1842 static ALWAYS_INLINE struct si_shader_ctx_state *
si_get_vs_inline(struct si_context * sctx,enum si_has_tess has_tess,enum si_has_gs has_gs)1843 si_get_vs_inline(struct si_context *sctx, enum si_has_tess has_tess, enum si_has_gs has_gs)
1844 {
1845 if (has_gs)
1846 return &sctx->shader.gs;
1847 if (has_tess)
1848 return &sctx->shader.tes;
1849
1850 return &sctx->shader.vs;
1851 }
1852
si_get_vs(struct si_context * sctx)1853 static inline struct si_shader_ctx_state *si_get_vs(struct si_context *sctx)
1854 {
1855 return si_get_vs_inline(sctx, sctx->shader.tes.cso ? TESS_ON : TESS_OFF,
1856 sctx->shader.gs.cso ? GS_ON : GS_OFF);
1857 }
1858
si_get_strmout_en(struct si_context * sctx)1859 static inline bool si_get_strmout_en(struct si_context *sctx)
1860 {
1861 return sctx->streamout.streamout_enabled || sctx->streamout.prims_gen_query_enabled;
1862 }
1863
si_optimal_tcc_alignment(struct si_context * sctx,unsigned upload_size)1864 static inline unsigned si_optimal_tcc_alignment(struct si_context *sctx, unsigned upload_size)
1865 {
1866 unsigned alignment, tcc_cache_line_size;
1867
1868 /* If the upload size is less than the cache line size (e.g. 16, 32),
1869 * the whole thing will fit into a cache line if we align it to its size.
1870 * The idea is that multiple small uploads can share a cache line.
1871 * If the upload size is greater, align it to the cache line size.
1872 */
1873 alignment = util_next_power_of_two(upload_size);
1874 tcc_cache_line_size = sctx->screen->info.tcc_cache_line_size;
1875 return MIN2(alignment, tcc_cache_line_size);
1876 }
1877
si_saved_cs_reference(struct si_saved_cs ** dst,struct si_saved_cs * src)1878 static inline void si_saved_cs_reference(struct si_saved_cs **dst, struct si_saved_cs *src)
1879 {
1880 if (pipe_reference(&(*dst)->reference, &src->reference))
1881 si_destroy_saved_cs(*dst);
1882
1883 *dst = src;
1884 }
1885
si_make_CB_shader_coherent(struct si_context * sctx,unsigned num_samples,bool shaders_read_metadata,bool dcc_pipe_aligned)1886 static inline void si_make_CB_shader_coherent(struct si_context *sctx, unsigned num_samples,
1887 bool shaders_read_metadata, bool dcc_pipe_aligned)
1888 {
1889 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB | SI_CONTEXT_INV_VCACHE;
1890 sctx->force_cb_shader_coherent = false;
1891
1892 if (sctx->gfx_level >= GFX10) {
1893 if (sctx->screen->info.tcc_rb_non_coherent)
1894 sctx->flags |= SI_CONTEXT_INV_L2;
1895 else if (shaders_read_metadata)
1896 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1897 } else if (sctx->gfx_level == GFX9) {
1898 /* Single-sample color is coherent with shaders on GFX9, but
1899 * L2 metadata must be flushed if shaders read metadata.
1900 * (DCC, CMASK).
1901 */
1902 if (num_samples >= 2 || (shaders_read_metadata && !dcc_pipe_aligned))
1903 sctx->flags |= SI_CONTEXT_INV_L2;
1904 else if (shaders_read_metadata)
1905 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1906 } else {
1907 /* GFX6-GFX8 */
1908 sctx->flags |= SI_CONTEXT_INV_L2;
1909 }
1910
1911 si_mark_atom_dirty(sctx, &sctx->atoms.s.cache_flush);
1912 }
1913
si_make_DB_shader_coherent(struct si_context * sctx,unsigned num_samples,bool include_stencil,bool shaders_read_metadata)1914 static inline void si_make_DB_shader_coherent(struct si_context *sctx, unsigned num_samples,
1915 bool include_stencil, bool shaders_read_metadata)
1916 {
1917 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB | SI_CONTEXT_INV_VCACHE;
1918
1919 if (sctx->gfx_level >= GFX10) {
1920 if (sctx->screen->info.tcc_rb_non_coherent)
1921 sctx->flags |= SI_CONTEXT_INV_L2;
1922 else if (shaders_read_metadata)
1923 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1924 } else if (sctx->gfx_level == GFX9) {
1925 /* Single-sample depth (not stencil) is coherent with shaders
1926 * on GFX9, but L2 metadata must be flushed if shaders read
1927 * metadata.
1928 */
1929 if (num_samples >= 2 || include_stencil)
1930 sctx->flags |= SI_CONTEXT_INV_L2;
1931 else if (shaders_read_metadata)
1932 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1933 } else {
1934 /* GFX6-GFX8 */
1935 sctx->flags |= SI_CONTEXT_INV_L2;
1936 }
1937
1938 si_mark_atom_dirty(sctx, &sctx->atoms.s.cache_flush);
1939 }
1940
si_can_sample_zs(struct si_texture * tex,bool stencil_sampler)1941 static inline bool si_can_sample_zs(struct si_texture *tex, bool stencil_sampler)
1942 {
1943 return (stencil_sampler && tex->can_sample_s) || (!stencil_sampler && tex->can_sample_z);
1944 }
1945
si_htile_enabled(struct si_texture * tex,unsigned level,unsigned zs_mask)1946 static inline bool si_htile_enabled(struct si_texture *tex, unsigned level, unsigned zs_mask)
1947 {
1948 if (zs_mask == PIPE_MASK_S && (tex->htile_stencil_disabled || !tex->surface.has_stencil))
1949 return false;
1950
1951 if (!tex->is_depth || !tex->surface.meta_offset)
1952 return false;
1953
1954 struct si_screen *sscreen = (struct si_screen *)tex->buffer.b.b.screen;
1955 if (sscreen->info.gfx_level >= GFX8) {
1956 return level < tex->surface.num_meta_levels;
1957 } else {
1958 /* GFX6-7 don't have TC-compatible HTILE, which means they have to run
1959 * a decompression pass for every mipmap level before texturing, so compress
1960 * only one level to reduce the number of decompression passes to a minimum.
1961 */
1962 return level == 0;
1963 }
1964 }
1965
vi_tc_compat_htile_enabled(struct si_texture * tex,unsigned level,unsigned zs_mask)1966 static inline bool vi_tc_compat_htile_enabled(struct si_texture *tex, unsigned level,
1967 unsigned zs_mask)
1968 {
1969 assert(!tex->tc_compatible_htile || tex->surface.meta_offset);
1970 return tex->tc_compatible_htile && si_htile_enabled(tex, level, zs_mask);
1971 }
1972
si_get_ps_iter_samples(struct si_context * sctx)1973 static inline unsigned si_get_ps_iter_samples(struct si_context *sctx)
1974 {
1975 if (sctx->gfx11_force_msaa_num_samples_zero)
1976 return 1;
1977
1978 if (sctx->ps_uses_fbfetch)
1979 return sctx->framebuffer.nr_color_samples;
1980
1981 return MIN2(sctx->ps_iter_samples, sctx->framebuffer.nr_color_samples);
1982 }
1983
si_any_colorbuffer_written(struct si_context * sctx)1984 static inline bool si_any_colorbuffer_written(struct si_context *sctx)
1985 {
1986 if (sctx->queued.named.rasterizer->rasterizer_discard)
1987 return false;
1988
1989 struct si_shader_selector *ps = sctx->shader.ps.cso;
1990 if (!ps || !ps->info.colors_written_4bit)
1991 return false;
1992
1993 return (sctx->framebuffer.colorbuf_enabled_4bit &
1994 sctx->queued.named.blend->cb_target_enabled_4bit &
1995 (ps->info.color0_writes_all_cbufs ? ~0 : ps->info.colors_written_4bit)) != 0;
1996 }
1997
1998 #define UTIL_ALL_PRIM_LINE_MODES \
1999 ((1 << MESA_PRIM_LINES) | (1 << MESA_PRIM_LINE_LOOP) | (1 << MESA_PRIM_LINE_STRIP) | \
2000 (1 << MESA_PRIM_LINES_ADJACENCY) | (1 << MESA_PRIM_LINE_STRIP_ADJACENCY))
2001
2002 #define UTIL_ALL_PRIM_TRIANGLE_MODES \
2003 ((1 << MESA_PRIM_TRIANGLES) | (1 << MESA_PRIM_TRIANGLE_STRIP) | \
2004 (1 << MESA_PRIM_TRIANGLE_FAN) | (1 << MESA_PRIM_QUADS) | (1 << MESA_PRIM_QUAD_STRIP) | \
2005 (1 << MESA_PRIM_POLYGON) | (1 << MESA_PRIM_TRIANGLES_ADJACENCY) | \
2006 (1 << MESA_PRIM_TRIANGLE_STRIP_ADJACENCY))
2007
util_prim_is_lines(unsigned prim)2008 static inline bool util_prim_is_lines(unsigned prim)
2009 {
2010 return ((1 << prim) & UTIL_ALL_PRIM_LINE_MODES) != 0;
2011 }
2012
util_prim_is_points_or_lines(unsigned prim)2013 static inline bool util_prim_is_points_or_lines(unsigned prim)
2014 {
2015 return ((1 << prim) & (UTIL_ALL_PRIM_LINE_MODES | (1 << MESA_PRIM_POINTS))) != 0;
2016 }
2017
util_rast_prim_is_triangles(unsigned prim)2018 static inline bool util_rast_prim_is_triangles(unsigned prim)
2019 {
2020 return ((1 << prim) & UTIL_ALL_PRIM_TRIANGLE_MODES) != 0;
2021 }
2022
util_rast_prim_is_lines_or_triangles(unsigned prim)2023 static inline bool util_rast_prim_is_lines_or_triangles(unsigned prim)
2024 {
2025 return ((1 << prim) & (UTIL_ALL_PRIM_LINE_MODES | UTIL_ALL_PRIM_TRIANGLE_MODES)) != 0;
2026 }
2027
si_need_gfx_cs_space(struct si_context * ctx,unsigned num_draws)2028 static inline void si_need_gfx_cs_space(struct si_context *ctx, unsigned num_draws)
2029 {
2030 struct radeon_cmdbuf *cs = &ctx->gfx_cs;
2031
2032 if (!ctx->ws->cs_check_space(cs, si_get_minimum_num_gfx_cs_dwords(ctx, num_draws)))
2033 si_flush_gfx_cs(ctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
2034 }
2035
2036 /**
2037 * Add a buffer to the buffer list for the given command stream (CS).
2038 *
2039 * All buffers used by a CS must be added to the list. This tells the kernel
2040 * driver which buffers are used by GPU commands. Other buffers can
2041 * be swapped out (not accessible) during execution.
2042 *
2043 * The buffer list becomes empty after every context flush and must be
2044 * rebuilt.
2045 */
radeon_add_to_buffer_list(struct si_context * sctx,struct radeon_cmdbuf * cs,struct si_resource * bo,unsigned usage)2046 static inline void radeon_add_to_buffer_list(struct si_context *sctx, struct radeon_cmdbuf *cs,
2047 struct si_resource *bo, unsigned usage)
2048 {
2049 assert(usage);
2050 sctx->ws->cs_add_buffer(cs, bo->buf, usage | RADEON_USAGE_SYNCHRONIZED,
2051 bo->domains);
2052 }
2053
si_select_draw_vbo(struct si_context * sctx)2054 static inline void si_select_draw_vbo(struct si_context *sctx)
2055 {
2056 pipe_draw_func draw_vbo = sctx->draw_vbo[!!sctx->shader.tes.cso]
2057 [!!sctx->shader.gs.cso]
2058 [sctx->ngg];
2059 pipe_draw_vertex_state_func draw_vertex_state =
2060 sctx->draw_vertex_state[!!sctx->shader.tes.cso]
2061 [!!sctx->shader.gs.cso]
2062 [sctx->ngg];
2063 assert(draw_vbo);
2064 assert(draw_vertex_state);
2065
2066 if (unlikely(sctx->real_draw_vbo)) {
2067 assert(sctx->real_draw_vertex_state);
2068 sctx->real_draw_vbo = draw_vbo;
2069 sctx->real_draw_vertex_state = draw_vertex_state;
2070 } else {
2071 assert(!sctx->real_draw_vertex_state);
2072 sctx->b.draw_vbo = draw_vbo;
2073 sctx->b.draw_vertex_state = draw_vertex_state;
2074 }
2075 }
2076
2077 /* Return the number of samples that the rasterizer uses. */
si_get_num_coverage_samples(struct si_context * sctx)2078 static inline unsigned si_get_num_coverage_samples(struct si_context *sctx)
2079 {
2080 if (sctx->framebuffer.nr_samples > 1 &&
2081 sctx->queued.named.rasterizer->multisample_enable)
2082 return sctx->framebuffer.nr_samples;
2083
2084 /* Note that smoothing_enabled is set by si_update_shaders. */
2085 if (sctx->smoothing_enabled)
2086 return SI_NUM_SMOOTH_AA_SAMPLES;
2087
2088 return 1;
2089 }
2090
2091 static unsigned ALWAYS_INLINE
si_num_vbos_in_user_sgprs_inline(enum amd_gfx_level gfx_level)2092 si_num_vbos_in_user_sgprs_inline(enum amd_gfx_level gfx_level)
2093 {
2094 /* This decreases CPU overhead if all descriptors are in user SGPRs because we don't
2095 * have to allocate and count references for the upload buffer.
2096 */
2097 return gfx_level >= GFX9 ? 5 : 1;
2098 }
2099
si_num_vbos_in_user_sgprs(struct si_screen * sscreen)2100 static inline unsigned si_num_vbos_in_user_sgprs(struct si_screen *sscreen)
2101 {
2102 return si_num_vbos_in_user_sgprs_inline(sscreen->info.gfx_level);
2103 }
2104
2105 static inline
si_check_dirty_buffers_textures(struct si_context * sctx)2106 void si_check_dirty_buffers_textures(struct si_context *sctx)
2107 {
2108 /* Recompute and re-emit the texture resource states if needed. */
2109 unsigned dirty_tex_counter = p_atomic_read(&sctx->screen->dirty_tex_counter);
2110 if (unlikely(dirty_tex_counter != sctx->last_dirty_tex_counter)) {
2111 sctx->last_dirty_tex_counter = dirty_tex_counter;
2112 sctx->framebuffer.dirty_cbufs |= ((1 << sctx->framebuffer.state.nr_cbufs) - 1);
2113 sctx->framebuffer.dirty_zsbuf = true;
2114 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
2115 si_update_all_texture_descriptors(sctx);
2116 }
2117
2118 unsigned dirty_buf_counter = p_atomic_read(&sctx->screen->dirty_buf_counter);
2119 if (unlikely(dirty_buf_counter != sctx->last_dirty_buf_counter)) {
2120 sctx->last_dirty_buf_counter = dirty_buf_counter;
2121 /* Rebind all buffers unconditionally. */
2122 si_rebind_buffer(sctx, NULL);
2123 }
2124 }
2125
si_set_clip_discard_distance(struct si_context * sctx,float distance)2126 static inline void si_set_clip_discard_distance(struct si_context *sctx, float distance)
2127 {
2128 /* Determine whether the guardband registers change.
2129 *
2130 * When we see a value greater than min_clip_discard_distance_watermark, we increase it
2131 * up to a certain number to eliminate those state changes next time they happen.
2132 * See the comment at min_clip_discard_distance_watermark.
2133 */
2134 if (distance > sctx->min_clip_discard_distance_watermark) {
2135 /* The maximum number was determined from Viewperf. The number is in units of half-pixels. */
2136 sctx->min_clip_discard_distance_watermark = MIN2(distance, 6);
2137
2138 float old_distance = sctx->current_clip_discard_distance;
2139 float new_distance = MAX2(distance, sctx->min_clip_discard_distance_watermark);
2140
2141 if (old_distance != new_distance) {
2142 sctx->current_clip_discard_distance = new_distance;
2143 si_mark_atom_dirty(sctx, &sctx->atoms.s.guardband);
2144 }
2145 }
2146 }
2147
2148 /* Update these two GS_STATE fields. They depend on whatever the last shader before PS is
2149 * and the rasterizer state.
2150 *
2151 * It's expected that hw_vs and ngg are inline constants in draw_vbo after optimizations.
2152 */
2153 static inline void
si_update_ngg_sgpr_state_provoking_vtx(struct si_context * sctx,struct si_shader * hw_vs,bool ngg)2154 si_update_ngg_sgpr_state_provoking_vtx(struct si_context *sctx, struct si_shader *hw_vs, bool ngg)
2155 {
2156 if (ngg && hw_vs && hw_vs->uses_vs_state_provoking_vertex) {
2157 SET_FIELD(sctx->current_gs_state, GS_STATE_PROVOKING_VTX_FIRST,
2158 sctx->queued.named.rasterizer->flatshade_first);
2159 }
2160 }
2161
2162 static inline void
si_update_ngg_sgpr_state_out_prim(struct si_context * sctx,struct si_shader * hw_vs,bool ngg)2163 si_update_ngg_sgpr_state_out_prim(struct si_context *sctx, struct si_shader *hw_vs, bool ngg)
2164 {
2165 if (ngg && hw_vs && hw_vs->uses_gs_state_outprim)
2166 SET_FIELD(sctx->current_gs_state, GS_STATE_OUTPRIM, sctx->gs_out_prim);
2167 }
2168
2169 /* Set the primitive type seen by the rasterizer. GS and tessellation affect this.
2170 * It's expected that hw_vs and ngg are inline constants in draw_vbo after optimizations.
2171 */
2172 static ALWAYS_INLINE void
si_set_rasterized_prim(struct si_context * sctx,enum mesa_prim rast_prim,struct si_shader * hw_vs,bool ngg)2173 si_set_rasterized_prim(struct si_context *sctx, enum mesa_prim rast_prim,
2174 struct si_shader *hw_vs, bool ngg)
2175 {
2176 if (rast_prim != sctx->current_rast_prim) {
2177 bool is_rect = rast_prim == SI_PRIM_RECTANGLE_LIST;
2178 bool is_points = rast_prim == MESA_PRIM_POINTS;
2179 bool is_lines = util_prim_is_lines(rast_prim);
2180
2181 if (is_points) {
2182 si_set_clip_discard_distance(sctx, sctx->queued.named.rasterizer->max_point_size);
2183 sctx->gs_out_prim = V_028A6C_POINTLIST;
2184 } else if (is_lines) {
2185 si_set_clip_discard_distance(sctx, sctx->queued.named.rasterizer->line_width);
2186 sctx->gs_out_prim = V_028A6C_LINESTRIP;
2187 } else if (is_rect) {
2188 /* Don't change the clip discard distance for rectangles. */
2189 sctx->gs_out_prim = V_028A6C_RECTLIST;
2190 } else {
2191 si_set_clip_discard_distance(sctx, 0);
2192 sctx->gs_out_prim = V_028A6C_TRISTRIP;
2193 }
2194
2195 sctx->current_rast_prim = rast_prim;
2196 si_vs_ps_key_update_rast_prim_smooth_stipple(sctx);
2197 si_update_ngg_sgpr_state_out_prim(sctx, hw_vs, ngg);
2198 }
2199 }
2200
2201 /* There are 3 ways to flush caches and all of them are correct.
2202 *
2203 * 1) sctx->flags |= ...;
2204 * si_mark_atom_dirty(sctx, &sctx->atoms.s.cache_flush); // deferred
2205 *
2206 * 2) sctx->flags |= ...;
2207 * si_emit_cache_flush_direct(sctx); // immediate
2208 *
2209 * 3) sctx->flags |= ...;
2210 * sctx->emit_cache_flush(sctx, cs); // immediate (2 is better though)
2211 */
si_emit_cache_flush_direct(struct si_context * sctx)2212 static inline void si_emit_cache_flush_direct(struct si_context *sctx)
2213 {
2214 sctx->emit_cache_flush(sctx, &sctx->gfx_cs);
2215 sctx->dirty_atoms &= ~SI_ATOM_BIT(cache_flush);
2216 }
2217
2218 /* Return the number of samples that the rasterizer uses. */
si_get_num_coverage_samples(struct si_context * sctx)2219 static inline unsigned si_get_num_coverage_samples(struct si_context *sctx)
2220 {
2221 if (sctx->framebuffer.nr_samples > 1 &&
2222 sctx->queued.named.rasterizer->multisample_enable)
2223 return sctx->framebuffer.nr_samples;
2224
2225 /* Note that smoothing_enabled is set by si_update_shaders. */
2226 if (sctx->smoothing_enabled)
2227 return SI_NUM_SMOOTH_AA_SAMPLES;
2228
2229 return 1;
2230 }
2231
2232 #define PRINT_ERR(fmt, args...) \
2233 fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
2234
2235 #ifdef __cplusplus
2236 }
2237 #endif
2238
2239 #endif
2240