1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * SPDX-License-Identifier: MIT
5 */
6
7 #include "si_build_pm4.h"
8
9 #include "util/hash_table.h"
10 #define XXH_INLINE_ALL
11 #include "util/xxhash.h"
12 #include "util/u_cpu_detect.h"
13 #include "util/u_index_modify.h"
14 #include "util/u_prim.h"
15 #include "util/u_upload_mgr.h"
16 #include "ac_rtld.h"
17 #include "si_build_pm4.h"
18 #include "si_tracepoints.h"
19
20 #if (GFX_VER == 6)
21 #define GFX(name) name##GFX6
22 #elif (GFX_VER == 7)
23 #define GFX(name) name##GFX7
24 #elif (GFX_VER == 8)
25 #define GFX(name) name##GFX8
26 #elif (GFX_VER == 9)
27 #define GFX(name) name##GFX9
28 #elif (GFX_VER == 10)
29 #define GFX(name) name##GFX10
30 #elif (GFX_VER == 103)
31 #define GFX(name) name##GFX10_3
32 #elif (GFX_VER == 11)
33 #define GFX(name) name##GFX11
34 #elif (GFX_VER == 115)
35 #define GFX(name) name##GFX11_5
36 #else
37 #error "Unknown gfx level"
38 #endif
39
40 template <amd_gfx_level GFX_VERSION, si_has_tess HAS_TESS, si_has_gs HAS_GS, si_has_ngg NGG>
si_update_shaders(struct si_context * sctx)41 static bool si_update_shaders(struct si_context *sctx)
42 {
43 struct pipe_context *ctx = (struct pipe_context *)sctx;
44 struct si_shader *old_vs = si_get_vs_inline(sctx, HAS_TESS, HAS_GS)->current;
45 unsigned old_pa_cl_vs_out_cntl = old_vs ? old_vs->pa_cl_vs_out_cntl : 0;
46 bool old_uses_vs_state_provoking_vertex = old_vs ? old_vs->uses_vs_state_provoking_vertex : false;
47 bool old_uses_gs_state_outprim = old_vs ? old_vs->uses_gs_state_outprim : false;
48 struct si_shader *old_ps = sctx->shader.ps.current;
49 unsigned old_spi_shader_col_format =
50 old_ps ? old_ps->key.ps.part.epilog.spi_shader_col_format : 0;
51 int r;
52
53 /* Update TCS and TES. */
54 if (HAS_TESS) {
55 if (!sctx->tess_rings) {
56 si_init_tess_factor_ring(sctx);
57 if (!sctx->tess_rings)
58 return false;
59 }
60
61 if (!sctx->is_user_tcs) {
62 if (!si_set_tcs_to_fixed_func_shader(sctx))
63 return false;
64 }
65
66 r = si_shader_select(ctx, &sctx->shader.tcs);
67 if (r)
68 return false;
69 si_pm4_bind_state(sctx, hs, sctx->shader.tcs.current);
70
71 if (!HAS_GS || GFX_VERSION <= GFX8) {
72 r = si_shader_select(ctx, &sctx->shader.tes);
73 if (r)
74 return false;
75
76 if (HAS_GS) {
77 /* TES as ES */
78 assert(GFX_VERSION <= GFX8);
79 si_pm4_bind_state(sctx, es, sctx->shader.tes.current);
80 } else if (NGG) {
81 si_pm4_bind_state(sctx, gs, sctx->shader.tes.current);
82 } else {
83 si_pm4_bind_state(sctx, vs, sctx->shader.tes.current);
84 }
85 }
86 } else {
87 /* Reset TCS to clear fixed function shader. */
88 if (!sctx->is_user_tcs && sctx->shader.tcs.cso) {
89 sctx->shader.tcs.cso = NULL;
90 sctx->shader.tcs.current = NULL;
91 }
92
93 if (GFX_VERSION <= GFX8) {
94 si_pm4_bind_state(sctx, ls, NULL);
95 sctx->prefetch_L2_mask &= ~SI_PREFETCH_LS;
96 }
97 si_pm4_bind_state(sctx, hs, NULL);
98 sctx->prefetch_L2_mask &= ~SI_PREFETCH_HS;
99 }
100
101 /* Update GS. */
102 if (HAS_GS) {
103 r = si_shader_select(ctx, &sctx->shader.gs);
104 if (r)
105 return false;
106 si_pm4_bind_state(sctx, gs, sctx->shader.gs.current);
107 if (!NGG) {
108 si_pm4_bind_state(sctx, vs, sctx->shader.gs.current->gs_copy_shader);
109
110 if (!si_update_gs_ring_buffers(sctx))
111 return false;
112 } else if (GFX_VERSION < GFX11) {
113 si_pm4_bind_state(sctx, vs, NULL);
114 sctx->prefetch_L2_mask &= ~SI_PREFETCH_VS;
115 }
116 } else {
117 if (!NGG) {
118 si_pm4_bind_state(sctx, gs, NULL);
119 sctx->prefetch_L2_mask &= ~SI_PREFETCH_GS;
120 if (GFX_VERSION <= GFX8) {
121 si_pm4_bind_state(sctx, es, NULL);
122 sctx->prefetch_L2_mask &= ~SI_PREFETCH_ES;
123 }
124 }
125 }
126
127 /* Update VS. */
128 if ((!HAS_TESS && !HAS_GS) || GFX_VERSION <= GFX8) {
129 r = si_shader_select(ctx, &sctx->shader.vs);
130 if (r)
131 return false;
132
133 if (!HAS_TESS && !HAS_GS) {
134 if (NGG) {
135 si_pm4_bind_state(sctx, gs, sctx->shader.vs.current);
136 if (GFX_VERSION < GFX11) {
137 si_pm4_bind_state(sctx, vs, NULL);
138 sctx->prefetch_L2_mask &= ~SI_PREFETCH_VS;
139 }
140 } else {
141 si_pm4_bind_state(sctx, vs, sctx->shader.vs.current);
142 }
143 } else if (HAS_TESS) {
144 si_pm4_bind_state(sctx, ls, sctx->shader.vs.current);
145 } else {
146 assert(HAS_GS);
147 si_pm4_bind_state(sctx, es, sctx->shader.vs.current);
148 }
149 }
150
151 if (GFX_VERSION >= GFX9 && HAS_TESS)
152 sctx->vs_uses_base_instance = sctx->queued.named.hs->uses_base_instance;
153 else if (GFX_VERSION >= GFX9 && HAS_GS)
154 sctx->vs_uses_base_instance = sctx->shader.gs.current->uses_base_instance;
155 else
156 sctx->vs_uses_base_instance = sctx->shader.vs.current->uses_base_instance;
157
158 /* Update VGT_SHADER_STAGES_EN. */
159 uint32_t vgt_stages = 0;
160
161 if (HAS_TESS) {
162 vgt_stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
163 S_028B54_HS_EN(1) |
164 S_028B54_DYNAMIC_HS(1) |
165 S_028B54_HS_W32_EN(GFX_VERSION >= GFX10 &&
166 sctx->queued.named.hs->wave_size == 32);
167 }
168
169 if (NGG) {
170 vgt_stages |= si_get_vs_inline(sctx, HAS_TESS, HAS_GS)->current->ngg.vgt_shader_stages_en;
171 } else {
172 if (HAS_GS) {
173 /* Legacy GS only supports Wave64. */
174 assert(sctx->shader.gs.current->wave_size == 64);
175
176 vgt_stages |= S_028B54_ES_EN(HAS_TESS ? V_028B54_ES_STAGE_DS : V_028B54_ES_STAGE_REAL) |
177 S_028B54_GS_EN(1) |
178 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER) |
179 S_028B54_VS_W32_EN(GFX_VERSION >= GFX10 &&
180 sctx->shader.gs.current->gs_copy_shader->wave_size == 32);
181 } else if (HAS_TESS) {
182 vgt_stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
183 }
184
185 vgt_stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(GFX_VERSION >= GFX9 ? 2 : 0) |
186 S_028B54_VS_W32_EN(!HAS_GS && GFX_VERSION >= GFX10 &&
187 si_get_vs_inline(sctx, HAS_TESS, HAS_GS)->current->wave_size == 32);
188 }
189
190 /* Update GE_CNTL. */
191 uint32_t ge_cntl = 0;
192
193 if (GFX_VERSION >= GFX10) {
194 union si_vgt_param_key key = sctx->ia_multi_vgt_param_key;
195
196 if (NGG) {
197 if (HAS_TESS) {
198 if (GFX_VERSION >= GFX11) {
199 ge_cntl = si_get_vs_inline(sctx, HAS_TESS, HAS_GS)->current->ge_cntl |
200 S_03096C_BREAK_PRIMGRP_AT_EOI(key.u.tess_uses_prim_id);
201 } else {
202 /* PRIM_GRP_SIZE_GFX10 is set by si_emit_vgt_pipeline_state. */
203 ge_cntl = S_03096C_VERT_GRP_SIZE(0) |
204 S_03096C_BREAK_WAVE_AT_EOI(key.u.tess_uses_prim_id);
205 }
206 } else {
207 ge_cntl = si_get_vs_inline(sctx, HAS_TESS, HAS_GS)->current->ge_cntl;
208 }
209 } else {
210 unsigned primgroup_size;
211 unsigned vertgroup_size;
212 assert(GFX_VERSION < GFX11);
213
214 if (HAS_TESS) {
215 primgroup_size = 0; /* this is set by si_emit_vgt_pipeline_state */
216 vertgroup_size = 0;
217 } else if (HAS_GS) {
218 unsigned vgt_gs_onchip_cntl = sctx->shader.gs.current->gs.vgt_gs_onchip_cntl;
219 primgroup_size = G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl);
220 vertgroup_size = G_028A44_ES_VERTS_PER_SUBGRP(vgt_gs_onchip_cntl);
221 } else {
222 primgroup_size = 128; /* recommended without a GS and tess */
223 vertgroup_size = 0;
224 }
225
226 ge_cntl = S_03096C_PRIM_GRP_SIZE_GFX10(primgroup_size) |
227 S_03096C_VERT_GRP_SIZE(vertgroup_size) |
228 S_03096C_BREAK_WAVE_AT_EOI(key.u.uses_tess && key.u.tess_uses_prim_id);
229 }
230
231 /* Note: GE_CNTL.PACKET_TO_ONE_PA should only be set if LINE_STIPPLE_TEX_ENA == 1.
232 * Since we don't use that, we don't have to do anything.
233 */
234 }
235
236 if (vgt_stages != sctx->vgt_shader_stages_en ||
237 (GFX_VERSION >= GFX10 && ge_cntl != sctx->ge_cntl)) {
238 sctx->vgt_shader_stages_en = vgt_stages;
239 sctx->ge_cntl = ge_cntl;
240 si_mark_atom_dirty(sctx, &sctx->atoms.s.vgt_pipeline_state);
241 }
242
243 struct si_shader *hw_vs = si_get_vs_inline(sctx, HAS_TESS, HAS_GS)->current;
244
245 if (old_pa_cl_vs_out_cntl != hw_vs->pa_cl_vs_out_cntl)
246 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
247
248 /* If we start to use any of these, we need to update the SGPR. */
249 if ((hw_vs->uses_vs_state_provoking_vertex && !old_uses_vs_state_provoking_vertex) ||
250 (hw_vs->uses_gs_state_outprim && !old_uses_gs_state_outprim)) {
251 si_update_ngg_sgpr_state_out_prim(sctx, hw_vs, NGG);
252 si_update_ngg_sgpr_state_provoking_vtx(sctx, hw_vs, NGG);
253 }
254
255 r = si_shader_select(ctx, &sctx->shader.ps);
256 if (r)
257 return false;
258 si_pm4_bind_state(sctx, ps, sctx->shader.ps.current);
259
260 unsigned db_shader_control = sctx->shader.ps.current->ps.db_shader_control;
261 if (sctx->ps_db_shader_control != db_shader_control) {
262 sctx->ps_db_shader_control = db_shader_control;
263 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
264 if (sctx->screen->dpbb_allowed)
265 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
266 }
267
268 if (si_pm4_state_changed(sctx, ps) ||
269 (!NGG && si_pm4_state_changed(sctx, vs)) ||
270 (NGG && si_pm4_state_changed(sctx, gs))) {
271 sctx->atoms.s.spi_map.emit = sctx->emit_spi_map[sctx->shader.ps.current->ps.num_interp];
272 si_mark_atom_dirty(sctx, &sctx->atoms.s.spi_map);
273 }
274
275 if ((GFX_VERSION >= GFX10_3 || (GFX_VERSION >= GFX9 && sctx->screen->info.rbplus_allowed)) &&
276 si_pm4_state_changed(sctx, ps) &&
277 (!old_ps || old_spi_shader_col_format !=
278 sctx->shader.ps.current->key.ps.part.epilog.spi_shader_col_format))
279 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
280
281 if (sctx->smoothing_enabled !=
282 sctx->shader.ps.current->key.ps.mono.poly_line_smoothing) {
283 sctx->smoothing_enabled = sctx->shader.ps.current->key.ps.mono.poly_line_smoothing;
284 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
285
286 /* NGG cull state uses smoothing_enabled. */
287 if (GFX_VERSION >= GFX10 && sctx->screen->use_ngg_culling)
288 si_mark_atom_dirty(sctx, &sctx->atoms.s.ngg_cull_state);
289
290 if (GFX_VERSION == GFX11 && sctx->screen->info.has_export_conflict_bug)
291 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
292
293 if (sctx->framebuffer.nr_samples <= 1)
294 si_mark_atom_dirty(sctx, &sctx->atoms.s.sample_locations);
295 }
296
297 if (HAS_TESS)
298 si_update_tess_io_layout_state(sctx);
299
300 if (GFX_VERSION >= GFX9 && unlikely(sctx->sqtt)) {
301 /* Pretend the bound shaders form a vk pipeline. Include the scratch size in
302 * the hash calculation to force re-emitting the pipeline if the scratch bo
303 * changes.
304 */
305 uint64_t scratch_bo_size = sctx->scratch_buffer ? sctx->scratch_buffer->bo_size : 0;
306 uint64_t pipeline_code_hash = scratch_bo_size;
307 uint32_t total_size = 0;
308
309 /* Compute pipeline code hash. */
310 for (int i = 0; i < SI_NUM_GRAPHICS_SHADERS; i++) {
311 struct si_shader *shader = sctx->shaders[i].current;
312 if (sctx->shaders[i].cso && shader) {
313 pipeline_code_hash = XXH64(
314 shader->binary.code_buffer,
315 shader->binary.code_size,
316 pipeline_code_hash);
317
318 total_size += (uint32_t)align_uintptr(shader->binary.uploaded_code_size, 256);
319 }
320 }
321
322 struct si_sqtt_fake_pipeline *pipeline = NULL;
323 if (!si_sqtt_pipeline_is_registered(sctx->sqtt, pipeline_code_hash)) {
324 /* This is a new pipeline. Allocate a new bo to hold all the shaders. Without
325 * this, shader code export process creates huge rgp files because RGP assumes
326 * the shaders live sequentially in memory (shader N address = shader 0 + offset N)
327 */
328 struct si_resource *bo = si_aligned_buffer_create(
329 &sctx->screen->b,
330 (sctx->screen->info.cpdma_prefetch_writes_memory ? 0 : SI_RESOURCE_FLAG_READ_ONLY) |
331 SI_RESOURCE_FLAG_DRIVER_INTERNAL | SI_RESOURCE_FLAG_32BIT,
332 PIPE_USAGE_IMMUTABLE, align(total_size, SI_CPDMA_ALIGNMENT), 256);
333
334 char *ptr = (char *) (bo ? sctx->screen->ws->buffer_map(sctx->screen->ws,
335 bo->buf, NULL,
336 (enum pipe_map_flags)(PIPE_MAP_READ_WRITE | PIPE_MAP_UNSYNCHRONIZED | RADEON_MAP_TEMPORARY)) :
337 NULL);
338
339 uint32_t offset = 0;
340 uint64_t scratch_va = sctx->scratch_buffer ? sctx->scratch_buffer->gpu_address : 0;
341
342 if (ptr) {
343 pipeline = (struct si_sqtt_fake_pipeline *)
344 CALLOC(1, sizeof(struct si_sqtt_fake_pipeline));
345 pipeline->code_hash = pipeline_code_hash;
346 si_resource_reference(&pipeline->bo, bo);
347
348 /* Re-upload all gfx shaders and init PM4. */
349 si_pm4_clear_state(&pipeline->pm4, sctx->screen, false);
350
351 for (int i = 0; i < SI_NUM_GRAPHICS_SHADERS; i++) {
352 struct si_shader *shader = sctx->shaders[i].current;
353 if (sctx->shaders[i].cso && shader) {
354 struct ac_rtld_binary binary;
355 si_shader_binary_open(sctx->screen, shader, &binary);
356
357 struct ac_rtld_upload_info u = {};
358 u.binary = &binary;
359 u.get_external_symbol = si_get_external_symbol;
360 u.cb_data = &scratch_va;
361 u.rx_va = bo->gpu_address + offset;
362 u.rx_ptr = ptr + offset;
363
364 int size = ac_rtld_upload(&u);
365 ac_rtld_close(&binary);
366
367 pipeline->offset[i] = offset;
368
369 shader->gpu_address = u.rx_va;
370
371 offset += align(size, 256);
372
373 struct si_pm4_state *pm4 = &shader->pm4;
374
375 uint64_t va_low = (pipeline->bo->gpu_address + pipeline->offset[i]) >> 8;
376 uint32_t reg = pm4->spi_shader_pgm_lo_reg;
377 si_pm4_set_reg(&pipeline->pm4, reg, va_low);
378 }
379 }
380 si_pm4_finalize(&pipeline->pm4);
381 sctx->screen->ws->buffer_unmap(sctx->screen->ws, bo->buf);
382
383 _mesa_hash_table_u64_insert(sctx->sqtt->pipeline_bos,
384 pipeline_code_hash, pipeline);
385
386 si_sqtt_register_pipeline(sctx, pipeline, false);
387 } else {
388 if (bo)
389 si_resource_reference(&bo, NULL);
390 }
391 } else {
392 pipeline = (struct si_sqtt_fake_pipeline *)_mesa_hash_table_u64_search(
393 sctx->sqtt->pipeline_bos, pipeline_code_hash);
394 }
395 assert(pipeline);
396
397 pipeline->code_hash = pipeline_code_hash;
398 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, pipeline->bo,
399 RADEON_USAGE_READ | RADEON_PRIO_SHADER_BINARY);
400
401 si_sqtt_describe_pipeline_bind(sctx, pipeline_code_hash, 0);
402 si_pm4_bind_state(sctx, sqtt_pipeline, pipeline);
403 }
404
405 if ((GFX_VERSION <= GFX8 &&
406 (si_pm4_state_enabled_and_changed(sctx, ls) || si_pm4_state_enabled_and_changed(sctx, es))) ||
407 si_pm4_state_enabled_and_changed(sctx, hs) || si_pm4_state_enabled_and_changed(sctx, gs) ||
408 (!NGG && si_pm4_state_enabled_and_changed(sctx, vs)) || si_pm4_state_enabled_and_changed(sctx, ps)) {
409 unsigned scratch_size = 0;
410
411 if (HAS_TESS) {
412 if (GFX_VERSION <= GFX8) /* LS */
413 scratch_size = MAX2(scratch_size, sctx->shader.vs.current->config.scratch_bytes_per_wave);
414
415 scratch_size = MAX2(scratch_size, sctx->queued.named.hs->config.scratch_bytes_per_wave);
416
417 if (HAS_GS) {
418 if (GFX_VERSION <= GFX8) /* ES */
419 scratch_size = MAX2(scratch_size, sctx->shader.tes.current->config.scratch_bytes_per_wave);
420
421 scratch_size = MAX2(scratch_size, sctx->shader.gs.current->config.scratch_bytes_per_wave);
422 } else {
423 scratch_size = MAX2(scratch_size, sctx->shader.tes.current->config.scratch_bytes_per_wave);
424 }
425 } else if (HAS_GS) {
426 if (GFX_VERSION <= GFX8) /* ES */
427 scratch_size = MAX2(scratch_size, sctx->shader.vs.current->config.scratch_bytes_per_wave);
428
429 scratch_size = MAX2(scratch_size, sctx->shader.gs.current->config.scratch_bytes_per_wave);
430 } else {
431 scratch_size = MAX2(scratch_size, sctx->shader.vs.current->config.scratch_bytes_per_wave);
432 }
433
434 scratch_size = MAX2(scratch_size, sctx->shader.ps.current->config.scratch_bytes_per_wave);
435
436 if (scratch_size && !si_update_spi_tmpring_size(sctx, scratch_size))
437 return false;
438
439 if (GFX_VERSION >= GFX7) {
440 if (GFX_VERSION <= GFX8 && HAS_TESS && si_pm4_state_enabled_and_changed(sctx, ls))
441 sctx->prefetch_L2_mask |= SI_PREFETCH_LS;
442
443 if (HAS_TESS && si_pm4_state_enabled_and_changed(sctx, hs))
444 sctx->prefetch_L2_mask |= SI_PREFETCH_HS;
445
446 if (GFX_VERSION <= GFX8 && HAS_GS && si_pm4_state_enabled_and_changed(sctx, es))
447 sctx->prefetch_L2_mask |= SI_PREFETCH_ES;
448
449 if ((HAS_GS || NGG) && si_pm4_state_enabled_and_changed(sctx, gs))
450 sctx->prefetch_L2_mask |= SI_PREFETCH_GS;
451
452 if (!NGG && si_pm4_state_enabled_and_changed(sctx, vs))
453 sctx->prefetch_L2_mask |= SI_PREFETCH_VS;
454
455 if (si_pm4_state_enabled_and_changed(sctx, ps))
456 sctx->prefetch_L2_mask |= SI_PREFETCH_PS;
457 }
458 }
459
460 /* si_shader_select_with_key can clear the ngg_culling in the shader key if the shader
461 * compilation hasn't finished. Set it to the same value in si_context.
462 */
463 if (GFX_VERSION >= GFX10 && NGG)
464 sctx->ngg_culling = si_get_vs_inline(sctx, HAS_TESS, HAS_GS)->current->key.ge.opt.ngg_culling;
465
466 sctx->do_update_shaders = false;
467 return true;
468 }
469
470 ALWAYS_INLINE
si_conv_pipe_prim(unsigned mode)471 static unsigned si_conv_pipe_prim(unsigned mode)
472 {
473 static const unsigned prim_conv[] = {
474 [MESA_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
475 [MESA_PRIM_LINES] = V_008958_DI_PT_LINELIST,
476 [MESA_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
477 [MESA_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
478 [MESA_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
479 [MESA_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
480 [MESA_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
481 [MESA_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
482 [MESA_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
483 [MESA_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
484 [MESA_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
485 [MESA_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
486 [MESA_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
487 [MESA_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ,
488 [MESA_PRIM_PATCHES] = V_008958_DI_PT_PATCH,
489 [SI_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST};
490 assert(mode < ARRAY_SIZE(prim_conv));
491 return prim_conv[mode];
492 }
493
494 template<amd_gfx_level GFX_VERSION>
si_cp_dma_prefetch_inline(struct si_context * sctx,uint64_t address,unsigned size)495 static void si_cp_dma_prefetch_inline(struct si_context *sctx, uint64_t address, unsigned size)
496 {
497 assert(GFX_VERSION >= GFX7);
498
499 if (GFX_VERSION >= GFX11)
500 size = MIN2(size, 32768 - SI_CPDMA_ALIGNMENT);
501
502 /* The prefetch address and size must be aligned, so that we don't have to apply
503 * the complicated hw bug workaround.
504 *
505 * The size should also be less than 2 MB, so that we don't have to use a loop.
506 * Callers shouldn't need to prefetch more than 2 MB.
507 */
508 assert(size % SI_CPDMA_ALIGNMENT == 0);
509 assert(address % SI_CPDMA_ALIGNMENT == 0);
510 assert(size < S_415_BYTE_COUNT_GFX6(~0u));
511
512 uint32_t header = S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2);
513 uint32_t command = S_415_BYTE_COUNT_GFX6(size);
514
515 if (GFX_VERSION >= GFX9) {
516 command |= S_415_DISABLE_WR_CONFIRM_GFX9(1);
517 header |= S_411_DST_SEL(V_411_NOWHERE);
518 } else {
519 command |= S_415_DISABLE_WR_CONFIRM_GFX6(1);
520 header |= S_411_DST_SEL(V_411_DST_ADDR_TC_L2);
521 }
522
523 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
524 radeon_begin(cs);
525 radeon_emit(PKT3(PKT3_DMA_DATA, 5, 0));
526 radeon_emit(header);
527 radeon_emit(address); /* SRC_ADDR_LO [31:0] */
528 radeon_emit(address >> 32); /* SRC_ADDR_HI [31:0] */
529 radeon_emit(address); /* DST_ADDR_LO [31:0] */
530 radeon_emit(address >> 32); /* DST_ADDR_HI [31:0] */
531 radeon_emit(command);
532 radeon_end();
533 }
534
535 #if GFX_VER == 6 /* declare this function only once because it handles all chips. */
536
si_cp_dma_prefetch(struct si_context * sctx,struct pipe_resource * buf,unsigned offset,unsigned size)537 void si_cp_dma_prefetch(struct si_context *sctx, struct pipe_resource *buf,
538 unsigned offset, unsigned size)
539 {
540 uint64_t address = si_resource(buf)->gpu_address + offset;
541 switch (sctx->gfx_level) {
542 case GFX7:
543 si_cp_dma_prefetch_inline<GFX7>(sctx, address, size);
544 break;
545 case GFX8:
546 si_cp_dma_prefetch_inline<GFX8>(sctx, address, size);
547 break;
548 case GFX9:
549 si_cp_dma_prefetch_inline<GFX9>(sctx, address, size);
550 break;
551 case GFX10:
552 si_cp_dma_prefetch_inline<GFX10>(sctx, address, size);
553 break;
554 case GFX10_3:
555 si_cp_dma_prefetch_inline<GFX10_3>(sctx, address, size);
556 break;
557 case GFX11:
558 si_cp_dma_prefetch_inline<GFX11>(sctx, address, size);
559 break;
560 case GFX11_5:
561 si_cp_dma_prefetch_inline<GFX11_5>(sctx, address, size);
562 break;
563 default:
564 break;
565 }
566 }
567
568 #endif
569
570 template<amd_gfx_level GFX_VERSION>
si_prefetch_shader_async(struct si_context * sctx,struct si_shader * shader)571 static void si_prefetch_shader_async(struct si_context *sctx, struct si_shader *shader)
572 {
573 struct pipe_resource *bo = &shader->bo->b.b;
574 si_cp_dma_prefetch_inline<GFX_VERSION>(sctx, shader->gpu_address, bo->width0);
575 }
576
577 /**
578 * Prefetch shaders.
579 */
580 template<amd_gfx_level GFX_VERSION, si_has_tess HAS_TESS, si_has_gs HAS_GS, si_has_ngg NGG>
581 ALWAYS_INLINE
si_prefetch_shaders(struct si_context * sctx)582 static void si_prefetch_shaders(struct si_context *sctx)
583 {
584 unsigned mask = sctx->prefetch_L2_mask;
585
586 /* GFX6 doesn't support the L2 prefetch. */
587 if (GFX_VERSION < GFX7 || !mask)
588 return;
589
590 /* Prefetch shaders and VBO descriptors to TC L2. */
591 if (GFX_VERSION >= GFX11) {
592 if (HAS_TESS && mask & SI_PREFETCH_HS)
593 si_prefetch_shader_async<GFX_VERSION>(sctx, sctx->queued.named.hs);
594
595 if (mask & SI_PREFETCH_GS)
596 si_prefetch_shader_async<GFX_VERSION>(sctx, sctx->queued.named.gs);
597 } else if (GFX_VERSION >= GFX9) {
598 if (HAS_TESS) {
599 if (mask & SI_PREFETCH_HS)
600 si_prefetch_shader_async<GFX_VERSION>(sctx, sctx->queued.named.hs);
601 }
602 if ((HAS_GS || NGG) && mask & SI_PREFETCH_GS)
603 si_prefetch_shader_async<GFX_VERSION>(sctx, sctx->queued.named.gs);
604 if (!NGG && mask & SI_PREFETCH_VS)
605 si_prefetch_shader_async<GFX_VERSION>(sctx, sctx->queued.named.vs);
606 } else {
607 /* GFX6-GFX8 */
608 /* Choose the right spot for the VBO prefetch. */
609 if (HAS_TESS) {
610 if (mask & SI_PREFETCH_LS)
611 si_prefetch_shader_async<GFX_VERSION>(sctx, sctx->queued.named.ls);
612 if (mask & SI_PREFETCH_HS)
613 si_prefetch_shader_async<GFX_VERSION>(sctx, sctx->queued.named.hs);
614 if (mask & SI_PREFETCH_ES)
615 si_prefetch_shader_async<GFX_VERSION>(sctx, sctx->queued.named.es);
616 if (mask & SI_PREFETCH_GS)
617 si_prefetch_shader_async<GFX_VERSION>(sctx, sctx->queued.named.gs);
618 } else if (HAS_GS) {
619 if (mask & SI_PREFETCH_ES)
620 si_prefetch_shader_async<GFX_VERSION>(sctx, sctx->queued.named.es);
621 if (mask & SI_PREFETCH_GS)
622 si_prefetch_shader_async<GFX_VERSION>(sctx, sctx->queued.named.gs);
623 }
624 if (mask & SI_PREFETCH_VS)
625 si_prefetch_shader_async<GFX_VERSION>(sctx, sctx->queued.named.vs);
626 }
627
628 if (mask & SI_PREFETCH_PS)
629 si_prefetch_shader_async<GFX_VERSION>(sctx, sctx->queued.named.ps);
630
631 /* This must be cleared only when AFTER_DRAW is true. */
632 sctx->prefetch_L2_mask = 0;
633 }
634
si_num_prims_for_vertices(enum mesa_prim prim,unsigned count,unsigned vertices_per_patch)635 static unsigned si_num_prims_for_vertices(enum mesa_prim prim,
636 unsigned count, unsigned vertices_per_patch)
637 {
638 switch (prim) {
639 case MESA_PRIM_PATCHES:
640 return count / vertices_per_patch;
641 case MESA_PRIM_POLYGON:
642 /* It's a triangle fan with different edge flags. */
643 return count >= 3 ? count - 2 : 0;
644 case SI_PRIM_RECTANGLE_LIST:
645 return count / 3;
646 default:
647 return u_decomposed_prims_for_vertices(prim, count);
648 }
649 }
650
si_get_init_multi_vgt_param(struct si_screen * sscreen,union si_vgt_param_key * key)651 static unsigned si_get_init_multi_vgt_param(struct si_screen *sscreen, union si_vgt_param_key *key)
652 {
653 STATIC_ASSERT(sizeof(union si_vgt_param_key) == 2);
654 unsigned max_primgroup_in_wave = 2;
655
656 /* SWITCH_ON_EOP(0) is always preferable. */
657 bool wd_switch_on_eop = false;
658 bool ia_switch_on_eop = false;
659 bool ia_switch_on_eoi = false;
660 bool partial_vs_wave = false;
661 bool partial_es_wave = false;
662
663 if (key->u.uses_tess) {
664 /* SWITCH_ON_EOI must be set if PrimID is used. */
665 if (key->u.tess_uses_prim_id)
666 ia_switch_on_eoi = true;
667
668 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
669 if ((sscreen->info.family == CHIP_TAHITI || sscreen->info.family == CHIP_PITCAIRN ||
670 sscreen->info.family == CHIP_BONAIRE) &&
671 key->u.uses_gs)
672 partial_vs_wave = true;
673
674 /* Needed for 028B6C_DISTRIBUTION_MODE != 0. (implies >= GFX8) */
675 if (sscreen->info.has_distributed_tess) {
676 if (key->u.uses_gs) {
677 if (sscreen->info.gfx_level == GFX8)
678 partial_es_wave = true;
679 } else {
680 partial_vs_wave = true;
681 }
682 }
683 }
684
685 /* This is a hardware requirement. */
686 if (key->u.line_stipple_enabled || (sscreen->debug_flags & DBG(SWITCH_ON_EOP))) {
687 ia_switch_on_eop = true;
688 wd_switch_on_eop = true;
689 }
690
691 if (sscreen->info.gfx_level >= GFX7) {
692 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
693 * 4 shader engines. Set 1 to pass the assertion below.
694 * The other cases are hardware requirements.
695 *
696 * Polaris supports primitive restart with WD_SWITCH_ON_EOP=0
697 * for points, line strips, and tri strips.
698 */
699 if (sscreen->info.max_se <= 2 || key->u.prim == MESA_PRIM_POLYGON ||
700 key->u.prim == MESA_PRIM_LINE_LOOP || key->u.prim == MESA_PRIM_TRIANGLE_FAN ||
701 key->u.prim == MESA_PRIM_TRIANGLE_STRIP_ADJACENCY ||
702 (key->u.primitive_restart &&
703 (sscreen->info.family < CHIP_POLARIS10 ||
704 (key->u.prim != MESA_PRIM_POINTS && key->u.prim != MESA_PRIM_LINE_STRIP &&
705 key->u.prim != MESA_PRIM_TRIANGLE_STRIP))) ||
706 key->u.count_from_stream_output)
707 wd_switch_on_eop = true;
708
709 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
710 * We don't know that for indirect drawing, so treat it as
711 * always problematic. */
712 if (sscreen->info.family == CHIP_HAWAII && key->u.uses_instancing)
713 wd_switch_on_eop = true;
714
715 /* Performance recommendation for 4 SE Gfx7-8 parts if
716 * instances are smaller than a primgroup.
717 * Assume indirect draws always use small instances.
718 * This is needed for good VS wave utilization.
719 */
720 if (sscreen->info.gfx_level <= GFX8 && sscreen->info.max_se == 4 &&
721 key->u.multi_instances_smaller_than_primgroup)
722 wd_switch_on_eop = true;
723
724 /* Required on GFX7 and later. */
725 if (sscreen->info.max_se == 4 && !wd_switch_on_eop)
726 ia_switch_on_eoi = true;
727
728 /* HW engineers suggested that PARTIAL_VS_WAVE_ON should be set
729 * to work around a GS hang.
730 */
731 if (key->u.uses_gs &&
732 (sscreen->info.family == CHIP_TONGA || sscreen->info.family == CHIP_FIJI ||
733 sscreen->info.family == CHIP_POLARIS10 || sscreen->info.family == CHIP_POLARIS11 ||
734 sscreen->info.family == CHIP_POLARIS12 || sscreen->info.family == CHIP_VEGAM))
735 partial_vs_wave = true;
736
737 /* Required by Hawaii and, for some special cases, by GFX8. */
738 if (ia_switch_on_eoi &&
739 (sscreen->info.family == CHIP_HAWAII ||
740 (sscreen->info.gfx_level == GFX8 && (key->u.uses_gs || max_primgroup_in_wave != 2))))
741 partial_vs_wave = true;
742
743 /* Instancing bug on Bonaire. */
744 if (sscreen->info.family == CHIP_BONAIRE && ia_switch_on_eoi && key->u.uses_instancing)
745 partial_vs_wave = true;
746
747 /* This only applies to Polaris10 and later 4 SE chips.
748 * wd_switch_on_eop is already true on all other chips.
749 */
750 if (!wd_switch_on_eop && key->u.primitive_restart)
751 partial_vs_wave = true;
752
753 /* If the WD switch is false, the IA switch must be false too. */
754 assert(wd_switch_on_eop || !ia_switch_on_eop);
755 }
756
757 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
758 if (sscreen->info.gfx_level <= GFX8 && ia_switch_on_eoi)
759 partial_es_wave = true;
760
761 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) | S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
762 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
763 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
764 S_028AA8_WD_SWITCH_ON_EOP(sscreen->info.gfx_level >= GFX7 ? wd_switch_on_eop : 0) |
765 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
766 S_028AA8_MAX_PRIMGRP_IN_WAVE(sscreen->info.gfx_level == GFX8 ? max_primgroup_in_wave
767 : 0) |
768 S_030960_EN_INST_OPT_BASIC(sscreen->info.gfx_level >= GFX9) |
769 S_030960_EN_INST_OPT_ADV(sscreen->info.gfx_level >= GFX9);
770 }
771
si_init_ia_multi_vgt_param_table(struct si_context * sctx)772 static void si_init_ia_multi_vgt_param_table(struct si_context *sctx)
773 {
774 for (int prim = 0; prim <= SI_PRIM_RECTANGLE_LIST; prim++)
775 for (int uses_instancing = 0; uses_instancing < 2; uses_instancing++)
776 for (int multi_instances = 0; multi_instances < 2; multi_instances++)
777 for (int primitive_restart = 0; primitive_restart < 2; primitive_restart++)
778 for (int count_from_so = 0; count_from_so < 2; count_from_so++)
779 for (int line_stipple = 0; line_stipple < 2; line_stipple++)
780 for (int uses_tess = 0; uses_tess < 2; uses_tess++)
781 for (int tess_uses_primid = 0; tess_uses_primid < 2; tess_uses_primid++)
782 for (int uses_gs = 0; uses_gs < 2; uses_gs++) {
783 union si_vgt_param_key key;
784
785 key.index = 0;
786 key.u.prim = prim;
787 key.u.uses_instancing = uses_instancing;
788 key.u.multi_instances_smaller_than_primgroup = multi_instances;
789 key.u.primitive_restart = primitive_restart;
790 key.u.count_from_stream_output = count_from_so;
791 key.u.line_stipple_enabled = line_stipple;
792 key.u.uses_tess = uses_tess;
793 key.u.tess_uses_prim_id = tess_uses_primid;
794 key.u.uses_gs = uses_gs;
795
796 sctx->ia_multi_vgt_param[key.index] =
797 si_get_init_multi_vgt_param(sctx->screen, &key);
798 }
799 }
800
si_is_line_stipple_enabled(struct si_context * sctx)801 static bool si_is_line_stipple_enabled(struct si_context *sctx)
802 {
803 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
804
805 return rs->line_stipple_enable && sctx->current_rast_prim != MESA_PRIM_POINTS &&
806 (rs->polygon_mode_is_lines || util_prim_is_lines(sctx->current_rast_prim));
807 }
808
809 enum si_is_draw_vertex_state {
810 DRAW_VERTEX_STATE_OFF,
811 DRAW_VERTEX_STATE_ON,
812 };
813
814 enum si_has_sh_pairs_packed {
815 HAS_SH_PAIRS_PACKED_OFF,
816 HAS_SH_PAIRS_PACKED_ON,
817 };
818
819 template <si_is_draw_vertex_state IS_DRAW_VERTEX_STATE> ALWAYS_INLINE
num_instanced_prims_less_than(const struct pipe_draw_indirect_info * indirect,enum mesa_prim prim,unsigned min_vertex_count,unsigned instance_count,unsigned num_prims,uint8_t vertices_per_patch)820 static bool num_instanced_prims_less_than(const struct pipe_draw_indirect_info *indirect,
821 enum mesa_prim prim,
822 unsigned min_vertex_count,
823 unsigned instance_count,
824 unsigned num_prims,
825 uint8_t vertices_per_patch)
826 {
827 if (IS_DRAW_VERTEX_STATE)
828 return 0;
829
830 if (indirect) {
831 return indirect->buffer ||
832 (instance_count > 1 && indirect->count_from_stream_output);
833 } else {
834 return instance_count > 1 &&
835 si_num_prims_for_vertices(prim, min_vertex_count, vertices_per_patch) < num_prims;
836 }
837 }
838
839 template <amd_gfx_level GFX_VERSION, si_has_tess HAS_TESS, si_has_gs HAS_GS,
840 si_is_draw_vertex_state IS_DRAW_VERTEX_STATE> ALWAYS_INLINE
si_get_ia_multi_vgt_param(struct si_context * sctx,const struct pipe_draw_indirect_info * indirect,enum mesa_prim prim,unsigned instance_count,bool primitive_restart,unsigned min_vertex_count)841 static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
842 const struct pipe_draw_indirect_info *indirect,
843 enum mesa_prim prim, unsigned instance_count,
844 bool primitive_restart, unsigned min_vertex_count)
845 {
846 union si_vgt_param_key key = sctx->ia_multi_vgt_param_key;
847 unsigned primgroup_size;
848 unsigned ia_multi_vgt_param;
849
850 if (HAS_TESS) {
851 primgroup_size = sctx->num_patches_per_workgroup;
852 } else if (HAS_GS) {
853 primgroup_size = 64; /* recommended with a GS */
854 } else {
855 primgroup_size = 128; /* recommended without a GS and tess */
856 }
857
858 key.u.prim = prim;
859 key.u.uses_instancing = !IS_DRAW_VERTEX_STATE &&
860 ((indirect && indirect->buffer) || instance_count > 1);
861 key.u.multi_instances_smaller_than_primgroup =
862 num_instanced_prims_less_than<IS_DRAW_VERTEX_STATE>(indirect, prim, min_vertex_count,
863 instance_count, primgroup_size,
864 sctx->patch_vertices);
865 key.u.primitive_restart = !IS_DRAW_VERTEX_STATE && primitive_restart;
866 key.u.count_from_stream_output = !IS_DRAW_VERTEX_STATE && indirect &&
867 indirect->count_from_stream_output;
868 key.u.line_stipple_enabled = si_is_line_stipple_enabled(sctx);
869
870 ia_multi_vgt_param =
871 sctx->ia_multi_vgt_param[key.index] | S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1);
872
873 if (HAS_GS) {
874 /* GS requirement. */
875 if (GFX_VERSION <= GFX8 &&
876 SI_GS_PER_ES / primgroup_size >= sctx->screen->gs_table_depth - 3)
877 ia_multi_vgt_param |= S_028AA8_PARTIAL_ES_WAVE_ON(1);
878
879 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
880 * The hw doc says all multi-SE chips are affected, but Vulkan
881 * only applies it to Hawaii. Do what Vulkan does.
882 */
883 if (GFX_VERSION == GFX7 &&
884 sctx->family == CHIP_HAWAII && G_028AA8_SWITCH_ON_EOI(ia_multi_vgt_param) &&
885 num_instanced_prims_less_than<IS_DRAW_VERTEX_STATE>(indirect, prim, min_vertex_count,
886 instance_count, 2, sctx->patch_vertices)) {
887 /* The cache flushes should have been emitted already. */
888 assert(sctx->flags == 0);
889 sctx->flags = SI_CONTEXT_VGT_FLUSH;
890 si_emit_cache_flush_direct(sctx);
891 }
892 }
893
894 return ia_multi_vgt_param;
895 }
896
897 /* rast_prim is the primitive type after GS. */
898 template<amd_gfx_level GFX_VERSION, si_has_gs HAS_GS, si_has_ngg NGG> ALWAYS_INLINE
si_emit_rasterizer_prim_state(struct si_context * sctx)899 static void si_emit_rasterizer_prim_state(struct si_context *sctx)
900 {
901 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
902
903 radeon_begin(cs);
904
905 if (unlikely(si_is_line_stipple_enabled(sctx))) {
906 /* For lines, reset the stipple pattern at each primitive. Otherwise,
907 * reset the stipple pattern at each packet (line strips, line loops).
908 */
909 enum mesa_prim rast_prim = sctx->current_rast_prim;
910 bool reset_per_prim = rast_prim == MESA_PRIM_LINES ||
911 rast_prim == MESA_PRIM_LINES_ADJACENCY;
912 /* 0 = no reset, 1 = reset per prim, 2 = reset per packet */
913 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
914
915 radeon_opt_set_context_reg(sctx, R_028A0C_PA_SC_LINE_STIPPLE,
916 SI_TRACKED_PA_SC_LINE_STIPPLE,
917 rs->pa_sc_line_stipple |
918 S_028A0C_AUTO_RESET_CNTL(reset_per_prim ? 1 : 2));
919 }
920
921 if (NGG || HAS_GS) {
922 if (GFX_VERSION >= GFX11) {
923 radeon_opt_set_uconfig_reg(sctx, R_030998_VGT_GS_OUT_PRIM_TYPE,
924 SI_TRACKED_VGT_GS_OUT_PRIM_TYPE_UCONFIG, sctx->gs_out_prim);
925 } else {
926 radeon_opt_set_context_reg(sctx, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
927 SI_TRACKED_VGT_GS_OUT_PRIM_TYPE, sctx->gs_out_prim);
928 }
929 }
930
931 if (GFX_VERSION == GFX9)
932 radeon_end_update_context_roll(sctx);
933 else
934 radeon_end();
935 }
936
937 template <amd_gfx_level GFX_VERSION, si_has_tess HAS_TESS, si_has_gs HAS_GS, si_has_ngg NGG,
938 si_is_draw_vertex_state IS_DRAW_VERTEX_STATE, si_has_sh_pairs_packed HAS_SH_PAIRS_PACKED> ALWAYS_INLINE
si_emit_vs_state(struct si_context * sctx,unsigned index_size)939 static void si_emit_vs_state(struct si_context *sctx, unsigned index_size)
940 {
941 if (!IS_DRAW_VERTEX_STATE && sctx->num_vs_blit_sgprs) {
942 /* Re-emit the state after we leave u_blitter. */
943 sctx->last_vs_state = ~0;
944 sctx->last_gs_state = ~0;
945 return;
946 }
947
948 unsigned vs_state = sctx->current_vs_state; /* all VS bits including LS bits */
949 unsigned gs_state = sctx->current_gs_state; /* only GS and NGG bits; VS bits will be copied here */
950
951 if (sctx->shader.vs.cso->info.uses_base_vertex && index_size)
952 vs_state |= ENCODE_FIELD(VS_STATE_INDEXED, 1);
953
954 /* Copy all state bits from vs_state to gs_state except the LS bits. */
955 gs_state |= vs_state &
956 CLEAR_FIELD(VS_STATE_TCS_OUT_PATCH0_OFFSET) &
957 CLEAR_FIELD(VS_STATE_LS_OUT_VERTEX_SIZE);
958
959 if (vs_state != sctx->last_vs_state ||
960 ((HAS_GS || NGG) && gs_state != sctx->last_gs_state)) {
961 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
962
963 /* These are all constant expressions. */
964 unsigned vs_base = si_get_user_data_base(GFX_VERSION, HAS_TESS, HAS_GS, NGG,
965 PIPE_SHADER_VERTEX);
966 unsigned tes_base = si_get_user_data_base(GFX_VERSION, HAS_TESS, HAS_GS, NGG,
967 PIPE_SHADER_TESS_EVAL);
968 unsigned gs_base = si_get_user_data_base(GFX_VERSION, HAS_TESS, HAS_GS, NGG,
969 PIPE_SHADER_GEOMETRY);
970 unsigned gs_copy_base = R_00B130_SPI_SHADER_USER_DATA_VS_0;
971
972 radeon_begin(cs);
973 if (HAS_GS) {
974 radeon_set_or_push_gfx_sh_reg(vs_base + SI_SGPR_VS_STATE_BITS * 4, vs_state);
975
976 /* GS always uses the state bits for emulating VGT_ESGS_RING_ITEMSIZE on Gfx9
977 * (via nir_load_esgs_vertex_stride_amd) and for emulating GS pipeline statistics
978 * on gfx10.x. NGG GS also has lots of states in there.
979 */
980 if (GFX_VERSION >= GFX9)
981 radeon_set_or_push_gfx_sh_reg(gs_base + SI_SGPR_VS_STATE_BITS * 4, gs_state);
982
983 /* The GS copy shader (for legacy GS) always uses the state bits. */
984 if (!NGG)
985 radeon_set_or_push_gfx_sh_reg(gs_copy_base + SI_SGPR_VS_STATE_BITS * 4, gs_state);
986 } else if (HAS_TESS) {
987 radeon_set_or_push_gfx_sh_reg(vs_base + SI_SGPR_VS_STATE_BITS * 4, vs_state);
988 radeon_set_or_push_gfx_sh_reg(tes_base + SI_SGPR_VS_STATE_BITS * 4, NGG ? gs_state : vs_state);
989 } else {
990 radeon_set_or_push_gfx_sh_reg(vs_base + SI_SGPR_VS_STATE_BITS * 4, NGG ? gs_state : vs_state);
991 }
992 radeon_end();
993
994 sctx->last_vs_state = vs_state;
995 if (HAS_GS || NGG)
996 sctx->last_gs_state = gs_state;
997 }
998 }
999
1000 template <amd_gfx_level GFX_VERSION> ALWAYS_INLINE
si_prim_restart_index_changed(struct si_context * sctx,unsigned index_size,bool primitive_restart,unsigned restart_index)1001 static bool si_prim_restart_index_changed(struct si_context *sctx, unsigned index_size,
1002 bool primitive_restart, unsigned restart_index)
1003 {
1004 if (!primitive_restart)
1005 return false;
1006
1007 if (sctx->last_restart_index == SI_RESTART_INDEX_UNKNOWN)
1008 return true;
1009
1010 /* GFX8+ only compares the index type number of bits of the restart index, so the unused bits
1011 * are "don't care".
1012 *
1013 * Summary of restart index comparator behavior:
1014 * - GFX6-7: Compare all bits.
1015 * - GFX8: Only compare index type bits.
1016 * - GFX9+: If MATCH_ALL_BITS, compare all bits, else only compare index type bits.
1017 */
1018 if (GFX_VERSION >= GFX8) {
1019 /* This masking eliminates no-op 0xffffffff -> 0xffff restart index changes that cause
1020 * unnecessary context rolls when switching the index type.
1021 */
1022 unsigned index_mask = BITFIELD_MASK(index_size * 8);
1023 return (restart_index & index_mask) != (sctx->last_restart_index & index_mask);
1024 } else {
1025 return restart_index != sctx->last_restart_index;
1026 }
1027 }
1028
1029 template <amd_gfx_level GFX_VERSION, si_has_tess HAS_TESS, si_has_gs HAS_GS,
1030 si_is_draw_vertex_state IS_DRAW_VERTEX_STATE> ALWAYS_INLINE
si_emit_ia_multi_vgt_param(struct si_context * sctx,const struct pipe_draw_indirect_info * indirect,enum mesa_prim prim,unsigned instance_count,bool primitive_restart,unsigned min_vertex_count)1031 static void si_emit_ia_multi_vgt_param(struct si_context *sctx,
1032 const struct pipe_draw_indirect_info *indirect,
1033 enum mesa_prim prim, unsigned instance_count,
1034 bool primitive_restart, unsigned min_vertex_count)
1035 {
1036 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
1037 unsigned ia_multi_vgt_param;
1038
1039 ia_multi_vgt_param =
1040 si_get_ia_multi_vgt_param<GFX_VERSION, HAS_TESS, HAS_GS, IS_DRAW_VERTEX_STATE>
1041 (sctx, indirect, prim, instance_count, primitive_restart, min_vertex_count);
1042
1043 radeon_begin(cs);
1044 if (GFX_VERSION == GFX9) {
1045 /* Workaround for SpecviewPerf13 Catia hang on GFX9. */
1046 if (prim != sctx->last_prim)
1047 BITSET_CLEAR(sctx->tracked_regs.reg_saved_mask, SI_TRACKED_IA_MULTI_VGT_PARAM_UCONFIG);
1048
1049 radeon_opt_set_uconfig_reg_idx(sctx, GFX_VERSION, R_030960_IA_MULTI_VGT_PARAM,
1050 SI_TRACKED_IA_MULTI_VGT_PARAM_UCONFIG,
1051 4, ia_multi_vgt_param);
1052 } else if (GFX_VERSION >= GFX7) {
1053 radeon_opt_set_context_reg_idx(sctx, R_028AA8_IA_MULTI_VGT_PARAM,
1054 SI_TRACKED_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
1055 } else {
1056 radeon_opt_set_context_reg(sctx, R_028AA8_IA_MULTI_VGT_PARAM,
1057 SI_TRACKED_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
1058 }
1059 radeon_end();
1060 }
1061
1062 template <amd_gfx_level GFX_VERSION, si_has_tess HAS_TESS, si_has_gs HAS_GS, si_has_ngg NGG,
1063 si_is_draw_vertex_state IS_DRAW_VERTEX_STATE> ALWAYS_INLINE
si_emit_draw_registers(struct si_context * sctx,const struct pipe_draw_indirect_info * indirect,enum mesa_prim prim,unsigned index_size,unsigned instance_count,bool primitive_restart,unsigned restart_index,unsigned min_vertex_count)1064 static void si_emit_draw_registers(struct si_context *sctx,
1065 const struct pipe_draw_indirect_info *indirect,
1066 enum mesa_prim prim, unsigned index_size,
1067 unsigned instance_count, bool primitive_restart,
1068 unsigned restart_index, unsigned min_vertex_count)
1069 {
1070 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
1071
1072 if (GFX_VERSION <= GFX9) {
1073 si_emit_ia_multi_vgt_param<GFX_VERSION, HAS_TESS, HAS_GS, IS_DRAW_VERTEX_STATE>
1074 (sctx, indirect, prim, instance_count, primitive_restart, min_vertex_count);
1075 }
1076
1077 radeon_begin(cs);
1078
1079 if (prim != sctx->last_prim) {
1080 unsigned vgt_prim = HAS_TESS ? V_008958_DI_PT_PATCH : si_conv_pipe_prim(prim);
1081
1082 if (GFX_VERSION >= GFX10)
1083 radeon_set_uconfig_reg(R_030908_VGT_PRIMITIVE_TYPE, vgt_prim);
1084 else if (GFX_VERSION >= GFX7)
1085 radeon_set_uconfig_reg_idx(sctx->screen, GFX_VERSION, R_030908_VGT_PRIMITIVE_TYPE, 1, vgt_prim);
1086 else
1087 radeon_set_config_reg(R_008958_VGT_PRIMITIVE_TYPE, vgt_prim);
1088
1089 sctx->last_prim = prim;
1090 }
1091
1092 /* Primitive restart. */
1093 if (GFX_VERSION >= GFX11) {
1094 /* GFX11+ can ignore primitive restart for non-indexed draws because it has no effect.
1095 * (it's disabled for non-indexed draws by setting DISABLE_FOR_AUTO_INDEX in the preamble)
1096 */
1097 if (index_size) {
1098 if (primitive_restart != sctx->last_primitive_restart_en) {
1099 radeon_set_uconfig_reg(R_03092C_GE_MULTI_PRIM_IB_RESET_EN,
1100 S_03092C_RESET_EN(primitive_restart) |
1101 /* This disables primitive restart for non-indexed draws.
1102 * By keeping this set, we don't have to unset RESET_EN
1103 * for non-indexed draws. */
1104 S_03092C_DISABLE_FOR_AUTO_INDEX(1));
1105 sctx->last_primitive_restart_en = primitive_restart;
1106 }
1107 if (si_prim_restart_index_changed<GFX_VERSION>(sctx, index_size, primitive_restart,
1108 restart_index)) {
1109 radeon_set_context_reg(R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, restart_index);
1110 sctx->last_restart_index = restart_index;
1111 }
1112 }
1113 } else {
1114 if (primitive_restart != sctx->last_primitive_restart_en) {
1115 if (GFX_VERSION >= GFX9)
1116 radeon_set_uconfig_reg(R_03092C_VGT_MULTI_PRIM_IB_RESET_EN, primitive_restart);
1117 else
1118 radeon_set_context_reg(R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, primitive_restart);
1119 sctx->last_primitive_restart_en = primitive_restart;
1120 }
1121 if (si_prim_restart_index_changed<GFX_VERSION>(sctx, index_size, primitive_restart,
1122 restart_index)) {
1123 radeon_set_context_reg(R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, restart_index);
1124 sctx->last_restart_index = restart_index;
1125 if (GFX_VERSION == GFX9)
1126 sctx->context_roll = true;
1127 }
1128 }
1129 radeon_end();
1130 }
1131
1132 static ALWAYS_INLINE void
gfx11_emit_buffered_sh_regs_inline(struct si_context * sctx,unsigned * num_regs,struct gfx11_reg_pair * reg_pairs)1133 gfx11_emit_buffered_sh_regs_inline(struct si_context *sctx, unsigned *num_regs,
1134 struct gfx11_reg_pair *reg_pairs)
1135 {
1136 unsigned reg_count = *num_regs;
1137
1138 if (!reg_count)
1139 return;
1140
1141 *num_regs = 0;
1142
1143 /* If there is only one register, we can't use the packed SET packet. */
1144 if (reg_count == 1) {
1145 radeon_begin(&sctx->gfx_cs);
1146 radeon_emit(PKT3(PKT3_SET_SH_REG, 1, 0));
1147 radeon_emit(reg_pairs[0].reg_offset[0]);
1148 radeon_emit(reg_pairs[0].reg_value[0]);
1149 radeon_end();
1150 return;
1151 }
1152
1153 unsigned packet = reg_count <= 14 ? PKT3_SET_SH_REG_PAIRS_PACKED_N :
1154 PKT3_SET_SH_REG_PAIRS_PACKED;
1155 unsigned padded_reg_count = align(reg_count, 2);
1156
1157 radeon_begin(&sctx->gfx_cs);
1158 radeon_emit(PKT3(packet, (padded_reg_count / 2) * 3, 0) | PKT3_RESET_FILTER_CAM_S(1));
1159 radeon_emit(padded_reg_count);
1160 radeon_emit_array(reg_pairs, (reg_count / 2) * 3);
1161
1162 if (reg_count % 2 == 1) {
1163 unsigned i = reg_count / 2;
1164
1165 /* Pad the packet by setting the first register again at the end because the register
1166 * count must be even and 2 consecutive offsets must not be equal.
1167 */
1168 radeon_emit(reg_pairs[i].reg_offset[0] | ((uint32_t)reg_pairs[0].reg_offset[0] << 16));
1169 radeon_emit(reg_pairs[i].reg_value[0]);
1170 radeon_emit(reg_pairs[0].reg_value[0]);
1171 }
1172 radeon_end();
1173 }
1174
1175 #if GFX_VER == 6 /* declare this function only once because there is only one variant. */
1176
si_emit_buffered_compute_sh_regs(struct si_context * sctx)1177 void si_emit_buffered_compute_sh_regs(struct si_context *sctx)
1178 {
1179 gfx11_emit_buffered_sh_regs_inline(sctx, &sctx->num_buffered_compute_sh_regs,
1180 sctx->gfx11.buffered_compute_sh_regs);
1181 }
1182
1183 #endif
1184
1185 #define EMIT_SQTT_END_DRAW \
1186 do { \
1187 if (GFX_VERSION >= GFX9 && unlikely(sctx->sqtt_enabled)) { \
1188 radeon_begin(&sctx->gfx_cs); \
1189 radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); \
1190 radeon_emit(EVENT_TYPE(V_028A90_THREAD_TRACE_MARKER) | EVENT_INDEX(0)); \
1191 radeon_end(); \
1192 } \
1193 } while (0)
1194
1195 template <amd_gfx_level GFX_VERSION, si_has_tess HAS_TESS, si_has_gs HAS_GS, si_has_ngg NGG,
1196 si_is_draw_vertex_state IS_DRAW_VERTEX_STATE, si_has_sh_pairs_packed HAS_SH_PAIRS_PACKED> ALWAYS_INLINE
si_emit_draw_packets(struct si_context * sctx,const struct pipe_draw_info * info,unsigned drawid_base,const struct pipe_draw_indirect_info * indirect,const struct pipe_draw_start_count_bias * draws,unsigned num_draws,struct pipe_resource * indexbuf,unsigned index_size,unsigned index_offset,unsigned instance_count)1197 static void si_emit_draw_packets(struct si_context *sctx, const struct pipe_draw_info *info,
1198 unsigned drawid_base,
1199 const struct pipe_draw_indirect_info *indirect,
1200 const struct pipe_draw_start_count_bias *draws,
1201 unsigned num_draws,
1202 struct pipe_resource *indexbuf, unsigned index_size,
1203 unsigned index_offset, unsigned instance_count)
1204 {
1205 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
1206
1207 if (unlikely(sctx->sqtt_enabled)) {
1208 si_sqtt_write_event_marker(sctx, &sctx->gfx_cs, sctx->sqtt_next_event,
1209 UINT_MAX, UINT_MAX, UINT_MAX);
1210 }
1211
1212 uint32_t use_opaque = 0;
1213
1214 if (!IS_DRAW_VERTEX_STATE && indirect && indirect->count_from_stream_output) {
1215 struct si_streamout_target *t = (struct si_streamout_target *)indirect->count_from_stream_output;
1216
1217 radeon_begin(cs);
1218 radeon_set_context_reg(R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE, t->stride_in_dw);
1219 radeon_end();
1220
1221 if (GFX_VERSION >= GFX9) {
1222 /* Use PKT3_LOAD_CONTEXT_REG_INDEX instead of si_cp_copy_data to support state shadowing. */
1223 uint64_t va = t->buf_filled_size->gpu_address + t->buf_filled_size_offset;
1224
1225 radeon_begin(cs);
1226
1227 radeon_emit(PKT3(PKT3_LOAD_CONTEXT_REG_INDEX, 3, 0));
1228 radeon_emit(va);
1229 radeon_emit(va >> 32);
1230 radeon_emit((R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE - SI_CONTEXT_REG_OFFSET) >> 2);
1231 radeon_emit(1);
1232
1233 radeon_end();
1234 } else {
1235 si_cp_copy_data(sctx, &sctx->gfx_cs, COPY_DATA_REG, NULL,
1236 R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2, COPY_DATA_SRC_MEM,
1237 t->buf_filled_size, t->buf_filled_size_offset);
1238 }
1239 use_opaque = S_0287F0_USE_OPAQUE(1);
1240 indirect = NULL;
1241 }
1242
1243 uint32_t index_max_size = 0;
1244 uint64_t index_va = 0;
1245 bool disable_instance_packing = false;
1246
1247 radeon_begin(cs);
1248
1249 if (GFX_VERSION == GFX10_3) {
1250 /* Workaround for incorrect stats with adjacent primitive types
1251 * (see PAL's waDisableInstancePacking).
1252 */
1253 if (sctx->num_pipeline_stat_queries &&
1254 sctx->shader.gs.cso == NULL &&
1255 (instance_count > 1 || indirect) &&
1256 (1 << info->mode) & (1 << MESA_PRIM_LINES_ADJACENCY |
1257 1 << MESA_PRIM_LINE_STRIP_ADJACENCY |
1258 1 << MESA_PRIM_TRIANGLES_ADJACENCY |
1259 1 << MESA_PRIM_TRIANGLE_STRIP_ADJACENCY)) {
1260 disable_instance_packing = true;
1261 }
1262 }
1263
1264 /* draw packet */
1265 if (index_size) {
1266 /* Register shadowing doesn't shadow INDEX_TYPE. */
1267 if (index_size != sctx->last_index_size ||
1268 (GFX_VERSION == GFX10_3 && disable_instance_packing != sctx->disable_instance_packing)) {
1269 unsigned index_type;
1270
1271 /* Index type computation. When we look at how we need to translate index_size,
1272 * we can see that we just need 2 shifts to get the hw value.
1273 *
1274 * 1 = 001b --> 10b = 2
1275 * 2 = 010b --> 00b = 0
1276 * 4 = 100b --> 01b = 1
1277 */
1278 index_type = (((index_size >> 2) | (index_size << 1)) & 0x3) |
1279 S_028A7C_DISABLE_INSTANCE_PACKING(disable_instance_packing);
1280
1281 if (GFX_VERSION <= GFX7 && UTIL_ARCH_BIG_ENDIAN) {
1282 /* GFX7 doesn't support ubyte indices. */
1283 index_type |= index_size == 2 ? V_028A7C_VGT_DMA_SWAP_16_BIT
1284 : V_028A7C_VGT_DMA_SWAP_32_BIT;
1285 }
1286
1287 if (GFX_VERSION >= GFX9) {
1288 radeon_set_uconfig_reg_idx(sctx->screen, GFX_VERSION,
1289 R_03090C_VGT_INDEX_TYPE, 2, index_type);
1290 } else {
1291 radeon_emit(PKT3(PKT3_INDEX_TYPE, 0, 0));
1292 radeon_emit(index_type);
1293 }
1294
1295 sctx->last_index_size = index_size;
1296 if (GFX_VERSION == GFX10_3)
1297 sctx->disable_instance_packing = disable_instance_packing;
1298 }
1299
1300 index_max_size = (indexbuf->width0 - index_offset) >> util_logbase2(index_size);
1301 /* Skip draw calls with 0-sized index buffers.
1302 * They cause a hang on some chips, like Navi10-14.
1303 */
1304 if (!index_max_size) {
1305 radeon_end();
1306 return;
1307 }
1308
1309 index_va = si_resource(indexbuf)->gpu_address + index_offset;
1310
1311 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, si_resource(indexbuf),
1312 RADEON_USAGE_READ | RADEON_PRIO_INDEX_BUFFER);
1313 } else {
1314 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
1315 * so the state must be re-emitted before the next indexed draw.
1316 */
1317 if (GFX_VERSION >= GFX7)
1318 sctx->last_index_size = -1;
1319 if (GFX_VERSION == GFX10_3 && disable_instance_packing != sctx->disable_instance_packing) {
1320 radeon_set_uconfig_reg_idx(sctx->screen, GFX_VERSION,
1321 R_03090C_VGT_INDEX_TYPE, 2,
1322 S_028A7C_DISABLE_INSTANCE_PACKING(disable_instance_packing));
1323 sctx->disable_instance_packing = disable_instance_packing;
1324 }
1325 }
1326
1327 unsigned sh_base_reg = si_get_user_data_base(GFX_VERSION, HAS_TESS, HAS_GS, NGG,
1328 PIPE_SHADER_VERTEX);
1329 bool render_cond_bit = sctx->render_cond_enabled;
1330 unsigned tracked_base_vertex_reg;
1331
1332 if (HAS_TESS)
1333 tracked_base_vertex_reg = SI_TRACKED_SPI_SHADER_USER_DATA_LS__BASE_VERTEX;
1334 else if (HAS_GS || NGG)
1335 tracked_base_vertex_reg = SI_TRACKED_SPI_SHADER_USER_DATA_ES__BASE_VERTEX;
1336 else
1337 tracked_base_vertex_reg = SI_TRACKED_SPI_SHADER_USER_DATA_VS__BASE_VERTEX;
1338
1339 if (!IS_DRAW_VERTEX_STATE && indirect) {
1340 assert(num_draws == 1);
1341 uint64_t indirect_va = si_resource(indirect->buffer)->gpu_address;
1342
1343 assert(indirect_va % 8 == 0);
1344
1345 if (HAS_SH_PAIRS_PACKED) {
1346 radeon_end();
1347 gfx11_emit_buffered_sh_regs_inline(sctx, &sctx->num_buffered_gfx_sh_regs,
1348 sctx->gfx11.buffered_gfx_sh_regs);
1349 radeon_begin_again(cs);
1350 }
1351
1352 /* Invalidate tracked draw constants because DrawIndirect overwrites them. */
1353 BITSET_CLEAR(sctx->tracked_regs.reg_saved_mask, tracked_base_vertex_reg); /* BaseVertex */
1354 BITSET_CLEAR(sctx->tracked_regs.reg_saved_mask, tracked_base_vertex_reg + 1); /* DrawID */
1355 BITSET_CLEAR(sctx->tracked_regs.reg_saved_mask, tracked_base_vertex_reg + 2); /* StartInstance */
1356 sctx->last_instance_count = SI_INSTANCE_COUNT_UNKNOWN;
1357
1358 radeon_emit(PKT3(PKT3_SET_BASE, 2, 0));
1359 radeon_emit(1);
1360 radeon_emit(indirect_va);
1361 radeon_emit(indirect_va >> 32);
1362
1363 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, si_resource(indirect->buffer),
1364 RADEON_USAGE_READ | RADEON_PRIO_DRAW_INDIRECT);
1365
1366 unsigned di_src_sel = index_size ? V_0287F0_DI_SRC_SEL_DMA : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
1367
1368 assert(indirect->offset % 4 == 0);
1369
1370 if (index_size) {
1371 radeon_emit(PKT3(PKT3_INDEX_BASE, 1, 0));
1372 radeon_emit(index_va);
1373 radeon_emit(index_va >> 32);
1374
1375 radeon_emit(PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1376 radeon_emit(index_max_size);
1377 }
1378
1379 if (!sctx->screen->has_draw_indirect_multi) {
1380 radeon_emit(PKT3(index_size ? PKT3_DRAW_INDEX_INDIRECT : PKT3_DRAW_INDIRECT, 3,
1381 render_cond_bit));
1382 radeon_emit(indirect->offset);
1383 radeon_emit((sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
1384 radeon_emit((sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
1385 radeon_emit(di_src_sel);
1386 } else {
1387 uint64_t count_va = 0;
1388
1389 if (indirect->indirect_draw_count) {
1390 struct si_resource *params_buf = si_resource(indirect->indirect_draw_count);
1391
1392 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, params_buf,
1393 RADEON_USAGE_READ | RADEON_PRIO_DRAW_INDIRECT);
1394
1395 count_va = params_buf->gpu_address + indirect->indirect_draw_count_offset;
1396 }
1397
1398 radeon_emit(PKT3(index_size ? PKT3_DRAW_INDEX_INDIRECT_MULTI : PKT3_DRAW_INDIRECT_MULTI, 8,
1399 render_cond_bit));
1400 radeon_emit(indirect->offset);
1401 radeon_emit((sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
1402 radeon_emit((sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
1403 radeon_emit(((sh_base_reg + SI_SGPR_DRAWID * 4 - SI_SH_REG_OFFSET) >> 2) |
1404 S_2C3_DRAW_INDEX_ENABLE(sctx->shader.vs.cso->info.uses_drawid) |
1405 S_2C3_COUNT_INDIRECT_ENABLE(!!indirect->indirect_draw_count));
1406 radeon_emit(indirect->draw_count);
1407 radeon_emit(count_va);
1408 radeon_emit(count_va >> 32);
1409 radeon_emit(indirect->stride);
1410 radeon_emit(di_src_sel);
1411 }
1412 } else {
1413 if (sctx->last_instance_count == SI_INSTANCE_COUNT_UNKNOWN ||
1414 sctx->last_instance_count != instance_count) {
1415 radeon_emit(PKT3(PKT3_NUM_INSTANCES, 0, 0));
1416 radeon_emit(instance_count);
1417 sctx->last_instance_count = instance_count;
1418 }
1419
1420 /* Base vertex and start instance. */
1421 int base_vertex = index_size ? draws[0].index_bias : draws[0].start;
1422
1423 bool set_draw_id = !IS_DRAW_VERTEX_STATE && sctx->vs_uses_draw_id;
1424 bool set_base_instance = sctx->vs_uses_base_instance;
1425 bool is_blit = !IS_DRAW_VERTEX_STATE && sctx->num_vs_blit_sgprs;
1426
1427 if (!is_blit) {
1428 /* Prefer SET_SH_REG_PAIRS_PACKED* on Gfx11+. */
1429 if (HAS_SH_PAIRS_PACKED) {
1430 gfx11_opt_push_gfx_sh_reg(sh_base_reg + SI_SGPR_BASE_VERTEX * 4,
1431 tracked_base_vertex_reg, base_vertex);
1432 if (set_draw_id) {
1433 gfx11_opt_push_gfx_sh_reg(sh_base_reg + SI_SGPR_DRAWID * 4,
1434 tracked_base_vertex_reg + 1, drawid_base);
1435 }
1436 if (set_base_instance) {
1437 gfx11_opt_push_gfx_sh_reg(sh_base_reg + SI_SGPR_START_INSTANCE * 4,
1438 tracked_base_vertex_reg + 2, info->start_instance);
1439 }
1440 } else {
1441 if (set_base_instance) {
1442 radeon_opt_set_sh_reg3(sctx, sh_base_reg + SI_SGPR_BASE_VERTEX * 4,
1443 tracked_base_vertex_reg, base_vertex, drawid_base,
1444 info->start_instance);
1445 } else if (set_draw_id) {
1446 radeon_opt_set_sh_reg2(sctx, sh_base_reg + SI_SGPR_BASE_VERTEX * 4,
1447 tracked_base_vertex_reg, base_vertex, drawid_base);
1448 } else {
1449 radeon_opt_set_sh_reg(sctx, sh_base_reg + SI_SGPR_BASE_VERTEX * 4,
1450 tracked_base_vertex_reg, base_vertex);
1451 }
1452 }
1453 }
1454
1455 if (HAS_SH_PAIRS_PACKED) {
1456 radeon_end();
1457 gfx11_emit_buffered_sh_regs_inline(sctx, &sctx->num_buffered_gfx_sh_regs,
1458 sctx->gfx11.buffered_gfx_sh_regs);
1459 radeon_begin_again(cs);
1460 }
1461
1462 /* Blit SGPRs must be set after gfx11_emit_buffered_sh_regs_inline because they can
1463 * overwrite them.
1464 */
1465 if (is_blit) {
1466 /* Re-emit draw constants after we leave u_blitter. */
1467 BITSET_CLEAR(sctx->tracked_regs.reg_saved_mask, tracked_base_vertex_reg); /* BaseVertex */
1468 BITSET_CLEAR(sctx->tracked_regs.reg_saved_mask, tracked_base_vertex_reg + 1); /* DrawID */
1469 BITSET_CLEAR(sctx->tracked_regs.reg_saved_mask, tracked_base_vertex_reg + 2); /* StartInstance */
1470
1471 /* Blit VS doesn't use BASE_VERTEX, START_INSTANCE, and DRAWID. */
1472 radeon_set_sh_reg_seq(sh_base_reg + SI_SGPR_VS_BLIT_DATA * 4, sctx->num_vs_blit_sgprs);
1473 radeon_emit_array(sctx->vs_blit_sh_data, sctx->num_vs_blit_sgprs);
1474 }
1475
1476 /* Don't update draw_id in the following code if it doesn't increment. */
1477 bool increment_draw_id = !IS_DRAW_VERTEX_STATE && num_draws > 1 &&
1478 set_draw_id && info->increment_draw_id;
1479
1480 if (index_size) {
1481 /* NOT_EOP allows merging multiple draws into 1 wave, but only user VGPRs
1482 * can be changed between draws, and GS fast launch must be disabled.
1483 * NOT_EOP doesn't work on gfx9 and older.
1484 *
1485 * Instead of doing this, which evaluates the case conditions repeatedly:
1486 * for (all draws) {
1487 * if (case1);
1488 * else;
1489 * }
1490 *
1491 * Use this structuring to evaluate the case conditions once:
1492 * if (case1) for (all draws);
1493 * else for (all draws);
1494 *
1495 */
1496 bool index_bias_varies = !IS_DRAW_VERTEX_STATE && num_draws > 1 &&
1497 info->index_bias_varies;
1498
1499 if (increment_draw_id) {
1500 if (index_bias_varies) {
1501 for (unsigned i = 0; i < num_draws; i++) {
1502 uint64_t va = index_va + draws[i].start * index_size;
1503
1504 if (i > 0) {
1505 radeon_set_sh_reg_seq(sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 2);
1506 radeon_emit(draws[i].index_bias);
1507 radeon_emit(drawid_base + i);
1508 }
1509
1510 radeon_emit(PKT3(PKT3_DRAW_INDEX_2, 4, render_cond_bit));
1511 radeon_emit(index_max_size);
1512 radeon_emit(va);
1513 radeon_emit(va >> 32);
1514 radeon_emit(draws[i].count);
1515 radeon_emit(V_0287F0_DI_SRC_SEL_DMA); /* NOT_EOP disabled */
1516 }
1517 if (num_draws > 1) {
1518 BITSET_CLEAR(sctx->tracked_regs.reg_saved_mask, tracked_base_vertex_reg); /* BaseVertex */
1519 BITSET_CLEAR(sctx->tracked_regs.reg_saved_mask, tracked_base_vertex_reg + 1); /* DrawID */
1520 }
1521 } else {
1522 /* Only DrawID varies. */
1523 for (unsigned i = 0; i < num_draws; i++) {
1524 uint64_t va = index_va + draws[i].start * index_size;
1525
1526 if (i > 0)
1527 radeon_set_sh_reg(sh_base_reg + SI_SGPR_DRAWID * 4, drawid_base + i);
1528
1529 radeon_emit(PKT3(PKT3_DRAW_INDEX_2, 4, render_cond_bit));
1530 radeon_emit(index_max_size);
1531 radeon_emit(va);
1532 radeon_emit(va >> 32);
1533 radeon_emit(draws[i].count);
1534 radeon_emit(V_0287F0_DI_SRC_SEL_DMA); /* NOT_EOP disabled */
1535 }
1536 if (num_draws > 1) {
1537 BITSET_CLEAR(sctx->tracked_regs.reg_saved_mask, tracked_base_vertex_reg + 1); /* DrawID */
1538 }
1539 }
1540 } else {
1541 if (index_bias_varies) {
1542 /* Only BaseVertex varies. */
1543 for (unsigned i = 0; i < num_draws; i++) {
1544 uint64_t va = index_va + draws[i].start * index_size;
1545
1546 if (i > 0)
1547 radeon_set_sh_reg(sh_base_reg + SI_SGPR_BASE_VERTEX * 4, draws[i].index_bias);
1548
1549 radeon_emit(PKT3(PKT3_DRAW_INDEX_2, 4, render_cond_bit));
1550 radeon_emit(index_max_size);
1551 radeon_emit(va);
1552 radeon_emit(va >> 32);
1553 radeon_emit(draws[i].count);
1554 radeon_emit(V_0287F0_DI_SRC_SEL_DMA); /* NOT_EOP disabled */
1555 }
1556 if (num_draws > 1) {
1557 BITSET_CLEAR(sctx->tracked_regs.reg_saved_mask, tracked_base_vertex_reg); /* BaseVertex */
1558 }
1559 } else {
1560 /* DrawID and BaseVertex are constant. */
1561 if (GFX_VERSION == GFX10) {
1562 /* GFX10 has a bug that consecutive draw packets with NOT_EOP must not have
1563 * count == 0 in the last draw (which doesn't set NOT_EOP).
1564 *
1565 * So remove all trailing draws with count == 0.
1566 */
1567 while (num_draws > 1 && !draws[num_draws - 1].count)
1568 num_draws--;
1569 }
1570
1571 for (unsigned i = 0; i < num_draws; i++) {
1572 uint64_t va = index_va + draws[i].start * index_size;
1573
1574 radeon_emit(PKT3(PKT3_DRAW_INDEX_2, 4, render_cond_bit));
1575 radeon_emit(index_max_size);
1576 radeon_emit(va);
1577 radeon_emit(va >> 32);
1578 radeon_emit(draws[i].count);
1579 radeon_emit(V_0287F0_DI_SRC_SEL_DMA |
1580 S_0287F0_NOT_EOP(GFX_VERSION >= GFX10 && i < num_draws - 1));
1581 }
1582 }
1583 }
1584 } else {
1585 if (increment_draw_id) {
1586 for (unsigned i = 0; i < num_draws; i++) {
1587 if (i > 0) {
1588 unsigned draw_id = drawid_base + i;
1589
1590 radeon_set_sh_reg_seq(sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 2);
1591 radeon_emit(draws[i].start);
1592 radeon_emit(draw_id);
1593 }
1594
1595 radeon_emit(PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit));
1596 radeon_emit(draws[i].count);
1597 radeon_emit(V_0287F0_DI_SRC_SEL_AUTO_INDEX | use_opaque);
1598 }
1599 if (num_draws > 1 && (IS_DRAW_VERTEX_STATE || !sctx->num_vs_blit_sgprs)) {
1600 BITSET_CLEAR(sctx->tracked_regs.reg_saved_mask, tracked_base_vertex_reg); /* BaseVertex */
1601 BITSET_CLEAR(sctx->tracked_regs.reg_saved_mask, tracked_base_vertex_reg + 1); /* DrawID */
1602 }
1603 } else {
1604 for (unsigned i = 0; i < num_draws; i++) {
1605 if (i > 0)
1606 radeon_set_sh_reg(sh_base_reg + SI_SGPR_BASE_VERTEX * 4, draws[i].start);
1607
1608 radeon_emit(PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit));
1609 radeon_emit(draws[i].count);
1610 radeon_emit(V_0287F0_DI_SRC_SEL_AUTO_INDEX | use_opaque);
1611 }
1612 if (num_draws > 1 && (IS_DRAW_VERTEX_STATE || !sctx->num_vs_blit_sgprs)) {
1613 BITSET_CLEAR(sctx->tracked_regs.reg_saved_mask, tracked_base_vertex_reg); /* BaseVertex */
1614 }
1615 }
1616 }
1617 }
1618 radeon_end();
1619
1620 EMIT_SQTT_END_DRAW;
1621 }
1622
1623 /* Return false if not bound. */
1624 template<amd_gfx_level GFX_VERSION>
si_set_vb_descriptor(struct si_vertex_elements * velems,struct pipe_vertex_buffer * vb,unsigned index,uint32_t * desc)1625 static void ALWAYS_INLINE si_set_vb_descriptor(struct si_vertex_elements *velems,
1626 struct pipe_vertex_buffer *vb,
1627 unsigned index, /* vertex element index */
1628 uint32_t *desc) /* where to upload descriptors */
1629 {
1630 struct si_resource *buf = si_resource(vb->buffer.resource);
1631 int64_t offset = (int64_t)((int)vb->buffer_offset) + velems->elem[index].src_offset;
1632
1633 if (!buf || offset >= buf->b.b.width0) {
1634 memset(desc, 0, 16);
1635 return;
1636 }
1637
1638 uint64_t va = buf->gpu_address + offset;
1639 unsigned stride = velems->elem[index].stride;
1640
1641 int64_t num_records = (int64_t)buf->b.b.width0 - offset;
1642 if (GFX_VERSION != GFX8 && stride) {
1643 /* Round up by rounding down and adding 1 */
1644 num_records = (num_records - velems->elem[index].format_size) / stride + 1;
1645 }
1646 assert(num_records >= 0 && num_records <= UINT_MAX);
1647
1648 desc[0] = va;
1649 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1650 desc[2] = num_records;
1651 desc[3] = velems->elem[index].rsrc_word3;
1652 }
1653
1654 #if GFX_VER == 6 /* declare this function only once because it supports all chips. */
1655
si_set_vertex_buffer_descriptor(struct si_screen * sscreen,struct si_vertex_elements * velems,struct pipe_vertex_buffer * vb,unsigned element_index,uint32_t * out)1656 void si_set_vertex_buffer_descriptor(struct si_screen *sscreen, struct si_vertex_elements *velems,
1657 struct pipe_vertex_buffer *vb, unsigned element_index,
1658 uint32_t *out)
1659 {
1660 switch (sscreen->info.gfx_level) {
1661 case GFX6:
1662 si_set_vb_descriptor<GFX6>(velems, vb, element_index, out);
1663 break;
1664 case GFX7:
1665 si_set_vb_descriptor<GFX7>(velems, vb, element_index, out);
1666 break;
1667 case GFX8:
1668 si_set_vb_descriptor<GFX8>(velems, vb, element_index, out);
1669 break;
1670 case GFX9:
1671 si_set_vb_descriptor<GFX9>(velems, vb, element_index, out);
1672 break;
1673 case GFX10:
1674 si_set_vb_descriptor<GFX10>(velems, vb, element_index, out);
1675 break;
1676 case GFX10_3:
1677 si_set_vb_descriptor<GFX10_3>(velems, vb, element_index, out);
1678 break;
1679 case GFX11:
1680 si_set_vb_descriptor<GFX11>(velems, vb, element_index, out);
1681 break;
1682 case GFX11_5:
1683 si_set_vb_descriptor<GFX11_5>(velems, vb, element_index, out);
1684 break;
1685 default:
1686 unreachable("unhandled gfx level");
1687 }
1688 }
1689
1690 #endif
1691
1692 template<util_popcnt POPCNT>
get_next_vertex_state_elem(struct pipe_vertex_state * state,uint32_t * partial_velem_mask)1693 static ALWAYS_INLINE unsigned get_next_vertex_state_elem(struct pipe_vertex_state *state,
1694 uint32_t *partial_velem_mask)
1695 {
1696 unsigned semantic_index = u_bit_scan(partial_velem_mask);
1697 assert(state->input.full_velem_mask & BITFIELD_BIT(semantic_index));
1698 /* A prefix mask of the full mask gives us the index in pipe_vertex_state. */
1699 return util_bitcount_fast<POPCNT>(state->input.full_velem_mask & BITFIELD_MASK(semantic_index));
1700 }
1701
1702 template<amd_gfx_level GFX_VERSION, si_has_tess HAS_TESS, si_has_gs HAS_GS, si_has_ngg NGG>
get_vb_descriptor_sgpr_ptr_offset(void)1703 static unsigned get_vb_descriptor_sgpr_ptr_offset(void)
1704 {
1705 /* Find the location of the VB descriptor pointer. */
1706 unsigned dw_offset = SI_VS_NUM_USER_SGPR;
1707 if (GFX_VERSION >= GFX9) {
1708 if (HAS_TESS)
1709 dw_offset = GFX9_TCS_NUM_USER_SGPR;
1710 else if (HAS_GS || NGG)
1711 dw_offset = GFX9_GS_NUM_USER_SGPR;
1712 }
1713 return dw_offset * 4;
1714 }
1715
1716 template <amd_gfx_level GFX_VERSION, si_has_tess HAS_TESS, si_has_gs HAS_GS, si_has_ngg NGG,
1717 si_is_draw_vertex_state IS_DRAW_VERTEX_STATE, si_has_sh_pairs_packed HAS_SH_PAIRS_PACKED,
1718 util_popcnt POPCNT> ALWAYS_INLINE
si_upload_and_prefetch_VB_descriptors(struct si_context * sctx,struct pipe_vertex_state * state,uint32_t partial_velem_mask)1719 static bool si_upload_and_prefetch_VB_descriptors(struct si_context *sctx,
1720 struct pipe_vertex_state *state,
1721 uint32_t partial_velem_mask)
1722 {
1723 struct si_vertex_state *vstate = (struct si_vertex_state *)state;
1724 unsigned count = IS_DRAW_VERTEX_STATE ? util_bitcount_fast<POPCNT>(partial_velem_mask) :
1725 sctx->num_vertex_elements;
1726 unsigned sh_base = si_get_user_data_base(GFX_VERSION, HAS_TESS, HAS_GS, NGG,
1727 PIPE_SHADER_VERTEX);
1728 unsigned num_vbos_in_user_sgprs = si_num_vbos_in_user_sgprs_inline(GFX_VERSION);
1729
1730 assert(count <= SI_MAX_ATTRIBS);
1731
1732 if (sctx->vertex_buffers_dirty || IS_DRAW_VERTEX_STATE) {
1733 assert(count || IS_DRAW_VERTEX_STATE);
1734
1735 struct si_vertex_elements *velems = sctx->vertex_elements;
1736 unsigned alloc_size = IS_DRAW_VERTEX_STATE ?
1737 vstate->velems.vb_desc_list_alloc_size :
1738 velems->vb_desc_list_alloc_size;
1739 uint64_t vb_descriptors_address = 0;
1740 uint32_t *ptr;
1741
1742 if (alloc_size) {
1743 unsigned offset;
1744
1745 /* Vertex buffer descriptors are the only ones which are uploaded directly
1746 * and don't go through si_upload_graphics_shader_descriptors.
1747 */
1748 u_upload_alloc(sctx->b.const_uploader, 0, alloc_size,
1749 si_optimal_tcc_alignment(sctx, alloc_size), &offset,
1750 (struct pipe_resource **)&sctx->last_const_upload_buffer, (void **)&ptr);
1751 if (!sctx->last_const_upload_buffer)
1752 return false;
1753
1754 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, sctx->last_const_upload_buffer,
1755 RADEON_USAGE_READ | RADEON_PRIO_DESCRIPTORS);
1756 vb_descriptors_address = sctx->last_const_upload_buffer->gpu_address + offset;
1757
1758 /* GFX6 doesn't support the L2 prefetch. */
1759 if (GFX_VERSION >= GFX7) {
1760 uint64_t address = sctx->last_const_upload_buffer->gpu_address + offset;
1761 si_cp_dma_prefetch_inline<GFX_VERSION>(sctx, address, alloc_size);
1762 }
1763 }
1764
1765 unsigned count_in_user_sgprs = MIN2(count, num_vbos_in_user_sgprs);
1766 unsigned i = 0;
1767
1768 if (IS_DRAW_VERTEX_STATE) {
1769 radeon_begin(&sctx->gfx_cs);
1770
1771 if (count_in_user_sgprs) {
1772 radeon_set_sh_reg_seq(sh_base + SI_SGPR_VS_VB_DESCRIPTOR_FIRST * 4, count_in_user_sgprs * 4);
1773
1774 /* the first iteration always executes */
1775 do {
1776 unsigned velem_index = get_next_vertex_state_elem<POPCNT>(state, &partial_velem_mask);
1777
1778 radeon_emit_array(&vstate->descriptors[velem_index * 4], 4);
1779 } while (++i < count_in_user_sgprs);
1780 }
1781
1782 if (partial_velem_mask) {
1783 assert(alloc_size);
1784
1785 unsigned vb_desc_offset =
1786 sh_base + get_vb_descriptor_sgpr_ptr_offset<GFX_VERSION, HAS_TESS, HAS_GS, NGG>();
1787
1788 radeon_set_or_push_gfx_sh_reg(vb_desc_offset, vb_descriptors_address);
1789
1790 /* the first iteration always executes */
1791 do {
1792 unsigned velem_index = get_next_vertex_state_elem<POPCNT>(state, &partial_velem_mask);
1793 uint32_t *desc = &ptr[(i - num_vbos_in_user_sgprs) * 4];
1794
1795 memcpy(desc, &vstate->descriptors[velem_index * 4], 16);
1796 i++;
1797 } while (partial_velem_mask);
1798 }
1799 radeon_end();
1800
1801 if (vstate->b.input.vbuffer.buffer.resource != vstate->b.input.indexbuf) {
1802 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs,
1803 si_resource(vstate->b.input.vbuffer.buffer.resource),
1804 RADEON_USAGE_READ | RADEON_PRIO_VERTEX_BUFFER);
1805 }
1806
1807 /* The next draw_vbo should recompute and rebind vertex buffer descriptors. */
1808 sctx->vertex_buffers_dirty = sctx->num_vertex_elements > 0;
1809 } else {
1810 if (count_in_user_sgprs) {
1811 radeon_begin(&sctx->gfx_cs);
1812 radeon_set_sh_reg_seq(sh_base + SI_SGPR_VS_VB_DESCRIPTOR_FIRST * 4,
1813 count_in_user_sgprs * 4);
1814
1815 /* the first iteration always executes */
1816 do {
1817 unsigned vbo_index = velems->vertex_buffer_index[i];
1818 struct pipe_vertex_buffer *vb = &sctx->vertex_buffer[vbo_index];
1819 uint32_t *desc;
1820
1821 radeon_emit_array_get_ptr(4, &desc);
1822
1823 si_set_vb_descriptor<GFX_VERSION>(velems, vb, i, desc);
1824 } while (++i < count_in_user_sgprs);
1825
1826 radeon_end();
1827 }
1828
1829 if (alloc_size) {
1830 /* the first iteration always executes */
1831 do {
1832 unsigned vbo_index = velems->vertex_buffer_index[i];
1833 struct pipe_vertex_buffer *vb = &sctx->vertex_buffer[vbo_index];
1834 uint32_t *desc = &ptr[(i - num_vbos_in_user_sgprs) * 4];
1835
1836 si_set_vb_descriptor<GFX_VERSION>(velems, vb, i, desc);
1837 } while (++i < count);
1838
1839 unsigned vb_desc_ptr_offset =
1840 sh_base + get_vb_descriptor_sgpr_ptr_offset<GFX_VERSION, HAS_TESS, HAS_GS, NGG>();
1841 radeon_begin(&sctx->gfx_cs);
1842 radeon_set_or_push_gfx_sh_reg(vb_desc_ptr_offset, vb_descriptors_address);
1843 radeon_end();
1844 }
1845
1846 sctx->vertex_buffers_dirty = false;
1847 }
1848 }
1849
1850 return true;
1851 }
1852
si_get_draw_start_count(struct si_context * sctx,const struct pipe_draw_info * info,const struct pipe_draw_indirect_info * indirect,const struct pipe_draw_start_count_bias * draws,unsigned num_draws,unsigned * start,unsigned * count)1853 static void si_get_draw_start_count(struct si_context *sctx, const struct pipe_draw_info *info,
1854 const struct pipe_draw_indirect_info *indirect,
1855 const struct pipe_draw_start_count_bias *draws,
1856 unsigned num_draws, unsigned *start, unsigned *count)
1857 {
1858 if (indirect && !indirect->count_from_stream_output) {
1859 unsigned indirect_count;
1860 struct pipe_transfer *transfer;
1861 unsigned begin, end;
1862 unsigned map_size;
1863 unsigned *data;
1864
1865 if (indirect->indirect_draw_count) {
1866 data = (unsigned*)
1867 pipe_buffer_map_range(&sctx->b, indirect->indirect_draw_count,
1868 indirect->indirect_draw_count_offset, sizeof(unsigned),
1869 PIPE_MAP_READ, &transfer);
1870
1871 indirect_count = *data;
1872
1873 pipe_buffer_unmap(&sctx->b, transfer);
1874 } else {
1875 indirect_count = indirect->draw_count;
1876 }
1877
1878 if (!indirect_count) {
1879 *start = *count = 0;
1880 return;
1881 }
1882
1883 map_size = (indirect_count - 1) * indirect->stride + 3 * sizeof(unsigned);
1884 data = (unsigned*)
1885 pipe_buffer_map_range(&sctx->b, indirect->buffer, indirect->offset, map_size,
1886 PIPE_MAP_READ, &transfer);
1887
1888 begin = UINT_MAX;
1889 end = 0;
1890
1891 for (unsigned i = 0; i < indirect_count; ++i) {
1892 unsigned count = data[0];
1893 unsigned start = data[2];
1894
1895 if (count > 0) {
1896 begin = MIN2(begin, start);
1897 end = MAX2(end, start + count);
1898 }
1899
1900 data += indirect->stride / sizeof(unsigned);
1901 }
1902
1903 pipe_buffer_unmap(&sctx->b, transfer);
1904
1905 if (begin < end) {
1906 *start = begin;
1907 *count = end - begin;
1908 } else {
1909 *start = *count = 0;
1910 }
1911 } else {
1912 unsigned min_element = UINT_MAX;
1913 unsigned max_element = 0;
1914
1915 for (unsigned i = 0; i < num_draws; i++) {
1916 min_element = MIN2(min_element, draws[i].start);
1917 max_element = MAX2(max_element, draws[i].start + draws[i].count);
1918 }
1919
1920 *start = min_element;
1921 *count = max_element - min_element;
1922 }
1923 }
1924
1925 ALWAYS_INLINE
si_emit_all_states(struct si_context * sctx,uint64_t skip_atom_mask)1926 static void si_emit_all_states(struct si_context *sctx, uint64_t skip_atom_mask)
1927 {
1928 /* Emit states by calling their emit functions. */
1929 uint64_t dirty = sctx->dirty_atoms & ~skip_atom_mask;
1930
1931 if (dirty) {
1932 sctx->dirty_atoms &= skip_atom_mask;
1933
1934 /* u_bit_scan64 is too slow on i386. */
1935 if (sizeof(void*) == 8) {
1936 do {
1937 unsigned i = u_bit_scan64(&dirty);
1938 sctx->atoms.array[i].emit(sctx, i);
1939 } while (dirty);
1940 } else {
1941 unsigned dirty_lo = dirty;
1942 unsigned dirty_hi = dirty >> 32;
1943
1944 while (dirty_lo) {
1945 unsigned i = u_bit_scan(&dirty_lo);
1946 sctx->atoms.array[i].emit(sctx, i);
1947 }
1948 while (dirty_hi) {
1949 unsigned i = 32 + u_bit_scan(&dirty_hi);
1950 sctx->atoms.array[i].emit(sctx, i);
1951 }
1952 }
1953 }
1954 }
1955
1956 #define DRAW_CLEANUP do { \
1957 if (index_size && indexbuf != info->index.resource) \
1958 pipe_resource_reference(&indexbuf, NULL); \
1959 } while (0)
1960
1961 template <amd_gfx_level GFX_VERSION, si_has_tess HAS_TESS, si_has_gs HAS_GS, si_has_ngg NGG,
1962 si_is_draw_vertex_state IS_DRAW_VERTEX_STATE, si_has_sh_pairs_packed HAS_SH_PAIRS_PACKED,
1963 util_popcnt POPCNT> ALWAYS_INLINE
si_draw(struct pipe_context * ctx,const struct pipe_draw_info * info,unsigned drawid_offset,const struct pipe_draw_indirect_info * indirect,const struct pipe_draw_start_count_bias * draws,unsigned num_draws,struct pipe_vertex_state * state,uint32_t partial_velem_mask)1964 static void si_draw(struct pipe_context *ctx,
1965 const struct pipe_draw_info *info,
1966 unsigned drawid_offset,
1967 const struct pipe_draw_indirect_info *indirect,
1968 const struct pipe_draw_start_count_bias *draws,
1969 unsigned num_draws,
1970 struct pipe_vertex_state *state,
1971 uint32_t partial_velem_mask)
1972 {
1973 /* Keep code that uses the least number of local variables as close to the beginning
1974 * of this function as possible to minimize register pressure.
1975 *
1976 * It doesn't matter where we return due to invalid parameters because such cases
1977 * shouldn't occur in practice.
1978 */
1979 struct si_context *sctx = (struct si_context *)ctx;
1980
1981 si_check_dirty_buffers_textures(sctx);
1982
1983 if (GFX_VERSION < GFX11)
1984 gfx6_decompress_textures(sctx, u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS));
1985 else
1986 gfx11_decompress_textures(sctx, u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS));
1987
1988 si_need_gfx_cs_space(sctx, num_draws);
1989
1990 if (u_trace_perfetto_active(&sctx->ds.trace_context))
1991 trace_si_begin_draw(&sctx->trace);
1992
1993 unsigned instance_count = info->instance_count;
1994
1995 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
1996 * no workaround for indirect draws, but we can at least skip
1997 * direct draws.
1998 * 'instance_count == 0' seems to be problematic on Renoir chips (#4866),
1999 * so simplify the condition and drop these draws for all <= GFX9 chips.
2000 */
2001 if (GFX_VERSION <= GFX9 && unlikely(!IS_DRAW_VERTEX_STATE && !indirect && !instance_count))
2002 return;
2003
2004 struct si_shader_selector *vs = sctx->shader.vs.cso;
2005 struct si_vertex_state *vstate = (struct si_vertex_state *)state;
2006 if (unlikely(!vs ||
2007 (!IS_DRAW_VERTEX_STATE && sctx->num_vertex_elements < vs->info.num_vs_inputs) ||
2008 (IS_DRAW_VERTEX_STATE && vstate->velems.count < vs->info.num_vs_inputs) ||
2009 !sctx->shader.ps.cso || (HAS_TESS != (info->mode == MESA_PRIM_PATCHES)))) {
2010 assert(0);
2011 return;
2012 }
2013
2014 enum mesa_prim prim = HAS_TESS ? MESA_PRIM_PATCHES : (enum mesa_prim)info->mode;
2015
2016 if (GFX_VERSION <= GFX9 && HAS_GS) {
2017 /* Determine whether the GS triangle strip adjacency fix should
2018 * be applied. Rotate every other triangle if triangle strips with
2019 * adjacency are fed to the GS. This doesn't work if primitive
2020 * restart occurs after an odd number of triangles.
2021 */
2022 bool gs_tri_strip_adj_fix =
2023 !HAS_TESS && prim == MESA_PRIM_TRIANGLE_STRIP_ADJACENCY;
2024
2025 if (gs_tri_strip_adj_fix != sctx->shader.gs.key.ge.mono.u.gs_tri_strip_adj_fix) {
2026 sctx->shader.gs.key.ge.mono.u.gs_tri_strip_adj_fix = gs_tri_strip_adj_fix;
2027 sctx->do_update_shaders = true;
2028 }
2029 }
2030
2031 struct pipe_resource *indexbuf = info->index.resource;
2032 unsigned index_size = info->index_size;
2033 unsigned index_offset = indirect && indirect->buffer ? draws[0].start * index_size : 0;
2034
2035 if (index_size) {
2036 /* Translate or upload, if needed. */
2037 /* 8-bit indices are supported on GFX8. */
2038 if (!IS_DRAW_VERTEX_STATE && GFX_VERSION <= GFX7 && index_size == 1) {
2039 unsigned start, count, start_offset, size;
2040
2041 si_get_draw_start_count(sctx, info, indirect, draws, num_draws, &start, &count);
2042 start_offset = start * 2;
2043 size = count * 2;
2044
2045 /* Don't use u_upload_alloc because we don't need to map the buffer for CPU access. */
2046 indexbuf = pipe_buffer_create(&sctx->screen->b, 0, PIPE_USAGE_IMMUTABLE, start_offset + size);
2047 if (unlikely(!indexbuf))
2048 return;
2049
2050 si_compute_shorten_ubyte_buffer(sctx, indexbuf, info->index.resource,
2051 start_offset, index_offset + start, count,
2052 SI_OP_SKIP_CACHE_INV_BEFORE | SI_OP_SYNC_AFTER);
2053
2054 index_offset = 0;
2055 index_size = 2;
2056 } else if (!IS_DRAW_VERTEX_STATE && info->has_user_indices) {
2057 unsigned start_offset;
2058
2059 assert(!indirect);
2060 assert(num_draws == 1);
2061 start_offset = draws[0].start * index_size;
2062
2063 indexbuf = NULL;
2064 u_upload_data(ctx->stream_uploader, start_offset, draws[0].count * index_size,
2065 sctx->screen->info.tcc_cache_line_size,
2066 (char *)info->index.user + start_offset, &index_offset, &indexbuf);
2067 if (unlikely(!indexbuf))
2068 return;
2069
2070 /* info->start will be added by the drawing code */
2071 index_offset -= start_offset;
2072 } else if (GFX_VERSION <= GFX7 && si_resource(indexbuf)->TC_L2_dirty) {
2073 /* GFX8 reads index buffers through TC L2, so it doesn't
2074 * need this. */
2075 sctx->flags |= SI_CONTEXT_WB_L2;
2076 si_mark_atom_dirty(sctx, &sctx->atoms.s.cache_flush);
2077 si_resource(indexbuf)->TC_L2_dirty = false;
2078 }
2079 }
2080
2081 unsigned min_direct_count = 0;
2082 unsigned total_direct_count = 0;
2083
2084 if (!IS_DRAW_VERTEX_STATE && indirect) {
2085 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
2086 if (GFX_VERSION <= GFX8) {
2087 if (indirect->buffer && si_resource(indirect->buffer)->TC_L2_dirty) {
2088 sctx->flags |= SI_CONTEXT_WB_L2;
2089 si_mark_atom_dirty(sctx, &sctx->atoms.s.cache_flush);
2090 si_resource(indirect->buffer)->TC_L2_dirty = false;
2091 }
2092
2093 if (indirect->indirect_draw_count &&
2094 si_resource(indirect->indirect_draw_count)->TC_L2_dirty) {
2095 sctx->flags |= SI_CONTEXT_WB_L2;
2096 si_mark_atom_dirty(sctx, &sctx->atoms.s.cache_flush);
2097 si_resource(indirect->indirect_draw_count)->TC_L2_dirty = false;
2098 }
2099 }
2100 total_direct_count = INT_MAX; /* just set something other than 0 to enable shader culling */
2101 } else {
2102 total_direct_count = min_direct_count = draws[0].count;
2103
2104 for (unsigned i = 1; i < num_draws; i++) {
2105 unsigned count = draws[i].count;
2106
2107 total_direct_count += count;
2108 min_direct_count = MIN2(min_direct_count, count);
2109 }
2110 }
2111
2112 /* Set the rasterization primitive type.
2113 *
2114 * This must be done after si_decompress_textures, which can call
2115 * draw_vbo recursively, and before si_update_shaders, which uses
2116 * current_rast_prim for this draw_vbo call.
2117 */
2118 if (!HAS_GS && !HAS_TESS) {
2119 enum mesa_prim rast_prim;
2120
2121 if (util_rast_prim_is_triangles(prim)) {
2122 rast_prim = MESA_PRIM_TRIANGLES;
2123 } else {
2124 /* Only possibilities, POINTS, LINE*, RECTANGLES */
2125 rast_prim = prim;
2126 }
2127
2128 si_set_rasterized_prim(sctx, rast_prim, si_get_vs_inline(sctx, HAS_TESS, HAS_GS)->current,
2129 NGG);
2130 }
2131
2132 if (IS_DRAW_VERTEX_STATE) {
2133 /* draw_vertex_state doesn't use the current vertex buffers and vertex elements,
2134 * so disable all VS input lowering.
2135 */
2136 if (!sctx->force_trivial_vs_inputs) {
2137 sctx->force_trivial_vs_inputs = true;
2138
2139 /* Update shaders to disable VS input lowering. */
2140 if (sctx->uses_nontrivial_vs_inputs) {
2141 si_vs_key_update_inputs(sctx);
2142 sctx->do_update_shaders = true;
2143 }
2144 }
2145 } else {
2146 if (sctx->force_trivial_vs_inputs) {
2147 sctx->force_trivial_vs_inputs = false;
2148
2149 /* Update shaders to possibly enable VS input lowering. */
2150 if (sctx->uses_nontrivial_vs_inputs) {
2151 si_vs_key_update_inputs(sctx);
2152 sctx->do_update_shaders = true;
2153 }
2154 }
2155 }
2156
2157 /* Update NGG culling settings. */
2158 uint16_t old_ngg_culling = sctx->ngg_culling;
2159 if (GFX_VERSION >= GFX10) {
2160 struct si_shader_selector *hw_vs = si_get_vs_inline(sctx, HAS_TESS, HAS_GS)->cso;
2161
2162 if (NGG &&
2163 /* Tessellation and GS set ngg_cull_vert_threshold to UINT_MAX if the prim type
2164 * is not points, so this check is only needed for VS. */
2165 (HAS_TESS || HAS_GS || util_rast_prim_is_lines_or_triangles(sctx->current_rast_prim)) &&
2166 /* Only the first draw for a shader starts with culling disabled and it's disabled
2167 * until we pass the total_direct_count check and then it stays enabled until
2168 * the shader is changed. This eliminates most culling on/off state changes. */
2169 (old_ngg_culling || total_direct_count > hw_vs->ngg_cull_vert_threshold)) {
2170 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
2171
2172 /* Check that the current shader allows culling. */
2173 assert(hw_vs->ngg_cull_vert_threshold != UINT_MAX);
2174
2175 uint16_t ngg_culling;
2176
2177 if (util_prim_is_lines(sctx->current_rast_prim)) {
2178 /* Overwrite it to mask out face cull flags. */
2179 ngg_culling = rs->ngg_cull_flags_lines;
2180 } else {
2181 ngg_culling = sctx->viewport0_y_inverted ? rs->ngg_cull_flags_tris_y_inverted :
2182 rs->ngg_cull_flags_tris;
2183 assert(ngg_culling); /* rasterizer state should always set this to non-zero */
2184 }
2185
2186 if (ngg_culling != old_ngg_culling) {
2187 /* If shader compilation is not ready, this setting will be rejected. */
2188 sctx->ngg_culling = ngg_culling;
2189 sctx->do_update_shaders = true;
2190 }
2191 } else if (old_ngg_culling) {
2192 sctx->ngg_culling = 0;
2193 sctx->do_update_shaders = true;
2194 }
2195 }
2196
2197 if (unlikely(sctx->do_update_shaders)) {
2198 if (unlikely(!(si_update_shaders<GFX_VERSION, HAS_TESS, HAS_GS, NGG>(sctx)))) {
2199 DRAW_CLEANUP;
2200 return;
2201 }
2202 }
2203
2204 /* This is the optimal packet order:
2205 * Set all states first, so that all SET packets are processed in parallel with previous
2206 * draw calls. Then flush caches and wait if needed. Then draw and prefetch at the end.
2207 * It's better to draw before prefetches because we want to start fetching indices before
2208 * shaders. The idea is to minimize the time when the CUs are idle.
2209 */
2210
2211 /* Vega10/Raven scissor bug workaround. When any context register is
2212 * written (i.e. the GPU rolls the context), PA_SC_VPORT_SCISSOR
2213 * registers must be written too.
2214 */
2215 bool gfx9_scissor_bug = false;
2216 uint64_t masked_atoms = 0;
2217
2218 if (GFX_VERSION == GFX9 && sctx->screen->info.has_gfx9_scissor_bug) {
2219 masked_atoms |= si_get_atom_bit(sctx, &sctx->atoms.s.scissors);
2220 gfx9_scissor_bug = true;
2221
2222 if ((!IS_DRAW_VERTEX_STATE && indirect && indirect->count_from_stream_output) ||
2223 sctx->dirty_atoms & si_atoms_that_always_roll_context())
2224 sctx->context_roll = true;
2225 }
2226
2227 bool primitive_restart = !IS_DRAW_VERTEX_STATE && info->primitive_restart;
2228
2229 /* Emit states. */
2230 si_emit_rasterizer_prim_state<GFX_VERSION, HAS_GS, NGG>(sctx);
2231 /* This emits states and flushes caches. */
2232 si_emit_all_states(sctx, masked_atoms);
2233 /* This can be done after si_emit_all_states because it doesn't set cache flush flags. */
2234 si_emit_draw_registers<GFX_VERSION, HAS_TESS, HAS_GS, NGG, IS_DRAW_VERTEX_STATE>
2235 (sctx, indirect, prim, index_size, instance_count, primitive_restart,
2236 info->restart_index, min_direct_count);
2237
2238 /* <-- CUs are idle here if the cache_flush state waited. */
2239
2240 /* This must be done after si_emit_all_states, which can affect this. */
2241 si_emit_vs_state<GFX_VERSION, HAS_TESS, HAS_GS, NGG, IS_DRAW_VERTEX_STATE, HAS_SH_PAIRS_PACKED>
2242 (sctx, index_size);
2243
2244 /* This needs to be done after cache flushes because ACQUIRE_MEM rolls the context. */
2245 if (GFX_VERSION == GFX9 && gfx9_scissor_bug &&
2246 (sctx->context_roll || si_is_atom_dirty(sctx, &sctx->atoms.s.scissors))) {
2247 sctx->atoms.s.scissors.emit(sctx, -1);
2248 sctx->dirty_atoms &= ~si_get_atom_bit(sctx, &sctx->atoms.s.scissors);
2249 }
2250 assert(sctx->dirty_atoms == 0);
2251
2252 /* This uploads VBO descriptors, sets user SGPRs, and executes the L2 prefetch.
2253 * It should done after cache flushing.
2254 */
2255 if (unlikely((!si_upload_and_prefetch_VB_descriptors
2256 <GFX_VERSION, HAS_TESS, HAS_GS, NGG, IS_DRAW_VERTEX_STATE, HAS_SH_PAIRS_PACKED, POPCNT>
2257 (sctx, state, partial_velem_mask)))) {
2258 DRAW_CLEANUP;
2259 return;
2260 }
2261
2262 si_emit_draw_packets<GFX_VERSION, HAS_TESS, HAS_GS, NGG, IS_DRAW_VERTEX_STATE, HAS_SH_PAIRS_PACKED>
2263 (sctx, info, drawid_offset, indirect, draws, num_draws, indexbuf,
2264 index_size, index_offset, instance_count);
2265 /* <-- CUs start to get busy here if we waited. */
2266
2267 /* Start prefetches after the draw has been started. Both will run
2268 * in parallel, but starting the draw first is more important.
2269 */
2270 si_prefetch_shaders<GFX_VERSION, HAS_TESS, HAS_GS, NGG>(sctx);
2271
2272 /* Clear the context roll flag after the draw call.
2273 * Only used by the gfx9 scissor bug.
2274 */
2275 if (GFX_VERSION == GFX9)
2276 sctx->context_roll = false;
2277
2278 if (unlikely(sctx->current_saved_cs)) {
2279 si_trace_emit(sctx);
2280 si_log_draw_state(sctx, sctx->log);
2281 }
2282
2283 /* Workaround for a VGT hang when streamout is enabled.
2284 * It must be done after drawing. */
2285 if (((GFX_VERSION == GFX7 && sctx->family == CHIP_HAWAII) ||
2286 (GFX_VERSION == GFX8 && (sctx->family == CHIP_TONGA || sctx->family == CHIP_FIJI))) &&
2287 si_get_strmout_en(sctx)) {
2288 sctx->flags |= SI_CONTEXT_VGT_STREAMOUT_SYNC;
2289 si_mark_atom_dirty(sctx, &sctx->atoms.s.cache_flush);
2290 }
2291
2292 if (unlikely(sctx->decompression_enabled)) {
2293 sctx->num_decompress_calls++;
2294 } else {
2295 sctx->num_draw_calls += num_draws;
2296 }
2297
2298 if (sctx->framebuffer.state.zsbuf) {
2299 struct si_texture *zstex = (struct si_texture *)sctx->framebuffer.state.zsbuf->texture;
2300 zstex->depth_cleared_level_mask &= ~BITFIELD_BIT(sctx->framebuffer.state.zsbuf->u.tex.level);
2301 }
2302
2303 if (u_trace_perfetto_active(&sctx->ds.trace_context)) {
2304 trace_si_end_draw(&sctx->trace, total_direct_count);
2305 }
2306
2307 DRAW_CLEANUP;
2308 }
2309
2310 template <amd_gfx_level GFX_VERSION, si_has_tess HAS_TESS, si_has_gs HAS_GS, si_has_ngg NGG,
2311 si_has_sh_pairs_packed HAS_SH_PAIRS_PACKED>
si_draw_vbo(struct pipe_context * ctx,const struct pipe_draw_info * info,unsigned drawid_offset,const struct pipe_draw_indirect_info * indirect,const struct pipe_draw_start_count_bias * draws,unsigned num_draws)2312 static void si_draw_vbo(struct pipe_context *ctx,
2313 const struct pipe_draw_info *info,
2314 unsigned drawid_offset,
2315 const struct pipe_draw_indirect_info *indirect,
2316 const struct pipe_draw_start_count_bias *draws,
2317 unsigned num_draws)
2318 {
2319 si_draw<GFX_VERSION, HAS_TESS, HAS_GS, NGG, DRAW_VERTEX_STATE_OFF, HAS_SH_PAIRS_PACKED, POPCNT_NO>
2320 (ctx, info, drawid_offset, indirect, draws, num_draws, NULL, 0);
2321 }
2322
2323 template <amd_gfx_level GFX_VERSION, si_has_tess HAS_TESS, si_has_gs HAS_GS, si_has_ngg NGG,
2324 si_has_sh_pairs_packed HAS_SH_PAIRS_PACKED, util_popcnt POPCNT>
si_draw_vertex_state(struct pipe_context * ctx,struct pipe_vertex_state * vstate,uint32_t partial_velem_mask,struct pipe_draw_vertex_state_info info,const struct pipe_draw_start_count_bias * draws,unsigned num_draws)2325 static void si_draw_vertex_state(struct pipe_context *ctx,
2326 struct pipe_vertex_state *vstate,
2327 uint32_t partial_velem_mask,
2328 struct pipe_draw_vertex_state_info info,
2329 const struct pipe_draw_start_count_bias *draws,
2330 unsigned num_draws)
2331 {
2332 struct si_vertex_state *state = (struct si_vertex_state *)vstate;
2333 struct pipe_draw_info dinfo = {};
2334
2335 dinfo.mode = info.mode;
2336 dinfo.index_size = 4;
2337 dinfo.instance_count = 1;
2338 dinfo.index.resource = state->b.input.indexbuf;
2339
2340 si_draw<GFX_VERSION, HAS_TESS, HAS_GS, NGG, DRAW_VERTEX_STATE_ON, HAS_SH_PAIRS_PACKED, POPCNT>
2341 (ctx, &dinfo, 0, NULL, draws, num_draws, vstate, partial_velem_mask);
2342
2343 if (info.take_vertex_state_ownership)
2344 pipe_vertex_state_reference(&vstate, NULL);
2345 }
2346
si_draw_rectangle(struct blitter_context * blitter,void * vertex_elements_cso,blitter_get_vs_func get_vs,int x1,int y1,int x2,int y2,float depth,unsigned num_instances,enum blitter_attrib_type type,const union blitter_attrib * attrib)2347 static void si_draw_rectangle(struct blitter_context *blitter, void *vertex_elements_cso,
2348 blitter_get_vs_func get_vs, int x1, int y1, int x2, int y2,
2349 float depth, unsigned num_instances, enum blitter_attrib_type type,
2350 const union blitter_attrib *attrib)
2351 {
2352 struct pipe_context *pipe = util_blitter_get_pipe(blitter);
2353 struct si_context *sctx = (struct si_context *)pipe;
2354 uint32_t attribute_ring_address_lo =
2355 sctx->gfx_level >= GFX11 ? sctx->screen->attribute_ring->gpu_address : 0;
2356
2357 /* Pack position coordinates as signed int16. */
2358 sctx->vs_blit_sh_data[0] = (uint32_t)(x1 & 0xffff) | ((uint32_t)(y1 & 0xffff) << 16);
2359 sctx->vs_blit_sh_data[1] = (uint32_t)(x2 & 0xffff) | ((uint32_t)(y2 & 0xffff) << 16);
2360 sctx->vs_blit_sh_data[2] = fui(depth);
2361
2362 switch (type) {
2363 case UTIL_BLITTER_ATTRIB_COLOR:
2364 memcpy(&sctx->vs_blit_sh_data[3], attrib->color, sizeof(float) * 4);
2365 sctx->vs_blit_sh_data[7] = attribute_ring_address_lo;
2366 break;
2367 case UTIL_BLITTER_ATTRIB_TEXCOORD_XY:
2368 case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW:
2369 memcpy(&sctx->vs_blit_sh_data[3], &attrib->texcoord, sizeof(attrib->texcoord));
2370 sctx->vs_blit_sh_data[9] = attribute_ring_address_lo;
2371 break;
2372 case UTIL_BLITTER_ATTRIB_NONE:;
2373 }
2374
2375 pipe->bind_vs_state(pipe, si_get_blitter_vs(sctx, type, num_instances));
2376
2377 struct pipe_draw_info info = {};
2378 struct pipe_draw_start_count_bias draw;
2379
2380 info.mode = SI_PRIM_RECTANGLE_LIST;
2381 info.instance_count = num_instances;
2382
2383 draw.start = 0;
2384 draw.count = 3;
2385
2386 /* Blits don't use vertex buffers. */
2387 sctx->vertex_buffers_dirty = false;
2388
2389 pipe->draw_vbo(pipe, &info, 0, NULL, &draw, 1);
2390 }
2391
2392 template <amd_gfx_level GFX_VERSION, si_has_tess HAS_TESS, si_has_gs HAS_GS, si_has_ngg NGG>
si_init_draw_vbo(struct si_context * sctx)2393 static void si_init_draw_vbo(struct si_context *sctx)
2394 {
2395 if (NGG && GFX_VERSION < GFX10)
2396 return;
2397
2398 if (!NGG && GFX_VERSION >= GFX11)
2399 return;
2400
2401 if (GFX_VERSION >= GFX11 && sctx->screen->info.has_set_sh_pairs_packed) {
2402 sctx->draw_vbo[HAS_TESS][HAS_GS][NGG] =
2403 si_draw_vbo<GFX_VERSION, HAS_TESS, HAS_GS, NGG, HAS_SH_PAIRS_PACKED_ON>;
2404
2405 if (util_get_cpu_caps()->has_popcnt) {
2406 sctx->draw_vertex_state[HAS_TESS][HAS_GS][NGG] =
2407 si_draw_vertex_state<GFX_VERSION, HAS_TESS, HAS_GS, NGG, HAS_SH_PAIRS_PACKED_ON, POPCNT_YES>;
2408 } else {
2409 sctx->draw_vertex_state[HAS_TESS][HAS_GS][NGG] =
2410 si_draw_vertex_state<GFX_VERSION, HAS_TESS, HAS_GS, NGG, HAS_SH_PAIRS_PACKED_ON, POPCNT_NO>;
2411 }
2412 } else {
2413 sctx->draw_vbo[HAS_TESS][HAS_GS][NGG] =
2414 si_draw_vbo<GFX_VERSION, HAS_TESS, HAS_GS, NGG, HAS_SH_PAIRS_PACKED_OFF>;
2415
2416 if (util_get_cpu_caps()->has_popcnt) {
2417 sctx->draw_vertex_state[HAS_TESS][HAS_GS][NGG] =
2418 si_draw_vertex_state<GFX_VERSION, HAS_TESS, HAS_GS, NGG, HAS_SH_PAIRS_PACKED_OFF, POPCNT_YES>;
2419 } else {
2420 sctx->draw_vertex_state[HAS_TESS][HAS_GS][NGG] =
2421 si_draw_vertex_state<GFX_VERSION, HAS_TESS, HAS_GS, NGG, HAS_SH_PAIRS_PACKED_OFF, POPCNT_NO>;
2422 }
2423 }
2424 }
2425
2426 template <amd_gfx_level GFX_VERSION>
si_init_draw_vbo_all_pipeline_options(struct si_context * sctx)2427 static void si_init_draw_vbo_all_pipeline_options(struct si_context *sctx)
2428 {
2429 si_init_draw_vbo<GFX_VERSION, TESS_OFF, GS_OFF, NGG_OFF>(sctx);
2430 si_init_draw_vbo<GFX_VERSION, TESS_OFF, GS_ON, NGG_OFF>(sctx);
2431 si_init_draw_vbo<GFX_VERSION, TESS_ON, GS_OFF, NGG_OFF>(sctx);
2432 si_init_draw_vbo<GFX_VERSION, TESS_ON, GS_ON, NGG_OFF>(sctx);
2433 si_init_draw_vbo<GFX_VERSION, TESS_OFF, GS_OFF, NGG_ON>(sctx);
2434 si_init_draw_vbo<GFX_VERSION, TESS_OFF, GS_ON, NGG_ON>(sctx);
2435 si_init_draw_vbo<GFX_VERSION, TESS_ON, GS_OFF, NGG_ON>(sctx);
2436 si_init_draw_vbo<GFX_VERSION, TESS_ON, GS_ON, NGG_ON>(sctx);
2437 }
2438
si_invalid_draw_vbo(struct pipe_context * pipe,const struct pipe_draw_info * info,unsigned drawid_offset,const struct pipe_draw_indirect_info * indirect,const struct pipe_draw_start_count_bias * draws,unsigned num_draws)2439 static void si_invalid_draw_vbo(struct pipe_context *pipe,
2440 const struct pipe_draw_info *info,
2441 unsigned drawid_offset,
2442 const struct pipe_draw_indirect_info *indirect,
2443 const struct pipe_draw_start_count_bias *draws,
2444 unsigned num_draws)
2445 {
2446 unreachable("vertex shader not bound");
2447 }
2448
si_invalid_draw_vertex_state(struct pipe_context * ctx,struct pipe_vertex_state * vstate,uint32_t partial_velem_mask,struct pipe_draw_vertex_state_info info,const struct pipe_draw_start_count_bias * draws,unsigned num_draws)2449 static void si_invalid_draw_vertex_state(struct pipe_context *ctx,
2450 struct pipe_vertex_state *vstate,
2451 uint32_t partial_velem_mask,
2452 struct pipe_draw_vertex_state_info info,
2453 const struct pipe_draw_start_count_bias *draws,
2454 unsigned num_draws)
2455 {
2456 unreachable("vertex shader not bound");
2457 }
2458
2459 extern "C"
GFX(si_init_draw_functions_)2460 void GFX(si_init_draw_functions_)(struct si_context *sctx)
2461 {
2462 assert(sctx->gfx_level == GFX());
2463
2464 si_init_draw_vbo_all_pipeline_options<GFX()>(sctx);
2465
2466 /* Bind a fake draw_vbo, so that draw_vbo isn't NULL, which would skip
2467 * initialization of callbacks in upper layers (such as u_threaded_context).
2468 */
2469 sctx->b.draw_vbo = si_invalid_draw_vbo;
2470 sctx->b.draw_vertex_state = si_invalid_draw_vertex_state;
2471 sctx->blitter->draw_rectangle = si_draw_rectangle;
2472
2473 si_init_ia_multi_vgt_param_table(sctx);
2474 }
2475