1 /* 2 * Copyright © 2022 Imagination Technologies Ltd. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a copy 5 * of this software and associated documentation files (the "Software"), to deal 6 * in the Software without restriction, including without limitation the rights 7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 * copies of the Software, and to permit persons to whom the Software is 9 * furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 */ 23 24 #ifndef PVR_FORMATS_H 25 #define PVR_FORMATS_H 26 27 #include <stdbool.h> 28 #include <stdint.h> 29 #include <vulkan/vulkan.h> 30 31 #include "util/format/u_formats.h" 32 33 /* This is based on VkClearColorValue which is an array of RGBA, and on the 34 * output register usage for the biggest 32 bit 4 component formats which use up 35 * all 4 output registers. 36 * So this can be used for both unpacked RGBA value and to represent values 37 * packed according to the hardware (the accum format). 38 */ 39 #define PVR_CLEAR_COLOR_ARRAY_SIZE 4 40 41 #define PVR_TEX_FORMAT_COUNT (PVRX(TEXSTATE_IMAGE_WORD0_TEXFORMAT_MAX_SIZE) + 1) 42 43 enum pvr_pbe_accum_format { 44 PVR_PBE_ACCUM_FORMAT_INVALID = 0, /* Explicitly treat 0 as invalid. */ 45 PVR_PBE_ACCUM_FORMAT_U8, 46 PVR_PBE_ACCUM_FORMAT_S8, 47 PVR_PBE_ACCUM_FORMAT_U16, 48 PVR_PBE_ACCUM_FORMAT_S16, 49 PVR_PBE_ACCUM_FORMAT_F16, 50 PVR_PBE_ACCUM_FORMAT_F32, 51 PVR_PBE_ACCUM_FORMAT_UINT8, 52 PVR_PBE_ACCUM_FORMAT_UINT16, 53 PVR_PBE_ACCUM_FORMAT_UINT32, 54 PVR_PBE_ACCUM_FORMAT_SINT8, 55 PVR_PBE_ACCUM_FORMAT_SINT16, 56 PVR_PBE_ACCUM_FORMAT_SINT32, 57 /* Formats with medp shader output precision. */ 58 PVR_PBE_ACCUM_FORMAT_UINT32_MEDP, 59 PVR_PBE_ACCUM_FORMAT_SINT32_MEDP, 60 PVR_PBE_ACCUM_FORMAT_U1010102, 61 PVR_PBE_ACCUM_FORMAT_U24, 62 }; 63 64 /** 65 * Pixel related shader selector. The logic selecting the shader has to take 66 * into account the pixel related properties (controlling the conversion path in 67 * the shader) and the geometry related properties (controlling the sample 68 * position calcs). These two can be orthogonal. 69 * 70 * integer format conversions, bit depth : 8, 16, 32 per ch formats : signed, 71 * unsigned. Strategy: convert everything to U32 or S32 then USC pack. PBE just 72 * pass through. 73 * 74 * fixed point format conversions, bit depth 565, 1555, 555 etc. Strategy: 75 * fcnorm to 4 F32, then USC pack to F16F16. PBE converts to destination 76 * 77 * float/fixed format conversions 78 * strategy: fcnorm, then pack to f16 _when_ destination is not f32. 79 * fmt | unorm | flt | 80 * 8 | x | | 81 * 16 | x | x | 82 * 32 | x | x | 83 * 84 * 85 * non-merge type DS blit table 86 * ********************************************** 87 * * * S8 D16 D24S8 D32 D32S8 * 88 * ********************************************** 89 * * S8 * cpy i i i i * 90 * * D16 * i cpy i - i * 91 * * D24S8 * swiz - cpy (1) - * 92 * * D32 * i - i cpy i * 93 * * D32S8 * (2) - - cpy cpy * 94 * ********************************************** 95 * 96 * merge with stencil pick type DS blit table 97 * ********************************************** 98 * * * S8 D16 D24S8 D32 D32S8 * 99 * ********************************************** 100 * * S8 * i i (1) i (2) * 101 * * D16 * i i i i i * 102 * * D24S8 * i i (3) i (4) * 103 * * D32 * i i i i i * 104 * * D32S8 * i i (5) i (6) * 105 * ********************************************** 106 * 107 * merge with depth pick type DS blit table 108 * ********************************************** 109 * * * S8 D16 D24S8 D32 D32S8 * 110 * ********************************************** 111 * * S8 * i i i i i * 112 * * D16 * - - - - - * 113 * * D24S8 * - - (s) - - * 114 * * D32 * - - (1) - (2) * 115 * * D32S8 * - - - - (s) * 116 * ********************************************** 117 * 118 * D formats are unpacked into a single register according to their format 119 * S formats are unpacked into a single register in U8 120 * D24S8 is in a single 32 bit register (as the PBE can't read it from 121 * unpacked.) 122 * 123 * Swizzles are applied on the TPU not the PBE because of potential 124 * accumulation i.e. a non-iterated shader doesn't know if it writes the output 125 * buffer for PBE emit or a second pass blend. 126 */ 127 enum pvr_transfer_pbe_pixel_src { 128 PVR_TRANSFER_PBE_PIXEL_SRC_UU8888 = 0, 129 PVR_TRANSFER_PBE_PIXEL_SRC_US8888 = 1, 130 PVR_TRANSFER_PBE_PIXEL_SRC_UU16U16 = 2, 131 PVR_TRANSFER_PBE_PIXEL_SRC_US16S16 = 3, 132 PVR_TRANSFER_PBE_PIXEL_SRC_SU8888 = 4, 133 PVR_TRANSFER_PBE_PIXEL_SRC_SS8888 = 5, 134 PVR_TRANSFER_PBE_PIXEL_SRC_SU16U16 = 6, 135 PVR_TRANSFER_PBE_PIXEL_SRC_SS16S16 = 7, 136 137 PVR_TRANSFER_PBE_PIXEL_SRC_UU1010102 = 8, 138 PVR_TRANSFER_PBE_PIXEL_SRC_SU1010102 = 9, 139 PVR_TRANSFER_PBE_PIXEL_SRC_RBSWAP_UU1010102 = 10, 140 PVR_TRANSFER_PBE_PIXEL_SRC_RBSWAP_SU1010102 = 11, 141 142 PVR_TRANSFER_PBE_PIXEL_SRC_SU32U32 = 12, 143 PVR_TRANSFER_PBE_PIXEL_SRC_S4XU32 = 13, 144 PVR_TRANSFER_PBE_PIXEL_SRC_US32S32 = 14, 145 PVR_TRANSFER_PBE_PIXEL_SRC_U4XS32 = 15, 146 147 PVR_TRANSFER_PBE_PIXEL_SRC_F16F16 = 16, 148 PVR_TRANSFER_PBE_PIXEL_SRC_U16NORM = 17, 149 PVR_TRANSFER_PBE_PIXEL_SRC_S16NORM = 18, 150 151 PVR_TRANSFER_PBE_PIXEL_SRC_F32X4 = 19, 152 PVR_TRANSFER_PBE_PIXEL_SRC_F32X2 = 20, 153 PVR_TRANSFER_PBE_PIXEL_SRC_F32 = 21, 154 155 PVR_TRANSFER_PBE_PIXEL_SRC_RAW32 = 22, 156 PVR_TRANSFER_PBE_PIXEL_SRC_RAW64 = 23, 157 PVR_TRANSFER_PBE_PIXEL_SRC_RAW128 = 24, 158 159 /* f16 to U8 conversion in shader. */ 160 PVR_TRANSFER_PBE_PIXEL_SRC_F16_U8 = 25, 161 162 PVR_TRANSFER_PBE_PIXEL_SRC_SWAP_LMSB = 26, 163 PVR_TRANSFER_PBE_PIXEL_SRC_MOV_BY45 = 27, 164 165 PVR_TRANSFER_PBE_PIXEL_SRC_D24S8 = 28, 166 PVR_TRANSFER_PBE_PIXEL_SRC_S8D24 = 29, 167 PVR_TRANSFER_PBE_PIXEL_SRC_D32S8 = 30, 168 169 /* D: D32_S8 */ 170 PVR_TRANSFER_PBE_PIXEL_SRC_SMRG_S8_D32S8 = 31, 171 PVR_TRANSFER_PBE_PIXEL_SRC_SMRG_D24S8_D32S8 = 32, 172 PVR_TRANSFER_PBE_PIXEL_SRC_SMRG_D32S8_D32S8 = 33, 173 PVR_TRANSFER_PBE_PIXEL_SRC_DMRG_D32S8_D32S8 = 34, 174 175 /* D: D32 */ 176 PVR_TRANSFER_PBE_PIXEL_SRC_CONV_D24_D32 = 35, 177 PVR_TRANSFER_PBE_PIXEL_SRC_CONV_D32U_D32F = 36, 178 179 /* D : D24_S8 */ 180 PVR_TRANSFER_PBE_PIXEL_SRC_SMRG_S8_D24S8 = 37, 181 PVR_TRANSFER_PBE_PIXEL_SRC_SMRG_D24S8_D24S8 = 38, 182 PVR_TRANSFER_PBE_PIXEL_SRC_DMRG_D24S8_D24S8 = 39, 183 PVR_TRANSFER_PBE_PIXEL_SRC_CONV_D32_D24S8 = 40, 184 PVR_TRANSFER_PBE_PIXEL_SRC_DMRG_D32_D24S8 = 41, 185 PVR_TRANSFER_PBE_PIXEL_SRC_DMRG_D32U_D24S8 = 42, 186 187 /* ob0 holds Y and ob0 holds U or V. */ 188 PVR_TRANSFER_PBE_PIXEL_SRC_YUV_PACKED = 43, 189 190 /* ob0 holds Y, ob1 holds U, ob2 holds V. */ 191 PVR_TRANSFER_PBE_PIXEL_SRC_Y_U_V = 44, 192 193 PVR_TRANSFER_PBE_PIXEL_SRC_MASK16 = 45, 194 PVR_TRANSFER_PBE_PIXEL_SRC_MASK32 = 46, 195 PVR_TRANSFER_PBE_PIXEL_SRC_MASK48 = 47, 196 PVR_TRANSFER_PBE_PIXEL_SRC_MASK64 = 48, 197 PVR_TRANSFER_PBE_PIXEL_SRC_MASK96 = 49, 198 PVR_TRANSFER_PBE_PIXEL_SRC_MASK128 = 50, 199 200 PVR_TRANSFER_PBE_PIXEL_SRC_CONV_S8D24_D24S8 = 51, 201 202 /* ob0 holds Y and ob0 holds V or U. */ 203 PVR_TRANSFER_PBE_PIXEL_SRC_YVU_PACKED = 52, 204 205 /* ob0 holds Y, ob1 holds UV interleaved. */ 206 PVR_TRANSFER_PBE_PIXEL_SRC_Y_UV_INTERLEAVED = 53, 207 208 /* FIXME: This changes for other BVNC's which may change the hashing logic 209 * in pvr_hash_shader. 210 */ 211 PVR_TRANSFER_PBE_PIXEL_SRC_NUM = 54, 212 }; 213 214 /* FIXME: Replace all instances of uint32_t with PVRX(TEXSTATE_FORMAT) or 215 * PVRX(TEXSTATE_FORMAT_COMPRESSED) after the pvr_common cleanup is complete. 216 */ 217 218 struct pvr_tex_format_description { 219 uint32_t tex_format; 220 enum pipe_format pipe_format_int; 221 enum pipe_format pipe_format_float; 222 }; 223 224 struct pvr_tex_format_compressed_description { 225 uint32_t tex_format; 226 enum pipe_format pipe_format; 227 uint32_t tex_format_simple; 228 }; 229 230 bool pvr_tex_format_is_supported(uint32_t tex_format); 231 232 const struct pvr_tex_format_description * 233 pvr_get_tex_format_description(uint32_t tex_format); 234 235 bool pvr_tex_format_compressed_is_supported(uint32_t tex_format); 236 237 const struct pvr_tex_format_compressed_description * 238 pvr_get_tex_format_compressed_description(uint32_t tex_format); 239 240 const uint8_t *pvr_get_format_swizzle(VkFormat vk_format); 241 uint32_t pvr_get_tex_format(VkFormat vk_format); 242 uint32_t pvr_get_tex_format_aspect(VkFormat vk_format, 243 VkImageAspectFlags aspect_mask); 244 uint32_t pvr_get_pbe_packmode(VkFormat vk_format); 245 uint32_t pvr_get_pbe_accum_format(VkFormat vk_format); 246 uint32_t pvr_get_pbe_accum_format_size_in_bytes(VkFormat vk_format); 247 bool pvr_format_is_pbe_downscalable(VkFormat vk_format); 248 249 void pvr_get_hw_clear_color(VkFormat vk_format, 250 VkClearColorValue value, 251 uint32_t packed_out[static const 4]); 252 253 uint32_t pvr_pbe_pixel_num_loads(enum pvr_transfer_pbe_pixel_src pbe_format); 254 255 #endif /* PVR_FORMATS_H */ 256