1 /*
2 * Copyright © 2022 Imagination Technologies Ltd.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a copy
5 * of this software and associated documentation files (the "Software"), to deal
6 * in the Software without restriction, including without limitation the rights
7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
8 * copies of the Software, and to permit persons to whom the Software is
9 * furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include <stdbool.h>
25 #include <stdint.h>
26
27 #include "hwdef/rogue_hw_defs.h"
28 #include "hwdef/rogue_hw_utils.h"
29 #include "pvr_csb_enum_helpers.h"
30 #include "pvr_device_info.h"
31 #include "pvr_job_common.h"
32 #include "pvr_private.h"
33 #include "util/macros.h"
34 #include "util/u_math.h"
35 #include "vk_alloc.h"
36 #include "vk_format.h"
37 #include "vk_object.h"
38
pvr_pbe_get_src_format_and_gamma(VkFormat vk_format,enum pvr_pbe_gamma default_gamma,bool with_packed_usc_channel,uint32_t * const src_format_out,enum pvr_pbe_gamma * const gamma_out)39 void pvr_pbe_get_src_format_and_gamma(VkFormat vk_format,
40 enum pvr_pbe_gamma default_gamma,
41 bool with_packed_usc_channel,
42 uint32_t *const src_format_out,
43 enum pvr_pbe_gamma *const gamma_out)
44 {
45 uint32_t chan_0_width = vk_format_get_channel_width(vk_format, 0);
46
47 *gamma_out = default_gamma;
48
49 if (vk_format_has_32bit_component(vk_format) ||
50 vk_format_is_int(vk_format)) {
51 *src_format_out = PVRX(PBESTATE_SOURCE_FORMAT_8_PER_CHANNEL);
52 } else if (vk_format_is_float(vk_format)) {
53 *src_format_out = PVRX(PBESTATE_SOURCE_FORMAT_F16_PER_CHANNEL);
54 } else if (vk_format_is_srgb(vk_format)) {
55 *gamma_out = PVR_PBE_GAMMA_ENABLED;
56
57 /* F16 source for gamma'd formats. */
58 *src_format_out = PVRX(PBESTATE_SOURCE_FORMAT_F16_PER_CHANNEL);
59 } else if (vk_format_has_depth(vk_format) &&
60 vk_format_get_component_bits(vk_format,
61 UTIL_FORMAT_COLORSPACE_ZS,
62 0) > 16) {
63 *src_format_out = PVRX(PBESTATE_SOURCE_FORMAT_8_PER_CHANNEL);
64 } else if (vk_format_has_stencil(vk_format) &&
65 vk_format_get_component_bits(vk_format,
66 UTIL_FORMAT_COLORSPACE_ZS,
67 1) > 0) {
68 *src_format_out = PVRX(PBESTATE_SOURCE_FORMAT_8_PER_CHANNEL);
69 } else if (chan_0_width > 16) {
70 *src_format_out = PVRX(PBESTATE_SOURCE_FORMAT_8_PER_CHANNEL);
71 } else if (chan_0_width > 8) {
72 *src_format_out = PVRX(PBESTATE_SOURCE_FORMAT_F16_PER_CHANNEL);
73 } else if (!with_packed_usc_channel) {
74 *src_format_out = PVRX(PBESTATE_SOURCE_FORMAT_F16_PER_CHANNEL);
75 } else {
76 *src_format_out = PVRX(PBESTATE_SOURCE_FORMAT_8_PER_CHANNEL);
77 }
78 }
79
pvr_pbe_pack_state(const struct pvr_device_info * dev_info,const struct pvr_pbe_surf_params * surface_params,const struct pvr_pbe_render_params * render_params,uint32_t pbe_cs_words[static const ROGUE_NUM_PBESTATE_STATE_WORDS],uint64_t pbe_reg_words[static const ROGUE_NUM_PBESTATE_REG_WORDS])80 void pvr_pbe_pack_state(
81 const struct pvr_device_info *dev_info,
82 const struct pvr_pbe_surf_params *surface_params,
83 const struct pvr_pbe_render_params *render_params,
84 uint32_t pbe_cs_words[static const ROGUE_NUM_PBESTATE_STATE_WORDS],
85 uint64_t pbe_reg_words[static const ROGUE_NUM_PBESTATE_REG_WORDS])
86 {
87 /* This function needs updating if the value of
88 * ROGUE_NUM_PBESTATE_STATE_WORDS changes, so check that it's the expected
89 * value.
90 */
91 STATIC_ASSERT(ROGUE_NUM_PBESTATE_STATE_WORDS == 2);
92
93 /* This function needs updating if the value of ROGUE_NUM_PBESTATE_REG_WORDS
94 * changes, so check that it's the expected value.
95 */
96 STATIC_ASSERT(ROGUE_NUM_PBESTATE_REG_WORDS == 3);
97
98 pbe_reg_words[2] = 0;
99
100 if (surface_params->z_only_render) {
101 pbe_cs_words[0] = 0;
102
103 pvr_csb_pack (&pbe_cs_words[1], PBESTATE_STATE_WORD1, state) {
104 state.emptytile = true;
105 }
106
107 pbe_reg_words[0] = 0;
108 pbe_reg_words[1] = 0;
109
110 return;
111 }
112
113 pvr_csb_pack (&pbe_cs_words[0], PBESTATE_STATE_WORD0, state) {
114 state.address_low = surface_params->addr;
115 }
116
117 pvr_csb_pack (&pbe_cs_words[1], PBESTATE_STATE_WORD1, state) {
118 state.address_high = surface_params->addr;
119
120 state.source_format = surface_params->source_format;
121
122 state.source_pos = pvr_pbestate_source_pos(render_params->source_start);
123 if (PVR_HAS_FEATURE(dev_info, eight_output_registers)) {
124 state.source_pos_offset_128 = render_params->source_start >=
125 PVR_PBE_STARTPOS_BIT128;
126 } else {
127 assert(render_params->source_start < PVR_PBE_STARTPOS_BIT128);
128 }
129
130 /* MRT index (Use 0 for a single render target)/ */
131 state.mrt_index = render_params->mrt_index;
132
133 /* Normalization flag based on output format. */
134 state.norm = surface_params->is_normalized;
135
136 state.packmode = surface_params->pbe_packmode;
137 }
138
139 pvr_csb_pack (&pbe_reg_words[0], PBESTATE_REG_WORD0, reg) {
140 reg.tilerelative = true;
141
142 switch (surface_params->mem_layout) {
143 case PVR_MEMLAYOUT_TWIDDLED:
144 reg.memlayout = PVRX(PBESTATE_MEMLAYOUT_TWIDDLE_2D);
145 break;
146
147 case PVR_MEMLAYOUT_3DTWIDDLED:
148 reg.memlayout = PVRX(PBESTATE_MEMLAYOUT_TWIDDLE_3D);
149 break;
150
151 case PVR_MEMLAYOUT_LINEAR:
152 default:
153 reg.memlayout = PVRX(PBESTATE_MEMLAYOUT_LINEAR);
154 break;
155 }
156
157 /* FIXME: Remove rotation and y_flip hardcoding if needed. */
158 reg.rotation = PVRX(PBESTATE_ROTATION_TYPE_0_DEG);
159 reg.y_flip = false;
160
161 /* Note: Due to gamma being overridden above, anything other than
162 * ENABLED/NONE is ignored.
163 */
164 if (surface_params->gamma == PVR_PBE_GAMMA_ENABLED) {
165 reg.gamma = true;
166
167 if (surface_params->nr_components == 2)
168 reg.twocomp_gamma =
169 PVRX(PBESTATE_TWOCOMP_GAMMA_GAMMA_BOTH_CHANNELS);
170 }
171
172 reg.linestride = (surface_params->stride - 1) /
173 PVRX(PBESTATE_REG_WORD0_LINESTRIDE_UNIT_SIZE);
174 reg.minclip_x = render_params->min_x_clip;
175
176 /* r, y or depth*/
177 switch (surface_params->swizzle[0]) {
178 case PIPE_SWIZZLE_X:
179 reg.swiz_chan0 = ROGUE_PBESTATE_SWIZ_SOURCE_CHAN0;
180 break;
181 case PIPE_SWIZZLE_Y:
182 reg.swiz_chan1 = ROGUE_PBESTATE_SWIZ_SOURCE_CHAN0;
183 break;
184 case PIPE_SWIZZLE_Z:
185 reg.swiz_chan2 = ROGUE_PBESTATE_SWIZ_SOURCE_CHAN0;
186 break;
187 case PIPE_SWIZZLE_W:
188 reg.swiz_chan3 = ROGUE_PBESTATE_SWIZ_SOURCE_CHAN0;
189 break;
190 case PIPE_SWIZZLE_0:
191 case PIPE_SWIZZLE_NONE:
192 reg.swiz_chan0 = ROGUE_PBESTATE_SWIZ_ZERO;
193 break;
194 case PIPE_SWIZZLE_1:
195 reg.swiz_chan0 = ROGUE_PBESTATE_SWIZ_ONE;
196 break;
197 default:
198 unreachable("Unknown enum pipe_swizzle");
199 break;
200 }
201 /* g, u or stencil*/
202 switch (surface_params->swizzle[1]) {
203 case PIPE_SWIZZLE_X:
204 reg.swiz_chan0 = ROGUE_PBESTATE_SWIZ_SOURCE_CHAN1;
205 break;
206 case PIPE_SWIZZLE_Y:
207 reg.swiz_chan1 = ROGUE_PBESTATE_SWIZ_SOURCE_CHAN1;
208 break;
209 case PIPE_SWIZZLE_Z:
210 reg.swiz_chan2 = ROGUE_PBESTATE_SWIZ_SOURCE_CHAN1;
211 break;
212 case PIPE_SWIZZLE_W:
213 reg.swiz_chan3 = ROGUE_PBESTATE_SWIZ_SOURCE_CHAN1;
214 break;
215 case PIPE_SWIZZLE_0:
216 case PIPE_SWIZZLE_NONE:
217 reg.swiz_chan1 = ROGUE_PBESTATE_SWIZ_ZERO;
218 break;
219 case PIPE_SWIZZLE_1:
220 reg.swiz_chan1 = ROGUE_PBESTATE_SWIZ_ONE;
221 break;
222 default:
223 unreachable("Unknown enum pipe_swizzle");
224 break;
225 }
226 /* b or v*/
227 switch (surface_params->swizzle[2]) {
228 case PIPE_SWIZZLE_X:
229 reg.swiz_chan0 = ROGUE_PBESTATE_SWIZ_SOURCE_CHAN2;
230 break;
231 case PIPE_SWIZZLE_Y:
232 reg.swiz_chan1 = ROGUE_PBESTATE_SWIZ_SOURCE_CHAN2;
233 break;
234 case PIPE_SWIZZLE_Z:
235 reg.swiz_chan2 = ROGUE_PBESTATE_SWIZ_SOURCE_CHAN2;
236 break;
237 case PIPE_SWIZZLE_W:
238 reg.swiz_chan3 = ROGUE_PBESTATE_SWIZ_SOURCE_CHAN2;
239 break;
240 case PIPE_SWIZZLE_0:
241 case PIPE_SWIZZLE_NONE:
242 reg.swiz_chan2 = ROGUE_PBESTATE_SWIZ_ZERO;
243 break;
244 case PIPE_SWIZZLE_1:
245 reg.swiz_chan2 = ROGUE_PBESTATE_SWIZ_ONE;
246 break;
247 default:
248 unreachable("Unknown enum pipe_swizzle");
249 break;
250 }
251 /* a */
252 switch (surface_params->swizzle[3]) {
253 case PIPE_SWIZZLE_X:
254 reg.swiz_chan0 = ROGUE_PBESTATE_SWIZ_SOURCE_CHAN3;
255 break;
256 case PIPE_SWIZZLE_Y:
257 reg.swiz_chan1 = ROGUE_PBESTATE_SWIZ_SOURCE_CHAN3;
258 break;
259 case PIPE_SWIZZLE_Z:
260 reg.swiz_chan2 = ROGUE_PBESTATE_SWIZ_SOURCE_CHAN3;
261 break;
262 case PIPE_SWIZZLE_W:
263 reg.swiz_chan3 = ROGUE_PBESTATE_SWIZ_SOURCE_CHAN3;
264 break;
265 case PIPE_SWIZZLE_0:
266 case PIPE_SWIZZLE_NONE:
267 reg.swiz_chan3 = ROGUE_PBESTATE_SWIZ_ZERO;
268 break;
269 case PIPE_SWIZZLE_1:
270 reg.swiz_chan3 = ROGUE_PBESTATE_SWIZ_ONE;
271 break;
272 default:
273 unreachable("Unknown enum pipe_swizzle");
274 break;
275 }
276
277 if (surface_params->mem_layout == PVR_MEMLAYOUT_3DTWIDDLED)
278 reg.size_z = util_logbase2_ceil(surface_params->depth);
279
280 reg.downscale = surface_params->down_scale;
281 }
282
283 pvr_csb_pack (&pbe_reg_words[1], PBESTATE_REG_WORD1, reg) {
284 if (surface_params->mem_layout == PVR_MEMLAYOUT_TWIDDLED ||
285 surface_params->mem_layout == PVR_MEMLAYOUT_3DTWIDDLED) {
286 reg.size_x = util_logbase2_ceil(surface_params->width);
287 reg.size_y = util_logbase2_ceil(surface_params->height);
288 }
289
290 reg.minclip_y = render_params->min_y_clip;
291 reg.maxclip_x = render_params->max_x_clip;
292 reg.zslice = render_params->slice;
293 reg.maxclip_y = render_params->max_y_clip;
294 }
295 }
296
297 /* TODO: Split this into smaller functions to make it easier to follow. When
298 * doing this, it would be nice to have a function that returns
299 * total_tiles_in_flight so that CR_ISP_CTL can be fully packed in
300 * pvr_render_job_ws_fragment_state_init().
301 */
pvr_setup_tiles_in_flight(const struct pvr_device_info * dev_info,const struct pvr_device_runtime_info * dev_runtime_info,uint32_t msaa_mode,uint32_t pixel_width,bool paired_tiles,uint32_t max_tiles_in_flight,uint32_t * const isp_ctl_out,uint32_t * const pixel_ctl_out)302 void pvr_setup_tiles_in_flight(
303 const struct pvr_device_info *dev_info,
304 const struct pvr_device_runtime_info *dev_runtime_info,
305 uint32_t msaa_mode,
306 uint32_t pixel_width,
307 bool paired_tiles,
308 uint32_t max_tiles_in_flight,
309 uint32_t *const isp_ctl_out,
310 uint32_t *const pixel_ctl_out)
311 {
312 uint32_t total_tiles_in_flight = 0;
313 uint32_t usable_partition_size;
314 uint32_t partitions_available;
315 uint32_t usc_min_output_regs;
316 uint32_t max_partitions;
317 uint32_t partition_size;
318 uint32_t max_phantoms;
319 uint32_t tile_size_x;
320 uint32_t tile_size_y;
321 uint32_t isp_samples;
322
323 /* Round up the pixel width to the next allocation granularity. */
324 usc_min_output_regs =
325 PVR_GET_FEATURE_VALUE(dev_info, usc_min_output_registers_per_pix, 0);
326 pixel_width = MAX2(pixel_width, usc_min_output_regs);
327 pixel_width = util_next_power_of_two(pixel_width);
328
329 assert(pixel_width <= rogue_get_max_output_regs_per_pixel(dev_info));
330
331 partition_size = pixel_width;
332
333 isp_samples = PVR_GET_FEATURE_VALUE(dev_info, isp_samples_per_pixel, 1);
334 if (isp_samples == 2) {
335 if (msaa_mode != PVRX(CR_ISP_AA_MODE_TYPE_AA_NONE))
336 partition_size *= 2U;
337 } else if (isp_samples == 4) {
338 if (msaa_mode == PVRX(CR_ISP_AA_MODE_TYPE_AA_4X) ||
339 msaa_mode == PVRX(CR_ISP_AA_MODE_TYPE_AA_8X))
340 partition_size *= 4U;
341 else if (msaa_mode == PVRX(CR_ISP_AA_MODE_TYPE_AA_2X))
342 partition_size *= 2U;
343 }
344
345 /* Cores with a tile size of 16x16 don't have quadrant affinity. Hence the
346 * partition size is the same as for a 32x32 tile quadrant (with no MSAA).
347 * When MSAA is enabled, the USC has to process half the tile (16x8 pixels).
348 */
349 tile_size_x = PVR_GET_FEATURE_VALUE(dev_info, tile_size_x, 0);
350 tile_size_y = PVR_GET_FEATURE_VALUE(dev_info, tile_size_y, 0);
351
352 /* We only support square tiles. */
353 assert(tile_size_x == tile_size_y);
354
355 if (tile_size_x == 16U) {
356 /* Cores with 16x16 tiles does not use tile quadrants. */
357 partition_size *= tile_size_x * tile_size_y;
358 } else {
359 /* Size of a tile quadrant (in dwords). */
360 partition_size *= (tile_size_x * tile_size_y / 4U);
361 }
362
363 /* Maximum available partition space for partitions of this size. */
364 max_partitions = PVR_GET_FEATURE_VALUE(dev_info, max_partitions, 0);
365 usable_partition_size = MIN2(dev_runtime_info->total_reserved_partition_size,
366 partition_size * max_partitions);
367
368 if (PVR_GET_FEATURE_VALUE(dev_info, common_store_size_in_dwords, 0) <
369 (1024 * 4 * 4)) {
370 /* Do not apply the limit for cores with 16x16 tile size (no quadrant
371 * affinity). */
372 if (tile_size_x != 16) {
373 /* This is to counter the extremely limited CS size on some cores.
374 */
375 /* Available partition space is limited to 8 tile quadrants. */
376 usable_partition_size =
377 MIN2((tile_size_x * tile_size_y / 4U) * 8U, usable_partition_size);
378 }
379 }
380
381 /* Ensure that maximum number of partitions in use is not greater
382 * than the total number of partitions available.
383 */
384 partitions_available =
385 MIN2(max_partitions, usable_partition_size / partition_size);
386
387 if (PVR_HAS_FEATURE(dev_info, xt_top_infrastructure))
388 max_phantoms = dev_runtime_info->num_phantoms;
389 else if (PVR_HAS_FEATURE(dev_info, roguexe))
390 max_phantoms = PVR_GET_FEATURE_VALUE(dev_info, num_raster_pipes, 0);
391 else
392 max_phantoms = 1;
393
394 for (uint32_t i = 0; i < max_phantoms; i++) {
395 uint32_t usc_tiles_in_flight = partitions_available;
396 uint32_t isp_tiles_in_flight;
397
398 /* Cores with tiles size other than 16x16 use tile quadrants. */
399 if (tile_size_x != 16) {
400 uint32_t num_clusters =
401 PVR_GET_FEATURE_VALUE(dev_info, num_clusters, 0U);
402 usc_tiles_in_flight =
403 (usc_tiles_in_flight * MIN2(4U, num_clusters - (4U * i))) / 4U;
404 }
405
406 assert(usc_tiles_in_flight > 0);
407
408 isp_tiles_in_flight =
409 PVR_GET_FEATURE_VALUE(dev_info, isp_max_tiles_in_flight, 0);
410 /* Ensure that maximum number of ISP tiles in flight is not greater
411 * than the maximum number of USC tiles in flight.
412 */
413 if (!PVR_HAS_FEATURE(dev_info, simple_internal_parameter_format) ||
414 PVR_GET_FEATURE_VALUE(dev_info, simple_parameter_format_version, 0) !=
415 2) {
416 isp_tiles_in_flight /= dev_runtime_info->num_phantoms;
417 }
418
419 isp_tiles_in_flight = MIN2(usc_tiles_in_flight, isp_tiles_in_flight);
420
421 /* Limit the number of tiles in flight if the shaders have
422 * requested a large allocation of local memory.
423 */
424 if (max_tiles_in_flight > 0U) {
425 isp_tiles_in_flight = MIN2(usc_tiles_in_flight, max_tiles_in_flight);
426
427 if (PVR_HAS_FEATURE(dev_info, roguexe)) {
428 if (tile_size_x == 16) {
429 /* The FW infers the tiles in flight value from the
430 * partitions setting.
431 */
432 /* Partitions per tile. */
433 partitions_available = isp_tiles_in_flight;
434 } else {
435 /* Partitions per tile quadrant. */
436 partitions_available = isp_tiles_in_flight * 4U;
437 }
438 }
439 }
440
441 /* Due to limitations of ISP_CTL_PIPE there can only be a difference of
442 * 1 between Phantoms.
443 */
444 if (total_tiles_in_flight > (isp_tiles_in_flight + 1U))
445 total_tiles_in_flight = isp_tiles_in_flight + 1U;
446
447 total_tiles_in_flight += isp_tiles_in_flight;
448 }
449
450 if (PVR_HAS_FEATURE(dev_info, simple_internal_parameter_format) &&
451 PVR_GET_FEATURE_VALUE(dev_info, simple_parameter_format_version, 0) ==
452 2) {
453 /* Limit the ISP tiles in flight to fit into the available USC partition
454 * store.
455 */
456 total_tiles_in_flight = MIN2(total_tiles_in_flight, partitions_available);
457 }
458
459 if (PVR_HAS_FEATURE(dev_info, paired_tiles) && paired_tiles) {
460 total_tiles_in_flight =
461 MIN2(total_tiles_in_flight, partitions_available / 2);
462 }
463
464 pvr_csb_pack (pixel_ctl_out, CR_USC_PIXEL_OUTPUT_CTRL, reg) {
465 if (pixel_width == 1 && usc_min_output_regs == 1) {
466 reg.width = PVRX(CR_PIXEL_WIDTH_1REGISTER);
467 } else if (pixel_width == 2) {
468 reg.width = PVRX(CR_PIXEL_WIDTH_2REGISTERS);
469 } else if (pixel_width == 4) {
470 reg.width = PVRX(CR_PIXEL_WIDTH_4REGISTERS);
471 } else if (pixel_width == 8 &&
472 PVR_HAS_FEATURE(dev_info, eight_output_registers)) {
473 reg.width = PVRX(CR_PIXEL_WIDTH_8REGISTERS);
474 } else if (usc_min_output_regs == 1) {
475 reg.width = PVRX(CR_PIXEL_WIDTH_1REGISTER);
476 } else {
477 reg.width = PVRX(CR_PIXEL_WIDTH_2REGISTERS);
478 }
479
480 if (PVR_HAS_FEATURE(dev_info, usc_pixel_partition_mask)) {
481 /* Setup the partition mask based on the maximum number of
482 * partitions available.
483 */
484 reg.partition_mask = (1 << max_partitions) - 1;
485 } else {
486 reg.enable_4th_partition = true;
487
488 /* Setup the partition mask based on the number of partitions
489 * available.
490 */
491 reg.partition_mask = (1U << partitions_available) - 1U;
492 }
493 }
494
495 pvr_csb_pack (isp_ctl_out, CR_ISP_CTL, reg) {
496 if (PVR_HAS_FEATURE(dev_info, xt_top_infrastructure))
497 reg.pipe_enable = (2 * total_tiles_in_flight) - 1;
498 else
499 reg.pipe_enable = total_tiles_in_flight - 1;
500 }
501 }
502