1 /*
2 * Copyright (c) 2022 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #ifndef INTEL_GENX_STATE_BRW_H
25 #define INTEL_GENX_STATE_BRW_H
26
27 #ifndef GFX_VERx10
28 #error This file should only be included by genX files.
29 #endif
30
31 #include <stdbool.h>
32
33 #include "dev/intel_device_info.h"
34 #include "genxml/gen_macros.h"
35
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39
40 #if GFX_VER >= 7
41
42 static inline void
43 intel_set_ps_dispatch_state(struct GENX(3DSTATE_PS) *ps,
44 const struct intel_device_info *devinfo,
45 const struct brw_wm_prog_data *prog_data,
46 unsigned rasterization_samples,
47 enum intel_msaa_flags msaa_flags)
48 {
49 assert(rasterization_samples != 0);
50
51 bool enable_8 = prog_data->dispatch_8;
52 bool enable_16 = prog_data->dispatch_16;
53 bool enable_32 = prog_data->dispatch_32;
54
55 #if GFX_VER >= 9
56 /* SKL PRMs, Volume 2a: Command Reference: Instructions:
57 * 3DSTATE_PS_BODY::8 Pixel Dispatch Enable:
58 *
59 * "When Render Target Fast Clear Enable is ENABLED or Render Target
60 * Resolve Type = RESOLVE_PARTIAL or RESOLVE_FULL, this bit must be
61 * DISABLED."
62 */
63 if (ps->RenderTargetFastClearEnable ||
64 ps->RenderTargetResolveType == RESOLVE_PARTIAL ||
65 ps->RenderTargetResolveType == RESOLVE_FULL)
66 enable_8 = false;
67 #elif GFX_VER >= 8
68 /* BDW has the same wording as SKL, except some of the fields mentioned
69 * don't exist...
70 */
71 if (ps->RenderTargetFastClearEnable ||
72 ps->RenderTargetResolveEnable)
73 enable_8 = false;
74 #endif
75
76 const bool is_persample_dispatch =
77 brw_wm_prog_data_is_persample(prog_data, msaa_flags);
78
79 if (is_persample_dispatch) {
80 /* TGL PRMs, Volume 2d: Command Reference: Structures:
81 * 3DSTATE_PS_BODY::32 Pixel Dispatch Enable:
82 *
83 * "Must not be enabled when dispatch rate is sample AND NUM_MULTISAMPLES > 1."
84 */
85 if (GFX_VER >= 12 && rasterization_samples > 1)
86 enable_32 = false;
87
88 /* Starting with SandyBridge (where we first get MSAA), the different
89 * pixel dispatch combinations are grouped into classifications A
90 * through F (SNB PRM Vol. 2 Part 1 Section 7.7.1). On most hardware
91 * generations, the only configurations supporting persample dispatch
92 * are those in which only one dispatch width is enabled.
93 *
94 * The Gfx12 hardware spec has a similar dispatch grouping table, but
95 * the following conflicting restriction applies (from the page on
96 * "Structure_3DSTATE_PS_BODY"), so we need to keep the SIMD16 shader:
97 *
98 * "SIMD32 may only be enabled if SIMD16 or (dual)SIMD8 is also
99 * enabled."
100 */
101 if (enable_32 || enable_16)
102 enable_8 = false;
103 if (GFX_VER < 12 && enable_32)
104 enable_16 = false;
105 }
106
107 /* The docs for 3DSTATE_PS::32 Pixel Dispatch Enable say:
108 *
109 * "When NUM_MULTISAMPLES = 16 or FORCE_SAMPLE_COUNT = 16,
110 * SIMD32 Dispatch must not be enabled for PER_PIXEL dispatch
111 * mode."
112 *
113 * 16x MSAA only exists on Gfx9+, so we can skip this on Gfx8.
114 */
115 if (GFX_VER >= 9 && rasterization_samples == 16 && !is_persample_dispatch) {
116 assert(enable_8 || enable_16);
117 enable_32 = false;
118 }
119
120 assert(enable_8 || enable_16 || enable_32 ||
121 (GFX_VER >= 12 && prog_data->dispatch_multi));
122 assert(!prog_data->dispatch_multi ||
123 (GFX_VER >= 12 && !enable_8));
124
125 #if GFX_VER >= 20
126 if (prog_data->dispatch_multi) {
127 ps->Kernel0Enable = true;
128 ps->Kernel0SIMDWidth = (prog_data->dispatch_multi == 32 ?
129 PS_SIMD32 : PS_SIMD16);
130 ps->Kernel0MaximumPolysperThread =
131 prog_data->max_polygons - 1;
132 switch (prog_data->dispatch_multi /
133 prog_data->max_polygons) {
134 case 8:
135 ps->Kernel0PolyPackingPolicy = POLY_PACK8_FIXED;
136 break;
137 case 16:
138 ps->Kernel0PolyPackingPolicy = POLY_PACK16_FIXED;
139 break;
140 default:
141 unreachable("Invalid polygon width");
142 }
143
144 } else if (enable_16) {
145 ps->Kernel0Enable = true;
146 ps->Kernel0SIMDWidth = PS_SIMD16;
147 ps->Kernel0PolyPackingPolicy = POLY_PACK16_FIXED;
148 }
149
150 if (enable_32) {
151 ps->Kernel1Enable = true;
152 ps->Kernel1SIMDWidth = PS_SIMD32;
153
154 } else if (enable_16 && prog_data->dispatch_multi == 16) {
155 ps->Kernel1Enable = true;
156 ps->Kernel1SIMDWidth = PS_SIMD16;
157 }
158 #else
159 ps->_8PixelDispatchEnable = enable_8 ||
160 (GFX_VER == 12 && prog_data->dispatch_multi);
161 ps->_16PixelDispatchEnable = enable_16;
162 ps->_32PixelDispatchEnable = enable_32;
163 #endif
164 }
165
166 #endif
167
168 #if GFX_VERx10 >= 125
169
170 UNUSED static int
preferred_slm_allocation_size(const struct intel_device_info * devinfo)171 preferred_slm_allocation_size(const struct intel_device_info *devinfo)
172 {
173 if (devinfo->platform == INTEL_PLATFORM_LNL && devinfo->revision == 0)
174 return SLM_ENCODES_128K;
175
176 return 0;
177 }
178
179 #endif
180
181 #ifdef __cplusplus
182 }
183 #endif
184
185 #endif /* INTEL_GENX_STATE_BRW_H */
186