1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /** @file brw_fs_generator.cpp
25 *
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
28 */
29
30 #include "brw_eu.h"
31 #include "brw_disasm_info.h"
32 #include "brw_fs.h"
33 #include "brw_cfg.h"
34 #include "dev/intel_debug.h"
35 #include "util/mesa-sha1.h"
36 #include "util/half_float.h"
37
38 static enum brw_reg_file
brw_file_from_reg(fs_reg * reg)39 brw_file_from_reg(fs_reg *reg)
40 {
41 switch (reg->file) {
42 case ARF:
43 return BRW_ARCHITECTURE_REGISTER_FILE;
44 case FIXED_GRF:
45 case VGRF:
46 return BRW_GENERAL_REGISTER_FILE;
47 case IMM:
48 return BRW_IMMEDIATE_VALUE;
49 case BAD_FILE:
50 case ATTR:
51 case UNIFORM:
52 unreachable("not reached");
53 }
54 return BRW_ARCHITECTURE_REGISTER_FILE;
55 }
56
57 static struct brw_reg
brw_reg_from_fs_reg(const struct intel_device_info * devinfo,fs_inst * inst,fs_reg * reg,bool compressed)58 brw_reg_from_fs_reg(const struct intel_device_info *devinfo, fs_inst *inst,
59 fs_reg *reg, bool compressed)
60 {
61 struct brw_reg brw_reg;
62
63 switch (reg->file) {
64 case VGRF:
65 if (reg->stride == 0) {
66 brw_reg = brw_vec1_reg(brw_file_from_reg(reg), reg->nr, 0);
67 } else {
68 /* From the Haswell PRM:
69 *
70 * "VertStride must be used to cross GRF register boundaries. This
71 * rule implies that elements within a 'Width' cannot cross GRF
72 * boundaries."
73 *
74 * The maximum width value that could satisfy this restriction is:
75 */
76 const unsigned reg_width = REG_SIZE / (reg->stride * type_sz(reg->type));
77
78 /* Because the hardware can only split source regions at a whole
79 * multiple of width during decompression (i.e. vertically), clamp
80 * the value obtained above to the physical execution size of a
81 * single decompressed chunk of the instruction:
82 */
83 const unsigned phys_width = compressed ? inst->exec_size / 2 :
84 inst->exec_size;
85
86 const unsigned max_hw_width = 16;
87
88 /* XXX - The equation above is strictly speaking not correct on
89 * hardware that supports unbalanced GRF writes -- On Gfx9+
90 * each decompressed chunk of the instruction may have a
91 * different execution size when the number of components
92 * written to each destination GRF is not the same.
93 */
94 if (reg->stride > 4) {
95 assert(reg != &inst->dst);
96 assert(reg->stride * type_sz(reg->type) <= REG_SIZE);
97 brw_reg = brw_vecn_reg(1, brw_file_from_reg(reg), reg->nr, 0);
98 brw_reg = stride(brw_reg, reg->stride, 1, 0);
99 } else {
100 const unsigned width = MIN3(reg_width, phys_width, max_hw_width);
101 brw_reg = brw_vecn_reg(width, brw_file_from_reg(reg), reg->nr, 0);
102 brw_reg = stride(brw_reg, width * reg->stride, width, reg->stride);
103 }
104 }
105
106 brw_reg = retype(brw_reg, reg->type);
107 brw_reg = byte_offset(brw_reg, reg->offset);
108 brw_reg.abs = reg->abs;
109 brw_reg.negate = reg->negate;
110 break;
111 case ARF:
112 case FIXED_GRF:
113 case IMM:
114 assert(reg->offset == 0);
115 brw_reg = reg->as_brw_reg();
116 break;
117 case BAD_FILE:
118 /* Probably unused. */
119 brw_reg = brw_null_reg();
120 break;
121 case ATTR:
122 case UNIFORM:
123 unreachable("not reached");
124 }
125
126 return brw_reg;
127 }
128
fs_generator(const struct brw_compiler * compiler,const struct brw_compile_params * params,struct brw_stage_prog_data * prog_data,gl_shader_stage stage)129 fs_generator::fs_generator(const struct brw_compiler *compiler,
130 const struct brw_compile_params *params,
131 struct brw_stage_prog_data *prog_data,
132 gl_shader_stage stage)
133
134 : compiler(compiler), params(params),
135 devinfo(compiler->devinfo),
136 prog_data(prog_data), dispatch_width(0),
137 debug_flag(false),
138 shader_name(NULL), stage(stage), mem_ctx(params->mem_ctx)
139 {
140 p = rzalloc(mem_ctx, struct brw_codegen);
141 brw_init_codegen(&compiler->isa, p, mem_ctx);
142 }
143
~fs_generator()144 fs_generator::~fs_generator()
145 {
146 }
147
148 class ip_record : public exec_node {
149 public:
150 DECLARE_RALLOC_CXX_OPERATORS(ip_record)
151
ip_record(int ip)152 ip_record(int ip)
153 {
154 this->ip = ip;
155 }
156
157 int ip;
158 };
159
160 bool
patch_halt_jumps()161 fs_generator::patch_halt_jumps()
162 {
163 if (this->discard_halt_patches.is_empty())
164 return false;
165
166 int scale = brw_jump_scale(p->devinfo);
167
168 /* There is a somewhat strange undocumented requirement of using
169 * HALT, according to the simulator. If some channel has HALTed to
170 * a particular UIP, then by the end of the program, every channel
171 * must have HALTed to that UIP. Furthermore, the tracking is a
172 * stack, so you can't do the final halt of a UIP after starting
173 * halting to a new UIP.
174 *
175 * Symptoms of not emitting this instruction on actual hardware
176 * included GPU hangs and sparkly rendering on the piglit discard
177 * tests.
178 */
179 brw_inst *last_halt = brw_HALT(p);
180 brw_inst_set_uip(p->devinfo, last_halt, 1 * scale);
181 brw_inst_set_jip(p->devinfo, last_halt, 1 * scale);
182
183 int ip = p->nr_insn;
184
185 foreach_in_list(ip_record, patch_ip, &discard_halt_patches) {
186 brw_inst *patch = &p->store[patch_ip->ip];
187
188 assert(brw_inst_opcode(p->isa, patch) == BRW_OPCODE_HALT);
189 /* HALT takes a half-instruction distance from the pre-incremented IP. */
190 brw_inst_set_uip(p->devinfo, patch, (ip - patch_ip->ip) * scale);
191 }
192
193 this->discard_halt_patches.make_empty();
194
195 return true;
196 }
197
198 void
generate_send(fs_inst * inst,struct brw_reg dst,struct brw_reg desc,struct brw_reg ex_desc,struct brw_reg payload,struct brw_reg payload2)199 fs_generator::generate_send(fs_inst *inst,
200 struct brw_reg dst,
201 struct brw_reg desc,
202 struct brw_reg ex_desc,
203 struct brw_reg payload,
204 struct brw_reg payload2)
205 {
206 const bool dst_is_null = dst.file == BRW_ARCHITECTURE_REGISTER_FILE &&
207 dst.nr == BRW_ARF_NULL;
208 const unsigned rlen = dst_is_null ? 0 : inst->size_written / REG_SIZE;
209
210 uint32_t desc_imm = inst->desc |
211 brw_message_desc(devinfo, inst->mlen, rlen, inst->header_size);
212
213 uint32_t ex_desc_imm = inst->ex_desc |
214 brw_message_ex_desc(devinfo, inst->ex_mlen);
215
216 if (ex_desc.file != BRW_IMMEDIATE_VALUE || ex_desc.ud || ex_desc_imm ||
217 inst->send_ex_desc_scratch) {
218 /* If we have any sort of extended descriptor, then we need SENDS. This
219 * also covers the dual-payload case because ex_mlen goes in ex_desc.
220 */
221 brw_send_indirect_split_message(p, inst->sfid, dst, payload, payload2,
222 desc, desc_imm, ex_desc, ex_desc_imm,
223 inst->send_ex_desc_scratch,
224 inst->send_ex_bso, inst->eot);
225 if (inst->check_tdr)
226 brw_inst_set_opcode(p->isa, brw_last_inst,
227 devinfo->ver >= 12 ? BRW_OPCODE_SENDC : BRW_OPCODE_SENDSC);
228 } else {
229 brw_send_indirect_message(p, inst->sfid, dst, payload, desc, desc_imm,
230 inst->eot);
231 if (inst->check_tdr)
232 brw_inst_set_opcode(p->isa, brw_last_inst, BRW_OPCODE_SENDC);
233 }
234 }
235
236 void
generate_fb_read(fs_inst * inst,struct brw_reg dst,struct brw_reg payload)237 fs_generator::generate_fb_read(fs_inst *inst, struct brw_reg dst,
238 struct brw_reg payload)
239 {
240 assert(inst->size_written % REG_SIZE == 0);
241 struct brw_wm_prog_data *prog_data = brw_wm_prog_data(this->prog_data);
242 /* We assume that render targets start at binding table index 0. */
243 const unsigned surf_index = inst->target;
244
245 gfx9_fb_READ(p, dst, payload, surf_index,
246 inst->header_size, inst->size_written / REG_SIZE,
247 prog_data->persample_dispatch);
248 }
249
250 void
generate_mov_indirect(fs_inst * inst,struct brw_reg dst,struct brw_reg reg,struct brw_reg indirect_byte_offset)251 fs_generator::generate_mov_indirect(fs_inst *inst,
252 struct brw_reg dst,
253 struct brw_reg reg,
254 struct brw_reg indirect_byte_offset)
255 {
256 assert(indirect_byte_offset.type == BRW_REGISTER_TYPE_UD);
257 assert(indirect_byte_offset.file == BRW_GENERAL_REGISTER_FILE);
258 assert(!reg.abs && !reg.negate);
259
260 /* Gen12.5 adds the following region restriction:
261 *
262 * "Vx1 and VxH indirect addressing for Float, Half-Float, Double-Float
263 * and Quad-Word data must not be used."
264 *
265 * We require the source and destination types to match so stomp to an
266 * unsigned integer type.
267 */
268 assert(reg.type == dst.type);
269 reg.type = dst.type = brw_reg_type_from_bit_size(type_sz(reg.type) * 8,
270 BRW_REGISTER_TYPE_UD);
271
272 unsigned imm_byte_offset = reg.nr * REG_SIZE + reg.subnr;
273
274 if (indirect_byte_offset.file == BRW_IMMEDIATE_VALUE) {
275 imm_byte_offset += indirect_byte_offset.ud;
276
277 reg.nr = imm_byte_offset / REG_SIZE;
278 reg.subnr = imm_byte_offset % REG_SIZE;
279 if (type_sz(reg.type) > 4 && !devinfo->has_64bit_float) {
280 brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_D, 0),
281 subscript(reg, BRW_REGISTER_TYPE_D, 0));
282 brw_set_default_swsb(p, tgl_swsb_null());
283 brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_D, 1),
284 subscript(reg, BRW_REGISTER_TYPE_D, 1));
285 } else {
286 brw_MOV(p, dst, reg);
287 }
288 } else {
289 /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */
290 struct brw_reg addr = vec8(brw_address_reg(0));
291
292 /* Whether we can use destination dependency control without running the
293 * risk of a hang if an instruction gets shot down.
294 */
295 const bool use_dep_ctrl = !inst->predicate &&
296 inst->exec_size == dispatch_width;
297 brw_inst *insn;
298
299 /* The destination stride of an instruction (in bytes) must be greater
300 * than or equal to the size of the rest of the instruction. Since the
301 * address register is of type UW, we can't use a D-type instruction.
302 * In order to get around this, re retype to UW and use a stride.
303 */
304 indirect_byte_offset =
305 retype(spread(indirect_byte_offset, 2), BRW_REGISTER_TYPE_UW);
306
307 /* There are a number of reasons why we don't use the base offset here.
308 * One reason is that the field is only 9 bits which means we can only
309 * use it to access the first 16 GRFs. Also, from the Haswell PRM
310 * section "Register Region Restrictions":
311 *
312 * "The lower bits of the AddressImmediate must not overflow to
313 * change the register address. The lower 5 bits of Address
314 * Immediate when added to lower 5 bits of address register gives
315 * the sub-register offset. The upper bits of Address Immediate
316 * when added to upper bits of address register gives the register
317 * address. Any overflow from sub-register offset is dropped."
318 *
319 * Since the indirect may cause us to cross a register boundary, this
320 * makes the base offset almost useless. We could try and do something
321 * clever where we use a actual base offset if base_offset % 32 == 0 but
322 * that would mean we were generating different code depending on the
323 * base offset. Instead, for the sake of consistency, we'll just do the
324 * add ourselves. This restriction is only listed in the Haswell PRM
325 * but empirical testing indicates that it applies on all older
326 * generations and is lifted on Broadwell.
327 *
328 * In the end, while base_offset is nice to look at in the generated
329 * code, using it saves us 0 instructions and would require quite a bit
330 * of case-by-case work. It's just not worth it.
331 *
332 * Due to a hardware bug some platforms (particularly Gfx11+) seem to
333 * require the address components of all channels to be valid whether or
334 * not they're active, which causes issues if we use VxH addressing
335 * under non-uniform control-flow. We can easily work around that by
336 * initializing the whole address register with a pipelined NoMask MOV
337 * instruction.
338 */
339 insn = brw_MOV(p, addr, brw_imm_uw(imm_byte_offset));
340 brw_inst_set_mask_control(devinfo, insn, BRW_MASK_DISABLE);
341 brw_inst_set_pred_control(devinfo, insn, BRW_PREDICATE_NONE);
342 if (devinfo->ver >= 12)
343 brw_set_default_swsb(p, tgl_swsb_null());
344 else
345 brw_inst_set_no_dd_clear(devinfo, insn, use_dep_ctrl);
346
347 insn = brw_ADD(p, addr, indirect_byte_offset, brw_imm_uw(imm_byte_offset));
348 if (devinfo->ver >= 12)
349 brw_set_default_swsb(p, tgl_swsb_regdist(1));
350 else
351 brw_inst_set_no_dd_check(devinfo, insn, use_dep_ctrl);
352
353 if (type_sz(reg.type) > 4 &&
354 (intel_device_info_is_9lp(devinfo) ||
355 !devinfo->has_64bit_float || devinfo->verx10 >= 125)) {
356 /* IVB has an issue (which we found empirically) where it reads two
357 * address register components per channel for indirectly addressed
358 * 64-bit sources.
359 *
360 * From the Cherryview PRM Vol 7. "Register Region Restrictions":
361 *
362 * "When source or destination datatype is 64b or operation is
363 * integer DWord multiply, indirect addressing must not be used."
364 *
365 * To work around both of these, we do two integer MOVs insead of one
366 * 64-bit MOV. Because no double value should ever cross a register
367 * boundary, it's safe to use the immediate offset in the indirect
368 * here to handle adding 4 bytes to the offset and avoid the extra
369 * ADD to the register file.
370 */
371 brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_D, 0),
372 retype(brw_VxH_indirect(0, 0), BRW_REGISTER_TYPE_D));
373 brw_set_default_swsb(p, tgl_swsb_null());
374 brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_D, 1),
375 retype(brw_VxH_indirect(0, 4), BRW_REGISTER_TYPE_D));
376 } else {
377 struct brw_reg ind_src = brw_VxH_indirect(0, 0);
378
379 brw_MOV(p, dst, retype(ind_src, reg.type));
380 }
381 }
382 }
383
384 void
generate_shuffle(fs_inst * inst,struct brw_reg dst,struct brw_reg src,struct brw_reg idx)385 fs_generator::generate_shuffle(fs_inst *inst,
386 struct brw_reg dst,
387 struct brw_reg src,
388 struct brw_reg idx)
389 {
390 assert(src.file == BRW_GENERAL_REGISTER_FILE);
391 assert(!src.abs && !src.negate);
392
393 /* Ivy bridge has some strange behavior that makes this a real pain to
394 * implement for 64-bit values so we just don't bother.
395 */
396 assert(devinfo->has_64bit_float || type_sz(src.type) <= 4);
397
398 /* Gen12.5 adds the following region restriction:
399 *
400 * "Vx1 and VxH indirect addressing for Float, Half-Float, Double-Float
401 * and Quad-Word data must not be used."
402 *
403 * We require the source and destination types to match so stomp to an
404 * unsigned integer type.
405 */
406 assert(src.type == dst.type);
407 src.type = dst.type = brw_reg_type_from_bit_size(type_sz(src.type) * 8,
408 BRW_REGISTER_TYPE_UD);
409
410 /* Because we're using the address register, we're limited to 8-wide
411 * execution on gfx7. On gfx8, we're limited to 16-wide by the address
412 * register file and 8-wide for 64-bit types. We could try and make this
413 * instruction splittable higher up in the compiler but that gets weird
414 * because it reads all of the channels regardless of execution size. It's
415 * easier just to split it here.
416 */
417 const unsigned lower_width =
418 element_sz(src) > 4 || element_sz(dst) > 4 ? 8 :
419 MIN2(16, inst->exec_size);
420
421 brw_set_default_exec_size(p, cvt(lower_width) - 1);
422 for (unsigned group = 0; group < inst->exec_size; group += lower_width) {
423 brw_set_default_group(p, group);
424
425 if ((src.vstride == 0 && src.hstride == 0) ||
426 idx.file == BRW_IMMEDIATE_VALUE) {
427 /* Trivial, the source is already uniform or the index is a constant.
428 * We will typically not get here if the optimizer is doing its job,
429 * but asserting would be mean.
430 */
431 const unsigned i = idx.file == BRW_IMMEDIATE_VALUE ? idx.ud : 0;
432 struct brw_reg group_src = stride(suboffset(src, i), 0, 1, 0);
433 struct brw_reg group_dst = suboffset(dst, group << (dst.hstride - 1));
434 brw_MOV(p, group_dst, group_src);
435 } else {
436 /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */
437 struct brw_reg addr = vec8(brw_address_reg(0));
438
439 struct brw_reg group_idx = suboffset(idx, group);
440
441 if (lower_width == 8 && group_idx.width == BRW_WIDTH_16) {
442 /* Things get grumpy if the register is too wide. */
443 group_idx.width--;
444 group_idx.vstride--;
445 }
446
447 assert(type_sz(group_idx.type) <= 4);
448 if (type_sz(group_idx.type) == 4) {
449 /* The destination stride of an instruction (in bytes) must be
450 * greater than or equal to the size of the rest of the
451 * instruction. Since the address register is of type UW, we
452 * can't use a D-type instruction. In order to get around this,
453 * re retype to UW and use a stride.
454 */
455 group_idx = retype(spread(group_idx, 2), BRW_REGISTER_TYPE_W);
456 }
457
458 uint32_t src_start_offset = src.nr * REG_SIZE + src.subnr;
459
460 /* From the Haswell PRM:
461 *
462 * "When a sequence of NoDDChk and NoDDClr are used, the last
463 * instruction that completes the scoreboard clear must have a
464 * non-zero execution mask. This means, if any kind of predication
465 * can change the execution mask or channel enable of the last
466 * instruction, the optimization must be avoided. This is to
467 * avoid instructions being shot down the pipeline when no writes
468 * are required."
469 *
470 * Whenever predication is enabled or the instructions being emitted
471 * aren't the full width, it's possible that it will be run with zero
472 * channels enabled so we can't use dependency control without
473 * running the risk of a hang if an instruction gets shot down.
474 */
475 const bool use_dep_ctrl = !inst->predicate &&
476 lower_width == dispatch_width;
477 brw_inst *insn;
478
479 /* Due to a hardware bug some platforms (particularly Gfx11+) seem
480 * to require the address components of all channels to be valid
481 * whether or not they're active, which causes issues if we use VxH
482 * addressing under non-uniform control-flow. We can easily work
483 * around that by initializing the whole address register with a
484 * pipelined NoMask MOV instruction.
485 */
486 insn = brw_MOV(p, addr, brw_imm_uw(src_start_offset));
487 brw_inst_set_mask_control(devinfo, insn, BRW_MASK_DISABLE);
488 brw_inst_set_pred_control(devinfo, insn, BRW_PREDICATE_NONE);
489 if (devinfo->ver >= 12)
490 brw_set_default_swsb(p, tgl_swsb_null());
491 else
492 brw_inst_set_no_dd_clear(devinfo, insn, use_dep_ctrl);
493
494 /* Take into account the component size and horizontal stride. */
495 assert(src.vstride == src.hstride + src.width);
496 insn = brw_SHL(p, addr, group_idx,
497 brw_imm_uw(util_logbase2(type_sz(src.type)) +
498 src.hstride - 1));
499 if (devinfo->ver >= 12)
500 brw_set_default_swsb(p, tgl_swsb_regdist(1));
501 else
502 brw_inst_set_no_dd_check(devinfo, insn, use_dep_ctrl);
503
504 /* Add on the register start offset */
505 brw_ADD(p, addr, addr, brw_imm_uw(src_start_offset));
506 brw_MOV(p, suboffset(dst, group << (dst.hstride - 1)),
507 retype(brw_VxH_indirect(0, 0), src.type));
508 }
509
510 brw_set_default_swsb(p, tgl_swsb_null());
511 }
512 }
513
514 void
generate_quad_swizzle(const fs_inst * inst,struct brw_reg dst,struct brw_reg src,unsigned swiz)515 fs_generator::generate_quad_swizzle(const fs_inst *inst,
516 struct brw_reg dst, struct brw_reg src,
517 unsigned swiz)
518 {
519 /* Requires a quad. */
520 assert(inst->exec_size >= 4);
521
522 if (src.file == BRW_IMMEDIATE_VALUE ||
523 has_scalar_region(src)) {
524 /* The value is uniform across all channels */
525 brw_MOV(p, dst, src);
526
527 } else if (devinfo->ver < 11 && type_sz(src.type) == 4) {
528 /* This only works on 8-wide 32-bit values */
529 assert(inst->exec_size == 8);
530 assert(src.hstride == BRW_HORIZONTAL_STRIDE_1);
531 assert(src.vstride == src.width + 1);
532 brw_set_default_access_mode(p, BRW_ALIGN_16);
533 struct brw_reg swiz_src = stride(src, 4, 4, 1);
534 swiz_src.swizzle = swiz;
535 brw_MOV(p, dst, swiz_src);
536
537 } else {
538 assert(src.hstride == BRW_HORIZONTAL_STRIDE_1);
539 assert(src.vstride == src.width + 1);
540 const struct brw_reg src_0 = suboffset(src, BRW_GET_SWZ(swiz, 0));
541
542 switch (swiz) {
543 case BRW_SWIZZLE_XXXX:
544 case BRW_SWIZZLE_YYYY:
545 case BRW_SWIZZLE_ZZZZ:
546 case BRW_SWIZZLE_WWWW:
547 brw_MOV(p, dst, stride(src_0, 4, 4, 0));
548 break;
549
550 case BRW_SWIZZLE_XXZZ:
551 case BRW_SWIZZLE_YYWW:
552 brw_MOV(p, dst, stride(src_0, 2, 2, 0));
553 break;
554
555 case BRW_SWIZZLE_XYXY:
556 case BRW_SWIZZLE_ZWZW:
557 assert(inst->exec_size == 4);
558 brw_MOV(p, dst, stride(src_0, 0, 2, 1));
559 break;
560
561 default:
562 assert(inst->force_writemask_all);
563 brw_set_default_exec_size(p, cvt(inst->exec_size / 4) - 1);
564
565 for (unsigned c = 0; c < 4; c++) {
566 brw_inst *insn = brw_MOV(
567 p, stride(suboffset(dst, c),
568 4 * inst->dst.stride, 1, 4 * inst->dst.stride),
569 stride(suboffset(src, BRW_GET_SWZ(swiz, c)), 4, 1, 0));
570
571 if (devinfo->ver < 12) {
572 brw_inst_set_no_dd_clear(devinfo, insn, c < 3);
573 brw_inst_set_no_dd_check(devinfo, insn, c > 0);
574 }
575
576 brw_set_default_swsb(p, tgl_swsb_null());
577 }
578
579 break;
580 }
581 }
582 }
583
584 void
generate_cs_terminate(fs_inst * inst,struct brw_reg payload)585 fs_generator::generate_cs_terminate(fs_inst *inst, struct brw_reg payload)
586 {
587 struct brw_inst *insn;
588
589 insn = brw_next_insn(p, BRW_OPCODE_SEND);
590
591 brw_set_dest(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_UW));
592 brw_set_src0(p, insn, retype(payload, BRW_REGISTER_TYPE_UW));
593 if (devinfo->ver < 12)
594 brw_set_src1(p, insn, brw_imm_ud(0u));
595
596 /* For XeHP and newer send a message to the message gateway to terminate a
597 * compute shader. For older devices, a message is sent to the thread
598 * spawner.
599 */
600 if (devinfo->verx10 >= 125)
601 brw_inst_set_sfid(devinfo, insn, BRW_SFID_MESSAGE_GATEWAY);
602 else
603 brw_inst_set_sfid(devinfo, insn, BRW_SFID_THREAD_SPAWNER);
604 brw_inst_set_mlen(devinfo, insn, 1);
605 brw_inst_set_rlen(devinfo, insn, 0);
606 brw_inst_set_eot(devinfo, insn, inst->eot);
607 brw_inst_set_header_present(devinfo, insn, false);
608
609 brw_inst_set_ts_opcode(devinfo, insn, 0); /* Dereference resource */
610
611 if (devinfo->ver < 11) {
612 brw_inst_set_ts_request_type(devinfo, insn, 0); /* Root thread */
613
614 /* Note that even though the thread has a URB resource associated with it,
615 * we set the "do not dereference URB" bit, because the URB resource is
616 * managed by the fixed-function unit, so it will free it automatically.
617 */
618 brw_inst_set_ts_resource_select(devinfo, insn, 1); /* Do not dereference URB */
619 }
620
621 brw_inst_set_mask_control(devinfo, insn, BRW_MASK_DISABLE);
622 }
623
624 void
generate_barrier(fs_inst *,struct brw_reg src)625 fs_generator::generate_barrier(fs_inst *, struct brw_reg src)
626 {
627 brw_barrier(p, src);
628 if (devinfo->ver >= 12) {
629 brw_set_default_swsb(p, tgl_swsb_null());
630 brw_SYNC(p, TGL_SYNC_BAR);
631 } else {
632 brw_WAIT(p);
633 }
634 }
635
636 bool
generate_linterp(fs_inst * inst,struct brw_reg dst,struct brw_reg * src)637 fs_generator::generate_linterp(fs_inst *inst,
638 struct brw_reg dst, struct brw_reg *src)
639 {
640 /* PLN reads:
641 * / in SIMD16 \
642 * -----------------------------------
643 * | src1+0 | src1+1 | src1+2 | src1+3 |
644 * |-----------------------------------|
645 * |(x0, x1)|(y0, y1)|(x2, x3)|(y2, y3)|
646 * -----------------------------------
647 */
648 struct brw_reg delta_x = src[0];
649 struct brw_reg interp = src[1];
650
651 /* nir_lower_interpolation() will do the lowering to MAD instructions for
652 * us on gfx11+
653 */
654 assert(devinfo->ver < 11);
655 assert(devinfo->has_pln);
656
657 brw_PLN(p, dst, interp, delta_x);
658 return false;
659 }
660
661 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
662 * looking like:
663 *
664 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
665 *
666 * Ideally, we want to produce:
667 *
668 * DDX DDY
669 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
670 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
671 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
672 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
673 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
674 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
675 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
676 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
677 *
678 * and add another set of two more subspans if in 16-pixel dispatch mode.
679 *
680 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
681 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
682 * pair. But the ideal approximation may impose a huge performance cost on
683 * sample_d. On at least Haswell, sample_d instruction does some
684 * optimizations if the same LOD is used for all pixels in the subspan.
685 *
686 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
687 * appropriate swizzling.
688 */
689 void
generate_ddx(const fs_inst * inst,struct brw_reg dst,struct brw_reg src)690 fs_generator::generate_ddx(const fs_inst *inst,
691 struct brw_reg dst, struct brw_reg src)
692 {
693 unsigned vstride, width;
694
695 if (inst->opcode == FS_OPCODE_DDX_FINE) {
696 /* produce accurate derivatives */
697 vstride = BRW_VERTICAL_STRIDE_2;
698 width = BRW_WIDTH_2;
699 } else {
700 /* replicate the derivative at the top-left pixel to other pixels */
701 vstride = BRW_VERTICAL_STRIDE_4;
702 width = BRW_WIDTH_4;
703 }
704
705 struct brw_reg src0 = byte_offset(src, type_sz(src.type));;
706 struct brw_reg src1 = src;
707
708 src0.vstride = vstride;
709 src0.width = width;
710 src0.hstride = BRW_HORIZONTAL_STRIDE_0;
711 src1.vstride = vstride;
712 src1.width = width;
713 src1.hstride = BRW_HORIZONTAL_STRIDE_0;
714
715 brw_ADD(p, dst, src0, negate(src1));
716 }
717
718 /* The negate_value boolean is used to negate the derivative computation for
719 * FBOs, since they place the origin at the upper left instead of the lower
720 * left.
721 */
722 void
generate_ddy(const fs_inst * inst,struct brw_reg dst,struct brw_reg src)723 fs_generator::generate_ddy(const fs_inst *inst,
724 struct brw_reg dst, struct brw_reg src)
725 {
726 const uint32_t type_size = type_sz(src.type);
727
728 if (inst->opcode == FS_OPCODE_DDY_FINE) {
729 /* produce accurate derivatives.
730 *
731 * From the Broadwell PRM, Volume 7 (3D-Media-GPGPU)
732 * "Register Region Restrictions", Section "1. Special Restrictions":
733 *
734 * "In Align16 mode, the channel selects and channel enables apply to
735 * a pair of half-floats, because these parameters are defined for
736 * DWord elements ONLY. This is applicable when both source and
737 * destination are half-floats."
738 *
739 * So for half-float operations we use the Gfx11+ Align1 path. CHV
740 * inherits its FP16 hardware from SKL, so it is not affected.
741 */
742 if (devinfo->ver >= 11) {
743 src = stride(src, 0, 2, 1);
744
745 brw_push_insn_state(p);
746 brw_set_default_exec_size(p, BRW_EXECUTE_4);
747 for (uint32_t g = 0; g < inst->exec_size; g += 4) {
748 brw_set_default_group(p, inst->group + g);
749 brw_ADD(p, byte_offset(dst, g * type_size),
750 negate(byte_offset(src, g * type_size)),
751 byte_offset(src, (g + 2) * type_size));
752 brw_set_default_swsb(p, tgl_swsb_null());
753 }
754 brw_pop_insn_state(p);
755 } else {
756 struct brw_reg src0 = stride(src, 4, 4, 1);
757 struct brw_reg src1 = stride(src, 4, 4, 1);
758 src0.swizzle = BRW_SWIZZLE_XYXY;
759 src1.swizzle = BRW_SWIZZLE_ZWZW;
760
761 brw_push_insn_state(p);
762 brw_set_default_access_mode(p, BRW_ALIGN_16);
763 brw_ADD(p, dst, negate(src0), src1);
764 brw_pop_insn_state(p);
765 }
766 } else {
767 /* replicate the derivative at the top-left pixel to other pixels */
768 struct brw_reg src0 = byte_offset(stride(src, 4, 4, 0), 0 * type_size);
769 struct brw_reg src1 = byte_offset(stride(src, 4, 4, 0), 2 * type_size);
770
771 brw_ADD(p, dst, negate(src0), src1);
772 }
773 }
774
775 void
generate_halt(fs_inst *)776 fs_generator::generate_halt(fs_inst *)
777 {
778 /* This HALT will be patched up at FB write time to point UIP at the end of
779 * the program, and at brw_uip_jip() JIP will be set to the end of the
780 * current block (or the program).
781 */
782 this->discard_halt_patches.push_tail(new(mem_ctx) ip_record(p->nr_insn));
783 brw_HALT(p);
784 }
785
786 /* The A32 messages take a buffer base address in header.5:[31:0] (See
787 * MH1_A32_PSM for typed messages or MH_A32_GO for byte/dword scattered
788 * and OWord block messages in the SKL PRM Vol. 2d for more details.)
789 * Unfortunately, there are a number of subtle differences:
790 *
791 * For the block read/write messages:
792 *
793 * - We always stomp header.2 to fill in the actual scratch address (in
794 * units of OWORDs) so we don't care what's in there.
795 *
796 * - They rely on per-thread scratch space value in header.3[3:0] to do
797 * bounds checking so that needs to be valid. The upper bits of
798 * header.3 are ignored, though, so we can copy all of g0.3.
799 *
800 * - They ignore header.5[9:0] and assumes the address is 1KB aligned.
801 *
802 *
803 * For the byte/dword scattered read/write messages:
804 *
805 * - We want header.2 to be zero because that gets added to the per-channel
806 * offset in the non-header portion of the message.
807 *
808 * - Contrary to what the docs claim, they don't do any bounds checking so
809 * the value of header.3[3:0] doesn't matter.
810 *
811 * - They consider all of header.5 for the base address and header.5[9:0]
812 * are not ignored. This means that we can't copy g0.5 verbatim because
813 * g0.5[9:0] contains the FFTID on most platforms. Instead, we have to
814 * use an AND to mask off the bottom 10 bits.
815 *
816 *
817 * For block messages, just copying g0 gives a valid header because all the
818 * garbage gets ignored except for header.2 which we stomp as part of message
819 * setup. For byte/dword scattered messages, we can just zero out the header
820 * and copy over the bits we need from g0.5. This opcode, however, tries to
821 * satisfy the requirements of both by starting with 0 and filling out the
822 * information required by either set of opcodes.
823 */
824 void
generate_scratch_header(fs_inst * inst,struct brw_reg dst)825 fs_generator::generate_scratch_header(fs_inst *inst, struct brw_reg dst)
826 {
827 assert(inst->exec_size == 8 && inst->force_writemask_all);
828 assert(dst.file == BRW_GENERAL_REGISTER_FILE);
829
830 dst.type = BRW_REGISTER_TYPE_UD;
831
832 brw_inst *insn = brw_MOV(p, dst, brw_imm_ud(0));
833 if (devinfo->ver >= 12)
834 brw_set_default_swsb(p, tgl_swsb_null());
835 else
836 brw_inst_set_no_dd_clear(p->devinfo, insn, true);
837
838 /* Copy the per-thread scratch space size from g0.3[3:0] */
839 brw_set_default_exec_size(p, BRW_EXECUTE_1);
840 insn = brw_AND(p, suboffset(dst, 3),
841 retype(brw_vec1_grf(0, 3), BRW_REGISTER_TYPE_UD),
842 brw_imm_ud(INTEL_MASK(3, 0)));
843 if (devinfo->ver < 12) {
844 brw_inst_set_no_dd_clear(p->devinfo, insn, true);
845 brw_inst_set_no_dd_check(p->devinfo, insn, true);
846 }
847
848 /* Copy the scratch base address from g0.5[31:10] */
849 insn = brw_AND(p, suboffset(dst, 5),
850 retype(brw_vec1_grf(0, 5), BRW_REGISTER_TYPE_UD),
851 brw_imm_ud(INTEL_MASK(31, 10)));
852 if (devinfo->ver < 12)
853 brw_inst_set_no_dd_check(p->devinfo, insn, true);
854 }
855
856 void
enable_debug(const char * shader_name)857 fs_generator::enable_debug(const char *shader_name)
858 {
859 debug_flag = true;
860 this->shader_name = shader_name;
861 }
862
863 static gfx12_systolic_depth
translate_systolic_depth(unsigned d)864 translate_systolic_depth(unsigned d)
865 {
866 /* Could also return (ffs(d) - 1) & 3. */
867 switch (d) {
868 case 2: return BRW_SYSTOLIC_DEPTH_2;
869 case 4: return BRW_SYSTOLIC_DEPTH_4;
870 case 8: return BRW_SYSTOLIC_DEPTH_8;
871 case 16: return BRW_SYSTOLIC_DEPTH_16;
872 default: unreachable("Invalid systolic depth.");
873 }
874 }
875
876 int
generate_code(const cfg_t * cfg,int dispatch_width,struct shader_stats shader_stats,const brw::performance & perf,struct brw_compile_stats * stats,unsigned max_polygons)877 fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
878 struct shader_stats shader_stats,
879 const brw::performance &perf,
880 struct brw_compile_stats *stats,
881 unsigned max_polygons)
882 {
883 /* align to 64 byte boundary. */
884 brw_realign(p, 64);
885
886 this->dispatch_width = dispatch_width;
887
888 int start_offset = p->next_insn_offset;
889
890 int loop_count = 0, send_count = 0, nop_count = 0, sync_nop_count = 0;
891 bool is_accum_used = false;
892
893 struct disasm_info *disasm_info = disasm_initialize(p->isa, cfg);
894
895 foreach_block_and_inst (block, fs_inst, inst, cfg) {
896 if (inst->opcode == SHADER_OPCODE_UNDEF)
897 continue;
898
899 struct brw_reg src[4], dst;
900 unsigned int last_insn_offset = p->next_insn_offset;
901 bool multiple_instructions_emitted = false;
902 tgl_swsb swsb = inst->sched;
903
904 /* From the Broadwell PRM, Volume 7, "3D-Media-GPGPU", in the
905 * "Register Region Restrictions" section: for BDW, SKL:
906 *
907 * "A POW/FDIV operation must not be followed by an instruction
908 * that requires two destination registers."
909 *
910 * The documentation is often lacking annotations for Atom parts,
911 * and empirically this affects CHV as well.
912 */
913 if (devinfo->ver <= 9 &&
914 p->nr_insn > 1 &&
915 brw_inst_opcode(p->isa, brw_last_inst) == BRW_OPCODE_MATH &&
916 brw_inst_math_function(devinfo, brw_last_inst) == BRW_MATH_FUNCTION_POW &&
917 inst->dst.component_size(inst->exec_size) > REG_SIZE) {
918 brw_NOP(p);
919 last_insn_offset = p->next_insn_offset;
920
921 /* In order to avoid spurious instruction count differences when the
922 * instruction schedule changes, keep track of the number of inserted
923 * NOPs.
924 */
925 nop_count++;
926 }
927
928 /* Wa_14010017096:
929 *
930 * Clear accumulator register before end of thread.
931 */
932 if (inst->eot && is_accum_used &&
933 intel_needs_workaround(devinfo, 14010017096)) {
934 brw_set_default_exec_size(p, BRW_EXECUTE_16);
935 brw_set_default_group(p, 0);
936 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
937 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
938 brw_set_default_flag_reg(p, 0, 0);
939 brw_set_default_swsb(p, tgl_swsb_src_dep(swsb));
940 brw_MOV(p, brw_acc_reg(8), brw_imm_f(0.0f));
941 last_insn_offset = p->next_insn_offset;
942 swsb = tgl_swsb_dst_dep(swsb, 1);
943 }
944
945 if (!is_accum_used && !inst->eot) {
946 is_accum_used = inst->writes_accumulator_implicitly(devinfo) ||
947 inst->dst.is_accumulator();
948 }
949
950 /* Wa_14013672992:
951 *
952 * Always use @1 SWSB for EOT.
953 */
954 if (inst->eot && intel_needs_workaround(devinfo, 14013672992)) {
955 if (tgl_swsb_src_dep(swsb).mode) {
956 brw_set_default_exec_size(p, BRW_EXECUTE_1);
957 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
958 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
959 brw_set_default_flag_reg(p, 0, 0);
960 brw_set_default_swsb(p, tgl_swsb_src_dep(swsb));
961 brw_SYNC(p, TGL_SYNC_NOP);
962 last_insn_offset = p->next_insn_offset;
963 }
964
965 swsb = tgl_swsb_dst_dep(swsb, 1);
966 }
967
968 if (unlikely(debug_flag))
969 disasm_annotate(disasm_info, inst, p->next_insn_offset);
970
971 /* If the instruction writes to more than one register, it needs to be
972 * explicitly marked as compressed on Gen <= 5. On Gen >= 6 the
973 * hardware figures out by itself what the right compression mode is,
974 * but we still need to know whether the instruction is compressed to
975 * set up the source register regions appropriately.
976 *
977 * XXX - This is wrong for instructions that write a single register but
978 * read more than one which should strictly speaking be treated as
979 * compressed. For instructions that don't write any registers it
980 * relies on the destination being a null register of the correct
981 * type and regioning so the instruction is considered compressed
982 * or not accordingly.
983 */
984 const bool compressed =
985 inst->dst.component_size(inst->exec_size) > REG_SIZE;
986
987 if (devinfo->ver >= 20 && inst->group % 8 != 0) {
988 assert(inst->force_writemask_all);
989 assert(!inst->predicate && !inst->conditional_mod);
990 assert(!inst->writes_accumulator_implicitly(devinfo) &&
991 !inst->reads_accumulator_implicitly());
992 assert(inst->opcode != SHADER_OPCODE_SEL_EXEC);
993 brw_set_default_group(p, 0);
994 } else {
995 brw_set_default_group(p, inst->group);
996 }
997
998 for (unsigned int i = 0; i < inst->sources; i++) {
999 src[i] = brw_reg_from_fs_reg(devinfo, inst,
1000 &inst->src[i], compressed);
1001 /* The accumulator result appears to get used for the
1002 * conditional modifier generation. When negating a UD
1003 * value, there is a 33rd bit generated for the sign in the
1004 * accumulator value, so now you can't check, for example,
1005 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1006 */
1007 assert(!inst->conditional_mod ||
1008 inst->src[i].type != BRW_REGISTER_TYPE_UD ||
1009 !inst->src[i].negate);
1010 }
1011 dst = brw_reg_from_fs_reg(devinfo, inst,
1012 &inst->dst, compressed);
1013
1014 brw_set_default_access_mode(p, BRW_ALIGN_1);
1015 brw_set_default_predicate_control(p, inst->predicate);
1016 brw_set_default_predicate_inverse(p, inst->predicate_inverse);
1017 /* On gfx7 and above, hardware automatically adds the group onto the
1018 * flag subregister number.
1019 */
1020 const unsigned flag_subreg = inst->flag_subreg;
1021 brw_set_default_flag_reg(p, flag_subreg / 2, flag_subreg % 2);
1022 brw_set_default_saturate(p, inst->saturate);
1023 brw_set_default_mask_control(p, inst->force_writemask_all);
1024 if (devinfo->ver >= 20 && inst->writes_accumulator) {
1025 assert(inst->dst.is_accumulator() ||
1026 inst->opcode == BRW_OPCODE_ADDC ||
1027 inst->opcode == BRW_OPCODE_MACH ||
1028 inst->opcode == BRW_OPCODE_SUBB);
1029 } else {
1030 brw_set_default_acc_write_control(p, inst->writes_accumulator);
1031 }
1032 brw_set_default_swsb(p, swsb);
1033
1034 unsigned exec_size = inst->exec_size;
1035
1036 brw_set_default_exec_size(p, cvt(exec_size) - 1);
1037
1038 assert(inst->force_writemask_all || inst->exec_size >= 4);
1039 assert(inst->force_writemask_all || inst->group % inst->exec_size == 0);
1040 assert(inst->mlen <= BRW_MAX_MSG_LENGTH * reg_unit(devinfo));
1041
1042 switch (inst->opcode) {
1043 case BRW_OPCODE_SYNC:
1044 assert(src[0].file == BRW_IMMEDIATE_VALUE);
1045 brw_SYNC(p, tgl_sync_function(src[0].ud));
1046
1047 if (tgl_sync_function(src[0].ud) == TGL_SYNC_NOP)
1048 ++sync_nop_count;
1049
1050 break;
1051 case BRW_OPCODE_MOV:
1052 brw_MOV(p, dst, src[0]);
1053 break;
1054 case BRW_OPCODE_ADD:
1055 brw_ADD(p, dst, src[0], src[1]);
1056 break;
1057 case BRW_OPCODE_MUL:
1058 brw_MUL(p, dst, src[0], src[1]);
1059 break;
1060 case BRW_OPCODE_AVG:
1061 brw_AVG(p, dst, src[0], src[1]);
1062 break;
1063 case BRW_OPCODE_MACH:
1064 brw_MACH(p, dst, src[0], src[1]);
1065 break;
1066
1067 case BRW_OPCODE_DP4A:
1068 assert(devinfo->ver >= 12);
1069 brw_DP4A(p, dst, src[0], src[1], src[2]);
1070 break;
1071
1072 case BRW_OPCODE_LINE:
1073 brw_LINE(p, dst, src[0], src[1]);
1074 break;
1075
1076 case BRW_OPCODE_DPAS:
1077 assert(devinfo->verx10 >= 125);
1078 brw_DPAS(p, translate_systolic_depth(inst->sdepth), inst->rcount,
1079 dst, src[0], src[1], src[2]);
1080 break;
1081
1082 case BRW_OPCODE_MAD:
1083 if (devinfo->ver < 10)
1084 brw_set_default_access_mode(p, BRW_ALIGN_16);
1085 brw_MAD(p, dst, src[0], src[1], src[2]);
1086 break;
1087
1088 case BRW_OPCODE_LRP:
1089 assert(devinfo->ver <= 10);
1090 if (devinfo->ver < 10)
1091 brw_set_default_access_mode(p, BRW_ALIGN_16);
1092 brw_LRP(p, dst, src[0], src[1], src[2]);
1093 break;
1094
1095 case BRW_OPCODE_ADD3:
1096 assert(devinfo->verx10 >= 125);
1097 brw_ADD3(p, dst, src[0], src[1], src[2]);
1098 break;
1099
1100 case BRW_OPCODE_FRC:
1101 brw_FRC(p, dst, src[0]);
1102 break;
1103 case BRW_OPCODE_RNDD:
1104 brw_RNDD(p, dst, src[0]);
1105 break;
1106 case BRW_OPCODE_RNDE:
1107 brw_RNDE(p, dst, src[0]);
1108 break;
1109 case BRW_OPCODE_RNDZ:
1110 brw_RNDZ(p, dst, src[0]);
1111 break;
1112
1113 case BRW_OPCODE_AND:
1114 brw_AND(p, dst, src[0], src[1]);
1115 break;
1116 case BRW_OPCODE_OR:
1117 brw_OR(p, dst, src[0], src[1]);
1118 break;
1119 case BRW_OPCODE_XOR:
1120 brw_XOR(p, dst, src[0], src[1]);
1121 break;
1122 case BRW_OPCODE_NOT:
1123 brw_NOT(p, dst, src[0]);
1124 break;
1125 case BRW_OPCODE_ASR:
1126 brw_ASR(p, dst, src[0], src[1]);
1127 break;
1128 case BRW_OPCODE_SHR:
1129 brw_SHR(p, dst, src[0], src[1]);
1130 break;
1131 case BRW_OPCODE_SHL:
1132 brw_SHL(p, dst, src[0], src[1]);
1133 break;
1134 case BRW_OPCODE_ROL:
1135 assert(devinfo->ver >= 11);
1136 assert(src[0].type == dst.type);
1137 brw_ROL(p, dst, src[0], src[1]);
1138 break;
1139 case BRW_OPCODE_ROR:
1140 assert(devinfo->ver >= 11);
1141 assert(src[0].type == dst.type);
1142 brw_ROR(p, dst, src[0], src[1]);
1143 break;
1144 case BRW_OPCODE_CMP:
1145 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1146 break;
1147 case BRW_OPCODE_CMPN:
1148 brw_CMPN(p, dst, inst->conditional_mod, src[0], src[1]);
1149 break;
1150 case BRW_OPCODE_SEL:
1151 brw_SEL(p, dst, src[0], src[1]);
1152 break;
1153 case BRW_OPCODE_CSEL:
1154 if (devinfo->ver < 10)
1155 brw_set_default_access_mode(p, BRW_ALIGN_16);
1156 brw_CSEL(p, dst, src[0], src[1], src[2]);
1157 break;
1158 case BRW_OPCODE_BFREV:
1159 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
1160 retype(src[0], BRW_REGISTER_TYPE_UD));
1161 break;
1162 case BRW_OPCODE_FBH:
1163 brw_FBH(p, retype(dst, src[0].type), src[0]);
1164 break;
1165 case BRW_OPCODE_FBL:
1166 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD),
1167 retype(src[0], BRW_REGISTER_TYPE_UD));
1168 break;
1169 case BRW_OPCODE_LZD:
1170 brw_LZD(p, dst, src[0]);
1171 break;
1172 case BRW_OPCODE_CBIT:
1173 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD),
1174 retype(src[0], BRW_REGISTER_TYPE_UD));
1175 break;
1176 case BRW_OPCODE_ADDC:
1177 brw_ADDC(p, dst, src[0], src[1]);
1178 break;
1179 case BRW_OPCODE_SUBB:
1180 brw_SUBB(p, dst, src[0], src[1]);
1181 break;
1182 case BRW_OPCODE_MAC:
1183 brw_MAC(p, dst, src[0], src[1]);
1184 break;
1185
1186 case BRW_OPCODE_BFE:
1187 if (devinfo->ver < 10)
1188 brw_set_default_access_mode(p, BRW_ALIGN_16);
1189 brw_BFE(p, dst, src[0], src[1], src[2]);
1190 break;
1191
1192 case BRW_OPCODE_BFI1:
1193 brw_BFI1(p, dst, src[0], src[1]);
1194 break;
1195 case BRW_OPCODE_BFI2:
1196 if (devinfo->ver < 10)
1197 brw_set_default_access_mode(p, BRW_ALIGN_16);
1198 brw_BFI2(p, dst, src[0], src[1], src[2]);
1199 break;
1200
1201 case BRW_OPCODE_IF:
1202 /* Can't have embedded compare (was only allowed on Gfx6). */
1203 assert(inst->src[0].file == BAD_FILE);
1204 brw_IF(p, brw_get_default_exec_size(p));
1205 break;
1206
1207 case BRW_OPCODE_ELSE:
1208 brw_ELSE(p);
1209 break;
1210 case BRW_OPCODE_ENDIF:
1211 brw_ENDIF(p);
1212 break;
1213
1214 case BRW_OPCODE_DO:
1215 brw_DO(p, brw_get_default_exec_size(p));
1216 break;
1217
1218 case BRW_OPCODE_BREAK:
1219 brw_BREAK(p);
1220 break;
1221 case BRW_OPCODE_CONTINUE:
1222 brw_CONT(p);
1223 break;
1224
1225 case BRW_OPCODE_WHILE:
1226 brw_WHILE(p);
1227 loop_count++;
1228 break;
1229
1230 case SHADER_OPCODE_RCP:
1231 case SHADER_OPCODE_RSQ:
1232 case SHADER_OPCODE_SQRT:
1233 case SHADER_OPCODE_EXP2:
1234 case SHADER_OPCODE_LOG2:
1235 case SHADER_OPCODE_SIN:
1236 case SHADER_OPCODE_COS:
1237 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1238 assert(inst->mlen == 0);
1239 gfx6_math(p, dst, brw_math_function(inst->opcode),
1240 src[0], brw_null_reg());
1241 break;
1242 case SHADER_OPCODE_INT_QUOTIENT:
1243 case SHADER_OPCODE_INT_REMAINDER:
1244 case SHADER_OPCODE_POW:
1245 assert(devinfo->verx10 < 125);
1246 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1247 assert(inst->mlen == 0);
1248 assert(inst->opcode == SHADER_OPCODE_POW || inst->exec_size == 8);
1249 gfx6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
1250 break;
1251 case FS_OPCODE_LINTERP:
1252 multiple_instructions_emitted = generate_linterp(inst, dst, src);
1253 break;
1254 case FS_OPCODE_PIXEL_X:
1255 assert(src[0].type == BRW_REGISTER_TYPE_UW);
1256 assert(src[1].type == BRW_REGISTER_TYPE_UW);
1257 src[0].subnr = 0 * type_sz(src[0].type);
1258 if (src[1].file == BRW_IMMEDIATE_VALUE) {
1259 assert(src[1].ud == 0);
1260 brw_MOV(p, dst, stride(src[0], 8, 4, 1));
1261 } else {
1262 /* Coarse pixel case */
1263 brw_ADD(p, dst, stride(src[0], 8, 4, 1), src[1]);
1264 }
1265 break;
1266 case FS_OPCODE_PIXEL_Y:
1267 assert(src[0].type == BRW_REGISTER_TYPE_UW);
1268 assert(src[1].type == BRW_REGISTER_TYPE_UW);
1269 src[0].subnr = 4 * type_sz(src[0].type);
1270 if (src[1].file == BRW_IMMEDIATE_VALUE) {
1271 assert(src[1].ud == 0);
1272 brw_MOV(p, dst, stride(src[0], 8, 4, 1));
1273 } else {
1274 /* Coarse pixel case */
1275 brw_ADD(p, dst, stride(src[0], 8, 4, 1), src[1]);
1276 }
1277 break;
1278
1279 case SHADER_OPCODE_SEND:
1280 generate_send(inst, dst, src[0], src[1], src[2],
1281 inst->ex_mlen > 0 ? src[3] : brw_null_reg());
1282 send_count++;
1283 break;
1284
1285 case FS_OPCODE_DDX_COARSE:
1286 case FS_OPCODE_DDX_FINE:
1287 generate_ddx(inst, dst, src[0]);
1288 break;
1289 case FS_OPCODE_DDY_COARSE:
1290 case FS_OPCODE_DDY_FINE:
1291 generate_ddy(inst, dst, src[0]);
1292 break;
1293
1294 case SHADER_OPCODE_SCRATCH_HEADER:
1295 generate_scratch_header(inst, dst);
1296 break;
1297
1298 case SHADER_OPCODE_MOV_INDIRECT:
1299 generate_mov_indirect(inst, dst, src[0], src[1]);
1300 break;
1301
1302 case SHADER_OPCODE_MOV_RELOC_IMM:
1303 assert(src[0].file == BRW_IMMEDIATE_VALUE);
1304 brw_MOV_reloc_imm(p, dst, dst.type, src[0].ud);
1305 break;
1306
1307 case FS_OPCODE_FB_READ:
1308 generate_fb_read(inst, dst, src[0]);
1309 send_count++;
1310 break;
1311
1312 case BRW_OPCODE_HALT:
1313 generate_halt(inst);
1314 break;
1315
1316 case SHADER_OPCODE_INTERLOCK:
1317 case SHADER_OPCODE_MEMORY_FENCE: {
1318 assert(src[1].file == BRW_IMMEDIATE_VALUE);
1319 assert(src[2].file == BRW_IMMEDIATE_VALUE);
1320
1321 const enum opcode send_op = inst->opcode == SHADER_OPCODE_INTERLOCK ?
1322 BRW_OPCODE_SENDC : BRW_OPCODE_SEND;
1323
1324 brw_memory_fence(p, dst, src[0], send_op,
1325 brw_message_target(inst->sfid),
1326 inst->desc,
1327 /* commit_enable */ src[1].ud,
1328 /* bti */ src[2].ud);
1329 send_count++;
1330 break;
1331 }
1332
1333 case FS_OPCODE_SCHEDULING_FENCE:
1334 if (inst->sources == 0 && swsb.regdist == 0 &&
1335 swsb.mode == TGL_SBID_NULL) {
1336 if (unlikely(debug_flag))
1337 disasm_info->use_tail = true;
1338 break;
1339 }
1340
1341 if (devinfo->ver >= 12) {
1342 /* Use the available SWSB information to stall. A single SYNC is
1343 * sufficient since if there were multiple dependencies, the
1344 * scoreboard algorithm already injected other SYNCs before this
1345 * instruction.
1346 */
1347 brw_SYNC(p, TGL_SYNC_NOP);
1348 } else {
1349 for (unsigned i = 0; i < inst->sources; i++) {
1350 /* Emit a MOV to force a stall until the instruction producing the
1351 * registers finishes.
1352 */
1353 brw_MOV(p, retype(brw_null_reg(), BRW_REGISTER_TYPE_UW),
1354 retype(src[i], BRW_REGISTER_TYPE_UW));
1355 }
1356
1357 if (inst->sources > 1)
1358 multiple_instructions_emitted = true;
1359 }
1360
1361 break;
1362
1363 case SHADER_OPCODE_FIND_LIVE_CHANNEL:
1364 case SHADER_OPCODE_FIND_LAST_LIVE_CHANNEL:
1365 case SHADER_OPCODE_LOAD_LIVE_CHANNELS:
1366 unreachable("Should be lowered by lower_find_live_channel()");
1367 break;
1368
1369 case FS_OPCODE_LOAD_LIVE_CHANNELS: {
1370 assert(inst->force_writemask_all && inst->group == 0);
1371 assert(inst->dst.file == BAD_FILE);
1372 brw_set_default_exec_size(p, BRW_EXECUTE_1);
1373 brw_MOV(p, retype(brw_flag_subreg(inst->flag_subreg),
1374 BRW_REGISTER_TYPE_UD),
1375 retype(brw_mask_reg(0), BRW_REGISTER_TYPE_UD));
1376 break;
1377 }
1378 case SHADER_OPCODE_BROADCAST:
1379 assert(inst->force_writemask_all);
1380 brw_broadcast(p, dst, src[0], src[1]);
1381 break;
1382
1383 case SHADER_OPCODE_SHUFFLE:
1384 generate_shuffle(inst, dst, src[0], src[1]);
1385 break;
1386
1387 case SHADER_OPCODE_SEL_EXEC:
1388 assert(inst->force_writemask_all);
1389 assert(devinfo->has_64bit_float || type_sz(dst.type) <= 4);
1390 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1391 brw_MOV(p, dst, src[1]);
1392 brw_set_default_mask_control(p, BRW_MASK_ENABLE);
1393 brw_set_default_swsb(p, tgl_swsb_null());
1394 brw_MOV(p, dst, src[0]);
1395 break;
1396
1397 case SHADER_OPCODE_QUAD_SWIZZLE:
1398 assert(src[1].file == BRW_IMMEDIATE_VALUE);
1399 assert(src[1].type == BRW_REGISTER_TYPE_UD);
1400 generate_quad_swizzle(inst, dst, src[0], src[1].ud);
1401 break;
1402
1403 case SHADER_OPCODE_CLUSTER_BROADCAST: {
1404 assert((devinfo->platform != INTEL_PLATFORM_CHV &&
1405 !intel_device_info_is_9lp(devinfo) &&
1406 devinfo->has_64bit_float) || type_sz(src[0].type) <= 4);
1407 assert(!src[0].negate && !src[0].abs);
1408 assert(src[1].file == BRW_IMMEDIATE_VALUE);
1409 assert(src[1].type == BRW_REGISTER_TYPE_UD);
1410 assert(src[2].file == BRW_IMMEDIATE_VALUE);
1411 assert(src[2].type == BRW_REGISTER_TYPE_UD);
1412 const unsigned component = src[1].ud;
1413 const unsigned cluster_size = src[2].ud;
1414 assert(inst->src[0].file != ARF && inst->src[0].file != FIXED_GRF);
1415 const unsigned s = inst->src[0].stride;
1416 unsigned vstride = cluster_size * s;
1417 unsigned width = cluster_size;
1418
1419 /* The maximum exec_size is 32, but the maximum width is only 16. */
1420 if (inst->exec_size == width) {
1421 vstride = 0;
1422 width = 1;
1423 }
1424
1425 struct brw_reg strided = stride(suboffset(src[0], component * s),
1426 vstride, width, 0);
1427 brw_MOV(p, dst, strided);
1428 break;
1429 }
1430
1431 case SHADER_OPCODE_HALT_TARGET:
1432 /* This is the place where the final HALT needs to be inserted if
1433 * we've emitted any discards. If not, this will emit no code.
1434 */
1435 if (!patch_halt_jumps()) {
1436 if (unlikely(debug_flag)) {
1437 disasm_info->use_tail = true;
1438 }
1439 }
1440 break;
1441
1442 case CS_OPCODE_CS_TERMINATE:
1443 generate_cs_terminate(inst, src[0]);
1444 send_count++;
1445 break;
1446
1447 case SHADER_OPCODE_BARRIER:
1448 generate_barrier(inst, src[0]);
1449 send_count++;
1450 break;
1451
1452 case SHADER_OPCODE_RND_MODE: {
1453 assert(src[0].file == BRW_IMMEDIATE_VALUE);
1454 /*
1455 * Changes the floating point rounding mode updating the control
1456 * register field defined at cr0.0[5-6] bits.
1457 */
1458 enum brw_rnd_mode mode =
1459 (enum brw_rnd_mode) (src[0].d << BRW_CR0_RND_MODE_SHIFT);
1460 brw_float_controls_mode(p, mode, BRW_CR0_RND_MODE_MASK);
1461 }
1462 break;
1463
1464 case SHADER_OPCODE_FLOAT_CONTROL_MODE:
1465 assert(src[0].file == BRW_IMMEDIATE_VALUE);
1466 assert(src[1].file == BRW_IMMEDIATE_VALUE);
1467 brw_float_controls_mode(p, src[0].d, src[1].d);
1468 break;
1469
1470 case SHADER_OPCODE_READ_SR_REG:
1471 if (devinfo->ver >= 12) {
1472 /* There is a SWSB restriction that requires that any time sr0 is
1473 * accessed both the instruction doing the access and the next one
1474 * have SWSB set to RegDist(1).
1475 */
1476 if (brw_get_default_swsb(p).mode != TGL_SBID_NULL)
1477 brw_SYNC(p, TGL_SYNC_NOP);
1478 assert(src[0].file == BRW_IMMEDIATE_VALUE);
1479 brw_set_default_swsb(p, tgl_swsb_regdist(1));
1480 brw_MOV(p, dst, brw_sr0_reg(src[0].ud));
1481 brw_set_default_swsb(p, tgl_swsb_regdist(1));
1482 brw_AND(p, dst, dst, brw_imm_ud(0xffffffff));
1483 } else {
1484 brw_MOV(p, dst, brw_sr0_reg(src[0].ud));
1485 }
1486 break;
1487
1488 default:
1489 unreachable("Unsupported opcode");
1490
1491 case SHADER_OPCODE_LOAD_PAYLOAD:
1492 unreachable("Should be lowered by lower_load_payload()");
1493 }
1494
1495 if (multiple_instructions_emitted)
1496 continue;
1497
1498 if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
1499 assert(p->next_insn_offset == last_insn_offset + 16 ||
1500 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
1501 "emitting more than 1 instruction");
1502
1503 brw_inst *last = &p->store[last_insn_offset / 16];
1504
1505 if (inst->conditional_mod)
1506 brw_inst_set_cond_modifier(p->devinfo, last, inst->conditional_mod);
1507 if (devinfo->ver < 12) {
1508 brw_inst_set_no_dd_clear(p->devinfo, last, inst->no_dd_clear);
1509 brw_inst_set_no_dd_check(p->devinfo, last, inst->no_dd_check);
1510 }
1511 }
1512
1513 /* When enabled, insert sync NOP after every instruction and make sure
1514 * that current instruction depends on the previous instruction.
1515 */
1516 if (INTEL_DEBUG(DEBUG_SWSB_STALL) && devinfo->ver >= 12) {
1517 brw_set_default_swsb(p, tgl_swsb_regdist(1));
1518 brw_SYNC(p, TGL_SYNC_NOP);
1519 }
1520 }
1521
1522 brw_set_uip_jip(p, start_offset);
1523
1524 /* end of program sentinel */
1525 disasm_new_inst_group(disasm_info, p->next_insn_offset);
1526
1527 /* `send_count` explicitly does not include spills or fills, as we'd
1528 * like to use it as a metric for intentional memory access or other
1529 * shared function use. Otherwise, subtle changes to scheduling or
1530 * register allocation could cause it to fluctuate wildly - and that
1531 * effect is already counted in spill/fill counts.
1532 */
1533 send_count -= shader_stats.spill_count;
1534 send_count -= shader_stats.fill_count;
1535
1536 #ifndef NDEBUG
1537 bool validated =
1538 #else
1539 if (unlikely(debug_flag))
1540 #endif
1541 brw_validate_instructions(&compiler->isa, p->store,
1542 start_offset,
1543 p->next_insn_offset,
1544 disasm_info);
1545
1546 int before_size = p->next_insn_offset - start_offset;
1547 brw_compact_instructions(p, start_offset, disasm_info);
1548 int after_size = p->next_insn_offset - start_offset;
1549
1550 bool dump_shader_bin = brw_should_dump_shader_bin();
1551 unsigned char sha1[21];
1552 char sha1buf[41];
1553
1554 if (unlikely(debug_flag || dump_shader_bin)) {
1555 _mesa_sha1_compute(p->store + start_offset / sizeof(brw_inst),
1556 after_size, sha1);
1557 _mesa_sha1_format(sha1buf, sha1);
1558 }
1559
1560 if (unlikely(dump_shader_bin))
1561 brw_dump_shader_bin(p->store, start_offset, p->next_insn_offset,
1562 sha1buf);
1563
1564 if (unlikely(debug_flag)) {
1565 fprintf(stderr, "Native code for %s (src_hash 0x%08x) (sha1 %s)\n"
1566 "SIMD%d shader: %d instructions. %d loops. %u cycles. "
1567 "%d:%d spills:fills, %u sends, "
1568 "scheduled with mode %s. "
1569 "Promoted %u constants. "
1570 "Compacted %d to %d bytes (%.0f%%)\n",
1571 shader_name, params->source_hash, sha1buf,
1572 dispatch_width, before_size / 16,
1573 loop_count, perf.latency,
1574 shader_stats.spill_count,
1575 shader_stats.fill_count,
1576 send_count,
1577 shader_stats.scheduler_mode,
1578 shader_stats.promoted_constants,
1579 before_size, after_size,
1580 100.0f * (before_size - after_size) / before_size);
1581
1582 /* overriding the shader makes disasm_info invalid */
1583 if (!brw_try_override_assembly(p, start_offset, sha1buf)) {
1584 dump_assembly(p->store, start_offset, p->next_insn_offset,
1585 disasm_info, perf.block_latency);
1586 } else {
1587 fprintf(stderr, "Successfully overrode shader with sha1 %s\n\n", sha1buf);
1588 }
1589 }
1590 ralloc_free(disasm_info);
1591 #ifndef NDEBUG
1592 if (!validated && !debug_flag) {
1593 fprintf(stderr,
1594 "Validation failed. Rerun with INTEL_DEBUG=shaders to get more information.\n");
1595 }
1596 #endif
1597 assert(validated);
1598
1599 brw_shader_debug_log(compiler, params->log_data,
1600 "%s SIMD%d shader: %d inst, %d loops, %u cycles, "
1601 "%d:%d spills:fills, %u sends, "
1602 "scheduled with mode %s, "
1603 "Promoted %u constants, "
1604 "compacted %d to %d bytes.\n",
1605 _mesa_shader_stage_to_abbrev(stage),
1606 dispatch_width,
1607 before_size / 16 - nop_count - sync_nop_count,
1608 loop_count, perf.latency,
1609 shader_stats.spill_count,
1610 shader_stats.fill_count,
1611 send_count,
1612 shader_stats.scheduler_mode,
1613 shader_stats.promoted_constants,
1614 before_size, after_size);
1615 if (stats) {
1616 stats->dispatch_width = dispatch_width;
1617 stats->max_polygons = max_polygons;
1618 stats->max_dispatch_width = dispatch_width;
1619 stats->instructions = before_size / 16 - nop_count - sync_nop_count;
1620 stats->sends = send_count;
1621 stats->loops = loop_count;
1622 stats->cycles = perf.latency;
1623 stats->spills = shader_stats.spill_count;
1624 stats->fills = shader_stats.fill_count;
1625 stats->max_live_registers = shader_stats.max_register_pressure;
1626 }
1627
1628 return start_offset;
1629 }
1630
1631 void
add_const_data(void * data,unsigned size)1632 fs_generator::add_const_data(void *data, unsigned size)
1633 {
1634 assert(prog_data->const_data_size == 0);
1635 if (size > 0) {
1636 prog_data->const_data_size = size;
1637 prog_data->const_data_offset = brw_append_data(p, data, size, 32);
1638 }
1639 }
1640
1641 void
add_resume_sbt(unsigned num_resume_shaders,uint64_t * sbt)1642 fs_generator::add_resume_sbt(unsigned num_resume_shaders, uint64_t *sbt)
1643 {
1644 assert(brw_shader_stage_is_bindless(stage));
1645 struct brw_bs_prog_data *bs_prog_data = brw_bs_prog_data(prog_data);
1646 if (num_resume_shaders > 0) {
1647 bs_prog_data->resume_sbt_offset =
1648 brw_append_data(p, sbt, num_resume_shaders * sizeof(uint64_t), 32);
1649 for (unsigned i = 0; i < num_resume_shaders; i++) {
1650 size_t offset = bs_prog_data->resume_sbt_offset + i * sizeof(*sbt);
1651 assert(offset <= UINT32_MAX);
1652 brw_add_reloc(p, BRW_SHADER_RELOC_SHADER_START_OFFSET,
1653 BRW_SHADER_RELOC_TYPE_U32,
1654 (uint32_t)offset, (uint32_t)sbt[i]);
1655 }
1656 }
1657 }
1658
1659 const unsigned *
get_assembly()1660 fs_generator::get_assembly()
1661 {
1662 prog_data->relocs = brw_get_shader_relocs(p, &prog_data->num_relocs);
1663
1664 return brw_get_program(p, &prog_data->program_size);
1665 }
1666