1 %{
2 /*
3 * Copyright © 2018 Intel Corporation
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include <stdio.h>
26 #include <stdlib.h>
27 #include <string.h>
28 #include <strings.h>
29 #include "brw_asm.h"
30
31 #undef yyerror
32 #ifdef YYBYACC
33 struct YYLTYPE;
34 void yyerror (struct YYLTYPE *, char *);
35 #else
36 void yyerror (char *);
37 #endif
38
39 #undef ALIGN16
40
41 #define YYLTYPE YYLTYPE
42 typedef struct YYLTYPE
43 {
44 int first_line;
45 int first_column;
46 int last_line;
47 int last_column;
48 } YYLTYPE;
49
50 enum message_level {
51 WARN,
52 ERROR,
53 };
54
55 int yydebug = 1;
56
57 static void
message(enum message_level level,YYLTYPE * location,const char * fmt,...)58 message(enum message_level level, YYLTYPE *location,
59 const char *fmt, ...)
60 {
61 static const char *level_str[] = { "warning", "error" };
62 va_list args;
63
64 if (location)
65 fprintf(stderr, "%s:%d:%d: %s: ", input_filename,
66 location->first_line,
67 location->first_column, level_str[level]);
68 else
69 fprintf(stderr, "%s:%s: ", input_filename, level_str[level]);
70
71 va_start(args, fmt);
72 vfprintf(stderr, fmt, args);
73 va_end(args);
74 }
75
76 #define warn(flag, l, fmt, ...) \
77 do { \
78 if (warning_flags & WARN_ ## flag) \
79 message(WARN, l, fmt, ## __VA_ARGS__); \
80 } while (0)
81
82 #define error(l, fmt, ...) \
83 do { \
84 message(ERROR, l, fmt, ## __VA_ARGS__); \
85 } while (0)
86
87 static bool
isPowerofTwo(unsigned int x)88 isPowerofTwo(unsigned int x)
89 {
90 return x && (!(x & (x - 1)));
91 }
92
93 static struct brw_reg
set_direct_src_operand(struct brw_reg * reg,int type)94 set_direct_src_operand(struct brw_reg *reg, int type)
95 {
96 return brw_reg(reg->file,
97 reg->nr,
98 reg->subnr,
99 0, // negate
100 0, // abs
101 type,
102 0, // vstride
103 0, // width
104 0, // hstride
105 BRW_SWIZZLE_NOOP,
106 WRITEMASK_XYZW);
107 }
108
109 static void
i965_asm_unary_instruction(int opcode,struct brw_codegen * p,struct brw_reg dest,struct brw_reg src0)110 i965_asm_unary_instruction(int opcode, struct brw_codegen *p,
111 struct brw_reg dest, struct brw_reg src0)
112 {
113 switch (opcode) {
114 case BRW_OPCODE_BFREV:
115 brw_BFREV(p, dest, src0);
116 break;
117 case BRW_OPCODE_CBIT:
118 brw_CBIT(p, dest, src0);
119 break;
120 case BRW_OPCODE_MOV:
121 brw_MOV(p, dest, src0);
122 break;
123 case BRW_OPCODE_FBL:
124 brw_FBL(p, dest, src0);
125 break;
126 case BRW_OPCODE_FRC:
127 brw_FRC(p, dest, src0);
128 break;
129 case BRW_OPCODE_FBH:
130 brw_FBH(p, dest, src0);
131 break;
132 case BRW_OPCODE_NOT:
133 brw_NOT(p, dest, src0);
134 break;
135 case BRW_OPCODE_RNDE:
136 brw_RNDE(p, dest, src0);
137 break;
138 case BRW_OPCODE_RNDZ:
139 brw_RNDZ(p, dest, src0);
140 break;
141 case BRW_OPCODE_RNDD:
142 brw_RNDD(p, dest, src0);
143 break;
144 case BRW_OPCODE_LZD:
145 brw_LZD(p, dest, src0);
146 break;
147 case BRW_OPCODE_RNDU:
148 fprintf(stderr, "Opcode BRW_OPCODE_RNDU unhandled\n");
149 break;
150 default:
151 fprintf(stderr, "Unsupported unary opcode\n");
152 }
153 }
154
155 static void
i965_asm_binary_instruction(int opcode,struct brw_codegen * p,struct brw_reg dest,struct brw_reg src0,struct brw_reg src1)156 i965_asm_binary_instruction(int opcode,
157 struct brw_codegen *p,
158 struct brw_reg dest,
159 struct brw_reg src0,
160 struct brw_reg src1)
161 {
162 switch (opcode) {
163 case BRW_OPCODE_ADDC:
164 brw_ADDC(p, dest, src0, src1);
165 break;
166 case BRW_OPCODE_BFI1:
167 brw_BFI1(p, dest, src0, src1);
168 break;
169 case BRW_OPCODE_DP2:
170 brw_DP2(p, dest, src0, src1);
171 break;
172 case BRW_OPCODE_DP3:
173 brw_DP3(p, dest, src0, src1);
174 break;
175 case BRW_OPCODE_DP4:
176 brw_DP4(p, dest, src0, src1);
177 break;
178 case BRW_OPCODE_DPH:
179 brw_DPH(p, dest, src0, src1);
180 break;
181 case BRW_OPCODE_LINE:
182 brw_LINE(p, dest, src0, src1);
183 break;
184 case BRW_OPCODE_MAC:
185 brw_MAC(p, dest, src0, src1);
186 break;
187 case BRW_OPCODE_MACH:
188 brw_MACH(p, dest, src0, src1);
189 break;
190 case BRW_OPCODE_PLN:
191 brw_PLN(p, dest, src0, src1);
192 break;
193 case BRW_OPCODE_ROL:
194 brw_ROL(p, dest, src0, src1);
195 break;
196 case BRW_OPCODE_ROR:
197 brw_ROR(p, dest, src0, src1);
198 break;
199 case BRW_OPCODE_SAD2:
200 fprintf(stderr, "Opcode BRW_OPCODE_SAD2 unhandled\n");
201 break;
202 case BRW_OPCODE_SADA2:
203 fprintf(stderr, "Opcode BRW_OPCODE_SADA2 unhandled\n");
204 break;
205 case BRW_OPCODE_SUBB:
206 brw_SUBB(p, dest, src0, src1);
207 break;
208 case BRW_OPCODE_ADD:
209 brw_ADD(p, dest, src0, src1);
210 break;
211 case BRW_OPCODE_CMP:
212 /* Third parameter is conditional modifier
213 * which gets updated later
214 */
215 brw_CMP(p, dest, 0, src0, src1);
216 break;
217 case BRW_OPCODE_AND:
218 brw_AND(p, dest, src0, src1);
219 break;
220 case BRW_OPCODE_ASR:
221 brw_ASR(p, dest, src0, src1);
222 break;
223 case BRW_OPCODE_AVG:
224 brw_AVG(p, dest, src0, src1);
225 break;
226 case BRW_OPCODE_OR:
227 brw_OR(p, dest, src0, src1);
228 break;
229 case BRW_OPCODE_SEL:
230 brw_SEL(p, dest, src0, src1);
231 break;
232 case BRW_OPCODE_SHL:
233 brw_SHL(p, dest, src0, src1);
234 break;
235 case BRW_OPCODE_SHR:
236 brw_SHR(p, dest, src0, src1);
237 break;
238 case BRW_OPCODE_XOR:
239 brw_XOR(p, dest, src0, src1);
240 break;
241 case BRW_OPCODE_MUL:
242 brw_MUL(p, dest, src0, src1);
243 break;
244 default:
245 fprintf(stderr, "Unsupported binary opcode\n");
246 }
247 }
248
249 static void
i965_asm_ternary_instruction(int opcode,struct brw_codegen * p,struct brw_reg dest,struct brw_reg src0,struct brw_reg src1,struct brw_reg src2)250 i965_asm_ternary_instruction(int opcode,
251 struct brw_codegen *p,
252 struct brw_reg dest,
253 struct brw_reg src0,
254 struct brw_reg src1,
255 struct brw_reg src2)
256 {
257 switch (opcode) {
258 case BRW_OPCODE_MAD:
259 brw_MAD(p, dest, src0, src1, src2);
260 break;
261 case BRW_OPCODE_CSEL:
262 brw_CSEL(p, dest, src0, src1, src2);
263 break;
264 case BRW_OPCODE_LRP:
265 brw_LRP(p, dest, src0, src1, src2);
266 break;
267 case BRW_OPCODE_BFE:
268 brw_BFE(p, dest, src0, src1, src2);
269 break;
270 case BRW_OPCODE_BFI2:
271 brw_BFI2(p, dest, src0, src1, src2);
272 break;
273 case BRW_OPCODE_DP4A:
274 brw_DP4A(p, dest, src0, src1, src2);
275 break;
276 case BRW_OPCODE_ADD3:
277 brw_ADD3(p, dest, src0, src1, src2);
278 break;
279 default:
280 fprintf(stderr, "Unsupported ternary opcode\n");
281 }
282 }
283
284 static void
i965_asm_set_instruction_options(struct brw_codegen * p,struct options options)285 i965_asm_set_instruction_options(struct brw_codegen *p,
286 struct options options)
287 {
288 brw_inst_set_access_mode(p->devinfo, brw_last_inst,
289 options.access_mode);
290 brw_inst_set_mask_control(p->devinfo, brw_last_inst,
291 options.mask_control);
292 if (p->devinfo->ver < 12) {
293 brw_inst_set_thread_control(p->devinfo, brw_last_inst,
294 options.thread_control);
295 brw_inst_set_no_dd_check(p->devinfo, brw_last_inst,
296 options.no_dd_check);
297 brw_inst_set_no_dd_clear(p->devinfo, brw_last_inst,
298 options.no_dd_clear);
299 } else {
300 brw_inst_set_swsb(p->devinfo, brw_last_inst,
301 tgl_swsb_encode(p->devinfo, options.depinfo));
302 }
303 brw_inst_set_debug_control(p->devinfo, brw_last_inst,
304 options.debug_control);
305 brw_inst_set_acc_wr_control(p->devinfo, brw_last_inst,
306 options.acc_wr_control);
307 brw_inst_set_cmpt_control(p->devinfo, brw_last_inst,
308 options.compaction);
309 }
310
311 static void
add_label(struct brw_codegen * p,const char * label_name,enum instr_label_type type)312 add_label(struct brw_codegen *p, const char* label_name, enum instr_label_type type)
313 {
314 if (!label_name) {
315 return;
316 }
317
318 struct instr_label *label = rzalloc(p->mem_ctx, struct instr_label);
319
320 label->name = ralloc_strdup(p->mem_ctx, label_name);
321 label->offset = p->next_insn_offset;
322 label->type = type;
323
324 list_addtail(&label->link, &instr_labels);
325 }
326
327 %}
328
329 %locations
330
331 %start ROOT
332
333 %union {
334 char *string;
335 double number;
336 int integer;
337 unsigned long long int llint;
338 struct brw_reg reg;
339 enum brw_reg_type reg_type;
340 struct brw_codegen *program;
341 struct predicate predicate;
342 struct condition condition;
343 struct options options;
344 struct instoption instoption;
345 struct msgdesc msgdesc;
346 struct tgl_swsb depinfo;
347 brw_inst *instruction;
348 }
349
350 %token ABS
351 %token COLON
352 %token COMMA
353 %token DOT
354 %token LANGLE RANGLE
355 %token LCURLY RCURLY
356 %token LPAREN RPAREN
357 %token LSQUARE RSQUARE
358 %token PLUS MINUS
359 %token SEMICOLON
360 %token ASSIGN
361
362 /* datatypes */
363 %token <integer> TYPE_B TYPE_UB
364 %token <integer> TYPE_W TYPE_UW
365 %token <integer> TYPE_D TYPE_UD
366 %token <integer> TYPE_Q TYPE_UQ
367 %token <integer> TYPE_V TYPE_UV
368 %token <integer> TYPE_F TYPE_HF
369 %token <integer> TYPE_DF TYPE_NF
370 %token <integer> TYPE_VF
371
372 /* label */
373 %token <string> JUMP_LABEL
374 %token <string> JUMP_LABEL_TARGET
375
376 /* opcodes */
377 %token <integer> ADD ADD3 ADDC AND ASR AVG
378 %token <integer> BFE BFI1 BFI2 BFB BFREV BRC BRD BREAK
379 %token <integer> CALL CALLA CASE CBIT CMP CMPN CONT CSEL
380 %token <integer> DIM DO DPAS DPASW DP2 DP3 DP4 DP4A DPH
381 %token <integer> ELSE ENDIF FBH FBL FORK FRC
382 %token <integer> GOTO
383 %token <integer> HALT
384 %token <integer> IF ILLEGAL
385 %token <integer> JMPI JOIN
386 %token <integer> LINE LRP LZD
387 %token <integer> MAC MACH MAD MADM MOV MOVI MUL MREST MSAVE
388 %token <integer> NENOP NOP NOT
389 %token <integer> OR
390 %token <integer> PLN POP PUSH
391 %token <integer> RET RNDD RNDE RNDU RNDZ ROL ROR
392 %token <integer> SAD2 SADA2 SEL SENDS SENDSC SHL SHR SMOV SUBB SYNC
393 %token <integer> SEND_GFX4 SENDC_GFX4 SEND_GFX12 SENDC_GFX12
394 %token <integer> WAIT WHILE
395 %token <integer> XOR
396
397 /* extended math functions */
398 %token <integer> COS EXP FDIV INV INVM INTDIV INTDIVMOD INTMOD LOG POW RSQ
399 %token <integer> RSQRTM SIN SINCOS SQRT
400
401 /* sync instruction */
402 %token <integer> ALLRD ALLWR FENCE BAR HOST
403 %type <integer> sync_function
404 %type <reg> sync_arg
405
406 /* shared functions for send */
407 %token CONST CRE DATA DP_DATA_1 GATEWAY MATH PIXEL_INTERP READ RENDER SAMPLER
408 %token THREAD_SPAWNER URB VME WRITE DP_SAMPLER RT_ACCEL SLM TGM UGM
409
410 /* message details for send */
411 %token MSGDESC_BEGIN SRC1_LEN EX_BSO MSGDESC_END
412 %type <msgdesc> msgdesc msgdesc_parts;
413
414 /* Conditional modifiers */
415 %token <integer> EQUAL GREATER GREATER_EQUAL LESS LESS_EQUAL NOT_EQUAL
416 %token <integer> NOT_ZERO OVERFLOW UNORDERED ZERO
417
418 /* register Access Modes */
419 %token ALIGN1 ALIGN16
420
421 /* accumulator write control */
422 %token ACCWREN
423
424 /* compaction control */
425 %token CMPTCTRL
426
427 /* mask control (WeCtrl) */
428 %token WECTRL
429
430 /* debug control */
431 %token BREAKPOINT
432
433 /* dependency control */
434 %token NODDCLR NODDCHK
435
436 /* end of thread */
437 %token EOT
438
439 /* mask control */
440 %token MASK_DISABLE;
441
442 /* predicate control */
443 %token <integer> ANYV ALLV ANY2H ALL2H ANY4H ALL4H ANY8H ALL8H ANY16H ALL16H
444 %token <integer> ANY32H ALL32H
445
446 /* round instructions */
447 %token <integer> ROUND_INCREMENT
448
449 /* staturation */
450 %token SATURATE
451
452 /* thread control */
453 %token ATOMIC SWITCH
454
455 /* quater control */
456 %token QTR_2Q QTR_3Q QTR_4Q QTR_2H QTR_2N QTR_3N QTR_4N QTR_5N
457 %token QTR_6N QTR_7N QTR_8N
458
459 /* channels */
460 %token <integer> X Y Z W
461
462 /* reg files */
463 %token GENREGFILE
464
465 /* vertical stride in register region */
466 %token VxH
467
468 /* register type */
469 %token <integer> GENREG ADDRREG ACCREG FLAGREG NOTIFYREG STATEREG
470 %token <integer> CONTROLREG IPREG PERFORMANCEREG THREADREG CHANNELENABLEREG
471 %token <integer> MASKREG
472
473 %token <integer> INTEGER
474 %token <llint> LONG
475 %token NULL_TOKEN
476
477 %nonassoc SUBREGNUM
478 %left PLUS MINUS
479 %nonassoc DOT
480 %nonassoc EMPTYEXECSIZE
481 %nonassoc LPAREN
482
483 %type <integer> execsize exp
484 %type <llint> exp2
485
486 /* predicate control */
487 %type <integer> predctrl predstate
488 %type <predicate> predicate
489
490 /* conditional modifier */
491 %type <condition> cond_mod
492 %type <integer> condModifiers
493
494 /* instruction options */
495 %type <options> instoptions instoption_list
496 %type <instoption> instoption
497
498 /* writemask */
499 %type <integer> writemask_x writemask_y writemask_z writemask_w
500 %type <integer> writemask
501
502 /* dst operand */
503 %type <reg> dst dstoperand dstoperandex dstoperandex_typed dstreg
504 %type <integer> dstregion
505
506 %type <integer> saturate
507 %type <reg> relativelocation2
508
509 /* src operand */
510 %type <reg> directsrcoperand directsrcaccoperand indirectsrcoperand srcacc
511 %type <reg> srcarcoperandex srcaccimm srcarcoperandex_typed srcimm
512 %type <reg> indirectgenreg indirectregion
513 %type <reg> immreg src reg32 payload directgenreg_list addrparam region
514 %type <reg> region_wh directgenreg
515 %type <reg> desc ex_desc reg32a
516 %type <integer> swizzle
517
518 /* registers */
519 %type <reg> accreg addrreg channelenablereg controlreg flagreg ipreg
520 %type <reg> notifyreg nullreg performancereg threadcontrolreg statereg maskreg
521 %type <integer> subregnum
522
523 /* register types */
524 %type <reg_type> reg_type imm_type
525
526 /* immediate values */
527 %type <llint> immval
528
529 /* instruction opcodes */
530 %type <integer> unaryopcodes binaryopcodes binaryaccopcodes ternaryopcodes
531 %type <integer> sendop sendsop
532 %type <instruction> sendopcode sendsopcode
533
534 %type <integer> negate abs chansel math_function sharedfunction
535
536 %type <string> jumplabeltarget
537 %type <string> jumplabel
538
539 /* SWSB */
540 %token <integer> REG_DIST_CURRENT
541 %token <integer> REG_DIST_FLOAT
542 %token <integer> REG_DIST_INT
543 %token <integer> REG_DIST_LONG
544 %token <integer> REG_DIST_ALL
545 %token <integer> SBID_ALLOC
546 %token <integer> SBID_WAIT_SRC
547 %token <integer> SBID_WAIT_DST
548
549 %type <depinfo> depinfo
550
551 %code {
552
553 static void
add_instruction_option(struct options * options,struct instoption opt)554 add_instruction_option(struct options *options, struct instoption opt)
555 {
556 if (opt.type == INSTOPTION_DEP_INFO) {
557 if (opt.depinfo_value.regdist) {
558 options->depinfo.regdist = opt.depinfo_value.regdist;
559 options->depinfo.pipe = opt.depinfo_value.pipe;
560 } else {
561 options->depinfo.sbid = opt.depinfo_value.sbid;
562 options->depinfo.mode = opt.depinfo_value.mode;
563 }
564 return;
565 }
566 switch (opt.uint_value) {
567 case ALIGN1:
568 options->access_mode = BRW_ALIGN_1;
569 break;
570 case ALIGN16:
571 options->access_mode = BRW_ALIGN_16;
572 break;
573 case SWITCH:
574 options->thread_control |= BRW_THREAD_SWITCH;
575 break;
576 case ATOMIC:
577 options->thread_control |= BRW_THREAD_ATOMIC;
578 break;
579 case NODDCHK:
580 options->no_dd_check = true;
581 break;
582 case NODDCLR:
583 options->no_dd_clear = BRW_DEPENDENCY_NOTCLEARED;
584 break;
585 case MASK_DISABLE:
586 options->mask_control |= BRW_MASK_DISABLE;
587 break;
588 case BREAKPOINT:
589 options->debug_control = BRW_DEBUG_BREAKPOINT;
590 break;
591 case WECTRL:
592 options->mask_control |= BRW_WE_ALL;
593 break;
594 case CMPTCTRL:
595 options->compaction = true;
596 break;
597 case ACCWREN:
598 options->acc_wr_control = true;
599 break;
600 case EOT:
601 options->end_of_thread = true;
602 break;
603 /* TODO : Figure out how to set instruction group and get rid of
604 * code below
605 */
606 case QTR_2Q:
607 options->qtr_ctrl = BRW_COMPRESSION_2NDHALF;
608 break;
609 case QTR_3Q:
610 options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
611 break;
612 case QTR_4Q:
613 options->qtr_ctrl = 3;
614 break;
615 case QTR_2H:
616 options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
617 break;
618 case QTR_2N:
619 options->qtr_ctrl = BRW_COMPRESSION_NONE;
620 options->nib_ctrl = true;
621 break;
622 case QTR_3N:
623 options->qtr_ctrl = BRW_COMPRESSION_2NDHALF;
624 break;
625 case QTR_4N:
626 options->qtr_ctrl = BRW_COMPRESSION_2NDHALF;
627 options->nib_ctrl = true;
628 break;
629 case QTR_5N:
630 options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
631 break;
632 case QTR_6N:
633 options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
634 options->nib_ctrl = true;
635 break;
636 case QTR_7N:
637 options->qtr_ctrl = 3;
638 break;
639 case QTR_8N:
640 options->qtr_ctrl = 3;
641 options->nib_ctrl = true;
642 break;
643 }
644 }
645 }
646 %%
647
648 ROOT:
649 instrseq
650 ;
651
652 instrseq:
653 instrseq instruction SEMICOLON
654 | instrseq relocatableinstruction SEMICOLON
655 | instruction SEMICOLON
656 | relocatableinstruction SEMICOLON
657 | instrseq jumplabeltarget
658 | jumplabeltarget
659 ;
660
661 /* Instruction Group */
662 instruction:
663 unaryinstruction
664 | binaryinstruction
665 | binaryaccinstruction
666 | mathinstruction
667 | nopinstruction
668 | waitinstruction
669 | ternaryinstruction
670 | sendinstruction
671 | illegalinstruction
672 | syncinstruction
673 ;
674
675 relocatableinstruction:
676 jumpinstruction
677 | branchinstruction
678 | breakinstruction
679 | loopinstruction
680 ;
681
682 illegalinstruction:
683 ILLEGAL execsize instoptions
684 {
685 brw_next_insn(p, $1);
686 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
687 i965_asm_set_instruction_options(p, $3);
688 }
689 ;
690
691 /* Unary instruction */
692 unaryinstruction:
693 predicate unaryopcodes saturate cond_mod execsize dst srcaccimm instoptions
694 {
695 brw_set_default_access_mode(p, $8.access_mode);
696 i965_asm_unary_instruction($2, p, $6, $7);
697 brw_pop_insn_state(p);
698 i965_asm_set_instruction_options(p, $8);
699 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
700 $4.cond_modifier);
701
702 if (!brw_inst_flag_reg_nr(p->devinfo, brw_last_inst)) {
703 brw_inst_set_flag_reg_nr(p->devinfo,
704 brw_last_inst,
705 $4.flag_reg_nr);
706 brw_inst_set_flag_subreg_nr(p->devinfo,
707 brw_last_inst,
708 $4.flag_subreg_nr);
709 }
710
711 if ($7.file != BRW_IMMEDIATE_VALUE) {
712 brw_inst_set_src0_vstride(p->devinfo, brw_last_inst,
713 $7.vstride);
714 }
715 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
716 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
717 // TODO: set instruction group instead of qtr and nib ctrl
718 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
719 $8.qtr_ctrl);
720
721 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
722 $8.nib_ctrl);
723 }
724 ;
725
726 unaryopcodes:
727 BFREV
728 | CBIT
729 | DIM
730 | FBH
731 | FBL
732 | FRC
733 | LZD
734 | MOV
735 | NOT
736 | RNDD
737 | RNDE
738 | RNDU
739 | RNDZ
740 ;
741
742 /* Binary instruction */
743 binaryinstruction:
744 predicate binaryopcodes saturate cond_mod execsize dst srcimm srcimm instoptions
745 {
746 brw_set_default_access_mode(p, $9.access_mode);
747 i965_asm_binary_instruction($2, p, $6, $7, $8);
748 i965_asm_set_instruction_options(p, $9);
749 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
750 $4.cond_modifier);
751
752 if (!brw_inst_flag_reg_nr(p->devinfo, brw_last_inst)) {
753 brw_inst_set_flag_reg_nr(p->devinfo, brw_last_inst,
754 $4.flag_reg_nr);
755 brw_inst_set_flag_subreg_nr(p->devinfo, brw_last_inst,
756 $4.flag_subreg_nr);
757 }
758
759 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
760 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
761 // TODO: set instruction group instead of qtr and nib ctrl
762 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
763 $9.qtr_ctrl);
764
765 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
766 $9.nib_ctrl);
767
768 brw_pop_insn_state(p);
769 }
770 ;
771
772 binaryopcodes:
773 ADDC
774 | BFI1
775 | DP2
776 | DP3
777 | DP4
778 | DPH
779 | LINE
780 | MAC
781 | MACH
782 | MUL
783 | PLN
784 | ROL
785 | ROR
786 | SAD2
787 | SADA2
788 | SUBB
789 ;
790
791 /* Binary acc instruction */
792 binaryaccinstruction:
793 predicate binaryaccopcodes saturate cond_mod execsize dst srcacc srcimm instoptions
794 {
795 brw_set_default_access_mode(p, $9.access_mode);
796 i965_asm_binary_instruction($2, p, $6, $7, $8);
797 brw_pop_insn_state(p);
798 i965_asm_set_instruction_options(p, $9);
799 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
800 $4.cond_modifier);
801
802 if (!brw_inst_flag_reg_nr(p->devinfo, brw_last_inst)) {
803 brw_inst_set_flag_reg_nr(p->devinfo,
804 brw_last_inst,
805 $4.flag_reg_nr);
806 brw_inst_set_flag_subreg_nr(p->devinfo,
807 brw_last_inst,
808 $4.flag_subreg_nr);
809 }
810
811 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
812 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
813 // TODO: set instruction group instead of qtr and nib ctrl
814 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
815 $9.qtr_ctrl);
816
817 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
818 $9.nib_ctrl);
819 }
820 ;
821
822 binaryaccopcodes:
823 ADD
824 | AND
825 | ASR
826 | AVG
827 | CMP
828 | CMPN
829 | OR
830 | SEL
831 | SHL
832 | SHR
833 | XOR
834 ;
835
836 /* Math instruction */
837 mathinstruction:
838 predicate MATH saturate math_function execsize dst src srcimm instoptions
839 {
840 brw_set_default_access_mode(p, $9.access_mode);
841 gfx6_math(p, $6, $4, $7, $8);
842 i965_asm_set_instruction_options(p, $9);
843 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
844 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
845 // TODO: set instruction group instead
846 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
847 $9.qtr_ctrl);
848
849 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
850 $9.nib_ctrl);
851
852 brw_pop_insn_state(p);
853 }
854 ;
855
856 math_function:
857 COS
858 | EXP
859 | FDIV
860 | INV
861 | INVM
862 | INTDIV
863 | INTDIVMOD
864 | INTMOD
865 | LOG
866 | POW
867 | RSQ
868 | RSQRTM
869 | SIN
870 | SQRT
871 | SINCOS
872 ;
873
874 /* NOP instruction */
875 nopinstruction:
876 NOP
877 {
878 brw_NOP(p);
879 }
880 ;
881
882 /* Ternary operand instruction */
883 ternaryinstruction:
884 predicate ternaryopcodes saturate cond_mod execsize dst srcimm src srcimm instoptions
885 {
886 brw_set_default_access_mode(p, $10.access_mode);
887 i965_asm_ternary_instruction($2, p, $6, $7, $8, $9);
888 brw_pop_insn_state(p);
889 i965_asm_set_instruction_options(p, $10);
890 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
891 $4.cond_modifier);
892
893 if (p->devinfo->ver < 12) {
894 brw_inst_set_3src_a16_flag_reg_nr(p->devinfo, brw_last_inst,
895 $4.flag_reg_nr);
896 brw_inst_set_3src_a16_flag_subreg_nr(p->devinfo, brw_last_inst,
897 $4.flag_subreg_nr);
898 }
899
900 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
901 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
902 // TODO: set instruction group instead of qtr and nib ctrl
903 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
904 $10.qtr_ctrl);
905
906 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
907 $10.nib_ctrl);
908 }
909 ;
910
911 ternaryopcodes:
912 CSEL
913 | BFE
914 | BFI2
915 | LRP
916 | MAD
917 | DP4A
918 | ADD3
919 ;
920
921 /* Wait instruction */
922 waitinstruction:
923 WAIT execsize dst instoptions
924 {
925 brw_next_insn(p, $1);
926 i965_asm_set_instruction_options(p, $4);
927 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
928 brw_set_default_access_mode(p, $4.access_mode);
929 struct brw_reg dest = $3;
930 dest.swizzle = brw_swizzle_for_mask(dest.writemask);
931 if (dest.file != ARF || dest.nr != BRW_ARF_NOTIFICATION_COUNT)
932 error(&@1, "WAIT must use the notification register\n");
933 brw_set_dest(p, brw_last_inst, dest);
934 brw_set_src0(p, brw_last_inst, dest);
935 brw_set_src1(p, brw_last_inst, brw_null_reg());
936 brw_inst_set_mask_control(p->devinfo, brw_last_inst, BRW_MASK_DISABLE);
937 }
938 ;
939
940 /* Send instruction */
941 sendinstruction:
942 predicate sendopcode execsize dst payload exp2 sharedfunction msgdesc instoptions
943 {
944 i965_asm_set_instruction_options(p, $9);
945 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
946 brw_set_dest(p, brw_last_inst, $4);
947 brw_set_src0(p, brw_last_inst, $5);
948 brw_inst_set_bits(brw_last_inst, 127, 96, $6);
949 brw_inst_set_src1_file_type(p->devinfo, brw_last_inst,
950 BRW_IMMEDIATE_VALUE,
951 BRW_REGISTER_TYPE_UD);
952 brw_inst_set_sfid(p->devinfo, brw_last_inst, $7);
953 brw_inst_set_eot(p->devinfo, brw_last_inst, $9.end_of_thread);
954 // TODO: set instruction group instead of qtr and nib ctrl
955 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
956 $9.qtr_ctrl);
957
958 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
959 $9.nib_ctrl);
960
961 brw_pop_insn_state(p);
962 }
963 | predicate sendopcode execsize dst payload payload exp2 sharedfunction msgdesc instoptions
964 {
965 assert(p->devinfo->ver < 12);
966
967 i965_asm_set_instruction_options(p, $10);
968 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
969 brw_set_dest(p, brw_last_inst, $4);
970 brw_set_src0(p, brw_last_inst, $5);
971 brw_inst_set_bits(brw_last_inst, 127, 96, $7);
972 brw_inst_set_sfid(p->devinfo, brw_last_inst, $8);
973 brw_inst_set_eot(p->devinfo, brw_last_inst, $10.end_of_thread);
974 // TODO: set instruction group instead of qtr and nib ctrl
975 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
976 $10.qtr_ctrl);
977
978 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
979 $10.nib_ctrl);
980
981 brw_pop_insn_state(p);
982 }
983 | predicate sendsopcode execsize dst payload payload desc ex_desc sharedfunction msgdesc instoptions
984 {
985 i965_asm_set_instruction_options(p, $11);
986 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
987 brw_set_dest(p, brw_last_inst, $4);
988 brw_set_src0(p, brw_last_inst, $5);
989 brw_set_src1(p, brw_last_inst, $6);
990
991 if ($7.file == BRW_IMMEDIATE_VALUE) {
992 brw_inst_set_send_sel_reg32_desc(p->devinfo, brw_last_inst, 0);
993 brw_inst_set_send_desc(p->devinfo, brw_last_inst, $7.ud);
994 } else {
995 brw_inst_set_send_sel_reg32_desc(p->devinfo, brw_last_inst, 1);
996 }
997
998 if ($8.file == BRW_IMMEDIATE_VALUE) {
999 brw_inst_set_send_sel_reg32_ex_desc(p->devinfo, brw_last_inst, 0);
1000 brw_inst_set_sends_ex_desc(p->devinfo, brw_last_inst, $8.ud);
1001 } else {
1002 brw_inst_set_send_sel_reg32_ex_desc(p->devinfo, brw_last_inst, 1);
1003 brw_inst_set_send_ex_desc_ia_subreg_nr(p->devinfo, brw_last_inst, $8.subnr >> 2);
1004 }
1005
1006 brw_inst_set_sfid(p->devinfo, brw_last_inst, $9);
1007 brw_inst_set_eot(p->devinfo, brw_last_inst, $11.end_of_thread);
1008 // TODO: set instruction group instead of qtr and nib ctrl
1009 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
1010 $11.qtr_ctrl);
1011
1012 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
1013 $11.nib_ctrl);
1014
1015 if (p->devinfo->verx10 >= 125 && $10.ex_bso) {
1016 brw_inst_set_send_ex_bso(p->devinfo, brw_last_inst, 1);
1017 brw_inst_set_send_src1_len(p->devinfo, brw_last_inst,
1018 $10.src1_len);
1019 }
1020
1021 brw_pop_insn_state(p);
1022 }
1023 ;
1024
1025 sendop:
1026 SEND_GFX4
1027 | SENDC_GFX4
1028 ;
1029
1030 sendsop:
1031 SEND_GFX12
1032 | SENDC_GFX12
1033 | SENDS
1034 | SENDSC
1035 ;
1036
1037 sendopcode:
1038 sendop { $$ = brw_next_insn(p, $1); }
1039 ;
1040
1041 sendsopcode:
1042 sendsop { $$ = brw_next_insn(p, $1); }
1043 ;
1044
1045 sharedfunction:
1046 NULL_TOKEN { $$ = BRW_SFID_NULL; }
1047 | MATH { $$ = BRW_SFID_MATH; }
1048 | GATEWAY { $$ = BRW_SFID_MESSAGE_GATEWAY; }
1049 | READ { $$ = BRW_SFID_DATAPORT_READ; }
1050 | WRITE { $$ = BRW_SFID_DATAPORT_WRITE; }
1051 | URB { $$ = BRW_SFID_URB; }
1052 | THREAD_SPAWNER { $$ = BRW_SFID_THREAD_SPAWNER; }
1053 | VME { $$ = BRW_SFID_VME; }
1054 | RENDER { $$ = GFX6_SFID_DATAPORT_RENDER_CACHE; }
1055 | CONST { $$ = GFX6_SFID_DATAPORT_CONSTANT_CACHE; }
1056 | DATA { $$ = GFX7_SFID_DATAPORT_DATA_CACHE; }
1057 | PIXEL_INTERP { $$ = GFX7_SFID_PIXEL_INTERPOLATOR; }
1058 | DP_DATA_1 { $$ = HSW_SFID_DATAPORT_DATA_CACHE_1; }
1059 | CRE { $$ = HSW_SFID_CRE; }
1060 | SAMPLER { $$ = BRW_SFID_SAMPLER; }
1061 | DP_SAMPLER { $$ = GFX6_SFID_DATAPORT_SAMPLER_CACHE; }
1062 | RT_ACCEL { $$ = GEN_RT_SFID_RAY_TRACE_ACCELERATOR; }
1063 | SLM { $$ = GFX12_SFID_SLM; }
1064 | TGM { $$ = GFX12_SFID_TGM; }
1065 | UGM { $$ = GFX12_SFID_UGM; }
1066 ;
1067
1068 exp2:
1069 LONG { $$ = $1; }
1070 | MINUS LONG { $$ = -$2; }
1071 ;
1072
1073 desc:
1074 reg32a
1075 | exp2
1076 {
1077 $$ = brw_imm_ud($1);
1078 }
1079 ;
1080
1081 ex_desc:
1082 reg32a
1083 | exp2
1084 {
1085 $$ = brw_imm_ud($1);
1086 }
1087 ;
1088
1089 reg32a:
1090 addrreg region reg_type
1091 {
1092 $$ = set_direct_src_operand(&$1, $3);
1093 $$ = stride($$, $2.vstride, $2.width, $2.hstride);
1094 }
1095 ;
1096
1097
1098 /* Jump instruction */
1099 jumpinstruction:
1100 predicate JMPI execsize relativelocation2 instoptions
1101 {
1102 brw_next_insn(p, $2);
1103 i965_asm_set_instruction_options(p, $5);
1104 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1105 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1106 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1107 brw_set_src1(p, brw_last_inst, $4);
1108 brw_inst_set_pred_control(p->devinfo, brw_last_inst,
1109 brw_inst_pred_control(p->devinfo,
1110 brw_last_inst));
1111 brw_pop_insn_state(p);
1112 }
1113 ;
1114
1115 /* branch instruction */
1116 branchinstruction:
1117 predicate ENDIF execsize JUMP_LABEL instoptions
1118 {
1119 add_label(p, $4, INSTR_LABEL_JIP);
1120
1121 brw_next_insn(p, $2);
1122 i965_asm_set_instruction_options(p, $5);
1123 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1124
1125 brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
1126
1127 brw_pop_insn_state(p);
1128 }
1129 | ELSE execsize JUMP_LABEL jumplabel instoptions
1130 {
1131 add_label(p, $3, INSTR_LABEL_JIP);
1132 add_label(p, $4, INSTR_LABEL_UIP);
1133
1134 brw_next_insn(p, $1);
1135 i965_asm_set_instruction_options(p, $5);
1136 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
1137
1138 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1139 BRW_REGISTER_TYPE_D));
1140 if (p->devinfo->ver < 12)
1141 brw_set_src0(p, brw_last_inst, brw_imm_d(0));
1142 }
1143 | predicate IF execsize JUMP_LABEL jumplabel instoptions
1144 {
1145 add_label(p, $4, INSTR_LABEL_JIP);
1146 add_label(p, $5, INSTR_LABEL_UIP);
1147
1148 brw_next_insn(p, $2);
1149 i965_asm_set_instruction_options(p, $6);
1150 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1151
1152 brw_set_dest(p, brw_last_inst,
1153 vec1(retype(brw_null_reg(),
1154 BRW_REGISTER_TYPE_D)));
1155 if (p->devinfo->ver < 12)
1156 brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
1157
1158 brw_pop_insn_state(p);
1159 }
1160 ;
1161
1162 /* break instruction */
1163 breakinstruction:
1164 predicate BREAK execsize JUMP_LABEL JUMP_LABEL instoptions
1165 {
1166 add_label(p, $4, INSTR_LABEL_JIP);
1167 add_label(p, $5, INSTR_LABEL_UIP);
1168
1169 brw_next_insn(p, $2);
1170 i965_asm_set_instruction_options(p, $6);
1171 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1172
1173 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1174 BRW_REGISTER_TYPE_D));
1175 brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
1176
1177 brw_pop_insn_state(p);
1178 }
1179 | predicate HALT execsize JUMP_LABEL JUMP_LABEL instoptions
1180 {
1181 add_label(p, $4, INSTR_LABEL_JIP);
1182 add_label(p, $5, INSTR_LABEL_UIP);
1183
1184 brw_next_insn(p, $2);
1185 i965_asm_set_instruction_options(p, $6);
1186 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1187
1188 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1189 BRW_REGISTER_TYPE_D));
1190
1191 if (p->devinfo->ver < 12) {
1192 brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
1193 }
1194
1195 brw_pop_insn_state(p);
1196 }
1197 | predicate CONT execsize JUMP_LABEL JUMP_LABEL instoptions
1198 {
1199 add_label(p, $4, INSTR_LABEL_JIP);
1200 add_label(p, $5, INSTR_LABEL_UIP);
1201
1202 brw_next_insn(p, $2);
1203 i965_asm_set_instruction_options(p, $6);
1204 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1205 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1206
1207 brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
1208
1209 brw_pop_insn_state(p);
1210 }
1211 ;
1212
1213 /* loop instruction */
1214 loopinstruction:
1215 predicate WHILE execsize JUMP_LABEL instoptions
1216 {
1217 add_label(p, $4, INSTR_LABEL_JIP);
1218
1219 brw_next_insn(p, $2);
1220 i965_asm_set_instruction_options(p, $5);
1221 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1222
1223 brw_set_dest(p, brw_last_inst,
1224 retype(brw_null_reg(),
1225 BRW_REGISTER_TYPE_D));
1226 if (p->devinfo->ver < 12)
1227 brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
1228
1229 brw_pop_insn_state(p);
1230 }
1231 | DO execsize instoptions
1232 {
1233 brw_next_insn(p, $1);
1234 }
1235 ;
1236
1237 /* sync instruction */
1238 syncinstruction:
1239 predicate SYNC sync_function execsize sync_arg instoptions
1240 {
1241 if (p->devinfo->ver < 12) {
1242 error(&@2, "sync instruction is supported only on gfx12+\n");
1243 }
1244
1245 if ($5.file == BRW_IMMEDIATE_VALUE &&
1246 $3 != TGL_SYNC_ALLRD &&
1247 $3 != TGL_SYNC_ALLWR) {
1248 error(&@2, "Only allrd and allwr support immediate argument\n");
1249 }
1250
1251 brw_set_default_access_mode(p, $6.access_mode);
1252 brw_SYNC(p, $3);
1253 i965_asm_set_instruction_options(p, $6);
1254 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $4);
1255 brw_set_src0(p, brw_last_inst, $5);
1256 brw_inst_set_eot(p->devinfo, brw_last_inst, $6.end_of_thread);
1257 brw_inst_set_qtr_control(p->devinfo, brw_last_inst, $6.qtr_ctrl);
1258 brw_inst_set_nib_control(p->devinfo, brw_last_inst, $6.nib_ctrl);
1259
1260 brw_pop_insn_state(p);
1261 }
1262 ;
1263
1264 sync_function:
1265 NOP { $$ = TGL_SYNC_NOP; }
1266 | ALLRD
1267 | ALLWR
1268 | FENCE
1269 | BAR
1270 | HOST
1271 ;
1272
1273 sync_arg:
1274 nullreg region reg_type
1275 {
1276 $$ = $1;
1277 $$.vstride = $2.vstride;
1278 $$.width = $2.width;
1279 $$.hstride = $2.hstride;
1280 $$.type = $3;
1281 }
1282 | immreg
1283 ;
1284
1285 /* Relative location */
1286 relativelocation2:
1287 immreg
1288 | reg32
1289 ;
1290
1291 jumplabel:
1292 JUMP_LABEL { $$ = $1; }
1293 | /* empty */ { $$ = NULL; }
1294 ;
1295
1296 jumplabeltarget:
1297 JUMP_LABEL_TARGET
1298 {
1299 struct target_label *label = rzalloc(p->mem_ctx, struct target_label);
1300
1301 label->name = ralloc_strdup(p->mem_ctx, $1);
1302 label->offset = p->next_insn_offset;
1303
1304 list_addtail(&label->link, &target_labels);
1305 }
1306 ;
1307
1308 /* Destination register */
1309 dst:
1310 dstoperand
1311 | dstoperandex
1312 ;
1313
1314 dstoperand:
1315 dstreg dstregion writemask reg_type
1316 {
1317 $$ = $1;
1318 $$.vstride = BRW_VERTICAL_STRIDE_1;
1319 $$.width = BRW_WIDTH_1;
1320 $$.hstride = $2;
1321 $$.type = $4;
1322 $$.writemask = $3;
1323 $$.swizzle = BRW_SWIZZLE_NOOP;
1324 $$.subnr = $$.subnr * brw_reg_type_to_size($4);
1325 }
1326 ;
1327
1328 dstoperandex:
1329 dstoperandex_typed dstregion writemask reg_type
1330 {
1331 $$ = $1;
1332 $$.hstride = $2;
1333 $$.type = $4;
1334 $$.writemask = $3;
1335 $$.subnr = $$.subnr * brw_reg_type_to_size($4);
1336 }
1337 /* BSpec says "When the conditional modifier is present, updates
1338 * to the selected flag register also occur. In this case, the
1339 * register region fields of the ‘null’ operand are valid."
1340 */
1341 | nullreg dstregion writemask reg_type
1342 {
1343 $$ = $1;
1344 $$.vstride = BRW_VERTICAL_STRIDE_1;
1345 $$.width = BRW_WIDTH_1;
1346 $$.hstride = $2;
1347 $$.writemask = $3;
1348 $$.type = $4;
1349 }
1350 | threadcontrolreg
1351 {
1352 $$ = $1;
1353 $$.hstride = 1;
1354 $$.type = BRW_REGISTER_TYPE_UW;
1355 }
1356 ;
1357
1358 dstoperandex_typed:
1359 accreg
1360 | addrreg
1361 | channelenablereg
1362 | controlreg
1363 | flagreg
1364 | ipreg
1365 | maskreg
1366 | notifyreg
1367 | performancereg
1368 | statereg
1369 ;
1370
1371 dstreg:
1372 directgenreg
1373 {
1374 $$ = $1;
1375 $$.address_mode = BRW_ADDRESS_DIRECT;
1376 }
1377 | indirectgenreg
1378 {
1379 $$ = $1;
1380 $$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
1381 }
1382 ;
1383
1384 /* Source register */
1385 srcaccimm:
1386 srcacc
1387 | immreg
1388 ;
1389
1390 immreg:
1391 immval imm_type
1392 {
1393 switch ($2) {
1394 case BRW_REGISTER_TYPE_UD:
1395 $$ = brw_imm_ud($1);
1396 break;
1397 case BRW_REGISTER_TYPE_D:
1398 $$ = brw_imm_d($1);
1399 break;
1400 case BRW_REGISTER_TYPE_UW:
1401 $$ = brw_imm_uw($1 | ($1 << 16));
1402 break;
1403 case BRW_REGISTER_TYPE_W:
1404 $$ = brw_imm_w($1);
1405 break;
1406 case BRW_REGISTER_TYPE_F:
1407 $$ = brw_imm_reg(BRW_REGISTER_TYPE_F);
1408 /* Set u64 instead of ud since DIM uses a 64-bit F-typed imm */
1409 $$.u64 = $1;
1410 break;
1411 case BRW_REGISTER_TYPE_V:
1412 $$ = brw_imm_v($1);
1413 break;
1414 case BRW_REGISTER_TYPE_UV:
1415 $$ = brw_imm_uv($1);
1416 break;
1417 case BRW_REGISTER_TYPE_VF:
1418 $$ = brw_imm_vf($1);
1419 break;
1420 case BRW_REGISTER_TYPE_Q:
1421 $$ = brw_imm_q($1);
1422 break;
1423 case BRW_REGISTER_TYPE_UQ:
1424 $$ = brw_imm_uq($1);
1425 break;
1426 case BRW_REGISTER_TYPE_DF:
1427 $$ = brw_imm_reg(BRW_REGISTER_TYPE_DF);
1428 $$.d64 = $1;
1429 break;
1430 case BRW_REGISTER_TYPE_HF:
1431 $$ = brw_imm_reg(BRW_REGISTER_TYPE_HF);
1432 $$.ud = $1 | ($1 << 16);
1433 break;
1434 default:
1435 error(&@2, "Unknown immediate type %s\n",
1436 brw_reg_type_to_letters($2));
1437 }
1438 }
1439 ;
1440
1441 reg32:
1442 directgenreg region reg_type
1443 {
1444 $$ = set_direct_src_operand(&$1, $3);
1445 $$ = stride($$, $2.vstride, $2.width, $2.hstride);
1446 }
1447 ;
1448
1449 payload:
1450 directsrcoperand
1451 ;
1452
1453 src:
1454 directsrcoperand
1455 | indirectsrcoperand
1456 ;
1457
1458 srcacc:
1459 directsrcaccoperand
1460 | indirectsrcoperand
1461 ;
1462
1463 srcimm:
1464 directsrcoperand
1465 | indirectsrcoperand
1466 | immreg
1467 ;
1468
1469 directsrcaccoperand:
1470 directsrcoperand
1471 | negate abs accreg region reg_type
1472 {
1473 $$ = set_direct_src_operand(&$3, $5);
1474 $$.negate = $1;
1475 $$.abs = $2;
1476 $$.vstride = $4.vstride;
1477 $$.width = $4.width;
1478 $$.hstride = $4.hstride;
1479 }
1480 ;
1481
1482 srcarcoperandex:
1483 srcarcoperandex_typed region reg_type
1484 {
1485 $$ = brw_reg($1.file,
1486 $1.nr,
1487 $1.subnr,
1488 0,
1489 0,
1490 $3,
1491 $2.vstride,
1492 $2.width,
1493 $2.hstride,
1494 BRW_SWIZZLE_NOOP,
1495 WRITEMASK_XYZW);
1496 }
1497 | nullreg region reg_type
1498 {
1499 $$ = set_direct_src_operand(&$1, $3);
1500 $$.vstride = $2.vstride;
1501 $$.width = $2.width;
1502 $$.hstride = $2.hstride;
1503 }
1504 | threadcontrolreg
1505 {
1506 $$ = set_direct_src_operand(&$1, BRW_REGISTER_TYPE_UW);
1507 }
1508 ;
1509
1510 srcarcoperandex_typed:
1511 channelenablereg
1512 | controlreg
1513 | flagreg
1514 | ipreg
1515 | maskreg
1516 | statereg
1517 ;
1518
1519 indirectsrcoperand:
1520 negate abs indirectgenreg indirectregion swizzle reg_type
1521 {
1522 $$ = brw_reg($3.file,
1523 0,
1524 $3.subnr,
1525 $1, // negate
1526 $2, // abs
1527 $6,
1528 $4.vstride,
1529 $4.width,
1530 $4.hstride,
1531 $5,
1532 WRITEMASK_X);
1533
1534 $$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
1535 // brw_reg set indirect_offset to 0 so set it to valid value
1536 $$.indirect_offset = $3.indirect_offset;
1537 }
1538 ;
1539
1540 directgenreg_list:
1541 directgenreg
1542 | notifyreg
1543 | addrreg
1544 | performancereg
1545 ;
1546
1547 directsrcoperand:
1548 negate abs directgenreg_list region swizzle reg_type
1549 {
1550 $$ = brw_reg($3.file,
1551 $3.nr,
1552 $3.subnr,
1553 $1,
1554 $2,
1555 $6,
1556 $4.vstride,
1557 $4.width,
1558 $4.hstride,
1559 $5,
1560 WRITEMASK_X);
1561 }
1562 | srcarcoperandex
1563 ;
1564
1565 /* Address register */
1566 addrparam:
1567 addrreg exp
1568 {
1569 memset(&$$, '\0', sizeof($$));
1570 $$.subnr = $1.subnr;
1571 $$.indirect_offset = $2;
1572 }
1573 | addrreg
1574 ;
1575
1576 /* Register files and register numbers */
1577 exp:
1578 INTEGER { $$ = $1; }
1579 | LONG { $$ = $1; }
1580 ;
1581
1582 subregnum:
1583 DOT exp { $$ = $2; }
1584 | /* empty */ %prec SUBREGNUM { $$ = 0; }
1585 ;
1586
1587 directgenreg:
1588 GENREG subregnum
1589 {
1590 memset(&$$, '\0', sizeof($$));
1591 $$.file = BRW_GENERAL_REGISTER_FILE;
1592 $$.nr = $1;
1593 $$.subnr = $2;
1594 }
1595 ;
1596
1597 indirectgenreg:
1598 GENREGFILE LSQUARE addrparam RSQUARE
1599 {
1600 memset(&$$, '\0', sizeof($$));
1601 $$.file = BRW_GENERAL_REGISTER_FILE;
1602 $$.subnr = $3.subnr;
1603 $$.indirect_offset = $3.indirect_offset;
1604 }
1605 ;
1606
1607 addrreg:
1608 ADDRREG subregnum
1609 {
1610 int subnr = 16;
1611
1612 if ($2 > subnr)
1613 error(&@2, "Address sub register number %d"
1614 "out of range\n", $2);
1615
1616 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1617 $$.nr = BRW_ARF_ADDRESS;
1618 $$.subnr = $2;
1619 }
1620 ;
1621
1622 accreg:
1623 ACCREG subregnum
1624 {
1625 int nr_reg = 10;
1626
1627 if ($1 > nr_reg)
1628 error(&@1, "Accumulator register number %d"
1629 " out of range\n", $1);
1630
1631 memset(&$$, '\0', sizeof($$));
1632 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1633 $$.nr = BRW_ARF_ACCUMULATOR;
1634 $$.subnr = $2;
1635 }
1636 ;
1637
1638 flagreg:
1639 FLAGREG subregnum
1640 {
1641 // 2 flag reg
1642 int nr_reg = 2;
1643 int subnr = nr_reg;
1644
1645 if ($1 > nr_reg)
1646 error(&@1, "Flag register number %d"
1647 " out of range \n", $1);
1648 if ($2 > subnr)
1649 error(&@2, "Flag subregister number %d"
1650 " out of range\n", $2);
1651
1652 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1653 $$.nr = BRW_ARF_FLAG | $1;
1654 $$.subnr = $2;
1655 }
1656 ;
1657
1658 maskreg:
1659 MASKREG subregnum
1660 {
1661 if ($1 > 0)
1662 error(&@1, "Mask register number %d"
1663 " out of range\n", $1);
1664
1665 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1666 $$.nr = BRW_ARF_MASK;
1667 $$.subnr = $2;
1668 }
1669 ;
1670
1671 notifyreg:
1672 NOTIFYREG subregnum
1673 {
1674 int subnr = (p->devinfo->ver >= 11) ? 2 : 3;
1675 if ($2 > subnr)
1676 error(&@2, "Notification sub register number %d"
1677 " out of range\n", $2);
1678
1679 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1680 $$.nr = BRW_ARF_NOTIFICATION_COUNT;
1681 $$.subnr = $2;
1682 }
1683 ;
1684
1685 statereg:
1686 STATEREG subregnum
1687 {
1688 if ($1 > 2)
1689 error(&@1, "State register number %d"
1690 " out of range\n", $1);
1691
1692 if ($2 > 4)
1693 error(&@2, "State sub register number %d"
1694 " out of range\n", $2);
1695
1696 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1697 $$.nr = BRW_ARF_STATE;
1698 $$.subnr = $2;
1699 }
1700 ;
1701
1702 controlreg:
1703 CONTROLREG subregnum
1704 {
1705 if ($2 > 3)
1706 error(&@2, "control sub register number %d"
1707 " out of range\n", $2);
1708
1709 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1710 $$.nr = BRW_ARF_CONTROL;
1711 $$.subnr = $2;
1712 }
1713 ;
1714
1715 ipreg:
1716 IPREG { $$ = brw_ip_reg(); }
1717 ;
1718
1719 nullreg:
1720 NULL_TOKEN { $$ = brw_null_reg(); }
1721 ;
1722
1723 threadcontrolreg:
1724 THREADREG subregnum
1725 {
1726 if ($2 > 7)
1727 error(&@2, "Thread control sub register number %d"
1728 " out of range\n", $2);
1729
1730 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1731 $$.nr = BRW_ARF_TDR;
1732 $$.subnr = $2;
1733 }
1734 ;
1735
1736 performancereg:
1737 PERFORMANCEREG subregnum
1738 {
1739 int subnr;
1740 if (p->devinfo->ver >= 10)
1741 subnr = 5;
1742 else
1743 subnr = 4;
1744
1745 if ($2 > subnr)
1746 error(&@2, "Performance sub register number %d"
1747 " out of range\n", $2);
1748
1749 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1750 $$.nr = BRW_ARF_TIMESTAMP;
1751 $$.subnr = $2;
1752 }
1753 ;
1754
1755 channelenablereg:
1756 CHANNELENABLEREG subregnum
1757 {
1758 if ($1 > 0)
1759 error(&@1, "Channel enable register number %d"
1760 " out of range\n", $1);
1761
1762 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1763 $$.nr = BRW_ARF_MASK;
1764 $$.subnr = $2;
1765 }
1766 ;
1767
1768 /* Immediate values */
1769 immval:
1770 exp2
1771 {
1772 $$ = $1;
1773 }
1774 | LSQUARE exp2 COMMA exp2 COMMA exp2 COMMA exp2 RSQUARE
1775 {
1776 $$ = ($2 << 0) | ($4 << 8) | ($6 << 16) | ($8 << 24);
1777 }
1778 ;
1779
1780 /* Regions */
1781 dstregion:
1782 /* empty */
1783 {
1784 $$ = BRW_HORIZONTAL_STRIDE_1;
1785 }
1786 | LANGLE exp RANGLE
1787 {
1788 if ($2 != 0 && ($2 > 4 || !isPowerofTwo($2)))
1789 error(&@2, "Invalid Horizontal stride %d\n", $2);
1790
1791 $$ = ffs($2);
1792 }
1793 ;
1794
1795 indirectregion:
1796 region
1797 | region_wh
1798 ;
1799
1800 region:
1801 /* empty */
1802 {
1803 $$ = stride($$, 0, 1, 0);
1804 }
1805 | LANGLE exp RANGLE
1806 {
1807 if ($2 != 0 && ($2 > 32 || !isPowerofTwo($2)))
1808 error(&@2, "Invalid VertStride %d\n", $2);
1809
1810 $$ = stride($$, $2, 1, 0);
1811 }
1812 | LANGLE exp COMMA exp COMMA exp RANGLE
1813 {
1814
1815 if ($2 != 0 && ($2 > 32 || !isPowerofTwo($2)))
1816 error(&@2, "Invalid VertStride %d\n", $2);
1817
1818 if ($4 > 16 || !isPowerofTwo($4))
1819 error(&@4, "Invalid width %d\n", $4);
1820
1821 if ($6 != 0 && ($6 > 4 || !isPowerofTwo($6)))
1822 error(&@6, "Invalid Horizontal stride in"
1823 " region_wh %d\n", $6);
1824
1825 $$ = stride($$, $2, $4, $6);
1826 }
1827 | LANGLE exp SEMICOLON exp COMMA exp RANGLE
1828 {
1829 if ($2 != 0 && ($2 > 32 || !isPowerofTwo($2)))
1830 error(&@2, "Invalid VertStride %d\n", $2);
1831
1832 if ($4 > 16 || !isPowerofTwo($4))
1833 error(&@4, "Invalid width %d\n", $4);
1834
1835 if ($6 != 0 && ($6 > 4 || !isPowerofTwo($6)))
1836 error(&@6, "Invalid Horizontal stride in"
1837 " region_wh %d\n", $6);
1838
1839 $$ = stride($$, $2, $4, $6);
1840 }
1841 | LANGLE VxH COMMA exp COMMA exp RANGLE
1842 {
1843 if ($4 > 16 || !isPowerofTwo($4))
1844 error(&@4, "Invalid width %d\n", $4);
1845
1846 if ($6 != 0 && ($6 > 4 || !isPowerofTwo($6)))
1847 error(&@6, "Invalid Horizontal stride in"
1848 " region_wh %d\n", $6);
1849
1850 $$ = brw_VxH_indirect(0, 0);
1851 }
1852 ;
1853
1854 region_wh:
1855 LANGLE exp COMMA exp RANGLE
1856 {
1857 if ($2 > 16 || !isPowerofTwo($2))
1858 error(&@2, "Invalid width %d\n", $2);
1859
1860 if ($4 != 0 && ($4 > 4 || !isPowerofTwo($4)))
1861 error(&@4, "Invalid Horizontal stride in"
1862 " region_wh %d\n", $4);
1863
1864 $$ = stride($$, 0, $2, $4);
1865 $$.vstride = BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL;
1866 }
1867 ;
1868
1869 reg_type:
1870 TYPE_F { $$ = BRW_REGISTER_TYPE_F; }
1871 | TYPE_UD { $$ = BRW_REGISTER_TYPE_UD; }
1872 | TYPE_D { $$ = BRW_REGISTER_TYPE_D; }
1873 | TYPE_UW { $$ = BRW_REGISTER_TYPE_UW; }
1874 | TYPE_W { $$ = BRW_REGISTER_TYPE_W; }
1875 | TYPE_UB { $$ = BRW_REGISTER_TYPE_UB; }
1876 | TYPE_B { $$ = BRW_REGISTER_TYPE_B; }
1877 | TYPE_DF { $$ = BRW_REGISTER_TYPE_DF; }
1878 | TYPE_UQ { $$ = BRW_REGISTER_TYPE_UQ; }
1879 | TYPE_Q { $$ = BRW_REGISTER_TYPE_Q; }
1880 | TYPE_HF { $$ = BRW_REGISTER_TYPE_HF; }
1881 | TYPE_NF { $$ = BRW_REGISTER_TYPE_NF; }
1882 ;
1883
1884 imm_type:
1885 reg_type { $$ = $1; }
1886 | TYPE_V { $$ = BRW_REGISTER_TYPE_V; }
1887 | TYPE_VF { $$ = BRW_REGISTER_TYPE_VF; }
1888 | TYPE_UV { $$ = BRW_REGISTER_TYPE_UV; }
1889 ;
1890
1891 writemask:
1892 /* empty */
1893 {
1894 $$ = WRITEMASK_XYZW;
1895 }
1896 | DOT writemask_x writemask_y writemask_z writemask_w
1897 {
1898 $$ = $2 | $3 | $4 | $5;
1899 }
1900 ;
1901
1902 writemask_x:
1903 /* empty */ { $$ = 0; }
1904 | X { $$ = 1 << BRW_CHANNEL_X; }
1905 ;
1906
1907 writemask_y:
1908 /* empty */ { $$ = 0; }
1909 | Y { $$ = 1 << BRW_CHANNEL_Y; }
1910 ;
1911
1912 writemask_z:
1913 /* empty */ { $$ = 0; }
1914 | Z { $$ = 1 << BRW_CHANNEL_Z; }
1915 ;
1916
1917 writemask_w:
1918 /* empty */ { $$ = 0; }
1919 | W { $$ = 1 << BRW_CHANNEL_W; }
1920 ;
1921
1922 swizzle:
1923 /* empty */
1924 {
1925 $$ = BRW_SWIZZLE_NOOP;
1926 }
1927 | DOT chansel
1928 {
1929 $$ = BRW_SWIZZLE4($2, $2, $2, $2);
1930 }
1931 | DOT chansel chansel chansel chansel
1932 {
1933 $$ = BRW_SWIZZLE4($2, $3, $4, $5);
1934 }
1935 ;
1936
1937 chansel:
1938 X
1939 | Y
1940 | Z
1941 | W
1942 ;
1943
1944 /* Instruction prediction and modifiers */
1945 predicate:
1946 /* empty */
1947 {
1948 brw_push_insn_state(p);
1949 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1950 brw_set_default_flag_reg(p, 0, 0);
1951 brw_set_default_predicate_inverse(p, false);
1952 }
1953 | LPAREN predstate flagreg predctrl RPAREN
1954 {
1955 brw_push_insn_state(p);
1956 brw_set_default_predicate_inverse(p, $2);
1957 brw_set_default_flag_reg(p, $3.nr, $3.subnr);
1958 brw_set_default_predicate_control(p, $4);
1959 }
1960 ;
1961
1962 predstate:
1963 /* empty */ { $$ = 0; }
1964 | PLUS { $$ = 0; }
1965 | MINUS { $$ = 1; }
1966 ;
1967
1968 predctrl:
1969 /* empty */ { $$ = BRW_PREDICATE_NORMAL; }
1970 | DOT X { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_X; }
1971 | DOT Y { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_Y; }
1972 | DOT Z { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_Z; }
1973 | DOT W { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_W; }
1974 | ANYV
1975 | ALLV
1976 | ANY2H
1977 | ALL2H
1978 | ANY4H
1979 | ALL4H
1980 | ANY8H
1981 | ALL8H
1982 | ANY16H
1983 | ALL16H
1984 | ANY32H
1985 | ALL32H
1986 ;
1987
1988 /* Source Modification */
1989 negate:
1990 /* empty */ { $$ = 0; }
1991 | MINUS { $$ = 1; }
1992 ;
1993
1994 abs:
1995 /* empty */ { $$ = 0; }
1996 | ABS { $$ = 1; }
1997 ;
1998
1999 /* Flag (Conditional) Modifier */
2000 cond_mod:
2001 condModifiers
2002 {
2003 $$.cond_modifier = $1;
2004 $$.flag_reg_nr = 0;
2005 $$.flag_subreg_nr = 0;
2006 }
2007 | condModifiers DOT flagreg
2008 {
2009 $$.cond_modifier = $1;
2010 $$.flag_reg_nr = $3.nr;
2011 $$.flag_subreg_nr = $3.subnr;
2012 }
2013 ;
2014
2015 condModifiers:
2016 /* empty */ { $$ = BRW_CONDITIONAL_NONE; }
2017 | ZERO
2018 | EQUAL
2019 | NOT_ZERO
2020 | NOT_EQUAL
2021 | GREATER
2022 | GREATER_EQUAL
2023 | LESS
2024 | LESS_EQUAL
2025 | OVERFLOW
2026 | ROUND_INCREMENT
2027 | UNORDERED
2028 ;
2029
2030 /* message details for send */
2031 msgdesc:
2032 MSGDESC_BEGIN msgdesc_parts MSGDESC_END { $$ = $2; }
2033 ;
2034
2035 msgdesc_parts:
2036 SRC1_LEN ASSIGN INTEGER msgdesc_parts
2037 {
2038 $$ = $4;
2039 $$.src1_len = $3;
2040 }
2041 | EX_BSO msgdesc_parts
2042 {
2043 $$ = $2;
2044 $$.ex_bso = 1;
2045 }
2046 | INTEGER msgdesc_parts { $$ = $2; }
2047 | ASSIGN msgdesc_parts { $$ = $2; }
2048 | /* empty */
2049 {
2050 memset(&$$, 0, sizeof($$));
2051 }
2052 ;
2053
2054 saturate:
2055 /* empty */ { $$ = BRW_INSTRUCTION_NORMAL; }
2056 | SATURATE { $$ = BRW_INSTRUCTION_SATURATE; }
2057 ;
2058
2059 /* Execution size */
2060 execsize:
2061 /* empty */ %prec EMPTYEXECSIZE
2062 {
2063 $$ = 0;
2064 }
2065 | LPAREN exp2 RPAREN
2066 {
2067 if ($2 > 32 || !isPowerofTwo($2))
2068 error(&@2, "Invalid execution size %llu\n", $2);
2069
2070 $$ = cvt($2) - 1;
2071 }
2072 ;
2073
2074 /* Instruction options */
2075 instoptions:
2076 /* empty */
2077 {
2078 memset(&$$, 0, sizeof($$));
2079 }
2080 | LCURLY instoption_list RCURLY
2081 {
2082 memset(&$$, 0, sizeof($$));
2083 $$ = $2;
2084 }
2085 ;
2086
2087 instoption_list:
2088 instoption_list COMMA instoption
2089 {
2090 memset(&$$, 0, sizeof($$));
2091 $$ = $1;
2092 add_instruction_option(&$$, $3);
2093 }
2094 | instoption_list instoption
2095 {
2096 memset(&$$, 0, sizeof($$));
2097 $$ = $1;
2098 add_instruction_option(&$$, $2);
2099 }
2100 | /* empty */
2101 {
2102 memset(&$$, 0, sizeof($$));
2103 }
2104 ;
2105
2106 depinfo:
2107 REG_DIST_CURRENT
2108 {
2109 memset(&$$, 0, sizeof($$));
2110 $$.regdist = $1;
2111 $$.pipe = TGL_PIPE_NONE;
2112 }
2113 | REG_DIST_FLOAT
2114 {
2115 memset(&$$, 0, sizeof($$));
2116 $$.regdist = $1;
2117 $$.pipe = TGL_PIPE_FLOAT;
2118 }
2119 | REG_DIST_INT
2120 {
2121 memset(&$$, 0, sizeof($$));
2122 $$.regdist = $1;
2123 $$.pipe = TGL_PIPE_INT;
2124 }
2125 | REG_DIST_LONG
2126 {
2127 memset(&$$, 0, sizeof($$));
2128 $$.regdist = $1;
2129 $$.pipe = TGL_PIPE_LONG;
2130 }
2131 | REG_DIST_ALL
2132 {
2133 memset(&$$, 0, sizeof($$));
2134 $$.regdist = $1;
2135 $$.pipe = TGL_PIPE_ALL;
2136 }
2137 | SBID_ALLOC
2138 {
2139 memset(&$$, 0, sizeof($$));
2140 $$.sbid = $1;
2141 $$.mode = TGL_SBID_SET;
2142 }
2143 | SBID_WAIT_SRC
2144 {
2145 memset(&$$, 0, sizeof($$));
2146 $$.sbid = $1;
2147 $$.mode = TGL_SBID_SRC;
2148 }
2149 | SBID_WAIT_DST
2150 {
2151 memset(&$$, 0, sizeof($$));
2152 $$.sbid = $1;
2153 $$.mode = TGL_SBID_DST;
2154 }
2155
2156 instoption:
2157 ALIGN1 { $$.type = INSTOPTION_FLAG; $$.uint_value = ALIGN1;}
2158 | ALIGN16 { $$.type = INSTOPTION_FLAG; $$.uint_value = ALIGN16; }
2159 | ACCWREN { $$.type = INSTOPTION_FLAG; $$.uint_value = ACCWREN; }
2160 | BREAKPOINT { $$.type = INSTOPTION_FLAG; $$.uint_value = BREAKPOINT; }
2161 | NODDCLR { $$.type = INSTOPTION_FLAG; $$.uint_value = NODDCLR; }
2162 | NODDCHK { $$.type = INSTOPTION_FLAG; $$.uint_value = NODDCHK; }
2163 | MASK_DISABLE { $$.type = INSTOPTION_FLAG; $$.uint_value = MASK_DISABLE; }
2164 | EOT { $$.type = INSTOPTION_FLAG; $$.uint_value = EOT; }
2165 | SWITCH { $$.type = INSTOPTION_FLAG; $$.uint_value = SWITCH; }
2166 | ATOMIC { $$.type = INSTOPTION_FLAG; $$.uint_value = ATOMIC; }
2167 | CMPTCTRL { $$.type = INSTOPTION_FLAG; $$.uint_value = CMPTCTRL; }
2168 | WECTRL { $$.type = INSTOPTION_FLAG; $$.uint_value = WECTRL; }
2169 | QTR_2Q { $$.type = INSTOPTION_FLAG; $$.uint_value = QTR_2Q; }
2170 | QTR_3Q { $$.type = INSTOPTION_FLAG; $$.uint_value = QTR_3Q; }
2171 | QTR_4Q { $$.type = INSTOPTION_FLAG; $$.uint_value = QTR_4Q; }
2172 | QTR_2H { $$.type = INSTOPTION_FLAG; $$.uint_value = QTR_2H; }
2173 | QTR_2N { $$.type = INSTOPTION_FLAG; $$.uint_value = QTR_2N; }
2174 | QTR_3N { $$.type = INSTOPTION_FLAG; $$.uint_value = QTR_3N; }
2175 | QTR_4N { $$.type = INSTOPTION_FLAG; $$.uint_value = QTR_4N; }
2176 | QTR_5N { $$.type = INSTOPTION_FLAG; $$.uint_value = QTR_5N; }
2177 | QTR_6N { $$.type = INSTOPTION_FLAG; $$.uint_value = QTR_6N; }
2178 | QTR_7N { $$.type = INSTOPTION_FLAG; $$.uint_value = QTR_7N; }
2179 | QTR_8N { $$.type = INSTOPTION_FLAG; $$.uint_value = QTR_8N; }
2180 | depinfo { $$.type = INSTOPTION_DEP_INFO; $$.depinfo_value = $1; }
2181 ;
2182
2183 %%
2184
2185 extern int yylineno;
2186
2187 #ifdef YYBYACC
2188 void
yyerror(YYLTYPE * ltype,char * msg)2189 yyerror(YYLTYPE *ltype, char *msg)
2190 #else
2191 void
2192 yyerror(char *msg)
2193 #endif
2194 {
2195 fprintf(stderr, "%s: %d: %s at \"%s\"\n",
2196 input_filename, yylineno, msg, lex_text());
2197 ++errors;
2198 }
2199