1 /* -*- c++ -*- */ 2 /* 3 * Copyright © 2010-2016 Intel Corporation 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 22 * IN THE SOFTWARE. 23 */ 24 25 #ifndef BRW_IR_H 26 #define BRW_IR_H 27 28 #include <assert.h> 29 #include "brw_reg.h" 30 #include "compiler/glsl/list.h" 31 32 #define MAX_SAMPLER_MESSAGE_SIZE 11 33 34 /* The sampler can return a vec5 when sampling with sparse residency. In 35 * SIMD32, each component takes up 4 GRFs, so we need to allow up to size-20 36 * VGRFs to hold the result. 37 */ 38 #define MAX_VGRF_SIZE(devinfo) ((devinfo)->ver >= 20 ? 40 : 20) 39 40 #ifdef __cplusplus 41 struct backend_reg : private brw_reg 42 { backend_regbackend_reg43 backend_reg() {} backend_regbackend_reg44 backend_reg(const struct brw_reg ®) : brw_reg(reg), offset(0) {} 45 as_brw_regbackend_reg46 const brw_reg &as_brw_reg() const 47 { 48 assert(file == ARF || file == FIXED_GRF || file == IMM); 49 assert(offset == 0); 50 return static_cast<const brw_reg &>(*this); 51 } 52 as_brw_regbackend_reg53 brw_reg &as_brw_reg() 54 { 55 assert(file == ARF || file == FIXED_GRF || file == IMM); 56 assert(offset == 0); 57 return static_cast<brw_reg &>(*this); 58 } 59 60 bool equals(const backend_reg &r) const; 61 bool negative_equals(const backend_reg &r) const; 62 63 bool is_zero() const; 64 bool is_one() const; 65 bool is_negative_one() const; 66 bool is_null() const; 67 bool is_accumulator() const; 68 69 /** Offset from the start of the (virtual) register in bytes. */ 70 uint16_t offset; 71 72 using brw_reg::type; 73 using brw_reg::file; 74 using brw_reg::negate; 75 using brw_reg::abs; 76 using brw_reg::address_mode; 77 using brw_reg::subnr; 78 using brw_reg::nr; 79 80 using brw_reg::swizzle; 81 using brw_reg::writemask; 82 using brw_reg::indirect_offset; 83 using brw_reg::vstride; 84 using brw_reg::width; 85 using brw_reg::hstride; 86 87 using brw_reg::df; 88 using brw_reg::f; 89 using brw_reg::d; 90 using brw_reg::ud; 91 using brw_reg::d64; 92 using brw_reg::u64; 93 }; 94 95 struct bblock_t; 96 97 struct backend_instruction : public exec_node { 98 bool is_3src(const struct brw_compiler *compiler) const; 99 bool is_math() const; 100 bool is_control_flow_begin() const; 101 bool is_control_flow_end() const; 102 bool is_control_flow() const; 103 bool is_commutative() const; 104 bool can_do_source_mods() const; 105 bool can_do_saturate() const; 106 bool can_do_cmod() const; 107 bool reads_accumulator_implicitly() const; 108 bool writes_accumulator_implicitly(const struct intel_device_info *devinfo) const; 109 110 /** 111 * Instructions that use indirect addressing have additional register 112 * regioning restrictions. 113 */ 114 bool uses_indirect_addressing() const; 115 116 void remove(bblock_t *block, bool defer_later_block_ip_updates = false); 117 void insert_after(bblock_t *block, backend_instruction *inst); 118 void insert_before(bblock_t *block, backend_instruction *inst); 119 120 /** 121 * True if the instruction has side effects other than writing to 122 * its destination registers. You are expected not to reorder or 123 * optimize these out unless you know what you are doing. 124 */ 125 bool has_side_effects() const; 126 127 /** 128 * True if the instruction might be affected by side effects of other 129 * instructions. 130 */ 131 bool is_volatile() const; 132 #else 133 struct backend_instruction { 134 struct exec_node link; 135 #endif 136 /** @{ 137 * Annotation for the generated IR. One of the two can be set. 138 */ 139 const void *ir; 140 const char *annotation; 141 /** @} */ 142 143 /** 144 * Execution size of the instruction. This is used by the generator to 145 * generate the correct binary for the given instruction. Current valid 146 * values are 1, 4, 8, 16, 32. 147 */ 148 uint8_t exec_size; 149 150 /** 151 * Channel group from the hardware execution and predication mask that 152 * should be applied to the instruction. The subset of channel enable 153 * signals (calculated from the EU control flow and predication state) 154 * given by [group, group + exec_size) will be used to mask GRF writes and 155 * any other side effects of the instruction. 156 */ 157 uint8_t group; 158 159 uint32_t offset; /**< spill/unspill offset or texture offset bitfield */ 160 uint8_t mlen; /**< SEND message length */ 161 uint8_t ex_mlen; /**< SENDS extended message length */ 162 uint8_t target; /**< MRT target. */ 163 uint8_t sfid; /**< SFID for SEND instructions */ 164 uint32_t desc; /**< SEND[S] message descriptor immediate */ 165 uint32_t ex_desc; /**< SEND[S] extended message descriptor immediate */ 166 unsigned size_written; /**< Data written to the destination register in bytes. */ 167 168 enum opcode opcode; /* BRW_OPCODE_* or FS_OPCODE_* */ 169 enum brw_conditional_mod conditional_mod; /**< BRW_CONDITIONAL_* */ 170 enum brw_predicate predicate; 171 bool predicate_inverse:1; 172 bool writes_accumulator:1; /**< instruction implicitly writes accumulator */ 173 bool force_writemask_all:1; 174 bool no_dd_clear:1; 175 bool no_dd_check:1; 176 bool saturate:1; 177 bool shadow_compare:1; 178 bool check_tdr:1; /**< Only valid for SEND; turns it into a SENDC */ 179 bool send_has_side_effects:1; /**< Only valid for SHADER_OPCODE_SEND */ 180 bool send_is_volatile:1; /**< Only valid for SHADER_OPCODE_SEND */ 181 bool send_ex_desc_scratch:1; /**< Only valid for SHADER_OPCODE_SEND, use 182 * the scratch surface offset to build 183 * extended descriptor 184 */ 185 bool send_ex_bso:1; /**< Only for SHADER_OPCODE_SEND, use extended bindless 186 * surface offset (26bits instead of 20bits) 187 */ 188 bool predicate_trivial:1; /**< The predication mask applied to this 189 * instruction is guaranteed to be uniform and 190 * a superset of the execution mask of the 191 * present block, no currently enabled channels 192 * will be disabled by the predicate. 193 */ 194 bool eot:1; 195 196 /* Chooses which flag subregister (f0.0 to f3.1) is used for conditional 197 * mod and predication. 198 */ 199 unsigned flag_subreg:3; 200 201 /** 202 * Systolic depth used by DPAS instruction. 203 */ 204 unsigned sdepth:4; 205 206 /** 207 * Repeat count used by DPAS instruction. 208 */ 209 unsigned rcount:4; 210 211 /** The number of hardware registers used for a message header. */ 212 uint8_t header_size; 213 }; 214 215 #endif 216