1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #ifndef BRW_SHADER_H
25 #define BRW_SHADER_H
26
27 #include <stdint.h>
28 #include "brw_cfg.h"
29 #include "brw_compiler.h"
30 #include "compiler/nir/nir.h"
31
32 #ifdef __cplusplus
33 #include "brw_ir_analysis.h"
34 #include "brw_ir_allocator.h"
35
36 enum instruction_scheduler_mode {
37 SCHEDULE_PRE,
38 SCHEDULE_PRE_NON_LIFO,
39 SCHEDULE_PRE_LIFO,
40 SCHEDULE_POST,
41 SCHEDULE_NONE,
42 };
43
44 #define UBO_START ((1 << 16) - 4)
45
46 struct backend_shader {
47 protected:
48
49 backend_shader(const struct brw_compiler *compiler,
50 const struct brw_compile_params *params,
51 const nir_shader *shader,
52 struct brw_stage_prog_data *stage_prog_data,
53 bool debug_enabled);
54
55 public:
56 virtual ~backend_shader();
57
58 const struct brw_compiler *compiler;
59 void *log_data; /* Passed to compiler->*_log functions */
60
61 const struct intel_device_info * const devinfo;
62 const nir_shader *nir;
63 struct brw_stage_prog_data * const stage_prog_data;
64
65 /** ralloc context for temporary data used during compile */
66 void *mem_ctx;
67
68 /**
69 * List of either fs_inst or vec4_instruction (inheriting from
70 * backend_instruction)
71 */
72 exec_list instructions;
73
74 cfg_t *cfg;
75 brw_analysis<brw::idom_tree, backend_shader> idom_analysis;
76
77 gl_shader_stage stage;
78 bool debug_enabled;
79
80 brw::simple_allocator alloc;
81
82 virtual void dump_instruction_to_file(const backend_instruction *inst, FILE *file) const = 0;
83 virtual void dump_instructions_to_file(FILE *file) const;
84
85 /* Convenience functions based on the above. */
86 void dump_instruction(const backend_instruction *inst, FILE *file = stderr) const {
87 dump_instruction_to_file(inst, file);
88 }
89 void dump_instructions(const char *name = nullptr) const;
90
91 void calculate_cfg();
92
93 virtual void invalidate_analysis(brw::analysis_dependency_class c);
94 };
95
96 bool opt_predicated_break(backend_shader &s);
97
98 #else
99 struct backend_shader;
100 #endif /* __cplusplus */
101
102 enum brw_reg_type brw_type_for_base_type(const struct glsl_type *type);
103 uint32_t brw_math_function(enum opcode op);
104 const char *brw_instruction_name(const struct brw_isa_info *isa,
105 enum opcode op);
106 bool brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg);
107 bool brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg);
108 bool brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg);
109
110 #ifdef __cplusplus
111 extern "C" {
112 #endif
113
114 /* brw_fs_reg_allocate.cpp */
115 void brw_fs_alloc_reg_sets(struct brw_compiler *compiler);
116
117 /* brw_disasm.c */
118 extern const char *const conditional_modifier[16];
119 extern const char *const pred_ctrl_align16[16];
120
121 /* Per-thread scratch space is a power-of-two multiple of 1KB. */
122 static inline unsigned
brw_get_scratch_size(int size)123 brw_get_scratch_size(int size)
124 {
125 return MAX2(1024, util_next_power_of_two(size));
126 }
127
128
129 static inline nir_variable_mode
brw_nir_no_indirect_mask(const struct brw_compiler * compiler,gl_shader_stage stage)130 brw_nir_no_indirect_mask(const struct brw_compiler *compiler,
131 gl_shader_stage stage)
132 {
133 nir_variable_mode indirect_mask = (nir_variable_mode) 0;
134
135 switch (stage) {
136 case MESA_SHADER_VERTEX:
137 case MESA_SHADER_FRAGMENT:
138 indirect_mask |= nir_var_shader_in;
139 break;
140
141 default:
142 /* Everything else can handle indirect inputs */
143 break;
144 }
145
146 if (stage != MESA_SHADER_TESS_CTRL &&
147 stage != MESA_SHADER_TASK &&
148 stage != MESA_SHADER_MESH)
149 indirect_mask |= nir_var_shader_out;
150
151 return indirect_mask;
152 }
153
154 bool brw_texture_offset(const nir_tex_instr *tex, unsigned src,
155 uint32_t *offset_bits);
156
157 /**
158 * Scratch data used when compiling a GLSL geometry shader.
159 */
160 struct brw_gs_compile
161 {
162 struct brw_gs_prog_key key;
163 struct intel_vue_map input_vue_map;
164
165 unsigned control_data_bits_per_vertex;
166 unsigned control_data_header_size_bits;
167 };
168
169 #ifdef __cplusplus
170 }
171 #endif
172
173 #endif /* BRW_SHADER_H */
174