1 /* 2 * Copyright © 2024 Intel Corporation 3 * SPDX-License-Identifier: MIT 4 */ 5 6 #ifndef ELK_EU_OPCODES_H 7 #define ELK_EU_OPCODES_H 8 9 #ifdef __cplusplus 10 extern "C" { 11 #endif 12 13 enum elk_opcode { 14 /* These are the actual hardware instructions. */ 15 ELK_OPCODE_ILLEGAL, 16 ELK_OPCODE_SYNC, 17 ELK_OPCODE_MOV, 18 ELK_OPCODE_SEL, 19 ELK_OPCODE_MOVI, /**< G45+ */ 20 ELK_OPCODE_NOT, 21 ELK_OPCODE_AND, 22 ELK_OPCODE_OR, 23 ELK_OPCODE_XOR, 24 ELK_OPCODE_SHR, 25 ELK_OPCODE_SHL, 26 ELK_OPCODE_DIM, /**< Gfx7.5 only */ 27 ELK_OPCODE_SMOV, /**< Gfx8+ */ 28 ELK_OPCODE_ASR, 29 ELK_OPCODE_ROR, /**< Gfx11+ */ 30 ELK_OPCODE_ROL, /**< Gfx11+ */ 31 ELK_OPCODE_CMP, 32 ELK_OPCODE_CMPN, 33 ELK_OPCODE_CSEL, /**< Gfx8+ */ 34 ELK_OPCODE_F32TO16, /**< Gfx7 only */ 35 ELK_OPCODE_F16TO32, /**< Gfx7 only */ 36 ELK_OPCODE_BFREV, /**< Gfx7+ */ 37 ELK_OPCODE_BFE, /**< Gfx7+ */ 38 ELK_OPCODE_BFI1, /**< Gfx7+ */ 39 ELK_OPCODE_BFI2, /**< Gfx7+ */ 40 ELK_OPCODE_JMPI, 41 ELK_OPCODE_BRD, /**< Gfx7+ */ 42 ELK_OPCODE_IF, 43 ELK_OPCODE_IFF, /**< Pre-Gfx6 */ 44 ELK_OPCODE_BRC, /**< Gfx7+ */ 45 ELK_OPCODE_ELSE, 46 ELK_OPCODE_ENDIF, 47 ELK_OPCODE_DO, /**< Pre-Gfx6 */ 48 ELK_OPCODE_CASE, /**< Gfx6 only */ 49 ELK_OPCODE_WHILE, 50 ELK_OPCODE_BREAK, 51 ELK_OPCODE_CONTINUE, 52 ELK_OPCODE_HALT, 53 ELK_OPCODE_CALLA, /**< Gfx7.5+ */ 54 ELK_OPCODE_MSAVE, /**< Pre-Gfx6 */ 55 ELK_OPCODE_CALL, /**< Gfx6+ */ 56 ELK_OPCODE_MREST, /**< Pre-Gfx6 */ 57 ELK_OPCODE_RET, /**< Gfx6+ */ 58 ELK_OPCODE_PUSH, /**< Pre-Gfx6 */ 59 ELK_OPCODE_FORK, /**< Gfx6 only */ 60 ELK_OPCODE_GOTO, /**< Gfx8+ */ 61 ELK_OPCODE_POP, /**< Pre-Gfx6 */ 62 ELK_OPCODE_WAIT, 63 ELK_OPCODE_SEND, 64 ELK_OPCODE_SENDC, 65 ELK_OPCODE_SENDS, /**< Gfx9+ */ 66 ELK_OPCODE_SENDSC, /**< Gfx9+ */ 67 ELK_OPCODE_MATH, /**< Gfx6+ */ 68 ELK_OPCODE_ADD, 69 ELK_OPCODE_MUL, 70 ELK_OPCODE_AVG, 71 ELK_OPCODE_FRC, 72 ELK_OPCODE_RNDU, 73 ELK_OPCODE_RNDD, 74 ELK_OPCODE_RNDE, 75 ELK_OPCODE_RNDZ, 76 ELK_OPCODE_MAC, 77 ELK_OPCODE_MACH, 78 ELK_OPCODE_LZD, 79 ELK_OPCODE_FBH, /**< Gfx7+ */ 80 ELK_OPCODE_FBL, /**< Gfx7+ */ 81 ELK_OPCODE_CBIT, /**< Gfx7+ */ 82 ELK_OPCODE_ADDC, /**< Gfx7+ */ 83 ELK_OPCODE_SUBB, /**< Gfx7+ */ 84 ELK_OPCODE_SAD2, 85 ELK_OPCODE_SADA2, 86 ELK_OPCODE_ADD3, /* Gen12+ only */ 87 ELK_OPCODE_DP4, 88 ELK_OPCODE_DPH, 89 ELK_OPCODE_DP3, 90 ELK_OPCODE_DP2, 91 ELK_OPCODE_DP4A, /**< Gfx12+ */ 92 ELK_OPCODE_LINE, 93 ELK_OPCODE_DPAS, /**< Gfx12.5+ */ 94 ELK_OPCODE_PLN, /**< G45+ */ 95 ELK_OPCODE_MAD, /**< Gfx6+ */ 96 ELK_OPCODE_LRP, /**< Gfx6+ */ 97 ELK_OPCODE_MADM, /**< Gfx8+ */ 98 ELK_OPCODE_NENOP, /**< G45 only */ 99 ELK_OPCODE_NOP, 100 101 NUM_ELK_OPCODES, 102 103 /* These are compiler backend opcodes that get translated into other 104 * instructions. 105 */ 106 ELK_FS_OPCODE_FB_WRITE = NUM_ELK_OPCODES, 107 108 /** 109 * Same as ELK_FS_OPCODE_FB_WRITE but expects its arguments separately as 110 * individual sources instead of as a single payload blob. The 111 * position/ordering of the arguments are defined by the enum 112 * fb_write_logical_srcs. 113 */ 114 ELK_FS_OPCODE_FB_WRITE_LOGICAL, 115 116 ELK_FS_OPCODE_REP_FB_WRITE, 117 118 ELK_FS_OPCODE_FB_READ, 119 ELK_FS_OPCODE_FB_READ_LOGICAL, 120 121 ELK_SHADER_OPCODE_RCP, 122 ELK_SHADER_OPCODE_RSQ, 123 ELK_SHADER_OPCODE_SQRT, 124 ELK_SHADER_OPCODE_EXP2, 125 ELK_SHADER_OPCODE_LOG2, 126 ELK_SHADER_OPCODE_POW, 127 ELK_SHADER_OPCODE_INT_QUOTIENT, 128 ELK_SHADER_OPCODE_INT_REMAINDER, 129 ELK_SHADER_OPCODE_SIN, 130 ELK_SHADER_OPCODE_COS, 131 132 /** 133 * A generic "send" opcode. The first two sources are the message 134 * descriptor and extended message descriptor respectively. The third 135 * and optional fourth sources are the message payload 136 */ 137 ELK_SHADER_OPCODE_SEND, 138 139 /** 140 * An "undefined" write which does nothing but indicates to liveness that 141 * we don't care about any values in the register which predate this 142 * instruction. Used to prevent partial writes from causing issues with 143 * live ranges. 144 */ 145 ELK_SHADER_OPCODE_UNDEF, 146 147 /** 148 * Texture sampling opcodes. 149 * 150 * LOGICAL opcodes are eventually translated to the matching non-LOGICAL 151 * opcode but instead of taking a single payload blob they expect their 152 * arguments separately as individual sources. The position/ordering of the 153 * arguments are defined by the enum tex_logical_srcs. 154 */ 155 ELK_SHADER_OPCODE_TEX, 156 ELK_SHADER_OPCODE_TEX_LOGICAL, 157 ELK_SHADER_OPCODE_TXD, 158 ELK_SHADER_OPCODE_TXD_LOGICAL, 159 ELK_SHADER_OPCODE_TXF, 160 ELK_SHADER_OPCODE_TXF_LOGICAL, 161 ELK_SHADER_OPCODE_TXF_LZ, 162 ELK_SHADER_OPCODE_TXL, 163 ELK_SHADER_OPCODE_TXL_LOGICAL, 164 ELK_SHADER_OPCODE_TXL_LZ, 165 ELK_SHADER_OPCODE_TXS, 166 ELK_SHADER_OPCODE_TXS_LOGICAL, 167 ELK_FS_OPCODE_TXB, 168 ELK_FS_OPCODE_TXB_LOGICAL, 169 ELK_SHADER_OPCODE_TXF_CMS, 170 ELK_SHADER_OPCODE_TXF_CMS_LOGICAL, 171 ELK_SHADER_OPCODE_TXF_CMS_W, 172 ELK_SHADER_OPCODE_TXF_CMS_W_LOGICAL, 173 ELK_SHADER_OPCODE_TXF_CMS_W_GFX12_LOGICAL, 174 ELK_SHADER_OPCODE_TXF_UMS, 175 ELK_SHADER_OPCODE_TXF_UMS_LOGICAL, 176 ELK_SHADER_OPCODE_TXF_MCS, 177 ELK_SHADER_OPCODE_TXF_MCS_LOGICAL, 178 ELK_SHADER_OPCODE_LOD, 179 ELK_SHADER_OPCODE_LOD_LOGICAL, 180 ELK_SHADER_OPCODE_TG4, 181 ELK_SHADER_OPCODE_TG4_LOGICAL, 182 ELK_SHADER_OPCODE_TG4_OFFSET, 183 ELK_SHADER_OPCODE_TG4_OFFSET_LOGICAL, 184 ELK_SHADER_OPCODE_SAMPLEINFO, 185 ELK_SHADER_OPCODE_SAMPLEINFO_LOGICAL, 186 187 ELK_SHADER_OPCODE_IMAGE_SIZE_LOGICAL, 188 189 /** 190 * Combines multiple sources of size 1 into a larger virtual GRF. 191 * For example, parameters for a send-from-GRF message. Or, updating 192 * channels of a size 4 VGRF used to store vec4s such as texturing results. 193 * 194 * This will be lowered into MOVs from each source to consecutive offsets 195 * of the destination VGRF. 196 * 197 * src[0] may be BAD_FILE. If so, the lowering pass skips emitting the MOV, 198 * but still reserves the first channel of the destination VGRF. This can be 199 * used to reserve space for, say, a message header set up by the generators. 200 */ 201 ELK_SHADER_OPCODE_LOAD_PAYLOAD, 202 203 /** 204 * Packs a number of sources into a single value. Unlike LOAD_PAYLOAD, this 205 * acts intra-channel, obtaining the final value for each channel by 206 * combining the sources values for the same channel, the first source 207 * occupying the lowest bits and the last source occupying the highest 208 * bits. 209 */ 210 ELK_FS_OPCODE_PACK, 211 212 /** 213 * Typed and untyped surface access opcodes. 214 * 215 * LOGICAL opcodes are eventually translated to the matching non-LOGICAL 216 * opcode but instead of taking a single payload blob they expect their 217 * arguments separately as individual sources: 218 * 219 * Source 0: [required] Surface coordinates. 220 * Source 1: [optional] Operation source. 221 * Source 2: [required] Surface index. 222 * Source 3: [required] Number of coordinate components (as UD immediate). 223 * Source 4: [required] Opcode-specific control immediate, same as source 2 224 * of the matching non-LOGICAL opcode. 225 */ 226 ELK_VEC4_OPCODE_UNTYPED_ATOMIC, 227 ELK_SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL, 228 ELK_VEC4_OPCODE_UNTYPED_SURFACE_READ, 229 ELK_SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL, 230 ELK_VEC4_OPCODE_UNTYPED_SURFACE_WRITE, 231 ELK_SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL, 232 233 ELK_SHADER_OPCODE_UNALIGNED_OWORD_BLOCK_READ_LOGICAL, 234 ELK_SHADER_OPCODE_OWORD_BLOCK_WRITE_LOGICAL, 235 236 /** 237 * Untyped A64 surface access opcodes. 238 * 239 * Source 0: 64-bit address 240 * Source 1: Operational source 241 * Source 2: [required] Opcode-specific control immediate, same as source 2 242 * of the matching non-LOGICAL opcode. 243 */ 244 ELK_SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL, 245 ELK_SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL, 246 ELK_SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL, 247 ELK_SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL, 248 ELK_SHADER_OPCODE_A64_OWORD_BLOCK_READ_LOGICAL, 249 ELK_SHADER_OPCODE_A64_UNALIGNED_OWORD_BLOCK_READ_LOGICAL, 250 ELK_SHADER_OPCODE_A64_OWORD_BLOCK_WRITE_LOGICAL, 251 ELK_SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL, 252 253 ELK_SHADER_OPCODE_TYPED_ATOMIC_LOGICAL, 254 ELK_SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL, 255 ELK_SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL, 256 257 ELK_SHADER_OPCODE_RND_MODE, 258 ELK_SHADER_OPCODE_FLOAT_CONTROL_MODE, 259 260 /** 261 * Byte scattered write/read opcodes. 262 * 263 * LOGICAL opcodes are eventually translated to the matching non-LOGICAL 264 * opcode, but instead of taking a single payload blog they expect their 265 * arguments separately as individual sources, like untyped write/read. 266 */ 267 ELK_SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL, 268 ELK_SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL, 269 ELK_SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL, 270 ELK_SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL, 271 272 /** 273 * Memory fence messages. 274 * 275 * Source 0: Must be register g0, used as header. 276 * Source 1: Immediate bool to indicate whether control is returned to the 277 * thread only after the fence has been honored. 278 * Source 2: Immediate byte indicating which memory to fence. Zero means 279 * global memory; GFX7_BTI_SLM means SLM (for Gfx11+ only). 280 * 281 * Vec4 backend only uses Source 0. 282 */ 283 ELK_SHADER_OPCODE_MEMORY_FENCE, 284 285 /** 286 * Scheduling-only fence. 287 * 288 * Sources can be used to force a stall until the registers in those are 289 * available. This might generate MOVs or SYNC_NOPs (Gfx12+). 290 */ 291 ELK_FS_OPCODE_SCHEDULING_FENCE, 292 293 ELK_SHADER_OPCODE_GFX4_SCRATCH_READ, 294 ELK_SHADER_OPCODE_GFX4_SCRATCH_WRITE, 295 ELK_SHADER_OPCODE_GFX7_SCRATCH_READ, 296 297 ELK_SHADER_OPCODE_SCRATCH_HEADER, 298 299 /** 300 * Gfx8+ SIMD8 URB messages. 301 */ 302 ELK_SHADER_OPCODE_URB_READ_LOGICAL, 303 ELK_SHADER_OPCODE_URB_WRITE_LOGICAL, 304 305 /** 306 * Return the index of the first enabled live channel and assign it to 307 * to the first component of the destination. Frequently used as input 308 * for the BROADCAST pseudo-opcode. 309 */ 310 ELK_SHADER_OPCODE_FIND_LIVE_CHANNEL, 311 312 /** 313 * Return the index of the last enabled live channel and assign it to 314 * the first component of the destination. 315 */ 316 ELK_SHADER_OPCODE_FIND_LAST_LIVE_CHANNEL, 317 318 /** 319 * Return the current execution mask in the specified flag subregister. 320 * Can be CSE'ed more easily than a plain MOV from the ce0 ARF register. 321 */ 322 ELK_FS_OPCODE_LOAD_LIVE_CHANNELS, 323 324 /** 325 * Pick the channel from its first source register given by the index 326 * specified as second source. Useful for variable indexing of surfaces. 327 * 328 * Note that because the result of this instruction is by definition 329 * uniform and it can always be splatted to multiple channels using a 330 * scalar regioning mode, only the first channel of the destination region 331 * is guaranteed to be updated, which implies that BROADCAST instructions 332 * should usually be marked force_writemask_all. 333 */ 334 ELK_SHADER_OPCODE_BROADCAST, 335 336 /* Pick the channel from its first source register given by the index 337 * specified as second source. 338 * 339 * This is similar to the BROADCAST instruction except that it takes a 340 * dynamic index and potentially puts a different value in each output 341 * channel. 342 */ 343 ELK_SHADER_OPCODE_SHUFFLE, 344 345 /* Select between src0 and src1 based on channel enables. 346 * 347 * This instruction copies src0 into the enabled channels of the 348 * destination and copies src1 into the disabled channels. 349 */ 350 ELK_SHADER_OPCODE_SEL_EXEC, 351 352 /* This turns into an align16 mov from src0 to dst with a swizzle 353 * provided as an immediate in src1. 354 */ 355 ELK_SHADER_OPCODE_QUAD_SWIZZLE, 356 357 /* Take every Nth element in src0 and broadcast it to the group of N 358 * channels in which it lives in the destination. The offset within the 359 * cluster is given by src1 and the cluster size is given by src2. 360 */ 361 ELK_SHADER_OPCODE_CLUSTER_BROADCAST, 362 363 ELK_SHADER_OPCODE_GET_BUFFER_SIZE, 364 365 ELK_SHADER_OPCODE_INTERLOCK, 366 367 /** Target for a HALT 368 * 369 * All HALT instructions in a shader must target the same jump point and 370 * that point is denoted by a HALT_TARGET instruction. 371 */ 372 ELK_SHADER_OPCODE_HALT_TARGET, 373 374 ELK_VEC4_OPCODE_MOV_BYTES, 375 ELK_VEC4_OPCODE_PACK_BYTES, 376 ELK_VEC4_OPCODE_UNPACK_UNIFORM, 377 ELK_VEC4_OPCODE_DOUBLE_TO_F32, 378 ELK_VEC4_OPCODE_DOUBLE_TO_D32, 379 ELK_VEC4_OPCODE_DOUBLE_TO_U32, 380 ELK_VEC4_OPCODE_TO_DOUBLE, 381 ELK_VEC4_OPCODE_PICK_LOW_32BIT, 382 ELK_VEC4_OPCODE_PICK_HIGH_32BIT, 383 ELK_VEC4_OPCODE_SET_LOW_32BIT, 384 ELK_VEC4_OPCODE_SET_HIGH_32BIT, 385 ELK_VEC4_OPCODE_MOV_FOR_SCRATCH, 386 ELK_VEC4_OPCODE_ZERO_OOB_PUSH_REGS, 387 388 ELK_FS_OPCODE_DDX_COARSE, 389 ELK_FS_OPCODE_DDX_FINE, 390 /** 391 * Compute dFdy(), dFdyCoarse(), or dFdyFine(). 392 */ 393 ELK_FS_OPCODE_DDY_COARSE, 394 ELK_FS_OPCODE_DDY_FINE, 395 ELK_FS_OPCODE_LINTERP, 396 ELK_FS_OPCODE_PIXEL_X, 397 ELK_FS_OPCODE_PIXEL_Y, 398 ELK_FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD, 399 ELK_FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GFX4, 400 ELK_FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL, 401 ELK_FS_OPCODE_SET_SAMPLE_ID, 402 ELK_FS_OPCODE_PACK_HALF_2x16_SPLIT, 403 ELK_FS_OPCODE_INTERPOLATE_AT_SAMPLE, 404 ELK_FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET, 405 ELK_FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET, 406 407 ELK_VEC4_VS_OPCODE_URB_WRITE, 408 ELK_VS_OPCODE_PULL_CONSTANT_LOAD, 409 ELK_VS_OPCODE_PULL_CONSTANT_LOAD_GFX7, 410 411 ELK_VS_OPCODE_UNPACK_FLAGS_SIMD4X2, 412 413 /** 414 * Write geometry shader output data to the URB. 415 * 416 * Unlike ELK_VEC4_VS_OPCODE_URB_WRITE, this opcode doesn't do an implied move from 417 * R0 to the first MRF. This allows the geometry shader to override the 418 * "Slot {0,1} Offset" fields in the message header. 419 */ 420 ELK_VEC4_GS_OPCODE_URB_WRITE, 421 422 /** 423 * Write geometry shader output data to the URB and request a new URB 424 * handle (gfx6). 425 * 426 * This opcode doesn't do an implied move from R0 to the first MRF. 427 */ 428 ELK_VEC4_GS_OPCODE_URB_WRITE_ALLOCATE, 429 430 /** 431 * Terminate the geometry shader thread by doing an empty URB write. 432 * 433 * This opcode doesn't do an implied move from R0 to the first MRF. This 434 * allows the geometry shader to override the "GS Number of Output Vertices 435 * for Slot {0,1}" fields in the message header. 436 */ 437 ELK_GS_OPCODE_THREAD_END, 438 439 /** 440 * Set the "Slot {0,1} Offset" fields of a URB_WRITE message header. 441 * 442 * - dst is the MRF containing the message header. 443 * 444 * - src0.x indicates which portion of the URB should be written to (e.g. a 445 * vertex number) 446 * 447 * - src1 is an immediate multiplier which will be applied to src0 448 * (e.g. the size of a single vertex in the URB). 449 * 450 * Note: the hardware will apply this offset *in addition to* the offset in 451 * vec4_instruction::offset. 452 */ 453 ELK_GS_OPCODE_SET_WRITE_OFFSET, 454 455 /** 456 * Set the "GS Number of Output Vertices for Slot {0,1}" fields of a 457 * URB_WRITE message header. 458 * 459 * - dst is the MRF containing the message header. 460 * 461 * - src0.x is the vertex count. The upper 16 bits will be ignored. 462 */ 463 ELK_GS_OPCODE_SET_VERTEX_COUNT, 464 465 /** 466 * Set DWORD 2 of dst to the value in src. 467 */ 468 ELK_GS_OPCODE_SET_DWORD_2, 469 470 /** 471 * Prepare the dst register for storage in the "Channel Mask" fields of a 472 * URB_WRITE message header. 473 * 474 * DWORD 4 of dst is shifted left by 4 bits, so that later, 475 * ELK_GS_OPCODE_SET_CHANNEL_MASKS can OR DWORDs 0 and 4 together to form the 476 * final channel mask. 477 * 478 * Note: since ELK_GS_OPCODE_SET_CHANNEL_MASKS ORs DWORDs 0 and 4 together to 479 * form the final channel mask, DWORDs 0 and 4 of the dst register must not 480 * have any extraneous bits set prior to execution of this opcode (that is, 481 * they should be in the range 0x0 to 0xf). 482 */ 483 ELK_GS_OPCODE_PREPARE_CHANNEL_MASKS, 484 485 /** 486 * Set the "Channel Mask" fields of a URB_WRITE message header. 487 * 488 * - dst is the MRF containing the message header. 489 * 490 * - src.x is the channel mask, as prepared by 491 * ELK_GS_OPCODE_PREPARE_CHANNEL_MASKS. DWORDs 0 and 4 are OR'ed together to 492 * form the final channel mask. 493 */ 494 ELK_GS_OPCODE_SET_CHANNEL_MASKS, 495 496 /** 497 * Get the "Instance ID" fields from the payload. 498 * 499 * - dst is the GRF for gl_InvocationID. 500 */ 501 ELK_GS_OPCODE_GET_INSTANCE_ID, 502 503 /** 504 * Send a FF_SYNC message to allocate initial URB handles (gfx6). 505 * 506 * - dst will be used as the writeback register for the FF_SYNC operation. 507 * 508 * - src0 is the number of primitives written. 509 * 510 * - src1 is the value to hold in M0.0: number of SO vertices to write 511 * and number of SO primitives needed. Its value will be overwritten 512 * with the SVBI values if transform feedback is enabled. 513 * 514 * Note: This opcode uses an implicit MRF register for the ff_sync message 515 * header, so the caller is expected to set inst->base_mrf and initialize 516 * that MRF register to r0. This opcode will also write to this MRF register 517 * to include the allocated URB handle so it can then be reused directly as 518 * the header in the URB write operation we are allocating the handle for. 519 */ 520 ELK_GS_OPCODE_FF_SYNC, 521 522 /** 523 * Move r0.1 (which holds PrimitiveID information in gfx6) to a separate 524 * register. 525 * 526 * - dst is the GRF where PrimitiveID information will be moved. 527 */ 528 ELK_GS_OPCODE_SET_PRIMITIVE_ID, 529 530 /** 531 * Write transform feedback data to the SVB by sending a SVB WRITE message. 532 * Used in gfx6. 533 * 534 * - dst is the MRF register containing the message header. 535 * 536 * - src0 is the register where the vertex data is going to be copied from. 537 * 538 * - src1 is the destination register when write commit occurs. 539 */ 540 ELK_GS_OPCODE_SVB_WRITE, 541 542 /** 543 * Set destination index in the SVB write message payload (M0.5). Used 544 * in gfx6 for transform feedback. 545 * 546 * - dst is the header to save the destination indices for SVB WRITE. 547 * - src is the register that holds the destination indices value. 548 */ 549 ELK_GS_OPCODE_SVB_SET_DST_INDEX, 550 551 /** 552 * Prepare Mx.0 subregister for being used in the FF_SYNC message header. 553 * Used in gfx6 for transform feedback. 554 * 555 * - dst will hold the register with the final Mx.0 value. 556 * 557 * - src0 has the number of vertices emitted in SO (NumSOVertsToWrite) 558 * 559 * - src1 has the number of needed primitives for SO (NumSOPrimsNeeded) 560 * 561 * - src2 is the value to hold in M0: number of SO vertices to write 562 * and number of SO primitives needed. 563 */ 564 ELK_GS_OPCODE_FF_SYNC_SET_PRIMITIVES, 565 566 /** 567 * Terminate the compute shader. 568 */ 569 ELK_CS_OPCODE_CS_TERMINATE, 570 571 /** 572 * GLSL barrier() 573 */ 574 ELK_SHADER_OPCODE_BARRIER, 575 576 /** 577 * Calculate the high 32-bits of a 32x32 multiply. 578 */ 579 ELK_SHADER_OPCODE_MULH, 580 581 /** Signed subtraction with saturation. */ 582 ELK_SHADER_OPCODE_ISUB_SAT, 583 584 /** Unsigned subtraction with saturation. */ 585 ELK_SHADER_OPCODE_USUB_SAT, 586 587 /** 588 * A MOV that uses VxH indirect addressing. 589 * 590 * Source 0: A register to start from (HW_REG). 591 * Source 1: An indirect offset (in bytes, UD GRF). 592 * Source 2: The length of the region that could be accessed (in bytes, 593 * UD immediate). 594 */ 595 ELK_SHADER_OPCODE_MOV_INDIRECT, 596 597 /** Fills out a relocatable immediate */ 598 ELK_SHADER_OPCODE_MOV_RELOC_IMM, 599 600 ELK_VEC4_OPCODE_URB_READ, 601 ELK_TCS_OPCODE_GET_INSTANCE_ID, 602 ELK_VEC4_TCS_OPCODE_URB_WRITE, 603 ELK_VEC4_TCS_OPCODE_SET_INPUT_URB_OFFSETS, 604 ELK_VEC4_TCS_OPCODE_SET_OUTPUT_URB_OFFSETS, 605 ELK_TCS_OPCODE_GET_PRIMITIVE_ID, 606 ELK_TCS_OPCODE_CREATE_BARRIER_HEADER, 607 ELK_TCS_OPCODE_SRC0_010_IS_ZERO, 608 ELK_TCS_OPCODE_RELEASE_INPUT, 609 ELK_TCS_OPCODE_THREAD_END, 610 611 ELK_TES_OPCODE_GET_PRIMITIVE_ID, 612 ELK_TES_OPCODE_CREATE_INPUT_READ_HEADER, 613 ELK_TES_OPCODE_ADD_INDIRECT_URB_OFFSET, 614 615 ELK_SHADER_OPCODE_BTD_SPAWN_LOGICAL, 616 ELK_SHADER_OPCODE_BTD_RETIRE_LOGICAL, 617 618 ELK_SHADER_OPCODE_READ_SR_REG, 619 620 ELK_RT_OPCODE_TRACE_RAY_LOGICAL, 621 }; 622 623 624 #ifdef __cplusplus 625 } 626 #endif 627 628 #endif 629 630