1 /*
2 * Copyright © 2021 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #ifndef INTEL_DRIVER_DS_H
25 #define INTEL_DRIVER_DS_H
26
27 #include <stdint.h>
28
29 #include "util/macros.h"
30 #include "util/perf/u_trace.h"
31 #include "util/u_vector.h"
32
33 #include "dev/intel_device_info.h"
34
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38
39 enum intel_ds_api {
40 INTEL_DS_API_OPENGL,
41 INTEL_DS_API_VULKAN,
42 };
43
44 enum intel_ds_stall_flag {
45 INTEL_DS_DEPTH_CACHE_FLUSH_BIT = BITFIELD_BIT(0),
46 INTEL_DS_DATA_CACHE_FLUSH_BIT = BITFIELD_BIT(1),
47 INTEL_DS_HDC_PIPELINE_FLUSH_BIT = BITFIELD_BIT(2),
48 INTEL_DS_RENDER_TARGET_CACHE_FLUSH_BIT = BITFIELD_BIT(3),
49 INTEL_DS_TILE_CACHE_FLUSH_BIT = BITFIELD_BIT(4),
50 INTEL_DS_STATE_CACHE_INVALIDATE_BIT = BITFIELD_BIT(5),
51 INTEL_DS_CONST_CACHE_INVALIDATE_BIT = BITFIELD_BIT(6),
52 INTEL_DS_VF_CACHE_INVALIDATE_BIT = BITFIELD_BIT(7),
53 INTEL_DS_TEXTURE_CACHE_INVALIDATE_BIT = BITFIELD_BIT(8),
54 INTEL_DS_INST_CACHE_INVALIDATE_BIT = BITFIELD_BIT(9),
55 INTEL_DS_STALL_AT_SCOREBOARD_BIT = BITFIELD_BIT(10),
56 INTEL_DS_DEPTH_STALL_BIT = BITFIELD_BIT(11),
57 INTEL_DS_CS_STALL_BIT = BITFIELD_BIT(12),
58 INTEL_DS_UNTYPED_DATAPORT_CACHE_FLUSH_BIT = BITFIELD_BIT(13),
59 INTEL_DS_PSS_STALL_SYNC_BIT = BITFIELD_BIT(14),
60 INTEL_DS_END_OF_PIPE_BIT = BITFIELD_BIT(15),
61 INTEL_DS_CCS_CACHE_FLUSH_BIT = BITFIELD_BIT(16),
62 };
63
64 /* Convert internal driver PIPE_CONTROL stall bits to intel_ds_stall_flag. */
65 typedef enum intel_ds_stall_flag (*intel_ds_stall_cb_t)(uint32_t flags);
66
67 enum intel_ds_queue_stage {
68 INTEL_DS_QUEUE_STAGE_QUEUE,
69 INTEL_DS_QUEUE_STAGE_FRAME,
70 INTEL_DS_QUEUE_STAGE_CMD_BUFFER,
71 INTEL_DS_QUEUE_STAGE_INTERNAL_OPS,
72 INTEL_DS_QUEUE_STAGE_STALL,
73 INTEL_DS_QUEUE_STAGE_COMPUTE,
74 INTEL_DS_QUEUE_STAGE_AS,
75 INTEL_DS_QUEUE_STAGE_RT,
76 INTEL_DS_QUEUE_STAGE_RENDER_PASS,
77 INTEL_DS_QUEUE_STAGE_BLORP,
78 INTEL_DS_QUEUE_STAGE_DRAW,
79 INTEL_DS_QUEUE_STAGE_DRAW_MESH,
80 INTEL_DS_QUEUE_STAGE_N_STAGES,
81 };
82
83 struct intel_ds_device {
84 struct intel_device_info info;
85
86 /* DRM fd */
87 int fd;
88
89 /* API of this device */
90 enum intel_ds_api api;
91
92 /* GPU identifier (minor number) */
93 uint32_t gpu_id;
94
95 /* Clock identifier for this device. */
96 uint32_t gpu_clock_id;
97
98 /* The timestamp at the point where we first emitted the clock_sync..
99 * this will be a *later* timestamp that the first GPU traces (since
100 * we capture the first clock_sync from the CPU *after* the first GPU
101 * tracepoints happen). To avoid confusing perfetto we need to drop
102 * the GPU traces with timestamps before this.
103 */
104 uint64_t sync_gpu_ts;
105
106 /* Next timestamp after which we should resend a clock correlation. */
107 uint64_t next_clock_sync_ns;
108
109 /* Unique perfetto identifier for the context */
110 uint64_t iid;
111
112 /* Event ID generator (manipulate only inside
113 * IntelRenderpassDataSource::Trace)
114 */
115 uint64_t event_id;
116
117 /* Tracepoint name perfetto identifiers for each of the events. */
118 uint64_t tracepoint_iids[96];
119
120 /* Protects submissions of u_trace data to trace_context */
121 simple_mtx_t trace_context_mutex;
122
123 struct u_trace_context trace_context;
124
125 /* List of intel_ds_queue */
126 struct list_head queues;
127 };
128
129 struct intel_ds_stage {
130 /* Unique hw_queue IID */
131 uint64_t queue_iid;
132
133 /* Unique stage IID */
134 uint64_t stage_iid;
135
136 /* Start timestamp of the last work element. We have a array indexed by
137 * level so that we can track multi levels of events (like
138 * primary/secondary command buffers).
139 */
140 uint64_t start_ns[5];
141
142 /* Current number of valid elements in start_ns */
143 uint32_t level;
144 };
145
146 struct intel_ds_queue {
147 struct list_head link;
148
149 /* Device this queue belongs to */
150 struct intel_ds_device *device;
151
152 /* Unique name of the queue */
153 char name[80];
154
155 /* Counter incremented on each intel_ds_end_submit() call */
156 uint64_t submission_id;
157
158 struct intel_ds_stage stages[INTEL_DS_QUEUE_STAGE_N_STAGES];
159 };
160
161 struct intel_ds_flush_data {
162 struct intel_ds_queue *queue;
163
164 /* u_trace element in which we copy other traces in case we deal with
165 * reusable command buffers.
166 */
167 struct u_trace trace;
168
169 /* Unique submission ID associated with the trace */
170 uint64_t submission_id;
171 };
172
173 void intel_driver_ds_init(void);
174
175 void intel_ds_device_init(struct intel_ds_device *device,
176 const struct intel_device_info *devinfo,
177 int drm_fd,
178 uint32_t gpu_id,
179 enum intel_ds_api api);
180 void intel_ds_device_fini(struct intel_ds_device *device);
181
182 struct intel_ds_queue *
183 intel_ds_device_init_queue(struct intel_ds_device *device,
184 struct intel_ds_queue *queue,
185 const char *fmt_name,
186 ...);
187
188 void intel_ds_flush_data_init(struct intel_ds_flush_data *data,
189 struct intel_ds_queue *queue,
190 uint64_t submission_id);
191
192 void intel_ds_flush_data_fini(struct intel_ds_flush_data *data);
193
194 void intel_ds_queue_flush_data(struct intel_ds_queue *queue,
195 struct u_trace *ut,
196 struct intel_ds_flush_data *data,
197 bool free_data);
198
199 void intel_ds_device_process(struct intel_ds_device *device, bool eof);
200
201 #ifdef HAVE_PERFETTO
202
203 uint64_t intel_ds_begin_submit(struct intel_ds_queue *queue);
204 void intel_ds_end_submit(struct intel_ds_queue *queue,
205 uint64_t start_ts);
206
207 #else
208
intel_ds_begin_submit(struct intel_ds_queue * queue)209 static inline uint64_t intel_ds_begin_submit(struct intel_ds_queue *queue)
210 {
211 return 0;
212 }
213
intel_ds_end_submit(struct intel_ds_queue * queue,uint64_t start_ts)214 static inline void intel_ds_end_submit(struct intel_ds_queue *queue,
215 uint64_t start_ts)
216 {
217 }
218
219 #endif /* HAVE_PERFETTO */
220
221 #ifdef __cplusplus
222 }
223 #endif
224
225 #endif /* INTEL_DRIVER_DS_H */
226