1 /*
2 * Copyright 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /**
25 * @file
26 * @brief Intel Surface Layout
27 *
28 * Header Layout
29 * -------------
30 * The header is ordered as:
31 * - forward declarations
32 * - macros that may be overridden at compile-time for specific gens
33 * - enums and constants
34 * - structs and unions
35 * - functions
36 */
37
38 #ifndef ISL_H
39 #define ISL_H
40
41 #include <assert.h>
42 #include <stdbool.h>
43 #include <stdint.h>
44
45 #include "drm-uapi/drm_fourcc.h"
46 #include "util/compiler.h"
47 #include "util/macros.h"
48 #include "util/format/u_format.h"
49
50 #ifdef __cplusplus
51 extern "C" {
52 #endif
53
54 struct intel_device_info;
55
56 #ifndef ISL_GFX_VER
57 /**
58 * Get the hardware generation of isl_device.
59 *
60 * You can define this as a compile-time constant in the CFLAGS. For example,
61 * `gcc -DISL_GFX_VER(dev)=9 ...`.
62 */
63 #define ISL_GFX_VER(__dev) ((__dev)->info->ver)
64 #define ISL_GFX_VERX10(__dev) ((__dev)->info->verx10)
65 #define ISL_GFX_VER_SANITIZE(__dev)
66 #else
67 #define ISL_GFX_VER_SANITIZE(__dev) \
68 (assert(ISL_GFX_VER(__dev) == (__dev)->info->ver) && \
69 ISL_GFX_VERX10(__dev) == (__dev)->info->verx10))
70 #endif
71
72 #ifndef ISL_DEV_IS_G4X
73 #define ISL_DEV_IS_G4X(__dev) ((__dev)->info->platform == INTEL_PLATFORM_G4X)
74 #endif
75
76 #ifndef ISL_DEV_IS_HASWELL
77 /**
78 * @brief Get the hardware generation of isl_device.
79 *
80 * You can define this as a compile-time constant in the CFLAGS. For example,
81 * `gcc -DISL_GFX_VER(dev)=9 ...`.
82 */
83 #define ISL_DEV_IS_HASWELL(__dev) ((__dev)->info->platform == INTEL_PLATFORM_HSW)
84 #endif
85
86 #ifndef ISL_DEV_IS_BAYTRAIL
87 #define ISL_DEV_IS_BAYTRAIL(__dev) ((__dev)->info->platform == INTEL_PLATFORM_BYT)
88 #endif
89
90 #ifndef ISL_DEV_USE_SEPARATE_STENCIL
91 /**
92 * You can define this as a compile-time constant in the CFLAGS. For example,
93 * `gcc -DISL_DEV_USE_SEPARATE_STENCIL(dev)=1 ...`.
94 */
95 #define ISL_DEV_USE_SEPARATE_STENCIL(__dev) ((__dev)->use_separate_stencil)
96 #define ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(__dev)
97 #else
98 #define ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(__dev) \
99 (assert(ISL_DEV_USE_SEPARATE_STENCIL(__dev) == (__dev)->use_separate_stencil))
100 #endif
101
102 /**
103 * Hardware enumeration SURFACE_FORMAT.
104 *
105 * For the official list, see Broadwell PRM: Volume 2b: Command Reference:
106 * Enumerations: SURFACE_FORMAT.
107 */
108 enum isl_format {
109 ISL_FORMAT_R32G32B32A32_FLOAT = 0,
110 ISL_FORMAT_R32G32B32A32_SINT = 1,
111 ISL_FORMAT_R32G32B32A32_UINT = 2,
112 ISL_FORMAT_R32G32B32A32_UNORM = 3,
113 ISL_FORMAT_R32G32B32A32_SNORM = 4,
114 ISL_FORMAT_R64G64_FLOAT = 5,
115 ISL_FORMAT_R32G32B32X32_FLOAT = 6,
116 ISL_FORMAT_R32G32B32A32_SSCALED = 7,
117 ISL_FORMAT_R32G32B32A32_USCALED = 8,
118 ISL_FORMAT_R32G32B32A32_SFIXED = 32,
119 ISL_FORMAT_R64G64_PASSTHRU = 33,
120 ISL_FORMAT_R32G32B32_FLOAT = 64,
121 ISL_FORMAT_R32G32B32_SINT = 65,
122 ISL_FORMAT_R32G32B32_UINT = 66,
123 ISL_FORMAT_R32G32B32_UNORM = 67,
124 ISL_FORMAT_R32G32B32_SNORM = 68,
125 ISL_FORMAT_R32G32B32_SSCALED = 69,
126 ISL_FORMAT_R32G32B32_USCALED = 70,
127 ISL_FORMAT_R32G32B32_SFIXED = 80,
128 ISL_FORMAT_R16G16B16A16_UNORM = 128,
129 ISL_FORMAT_R16G16B16A16_SNORM = 129,
130 ISL_FORMAT_R16G16B16A16_SINT = 130,
131 ISL_FORMAT_R16G16B16A16_UINT = 131,
132 ISL_FORMAT_R16G16B16A16_FLOAT = 132,
133 ISL_FORMAT_R32G32_FLOAT = 133,
134 ISL_FORMAT_R32G32_SINT = 134,
135 ISL_FORMAT_R32G32_UINT = 135,
136 ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS = 136,
137 ISL_FORMAT_X32_TYPELESS_G8X24_UINT = 137,
138 ISL_FORMAT_L32A32_FLOAT = 138,
139 ISL_FORMAT_R32G32_UNORM = 139,
140 ISL_FORMAT_R32G32_SNORM = 140,
141 ISL_FORMAT_R64_FLOAT = 141,
142 ISL_FORMAT_R16G16B16X16_UNORM = 142,
143 ISL_FORMAT_R16G16B16X16_FLOAT = 143,
144 ISL_FORMAT_A32X32_FLOAT = 144,
145 ISL_FORMAT_L32X32_FLOAT = 145,
146 ISL_FORMAT_I32X32_FLOAT = 146,
147 ISL_FORMAT_R16G16B16A16_SSCALED = 147,
148 ISL_FORMAT_R16G16B16A16_USCALED = 148,
149 ISL_FORMAT_R32G32_SSCALED = 149,
150 ISL_FORMAT_R32G32_USCALED = 150,
151 ISL_FORMAT_R32G32_FLOAT_LD = 151,
152 ISL_FORMAT_R32G32_SFIXED = 160,
153 ISL_FORMAT_R64_PASSTHRU = 161,
154 ISL_FORMAT_B8G8R8A8_UNORM = 192,
155 ISL_FORMAT_B8G8R8A8_UNORM_SRGB = 193,
156 ISL_FORMAT_R10G10B10A2_UNORM = 194,
157 ISL_FORMAT_R10G10B10A2_UNORM_SRGB = 195,
158 ISL_FORMAT_R10G10B10A2_UINT = 196,
159 ISL_FORMAT_R10G10B10_SNORM_A2_UNORM = 197,
160 ISL_FORMAT_R8G8B8A8_UNORM = 199,
161 ISL_FORMAT_R8G8B8A8_UNORM_SRGB = 200,
162 ISL_FORMAT_R8G8B8A8_SNORM = 201,
163 ISL_FORMAT_R8G8B8A8_SINT = 202,
164 ISL_FORMAT_R8G8B8A8_UINT = 203,
165 ISL_FORMAT_R16G16_UNORM = 204,
166 ISL_FORMAT_R16G16_SNORM = 205,
167 ISL_FORMAT_R16G16_SINT = 206,
168 ISL_FORMAT_R16G16_UINT = 207,
169 ISL_FORMAT_R16G16_FLOAT = 208,
170 ISL_FORMAT_B10G10R10A2_UNORM = 209,
171 ISL_FORMAT_B10G10R10A2_UNORM_SRGB = 210,
172 ISL_FORMAT_R11G11B10_FLOAT = 211,
173 ISL_FORMAT_R10G10B10_FLOAT_A2_UNORM = 213,
174 ISL_FORMAT_R32_SINT = 214,
175 ISL_FORMAT_R32_UINT = 215,
176 ISL_FORMAT_R32_FLOAT = 216,
177 ISL_FORMAT_R24_UNORM_X8_TYPELESS = 217,
178 ISL_FORMAT_X24_TYPELESS_G8_UINT = 218,
179 ISL_FORMAT_L32_UNORM = 221,
180 ISL_FORMAT_A32_UNORM = 222,
181 ISL_FORMAT_L16A16_UNORM = 223,
182 ISL_FORMAT_I24X8_UNORM = 224,
183 ISL_FORMAT_L24X8_UNORM = 225,
184 ISL_FORMAT_A24X8_UNORM = 226,
185 ISL_FORMAT_I32_FLOAT = 227,
186 ISL_FORMAT_L32_FLOAT = 228,
187 ISL_FORMAT_A32_FLOAT = 229,
188 ISL_FORMAT_X8B8_UNORM_G8R8_SNORM = 230,
189 ISL_FORMAT_A8X8_UNORM_G8R8_SNORM = 231,
190 ISL_FORMAT_B8X8_UNORM_G8R8_SNORM = 232,
191 ISL_FORMAT_B8G8R8X8_UNORM = 233,
192 ISL_FORMAT_B8G8R8X8_UNORM_SRGB = 234,
193 ISL_FORMAT_R8G8B8X8_UNORM = 235,
194 ISL_FORMAT_R8G8B8X8_UNORM_SRGB = 236,
195 ISL_FORMAT_R9G9B9E5_SHAREDEXP = 237,
196 ISL_FORMAT_B10G10R10X2_UNORM = 238,
197 ISL_FORMAT_L16A16_FLOAT = 240,
198 ISL_FORMAT_R32_UNORM = 241,
199 ISL_FORMAT_R32_SNORM = 242,
200 ISL_FORMAT_R10G10B10X2_USCALED = 243,
201 ISL_FORMAT_R8G8B8A8_SSCALED = 244,
202 ISL_FORMAT_R8G8B8A8_USCALED = 245,
203 ISL_FORMAT_R16G16_SSCALED = 246,
204 ISL_FORMAT_R16G16_USCALED = 247,
205 ISL_FORMAT_R32_SSCALED = 248,
206 ISL_FORMAT_R32_USCALED = 249,
207 ISL_FORMAT_B5G6R5_UNORM = 256,
208 ISL_FORMAT_B5G6R5_UNORM_SRGB = 257,
209 ISL_FORMAT_B5G5R5A1_UNORM = 258,
210 ISL_FORMAT_B5G5R5A1_UNORM_SRGB = 259,
211 ISL_FORMAT_B4G4R4A4_UNORM = 260,
212 ISL_FORMAT_B4G4R4A4_UNORM_SRGB = 261,
213 ISL_FORMAT_R8G8_UNORM = 262,
214 ISL_FORMAT_R8G8_SNORM = 263,
215 ISL_FORMAT_R8G8_SINT = 264,
216 ISL_FORMAT_R8G8_UINT = 265,
217 ISL_FORMAT_R16_UNORM = 266,
218 ISL_FORMAT_R16_SNORM = 267,
219 ISL_FORMAT_R16_SINT = 268,
220 ISL_FORMAT_R16_UINT = 269,
221 ISL_FORMAT_R16_FLOAT = 270,
222 ISL_FORMAT_A8P8_UNORM_PALETTE0 = 271,
223 ISL_FORMAT_A8P8_UNORM_PALETTE1 = 272,
224 ISL_FORMAT_I16_UNORM = 273,
225 ISL_FORMAT_L16_UNORM = 274,
226 ISL_FORMAT_A16_UNORM = 275,
227 ISL_FORMAT_L8A8_UNORM = 276,
228 ISL_FORMAT_I16_FLOAT = 277,
229 ISL_FORMAT_L16_FLOAT = 278,
230 ISL_FORMAT_A16_FLOAT = 279,
231 ISL_FORMAT_L8A8_UNORM_SRGB = 280,
232 ISL_FORMAT_R5G5_SNORM_B6_UNORM = 281,
233 ISL_FORMAT_B5G5R5X1_UNORM = 282,
234 ISL_FORMAT_B5G5R5X1_UNORM_SRGB = 283,
235 ISL_FORMAT_R8G8_SSCALED = 284,
236 ISL_FORMAT_R8G8_USCALED = 285,
237 ISL_FORMAT_R16_SSCALED = 286,
238 ISL_FORMAT_R16_USCALED = 287,
239 ISL_FORMAT_P8A8_UNORM_PALETTE0 = 290,
240 ISL_FORMAT_P8A8_UNORM_PALETTE1 = 291,
241 ISL_FORMAT_A1B5G5R5_UNORM = 292,
242 ISL_FORMAT_A4B4G4R4_UNORM = 293,
243 ISL_FORMAT_L8A8_UINT = 294,
244 ISL_FORMAT_L8A8_SINT = 295,
245 ISL_FORMAT_R8_UNORM = 320,
246 ISL_FORMAT_R8_SNORM = 321,
247 ISL_FORMAT_R8_SINT = 322,
248 ISL_FORMAT_R8_UINT = 323,
249 ISL_FORMAT_A8_UNORM = 324,
250 ISL_FORMAT_I8_UNORM = 325,
251 ISL_FORMAT_L8_UNORM = 326,
252 ISL_FORMAT_P4A4_UNORM_PALETTE0 = 327,
253 ISL_FORMAT_A4P4_UNORM_PALETTE0 = 328,
254 ISL_FORMAT_R8_SSCALED = 329,
255 ISL_FORMAT_R8_USCALED = 330,
256 ISL_FORMAT_P8_UNORM_PALETTE0 = 331,
257 ISL_FORMAT_L8_UNORM_SRGB = 332,
258 ISL_FORMAT_P8_UNORM_PALETTE1 = 333,
259 ISL_FORMAT_P4A4_UNORM_PALETTE1 = 334,
260 ISL_FORMAT_A4P4_UNORM_PALETTE1 = 335,
261 ISL_FORMAT_Y8_UNORM = 336,
262 ISL_FORMAT_L8_UINT = 338,
263 ISL_FORMAT_L8_SINT = 339,
264 ISL_FORMAT_I8_UINT = 340,
265 ISL_FORMAT_I8_SINT = 341,
266 ISL_FORMAT_DXT1_RGB_SRGB = 384,
267 ISL_FORMAT_R1_UNORM = 385,
268 ISL_FORMAT_YCRCB_NORMAL = 386,
269 ISL_FORMAT_YCRCB_SWAPUVY = 387,
270 ISL_FORMAT_P2_UNORM_PALETTE0 = 388,
271 ISL_FORMAT_P2_UNORM_PALETTE1 = 389,
272 ISL_FORMAT_BC1_UNORM = 390,
273 ISL_FORMAT_BC2_UNORM = 391,
274 ISL_FORMAT_BC3_UNORM = 392,
275 ISL_FORMAT_BC4_UNORM = 393,
276 ISL_FORMAT_BC5_UNORM = 394,
277 ISL_FORMAT_BC1_UNORM_SRGB = 395,
278 ISL_FORMAT_BC2_UNORM_SRGB = 396,
279 ISL_FORMAT_BC3_UNORM_SRGB = 397,
280 ISL_FORMAT_MONO8 = 398,
281 ISL_FORMAT_YCRCB_SWAPUV = 399,
282 ISL_FORMAT_YCRCB_SWAPY = 400,
283 ISL_FORMAT_DXT1_RGB = 401,
284 ISL_FORMAT_FXT1 = 402,
285 ISL_FORMAT_R8G8B8_UNORM = 403,
286 ISL_FORMAT_R8G8B8_SNORM = 404,
287 ISL_FORMAT_R8G8B8_SSCALED = 405,
288 ISL_FORMAT_R8G8B8_USCALED = 406,
289 ISL_FORMAT_R64G64B64A64_FLOAT = 407,
290 ISL_FORMAT_R64G64B64_FLOAT = 408,
291 ISL_FORMAT_BC4_SNORM = 409,
292 ISL_FORMAT_BC5_SNORM = 410,
293 ISL_FORMAT_R16G16B16_FLOAT = 411,
294 ISL_FORMAT_R16G16B16_UNORM = 412,
295 ISL_FORMAT_R16G16B16_SNORM = 413,
296 ISL_FORMAT_R16G16B16_SSCALED = 414,
297 ISL_FORMAT_R16G16B16_USCALED = 415,
298 ISL_FORMAT_BC6H_SF16 = 417,
299 ISL_FORMAT_BC7_UNORM = 418,
300 ISL_FORMAT_BC7_UNORM_SRGB = 419,
301 ISL_FORMAT_BC6H_UF16 = 420,
302 ISL_FORMAT_PLANAR_420_8 = 421,
303 ISL_FORMAT_PLANAR_420_16 = 422,
304 ISL_FORMAT_R8G8B8_UNORM_SRGB = 424,
305 ISL_FORMAT_ETC1_RGB8 = 425,
306 ISL_FORMAT_ETC2_RGB8 = 426,
307 ISL_FORMAT_EAC_R11 = 427,
308 ISL_FORMAT_EAC_RG11 = 428,
309 ISL_FORMAT_EAC_SIGNED_R11 = 429,
310 ISL_FORMAT_EAC_SIGNED_RG11 = 430,
311 ISL_FORMAT_ETC2_SRGB8 = 431,
312 ISL_FORMAT_R16G16B16_UINT = 432,
313 ISL_FORMAT_R16G16B16_SINT = 433,
314 ISL_FORMAT_R32_SFIXED = 434,
315 ISL_FORMAT_R10G10B10A2_SNORM = 435,
316 ISL_FORMAT_R10G10B10A2_USCALED = 436,
317 ISL_FORMAT_R10G10B10A2_SSCALED = 437,
318 ISL_FORMAT_R10G10B10A2_SINT = 438,
319 ISL_FORMAT_B10G10R10A2_SNORM = 439,
320 ISL_FORMAT_B10G10R10A2_USCALED = 440,
321 ISL_FORMAT_B10G10R10A2_SSCALED = 441,
322 ISL_FORMAT_B10G10R10A2_UINT = 442,
323 ISL_FORMAT_B10G10R10A2_SINT = 443,
324 ISL_FORMAT_R64G64B64A64_PASSTHRU = 444,
325 ISL_FORMAT_R64G64B64_PASSTHRU = 445,
326 ISL_FORMAT_ETC2_RGB8_PTA = 448,
327 ISL_FORMAT_ETC2_SRGB8_PTA = 449,
328 ISL_FORMAT_ETC2_EAC_RGBA8 = 450,
329 ISL_FORMAT_ETC2_EAC_SRGB8_A8 = 451,
330 ISL_FORMAT_R8G8B8_UINT = 456,
331 ISL_FORMAT_R8G8B8_SINT = 457,
332 ISL_FORMAT_RAW = 511,
333 ISL_FORMAT_ASTC_LDR_2D_4X4_U8SRGB = 512,
334 ISL_FORMAT_ASTC_LDR_2D_5X4_U8SRGB = 520,
335 ISL_FORMAT_ASTC_LDR_2D_5X5_U8SRGB = 521,
336 ISL_FORMAT_ASTC_LDR_2D_6X5_U8SRGB = 529,
337 ISL_FORMAT_ASTC_LDR_2D_6X6_U8SRGB = 530,
338 ISL_FORMAT_ASTC_LDR_2D_8X5_U8SRGB = 545,
339 ISL_FORMAT_ASTC_LDR_2D_8X6_U8SRGB = 546,
340 ISL_FORMAT_ASTC_LDR_2D_8X8_U8SRGB = 548,
341 ISL_FORMAT_ASTC_LDR_2D_10X5_U8SRGB = 561,
342 ISL_FORMAT_ASTC_LDR_2D_10X6_U8SRGB = 562,
343 ISL_FORMAT_ASTC_LDR_2D_10X8_U8SRGB = 564,
344 ISL_FORMAT_ASTC_LDR_2D_10X10_U8SRGB = 566,
345 ISL_FORMAT_ASTC_LDR_2D_12X10_U8SRGB = 574,
346 ISL_FORMAT_ASTC_LDR_2D_12X12_U8SRGB = 575,
347 ISL_FORMAT_ASTC_LDR_2D_4X4_FLT16 = 576,
348 ISL_FORMAT_ASTC_LDR_2D_5X4_FLT16 = 584,
349 ISL_FORMAT_ASTC_LDR_2D_5X5_FLT16 = 585,
350 ISL_FORMAT_ASTC_LDR_2D_6X5_FLT16 = 593,
351 ISL_FORMAT_ASTC_LDR_2D_6X6_FLT16 = 594,
352 ISL_FORMAT_ASTC_LDR_2D_8X5_FLT16 = 609,
353 ISL_FORMAT_ASTC_LDR_2D_8X6_FLT16 = 610,
354 ISL_FORMAT_ASTC_LDR_2D_8X8_FLT16 = 612,
355 ISL_FORMAT_ASTC_LDR_2D_10X5_FLT16 = 625,
356 ISL_FORMAT_ASTC_LDR_2D_10X6_FLT16 = 626,
357 ISL_FORMAT_ASTC_LDR_2D_10X8_FLT16 = 628,
358 ISL_FORMAT_ASTC_LDR_2D_10X10_FLT16 = 630,
359 ISL_FORMAT_ASTC_LDR_2D_12X10_FLT16 = 638,
360 ISL_FORMAT_ASTC_LDR_2D_12X12_FLT16 = 639,
361 ISL_FORMAT_ASTC_HDR_2D_4X4_FLT16 = 832,
362 ISL_FORMAT_ASTC_HDR_2D_5X4_FLT16 = 840,
363 ISL_FORMAT_ASTC_HDR_2D_5X5_FLT16 = 841,
364 ISL_FORMAT_ASTC_HDR_2D_6X5_FLT16 = 849,
365 ISL_FORMAT_ASTC_HDR_2D_6X6_FLT16 = 850,
366 ISL_FORMAT_ASTC_HDR_2D_8X5_FLT16 = 865,
367 ISL_FORMAT_ASTC_HDR_2D_8X6_FLT16 = 866,
368 ISL_FORMAT_ASTC_HDR_2D_8X8_FLT16 = 868,
369 ISL_FORMAT_ASTC_HDR_2D_10X5_FLT16 = 881,
370 ISL_FORMAT_ASTC_HDR_2D_10X6_FLT16 = 882,
371 ISL_FORMAT_ASTC_HDR_2D_10X8_FLT16 = 884,
372 ISL_FORMAT_ASTC_HDR_2D_10X10_FLT16 = 886,
373 ISL_FORMAT_ASTC_HDR_2D_12X10_FLT16 = 894,
374 ISL_FORMAT_ASTC_HDR_2D_12X12_FLT16 = 895,
375
376 /* The formats that follow are internal to ISL and as such don't have an
377 * explicit number. We'll just let the C compiler assign it for us. Any
378 * actual hardware formats *must* come before these in the list.
379 */
380
381 /* Formats for the aux-map */
382 ISL_FORMAT_PLANAR_420_10,
383 ISL_FORMAT_PLANAR_420_12,
384
385 /* Formats for auxiliary surfaces */
386 ISL_FORMAT_HIZ,
387 ISL_FORMAT_GFX125_HIZ,
388 ISL_FORMAT_MCS_2X,
389 ISL_FORMAT_MCS_4X,
390 ISL_FORMAT_MCS_8X,
391 ISL_FORMAT_MCS_16X,
392 ISL_FORMAT_GFX7_CCS_32BPP_X,
393 ISL_FORMAT_GFX7_CCS_64BPP_X,
394 ISL_FORMAT_GFX7_CCS_128BPP_X,
395 ISL_FORMAT_GFX7_CCS_32BPP_Y,
396 ISL_FORMAT_GFX7_CCS_64BPP_Y,
397 ISL_FORMAT_GFX7_CCS_128BPP_Y,
398 ISL_FORMAT_GFX9_CCS_32BPP,
399 ISL_FORMAT_GFX9_CCS_64BPP,
400 ISL_FORMAT_GFX9_CCS_128BPP,
401 ISL_FORMAT_GFX12_CCS_8BPP_Y0,
402 ISL_FORMAT_GFX12_CCS_16BPP_Y0,
403 ISL_FORMAT_GFX12_CCS_32BPP_Y0,
404 ISL_FORMAT_GFX12_CCS_64BPP_Y0,
405 ISL_FORMAT_GFX12_CCS_128BPP_Y0,
406
407 /* An upper bound on the supported format enumerations */
408 ISL_NUM_FORMATS,
409
410 /* Hardware doesn't understand this out-of-band value */
411 ISL_FORMAT_UNSUPPORTED = UINT16_MAX,
412 };
413
414 /**
415 * Numerical base type for channels of isl_format.
416 */
417 enum ENUM_PACKED isl_base_type {
418 /** Data which takes up space but is ignored */
419 ISL_VOID,
420
421 /** Data in a "raw" form and cannot be easily interpreted */
422 ISL_RAW,
423
424 /**
425 * Unsigned normalized data
426 *
427 * Though stored as an integer, the data is interpreted as a floating-point
428 * number in the range [0, 1] where the conversion from the in-memory
429 * representation to float is given by :math:`\frac{x}{2^{bits} - 1}`.
430 */
431 ISL_UNORM,
432
433 /**
434 * Signed normalized data
435 *
436 * Though stored as an integer, the data is interpreted as a floating-point
437 * number in the range [-1, 1] where the conversion from the in-memory
438 * representation to float is given by
439 * :math:`max\left(\frac{x}{2^{bits - 1} - 1}, -1\right)`.
440 */
441 ISL_SNORM,
442
443 /**
444 * Unsigned floating-point data
445 *
446 * Unlike the standard IEEE floating-point representation, unsigned
447 * floating-point data has no sign bit. This saves a bit of space which is
448 * important if more than one float is required to represent a color value.
449 * As with IEEE floats, the high bits are the exponent and the low bits are
450 * the mantissa. The available bit sizes for unsigned floats are as
451 * follows:
452 *
453 * ===== ========= =========
454 * Bits Mantissa Exponent
455 * ===== ========= =========
456 * 11 6 5
457 * 10 5 5
458 * ===== ========= =========
459 *
460 * In particular, both unsigned floating-point formats are identical to
461 * IEEE float16 except that the sign bit and the bottom mantissa bits are
462 * removed.
463 */
464 ISL_UFLOAT,
465
466 /** Signed floating-point data
467 *
468 * Signed floating-point data is represented as standard IEEE floats with
469 * the usual number of mantissa and exponent bits
470 *
471 * ===== ========= =========
472 * Bits Mantissa Exponent
473 * ===== ========= =========
474 * 64 52 11
475 * 32 23 8
476 * 16 10 5
477 * ===== ========= =========
478 */
479 ISL_SFLOAT,
480
481 /**
482 * Unsigned fixed-point data
483 *
484 * This is a 32-bit unsigned integer that is interpreted as a 16.16
485 * fixed-point value.
486 */
487 ISL_UFIXED,
488
489 /**
490 * Signed fixed-point data
491 *
492 * This is a 32-bit signed integer that is interpreted as a 16.16
493 * fixed-point value.
494 */
495 ISL_SFIXED,
496
497 /** Unsigned integer data */
498 ISL_UINT,
499
500 /** Signed integer data */
501 ISL_SINT,
502
503 /**
504 * Unsigned scaled data
505 *
506 * This is data which is stored as an unsigned integer but interpreted as a
507 * floating-point value by the hardware. The re-interpretation is done via
508 * a simple unsigned integer to float cast. This is typically used as a
509 * vertex format.
510 */
511 ISL_USCALED,
512
513 /**
514 * Signed scaled data
515 *
516 * This is data which is stored as a signed integer but interpreted as a
517 * floating-point value by the hardware. The re-interpretation is done via
518 * a simple signed integer to float cast. This is typically used as a
519 * vertex format.
520 */
521 ISL_SSCALED,
522 };
523
524 /**
525 * Colorspace of isl_format.
526 */
527 enum isl_colorspace {
528 ISL_COLORSPACE_NONE = 0,
529 ISL_COLORSPACE_LINEAR,
530 ISL_COLORSPACE_SRGB,
531 ISL_COLORSPACE_YUV,
532 };
533
534 /**
535 * Texture compression mode of isl_format.
536 */
537 enum isl_txc {
538 ISL_TXC_NONE = 0,
539 ISL_TXC_DXT1,
540 ISL_TXC_DXT3,
541 ISL_TXC_DXT5,
542 ISL_TXC_FXT1,
543 ISL_TXC_RGTC1,
544 ISL_TXC_RGTC2,
545 ISL_TXC_BPTC,
546 ISL_TXC_ETC1,
547 ISL_TXC_ETC2,
548 ISL_TXC_ASTC,
549
550 /* Used for auxiliary surface formats */
551 ISL_TXC_HIZ,
552 ISL_TXC_MCS,
553 ISL_TXC_CCS,
554 };
555
556 /**
557 * Describes the memory tiling of a surface
558 *
559 * This differs from the HW enum values used to represent tiling. The bits
560 * used by hardware have varried significantly over the years from the
561 * "Tile Walk" bit on old pre-Broadwell parts to the "Tile Mode" enum on
562 * Broadwell to the combination of "Tile Mode" and "Tiled Resource Mode" on
563 * Skylake. This enum represents them all in a consistent manner and in one
564 * place.
565 *
566 * Note that legacy Y tiling is ISL_TILING_Y0 instead of ISL_TILING_Y, to
567 * clearly distinguish it from Yf and Ys.
568 */
569 enum isl_tiling {
570 /** Linear, or no tiling */
571 ISL_TILING_LINEAR = 0,
572 /** W tiling */
573 ISL_TILING_W,
574 /** X tiling */
575 ISL_TILING_X,
576 /** Legacy Y tiling */
577 ISL_TILING_Y0,
578 /** Standard 4K tiling. The 'f' means "four". */
579 ISL_TILING_SKL_Yf,
580 /** Standard 64K tiling. The 's' means "sixty-four". */
581 ISL_TILING_SKL_Ys,
582 /** Standard 4K tiling. The 'f' means "four". */
583 ISL_TILING_ICL_Yf,
584 /** Standard 64K tiling. The 's' means "sixty-four". */
585 ISL_TILING_ICL_Ys,
586 /** 4K tiling. */
587 ISL_TILING_4,
588 /** 64K tiling.*/
589 ISL_TILING_64,
590 /** Xe2 64K tiling.*/
591 ISL_TILING_64_XE2,
592 /** Tiling format for HiZ surfaces */
593 ISL_TILING_HIZ,
594 /** Tiling format for CCS surfaces */
595 ISL_TILING_CCS,
596 /** Tiling format for Gfx12 CCS surfaces */
597 ISL_TILING_GFX12_CCS,
598 };
599
600 /**
601 * @defgroup Tiling Flags
602 * @{
603 */
604 typedef uint32_t isl_tiling_flags_t;
605 #define ISL_TILING_LINEAR_BIT (1u << ISL_TILING_LINEAR)
606 #define ISL_TILING_W_BIT (1u << ISL_TILING_W)
607 #define ISL_TILING_X_BIT (1u << ISL_TILING_X)
608 #define ISL_TILING_Y0_BIT (1u << ISL_TILING_Y0)
609 #define ISL_TILING_SKL_Yf_BIT (1u << ISL_TILING_SKL_Yf)
610 #define ISL_TILING_SKL_Ys_BIT (1u << ISL_TILING_SKL_Ys)
611 #define ISL_TILING_ICL_Yf_BIT (1u << ISL_TILING_ICL_Yf)
612 #define ISL_TILING_ICL_Ys_BIT (1u << ISL_TILING_ICL_Ys)
613 #define ISL_TILING_4_BIT (1u << ISL_TILING_4)
614 #define ISL_TILING_64_BIT (1u << ISL_TILING_64)
615 #define ISL_TILING_64_XE2_BIT (1u << ISL_TILING_64_XE2)
616 #define ISL_TILING_HIZ_BIT (1u << ISL_TILING_HIZ)
617 #define ISL_TILING_CCS_BIT (1u << ISL_TILING_CCS)
618 #define ISL_TILING_GFX12_CCS_BIT (1u << ISL_TILING_GFX12_CCS)
619 #define ISL_TILING_ANY_MASK (~0u)
620 #define ISL_TILING_NON_LINEAR_MASK (~ISL_TILING_LINEAR_BIT)
621
622 /** Any Y tiling, including legacy Y tiling. */
623 #define ISL_TILING_ANY_Y_MASK (ISL_TILING_Y0_BIT | \
624 ISL_TILING_SKL_Yf_BIT | \
625 ISL_TILING_SKL_Ys_BIT | \
626 ISL_TILING_ICL_Yf_BIT | \
627 ISL_TILING_ICL_Ys_BIT)
628
629 /** The Skylake BSpec refers to Yf and Ys as "standard tiling formats". */
630 #define ISL_TILING_STD_Y_MASK (ISL_TILING_SKL_Yf_BIT | \
631 ISL_TILING_SKL_Ys_BIT | \
632 ISL_TILING_ICL_Yf_BIT | \
633 ISL_TILING_ICL_Ys_BIT)
634
635 /** Any Tiling 64 */
636 #define ISL_TILING_STD_64_MASK (ISL_TILING_64_BIT | \
637 ISL_TILING_64_XE2_BIT)
638
639 /** @} */
640
641 /**
642 * @brief Logical dimension of surface.
643 *
644 * Note: There is no dimension for cube map surfaces. ISL interprets cube maps
645 * as 2D array surfaces.
646 */
647 enum isl_surf_dim {
648 ISL_SURF_DIM_1D,
649 ISL_SURF_DIM_2D,
650 ISL_SURF_DIM_3D,
651 };
652
653 /**
654 * @brief Physical layout of the surface's dimensions.
655 */
656 enum isl_dim_layout {
657 /**
658 * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
659 * 6.17.3: 2D Surfaces.
660 *
661 * On many gens, 1D surfaces share the same layout as 2D surfaces. From
662 * the G35 PRM >> Volume 1: Graphics Core >> Section 6.17.2: 1D Surfaces:
663 *
664 * One-dimensional surfaces are identical to 2D surfaces with height of
665 * one.
666 */
667 ISL_DIM_LAYOUT_GFX4_2D,
668
669 /**
670 * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
671 * 6.17.5: 3D Surfaces.
672 *
673 * :invariant: isl_surf::phys_level0_sa::array_len == 1
674 */
675 ISL_DIM_LAYOUT_GFX4_3D,
676
677 /**
678 * Special layout used for HiZ and stencil on Sandy Bridge to work around
679 * the hardware's lack of mipmap support. On gfx6, HiZ and stencil buffers
680 * work the same as on gfx7+ except that they don't technically support
681 * mipmapping. That does not, however, stop us from doing it. As far as
682 * Sandy Bridge hardware is concerned, HiZ and stencil always operates on a
683 * single miplevel 2D (possibly array) image. The dimensions of that image
684 * are NOT minified.
685 *
686 * In order to implement HiZ and stencil on Sandy Bridge, we create one
687 * full-sized 2D (possibly array) image for every LOD with every image
688 * aligned to a page boundary. When the surface is used with the stencil
689 * or HiZ hardware, we manually offset to the image for the given LOD.
690 *
691 * As a memory saving measure, we pretend that the width of each miplevel
692 * is minified and we place LOD1 and above below LOD0 but horizontally
693 * adjacent to each other. When considered as full-sized images, LOD1 and
694 * above technically overlap. However, since we only write to part of that
695 * image, the hardware will never notice the overlap.
696 *
697 * This layout looks something like this:
698 *
699 * +---------+
700 * | |
701 * | |
702 * +---------+
703 * | |
704 * | |
705 * +---------+
706 *
707 * +----+ +-+ .
708 * | | +-+
709 * +----+
710 *
711 * +----+ +-+ .
712 * | | +-+
713 * +----+
714 */
715 ISL_DIM_LAYOUT_GFX6_STENCIL_HIZ,
716
717 /**
718 * For details, see the Skylake BSpec >> Memory Views >> Common Surface
719 * Formats >> Surface Layout and Tiling >> » 1D Surfaces.
720 */
721 ISL_DIM_LAYOUT_GFX9_1D,
722 };
723
724 /**
725 * Enumerates the different forms of auxiliary surface compression
726 */
727 enum isl_aux_usage {
728 /** No Auxiliary surface is used */
729 ISL_AUX_USAGE_NONE,
730
731 /** Hierarchical depth compression
732 *
733 * First introduced on Iron Lake, this compression scheme compresses depth
734 * surfaces by storing alternate forms of the depth value in a HiZ surface.
735 * Possible (not all) compressed forms include:
736 *
737 * - An uncompressed "look at the main surface" value
738 *
739 * - A special value indicating that the main surface data should be
740 * ignored and considered to contain the clear value.
741 *
742 * - The depth for the entire main-surface block as a plane equation
743 *
744 * - The minimum/maximum depth for the main-surface block
745 *
746 * This second one isn't helpful for getting exact depth values but can
747 * still substantially accelerate depth testing if the specified range is
748 * sufficiently small.
749 */
750 ISL_AUX_USAGE_HIZ,
751
752 /** Multisampled color compression
753 *
754 * Introduced on Ivy Bridge, this compression scheme compresses
755 * multisampled color surfaces by storing a mapping from samples to planes
756 * in the MCS surface, allowing for de-duplication of identical samples.
757 * The MCS value of all 1's is reserved to indicate that the pixel contains
758 * the clear color. Exact details about the data stored in the MCS and how
759 * it maps samples to slices is documented in the PRMs.
760 *
761 * :invariant: :c:member:`isl_surf.samples` > 1
762 */
763 ISL_AUX_USAGE_MCS,
764
765 /** Single-sampled fast-clear-only color compression
766 *
767 * Introduced on Ivy Bridge, this compression scheme compresses
768 * single-sampled color surfaces by storing a bit for each cache line pair
769 * in the main surface in the CCS which indicates that the corresponding
770 * pair of cache lines in the main surface only contains the clear color.
771 * On Skylake, this is increased to two bits per cache line pair with 0x0
772 * meaning resolved and 0x3 meaning clear.
773 *
774 * :invariant: The surface is a color surface
775 * :invariant: :c:member:`isl_surf.samples` == 1
776 */
777 ISL_AUX_USAGE_CCS_D,
778
779 /** Single-sample lossless color compression
780 *
781 * Introduced on Skylake, this compression scheme compresses single-sampled
782 * color surfaces by storing a 2-bit value for each cache line pair in the
783 * main surface which says how the corresponding pair of cache lines in the
784 * main surface are to be interpreted. Valid CCS values include:
785 *
786 * - `0x0`: Indicates that the corresponding pair of cache lines in the
787 * main surface contain valid color data
788 *
789 * - `0x1`: Indicates that the corresponding pair of cache lines in the
790 * main surface contain compressed color data. Typically, the
791 * compressed data fits in one of the two cache lines.
792 *
793 * - `0x3`: Indicates that the corresponding pair of cache lines in the
794 * main surface should be ignored. Those cache lines should be
795 * considered to contain the clear color.
796 *
797 * Starting with Tigerlake, each CCS value is 4 bits per cache line pair in
798 * the main surface.
799 *
800 * :invariant: The surface is a color surface
801 * :invariant: :c:member:`isl_surf.samples` == 1
802 */
803 ISL_AUX_USAGE_CCS_E,
804
805 /** Single-sample lossless color compression with fast clear optimization
806 *
807 * Introduced on Tigerlake, this is identical to ISL_AUX_USAGE_CCS_E except
808 * it also encodes a feature about regular render writes possibly
809 * fast-clearing blocks in the surface. In the Alchemist docs, the name of
810 * the feature is easier to find. In the 3DSTATE_3D_MODE packet, it is
811 * referred to as "Fast Clear Optimization (FCV)".
812 *
813 * :invariant: The surface is a color surface
814 * :invariant: :c:member:`isl_surf.samples` == 1
815 */
816 ISL_AUX_USAGE_FCV_CCS_E,
817
818 /** Media color compression
819 *
820 * Used by the media engine on Tigerlake and above. This compression form
821 * is typically not produced by 3D drivers but they need to be able to
822 * consume it in order to get end-to-end compression when the image comes
823 * from media decode.
824 *
825 * :invariant: The surface is a color surface
826 * :invariant: :c:member:`isl_surf.samples` == 1
827 */
828 ISL_AUX_USAGE_MC,
829
830 /** Combined HiZ+CCS in write-through mode
831 *
832 * In this mode, introduced on Tigerlake, the HiZ and CCS surfaces act as a
833 * single fused compression surface where resolves (but not ambiguates)
834 * operate on both surfaces at the same time. In this mode, the HiZ
835 * surface operates in write-through mode where it is only used for
836 * accelerating depth testing and not for actual compression. The
837 * CCS-compressed surface contains valid data at all times.
838 *
839 * :invariant: The surface is a color surface
840 * :invariant: :c:member:`isl_surf.samples` == 1
841 */
842 ISL_AUX_USAGE_HIZ_CCS_WT,
843
844 /** Combined HiZ+CCS without write-through
845 *
846 * In this mode, introduced on Tigerlake, the HiZ and CCS surfaces act as a
847 * single fused compression surface where resolves (but not ambiguates)
848 * operate on both surfaces at the same time. In this mode, full HiZ
849 * compression is enabled and the CCS-compressed main surface may not
850 * contain valid data. The only way to read the surface outside of the
851 * depth hardware is to do a full resolve which resolves both HiZ and CCS
852 * so the surface is in the pass-through state.
853 *
854 * :invariant: The surface is a depth surface
855 */
856 ISL_AUX_USAGE_HIZ_CCS,
857
858 /** Combined MCS+CCS without write-through
859 *
860 * In this mode, introduced on Tigerlake, we have fused MCS+CCS compression
861 * where the MCS is used for fast-clears and "identical samples"
862 * compression just like on Gfx7-11 but each plane is then CCS compressed.
863 *
864 * :invariant: The surface is a depth surface
865 * :invariant: :c:member:`isl_surf.samples` > 1
866 */
867 ISL_AUX_USAGE_MCS_CCS,
868
869 /** Stencil compression
870 *
871 * Introduced on Tigerlake, this is similar to CCS_E only used to compress
872 * stencil surfaces.
873 *
874 * :invariant: The surface is a stencil surface
875 * :invariant: :c:member:`isl_surf.samples` == 1
876 */
877 ISL_AUX_USAGE_STC_CCS,
878 };
879
880 /**
881 * Enum for keeping track of the state an auxiliary compressed surface.
882 *
883 * For any given auxiliary surface compression format (HiZ, CCS, or MCS), any
884 * given slice (lod + array layer) can be in one of the seven states described
885 * by this enum. Drawing with or without aux enabled may implicitly cause the
886 * surface to transition between these states. There are also four types of
887 * auxiliary compression operations which cause an explicit transition which
888 * are described by the isl_aux_op enum below.
889 *
890 * Not all operations are valid or useful in all states. The diagram below
891 * contains a complete description of the states and all valid and useful
892 * transitions except clear.
893 *
894 * ::
895 *
896 * Draw w/ Aux
897 * +----------+
898 * | |
899 * | +-------------+ Draw w/ Aux +-------------+
900 * +------>| Compressed |<-------------------| Clear |
901 * | w/ Clear |----->----+ | |
902 * +-------------+ | +-------------+
903 * | /|\ | | |
904 * | | | | |
905 * | | +------<-----+ | Draw w/
906 * | | | | Clear Only
907 * | | Full | | +----------+
908 * Partial | | Resolve | \|/ | |
909 * Resolve | | | +-------------+ |
910 * | | | | Partial |<------+
911 * | | | | Clear |<----------+
912 * | | | +-------------+ |
913 * | | | | |
914 * | | +------>---------+ Full |
915 * | | | Resolve |
916 * Draw w/ aux | | Partial Fast Clear | |
917 * +----------+ | +--------------------------+ | |
918 * | | \|/ | \|/ |
919 * | +-------------+ Full Resolve +-------------+ |
920 * +------>| Compressed |------------------->| Resolved | |
921 * | w/o Clear |<-------------------| | |
922 * +-------------+ Draw w/ Aux +-------------+ |
923 * /|\ | | |
924 * | Draw | | Draw |
925 * | w/ Aux | | w/o Aux |
926 * | Ambiguate | | |
927 * | +--------------------------+ | |
928 * Draw w/o Aux | | | Draw w/o Aux |
929 * +----------+ | | | +----------+ |
930 * | | | \|/ \|/ | | |
931 * | +-------------+ Ambiguate +-------------+ | |
932 * +------>| Pass- |<-------------------| Aux |<------+ |
933 * +------>| through | | Invalid | |
934 * | +-------------+ +-------------+ |
935 * | | | |
936 * +----------+ +-----------------------------------------------------+
937 * Draw w/ Partial Fast Clear
938 * Clear Only
939 *
940 *
941 * While the above general theory applies to all forms of auxiliary
942 * compression on Intel hardware, not all states and operations are available
943 * on all compression types. However, each of the auxiliary states and
944 * operations can be fairly easily mapped onto the above diagram:
945 *
946 * **HiZ:** Hierarchical depth compression is capable of being in any of
947 * the states above. Hardware provides three HiZ operations: "Depth
948 * Clear", "Depth Resolve", and "HiZ Resolve" which map to "Fast Clear",
949 * "Full Resolve", and "Ambiguate" respectively. The hardware provides no
950 * HiZ partial resolve operation so the only way to get into the
951 * "Compressed w/o Clear" state is to render with HiZ when the surface is
952 * in the resolved or pass-through states.
953 *
954 * **MCS:** Multisample compression is technically capable of being in any of
955 * the states above except that most of them aren't useful. Both the render
956 * engine and the sampler support MCS compression and, apart from clear color,
957 * MCS is format-unaware so we leave the surface compressed 100% of the time.
958 * The hardware provides no MCS operations.
959 *
960 * **CCS_D:** Single-sample fast-clears (also called CCS_D in ISL) are one of
961 * the simplest forms of compression since they don't do anything beyond clear
962 * color tracking. They really only support three of the six states: Clear,
963 * Partial Clear, and Pass-through. The only CCS_D operation is "Resolve"
964 * which maps to a full resolve followed by an ambiguate.
965 *
966 * **CCS_E:** Single-sample render target compression (also called CCS_E in
967 * ISL) is capable of being in almost all of the above states. THe only
968 * exception is that it does not have separate resolved and pass- through
969 * states. Instead, the CCS_E full resolve operation does both a resolve and
970 * an ambiguate so it goes directly into the pass-through state. CCS_E also
971 * provides fast clear and partial resolve operations which work as described
972 * above.
973 *
974 * .. note::
975 *
976 * The state machine above isn't quite correct for CCS on TGL. There is a
977 * HW bug (or feature, depending on who you ask) which can cause blocks to
978 * enter the fast-clear state as a side-effect of a regular draw call. This
979 * means that a draw in the resolved or compressed without clear states
980 * takes you to the compressed with clear state, not the compressed without
981 * clear state.
982 */
983 enum isl_aux_state {
984 #ifdef IN_UNIT_TEST
985 ISL_AUX_STATE_ASSERT,
986 #endif
987 /** Clear
988 *
989 * In this state, each block in the auxiliary surface contains a magic
990 * value that indicates that the block is in the clear state. If a block
991 * is in the clear state, its values in the primary surface are ignored
992 * and the color of the samples in the block is taken either the
993 * RENDER_SURFACE_STATE packet for color or 3DSTATE_CLEAR_PARAMS for depth.
994 * Since neither the primary surface nor the auxiliary surface contains the
995 * clear value, the surface can be cleared to a different color by simply
996 * changing the clear color without modifying either surface.
997 */
998 ISL_AUX_STATE_CLEAR,
999
1000 /** Partial Clear
1001 *
1002 * In this state, each block in the auxiliary surface contains either the
1003 * magic clear or pass-through value. See Clear and Pass-through for more
1004 * details.
1005 */
1006 ISL_AUX_STATE_PARTIAL_CLEAR,
1007
1008 /** Compressed with clear color
1009 *
1010 * In this state, neither the auxiliary surface nor the primary surface has
1011 * a complete representation of the data. Instead, both surfaces must be
1012 * used together or else rendering corruption may occur. Depending on the
1013 * auxiliary compression format and the data, any given block in the
1014 * primary surface may contain all, some, or none of the data required to
1015 * reconstruct the actual sample values. Blocks may also be in the clear
1016 * state (see Clear) and have their value taken from outside the surface.
1017 */
1018 ISL_AUX_STATE_COMPRESSED_CLEAR,
1019
1020 /** Compressed without clear color
1021 *
1022 * This state is identical to the state above except that no blocks are in
1023 * the clear state. In this state, all of the data required to reconstruct
1024 * the final sample values is contained in the auxiliary and primary
1025 * surface and the clear value is not considered.
1026 */
1027 ISL_AUX_STATE_COMPRESSED_NO_CLEAR,
1028
1029 /** Resolved
1030 *
1031 * In this state, the primary surface contains 100% of the data. The
1032 * auxiliary surface is also valid so the surface can be validly used with
1033 * or without aux enabled. The auxiliary surface may, however, contain
1034 * non-trivial data and any update to the primary surface with aux disabled
1035 * will cause the two to get out of sync.
1036 */
1037 ISL_AUX_STATE_RESOLVED,
1038
1039 /** Pass-through
1040 *
1041 * In this state, the primary surface contains 100% of the data and every
1042 * block in the auxiliary surface contains a magic value which indicates
1043 * that the auxiliary surface should be ignored and only the primary
1044 * surface should be considered. In this mode, the primary surface can
1045 * safely be written with ISL_AUX_USAGE_NONE or by something that ignores
1046 * compression such as the blit/copy engine or a CPU map and it will stay
1047 * in the pass-through state. Writing to a surface in pass-through mode
1048 * with aux enabled may cause the auxiliary to be updated to contain
1049 * non-trivial data and it will no longer be in the pass-through state.
1050 * Likely, it will end up compressed, with or without clear color.
1051 */
1052 ISL_AUX_STATE_PASS_THROUGH,
1053
1054 /** Aux Invalid
1055 *
1056 * In this state, the primary surface contains 100% of the data and the
1057 * auxiliary surface is completely bogus. Any attempt to use the auxiliary
1058 * surface is liable to result in rendering corruption. The only thing
1059 * that one can do to re-enable aux once this state is reached is to use an
1060 * ambiguate pass to transition into the pass-through state.
1061 */
1062 ISL_AUX_STATE_AUX_INVALID,
1063 };
1064
1065 /** Enum describing explicit aux transition operations
1066 *
1067 * These operations are used to transition from one isl_aux_state to another.
1068 * Even though a draw does transition the state machine, it's not included in
1069 * this enum as it's something of a special case.
1070 */
1071 enum isl_aux_op {
1072 #ifdef IN_UNIT_TEST
1073 ISL_AUX_OP_ASSERT,
1074 #endif
1075
1076 /** Do nothing */
1077 ISL_AUX_OP_NONE,
1078
1079 /** Fast Clear
1080 *
1081 * This operation writes the magic "clear" value to the auxiliary surface.
1082 * This operation will safely transition any slice of a surface from any
1083 * state to the clear state so long as the entire slice is fast cleared at
1084 * once. A fast clear that only covers part of a slice of a surface is
1085 * called a partial fast clear.
1086 */
1087 ISL_AUX_OP_FAST_CLEAR,
1088
1089 /** Full Resolve
1090 *
1091 * This operation combines the auxiliary surface data with the primary
1092 * surface data and writes the result to the primary. For HiZ, the docs
1093 * call this a depth resolve. For CCS, the hardware full resolve operation
1094 * does both a full resolve and an ambiguate so it actually takes you all
1095 * the way to the pass-through state.
1096 */
1097 ISL_AUX_OP_FULL_RESOLVE,
1098
1099 /** Partial Resolve
1100 *
1101 * This operation considers blocks which are in the "clear" state and
1102 * writes the clear value directly into the primary or auxiliary surface.
1103 * Once this operation completes, the surface is still compressed but no
1104 * longer references the clear color. This operation is only available
1105 * for CCS_E.
1106 */
1107 ISL_AUX_OP_PARTIAL_RESOLVE,
1108
1109 /** Ambiguate
1110 *
1111 * This operation throws away the current auxiliary data and replaces it
1112 * with the magic pass-through value. If an ambiguate operation is
1113 * performed when the primary surface does not contain 100% of the data,
1114 * data will be lost. This operation is only implemented in hardware for
1115 * depth where it is called a HiZ resolve.
1116 */
1117 ISL_AUX_OP_AMBIGUATE,
1118 };
1119
1120 /* TODO(chadv): Explain */
1121 enum isl_array_pitch_span {
1122 ISL_ARRAY_PITCH_SPAN_FULL,
1123 ISL_ARRAY_PITCH_SPAN_COMPACT,
1124 };
1125
1126 /**
1127 * @defgroup Surface Usage
1128 * @{
1129 */
1130 typedef uint64_t isl_surf_usage_flags_t;
1131 #define ISL_SURF_USAGE_RENDER_TARGET_BIT (1u << 0)
1132 #define ISL_SURF_USAGE_DEPTH_BIT (1u << 1)
1133 #define ISL_SURF_USAGE_STENCIL_BIT (1u << 2)
1134 #define ISL_SURF_USAGE_TEXTURE_BIT (1u << 3)
1135 #define ISL_SURF_USAGE_CUBE_BIT (1u << 4)
1136 #define ISL_SURF_USAGE_DISABLE_AUX_BIT (1u << 5)
1137 #define ISL_SURF_USAGE_DISPLAY_BIT (1u << 6)
1138 #define ISL_SURF_USAGE_STORAGE_BIT (1u << 7)
1139 #define ISL_SURF_USAGE_HIZ_BIT (1u << 8)
1140 #define ISL_SURF_USAGE_MCS_BIT (1u << 9)
1141 #define ISL_SURF_USAGE_CCS_BIT (1u << 10)
1142 #define ISL_SURF_USAGE_VERTEX_BUFFER_BIT (1u << 11)
1143 #define ISL_SURF_USAGE_INDEX_BUFFER_BIT (1u << 12)
1144 #define ISL_SURF_USAGE_CONSTANT_BUFFER_BIT (1u << 13)
1145 #define ISL_SURF_USAGE_STAGING_BIT (1u << 14)
1146 #define ISL_SURF_USAGE_CPB_BIT (1u << 15)
1147 #define ISL_SURF_USAGE_PROTECTED_BIT (1u << 16)
1148 #define ISL_SURF_USAGE_VIDEO_DECODE_BIT (1u << 17)
1149 #define ISL_SURF_USAGE_STREAM_OUT_BIT (1u << 18)
1150 #define ISL_SURF_USAGE_2D_3D_COMPATIBLE_BIT (1u << 19)
1151 #define ISL_SURF_USAGE_SPARSE_BIT (1u << 20)
1152 #define ISL_SURF_USAGE_NO_AUX_TT_ALIGNMENT_BIT (1u << 21)
1153 /** @} */
1154
1155 /**
1156 * @defgroup Channel Mask
1157 *
1158 * These #define values are chosen to match the values of
1159 * RENDER_SURFACE_STATE::Color Buffer Component Write Disables
1160 *
1161 * @{
1162 */
1163 typedef uint8_t isl_channel_mask_t;
1164 #define ISL_CHANNEL_BLUE_BIT (1 << 0)
1165 #define ISL_CHANNEL_GREEN_BIT (1 << 1)
1166 #define ISL_CHANNEL_RED_BIT (1 << 2)
1167 #define ISL_CHANNEL_ALPHA_BIT (1 << 3)
1168 /** @} */
1169
1170 /**
1171 * @brief A channel select (also known as texture swizzle) value
1172 */
1173 enum ENUM_PACKED isl_channel_select {
1174 ISL_CHANNEL_SELECT_ZERO = 0,
1175 ISL_CHANNEL_SELECT_ONE = 1,
1176 ISL_CHANNEL_SELECT_RED = 4,
1177 ISL_CHANNEL_SELECT_GREEN = 5,
1178 ISL_CHANNEL_SELECT_BLUE = 6,
1179 ISL_CHANNEL_SELECT_ALPHA = 7,
1180 };
1181
1182 /**
1183 * Identical to VkSampleCountFlagBits.
1184 */
1185 enum isl_sample_count {
1186 ISL_SAMPLE_COUNT_1_BIT = 1u,
1187 ISL_SAMPLE_COUNT_2_BIT = 2u,
1188 ISL_SAMPLE_COUNT_4_BIT = 4u,
1189 ISL_SAMPLE_COUNT_8_BIT = 8u,
1190 ISL_SAMPLE_COUNT_16_BIT = 16u,
1191 };
1192 typedef uint32_t isl_sample_count_mask_t;
1193
1194 /**
1195 * @brief Multisample Format
1196 */
1197 enum isl_msaa_layout {
1198 /**
1199 * @brief Surface is single-sampled.
1200 */
1201 ISL_MSAA_LAYOUT_NONE,
1202
1203 /**
1204 * @brief [SNB+] Interleaved Multisample Format
1205 *
1206 * In this format, multiple samples are interleaved into each cacheline.
1207 * In other words, the sample index is swizzled into the low 6 bits of the
1208 * surface's virtual address space.
1209 *
1210 * For example, suppose the surface is legacy Y tiled, is 4x multisampled,
1211 * and its pixel format is 32bpp. Then the first cacheline is arranged
1212 * thus:
1213 *
1214 * (0,0,0) (0,1,0) (0,0,1) (1,0,1)
1215 * (1,0,0) (1,1,0) (0,1,1) (1,1,1)
1216 *
1217 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
1218 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
1219 *
1220 * The hardware docs refer to this format with multiple terms. In
1221 * Sandybridge, this is the only multisample format; so no term is used.
1222 * The Ivybridge docs refer to surfaces in this format as IMS (Interleaved
1223 * Multisample Surface). Later hardware docs additionally refer to this
1224 * format as MSFMT_DEPTH_STENCIL (because the format is deprecated for
1225 * color surfaces).
1226 *
1227 * See the Sandybridge PRM, Volume 4, Part 1, Section 2.7 "Multisampled
1228 * Surface Behavior".
1229 *
1230 * See the Ivybridge PRM, Volume 1, Part 1, Section 6.18.4.1 "Interleaved
1231 * Multisampled Surfaces".
1232 */
1233 ISL_MSAA_LAYOUT_INTERLEAVED,
1234
1235 /**
1236 * @brief [IVB+] Array Multisample Format
1237 *
1238 * In this format, the surface's physical layout resembles that of a
1239 * 2D array surface.
1240 *
1241 * Suppose the multisample surface's logical extent is (w, h) and its
1242 * sample count is N. Then surface's physical extent is the same as
1243 * a singlesample 2D surface whose logical extent is (w, h) and array
1244 * length is N. Array slice `i` contains the pixel values for sample
1245 * index `i`.
1246 *
1247 * The Ivybridge docs refer to surfaces in this format as UMS
1248 * (Uncompressed Multsample Layout) and CMS (Compressed Multisample
1249 * Surface). The Broadwell docs additionally refer to this format as
1250 * MSFMT_MSS (MSS=Multisample Surface Storage).
1251 *
1252 * See the Broadwell PRM, Volume 5 "Memory Views", Section "Uncompressed
1253 * Multisample Surfaces".
1254 *
1255 * See the Broadwell PRM, Volume 5 "Memory Views", Section "Compressed
1256 * Multisample Surfaces".
1257 */
1258 ISL_MSAA_LAYOUT_ARRAY,
1259 };
1260
1261 typedef enum {
1262 ISL_MEMCPY = 0,
1263 ISL_MEMCPY_BGRA8,
1264 ISL_MEMCPY_STREAMING_LOAD,
1265 ISL_MEMCPY_INVALID,
1266 } isl_memcpy_type;
1267
1268 struct isl_surf_fill_state_info;
1269 struct isl_buffer_fill_state_info;
1270 struct isl_depth_stencil_hiz_emit_info;
1271 struct isl_null_fill_state_info;
1272 struct isl_cpb_emit_info;
1273
1274 struct isl_device {
1275 const struct intel_device_info *info;
1276 bool use_separate_stencil;
1277 bool has_bit6_swizzling;
1278
1279 /**
1280 * Describes the layout of a RENDER_SURFACE_STATE structure for the
1281 * current gen.
1282 */
1283 struct {
1284 uint8_t size;
1285 uint8_t align;
1286 uint8_t addr_offset;
1287 uint8_t aux_addr_offset;
1288
1289 /* Rounded up to the nearest dword to simplify GPU memcpy operations. */
1290
1291 /* size of the state buffer used to store the clear color + extra
1292 * additional space used by the hardware */
1293 uint8_t clear_color_state_size;
1294 uint8_t clear_color_state_offset;
1295 /* size of the clear color itself - used to copy it to/from a BO */
1296 uint8_t clear_value_size;
1297 uint8_t clear_value_offset;
1298 } ss;
1299
1300 uint64_t max_buffer_size;
1301
1302 /**
1303 * Describes the layout of the depth/stencil/hiz commands as emitted by
1304 * isl_emit_depth_stencil_hiz.
1305 */
1306 struct {
1307 uint8_t size;
1308 uint8_t depth_offset;
1309 uint8_t stencil_offset;
1310 uint8_t hiz_offset;
1311 } ds;
1312
1313 /**
1314 * Describes the layout of the coarse pixel control commands as emitted by
1315 * isl_emit_cpb_control.
1316 */
1317 struct {
1318 uint8_t size;
1319 uint8_t offset;
1320 } cpb;
1321
1322 struct {
1323 uint32_t internal;
1324 uint32_t external;
1325 uint32_t uncached;
1326 uint32_t l1_hdc_l3_llc;
1327 uint32_t blitter_src;
1328 uint32_t blitter_dst;
1329 /* Protected is an additional bit on top of the existing entry index. */
1330 uint32_t protected_mask;
1331 } mocs;
1332
1333 /* Options to configure by the driver: */
1334
1335 /**
1336 * Write buffer length in the upper dword of the
1337 * RENDER_SURFACE_STATE::AuxilliarySurfaceBaseAddress field.
1338 *
1339 * This field is unused for buffer surfaces so we can reuse it store the
1340 * buffer length. This is useful when you want to load a vec4 with (main
1341 * address, size).
1342 */
1343 bool buffer_length_in_aux_addr;
1344
1345 void (*surf_fill_state_s)(const struct isl_device *dev, void *state,
1346 const struct isl_surf_fill_state_info *restrict info);
1347
1348 void (*buffer_fill_state_s)(const struct isl_device *dev, void *state,
1349 const struct isl_buffer_fill_state_info *restrict info);
1350
1351 void (*emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch,
1352 const struct isl_depth_stencil_hiz_emit_info *restrict info);
1353
1354 void (*null_fill_state_s)(const struct isl_device *dev, void *state,
1355 const struct isl_null_fill_state_info *restrict info);
1356
1357 void (*emit_cpb_control_s)(const struct isl_device *dev, void *batch,
1358 const struct isl_cpb_emit_info *restrict info);
1359 };
1360
1361 struct isl_extent2d {
1362 union { uint32_t w, width; };
1363 union { uint32_t h, height; };
1364 };
1365
1366 struct isl_extent3d {
1367 union { uint32_t w, width; };
1368 union { uint32_t h, height; };
1369 union { uint32_t d, depth; };
1370 };
1371
1372 struct isl_extent4d {
1373 union { uint32_t w, width; };
1374 union { uint32_t h, height; };
1375 union { uint32_t d, depth; };
1376 union { uint32_t a, array_len; };
1377 };
1378
1379 /**
1380 * Describes a single channel of an isl_format
1381 */
1382 struct isl_channel_layout {
1383 /** Channel data encoding */
1384 enum isl_base_type type;
1385 /** Bit at which this channel starts */
1386 uint8_t start_bit;
1387 /** Size in bits */
1388 uint8_t bits;
1389 };
1390
1391 /**
1392 * Describes the layout of an isl_format
1393 *
1394 * Each format has 3D block extent (width, height, depth). The block extent of
1395 * compressed formats is that of the format's compression block. For example,
1396 * the block extent of ``ISL_FORMAT_ETC2_RGB8`` is ``(w=4, h=4, d=1)``. The block
1397 * extent of uncompressed pixel formats, such as ``ISL_FORMAT_R8G8B8A8_UNORM``,
1398 * is ``(w=1, h=1, d=1)``.
1399 */
1400 struct isl_format_layout {
1401 /** Format */
1402 enum isl_format format;
1403
1404 /** Bits per block */
1405 uint16_t bpb;
1406 /** Block width, in pixels */
1407 uint8_t bw;
1408 /** Block height, in pixels */
1409 uint8_t bh;
1410 /** Block depth, in pixels */
1411 uint8_t bd;
1412
1413 /***/
1414 union {
1415 /***/
1416 struct {
1417 /** Red channel */
1418 struct isl_channel_layout r;
1419 /** Green channel */
1420 struct isl_channel_layout g;
1421 /** Blue channel */
1422 struct isl_channel_layout b;
1423 /** Alpha channel */
1424 struct isl_channel_layout a;
1425 /** Luminance channel */
1426 struct isl_channel_layout l;
1427 /** Intensity channel */
1428 struct isl_channel_layout i;
1429 /** Palette channel */
1430 struct isl_channel_layout p;
1431 } channels;
1432 struct isl_channel_layout channels_array[7];
1433 };
1434
1435 /** Set if all channels have the same isl_base_type. Otherwise, ISL_VOID. */
1436 enum isl_base_type uniform_channel_type;
1437
1438 enum isl_colorspace colorspace;
1439 enum isl_txc txc;
1440 };
1441
1442 /***/
1443 struct isl_tile_info {
1444 /** Tiling represented by this isl_tile_info */
1445 enum isl_tiling tiling;
1446
1447 /**
1448 * The size (in bits per block) of a single surface element
1449 *
1450 * For surfaces with power-of-two formats, this is the same as
1451 * isl_format_layout::bpb. For non-power-of-two formats it may be smaller.
1452 * The logical_extent_el field is in terms of elements of this size.
1453 *
1454 * For example, consider ISL_FORMAT_R32G32B32_FLOAT for which
1455 * isl_format_layout::bpb is 96 (a non-power-of-two). In this case, none
1456 * of the tiling formats can actually hold an integer number of 96-bit
1457 * surface elements so isl_tiling_get_info returns an isl_tile_info for a
1458 * 32-bit element size. It is the responsibility of the caller to
1459 * recognize that 32 != 96 ad adjust accordingly. For instance, to compute
1460 * the width of a surface in tiles, you would do::
1461 *
1462 * width_tl = DIV_ROUND_UP(width_el * (format_bpb / tile_info.format_bpb),
1463 * tile_info.logical_extent_el.width);
1464 */
1465 uint32_t format_bpb;
1466
1467 /**
1468 * The logical size of the tile in units of format_bpb size elements
1469 *
1470 * This field determines how a given surface is cut up into tiles. It is
1471 * used to compute the size of a surface in tiles and can be used to
1472 * determine the location of the tile containing any given surface element.
1473 * The exact value of this field depends heavily on the bits-per-block of
1474 * the format being used.
1475 */
1476 struct isl_extent4d logical_extent_el;
1477
1478 /**
1479 * The maximum number of miplevels that will fit in the miptail.
1480 *
1481 * This does not guarantee that the given number of miplevels will fit in
1482 * the miptail as that is also dependent on the size of the miplevels.
1483 */
1484 uint32_t max_miptail_levels;
1485
1486 /**
1487 * The physical size of the tile in bytes and rows of bytes
1488 *
1489 * This field determines how the tiles of a surface are physically laid
1490 * out in memory. The logical and physical tile extent are frequently the
1491 * same but this is not always the case. For instance, a W-tile (which is
1492 * always used with ISL_FORMAT_R8) has a logical size of 64el x 64el but
1493 * its physical size is 128B x 32rows, the same as a Y-tile.
1494 *
1495 * See :c:member:`isl_surf.row_pitch_B`
1496 */
1497 struct isl_extent2d phys_extent_B;
1498 };
1499
1500 /**
1501 * Metadata about a DRM format modifier.
1502 */
1503 struct isl_drm_modifier_info {
1504 uint64_t modifier;
1505
1506 /** Text name of the modifier */
1507 const char *name;
1508
1509 /** ISL tiling implied by this modifier */
1510 enum isl_tiling tiling;
1511
1512 /** Compression types supported by this modifier */
1513 bool supports_render_compression;
1514 bool supports_media_compression;
1515
1516 /** Whether or not this modifier supports clear color */
1517 bool supports_clear_color;
1518 };
1519
1520 /**
1521 * @brief Input to surface initialization
1522 *
1523 * :invariant: width >= 1
1524 * :invariant: height >= 1
1525 * :invariant: depth >= 1
1526 * :invariant: levels >= 1
1527 * :invariant: samples >= 1
1528 * :invariant: array_len >= 1
1529 *
1530 * :invariant: if 1D then height == 1 and depth == 1 and samples == 1
1531 * :invariant: if 2D then depth == 1
1532 * :invariant: if 3D then array_len == 1 and samples == 1
1533 */
1534 struct isl_surf_init_info {
1535 enum isl_surf_dim dim;
1536 enum isl_format format;
1537
1538 uint32_t width;
1539 uint32_t height;
1540 uint32_t depth;
1541 uint32_t levels;
1542 uint32_t array_len;
1543 uint32_t samples;
1544
1545 /** Lower bound for :c:member:`isl_surf.alignment`, in bytes. */
1546 uint32_t min_alignment_B;
1547
1548 /** Lower bound for where to start the miptail */
1549 uint32_t min_miptail_start_level;
1550
1551 /**
1552 * Exact value for :c:member:`isl_surf.row_pitch`. Ignored if zero.
1553 * isl_surf_init() will fail if this is misaligned or out of bounds.
1554 */
1555 uint32_t row_pitch_B;
1556
1557 isl_surf_usage_flags_t usage;
1558
1559 /** Flags that alter how ISL selects isl_surf::tiling. */
1560 isl_tiling_flags_t tiling_flags;
1561 };
1562
1563 /***/
1564 struct isl_surf {
1565 /** Dimensionality of the surface */
1566 enum isl_surf_dim dim;
1567
1568 /**
1569 * Spatial layout of the surface in memory
1570 *
1571 * This is dependent on :c:member:`isl_surf.dim` and hardware generation.
1572 */
1573 enum isl_dim_layout dim_layout;
1574
1575 /** Spatial layout of the samples if isl_surf::samples > 1 */
1576 enum isl_msaa_layout msaa_layout;
1577
1578 /** Memory tiling used by the surface */
1579 enum isl_tiling tiling;
1580
1581 /**
1582 * Base image format of the surface
1583 *
1584 * This need not be the same as the format specified in isl_view::format
1585 * when a surface state is constructed. It must, however, have the same
1586 * number of bits per pixel or else memory calculations will go wrong.
1587 */
1588 enum isl_format format;
1589
1590 /**
1591 * Alignment of the upper-left sample of each subimage, in units of surface
1592 * elements.
1593 */
1594 struct isl_extent3d image_alignment_el;
1595
1596 /**
1597 * Logical extent of the surface's base level, in units of pixels. This is
1598 * identical to the extent defined in isl_surf_init_info.
1599 */
1600 struct isl_extent4d logical_level0_px;
1601
1602 /**
1603 * Physical extent of the surface's base level, in units of physical
1604 * surface samples.
1605 *
1606 * Consider isl_dim_layout as an operator that transforms a logical surface
1607 * layout to a physical surface layout. Then
1608 *
1609 * logical_layout := (isl_surf::dim, isl_surf::logical_level0_px)
1610 * isl_surf::phys_level0_sa := isl_surf::dim_layout * logical_layout
1611 */
1612 struct isl_extent4d phys_level0_sa;
1613
1614 /** Number of miplevels in the surface */
1615 uint32_t levels;
1616
1617 /**
1618 * Number of samples in the surface
1619 *
1620 * :invariant: samples >= 1
1621 */
1622 uint32_t samples;
1623
1624 /** Total size of the surface, in bytes. */
1625 uint64_t size_B;
1626
1627 /** Required alignment for the surface's base address. */
1628 uint32_t alignment_B;
1629
1630 /**
1631 * The interpretation of this field depends on the value of
1632 * isl_tile_info::physical_extent_B. In particular, the width of the
1633 * surface in tiles is row_pitch_B / isl_tile_info::physical_extent_B.width
1634 * and the distance in bytes between vertically adjacent tiles in the image
1635 * is given by row_pitch_B * isl_tile_info::physical_extent_B.height.
1636 *
1637 * For linear images where isl_tile_info::physical_extent_B.height == 1,
1638 * this cleanly reduces to being the distance, in bytes, between vertically
1639 * adjacent surface elements.
1640 *
1641 * @see isl_tile_info::phys_extent_B;
1642 */
1643 uint32_t row_pitch_B;
1644
1645 /**
1646 * Pitch between physical array slices, in rows of surface elements.
1647 */
1648 uint32_t array_pitch_el_rows;
1649
1650 enum isl_array_pitch_span array_pitch_span;
1651
1652 /**
1653 * Level at which the miptail starts.
1654 *
1655 * This value is inclusive in the sense that the miptail contains this
1656 * level.
1657 */
1658 uint32_t miptail_start_level;
1659
1660 /** Copy of isl_surf_init_info::usage. */
1661 isl_surf_usage_flags_t usage;
1662 };
1663
1664 struct isl_swizzle {
1665 enum isl_channel_select r:4;
1666 enum isl_channel_select g:4;
1667 enum isl_channel_select b:4;
1668 enum isl_channel_select a:4;
1669 };
1670
1671 #define ISL_SWIZZLE(R, G, B, A) ((struct isl_swizzle) { \
1672 .r = ISL_CHANNEL_SELECT_##R, \
1673 .g = ISL_CHANNEL_SELECT_##G, \
1674 .b = ISL_CHANNEL_SELECT_##B, \
1675 .a = ISL_CHANNEL_SELECT_##A, \
1676 })
1677
1678 #define ISL_SWIZZLE_IDENTITY ISL_SWIZZLE(RED, GREEN, BLUE, ALPHA)
1679
1680 struct isl_view {
1681 /**
1682 * Indicates the usage of the particular view
1683 *
1684 * Normally, this is one bit. However, for a cube map texture, it
1685 * should be ISL_SURF_USAGE_TEXTURE_BIT | ISL_SURF_USAGE_CUBE_BIT.
1686 */
1687 isl_surf_usage_flags_t usage;
1688
1689 /**
1690 * The format to use in the view
1691 *
1692 * This may differ from the format of the actual isl_surf but must have
1693 * the same block size.
1694 */
1695 enum isl_format format;
1696
1697 uint32_t base_level;
1698 uint32_t levels;
1699
1700 /**
1701 * Base array layer
1702 *
1703 * For cube maps, both base_array_layer and array_len should be
1704 * specified in terms of 2-D layers and must be a multiple of 6.
1705 *
1706 * 3-D textures are effectively treated as 2-D arrays when used as a
1707 * storage image or render target. If `usage` contains
1708 * ISL_SURF_USAGE_RENDER_TARGET_BIT or ISL_SURF_USAGE_STORAGE_BIT then
1709 * base_array_layer and array_len are applied. If the surface is only used
1710 * for texturing, they are ignored.
1711 */
1712 uint32_t base_array_layer;
1713
1714 /**
1715 * Array Length
1716 *
1717 * Indicates the number of array elements starting at Base Array Layer.
1718 */
1719 uint32_t array_len;
1720
1721 /**
1722 * Minimum LOD
1723 *
1724 * Similar to sampler minimum LOD, the computed LOD is clamped to be at
1725 * least min_lod_clamp.
1726 */
1727 float min_lod_clamp;
1728
1729 struct isl_swizzle swizzle;
1730 };
1731
1732 union isl_color_value {
1733 float f32[4];
1734 uint32_t u32[4];
1735 int32_t i32[4];
1736 };
1737
1738 struct isl_surf_fill_state_info {
1739 const struct isl_surf *surf;
1740 const struct isl_view *view;
1741
1742 /**
1743 * The address of the surface in GPU memory.
1744 */
1745 uint64_t address;
1746
1747 /**
1748 * The Memory Object Control state for the filled surface state.
1749 *
1750 * The exact format of this value depends on hardware generation.
1751 */
1752 uint32_t mocs;
1753
1754 /**
1755 * The auxiliary surface or NULL if no auxiliary surface is to be used.
1756 */
1757 const struct isl_surf *aux_surf;
1758 enum isl_aux_usage aux_usage;
1759 uint64_t aux_address;
1760
1761 /**
1762 * The format to use for decoding media compression.
1763 *
1764 * Used together with the surface format.
1765 */
1766 enum isl_format mc_format;
1767
1768 /**
1769 * The clear color for this surface
1770 *
1771 * Valid values depend on hardware generation.
1772 */
1773 union isl_color_value clear_color;
1774
1775 /**
1776 * Send only the clear value address
1777 *
1778 * If set, we only pass the clear address to the GPU and it will fetch it
1779 * from wherever it is.
1780 */
1781 bool use_clear_address;
1782 uint64_t clear_address;
1783
1784 /**
1785 * Surface write disables for gfx4-5
1786 */
1787 isl_channel_mask_t write_disables;
1788
1789 /**
1790 * blend enable for gfx4-5
1791 */
1792 bool blend_enable;
1793
1794 /* Intra-tile offset */
1795 uint16_t x_offset_sa, y_offset_sa;
1796
1797 /**
1798 * Robust image access enabled
1799 *
1800 * This is used to turn off a performance workaround.
1801 */
1802 bool robust_image_access;
1803 };
1804
1805 struct isl_buffer_fill_state_info {
1806 /**
1807 * The address of the surface in GPU memory.
1808 */
1809 uint64_t address;
1810
1811 /**
1812 * The size of the buffer
1813 */
1814 uint64_t size_B;
1815
1816 /**
1817 * The Memory Object Control state for the filled surface state.
1818 *
1819 * The exact format of this value depends on hardware generation.
1820 */
1821 uint32_t mocs;
1822
1823 /**
1824 * The format to use in the surface state
1825 *
1826 * This may differ from the format of the actual isl_surf but have the
1827 * same block size.
1828 */
1829 enum isl_format format;
1830
1831 /**
1832 * The swizzle to use in the surface state
1833 */
1834 struct isl_swizzle swizzle;
1835
1836 uint32_t stride_B;
1837
1838 bool is_scratch;
1839 };
1840
1841 struct isl_depth_stencil_hiz_emit_info {
1842 /**
1843 * The depth surface
1844 */
1845 const struct isl_surf *depth_surf;
1846
1847 /**
1848 * The stencil surface
1849 *
1850 * If separate stencil is not available, this must point to the same
1851 * isl_surf as depth_surf.
1852 */
1853 const struct isl_surf *stencil_surf;
1854
1855 /**
1856 * The view into the depth and stencil surfaces.
1857 *
1858 * This view applies to both surfaces simultaneously.
1859 */
1860 const struct isl_view *view;
1861
1862 /**
1863 * The address of the depth surface in GPU memory
1864 */
1865 uint64_t depth_address;
1866
1867 /**
1868 * The address of the stencil surface in GPU memory
1869 *
1870 * If separate stencil is not available, this must have the same value as
1871 * depth_address.
1872 */
1873 uint64_t stencil_address;
1874
1875 /**
1876 * The Memory Object Control state for depth and stencil buffers
1877 *
1878 * Both depth and stencil will get the same MOCS value. The exact format
1879 * of this value depends on hardware generation.
1880 */
1881 uint32_t mocs;
1882
1883 /**
1884 * The HiZ surface or NULL if HiZ is disabled.
1885 */
1886 const struct isl_surf *hiz_surf;
1887 enum isl_aux_usage hiz_usage;
1888 uint64_t hiz_address;
1889
1890 /**
1891 * The depth clear value
1892 */
1893 float depth_clear_value;
1894
1895 /**
1896 * Track stencil aux usage for Gen >= 12
1897 */
1898 enum isl_aux_usage stencil_aux_usage;
1899 };
1900
1901 struct isl_null_fill_state_info {
1902 struct isl_extent3d size;
1903 uint32_t levels;
1904 uint32_t minimum_array_element;
1905 };
1906
1907 struct isl_cpb_emit_info {
1908 /**
1909 * The coarse pixel shading control surface.
1910 */
1911 const struct isl_surf *surf;
1912
1913 /**
1914 * The view into the control surface.
1915 */
1916 const struct isl_view *view;
1917
1918 /**
1919 * The address of the control surface in GPU memory.
1920 */
1921 uint64_t address;
1922
1923 /**
1924 * The Memory Object Control state for the surface.
1925 */
1926 uint32_t mocs;
1927 };
1928
1929 /*
1930 * Image metadata structure as laid out in the shader parameter
1931 * buffer. Entries have to be 16B-aligned for the vec4 back-end to be
1932 * able to use them. That's okay because the padding and any unused
1933 * entries [most of them except when we're doing untyped surface
1934 * access] will be removed by the uniform packing pass.
1935 */
1936 #define ISL_IMAGE_PARAM_OFFSET_OFFSET 0
1937 #define ISL_IMAGE_PARAM_SIZE_OFFSET 4
1938 #define ISL_IMAGE_PARAM_STRIDE_OFFSET 8
1939 #define ISL_IMAGE_PARAM_TILING_OFFSET 12
1940 #define ISL_IMAGE_PARAM_SWIZZLING_OFFSET 16
1941 #define ISL_IMAGE_PARAM_SIZE 20
1942
1943 struct isl_image_param {
1944 /** Offset applied to the X and Y surface coordinates. */
1945 uint32_t offset[2];
1946
1947 /** Surface X, Y and Z dimensions. */
1948 uint32_t size[3];
1949
1950 /** X-stride in bytes, Y-stride in pixels, horizontal slice stride in
1951 * pixels, vertical slice stride in pixels.
1952 */
1953 uint32_t stride[4];
1954
1955 /** Log2 of the tiling modulus in the X, Y and Z dimension. */
1956 uint32_t tiling[3];
1957
1958 /**
1959 * Right shift to apply for bit 6 address swizzling. Two different
1960 * swizzles can be specified and will be applied one after the other. The
1961 * resulting address will be:
1962 *
1963 * addr' = addr ^ ((1 << 6) & ((addr >> swizzling[0]) ^
1964 * (addr >> swizzling[1])))
1965 *
1966 * Use \c 0xff if any of the swizzles is not required.
1967 */
1968 uint32_t swizzling[2];
1969 };
1970
1971 extern const struct isl_format_layout isl_format_layouts[];
1972 extern const char isl_format_names[];
1973 extern const uint16_t isl_format_name_offsets[];
1974
1975 void
1976 isl_device_init(struct isl_device *dev,
1977 const struct intel_device_info *info);
1978
1979 isl_sample_count_mask_t ATTRIBUTE_CONST
1980 isl_device_get_sample_counts(const struct isl_device *dev);
1981
1982 /**
1983 * :returns: The isl_format_layout for the given isl_format
1984 */
1985 static inline const struct isl_format_layout * ATTRIBUTE_CONST
isl_format_get_layout(enum isl_format fmt)1986 isl_format_get_layout(enum isl_format fmt)
1987 {
1988 assert(fmt != ISL_FORMAT_UNSUPPORTED);
1989 assert(fmt < ISL_NUM_FORMATS);
1990 return &isl_format_layouts[fmt];
1991 }
1992
1993 bool isl_format_is_valid(enum isl_format);
1994
1995 static inline const char * ATTRIBUTE_CONST
isl_format_get_name(enum isl_format fmt)1996 isl_format_get_name(enum isl_format fmt)
1997 {
1998 assert(fmt != ISL_FORMAT_UNSUPPORTED);
1999 assert(fmt < ISL_NUM_FORMATS);
2000 return isl_format_names + isl_format_name_offsets[fmt];
2001 }
2002
2003 static inline const char * ATTRIBUTE_CONST
isl_format_get_short_name(enum isl_format fmt)2004 isl_format_get_short_name(enum isl_format fmt)
2005 {
2006 return isl_format_get_name(fmt) + 11 /* ISL_FORMAT_ */;
2007 }
2008
2009 /***/
2010 enum isl_format isl_format_for_pipe_format(enum pipe_format pf);
2011
2012 /***/
2013 bool isl_format_supports_rendering(const struct intel_device_info *devinfo,
2014 enum isl_format format);
2015 /***/
2016 bool isl_format_supports_alpha_blending(const struct intel_device_info *devinfo,
2017 enum isl_format format);
2018 /***/
2019 bool isl_format_supports_sampling(const struct intel_device_info *devinfo,
2020 enum isl_format format);
2021 /***/
2022 bool isl_format_supports_filtering(const struct intel_device_info *devinfo,
2023 enum isl_format format);
2024 /***/
2025 bool isl_format_supports_vertex_fetch(const struct intel_device_info *devinfo,
2026 enum isl_format format);
2027 /***/
2028 bool isl_format_supports_typed_writes(const struct intel_device_info *devinfo,
2029 enum isl_format format);
2030 bool isl_format_supports_typed_reads(const struct intel_device_info *devinfo,
2031 enum isl_format format);
2032 bool isl_format_supports_ccs_d(const struct intel_device_info *devinfo,
2033 enum isl_format format);
2034 bool isl_format_supports_ccs_e(const struct intel_device_info *devinfo,
2035 enum isl_format format);
2036 /***/
2037 bool isl_format_supports_multisampling(const struct intel_device_info *devinfo,
2038 enum isl_format format);
2039 bool isl_format_supports_typed_atomics(const struct intel_device_info *devinfo,
2040 enum isl_format fmt);
2041
2042 bool isl_formats_are_ccs_e_compatible(const struct intel_device_info *devinfo,
2043 enum isl_format format1,
2044 enum isl_format format2);
2045 uint8_t isl_format_get_aux_map_encoding(enum isl_format format);
2046 uint8_t isl_get_render_compression_format(enum isl_format format);
2047
2048 bool isl_formats_have_same_bits_per_channel(enum isl_format format1,
2049 enum isl_format format2);
2050
2051 bool isl_format_has_unorm_channel(enum isl_format fmt) ATTRIBUTE_CONST;
2052 bool isl_format_has_snorm_channel(enum isl_format fmt) ATTRIBUTE_CONST;
2053 bool isl_format_has_ufloat_channel(enum isl_format fmt) ATTRIBUTE_CONST;
2054 bool isl_format_has_sfloat_channel(enum isl_format fmt) ATTRIBUTE_CONST;
2055 bool isl_format_has_uint_channel(enum isl_format fmt) ATTRIBUTE_CONST;
2056 bool isl_format_has_sint_channel(enum isl_format fmt) ATTRIBUTE_CONST;
2057
2058 static inline bool
isl_format_has_normalized_channel(enum isl_format fmt)2059 isl_format_has_normalized_channel(enum isl_format fmt)
2060 {
2061 return isl_format_has_unorm_channel(fmt) ||
2062 isl_format_has_snorm_channel(fmt);
2063 }
2064
2065 static inline bool
isl_format_has_float_channel(enum isl_format fmt)2066 isl_format_has_float_channel(enum isl_format fmt)
2067 {
2068 return isl_format_has_ufloat_channel(fmt) ||
2069 isl_format_has_sfloat_channel(fmt);
2070 }
2071
2072 static inline bool
isl_format_has_int_channel(enum isl_format fmt)2073 isl_format_has_int_channel(enum isl_format fmt)
2074 {
2075 return isl_format_has_uint_channel(fmt) ||
2076 isl_format_has_sint_channel(fmt);
2077 }
2078
2079 bool isl_format_has_color_component(enum isl_format fmt,
2080 int component) ATTRIBUTE_CONST;
2081
2082 unsigned isl_format_get_num_channels(enum isl_format fmt);
2083
2084 uint32_t isl_format_get_depth_format(enum isl_format fmt, bool has_stencil);
2085
2086 static inline bool
isl_format_is_compressed(enum isl_format fmt)2087 isl_format_is_compressed(enum isl_format fmt)
2088 {
2089 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
2090
2091 return fmtl->txc != ISL_TXC_NONE;
2092 }
2093
2094 static inline bool
isl_format_has_bc_compression(enum isl_format fmt)2095 isl_format_has_bc_compression(enum isl_format fmt)
2096 {
2097 switch (isl_format_get_layout(fmt)->txc) {
2098 case ISL_TXC_DXT1:
2099 case ISL_TXC_DXT3:
2100 case ISL_TXC_DXT5:
2101 return true;
2102 case ISL_TXC_NONE:
2103 case ISL_TXC_FXT1:
2104 case ISL_TXC_RGTC1:
2105 case ISL_TXC_RGTC2:
2106 case ISL_TXC_BPTC:
2107 case ISL_TXC_ETC1:
2108 case ISL_TXC_ETC2:
2109 case ISL_TXC_ASTC:
2110 return false;
2111
2112 case ISL_TXC_HIZ:
2113 case ISL_TXC_MCS:
2114 case ISL_TXC_CCS:
2115 unreachable("Should not be called on an aux surface");
2116 }
2117
2118 unreachable("bad texture compression mode");
2119 return false;
2120 }
2121
2122 static inline bool
isl_format_is_mcs(enum isl_format fmt)2123 isl_format_is_mcs(enum isl_format fmt)
2124 {
2125 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
2126
2127 return fmtl->txc == ISL_TXC_MCS;
2128 }
2129
2130 static inline bool
isl_format_is_hiz(enum isl_format fmt)2131 isl_format_is_hiz(enum isl_format fmt)
2132 {
2133 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
2134
2135 return fmtl->txc == ISL_TXC_HIZ;
2136 }
2137
2138 static inline bool
isl_format_is_planar(enum isl_format fmt)2139 isl_format_is_planar(enum isl_format fmt)
2140 {
2141 return fmt == ISL_FORMAT_PLANAR_420_8 ||
2142 fmt == ISL_FORMAT_PLANAR_420_10 ||
2143 fmt == ISL_FORMAT_PLANAR_420_12 ||
2144 fmt == ISL_FORMAT_PLANAR_420_16;
2145 }
2146
2147 static inline bool
isl_format_is_yuv(enum isl_format fmt)2148 isl_format_is_yuv(enum isl_format fmt)
2149 {
2150 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
2151
2152 return fmtl->colorspace == ISL_COLORSPACE_YUV;
2153 }
2154
2155 static inline bool
isl_format_block_is_1x1x1(enum isl_format fmt)2156 isl_format_block_is_1x1x1(enum isl_format fmt)
2157 {
2158 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
2159
2160 return fmtl->bw == 1 && fmtl->bh == 1 && fmtl->bd == 1;
2161 }
2162
2163 static inline bool
isl_format_is_srgb(enum isl_format fmt)2164 isl_format_is_srgb(enum isl_format fmt)
2165 {
2166 return isl_format_get_layout(fmt)->colorspace == ISL_COLORSPACE_SRGB;
2167 }
2168
2169 enum isl_format isl_format_srgb_to_linear(enum isl_format fmt);
2170
2171 static inline bool
isl_format_is_rgb(enum isl_format fmt)2172 isl_format_is_rgb(enum isl_format fmt)
2173 {
2174 if (isl_format_is_yuv(fmt))
2175 return false;
2176
2177 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
2178
2179 return fmtl->channels.r.bits > 0 &&
2180 fmtl->channels.g.bits > 0 &&
2181 fmtl->channels.b.bits > 0 &&
2182 fmtl->channels.a.bits == 0;
2183 }
2184
2185 static inline bool
isl_format_is_rgbx(enum isl_format fmt)2186 isl_format_is_rgbx(enum isl_format fmt)
2187 {
2188 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
2189
2190 return fmtl->channels.r.bits > 0 &&
2191 fmtl->channels.g.bits > 0 &&
2192 fmtl->channels.b.bits > 0 &&
2193 fmtl->channels.a.bits > 0 &&
2194 fmtl->channels.a.type == ISL_VOID;
2195 }
2196
2197 enum isl_format isl_format_rgb_to_rgba(enum isl_format rgb) ATTRIBUTE_CONST;
2198 enum isl_format isl_format_rgb_to_rgbx(enum isl_format rgb) ATTRIBUTE_CONST;
2199 enum isl_format isl_format_rgbx_to_rgba(enum isl_format rgb) ATTRIBUTE_CONST;
2200
2201 bool isl_format_support_sampler_route_to_lsc(enum isl_format fmt);
2202
2203 union isl_color_value
2204 isl_color_value_swizzle(union isl_color_value src,
2205 struct isl_swizzle swizzle,
2206 bool is_float);
2207
2208 union isl_color_value
2209 isl_color_value_swizzle_inv(union isl_color_value src,
2210 struct isl_swizzle swizzle);
2211
2212 void isl_color_value_pack(const union isl_color_value *value,
2213 enum isl_format format,
2214 uint32_t *data_out);
2215 void isl_color_value_unpack(union isl_color_value *value,
2216 enum isl_format format,
2217 const uint32_t *data_in);
2218
2219 bool isl_is_storage_image_format(const struct intel_device_info *devinfo,
2220 enum isl_format fmt);
2221
2222 enum isl_format
2223 isl_lower_storage_image_format(const struct intel_device_info *devinfo,
2224 enum isl_format fmt);
2225
2226 /* Returns true if this hardware supports typed load/store on a format with
2227 * the same size as the given format.
2228 */
2229 bool
2230 isl_has_matching_typed_storage_image_format(const struct intel_device_info *devinfo,
2231 enum isl_format fmt);
2232
2233 void
2234 isl_tiling_get_info(enum isl_tiling tiling,
2235 enum isl_surf_dim dim,
2236 enum isl_msaa_layout msaa_layout,
2237 uint32_t format_bpb,
2238 uint32_t samples,
2239 struct isl_tile_info *tile_info);
2240
2241 static inline enum isl_tiling
isl_tiling_flag_to_enum(isl_tiling_flags_t flag)2242 isl_tiling_flag_to_enum(isl_tiling_flags_t flag)
2243 {
2244 assert(__builtin_popcount(flag) == 1);
2245 return (enum isl_tiling) (__builtin_ffs(flag) - 1);
2246 }
2247
2248 static inline bool
isl_tiling_is_any_y(enum isl_tiling tiling)2249 isl_tiling_is_any_y(enum isl_tiling tiling)
2250 {
2251 return (1u << tiling) & ISL_TILING_ANY_Y_MASK;
2252 }
2253
2254 static inline bool
isl_tiling_is_std_y(enum isl_tiling tiling)2255 isl_tiling_is_std_y(enum isl_tiling tiling)
2256 {
2257 return (1u << tiling) & ISL_TILING_STD_Y_MASK;
2258 }
2259
2260 static inline bool
isl_tiling_is_64(enum isl_tiling tiling)2261 isl_tiling_is_64(enum isl_tiling tiling)
2262 {
2263 return (1u << tiling) & ISL_TILING_STD_64_MASK;
2264 }
2265
2266 uint32_t
2267 isl_tiling_to_i915_tiling(enum isl_tiling tiling);
2268
2269 enum isl_tiling
2270 isl_tiling_from_i915_tiling(uint32_t tiling);
2271
2272 /**
2273 * Return an isl_aux_op needed to enable an access to occur in an
2274 * isl_aux_state suitable for the isl_aux_usage.
2275 *
2276 * .. note::
2277 * If the access will invalidate the main surface, this function should not be
2278 * called and the isl_aux_op of NONE should be used instead. Otherwise, an
2279 * extra (but still lossless) ambiguate may occur.
2280 *
2281 * :invariant: initial_state is possible with an isl_aux_usage compatible with
2282 * the given usage. Two usages are compatible if it's possible to
2283 * switch between them (e.g. CCS_E <-> CCS_D).
2284 * :invariant: fast_clear is false if the aux doesn't support fast clears.
2285 */
2286 enum isl_aux_op
2287 isl_aux_prepare_access(enum isl_aux_state initial_state,
2288 enum isl_aux_usage usage,
2289 bool fast_clear_supported);
2290
2291 /**
2292 * Return the isl_aux_state entered after performing an isl_aux_op.
2293 *
2294 * :invariant: initial_state is possible with the given usage.
2295 * :invariant: op is possible with the given usage.
2296 * :invariant: op must not cause HW to read from an invalid aux.
2297 */
2298 enum isl_aux_state
2299 isl_aux_state_transition_aux_op(enum isl_aux_state initial_state,
2300 enum isl_aux_usage usage,
2301 enum isl_aux_op op);
2302
2303 /**
2304 * Return the isl_aux_state entered after performing a write.
2305 *
2306 * .. note::
2307 *
2308 * full_surface should be true if the write covers the entire slice. Setting
2309 * it to false in this case will still result in a correct (but imprecise)
2310 * aux state.
2311 *
2312 * :invariant: if usage is not ISL_AUX_USAGE_NONE, then initial_state is
2313 * possible with the given usage.
2314 * :invariant: usage can be ISL_AUX_USAGE_NONE iff:
2315 * * the main surface is valid, or
2316 * * the main surface is being invalidated/replaced.
2317 */
2318 enum isl_aux_state
2319 isl_aux_state_transition_write(enum isl_aux_state initial_state,
2320 enum isl_aux_usage usage,
2321 bool full_surface);
2322
2323 /***/
2324 bool
2325 isl_aux_usage_has_fast_clears(enum isl_aux_usage usage);
2326
2327 /***/
2328 bool
2329 isl_aux_usage_has_compression(enum isl_aux_usage usage);
2330
2331 /***/
2332 static inline bool
isl_aux_usage_has_hiz(enum isl_aux_usage usage)2333 isl_aux_usage_has_hiz(enum isl_aux_usage usage)
2334 {
2335 return usage == ISL_AUX_USAGE_HIZ ||
2336 usage == ISL_AUX_USAGE_HIZ_CCS_WT ||
2337 usage == ISL_AUX_USAGE_HIZ_CCS;
2338 }
2339
2340 /***/
2341 static inline bool
isl_aux_usage_has_mcs(enum isl_aux_usage usage)2342 isl_aux_usage_has_mcs(enum isl_aux_usage usage)
2343 {
2344 return usage == ISL_AUX_USAGE_MCS ||
2345 usage == ISL_AUX_USAGE_MCS_CCS;
2346 }
2347
2348 /***/
2349 static inline bool
isl_aux_usage_has_ccs(enum isl_aux_usage usage)2350 isl_aux_usage_has_ccs(enum isl_aux_usage usage)
2351 {
2352 return usage == ISL_AUX_USAGE_CCS_D ||
2353 usage == ISL_AUX_USAGE_CCS_E ||
2354 usage == ISL_AUX_USAGE_FCV_CCS_E ||
2355 usage == ISL_AUX_USAGE_MC ||
2356 usage == ISL_AUX_USAGE_HIZ_CCS_WT ||
2357 usage == ISL_AUX_USAGE_HIZ_CCS ||
2358 usage == ISL_AUX_USAGE_MCS_CCS ||
2359 usage == ISL_AUX_USAGE_STC_CCS;
2360 }
2361
2362 static inline bool
isl_aux_usage_has_ccs_e(enum isl_aux_usage usage)2363 isl_aux_usage_has_ccs_e(enum isl_aux_usage usage)
2364 {
2365 return usage == ISL_AUX_USAGE_CCS_E ||
2366 usage == ISL_AUX_USAGE_FCV_CCS_E;
2367 }
2368
2369 /***/
2370 static inline bool
isl_aux_state_has_valid_primary(enum isl_aux_state state)2371 isl_aux_state_has_valid_primary(enum isl_aux_state state)
2372 {
2373 return state == ISL_AUX_STATE_RESOLVED ||
2374 state == ISL_AUX_STATE_PASS_THROUGH ||
2375 state == ISL_AUX_STATE_AUX_INVALID;
2376 }
2377
2378 /***/
2379 static inline bool
isl_aux_state_has_valid_aux(enum isl_aux_state state)2380 isl_aux_state_has_valid_aux(enum isl_aux_state state)
2381 {
2382 return state != ISL_AUX_STATE_AUX_INVALID;
2383 }
2384
2385 extern const struct isl_drm_modifier_info isl_drm_modifier_info_list[];
2386
2387 #define isl_drm_modifier_info_for_each(__info) \
2388 for (const struct isl_drm_modifier_info *__info = isl_drm_modifier_info_list; \
2389 __info->modifier != DRM_FORMAT_MOD_INVALID; \
2390 ++__info)
2391
2392 const struct isl_drm_modifier_info * ATTRIBUTE_CONST
2393 isl_drm_modifier_get_info(uint64_t modifier);
2394
2395 static inline bool
isl_drm_modifier_has_aux(uint64_t modifier)2396 isl_drm_modifier_has_aux(uint64_t modifier)
2397 {
2398 if (modifier == DRM_FORMAT_MOD_INVALID)
2399 return false;
2400
2401 return isl_drm_modifier_get_info(modifier)->supports_render_compression ||
2402 isl_drm_modifier_get_info(modifier)->supports_media_compression;
2403 }
2404
2405 static inline bool
isl_drm_modifier_plane_is_clear_color(uint64_t modifier,uint32_t plane)2406 isl_drm_modifier_plane_is_clear_color(uint64_t modifier, uint32_t plane)
2407 {
2408 if (modifier == DRM_FORMAT_MOD_INVALID)
2409 return false;
2410
2411 ASSERTED const struct isl_drm_modifier_info *mod_info =
2412 isl_drm_modifier_get_info(modifier);
2413 assert(mod_info);
2414
2415 switch (modifier) {
2416 case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC:
2417 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
2418 assert(mod_info->supports_clear_color);
2419 return plane == 2;
2420 case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
2421 assert(mod_info->supports_clear_color);
2422 return plane == 1;
2423 default:
2424 assert(!mod_info->supports_clear_color);
2425 return false;
2426 }
2427 }
2428
2429 /** Returns the default isl_aux_state for the given modifier.
2430 *
2431 * If we have a modifier which supports compression, then the auxiliary data
2432 * could be in state other than ISL_AUX_STATE_AUX_INVALID. In particular, it
2433 * can be in any of the following:
2434 *
2435 * - ISL_AUX_STATE_CLEAR
2436 * - ISL_AUX_STATE_PARTIAL_CLEAR
2437 * - ISL_AUX_STATE_COMPRESSED_CLEAR
2438 * - ISL_AUX_STATE_COMPRESSED_NO_CLEAR
2439 * - ISL_AUX_STATE_RESOLVED
2440 * - ISL_AUX_STATE_PASS_THROUGH
2441 *
2442 * If the modifier does not support fast-clears, then we are guaranteed
2443 * that the surface is at least partially resolved and the first three not
2444 * possible. We return ISL_AUX_STATE_COMPRESSED_CLEAR if the modifier
2445 * supports fast clears and ISL_AUX_STATE_COMPRESSED_NO_CLEAR if it does not
2446 * because they are the least common denominator of the set of possible aux
2447 * states and will yield a valid interpretation of the aux data.
2448 *
2449 * For modifiers with no aux support, ISL_AUX_STATE_AUX_INVALID is returned.
2450 */
2451 static inline enum isl_aux_state
isl_drm_modifier_get_default_aux_state(uint64_t modifier)2452 isl_drm_modifier_get_default_aux_state(uint64_t modifier)
2453 {
2454 const struct isl_drm_modifier_info *mod_info =
2455 isl_drm_modifier_get_info(modifier);
2456
2457 if (!mod_info || !isl_drm_modifier_has_aux(modifier))
2458 return ISL_AUX_STATE_AUX_INVALID;
2459
2460 assert(mod_info->supports_render_compression !=
2461 mod_info->supports_media_compression);
2462 return mod_info->supports_clear_color ? ISL_AUX_STATE_COMPRESSED_CLEAR :
2463 ISL_AUX_STATE_COMPRESSED_NO_CLEAR;
2464 }
2465
2466 /**
2467 * Return the modifier's score, which indicates the driver's preference for the
2468 * modifier relative to others. A higher score is better. Zero means
2469 * unsupported.
2470 *
2471 * Intended to assist selection of a modifier from an externally provided list,
2472 * such as VkImageDrmFormatModifierListCreateInfoEXT.
2473 */
2474 uint32_t
2475 isl_drm_modifier_get_score(const struct intel_device_info *devinfo,
2476 uint64_t modifier);
2477
2478 /* Return the number of planes used by an image with the given parameters. */
2479 uint32_t
2480 isl_drm_modifier_get_plane_count(const struct intel_device_info *devinfo,
2481 uint64_t modifier,
2482 uint32_t fmt_planes);
2483
2484 struct isl_extent2d ATTRIBUTE_CONST
2485 isl_get_interleaved_msaa_px_size_sa(uint32_t samples);
2486
2487 static inline bool
isl_surf_usage_is_display(isl_surf_usage_flags_t usage)2488 isl_surf_usage_is_display(isl_surf_usage_flags_t usage)
2489 {
2490 return usage & ISL_SURF_USAGE_DISPLAY_BIT;
2491 }
2492
2493 static inline bool
isl_surf_usage_is_depth(isl_surf_usage_flags_t usage)2494 isl_surf_usage_is_depth(isl_surf_usage_flags_t usage)
2495 {
2496 return usage & ISL_SURF_USAGE_DEPTH_BIT;
2497 }
2498
2499 static inline bool
isl_surf_usage_is_stencil(isl_surf_usage_flags_t usage)2500 isl_surf_usage_is_stencil(isl_surf_usage_flags_t usage)
2501 {
2502 return usage & ISL_SURF_USAGE_STENCIL_BIT;
2503 }
2504
2505 static inline bool
isl_surf_usage_is_depth_and_stencil(isl_surf_usage_flags_t usage)2506 isl_surf_usage_is_depth_and_stencil(isl_surf_usage_flags_t usage)
2507 {
2508 return (usage & ISL_SURF_USAGE_DEPTH_BIT) &&
2509 (usage & ISL_SURF_USAGE_STENCIL_BIT);
2510 }
2511
2512 static inline bool
isl_surf_usage_is_depth_or_stencil(isl_surf_usage_flags_t usage)2513 isl_surf_usage_is_depth_or_stencil(isl_surf_usage_flags_t usage)
2514 {
2515 return usage & (ISL_SURF_USAGE_DEPTH_BIT | ISL_SURF_USAGE_STENCIL_BIT);
2516 }
2517
2518 static inline bool
isl_surf_usage_is_cpb(isl_surf_usage_flags_t usage)2519 isl_surf_usage_is_cpb(isl_surf_usage_flags_t usage)
2520 {
2521 return usage & ISL_SURF_USAGE_CPB_BIT;
2522 }
2523
2524 static inline bool
isl_surf_info_is_z16(const struct isl_surf_init_info * info)2525 isl_surf_info_is_z16(const struct isl_surf_init_info *info)
2526 {
2527 return (info->usage & ISL_SURF_USAGE_DEPTH_BIT) &&
2528 (info->format == ISL_FORMAT_R16_UNORM);
2529 }
2530
2531 static inline bool
isl_surf_info_is_z32_float(const struct isl_surf_init_info * info)2532 isl_surf_info_is_z32_float(const struct isl_surf_init_info *info)
2533 {
2534 return (info->usage & ISL_SURF_USAGE_DEPTH_BIT) &&
2535 (info->format == ISL_FORMAT_R32_FLOAT);
2536 }
2537
2538 static inline struct isl_extent2d
isl_extent2d(uint32_t width,uint32_t height)2539 isl_extent2d(uint32_t width, uint32_t height)
2540 {
2541 struct isl_extent2d e = { { 0 } };
2542
2543 e.width = width;
2544 e.height = height;
2545
2546 return e;
2547 }
2548
2549 static inline struct isl_extent3d
isl_extent3d(uint32_t width,uint32_t height,uint32_t depth)2550 isl_extent3d(uint32_t width, uint32_t height, uint32_t depth)
2551 {
2552 struct isl_extent3d e = { { 0 } };
2553
2554 e.width = width;
2555 e.height = height;
2556 e.depth = depth;
2557
2558 return e;
2559 }
2560
2561 static inline struct isl_extent4d
isl_extent4d(uint32_t width,uint32_t height,uint32_t depth,uint32_t array_len)2562 isl_extent4d(uint32_t width, uint32_t height, uint32_t depth,
2563 uint32_t array_len)
2564 {
2565 struct isl_extent4d e = { { 0 } };
2566
2567 e.width = width;
2568 e.height = height;
2569 e.depth = depth;
2570 e.array_len = array_len;
2571
2572 return e;
2573 }
2574
2575 bool isl_color_value_is_zero(union isl_color_value value,
2576 enum isl_format format);
2577
2578 bool isl_color_value_is_zero_one(union isl_color_value value,
2579 enum isl_format format);
2580
2581 static inline bool
isl_swizzle_is_identity(struct isl_swizzle swizzle)2582 isl_swizzle_is_identity(struct isl_swizzle swizzle)
2583 {
2584 return swizzle.r == ISL_CHANNEL_SELECT_RED &&
2585 swizzle.g == ISL_CHANNEL_SELECT_GREEN &&
2586 swizzle.b == ISL_CHANNEL_SELECT_BLUE &&
2587 swizzle.a == ISL_CHANNEL_SELECT_ALPHA;
2588 }
2589
2590 static inline bool
isl_swizzle_is_identity_for_format(enum isl_format format,struct isl_swizzle swizzle)2591 isl_swizzle_is_identity_for_format(enum isl_format format,
2592 struct isl_swizzle swizzle)
2593 {
2594 const struct isl_format_layout *layout = isl_format_get_layout(format);
2595
2596 #define channel_id_or_zero(name, ID) \
2597 (swizzle.name == ISL_CHANNEL_SELECT_##ID || \
2598 layout->channels.name.bits == 0)
2599 return channel_id_or_zero(r, RED) &&
2600 channel_id_or_zero(g, GREEN) &&
2601 channel_id_or_zero(b, BLUE) &&
2602 channel_id_or_zero(a, ALPHA);
2603 #undef channel_id_or_zero
2604 }
2605
2606 bool
2607 isl_swizzle_supports_rendering(const struct intel_device_info *devinfo,
2608 struct isl_swizzle swizzle);
2609
2610 struct isl_swizzle
2611 isl_swizzle_compose(struct isl_swizzle first, struct isl_swizzle second);
2612 struct isl_swizzle
2613 isl_swizzle_invert(struct isl_swizzle swizzle);
2614
2615 uint32_t isl_mocs(const struct isl_device *dev, isl_surf_usage_flags_t usage,
2616 bool external);
2617
2618 #define isl_surf_init(dev, surf, ...) \
2619 isl_surf_init_s((dev), (surf), \
2620 &(struct isl_surf_init_info) { __VA_ARGS__ });
2621
2622 bool
2623 isl_surf_init_s(const struct isl_device *dev,
2624 struct isl_surf *surf,
2625 const struct isl_surf_init_info *restrict info);
2626
2627 void
2628 isl_surf_get_tile_info(const struct isl_surf *surf,
2629 struct isl_tile_info *tile_info);
2630
2631 /**
2632 * :param surf: |in| The main surface
2633 * :param hiz_or_mcs_surf: |in| HiZ or MCS surface associated with the main
2634 * surface
2635 * :returns: true if the given surface supports CCS.
2636 */
2637 bool
2638 isl_surf_supports_ccs(const struct isl_device *dev,
2639 const struct isl_surf *surf,
2640 const struct isl_surf *hiz_or_mcs_surf);
2641
2642 /** Constructs a HiZ surface for the given main surface.
2643 *
2644 * :param surf: |in| The main surface
2645 * :param hiz_surf: |out| The HiZ surface to populate on success
2646 * :returns: false if the main surface cannot support HiZ.
2647 */
2648 bool
2649 isl_surf_get_hiz_surf(const struct isl_device *dev,
2650 const struct isl_surf *surf,
2651 struct isl_surf *hiz_surf);
2652
2653 /** Constructs a MCS for the given main surface.
2654 *
2655 * :param surf: |in| The main surface
2656 * :param mcs_surf: |out| The MCS to populate on success
2657 * :returns: false if the main surface cannot support MCS.
2658 */
2659 bool
2660 isl_surf_get_mcs_surf(const struct isl_device *dev,
2661 const struct isl_surf *surf,
2662 struct isl_surf *mcs_surf);
2663
2664 /** Constructs a CCS for the given main surface.
2665 *
2666 * .. note::
2667 *
2668 * Starting with Tigerlake, the CCS is no longer really a surface. It's not
2669 * laid out as an independent surface and isn't referenced by
2670 * RENDER_SURFACE_STATE::"Auxiliary Surface Base Address" like other
2671 * auxiliary compression surfaces. It's a blob of memory that's a 1:256
2672 * scale-down from the main surfaced that's attached side-band via a second
2673 * set of page tables.
2674 *
2675 * In spite of this, it's sometimes useful to think of it as being a linear
2676 * buffer-like surface, at least for the purposes of allocation. When invoked
2677 * on Tigerlake or later, this function still works and produces such a linear
2678 * surface.
2679 *
2680 * :param surf: |in| The main surface
2681 * :param hiz_or_mcs_surf: |in| HiZ or MCS surface associated with the main
2682 * surface
2683 * :param ccs_surf: |out| The CCS to populate on success
2684 * :param row_pitch_B: The row pitch for the CCS in bytes or 0 if
2685 * ISL should calculate the row pitch.
2686 * :returns: false if the main surface cannot support CCS.
2687 */
2688 bool
2689 isl_surf_get_ccs_surf(const struct isl_device *dev,
2690 const struct isl_surf *surf,
2691 const struct isl_surf *hiz_or_mcs_surf,
2692 struct isl_surf *ccs_surf,
2693 uint32_t row_pitch_B);
2694
2695 #define isl_surf_fill_state(dev, state, ...) \
2696 (dev)->surf_fill_state_s(dev, state, \
2697 &(struct isl_surf_fill_state_info) { __VA_ARGS__ });
2698
2699 #define isl_surf_fill_state_s(dev, state, info) \
2700 (dev)->surf_fill_state_s(dev, state, info)
2701
2702 #define isl_buffer_fill_state(dev, state, ...) \
2703 (dev)->buffer_fill_state_s(dev, state, \
2704 &(struct isl_buffer_fill_state_info) { __VA_ARGS__ });
2705
2706 #define isl_buffer_fill_state_s(dev, state, info) \
2707 (dev)->buffer_fill_state_s(dev, state, info);
2708
2709 #define isl_null_fill_state(dev, state, ...) \
2710 (dev)->null_fill_state_s(dev, state, \
2711 &(struct isl_null_fill_state_info) { __VA_ARGS__ });
2712
2713 #define isl_null_fill_state_s(dev, state, info) \
2714 (dev)->null_fill_state_s(dev, state, info);
2715
2716 #define isl_emit_depth_stencil_hiz(dev, batch, ...) \
2717 (dev)->emit_depth_stencil_hiz_s(dev, batch, \
2718 &(struct isl_depth_stencil_hiz_emit_info) { __VA_ARGS__ })
2719
2720 #define isl_emit_depth_stencil_hiz_s(dev, batch, info) \
2721 (dev)->emit_depth_stencil_hiz_s(dev, batch, info)
2722
2723 #define isl_emit_cpb_control_s(dev, batch, info) \
2724 (dev)->emit_cpb_control_s(dev, batch, info)
2725
2726 void
2727 isl_surf_fill_image_param(const struct isl_device *dev,
2728 struct isl_image_param *param,
2729 const struct isl_surf *surf,
2730 const struct isl_view *view);
2731
2732 void
2733 isl_buffer_fill_image_param(const struct isl_device *dev,
2734 struct isl_image_param *param,
2735 enum isl_format format,
2736 uint64_t size);
2737
2738 /**
2739 * Alignment of the upper-left sample of each subimage, in units of surface
2740 * elements.
2741 */
2742 static inline struct isl_extent3d
isl_surf_get_image_alignment_el(const struct isl_surf * surf)2743 isl_surf_get_image_alignment_el(const struct isl_surf *surf)
2744 {
2745 return surf->image_alignment_el;
2746 }
2747
2748 /**
2749 * Alignment of the upper-left sample of each subimage, in units of surface
2750 * samples.
2751 */
2752 static inline struct isl_extent3d
isl_surf_get_image_alignment_sa(const struct isl_surf * surf)2753 isl_surf_get_image_alignment_sa(const struct isl_surf *surf)
2754 {
2755 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
2756
2757 return isl_extent3d(fmtl->bw * surf->image_alignment_el.w,
2758 fmtl->bh * surf->image_alignment_el.h,
2759 fmtl->bd * surf->image_alignment_el.d);
2760 }
2761
2762 /**
2763 * Logical extent of level 0 in units of surface elements.
2764 */
2765 static inline struct isl_extent4d
isl_surf_get_logical_level0_el(const struct isl_surf * surf)2766 isl_surf_get_logical_level0_el(const struct isl_surf *surf)
2767 {
2768 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
2769
2770 return isl_extent4d(DIV_ROUND_UP(surf->logical_level0_px.w, fmtl->bw),
2771 DIV_ROUND_UP(surf->logical_level0_px.h, fmtl->bh),
2772 DIV_ROUND_UP(surf->logical_level0_px.d, fmtl->bd),
2773 surf->logical_level0_px.a);
2774 }
2775
2776 /**
2777 * Physical extent of level 0 in units of surface elements.
2778 */
2779 static inline struct isl_extent4d
isl_surf_get_phys_level0_el(const struct isl_surf * surf)2780 isl_surf_get_phys_level0_el(const struct isl_surf *surf)
2781 {
2782 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
2783
2784 return isl_extent4d(DIV_ROUND_UP(surf->phys_level0_sa.w, fmtl->bw),
2785 DIV_ROUND_UP(surf->phys_level0_sa.h, fmtl->bh),
2786 DIV_ROUND_UP(surf->phys_level0_sa.d, fmtl->bd),
2787 surf->phys_level0_sa.a);
2788 }
2789
2790 /**
2791 * Pitch between vertically adjacent surface elements, in bytes.
2792 */
2793 static inline uint32_t
isl_surf_get_row_pitch_B(const struct isl_surf * surf)2794 isl_surf_get_row_pitch_B(const struct isl_surf *surf)
2795 {
2796 return surf->row_pitch_B;
2797 }
2798
2799 /**
2800 * Pitch between vertically adjacent surface elements, in units of surface elements.
2801 */
2802 static inline uint32_t
isl_surf_get_row_pitch_el(const struct isl_surf * surf)2803 isl_surf_get_row_pitch_el(const struct isl_surf *surf)
2804 {
2805 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
2806
2807 assert(surf->row_pitch_B % (fmtl->bpb / 8) == 0);
2808 return surf->row_pitch_B / (fmtl->bpb / 8);
2809 }
2810
2811 /**
2812 * Pitch between physical array slices, in rows of surface elements.
2813 */
2814 static inline uint32_t
isl_surf_get_array_pitch_el_rows(const struct isl_surf * surf)2815 isl_surf_get_array_pitch_el_rows(const struct isl_surf *surf)
2816 {
2817 return surf->array_pitch_el_rows;
2818 }
2819
2820 /**
2821 * Pitch between physical array slices, in units of surface elements.
2822 */
2823 static inline uint32_t
isl_surf_get_array_pitch_el(const struct isl_surf * surf)2824 isl_surf_get_array_pitch_el(const struct isl_surf *surf)
2825 {
2826 return isl_surf_get_array_pitch_el_rows(surf) *
2827 isl_surf_get_row_pitch_el(surf);
2828 }
2829
2830 /**
2831 * Pitch between physical array slices, in rows of surface samples.
2832 */
2833 static inline uint32_t
isl_surf_get_array_pitch_sa_rows(const struct isl_surf * surf)2834 isl_surf_get_array_pitch_sa_rows(const struct isl_surf *surf)
2835 {
2836 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
2837 return fmtl->bh * isl_surf_get_array_pitch_el_rows(surf);
2838 }
2839
2840 /**
2841 * Pitch between physical array slices, in bytes.
2842 */
2843 static inline uint32_t
isl_surf_get_array_pitch(const struct isl_surf * surf)2844 isl_surf_get_array_pitch(const struct isl_surf *surf)
2845 {
2846 return isl_surf_get_array_pitch_sa_rows(surf) * surf->row_pitch_B;
2847 }
2848
2849 /**
2850 * Calculate the offset, in units of surface samples, to a subimage in the
2851 * surface.
2852 *
2853 * :invariant: level < surface levels
2854 * :invariant: logical_array_layer < logical array length of surface
2855 * :invariant: logical_z_offset_px < logical depth of surface at level
2856 */
2857 void
2858 isl_surf_get_image_offset_sa(const struct isl_surf *surf,
2859 uint32_t level,
2860 uint32_t logical_array_layer,
2861 uint32_t logical_z_offset_px,
2862 uint32_t *x_offset_sa,
2863 uint32_t *y_offset_sa,
2864 uint32_t *z_offset_sa,
2865 uint32_t *array_offset);
2866
2867 /**
2868 * Calculate the offset, in units of surface elements, to a subimage in the
2869 * surface.
2870 *
2871 * :invariant: level < surface levels
2872 * :invariant: logical_array_layer < logical array length of surface
2873 * :invariant: logical_z_offset_px < logical depth of surface at level
2874 */
2875 void
2876 isl_surf_get_image_offset_el(const struct isl_surf *surf,
2877 uint32_t level,
2878 uint32_t logical_array_layer,
2879 uint32_t logical_z_offset_px,
2880 uint32_t *x_offset_el,
2881 uint32_t *y_offset_el,
2882 uint32_t *z_offset_el,
2883 uint32_t *array_offset);
2884
2885 /**
2886 * Calculate the offset, in bytes and intratile surface samples, to a
2887 * subimage in the surface.
2888 *
2889 * This is equivalent to calling isl_surf_get_image_offset_el, passing the
2890 * result to isl_tiling_get_intratile_offset_el, and converting the tile
2891 * offsets to samples.
2892 *
2893 * :invariant: level < surface levels
2894 * :invariant: logical_array_layer < logical array length of surface
2895 * :invariant: logical_z_offset_px < logical depth of surface at level
2896 */
2897 void
2898 isl_surf_get_image_offset_B_tile_sa(const struct isl_surf *surf,
2899 uint32_t level,
2900 uint32_t logical_array_layer,
2901 uint32_t logical_z_offset_px,
2902 uint64_t *offset_B,
2903 uint32_t *x_offset_sa,
2904 uint32_t *y_offset_sa);
2905
2906 /**
2907 * Calculate the offset, in bytes and intratile surface elements, to a
2908 * subimage in the surface.
2909 *
2910 * This is equivalent to calling isl_surf_get_image_offset_el, passing the
2911 * result to isl_tiling_get_intratile_offset_el.
2912 *
2913 * :invariant: level < surface levels
2914 * :invariant: logical_array_layer < logical array length of surface
2915 * :invariant: logical_z_offset_px < logical depth of surface at level
2916 */
2917 void
2918 isl_surf_get_image_offset_B_tile_el(const struct isl_surf *surf,
2919 uint32_t level,
2920 uint32_t logical_array_layer,
2921 uint32_t logical_z_offset_px,
2922 uint64_t *offset_B,
2923 uint32_t *x_offset_el,
2924 uint32_t *y_offset_el);
2925
2926 /**
2927 * Calculate the range in bytes occupied by a subimage, to the nearest tile.
2928 *
2929 * The range returned will be the smallest memory range in which the give
2930 * subimage fits, rounded to even tiles. Intel images do not usually have a
2931 * direct subimage -> range mapping so the range returned may contain data
2932 * from other sub-images. The returned range is a half-open interval where
2933 * all of the addresses within the subimage are < end_tile_B.
2934 *
2935 * :invariant: level < surface levels
2936 * :invariant: logical_array_layer < logical array length of surface
2937 * :invariant: logical_z_offset_px < logical depth of surface at level
2938 */
2939 void
2940 isl_surf_get_image_range_B_tile(const struct isl_surf *surf,
2941 uint32_t level,
2942 uint32_t logical_array_layer,
2943 uint32_t logical_z_offset_px,
2944 uint64_t *start_tile_B,
2945 uint64_t *end_tile_B);
2946
2947 /**
2948 * Create an isl_surf that represents a particular subimage in the surface.
2949 *
2950 * The newly created surface will have a single miplevel and array slice. The
2951 * surface lives at the returned byte and intratile offsets, in samples.
2952 *
2953 * It is safe to call this function with surf == image_surf.
2954 *
2955 * :invariant: level < surface levels
2956 * :invariant: logical_array_layer < logical array length of surface
2957 * :invariant: logical_z_offset_px < logical depth of surface at level
2958 */
2959 void
2960 isl_surf_get_image_surf(const struct isl_device *dev,
2961 const struct isl_surf *surf,
2962 uint32_t level,
2963 uint32_t logical_array_layer,
2964 uint32_t logical_z_offset_px,
2965 struct isl_surf *image_surf,
2966 uint64_t *offset_B,
2967 uint32_t *x_offset_sa,
2968 uint32_t *y_offset_sa);
2969
2970 /**
2971 * Create an isl_surf that is an uncompressed view of a compressed isl_surf
2972 *
2973 * The incoming surface must have a compressed format. The incoming view must
2974 * be a valid view for the given surface with the exception that it's format
2975 * is an umcompressed format with the same bpb as the surface format. The
2976 * incoming view must have isl_view::levels == 1.
2977 *
2978 * When the function returns, the resulting combination of uncompressed_surf
2979 * and uncompressed_view will be a valid view giving an uncompressed view of
2980 * the incoming surface. Depending on tiling, uncompressed_surf may have a
2981 * different isl_surf::dim from surf and uncompressed_view may or may not have
2982 * a zero base_array_layer. For legacy tiling (not Yf or Ys), an intratile
2983 * offset is returned in x_offset_sa and y_offset_sa. For standard Y tilings
2984 * (Yf and Ys), x_offset_sa and y_offset_sa will be set to zero.
2985 *
2986 * It is safe to call this function with surf == uncompressed_surf and
2987 * view == uncompressed_view.
2988 */
2989 bool MUST_CHECK
2990 isl_surf_get_uncompressed_surf(const struct isl_device *dev,
2991 const struct isl_surf *surf,
2992 const struct isl_view *view,
2993 struct isl_surf *uncompressed_surf,
2994 struct isl_view *uncompressed_view,
2995 uint64_t *offset_B,
2996 uint32_t *x_offset_el,
2997 uint32_t *y_offset_el);
2998
2999 /**
3000 * Calculate the intratile offsets to a surface coordinate, in elements.
3001 *
3002 * This function takes a coordinate in global tile space and returns the byte
3003 * offset to the specific tile as well as the offset within that tile to the
3004 * given coordinate in tile space. The returned x/y/z/array offsets are
3005 * guaranteed to lie within the tile.
3006 *
3007 * :param tiling: |in| The tiling of the surface
3008 * :param bpb: |in| The size of the surface format in bits per
3009 * block
3010 * :param array_pitch_el_rows: |in| The array pitch of the surface for flat 2D
3011 * tilings such as ISL_TILING_Y0
3012 * :param total_x_offset_el: |in| The X offset in tile space, in elements
3013 * :param total_y_offset_el: |in| The Y offset in tile space, in elements
3014 * :param total_z_offset_el: |in| The Z offset in tile space, in elements
3015 * :param total_array_offset: |in| The array offset in tile space
3016 * :param tile_offset_B: |out| The returned byte offset to the tile
3017 * :param x_offset_el: |out| The X offset within the tile, in elements
3018 * :param y_offset_el: |out| The Y offset within the tile, in elements
3019 * :param z_offset_el: |out| The Z offset within the tile, in elements
3020 * :param array_offset: |out| The array offset within the tile
3021 */
3022 void
3023 isl_tiling_get_intratile_offset_el(enum isl_tiling tiling,
3024 enum isl_surf_dim dim,
3025 enum isl_msaa_layout msaa_layout,
3026 uint32_t bpb,
3027 uint32_t samples,
3028 uint32_t row_pitch_B,
3029 uint32_t array_pitch_el_rows,
3030 uint32_t total_x_offset_el,
3031 uint32_t total_y_offset_el,
3032 uint32_t total_z_offset_el,
3033 uint32_t total_array_offset,
3034 uint64_t *tile_offset_B,
3035 uint32_t *x_offset_el,
3036 uint32_t *y_offset_el,
3037 uint32_t *z_offset_el,
3038 uint32_t *array_offset);
3039
3040 /**
3041 * Calculate the intratile offsets to a surface coordinate, in samples.
3042 *
3043 * This function takes a coordinate in global tile space and returns the byte
3044 * offset to the specific tile as well as the offset within that tile to the
3045 * given coordinate in tile space. The returned x/y/z/array offsets are
3046 * guaranteed to lie within the tile.
3047 *
3048 * :param tiling: |in| The tiling of the surface
3049 * :param bpb: |in| The size of the surface format in bits per
3050 * block
3051 * :param array_pitch_el_rows: |in| The array pitch of the surface for flat 2D
3052 * tilings such as ISL_TILING_Y0
3053 * :param total_x_offset_sa: |in| The X offset in tile space, in samples
3054 * :param total_y_offset_sa: |in| The Y offset in tile space, in samples
3055 * :param total_z_offset_sa: |in| The Z offset in tile space, in samples
3056 * :param total_array_offset: |in| The array offset in tile space
3057 * :param tile_offset_B: |out| The returned byte offset to the tile
3058 * :param x_offset_sa: |out| The X offset within the tile, in samples
3059 * :param y_offset_sa: |out| The Y offset within the tile, in samples
3060 * :param z_offset_sa: |out| The Z offset within the tile, in samples
3061 * :param array_offset: |out| The array offset within the tile
3062 */
3063 static inline void
isl_tiling_get_intratile_offset_sa(enum isl_tiling tiling,enum isl_surf_dim dim,enum isl_msaa_layout msaa_layout,enum isl_format format,uint32_t samples,uint32_t row_pitch_B,uint32_t array_pitch_el_rows,uint32_t total_x_offset_sa,uint32_t total_y_offset_sa,uint32_t total_z_offset_sa,uint32_t total_array_offset,uint64_t * tile_offset_B,uint32_t * x_offset_sa,uint32_t * y_offset_sa,uint32_t * z_offset_sa,uint32_t * array_offset)3064 isl_tiling_get_intratile_offset_sa(enum isl_tiling tiling,
3065 enum isl_surf_dim dim,
3066 enum isl_msaa_layout msaa_layout,
3067 enum isl_format format,
3068 uint32_t samples,
3069 uint32_t row_pitch_B,
3070 uint32_t array_pitch_el_rows,
3071 uint32_t total_x_offset_sa,
3072 uint32_t total_y_offset_sa,
3073 uint32_t total_z_offset_sa,
3074 uint32_t total_array_offset,
3075 uint64_t *tile_offset_B,
3076 uint32_t *x_offset_sa,
3077 uint32_t *y_offset_sa,
3078 uint32_t *z_offset_sa,
3079 uint32_t *array_offset)
3080 {
3081 const struct isl_format_layout *fmtl = isl_format_get_layout(format);
3082
3083 /* For computing the intratile offsets, we actually want a strange unit
3084 * which is samples for multisampled surfaces but elements for compressed
3085 * surfaces.
3086 */
3087 assert(total_x_offset_sa % fmtl->bw == 0);
3088 assert(total_y_offset_sa % fmtl->bh == 0);
3089 assert(total_z_offset_sa % fmtl->bd == 0);
3090 const uint32_t total_x_offset_el = total_x_offset_sa / fmtl->bw;
3091 const uint32_t total_y_offset_el = total_y_offset_sa / fmtl->bh;
3092 const uint32_t total_z_offset_el = total_z_offset_sa / fmtl->bd;
3093
3094 isl_tiling_get_intratile_offset_el(tiling, dim, msaa_layout, fmtl->bpb,
3095 samples, row_pitch_B,
3096 array_pitch_el_rows,
3097 total_x_offset_el,
3098 total_y_offset_el,
3099 total_z_offset_el,
3100 total_array_offset,
3101 tile_offset_B,
3102 x_offset_sa, y_offset_sa,
3103 z_offset_sa, array_offset);
3104 *x_offset_sa *= fmtl->bw;
3105 *y_offset_sa *= fmtl->bh;
3106 *z_offset_sa *= fmtl->bd;
3107 }
3108
3109 /**
3110 * Get value of 3DSTATE_DEPTH_BUFFER.SurfaceFormat
3111 *
3112 * @pre surf->usage has ISL_SURF_USAGE_DEPTH_BIT
3113 * @pre surf->format must be a valid format for depth surfaces
3114 */
3115 uint32_t
3116 isl_surf_get_depth_format(const struct isl_device *dev,
3117 const struct isl_surf *surf);
3118
3119 /**
3120 * Performs a copy from linear to tiled surface
3121 */
3122 void
3123 isl_memcpy_linear_to_tiled(uint32_t xt1, uint32_t xt2,
3124 uint32_t yt1, uint32_t yt2,
3125 char *dst, const char *src,
3126 uint32_t dst_pitch, int32_t src_pitch,
3127 bool has_swizzling,
3128 enum isl_tiling tiling,
3129 isl_memcpy_type copy_type);
3130
3131 /**
3132 * Performs a copy from tiled to linear surface
3133 */
3134 void
3135 isl_memcpy_tiled_to_linear(uint32_t xt1, uint32_t xt2,
3136 uint32_t yt1, uint32_t yt2,
3137 char *dst, const char *src,
3138 int32_t dst_pitch, uint32_t src_pitch,
3139 bool has_swizzling,
3140 enum isl_tiling tiling,
3141 isl_memcpy_type copy_type);
3142
3143 /**
3144 * Computes the tile_w (in bytes) and tile_h (in rows) of
3145 * different tiling patterns.
3146 */
3147 static inline void
isl_get_tile_dims(enum isl_tiling tiling,uint32_t cpp,uint32_t * tile_w,uint32_t * tile_h)3148 isl_get_tile_dims(enum isl_tiling tiling, uint32_t cpp,
3149 uint32_t *tile_w, uint32_t *tile_h)
3150 {
3151 switch (tiling) {
3152 case ISL_TILING_X:
3153 *tile_w = 512;
3154 *tile_h = 8;
3155 break;
3156 case ISL_TILING_Y0:
3157 *tile_w = 128;
3158 *tile_h = 32;
3159 break;
3160 case ISL_TILING_LINEAR:
3161 *tile_w = cpp;
3162 *tile_h = 1;
3163 break;
3164 default:
3165 unreachable("not reached");
3166 }
3167 }
3168
3169 /**
3170 * Computes masks that may be used to select the bits of the X and Y
3171 * coordinates that indicate the offset within a tile. If the BO is untiled,
3172 * the masks are set to 0.
3173 */
3174 static inline void
isl_get_tile_masks(enum isl_tiling tiling,uint32_t cpp,uint32_t * mask_x,uint32_t * mask_y)3175 isl_get_tile_masks(enum isl_tiling tiling, uint32_t cpp,
3176 uint32_t *mask_x, uint32_t *mask_y)
3177 {
3178 uint32_t tile_w_bytes, tile_h;
3179
3180 isl_get_tile_dims(tiling, cpp, &tile_w_bytes, &tile_h);
3181
3182 *mask_x = tile_w_bytes / cpp - 1;
3183 *mask_y = tile_h - 1;
3184 }
3185
3186 const char *
3187 isl_aux_op_to_name(enum isl_aux_op op);
3188
3189 const char *
3190 isl_tiling_to_name(enum isl_tiling tiling);
3191
3192 const char *
3193 isl_aux_usage_to_name(enum isl_aux_usage usage);
3194
3195 const char *
3196 isl_aux_state_to_name(enum isl_aux_state state);
3197
3198 #ifdef __cplusplus
3199 }
3200 #endif
3201
3202 #endif /* ISL_H */
3203