1 /*
2 * Copyright 2016 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <stdint.h>
25
26 #define __gen_address_type uint64_t
27 #define __gen_user_data void
28
29 static uint64_t
__gen_combine_address(void * data,void * loc,uint64_t addr,uint32_t delta)30 __gen_combine_address(__attribute__((unused)) void *data,
31 __attribute__((unused)) void *loc, uint64_t addr,
32 uint32_t delta)
33 {
34 return addr + delta;
35 }
36
37 #include "genxml/gen_macros.h"
38 #include "genxml/genX_pack.h"
39
40 #include "isl_priv.h"
41
42 static const uint32_t isl_encode_ds_surftype[] = {
43 #if GFX_VER >= 9
44 /* From the SKL PRM, "3DSTATE_DEPTH_STENCIL::SurfaceType":
45 *
46 * "If depth/stencil is enabled with 1D render target, depth/stencil
47 * surface type needs to be set to 2D surface type and height set to 1.
48 * Depth will use (legacy) TileY and stencil will use TileW. For this
49 * case only, the Surface Type of the depth buffer can be 2D while the
50 * Surface Type of the render target(s) are 1D, representing an
51 * exception to a programming note above.
52 */
53 [ISL_SURF_DIM_1D] = SURFTYPE_2D,
54 #else
55 [ISL_SURF_DIM_1D] = SURFTYPE_1D,
56 #endif
57 [ISL_SURF_DIM_2D] = SURFTYPE_2D,
58 [ISL_SURF_DIM_3D] = SURFTYPE_3D,
59 };
60
61 #if GFX_VER >= 9
62 static const uint8_t isl_encode_tiling[] = {
63 #if GFX_VER >= 20
64 [ISL_TILING_4] = TILE4,
65 [ISL_TILING_64_XE2] = TILE64,
66 #elif GFX_VERx10 >= 125
67 [ISL_TILING_4] = TILE4,
68 [ISL_TILING_64] = TILE64,
69 #else
70 [ISL_TILING_Y0] = NONE,
71 [ISL_TILING_SKL_Yf] = TILEYF,
72 [ISL_TILING_SKL_Ys] = TILEYS,
73 [ISL_TILING_ICL_Yf] = TILEYF,
74 [ISL_TILING_ICL_Ys] = TILEYS,
75 #endif
76 };
77 #endif /* GFX_VER >= 9 */
78
79 void
isl_genX(emit_depth_stencil_hiz_s)80 isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch,
81 const struct isl_depth_stencil_hiz_emit_info *restrict info)
82 {
83 if (info->depth_surf && info->stencil_surf) {
84 if (!dev->info->has_hiz_and_separate_stencil) {
85 assert(info->depth_surf == info->stencil_surf);
86 assert(info->depth_address == info->stencil_address);
87 }
88 assert(info->depth_surf->dim == info->stencil_surf->dim);
89 }
90
91 if (info->depth_surf) {
92 assert((info->depth_surf->usage & ISL_SURF_USAGE_DEPTH_BIT));
93 if (info->depth_surf->dim == ISL_SURF_DIM_3D) {
94 assert(info->view->base_array_layer + info->view->array_len <=
95 info->depth_surf->logical_level0_px.depth);
96 } else {
97 assert(info->view->base_array_layer + info->view->array_len <=
98 info->depth_surf->logical_level0_px.array_len);
99 }
100 }
101
102 if (info->stencil_surf) {
103 assert((info->stencil_surf->usage & ISL_SURF_USAGE_STENCIL_BIT));
104 if (info->stencil_surf->dim == ISL_SURF_DIM_3D) {
105 assert(info->view->base_array_layer + info->view->array_len <=
106 info->stencil_surf->logical_level0_px.depth);
107 } else {
108 assert(info->view->base_array_layer + info->view->array_len <=
109 info->stencil_surf->logical_level0_px.array_len);
110 }
111 }
112
113 struct GENX(3DSTATE_DEPTH_BUFFER) db = {
114 GENX(3DSTATE_DEPTH_BUFFER_header),
115 #if GFX_VER >= 6
116 .MOCS = info->mocs,
117 #endif
118 };
119
120 if (info->depth_surf) {
121 db.SurfaceType = isl_encode_ds_surftype[info->depth_surf->dim];
122 db.SurfaceFormat = isl_surf_get_depth_format(dev, info->depth_surf);
123 db.Width = info->depth_surf->logical_level0_px.width - 1;
124 db.Height = info->depth_surf->logical_level0_px.height - 1;
125 if (db.SurfaceType == SURFTYPE_3D)
126 db.Depth = info->depth_surf->logical_level0_px.depth - 1;
127 } else if (info->stencil_surf) {
128 /* On Gfx12+ 3DSTATE_STENCIL_BUFFER has its own fields for all of
129 * this. No need to replicate it here.
130 */
131 #if GFX_VER < 12
132 db.SurfaceType = isl_encode_ds_surftype[info->stencil_surf->dim];
133 db.SurfaceFormat = D32_FLOAT;
134 db.Width = info->stencil_surf->logical_level0_px.width - 1;
135 db.Height = info->stencil_surf->logical_level0_px.height - 1;
136 if (db.SurfaceType == SURFTYPE_3D)
137 db.Depth = info->stencil_surf->logical_level0_px.depth - 1;
138 #else
139 db.SurfaceType = SURFTYPE_NULL;
140 db.SurfaceFormat = D32_FLOAT;
141 #endif
142 } else {
143 db.SurfaceType = SURFTYPE_NULL;
144 db.SurfaceFormat = D32_FLOAT;
145 }
146
147 if (info->depth_surf || info->stencil_surf) {
148 /* These are based entirely on the view */
149 db.RenderTargetViewExtent = info->view->array_len - 1;
150 db.LOD = info->view->base_level;
151 db.MinimumArrayElement = info->view->base_array_layer;
152
153 /* From the Haswell PRM docs for 3DSTATE_DEPTH_BUFFER::Depth
154 *
155 * "This field specifies the total number of levels for a volume
156 * texture or the number of array elements allowed to be accessed
157 * starting at the Minimum Array Element for arrayed surfaces. If the
158 * volume texture is MIP-mapped, this field specifies the depth of
159 * the base MIP level."
160 *
161 * For 3D surfaces, we set it to the correct depth above. For non-3D
162 * surfaces, this is the same as RenderTargetViewExtent.
163 */
164 if (db.SurfaceType != SURFTYPE_3D)
165 db.Depth = db.RenderTargetViewExtent;
166 }
167
168 if (info->depth_surf) {
169 #if GFX_VER >= 7
170 db.DepthWriteEnable = true;
171 #endif
172 db.SurfaceBaseAddress = info->depth_address;
173
174 #if GFX_VERx10 >= 125
175 db.TiledMode = isl_encode_tiling[info->depth_surf->tiling];
176 db.MipTailStartLOD = info->depth_surf->miptail_start_level;
177 #if GFX_VERx10 < 20
178 db.CompressionMode = isl_aux_usage_has_ccs(info->hiz_usage);
179 #endif
180 db.RenderCompressionFormat =
181 isl_get_render_compression_format(info->depth_surf->format);
182 #elif GFX_VER >= 9
183 /* Gen9+ depth is always Y-tiled but it may be Y0, Yf, or Ys. */
184 assert(isl_tiling_is_any_y(info->depth_surf->tiling));
185 db.TiledResourceMode = isl_encode_tiling[info->depth_surf->tiling];
186 db.MipTailStartLOD = info->depth_surf->miptail_start_level;
187 #elif GFX_VER >= 7
188 /* Gen7+ depth is always Y-tiled. We don't even have a bit for it */
189 #else
190 assert(info->depth_surf->tiling == ISL_TILING_Y0);
191 db.TiledSurface = true;
192 db.TileWalk = TILEWALK_YMAJOR;
193 db.MIPMapLayoutMode = MIPLAYOUT_BELOW;
194 #endif
195
196 db.SurfacePitch = info->depth_surf->row_pitch_B - 1;
197 #if GFX_VER >= 8
198 db.SurfaceQPitch =
199 isl_surf_get_array_pitch_el_rows(info->depth_surf) >> 2;
200 #endif
201
202 #if GFX_VER == 12
203 db.ControlSurfaceEnable = db.DepthBufferCompressionEnable =
204 isl_aux_usage_has_ccs(info->hiz_usage);
205 #endif
206 }
207
208 #if GFX_VER == 5 || GFX_VER == 6
209 const bool separate_stencil =
210 info->stencil_surf && info->stencil_surf->format == ISL_FORMAT_R8_UINT;
211 if (separate_stencil || info->hiz_usage == ISL_AUX_USAGE_HIZ) {
212 assert(ISL_DEV_USE_SEPARATE_STENCIL(dev));
213 /* From the IronLake PRM, Vol 2 Part 1:
214 *
215 * 3DSTATE_DEPTH_BUFFER::Separate Stencil Buffer Enable
216 * If this field is enabled, Hierarchical Depth Buffer Enable must
217 * also be enabled.
218 *
219 * 3DSTATE_DEPTH_BUFFER::Tiled Surface
220 * When Hierarchical Depth Buffer is enabled, this bit must be set.
221 */
222 db.SeparateStencilBufferEnable = true;
223 db.HierarchicalDepthBufferEnable = true;
224 db.TiledSurface = true;
225 }
226 #endif
227
228 #if GFX_VER >= 6
229 struct GENX(3DSTATE_STENCIL_BUFFER) sb = {
230 GENX(3DSTATE_STENCIL_BUFFER_header),
231 .MOCS = info->mocs,
232 };
233 #else
234 # define sb db
235 #endif
236
237 if (info->stencil_surf) {
238 #if GFX_VER >= 7 && GFX_VER < 12
239 db.StencilWriteEnable = true;
240 #endif
241 #if GFX_VERx10 >= 125
242 #if GFX_VER < 20
243 sb.CompressionMode = isl_aux_usage_has_ccs(info->stencil_aux_usage);
244 sb.RenderCompressionFormat =
245 isl_get_render_compression_format(info->stencil_surf->format);
246 #else
247 sb.CompressionFormat =
248 isl_get_render_compression_format(info->stencil_surf->format);
249 #endif
250 #endif
251 #if GFX_VER >= 12
252 sb.TiledMode = isl_encode_tiling[info->stencil_surf->tiling];
253 sb.MipTailStartLOD = info->stencil_surf->miptail_start_level;
254 sb.StencilWriteEnable = true;
255 sb.SurfaceType = SURFTYPE_2D;
256 sb.Width = info->stencil_surf->logical_level0_px.width - 1;
257 sb.Height = info->stencil_surf->logical_level0_px.height - 1;
258 sb.Depth = sb.RenderTargetViewExtent = info->view->array_len - 1;
259 sb.SurfLOD = info->view->base_level;
260 sb.MinimumArrayElement = info->view->base_array_layer;
261 assert(info->stencil_aux_usage == ISL_AUX_USAGE_NONE ||
262 info->stencil_aux_usage == ISL_AUX_USAGE_STC_CCS);
263 #if GFX_VER < 20
264 sb.StencilCompressionEnable =
265 info->stencil_aux_usage == ISL_AUX_USAGE_STC_CCS;
266 sb.ControlSurfaceEnable = sb.StencilCompressionEnable;
267 #endif
268 #elif GFX_VERx10 >= 75
269 sb.StencilBufferEnable = true;
270 #endif
271 sb.SurfaceBaseAddress = info->stencil_address;
272 sb.SurfacePitch = info->stencil_surf->row_pitch_B - 1;
273 #if GFX_VER >= 8
274 sb.SurfaceQPitch =
275 isl_surf_get_array_pitch_el_rows(info->stencil_surf) >> 2;
276 #endif
277 } else {
278 #if GFX_VER >= 12
279 sb.SurfaceType = SURFTYPE_NULL;
280
281 /* The docs seem to indicate that if surf-type is null, then we may need
282 * to match the depth-buffer value for `Depth`. It may be a
283 * documentation bug, since the other fields don't require this.
284 *
285 * TODO: Confirm documentation and remove setting of `Depth` if not
286 * required.
287 */
288 sb.Depth = db.Depth;
289 #endif
290 }
291
292 #if GFX_VER >= 6
293 struct GENX(3DSTATE_HIER_DEPTH_BUFFER) hiz = {
294 GENX(3DSTATE_HIER_DEPTH_BUFFER_header),
295 .MOCS = info->mocs,
296 };
297 #if GFX_VER < 20
298 struct GENX(3DSTATE_CLEAR_PARAMS) clear = {
299 GENX(3DSTATE_CLEAR_PARAMS_header),
300 };
301 #endif
302
303 assert(info->hiz_usage == ISL_AUX_USAGE_NONE ||
304 isl_aux_usage_has_hiz(info->hiz_usage));
305 if (isl_aux_usage_has_hiz(info->hiz_usage)) {
306 assert(GFX_VER >= 12 || info->hiz_usage == ISL_AUX_USAGE_HIZ);
307 db.HierarchicalDepthBufferEnable = true;
308
309 hiz.SurfaceBaseAddress = info->hiz_address;
310 hiz.SurfacePitch = info->hiz_surf->row_pitch_B - 1;
311
312 #if GFX_VERx10 >= 125
313 /* From 3DSTATE_HIER_DEPTH_BUFFER_BODY::TiledMode,
314 *
315 * HZ buffer only supports Tile4 mode
316 *
317 * and from Bspec 47009, "Hierarchical Depth Buffer",
318 *
319 * The format of the data in the hierarchical depth buffer is not
320 * documented here, as this surface needs only to be allocated by
321 * software.
322 *
323 * We choose to apply the second quote to the first. ISL describes HiZ
324 * with a tiling that has the same extent as Tile4 (128Bx32), but a
325 * different internal layout. This has two benefits: 1) it allows us to
326 * have the correct allocation size and 2) we can continue to use a
327 * tiling that was determined to exist on some prior platforms.
328 */
329 assert(info->hiz_surf->tiling == ISL_TILING_HIZ);
330 hiz.TiledMode = TILE4;
331 #elif GFX_VERx10 >= 120
332 /* From 3DSTATE_HIER_DEPTH_BUFFER_BODY::TiledMode,
333 *
334 * HZ buffer only supports Tile Y mode.
335 *
336 * and
337 *
338 * Value | Name
339 * ----------------------------------------
340 * 0h | No tiled resource (Tile Y Mode).
341 */
342 assert(info->hiz_surf->tiling == ISL_TILING_HIZ);
343 hiz.TiledMode = NONE;
344 #endif
345
346 #if GFX_VER >= 12
347 hiz.HierarchicalDepthBufferWriteThruEnable =
348 info->hiz_usage == ISL_AUX_USAGE_HIZ_CCS_WT;
349
350 /* The bspec docs for this bit are fairly unclear about exactly what is
351 * and isn't supported with HiZ write-through. It's fairly clear that
352 * you can't sample from a multisampled depth buffer with CCS. This
353 * limitation isn't called out explicitly but the docs for the CCS_E
354 * value of RENDER_SURFACE_STATE::AuxiliarySurfaceMode say:
355 *
356 * "If Number of multisamples > 1, programming this value means MSAA
357 * compression is enabled for that surface. Auxiliary surface is MSC
358 * with tile y."
359 *
360 * Since this interpretation ignores whether the surface is
361 * depth/stencil or not and since multisampled depth buffers use
362 * ISL_MSAA_LAYOUT_INTERLEAVED which is incompatible with MCS
363 * compression, this means that we can't even specify MSAA depth CCS in
364 * RENDER_SURFACE_STATE::AuxiliarySurfaceMode. The BSpec also says, for
365 * 3DSTATE_HIER_DEPTH_BUFFER::HierarchicalDepthBufferWriteThruEnable,
366 *
367 * "This bit must NOT be set for >1x MSAA modes, since sampler
368 * doesn't support sampling from >1x MSAA depth buffer."
369 *
370 * Again, this is all focused around what the sampler can do and not
371 * what the depth hardware can do.
372 *
373 * Reading even more internal docs which can't be quoted here makes it
374 * pretty clear that, even if it's not currently called out in the
375 * BSpec, HiZ+CCS write-through isn't intended to work with MSAA and we
376 * shouldn't try to use it. Treat it as if it's disallowed even if the
377 * BSpec doesn't explicitly document that.
378 */
379 if (hiz.HierarchicalDepthBufferWriteThruEnable)
380 assert(info->depth_surf->samples == 1);
381 #endif
382
383 #if GFX_VER >= 8
384 /* From the SKL PRM Vol2a:
385 *
386 * The interpretation of this field is dependent on Surface Type
387 * as follows:
388 * - SURFTYPE_1D: distance in pixels between array slices
389 * - SURFTYPE_2D/CUBE: distance in rows between array slices
390 * - SURFTYPE_3D: distance in rows between R - slices
391 *
392 * Unfortunately, the docs aren't 100% accurate here. They fail to
393 * mention that the 1-D rule only applies to linear 1-D images.
394 * Since depth and HiZ buffers are always tiled, they are treated as
395 * 2-D images. Prior to Sky Lake, this field is always in rows.
396 */
397 hiz.SurfaceQPitch =
398 isl_surf_get_array_pitch_sa_rows(info->hiz_surf) >> 2;
399 #endif
400
401 #if GFX_VER < 20
402 clear.DepthClearValueValid = true;
403 #if GFX_VER >= 8
404 clear.DepthClearValue = info->depth_clear_value;
405 #else
406 switch (info->depth_surf->format) {
407 case ISL_FORMAT_R32_FLOAT: {
408 union { float f; uint32_t u; } fu;
409 fu.f = info->depth_clear_value;
410 clear.DepthClearValue = fu.u;
411 break;
412 }
413 case ISL_FORMAT_R24_UNORM_X8_TYPELESS:
414 clear.DepthClearValue = info->depth_clear_value * ((1u << 24) - 1);
415 break;
416 case ISL_FORMAT_R16_UNORM:
417 clear.DepthClearValue = info->depth_clear_value * ((1u << 16) - 1);
418 break;
419 default:
420 unreachable("Invalid depth type");
421 }
422 #endif
423 #endif
424 }
425 #endif /* GFX_VER >= 6 */
426
427 /* Pack everything into the batch */
428 uint32_t *dw = batch;
429 GENX(3DSTATE_DEPTH_BUFFER_pack)(NULL, dw, &db);
430 dw += GENX(3DSTATE_DEPTH_BUFFER_length);
431
432 #if GFX_VER >= 6
433 GENX(3DSTATE_STENCIL_BUFFER_pack)(NULL, dw, &sb);
434 dw += GENX(3DSTATE_STENCIL_BUFFER_length);
435
436 GENX(3DSTATE_HIER_DEPTH_BUFFER_pack)(NULL, dw, &hiz);
437 dw += GENX(3DSTATE_HIER_DEPTH_BUFFER_length);
438
439 #if GFX_VER < 20
440 GENX(3DSTATE_CLEAR_PARAMS_pack)(NULL, dw, &clear);
441 dw += GENX(3DSTATE_CLEAR_PARAMS_length);
442 #endif /* GFX_VER < 20 */
443 #endif /* GFX_VER >= 6 */
444 }
445