1 /*
2 * Copyright (c) 2018 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "isl_gfx9.h"
25 #include "isl_gfx12.h"
26 #include "isl_priv.h"
27
28 /**
29 * @brief Filter out tiling flags that are incompatible with the surface.
30 *
31 * The resultant outgoing @a flags is a subset of the incoming @a flags. The
32 * outgoing flags may be empty (0x0) if the incoming flags were too
33 * restrictive.
34 *
35 * For example, if the surface will be used for a display
36 * (ISL_SURF_USAGE_DISPLAY_BIT), then this function filters out all tiling
37 * flags except ISL_TILING_4_BIT, ISL_TILING_X_BIT, and ISL_TILING_LINEAR_BIT.
38 */
39 void
isl_gfx125_filter_tiling(const struct isl_device * dev,const struct isl_surf_init_info * restrict info,isl_tiling_flags_t * flags)40 isl_gfx125_filter_tiling(const struct isl_device *dev,
41 const struct isl_surf_init_info *restrict info,
42 isl_tiling_flags_t *flags)
43 {
44 /* Clear flags unsupported on this hardware */
45 assert(ISL_GFX_VERX10(dev) >= 125);
46
47 const isl_tiling_flags_t tile64_bit =
48 ISL_GFX_VERX10(dev) >= 200 ? ISL_TILING_64_XE2_BIT : ISL_TILING_64_BIT;
49
50 *flags &= ISL_TILING_LINEAR_BIT |
51 ISL_TILING_X_BIT |
52 ISL_TILING_4_BIT |
53 tile64_bit;
54
55 if (isl_surf_usage_is_depth_or_stencil(info->usage)) {
56 *flags &= ISL_TILING_4_BIT | ISL_TILING_STD_64_MASK;
57
58 /* We choose to avoid Tile64 for 3D depth/stencil buffers. The swizzle
59 * for Tile64 is dependent on the image dimension. So, reads and writes
60 * should specify the same dimension to consistently interpret the data.
61 * This is not possible for 3D depth/stencil buffers however. Such
62 * buffers can be sampled from with a 3D view, but rendering is only
63 * possible with a 2D view due to the limitations of
64 * 3DSTATE_(DEPTH|STENCIL)_BUFFER.
65 */
66 if (info->dim == ISL_SURF_DIM_3D)
67 *flags &= ~ISL_TILING_STD_64_MASK;
68 }
69
70 if (info->usage & ISL_SURF_USAGE_DISPLAY_BIT)
71 *flags &= ~ISL_TILING_STD_64_MASK;
72
73 /* From RENDER_SURFACE_STATE::AuxiliarySurfaceMode,
74 *
75 * MCS tiling format is always Tile4
76 */
77 if (info->usage & ISL_SURF_USAGE_MCS_BIT)
78 *flags &= ISL_TILING_4_BIT;
79
80 /* From RENDER_SURFACE_STATE::TileMode,
81 *
82 * TILEMODE_XMAJOR is only allowed if Surface Type is SURFTYPE_2D.
83 *
84 * X-tiling is only allowed for 2D surfaces.
85 */
86 if (info->dim != ISL_SURF_DIM_2D)
87 *flags &= ~ISL_TILING_X_BIT;
88
89 /* From ATS-M PRMs, Volume 2d: Command Reference: Structures,
90 * RENDER_SURFACE_STATE:TileMode :
91 *
92 * "If Surface Type is SURFTYPE_1D this field must be TILEMODE_LINEAR,
93 * unless Sampler Legacy 1D Map Layout Disable is set to 0, in which
94 * case TILEMODE_YMAJOR is also allowed. Horizontal Alignment must be
95 * programmed for the required alignment between MIPs. MIP tails are
96 * not supported."
97 *
98 * Tile4 is the replacement for TileY0 on ACM.
99 */
100 if (info->dim == ISL_SURF_DIM_1D)
101 *flags &= ISL_TILING_LINEAR_BIT | ISL_TILING_4_BIT;
102
103 /* TILE64 does not work with YCRCB formats, according to bspec 58767:
104 * "Packed YUV surface formats such as YCRCB_NORMAL, YCRCB_SWAPUVY etc.
105 * will not support as Tile64"
106 */
107 if (isl_format_is_yuv(info->format))
108 *flags &= ~ISL_TILING_STD_64_MASK;
109
110 /* Tile64 tilings for 3D have a different swizzling than a 2D surface. So
111 * filter them out if the usage wants 2D/3D compatibility.
112 */
113 if (info->usage & ISL_SURF_USAGE_2D_3D_COMPATIBLE_BIT)
114 *flags &= ~ISL_TILING_STD_64_MASK;
115
116 /* From RENDER_SURFACE_STATE::NumberofMultisamples,
117 *
118 * This field must not be programmed to anything other than
119 * [MULTISAMPLECOUNT_1] unless the Tile Mode field is programmed to
120 * Tile64.
121 *
122 * Tile64 is required for multisampling.
123 */
124 if (info->samples > 1)
125 *flags &= ISL_TILING_STD_64_MASK;
126
127 /* Tile64 is not defined for format sizes that are 24, 48, and 96 bpb. */
128 if (isl_format_get_layout(info->format)->bpb % 3 == 0)
129 *flags &= ~ISL_TILING_STD_64_MASK;
130
131 /* BSpec 46962: 3DSTATE_CPSIZE_CONTROL_BUFFER::Tiled Mode : TILE4 & TILE64
132 * are the only 2 valid values.
133 *
134 * TODO: For now we only TILE64 as we need to figure out potential
135 * additional requirements for TILE4.
136 */
137 if (info->usage & ISL_SURF_USAGE_CPB_BIT)
138 *flags &= ISL_TILING_STD_64_MASK;
139 }
140
141 void
isl_gfx125_choose_image_alignment_el(const struct isl_device * dev,const struct isl_surf_init_info * restrict info,enum isl_tiling tiling,enum isl_dim_layout dim_layout,enum isl_msaa_layout msaa_layout,struct isl_extent3d * image_align_el)142 isl_gfx125_choose_image_alignment_el(const struct isl_device *dev,
143 const struct isl_surf_init_info *restrict info,
144 enum isl_tiling tiling,
145 enum isl_dim_layout dim_layout,
146 enum isl_msaa_layout msaa_layout,
147 struct isl_extent3d *image_align_el)
148 {
149 /* Handled by isl_choose_image_alignment_el */
150 assert(info->format != ISL_FORMAT_GFX125_HIZ);
151
152 const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
153
154 if (isl_tiling_is_64(tiling)) {
155 /* From RENDER_SURFACE_STATE::SurfaceHorizontalAlignment,
156 *
157 * This field is ignored for Tile64 surface formats because horizontal
158 * alignment is always to the start of the next tile in that case.
159 *
160 * From RENDER_SURFACE_STATE::SurfaceQPitch,
161 *
162 * Because MSAA is only supported for Tile64, QPitch must also be
163 * programmed to an aligned tile boundary for MSAA surfaces.
164 *
165 * Images in this surface must be tile-aligned. The table on the Bspec
166 * page, "2D/CUBE Alignment Requirement", shows that the vertical
167 * alignment is also a tile height for non-MSAA as well.
168 */
169 struct isl_tile_info tile_info;
170 isl_tiling_get_info(tiling, info->dim, msaa_layout, fmtl->bpb,
171 info->samples, &tile_info);
172
173 *image_align_el = isl_extent3d(tile_info.logical_extent_el.w,
174 tile_info.logical_extent_el.h,
175 1);
176 } else if (isl_surf_usage_is_depth(info->usage)) {
177 /* From RENDER_SURFACE_STATE::SurfaceHorizontalAlignment,
178 *
179 * - 16b Depth Surfaces Must Be HALIGN=16Bytes (8texels)
180 * - 32b Depth Surfaces Must Be HALIGN=32Bytes (8texels)
181 *
182 * From RENDER_SURFACE_STATE::SurfaceVerticalAlignment,
183 *
184 * This field is intended to be set to VALIGN_4 if the surface
185 * was rendered as a depth buffer [...]
186 *
187 * and
188 *
189 * This field should also be set to VALIGN_8 if the surface was
190 * rendered as a D16_UNORM depth buffer [...]
191 */
192 *image_align_el =
193 info->format != ISL_FORMAT_R16_UNORM ?
194 isl_extent3d(8, 4, 1) :
195 isl_extent3d(8, 8, 1);
196 } else if (isl_surf_usage_is_stencil(info->usage)) {
197 /* From RENDER_SURFACE_STATE::SurfaceHorizontalAlignment,
198 *
199 * - Stencil Surfaces (8b) Must be HALIGN=16Bytes (16texels)
200 *
201 * From RENDER_SURFACE_STATE::SurfaceVerticalAlignment,
202 *
203 * This field is intended to be set to VALIGN_8 only if
204 * the surface was rendered as a stencil buffer, since stencil buffer
205 * surfaces support only alignment of 8.
206 */
207 *image_align_el = isl_extent3d(16, 8, 1);
208 } else if (!isl_is_pow2(fmtl->bpb)) {
209 /* From RENDER_SURFACE_STATE::SurfaceHorizontalAlignment,
210 *
211 * - Linear Surfaces surfaces must use HALIGN=128, including 1D which
212 * is always Linear. For 24,48 and 96bpp this means 128texels.
213 * - Tiled 24bpp, 48bpp and 96bpp surfaces must use HALIGN=16
214 */
215 *image_align_el = tiling == ISL_TILING_LINEAR ?
216 isl_extent3d(128, 4, 1) :
217 isl_extent3d(16, 4, 1);
218 } else {
219 /* From RENDER_SURFACE_STATE::SurfaceHorizontalAlignment,
220 *
221 * - Losslessly Compressed Surfaces Must be HALIGN=128 for all
222 * supported Bpp
223 * - 64bpe and 128bpe Surfaces Must Be HALIGN=64Bytes or 128Bytes (4,
224 * 8 texels or 16 texels)
225 * - Linear Surfaces surfaces must use HALIGN=128, including 1D which
226 * is always Linear.
227 *
228 * Even though we could choose a horizontal alignment of 64B for certain
229 * 64 and 128-bit formats, we want to be able to enable CCS whenever
230 * possible and CCS requires 128B horizontal alignment.
231 */
232 *image_align_el = isl_extent3d(128 * 8 / fmtl->bpb, 4, 1);
233 }
234 }
235
236 void
isl_gfx12_choose_image_alignment_el(const struct isl_device * dev,const struct isl_surf_init_info * restrict info,enum isl_tiling tiling,enum isl_dim_layout dim_layout,enum isl_msaa_layout msaa_layout,struct isl_extent3d * image_align_el)237 isl_gfx12_choose_image_alignment_el(const struct isl_device *dev,
238 const struct isl_surf_init_info *restrict info,
239 enum isl_tiling tiling,
240 enum isl_dim_layout dim_layout,
241 enum isl_msaa_layout msaa_layout,
242 struct isl_extent3d *image_align_el)
243 {
244 /* Handled by isl_choose_image_alignment_el */
245 assert(info->format != ISL_FORMAT_HIZ);
246
247 const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
248 if (fmtl->txc == ISL_TXC_CCS) {
249 /* This CCS compresses a 2D-view of the entire surface. */
250 assert(info->levels == 1 && info->array_len == 1 && info->depth == 1);
251 *image_align_el = isl_extent3d(1, 1, 1);
252 return;
253 }
254
255 if (isl_tiling_is_std_y(tiling)) {
256 /* From RENDER_SURFACE_STATE::SurfaceHorizontalAlignment,
257 *
258 * This field is ignored for Tile64 surface formats because horizontal
259 * alignment is always to the start of the next tile in that case.
260 *
261 * From RENDER_SURFACE_STATE::SurfaceQPitch,
262 *
263 * Because MSAA is only supported for Tile64, QPitch must also be
264 * programmed to an aligned tile boundary for MSAA surfaces.
265 *
266 * Images in this surface must be tile-aligned. The table on the Bspec
267 * page, "2D/CUBE Alignment Requirement", shows that the vertical
268 * alignment is also a tile height for non-MSAA as well.
269 */
270 struct isl_tile_info tile_info;
271 isl_tiling_get_info(tiling, info->dim, msaa_layout, fmtl->bpb,
272 info->samples, &tile_info);
273
274 *image_align_el = isl_extent3d(tile_info.logical_extent_el.w,
275 tile_info.logical_extent_el.h,
276 1);
277 } else if (isl_surf_usage_is_depth(info->usage)) {
278 /* The alignment parameters for depth buffers are summarized in the
279 * following table:
280 *
281 * Surface Format | MSAA | Align Width | Align Height
282 * -----------------+-------------+-------------+--------------
283 * D16_UNORM | 1x, 4x, 16x | 8 | 8
284 * ----------------+-------------+-------------+--------------
285 * D16_UNORM | 2x, 8x | 16 | 4
286 * ----------------+-------------+-------------+--------------
287 * other | any | 8 | 4
288 * -----------------+-------------+-------------+--------------
289 */
290 assert(isl_is_pow2(info->samples));
291 *image_align_el =
292 info->format != ISL_FORMAT_R16_UNORM ?
293 isl_extent3d(8, 4, 1) :
294 (info->samples == 2 || info->samples == 8 ?
295 isl_extent3d(16, 4, 1) : isl_extent3d(8, 8, 1));
296 } else if (isl_surf_usage_is_stencil(info->usage)) {
297 *image_align_el = isl_extent3d(16, 8, 1);
298 } else {
299 isl_gfx9_choose_image_alignment_el(dev, info, tiling, dim_layout,
300 msaa_layout, image_align_el);
301 }
302 }
303