1 /*
2 * Copyright 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "isl_gfx8.h"
25 #include "isl_gfx9.h"
26 #include "isl_priv.h"
27
28 void
isl_gfx9_choose_image_alignment_el(const struct isl_device * dev,const struct isl_surf_init_info * restrict info,enum isl_tiling tiling,enum isl_dim_layout dim_layout,enum isl_msaa_layout msaa_layout,struct isl_extent3d * image_align_el)29 isl_gfx9_choose_image_alignment_el(const struct isl_device *dev,
30 const struct isl_surf_init_info *restrict info,
31 enum isl_tiling tiling,
32 enum isl_dim_layout dim_layout,
33 enum isl_msaa_layout msaa_layout,
34 struct isl_extent3d *image_align_el)
35 {
36 /* Handled by isl_choose_image_alignment_el */
37 assert(info->format != ISL_FORMAT_HIZ);
38
39 const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
40 if (fmtl->txc == ISL_TXC_CCS) {
41 /* Sky Lake PRM Vol. 7, "MCS Buffer for Render Target(s)" (p. 632):
42 *
43 * "Mip-mapped and arrayed surfaces are supported with MCS buffer
44 * layout with these alignments in the RT space: Horizontal
45 * Alignment = 128 and Vertical Alignment = 64."
46 */
47 *image_align_el = isl_extent3d(128 / fmtl->bw, 64 / fmtl->bh, 1);
48 return;
49 }
50
51 /* This BSpec text provides some insight into the hardware's alignment
52 * requirements [Skylake BSpec > Memory Views > Common Surface Formats >
53 * Surface Layout and Tiling > 2D Surfaces]:
54 *
55 * An LOD must be aligned to a cache-line except for some special cases
56 * related to Planar YUV surfaces. In general, the cache-alignment
57 * restriction implies there is a minimum height for an LOD of 4 texels.
58 * So, LODs which are smaller than 4 high are padded.
59 *
60 * From the Skylake BSpec, RENDER_SURFACE_STATE Surface Vertical Alignment:
61 *
62 * - For Sampling Engine and Render Target Surfaces: This field
63 * specifies the vertical alignment requirement in elements for the
64 * surface. [...] An element is defined as a pixel in uncompressed
65 * surface formats, and as a compression block in compressed surface
66 * formats. For MSFMT_DEPTH_STENCIL type multisampled surfaces, an
67 * element is a sample.
68 *
69 * - This field is used for 2D, CUBE, and 3D surface alignment when Tiled
70 * Resource Mode is TRMODE_NONE (Tiled Resource Mode is disabled).
71 * This field is ignored for 1D surfaces and also when Tiled Resource
72 * Mode is not TRMODE_NONE (e.g. Tiled Resource Mode is enabled).
73 *
74 * See the appropriate Alignment table in the "Surface Layout and
75 * Tiling" section under Common Surface Formats for the table of
76 * alignment values for Tiled Resources.
77 *
78 * - For uncompressed surfaces, the units of "j" are rows of pixels on
79 * the physical surface. For compressed texture formats, the units of
80 * "j" are in compression blocks, thus each increment in "j" is equal
81 * to h pixels, where h is the height of the compression block in
82 * pixels.
83 *
84 * - Valid Values: VALIGN_4, VALIGN_8, VALIGN_16
85 *
86 * From the Skylake BSpec, RENDER_SURFACE_STATE Surface Horizontal
87 * Alignment:
88 *
89 * - For uncompressed surfaces, the units of "i" are pixels on the
90 * physical surface. For compressed texture formats, the units of "i"
91 * are in compression blocks, thus each increment in "i" is equal to
92 * w pixels, where w is the width of the compression block in pixels.
93 *
94 * - Valid Values: HALIGN_4, HALIGN_8, HALIGN_16
95 */
96
97 if (isl_tiling_is_std_y(tiling)) {
98 /* Ys and Yf tiled images are aligned to the tile size */
99 struct isl_tile_info tile_info;
100 isl_tiling_get_info(tiling, info->dim, msaa_layout,
101 fmtl->bpb, info->samples, &tile_info);
102 *image_align_el = (struct isl_extent3d) {
103 .w = tile_info.logical_extent_el.w,
104 .h = tile_info.logical_extent_el.h,
105 .d = tile_info.logical_extent_el.d,
106 };
107 return;
108 }
109
110 if (dim_layout == ISL_DIM_LAYOUT_GFX9_1D) {
111 /* See the Skylake BSpec > Memory Views > Common Surface Formats > Surface
112 * Layout and Tiling > 1D Surfaces > 1D Alignment Requirements.
113 */
114 *image_align_el = isl_extent3d(64, 1, 1);
115 return;
116 }
117
118 if (isl_format_is_compressed(info->format)) {
119 /* On Gfx9, the meaning of RENDER_SURFACE_STATE's
120 * SurfaceHorizontalAlignment and SurfaceVerticalAlignment changed for
121 * compressed formats. They now indicate a multiple of the compression
122 * block. For example, if the compression mode is ETC2 then HALIGN_4
123 * indicates a horizontal alignment of 16 pixels.
124 *
125 * To avoid wasting memory, choose the smallest alignment possible:
126 * HALIGN_4 and VALIGN_4.
127 */
128 *image_align_el = isl_extent3d(4, 4, 1);
129 return;
130 }
131
132 isl_gfx8_choose_image_alignment_el(dev, info, tiling, dim_layout,
133 msaa_layout, image_align_el);
134 }
135