1 /*
2 * Copyright 2016 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <stdint.h>
25
26 #define __gen_address_type uint64_t
27 #define __gen_user_data void
28
29 static uint64_t
__gen_combine_address(void * data,void * loc,uint64_t addr,uint32_t delta)30 __gen_combine_address(__attribute__((unused)) void *data,
31 __attribute__((unused)) void *loc, uint64_t addr,
32 uint32_t delta)
33 {
34 return addr + delta;
35 }
36
37 #include "genxml/gen_macros.h"
38 #include "genxml/genX_pack.h"
39
40 #include "isl_priv.h"
41 #include "isl_genX_helpers.h"
42
43 #if GFX_VER >= 8
44 static const uint8_t isl_encode_tiling[] = {
45 [ISL_TILING_LINEAR] = LINEAR,
46 [ISL_TILING_X] = XMAJOR,
47 #if GFX_VER >= 20
48 [ISL_TILING_4] = TILE4,
49 [ISL_TILING_64_XE2] = TILE64,
50 #elif GFX_VERx10 >= 125
51 [ISL_TILING_4] = TILE4,
52 [ISL_TILING_64] = TILE64,
53 #else
54 [ISL_TILING_Y0] = YMAJOR,
55 [ISL_TILING_ICL_Yf] = YMAJOR,
56 [ISL_TILING_ICL_Ys] = YMAJOR,
57 [ISL_TILING_SKL_Yf] = YMAJOR,
58 [ISL_TILING_SKL_Ys] = YMAJOR,
59 #endif /* GFX_VERx10 < 125 */
60 #if GFX_VER <= 11
61 [ISL_TILING_W] = WMAJOR,
62 #endif
63 };
64 #endif
65
66 #if GFX_VER >= 9 && GFX_VERx10 <= 120
67 static const uint8_t isl_tiling_encode_trmode[] = {
68 [ISL_TILING_Y0] = NONE,
69 [ISL_TILING_SKL_Yf] = TILEYF,
70 [ISL_TILING_SKL_Ys] = TILEYS,
71 [ISL_TILING_ICL_Yf] = TILEYF,
72 [ISL_TILING_ICL_Ys] = TILEYS,
73 };
74 #endif
75
76 #if GFX_VER >= 7
77 static const uint32_t isl_encode_multisample_layout[] = {
78 [ISL_MSAA_LAYOUT_NONE] = MSFMT_MSS,
79 [ISL_MSAA_LAYOUT_INTERLEAVED] = MSFMT_DEPTH_STENCIL,
80 [ISL_MSAA_LAYOUT_ARRAY] = MSFMT_MSS,
81 };
82 #endif
83
84 #if GFX_VER >= 20
85 static const uint32_t isl_encode_aux_mode[] = {
86 [ISL_AUX_USAGE_NONE] = AUX_NONE,
87 [ISL_AUX_USAGE_MC] = AUX_NONE,
88 [ISL_AUX_USAGE_MCS_CCS] = AUX_MCS,
89 };
90 #elif GFX_VER >= 12
91 static const uint32_t isl_encode_aux_mode[] = {
92 [ISL_AUX_USAGE_NONE] = AUX_NONE,
93 [ISL_AUX_USAGE_MC] = AUX_NONE,
94 [ISL_AUX_USAGE_MCS] = AUX_CCS_E,
95 [ISL_AUX_USAGE_FCV_CCS_E] = AUX_CCS_E,
96 [ISL_AUX_USAGE_CCS_E] = AUX_CCS_E,
97 [ISL_AUX_USAGE_HIZ_CCS_WT] = AUX_CCS_E,
98 [ISL_AUX_USAGE_MCS_CCS] = AUX_MCS_LCE,
99 [ISL_AUX_USAGE_STC_CCS] = AUX_CCS_E,
100 };
101 #elif GFX_VER >= 9
102 static const uint32_t isl_encode_aux_mode[] = {
103 [ISL_AUX_USAGE_NONE] = AUX_NONE,
104 [ISL_AUX_USAGE_HIZ] = AUX_HIZ,
105 [ISL_AUX_USAGE_MCS] = AUX_CCS_D,
106 [ISL_AUX_USAGE_CCS_D] = AUX_CCS_D,
107 [ISL_AUX_USAGE_CCS_E] = AUX_CCS_E,
108 };
109 #elif GFX_VER >= 8
110 static const uint32_t isl_encode_aux_mode[] = {
111 [ISL_AUX_USAGE_NONE] = AUX_NONE,
112 [ISL_AUX_USAGE_HIZ] = AUX_HIZ,
113 [ISL_AUX_USAGE_MCS] = AUX_MCS,
114 [ISL_AUX_USAGE_CCS_D] = AUX_MCS,
115 };
116 #endif
117
118 static uint8_t
get_surftype(enum isl_surf_dim dim,isl_surf_usage_flags_t usage)119 get_surftype(enum isl_surf_dim dim, isl_surf_usage_flags_t usage)
120 {
121 switch (dim) {
122 default:
123 unreachable("bad isl_surf_dim");
124 case ISL_SURF_DIM_1D:
125 assert(!(usage & ISL_SURF_USAGE_CUBE_BIT));
126 return SURFTYPE_1D;
127 case ISL_SURF_DIM_2D:
128 if ((usage & ISL_SURF_USAGE_CUBE_BIT) &&
129 (usage & ISL_SURF_USAGE_TEXTURE_BIT)) {
130 /* We need SURFTYPE_CUBE to make cube sampling work */
131 return SURFTYPE_CUBE;
132 } else {
133 /* Everything else (render and storage) treat cubes as plain
134 * 2D array textures
135 */
136 return SURFTYPE_2D;
137 }
138 case ISL_SURF_DIM_3D:
139 assert(!(usage & ISL_SURF_USAGE_CUBE_BIT));
140 return SURFTYPE_3D;
141 }
142 }
143
144 #if GFX_VERx10 >= 125
145 static uint8_t
get_media_compression_format(enum isl_format format,enum isl_format lowered_format)146 get_media_compression_format(enum isl_format format,
147 enum isl_format lowered_format)
148 {
149 const uint32_t plane_bpb = isl_format_get_layout(lowered_format)->bpb;
150
151 /* From Bspec 43868, Enumeration_MediaCompressionFormat:
152 *
153 * Luma P010 has MSB of 0 while chroma P010 has MSB of 1.
154 * Luma P016 has MSB of 0 while chroma P016 has MSB of 1.
155 * Luma NV12 has MSB of 0 while chroma NV12 has MSB of 1.
156 */
157 switch (format) {
158 case ISL_FORMAT_PLANAR_420_8: /* NV12 */
159 assert(plane_bpb == 8 || plane_bpb == 16);
160 assert((isl_format_get_aux_map_encoding(format) & 0xf0) == 0);
161
162 /* drm_fourcc.h defines the chroma plane of NV12 as 16-bpb */
163 return (plane_bpb == 16) << 4 | isl_format_get_aux_map_encoding(format);
164 case ISL_FORMAT_PLANAR_420_10:
165 case ISL_FORMAT_PLANAR_420_12:
166 case ISL_FORMAT_PLANAR_420_16:
167 assert(plane_bpb == 16 || plane_bpb == 32);
168 assert((isl_format_get_aux_map_encoding(format) & 0xf0) == 0);
169
170 /* drm_fourcc.h defines the chroma plane of P01X as 32-bpb */
171 return (plane_bpb == 32) << 4 | isl_format_get_aux_map_encoding(format);
172 default:
173 return isl_format_get_aux_map_encoding(format);
174 }
175 }
176 #endif
177
178 void
isl_genX(surf_fill_state_s)179 isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
180 const struct isl_surf_fill_state_info *restrict info)
181 {
182 #ifndef NDEBUG
183 isl_surf_usage_flags_t _base_usage =
184 info->view->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT |
185 ISL_SURF_USAGE_TEXTURE_BIT |
186 ISL_SURF_USAGE_STORAGE_BIT);
187 /* They may only specify one of the above bits at a time */
188 assert(__builtin_popcount(_base_usage) == 1);
189 /* The only other allowed bit is ISL_SURF_USAGE_CUBE_BIT */
190 assert((info->view->usage & ~ISL_SURF_USAGE_CUBE_BIT) == _base_usage);
191 #endif
192
193 if (info->surf->dim == ISL_SURF_DIM_3D) {
194 assert(info->view->base_array_layer + info->view->array_len <=
195 info->surf->logical_level0_px.depth);
196 } else {
197 assert(info->view->base_array_layer + info->view->array_len <=
198 info->surf->logical_level0_px.array_len);
199 }
200
201 struct GENX(RENDER_SURFACE_STATE) s = { 0 };
202
203 s.SurfaceType = get_surftype(info->surf->dim, info->view->usage);
204
205 if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT)
206 assert(isl_format_supports_rendering(dev->info, info->view->format));
207 else if (info->view->usage & ISL_SURF_USAGE_TEXTURE_BIT)
208 assert(isl_format_supports_sampling(dev->info, info->view->format));
209
210 /* From the Sky Lake PRM Vol. 2d, RENDER_SURFACE_STATE::SurfaceFormat
211 *
212 * This field cannot be a compressed (BC*, DXT*, FXT*, ETC*, EAC*)
213 * format if the Surface Type is SURFTYPE_1D
214 */
215 if (info->surf->dim == ISL_SURF_DIM_1D)
216 assert(!isl_format_is_compressed(info->view->format));
217
218 if (isl_format_is_compressed(info->surf->format)) {
219 /* You're not allowed to make a view of a compressed format with any
220 * format other than the surface format. None of the userspace APIs
221 * allow for this directly and doing so would mess up a number of
222 * surface parameters such as Width, Height, and alignments. Ideally,
223 * we'd like to assert that the two formats match. However, we have an
224 * S3TC workaround that requires us to do reinterpretation. So assert
225 * that they're at least the same bpb and block size.
226 */
227 ASSERTED const struct isl_format_layout *surf_fmtl =
228 isl_format_get_layout(info->surf->format);
229 ASSERTED const struct isl_format_layout *view_fmtl =
230 isl_format_get_layout(info->view->format);
231
232 assert(surf_fmtl->bpb == view_fmtl->bpb);
233
234 /* We could be attempting to upload blocks of compressed data via an
235 * uncompressed view, blocksize will not match there.
236 */
237 if (isl_format_is_compressed(info->view->format)) {
238 assert(surf_fmtl->bw == view_fmtl->bw);
239 assert(surf_fmtl->bh == view_fmtl->bh);
240 }
241 }
242
243 s.SurfaceFormat = info->view->format;
244
245 #if GFX_VER >= 12
246 /* The BSpec description of this field says:
247 *
248 * "This bit field, when set, indicates if the resource is created as
249 * Depth/Stencil resource."
250 *
251 * "SW must set this bit for any resource that was created with
252 * Depth/Stencil resource flag. Setting this bit allows HW to properly
253 * interpret the data-layout for various cases. For any resource that's
254 * created without Depth/Stencil resource flag, it must be reset."
255 *
256 * Even though the docs for this bit seem to imply that it's required for
257 * anything which might have been used for depth/stencil, empirical
258 * evidence suggests that it only affects CCS compression usage. There are
259 * a few things which back this up:
260 *
261 * 1. The docs are also pretty clear that this bit was added as part
262 * of enabling Gfx12 depth/stencil lossless compression.
263 *
264 * 2. The only new difference between depth/stencil and color images on
265 * Gfx12 (where the bit was added) is how they treat CCS compression.
266 * All other differences such as alignment requirements and MSAA layout
267 * are already covered by other bits.
268 *
269 * Under these assumptions, it makes sense for ISL to model this bit as
270 * being an extension of AuxiliarySurfaceMode where STC_CCS and HIZ_CCS_WT
271 * are indicated by AuxiliarySurfaceMode == CCS_E and DepthStencilResource
272 * == true.
273 */
274 s.DepthStencilResource = info->aux_usage == ISL_AUX_USAGE_HIZ_CCS_WT ||
275 info->aux_usage == ISL_AUX_USAGE_STC_CCS;
276 #endif
277
278 #if GFX_VER <= 5
279 s.ColorBufferComponentWriteDisables = info->write_disables;
280 s.ColorBlendEnable = info->blend_enable;
281 #else
282 assert(info->write_disables == 0);
283 #endif
284
285 #if GFX_VERx10 == 75
286 s.IntegerSurfaceFormat =
287 isl_format_has_int_channel((enum isl_format) s.SurfaceFormat);
288 #endif
289
290 assert(info->surf->logical_level0_px.width > 0 &&
291 info->surf->logical_level0_px.height > 0);
292
293 s.Width = info->surf->logical_level0_px.width - 1;
294 s.Height = info->surf->logical_level0_px.height - 1;
295
296 /* In the gfx6 PRM Volume 1 Part 1: Graphics Core, Section 7.18.3.7.1
297 * (Surface Arrays For all surfaces other than separate stencil buffer):
298 *
299 * "[DevSNB] Errata: Sampler MSAA Qpitch will be 4 greater than the value
300 * calculated in the equation above , for every other odd Surface Height
301 * starting from 1 i.e. 1,5,9,13"
302 *
303 * Since this Qpitch errata only impacts the sampler, we have to adjust the
304 * input for the rendering surface to achieve the same qpitch. For the
305 * affected heights, we increment the height by 1 for the rendering
306 * surface.
307 */
308 if (GFX_VER == 6 && (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) &&
309 info->surf->samples > 1 &&
310 (info->surf->logical_level0_px.height % 4) == 1)
311 s.Height++;
312
313 switch (s.SurfaceType) {
314 case SURFTYPE_1D:
315 case SURFTYPE_2D:
316 /* From the Ivy Bridge PRM >> RENDER_SURFACE_STATE::MinimumArrayElement:
317 *
318 * "If Number of Multisamples is not MULTISAMPLECOUNT_1, this field
319 * must be set to zero if this surface is used with sampling engine
320 * messages."
321 *
322 * This restriction appears to exist only on Ivy Bridge.
323 */
324 if (GFX_VERx10 == 70 && !ISL_DEV_IS_BAYTRAIL(dev) &&
325 (info->view->usage & ISL_SURF_USAGE_TEXTURE_BIT) &&
326 info->surf->samples > 1)
327 assert(info->view->base_array_layer == 0);
328
329 s.MinimumArrayElement = info->view->base_array_layer;
330
331 /* From the Broadwell PRM >> RENDER_SURFACE_STATE::Depth:
332 *
333 * For SURFTYPE_1D, 2D, and CUBE: The range of this field is reduced
334 * by one for each increase from zero of Minimum Array Element. For
335 * example, if Minimum Array Element is set to 1024 on a 2D surface,
336 * the range of this field is reduced to [0,1023].
337 *
338 * In other words, 'Depth' is the number of array layers.
339 */
340 s.Depth = info->view->array_len - 1;
341
342 /* From the Broadwell PRM >> RENDER_SURFACE_STATE::RenderTargetViewExtent:
343 *
344 * For Render Target and Typed Dataport 1D and 2D Surfaces:
345 * This field must be set to the same value as the Depth field.
346 */
347 if (info->view->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT |
348 ISL_SURF_USAGE_STORAGE_BIT))
349 s.RenderTargetViewExtent = s.Depth;
350 break;
351 case SURFTYPE_CUBE:
352 s.MinimumArrayElement = info->view->base_array_layer;
353 /* Same as SURFTYPE_2D, but divided by 6 */
354 s.Depth = info->view->array_len / 6 - 1;
355 if (info->view->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT |
356 ISL_SURF_USAGE_STORAGE_BIT))
357 s.RenderTargetViewExtent = s.Depth;
358 break;
359 case SURFTYPE_3D:
360 /* From the Broadwell PRM >> RENDER_SURFACE_STATE::Depth:
361 *
362 * If the volume texture is MIP-mapped, this field specifies the
363 * depth of the base MIP level.
364 */
365 s.Depth = info->surf->logical_level0_px.depth - 1;
366
367 /* From the Broadwell PRM >> RENDER_SURFACE_STATE::RenderTargetViewExtent:
368 *
369 * For Render Target and Typed Dataport 3D Surfaces: This field
370 * indicates the extent of the accessible 'R' coordinates minus 1 on
371 * the LOD currently being rendered to.
372 *
373 * The docs specify that this only matters for render targets and
374 * surfaces used with typed dataport messages. Prior to Ivy Bridge, the
375 * Depth field has more bits than RenderTargetViewExtent so we can have
376 * textures with more levels than we can render to. In order to prevent
377 * assert-failures in the packing function below, we only set the field
378 * when it's actually going to be used by the hardware.
379 *
380 * The MinimumArrayElement field is ignored by all hardware
381 * prior to Sky Lake when texturing, and drivers are responsible
382 * for validating the correctness of this parameter.
383 * KHR_gl_texture_3D_image requires this functionality.
384 */
385 s.MinimumArrayElement = info->view->base_array_layer;
386 s.RenderTargetViewExtent = info->view->array_len - 1;
387 break;
388 default:
389 unreachable("bad SurfaceType");
390 }
391
392 #if GFX_VER >= 7
393 if (INTEL_NEEDS_WA_1806565034) {
394 /* Wa_1806565034:
395 *
396 * "Only set SurfaceArray if arrayed surface is > 1."
397 *
398 * Since this is a performance workaround, we only enable it when robust
399 * image access is disabled. Otherwise layered robust access is not
400 * specification compliant.
401 */
402 s.SurfaceArray = info->surf->dim != ISL_SURF_DIM_3D &&
403 (info->robust_image_access || info->view->array_len > 1);
404 } else {
405 s.SurfaceArray = info->surf->dim != ISL_SURF_DIM_3D;
406 }
407 #endif
408
409 if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) {
410 /* For render target surfaces, the hardware interprets field
411 * MIPCount/LOD as LOD. The Broadwell PRM says:
412 *
413 * MIPCountLOD defines the LOD that will be rendered into.
414 * SurfaceMinLOD is ignored.
415 */
416 s.MIPCountLOD = info->view->base_level;
417 s.SurfaceMinLOD = 0;
418 } else {
419 /* For non render target surfaces, the hardware interprets field
420 * MIPCount/LOD as MIPCount. The range of levels accessible by the
421 * sampler engine is [SurfaceMinLOD, SurfaceMinLOD + MIPCountLOD].
422 */
423 s.SurfaceMinLOD = info->view->base_level;
424 s.MIPCountLOD = MAX(info->view->levels, 1) - 1;
425 }
426
427 #if GFX_VER >= 9
428 s.MipTailStartLOD = info->surf->miptail_start_level;
429 #endif
430
431 #if GFX_VERx10 >= 125
432 /* Setting L1 caching policy to Write-back mode. */
433 s.L1CacheControl = L1CC_WB;
434 #endif
435
436 #if GFX_VER >= 6
437 const struct isl_extent3d image_align =
438 isl_get_image_alignment(info->surf);
439 s.SurfaceVerticalAlignment = isl_encode_valign(image_align.height);
440 #if GFX_VER >= 7
441 s.SurfaceHorizontalAlignment = isl_encode_halign(image_align.width);
442 #endif
443 #endif
444
445 if (info->surf->dim_layout == ISL_DIM_LAYOUT_GFX9_1D) {
446 /* For gfx9 1-D textures, surface pitch is ignored */
447 s.SurfacePitch = 0;
448 } else {
449 s.SurfacePitch = info->surf->row_pitch_B - 1;
450 }
451
452 #if GFX_VER >= 8
453 s.SurfaceQPitch = isl_get_qpitch(info->surf) >> 2;
454 #elif GFX_VER == 7
455 s.SurfaceArraySpacing = info->surf->array_pitch_span ==
456 ISL_ARRAY_PITCH_SPAN_COMPACT;
457 #endif
458
459 #if GFX_VER >= 9 && GFX_VERx10 <= 120
460 assert(GFX_VER < 12 || info->surf->tiling != ISL_TILING_W);
461
462 /* From the SKL+ PRMs, RENDER_SURFACE_STATE:TileMode,
463 *
464 * If Surface Format is ASTC*, this field must be TILEMODE_YMAJOR.
465 */
466 if (isl_format_get_layout(info->view->format)->txc == ISL_TXC_ASTC)
467 assert(isl_tiling_is_any_y(info->surf->tiling));
468
469 s.TileMode = isl_encode_tiling[info->surf->tiling];
470 if (isl_tiling_is_std_y(info->surf->tiling))
471 s.TiledResourceMode = isl_tiling_encode_trmode[info->surf->tiling];
472 #elif GFX_VER >= 8
473 assert(isl_format_get_layout(info->view->format)->txc != ISL_TXC_ASTC);
474 assert(!isl_tiling_is_std_y(info->surf->tiling));
475 s.TileMode = isl_encode_tiling[info->surf->tiling];
476 #else
477 s.TiledSurface = info->surf->tiling != ISL_TILING_LINEAR,
478 s.TileWalk = info->surf->tiling == ISL_TILING_Y0 ? TILEWALK_YMAJOR :
479 TILEWALK_XMAJOR,
480 #endif
481
482 #if GFX_VER >= 8
483 s.RenderCacheReadWriteMode = WriteOnlyCache;
484 #else
485 s.RenderCacheReadWriteMode = 0;
486 #endif
487
488 #if GFX_VER >= 11 && GFX_VERx10 < 125
489 /* We've seen dEQP failures when enabling this bit with UINT formats,
490 * which particularly affects blorp_copy() operations. It shouldn't
491 * have any effect on UINT textures anyway, so disable it for them.
492 */
493 s.EnableUnormPathInColorPipe =
494 !isl_format_has_int_channel(info->view->format);
495 #endif
496
497 s.CubeFaceEnablePositiveZ = 1;
498 s.CubeFaceEnableNegativeZ = 1;
499 s.CubeFaceEnablePositiveY = 1;
500 s.CubeFaceEnableNegativeY = 1;
501 s.CubeFaceEnablePositiveX = 1;
502 s.CubeFaceEnableNegativeX = 1;
503
504 #if GFX_VER >= 6
505 /* From the Broadwell PRM for "Number of Multisamples":
506 *
507 * "If this field is any value other than MULTISAMPLECOUNT_1, Surface
508 * Min LOD, Mip Count / LOD, and Resource Min LOD must be set to zero."
509 *
510 * This is fine because no 3D API allows multisampling and mipmapping at
511 * the same time.
512 */
513 if (info->surf->samples > 1) {
514 assert(info->view->min_lod_clamp == 0);
515 assert(info->view->base_level == 0);
516 assert(info->view->levels == 1);
517 }
518 s.NumberofMultisamples = ffs(info->surf->samples) - 1;
519 #if GFX_VER >= 7
520 s.MultisampledSurfaceStorageFormat =
521 isl_encode_multisample_layout[info->surf->msaa_layout];
522 #endif
523 #endif
524
525 #if GFX_VER >= 7
526 s.ResourceMinLOD = info->view->min_lod_clamp;
527
528 #if GFX_VERx10 >= 200
529 s.EnableSamplerRoutetoLSC = isl_format_support_sampler_route_to_lsc(info->view->format);
530 s.EnableSamplerRoutetoLSC &= (s.SurfaceType == SURFTYPE_2D);
531
532 /* Wa_14018471104:
533 * For APIs that use ResourceMinLod, do the following: (remains same as before)
534 * 1. If ResourceMinLod == 0.0 then **Enable Sampler Route to LSC**
535 * in RENDER SURFACE STATE to 1 else to 0
536 */
537 #if INTEL_NEEDS_WA_14018471104
538 s.EnableSamplerRoutetoLSC &= info->view->min_lod_clamp == 0;
539 #endif
540 #endif /* if GFX_VERx10 >= 200 */
541
542 #else
543 assert(info->view->min_lod_clamp == 0);
544 #endif
545
546 #if (GFX_VERx10 >= 75)
547 if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT)
548 assert(isl_swizzle_supports_rendering(dev->info, info->view->swizzle));
549
550 s.ShaderChannelSelectRed = (enum GENX(ShaderChannelSelect)) info->view->swizzle.r;
551 s.ShaderChannelSelectGreen = (enum GENX(ShaderChannelSelect)) info->view->swizzle.g;
552 s.ShaderChannelSelectBlue = (enum GENX(ShaderChannelSelect)) info->view->swizzle.b;
553 s.ShaderChannelSelectAlpha = (enum GENX(ShaderChannelSelect)) info->view->swizzle.a;
554 #else
555 assert(isl_swizzle_is_identity(info->view->swizzle));
556 #endif
557
558 s.SurfaceBaseAddress = info->address;
559
560 #if GFX_VER >= 6
561 s.MOCS = info->mocs;
562 #endif
563
564 #if GFX_VERx10 >= 45
565 if (info->x_offset_sa != 0 || info->y_offset_sa != 0) {
566 /* There are fairly strict rules about when the offsets can be used.
567 * These are mostly taken from the Sky Lake PRM documentation for
568 * RENDER_SURFACE_STATE.
569 */
570 assert(info->surf->tiling != ISL_TILING_LINEAR);
571 assert(info->surf->dim == ISL_SURF_DIM_2D);
572 assert(isl_is_pow2(isl_format_get_layout(info->view->format)->bpb));
573 assert(info->surf->levels == 1);
574 assert(info->surf->logical_level0_px.array_len == 1);
575 assert(info->aux_usage == ISL_AUX_USAGE_NONE);
576
577 if (GFX_VER >= 8) {
578 /* Broadwell added more rules. */
579 assert(info->surf->samples == 1);
580 if (isl_format_get_layout(info->view->format)->bpb == 8)
581 assert(info->x_offset_sa % 16 == 0);
582 if (isl_format_get_layout(info->view->format)->bpb == 16)
583 assert(info->x_offset_sa % 8 == 0);
584 }
585
586 #if GFX_VER >= 7
587 s.SurfaceArray = false;
588 #endif
589 }
590
591 const unsigned x_div = 4;
592 const unsigned y_div = GFX_VER >= 8 ? 4 : 2;
593 assert(info->x_offset_sa % x_div == 0);
594 assert(info->y_offset_sa % y_div == 0);
595 s.XOffset = info->x_offset_sa / x_div;
596 s.YOffset = info->y_offset_sa / y_div;
597 #else
598 assert(info->x_offset_sa == 0);
599 assert(info->y_offset_sa == 0);
600 #endif
601
602 #if GFX_VER >= 7
603 if (info->aux_usage != ISL_AUX_USAGE_NONE) {
604 /* Check valid aux usages per-gen */
605 if (GFX_VER >= 12) {
606 assert(info->aux_usage == ISL_AUX_USAGE_MCS ||
607 info->aux_usage == ISL_AUX_USAGE_CCS_E ||
608 info->aux_usage == ISL_AUX_USAGE_FCV_CCS_E ||
609 info->aux_usage == ISL_AUX_USAGE_MC ||
610 info->aux_usage == ISL_AUX_USAGE_HIZ_CCS_WT ||
611 info->aux_usage == ISL_AUX_USAGE_MCS_CCS ||
612 info->aux_usage == ISL_AUX_USAGE_STC_CCS);
613 } else if (GFX_VER >= 9) {
614 assert(info->aux_usage == ISL_AUX_USAGE_HIZ ||
615 info->aux_usage == ISL_AUX_USAGE_MCS ||
616 info->aux_usage == ISL_AUX_USAGE_CCS_D ||
617 info->aux_usage == ISL_AUX_USAGE_CCS_E);
618 } else if (GFX_VER >= 8) {
619 assert(info->aux_usage == ISL_AUX_USAGE_HIZ ||
620 info->aux_usage == ISL_AUX_USAGE_MCS ||
621 info->aux_usage == ISL_AUX_USAGE_CCS_D);
622 } else if (GFX_VER >= 7) {
623 assert(info->aux_usage == ISL_AUX_USAGE_MCS ||
624 info->aux_usage == ISL_AUX_USAGE_CCS_D);
625 }
626
627 /* The docs don't appear to say anything whatsoever about compression
628 * and the data port. Testing seems to indicate that the data port
629 * completely ignores the AuxiliarySurfaceMode field.
630 *
631 * On gfx12 HDC supports compression.
632 */
633 if (GFX_VER < 12)
634 assert(!(info->view->usage & ISL_SURF_USAGE_STORAGE_BIT));
635
636 if (isl_surf_usage_is_depth(info->surf->usage))
637 assert(isl_aux_usage_has_hiz(info->aux_usage));
638
639 if (isl_surf_usage_is_stencil(info->surf->usage))
640 assert(info->aux_usage == ISL_AUX_USAGE_STC_CCS);
641
642 if (isl_aux_usage_has_hiz(info->aux_usage)) {
643 /* For Gfx8-10, there are some restrictions around sampling from HiZ.
644 * The Skylake PRM docs for RENDER_SURFACE_STATE::AuxiliarySurfaceMode
645 * say:
646 *
647 * "If this field is set to AUX_HIZ, Number of Multisamples must
648 * be MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D."
649 *
650 * On Gfx12, the docs are a bit less obvious but the restriction is
651 * the same. The limitation isn't called out explicitly but the docs
652 * for the CCS_E value of RENDER_SURFACE_STATE::AuxiliarySurfaceMode
653 * say:
654 *
655 * "If Number of multisamples > 1, programming this value means
656 * MSAA compression is enabled for that surface. Auxiliary surface
657 * is MSC with tile y."
658 *
659 * Since this interpretation ignores whether the surface is
660 * depth/stencil or not and since multisampled depth buffers use
661 * ISL_MSAA_LAYOUT_INTERLEAVED which is incompatible with MCS
662 * compression, this means that we can't even specify MSAA depth CCS
663 * in RENDER_SURFACE_STATE::AuxiliarySurfaceMode.
664 */
665 assert(info->surf->samples == 1);
666
667 /* The dimension must not be 3D */
668 assert(info->surf->dim != ISL_SURF_DIM_3D);
669
670 /* The format must be one of the following: */
671 switch (info->view->format) {
672 case ISL_FORMAT_R32_FLOAT:
673 case ISL_FORMAT_R24_UNORM_X8_TYPELESS:
674 case ISL_FORMAT_R16_UNORM:
675 break;
676 default:
677 assert(!"Incompatible HiZ Sampling format");
678 break;
679 }
680 }
681
682 #if GFX_VERx10 >= 125
683 if (info->aux_usage == ISL_AUX_USAGE_MC) {
684 s.CompressionFormat =
685 get_media_compression_format(info->mc_format, info->surf->format);
686 } else {
687 s.CompressionFormat =
688 isl_get_render_compression_format(info->surf->format);
689 }
690 #endif
691 #if GFX_VER == 12
692 s.MemoryCompressionEnable = info->aux_usage == ISL_AUX_USAGE_MC;
693
694 /* The Tiger Lake PRM for RENDER_SURFACE_STATE::DecompressInL3 says:
695 *
696 * When this field is set to 1h, the associated compressible surface,
697 * when accessed by sampler and data-port, will be uncompressed in
698 * L3. If the surface is not compressible, this bit field is ignored.
699 *
700 * The sampler's decompressor seems to lack support for some types of
701 * format re-interpretation. Use the more capable decompressor for these
702 * cases.
703 */
704 s.DecompressInL3 =
705 !isl_formats_have_same_bits_per_channel(info->surf->format,
706 info->view->format);
707 #endif
708 #if GFX_VER >= 9
709 /* Some CCS aux usages have format restrictions. The Skylake PRM doc for
710 * RENDER_SURFACE_STATE::AuxiliarySurfaceMode says:
711 *
712 * If Number of Multisamples is MULTISAMPLECOUNT_1, AUX_CCS_E setting
713 * is only allowed if Surface Format is supported for Render Target
714 * Compression. This setting enables render target compression.
715 *
716 * If CCS_E is in use, the format must support it.
717 */
718 if (isl_aux_usage_has_ccs_e(info->aux_usage))
719 assert(isl_format_supports_ccs_e(dev->info, info->view->format));
720
721 /* It also says:
722 *
723 * If Number of Multisamples is MULTISAMPLECOUNT_1, AUX_CCS_D setting
724 * is only allowed if Surface Format supported for Fast Clear. In
725 * addition, if the surface is bound to the sampling engine, Surface
726 * Format must be supported for Render Target Compression for
727 * surfaces bound to the sampling engine. For render target surfaces,
728 * this setting disables render target compression. For sampling
729 * engine surfaces, this mode behaves the same as AUX_CCS_E.
730 *
731 * If CCS_D is in use while rendering, the format must support it. If
732 * it's in use while sampling, the format must support CCS_E.
733 */
734 if (info->aux_usage == ISL_AUX_USAGE_CCS_D) {
735 if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) {
736 assert(isl_format_supports_ccs_d(dev->info, info->view->format));
737 } else {
738 assert(info->view->usage & ISL_SURF_USAGE_TEXTURE_BIT);
739 assert(isl_format_supports_ccs_e(dev->info, info->view->format));
740 }
741 }
742 #endif
743 #if GFX_VER >= 8
744 s.AuxiliarySurfaceMode = isl_encode_aux_mode[info->aux_usage];
745 #else
746 s.MCSEnable = true;
747 #endif
748 }
749
750 /* The auxiliary buffer info is filled when it's usable by the HW.
751 *
752 * Starting with Gfx12, the only form of compression that can be used
753 * with RENDER_SURFACE_STATE which requires an aux surface is MCS.
754 * HiZ still requires a surface but the HiZ surface can only be
755 * accessed through 3DSTATE_HIER_DEPTH_BUFFER.
756 *
757 * On all earlier hardware, an aux surface is required for all forms
758 * of compression.
759 */
760 if ((GFX_VER < 12 && info->aux_usage != ISL_AUX_USAGE_NONE) ||
761 (GFX_VER >= 12 && isl_aux_usage_has_mcs(info->aux_usage))) {
762
763 assert(info->aux_surf != NULL);
764
765 struct isl_tile_info tile_info;
766 isl_surf_get_tile_info(info->aux_surf, &tile_info);
767 uint32_t pitch_in_tiles =
768 info->aux_surf->row_pitch_B / tile_info.phys_extent_B.width;
769
770 s.AuxiliarySurfaceBaseAddress = info->aux_address;
771 s.AuxiliarySurfacePitch = pitch_in_tiles - 1;
772
773 #if GFX_VER >= 8
774 /* Auxiliary surfaces in ISL have compressed formats but the hardware
775 * doesn't expect our definition of the compression, it expects qpitch
776 * in units of samples on the main surface.
777 */
778 s.AuxiliarySurfaceQPitch =
779 isl_surf_get_array_pitch_sa_rows(info->aux_surf) >> 2;
780 #endif
781 }
782 #endif
783
784 #if GFX_VER >= 8 && GFX_VER < 11
785 /* From the CHV PRM, Volume 2d, page 321 (RENDER_SURFACE_STATE dword 0
786 * bit 9 "Sampler L2 Bypass Mode Disable" Programming Notes):
787 *
788 * This bit must be set for the following surface types: BC2_UNORM
789 * BC3_UNORM BC5_UNORM BC5_SNORM BC7_UNORM
790 */
791 if (GFX_VER >= 9 || dev->info->platform == INTEL_PLATFORM_CHV) {
792 switch (info->view->format) {
793 case ISL_FORMAT_BC2_UNORM:
794 case ISL_FORMAT_BC3_UNORM:
795 case ISL_FORMAT_BC5_UNORM:
796 case ISL_FORMAT_BC5_SNORM:
797 case ISL_FORMAT_BC7_UNORM:
798 s.SamplerL2BypassModeDisable = true;
799 break;
800 default:
801 /* From the SKL PRM, Programming Note under Sampler Output Channel
802 * Mapping:
803 *
804 * If a surface has an associated HiZ Auxiliary surface, the
805 * Sampler L2 Bypass Mode Disable field in the RENDER_SURFACE_STATE
806 * must be set.
807 */
808 if (GFX_VER >= 9 && info->aux_usage == ISL_AUX_USAGE_HIZ)
809 s.SamplerL2BypassModeDisable = true;
810 break;
811 }
812 }
813 #endif
814
815 if (isl_aux_usage_has_fast_clears(info->aux_usage)) {
816 if (info->use_clear_address) {
817 #if GFX_VER > 10 && GFX_VER < 20
818 s.ClearValueAddressEnable = true;
819 s.ClearValueAddress = info->clear_address;
820 #else
821 unreachable("Only Gfx11 and Gfx12 support indirect clear colors");
822 #endif
823 }
824
825 #if GFX_VER == 11
826 /*
827 * From BXML > GT > Shared Functions > vol5c Shared Functions >
828 * [Structure] RENDER_SURFACE_STATE [BDW+] > ClearColorConversionEnable:
829 *
830 * Project: Gfx11
831 *
832 * "Enables Pixel backend hw to convert clear values into native format
833 * and write back to clear address, so that display and sampler can use
834 * the converted value for resolving fast cleared RTs."
835 *
836 * Summary:
837 * Clear color conversion must be enabled if the clear color is stored
838 * indirectly and fast color clears are enabled.
839 */
840 if (info->use_clear_address) {
841 s.ClearColorConversionEnable = true;
842 }
843 #endif
844
845 #if GFX_VER >= 12
846 assert(info->use_clear_address);
847 #elif GFX_VER >= 9
848 if (!info->use_clear_address) {
849 s.RedClearColor = info->clear_color.u32[0];
850 s.GreenClearColor = info->clear_color.u32[1];
851 s.BlueClearColor = info->clear_color.u32[2];
852 s.AlphaClearColor = info->clear_color.u32[3];
853 }
854 #elif GFX_VER >= 7
855 /* Prior to Sky Lake, we only have one bit for the clear color which
856 * gives us 0 or 1 in whatever the surface's format happens to be.
857 */
858 if (isl_format_has_int_channel(info->view->format)) {
859 for (unsigned i = 0; i < 4; i++) {
860 assert(info->clear_color.u32[i] == 0 ||
861 info->clear_color.u32[i] == 1);
862 }
863 s.RedClearColor = info->clear_color.u32[0] != 0;
864 s.GreenClearColor = info->clear_color.u32[1] != 0;
865 s.BlueClearColor = info->clear_color.u32[2] != 0;
866 s.AlphaClearColor = info->clear_color.u32[3] != 0;
867 } else {
868 for (unsigned i = 0; i < 4; i++) {
869 assert(info->clear_color.f32[i] == 0.0f ||
870 info->clear_color.f32[i] == 1.0f);
871 }
872 s.RedClearColor = info->clear_color.f32[0] != 0.0f;
873 s.GreenClearColor = info->clear_color.f32[1] != 0.0f;
874 s.BlueClearColor = info->clear_color.f32[2] != 0.0f;
875 s.AlphaClearColor = info->clear_color.f32[3] != 0.0f;
876 }
877 #endif
878 }
879
880 GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s);
881 }
882
883 void
isl_genX(buffer_fill_state_s)884 isl_genX(buffer_fill_state_s)(const struct isl_device *dev, void *state,
885 const struct isl_buffer_fill_state_info *restrict info)
886 {
887 uint64_t buffer_size = info->size_B;
888
889 /* Uniform and Storage buffers need to have surface size not less that the
890 * aligned 32-bit size of the buffer. To calculate the array length on
891 * unsized arrays in StorageBuffer the last 2 bits store the padding size
892 * added to the surface, so we can calculate latter the original buffer
893 * size to know the number of elements.
894 *
895 * surface_size = isl_align(buffer_size, 4) +
896 * (isl_align(buffer_size) - buffer_size)
897 *
898 * buffer_size = (surface_size & ~3) - (surface_size & 3)
899 */
900 if ((info->format == ISL_FORMAT_RAW ||
901 info->stride_B < isl_format_get_layout(info->format)->bpb / 8) &&
902 !info->is_scratch) {
903 assert(info->stride_B == 1);
904 uint64_t aligned_size = isl_align(buffer_size, 4);
905 buffer_size = aligned_size + (aligned_size - buffer_size);
906 }
907
908 uint32_t num_elements = buffer_size / info->stride_B;
909
910 assert(num_elements > 0);
911 if (info->format == ISL_FORMAT_RAW) {
912 assert(num_elements <= dev->max_buffer_size);
913 } else {
914 /* From the IVB PRM, SURFACE_STATE::Height,
915 *
916 * For typed buffer and structured buffer surfaces, the number
917 * of entries in the buffer ranges from 1 to 2^27.
918 */
919 assert(num_elements <= (1ull << 27));
920 }
921
922 struct GENX(RENDER_SURFACE_STATE) s = { 0, };
923
924 s.SurfaceFormat = info->format;
925
926 s.SurfaceType = SURFTYPE_BUFFER;
927 #if GFX_VERx10 >= 125
928 if (info->is_scratch) {
929 /* From the BSpec:
930 *
931 * "For surfaces of type SURFTYPE_SCRATCH, valid range of pitch is:
932 * [63,262143] -> [64B, 256KB]. Also, for SURFTYPE_SCRATCH, the
933 * pitch must be a multiple of 64bytes."
934 */
935 assert(info->format == ISL_FORMAT_RAW);
936 assert(info->stride_B % 64 == 0);
937 assert(info->stride_B <= 256 * 1024);
938 s.SurfaceType = SURFTYPE_SCRATCH;
939 }
940 #else
941 assert(!info->is_scratch);
942 #endif
943
944 s.SurfacePitch = info->stride_B - 1;
945
946 #if GFX_VER >= 6
947 s.SurfaceVerticalAlignment = isl_encode_valign(4);
948 #if GFX_VERx10 >= 125
949 s.SurfaceHorizontalAlignment = isl_encode_halign(128);
950 #elif GFX_VER >= 7
951 s.SurfaceHorizontalAlignment = isl_encode_halign(4);
952 s.SurfaceArray = false;
953 #endif
954 #endif
955
956 #if GFX_VER >= 9
957 s.Height = ((num_elements - 1) >> 7) & 0x3fff;
958 s.Width = (num_elements - 1) & 0x7f;
959 s.Depth = ((num_elements - 1) >> 21) & 0x7ff;
960 #elif GFX_VER >= 7
961 s.Height = ((num_elements - 1) >> 7) & 0x3fff;
962 s.Width = (num_elements - 1) & 0x7f;
963 s.Depth = ((num_elements - 1) >> 21) & 0x3ff;
964 #else
965 s.Height = ((num_elements - 1) >> 7) & 0x1fff;
966 s.Width = (num_elements - 1) & 0x7f;
967 s.Depth = ((num_elements - 1) >> 20) & 0x7f;
968 #endif
969
970 #if GFX_VER >= 6
971 s.NumberofMultisamples = MULTISAMPLECOUNT_1;
972 #endif
973
974 #if (GFX_VER >= 8)
975 s.TileMode = LINEAR;
976 #else
977 s.TiledSurface = false;
978 #endif
979
980 #if (GFX_VER >= 8)
981 s.RenderCacheReadWriteMode = WriteOnlyCache;
982 #else
983 s.RenderCacheReadWriteMode = 0;
984 #endif
985
986 #if GFX_VERx10 >= 200
987 s.EnableSamplerRoutetoLSC = isl_format_support_sampler_route_to_lsc(info->format);
988 #endif /* if GFX_VERx10 >= 200 */
989
990 s.SurfaceBaseAddress = info->address;
991 #if GFX_VER >= 6
992 s.MOCS = info->mocs;
993 #endif
994
995 #if GFX_VER >= 9
996 /* Store the buffer size in the upper dword of the AUX surface base
997 * address. Only enabled on Gfx9+ since Gfx8 has an Atom version with only
998 * 32bits of address space.
999 */
1000 if (dev->buffer_length_in_aux_addr)
1001 s.AuxiliarySurfaceBaseAddress = info->size_B << 32;
1002 #else
1003 assert(!dev->buffer_length_in_aux_addr);
1004 #endif
1005
1006 #if GFX_VERx10 >= 125
1007 /* Setting L1 caching policy to Write-back mode. */
1008 s.L1CacheControl = L1CC_WB;
1009 #endif
1010
1011 #if (GFX_VERx10 >= 75)
1012 s.ShaderChannelSelectRed = (enum GENX(ShaderChannelSelect)) info->swizzle.r;
1013 s.ShaderChannelSelectGreen = (enum GENX(ShaderChannelSelect)) info->swizzle.g;
1014 s.ShaderChannelSelectBlue = (enum GENX(ShaderChannelSelect)) info->swizzle.b;
1015 s.ShaderChannelSelectAlpha = (enum GENX(ShaderChannelSelect)) info->swizzle.a;
1016 #endif
1017
1018 GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s);
1019 }
1020
1021 void
isl_genX(null_fill_state_s)1022 isl_genX(null_fill_state_s)(const struct isl_device *dev, void *state,
1023 const struct isl_null_fill_state_info *restrict info)
1024 {
1025 struct GENX(RENDER_SURFACE_STATE) s = {
1026 .SurfaceType = SURFTYPE_NULL,
1027 /* We previously had this format set to B8G8R8A8_UNORM but ran into
1028 * hangs on IVB. R32_UINT seems to work for everybody.
1029 *
1030 * https://gitlab.freedesktop.org/mesa/mesa/-/issues/1872
1031 */
1032 .SurfaceFormat = ISL_FORMAT_R32_UINT,
1033 #if GFX_VER >= 7
1034 .SurfaceArray = info->size.depth > 1,
1035 #endif
1036 #if GFX_VERx10 >= 125
1037 .TileMode = TILE4,
1038 #elif GFX_VER >= 8
1039 .TileMode = YMAJOR,
1040 #else
1041 .TiledSurface = true,
1042 .TileWalk = TILEWALK_YMAJOR,
1043 #endif
1044 #if GFX_VER >= 6
1045 .MOCS = isl_mocs(dev, 0, false),
1046 #endif
1047 #if GFX_VER == 7
1048 /* According to PRMs: "Volume 4 Part 1: Subsystem and Cores – Shared
1049 * Functions"
1050 *
1051 * RENDER_SURFACE_STATE::Surface Vertical Alignment
1052 *
1053 * "This field must be set to VALIGN_4 for all tiled Y Render Target
1054 * surfaces."
1055 *
1056 * Affect IVB, HSW.
1057 */
1058 .SurfaceVerticalAlignment = VALIGN_4,
1059 #endif
1060 .MIPCountLOD = info->levels,
1061 .Width = info->size.width - 1,
1062 .Height = info->size.height - 1,
1063 .Depth = info->size.depth - 1,
1064 .RenderTargetViewExtent = info->size.depth - 1,
1065 #if GFX_VER <= 5
1066 .MinimumArrayElement = info->minimum_array_element,
1067 .ColorBufferComponentWriteDisables = 0xf,
1068 #endif
1069 };
1070 GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s);
1071 }
1072