1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #ifndef ANV_NIR_H
25 #define ANV_NIR_H
26
27 #include "nir/nir.h"
28 #include "anv_private.h"
29
30 #ifdef __cplusplus
31 extern "C" {
32 #endif
33
34 /* This map is represent a mapping where the key is the NIR
35 * nir_intrinsic_resource_intel::block index. It allows mapping bindless UBOs
36 * accesses to descriptor entry.
37 *
38 * This map only temporary lives between the anv_nir_apply_pipeline_layout()
39 * and anv_nir_compute_push_layout() passes.
40 */
41 struct anv_pipeline_push_map {
42 uint32_t block_count;
43 struct anv_pipeline_binding *block_to_descriptor;
44 };
45
46 bool anv_check_for_primitive_replication(struct anv_device *device,
47 VkShaderStageFlags stages,
48 nir_shader **shaders,
49 uint32_t view_mask);
50
51 bool anv_nir_lower_load_patch_vertices_in(nir_shader *shader);
52
53 bool anv_nir_lower_multiview(nir_shader *shader, uint32_t view_mask,
54 bool use_primitive_replication);
55
56 bool anv_nir_lower_ycbcr_textures(nir_shader *shader,
57 const struct anv_pipeline_sets_layout *layout);
58
59 static inline nir_address_format
anv_nir_ssbo_addr_format(const struct anv_physical_device * pdevice,enum brw_robustness_flags robust_flags)60 anv_nir_ssbo_addr_format(const struct anv_physical_device *pdevice,
61 enum brw_robustness_flags robust_flags)
62 {
63 if (robust_flags & BRW_ROBUSTNESS_SSBO)
64 return nir_address_format_64bit_bounded_global;
65 else
66 return nir_address_format_64bit_global_32bit_offset;
67 }
68
69 static inline nir_address_format
anv_nir_ubo_addr_format(const struct anv_physical_device * pdevice,enum brw_robustness_flags robust_flags)70 anv_nir_ubo_addr_format(const struct anv_physical_device *pdevice,
71 enum brw_robustness_flags robust_flags)
72 {
73 if (robust_flags & BRW_ROBUSTNESS_UBO)
74 return nir_address_format_64bit_bounded_global;
75 else
76 return nir_address_format_64bit_global_32bit_offset;
77 }
78
79 bool anv_nir_lower_ubo_loads(nir_shader *shader);
80
81 void anv_nir_apply_pipeline_layout(nir_shader *shader,
82 const struct anv_physical_device *pdevice,
83 enum brw_robustness_flags robust_flags,
84 bool independent_sets,
85 const struct anv_pipeline_sets_layout *layout,
86 struct anv_pipeline_bind_map *map,
87 struct anv_pipeline_push_map *push_map,
88 void *push_map_mem_ctx);
89
90 void anv_nir_compute_push_layout(nir_shader *nir,
91 const struct anv_physical_device *pdevice,
92 enum brw_robustness_flags robust_flags,
93 bool fragment_dynamic,
94 struct brw_stage_prog_data *prog_data,
95 struct anv_pipeline_bind_map *map,
96 const struct anv_pipeline_push_map *push_map,
97 void *mem_ctx);
98
99 void anv_nir_validate_push_layout(struct brw_stage_prog_data *prog_data,
100 struct anv_pipeline_bind_map *map);
101
102 bool anv_nir_update_resource_intel_block(nir_shader *shader);
103
104 bool anv_nir_lower_resource_intel(nir_shader *shader,
105 const struct anv_physical_device *device,
106 enum anv_descriptor_set_layout_type desc_type);
107
108 bool anv_nir_add_base_work_group_id(nir_shader *shader);
109
110 uint32_t anv_nir_compute_used_push_descriptors(nir_shader *shader,
111 const struct anv_pipeline_sets_layout *layout);
112
113 bool anv_nir_loads_push_desc_buffer(nir_shader *nir,
114 const struct anv_pipeline_sets_layout *layout,
115 const struct anv_pipeline_bind_map *bind_map);
116
117 uint32_t anv_nir_push_desc_ubo_fully_promoted(nir_shader *nir,
118 const struct anv_pipeline_sets_layout *layout,
119 const struct anv_pipeline_bind_map *bind_map);
120
121 #ifdef __cplusplus
122 }
123 #endif
124
125 #endif /* ANV_NIR_H */
126