1 /*
2 * Copyright © Microsoft Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #ifndef DZN_PRIVATE_H
25 #define DZN_PRIVATE_H
26
27 #define COBJMACROS
28
29 #include "vk_command_pool.h"
30 #include "vk_command_buffer.h"
31 #include "vk_cmd_queue.h"
32 #include "vk_debug_report.h"
33 #include "vk_descriptor_set_layout.h"
34 #include "vk_device.h"
35 #include "vk_image.h"
36 #include "vk_log.h"
37 #include "vk_physical_device.h"
38 #include "vk_pipeline_layout.h"
39 #include "vk_render_pass.h"
40 #include "vk_sync.h"
41 #include "vk_sync_binary.h"
42 #include "vk_queue.h"
43 #include "vk_shader_module.h"
44 #include "wsi_common.h"
45
46 #include "util/bitset.h"
47 #include "util/blob.h"
48 #include "util/hash_table.h"
49 #include "util/u_dynarray.h"
50 #include "util/log.h"
51 #include "util/xmlconfig.h"
52
53 #include "shader_enums.h"
54
55 #include "dzn_entrypoints.h"
56 #include "dzn_nir.h"
57 #include "dzn_physical_device_enum.h"
58
59 #include <vulkan/vulkan.h>
60 #include <vulkan/vk_icd.h>
61
62 #define D3D12_IGNORE_SDK_LAYERS
63 #include <unknwn.h>
64 #include <directx/d3d12.h>
65
66 #include "spirv_to_dxil.h"
67 #include "dzn_abi_helper.h"
68
69 #define DZN_SWAP(t, a, b) \
70 do { \
71 t __tmp = a; \
72 a = b; \
73 b = __tmp; \
74 } while (0)
75
76 #define dzn_stub() unreachable("Unsupported feature")
77
78 #if defined(VK_USE_PLATFORM_WIN32_KHR) || \
79 defined(VK_USE_PLATFORM_WAYLAND_KHR) || \
80 defined(VK_USE_PLATFORM_XCB_KHR) || \
81 defined(VK_USE_PLATFORM_XLIB_KHR)
82 #define DZN_USE_WSI_PLATFORM
83 #endif
84
85 struct dxil_validator;
86 struct util_dl_library;
87
88 struct dzn_instance;
89 struct dzn_device;
90
91 struct dzn_meta_indirect_draw {
92 ID3D12RootSignature *root_sig;
93 ID3D12PipelineState *pipeline_state;
94 };
95
96 enum dzn_index_type {
97 DZN_NO_INDEX,
98 DZN_INDEX_2B,
99 DZN_INDEX_4B,
100 DZN_INDEX_2B_WITH_PRIM_RESTART,
101 DZN_INDEX_4B_WITH_PRIM_RESTART,
102 DZN_NUM_INDEX_TYPE,
103 };
104
105 static inline enum dzn_index_type
dzn_index_type_from_size(uint8_t index_size)106 dzn_index_type_from_size(uint8_t index_size)
107 {
108 switch (index_size) {
109 case 0: return DZN_NO_INDEX;
110 case 2: return DZN_INDEX_2B;
111 case 4: return DZN_INDEX_4B;
112 default: unreachable("Invalid index size");
113 }
114 }
115
116 static inline enum dzn_index_type
dzn_index_type_from_dxgi_format(DXGI_FORMAT format,bool prim_restart)117 dzn_index_type_from_dxgi_format(DXGI_FORMAT format, bool prim_restart)
118 {
119 switch (format) {
120 case DXGI_FORMAT_UNKNOWN: return DZN_NO_INDEX;
121 case DXGI_FORMAT_R16_UINT:
122 return prim_restart ? DZN_INDEX_2B_WITH_PRIM_RESTART : DZN_INDEX_2B;
123 case DXGI_FORMAT_R32_UINT:
124 return prim_restart ? DZN_INDEX_4B_WITH_PRIM_RESTART : DZN_INDEX_4B;
125 default: unreachable("Invalid index format");
126 }
127 }
128
129 static inline uint8_t
dzn_index_size(enum dzn_index_type type)130 dzn_index_size(enum dzn_index_type type)
131 {
132 switch (type) {
133 case DZN_NO_INDEX:
134 return 0;
135 case DZN_INDEX_2B_WITH_PRIM_RESTART:
136 case DZN_INDEX_2B:
137 return 2;
138 case DZN_INDEX_4B_WITH_PRIM_RESTART:
139 case DZN_INDEX_4B:
140 return 4;
141 default: unreachable("Invalid index type");
142 }
143 }
144
145 struct dzn_meta_triangle_fan_rewrite_index {
146 ID3D12RootSignature *root_sig;
147 ID3D12PipelineState *pipeline_state;
148 ID3D12CommandSignature *cmd_sig;
149 };
150
151 struct dzn_meta_blit_key {
152 union {
153 struct {
154 DXGI_FORMAT out_format;
155 uint32_t samples : 6;
156 uint32_t loc : 4;
157 uint32_t out_type : 4;
158 uint32_t sampler_dim : 4;
159 uint32_t src_is_array : 1;
160 uint32_t resolve_mode : 3;
161 uint32_t linear_filter : 1;
162 uint32_t stencil_bit : 4;
163 uint32_t padding : 5;
164 };
165 const uint64_t u64;
166 };
167 };
168
169 struct dzn_meta_blit {
170 ID3D12RootSignature *root_sig;
171 ID3D12PipelineState *pipeline_state;
172 };
173
174 struct dzn_meta_blits {
175 mtx_t shaders_lock;
176 D3D12_SHADER_BYTECODE vs;
177 struct hash_table *fs;
178 mtx_t contexts_lock;
179 struct hash_table_u64 *contexts;
180 };
181
182 const struct dzn_meta_blit *
183 dzn_meta_blits_get_context(struct dzn_device *device,
184 const struct dzn_meta_blit_key *key);
185
186 #define MAX_SYNC_TYPES 3
187 #define MAX_QUEUE_FAMILIES 2
188
189 struct dzn_physical_device {
190 struct vk_physical_device vk;
191
192 struct vk_physical_device_dispatch_table dispatch;
193
194 IUnknown *adapter;
195 struct dzn_physical_device_desc desc;
196
197 uint32_t queue_family_count;
198 struct dzn_queue_family {
199 VkQueueFamilyProperties props;
200 D3D12_COMMAND_QUEUE_DESC desc;
201 } queue_families[MAX_QUEUE_FAMILIES];
202
203 uint8_t pipeline_cache_uuid[VK_UUID_SIZE];
204 uint8_t device_uuid[VK_UUID_SIZE];
205 uint8_t driver_uuid[VK_UUID_SIZE];
206
207 struct wsi_device wsi_device;
208
209 ID3D12Device4 *dev;
210 ID3D12Device10 *dev10;
211 ID3D12Device11 *dev11;
212 ID3D12Device12 *dev12;
213 ID3D12Device13 *dev13;
214 D3D_FEATURE_LEVEL feature_level;
215 D3D_SHADER_MODEL shader_model;
216 D3D_ROOT_SIGNATURE_VERSION root_sig_version;
217 D3D12_FEATURE_DATA_ARCHITECTURE1 architecture;
218 D3D12_FEATURE_DATA_D3D12_OPTIONS options;
219 D3D12_FEATURE_DATA_D3D12_OPTIONS1 options1;
220 D3D12_FEATURE_DATA_D3D12_OPTIONS2 options2;
221 D3D12_FEATURE_DATA_D3D12_OPTIONS3 options3;
222 D3D12_FEATURE_DATA_D3D12_OPTIONS4 options4;
223 D3D12_FEATURE_DATA_D3D12_OPTIONS12 options12;
224 D3D12_FEATURE_DATA_D3D12_OPTIONS13 options13;
225 D3D12_FEATURE_DATA_D3D12_OPTIONS14 options14;
226 D3D12_FEATURE_DATA_D3D12_OPTIONS15 options15;
227 D3D12_FEATURE_DATA_D3D12_OPTIONS16 options16;
228 D3D12_FEATURE_DATA_D3D12_OPTIONS17 options17;
229 D3D12_FEATURE_DATA_D3D12_OPTIONS19 options19;
230 VkPhysicalDeviceMemoryProperties memory;
231 D3D12_HEAP_FLAGS heap_flags_for_mem_type[VK_MAX_MEMORY_TYPES];
232 const struct vk_sync_type *sync_types[MAX_SYNC_TYPES + 1];
233 float timestamp_period;
234 bool support_a4b4g4r4;
235 };
236
237 D3D12_FEATURE_DATA_FORMAT_SUPPORT
238 dzn_physical_device_get_format_support(struct dzn_physical_device *pdev,
239 VkFormat format,
240 VkImageCreateFlags create_flags);
241
242 uint32_t
243 dzn_physical_device_get_mem_type_mask_for_resource(const struct dzn_physical_device *pdev,
244 const D3D12_RESOURCE_DESC *desc,
245 bool shared);
246
247 enum dxil_shader_model
248 dzn_get_shader_model(const struct dzn_physical_device *pdev);
249
250 #define dzn_debug_ignored_stype(sType) \
251 mesa_logd("%s: ignored VkStructureType %u\n", __func__, (sType))
252
253 PFN_D3D12_SERIALIZE_VERSIONED_ROOT_SIGNATURE
254 d3d12_get_serialize_root_sig(struct util_dl_library *d3d12_mod);
255
256 void
257 d3d12_enable_debug_layer(struct util_dl_library *d3d12_mod, ID3D12DeviceFactory *factory);
258
259 void
260 d3d12_enable_gpu_validation(struct util_dl_library *d3d12_mod, ID3D12DeviceFactory *factory);
261
262 ID3D12Device4 *
263 d3d12_create_device(struct util_dl_library *d3d12_mod, IUnknown *adapter, ID3D12DeviceFactory *factory, bool experimental_features);
264
265 struct dzn_queue {
266 struct vk_queue vk;
267
268 ID3D12CommandQueue *cmdqueue;
269 ID3D12Fence *fence;
270 uint64_t fence_point;
271 };
272
273 struct dzn_descriptor_heap {
274 ID3D12DescriptorHeap *heap;
275 SIZE_T cpu_base;
276 uint64_t gpu_base;
277 uint32_t desc_count;
278 uint32_t desc_sz;
279 };
280
281 struct dzn_device_descriptor_heap {
282 struct dzn_descriptor_heap heap;
283 mtx_t lock;
284 struct util_dynarray slot_freelist;
285 uint32_t next_alloc_slot;
286 };
287
288 #define NUM_POOL_TYPES D3D12_DESCRIPTOR_HEAP_TYPE_SAMPLER + 1
289
290 struct dzn_device {
291 struct vk_device vk;
292 struct vk_device_extension_table enabled_extensions;
293 struct vk_device_dispatch_table cmd_dispatch;
294
295 ID3D12Device4 *dev;
296 ID3D12Device10 *dev10;
297 ID3D12Device11 *dev11;
298 ID3D12Device12 *dev12;
299 ID3D12Device13 *dev13;
300 ID3D12DeviceConfiguration *dev_config;
301
302 struct dzn_meta_indirect_draw indirect_draws[DZN_NUM_INDIRECT_DRAW_TYPES];
303 struct dzn_meta_triangle_fan_rewrite_index triangle_fan[DZN_NUM_INDEX_TYPE];
304 struct dzn_meta_blits blits;
305
306 struct {
307 #define DZN_QUERY_REFS_SECTION_SIZE 4096
308 #define DZN_QUERY_REFS_ALL_ONES_OFFSET 0
309 #define DZN_QUERY_REFS_ALL_ZEROS_OFFSET (DZN_QUERY_REFS_ALL_ONES_OFFSET + DZN_QUERY_REFS_SECTION_SIZE)
310 #define DZN_QUERY_REFS_RES_SIZE (DZN_QUERY_REFS_ALL_ZEROS_OFFSET + DZN_QUERY_REFS_SECTION_SIZE)
311 ID3D12Resource *refs;
312 } queries;
313
314 /* Will be the app's graphics queue if there's exactly one, otherwise this will be
315 * a dedicated graphics queue to host swapchain blits.
316 */
317 bool need_swapchain_blits;
318 struct dzn_queue *swapchain_queue;
319
320 bool bindless;
321 bool support_static_samplers;
322 struct dzn_device_descriptor_heap device_heaps[NUM_POOL_TYPES];
323 };
324
325 void dzn_meta_finish(struct dzn_device *device);
326
327 VkResult dzn_meta_init(struct dzn_device *device);
328
329 const struct dzn_meta_blit *
330 dzn_meta_blits_get_context(struct dzn_device *device,
331 const struct dzn_meta_blit_key *key);
332
333 ID3D12RootSignature *
334 dzn_device_create_root_sig(struct dzn_device *device,
335 const D3D12_VERSIONED_ROOT_SIGNATURE_DESC *desc);
336
337 struct dzn_device_memory {
338 struct vk_object_base base;
339
340 struct list_head link;
341
342 /* Dedicated image/buffer resource. Can be used for import (e.g. from a swapchain)
343 * or just from a dedicated allocation request.
344 */
345 ID3D12Resource *dedicated_res;
346
347 ID3D12Heap *heap;
348 VkDeviceSize size;
349
350 /* A buffer-resource spanning the entire heap, used for mapping memory */
351 ID3D12Resource *map_res;
352
353 VkDeviceSize map_size;
354 void *map;
355
356 /* If the resource is exportable, this is the pre-created handle for that */
357 HANDLE export_handle;
358
359 /* These flags need to be added into all resources created on this heap */
360 D3D12_RESOURCE_FLAGS res_flags;
361 };
362
363 enum dzn_cmd_bindpoint_dirty {
364 DZN_CMD_BINDPOINT_DIRTY_PIPELINE = 1 << 0,
365 DZN_CMD_BINDPOINT_DIRTY_DYNAMIC_BUFFERS = 1 << 1,
366 DZN_CMD_BINDPOINT_DIRTY_SYSVALS = 1 << 2,
367 DZN_CMD_BINDPOINT_DIRTY_DESC_SET0 = 1 << 3,
368 DZN_CMD_BINDPOINT_DIRTY_DESC_SET1 = 1 << 4,
369 DZN_CMD_BINDPOINT_DIRTY_DESC_SET2 = 1 << 5,
370 DZN_CMD_BINDPOINT_DIRTY_DESC_SET3 = 1 << 6,
371 DZN_CMD_BINDPOINT_DIRTY_DESC_SET4 = 1 << 7,
372 DZN_CMD_BINDPOINT_DIRTY_DESC_SET5 = 1 << 8,
373 DZN_CMD_BINDPOINT_DIRTY_DESC_SET6 = 1 << 9,
374 DZN_CMD_BINDPOINT_DIRTY_DESC_SET7 = 1 << 10,
375 DZN_CMD_BINDPOINT_DIRTY_DESC_SETS =
376 DZN_CMD_BINDPOINT_DIRTY_DESC_SET0 |
377 DZN_CMD_BINDPOINT_DIRTY_DESC_SET1 |
378 DZN_CMD_BINDPOINT_DIRTY_DESC_SET2 |
379 DZN_CMD_BINDPOINT_DIRTY_DESC_SET3 |
380 DZN_CMD_BINDPOINT_DIRTY_DESC_SET4 |
381 DZN_CMD_BINDPOINT_DIRTY_DESC_SET5 |
382 DZN_CMD_BINDPOINT_DIRTY_DESC_SET6 |
383 DZN_CMD_BINDPOINT_DIRTY_DESC_SET7,
384 DZN_CMD_BINDPOINT_DIRTY_HEAPS =
385 DZN_CMD_BINDPOINT_DIRTY_DYNAMIC_BUFFERS |
386 DZN_CMD_BINDPOINT_DIRTY_SYSVALS |
387 DZN_CMD_BINDPOINT_DIRTY_DESC_SETS,
388 };
389
390 enum dzn_cmd_dirty {
391 DZN_CMD_DIRTY_VIEWPORTS = 1 << 0,
392 DZN_CMD_DIRTY_SCISSORS = 1 << 1,
393 DZN_CMD_DIRTY_IB = 1 << 2,
394 DZN_CMD_DIRTY_STENCIL_REF = 1 << 3,
395 DZN_CMD_DIRTY_STENCIL_COMPARE_MASK = 1 << 4,
396 DZN_CMD_DIRTY_STENCIL_WRITE_MASK = 1 << 5,
397 DZN_CMD_DIRTY_BLEND_CONSTANTS = 1 << 6,
398 DZN_CMD_DIRTY_DEPTH_BOUNDS = 1 << 7,
399 DZN_CMD_DIRTY_DEPTH_BIAS = 1 << 8,
400 };
401
402 #define MAX_VBS D3D12_IA_VERTEX_INPUT_RESOURCE_SLOT_COUNT
403 #define MAX_VP D3D12_VIEWPORT_AND_SCISSORRECT_OBJECT_COUNT_PER_PIPELINE
404 #define MAX_SCISSOR D3D12_VIEWPORT_AND_SCISSORRECT_OBJECT_COUNT_PER_PIPELINE
405 #define MAX_SETS 8
406 #define MAX_DYNAMIC_UNIFORM_BUFFERS 8
407 #define MAX_DYNAMIC_STORAGE_BUFFERS 4
408 #define MAX_DYNAMIC_BUFFERS \
409 (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
410 #define MAX_PUSH_CONSTANT_DWORDS 32
411
412 #define NUM_BIND_POINT VK_PIPELINE_BIND_POINT_COMPUTE + 1
413
414 #define dzn_foreach_pool_type(type) \
415 for (D3D12_DESCRIPTOR_HEAP_TYPE type = D3D12_DESCRIPTOR_HEAP_TYPE_CBV_SRV_UAV; \
416 type <= D3D12_DESCRIPTOR_HEAP_TYPE_SAMPLER; \
417 type = (D3D12_DESCRIPTOR_HEAP_TYPE)(type + 1))
418
419 struct dzn_cmd_event_signal {
420 struct dzn_event *event;
421 bool value;
422 };
423
424 struct dzn_cmd_buffer;
425
426 struct dzn_descriptor_state {
427 struct {
428 const struct dzn_descriptor_set *set;
429 uint32_t dynamic_offsets[MAX_DYNAMIC_BUFFERS];
430 } sets[MAX_SETS];
431 struct dzn_descriptor_heap *heaps[NUM_POOL_TYPES];
432 };
433
434 struct dzn_sampler;
435 struct dzn_image_view;
436 struct dzn_buffer_view;
437
438 struct dzn_buffer_desc {
439 VkDescriptorType type;
440 struct dzn_buffer *buffer;
441 VkDeviceSize range;
442 VkDeviceSize offset;
443 };
444
445 #define MAX_DESCS_PER_SAMPLER_HEAP D3D12_MAX_SHADER_VISIBLE_SAMPLER_HEAP_SIZE
446 #define MAX_DESCS_PER_CBV_SRV_UAV_HEAP D3D12_MAX_SHADER_VISIBLE_DESCRIPTOR_HEAP_SIZE_TIER_1
447
448 VkResult
449 dzn_descriptor_heap_init(struct dzn_descriptor_heap *heap,
450 struct dzn_device *device,
451 D3D12_DESCRIPTOR_HEAP_TYPE type,
452 uint32_t desc_count,
453 bool shader_visible);
454
455 void
456 dzn_descriptor_heap_finish(struct dzn_descriptor_heap *heap);
457
458 D3D12_CPU_DESCRIPTOR_HANDLE
459 dzn_descriptor_heap_get_cpu_handle(const struct dzn_descriptor_heap *heap, uint32_t slot);
460
461 D3D12_GPU_DESCRIPTOR_HANDLE
462 dzn_descriptor_heap_get_gpu_handle(const struct dzn_descriptor_heap *heap, uint32_t slot);
463
464 void
465 dzn_descriptor_heap_write_image_view_desc(struct dzn_device *device,
466 struct dzn_descriptor_heap *heap,
467 uint32_t heap_offset,
468 bool writeable,
469 bool cube_as_2darray,
470 const struct dzn_image_view *iview);
471
472 void
473 dzn_descriptor_heap_write_buffer_view_desc(struct dzn_device *device,
474 struct dzn_descriptor_heap *heap,
475 uint32_t heap_offset,
476 bool writeable,
477 const struct dzn_buffer_view *bview);
478
479 void
480 dzn_descriptor_heap_write_buffer_desc(struct dzn_device *device,
481 struct dzn_descriptor_heap *heap,
482 uint32_t heap_offset,
483 bool writeable,
484 const struct dzn_buffer_desc *bdesc);
485
486 void
487 dzn_descriptor_heap_write_sampler_desc(struct dzn_device *device,
488 struct dzn_descriptor_heap *heap,
489 uint32_t desc_offset,
490 const struct dzn_sampler *sampler);
491
492 void
493 dzn_descriptor_heap_copy(struct dzn_device *device,
494 struct dzn_descriptor_heap *dst_heap, uint32_t dst_heap_offset,
495 const struct dzn_descriptor_heap *src_heap, uint32_t src_heap_offset,
496 uint32_t desc_count, D3D12_DESCRIPTOR_HEAP_TYPE type);
497
498 struct dzn_descriptor_heap_pool_entry {
499 struct list_head link;
500 struct dzn_descriptor_heap heap;
501 };
502
503 struct dzn_descriptor_heap_pool {
504 const VkAllocationCallbacks *alloc;
505 D3D12_DESCRIPTOR_HEAP_TYPE type;
506 bool shader_visible;
507 struct list_head active_heaps, free_heaps;
508 uint32_t offset;
509 uint32_t desc_sz;
510 };
511
512 void
513 dzn_descriptor_heap_pool_init(struct dzn_descriptor_heap_pool *pool,
514 struct dzn_device *device,
515 D3D12_DESCRIPTOR_HEAP_TYPE type,
516 bool shader_visible,
517 const VkAllocationCallbacks *alloc);
518
519 void
520 dzn_descriptor_heap_pool_finish(struct dzn_descriptor_heap_pool *pool);
521
522 void
523 dzn_descriptor_heap_pool_reset(struct dzn_descriptor_heap_pool *pool);
524
525 VkResult
526 dzn_descriptor_heap_pool_alloc_slots(struct dzn_descriptor_heap_pool *pool,
527 struct dzn_device *device,
528 uint32_t num_slots,
529 struct dzn_descriptor_heap **heap,
530 uint32_t *first_slot);
531
532 int
533 dzn_device_descriptor_heap_alloc_slot(struct dzn_device *device,
534 D3D12_DESCRIPTOR_HEAP_TYPE type);
535
536 void
537 dzn_device_descriptor_heap_free_slot(struct dzn_device *device,
538 D3D12_DESCRIPTOR_HEAP_TYPE type,
539 int slot);
540
541 struct dzn_cmd_buffer_query_range {
542 struct dzn_query_pool *qpool;
543 uint32_t start, count;
544 };
545
546 struct dzn_cmd_buffer_query_pool_state {
547 struct util_dynarray reset, collect, signal, zero;
548 };
549
550 struct dzn_internal_resource {
551 struct list_head link;
552 ID3D12Resource *res;
553 uint64_t size;
554 };
555
556 enum dzn_event_state {
557 DZN_EVENT_STATE_RESET = 0,
558 DZN_EVENT_STATE_SET = 1,
559 };
560
561 struct dzn_cmd_buffer_push_constant_state {
562 uint32_t offset;
563 uint32_t end;
564 uint32_t values[MAX_PUSH_CONSTANT_DWORDS];
565 };
566
567 struct dzn_rendering_attachment {
568 struct dzn_image_view *iview;
569 VkImageLayout layout;
570 struct {
571 VkResolveModeFlagBits mode;
572 struct dzn_image_view *iview;
573 VkImageLayout layout;
574 } resolve;
575 VkAttachmentStoreOp store_op;
576 };
577
578 struct dzn_graphics_pipeline_variant_key {
579 D3D12_INDEX_BUFFER_STRIP_CUT_VALUE ib_strip_cut;
580 struct {
581 int constant_factor;
582 float slope_factor;
583 float clamp;
584 } depth_bias;
585 struct {
586 struct {
587 uint32_t ref, compare_mask, write_mask;
588 } front, back;
589 } stencil_test;
590 };
591
592 struct dzn_graphics_pipeline_variant {
593 struct dzn_graphics_pipeline_variant_key key;
594 ID3D12PipelineState *state;
595 };
596
597 #define MAX_RTS D3D12_SIMULTANEOUS_RENDER_TARGET_COUNT
598
599 struct dzn_cmd_buffer_state {
600 const struct dzn_pipeline *pipeline;
601 struct dzn_descriptor_heap *heaps[NUM_POOL_TYPES];
602 struct dzn_graphics_pipeline_variant_key pipeline_variant;
603 struct {
604 VkRenderingFlags flags;
605 D3D12_RECT area;
606 uint32_t layer_count;
607 uint32_t view_mask;
608 struct {
609 uint32_t color_count;
610 struct dzn_rendering_attachment colors[MAX_RTS];
611 struct dzn_rendering_attachment depth, stencil;
612 } attachments;
613 } render;
614 struct {
615 BITSET_DECLARE(dirty, MAX_VBS);
616 D3D12_VERTEX_BUFFER_VIEW views[MAX_VBS];
617 } vb;
618 struct {
619 D3D12_INDEX_BUFFER_VIEW view;
620 } ib;
621 struct {
622 struct {
623 struct {
624 uint32_t ref, compare_mask, write_mask;
625 } front, back;
626 } stencil_test;
627 struct {
628 float min, max;
629 } depth_bounds;
630 } zsa;
631 struct {
632 float constants[4];
633 } blend;
634 D3D12_VIEWPORT viewports[MAX_VP];
635 D3D12_RECT scissors[MAX_SCISSOR];
636 struct {
637 struct dzn_cmd_buffer_push_constant_state gfx, compute;
638 } push_constant;
639 uint32_t dirty;
640 struct {
641 struct dzn_pipeline *pipeline;
642 ID3D12RootSignature *root_sig;
643 struct dzn_descriptor_state desc_state;
644 uint32_t dirty;
645 } bindpoint[NUM_BIND_POINT];
646 union {
647 struct dxil_spirv_vertex_runtime_data gfx;
648 struct dxil_spirv_compute_runtime_data compute;
649 } sysvals;
650 struct {
651 uint32_t num_views;
652 uint32_t view_mask;
653 } multiview;
654 };
655
656 struct dzn_cmd_buffer_rtv_key {
657 const struct dzn_image *image;
658 D3D12_RENDER_TARGET_VIEW_DESC desc;
659 };
660
661 struct dzn_cmd_buffer_rtv_entry {
662 struct dzn_cmd_buffer_rtv_key key;
663 D3D12_CPU_DESCRIPTOR_HANDLE handle;
664 };
665
666 struct dzn_cmd_buffer_dsv_key {
667 const struct dzn_image *image;
668 D3D12_DEPTH_STENCIL_VIEW_DESC desc;
669 };
670
671 struct dzn_cmd_buffer_dsv_entry {
672 struct dzn_cmd_buffer_dsv_key key;
673 D3D12_CPU_DESCRIPTOR_HANDLE handle;
674 };
675
676 enum dzn_internal_buf_bucket {
677 DZN_INTERNAL_BUF_UPLOAD,
678 DZN_INTERNAL_BUF_DEFAULT,
679 DZN_INTERNAL_BUF_BUCKET_COUNT,
680 };
681
682 struct dzn_cmd_buffer {
683 struct vk_command_buffer vk;
684 struct dzn_cmd_buffer_state state;
685
686 struct {
687 struct hash_table *ht;
688 struct util_dynarray reset;
689 struct util_dynarray signal;
690 } queries;
691
692 struct {
693 struct hash_table *ht;
694 struct util_dynarray signal;
695 } events;
696
697 struct {
698 struct hash_table *ht;
699 struct dzn_descriptor_heap_pool pool;
700 } rtvs, dsvs;
701
702 bool enhanced_barriers;
703 struct hash_table *transition_barriers;
704
705 struct dzn_descriptor_heap_pool cbv_srv_uav_pool, sampler_pool;
706 D3D12_CPU_DESCRIPTOR_HANDLE null_rtv;
707
708 struct list_head internal_bufs[DZN_INTERNAL_BUF_BUCKET_COUNT];
709 struct dzn_internal_resource *cur_upload_buf;
710 uint64_t cur_upload_buf_offset;
711
712 ID3D12CommandAllocator *cmdalloc;
713 ID3D12GraphicsCommandList1 *cmdlist;
714 ID3D12GraphicsCommandList8 *cmdlist8;
715 ID3D12GraphicsCommandList9 *cmdlist9;
716
717 D3D12_COMMAND_LIST_TYPE type;
718 D3D12_BARRIER_SYNC valid_sync;
719 D3D12_BARRIER_ACCESS valid_access;
720 };
721
722 struct dxil_spirv_bindless_entry;
723 struct dzn_descriptor_pool {
724 struct vk_object_base base;
725 VkAllocationCallbacks alloc;
726
727 uint32_t set_count;
728 uint32_t used_set_count;
729 struct dzn_descriptor_set *sets;
730 union {
731 struct dzn_descriptor_heap heaps[NUM_POOL_TYPES];
732 struct {
733 ID3D12Resource *buf;
734 volatile struct dxil_spirv_bindless_entry *map;
735 uint64_t gpuva;
736 } bindless;
737 };
738 uint32_t desc_count[NUM_POOL_TYPES];
739 uint32_t used_desc_count[NUM_POOL_TYPES];
740 uint32_t free_offset[NUM_POOL_TYPES];
741 };
742
743 #define MAX_SHADER_VISIBILITIES (D3D12_SHADER_VISIBILITY_PIXEL + 1)
744 #define STATIC_SAMPLER_TAG (~0u - 1)
745
746 struct dzn_descriptor_set_layout_binding {
747 VkDescriptorType type;
748 uint32_t stages;
749 D3D12_SHADER_VISIBILITY visibility;
750 uint32_t base_shader_register;
751 uint32_t range_idx[NUM_POOL_TYPES];
752 union {
753 /* For sampler types, index into the set layout's immutable sampler list,
754 * or STATIC_SAMPLER_TAG for static samplers, or ~0 for dynamic samplers. */
755 uint32_t immutable_sampler_idx;
756 /* For dynamic buffer types, index into the set's dynamic buffer list.
757 * For non-dynamic buffer types, index into the set's buffer descriptor slot list when bindless. */
758 uint32_t buffer_idx;
759 };
760 bool variable_size;
761 };
762
763 struct dzn_descriptor_set_layout {
764 struct vk_descriptor_set_layout vk;
765
766 /* Ranges are bucketed by shader visibility so that each visibility can have
767 * a single descriptor table in the root signature, with all ranges concatenated. */
768 uint32_t range_count[MAX_SHADER_VISIBILITIES][NUM_POOL_TYPES];
769 const D3D12_DESCRIPTOR_RANGE1 *ranges[MAX_SHADER_VISIBILITIES][NUM_POOL_TYPES];
770
771 /* The number of descriptors across all ranges/visibilities for this type */
772 uint32_t range_desc_count[NUM_POOL_TYPES];
773
774 /* Static samplers actually go into the D3D12 root signature.
775 * Immutable samplers are only stored here to be copied into descriptor tables later. */
776 uint32_t static_sampler_count;
777 const D3D12_STATIC_SAMPLER_DESC1 *static_samplers;
778 uint32_t immutable_sampler_count;
779 const struct dzn_sampler **immutable_samplers;
780
781 struct {
782 uint32_t bindings[MAX_DYNAMIC_BUFFERS];
783 uint32_t count;
784 uint32_t desc_count;
785 uint32_t range_offset;
786 } dynamic_buffers;
787 uint32_t buffer_count;
788 uint32_t stages;
789
790 uint32_t binding_count;
791 const struct dzn_descriptor_set_layout_binding *bindings;
792 };
793
794 struct dzn_descriptor_set {
795 struct vk_object_base base;
796 struct dzn_buffer_desc dynamic_buffers[MAX_DYNAMIC_BUFFERS];
797 struct dzn_descriptor_pool *pool;
798 /* The offset in the current active staging descriptor heap for the set's pool. */
799 uint32_t heap_offsets[NUM_POOL_TYPES];
800 /* The number of descriptors needed for this set */
801 uint32_t heap_sizes[NUM_POOL_TYPES];
802 /* Layout (and pool) is null for a freed descriptor set */
803 const struct dzn_descriptor_set_layout *layout;
804 };
805
806 struct dzn_pipeline_layout_set {
807 /* The offset from the start of a descriptor table where the set should be copied */
808 uint32_t heap_offsets[NUM_POOL_TYPES];
809 struct {
810 uint32_t primary, alt;
811 } dynamic_buffer_heap_offsets[MAX_DYNAMIC_BUFFERS];
812 uint32_t dynamic_buffer_count;
813 uint32_t range_desc_count[NUM_POOL_TYPES];
814 };
815
816 enum dzn_pipeline_binding_class {
817 DZN_PIPELINE_BINDING_NORMAL,
818 DZN_PIPELINE_BINDING_DYNAMIC_BUFFER,
819 DZN_PIPELINE_BINDING_STATIC_SAMPLER,
820 };
821
822 struct dzn_pipeline_layout {
823 struct vk_pipeline_layout vk;
824 struct dzn_pipeline_layout_set sets[MAX_SETS];
825 struct {
826 uint32_t binding_count;
827 /* A mapping from a binding value, which can be shared among multiple descriptors
828 * in an array, to unique 0-based registers. This mapping is applied to the shaders
829 * during pipeline creation. */
830 uint32_t *base_reg;
831 uint8_t *binding_class;
832 } binding_translation[MAX_SETS];
833 uint32_t set_count;
834 /* How much space needs to be allocated to copy descriptors during cmdbuf recording? */
835 uint32_t desc_count[NUM_POOL_TYPES];
836 uint32_t dynamic_buffer_count;
837 struct {
838 uint32_t param_count;
839 uint32_t sets_param_count;
840 uint32_t sysval_cbv_param_idx;
841 uint32_t push_constant_cbv_param_idx;
842 uint32_t dynamic_buffer_bindless_param_idx;
843 D3D12_DESCRIPTOR_HEAP_TYPE type[MAX_SHADER_VISIBILITIES];
844 ID3D12RootSignature *sig;
845 } root;
846 struct {
847 uint8_t hash[SHA1_DIGEST_LENGTH];
848 } stages[MESA_VULKAN_SHADER_STAGES];
849 };
850
851 struct dzn_descriptor_update_template_entry {
852 VkDescriptorType type;
853 uint32_t desc_count;
854 uint32_t buffer_idx;
855 struct {
856 uint32_t cbv_srv_uav;
857 union {
858 uint32_t sampler, extra_srv;
859 };
860 } heap_offsets;
861 struct {
862 size_t offset;
863 size_t stride;
864 } user_data;
865 };
866
867 struct dzn_descriptor_update_template {
868 struct vk_object_base base;
869 uint32_t entry_count;
870 const struct dzn_descriptor_update_template_entry *entries;
871 };
872
873 enum dzn_register_space {
874 DZN_REGISTER_SPACE_SYSVALS = MAX_SETS,
875 DZN_REGISTER_SPACE_PUSH_CONSTANT,
876 };
877
878 #define D3D12_PIPELINE_STATE_STREAM_DESC_SIZE(__type) \
879 ALIGN_POT(ALIGN_POT(sizeof(D3D12_PIPELINE_STATE_SUBOBJECT_TYPE), alignof(__type)) + sizeof(__type), alignof(void *))
880
881 static_assert(sizeof(D3D12_DEPTH_STENCIL_DESC2) > sizeof(D3D12_DEPTH_STENCIL_DESC1),
882 "Using just one of these descs in the max size calculation");
883 static_assert(sizeof(D3D12_RASTERIZER_DESC) >= sizeof(D3D12_RASTERIZER_DESC1) &&
884 sizeof(D3D12_RASTERIZER_DESC) >= sizeof(D3D12_RASTERIZER_DESC2),
885 "Using just one of these descs in the max size calculation");
886
887 #define MAX_GFX_PIPELINE_STATE_STREAM_SIZE \
888 D3D12_PIPELINE_STATE_STREAM_DESC_SIZE(ID3D12RootSignature *) + \
889 (D3D12_PIPELINE_STATE_STREAM_DESC_SIZE(D3D12_SHADER_BYTECODE) * 5) + /* VS, PS, DS, HS, GS */ \
890 D3D12_PIPELINE_STATE_STREAM_DESC_SIZE(D3D12_STREAM_OUTPUT_DESC) + \
891 D3D12_PIPELINE_STATE_STREAM_DESC_SIZE(D3D12_BLEND_DESC) + \
892 D3D12_PIPELINE_STATE_STREAM_DESC_SIZE(UINT) + /* SampleMask */ \
893 D3D12_PIPELINE_STATE_STREAM_DESC_SIZE(D3D12_RASTERIZER_DESC) + \
894 D3D12_PIPELINE_STATE_STREAM_DESC_SIZE(D3D12_INPUT_LAYOUT_DESC) + \
895 D3D12_PIPELINE_STATE_STREAM_DESC_SIZE(D3D12_INDEX_BUFFER_STRIP_CUT_VALUE) + \
896 D3D12_PIPELINE_STATE_STREAM_DESC_SIZE(D3D12_PRIMITIVE_TOPOLOGY_TYPE) + \
897 D3D12_PIPELINE_STATE_STREAM_DESC_SIZE(struct D3D12_RT_FORMAT_ARRAY) + \
898 D3D12_PIPELINE_STATE_STREAM_DESC_SIZE(DXGI_FORMAT) + /* DS format */ \
899 D3D12_PIPELINE_STATE_STREAM_DESC_SIZE(DXGI_SAMPLE_DESC) + \
900 D3D12_PIPELINE_STATE_STREAM_DESC_SIZE(D3D12_NODE_MASK) + \
901 D3D12_PIPELINE_STATE_STREAM_DESC_SIZE(D3D12_CACHED_PIPELINE_STATE) + \
902 D3D12_PIPELINE_STATE_STREAM_DESC_SIZE(D3D12_PIPELINE_STATE_FLAGS) + \
903 D3D12_PIPELINE_STATE_STREAM_DESC_SIZE(D3D12_DEPTH_STENCIL_DESC2) + \
904 D3D12_PIPELINE_STATE_STREAM_DESC_SIZE(D3D12_VIEW_INSTANCING_DESC) + \
905 D3D12_PIPELINE_STATE_STREAM_DESC_SIZE(D3D12_PIPELINE_STATE_FLAGS)
906
907 #define MAX_COMPUTE_PIPELINE_STATE_STREAM_SIZE \
908 D3D12_PIPELINE_STATE_STREAM_DESC_SIZE(ID3D12RootSignature *) + \
909 D3D12_PIPELINE_STATE_STREAM_DESC_SIZE(D3D12_SHADER_BYTECODE) + \
910 D3D12_PIPELINE_STATE_STREAM_DESC_SIZE(D3D12_CACHED_PIPELINE_STATE)
911
912 struct dzn_pipeline {
913 struct vk_object_base base;
914 VkPipelineBindPoint type;
915 struct dzn_device *device;
916 struct {
917 uint32_t sets_param_count;
918 uint32_t sysval_cbv_param_idx;
919 uint32_t push_constant_cbv_param_idx;
920 uint32_t dynamic_buffer_bindless_param_idx;
921 D3D12_DESCRIPTOR_HEAP_TYPE type[MAX_SHADER_VISIBILITIES];
922 ID3D12RootSignature *sig;
923 } root;
924 struct dzn_pipeline_layout_set sets[MAX_SETS];
925 uint32_t set_count;
926 uint32_t desc_count[NUM_POOL_TYPES];
927 uint32_t dynamic_buffer_count;
928 ID3D12PipelineState *state;
929 };
930
931 extern const struct vk_pipeline_cache_object_ops dzn_cached_blob_ops;
932
933 enum dzn_indirect_draw_cmd_sig_type {
934 DZN_INDIRECT_DRAW_CMD_SIG,
935 DZN_INDIRECT_INDEXED_DRAW_CMD_SIG,
936 DZN_INDIRECT_DRAW_TRIANGLE_FAN_CMD_SIG,
937 DZN_NUM_INDIRECT_DRAW_CMD_SIGS,
938 };
939
940 struct dzn_graphics_pipeline {
941 struct dzn_pipeline base;
942 struct {
943 unsigned count;
944 uint32_t strides[MAX_VBS];
945 } vb;
946
947 struct {
948 bool triangle_fan;
949 D3D_PRIMITIVE_TOPOLOGY topology;
950 } ia;
951
952 struct {
953 unsigned count;
954 bool dynamic;
955 D3D12_VIEWPORT desc[MAX_VP];
956 } vp;
957
958 struct {
959 unsigned count;
960 bool dynamic;
961 D3D12_RECT desc[MAX_SCISSOR];
962 } scissor;
963
964 struct {
965 struct {
966 bool enable;
967 bool dynamic_ref;
968 bool dynamic_write_mask;
969 bool dynamic_compare_mask;
970 struct {
971 uint32_t ref;
972 uint32_t write_mask;
973 uint32_t compare_mask;
974 bool uses_ref;
975 } front, back;
976 } stencil_test;
977 struct {
978 bool enable;
979 bool dynamic;
980 float min, max;
981 } depth_bounds;
982 bool dynamic_depth_bias;
983 DXGI_FORMAT ds_fmt;
984 } zsa;
985
986 struct {
987 bool dynamic_constants;
988 float constants[4];
989 } blend;
990
991 bool rast_disabled_from_missing_position;
992 bool use_gs_for_polygon_mode_point;
993
994 struct {
995 uint32_t view_mask;
996 bool native_view_instancing;
997 } multiview;
998
999 struct {
1000 uintptr_t stream_buf[MAX_GFX_PIPELINE_STATE_STREAM_SIZE / sizeof(uintptr_t)];
1001 D3D12_PIPELINE_STATE_STREAM_DESC stream_desc;
1002 struct {
1003 uint32_t ib_strip_cut;
1004 uint32_t rast;
1005 uint32_t ds;
1006 } desc_offsets;
1007 D3D12_INPUT_ELEMENT_DESC inputs[D3D12_VS_INPUT_REGISTER_COUNT];
1008 struct {
1009 D3D12_SHADER_BYTECODE *bc;
1010 nir_shader *nir;
1011 } shaders[MESA_VULKAN_SHADER_STAGES];
1012 } templates;
1013
1014 struct hash_table *variants;
1015
1016 ID3D12CommandSignature *indirect_cmd_sigs[DZN_NUM_INDIRECT_DRAW_CMD_SIGS];
1017 };
1018
1019 #define dzn_graphics_pipeline_get_desc(pipeline, streambuf, name) \
1020 (void *)(pipeline->templates.desc_offsets.name == 0 ? NULL : \
1021 (uint8_t *)streambuf + pipeline->templates.desc_offsets.name)
1022
1023 #define dzn_graphics_pipeline_get_desc_template(pipeline, name) \
1024 (const void *)dzn_graphics_pipeline_get_desc(pipeline, pipeline->templates.stream_buf, name)
1025
1026 ID3D12PipelineState *
1027 dzn_graphics_pipeline_get_state(struct dzn_graphics_pipeline *pipeline,
1028 const struct dzn_graphics_pipeline_variant_key *key);
1029
1030 ID3D12CommandSignature *
1031 dzn_graphics_pipeline_get_indirect_cmd_sig(struct dzn_graphics_pipeline *pipeline,
1032 enum dzn_indirect_draw_cmd_sig_type cmd_sig_type);
1033
1034 VkFormat dzn_graphics_pipeline_patch_vi_format(VkFormat format);
1035
1036 struct dzn_compute_pipeline {
1037 struct dzn_pipeline base;
1038 struct {
1039 uint32_t x, y, z;
1040 } local_size;
1041
1042 ID3D12CommandSignature *indirect_cmd_sig;
1043 };
1044
1045 ID3D12CommandSignature *
1046 dzn_compute_pipeline_get_indirect_cmd_sig(struct dzn_compute_pipeline *pipeline);
1047
1048 #define MAX_MIP_LEVELS 14
1049
1050 struct dzn_image {
1051 struct vk_image vk;
1052
1053 struct {
1054 uint32_t row_stride;
1055 uint32_t size;
1056 } linear;
1057 D3D12_RESOURCE_DESC desc;
1058 ID3D12Resource *res;
1059 struct dzn_device_memory *mem;
1060 uint32_t castable_format_count;
1061 const DXGI_FORMAT *castable_formats;
1062
1063 D3D12_BARRIER_ACCESS valid_access;
1064 };
1065
1066 bool
1067 dzn_image_formats_are_compatible(const struct dzn_device *device,
1068 VkFormat orig_fmt, VkFormat new_fmt,
1069 VkImageUsageFlags usage,
1070 VkImageAspectFlagBits aspect);
1071
1072 void
1073 dzn_image_align_extent(const struct dzn_image *image,
1074 VkExtent3D *extent);
1075
1076 DXGI_FORMAT
1077 dzn_image_get_dxgi_format(const struct dzn_physical_device *pdev,
1078 VkFormat format,
1079 VkImageUsageFlags usage,
1080 VkImageAspectFlags aspects);
1081
1082 VkFormat
1083 dzn_image_get_plane_format(VkFormat fmt, VkImageAspectFlags aspect);
1084
1085 DXGI_FORMAT
1086 dzn_image_get_placed_footprint_format(const struct dzn_physical_device *pdev,
1087 VkFormat fmt, VkImageAspectFlags aspect);
1088
1089 D3D12_DEPTH_STENCIL_VIEW_DESC
1090 dzn_image_get_dsv_desc(const struct dzn_image *image,
1091 const VkImageSubresourceRange *range,
1092 uint32_t level);
1093
1094 D3D12_RENDER_TARGET_VIEW_DESC
1095 dzn_image_get_rtv_desc(const struct dzn_image *image,
1096 const VkImageSubresourceRange *range,
1097 uint32_t level);
1098
1099 D3D12_RESOURCE_STATES
1100 dzn_image_layout_to_state(const struct dzn_image *image,
1101 VkImageLayout layout,
1102 VkImageAspectFlagBits aspect,
1103 D3D12_COMMAND_LIST_TYPE type);
1104
1105 D3D12_BARRIER_LAYOUT
1106 dzn_vk_layout_to_d3d_layout(VkImageLayout layout,
1107 D3D12_COMMAND_LIST_TYPE type,
1108 VkImageAspectFlags aspect);
1109
1110 uint32_t
1111 dzn_image_layers_get_subresource_index(const struct dzn_image *image,
1112 const VkImageSubresourceLayers *subres,
1113 VkImageAspectFlagBits aspect,
1114 uint32_t layer);
1115 uint32_t
1116 dzn_image_range_get_subresource_index(const struct dzn_image *image,
1117 const VkImageSubresourceRange *range,
1118 VkImageAspectFlagBits aspect,
1119 uint32_t level, uint32_t layer);
1120
1121 D3D12_TEXTURE_COPY_LOCATION
1122 dzn_image_get_copy_loc(const struct dzn_image *image,
1123 const VkImageSubresourceLayers *layers,
1124 VkImageAspectFlagBits aspect,
1125 uint32_t layer);
1126
1127 struct dzn_image_view {
1128 struct vk_image_view vk;
1129 D3D12_SHADER_RESOURCE_VIEW_DESC srv_desc;
1130 D3D12_UNORDERED_ACCESS_VIEW_DESC uav_desc;
1131 D3D12_RENDER_TARGET_VIEW_DESC rtv_desc;
1132 D3D12_DEPTH_STENCIL_VIEW_DESC dsv_desc;
1133 int srv_bindless_slot;
1134 int uav_bindless_slot;
1135 };
1136
1137 void
1138 dzn_image_view_init(struct dzn_device *device,
1139 struct dzn_image_view *iview,
1140 const VkImageViewCreateInfo *info);
1141
1142 void
1143 dzn_image_view_finish(struct dzn_image_view *iview);
1144
1145 struct dzn_buffer {
1146 struct vk_object_base base;
1147
1148 VkDeviceSize size;
1149
1150 D3D12_RESOURCE_DESC desc;
1151 ID3D12Resource *res;
1152
1153 VkBufferCreateFlags create_flags;
1154 VkBufferUsageFlags usage;
1155 bool shared;
1156
1157 D3D12_BARRIER_ACCESS valid_access;
1158 D3D12_GPU_VIRTUAL_ADDRESS gpuva;
1159
1160 mtx_t bindless_view_lock;
1161 int cbv_bindless_slot;
1162 int uav_bindless_slot;
1163 struct hash_table *custom_views;
1164 };
1165
1166 void
1167 dzn_buffer_get_bindless_buffer_descriptor(struct dzn_device *device,
1168 const struct dzn_buffer_desc *bdesc,
1169 volatile struct dxil_spirv_bindless_entry *out);
1170
1171 DXGI_FORMAT
1172 dzn_buffer_get_dxgi_format(VkFormat format);
1173
1174 D3D12_TEXTURE_COPY_LOCATION
1175 dzn_buffer_get_copy_loc(const struct dzn_buffer *buf, VkFormat format,
1176 const VkBufferImageCopy2 *info,
1177 VkImageAspectFlagBits aspect,
1178 uint32_t layer);
1179
1180 D3D12_TEXTURE_COPY_LOCATION
1181 dzn_buffer_get_line_copy_loc(const struct dzn_buffer *buf, VkFormat format,
1182 const VkBufferImageCopy2 *region,
1183 const D3D12_TEXTURE_COPY_LOCATION *loc,
1184 uint32_t y, uint32_t z, uint32_t *start_x);
1185
1186 bool
1187 dzn_buffer_supports_region_copy(struct dzn_physical_device *pdev,
1188 const D3D12_TEXTURE_COPY_LOCATION *loc);
1189
1190 struct dzn_buffer_view {
1191 struct vk_object_base base;
1192
1193 const struct dzn_buffer *buffer;
1194
1195 D3D12_SHADER_RESOURCE_VIEW_DESC srv_desc;
1196 D3D12_UNORDERED_ACCESS_VIEW_DESC uav_desc;
1197 int srv_bindless_slot;
1198 int uav_bindless_slot;
1199 };
1200
1201 struct dzn_sampler {
1202 struct vk_object_base base;
1203 D3D12_SAMPLER_DESC2 desc;
1204 D3D12_STATIC_BORDER_COLOR static_border_color;
1205 int bindless_slot;
1206 };
1207
1208 /* This is defined as a macro so that it works for both
1209 * VkImageSubresourceRange and VkImageSubresourceLayers
1210 */
1211 #define dzn_get_layer_count(_image, _range) \
1212 ((_range)->layerCount == VK_REMAINING_ARRAY_LAYERS ? \
1213 (_image)->vk.array_layers - (_range)->baseArrayLayer : (_range)->layerCount)
1214
1215 #define dzn_get_level_count(_image, _range) \
1216 ((_range)->levelCount == VK_REMAINING_MIP_LEVELS ? \
1217 (_image)->vk.mip_levels - (_range)->baseMipLevel : (_range)->levelCount)
1218
1219 DXGI_FORMAT dzn_pipe_to_dxgi_format(enum pipe_format in);
1220 DXGI_FORMAT dzn_get_typeless_dxgi_format(DXGI_FORMAT in);
1221 D3D12_FILTER dzn_translate_sampler_filter(const struct dzn_physical_device *pdev,
1222 const VkSamplerCreateInfo *create_info);
1223 D3D12_COMPARISON_FUNC dzn_translate_compare_op(VkCompareOp in);
1224 void dzn_translate_viewport(D3D12_VIEWPORT *out, const VkViewport *in);
1225 void dzn_translate_rect(D3D12_RECT *out, const VkRect2D *in);
1226
1227 #define dzn_foreach_aspect(aspect, mask) \
1228 for (VkImageAspectFlagBits aspect = VK_IMAGE_ASPECT_COLOR_BIT; \
1229 aspect <= VK_IMAGE_ASPECT_STENCIL_BIT; \
1230 aspect = (VkImageAspectFlagBits)(aspect << 1)) \
1231 if (mask & aspect)
1232
1233 VkResult dzn_wsi_init(struct dzn_physical_device *physical_device);
1234 void dzn_wsi_finish(struct dzn_physical_device *physical_device);
1235
1236 struct dzn_app_info {
1237 const char *app_name;
1238 uint32_t app_version;
1239 const char *engine_name;
1240 uint32_t engine_version;
1241 uint32_t api_version;
1242 };
1243
1244 enum dzn_debug_flags {
1245 DZN_DEBUG_SYNC = 1 << 0,
1246 DZN_DEBUG_NIR = 1 << 1,
1247 DZN_DEBUG_DXIL = 1 << 2,
1248 DZN_DEBUG_WARP = 1 << 3,
1249 DZN_DEBUG_INTERNAL = 1 << 4,
1250 DZN_DEBUG_SIG = 1 << 5,
1251 DZN_DEBUG_GBV = 1 << 6,
1252 DZN_DEBUG_D3D12 = 1 << 7,
1253 DZN_DEBUG_DEBUGGER = 1 << 8,
1254 DZN_DEBUG_REDIRECTS = 1 << 9,
1255 DZN_DEBUG_BINDLESS = 1 << 10,
1256 DZN_DEBUG_NO_BINDLESS = 1 << 11,
1257 DZN_DEBUG_EXPERIMENTAL = 1 << 12,
1258 DZN_DEBUG_MULTIVIEW = 1 << 13,
1259 };
1260
1261 struct dzn_instance {
1262 struct vk_instance vk;
1263
1264 struct dxil_validator *dxil_validator;
1265 struct util_dl_library *d3d12_mod;
1266 ID3D12DeviceFactory *factory;
1267 struct {
1268 PFN_D3D12_SERIALIZE_VERSIONED_ROOT_SIGNATURE serialize_root_sig;
1269 } d3d12;
1270 uint32_t debug_flags;
1271
1272 struct vk_sync_binary_type sync_binary_type;
1273
1274 struct driOptionCache dri_options;
1275 struct driOptionCache available_dri_options;
1276 };
1277
1278 struct dzn_event {
1279 struct vk_object_base base;
1280 ID3D12Fence *fence;
1281 };
1282
1283 struct dzn_sync {
1284 struct vk_sync vk;
1285 ID3D12Fence *fence;
1286 HANDLE export_handle;
1287 };
1288
1289 extern const struct vk_sync_type dzn_sync_type;
1290
1291 struct dzn_query {
1292 D3D12_QUERY_TYPE type;
1293 ID3D12Fence *fence;
1294 uint64_t fence_value;
1295 };
1296
1297 struct dzn_query_pool {
1298 struct vk_object_base base;
1299
1300 D3D12_QUERY_HEAP_TYPE heap_type;
1301 ID3D12QueryHeap *heap;
1302 uint32_t query_count;
1303 struct dzn_query *queries;
1304 mtx_t queries_lock;
1305 ID3D12Resource *resolve_buffer;
1306 ID3D12Resource *collect_buffer;
1307 VkQueryPipelineStatisticFlags pipeline_statistics;
1308 uint32_t query_size;
1309 uint64_t *collect_map;
1310 };
1311
1312 D3D12_QUERY_TYPE
1313 dzn_query_pool_get_query_type(const struct dzn_query_pool *qpool, VkQueryControlFlags flag);
1314
1315 uint32_t
1316 dzn_query_pool_get_result_offset(const struct dzn_query_pool *qpool, uint32_t query);
1317
1318 uint32_t
1319 dzn_query_pool_get_availability_offset(const struct dzn_query_pool *qpool, uint32_t query);
1320
1321 uint32_t
1322 dzn_query_pool_get_result_size(const struct dzn_query_pool *qpool, uint32_t count);
1323
1324 VKAPI_ATTR void VKAPI_CALL
1325 dzn_CmdPipelineBarrier2_enhanced(VkCommandBuffer commandBuffer,
1326 const VkDependencyInfo *info);
1327
1328 VK_DEFINE_HANDLE_CASTS(dzn_cmd_buffer, vk.base, VkCommandBuffer, VK_OBJECT_TYPE_COMMAND_BUFFER)
1329 VK_DEFINE_HANDLE_CASTS(dzn_device, vk.base, VkDevice, VK_OBJECT_TYPE_DEVICE)
1330 VK_DEFINE_HANDLE_CASTS(dzn_instance, vk.base, VkInstance, VK_OBJECT_TYPE_INSTANCE)
1331 VK_DEFINE_HANDLE_CASTS(dzn_physical_device, vk.base, VkPhysicalDevice, VK_OBJECT_TYPE_PHYSICAL_DEVICE)
1332 VK_DEFINE_HANDLE_CASTS(dzn_queue, vk.base, VkQueue, VK_OBJECT_TYPE_QUEUE)
1333
1334 VK_DEFINE_NONDISP_HANDLE_CASTS(dzn_buffer, base, VkBuffer, VK_OBJECT_TYPE_BUFFER)
1335 VK_DEFINE_NONDISP_HANDLE_CASTS(dzn_buffer_view, base, VkBufferView, VK_OBJECT_TYPE_BUFFER_VIEW)
1336 VK_DEFINE_NONDISP_HANDLE_CASTS(dzn_device_memory, base, VkDeviceMemory, VK_OBJECT_TYPE_DEVICE_MEMORY)
1337 VK_DEFINE_NONDISP_HANDLE_CASTS(dzn_descriptor_pool, base, VkDescriptorPool, VK_OBJECT_TYPE_DESCRIPTOR_POOL)
1338 VK_DEFINE_NONDISP_HANDLE_CASTS(dzn_descriptor_set, base, VkDescriptorSet, VK_OBJECT_TYPE_DESCRIPTOR_SET)
1339 VK_DEFINE_NONDISP_HANDLE_CASTS(dzn_descriptor_set_layout, vk.base, VkDescriptorSetLayout, VK_OBJECT_TYPE_DESCRIPTOR_SET_LAYOUT)
1340 VK_DEFINE_NONDISP_HANDLE_CASTS(dzn_descriptor_update_template, base, VkDescriptorUpdateTemplate, VK_OBJECT_TYPE_DESCRIPTOR_UPDATE_TEMPLATE)
1341 VK_DEFINE_NONDISP_HANDLE_CASTS(dzn_event, base, VkEvent, VK_OBJECT_TYPE_EVENT)
1342 VK_DEFINE_NONDISP_HANDLE_CASTS(dzn_image, vk.base, VkImage, VK_OBJECT_TYPE_IMAGE)
1343 VK_DEFINE_NONDISP_HANDLE_CASTS(dzn_image_view, vk.base, VkImageView, VK_OBJECT_TYPE_IMAGE_VIEW)
1344 VK_DEFINE_NONDISP_HANDLE_CASTS(dzn_pipeline, base, VkPipeline, VK_OBJECT_TYPE_PIPELINE)
1345 VK_DEFINE_NONDISP_HANDLE_CASTS(dzn_graphics_pipeline, base.base, VkPipeline, VK_OBJECT_TYPE_PIPELINE)
1346 VK_DEFINE_NONDISP_HANDLE_CASTS(dzn_compute_pipeline, base.base, VkPipeline, VK_OBJECT_TYPE_PIPELINE)
1347 VK_DEFINE_NONDISP_HANDLE_CASTS(dzn_pipeline_layout, vk.base, VkPipelineLayout, VK_OBJECT_TYPE_PIPELINE_LAYOUT)
1348 VK_DEFINE_NONDISP_HANDLE_CASTS(dzn_query_pool, base, VkQueryPool, VK_OBJECT_TYPE_QUERY_POOL)
1349 VK_DEFINE_NONDISP_HANDLE_CASTS(dzn_sampler, base, VkSampler, VK_OBJECT_TYPE_SAMPLER)
1350
1351 #endif /* DZN_PRIVATE_H */
1352