1 /*
2 * Copyright © 2021 Ilia Mirkin
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24 #include <limits.h>
25 #include <stdio.h>
26 #include <stdint.h>
27 #include <stdlib.h>
28 #include <sys/ioctl.h>
29 #include "drm-uapi/nouveau_drm.h"
30 #include "nouveau/nvif/ioctl.h"
31 #include "nouveau/nvif/cl0080.h"
32 #include "drm-shim/drm_shim.h"
33 #include "util/u_math.h"
34
35 #include "../../gallium/drivers/nouveau/nv_object.xml.h"
36 bool drm_shim_driver_prefers_first_render_node = true;
37
38 struct nouveau_device {
39 uint64_t next_offset;
40 };
41
42 static struct nouveau_device nouveau = {
43 .next_offset = 0x1000,
44 };
45
46 struct nouveau_shim_bo {
47 struct shim_bo base;
48 uint64_t offset;
49 };
50
51 static struct nouveau_shim_bo *
nouveau_shim_bo(struct shim_bo * bo)52 nouveau_shim_bo(struct shim_bo *bo)
53 {
54 return (struct nouveau_shim_bo *)bo;
55 }
56
57 struct nouveau_device_info {
58 uint32_t chip_id;
59 };
60
61 static struct nouveau_device_info device_info;
62
63 static int
nouveau_ioctl_noop(int fd,unsigned long request,void * arg)64 nouveau_ioctl_noop(int fd, unsigned long request, void *arg)
65 {
66 return 0;
67 }
68
69 static int
nouveau_ioctl_gem_new(int fd,unsigned long request,void * arg)70 nouveau_ioctl_gem_new(int fd, unsigned long request, void *arg)
71 {
72 struct shim_fd *shim_fd = drm_shim_fd_lookup(fd);
73 struct drm_nouveau_gem_new *create = arg;
74 struct nouveau_shim_bo *bo = calloc(1, sizeof(*bo));
75
76 drm_shim_bo_init(&bo->base, create->info.size);
77
78 assert(ULONG_MAX - nouveau.next_offset > create->info.size);
79
80 create->info.handle = drm_shim_bo_get_handle(shim_fd, &bo->base);
81 create->info.map_handle = drm_shim_bo_get_mmap_offset(shim_fd, &bo->base);
82
83 if (create->align != 0)
84 nouveau.next_offset = align64(nouveau.next_offset, create->align);
85 create->info.offset = nouveau.next_offset;
86 nouveau.next_offset += create->info.size;
87
88 bo->offset = create->info.offset;
89
90 drm_shim_bo_put(&bo->base);
91
92 return 0;
93 }
94
95 static int
nouveau_ioctl_gem_info(int fd,unsigned long request,void * arg)96 nouveau_ioctl_gem_info(int fd, unsigned long request, void *arg)
97 {
98 struct shim_fd *shim_fd = drm_shim_fd_lookup(fd);
99 struct drm_nouveau_gem_info *info = arg;
100 struct nouveau_shim_bo *bo =
101 nouveau_shim_bo(drm_shim_bo_lookup(shim_fd, info->handle));
102 info->map_handle = drm_shim_bo_get_mmap_offset(shim_fd, &bo->base);
103 info->offset = bo->offset;
104 info->size = bo->base.size;
105
106 drm_shim_bo_put(&bo->base);
107
108 return 0;
109 }
110
111 static int
nouveau_ioctl_gem_pushbuf(int fd,unsigned long request,void * arg)112 nouveau_ioctl_gem_pushbuf(int fd, unsigned long request, void *arg)
113 {
114 struct drm_nouveau_gem_pushbuf *submit = arg;
115 submit->vram_available = 3ULL << 30;
116 submit->gart_available = 1ULL << 40;
117 return 0;
118 }
119
120 static int
nouveau_ioctl_channel_alloc(int fd,unsigned long request,void * arg)121 nouveau_ioctl_channel_alloc(int fd, unsigned long request, void *arg)
122 {
123 struct shim_fd *shim_fd = drm_shim_fd_lookup(fd);
124 struct drm_nouveau_channel_alloc *alloc = arg;
125 if (device_info.chip_id == 0x50 || device_info.chip_id >= 0x80)
126 alloc->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM | NOUVEAU_GEM_DOMAIN_GART;
127 else
128 alloc->pushbuf_domains = NOUVEAU_GEM_DOMAIN_GART;
129
130 /* NOTE: this will get leaked since we don't handle the channel
131 * free. However only one channel is created per screen, so impact should
132 * be limited. */
133 struct nouveau_shim_bo *notify = calloc(1, sizeof(*notify));
134 drm_shim_bo_init(¬ify->base, 0x1000);
135 notify->offset = nouveau.next_offset;
136 nouveau.next_offset += 0x1000;
137 alloc->notifier_handle = drm_shim_bo_get_handle(shim_fd, ¬ify->base);
138
139 drm_shim_bo_put(¬ify->base);
140
141 return 0;
142 }
143
144 static int
nouveau_ioctl_get_param(int fd,unsigned long request,void * arg)145 nouveau_ioctl_get_param(int fd, unsigned long request, void *arg)
146 {
147 struct drm_nouveau_getparam *gp = arg;
148
149 switch (gp->param) {
150 case NOUVEAU_GETPARAM_CHIPSET_ID:
151 gp->value = device_info.chip_id;
152 return 0;
153 case NOUVEAU_GETPARAM_PCI_VENDOR:
154 gp->value = 0x10de;
155 return 0;
156 case NOUVEAU_GETPARAM_PCI_DEVICE:
157 gp->value = 0x1004;
158 return 0;
159 case NOUVEAU_GETPARAM_BUS_TYPE:
160 gp->value = 2 /* NV_PCIE */;
161 return 0;
162 case NOUVEAU_GETPARAM_FB_SIZE:
163 gp->value = 3ULL << 30;
164 return 0;
165 case NOUVEAU_GETPARAM_AGP_SIZE:
166 gp->value = 1ULL << 40;
167 return 0;
168 case NOUVEAU_GETPARAM_PTIMER_TIME:
169 gp->value = 0;
170 return 0;
171 case NOUVEAU_GETPARAM_HAS_BO_USAGE:
172 gp->value = 1;
173 return 0;
174 case NOUVEAU_GETPARAM_GRAPH_UNITS:
175 gp->value = 0x01000101;
176 return 0;
177 default:
178 fprintf(stderr, "Unknown DRM_IOCTL_NOUVEAU_GETPARAM %llu\n",
179 (long long unsigned)gp->param);
180 return -1;
181 }
182 }
183
184 static int
nouveau_ioctl_nvif(int fd,unsigned long request,void * arg)185 nouveau_ioctl_nvif(int fd, unsigned long request, void *arg)
186 {
187 struct {
188 struct nvif_ioctl_v0 ioctl;
189 } *args = arg;
190
191 switch (args->ioctl.type) {
192 case NVIF_IOCTL_V0_MTHD: {
193 struct {
194 struct nvif_ioctl_v0 ioctl;
195 struct nvif_ioctl_mthd_v0 mthd;
196 } *mthd = (void *)args;
197 switch (mthd->mthd.method) {
198 case NV_DEVICE_V0_INFO: {
199 struct nv_device_info_v0 *info = (void *)&mthd->mthd.data;
200 info->chipset = device_info.chip_id;
201 info->platform = NV_DEVICE_INFO_V0_PCIE;
202 break;
203 }
204 default:
205 break;
206 }
207 break;
208 }
209 case NVIF_IOCTL_V0_SCLASS: {
210 struct {
211 struct nvif_ioctl_v0 ioctl;
212 struct nvif_ioctl_sclass_v0 sclass;
213 } *sclass = (void *)args;
214
215 if (sclass->sclass.count == 0) {
216 sclass->sclass.count = device_info.chip_id >= 0xe0 ? 4 : 3;
217 return 0;
218 }
219 int idx = 0;
220 /* m2mf */
221 switch (device_info.chip_id & ~0xf) {
222 case 0x170:
223 case 0x160:
224 case 0x140:
225 case 0x130:
226 case 0x120:
227 case 0x110:
228 case 0x100:
229 case 0xf0:
230 sclass->sclass.oclass[idx].oclass = NVF0_P2MF_CLASS;
231 break;
232 case 0xe0:
233 sclass->sclass.oclass[idx].oclass = NVE4_P2MF_CLASS;
234 break;
235 default:
236 sclass->sclass.oclass[idx].oclass = NVC0_M2MF_CLASS;
237 break;
238 }
239 sclass->sclass.oclass[idx].minver = -1;
240 sclass->sclass.oclass[idx].maxver = -1;
241 idx++;
242 if (device_info.chip_id >= 0xe0) {
243 switch (device_info.chip_id & ~0xf) {
244 case 0x170:
245 sclass->sclass.oclass[idx].oclass = AMPERE_DMA_COPY_A;
246 break;
247 case 0x160:
248 sclass->sclass.oclass[idx].oclass = TURING_DMA_COPY_A;
249 break;
250 case 0x140:
251 sclass->sclass.oclass[idx].oclass = VOLTA_DMA_COPY_A;
252 break;
253 case 0x130:
254 sclass->sclass.oclass[idx].oclass = PASCAL_DMA_COPY_A;
255 break;
256 case 0x120:
257 case 0x110:
258 sclass->sclass.oclass[idx].oclass = MAXWELL_DMA_COPY_A;
259 break;
260 case 0x100:
261 case 0xf0:
262 case 0xe0:
263 sclass->sclass.oclass[idx].oclass = KEPLER_DMA_COPY_A;
264 break;
265 }
266 sclass->sclass.oclass[idx].minver = -1;
267 sclass->sclass.oclass[idx].maxver = -1;
268 idx++;
269 }
270 /* 2d */
271 if (device_info.chip_id >= 0x50) {
272 if (device_info.chip_id <= 0xa0)
273 sclass->sclass.oclass[idx].oclass = NV50_2D_CLASS;
274 else
275 sclass->sclass.oclass[idx].oclass = NVC0_2D_CLASS;
276
277 sclass->sclass.oclass[idx].minver = -1;
278 sclass->sclass.oclass[idx].maxver = -1;
279 idx++;
280 }
281 /* 3d */
282 switch (device_info.chip_id & ~0xf) {
283 case 0x170:
284 sclass->sclass.oclass[idx].oclass = GA102_3D_CLASS;
285 break;
286 case 0x160:
287 sclass->sclass.oclass[idx].oclass = TU102_3D_CLASS;
288 break;
289 case 0x140:
290 sclass->sclass.oclass[idx].oclass = GV100_3D_CLASS;
291 break;
292 case 0x130:
293 switch (device_info.chip_id) {
294 case 0x130:
295 case 0x13b:
296 sclass->sclass.oclass[idx].oclass = GP100_3D_CLASS;
297 break;
298 default:
299 sclass->sclass.oclass[idx].oclass = GP102_3D_CLASS;
300 break;
301 }
302 break;
303 case 0x120:
304 sclass->sclass.oclass[idx].oclass = GM200_3D_CLASS;
305 break;
306 case 0x110:
307 sclass->sclass.oclass[idx].oclass = GM107_3D_CLASS;
308 break;
309 case 0x100:
310 case 0xf0:
311 sclass->sclass.oclass[idx].oclass = NVF0_3D_CLASS;
312 break;
313 case 0xe0:
314 switch (device_info.chip_id) {
315 case 0xea:
316 sclass->sclass.oclass[idx].oclass = NVEA_3D_CLASS;
317 break;
318 default:
319 sclass->sclass.oclass[idx].oclass = NVE4_3D_CLASS;
320 break;
321 }
322 break;
323 case 0xd0:
324 sclass->sclass.oclass[idx].oclass = NVC8_3D_CLASS;
325 break;
326 default:
327 case 0xc0:
328 switch (device_info.chip_id) {
329 case 0xc8:
330 sclass->sclass.oclass[idx].oclass = NVC8_3D_CLASS;
331 break;
332 case 0xc1:
333 sclass->sclass.oclass[idx].oclass = NVC1_3D_CLASS;
334 break;
335 default:
336 sclass->sclass.oclass[idx].oclass = NVC0_3D_CLASS;
337 break;
338 }
339 break;
340 }
341 sclass->sclass.oclass[idx].minver = -1;
342 sclass->sclass.oclass[idx].maxver = -1;
343 idx++;
344 switch (device_info.chip_id & ~0xf) {
345 case 0x170:
346 sclass->sclass.oclass[idx].oclass = GA102_COMPUTE_CLASS;
347 break;
348 case 0x160:
349 sclass->sclass.oclass[idx].oclass = TU102_COMPUTE_CLASS;
350 break;
351 case 0x140:
352 sclass->sclass.oclass[idx].oclass = GV100_COMPUTE_CLASS;
353 break;
354 case 0x130:
355 switch (device_info.chip_id) {
356 case 0x130:
357 case 0x13b:
358 sclass->sclass.oclass[idx].oclass = GP100_COMPUTE_CLASS;
359 break;
360 default:
361 sclass->sclass.oclass[idx].oclass = GP104_COMPUTE_CLASS;
362 break;
363 }
364 break;
365 case 0x120:
366 sclass->sclass.oclass[idx].oclass = GM200_COMPUTE_CLASS;
367 break;
368 case 0x110:
369 sclass->sclass.oclass[idx].oclass = GM107_COMPUTE_CLASS;
370 break;
371 case 0x100:
372 case 0xf0:
373 sclass->sclass.oclass[idx].oclass = NVF0_COMPUTE_CLASS;
374 break;
375 case 0xe0:
376 sclass->sclass.oclass[idx].oclass = NVE4_COMPUTE_CLASS;
377 break;
378 default:
379 sclass->sclass.oclass[idx].oclass = NVC0_COMPUTE_CLASS;
380 break;
381 }
382 sclass->sclass.oclass[idx].minver = -1;
383 sclass->sclass.oclass[idx].maxver = -1;
384 break;
385 }
386 default:
387 break;
388 }
389
390 return 0;
391 }
392
393 static ioctl_fn_t driver_ioctls[] = {
394 [DRM_NOUVEAU_GETPARAM] = nouveau_ioctl_get_param,
395 [DRM_NOUVEAU_NVIF] = nouveau_ioctl_nvif,
396 [DRM_NOUVEAU_CHANNEL_ALLOC] = nouveau_ioctl_channel_alloc,
397 [DRM_NOUVEAU_CHANNEL_FREE] = nouveau_ioctl_noop,
398 [DRM_NOUVEAU_GROBJ_ALLOC] = nouveau_ioctl_noop,
399 [DRM_NOUVEAU_NOTIFIEROBJ_ALLOC] = nouveau_ioctl_noop,
400 [DRM_NOUVEAU_GPUOBJ_FREE] = nouveau_ioctl_noop,
401 [DRM_NOUVEAU_GEM_NEW] = nouveau_ioctl_gem_new,
402 [DRM_NOUVEAU_GEM_PUSHBUF] = nouveau_ioctl_gem_pushbuf,
403 [DRM_NOUVEAU_GEM_CPU_PREP] = nouveau_ioctl_noop,
404 [DRM_NOUVEAU_GEM_INFO] = nouveau_ioctl_gem_info,
405 [DRM_NOUVEAU_GEM_CPU_FINI] = nouveau_ioctl_gem_info,
406 [DRM_NOUVEAU_VM_INIT] = nouveau_ioctl_noop,
407 [DRM_NOUVEAU_VM_BIND] = nouveau_ioctl_noop,
408 [DRM_NOUVEAU_EXEC] = nouveau_ioctl_noop,
409 };
410
411 static void
nouveau_driver_get_device_info(void)412 nouveau_driver_get_device_info(void)
413 {
414 const char *env = getenv("NOUVEAU_CHIPSET");
415
416 if (!env) {
417 device_info.chip_id = 0xf0;
418 return;
419 }
420
421 device_info.chip_id = strtol(env, NULL, 16);
422 }
423
424 void
drm_shim_driver_init(void)425 drm_shim_driver_init(void)
426 {
427 shim_device.bus_type = DRM_BUS_PCI;
428 shim_device.driver_name = "nouveau";
429 shim_device.driver_ioctls = driver_ioctls;
430 shim_device.driver_ioctl_count = ARRAY_SIZE(driver_ioctls);
431
432 shim_device.version_major = 1;
433 shim_device.version_minor = 3;
434 shim_device.version_patchlevel = 1;
435
436 nouveau_driver_get_device_info();
437
438 /* Ask userspace to consider all fences completed. */
439 setenv("NOUVEAU_DISABLE_FENCES", "true", true);
440
441 /* nothing looks at the pci id, so fix it to a GTX 780 */
442 static const char uevent_content[] =
443 "DRIVER=nouveau\n"
444 "PCI_CLASS=30000\n"
445 "PCI_ID=10de:1004\n"
446 "PCI_SUBSYS_ID=1028:075B\n"
447 "PCI_SLOT_NAME=0000:01:00.0\n"
448 "MODALIAS=pci:v000010ded00005916sv00001028sd0000075Bbc03sc00i00\n";
449 drm_shim_override_file(uevent_content,
450 "/sys/dev/char/%d:%d/device/uevent",
451 DRM_MAJOR, render_node_minor);
452 drm_shim_override_file("0x0\n",
453 "/sys/dev/char/%d:%d/device/revision",
454 DRM_MAJOR, render_node_minor);
455 drm_shim_override_file("0x10de",
456 "/sys/dev/char/%d:%d/device/vendor",
457 DRM_MAJOR, render_node_minor);
458 drm_shim_override_file("0x10de",
459 "/sys/devices/pci0000:00/0000:01:00.0/vendor");
460 drm_shim_override_file("0x1004",
461 "/sys/dev/char/%d:%d/device/device",
462 DRM_MAJOR, render_node_minor);
463 drm_shim_override_file("0x1004",
464 "/sys/devices/pci0000:00/0000:01:00.0/device");
465 drm_shim_override_file("0x1234",
466 "/sys/dev/char/%d:%d/device/subsystem_vendor",
467 DRM_MAJOR, render_node_minor);
468 drm_shim_override_file("0x1234",
469 "/sys/devices/pci0000:00/0000:01:00.0/subsystem_vendor");
470 drm_shim_override_file("0x1234",
471 "/sys/dev/char/%d:%d/device/subsystem_device",
472 DRM_MAJOR, render_node_minor);
473 drm_shim_override_file("0x1234",
474 "/sys/devices/pci0000:00/0000:01:00.0/subsystem_device");
475 }
476