1 /*
2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
3 * Copyright (C) 2019-2020 Collabora, Ltd.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 */
24
25 #include <err.h>
26 #include <fcntl.h>
27 #include <stdint.h>
28 #include <stdio.h>
29 #include <stdlib.h>
30 #include <sys/mman.h>
31 #include <sys/stat.h>
32 #include <sys/types.h>
33
34 #include "compiler/glsl_types.h"
35 #include "compiler/glsl/glsl_to_nir.h"
36 #include "compiler/nir/nir_builder.h"
37 #include "util/half_float.h"
38 #include "util/list.h"
39 #include "util/u_debug.h"
40 #include "util/u_dynarray.h"
41 #include "util/u_math.h"
42
43 #include "compiler.h"
44 #include "helpers.h"
45 #include "midgard.h"
46 #include "midgard_compile.h"
47 #include "midgard_nir.h"
48 #include "midgard_ops.h"
49 #include "midgard_quirks.h"
50
51 #include "disassemble.h"
52
53 static const struct debug_named_value midgard_debug_options[] = {
54 {"shaders", MIDGARD_DBG_SHADERS, "Dump shaders in NIR and MIR"},
55 {"shaderdb", MIDGARD_DBG_SHADERDB, "Prints shader-db statistics"},
56 {"inorder", MIDGARD_DBG_INORDER, "Disables out-of-order scheduling"},
57 {"verbose", MIDGARD_DBG_VERBOSE, "Dump shaders verbosely"},
58 {"internal", MIDGARD_DBG_INTERNAL, "Dump internal shaders"},
59 DEBUG_NAMED_VALUE_END};
60
61 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug, "MIDGARD_MESA_DEBUG",
62 midgard_debug_options, 0)
63
64 int midgard_debug = 0;
65
66 static midgard_block *
create_empty_block(compiler_context * ctx)67 create_empty_block(compiler_context *ctx)
68 {
69 midgard_block *blk = rzalloc(ctx, midgard_block);
70
71 blk->base.predecessors =
72 _mesa_set_create(blk, _mesa_hash_pointer, _mesa_key_pointer_equal);
73
74 blk->base.name = ctx->block_source_count++;
75
76 return blk;
77 }
78
79 static void
schedule_barrier(compiler_context * ctx)80 schedule_barrier(compiler_context *ctx)
81 {
82 midgard_block *temp = ctx->after_block;
83 ctx->after_block = create_empty_block(ctx);
84 ctx->block_count++;
85 list_addtail(&ctx->after_block->base.link, &ctx->blocks);
86 list_inithead(&ctx->after_block->base.instructions);
87 pan_block_add_successor(&ctx->current_block->base, &ctx->after_block->base);
88 ctx->current_block = ctx->after_block;
89 ctx->after_block = temp;
90 }
91
92 /* Helpers to generate midgard_instruction's using macro magic, since every
93 * driver seems to do it that way */
94
95 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
96
97 #define M_LOAD_STORE(name, store, T) \
98 static midgard_instruction m_##name(unsigned ssa, unsigned address) \
99 { \
100 midgard_instruction i = { \
101 .type = TAG_LOAD_STORE_4, \
102 .mask = 0xF, \
103 .dest = ~0, \
104 .src = {~0, ~0, ~0, ~0}, \
105 .swizzle = SWIZZLE_IDENTITY_4, \
106 .op = midgard_op_##name, \
107 .load_store = \
108 { \
109 .signed_offset = address, \
110 }, \
111 }; \
112 \
113 if (store) { \
114 i.src[0] = ssa; \
115 i.src_types[0] = T; \
116 i.dest_type = T; \
117 } else { \
118 i.dest = ssa; \
119 i.dest_type = T; \
120 } \
121 return i; \
122 }
123
124 #define M_LOAD(name, T) M_LOAD_STORE(name, false, T)
125 #define M_STORE(name, T) M_LOAD_STORE(name, true, T)
126
127 M_LOAD(ld_attr_32, nir_type_uint32);
128 M_LOAD(ld_vary_32, nir_type_uint32);
129 M_LOAD(ld_ubo_u8, nir_type_uint32); /* mandatory extension to 32-bit */
130 M_LOAD(ld_ubo_u16, nir_type_uint32);
131 M_LOAD(ld_ubo_32, nir_type_uint32);
132 M_LOAD(ld_ubo_64, nir_type_uint32);
133 M_LOAD(ld_ubo_128, nir_type_uint32);
134 M_LOAD(ld_u8, nir_type_uint8);
135 M_LOAD(ld_u16, nir_type_uint16);
136 M_LOAD(ld_32, nir_type_uint32);
137 M_LOAD(ld_64, nir_type_uint32);
138 M_LOAD(ld_128, nir_type_uint32);
139 M_STORE(st_u8, nir_type_uint8);
140 M_STORE(st_u16, nir_type_uint16);
141 M_STORE(st_32, nir_type_uint32);
142 M_STORE(st_64, nir_type_uint32);
143 M_STORE(st_128, nir_type_uint32);
144 M_LOAD(ld_tilebuffer_raw, nir_type_uint32);
145 M_LOAD(ld_tilebuffer_16f, nir_type_float16);
146 M_LOAD(ld_tilebuffer_32f, nir_type_float32);
147 M_STORE(st_vary_32, nir_type_uint32);
148 M_LOAD(ld_cubemap_coords, nir_type_uint32);
149 M_LOAD(ldst_mov, nir_type_uint32);
150 M_LOAD(ld_image_32f, nir_type_float32);
151 M_LOAD(ld_image_16f, nir_type_float16);
152 M_LOAD(ld_image_32u, nir_type_uint32);
153 M_LOAD(ld_image_32i, nir_type_int32);
154 M_STORE(st_image_32f, nir_type_float32);
155 M_STORE(st_image_16f, nir_type_float16);
156 M_STORE(st_image_32u, nir_type_uint32);
157 M_STORE(st_image_32i, nir_type_int32);
158 M_LOAD(lea_image, nir_type_uint64);
159
160 #define M_IMAGE(op) \
161 static midgard_instruction op##_image(nir_alu_type type, unsigned val, \
162 unsigned address) \
163 { \
164 switch (type) { \
165 case nir_type_float32: \
166 return m_##op##_image_32f(val, address); \
167 case nir_type_float16: \
168 return m_##op##_image_16f(val, address); \
169 case nir_type_uint32: \
170 return m_##op##_image_32u(val, address); \
171 case nir_type_int32: \
172 return m_##op##_image_32i(val, address); \
173 default: \
174 unreachable("Invalid image type"); \
175 } \
176 }
177
178 M_IMAGE(ld);
179 M_IMAGE(st);
180
181 static midgard_instruction
v_branch(bool conditional,bool invert)182 v_branch(bool conditional, bool invert)
183 {
184 midgard_instruction ins = {
185 .type = TAG_ALU_4,
186 .unit = ALU_ENAB_BRANCH,
187 .compact_branch = true,
188 .branch =
189 {
190 .conditional = conditional,
191 .invert_conditional = invert,
192 },
193 .dest = ~0,
194 .src = {~0, ~0, ~0, ~0},
195 };
196
197 return ins;
198 }
199
200 static void
attach_constants(compiler_context * ctx,midgard_instruction * ins,void * constants,int name)201 attach_constants(compiler_context *ctx, midgard_instruction *ins,
202 void *constants, int name)
203 {
204 ins->has_constants = true;
205 memcpy(&ins->constants, constants, 16);
206 }
207
208 static int
glsl_type_size(const struct glsl_type * type,bool bindless)209 glsl_type_size(const struct glsl_type *type, bool bindless)
210 {
211 return glsl_count_attribute_slots(type, false);
212 }
213
214 static bool
midgard_nir_lower_global_load_instr(nir_builder * b,nir_intrinsic_instr * intr,void * data)215 midgard_nir_lower_global_load_instr(nir_builder *b, nir_intrinsic_instr *intr,
216 void *data)
217 {
218 if (intr->intrinsic != nir_intrinsic_load_global &&
219 intr->intrinsic != nir_intrinsic_load_shared)
220 return false;
221
222 unsigned compsz = intr->def.bit_size;
223 unsigned totalsz = compsz * intr->def.num_components;
224 /* 8, 16, 32, 64 and 128 bit loads don't need to be lowered */
225 if (util_bitcount(totalsz) < 2 && totalsz <= 128)
226 return false;
227
228 b->cursor = nir_before_instr(&intr->instr);
229
230 nir_def *addr = intr->src[0].ssa;
231
232 nir_def *comps[MIR_VEC_COMPONENTS];
233 unsigned ncomps = 0;
234
235 while (totalsz) {
236 unsigned loadsz = MIN2(1 << (util_last_bit(totalsz) - 1), 128);
237 unsigned loadncomps = loadsz / compsz;
238
239 nir_def *load;
240 if (intr->intrinsic == nir_intrinsic_load_global) {
241 load = nir_load_global(b, addr, compsz / 8, loadncomps, compsz);
242 } else {
243 assert(intr->intrinsic == nir_intrinsic_load_shared);
244 nir_intrinsic_instr *shared_load =
245 nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_shared);
246 shared_load->num_components = loadncomps;
247 shared_load->src[0] = nir_src_for_ssa(addr);
248 nir_intrinsic_set_align(shared_load, compsz / 8, 0);
249 nir_intrinsic_set_base(shared_load, nir_intrinsic_base(intr));
250 nir_def_init(&shared_load->instr, &shared_load->def,
251 shared_load->num_components, compsz);
252 nir_builder_instr_insert(b, &shared_load->instr);
253 load = &shared_load->def;
254 }
255
256 for (unsigned i = 0; i < loadncomps; i++)
257 comps[ncomps++] = nir_channel(b, load, i);
258
259 totalsz -= loadsz;
260 addr = nir_iadd_imm(b, addr, loadsz / 8);
261 }
262
263 assert(ncomps == intr->def.num_components);
264 nir_def_rewrite_uses(&intr->def, nir_vec(b, comps, ncomps));
265
266 return true;
267 }
268
269 static bool
midgard_nir_lower_global_load(nir_shader * shader)270 midgard_nir_lower_global_load(nir_shader *shader)
271 {
272 return nir_shader_intrinsics_pass(
273 shader, midgard_nir_lower_global_load_instr,
274 nir_metadata_block_index | nir_metadata_dominance, NULL);
275 }
276
277 static bool
mdg_should_scalarize(const nir_instr * instr,const void * _unused)278 mdg_should_scalarize(const nir_instr *instr, const void *_unused)
279 {
280 const nir_alu_instr *alu = nir_instr_as_alu(instr);
281
282 if (nir_src_bit_size(alu->src[0].src) == 64)
283 return true;
284
285 if (alu->def.bit_size == 64)
286 return true;
287
288 switch (alu->op) {
289 case nir_op_fdot2:
290 case nir_op_umul_high:
291 case nir_op_imul_high:
292 case nir_op_pack_half_2x16:
293 case nir_op_unpack_half_2x16:
294
295 /* The LUT unit is scalar */
296 case nir_op_fsqrt:
297 case nir_op_frcp:
298 case nir_op_frsq:
299 case nir_op_fsin_mdg:
300 case nir_op_fcos_mdg:
301 case nir_op_fexp2:
302 case nir_op_flog2:
303 return true;
304 default:
305 return false;
306 }
307 }
308
309 /* Only vectorize int64 up to vec2 */
310 static uint8_t
midgard_vectorize_filter(const nir_instr * instr,const void * data)311 midgard_vectorize_filter(const nir_instr *instr, const void *data)
312 {
313 if (instr->type != nir_instr_type_alu)
314 return 0;
315
316 const nir_alu_instr *alu = nir_instr_as_alu(instr);
317 int src_bit_size = nir_src_bit_size(alu->src[0].src);
318 int dst_bit_size = alu->def.bit_size;
319
320 if (src_bit_size == 64 || dst_bit_size == 64)
321 return 2;
322
323 return 4;
324 }
325
326 void
midgard_preprocess_nir(nir_shader * nir,unsigned gpu_id)327 midgard_preprocess_nir(nir_shader *nir, unsigned gpu_id)
328 {
329 unsigned quirks = midgard_get_quirks(gpu_id);
330
331 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
332 * (so we don't accidentally duplicate the epilogue since mesa/st has
333 * messed with our I/O quite a bit already).
334 */
335 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
336
337 if (nir->info.stage == MESA_SHADER_VERTEX) {
338 NIR_PASS_V(nir, nir_lower_viewport_transform);
339 NIR_PASS_V(nir, nir_lower_point_size, 1.0, 0.0);
340 }
341
342 NIR_PASS_V(nir, nir_lower_var_copies);
343 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
344 NIR_PASS_V(nir, nir_split_var_copies);
345 NIR_PASS_V(nir, nir_lower_var_copies);
346 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
347 NIR_PASS_V(nir, nir_lower_var_copies);
348 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
349
350 NIR_PASS_V(nir, nir_lower_io, nir_var_shader_in | nir_var_shader_out,
351 glsl_type_size, 0);
352
353 if (nir->info.stage == MESA_SHADER_VERTEX) {
354 /* nir_lower[_explicit]_io is lazy and emits mul+add chains even
355 * for offsets it could figure out are constant. Do some
356 * constant folding before pan_nir_lower_store_component below.
357 */
358 NIR_PASS_V(nir, nir_opt_constant_folding);
359 NIR_PASS_V(nir, pan_nir_lower_store_component);
360 }
361
362 NIR_PASS_V(nir, nir_lower_ssbo);
363 NIR_PASS_V(nir, pan_nir_lower_zs_store);
364
365 NIR_PASS_V(nir, nir_lower_frexp);
366 NIR_PASS_V(nir, midgard_nir_lower_global_load);
367
368 nir_lower_idiv_options idiv_options = {
369 .allow_fp16 = true,
370 };
371
372 NIR_PASS_V(nir, nir_lower_idiv, &idiv_options);
373
374 nir_lower_tex_options lower_tex_options = {
375 .lower_txs_lod = true,
376 .lower_txp = ~0,
377 .lower_tg4_broadcom_swizzle = true,
378 .lower_txd = true,
379 .lower_invalid_implicit_lod = true,
380 };
381
382 NIR_PASS_V(nir, nir_lower_tex, &lower_tex_options);
383 NIR_PASS_V(nir, nir_lower_image_atomics_to_global);
384
385 /* TEX_GRAD fails to apply sampler descriptor settings on some
386 * implementations, requiring a lowering.
387 */
388 if (quirks & MIDGARD_BROKEN_LOD)
389 NIR_PASS_V(nir, midgard_nir_lod_errata);
390
391 /* lower MSAA image operations to 3D load before coordinate lowering */
392 NIR_PASS_V(nir, pan_nir_lower_image_ms);
393
394 /* Midgard image ops coordinates are 16-bit instead of 32-bit */
395 NIR_PASS_V(nir, midgard_nir_lower_image_bitsize);
396
397 if (nir->info.stage == MESA_SHADER_FRAGMENT)
398 NIR_PASS_V(nir, nir_lower_helper_writes, true);
399
400 NIR_PASS_V(nir, pan_lower_helper_invocation);
401 NIR_PASS_V(nir, pan_lower_sample_pos);
402 NIR_PASS_V(nir, midgard_nir_lower_algebraic_early);
403 NIR_PASS_V(nir, nir_lower_alu_to_scalar, mdg_should_scalarize, NULL);
404 NIR_PASS_V(nir, nir_lower_flrp, 16 | 32 | 64, false /* always_precise */);
405 NIR_PASS_V(nir, nir_lower_var_copies);
406 }
407
408 static void
optimise_nir(nir_shader * nir,unsigned quirks,bool is_blend)409 optimise_nir(nir_shader *nir, unsigned quirks, bool is_blend)
410 {
411 bool progress;
412
413 do {
414 progress = false;
415
416 NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
417
418 NIR_PASS(progress, nir, nir_copy_prop);
419 NIR_PASS(progress, nir, nir_opt_remove_phis);
420 NIR_PASS(progress, nir, nir_opt_dce);
421 NIR_PASS(progress, nir, nir_opt_dead_cf);
422 NIR_PASS(progress, nir, nir_opt_cse);
423 NIR_PASS(progress, nir, nir_opt_peephole_select, 64, false, true);
424 NIR_PASS(progress, nir, nir_opt_algebraic);
425 NIR_PASS(progress, nir, nir_opt_constant_folding);
426 NIR_PASS(progress, nir, nir_opt_undef);
427 NIR_PASS(progress, nir, nir_lower_undef_to_zero);
428
429 NIR_PASS(progress, nir, nir_opt_loop_unroll);
430
431 NIR_PASS(progress, nir, nir_opt_vectorize, midgard_vectorize_filter,
432 NULL);
433 } while (progress);
434
435 NIR_PASS_V(nir, nir_lower_alu_to_scalar, mdg_should_scalarize, NULL);
436
437 /* Run after opts so it can hit more */
438 if (!is_blend)
439 NIR_PASS(progress, nir, nir_fuse_io_16);
440
441 do {
442 progress = false;
443
444 NIR_PASS(progress, nir, nir_opt_dce);
445 NIR_PASS(progress, nir, nir_opt_algebraic);
446 NIR_PASS(progress, nir, nir_opt_constant_folding);
447 NIR_PASS(progress, nir, nir_copy_prop);
448 } while (progress);
449
450 NIR_PASS(progress, nir, nir_opt_algebraic_late);
451 NIR_PASS(progress, nir, nir_opt_algebraic_distribute_src_mods);
452
453 /* We implement booleans as 32-bit 0/~0 */
454 NIR_PASS(progress, nir, nir_lower_bool_to_int32);
455
456 /* Now that booleans are lowered, we can run out late opts */
457 NIR_PASS(progress, nir, midgard_nir_lower_algebraic_late);
458 NIR_PASS(progress, nir, midgard_nir_cancel_inot);
459 NIR_PASS_V(nir, midgard_nir_type_csel);
460
461 /* Clean up after late opts */
462 do {
463 progress = false;
464
465 NIR_PASS(progress, nir, nir_opt_dce);
466 NIR_PASS(progress, nir, nir_opt_constant_folding);
467 NIR_PASS(progress, nir, nir_copy_prop);
468 } while (progress);
469
470 /* Backend scheduler is purely local, so do some global optimizations
471 * to reduce register pressure. */
472 nir_move_options move_all = nir_move_const_undef | nir_move_load_ubo |
473 nir_move_load_input | nir_move_comparisons |
474 nir_move_copies | nir_move_load_ssbo;
475
476 NIR_PASS_V(nir, nir_opt_sink, move_all);
477 NIR_PASS_V(nir, nir_opt_move, move_all);
478
479 /* Take us out of SSA */
480 NIR_PASS(progress, nir, nir_convert_from_ssa, true);
481
482 /* We are a vector architecture; write combine where possible */
483 NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest, false);
484 NIR_PASS(progress, nir, nir_lower_vec_to_regs, NULL, NULL);
485
486 NIR_PASS(progress, nir, nir_opt_dce);
487 NIR_PASS_V(nir, nir_trivialize_registers);
488 }
489
490 /* Do not actually emit a load; instead, cache the constant for inlining */
491
492 static void
emit_load_const(compiler_context * ctx,nir_load_const_instr * instr)493 emit_load_const(compiler_context *ctx, nir_load_const_instr *instr)
494 {
495 nir_def def = instr->def;
496
497 midgard_constants *consts = rzalloc(ctx, midgard_constants);
498
499 assert(instr->def.num_components * instr->def.bit_size <=
500 sizeof(*consts) * 8);
501
502 #define RAW_CONST_COPY(bits) \
503 nir_const_value_to_array(consts->u##bits, instr->value, \
504 instr->def.num_components, u##bits)
505
506 switch (instr->def.bit_size) {
507 case 64:
508 RAW_CONST_COPY(64);
509 break;
510 case 32:
511 RAW_CONST_COPY(32);
512 break;
513 case 16:
514 RAW_CONST_COPY(16);
515 break;
516 case 8:
517 RAW_CONST_COPY(8);
518 break;
519 default:
520 unreachable("Invalid bit_size for load_const instruction\n");
521 }
522
523 /* Shifted for SSA, +1 for off-by-one */
524 _mesa_hash_table_u64_insert(ctx->ssa_constants, (def.index << 1) + 1,
525 consts);
526 }
527
528 /* Normally constants are embedded implicitly, but for I/O and such we have to
529 * explicitly emit a move with the constant source */
530
531 static void
emit_explicit_constant(compiler_context * ctx,unsigned node)532 emit_explicit_constant(compiler_context *ctx, unsigned node)
533 {
534 void *constant_value =
535 _mesa_hash_table_u64_search(ctx->ssa_constants, node + 1);
536
537 if (constant_value) {
538 midgard_instruction ins =
539 v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), node);
540 attach_constants(ctx, &ins, constant_value, node + 1);
541 emit_mir_instruction(ctx, ins);
542 }
543 }
544
545 static bool
nir_is_non_scalar_swizzle(nir_alu_src * src,unsigned nr_components)546 nir_is_non_scalar_swizzle(nir_alu_src *src, unsigned nr_components)
547 {
548 unsigned comp = src->swizzle[0];
549
550 for (unsigned c = 1; c < nr_components; ++c) {
551 if (src->swizzle[c] != comp)
552 return true;
553 }
554
555 return false;
556 }
557
558 #define ALU_CASE(nir, _op) \
559 case nir_op_##nir: \
560 op = midgard_alu_op_##_op; \
561 assert(src_bitsize == dst_bitsize); \
562 break;
563
564 #define ALU_CASE_RTZ(nir, _op) \
565 case nir_op_##nir: \
566 op = midgard_alu_op_##_op; \
567 roundmode = MIDGARD_RTZ; \
568 break;
569
570 #define ALU_CHECK_CMP() \
571 assert(src_bitsize == 16 || src_bitsize == 32 || src_bitsize == 64); \
572 assert(dst_bitsize == 16 || dst_bitsize == 32);
573
574 #define ALU_CASE_BCAST(nir, _op, count) \
575 case nir_op_##nir: \
576 op = midgard_alu_op_##_op; \
577 broadcast_swizzle = count; \
578 ALU_CHECK_CMP(); \
579 break;
580
581 #define ALU_CASE_CMP(nir, _op) \
582 case nir_op_##nir: \
583 op = midgard_alu_op_##_op; \
584 ALU_CHECK_CMP(); \
585 break;
586
587 static void
mir_copy_src(midgard_instruction * ins,nir_alu_instr * instr,unsigned i,unsigned to,bool is_int,unsigned bcast_count)588 mir_copy_src(midgard_instruction *ins, nir_alu_instr *instr, unsigned i,
589 unsigned to, bool is_int, unsigned bcast_count)
590 {
591 nir_alu_src src = instr->src[i];
592 unsigned bits = nir_src_bit_size(src.src);
593
594 ins->src[to] = nir_src_index(NULL, &src.src);
595 ins->src_types[to] = nir_op_infos[instr->op].input_types[i] | bits;
596
597 /* Figure out which component we should fill unused channels with. This
598 * doesn't matter too much in the non-broadcast case, but it makes
599 * should that scalar sources are packed with replicated swizzles,
600 * which works around issues seen with the combination of source
601 * expansion and destination shrinking.
602 */
603 unsigned replicate_c = 0;
604 if (bcast_count) {
605 replicate_c = bcast_count - 1;
606 } else {
607 for (unsigned c = 0; c < NIR_MAX_VEC_COMPONENTS; ++c) {
608 if (nir_alu_instr_channel_used(instr, i, c))
609 replicate_c = c;
610 }
611 }
612
613 for (unsigned c = 0; c < NIR_MAX_VEC_COMPONENTS; ++c) {
614 ins->swizzle[to][c] =
615 src.swizzle[((!bcast_count || c < bcast_count) &&
616 nir_alu_instr_channel_used(instr, i, c))
617 ? c
618 : replicate_c];
619 }
620 }
621
622 static void
emit_alu(compiler_context * ctx,nir_alu_instr * instr)623 emit_alu(compiler_context *ctx, nir_alu_instr *instr)
624 {
625 /* Derivatives end up emitted on the texture pipe, not the ALUs. This
626 * is handled elsewhere */
627
628 if (instr->op == nir_op_fddx || instr->op == nir_op_fddy) {
629 midgard_emit_derivatives(ctx, instr);
630 return;
631 }
632
633 unsigned nr_components = instr->def.num_components;
634 unsigned nr_inputs = nir_op_infos[instr->op].num_inputs;
635 unsigned op = 0;
636
637 /* Number of components valid to check for the instruction (the rest
638 * will be forced to the last), or 0 to use as-is. Relevant as
639 * ball-type instructions have a channel count in NIR but are all vec4
640 * in Midgard */
641
642 unsigned broadcast_swizzle = 0;
643
644 /* Should we swap arguments? */
645 bool flip_src12 = false;
646
647 ASSERTED unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
648 unsigned dst_bitsize = instr->def.bit_size;
649
650 enum midgard_roundmode roundmode = MIDGARD_RTE;
651
652 switch (instr->op) {
653 ALU_CASE(fadd, fadd);
654 ALU_CASE(fmul, fmul);
655 ALU_CASE(fmin, fmin);
656 ALU_CASE(fmax, fmax);
657 ALU_CASE(imin, imin);
658 ALU_CASE(imax, imax);
659 ALU_CASE(umin, umin);
660 ALU_CASE(umax, umax);
661 ALU_CASE(ffloor, ffloor);
662 ALU_CASE(fround_even, froundeven);
663 ALU_CASE(ftrunc, ftrunc);
664 ALU_CASE(fceil, fceil);
665 ALU_CASE(fdot3, fdot3);
666 ALU_CASE(fdot4, fdot4);
667 ALU_CASE(iadd, iadd);
668 ALU_CASE(isub, isub);
669 ALU_CASE(iadd_sat, iaddsat);
670 ALU_CASE(isub_sat, isubsat);
671 ALU_CASE(uadd_sat, uaddsat);
672 ALU_CASE(usub_sat, usubsat);
673 ALU_CASE(imul, imul);
674 ALU_CASE(imul_high, imul);
675 ALU_CASE(umul_high, imul);
676 ALU_CASE(uclz, iclz);
677
678 /* Zero shoved as second-arg */
679 ALU_CASE(iabs, iabsdiff);
680
681 ALU_CASE(uabs_isub, iabsdiff);
682 ALU_CASE(uabs_usub, uabsdiff);
683
684 ALU_CASE(mov, imov);
685
686 ALU_CASE_CMP(feq32, feq);
687 ALU_CASE_CMP(fneu32, fne);
688 ALU_CASE_CMP(flt32, flt);
689 ALU_CASE_CMP(ieq32, ieq);
690 ALU_CASE_CMP(ine32, ine);
691 ALU_CASE_CMP(ilt32, ilt);
692 ALU_CASE_CMP(ult32, ult);
693
694 /* We don't have a native b2f32 instruction. Instead, like many
695 * GPUs, we exploit booleans as 0/~0 for false/true, and
696 * correspondingly AND
697 * by 1.0 to do the type conversion. For the moment, prime us
698 * to emit:
699 *
700 * iand [whatever], #0
701 *
702 * At the end of emit_alu (as MIR), we'll fix-up the constant
703 */
704
705 ALU_CASE_CMP(b2f32, iand);
706 ALU_CASE_CMP(b2f16, iand);
707 ALU_CASE_CMP(b2i32, iand);
708
709 ALU_CASE(frcp, frcp);
710 ALU_CASE(frsq, frsqrt);
711 ALU_CASE(fsqrt, fsqrt);
712 ALU_CASE(fexp2, fexp2);
713 ALU_CASE(flog2, flog2);
714
715 ALU_CASE_RTZ(f2i64, f2i_rte);
716 ALU_CASE_RTZ(f2u64, f2u_rte);
717 ALU_CASE_RTZ(i2f64, i2f_rte);
718 ALU_CASE_RTZ(u2f64, u2f_rte);
719
720 ALU_CASE_RTZ(f2i32, f2i_rte);
721 ALU_CASE_RTZ(f2u32, f2u_rte);
722 ALU_CASE_RTZ(i2f32, i2f_rte);
723 ALU_CASE_RTZ(u2f32, u2f_rte);
724
725 ALU_CASE_RTZ(f2i8, f2i_rte);
726 ALU_CASE_RTZ(f2u8, f2u_rte);
727
728 ALU_CASE_RTZ(f2i16, f2i_rte);
729 ALU_CASE_RTZ(f2u16, f2u_rte);
730 ALU_CASE_RTZ(i2f16, i2f_rte);
731 ALU_CASE_RTZ(u2f16, u2f_rte);
732
733 ALU_CASE(fsin_mdg, fsinpi);
734 ALU_CASE(fcos_mdg, fcospi);
735
736 /* We'll get 0 in the second arg, so:
737 * ~a = ~(a | 0) = nor(a, 0) */
738 ALU_CASE(inot, inor);
739 ALU_CASE(iand, iand);
740 ALU_CASE(ior, ior);
741 ALU_CASE(ixor, ixor);
742 ALU_CASE(ishl, ishl);
743 ALU_CASE(ishr, iasr);
744 ALU_CASE(ushr, ilsr);
745
746 ALU_CASE_BCAST(b32all_fequal2, fball_eq, 2);
747 ALU_CASE_BCAST(b32all_fequal3, fball_eq, 3);
748 ALU_CASE_CMP(b32all_fequal4, fball_eq);
749
750 ALU_CASE_BCAST(b32any_fnequal2, fbany_neq, 2);
751 ALU_CASE_BCAST(b32any_fnequal3, fbany_neq, 3);
752 ALU_CASE_CMP(b32any_fnequal4, fbany_neq);
753
754 ALU_CASE_BCAST(b32all_iequal2, iball_eq, 2);
755 ALU_CASE_BCAST(b32all_iequal3, iball_eq, 3);
756 ALU_CASE_CMP(b32all_iequal4, iball_eq);
757
758 ALU_CASE_BCAST(b32any_inequal2, ibany_neq, 2);
759 ALU_CASE_BCAST(b32any_inequal3, ibany_neq, 3);
760 ALU_CASE_CMP(b32any_inequal4, ibany_neq);
761
762 /* Source mods will be shoved in later */
763 ALU_CASE(fabs, fmov);
764 ALU_CASE(fneg, fmov);
765 ALU_CASE(fsat, fmov);
766 ALU_CASE(fsat_signed_mali, fmov);
767 ALU_CASE(fclamp_pos_mali, fmov);
768
769 /* For size conversion, we use a move. Ideally though we would squash
770 * these ops together; maybe that has to happen after in NIR as part of
771 * propagation...? An earlier algebraic pass ensured we step down by
772 * only / exactly one size. If stepping down, we use a dest override to
773 * reduce the size; if stepping up, we use a larger-sized move with a
774 * half source and a sign/zero-extension modifier */
775
776 case nir_op_i2i8:
777 case nir_op_i2i16:
778 case nir_op_i2i32:
779 case nir_op_i2i64:
780 case nir_op_u2u8:
781 case nir_op_u2u16:
782 case nir_op_u2u32:
783 case nir_op_u2u64:
784 case nir_op_f2f16:
785 case nir_op_f2f32:
786 case nir_op_f2f64: {
787 if (instr->op == nir_op_f2f16 || instr->op == nir_op_f2f32 ||
788 instr->op == nir_op_f2f64)
789 op = midgard_alu_op_fmov;
790 else
791 op = midgard_alu_op_imov;
792
793 break;
794 }
795
796 /* For greater-or-equal, we lower to less-or-equal and flip the
797 * arguments */
798
799 case nir_op_fge:
800 case nir_op_fge32:
801 case nir_op_ige32:
802 case nir_op_uge32: {
803 op = instr->op == nir_op_fge ? midgard_alu_op_fle
804 : instr->op == nir_op_fge32 ? midgard_alu_op_fle
805 : instr->op == nir_op_ige32 ? midgard_alu_op_ile
806 : instr->op == nir_op_uge32 ? midgard_alu_op_ule
807 : 0;
808
809 flip_src12 = true;
810 ALU_CHECK_CMP();
811 break;
812 }
813
814 case nir_op_b32csel:
815 case nir_op_b32fcsel_mdg: {
816 bool mixed = nir_is_non_scalar_swizzle(&instr->src[0], nr_components);
817 bool is_float = instr->op == nir_op_b32fcsel_mdg;
818 op = is_float ? (mixed ? midgard_alu_op_fcsel_v : midgard_alu_op_fcsel)
819 : (mixed ? midgard_alu_op_icsel_v : midgard_alu_op_icsel);
820
821 int index = nir_src_index(ctx, &instr->src[0].src);
822 emit_explicit_constant(ctx, index);
823
824 break;
825 }
826
827 case nir_op_unpack_32_2x16:
828 case nir_op_unpack_32_4x8:
829 case nir_op_pack_32_2x16:
830 case nir_op_pack_32_4x8: {
831 op = midgard_alu_op_imov;
832 break;
833 }
834
835 default:
836 mesa_loge("Unhandled ALU op %s\n", nir_op_infos[instr->op].name);
837 assert(0);
838 return;
839 }
840
841 /* Promote imov to fmov if it might help inline a constant */
842 if (op == midgard_alu_op_imov && nir_src_is_const(instr->src[0].src) &&
843 nir_src_bit_size(instr->src[0].src) == 32 &&
844 nir_is_same_comp_swizzle(instr->src[0].swizzle,
845 nir_src_num_components(instr->src[0].src))) {
846 op = midgard_alu_op_fmov;
847 }
848
849 /* Midgard can perform certain modifiers on output of an ALU op */
850
851 unsigned outmod = 0;
852 bool is_int = midgard_is_integer_op(op);
853
854 if (instr->op == nir_op_umul_high || instr->op == nir_op_imul_high) {
855 outmod = midgard_outmod_keephi;
856 } else if (midgard_is_integer_out_op(op)) {
857 outmod = midgard_outmod_keeplo;
858 } else if (instr->op == nir_op_fsat) {
859 outmod = midgard_outmod_clamp_0_1;
860 } else if (instr->op == nir_op_fsat_signed_mali) {
861 outmod = midgard_outmod_clamp_m1_1;
862 } else if (instr->op == nir_op_fclamp_pos_mali) {
863 outmod = midgard_outmod_clamp_0_inf;
864 }
865
866 /* Fetch unit, quirks, etc information */
867 unsigned opcode_props = alu_opcode_props[op].props;
868 bool quirk_flipped_r24 = opcode_props & QUIRK_FLIPPED_R24;
869
870 midgard_instruction ins = {
871 .type = TAG_ALU_4,
872 .dest_type = nir_op_infos[instr->op].output_type | dst_bitsize,
873 .roundmode = roundmode,
874 };
875
876 ins.dest = nir_def_index_with_mask(&instr->def, &ins.mask);
877
878 for (unsigned i = nr_inputs; i < ARRAY_SIZE(ins.src); ++i)
879 ins.src[i] = ~0;
880
881 if (quirk_flipped_r24) {
882 ins.src[0] = ~0;
883 mir_copy_src(&ins, instr, 0, 1, is_int, broadcast_swizzle);
884 } else {
885 for (unsigned i = 0; i < nr_inputs; ++i) {
886 unsigned to = i;
887
888 if (instr->op == nir_op_b32csel || instr->op == nir_op_b32fcsel_mdg) {
889 /* The condition is the first argument; move
890 * the other arguments up one to be a binary
891 * instruction for Midgard with the condition
892 * last */
893
894 if (i == 0)
895 to = 2;
896 else if (flip_src12)
897 to = 2 - i;
898 else
899 to = i - 1;
900 } else if (flip_src12) {
901 to = 1 - to;
902 }
903
904 mir_copy_src(&ins, instr, i, to, is_int, broadcast_swizzle);
905 }
906 }
907
908 if (instr->op == nir_op_fneg || instr->op == nir_op_fabs) {
909 /* Lowered to move */
910 if (instr->op == nir_op_fneg)
911 ins.src_neg[1] ^= true;
912
913 if (instr->op == nir_op_fabs)
914 ins.src_abs[1] = true;
915 }
916
917 ins.op = op;
918 ins.outmod = outmod;
919
920 /* Late fixup for emulated instructions */
921
922 if (instr->op == nir_op_b2f32 || instr->op == nir_op_b2i32) {
923 /* Presently, our second argument is an inline #0 constant.
924 * Switch over to an embedded 1.0 constant (that can't fit
925 * inline, since we're 32-bit, not 16-bit like the inline
926 * constants) */
927
928 ins.has_inline_constant = false;
929 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
930 ins.src_types[1] = nir_type_float32;
931 ins.has_constants = true;
932
933 if (instr->op == nir_op_b2f32)
934 ins.constants.f32[0] = 1.0f;
935 else
936 ins.constants.i32[0] = 1;
937
938 for (unsigned c = 0; c < 16; ++c)
939 ins.swizzle[1][c] = 0;
940 } else if (instr->op == nir_op_b2f16) {
941 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
942 ins.src_types[1] = nir_type_float16;
943 ins.has_constants = true;
944 ins.constants.i16[0] = _mesa_float_to_half(1.0);
945
946 for (unsigned c = 0; c < 16; ++c)
947 ins.swizzle[1][c] = 0;
948 } else if (nr_inputs == 1 && !quirk_flipped_r24) {
949 /* Lots of instructions need a 0 plonked in */
950 ins.has_inline_constant = false;
951 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
952 ins.src_types[1] = ins.src_types[0];
953 ins.has_constants = true;
954 ins.constants.u32[0] = 0;
955
956 for (unsigned c = 0; c < 16; ++c)
957 ins.swizzle[1][c] = 0;
958 } else if (instr->op == nir_op_pack_32_2x16) {
959 ins.dest_type = nir_type_uint16;
960 ins.mask = mask_of(nr_components * 2);
961 ins.is_pack = true;
962 } else if (instr->op == nir_op_pack_32_4x8) {
963 ins.dest_type = nir_type_uint8;
964 ins.mask = mask_of(nr_components * 4);
965 ins.is_pack = true;
966 } else if (instr->op == nir_op_unpack_32_2x16) {
967 ins.dest_type = nir_type_uint32;
968 ins.mask = mask_of(nr_components >> 1);
969 ins.is_pack = true;
970 } else if (instr->op == nir_op_unpack_32_4x8) {
971 ins.dest_type = nir_type_uint32;
972 ins.mask = mask_of(nr_components >> 2);
973 ins.is_pack = true;
974 }
975
976 emit_mir_instruction(ctx, ins);
977 }
978
979 #undef ALU_CASE
980
981 static void
mir_set_intr_mask(nir_instr * instr,midgard_instruction * ins,bool is_read)982 mir_set_intr_mask(nir_instr *instr, midgard_instruction *ins, bool is_read)
983 {
984 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
985 unsigned nir_mask = 0;
986 unsigned dsize = 0;
987
988 if (is_read) {
989 nir_mask = mask_of(nir_intrinsic_dest_components(intr));
990
991 /* Extension is mandatory for 8/16-bit loads */
992 dsize = intr->def.bit_size == 64 ? 64 : 32;
993 } else {
994 nir_mask = nir_intrinsic_write_mask(intr);
995 dsize = OP_IS_COMMON_STORE(ins->op) ? nir_src_bit_size(intr->src[0]) : 32;
996 }
997
998 /* Once we have the NIR mask, we need to normalize to work in 32-bit space */
999 unsigned bytemask = pan_to_bytemask(dsize, nir_mask);
1000 ins->dest_type = nir_type_uint | dsize;
1001 mir_set_bytemask(ins, bytemask);
1002 }
1003
1004 /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
1005 * optimized) versions of UBO #0 */
1006
1007 static midgard_instruction *
emit_ubo_read(compiler_context * ctx,nir_instr * instr,unsigned dest,unsigned offset,nir_src * indirect_offset,unsigned indirect_shift,unsigned index,unsigned nr_comps)1008 emit_ubo_read(compiler_context *ctx, nir_instr *instr, unsigned dest,
1009 unsigned offset, nir_src *indirect_offset,
1010 unsigned indirect_shift, unsigned index, unsigned nr_comps)
1011 {
1012 midgard_instruction ins;
1013
1014 unsigned dest_size = (instr->type == nir_instr_type_intrinsic)
1015 ? nir_instr_as_intrinsic(instr)->def.bit_size
1016 : 32;
1017
1018 unsigned bitsize = dest_size * nr_comps;
1019
1020 /* Pick the smallest intrinsic to avoid out-of-bounds reads */
1021 if (bitsize <= 8)
1022 ins = m_ld_ubo_u8(dest, 0);
1023 else if (bitsize <= 16)
1024 ins = m_ld_ubo_u16(dest, 0);
1025 else if (bitsize <= 32)
1026 ins = m_ld_ubo_32(dest, 0);
1027 else if (bitsize <= 64)
1028 ins = m_ld_ubo_64(dest, 0);
1029 else if (bitsize <= 128)
1030 ins = m_ld_ubo_128(dest, 0);
1031 else
1032 unreachable("Invalid UBO read size");
1033
1034 ins.constants.u32[0] = offset;
1035
1036 if (instr->type == nir_instr_type_intrinsic)
1037 mir_set_intr_mask(instr, &ins, true);
1038
1039 if (indirect_offset) {
1040 ins.src[2] = nir_src_index(ctx, indirect_offset);
1041 ins.src_types[2] = nir_type_uint32;
1042 ins.load_store.index_shift = indirect_shift;
1043
1044 /* X component for the whole swizzle to prevent register
1045 * pressure from ballooning from the extra components */
1046 for (unsigned i = 0; i < ARRAY_SIZE(ins.swizzle[2]); ++i)
1047 ins.swizzle[2][i] = 0;
1048 } else {
1049 ins.load_store.index_reg = REGISTER_LDST_ZERO;
1050 }
1051
1052 if (indirect_offset && !indirect_shift)
1053 mir_set_ubo_offset(&ins, indirect_offset, offset);
1054
1055 midgard_pack_ubo_index_imm(&ins.load_store, index);
1056
1057 return emit_mir_instruction(ctx, ins);
1058 }
1059
1060 /* Globals are like UBOs if you squint. And shared memory is like globals if
1061 * you squint even harder */
1062
1063 static void
emit_global(compiler_context * ctx,nir_instr * instr,bool is_read,unsigned srcdest,nir_src * offset,unsigned seg)1064 emit_global(compiler_context *ctx, nir_instr *instr, bool is_read,
1065 unsigned srcdest, nir_src *offset, unsigned seg)
1066 {
1067 midgard_instruction ins;
1068
1069 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
1070 if (is_read) {
1071 unsigned bitsize = intr->def.bit_size * intr->def.num_components;
1072
1073 switch (bitsize) {
1074 case 8:
1075 ins = m_ld_u8(srcdest, 0);
1076 break;
1077 case 16:
1078 ins = m_ld_u16(srcdest, 0);
1079 break;
1080 case 32:
1081 ins = m_ld_32(srcdest, 0);
1082 break;
1083 case 64:
1084 ins = m_ld_64(srcdest, 0);
1085 break;
1086 case 128:
1087 ins = m_ld_128(srcdest, 0);
1088 break;
1089 default:
1090 unreachable("Invalid global read size");
1091 }
1092
1093 mir_set_intr_mask(instr, &ins, is_read);
1094
1095 /* For anything not aligned on 32bit, make sure we write full
1096 * 32 bits registers. */
1097 if (bitsize & 31) {
1098 unsigned comps_per_32b = 32 / intr->def.bit_size;
1099
1100 for (unsigned c = 0; c < 4 * comps_per_32b; c += comps_per_32b) {
1101 if (!(ins.mask & BITFIELD_RANGE(c, comps_per_32b)))
1102 continue;
1103
1104 unsigned base = ~0;
1105 for (unsigned i = 0; i < comps_per_32b; i++) {
1106 if (ins.mask & BITFIELD_BIT(c + i)) {
1107 base = ins.swizzle[0][c + i];
1108 break;
1109 }
1110 }
1111
1112 assert(base != ~0);
1113
1114 for (unsigned i = 0; i < comps_per_32b; i++) {
1115 if (!(ins.mask & BITFIELD_BIT(c + i))) {
1116 ins.swizzle[0][c + i] = base + i;
1117 ins.mask |= BITFIELD_BIT(c + i);
1118 }
1119 assert(ins.swizzle[0][c + i] == base + i);
1120 }
1121 }
1122 }
1123 } else {
1124 unsigned bitsize =
1125 nir_src_bit_size(intr->src[0]) * nir_src_num_components(intr->src[0]);
1126
1127 if (bitsize == 8)
1128 ins = m_st_u8(srcdest, 0);
1129 else if (bitsize == 16)
1130 ins = m_st_u16(srcdest, 0);
1131 else if (bitsize <= 32)
1132 ins = m_st_32(srcdest, 0);
1133 else if (bitsize <= 64)
1134 ins = m_st_64(srcdest, 0);
1135 else if (bitsize <= 128)
1136 ins = m_st_128(srcdest, 0);
1137 else
1138 unreachable("Invalid global store size");
1139
1140 mir_set_intr_mask(instr, &ins, is_read);
1141 }
1142
1143 mir_set_offset(ctx, &ins, offset, seg);
1144
1145 /* Set a valid swizzle for masked out components */
1146 assert(ins.mask);
1147 unsigned first_component = __builtin_ffs(ins.mask) - 1;
1148
1149 for (unsigned i = 0; i < ARRAY_SIZE(ins.swizzle[0]); ++i) {
1150 if (!(ins.mask & (1 << i)))
1151 ins.swizzle[0][i] = first_component;
1152 }
1153
1154 emit_mir_instruction(ctx, ins);
1155 }
1156
1157 static midgard_load_store_op
translate_atomic_op(nir_atomic_op op)1158 translate_atomic_op(nir_atomic_op op)
1159 {
1160 /* clang-format off */
1161 switch (op) {
1162 case nir_atomic_op_xchg: return midgard_op_atomic_xchg;
1163 case nir_atomic_op_cmpxchg: return midgard_op_atomic_cmpxchg;
1164 case nir_atomic_op_iadd: return midgard_op_atomic_add;
1165 case nir_atomic_op_iand: return midgard_op_atomic_and;
1166 case nir_atomic_op_imax: return midgard_op_atomic_imax;
1167 case nir_atomic_op_imin: return midgard_op_atomic_imin;
1168 case nir_atomic_op_ior: return midgard_op_atomic_or;
1169 case nir_atomic_op_umax: return midgard_op_atomic_umax;
1170 case nir_atomic_op_umin: return midgard_op_atomic_umin;
1171 case nir_atomic_op_ixor: return midgard_op_atomic_xor;
1172 default: unreachable("Unexpected atomic");
1173 }
1174 /* clang-format on */
1175 }
1176
1177 /* Emit an atomic to shared memory or global memory. */
1178 static void
emit_atomic(compiler_context * ctx,nir_intrinsic_instr * instr)1179 emit_atomic(compiler_context *ctx, nir_intrinsic_instr *instr)
1180 {
1181 midgard_load_store_op op =
1182 translate_atomic_op(nir_intrinsic_atomic_op(instr));
1183
1184 nir_alu_type type =
1185 (op == midgard_op_atomic_imin || op == midgard_op_atomic_imax)
1186 ? nir_type_int
1187 : nir_type_uint;
1188
1189 bool is_shared = (instr->intrinsic == nir_intrinsic_shared_atomic) ||
1190 (instr->intrinsic == nir_intrinsic_shared_atomic_swap);
1191
1192 unsigned dest = nir_def_index(&instr->def);
1193 unsigned val = nir_src_index(ctx, &instr->src[1]);
1194 unsigned bitsize = nir_src_bit_size(instr->src[1]);
1195 emit_explicit_constant(ctx, val);
1196
1197 midgard_instruction ins = {
1198 .type = TAG_LOAD_STORE_4,
1199 .mask = 0xF,
1200 .dest = dest,
1201 .src = {~0, ~0, ~0, val},
1202 .src_types = {0, 0, 0, type | bitsize},
1203 .op = op,
1204 };
1205
1206 nir_src *src_offset = nir_get_io_offset_src(instr);
1207
1208 if (op == midgard_op_atomic_cmpxchg) {
1209 unsigned xchg_val = nir_src_index(ctx, &instr->src[2]);
1210 emit_explicit_constant(ctx, xchg_val);
1211
1212 ins.src[2] = val;
1213 ins.src_types[2] = type | bitsize;
1214 ins.src[3] = xchg_val;
1215
1216 if (is_shared) {
1217 ins.load_store.arg_reg = REGISTER_LDST_LOCAL_STORAGE_PTR;
1218 ins.load_store.arg_comp = COMPONENT_Z;
1219 ins.load_store.bitsize_toggle = true;
1220 } else {
1221 for (unsigned i = 0; i < 2; ++i)
1222 ins.swizzle[1][i] = i;
1223
1224 ins.src[1] = nir_src_index(ctx, src_offset);
1225 ins.src_types[1] = nir_type_uint64;
1226 }
1227 } else
1228 mir_set_offset(ctx, &ins, src_offset,
1229 is_shared ? LDST_SHARED : LDST_GLOBAL);
1230
1231 mir_set_intr_mask(&instr->instr, &ins, true);
1232
1233 emit_mir_instruction(ctx, ins);
1234 }
1235
1236 static void
emit_varying_read(compiler_context * ctx,unsigned dest,unsigned offset,unsigned nr_comp,unsigned component,nir_src * indirect_offset,nir_alu_type type,bool flat)1237 emit_varying_read(compiler_context *ctx, unsigned dest, unsigned offset,
1238 unsigned nr_comp, unsigned component,
1239 nir_src *indirect_offset, nir_alu_type type, bool flat)
1240 {
1241 midgard_instruction ins = m_ld_vary_32(dest, PACK_LDST_ATTRIB_OFS(offset));
1242 ins.mask = mask_of(nr_comp);
1243 ins.dest_type = type;
1244
1245 if (type == nir_type_float16) {
1246 /* Ensure we are aligned so we can pack it later */
1247 ins.mask = mask_of(ALIGN_POT(nr_comp, 2));
1248 }
1249
1250 for (unsigned i = 0; i < ARRAY_SIZE(ins.swizzle[0]); ++i)
1251 ins.swizzle[0][i] = MIN2(i + component, COMPONENT_W);
1252
1253 midgard_varying_params p = {
1254 .flat_shading = flat,
1255 .perspective_correction = 1,
1256 .interpolate_sample = true,
1257 };
1258 midgard_pack_varying_params(&ins.load_store, p);
1259
1260 if (indirect_offset) {
1261 ins.src[2] = nir_src_index(ctx, indirect_offset);
1262 ins.src_types[2] = nir_type_uint32;
1263 } else
1264 ins.load_store.index_reg = REGISTER_LDST_ZERO;
1265
1266 ins.load_store.arg_reg = REGISTER_LDST_ZERO;
1267 ins.load_store.index_format = midgard_index_address_u32;
1268
1269 /* For flat shading, we always use .u32 and require 32-bit mode. For
1270 * smooth shading, we use the appropriate floating-point type.
1271 *
1272 * This could be optimized, but it makes it easy to check correctness.
1273 */
1274 if (flat) {
1275 assert(nir_alu_type_get_type_size(type) == 32);
1276 ins.op = midgard_op_ld_vary_32u;
1277 } else {
1278 assert(nir_alu_type_get_base_type(type) == nir_type_float);
1279
1280 ins.op = (nir_alu_type_get_type_size(type) == 32) ? midgard_op_ld_vary_32
1281 : midgard_op_ld_vary_16;
1282 }
1283
1284 emit_mir_instruction(ctx, ins);
1285 }
1286
1287 static midgard_instruction
emit_image_op(compiler_context * ctx,nir_intrinsic_instr * instr)1288 emit_image_op(compiler_context *ctx, nir_intrinsic_instr *instr)
1289 {
1290 enum glsl_sampler_dim dim = nir_intrinsic_image_dim(instr);
1291 unsigned nr_attr = ctx->stage == MESA_SHADER_VERTEX
1292 ? util_bitcount64(ctx->nir->info.inputs_read)
1293 : 0;
1294 unsigned nr_dim = glsl_get_sampler_dim_coordinate_components(dim);
1295 bool is_array = nir_intrinsic_image_array(instr);
1296 bool is_store = instr->intrinsic == nir_intrinsic_image_store;
1297
1298 assert(dim != GLSL_SAMPLER_DIM_MS && "MSAA'd image not lowered");
1299
1300 unsigned coord_reg = nir_src_index(ctx, &instr->src[1]);
1301 emit_explicit_constant(ctx, coord_reg);
1302
1303 nir_src *index = &instr->src[0];
1304 bool is_direct = nir_src_is_const(*index);
1305
1306 /* For image opcodes, address is used as an index into the attribute
1307 * descriptor */
1308 unsigned address = nr_attr;
1309 if (is_direct)
1310 address += nir_src_as_uint(*index);
1311
1312 midgard_instruction ins;
1313 if (is_store) { /* emit st_image_* */
1314 unsigned val = nir_src_index(ctx, &instr->src[3]);
1315 emit_explicit_constant(ctx, val);
1316
1317 nir_alu_type type = nir_intrinsic_src_type(instr);
1318 ins = st_image(type, val, PACK_LDST_ATTRIB_OFS(address));
1319 nir_alu_type base_type = nir_alu_type_get_base_type(type);
1320 ins.src_types[0] = base_type | nir_src_bit_size(instr->src[3]);
1321 } else if (instr->intrinsic == nir_intrinsic_image_texel_address) {
1322 ins =
1323 m_lea_image(nir_def_index(&instr->def), PACK_LDST_ATTRIB_OFS(address));
1324 ins.mask = mask_of(2); /* 64-bit memory address */
1325 } else { /* emit ld_image_* */
1326 nir_alu_type type = nir_intrinsic_dest_type(instr);
1327 ins = ld_image(type, nir_def_index(&instr->def),
1328 PACK_LDST_ATTRIB_OFS(address));
1329 ins.mask = mask_of(nir_intrinsic_dest_components(instr));
1330 ins.dest_type = type;
1331 }
1332
1333 /* Coord reg */
1334 ins.src[1] = coord_reg;
1335 ins.src_types[1] = nir_type_uint16;
1336 if (nr_dim == 3 || is_array) {
1337 ins.load_store.bitsize_toggle = true;
1338 }
1339
1340 /* Image index reg */
1341 if (!is_direct) {
1342 ins.src[2] = nir_src_index(ctx, index);
1343 ins.src_types[2] = nir_type_uint32;
1344 } else
1345 ins.load_store.index_reg = REGISTER_LDST_ZERO;
1346
1347 emit_mir_instruction(ctx, ins);
1348
1349 return ins;
1350 }
1351
1352 static void
emit_attr_read(compiler_context * ctx,unsigned dest,unsigned offset,unsigned nr_comp,nir_alu_type t)1353 emit_attr_read(compiler_context *ctx, unsigned dest, unsigned offset,
1354 unsigned nr_comp, nir_alu_type t)
1355 {
1356 midgard_instruction ins = m_ld_attr_32(dest, PACK_LDST_ATTRIB_OFS(offset));
1357 ins.load_store.arg_reg = REGISTER_LDST_ZERO;
1358 ins.load_store.index_reg = REGISTER_LDST_ZERO;
1359 ins.mask = mask_of(nr_comp);
1360
1361 /* Use the type appropriate load */
1362 switch (t) {
1363 case nir_type_uint:
1364 case nir_type_bool:
1365 ins.op = midgard_op_ld_attr_32u;
1366 break;
1367 case nir_type_int:
1368 ins.op = midgard_op_ld_attr_32i;
1369 break;
1370 case nir_type_float:
1371 ins.op = midgard_op_ld_attr_32;
1372 break;
1373 default:
1374 unreachable("Attempted to load unknown type");
1375 break;
1376 }
1377
1378 emit_mir_instruction(ctx, ins);
1379 }
1380
1381 static unsigned
compute_builtin_arg(nir_intrinsic_op op)1382 compute_builtin_arg(nir_intrinsic_op op)
1383 {
1384 switch (op) {
1385 case nir_intrinsic_load_workgroup_id:
1386 return REGISTER_LDST_GROUP_ID;
1387 case nir_intrinsic_load_local_invocation_id:
1388 return REGISTER_LDST_LOCAL_THREAD_ID;
1389 case nir_intrinsic_load_global_invocation_id:
1390 case nir_intrinsic_load_global_invocation_id_zero_base:
1391 return REGISTER_LDST_GLOBAL_THREAD_ID;
1392 default:
1393 unreachable("Invalid compute paramater loaded");
1394 }
1395 }
1396
1397 static void
emit_fragment_store(compiler_context * ctx,unsigned src,unsigned src_z,unsigned src_s,enum midgard_rt_id rt,unsigned sample_iter)1398 emit_fragment_store(compiler_context *ctx, unsigned src, unsigned src_z,
1399 unsigned src_s, enum midgard_rt_id rt, unsigned sample_iter)
1400 {
1401 assert(rt < ARRAY_SIZE(ctx->writeout_branch));
1402 assert(sample_iter < ARRAY_SIZE(ctx->writeout_branch[0]));
1403
1404 midgard_instruction *br = ctx->writeout_branch[rt][sample_iter];
1405
1406 assert(!br);
1407
1408 emit_explicit_constant(ctx, src);
1409
1410 struct midgard_instruction ins = v_branch(false, false);
1411
1412 bool depth_only = (rt == MIDGARD_ZS_RT);
1413
1414 ins.writeout = depth_only ? 0 : PAN_WRITEOUT_C;
1415
1416 /* Add dependencies */
1417 ins.src[0] = src;
1418 ins.src_types[0] = nir_type_uint32;
1419
1420 if (depth_only)
1421 ins.constants.u32[0] = 0xFF;
1422 else
1423 ins.constants.u32[0] = ((rt - MIDGARD_COLOR_RT0) << 8) | sample_iter;
1424
1425 for (int i = 0; i < 4; ++i)
1426 ins.swizzle[0][i] = i;
1427
1428 if (~src_z) {
1429 emit_explicit_constant(ctx, src_z);
1430 ins.src[2] = src_z;
1431 ins.src_types[2] = nir_type_uint32;
1432 ins.writeout |= PAN_WRITEOUT_Z;
1433 }
1434 if (~src_s) {
1435 emit_explicit_constant(ctx, src_s);
1436 ins.src[3] = src_s;
1437 ins.src_types[3] = nir_type_uint32;
1438 ins.writeout |= PAN_WRITEOUT_S;
1439 }
1440
1441 /* Emit the branch */
1442 br = emit_mir_instruction(ctx, ins);
1443 schedule_barrier(ctx);
1444 ctx->writeout_branch[rt][sample_iter] = br;
1445
1446 /* Push our current location = current block count - 1 = where we'll
1447 * jump to. Maybe a bit too clever for my own good */
1448
1449 br->branch.target_block = ctx->block_count - 1;
1450 }
1451
1452 static void
emit_compute_builtin(compiler_context * ctx,nir_intrinsic_instr * instr)1453 emit_compute_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1454 {
1455 unsigned reg = nir_def_index(&instr->def);
1456 midgard_instruction ins = m_ldst_mov(reg, 0);
1457 ins.mask = mask_of(3);
1458 ins.swizzle[0][3] = COMPONENT_X; /* xyzx */
1459 ins.load_store.arg_reg = compute_builtin_arg(instr->intrinsic);
1460 emit_mir_instruction(ctx, ins);
1461 }
1462
1463 static unsigned
vertex_builtin_arg(nir_intrinsic_op op)1464 vertex_builtin_arg(nir_intrinsic_op op)
1465 {
1466 switch (op) {
1467 case nir_intrinsic_load_vertex_id_zero_base:
1468 return PAN_VERTEX_ID;
1469 case nir_intrinsic_load_instance_id:
1470 return PAN_INSTANCE_ID;
1471 default:
1472 unreachable("Invalid vertex builtin");
1473 }
1474 }
1475
1476 static void
emit_vertex_builtin(compiler_context * ctx,nir_intrinsic_instr * instr)1477 emit_vertex_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1478 {
1479 unsigned reg = nir_def_index(&instr->def);
1480 emit_attr_read(ctx, reg, vertex_builtin_arg(instr->intrinsic), 1,
1481 nir_type_int);
1482 }
1483
1484 static void
emit_special(compiler_context * ctx,nir_intrinsic_instr * instr,unsigned idx)1485 emit_special(compiler_context *ctx, nir_intrinsic_instr *instr, unsigned idx)
1486 {
1487 unsigned reg = nir_def_index(&instr->def);
1488
1489 midgard_instruction ld = m_ld_tilebuffer_raw(reg, 0);
1490 ld.op = midgard_op_ld_special_32u;
1491 ld.load_store.signed_offset = PACK_LDST_SELECTOR_OFS(idx);
1492 ld.load_store.index_reg = REGISTER_LDST_ZERO;
1493
1494 for (int i = 0; i < 4; ++i)
1495 ld.swizzle[0][i] = COMPONENT_X;
1496
1497 emit_mir_instruction(ctx, ld);
1498 }
1499
1500 static void
emit_control_barrier(compiler_context * ctx)1501 emit_control_barrier(compiler_context *ctx)
1502 {
1503 midgard_instruction ins = {
1504 .type = TAG_TEXTURE_4,
1505 .dest = ~0,
1506 .src = {~0, ~0, ~0, ~0},
1507 .op = midgard_tex_op_barrier,
1508 };
1509
1510 emit_mir_instruction(ctx, ins);
1511 }
1512
1513 static uint8_t
output_load_rt_addr(compiler_context * ctx,nir_intrinsic_instr * instr)1514 output_load_rt_addr(compiler_context *ctx, nir_intrinsic_instr *instr)
1515 {
1516 unsigned loc = nir_intrinsic_io_semantics(instr).location;
1517
1518 if (loc >= FRAG_RESULT_DATA0)
1519 return loc - FRAG_RESULT_DATA0;
1520
1521 if (loc == FRAG_RESULT_DEPTH)
1522 return 0x1F;
1523 if (loc == FRAG_RESULT_STENCIL)
1524 return 0x1E;
1525
1526 unreachable("Invalid RT to load from");
1527 }
1528
1529 static void
emit_intrinsic(compiler_context * ctx,nir_intrinsic_instr * instr)1530 emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
1531 {
1532 unsigned offset = 0, reg;
1533
1534 switch (instr->intrinsic) {
1535 case nir_intrinsic_decl_reg:
1536 case nir_intrinsic_store_reg:
1537 /* Always fully consumed */
1538 break;
1539
1540 case nir_intrinsic_load_reg: {
1541 /* NIR guarantees that, for typical isel, this will always be fully
1542 * consumed. However, we also do our own nir_scalar chasing for
1543 * address arithmetic, bypassing the source chasing helpers. So we can end
1544 * up with unconsumed load_register instructions. Translate them here. 99%
1545 * of the time, these moves will be DCE'd away.
1546 */
1547 nir_def *handle = instr->src[0].ssa;
1548
1549 midgard_instruction ins =
1550 v_mov(nir_reg_index(handle), nir_def_index(&instr->def));
1551
1552 ins.dest_type = ins.src_types[1] = nir_type_uint | instr->def.bit_size;
1553
1554 ins.mask = BITFIELD_MASK(instr->def.num_components);
1555 emit_mir_instruction(ctx, ins);
1556 break;
1557 }
1558
1559 case nir_intrinsic_discard_if:
1560 case nir_intrinsic_discard: {
1561 bool conditional = instr->intrinsic == nir_intrinsic_discard_if;
1562 struct midgard_instruction discard = v_branch(conditional, false);
1563 discard.branch.target_type = TARGET_DISCARD;
1564
1565 if (conditional) {
1566 discard.src[0] = nir_src_index(ctx, &instr->src[0]);
1567 discard.src_types[0] = nir_type_uint32;
1568 }
1569
1570 emit_mir_instruction(ctx, discard);
1571 schedule_barrier(ctx);
1572
1573 break;
1574 }
1575
1576 case nir_intrinsic_image_load:
1577 case nir_intrinsic_image_store:
1578 case nir_intrinsic_image_texel_address:
1579 emit_image_op(ctx, instr);
1580 break;
1581
1582 case nir_intrinsic_load_ubo:
1583 case nir_intrinsic_load_global:
1584 case nir_intrinsic_load_global_constant:
1585 case nir_intrinsic_load_shared:
1586 case nir_intrinsic_load_scratch:
1587 case nir_intrinsic_load_input:
1588 case nir_intrinsic_load_interpolated_input: {
1589 bool is_ubo = instr->intrinsic == nir_intrinsic_load_ubo;
1590 bool is_global = instr->intrinsic == nir_intrinsic_load_global ||
1591 instr->intrinsic == nir_intrinsic_load_global_constant;
1592 bool is_shared = instr->intrinsic == nir_intrinsic_load_shared;
1593 bool is_scratch = instr->intrinsic == nir_intrinsic_load_scratch;
1594 bool is_flat = instr->intrinsic == nir_intrinsic_load_input;
1595 bool is_interp =
1596 instr->intrinsic == nir_intrinsic_load_interpolated_input;
1597
1598 /* Get the base type of the intrinsic */
1599 /* TODO: Infer type? Does it matter? */
1600 nir_alu_type t = (is_interp) ? nir_type_float
1601 : (is_flat) ? nir_intrinsic_dest_type(instr)
1602 : nir_type_uint;
1603
1604 t = nir_alu_type_get_base_type(t);
1605
1606 if (!(is_ubo || is_global || is_scratch)) {
1607 offset = nir_intrinsic_base(instr);
1608 }
1609
1610 unsigned nr_comp = nir_intrinsic_dest_components(instr);
1611
1612 nir_src *src_offset = nir_get_io_offset_src(instr);
1613
1614 bool direct = nir_src_is_const(*src_offset);
1615 nir_src *indirect_offset = direct ? NULL : src_offset;
1616
1617 if (direct)
1618 offset += nir_src_as_uint(*src_offset);
1619
1620 /* We may need to apply a fractional offset */
1621 int component =
1622 (is_flat || is_interp) ? nir_intrinsic_component(instr) : 0;
1623 reg = nir_def_index(&instr->def);
1624
1625 if (is_ubo) {
1626 nir_src index = instr->src[0];
1627
1628 /* TODO: Is indirect block number possible? */
1629 assert(nir_src_is_const(index));
1630
1631 uint32_t uindex = nir_src_as_uint(index);
1632 emit_ubo_read(ctx, &instr->instr, reg, offset, indirect_offset, 0,
1633 uindex, nr_comp);
1634 } else if (is_global || is_shared || is_scratch) {
1635 unsigned seg =
1636 is_global ? LDST_GLOBAL : (is_shared ? LDST_SHARED : LDST_SCRATCH);
1637 emit_global(ctx, &instr->instr, true, reg, src_offset, seg);
1638 } else if (ctx->stage == MESA_SHADER_FRAGMENT && !ctx->inputs->is_blend) {
1639 emit_varying_read(ctx, reg, offset, nr_comp, component,
1640 indirect_offset, t | instr->def.bit_size, is_flat);
1641 } else if (ctx->inputs->is_blend) {
1642 /* ctx->blend_input will be precoloured to r0/r2, where
1643 * the input is preloaded */
1644
1645 unsigned *input = offset ? &ctx->blend_src1 : &ctx->blend_input;
1646
1647 if (*input == ~0)
1648 *input = reg;
1649 else
1650 emit_mir_instruction(ctx, v_mov(*input, reg));
1651 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1652 emit_attr_read(ctx, reg, offset, nr_comp, t);
1653 } else {
1654 unreachable("Unknown load");
1655 }
1656
1657 break;
1658 }
1659
1660 /* Handled together with load_interpolated_input */
1661 case nir_intrinsic_load_barycentric_pixel:
1662 case nir_intrinsic_load_barycentric_centroid:
1663 case nir_intrinsic_load_barycentric_sample:
1664 break;
1665
1666 /* Reads 128-bit value raw off the tilebuffer during blending, tasty */
1667
1668 case nir_intrinsic_load_raw_output_pan: {
1669 reg = nir_def_index(&instr->def);
1670
1671 /* T720 and below use different blend opcodes with slightly
1672 * different semantics than T760 and up */
1673
1674 midgard_instruction ld = m_ld_tilebuffer_raw(reg, 0);
1675
1676 unsigned target = output_load_rt_addr(ctx, instr);
1677 ld.load_store.index_comp = target & 0x3;
1678 ld.load_store.index_reg = target >> 2;
1679
1680 if (nir_src_is_const(instr->src[0])) {
1681 unsigned sample = nir_src_as_uint(instr->src[0]);
1682 ld.load_store.arg_comp = sample & 0x3;
1683 ld.load_store.arg_reg = sample >> 2;
1684 } else {
1685 /* Enable sample index via register. */
1686 ld.load_store.signed_offset |= 1;
1687 ld.src[1] = nir_src_index(ctx, &instr->src[0]);
1688 ld.src_types[1] = nir_type_int32;
1689 }
1690
1691 if (ctx->quirks & MIDGARD_OLD_BLEND) {
1692 ld.op = midgard_op_ld_special_32u;
1693 ld.load_store.signed_offset = PACK_LDST_SELECTOR_OFS(16);
1694 ld.load_store.index_reg = REGISTER_LDST_ZERO;
1695 }
1696
1697 emit_mir_instruction(ctx, ld);
1698 break;
1699 }
1700
1701 case nir_intrinsic_load_output: {
1702 reg = nir_def_index(&instr->def);
1703
1704 unsigned bits = instr->def.bit_size;
1705
1706 midgard_instruction ld;
1707 if (bits == 16)
1708 ld = m_ld_tilebuffer_16f(reg, 0);
1709 else
1710 ld = m_ld_tilebuffer_32f(reg, 0);
1711
1712 unsigned index = output_load_rt_addr(ctx, instr);
1713 ld.load_store.index_comp = index & 0x3;
1714 ld.load_store.index_reg = index >> 2;
1715
1716 for (unsigned c = 4; c < 16; ++c)
1717 ld.swizzle[0][c] = 0;
1718
1719 if (ctx->quirks & MIDGARD_OLD_BLEND) {
1720 if (bits == 16)
1721 ld.op = midgard_op_ld_special_16f;
1722 else
1723 ld.op = midgard_op_ld_special_32f;
1724 ld.load_store.signed_offset = PACK_LDST_SELECTOR_OFS(1);
1725 ld.load_store.index_reg = REGISTER_LDST_ZERO;
1726 }
1727
1728 emit_mir_instruction(ctx, ld);
1729 break;
1730 }
1731
1732 case nir_intrinsic_store_output:
1733 case nir_intrinsic_store_combined_output_pan:
1734 assert(nir_src_is_const(instr->src[1]) && "no indirect outputs");
1735
1736 reg = nir_src_index(ctx, &instr->src[0]);
1737
1738 if (ctx->stage == MESA_SHADER_FRAGMENT) {
1739 bool combined =
1740 instr->intrinsic == nir_intrinsic_store_combined_output_pan;
1741
1742 enum midgard_rt_id rt;
1743
1744 unsigned reg_z = ~0, reg_s = ~0, reg_2 = ~0;
1745 unsigned writeout = PAN_WRITEOUT_C;
1746 if (combined) {
1747 writeout = nir_intrinsic_component(instr);
1748 if (writeout & PAN_WRITEOUT_Z)
1749 reg_z = nir_src_index(ctx, &instr->src[2]);
1750 if (writeout & PAN_WRITEOUT_S)
1751 reg_s = nir_src_index(ctx, &instr->src[3]);
1752 if (writeout & PAN_WRITEOUT_2)
1753 reg_2 = nir_src_index(ctx, &instr->src[4]);
1754 }
1755
1756 if (writeout & PAN_WRITEOUT_C) {
1757 nir_io_semantics sem = nir_intrinsic_io_semantics(instr);
1758
1759 rt = MIDGARD_COLOR_RT0 + (sem.location - FRAG_RESULT_DATA0);
1760 } else {
1761 rt = MIDGARD_ZS_RT;
1762 }
1763
1764 /* Dual-source blend writeout is done by leaving the
1765 * value in r2 for the blend shader to use. */
1766 if (~reg_2) {
1767 emit_explicit_constant(ctx, reg_2);
1768
1769 unsigned out = make_compiler_temp(ctx);
1770
1771 midgard_instruction ins = v_mov(reg_2, out);
1772 emit_mir_instruction(ctx, ins);
1773
1774 ctx->blend_src1 = out;
1775 }
1776
1777 emit_fragment_store(ctx, reg, reg_z, reg_s, rt, 0);
1778 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1779 assert(instr->intrinsic == nir_intrinsic_store_output);
1780
1781 /* We should have been vectorized, though we don't
1782 * currently check that st_vary is emitted only once
1783 * per slot (this is relevant, since there's not a mask
1784 * parameter available on the store [set to 0 by the
1785 * blob]). We do respect the component by adjusting the
1786 * swizzle. If this is a constant source, we'll need to
1787 * emit that explicitly. */
1788
1789 emit_explicit_constant(ctx, reg);
1790
1791 offset = nir_intrinsic_base(instr) + nir_src_as_uint(instr->src[1]);
1792
1793 unsigned dst_component = nir_intrinsic_component(instr);
1794 unsigned nr_comp = nir_src_num_components(instr->src[0]);
1795
1796 /* ABI: Format controlled by the attribute descriptor.
1797 * This simplifies flat shading, although it prevents
1798 * certain (unimplemented) 16-bit optimizations.
1799 *
1800 * In particular, it lets the driver handle internal
1801 * TGSI shaders that set flat in the VS but smooth in
1802 * the FS. This matches our handling on Bifrost.
1803 */
1804 bool auto32 = true;
1805 assert(nir_alu_type_get_type_size(nir_intrinsic_src_type(instr)) ==
1806 32);
1807
1808 /* ABI: varyings in the secondary attribute table */
1809 bool secondary_table = true;
1810
1811 midgard_instruction st =
1812 m_st_vary_32(reg, PACK_LDST_ATTRIB_OFS(offset));
1813 st.load_store.arg_reg = REGISTER_LDST_ZERO;
1814 st.load_store.index_reg = REGISTER_LDST_ZERO;
1815
1816 /* Attribute instruction uses these 2-bits for the
1817 * a32 and table bits, pack this specially.
1818 */
1819 st.load_store.index_format =
1820 (auto32 ? (1 << 0) : 0) | (secondary_table ? (1 << 1) : 0);
1821
1822 /* nir_intrinsic_component(store_intr) encodes the
1823 * destination component start. Source component offset
1824 * adjustment is taken care of in
1825 * install_registers_instr(), when offset_swizzle() is
1826 * called.
1827 */
1828 unsigned src_component = COMPONENT_X;
1829
1830 assert(nr_comp > 0);
1831 for (unsigned i = 0; i < ARRAY_SIZE(st.swizzle); ++i) {
1832 st.swizzle[0][i] = src_component;
1833 if (i >= dst_component && i < dst_component + nr_comp - 1)
1834 src_component++;
1835 }
1836
1837 emit_mir_instruction(ctx, st);
1838 } else {
1839 unreachable("Unknown store");
1840 }
1841
1842 break;
1843
1844 /* Special case of store_output for lowered blend shaders */
1845 case nir_intrinsic_store_raw_output_pan: {
1846 assert(ctx->stage == MESA_SHADER_FRAGMENT);
1847 reg = nir_src_index(ctx, &instr->src[0]);
1848
1849 nir_io_semantics sem = nir_intrinsic_io_semantics(instr);
1850 assert(sem.location >= FRAG_RESULT_DATA0);
1851 unsigned rt = sem.location - FRAG_RESULT_DATA0;
1852
1853 emit_fragment_store(ctx, reg, ~0, ~0, rt + MIDGARD_COLOR_RT0,
1854 nir_intrinsic_base(instr));
1855 break;
1856 }
1857
1858 case nir_intrinsic_store_global:
1859 case nir_intrinsic_store_shared:
1860 case nir_intrinsic_store_scratch:
1861 reg = nir_src_index(ctx, &instr->src[0]);
1862 emit_explicit_constant(ctx, reg);
1863
1864 unsigned seg;
1865 if (instr->intrinsic == nir_intrinsic_store_global)
1866 seg = LDST_GLOBAL;
1867 else if (instr->intrinsic == nir_intrinsic_store_shared)
1868 seg = LDST_SHARED;
1869 else
1870 seg = LDST_SCRATCH;
1871
1872 emit_global(ctx, &instr->instr, false, reg, &instr->src[1], seg);
1873 break;
1874
1875 case nir_intrinsic_load_workgroup_id:
1876 case nir_intrinsic_load_local_invocation_id:
1877 case nir_intrinsic_load_global_invocation_id:
1878 case nir_intrinsic_load_global_invocation_id_zero_base:
1879 emit_compute_builtin(ctx, instr);
1880 break;
1881
1882 case nir_intrinsic_load_vertex_id_zero_base:
1883 case nir_intrinsic_load_instance_id:
1884 emit_vertex_builtin(ctx, instr);
1885 break;
1886
1887 case nir_intrinsic_load_sample_mask_in:
1888 emit_special(ctx, instr, 96);
1889 break;
1890
1891 case nir_intrinsic_load_sample_id:
1892 emit_special(ctx, instr, 97);
1893 break;
1894
1895 case nir_intrinsic_barrier:
1896 if (nir_intrinsic_execution_scope(instr) != SCOPE_NONE) {
1897 schedule_barrier(ctx);
1898 emit_control_barrier(ctx);
1899 schedule_barrier(ctx);
1900 } else if (nir_intrinsic_memory_scope(instr) != SCOPE_NONE) {
1901 /* Midgard doesn't seem to want special handling, though we do need to
1902 * take care when scheduling to avoid incorrect reordering.
1903 *
1904 * Note this is an "else if" since the handling for the execution scope
1905 * case already covers the case when both scopes are present.
1906 */
1907 schedule_barrier(ctx);
1908 }
1909 break;
1910
1911 case nir_intrinsic_shared_atomic:
1912 case nir_intrinsic_shared_atomic_swap:
1913 case nir_intrinsic_global_atomic:
1914 case nir_intrinsic_global_atomic_swap:
1915 emit_atomic(ctx, instr);
1916 break;
1917
1918 default:
1919 fprintf(stderr, "Unhandled intrinsic %s\n",
1920 nir_intrinsic_infos[instr->intrinsic].name);
1921 assert(0);
1922 break;
1923 }
1924 }
1925
1926 /* Returns dimension with 0 special casing cubemaps */
1927 static unsigned
midgard_tex_format(enum glsl_sampler_dim dim)1928 midgard_tex_format(enum glsl_sampler_dim dim)
1929 {
1930 switch (dim) {
1931 case GLSL_SAMPLER_DIM_1D:
1932 case GLSL_SAMPLER_DIM_BUF:
1933 return 1;
1934
1935 case GLSL_SAMPLER_DIM_2D:
1936 case GLSL_SAMPLER_DIM_MS:
1937 case GLSL_SAMPLER_DIM_EXTERNAL:
1938 case GLSL_SAMPLER_DIM_RECT:
1939 return 2;
1940
1941 case GLSL_SAMPLER_DIM_3D:
1942 return 3;
1943
1944 case GLSL_SAMPLER_DIM_CUBE:
1945 return 0;
1946
1947 default:
1948 unreachable("Unknown sampler dim type");
1949 }
1950 }
1951
1952 /* Tries to attach an explicit LOD or bias as a constant. Returns whether this
1953 * was successful */
1954
1955 static bool
pan_attach_constant_bias(compiler_context * ctx,nir_src lod,midgard_texture_word * word)1956 pan_attach_constant_bias(compiler_context *ctx, nir_src lod,
1957 midgard_texture_word *word)
1958 {
1959 /* To attach as constant, it has to *be* constant */
1960
1961 if (!nir_src_is_const(lod))
1962 return false;
1963
1964 float f = nir_src_as_float(lod);
1965
1966 /* Break into fixed-point */
1967 signed lod_int = f;
1968 float lod_frac = f - lod_int;
1969
1970 /* Carry over negative fractions */
1971 if (lod_frac < 0.0) {
1972 lod_int--;
1973 lod_frac += 1.0;
1974 }
1975
1976 /* Encode */
1977 word->bias = float_to_ubyte(lod_frac);
1978 word->bias_int = lod_int;
1979
1980 return true;
1981 }
1982
1983 static enum mali_texture_mode
mdg_texture_mode(nir_tex_instr * instr)1984 mdg_texture_mode(nir_tex_instr *instr)
1985 {
1986 if (instr->op == nir_texop_tg4 && instr->is_shadow)
1987 return TEXTURE_GATHER_SHADOW;
1988 else if (instr->op == nir_texop_tg4)
1989 return TEXTURE_GATHER_X + instr->component;
1990 else if (instr->is_shadow)
1991 return TEXTURE_SHADOW;
1992 else
1993 return TEXTURE_NORMAL;
1994 }
1995
1996 static void
set_tex_coord(compiler_context * ctx,nir_tex_instr * instr,midgard_instruction * ins)1997 set_tex_coord(compiler_context *ctx, nir_tex_instr *instr,
1998 midgard_instruction *ins)
1999 {
2000 int coord_idx = nir_tex_instr_src_index(instr, nir_tex_src_coord);
2001
2002 assert(coord_idx >= 0);
2003
2004 int comparator_idx = nir_tex_instr_src_index(instr, nir_tex_src_comparator);
2005 int ms_idx = nir_tex_instr_src_index(instr, nir_tex_src_ms_index);
2006 assert(comparator_idx < 0 || ms_idx < 0);
2007 int ms_or_comparator_idx = ms_idx >= 0 ? ms_idx : comparator_idx;
2008
2009 unsigned coords = nir_src_index(ctx, &instr->src[coord_idx].src);
2010
2011 emit_explicit_constant(ctx, coords);
2012
2013 ins->src_types[1] = nir_tex_instr_src_type(instr, coord_idx) |
2014 nir_src_bit_size(instr->src[coord_idx].src);
2015
2016 unsigned nr_comps = instr->coord_components;
2017 unsigned written_mask = 0, write_mask = 0;
2018
2019 /* Initialize all components to coord.x which is expected to always be
2020 * present. Swizzle is updated below based on the texture dimension
2021 * and extra attributes that are packed in the coordinate argument.
2022 */
2023 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; c++)
2024 ins->swizzle[1][c] = COMPONENT_X;
2025
2026 /* Shadow ref value is part of the coordinates if there's no comparator
2027 * source, in that case it's always placed in the last component.
2028 * Midgard wants the ref value in coord.z.
2029 */
2030 if (instr->is_shadow && comparator_idx < 0) {
2031 ins->swizzle[1][COMPONENT_Z] = --nr_comps;
2032 write_mask |= 1 << COMPONENT_Z;
2033 }
2034
2035 /* The array index is the last component if there's no shadow ref value
2036 * or second last if there's one. We already decremented the number of
2037 * components to account for the shadow ref value above.
2038 * Midgard wants the array index in coord.w.
2039 */
2040 if (instr->is_array) {
2041 ins->swizzle[1][COMPONENT_W] = --nr_comps;
2042 write_mask |= 1 << COMPONENT_W;
2043 }
2044
2045 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2046 /* texelFetch is undefined on samplerCube */
2047 assert(ins->op != midgard_tex_op_fetch);
2048
2049 ins->src[1] = make_compiler_temp_reg(ctx);
2050
2051 /* For cubemaps, we use a special ld/st op to select the face
2052 * and copy the xy into the texture register
2053 */
2054 midgard_instruction ld = m_ld_cubemap_coords(ins->src[1], 0);
2055 ld.src[1] = coords;
2056 ld.src_types[1] = ins->src_types[1];
2057 ld.mask = 0x3; /* xy */
2058 ld.load_store.bitsize_toggle = true;
2059 ld.swizzle[1][3] = COMPONENT_X;
2060 emit_mir_instruction(ctx, ld);
2061
2062 /* We packed cube coordiates (X,Y,Z) into (X,Y), update the
2063 * written mask accordingly and decrement the number of
2064 * components
2065 */
2066 nr_comps--;
2067 written_mask |= 3;
2068 }
2069
2070 /* Now flag tex coord components that have not been written yet */
2071 write_mask |= mask_of(nr_comps) & ~written_mask;
2072 for (unsigned c = 0; c < nr_comps; c++)
2073 ins->swizzle[1][c] = c;
2074
2075 /* Sample index and shadow ref are expected in coord.z */
2076 if (ms_or_comparator_idx >= 0) {
2077 assert(!((write_mask | written_mask) & (1 << COMPONENT_Z)));
2078
2079 unsigned sample_or_ref =
2080 nir_src_index(ctx, &instr->src[ms_or_comparator_idx].src);
2081
2082 emit_explicit_constant(ctx, sample_or_ref);
2083
2084 if (ins->src[1] == ~0)
2085 ins->src[1] = make_compiler_temp_reg(ctx);
2086
2087 midgard_instruction mov = v_mov(sample_or_ref, ins->src[1]);
2088
2089 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; c++)
2090 mov.swizzle[1][c] = COMPONENT_X;
2091
2092 mov.mask = 1 << COMPONENT_Z;
2093 written_mask |= 1 << COMPONENT_Z;
2094 ins->swizzle[1][COMPONENT_Z] = COMPONENT_Z;
2095 emit_mir_instruction(ctx, mov);
2096 }
2097
2098 /* Texelfetch coordinates uses all four elements (xyz/index) regardless
2099 * of texture dimensionality, which means it's necessary to zero the
2100 * unused components to keep everything happy.
2101 */
2102 if (ins->op == midgard_tex_op_fetch && (written_mask | write_mask) != 0xF) {
2103 if (ins->src[1] == ~0)
2104 ins->src[1] = make_compiler_temp_reg(ctx);
2105
2106 /* mov index.zw, #0, or generalized */
2107 midgard_instruction mov =
2108 v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), ins->src[1]);
2109 mov.has_constants = true;
2110 mov.mask = (written_mask | write_mask) ^ 0xF;
2111 emit_mir_instruction(ctx, mov);
2112 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; c++) {
2113 if (mov.mask & (1 << c))
2114 ins->swizzle[1][c] = c;
2115 }
2116 }
2117
2118 if (ins->src[1] == ~0) {
2119 /* No temporary reg created, use the src coords directly */
2120 ins->src[1] = coords;
2121 } else if (write_mask) {
2122 /* Move the remaining coordinates to the temporary reg */
2123 midgard_instruction mov = v_mov(coords, ins->src[1]);
2124
2125 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; c++) {
2126 if ((1 << c) & write_mask) {
2127 mov.swizzle[1][c] = ins->swizzle[1][c];
2128 ins->swizzle[1][c] = c;
2129 } else {
2130 mov.swizzle[1][c] = COMPONENT_X;
2131 }
2132 }
2133
2134 mov.mask = write_mask;
2135 emit_mir_instruction(ctx, mov);
2136 }
2137 }
2138
2139 static void
emit_texop_native(compiler_context * ctx,nir_tex_instr * instr,unsigned midgard_texop)2140 emit_texop_native(compiler_context *ctx, nir_tex_instr *instr,
2141 unsigned midgard_texop)
2142 {
2143 int texture_index = instr->texture_index;
2144 int sampler_index = instr->sampler_index;
2145
2146 /* If txf is used, we assume there is a valid sampler bound at index 0. Use
2147 * it for txf operations, since there may be no other valid samplers. This is
2148 * a workaround: txf does not require a sampler in NIR (so sampler_index is
2149 * undefined) but we need one in the hardware. This is ABI with the driver.
2150 */
2151 if (!nir_tex_instr_need_sampler(instr))
2152 sampler_index = 0;
2153
2154 midgard_instruction ins = {
2155 .type = TAG_TEXTURE_4,
2156 .mask = 0xF,
2157 .dest = nir_def_index(&instr->def),
2158 .src = {~0, ~0, ~0, ~0},
2159 .dest_type = instr->dest_type,
2160 .swizzle = SWIZZLE_IDENTITY_4,
2161 .outmod = midgard_outmod_none,
2162 .op = midgard_texop,
2163 .texture = {
2164 .format = midgard_tex_format(instr->sampler_dim),
2165 .texture_handle = texture_index,
2166 .sampler_handle = sampler_index,
2167 .mode = mdg_texture_mode(instr),
2168 }};
2169
2170 if (instr->is_shadow && !instr->is_new_style_shadow &&
2171 instr->op != nir_texop_tg4)
2172 for (int i = 0; i < 4; ++i)
2173 ins.swizzle[0][i] = COMPONENT_X;
2174
2175 for (unsigned i = 0; i < instr->num_srcs; ++i) {
2176 int index = nir_src_index(ctx, &instr->src[i].src);
2177 unsigned sz = nir_src_bit_size(instr->src[i].src);
2178 nir_alu_type T = nir_tex_instr_src_type(instr, i) | sz;
2179
2180 switch (instr->src[i].src_type) {
2181 case nir_tex_src_coord:
2182 set_tex_coord(ctx, instr, &ins);
2183 break;
2184
2185 case nir_tex_src_bias:
2186 case nir_tex_src_lod: {
2187 /* Try as a constant if we can */
2188
2189 bool is_txf = midgard_texop == midgard_tex_op_fetch;
2190 if (!is_txf &&
2191 pan_attach_constant_bias(ctx, instr->src[i].src, &ins.texture))
2192 break;
2193
2194 ins.texture.lod_register = true;
2195 ins.src[2] = index;
2196 ins.src_types[2] = T;
2197
2198 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
2199 ins.swizzle[2][c] = COMPONENT_X;
2200
2201 emit_explicit_constant(ctx, index);
2202
2203 break;
2204 };
2205
2206 case nir_tex_src_offset: {
2207 ins.texture.offset_register = true;
2208 ins.src[3] = index;
2209 ins.src_types[3] = T;
2210
2211 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
2212 ins.swizzle[3][c] = (c > COMPONENT_Z) ? 0 : c;
2213
2214 emit_explicit_constant(ctx, index);
2215 break;
2216 };
2217
2218 case nir_tex_src_comparator:
2219 case nir_tex_src_ms_index:
2220 /* Nothing to do, handled in set_tex_coord() */
2221 break;
2222
2223 default: {
2224 fprintf(stderr, "Unknown texture source type: %d\n",
2225 instr->src[i].src_type);
2226 assert(0);
2227 }
2228 }
2229 }
2230
2231 emit_mir_instruction(ctx, ins);
2232 }
2233
2234 static void
emit_tex(compiler_context * ctx,nir_tex_instr * instr)2235 emit_tex(compiler_context *ctx, nir_tex_instr *instr)
2236 {
2237 switch (instr->op) {
2238 case nir_texop_tex:
2239 case nir_texop_txb:
2240 emit_texop_native(ctx, instr, midgard_tex_op_normal);
2241 break;
2242 case nir_texop_txl:
2243 case nir_texop_tg4:
2244 emit_texop_native(ctx, instr, midgard_tex_op_gradient);
2245 break;
2246 case nir_texop_txf:
2247 case nir_texop_txf_ms:
2248 emit_texop_native(ctx, instr, midgard_tex_op_fetch);
2249 break;
2250 default: {
2251 fprintf(stderr, "Unhandled texture op: %d\n", instr->op);
2252 assert(0);
2253 }
2254 }
2255 }
2256
2257 static void
emit_jump(compiler_context * ctx,nir_jump_instr * instr)2258 emit_jump(compiler_context *ctx, nir_jump_instr *instr)
2259 {
2260 switch (instr->type) {
2261 case nir_jump_break: {
2262 /* Emit a branch out of the loop */
2263 struct midgard_instruction br = v_branch(false, false);
2264 br.branch.target_type = TARGET_BREAK;
2265 br.branch.target_break = ctx->current_loop_depth;
2266 emit_mir_instruction(ctx, br);
2267 break;
2268 }
2269
2270 default:
2271 unreachable("Unhandled jump");
2272 }
2273 }
2274
2275 static void
emit_instr(compiler_context * ctx,struct nir_instr * instr)2276 emit_instr(compiler_context *ctx, struct nir_instr *instr)
2277 {
2278 switch (instr->type) {
2279 case nir_instr_type_load_const:
2280 emit_load_const(ctx, nir_instr_as_load_const(instr));
2281 break;
2282
2283 case nir_instr_type_intrinsic:
2284 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
2285 break;
2286
2287 case nir_instr_type_alu:
2288 emit_alu(ctx, nir_instr_as_alu(instr));
2289 break;
2290
2291 case nir_instr_type_tex:
2292 emit_tex(ctx, nir_instr_as_tex(instr));
2293 break;
2294
2295 case nir_instr_type_jump:
2296 emit_jump(ctx, nir_instr_as_jump(instr));
2297 break;
2298
2299 case nir_instr_type_undef:
2300 /* Spurious */
2301 break;
2302
2303 default:
2304 unreachable("Unhandled instruction type");
2305 }
2306 }
2307
2308 /* ALU instructions can inline or embed constants, which decreases register
2309 * pressure and saves space. */
2310
2311 #define CONDITIONAL_ATTACH(idx) \
2312 { \
2313 void *entry = \
2314 _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[idx] + 1); \
2315 \
2316 if (entry) { \
2317 attach_constants(ctx, alu, entry, alu->src[idx] + 1); \
2318 alu->src[idx] = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
2319 } \
2320 }
2321
2322 static void
inline_alu_constants(compiler_context * ctx,midgard_block * block)2323 inline_alu_constants(compiler_context *ctx, midgard_block *block)
2324 {
2325 mir_foreach_instr_in_block(block, alu) {
2326 /* Other instructions cannot inline constants */
2327 if (alu->type != TAG_ALU_4)
2328 continue;
2329 if (alu->compact_branch)
2330 continue;
2331
2332 /* If there is already a constant here, we can do nothing */
2333 if (alu->has_constants)
2334 continue;
2335
2336 CONDITIONAL_ATTACH(0);
2337
2338 if (!alu->has_constants) {
2339 CONDITIONAL_ATTACH(1)
2340 } else if (!alu->inline_constant) {
2341 /* Corner case: _two_ vec4 constants, for instance with a
2342 * csel. For this case, we can only use a constant
2343 * register for one, we'll have to emit a move for the
2344 * other. */
2345
2346 void *entry =
2347 _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[1] + 1);
2348 unsigned scratch = make_compiler_temp(ctx);
2349
2350 if (entry) {
2351 midgard_instruction ins =
2352 v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), scratch);
2353 attach_constants(ctx, &ins, entry, alu->src[1] + 1);
2354
2355 /* Set the source */
2356 alu->src[1] = scratch;
2357
2358 /* Inject us -before- the last instruction which set r31, if
2359 * possible.
2360 */
2361 midgard_instruction *first = list_first_entry(
2362 &block->base.instructions, midgard_instruction, link);
2363
2364 if (alu == first) {
2365 mir_insert_instruction_before(ctx, alu, ins);
2366 } else {
2367 mir_insert_instruction_before(ctx, mir_prev_op(alu), ins);
2368 }
2369 }
2370 }
2371 }
2372 }
2373
2374 unsigned
max_bitsize_for_alu(midgard_instruction * ins)2375 max_bitsize_for_alu(midgard_instruction *ins)
2376 {
2377 unsigned max_bitsize = 0;
2378 for (int i = 0; i < MIR_SRC_COUNT; i++) {
2379 if (ins->src[i] == ~0)
2380 continue;
2381 unsigned src_bitsize = nir_alu_type_get_type_size(ins->src_types[i]);
2382 max_bitsize = MAX2(src_bitsize, max_bitsize);
2383 }
2384 unsigned dst_bitsize = nir_alu_type_get_type_size(ins->dest_type);
2385 max_bitsize = MAX2(dst_bitsize, max_bitsize);
2386
2387 /* We emulate 8-bit as 16-bit for simplicity of packing */
2388 max_bitsize = MAX2(max_bitsize, 16);
2389
2390 /* We don't have fp16 LUTs, so we'll want to emit code like:
2391 *
2392 * vlut.fsinr hr0, hr0
2393 *
2394 * where both input and output are 16-bit but the operation is carried
2395 * out in 32-bit
2396 */
2397
2398 switch (ins->op) {
2399 case midgard_alu_op_fsqrt:
2400 case midgard_alu_op_frcp:
2401 case midgard_alu_op_frsqrt:
2402 case midgard_alu_op_fsinpi:
2403 case midgard_alu_op_fcospi:
2404 case midgard_alu_op_fexp2:
2405 case midgard_alu_op_flog2:
2406 max_bitsize = MAX2(max_bitsize, 32);
2407 break;
2408
2409 default:
2410 break;
2411 }
2412
2413 /* High implies computing at a higher bitsize, e.g umul_high of 32-bit
2414 * requires computing at 64-bit */
2415 if (midgard_is_integer_out_op(ins->op) &&
2416 ins->outmod == midgard_outmod_keephi) {
2417 max_bitsize *= 2;
2418 assert(max_bitsize <= 64);
2419 }
2420
2421 return max_bitsize;
2422 }
2423
2424 midgard_reg_mode
reg_mode_for_bitsize(unsigned bitsize)2425 reg_mode_for_bitsize(unsigned bitsize)
2426 {
2427 switch (bitsize) {
2428 /* use 16 pipe for 8 since we don't support vec16 yet */
2429 case 8:
2430 case 16:
2431 return midgard_reg_mode_16;
2432 case 32:
2433 return midgard_reg_mode_32;
2434 case 64:
2435 return midgard_reg_mode_64;
2436 default:
2437 unreachable("invalid bit size");
2438 }
2439 }
2440
2441 /* Midgard supports two types of constants, embedded constants (128-bit) and
2442 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2443 * constants can be demoted to inline constants, for space savings and
2444 * sometimes a performance boost */
2445
2446 static void
embedded_to_inline_constant(compiler_context * ctx,midgard_block * block)2447 embedded_to_inline_constant(compiler_context *ctx, midgard_block *block)
2448 {
2449 mir_foreach_instr_in_block(block, ins) {
2450 if (!ins->has_constants)
2451 continue;
2452 if (ins->has_inline_constant)
2453 continue;
2454
2455 unsigned max_bitsize = max_bitsize_for_alu(ins);
2456
2457 /* We can inline 32-bit (sometimes) or 16-bit (usually) */
2458 bool is_16 = max_bitsize == 16;
2459 bool is_32 = max_bitsize == 32;
2460
2461 if (!(is_16 || is_32))
2462 continue;
2463
2464 /* src1 cannot be an inline constant due to encoding
2465 * restrictions. So, if possible we try to flip the arguments
2466 * in that case */
2467
2468 int op = ins->op;
2469
2470 if (ins->src[0] == SSA_FIXED_REGISTER(REGISTER_CONSTANT) &&
2471 alu_opcode_props[op].props & OP_COMMUTES) {
2472 mir_flip(ins);
2473 }
2474
2475 if (ins->src[1] == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
2476 /* Component is from the swizzle. Take a nonzero component */
2477 assert(ins->mask);
2478 unsigned first_comp = ffs(ins->mask) - 1;
2479 unsigned component = ins->swizzle[1][first_comp];
2480
2481 /* Scale constant appropriately, if we can legally */
2482 int16_t scaled_constant = 0;
2483
2484 if (is_16) {
2485 scaled_constant = ins->constants.u16[component];
2486 } else if (midgard_is_integer_op(op)) {
2487 scaled_constant = ins->constants.u32[component];
2488
2489 /* Constant overflow after resize */
2490 if (scaled_constant != ins->constants.u32[component])
2491 continue;
2492 } else {
2493 float original = ins->constants.f32[component];
2494 scaled_constant = _mesa_float_to_half(original);
2495
2496 /* Check for loss of precision. If this is
2497 * mediump, we don't care, but for a highp
2498 * shader, we need to pay attention. NIR
2499 * doesn't yet tell us which mode we're in!
2500 * Practically this prevents most constants
2501 * from being inlined, sadly. */
2502
2503 float fp32 = _mesa_half_to_float(scaled_constant);
2504
2505 if (fp32 != original)
2506 continue;
2507 }
2508
2509 /* Should've been const folded */
2510 if (ins->src_abs[1] || ins->src_neg[1])
2511 continue;
2512
2513 /* Make sure that the constant is not itself a vector
2514 * by checking if all accessed values are the same. */
2515
2516 const midgard_constants *cons = &ins->constants;
2517 uint32_t value = is_16 ? cons->u16[component] : cons->u32[component];
2518
2519 bool is_vector = false;
2520 unsigned mask = effective_writemask(ins->op, ins->mask);
2521
2522 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c) {
2523 /* We only care if this component is actually used */
2524 if (!(mask & (1 << c)))
2525 continue;
2526
2527 uint32_t test = is_16 ? cons->u16[ins->swizzle[1][c]]
2528 : cons->u32[ins->swizzle[1][c]];
2529
2530 if (test != value) {
2531 is_vector = true;
2532 break;
2533 }
2534 }
2535
2536 if (is_vector)
2537 continue;
2538
2539 /* Get rid of the embedded constant */
2540 ins->has_constants = false;
2541 ins->src[1] = ~0;
2542 ins->has_inline_constant = true;
2543 ins->inline_constant = scaled_constant;
2544 }
2545 }
2546 }
2547
2548 /* Dead code elimination for branches at the end of a block - only one branch
2549 * per block is legal semantically */
2550
2551 static void
midgard_cull_dead_branch(compiler_context * ctx,midgard_block * block)2552 midgard_cull_dead_branch(compiler_context *ctx, midgard_block *block)
2553 {
2554 bool branched = false;
2555
2556 mir_foreach_instr_in_block_safe(block, ins) {
2557 if (!midgard_is_branch_unit(ins->unit))
2558 continue;
2559
2560 if (branched)
2561 mir_remove_instruction(ins);
2562
2563 branched = true;
2564 }
2565 }
2566
2567 /* We want to force the invert on AND/OR to the second slot to legalize into
2568 * iandnot/iornot. The relevant patterns are for AND (and OR respectively)
2569 *
2570 * ~a & #b = ~a & ~(#~b)
2571 * ~a & b = b & ~a
2572 */
2573
2574 static void
midgard_legalize_invert(compiler_context * ctx,midgard_block * block)2575 midgard_legalize_invert(compiler_context *ctx, midgard_block *block)
2576 {
2577 mir_foreach_instr_in_block(block, ins) {
2578 if (ins->type != TAG_ALU_4)
2579 continue;
2580
2581 if (ins->op != midgard_alu_op_iand && ins->op != midgard_alu_op_ior)
2582 continue;
2583
2584 if (ins->src_invert[1] || !ins->src_invert[0])
2585 continue;
2586
2587 if (ins->has_inline_constant) {
2588 /* ~(#~a) = ~(~#a) = a, so valid, and forces both
2589 * inverts on */
2590 ins->inline_constant = ~ins->inline_constant;
2591 ins->src_invert[1] = true;
2592 } else {
2593 /* Flip to the right invert order. Note
2594 * has_inline_constant false by assumption on the
2595 * branch, so flipping makes sense. */
2596 mir_flip(ins);
2597 }
2598 }
2599 }
2600
2601 static unsigned
emit_fragment_epilogue(compiler_context * ctx,unsigned rt,unsigned sample_iter)2602 emit_fragment_epilogue(compiler_context *ctx, unsigned rt, unsigned sample_iter)
2603 {
2604 /* Loop to ourselves */
2605 midgard_instruction *br = ctx->writeout_branch[rt][sample_iter];
2606 struct midgard_instruction ins = v_branch(false, false);
2607 ins.writeout = br->writeout;
2608 ins.branch.target_block = ctx->block_count - 1;
2609 ins.constants.u32[0] = br->constants.u32[0];
2610 memcpy(&ins.src_types, &br->src_types, sizeof(ins.src_types));
2611 emit_mir_instruction(ctx, ins);
2612
2613 ctx->current_block->epilogue = true;
2614 schedule_barrier(ctx);
2615 return ins.branch.target_block;
2616 }
2617
2618 static midgard_block *
emit_block_init(compiler_context * ctx)2619 emit_block_init(compiler_context *ctx)
2620 {
2621 midgard_block *this_block = ctx->after_block;
2622 ctx->after_block = NULL;
2623
2624 if (!this_block)
2625 this_block = create_empty_block(ctx);
2626
2627 list_addtail(&this_block->base.link, &ctx->blocks);
2628
2629 this_block->scheduled = false;
2630 ++ctx->block_count;
2631
2632 /* Set up current block */
2633 list_inithead(&this_block->base.instructions);
2634 ctx->current_block = this_block;
2635
2636 return this_block;
2637 }
2638
2639 static midgard_block *
emit_block(compiler_context * ctx,nir_block * block)2640 emit_block(compiler_context *ctx, nir_block *block)
2641 {
2642 midgard_block *this_block = emit_block_init(ctx);
2643
2644 nir_foreach_instr(instr, block) {
2645 emit_instr(ctx, instr);
2646 ++ctx->instruction_count;
2647 }
2648
2649 return this_block;
2650 }
2651
2652 static midgard_block *emit_cf_list(struct compiler_context *ctx,
2653 struct exec_list *list);
2654
2655 static void
emit_if(struct compiler_context * ctx,nir_if * nif)2656 emit_if(struct compiler_context *ctx, nir_if *nif)
2657 {
2658 midgard_block *before_block = ctx->current_block;
2659
2660 /* Speculatively emit the branch, but we can't fill it in until later */
2661 EMIT(branch, true, true);
2662 midgard_instruction *then_branch = mir_last_in_block(ctx->current_block);
2663 then_branch->src[0] = nir_src_index(ctx, &nif->condition);
2664 then_branch->src_types[0] = nir_type_uint32;
2665
2666 /* Emit the two subblocks. */
2667 midgard_block *then_block = emit_cf_list(ctx, &nif->then_list);
2668 midgard_block *end_then_block = ctx->current_block;
2669
2670 /* Emit a jump from the end of the then block to the end of the else */
2671 EMIT(branch, false, false);
2672 midgard_instruction *then_exit = mir_last_in_block(ctx->current_block);
2673
2674 /* Emit second block, and check if it's empty */
2675
2676 int else_idx = ctx->block_count;
2677 int count_in = ctx->instruction_count;
2678 midgard_block *else_block = emit_cf_list(ctx, &nif->else_list);
2679 midgard_block *end_else_block = ctx->current_block;
2680 int after_else_idx = ctx->block_count;
2681
2682 /* Now that we have the subblocks emitted, fix up the branches */
2683
2684 assert(then_block);
2685 assert(else_block);
2686
2687 if (ctx->instruction_count == count_in) {
2688 /* The else block is empty, so don't emit an exit jump */
2689 mir_remove_instruction(then_exit);
2690 then_branch->branch.target_block = after_else_idx;
2691 } else {
2692 then_branch->branch.target_block = else_idx;
2693 then_exit->branch.target_block = after_else_idx;
2694 }
2695
2696 /* Wire up the successors */
2697
2698 ctx->after_block = create_empty_block(ctx);
2699
2700 pan_block_add_successor(&before_block->base, &then_block->base);
2701 pan_block_add_successor(&before_block->base, &else_block->base);
2702
2703 pan_block_add_successor(&end_then_block->base, &ctx->after_block->base);
2704 pan_block_add_successor(&end_else_block->base, &ctx->after_block->base);
2705 }
2706
2707 static void
emit_loop(struct compiler_context * ctx,nir_loop * nloop)2708 emit_loop(struct compiler_context *ctx, nir_loop *nloop)
2709 {
2710 assert(!nir_loop_has_continue_construct(nloop));
2711
2712 /* Remember where we are */
2713 midgard_block *start_block = ctx->current_block;
2714
2715 /* Allocate a loop number, growing the current inner loop depth */
2716 int loop_idx = ++ctx->current_loop_depth;
2717
2718 /* Get index from before the body so we can loop back later */
2719 int start_idx = ctx->block_count;
2720
2721 /* Emit the body itself */
2722 midgard_block *loop_block = emit_cf_list(ctx, &nloop->body);
2723
2724 /* Branch back to loop back */
2725 struct midgard_instruction br_back = v_branch(false, false);
2726 br_back.branch.target_block = start_idx;
2727 emit_mir_instruction(ctx, br_back);
2728
2729 /* Mark down that branch in the graph. */
2730 pan_block_add_successor(&start_block->base, &loop_block->base);
2731 pan_block_add_successor(&ctx->current_block->base, &loop_block->base);
2732
2733 /* Find the index of the block about to follow us (note: we don't add
2734 * one; blocks are 0-indexed so we get a fencepost problem) */
2735 int break_block_idx = ctx->block_count;
2736
2737 /* Fix up the break statements we emitted to point to the right place,
2738 * now that we can allocate a block number for them */
2739 ctx->after_block = create_empty_block(ctx);
2740
2741 mir_foreach_block_from(ctx, start_block, _block) {
2742 mir_foreach_instr_in_block(((midgard_block *)_block), ins) {
2743 if (ins->type != TAG_ALU_4)
2744 continue;
2745 if (!ins->compact_branch)
2746 continue;
2747
2748 /* We found a branch -- check the type to see if we need to do anything
2749 */
2750 if (ins->branch.target_type != TARGET_BREAK)
2751 continue;
2752
2753 /* It's a break! Check if it's our break */
2754 if (ins->branch.target_break != loop_idx)
2755 continue;
2756
2757 /* Okay, cool, we're breaking out of this loop.
2758 * Rewrite from a break to a goto */
2759
2760 ins->branch.target_type = TARGET_GOTO;
2761 ins->branch.target_block = break_block_idx;
2762
2763 pan_block_add_successor(_block, &ctx->after_block->base);
2764 }
2765 }
2766
2767 /* Now that we've finished emitting the loop, free up the depth again
2768 * so we play nice with recursion amid nested loops */
2769 --ctx->current_loop_depth;
2770
2771 /* Dump loop stats */
2772 ++ctx->loop_count;
2773 }
2774
2775 static midgard_block *
emit_cf_list(struct compiler_context * ctx,struct exec_list * list)2776 emit_cf_list(struct compiler_context *ctx, struct exec_list *list)
2777 {
2778 midgard_block *start_block = NULL;
2779
2780 foreach_list_typed(nir_cf_node, node, node, list) {
2781 switch (node->type) {
2782 case nir_cf_node_block: {
2783 midgard_block *block = emit_block(ctx, nir_cf_node_as_block(node));
2784
2785 if (!start_block)
2786 start_block = block;
2787
2788 break;
2789 }
2790
2791 case nir_cf_node_if:
2792 emit_if(ctx, nir_cf_node_as_if(node));
2793 break;
2794
2795 case nir_cf_node_loop:
2796 emit_loop(ctx, nir_cf_node_as_loop(node));
2797 break;
2798
2799 case nir_cf_node_function:
2800 assert(0);
2801 break;
2802 }
2803 }
2804
2805 return start_block;
2806 }
2807
2808 /* Due to lookahead, we need to report the first tag executed in the command
2809 * stream and in branch targets. An initial block might be empty, so iterate
2810 * until we find one that 'works' */
2811
2812 unsigned
midgard_get_first_tag_from_block(compiler_context * ctx,unsigned block_idx)2813 midgard_get_first_tag_from_block(compiler_context *ctx, unsigned block_idx)
2814 {
2815 midgard_block *initial_block = mir_get_block(ctx, block_idx);
2816
2817 mir_foreach_block_from(ctx, initial_block, _v) {
2818 midgard_block *v = (midgard_block *)_v;
2819 if (v->quadword_count) {
2820 midgard_bundle *initial_bundle =
2821 util_dynarray_element(&v->bundles, midgard_bundle, 0);
2822
2823 return initial_bundle->tag;
2824 }
2825 }
2826
2827 /* Default to a tag 1 which will break from the shader, in case we jump
2828 * to the exit block (i.e. `return` in a compute shader) */
2829
2830 return 1;
2831 }
2832
2833 /* For each fragment writeout instruction, generate a writeout loop to
2834 * associate with it */
2835
2836 static void
mir_add_writeout_loops(compiler_context * ctx)2837 mir_add_writeout_loops(compiler_context *ctx)
2838 {
2839 for (unsigned rt = 0; rt < ARRAY_SIZE(ctx->writeout_branch); ++rt) {
2840 for (unsigned s = 0; s < MIDGARD_MAX_SAMPLE_ITER; ++s) {
2841 midgard_instruction *br = ctx->writeout_branch[rt][s];
2842 if (!br)
2843 continue;
2844
2845 unsigned popped = br->branch.target_block;
2846 pan_block_add_successor(&(mir_get_block(ctx, popped - 1)->base),
2847 &ctx->current_block->base);
2848 br->branch.target_block = emit_fragment_epilogue(ctx, rt, s);
2849 br->branch.target_type = TARGET_GOTO;
2850
2851 /* If we have more RTs, we'll need to restore back after our
2852 * loop terminates */
2853 midgard_instruction *next_br = NULL;
2854
2855 if ((s + 1) < MIDGARD_MAX_SAMPLE_ITER)
2856 next_br = ctx->writeout_branch[rt][s + 1];
2857
2858 if (!next_br && (rt + 1) < ARRAY_SIZE(ctx->writeout_branch))
2859 next_br = ctx->writeout_branch[rt + 1][0];
2860
2861 if (next_br) {
2862 midgard_instruction uncond = v_branch(false, false);
2863 uncond.branch.target_block = popped;
2864 uncond.branch.target_type = TARGET_GOTO;
2865 emit_mir_instruction(ctx, uncond);
2866 pan_block_add_successor(&ctx->current_block->base,
2867 &(mir_get_block(ctx, popped)->base));
2868 schedule_barrier(ctx);
2869 } else {
2870 /* We're last, so we can terminate here */
2871 br->last_writeout = true;
2872 }
2873 }
2874 }
2875 }
2876
2877 void
midgard_compile_shader_nir(nir_shader * nir,const struct panfrost_compile_inputs * inputs,struct util_dynarray * binary,struct pan_shader_info * info)2878 midgard_compile_shader_nir(nir_shader *nir,
2879 const struct panfrost_compile_inputs *inputs,
2880 struct util_dynarray *binary,
2881 struct pan_shader_info *info)
2882 {
2883 midgard_debug = debug_get_option_midgard_debug();
2884
2885 /* TODO: Bound against what? */
2886 compiler_context *ctx = rzalloc(NULL, compiler_context);
2887
2888 ctx->inputs = inputs;
2889 ctx->nir = nir;
2890 ctx->info = info;
2891 ctx->stage = nir->info.stage;
2892 ctx->blend_input = ~0;
2893 ctx->blend_src1 = ~0;
2894 ctx->quirks = midgard_get_quirks(inputs->gpu_id);
2895
2896 /* Initialize at a global (not block) level hash tables */
2897
2898 ctx->ssa_constants = _mesa_hash_table_u64_create(ctx);
2899
2900 /* Collect varyings after lowering I/O */
2901 pan_nir_collect_varyings(nir, info);
2902
2903 /* Optimisation passes */
2904 optimise_nir(nir, ctx->quirks, inputs->is_blend);
2905
2906 bool skip_internal = nir->info.internal;
2907 skip_internal &= !(midgard_debug & MIDGARD_DBG_INTERNAL);
2908
2909 if (midgard_debug & MIDGARD_DBG_SHADERS && !skip_internal)
2910 nir_print_shader(nir, stdout);
2911
2912 info->tls_size = nir->scratch_size;
2913
2914 nir_foreach_function_with_impl(func, impl, nir) {
2915 list_inithead(&ctx->blocks);
2916 ctx->block_count = 0;
2917 ctx->func = func;
2918
2919 if (nir->info.outputs_read && !inputs->is_blend) {
2920 emit_block_init(ctx);
2921
2922 struct midgard_instruction wait = v_branch(false, false);
2923 wait.branch.target_type = TARGET_TILEBUF_WAIT;
2924
2925 emit_mir_instruction(ctx, wait);
2926
2927 ++ctx->instruction_count;
2928 }
2929
2930 emit_cf_list(ctx, &impl->body);
2931 break; /* TODO: Multi-function shaders */
2932 }
2933
2934 /* Per-block lowering before opts */
2935
2936 mir_foreach_block(ctx, _block) {
2937 midgard_block *block = (midgard_block *)_block;
2938 inline_alu_constants(ctx, block);
2939 embedded_to_inline_constant(ctx, block);
2940 }
2941 /* MIR-level optimizations */
2942
2943 bool progress = false;
2944
2945 do {
2946 progress = false;
2947 progress |= midgard_opt_dead_code_eliminate(ctx);
2948 progress |= midgard_opt_prop(ctx);
2949
2950 mir_foreach_block(ctx, _block) {
2951 midgard_block *block = (midgard_block *)_block;
2952 progress |= midgard_opt_copy_prop(ctx, block);
2953 progress |= midgard_opt_combine_projection(ctx, block);
2954 progress |= midgard_opt_varying_projection(ctx, block);
2955 }
2956 } while (progress);
2957
2958 mir_foreach_block(ctx, _block) {
2959 midgard_block *block = (midgard_block *)_block;
2960 midgard_lower_derivatives(ctx, block);
2961 midgard_legalize_invert(ctx, block);
2962 midgard_cull_dead_branch(ctx, block);
2963 }
2964
2965 if (ctx->stage == MESA_SHADER_FRAGMENT)
2966 mir_add_writeout_loops(ctx);
2967
2968 /* Analyze now that the code is known but before scheduling creates
2969 * pipeline registers which are harder to track */
2970 mir_analyze_helper_requirements(ctx);
2971
2972 if (midgard_debug & MIDGARD_DBG_SHADERS && !skip_internal)
2973 mir_print_shader(ctx);
2974
2975 /* Schedule! */
2976 midgard_schedule_program(ctx);
2977 mir_ra(ctx);
2978
2979 if (midgard_debug & MIDGARD_DBG_SHADERS && !skip_internal)
2980 mir_print_shader(ctx);
2981
2982 /* Analyze after scheduling since this is order-dependent */
2983 mir_analyze_helper_terminate(ctx);
2984
2985 /* Emit flat binary from the instruction arrays. Iterate each block in
2986 * sequence. Save instruction boundaries such that lookahead tags can
2987 * be assigned easily */
2988
2989 /* Cache _all_ bundles in source order for lookahead across failed branches */
2990
2991 int bundle_count = 0;
2992 mir_foreach_block(ctx, _block) {
2993 midgard_block *block = (midgard_block *)_block;
2994 bundle_count += block->bundles.size / sizeof(midgard_bundle);
2995 }
2996 midgard_bundle **source_order_bundles =
2997 malloc(sizeof(midgard_bundle *) * bundle_count);
2998 int bundle_idx = 0;
2999 mir_foreach_block(ctx, _block) {
3000 midgard_block *block = (midgard_block *)_block;
3001 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
3002 source_order_bundles[bundle_idx++] = bundle;
3003 }
3004 }
3005
3006 int current_bundle = 0;
3007
3008 /* Midgard prefetches instruction types, so during emission we
3009 * need to lookahead. Unless this is the last instruction, in
3010 * which we return 1. */
3011
3012 mir_foreach_block(ctx, _block) {
3013 midgard_block *block = (midgard_block *)_block;
3014 mir_foreach_bundle_in_block(block, bundle) {
3015 int lookahead = 1;
3016
3017 if (!bundle->last_writeout && (current_bundle + 1 < bundle_count))
3018 lookahead = source_order_bundles[current_bundle + 1]->tag;
3019
3020 emit_binary_bundle(ctx, block, bundle, binary, lookahead);
3021 ++current_bundle;
3022 }
3023
3024 /* TODO: Free deeper */
3025 // util_dynarray_fini(&block->instructions);
3026 }
3027
3028 free(source_order_bundles);
3029
3030 /* Report the very first tag executed */
3031 info->midgard.first_tag = midgard_get_first_tag_from_block(ctx, 0);
3032
3033 info->ubo_mask = ctx->ubo_mask & ((1 << ctx->nir->info.num_ubos) - 1);
3034
3035 if (midgard_debug & MIDGARD_DBG_SHADERS && !skip_internal) {
3036 disassemble_midgard(stdout, binary->data, binary->size, inputs->gpu_id,
3037 midgard_debug & MIDGARD_DBG_VERBOSE);
3038 fflush(stdout);
3039 }
3040
3041 /* A shader ending on a 16MB boundary causes INSTR_INVALID_PC faults,
3042 * workaround by adding some padding to the end of the shader. (The
3043 * kernel makes sure shader BOs can't cross 16MB boundaries.) */
3044 if (binary->size)
3045 memset(util_dynarray_grow(binary, uint8_t, 16), 0, 16);
3046
3047 if ((midgard_debug & MIDGARD_DBG_SHADERDB || inputs->debug) &&
3048 !nir->info.internal) {
3049 unsigned nr_bundles = 0, nr_ins = 0;
3050
3051 /* Count instructions and bundles */
3052
3053 mir_foreach_block(ctx, _block) {
3054 midgard_block *block = (midgard_block *)_block;
3055 nr_bundles +=
3056 util_dynarray_num_elements(&block->bundles, midgard_bundle);
3057
3058 mir_foreach_bundle_in_block(block, bun)
3059 nr_ins += bun->instruction_count;
3060 }
3061
3062 /* Calculate thread count. There are certain cutoffs by
3063 * register count for thread count */
3064
3065 unsigned nr_registers = info->work_reg_count;
3066
3067 unsigned nr_threads = (nr_registers <= 4) ? 4
3068 : (nr_registers <= 8) ? 2
3069 : 1;
3070
3071 char *shaderdb = NULL;
3072
3073 /* Dump stats */
3074
3075 asprintf(&shaderdb,
3076 "%s shader: "
3077 "%u inst, %u bundles, %u quadwords, "
3078 "%u registers, %u threads, %u loops, "
3079 "%u:%u spills:fills",
3080 ctx->inputs->is_blend ? "PAN_SHADER_BLEND"
3081 : gl_shader_stage_name(ctx->stage),
3082 nr_ins, nr_bundles, ctx->quadword_count, nr_registers,
3083 nr_threads, ctx->loop_count, ctx->spills, ctx->fills);
3084
3085 if (midgard_debug & MIDGARD_DBG_SHADERDB)
3086 fprintf(stderr, "SHADER-DB: %s\n", shaderdb);
3087
3088 if (inputs->debug)
3089 util_debug_message(inputs->debug, SHADER_INFO, "%s", shaderdb);
3090
3091 free(shaderdb);
3092 }
3093
3094 _mesa_hash_table_u64_destroy(ctx->ssa_constants);
3095 ralloc_free(ctx);
3096 }
3097