1 /*
2 * Copyright © 2021 Collabora Ltd.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "nir/nir_builder.h"
25 #include "pan_blitter.h"
26 #include "pan_encoder.h"
27 #include "pan_props.h"
28 #include "pan_shader.h"
29
30 #include "panvk_private.h"
31 #include "panvk_vX_meta.h"
32
33 #include "vk_format.h"
34
35 static mali_ptr
panvk_meta_clear_color_attachment_shader(struct panvk_device * dev,enum glsl_base_type base_type,struct pan_shader_info * shader_info)36 panvk_meta_clear_color_attachment_shader(struct panvk_device *dev,
37 enum glsl_base_type base_type,
38 struct pan_shader_info *shader_info)
39 {
40 struct pan_pool *bin_pool = &dev->meta.bin_pool.base;
41
42 nir_builder b = nir_builder_init_simple_shader(
43 MESA_SHADER_FRAGMENT, GENX(pan_shader_get_compiler_options)(),
44 "panvk_meta_clear_attachment(base_type=%d)", base_type);
45
46 const struct glsl_type *out_type = glsl_vector_type(base_type, 4);
47 nir_variable *out =
48 nir_variable_create(b.shader, nir_var_shader_out, out_type, "out");
49 out->data.location = FRAG_RESULT_DATA0;
50
51 nir_def *clear_values =
52 nir_load_push_constant(&b, 4, 32, nir_imm_int(&b, 0), .range = ~0);
53 nir_store_var(&b, out, clear_values, 0xff);
54
55 struct panfrost_compile_inputs inputs = {
56 .gpu_id = dev->physical_device->kmod.props.gpu_prod_id,
57 .is_blit = true,
58 .no_ubo_to_push = true,
59 };
60
61 struct util_dynarray binary;
62
63 util_dynarray_init(&binary, NULL);
64 pan_shader_preprocess(b.shader, inputs.gpu_id);
65 GENX(pan_shader_compile)(b.shader, &inputs, &binary, shader_info);
66
67 shader_info->push.count = 4;
68
69 mali_ptr shader =
70 pan_pool_upload_aligned(bin_pool, binary.data, binary.size, 128);
71
72 util_dynarray_fini(&binary);
73 ralloc_free(b.shader);
74
75 return shader;
76 }
77
78 static mali_ptr
panvk_meta_clear_color_attachment_emit_rsd(struct pan_pool * desc_pool,enum pipe_format format,unsigned rt,struct pan_shader_info * shader_info,mali_ptr shader)79 panvk_meta_clear_color_attachment_emit_rsd(struct pan_pool *desc_pool,
80 enum pipe_format format, unsigned rt,
81 struct pan_shader_info *shader_info,
82 mali_ptr shader)
83 {
84 struct panfrost_ptr rsd_ptr = pan_pool_alloc_desc_aggregate(
85 desc_pool, PAN_DESC(RENDERER_STATE), PAN_DESC_ARRAY(rt + 1, BLEND));
86
87 pan_pack(rsd_ptr.cpu, RENDERER_STATE, cfg) {
88 pan_shader_prepare_rsd(shader_info, shader, &cfg);
89
90 cfg.properties.depth_source = MALI_DEPTH_SOURCE_FIXED_FUNCTION;
91 cfg.multisample_misc.sample_mask = UINT16_MAX;
92 cfg.multisample_misc.depth_function = MALI_FUNC_ALWAYS;
93 cfg.properties.allow_forward_pixel_to_be_killed = true;
94 cfg.properties.allow_forward_pixel_to_kill = true;
95 cfg.properties.zs_update_operation = MALI_PIXEL_KILL_WEAK_EARLY;
96 cfg.properties.pixel_kill_operation = MALI_PIXEL_KILL_WEAK_EARLY;
97 }
98
99 void *bd = rsd_ptr.cpu + pan_size(RENDERER_STATE);
100
101 pan_pack(bd, BLEND, cfg) {
102 cfg.round_to_fb_precision = true;
103 cfg.load_destination = false;
104 cfg.equation.rgb.a = MALI_BLEND_OPERAND_A_SRC;
105 cfg.equation.rgb.b = MALI_BLEND_OPERAND_B_SRC;
106 cfg.equation.rgb.c = MALI_BLEND_OPERAND_C_ZERO;
107 cfg.equation.alpha.a = MALI_BLEND_OPERAND_A_SRC;
108 cfg.equation.alpha.b = MALI_BLEND_OPERAND_B_SRC;
109 cfg.equation.alpha.c = MALI_BLEND_OPERAND_C_ZERO;
110 cfg.internal.mode = MALI_BLEND_MODE_OPAQUE;
111 cfg.equation.color_mask = 0xf;
112 cfg.internal.fixed_function.num_comps = 4;
113 cfg.internal.fixed_function.rt = rt;
114 cfg.internal.fixed_function.conversion.memory_format =
115 GENX(panfrost_dithered_format_from_pipe_format)(format, false);
116 cfg.internal.fixed_function.conversion.register_format =
117 shader_info->bifrost.blend[0].format;
118 }
119
120 return rsd_ptr.gpu;
121 }
122
123 static mali_ptr
panvk_meta_clear_zs_attachment_emit_rsd(struct pan_pool * desc_pool,VkImageAspectFlags mask,VkClearDepthStencilValue value)124 panvk_meta_clear_zs_attachment_emit_rsd(struct pan_pool *desc_pool,
125 VkImageAspectFlags mask,
126 VkClearDepthStencilValue value)
127 {
128 struct panfrost_ptr rsd_ptr = pan_pool_alloc_desc(desc_pool, RENDERER_STATE);
129
130 pan_pack(rsd_ptr.cpu, RENDERER_STATE, cfg) {
131 cfg.properties.depth_source = MALI_DEPTH_SOURCE_FIXED_FUNCTION;
132 cfg.multisample_misc.sample_mask = UINT16_MAX;
133
134 if (mask & VK_IMAGE_ASPECT_DEPTH_BIT) {
135 cfg.multisample_misc.depth_write_mask = true;
136 cfg.multisample_misc.depth_function = MALI_FUNC_NOT_EQUAL;
137
138 if (value.depth != 0.0) {
139 cfg.stencil_mask_misc.front_facing_depth_bias = true;
140 cfg.stencil_mask_misc.back_facing_depth_bias = true;
141 cfg.depth_units = INFINITY;
142 cfg.depth_bias_clamp = value.depth;
143 }
144 }
145
146 if (mask & VK_IMAGE_ASPECT_STENCIL_BIT) {
147 cfg.stencil_mask_misc.stencil_enable = true;
148 cfg.stencil_mask_misc.stencil_mask_front = 0xFF;
149 cfg.stencil_mask_misc.stencil_mask_back = 0xFF;
150
151 cfg.stencil_front.compare_function = (mask & VK_IMAGE_ASPECT_DEPTH_BIT)
152 ? MALI_FUNC_ALWAYS
153 : MALI_FUNC_NOT_EQUAL;
154
155 cfg.stencil_front.stencil_fail = MALI_STENCIL_OP_KEEP;
156 cfg.stencil_front.depth_fail = MALI_STENCIL_OP_REPLACE;
157 cfg.stencil_front.depth_pass = MALI_STENCIL_OP_REPLACE;
158 cfg.stencil_front.reference_value = value.stencil;
159 cfg.stencil_front.mask = 0xFF;
160 cfg.stencil_back = cfg.stencil_front;
161 }
162
163 cfg.properties.allow_forward_pixel_to_be_killed = true;
164 cfg.properties.zs_update_operation = MALI_PIXEL_KILL_WEAK_EARLY;
165 cfg.properties.pixel_kill_operation = MALI_PIXEL_KILL_WEAK_EARLY;
166 }
167
168 return rsd_ptr.gpu;
169 }
170
171 static void
panvk_meta_clear_attachment_emit_dcd(struct pan_pool * pool,mali_ptr coords,mali_ptr push_constants,mali_ptr vpd,mali_ptr tsd,mali_ptr rsd,void * out)172 panvk_meta_clear_attachment_emit_dcd(struct pan_pool *pool, mali_ptr coords,
173 mali_ptr push_constants, mali_ptr vpd,
174 mali_ptr tsd, mali_ptr rsd, void *out)
175 {
176 pan_pack(out, DRAW, cfg) {
177 cfg.thread_storage = tsd;
178 cfg.state = rsd;
179 cfg.push_uniforms = push_constants;
180 cfg.position = coords;
181 cfg.viewport = vpd;
182 }
183 }
184
185 static struct panfrost_ptr
panvk_meta_clear_attachment_emit_tiler_job(struct pan_pool * desc_pool,struct pan_jc * jc,mali_ptr coords,mali_ptr push_constants,mali_ptr vpd,mali_ptr rsd,mali_ptr tsd,mali_ptr tiler)186 panvk_meta_clear_attachment_emit_tiler_job(struct pan_pool *desc_pool,
187 struct pan_jc *jc, mali_ptr coords,
188 mali_ptr push_constants,
189 mali_ptr vpd, mali_ptr rsd,
190 mali_ptr tsd, mali_ptr tiler)
191 {
192 struct panfrost_ptr job = pan_pool_alloc_desc(desc_pool, TILER_JOB);
193
194 panvk_meta_clear_attachment_emit_dcd(
195 desc_pool, coords, push_constants, vpd, tsd, rsd,
196 pan_section_ptr(job.cpu, TILER_JOB, DRAW));
197
198 pan_section_pack(job.cpu, TILER_JOB, PRIMITIVE, cfg) {
199 cfg.draw_mode = MALI_DRAW_MODE_TRIANGLE_STRIP;
200 cfg.index_count = 4;
201 cfg.job_task_split = 6;
202 }
203
204 pan_section_pack(job.cpu, TILER_JOB, PRIMITIVE_SIZE, cfg) {
205 cfg.constant = 1.0f;
206 }
207
208 void *invoc = pan_section_ptr(job.cpu, TILER_JOB, INVOCATION);
209 panfrost_pack_work_groups_compute(invoc, 1, 4, 1, 1, 1, 1, true, false);
210
211 pan_section_pack(job.cpu, TILER_JOB, PADDING, cfg)
212 ;
213 pan_section_pack(job.cpu, TILER_JOB, TILER, cfg) {
214 cfg.address = tiler;
215 }
216
217 pan_jc_add_job(desc_pool, jc, MALI_JOB_TYPE_TILER, false, false, 0, 0, &job,
218 false);
219 return job;
220 }
221
222 static enum glsl_base_type
panvk_meta_get_format_type(enum pipe_format format)223 panvk_meta_get_format_type(enum pipe_format format)
224 {
225 const struct util_format_description *desc = util_format_description(format);
226 int i;
227
228 i = util_format_get_first_non_void_channel(format);
229 assert(i >= 0);
230
231 if (desc->channel[i].normalized)
232 return GLSL_TYPE_FLOAT;
233
234 switch (desc->channel[i].type) {
235
236 case UTIL_FORMAT_TYPE_UNSIGNED:
237 return GLSL_TYPE_UINT;
238
239 case UTIL_FORMAT_TYPE_SIGNED:
240 return GLSL_TYPE_INT;
241
242 case UTIL_FORMAT_TYPE_FLOAT:
243 return GLSL_TYPE_FLOAT;
244
245 default:
246 unreachable("Unhandled format");
247 return GLSL_TYPE_FLOAT;
248 }
249 }
250
251 static void
panvk_meta_clear_attachment(struct panvk_cmd_buffer * cmdbuf,unsigned attachment,unsigned rt,VkImageAspectFlags mask,const VkClearValue * clear_value,const VkClearRect * clear_rect)252 panvk_meta_clear_attachment(struct panvk_cmd_buffer *cmdbuf,
253 unsigned attachment, unsigned rt,
254 VkImageAspectFlags mask,
255 const VkClearValue *clear_value,
256 const VkClearRect *clear_rect)
257 {
258 struct panvk_meta *meta = &cmdbuf->device->meta;
259 struct panvk_batch *batch = cmdbuf->state.batch;
260 const struct panvk_render_pass *pass = cmdbuf->state.pass;
261 const struct panvk_render_pass_attachment *att =
262 &pass->attachments[attachment];
263 unsigned minx = MAX2(clear_rect->rect.offset.x, 0);
264 unsigned miny = MAX2(clear_rect->rect.offset.y, 0);
265 unsigned maxx =
266 MAX2(clear_rect->rect.offset.x + clear_rect->rect.extent.width - 1, 0);
267 unsigned maxy =
268 MAX2(clear_rect->rect.offset.y + clear_rect->rect.extent.height - 1, 0);
269
270 panvk_per_arch(cmd_alloc_fb_desc)(cmdbuf);
271 panvk_per_arch(cmd_alloc_tls_desc)(cmdbuf, true);
272 panvk_per_arch(cmd_prepare_tiler_context)(cmdbuf);
273
274 mali_ptr vpd = panvk_per_arch(meta_emit_viewport)(&cmdbuf->desc_pool.base,
275 minx, miny, maxx, maxy);
276
277 float rect[] = {
278 minx, miny, 0.0, 1.0, maxx + 1, miny, 0.0, 1.0,
279 minx, maxy + 1, 0.0, 1.0, maxx + 1, maxy + 1, 0.0, 1.0,
280 };
281 mali_ptr coordinates =
282 pan_pool_upload_aligned(&cmdbuf->desc_pool.base, rect, sizeof(rect), 64);
283
284 enum glsl_base_type base_type = panvk_meta_get_format_type(att->format);
285
286 mali_ptr tiler = batch->tiler.descs.gpu;
287 mali_ptr tsd = batch->tls.gpu;
288
289 mali_ptr pushconsts = 0, rsd = 0;
290
291 if (mask & VK_IMAGE_ASPECT_COLOR_BIT) {
292 mali_ptr shader = meta->clear_attachment.color[base_type].shader;
293 struct pan_shader_info *shader_info =
294 &meta->clear_attachment.color[base_type].shader_info;
295
296 pushconsts = pan_pool_upload_aligned(&cmdbuf->desc_pool.base, clear_value,
297 sizeof(*clear_value), 16);
298
299 rsd = panvk_meta_clear_color_attachment_emit_rsd(
300 &cmdbuf->desc_pool.base, att->format, rt, shader_info, shader);
301 } else {
302 rsd = panvk_meta_clear_zs_attachment_emit_rsd(
303 &cmdbuf->desc_pool.base, mask, clear_value->depthStencil);
304 }
305
306 struct panfrost_ptr job;
307
308 job = panvk_meta_clear_attachment_emit_tiler_job(
309 &cmdbuf->desc_pool.base, &batch->jc, coordinates, pushconsts, vpd, rsd,
310 tsd, tiler);
311
312 util_dynarray_append(&batch->jobs, void *, job.cpu);
313 }
314
315 static void
panvk_meta_clear_color_img(struct panvk_cmd_buffer * cmdbuf,struct panvk_image * img,const VkClearColorValue * color,const VkImageSubresourceRange * range)316 panvk_meta_clear_color_img(struct panvk_cmd_buffer *cmdbuf,
317 struct panvk_image *img,
318 const VkClearColorValue *color,
319 const VkImageSubresourceRange *range)
320 {
321 struct pan_fb_info *fbinfo = &cmdbuf->state.fb.info;
322 struct pan_image_view view = {
323 .format = img->pimage.layout.format,
324 .dim = MALI_TEXTURE_DIMENSION_2D,
325 .planes[0] = &img->pimage,
326 .nr_samples = img->pimage.layout.nr_samples,
327 .swizzle = {PIPE_SWIZZLE_X, PIPE_SWIZZLE_Y, PIPE_SWIZZLE_Z,
328 PIPE_SWIZZLE_W},
329 };
330
331 cmdbuf->state.fb.crc_valid[0] = false;
332 *fbinfo = (struct pan_fb_info){
333 .tile_buf_budget = panfrost_query_optimal_tib_size(
334 cmdbuf->device->physical_device->model),
335 .nr_samples = img->pimage.layout.nr_samples,
336 .rt_count = 1,
337 .rts[0].view = &view,
338 .rts[0].clear = true,
339 .rts[0].crc_valid = &cmdbuf->state.fb.crc_valid[0],
340 };
341
342 uint32_t clearval[4];
343 pan_pack_color(panfrost_blendable_formats_v7, clearval,
344 (union pipe_color_union *)color, img->pimage.layout.format,
345 false);
346 memcpy(fbinfo->rts[0].clear_value, clearval,
347 sizeof(fbinfo->rts[0].clear_value));
348
349 unsigned level_count = vk_image_subresource_level_count(&img->vk, range);
350 unsigned layer_count = vk_image_subresource_layer_count(&img->vk, range);
351
352 for (unsigned level = range->baseMipLevel;
353 level < range->baseMipLevel + level_count; level++) {
354 view.first_level = view.last_level = level;
355 fbinfo->width = u_minify(img->pimage.layout.width, level);
356 fbinfo->height = u_minify(img->pimage.layout.height, level);
357 fbinfo->extent.maxx = fbinfo->width - 1;
358 fbinfo->extent.maxy = fbinfo->height - 1;
359
360 for (unsigned layer = range->baseArrayLayer;
361 layer < range->baseArrayLayer + layer_count; layer++) {
362 view.first_layer = view.last_layer = layer;
363 panvk_cmd_open_batch(cmdbuf);
364 panvk_per_arch(cmd_alloc_fb_desc)(cmdbuf);
365 panvk_per_arch(cmd_close_batch)(cmdbuf);
366 }
367 }
368 }
369
370 void
panvk_per_arch(CmdClearColorImage)371 panvk_per_arch(CmdClearColorImage)(VkCommandBuffer commandBuffer, VkImage image,
372 VkImageLayout imageLayout,
373 const VkClearColorValue *pColor,
374 uint32_t rangeCount,
375 const VkImageSubresourceRange *pRanges)
376 {
377 VK_FROM_HANDLE(panvk_cmd_buffer, cmdbuf, commandBuffer);
378 VK_FROM_HANDLE(panvk_image, img, image);
379
380 panvk_per_arch(cmd_close_batch)(cmdbuf);
381
382 for (unsigned i = 0; i < rangeCount; i++)
383 panvk_meta_clear_color_img(cmdbuf, img, pColor, &pRanges[i]);
384 }
385
386 static void
panvk_meta_clear_zs_img(struct panvk_cmd_buffer * cmdbuf,struct panvk_image * img,const VkClearDepthStencilValue * value,const VkImageSubresourceRange * range)387 panvk_meta_clear_zs_img(struct panvk_cmd_buffer *cmdbuf,
388 struct panvk_image *img,
389 const VkClearDepthStencilValue *value,
390 const VkImageSubresourceRange *range)
391 {
392 struct pan_fb_info *fbinfo = &cmdbuf->state.fb.info;
393 struct pan_image_view view = {
394 .format = img->pimage.layout.format,
395 .dim = MALI_TEXTURE_DIMENSION_2D,
396 .planes[0] = &img->pimage,
397 .nr_samples = img->pimage.layout.nr_samples,
398 .swizzle = {PIPE_SWIZZLE_X, PIPE_SWIZZLE_Y, PIPE_SWIZZLE_Z,
399 PIPE_SWIZZLE_W},
400 };
401
402 cmdbuf->state.fb.crc_valid[0] = false;
403 *fbinfo = (struct pan_fb_info){
404 .tile_buf_budget = panfrost_query_optimal_tib_size(
405 cmdbuf->device->physical_device->model),
406 .nr_samples = img->pimage.layout.nr_samples,
407 .rt_count = 1,
408 .zs.clear_value.depth = value->depth,
409 .zs.clear_value.stencil = value->stencil,
410 .zs.clear.z = range->aspectMask & VK_IMAGE_ASPECT_DEPTH_BIT,
411 .zs.clear.s = range->aspectMask & VK_IMAGE_ASPECT_STENCIL_BIT};
412
413 const struct util_format_description *fdesc =
414 util_format_description(view.format);
415
416 if (util_format_has_depth(fdesc)) {
417 fbinfo->zs.view.zs = &view;
418 if (util_format_has_stencil(fdesc)) {
419 fbinfo->zs.preload.z = !fbinfo->zs.clear.z;
420 fbinfo->zs.preload.s = !fbinfo->zs.clear.s;
421 }
422 } else {
423 fbinfo->zs.view.s = &view;
424 }
425
426 unsigned level_count = vk_image_subresource_level_count(&img->vk, range);
427 unsigned layer_count = vk_image_subresource_layer_count(&img->vk, range);
428
429 for (unsigned level = range->baseMipLevel;
430 level < range->baseMipLevel + level_count; level++) {
431 view.first_level = view.last_level = level;
432 fbinfo->width = u_minify(img->pimage.layout.width, level);
433 fbinfo->height = u_minify(img->pimage.layout.height, level);
434 fbinfo->extent.maxx = fbinfo->width - 1;
435 fbinfo->extent.maxy = fbinfo->height - 1;
436
437 for (unsigned layer = range->baseArrayLayer;
438 layer < range->baseArrayLayer + layer_count; layer++) {
439 view.first_layer = view.last_layer = layer;
440 panvk_cmd_open_batch(cmdbuf);
441 panvk_per_arch(cmd_alloc_fb_desc)(cmdbuf);
442 panvk_per_arch(cmd_close_batch)(cmdbuf);
443 }
444 }
445
446 memset(fbinfo, 0, sizeof(*fbinfo));
447 }
448
449 void
panvk_per_arch(CmdClearDepthStencilImage)450 panvk_per_arch(CmdClearDepthStencilImage)(
451 VkCommandBuffer commandBuffer, VkImage image, VkImageLayout imageLayout,
452 const VkClearDepthStencilValue *pDepthStencil, uint32_t rangeCount,
453 const VkImageSubresourceRange *pRanges)
454 {
455 VK_FROM_HANDLE(panvk_cmd_buffer, cmdbuf, commandBuffer);
456 VK_FROM_HANDLE(panvk_image, img, image);
457
458 panvk_per_arch(cmd_close_batch)(cmdbuf);
459
460 for (unsigned i = 0; i < rangeCount; i++)
461 panvk_meta_clear_zs_img(cmdbuf, img, pDepthStencil, &pRanges[i]);
462 }
463
464 void
panvk_per_arch(CmdClearAttachments)465 panvk_per_arch(CmdClearAttachments)(VkCommandBuffer commandBuffer,
466 uint32_t attachmentCount,
467 const VkClearAttachment *pAttachments,
468 uint32_t rectCount,
469 const VkClearRect *pRects)
470 {
471 VK_FROM_HANDLE(panvk_cmd_buffer, cmdbuf, commandBuffer);
472 const struct panvk_subpass *subpass = cmdbuf->state.subpass;
473
474 for (unsigned i = 0; i < attachmentCount; i++) {
475 for (unsigned j = 0; j < rectCount; j++) {
476
477 uint32_t attachment, rt = 0;
478 if (pAttachments[i].aspectMask & VK_IMAGE_ASPECT_COLOR_BIT) {
479 rt = pAttachments[i].colorAttachment;
480 attachment = subpass->color_attachments[rt].idx;
481 } else {
482 attachment = subpass->zs_attachment.idx;
483 }
484
485 if (attachment == VK_ATTACHMENT_UNUSED)
486 continue;
487
488 panvk_meta_clear_attachment(cmdbuf, attachment, rt,
489 pAttachments[i].aspectMask,
490 &pAttachments[i].clearValue, &pRects[j]);
491 }
492 }
493 }
494
495 static void
panvk_meta_clear_attachment_init(struct panvk_device * dev)496 panvk_meta_clear_attachment_init(struct panvk_device *dev)
497 {
498 dev->meta.clear_attachment.color[GLSL_TYPE_UINT].shader =
499 panvk_meta_clear_color_attachment_shader(
500 dev, GLSL_TYPE_UINT,
501 &dev->meta.clear_attachment.color[GLSL_TYPE_UINT].shader_info);
502
503 dev->meta.clear_attachment.color[GLSL_TYPE_INT].shader =
504 panvk_meta_clear_color_attachment_shader(
505 dev, GLSL_TYPE_INT,
506 &dev->meta.clear_attachment.color[GLSL_TYPE_INT].shader_info);
507
508 dev->meta.clear_attachment.color[GLSL_TYPE_FLOAT].shader =
509 panvk_meta_clear_color_attachment_shader(
510 dev, GLSL_TYPE_FLOAT,
511 &dev->meta.clear_attachment.color[GLSL_TYPE_FLOAT].shader_info);
512 }
513
514 void
panvk_per_arch(meta_clear_init)515 panvk_per_arch(meta_clear_init)(struct panvk_device *dev)
516 {
517 panvk_meta_clear_attachment_init(dev);
518 }
519