1 // Copyright 2022 The Pigweed Authors 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); you may not 4 // use this file except in compliance with the License. You may obtain a copy of 5 // the License at 6 // 7 // https://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT 11 // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the 12 // License for the specific language governing permissions and limitations under 13 // the License. 14 15 #include "pw_boot/boot.h" 16 17 #include <array> 18 19 #include "FreeRTOS.h" 20 #include "config/sf2_mss_hal_conf.h" 21 #include "m2sxxx.h" 22 #include "pw_boot_cortex_m/boot.h" 23 #include "pw_malloc/malloc.h" 24 #include "pw_preprocessor/compiler.h" 25 #include "pw_string/util.h" 26 #include "pw_sys_io_emcraft_sf2/init.h" 27 #include "pw_system/init.h" 28 #include "system_m2sxxx.h" 29 #include "task.h" 30 31 #include liberosoc_CONFIG_FILE 32 33 extern "C" void Reset_Handler(void); 34 35 // Functions needed when configGENERATE_RUN_TIME_STATS is on. configureTimerForRunTimeStats(void)36extern "C" void configureTimerForRunTimeStats(void) {} getRunTimeCounterValue(void)37extern "C" unsigned long getRunTimeCounterValue(void) { 38 return 10 /* TODO: b/325107250 - properly implement this function */; 39 } 40 // uwTick is an uint32_t incremented each Systick interrupt 1ms. uwTick is used 41 // to execute HAL_Delay function. 42 pw_boot_PreStaticMemoryInit()43extern "C" void pw_boot_PreStaticMemoryInit() { 44 #if SF2_MSS_NO_BOOTLOADER 45 SystemInit(); 46 // Initialize DDR 47 // inclusive-language: disable 48 MDDR->core.ddrc.DYN_SOFT_RESET_CR = 0x0000; 49 MDDR->core.ddrc.DYN_REFRESH_1_CR = 0x27de; 50 MDDR->core.ddrc.DYN_REFRESH_2_CR = 0x030f; 51 MDDR->core.ddrc.DYN_POWERDOWN_CR = 0x0002; 52 MDDR->core.ddrc.DYN_DEBUG_CR = 0x0000; 53 MDDR->core.ddrc.MODE_CR = 0x00C1; 54 MDDR->core.ddrc.ADDR_MAP_BANK_CR = 0x099f; 55 MDDR->core.ddrc.ECC_DATA_MASK_CR = 0x0000; 56 MDDR->core.ddrc.ADDR_MAP_COL_1_CR = 0x3333; 57 MDDR->core.ddrc.ADDR_MAP_COL_2_CR = 0xffff; 58 MDDR->core.ddrc.ADDR_MAP_ROW_1_CR = 0x7777; 59 MDDR->core.ddrc.ADDR_MAP_ROW_2_CR = 0x0fff; 60 MDDR->core.ddrc.INIT_1_CR = 0x0001; 61 MDDR->core.ddrc.CKE_RSTN_CYCLES_CR[0] = 0x4242; 62 MDDR->core.ddrc.CKE_RSTN_CYCLES_CR[1] = 0x0008; 63 MDDR->core.ddrc.INIT_MR_CR = 0x0033; 64 MDDR->core.ddrc.INIT_EMR_CR = 0x0020; 65 MDDR->core.ddrc.INIT_EMR2_CR = 0x0000; 66 MDDR->core.ddrc.INIT_EMR3_CR = 0x0000; 67 MDDR->core.ddrc.DRAM_BANK_TIMING_PARAM_CR = 0x00c0; 68 MDDR->core.ddrc.DRAM_RD_WR_LATENCY_CR = 0x0023; 69 MDDR->core.ddrc.DRAM_RD_WR_PRE_CR = 0x0235; 70 MDDR->core.ddrc.DRAM_MR_TIMING_PARAM_CR = 0x0064; 71 MDDR->core.ddrc.DRAM_RAS_TIMING_CR = 0x0108; 72 MDDR->core.ddrc.DRAM_RD_WR_TRNARND_TIME_CR = 0x0178; 73 MDDR->core.ddrc.DRAM_T_PD_CR = 0x0033; 74 MDDR->core.ddrc.DRAM_BANK_ACT_TIMING_CR = 0x1947; 75 MDDR->core.ddrc.ODT_PARAM_1_CR = 0x0010; 76 MDDR->core.ddrc.ODT_PARAM_2_CR = 0x0000; 77 MDDR->core.ddrc.ADDR_MAP_COL_3_CR = 0x3300; 78 MDDR->core.ddrc.MODE_REG_RD_WR_CR = 0x0000; 79 MDDR->core.ddrc.MODE_REG_DATA_CR = 0x0000; 80 MDDR->core.ddrc.PWR_SAVE_1_CR = 0x0514; 81 MDDR->core.ddrc.PWR_SAVE_2_CR = 0x0000; 82 MDDR->core.ddrc.ZQ_LONG_TIME_CR = 0x0200; 83 MDDR->core.ddrc.ZQ_SHORT_TIME_CR = 0x0040; 84 MDDR->core.ddrc.ZQ_SHORT_INT_REFRESH_MARGIN_CR[0] = 0x0012; 85 MDDR->core.ddrc.ZQ_SHORT_INT_REFRESH_MARGIN_CR[1] = 0x0002; 86 MDDR->core.ddrc.PERF_PARAM_1_CR = 0x4000; 87 MDDR->core.ddrc.HPR_QUEUE_PARAM_CR[0] = 0x80f8; 88 MDDR->core.ddrc.HPR_QUEUE_PARAM_CR[1] = 0x0007; 89 MDDR->core.ddrc.LPR_QUEUE_PARAM_CR[0] = 0x80f8; 90 MDDR->core.ddrc.LPR_QUEUE_PARAM_CR[1] = 0x0007; 91 MDDR->core.ddrc.WR_QUEUE_PARAM_CR = 0x0200; 92 MDDR->core.ddrc.PERF_PARAM_2_CR = 0x0001; 93 MDDR->core.ddrc.PERF_PARAM_3_CR = 0x0000; 94 MDDR->core.ddrc.DFI_RDDATA_EN_CR = 0x0003; 95 MDDR->core.ddrc.DFI_MIN_CTRLUPD_TIMING_CR = 0x0003; 96 MDDR->core.ddrc.DFI_MAX_CTRLUPD_TIMING_CR = 0x0040; 97 MDDR->core.ddrc.DFI_WR_LVL_CONTROL_CR[0] = 0x0000; 98 MDDR->core.ddrc.DFI_WR_LVL_CONTROL_CR[1] = 0x0000; 99 MDDR->core.ddrc.DFI_RD_LVL_CONTROL_CR[0] = 0x0000; 100 MDDR->core.ddrc.DFI_RD_LVL_CONTROL_CR[1] = 0x0000; 101 MDDR->core.ddrc.DFI_CTRLUPD_TIME_INTERVAL_CR = 0x0309; 102 MDDR->core.ddrc.AXI_FABRIC_PRI_ID_CR = 0x0000; 103 MDDR->core.ddrc.ECC_INT_CLR_REG = 0x0000; 104 105 MDDR->core.phy.LOOPBACK_TEST_CR = 0x0000; 106 MDDR->core.phy.CTRL_SLAVE_RATIO_CR = 0x0080; 107 MDDR->core.phy.DATA_SLICE_IN_USE_CR = 0x0003; 108 MDDR->core.phy.DQ_OFFSET_CR[0] = 0x00000000; 109 MDDR->core.phy.DQ_OFFSET_CR[2] = 0x0000; 110 MDDR->core.phy.DLL_LOCK_DIFF_CR = 0x000B; 111 MDDR->core.phy.FIFO_WE_SLAVE_RATIO_CR[0] = 0x0040; 112 MDDR->core.phy.FIFO_WE_SLAVE_RATIO_CR[1] = 0x0401; 113 MDDR->core.phy.FIFO_WE_SLAVE_RATIO_CR[2] = 0x4010; 114 MDDR->core.phy.FIFO_WE_SLAVE_RATIO_CR[3] = 0x0000; 115 MDDR->core.phy.LOCAL_ODT_CR = 0x0001; 116 MDDR->core.phy.RD_DQS_SLAVE_RATIO_CR[0] = 0x0040; 117 MDDR->core.phy.RD_DQS_SLAVE_RATIO_CR[1] = 0x0401; 118 MDDR->core.phy.RD_DQS_SLAVE_RATIO_CR[2] = 0x4010; 119 MDDR->core.phy.WR_DATA_SLAVE_RATIO_CR[0] = 0x0040; 120 MDDR->core.phy.WR_DATA_SLAVE_RATIO_CR[1] = 0x0401; 121 MDDR->core.phy.WR_DATA_SLAVE_RATIO_CR[2] = 0x4010; 122 MDDR->core.phy.WR_RD_RL_CR = 0x0021; 123 MDDR->core.phy.RDC_WE_TO_RE_DELAY_CR = 0x0003; 124 MDDR->core.phy.USE_FIXED_RE_CR = 0x0001; 125 MDDR->core.phy.USE_RANK0_DELAYS_CR = 0x0001; 126 MDDR->core.phy.CONFIG_CR = 0x0009; 127 MDDR->core.phy.DYN_RESET_CR = 0x01; 128 MDDR->core.ddrc.DYN_SOFT_RESET_CR = 0x01; 129 // inclusive-language: enable 130 // Wait for config 131 while ((MDDR->core.ddrc.DDRC_SR) == 0x0000) { 132 } 133 #endif 134 } 135 pw_boot_PreStaticConstructorInit()136extern "C" void pw_boot_PreStaticConstructorInit() { 137 // TODO(skeys) add "#if no_bootLoader" and the functions needed for init. 138 139 #if PW_MALLOC_ACTIVE 140 pw_MallocInit(&pw_boot_heap_low_addr, &pw_boot_heap_high_addr); 141 #endif // PW_MALLOC_ACTIVE 142 pw_sys_io_Init(); 143 } 144 145 // TODO(amontanez): pw_boot_PreMainInit() should get renamed to 146 // pw_boot_FinalizeBoot or similar when main() is removed. pw_boot_PreMainInit()147extern "C" void pw_boot_PreMainInit() { 148 pw::system::Init(); 149 vTaskStartScheduler(); 150 PW_UNREACHABLE; 151 } 152 sf2_SocInit()153extern "C" void sf2_SocInit() { 154 #if SF2_MSS_NO_BOOTLOADER 155 Reset_Handler(); 156 #endif 157 pw_boot_Entry(); 158 } 159 160 // This `main()` stub prevents another main function from being linked since 161 // this target deliberately doesn't run `main()`. main()162extern "C" int main() {} 163 pw_boot_PostMain()164extern "C" PW_NO_RETURN void pw_boot_PostMain() { 165 // In case main() returns, just sit here until the device is reset. 166 while (true) { 167 } 168 PW_UNREACHABLE; 169 } 170