1// This file is generated from a similarly-named Perl script in the BoringSSL 2// source tree. Do not edit by hand. 3 4#if !defined(__has_feature) 5#define __has_feature(x) 0 6#endif 7#if __has_feature(memory_sanitizer) && !defined(OPENSSL_NO_ASM) 8#define OPENSSL_NO_ASM 9#endif 10 11#if !defined(OPENSSL_NO_ASM) 12#if defined(__arm__) 13#include "ring_core_generated/prefix_symbols_asm.h" 14.syntax unified 15 16.arch armv7-a 17.fpu neon 18 19#if defined(__thumb2__) 20.thumb 21#else 22.code 32 23#endif 24 25.text 26 27.type _vpaes_consts,%object 28.align 7 @ totally strategic alignment 29_vpaes_consts: 30.Lk_mc_forward:@ mc_forward 31.quad 0x0407060500030201, 0x0C0F0E0D080B0A09 32.quad 0x080B0A0904070605, 0x000302010C0F0E0D 33.quad 0x0C0F0E0D080B0A09, 0x0407060500030201 34.quad 0x000302010C0F0E0D, 0x080B0A0904070605 35.Lk_mc_backward:@ mc_backward 36.quad 0x0605040702010003, 0x0E0D0C0F0A09080B 37.quad 0x020100030E0D0C0F, 0x0A09080B06050407 38.quad 0x0E0D0C0F0A09080B, 0x0605040702010003 39.quad 0x0A09080B06050407, 0x020100030E0D0C0F 40.Lk_sr:@ sr 41.quad 0x0706050403020100, 0x0F0E0D0C0B0A0908 42.quad 0x030E09040F0A0500, 0x0B06010C07020D08 43.quad 0x0F060D040B020900, 0x070E050C030A0108 44.quad 0x0B0E0104070A0D00, 0x0306090C0F020508 45 46@ 47@ "Hot" constants 48@ 49.Lk_inv:@ inv, inva 50.quad 0x0E05060F0D080180, 0x040703090A0B0C02 51.quad 0x01040A060F0B0780, 0x030D0E0C02050809 52.Lk_ipt:@ input transform (lo, hi) 53.quad 0xC2B2E8985A2A7000, 0xCABAE09052227808 54.quad 0x4C01307D317C4D00, 0xCD80B1FCB0FDCC81 55.Lk_sbo:@ sbou, sbot 56.quad 0xD0D26D176FBDC700, 0x15AABF7AC502A878 57.quad 0xCFE474A55FBB6A00, 0x8E1E90D1412B35FA 58.Lk_sb1:@ sb1u, sb1t 59.quad 0x3618D415FAE22300, 0x3BF7CCC10D2ED9EF 60.quad 0xB19BE18FCB503E00, 0xA5DF7A6E142AF544 61.Lk_sb2:@ sb2u, sb2t 62.quad 0x69EB88400AE12900, 0xC2A163C8AB82234A 63.quad 0xE27A93C60B712400, 0x5EB7E955BC982FCD 64 65.byte 86,101,99,116,111,114,32,80,101,114,109,117,116,97,116,105,111,110,32,65,69,83,32,102,111,114,32,65,82,77,118,55,32,78,69,79,78,44,32,77,105,107,101,32,72,97,109,98,117,114,103,32,40,83,116,97,110,102,111,114,100,32,85,110,105,118,101,114,115,105,116,121,41,0 66.align 2 67.size _vpaes_consts,.-_vpaes_consts 68.align 6 69@@ 70@@ _aes_preheat 71@@ 72@@ Fills q9-q15 as specified below. 73@@ 74.type _vpaes_preheat,%function 75.align 4 76_vpaes_preheat: 77 adr r10, .Lk_inv 78 vmov.i8 q9, #0x0f @ .Lk_s0F 79 vld1.64 {q10,q11}, [r10]! @ .Lk_inv 80 add r10, r10, #64 @ Skip .Lk_ipt, .Lk_sbo 81 vld1.64 {q12,q13}, [r10]! @ .Lk_sb1 82 vld1.64 {q14,q15}, [r10] @ .Lk_sb2 83 bx lr 84 85@@ 86@@ _aes_encrypt_core 87@@ 88@@ AES-encrypt q0. 89@@ 90@@ Inputs: 91@@ q0 = input 92@@ q9-q15 as in _vpaes_preheat 93@@ [r2] = scheduled keys 94@@ 95@@ Output in q0 96@@ Clobbers q1-q5, r8-r11 97@@ Preserves q6-q8 so you get some local vectors 98@@ 99@@ 100.type _vpaes_encrypt_core,%function 101.align 4 102_vpaes_encrypt_core: 103 mov r9, r2 104 ldr r8, [r2,#240] @ pull rounds 105 adr r11, .Lk_ipt 106 @ vmovdqa .Lk_ipt(%rip), %xmm2 # iptlo 107 @ vmovdqa .Lk_ipt+16(%rip), %xmm3 # ipthi 108 vld1.64 {q2, q3}, [r11] 109 adr r11, .Lk_mc_forward+16 110 vld1.64 {q5}, [r9]! @ vmovdqu (%r9), %xmm5 # round0 key 111 vand q1, q0, q9 @ vpand %xmm9, %xmm0, %xmm1 112 vshr.u8 q0, q0, #4 @ vpsrlb $4, %xmm0, %xmm0 113 vtbl.8 d2, {q2}, d2 @ vpshufb %xmm1, %xmm2, %xmm1 114 vtbl.8 d3, {q2}, d3 115 vtbl.8 d4, {q3}, d0 @ vpshufb %xmm0, %xmm3, %xmm2 116 vtbl.8 d5, {q3}, d1 117 veor q0, q1, q5 @ vpxor %xmm5, %xmm1, %xmm0 118 veor q0, q0, q2 @ vpxor %xmm2, %xmm0, %xmm0 119 120 @ .Lenc_entry ends with a bnz instruction which is normally paired with 121 @ subs in .Lenc_loop. 122 tst r8, r8 123 b .Lenc_entry 124 125.align 4 126.Lenc_loop: 127 @ middle of middle round 128 add r10, r11, #0x40 129 vtbl.8 d8, {q13}, d4 @ vpshufb %xmm2, %xmm13, %xmm4 # 4 = sb1u 130 vtbl.8 d9, {q13}, d5 131 vld1.64 {q1}, [r11]! @ vmovdqa -0x40(%r11,%r10), %xmm1 # .Lk_mc_forward[] 132 vtbl.8 d0, {q12}, d6 @ vpshufb %xmm3, %xmm12, %xmm0 # 0 = sb1t 133 vtbl.8 d1, {q12}, d7 134 veor q4, q4, q5 @ vpxor %xmm5, %xmm4, %xmm4 # 4 = sb1u + k 135 vtbl.8 d10, {q15}, d4 @ vpshufb %xmm2, %xmm15, %xmm5 # 4 = sb2u 136 vtbl.8 d11, {q15}, d5 137 veor q0, q0, q4 @ vpxor %xmm4, %xmm0, %xmm0 # 0 = A 138 vtbl.8 d4, {q14}, d6 @ vpshufb %xmm3, %xmm14, %xmm2 # 2 = sb2t 139 vtbl.8 d5, {q14}, d7 140 vld1.64 {q4}, [r10] @ vmovdqa (%r11,%r10), %xmm4 # .Lk_mc_backward[] 141 vtbl.8 d6, {q0}, d2 @ vpshufb %xmm1, %xmm0, %xmm3 # 0 = B 142 vtbl.8 d7, {q0}, d3 143 veor q2, q2, q5 @ vpxor %xmm5, %xmm2, %xmm2 # 2 = 2A 144 @ Write to q5 instead of q0, so the table and destination registers do 145 @ not overlap. 146 vtbl.8 d10, {q0}, d8 @ vpshufb %xmm4, %xmm0, %xmm0 # 3 = D 147 vtbl.8 d11, {q0}, d9 148 veor q3, q3, q2 @ vpxor %xmm2, %xmm3, %xmm3 # 0 = 2A+B 149 vtbl.8 d8, {q3}, d2 @ vpshufb %xmm1, %xmm3, %xmm4 # 0 = 2B+C 150 vtbl.8 d9, {q3}, d3 151 @ Here we restore the original q0/q5 usage. 152 veor q0, q5, q3 @ vpxor %xmm3, %xmm0, %xmm0 # 3 = 2A+B+D 153 and r11, r11, #~(1<<6) @ and $0x30, %r11 # ... mod 4 154 veor q0, q0, q4 @ vpxor %xmm4, %xmm0, %xmm0 # 0 = 2A+3B+C+D 155 subs r8, r8, #1 @ nr-- 156 157.Lenc_entry: 158 @ top of round 159 vand q1, q0, q9 @ vpand %xmm0, %xmm9, %xmm1 # 0 = k 160 vshr.u8 q0, q0, #4 @ vpsrlb $4, %xmm0, %xmm0 # 1 = i 161 vtbl.8 d10, {q11}, d2 @ vpshufb %xmm1, %xmm11, %xmm5 # 2 = a/k 162 vtbl.8 d11, {q11}, d3 163 veor q1, q1, q0 @ vpxor %xmm0, %xmm1, %xmm1 # 0 = j 164 vtbl.8 d6, {q10}, d0 @ vpshufb %xmm0, %xmm10, %xmm3 # 3 = 1/i 165 vtbl.8 d7, {q10}, d1 166 vtbl.8 d8, {q10}, d2 @ vpshufb %xmm1, %xmm10, %xmm4 # 4 = 1/j 167 vtbl.8 d9, {q10}, d3 168 veor q3, q3, q5 @ vpxor %xmm5, %xmm3, %xmm3 # 3 = iak = 1/i + a/k 169 veor q4, q4, q5 @ vpxor %xmm5, %xmm4, %xmm4 # 4 = jak = 1/j + a/k 170 vtbl.8 d4, {q10}, d6 @ vpshufb %xmm3, %xmm10, %xmm2 # 2 = 1/iak 171 vtbl.8 d5, {q10}, d7 172 vtbl.8 d6, {q10}, d8 @ vpshufb %xmm4, %xmm10, %xmm3 # 3 = 1/jak 173 vtbl.8 d7, {q10}, d9 174 veor q2, q2, q1 @ vpxor %xmm1, %xmm2, %xmm2 # 2 = io 175 veor q3, q3, q0 @ vpxor %xmm0, %xmm3, %xmm3 # 3 = jo 176 vld1.64 {q5}, [r9]! @ vmovdqu (%r9), %xmm5 177 bne .Lenc_loop 178 179 @ middle of last round 180 add r10, r11, #0x80 181 182 adr r11, .Lk_sbo 183 @ Read to q1 instead of q4, so the vtbl.8 instruction below does not 184 @ overlap table and destination registers. 185 vld1.64 {q1}, [r11]! @ vmovdqa -0x60(%r10), %xmm4 # 3 : sbou 186 vld1.64 {q0}, [r11] @ vmovdqa -0x50(%r10), %xmm0 # 0 : sbot .Lk_sbo+16 187 vtbl.8 d8, {q1}, d4 @ vpshufb %xmm2, %xmm4, %xmm4 # 4 = sbou 188 vtbl.8 d9, {q1}, d5 189 vld1.64 {q1}, [r10] @ vmovdqa 0x40(%r11,%r10), %xmm1 # .Lk_sr[] 190 @ Write to q2 instead of q0 below, to avoid overlapping table and 191 @ destination registers. 192 vtbl.8 d4, {q0}, d6 @ vpshufb %xmm3, %xmm0, %xmm0 # 0 = sb1t 193 vtbl.8 d5, {q0}, d7 194 veor q4, q4, q5 @ vpxor %xmm5, %xmm4, %xmm4 # 4 = sb1u + k 195 veor q2, q2, q4 @ vpxor %xmm4, %xmm0, %xmm0 # 0 = A 196 @ Here we restore the original q0/q2 usage. 197 vtbl.8 d0, {q2}, d2 @ vpshufb %xmm1, %xmm0, %xmm0 198 vtbl.8 d1, {q2}, d3 199 bx lr 200.size _vpaes_encrypt_core,.-_vpaes_encrypt_core 201 202.globl vpaes_encrypt 203.hidden vpaes_encrypt 204.type vpaes_encrypt,%function 205.align 4 206vpaes_encrypt: 207 @ _vpaes_encrypt_core uses r8-r11. Round up to r7-r11 to maintain stack 208 @ alignment. 209 stmdb sp!, {r7,r8,r9,r10,r11,lr} 210 @ _vpaes_encrypt_core uses q4-q5 (d8-d11), which are callee-saved. 211 vstmdb sp!, {d8,d9,d10,d11} 212 213 vld1.64 {q0}, [r0] 214 bl _vpaes_preheat 215 bl _vpaes_encrypt_core 216 vst1.64 {q0}, [r1] 217 218 vldmia sp!, {d8,d9,d10,d11} 219 ldmia sp!, {r7,r8,r9,r10,r11, pc} @ return 220.size vpaes_encrypt,.-vpaes_encrypt 221@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ 222@@ @@ 223@@ AES key schedule @@ 224@@ @@ 225@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ 226 227@ This function diverges from both x86_64 and armv7 in which constants are 228@ pinned. x86_64 has a common preheat function for all operations. aarch64 229@ separates them because it has enough registers to pin nearly all constants. 230@ armv7 does not have enough registers, but needing explicit loads and stores 231@ also complicates using x86_64's register allocation directly. 232@ 233@ We pin some constants for convenience and leave q14 and q15 free to load 234@ others on demand. 235 236@ 237@ Key schedule constants 238@ 239.type _vpaes_key_consts,%object 240.align 4 241_vpaes_key_consts: 242.Lk_rcon:@ rcon 243.quad 0x1F8391B9AF9DEEB6, 0x702A98084D7C7D81 244 245.Lk_opt:@ output transform 246.quad 0xFF9F4929D6B66000, 0xF7974121DEBE6808 247.quad 0x01EDBD5150BCEC00, 0xE10D5DB1B05C0CE0 248.Lk_deskew:@ deskew tables: inverts the sbox's "skew" 249.quad 0x07E4A34047A4E300, 0x1DFEB95A5DBEF91A 250.quad 0x5F36B5DC83EA6900, 0x2841C2ABF49D1E77 251.size _vpaes_key_consts,.-_vpaes_key_consts 252 253.type _vpaes_key_preheat,%function 254.align 4 255_vpaes_key_preheat: 256 adr r11, .Lk_rcon 257 vmov.i8 q12, #0x5b @ .Lk_s63 258 adr r10, .Lk_inv @ Must be aligned to 8 mod 16. 259 vmov.i8 q9, #0x0f @ .Lk_s0F 260 vld1.64 {q10,q11}, [r10] @ .Lk_inv 261 vld1.64 {q8}, [r11] @ .Lk_rcon 262 bx lr 263.size _vpaes_key_preheat,.-_vpaes_key_preheat 264 265.type _vpaes_schedule_core,%function 266.align 4 267_vpaes_schedule_core: 268 @ We only need to save lr, but ARM requires an 8-byte stack alignment, 269 @ so save an extra register. 270 stmdb sp!, {r3,lr} 271 272 bl _vpaes_key_preheat @ load the tables 273 274 adr r11, .Lk_ipt @ Must be aligned to 8 mod 16. 275 vld1.64 {q0}, [r0]! @ vmovdqu (%rdi), %xmm0 # load key (unaligned) 276 277 @ input transform 278 @ Use q4 here rather than q3 so .Lschedule_am_decrypting does not 279 @ overlap table and destination. 280 vmov q4, q0 @ vmovdqa %xmm0, %xmm3 281 bl _vpaes_schedule_transform 282 adr r10, .Lk_sr @ Must be aligned to 8 mod 16. 283 vmov q7, q0 @ vmovdqa %xmm0, %xmm7 284 285 add r8, r8, r10 286 287 @ encrypting, output zeroth round key after transform 288 vst1.64 {q0}, [r2] @ vmovdqu %xmm0, (%rdx) 289 290 @ *ring*: Decryption removed. 291 292.Lschedule_go: 293 cmp r1, #192 @ cmp $192, %esi 294 bhi .Lschedule_256 295 @ 128: fall though 296 297@@ 298@@ .schedule_128 299@@ 300@@ 128-bit specific part of key schedule. 301@@ 302@@ This schedule is really simple, because all its parts 303@@ are accomplished by the subroutines. 304@@ 305.Lschedule_128: 306 mov r0, #10 @ mov $10, %esi 307 308.Loop_schedule_128: 309 bl _vpaes_schedule_round 310 subs r0, r0, #1 @ dec %esi 311 beq .Lschedule_mangle_last 312 bl _vpaes_schedule_mangle @ write output 313 b .Loop_schedule_128 314 315@@ 316@@ .aes_schedule_256 317@@ 318@@ 256-bit specific part of key schedule. 319@@ 320@@ The structure here is very similar to the 128-bit 321@@ schedule, but with an additional "low side" in 322@@ q6. The low side's rounds are the same as the 323@@ high side's, except no rcon and no rotation. 324@@ 325.align 4 326.Lschedule_256: 327 vld1.64 {q0}, [r0] @ vmovdqu 16(%rdi),%xmm0 # load key part 2 (unaligned) 328 bl _vpaes_schedule_transform @ input transform 329 mov r0, #7 @ mov $7, %esi 330 331.Loop_schedule_256: 332 bl _vpaes_schedule_mangle @ output low result 333 vmov q6, q0 @ vmovdqa %xmm0, %xmm6 # save cur_lo in xmm6 334 335 @ high round 336 bl _vpaes_schedule_round 337 subs r0, r0, #1 @ dec %esi 338 beq .Lschedule_mangle_last 339 bl _vpaes_schedule_mangle 340 341 @ low round. swap xmm7 and xmm6 342 vdup.32 q0, d1[1] @ vpshufd $0xFF, %xmm0, %xmm0 343 vmov.i8 q4, #0 344 vmov q5, q7 @ vmovdqa %xmm7, %xmm5 345 vmov q7, q6 @ vmovdqa %xmm6, %xmm7 346 bl _vpaes_schedule_low_round 347 vmov q7, q5 @ vmovdqa %xmm5, %xmm7 348 349 b .Loop_schedule_256 350 351@@ 352@@ .aes_schedule_mangle_last 353@@ 354@@ Mangler for last round of key schedule 355@@ Mangles q0 356@@ when encrypting, outputs out(q0) ^ 63 357@@ when decrypting, outputs unskew(q0) 358@@ 359@@ Always called right before return... jumps to cleanup and exits 360@@ 361.align 4 362.Lschedule_mangle_last: 363 @ schedule last round key from xmm0 364 adr r11, .Lk_deskew @ lea .Lk_deskew(%rip),%r11 # prepare to deskew 365 366 @ encrypting 367 vld1.64 {q1}, [r8] @ vmovdqa (%r8,%r10),%xmm1 368 adr r11, .Lk_opt @ lea .Lk_opt(%rip), %r11 # prepare to output transform 369 add r2, r2, #32 @ add $32, %rdx 370 vmov q2, q0 371 vtbl.8 d0, {q2}, d2 @ vpshufb %xmm1, %xmm0, %xmm0 # output permute 372 vtbl.8 d1, {q2}, d3 373 374.Lschedule_mangle_last_dec: 375 sub r2, r2, #16 @ add $-16, %rdx 376 veor q0, q0, q12 @ vpxor .Lk_s63(%rip), %xmm0, %xmm0 377 bl _vpaes_schedule_transform @ output transform 378 vst1.64 {q0}, [r2] @ vmovdqu %xmm0, (%rdx) # save last key 379 380 @ cleanup 381 veor q0, q0, q0 @ vpxor %xmm0, %xmm0, %xmm0 382 veor q1, q1, q1 @ vpxor %xmm1, %xmm1, %xmm1 383 veor q2, q2, q2 @ vpxor %xmm2, %xmm2, %xmm2 384 veor q3, q3, q3 @ vpxor %xmm3, %xmm3, %xmm3 385 veor q4, q4, q4 @ vpxor %xmm4, %xmm4, %xmm4 386 veor q5, q5, q5 @ vpxor %xmm5, %xmm5, %xmm5 387 veor q6, q6, q6 @ vpxor %xmm6, %xmm6, %xmm6 388 veor q7, q7, q7 @ vpxor %xmm7, %xmm7, %xmm7 389 ldmia sp!, {r3,pc} @ return 390.size _vpaes_schedule_core,.-_vpaes_schedule_core 391 392@@ 393@@ .aes_schedule_round 394@@ 395@@ Runs one main round of the key schedule on q0, q7 396@@ 397@@ Specifically, runs subbytes on the high dword of q0 398@@ then rotates it by one byte and xors into the low dword of 399@@ q7. 400@@ 401@@ Adds rcon from low byte of q8, then rotates q8 for 402@@ next rcon. 403@@ 404@@ Smears the dwords of q7 by xoring the low into the 405@@ second low, result into third, result into highest. 406@@ 407@@ Returns results in q7 = q0. 408@@ Clobbers q1-q4, r11. 409@@ 410.type _vpaes_schedule_round,%function 411.align 4 412_vpaes_schedule_round: 413 @ extract rcon from xmm8 414 vmov.i8 q4, #0 @ vpxor %xmm4, %xmm4, %xmm4 415 vext.8 q1, q8, q4, #15 @ vpalignr $15, %xmm8, %xmm4, %xmm1 416 vext.8 q8, q8, q8, #15 @ vpalignr $15, %xmm8, %xmm8, %xmm8 417 veor q7, q7, q1 @ vpxor %xmm1, %xmm7, %xmm7 418 419 @ rotate 420 vdup.32 q0, d1[1] @ vpshufd $0xFF, %xmm0, %xmm0 421 vext.8 q0, q0, q0, #1 @ vpalignr $1, %xmm0, %xmm0, %xmm0 422 423 @ fall through... 424 425 @ low round: same as high round, but no rotation and no rcon. 426_vpaes_schedule_low_round: 427 @ The x86_64 version pins .Lk_sb1 in %xmm13 and .Lk_sb1+16 in %xmm12. 428 @ We pin other values in _vpaes_key_preheat, so load them now. 429 adr r11, .Lk_sb1 430 vld1.64 {q14,q15}, [r11] 431 432 @ smear xmm7 433 vext.8 q1, q4, q7, #12 @ vpslldq $4, %xmm7, %xmm1 434 veor q7, q7, q1 @ vpxor %xmm1, %xmm7, %xmm7 435 vext.8 q4, q4, q7, #8 @ vpslldq $8, %xmm7, %xmm4 436 437 @ subbytes 438 vand q1, q0, q9 @ vpand %xmm9, %xmm0, %xmm1 # 0 = k 439 vshr.u8 q0, q0, #4 @ vpsrlb $4, %xmm0, %xmm0 # 1 = i 440 veor q7, q7, q4 @ vpxor %xmm4, %xmm7, %xmm7 441 vtbl.8 d4, {q11}, d2 @ vpshufb %xmm1, %xmm11, %xmm2 # 2 = a/k 442 vtbl.8 d5, {q11}, d3 443 veor q1, q1, q0 @ vpxor %xmm0, %xmm1, %xmm1 # 0 = j 444 vtbl.8 d6, {q10}, d0 @ vpshufb %xmm0, %xmm10, %xmm3 # 3 = 1/i 445 vtbl.8 d7, {q10}, d1 446 veor q3, q3, q2 @ vpxor %xmm2, %xmm3, %xmm3 # 3 = iak = 1/i + a/k 447 vtbl.8 d8, {q10}, d2 @ vpshufb %xmm1, %xmm10, %xmm4 # 4 = 1/j 448 vtbl.8 d9, {q10}, d3 449 veor q7, q7, q12 @ vpxor .Lk_s63(%rip), %xmm7, %xmm7 450 vtbl.8 d6, {q10}, d6 @ vpshufb %xmm3, %xmm10, %xmm3 # 2 = 1/iak 451 vtbl.8 d7, {q10}, d7 452 veor q4, q4, q2 @ vpxor %xmm2, %xmm4, %xmm4 # 4 = jak = 1/j + a/k 453 vtbl.8 d4, {q10}, d8 @ vpshufb %xmm4, %xmm10, %xmm2 # 3 = 1/jak 454 vtbl.8 d5, {q10}, d9 455 veor q3, q3, q1 @ vpxor %xmm1, %xmm3, %xmm3 # 2 = io 456 veor q2, q2, q0 @ vpxor %xmm0, %xmm2, %xmm2 # 3 = jo 457 vtbl.8 d8, {q15}, d6 @ vpshufb %xmm3, %xmm13, %xmm4 # 4 = sbou 458 vtbl.8 d9, {q15}, d7 459 vtbl.8 d2, {q14}, d4 @ vpshufb %xmm2, %xmm12, %xmm1 # 0 = sb1t 460 vtbl.8 d3, {q14}, d5 461 veor q1, q1, q4 @ vpxor %xmm4, %xmm1, %xmm1 # 0 = sbox output 462 463 @ add in smeared stuff 464 veor q0, q1, q7 @ vpxor %xmm7, %xmm1, %xmm0 465 veor q7, q1, q7 @ vmovdqa %xmm0, %xmm7 466 bx lr 467.size _vpaes_schedule_round,.-_vpaes_schedule_round 468 469@@ 470@@ .aes_schedule_transform 471@@ 472@@ Linear-transform q0 according to tables at [r11] 473@@ 474@@ Requires that q9 = 0x0F0F... as in preheat 475@@ Output in q0 476@@ Clobbers q1, q2, q14, q15 477@@ 478.type _vpaes_schedule_transform,%function 479.align 4 480_vpaes_schedule_transform: 481 vld1.64 {q14,q15}, [r11] @ vmovdqa (%r11), %xmm2 # lo 482 @ vmovdqa 16(%r11), %xmm1 # hi 483 vand q1, q0, q9 @ vpand %xmm9, %xmm0, %xmm1 484 vshr.u8 q0, q0, #4 @ vpsrlb $4, %xmm0, %xmm0 485 vtbl.8 d4, {q14}, d2 @ vpshufb %xmm1, %xmm2, %xmm2 486 vtbl.8 d5, {q14}, d3 487 vtbl.8 d0, {q15}, d0 @ vpshufb %xmm0, %xmm1, %xmm0 488 vtbl.8 d1, {q15}, d1 489 veor q0, q0, q2 @ vpxor %xmm2, %xmm0, %xmm0 490 bx lr 491.size _vpaes_schedule_transform,.-_vpaes_schedule_transform 492 493@@ 494@@ .aes_schedule_mangle 495@@ 496@@ Mangles q0 from (basis-transformed) standard version 497@@ to our version. 498@@ 499@@ On encrypt, 500@@ xor with 0x63 501@@ multiply by circulant 0,1,1,1 502@@ apply shiftrows transform 503@@ 504@@ On decrypt, 505@@ xor with 0x63 506@@ multiply by "inverse mixcolumns" circulant E,B,D,9 507@@ deskew 508@@ apply shiftrows transform 509@@ 510@@ 511@@ Writes out to [r2], and increments or decrements it 512@@ Keeps track of round number mod 4 in r8 513@@ Preserves q0 514@@ Clobbers q1-q5 515@@ 516.type _vpaes_schedule_mangle,%function 517.align 4 518_vpaes_schedule_mangle: 519 tst r3, r3 520 vmov q4, q0 @ vmovdqa %xmm0, %xmm4 # save xmm0 for later 521 adr r11, .Lk_mc_forward @ Must be aligned to 8 mod 16. 522 vld1.64 {q5}, [r11] @ vmovdqa .Lk_mc_forward(%rip),%xmm5 523 524 @ encrypting 525 @ Write to q2 so we do not overlap table and destination below. 526 veor q2, q0, q12 @ vpxor .Lk_s63(%rip), %xmm0, %xmm4 527 add r2, r2, #16 @ add $16, %rdx 528 vtbl.8 d8, {q2}, d10 @ vpshufb %xmm5, %xmm4, %xmm4 529 vtbl.8 d9, {q2}, d11 530 vtbl.8 d2, {q4}, d10 @ vpshufb %xmm5, %xmm4, %xmm1 531 vtbl.8 d3, {q4}, d11 532 vtbl.8 d6, {q1}, d10 @ vpshufb %xmm5, %xmm1, %xmm3 533 vtbl.8 d7, {q1}, d11 534 veor q4, q4, q1 @ vpxor %xmm1, %xmm4, %xmm4 535 vld1.64 {q1}, [r8] @ vmovdqa (%r8,%r10), %xmm1 536 veor q3, q3, q4 @ vpxor %xmm4, %xmm3, %xmm3 537 538.Lschedule_mangle_both: 539 @ Write to q2 so table and destination do not overlap. 540 vtbl.8 d4, {q3}, d2 @ vpshufb %xmm1, %xmm3, %xmm3 541 vtbl.8 d5, {q3}, d3 542 add r8, r8, #64-16 @ add $-16, %r8 543 and r8, r8, #~(1<<6) @ and $0x30, %r8 544 vst1.64 {q2}, [r2] @ vmovdqu %xmm3, (%rdx) 545 bx lr 546.size _vpaes_schedule_mangle,.-_vpaes_schedule_mangle 547 548.globl vpaes_set_encrypt_key 549.hidden vpaes_set_encrypt_key 550.type vpaes_set_encrypt_key,%function 551.align 4 552vpaes_set_encrypt_key: 553 stmdb sp!, {r7,r8,r9,r10,r11, lr} 554 vstmdb sp!, {d8,d9,d10,d11,d12,d13,d14,d15} 555 556 lsr r9, r1, #5 @ shr $5,%eax 557 add r9, r9, #5 @ $5,%eax 558 str r9, [r2,#240] @ mov %eax,240(%rdx) # AES_KEY->rounds = nbits/32+5; 559 560 mov r3, #0 @ mov $0,%ecx 561 mov r8, #0x30 @ mov $0x30,%r8d 562 bl _vpaes_schedule_core 563 eor r0, r0, r0 564 565 vldmia sp!, {d8,d9,d10,d11,d12,d13,d14,d15} 566 ldmia sp!, {r7,r8,r9,r10,r11, pc} @ return 567.size vpaes_set_encrypt_key,.-vpaes_set_encrypt_key 568 569@ Additional constants for converting to bsaes. 570.type _vpaes_convert_consts,%object 571.align 4 572_vpaes_convert_consts: 573@ .Lk_opt_then_skew applies skew(opt(x)) XOR 0x63, where skew is the linear 574@ transform in the AES S-box. 0x63 is incorporated into the low half of the 575@ table. This was computed with the following script: 576@ 577@ def u64s_to_u128(x, y): 578@ return x | (y << 64) 579@ def u128_to_u64s(w): 580@ return w & ((1<<64)-1), w >> 64 581@ def get_byte(w, i): 582@ return (w >> (i*8)) & 0xff 583@ def apply_table(table, b): 584@ lo = b & 0xf 585@ hi = b >> 4 586@ return get_byte(table[0], lo) ^ get_byte(table[1], hi) 587@ def opt(b): 588@ table = [ 589@ u64s_to_u128(0xFF9F4929D6B66000, 0xF7974121DEBE6808), 590@ u64s_to_u128(0x01EDBD5150BCEC00, 0xE10D5DB1B05C0CE0), 591@ ] 592@ return apply_table(table, b) 593@ def rot_byte(b, n): 594@ return 0xff & ((b << n) | (b >> (8-n))) 595@ def skew(x): 596@ return (x ^ rot_byte(x, 1) ^ rot_byte(x, 2) ^ rot_byte(x, 3) ^ 597@ rot_byte(x, 4)) 598@ table = [0, 0] 599@ for i in range(16): 600@ table[0] |= (skew(opt(i)) ^ 0x63) << (i*8) 601@ table[1] |= skew(opt(i<<4)) << (i*8) 602@ print(" .quad 0x%016x, 0x%016x" % u128_to_u64s(table[0])) 603@ print(" .quad 0x%016x, 0x%016x" % u128_to_u64s(table[1])) 604.Lk_opt_then_skew: 605.quad 0x9cb8436798bc4763, 0x6440bb9f6044bf9b 606.quad 0x1f30062936192f00, 0xb49bad829db284ab 607 608@ void vpaes_encrypt_key_to_bsaes(AES_KEY *bsaes, const AES_KEY *vpaes); 609.globl vpaes_encrypt_key_to_bsaes 610.hidden vpaes_encrypt_key_to_bsaes 611.type vpaes_encrypt_key_to_bsaes,%function 612.align 4 613vpaes_encrypt_key_to_bsaes: 614 stmdb sp!, {r11, lr} 615 616 @ See _vpaes_schedule_core for the key schedule logic. In particular, 617 @ _vpaes_schedule_transform(.Lk_ipt) (section 2.2 of the paper), 618 @ _vpaes_schedule_mangle (section 4.3), and .Lschedule_mangle_last 619 @ contain the transformations not in the bsaes representation. This 620 @ function inverts those transforms. 621 @ 622 @ Note also that bsaes-armv7.pl expects aes-armv4.pl's key 623 @ representation, which does not match the other aes_nohw_* 624 @ implementations. The ARM aes_nohw_* stores each 32-bit word 625 @ byteswapped, as a convenience for (unsupported) big-endian ARM, at the 626 @ cost of extra REV and VREV32 operations in little-endian ARM. 627 628 vmov.i8 q9, #0x0f @ Required by _vpaes_schedule_transform 629 adr r2, .Lk_mc_forward @ Must be aligned to 8 mod 16. 630 add r3, r2, 0x90 @ .Lk_sr+0x10-.Lk_mc_forward = 0x90 (Apple's toolchain doesn't support the expression) 631 632 vld1.64 {q12}, [r2] 633 vmov.i8 q10, #0x5b @ .Lk_s63 from vpaes-x86_64 634 adr r11, .Lk_opt @ Must be aligned to 8 mod 16. 635 vmov.i8 q11, #0x63 @ .LK_s63 without .Lk_ipt applied 636 637 @ vpaes stores one fewer round count than bsaes, but the number of keys 638 @ is the same. 639 ldr r2, [r1,#240] 640 add r2, r2, #1 641 str r2, [r0,#240] 642 643 @ The first key is transformed with _vpaes_schedule_transform(.Lk_ipt). 644 @ Invert this with .Lk_opt. 645 vld1.64 {q0}, [r1]! 646 bl _vpaes_schedule_transform 647 vrev32.8 q0, q0 648 vst1.64 {q0}, [r0]! 649 650 @ The middle keys have _vpaes_schedule_transform(.Lk_ipt) applied, 651 @ followed by _vpaes_schedule_mangle. _vpaes_schedule_mangle XORs 0x63, 652 @ multiplies by the circulant 0,1,1,1, then applies ShiftRows. 653.Loop_enc_key_to_bsaes: 654 vld1.64 {q0}, [r1]! 655 656 @ Invert the ShiftRows step (see .Lschedule_mangle_both). Note we cycle 657 @ r3 in the opposite direction and start at .Lk_sr+0x10 instead of 0x30. 658 @ We use r3 rather than r8 to avoid a callee-saved register. 659 vld1.64 {q1}, [r3] 660 vtbl.8 d4, {q0}, d2 661 vtbl.8 d5, {q0}, d3 662 add r3, r3, #16 663 and r3, r3, #~(1<<6) 664 vmov q0, q2 665 666 @ Handle the last key differently. 667 subs r2, r2, #1 668 beq .Loop_enc_key_to_bsaes_last 669 670 @ Multiply by the circulant. This is its own inverse. 671 vtbl.8 d2, {q0}, d24 672 vtbl.8 d3, {q0}, d25 673 vmov q0, q1 674 vtbl.8 d4, {q1}, d24 675 vtbl.8 d5, {q1}, d25 676 veor q0, q0, q2 677 vtbl.8 d2, {q2}, d24 678 vtbl.8 d3, {q2}, d25 679 veor q0, q0, q1 680 681 @ XOR and finish. 682 veor q0, q0, q10 683 bl _vpaes_schedule_transform 684 vrev32.8 q0, q0 685 vst1.64 {q0}, [r0]! 686 b .Loop_enc_key_to_bsaes 687 688.Loop_enc_key_to_bsaes_last: 689 @ The final key does not have a basis transform (note 690 @ .Lschedule_mangle_last inverts the original transform). It only XORs 691 @ 0x63 and applies ShiftRows. The latter was already inverted in the 692 @ loop. Note that, because we act on the original representation, we use 693 @ q11, not q10. 694 veor q0, q0, q11 695 vrev32.8 q0, q0 696 vst1.64 {q0}, [r0] 697 698 @ Wipe registers which contained key material. 699 veor q0, q0, q0 700 veor q1, q1, q1 701 veor q2, q2, q2 702 703 ldmia sp!, {r11, pc} @ return 704.size vpaes_encrypt_key_to_bsaes,.-vpaes_encrypt_key_to_bsaes 705.globl vpaes_ctr32_encrypt_blocks 706.hidden vpaes_ctr32_encrypt_blocks 707.type vpaes_ctr32_encrypt_blocks,%function 708.align 4 709vpaes_ctr32_encrypt_blocks: 710 mov ip, sp 711 stmdb sp!, {r7,r8,r9,r10,r11, lr} 712 @ This function uses q4-q7 (d8-d15), which are callee-saved. 713 vstmdb sp!, {d8,d9,d10,d11,d12,d13,d14,d15} 714 715 cmp r2, #0 716 @ r8 is passed on the stack. 717 ldr r8, [ip] 718 beq .Lctr32_done 719 720 @ _vpaes_encrypt_core expects the key in r2, so swap r2 and r3. 721 mov r9, r3 722 mov r3, r2 723 mov r2, r9 724 725 @ Load the IV and counter portion. 726 ldr r7, [r8, #12] 727 vld1.8 {q7}, [r8] 728 729 bl _vpaes_preheat 730 rev r7, r7 @ The counter is big-endian. 731 732.Lctr32_loop: 733 vmov q0, q7 734 vld1.8 {q6}, [r0]! @ .Load input ahead of time 735 bl _vpaes_encrypt_core 736 veor q0, q0, q6 @ XOR input and result 737 vst1.8 {q0}, [r1]! 738 subs r3, r3, #1 739 @ Update the counter. 740 add r7, r7, #1 741 rev r9, r7 742 vmov.32 d15[1], r9 743 bne .Lctr32_loop 744 745.Lctr32_done: 746 vldmia sp!, {d8,d9,d10,d11,d12,d13,d14,d15} 747 ldmia sp!, {r7,r8,r9,r10,r11, pc} @ return 748.size vpaes_ctr32_encrypt_blocks,.-vpaes_ctr32_encrypt_blocks 749#endif 750#endif // !OPENSSL_NO_ASM 751.section .note.GNU-stack,"",%progbits 752