1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2|* *| 3|* "Fast" Instruction Selector for the AArch64 target *| 4|* *| 5|* Automatically generated file, do not edit! *| 6|* *| 7\*===----------------------------------------------------------------------===*/ 8 9 10// FastEmit Immediate Predicate functions. 11static bool Predicate_imm0_31(int64_t Imm) { 12 13 return ((uint64_t)Imm) < 32; 14 15} 16static bool Predicate_imm0_63(int64_t Imm) { 17 18 return ((uint64_t)Imm) < 64; 19 20} 21static bool Predicate_imm32_0_31(int64_t Imm) { 22 23 return ((uint64_t)Imm) < 32; 24 25} 26static bool Predicate_tbz_imm0_31_diag(int64_t Imm) { 27 28 return (((uint32_t)Imm) < 32); 29 30} 31static bool Predicate_tbz_imm32_63(int64_t Imm) { 32 33 return (((uint32_t)Imm) > 31) && (((uint32_t)Imm) < 64); 34 35} 36static bool Predicate_VectorIndexD(int64_t Imm) { 37 return ((uint64_t)Imm) < 2; 38} 39static bool Predicate_VectorIndexS(int64_t Imm) { 40 return ((uint64_t)Imm) < 4; 41} 42static bool Predicate_VectorIndexH(int64_t Imm) { 43 return ((uint64_t)Imm) < 8; 44} 45static bool Predicate_VectorIndexB(int64_t Imm) { 46 return ((uint64_t)Imm) < 16; 47} 48static bool Predicate_imm0_255(int64_t Imm) { 49 50 return ((uint32_t)Imm) < 256; 51 52} 53static bool Predicate_vecshiftL64(int64_t Imm) { 54 55 return (((uint32_t)Imm) < 64); 56 57} 58static bool Predicate_vecshiftL32(int64_t Imm) { 59 60 return (((uint32_t)Imm) < 32); 61 62} 63static bool Predicate_vecshiftR64(int64_t Imm) { 64 65 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 65); 66 67} 68static bool Predicate_vecshiftL8(int64_t Imm) { 69 70 return (((uint32_t)Imm) < 8); 71 72} 73static bool Predicate_vecshiftL16(int64_t Imm) { 74 75 return (((uint32_t)Imm) < 16); 76 77} 78static bool Predicate_vecshiftR8(int64_t Imm) { 79 80 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 9); 81 82} 83static bool Predicate_vecshiftR16(int64_t Imm) { 84 85 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17); 86 87} 88static bool Predicate_vecshiftR32(int64_t Imm) { 89 90 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 33); 91 92} 93 94 95// FastEmit functions for AArch64ISD::THREAD_POINTER. 96 97unsigned fastEmit_AArch64ISD_THREAD_POINTER_MVT_i64_(MVT RetVT) { 98 if (RetVT.SimpleTy != MVT::i64) 99 return 0; 100 return fastEmitInst_(AArch64::MOVbaseTLS, &AArch64::GPR64RegClass); 101} 102 103unsigned fastEmit_AArch64ISD_THREAD_POINTER_(MVT VT, MVT RetVT) { 104 switch (VT.SimpleTy) { 105 case MVT::i64: return fastEmit_AArch64ISD_THREAD_POINTER_MVT_i64_(RetVT); 106 default: return 0; 107 } 108} 109 110// Top-level FastEmit function. 111 112unsigned fastEmit_(MVT VT, MVT RetVT, unsigned Opcode) override { 113 switch (Opcode) { 114 case AArch64ISD::THREAD_POINTER: return fastEmit_AArch64ISD_THREAD_POINTER_(VT, RetVT); 115 default: return 0; 116 } 117} 118 119// FastEmit functions for AArch64ISD::CALL. 120 121unsigned fastEmit_AArch64ISD_CALL_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 122 if (RetVT.SimpleTy != MVT::isVoid) 123 return 0; 124 return fastEmitInst_r(AArch64::BLR, &AArch64::GPR64RegClass, Op0, Op0IsKill); 125} 126 127unsigned fastEmit_AArch64ISD_CALL_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 128 switch (VT.SimpleTy) { 129 case MVT::i64: return fastEmit_AArch64ISD_CALL_MVT_i64_r(RetVT, Op0, Op0IsKill); 130 default: return 0; 131 } 132} 133 134// FastEmit functions for AArch64ISD::CMEQz. 135 136unsigned fastEmit_AArch64ISD_CMEQz_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 137 if (RetVT.SimpleTy != MVT::v8i8) 138 return 0; 139 if ((Subtarget->hasNEON())) { 140 return fastEmitInst_r(AArch64::CMEQv8i8rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 141 } 142 return 0; 143} 144 145unsigned fastEmit_AArch64ISD_CMEQz_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 146 if (RetVT.SimpleTy != MVT::v16i8) 147 return 0; 148 if ((Subtarget->hasNEON())) { 149 return fastEmitInst_r(AArch64::CMEQv16i8rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 150 } 151 return 0; 152} 153 154unsigned fastEmit_AArch64ISD_CMEQz_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 155 if (RetVT.SimpleTy != MVT::v4i16) 156 return 0; 157 if ((Subtarget->hasNEON())) { 158 return fastEmitInst_r(AArch64::CMEQv4i16rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 159 } 160 return 0; 161} 162 163unsigned fastEmit_AArch64ISD_CMEQz_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 164 if (RetVT.SimpleTy != MVT::v8i16) 165 return 0; 166 if ((Subtarget->hasNEON())) { 167 return fastEmitInst_r(AArch64::CMEQv8i16rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 168 } 169 return 0; 170} 171 172unsigned fastEmit_AArch64ISD_CMEQz_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 173 if (RetVT.SimpleTy != MVT::v2i32) 174 return 0; 175 if ((Subtarget->hasNEON())) { 176 return fastEmitInst_r(AArch64::CMEQv2i32rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 177 } 178 return 0; 179} 180 181unsigned fastEmit_AArch64ISD_CMEQz_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 182 if (RetVT.SimpleTy != MVT::v4i32) 183 return 0; 184 if ((Subtarget->hasNEON())) { 185 return fastEmitInst_r(AArch64::CMEQv4i32rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 186 } 187 return 0; 188} 189 190unsigned fastEmit_AArch64ISD_CMEQz_MVT_v1i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 191 if (RetVT.SimpleTy != MVT::v1i64) 192 return 0; 193 if ((Subtarget->hasNEON())) { 194 return fastEmitInst_r(AArch64::CMEQv1i64rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 195 } 196 return 0; 197} 198 199unsigned fastEmit_AArch64ISD_CMEQz_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 200 if (RetVT.SimpleTy != MVT::v2i64) 201 return 0; 202 if ((Subtarget->hasNEON())) { 203 return fastEmitInst_r(AArch64::CMEQv2i64rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 204 } 205 return 0; 206} 207 208unsigned fastEmit_AArch64ISD_CMEQz_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 209 switch (VT.SimpleTy) { 210 case MVT::v8i8: return fastEmit_AArch64ISD_CMEQz_MVT_v8i8_r(RetVT, Op0, Op0IsKill); 211 case MVT::v16i8: return fastEmit_AArch64ISD_CMEQz_MVT_v16i8_r(RetVT, Op0, Op0IsKill); 212 case MVT::v4i16: return fastEmit_AArch64ISD_CMEQz_MVT_v4i16_r(RetVT, Op0, Op0IsKill); 213 case MVT::v8i16: return fastEmit_AArch64ISD_CMEQz_MVT_v8i16_r(RetVT, Op0, Op0IsKill); 214 case MVT::v2i32: return fastEmit_AArch64ISD_CMEQz_MVT_v2i32_r(RetVT, Op0, Op0IsKill); 215 case MVT::v4i32: return fastEmit_AArch64ISD_CMEQz_MVT_v4i32_r(RetVT, Op0, Op0IsKill); 216 case MVT::v1i64: return fastEmit_AArch64ISD_CMEQz_MVT_v1i64_r(RetVT, Op0, Op0IsKill); 217 case MVT::v2i64: return fastEmit_AArch64ISD_CMEQz_MVT_v2i64_r(RetVT, Op0, Op0IsKill); 218 default: return 0; 219 } 220} 221 222// FastEmit functions for AArch64ISD::CMGEz. 223 224unsigned fastEmit_AArch64ISD_CMGEz_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 225 if (RetVT.SimpleTy != MVT::v8i8) 226 return 0; 227 if ((Subtarget->hasNEON())) { 228 return fastEmitInst_r(AArch64::CMGEv8i8rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 229 } 230 return 0; 231} 232 233unsigned fastEmit_AArch64ISD_CMGEz_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 234 if (RetVT.SimpleTy != MVT::v16i8) 235 return 0; 236 if ((Subtarget->hasNEON())) { 237 return fastEmitInst_r(AArch64::CMGEv16i8rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 238 } 239 return 0; 240} 241 242unsigned fastEmit_AArch64ISD_CMGEz_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 243 if (RetVT.SimpleTy != MVT::v4i16) 244 return 0; 245 if ((Subtarget->hasNEON())) { 246 return fastEmitInst_r(AArch64::CMGEv4i16rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 247 } 248 return 0; 249} 250 251unsigned fastEmit_AArch64ISD_CMGEz_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 252 if (RetVT.SimpleTy != MVT::v8i16) 253 return 0; 254 if ((Subtarget->hasNEON())) { 255 return fastEmitInst_r(AArch64::CMGEv8i16rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 256 } 257 return 0; 258} 259 260unsigned fastEmit_AArch64ISD_CMGEz_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 261 if (RetVT.SimpleTy != MVT::v2i32) 262 return 0; 263 if ((Subtarget->hasNEON())) { 264 return fastEmitInst_r(AArch64::CMGEv2i32rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 265 } 266 return 0; 267} 268 269unsigned fastEmit_AArch64ISD_CMGEz_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 270 if (RetVT.SimpleTy != MVT::v4i32) 271 return 0; 272 if ((Subtarget->hasNEON())) { 273 return fastEmitInst_r(AArch64::CMGEv4i32rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 274 } 275 return 0; 276} 277 278unsigned fastEmit_AArch64ISD_CMGEz_MVT_v1i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 279 if (RetVT.SimpleTy != MVT::v1i64) 280 return 0; 281 if ((Subtarget->hasNEON())) { 282 return fastEmitInst_r(AArch64::CMGEv1i64rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 283 } 284 return 0; 285} 286 287unsigned fastEmit_AArch64ISD_CMGEz_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 288 if (RetVT.SimpleTy != MVT::v2i64) 289 return 0; 290 if ((Subtarget->hasNEON())) { 291 return fastEmitInst_r(AArch64::CMGEv2i64rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 292 } 293 return 0; 294} 295 296unsigned fastEmit_AArch64ISD_CMGEz_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 297 switch (VT.SimpleTy) { 298 case MVT::v8i8: return fastEmit_AArch64ISD_CMGEz_MVT_v8i8_r(RetVT, Op0, Op0IsKill); 299 case MVT::v16i8: return fastEmit_AArch64ISD_CMGEz_MVT_v16i8_r(RetVT, Op0, Op0IsKill); 300 case MVT::v4i16: return fastEmit_AArch64ISD_CMGEz_MVT_v4i16_r(RetVT, Op0, Op0IsKill); 301 case MVT::v8i16: return fastEmit_AArch64ISD_CMGEz_MVT_v8i16_r(RetVT, Op0, Op0IsKill); 302 case MVT::v2i32: return fastEmit_AArch64ISD_CMGEz_MVT_v2i32_r(RetVT, Op0, Op0IsKill); 303 case MVT::v4i32: return fastEmit_AArch64ISD_CMGEz_MVT_v4i32_r(RetVT, Op0, Op0IsKill); 304 case MVT::v1i64: return fastEmit_AArch64ISD_CMGEz_MVT_v1i64_r(RetVT, Op0, Op0IsKill); 305 case MVT::v2i64: return fastEmit_AArch64ISD_CMGEz_MVT_v2i64_r(RetVT, Op0, Op0IsKill); 306 default: return 0; 307 } 308} 309 310// FastEmit functions for AArch64ISD::CMGTz. 311 312unsigned fastEmit_AArch64ISD_CMGTz_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 313 if (RetVT.SimpleTy != MVT::v8i8) 314 return 0; 315 if ((Subtarget->hasNEON())) { 316 return fastEmitInst_r(AArch64::CMGTv8i8rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 317 } 318 return 0; 319} 320 321unsigned fastEmit_AArch64ISD_CMGTz_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 322 if (RetVT.SimpleTy != MVT::v16i8) 323 return 0; 324 if ((Subtarget->hasNEON())) { 325 return fastEmitInst_r(AArch64::CMGTv16i8rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 326 } 327 return 0; 328} 329 330unsigned fastEmit_AArch64ISD_CMGTz_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 331 if (RetVT.SimpleTy != MVT::v4i16) 332 return 0; 333 if ((Subtarget->hasNEON())) { 334 return fastEmitInst_r(AArch64::CMGTv4i16rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 335 } 336 return 0; 337} 338 339unsigned fastEmit_AArch64ISD_CMGTz_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 340 if (RetVT.SimpleTy != MVT::v8i16) 341 return 0; 342 if ((Subtarget->hasNEON())) { 343 return fastEmitInst_r(AArch64::CMGTv8i16rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 344 } 345 return 0; 346} 347 348unsigned fastEmit_AArch64ISD_CMGTz_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 349 if (RetVT.SimpleTy != MVT::v2i32) 350 return 0; 351 if ((Subtarget->hasNEON())) { 352 return fastEmitInst_r(AArch64::CMGTv2i32rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 353 } 354 return 0; 355} 356 357unsigned fastEmit_AArch64ISD_CMGTz_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 358 if (RetVT.SimpleTy != MVT::v4i32) 359 return 0; 360 if ((Subtarget->hasNEON())) { 361 return fastEmitInst_r(AArch64::CMGTv4i32rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 362 } 363 return 0; 364} 365 366unsigned fastEmit_AArch64ISD_CMGTz_MVT_v1i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 367 if (RetVT.SimpleTy != MVT::v1i64) 368 return 0; 369 if ((Subtarget->hasNEON())) { 370 return fastEmitInst_r(AArch64::CMGTv1i64rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 371 } 372 return 0; 373} 374 375unsigned fastEmit_AArch64ISD_CMGTz_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 376 if (RetVT.SimpleTy != MVT::v2i64) 377 return 0; 378 if ((Subtarget->hasNEON())) { 379 return fastEmitInst_r(AArch64::CMGTv2i64rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 380 } 381 return 0; 382} 383 384unsigned fastEmit_AArch64ISD_CMGTz_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 385 switch (VT.SimpleTy) { 386 case MVT::v8i8: return fastEmit_AArch64ISD_CMGTz_MVT_v8i8_r(RetVT, Op0, Op0IsKill); 387 case MVT::v16i8: return fastEmit_AArch64ISD_CMGTz_MVT_v16i8_r(RetVT, Op0, Op0IsKill); 388 case MVT::v4i16: return fastEmit_AArch64ISD_CMGTz_MVT_v4i16_r(RetVT, Op0, Op0IsKill); 389 case MVT::v8i16: return fastEmit_AArch64ISD_CMGTz_MVT_v8i16_r(RetVT, Op0, Op0IsKill); 390 case MVT::v2i32: return fastEmit_AArch64ISD_CMGTz_MVT_v2i32_r(RetVT, Op0, Op0IsKill); 391 case MVT::v4i32: return fastEmit_AArch64ISD_CMGTz_MVT_v4i32_r(RetVT, Op0, Op0IsKill); 392 case MVT::v1i64: return fastEmit_AArch64ISD_CMGTz_MVT_v1i64_r(RetVT, Op0, Op0IsKill); 393 case MVT::v2i64: return fastEmit_AArch64ISD_CMGTz_MVT_v2i64_r(RetVT, Op0, Op0IsKill); 394 default: return 0; 395 } 396} 397 398// FastEmit functions for AArch64ISD::CMLEz. 399 400unsigned fastEmit_AArch64ISD_CMLEz_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 401 if (RetVT.SimpleTy != MVT::v8i8) 402 return 0; 403 if ((Subtarget->hasNEON())) { 404 return fastEmitInst_r(AArch64::CMLEv8i8rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 405 } 406 return 0; 407} 408 409unsigned fastEmit_AArch64ISD_CMLEz_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 410 if (RetVT.SimpleTy != MVT::v16i8) 411 return 0; 412 if ((Subtarget->hasNEON())) { 413 return fastEmitInst_r(AArch64::CMLEv16i8rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 414 } 415 return 0; 416} 417 418unsigned fastEmit_AArch64ISD_CMLEz_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 419 if (RetVT.SimpleTy != MVT::v4i16) 420 return 0; 421 if ((Subtarget->hasNEON())) { 422 return fastEmitInst_r(AArch64::CMLEv4i16rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 423 } 424 return 0; 425} 426 427unsigned fastEmit_AArch64ISD_CMLEz_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 428 if (RetVT.SimpleTy != MVT::v8i16) 429 return 0; 430 if ((Subtarget->hasNEON())) { 431 return fastEmitInst_r(AArch64::CMLEv8i16rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 432 } 433 return 0; 434} 435 436unsigned fastEmit_AArch64ISD_CMLEz_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 437 if (RetVT.SimpleTy != MVT::v2i32) 438 return 0; 439 if ((Subtarget->hasNEON())) { 440 return fastEmitInst_r(AArch64::CMLEv2i32rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 441 } 442 return 0; 443} 444 445unsigned fastEmit_AArch64ISD_CMLEz_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 446 if (RetVT.SimpleTy != MVT::v4i32) 447 return 0; 448 if ((Subtarget->hasNEON())) { 449 return fastEmitInst_r(AArch64::CMLEv4i32rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 450 } 451 return 0; 452} 453 454unsigned fastEmit_AArch64ISD_CMLEz_MVT_v1i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 455 if (RetVT.SimpleTy != MVT::v1i64) 456 return 0; 457 if ((Subtarget->hasNEON())) { 458 return fastEmitInst_r(AArch64::CMLEv1i64rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 459 } 460 return 0; 461} 462 463unsigned fastEmit_AArch64ISD_CMLEz_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 464 if (RetVT.SimpleTy != MVT::v2i64) 465 return 0; 466 if ((Subtarget->hasNEON())) { 467 return fastEmitInst_r(AArch64::CMLEv2i64rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 468 } 469 return 0; 470} 471 472unsigned fastEmit_AArch64ISD_CMLEz_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 473 switch (VT.SimpleTy) { 474 case MVT::v8i8: return fastEmit_AArch64ISD_CMLEz_MVT_v8i8_r(RetVT, Op0, Op0IsKill); 475 case MVT::v16i8: return fastEmit_AArch64ISD_CMLEz_MVT_v16i8_r(RetVT, Op0, Op0IsKill); 476 case MVT::v4i16: return fastEmit_AArch64ISD_CMLEz_MVT_v4i16_r(RetVT, Op0, Op0IsKill); 477 case MVT::v8i16: return fastEmit_AArch64ISD_CMLEz_MVT_v8i16_r(RetVT, Op0, Op0IsKill); 478 case MVT::v2i32: return fastEmit_AArch64ISD_CMLEz_MVT_v2i32_r(RetVT, Op0, Op0IsKill); 479 case MVT::v4i32: return fastEmit_AArch64ISD_CMLEz_MVT_v4i32_r(RetVT, Op0, Op0IsKill); 480 case MVT::v1i64: return fastEmit_AArch64ISD_CMLEz_MVT_v1i64_r(RetVT, Op0, Op0IsKill); 481 case MVT::v2i64: return fastEmit_AArch64ISD_CMLEz_MVT_v2i64_r(RetVT, Op0, Op0IsKill); 482 default: return 0; 483 } 484} 485 486// FastEmit functions for AArch64ISD::CMLTz. 487 488unsigned fastEmit_AArch64ISD_CMLTz_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 489 if (RetVT.SimpleTy != MVT::v8i8) 490 return 0; 491 if ((Subtarget->hasNEON())) { 492 return fastEmitInst_r(AArch64::CMLTv8i8rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 493 } 494 return 0; 495} 496 497unsigned fastEmit_AArch64ISD_CMLTz_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 498 if (RetVT.SimpleTy != MVT::v16i8) 499 return 0; 500 if ((Subtarget->hasNEON())) { 501 return fastEmitInst_r(AArch64::CMLTv16i8rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 502 } 503 return 0; 504} 505 506unsigned fastEmit_AArch64ISD_CMLTz_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 507 if (RetVT.SimpleTy != MVT::v4i16) 508 return 0; 509 if ((Subtarget->hasNEON())) { 510 return fastEmitInst_r(AArch64::CMLTv4i16rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 511 } 512 return 0; 513} 514 515unsigned fastEmit_AArch64ISD_CMLTz_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 516 if (RetVT.SimpleTy != MVT::v8i16) 517 return 0; 518 if ((Subtarget->hasNEON())) { 519 return fastEmitInst_r(AArch64::CMLTv8i16rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 520 } 521 return 0; 522} 523 524unsigned fastEmit_AArch64ISD_CMLTz_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 525 if (RetVT.SimpleTy != MVT::v2i32) 526 return 0; 527 if ((Subtarget->hasNEON())) { 528 return fastEmitInst_r(AArch64::CMLTv2i32rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 529 } 530 return 0; 531} 532 533unsigned fastEmit_AArch64ISD_CMLTz_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 534 if (RetVT.SimpleTy != MVT::v4i32) 535 return 0; 536 if ((Subtarget->hasNEON())) { 537 return fastEmitInst_r(AArch64::CMLTv4i32rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 538 } 539 return 0; 540} 541 542unsigned fastEmit_AArch64ISD_CMLTz_MVT_v1i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 543 if (RetVT.SimpleTy != MVT::v1i64) 544 return 0; 545 if ((Subtarget->hasNEON())) { 546 return fastEmitInst_r(AArch64::CMLTv1i64rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 547 } 548 return 0; 549} 550 551unsigned fastEmit_AArch64ISD_CMLTz_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 552 if (RetVT.SimpleTy != MVT::v2i64) 553 return 0; 554 if ((Subtarget->hasNEON())) { 555 return fastEmitInst_r(AArch64::CMLTv2i64rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 556 } 557 return 0; 558} 559 560unsigned fastEmit_AArch64ISD_CMLTz_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 561 switch (VT.SimpleTy) { 562 case MVT::v8i8: return fastEmit_AArch64ISD_CMLTz_MVT_v8i8_r(RetVT, Op0, Op0IsKill); 563 case MVT::v16i8: return fastEmit_AArch64ISD_CMLTz_MVT_v16i8_r(RetVT, Op0, Op0IsKill); 564 case MVT::v4i16: return fastEmit_AArch64ISD_CMLTz_MVT_v4i16_r(RetVT, Op0, Op0IsKill); 565 case MVT::v8i16: return fastEmit_AArch64ISD_CMLTz_MVT_v8i16_r(RetVT, Op0, Op0IsKill); 566 case MVT::v2i32: return fastEmit_AArch64ISD_CMLTz_MVT_v2i32_r(RetVT, Op0, Op0IsKill); 567 case MVT::v4i32: return fastEmit_AArch64ISD_CMLTz_MVT_v4i32_r(RetVT, Op0, Op0IsKill); 568 case MVT::v1i64: return fastEmit_AArch64ISD_CMLTz_MVT_v1i64_r(RetVT, Op0, Op0IsKill); 569 case MVT::v2i64: return fastEmit_AArch64ISD_CMLTz_MVT_v2i64_r(RetVT, Op0, Op0IsKill); 570 default: return 0; 571 } 572} 573 574// FastEmit functions for AArch64ISD::DUP. 575 576unsigned fastEmit_AArch64ISD_DUP_MVT_i32_MVT_v8i8_r(unsigned Op0, bool Op0IsKill) { 577 if ((Subtarget->hasNEON())) { 578 return fastEmitInst_r(AArch64::DUPv8i8gpr, &AArch64::FPR64RegClass, Op0, Op0IsKill); 579 } 580 return 0; 581} 582 583unsigned fastEmit_AArch64ISD_DUP_MVT_i32_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) { 584 if ((Subtarget->hasNEON())) { 585 return fastEmitInst_r(AArch64::DUPv16i8gpr, &AArch64::FPR128RegClass, Op0, Op0IsKill); 586 } 587 return 0; 588} 589 590unsigned fastEmit_AArch64ISD_DUP_MVT_i32_MVT_v4i16_r(unsigned Op0, bool Op0IsKill) { 591 if ((Subtarget->hasNEON())) { 592 return fastEmitInst_r(AArch64::DUPv4i16gpr, &AArch64::FPR64RegClass, Op0, Op0IsKill); 593 } 594 return 0; 595} 596 597unsigned fastEmit_AArch64ISD_DUP_MVT_i32_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) { 598 if ((Subtarget->hasNEON())) { 599 return fastEmitInst_r(AArch64::DUPv8i16gpr, &AArch64::FPR128RegClass, Op0, Op0IsKill); 600 } 601 return 0; 602} 603 604unsigned fastEmit_AArch64ISD_DUP_MVT_i32_MVT_v2i32_r(unsigned Op0, bool Op0IsKill) { 605 if ((Subtarget->hasNEON())) { 606 return fastEmitInst_r(AArch64::DUPv2i32gpr, &AArch64::FPR64RegClass, Op0, Op0IsKill); 607 } 608 return 0; 609} 610 611unsigned fastEmit_AArch64ISD_DUP_MVT_i32_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) { 612 if ((Subtarget->hasNEON())) { 613 return fastEmitInst_r(AArch64::DUPv4i32gpr, &AArch64::FPR128RegClass, Op0, Op0IsKill); 614 } 615 return 0; 616} 617 618unsigned fastEmit_AArch64ISD_DUP_MVT_i32_MVT_nxv16i8_r(unsigned Op0, bool Op0IsKill) { 619 if ((Subtarget->hasSVE())) { 620 return fastEmitInst_r(AArch64::DUP_ZR_B, &AArch64::ZPRRegClass, Op0, Op0IsKill); 621 } 622 return 0; 623} 624 625unsigned fastEmit_AArch64ISD_DUP_MVT_i32_MVT_nxv8i16_r(unsigned Op0, bool Op0IsKill) { 626 if ((Subtarget->hasSVE())) { 627 return fastEmitInst_r(AArch64::DUP_ZR_H, &AArch64::ZPRRegClass, Op0, Op0IsKill); 628 } 629 return 0; 630} 631 632unsigned fastEmit_AArch64ISD_DUP_MVT_i32_MVT_nxv4i32_r(unsigned Op0, bool Op0IsKill) { 633 if ((Subtarget->hasSVE())) { 634 return fastEmitInst_r(AArch64::DUP_ZR_S, &AArch64::ZPRRegClass, Op0, Op0IsKill); 635 } 636 return 0; 637} 638 639unsigned fastEmit_AArch64ISD_DUP_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 640switch (RetVT.SimpleTy) { 641 case MVT::v8i8: return fastEmit_AArch64ISD_DUP_MVT_i32_MVT_v8i8_r(Op0, Op0IsKill); 642 case MVT::v16i8: return fastEmit_AArch64ISD_DUP_MVT_i32_MVT_v16i8_r(Op0, Op0IsKill); 643 case MVT::v4i16: return fastEmit_AArch64ISD_DUP_MVT_i32_MVT_v4i16_r(Op0, Op0IsKill); 644 case MVT::v8i16: return fastEmit_AArch64ISD_DUP_MVT_i32_MVT_v8i16_r(Op0, Op0IsKill); 645 case MVT::v2i32: return fastEmit_AArch64ISD_DUP_MVT_i32_MVT_v2i32_r(Op0, Op0IsKill); 646 case MVT::v4i32: return fastEmit_AArch64ISD_DUP_MVT_i32_MVT_v4i32_r(Op0, Op0IsKill); 647 case MVT::nxv16i8: return fastEmit_AArch64ISD_DUP_MVT_i32_MVT_nxv16i8_r(Op0, Op0IsKill); 648 case MVT::nxv8i16: return fastEmit_AArch64ISD_DUP_MVT_i32_MVT_nxv8i16_r(Op0, Op0IsKill); 649 case MVT::nxv4i32: return fastEmit_AArch64ISD_DUP_MVT_i32_MVT_nxv4i32_r(Op0, Op0IsKill); 650 default: return 0; 651} 652} 653 654unsigned fastEmit_AArch64ISD_DUP_MVT_i64_MVT_v2i64_r(unsigned Op0, bool Op0IsKill) { 655 if ((Subtarget->hasNEON())) { 656 return fastEmitInst_r(AArch64::DUPv2i64gpr, &AArch64::FPR128RegClass, Op0, Op0IsKill); 657 } 658 return 0; 659} 660 661unsigned fastEmit_AArch64ISD_DUP_MVT_i64_MVT_nxv2i64_r(unsigned Op0, bool Op0IsKill) { 662 if ((Subtarget->hasSVE())) { 663 return fastEmitInst_r(AArch64::DUP_ZR_D, &AArch64::ZPRRegClass, Op0, Op0IsKill); 664 } 665 return 0; 666} 667 668unsigned fastEmit_AArch64ISD_DUP_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 669switch (RetVT.SimpleTy) { 670 case MVT::v2i64: return fastEmit_AArch64ISD_DUP_MVT_i64_MVT_v2i64_r(Op0, Op0IsKill); 671 case MVT::nxv2i64: return fastEmit_AArch64ISD_DUP_MVT_i64_MVT_nxv2i64_r(Op0, Op0IsKill); 672 default: return 0; 673} 674} 675 676unsigned fastEmit_AArch64ISD_DUP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 677 switch (VT.SimpleTy) { 678 case MVT::i32: return fastEmit_AArch64ISD_DUP_MVT_i32_r(RetVT, Op0, Op0IsKill); 679 case MVT::i64: return fastEmit_AArch64ISD_DUP_MVT_i64_r(RetVT, Op0, Op0IsKill); 680 default: return 0; 681 } 682} 683 684// FastEmit functions for AArch64ISD::FCMEQz. 685 686unsigned fastEmit_AArch64ISD_FCMEQz_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 687 if (RetVT.SimpleTy != MVT::v4i16) 688 return 0; 689 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 690 return fastEmitInst_r(AArch64::FCMEQv4i16rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 691 } 692 return 0; 693} 694 695unsigned fastEmit_AArch64ISD_FCMEQz_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 696 if (RetVT.SimpleTy != MVT::v8i16) 697 return 0; 698 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 699 return fastEmitInst_r(AArch64::FCMEQv8i16rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 700 } 701 return 0; 702} 703 704unsigned fastEmit_AArch64ISD_FCMEQz_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 705 if (RetVT.SimpleTy != MVT::v2i32) 706 return 0; 707 if ((Subtarget->hasNEON())) { 708 return fastEmitInst_r(AArch64::FCMEQv2i32rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 709 } 710 return 0; 711} 712 713unsigned fastEmit_AArch64ISD_FCMEQz_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 714 if (RetVT.SimpleTy != MVT::v4i32) 715 return 0; 716 if ((Subtarget->hasNEON())) { 717 return fastEmitInst_r(AArch64::FCMEQv4i32rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 718 } 719 return 0; 720} 721 722unsigned fastEmit_AArch64ISD_FCMEQz_MVT_v1f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 723 if (RetVT.SimpleTy != MVT::v1i64) 724 return 0; 725 if ((Subtarget->hasNEON())) { 726 return fastEmitInst_r(AArch64::FCMEQv1i64rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 727 } 728 return 0; 729} 730 731unsigned fastEmit_AArch64ISD_FCMEQz_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 732 if (RetVT.SimpleTy != MVT::v2i64) 733 return 0; 734 if ((Subtarget->hasNEON())) { 735 return fastEmitInst_r(AArch64::FCMEQv2i64rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 736 } 737 return 0; 738} 739 740unsigned fastEmit_AArch64ISD_FCMEQz_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 741 switch (VT.SimpleTy) { 742 case MVT::v4f16: return fastEmit_AArch64ISD_FCMEQz_MVT_v4f16_r(RetVT, Op0, Op0IsKill); 743 case MVT::v8f16: return fastEmit_AArch64ISD_FCMEQz_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 744 case MVT::v2f32: return fastEmit_AArch64ISD_FCMEQz_MVT_v2f32_r(RetVT, Op0, Op0IsKill); 745 case MVT::v4f32: return fastEmit_AArch64ISD_FCMEQz_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 746 case MVT::v1f64: return fastEmit_AArch64ISD_FCMEQz_MVT_v1f64_r(RetVT, Op0, Op0IsKill); 747 case MVT::v2f64: return fastEmit_AArch64ISD_FCMEQz_MVT_v2f64_r(RetVT, Op0, Op0IsKill); 748 default: return 0; 749 } 750} 751 752// FastEmit functions for AArch64ISD::FCMGEz. 753 754unsigned fastEmit_AArch64ISD_FCMGEz_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 755 if (RetVT.SimpleTy != MVT::v4i16) 756 return 0; 757 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 758 return fastEmitInst_r(AArch64::FCMGEv4i16rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 759 } 760 return 0; 761} 762 763unsigned fastEmit_AArch64ISD_FCMGEz_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 764 if (RetVT.SimpleTy != MVT::v8i16) 765 return 0; 766 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 767 return fastEmitInst_r(AArch64::FCMGEv8i16rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 768 } 769 return 0; 770} 771 772unsigned fastEmit_AArch64ISD_FCMGEz_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 773 if (RetVT.SimpleTy != MVT::v2i32) 774 return 0; 775 if ((Subtarget->hasNEON())) { 776 return fastEmitInst_r(AArch64::FCMGEv2i32rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 777 } 778 return 0; 779} 780 781unsigned fastEmit_AArch64ISD_FCMGEz_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 782 if (RetVT.SimpleTy != MVT::v4i32) 783 return 0; 784 if ((Subtarget->hasNEON())) { 785 return fastEmitInst_r(AArch64::FCMGEv4i32rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 786 } 787 return 0; 788} 789 790unsigned fastEmit_AArch64ISD_FCMGEz_MVT_v1f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 791 if (RetVT.SimpleTy != MVT::v1i64) 792 return 0; 793 if ((Subtarget->hasNEON())) { 794 return fastEmitInst_r(AArch64::FCMGEv1i64rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 795 } 796 return 0; 797} 798 799unsigned fastEmit_AArch64ISD_FCMGEz_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 800 if (RetVT.SimpleTy != MVT::v2i64) 801 return 0; 802 if ((Subtarget->hasNEON())) { 803 return fastEmitInst_r(AArch64::FCMGEv2i64rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 804 } 805 return 0; 806} 807 808unsigned fastEmit_AArch64ISD_FCMGEz_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 809 switch (VT.SimpleTy) { 810 case MVT::v4f16: return fastEmit_AArch64ISD_FCMGEz_MVT_v4f16_r(RetVT, Op0, Op0IsKill); 811 case MVT::v8f16: return fastEmit_AArch64ISD_FCMGEz_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 812 case MVT::v2f32: return fastEmit_AArch64ISD_FCMGEz_MVT_v2f32_r(RetVT, Op0, Op0IsKill); 813 case MVT::v4f32: return fastEmit_AArch64ISD_FCMGEz_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 814 case MVT::v1f64: return fastEmit_AArch64ISD_FCMGEz_MVT_v1f64_r(RetVT, Op0, Op0IsKill); 815 case MVT::v2f64: return fastEmit_AArch64ISD_FCMGEz_MVT_v2f64_r(RetVT, Op0, Op0IsKill); 816 default: return 0; 817 } 818} 819 820// FastEmit functions for AArch64ISD::FCMGTz. 821 822unsigned fastEmit_AArch64ISD_FCMGTz_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 823 if (RetVT.SimpleTy != MVT::v4i16) 824 return 0; 825 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 826 return fastEmitInst_r(AArch64::FCMGTv4i16rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 827 } 828 return 0; 829} 830 831unsigned fastEmit_AArch64ISD_FCMGTz_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 832 if (RetVT.SimpleTy != MVT::v8i16) 833 return 0; 834 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 835 return fastEmitInst_r(AArch64::FCMGTv8i16rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 836 } 837 return 0; 838} 839 840unsigned fastEmit_AArch64ISD_FCMGTz_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 841 if (RetVT.SimpleTy != MVT::v2i32) 842 return 0; 843 if ((Subtarget->hasNEON())) { 844 return fastEmitInst_r(AArch64::FCMGTv2i32rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 845 } 846 return 0; 847} 848 849unsigned fastEmit_AArch64ISD_FCMGTz_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 850 if (RetVT.SimpleTy != MVT::v4i32) 851 return 0; 852 if ((Subtarget->hasNEON())) { 853 return fastEmitInst_r(AArch64::FCMGTv4i32rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 854 } 855 return 0; 856} 857 858unsigned fastEmit_AArch64ISD_FCMGTz_MVT_v1f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 859 if (RetVT.SimpleTy != MVT::v1i64) 860 return 0; 861 if ((Subtarget->hasNEON())) { 862 return fastEmitInst_r(AArch64::FCMGTv1i64rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 863 } 864 return 0; 865} 866 867unsigned fastEmit_AArch64ISD_FCMGTz_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 868 if (RetVT.SimpleTy != MVT::v2i64) 869 return 0; 870 if ((Subtarget->hasNEON())) { 871 return fastEmitInst_r(AArch64::FCMGTv2i64rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 872 } 873 return 0; 874} 875 876unsigned fastEmit_AArch64ISD_FCMGTz_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 877 switch (VT.SimpleTy) { 878 case MVT::v4f16: return fastEmit_AArch64ISD_FCMGTz_MVT_v4f16_r(RetVT, Op0, Op0IsKill); 879 case MVT::v8f16: return fastEmit_AArch64ISD_FCMGTz_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 880 case MVT::v2f32: return fastEmit_AArch64ISD_FCMGTz_MVT_v2f32_r(RetVT, Op0, Op0IsKill); 881 case MVT::v4f32: return fastEmit_AArch64ISD_FCMGTz_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 882 case MVT::v1f64: return fastEmit_AArch64ISD_FCMGTz_MVT_v1f64_r(RetVT, Op0, Op0IsKill); 883 case MVT::v2f64: return fastEmit_AArch64ISD_FCMGTz_MVT_v2f64_r(RetVT, Op0, Op0IsKill); 884 default: return 0; 885 } 886} 887 888// FastEmit functions for AArch64ISD::FCMLEz. 889 890unsigned fastEmit_AArch64ISD_FCMLEz_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 891 if (RetVT.SimpleTy != MVT::v4i16) 892 return 0; 893 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 894 return fastEmitInst_r(AArch64::FCMLEv4i16rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 895 } 896 return 0; 897} 898 899unsigned fastEmit_AArch64ISD_FCMLEz_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 900 if (RetVT.SimpleTy != MVT::v8i16) 901 return 0; 902 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 903 return fastEmitInst_r(AArch64::FCMLEv8i16rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 904 } 905 return 0; 906} 907 908unsigned fastEmit_AArch64ISD_FCMLEz_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 909 if (RetVT.SimpleTy != MVT::v2i32) 910 return 0; 911 if ((Subtarget->hasNEON())) { 912 return fastEmitInst_r(AArch64::FCMLEv2i32rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 913 } 914 return 0; 915} 916 917unsigned fastEmit_AArch64ISD_FCMLEz_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 918 if (RetVT.SimpleTy != MVT::v4i32) 919 return 0; 920 if ((Subtarget->hasNEON())) { 921 return fastEmitInst_r(AArch64::FCMLEv4i32rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 922 } 923 return 0; 924} 925 926unsigned fastEmit_AArch64ISD_FCMLEz_MVT_v1f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 927 if (RetVT.SimpleTy != MVT::v1i64) 928 return 0; 929 if ((Subtarget->hasNEON())) { 930 return fastEmitInst_r(AArch64::FCMLEv1i64rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 931 } 932 return 0; 933} 934 935unsigned fastEmit_AArch64ISD_FCMLEz_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 936 if (RetVT.SimpleTy != MVT::v2i64) 937 return 0; 938 if ((Subtarget->hasNEON())) { 939 return fastEmitInst_r(AArch64::FCMLEv2i64rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 940 } 941 return 0; 942} 943 944unsigned fastEmit_AArch64ISD_FCMLEz_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 945 switch (VT.SimpleTy) { 946 case MVT::v4f16: return fastEmit_AArch64ISD_FCMLEz_MVT_v4f16_r(RetVT, Op0, Op0IsKill); 947 case MVT::v8f16: return fastEmit_AArch64ISD_FCMLEz_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 948 case MVT::v2f32: return fastEmit_AArch64ISD_FCMLEz_MVT_v2f32_r(RetVT, Op0, Op0IsKill); 949 case MVT::v4f32: return fastEmit_AArch64ISD_FCMLEz_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 950 case MVT::v1f64: return fastEmit_AArch64ISD_FCMLEz_MVT_v1f64_r(RetVT, Op0, Op0IsKill); 951 case MVT::v2f64: return fastEmit_AArch64ISD_FCMLEz_MVT_v2f64_r(RetVT, Op0, Op0IsKill); 952 default: return 0; 953 } 954} 955 956// FastEmit functions for AArch64ISD::FCMLTz. 957 958unsigned fastEmit_AArch64ISD_FCMLTz_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 959 if (RetVT.SimpleTy != MVT::v4i16) 960 return 0; 961 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 962 return fastEmitInst_r(AArch64::FCMLTv4i16rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 963 } 964 return 0; 965} 966 967unsigned fastEmit_AArch64ISD_FCMLTz_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 968 if (RetVT.SimpleTy != MVT::v8i16) 969 return 0; 970 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 971 return fastEmitInst_r(AArch64::FCMLTv8i16rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 972 } 973 return 0; 974} 975 976unsigned fastEmit_AArch64ISD_FCMLTz_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 977 if (RetVT.SimpleTy != MVT::v2i32) 978 return 0; 979 if ((Subtarget->hasNEON())) { 980 return fastEmitInst_r(AArch64::FCMLTv2i32rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 981 } 982 return 0; 983} 984 985unsigned fastEmit_AArch64ISD_FCMLTz_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 986 if (RetVT.SimpleTy != MVT::v4i32) 987 return 0; 988 if ((Subtarget->hasNEON())) { 989 return fastEmitInst_r(AArch64::FCMLTv4i32rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 990 } 991 return 0; 992} 993 994unsigned fastEmit_AArch64ISD_FCMLTz_MVT_v1f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 995 if (RetVT.SimpleTy != MVT::v1i64) 996 return 0; 997 if ((Subtarget->hasNEON())) { 998 return fastEmitInst_r(AArch64::FCMLTv1i64rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 999 } 1000 return 0; 1001} 1002 1003unsigned fastEmit_AArch64ISD_FCMLTz_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1004 if (RetVT.SimpleTy != MVT::v2i64) 1005 return 0; 1006 if ((Subtarget->hasNEON())) { 1007 return fastEmitInst_r(AArch64::FCMLTv2i64rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1008 } 1009 return 0; 1010} 1011 1012unsigned fastEmit_AArch64ISD_FCMLTz_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 1013 switch (VT.SimpleTy) { 1014 case MVT::v4f16: return fastEmit_AArch64ISD_FCMLTz_MVT_v4f16_r(RetVT, Op0, Op0IsKill); 1015 case MVT::v8f16: return fastEmit_AArch64ISD_FCMLTz_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 1016 case MVT::v2f32: return fastEmit_AArch64ISD_FCMLTz_MVT_v2f32_r(RetVT, Op0, Op0IsKill); 1017 case MVT::v4f32: return fastEmit_AArch64ISD_FCMLTz_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 1018 case MVT::v1f64: return fastEmit_AArch64ISD_FCMLTz_MVT_v1f64_r(RetVT, Op0, Op0IsKill); 1019 case MVT::v2f64: return fastEmit_AArch64ISD_FCMLTz_MVT_v2f64_r(RetVT, Op0, Op0IsKill); 1020 default: return 0; 1021 } 1022} 1023 1024// FastEmit functions for AArch64ISD::FRECPE. 1025 1026unsigned fastEmit_AArch64ISD_FRECPE_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1027 if (RetVT.SimpleTy != MVT::f32) 1028 return 0; 1029 return fastEmitInst_r(AArch64::FRECPEv1i32, &AArch64::FPR32RegClass, Op0, Op0IsKill); 1030} 1031 1032unsigned fastEmit_AArch64ISD_FRECPE_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1033 if (RetVT.SimpleTy != MVT::f64) 1034 return 0; 1035 return fastEmitInst_r(AArch64::FRECPEv1i64, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1036} 1037 1038unsigned fastEmit_AArch64ISD_FRECPE_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1039 if (RetVT.SimpleTy != MVT::v2f32) 1040 return 0; 1041 return fastEmitInst_r(AArch64::FRECPEv2f32, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1042} 1043 1044unsigned fastEmit_AArch64ISD_FRECPE_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1045 if (RetVT.SimpleTy != MVT::v4f32) 1046 return 0; 1047 return fastEmitInst_r(AArch64::FRECPEv4f32, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1048} 1049 1050unsigned fastEmit_AArch64ISD_FRECPE_MVT_v1f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1051 if (RetVT.SimpleTy != MVT::v1f64) 1052 return 0; 1053 return fastEmitInst_r(AArch64::FRECPEv1i64, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1054} 1055 1056unsigned fastEmit_AArch64ISD_FRECPE_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1057 if (RetVT.SimpleTy != MVT::v2f64) 1058 return 0; 1059 return fastEmitInst_r(AArch64::FRECPEv2f64, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1060} 1061 1062unsigned fastEmit_AArch64ISD_FRECPE_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 1063 switch (VT.SimpleTy) { 1064 case MVT::f32: return fastEmit_AArch64ISD_FRECPE_MVT_f32_r(RetVT, Op0, Op0IsKill); 1065 case MVT::f64: return fastEmit_AArch64ISD_FRECPE_MVT_f64_r(RetVT, Op0, Op0IsKill); 1066 case MVT::v2f32: return fastEmit_AArch64ISD_FRECPE_MVT_v2f32_r(RetVT, Op0, Op0IsKill); 1067 case MVT::v4f32: return fastEmit_AArch64ISD_FRECPE_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 1068 case MVT::v1f64: return fastEmit_AArch64ISD_FRECPE_MVT_v1f64_r(RetVT, Op0, Op0IsKill); 1069 case MVT::v2f64: return fastEmit_AArch64ISD_FRECPE_MVT_v2f64_r(RetVT, Op0, Op0IsKill); 1070 default: return 0; 1071 } 1072} 1073 1074// FastEmit functions for AArch64ISD::FRSQRTE. 1075 1076unsigned fastEmit_AArch64ISD_FRSQRTE_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1077 if (RetVT.SimpleTy != MVT::f32) 1078 return 0; 1079 return fastEmitInst_r(AArch64::FRSQRTEv1i32, &AArch64::FPR32RegClass, Op0, Op0IsKill); 1080} 1081 1082unsigned fastEmit_AArch64ISD_FRSQRTE_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1083 if (RetVT.SimpleTy != MVT::f64) 1084 return 0; 1085 return fastEmitInst_r(AArch64::FRSQRTEv1i64, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1086} 1087 1088unsigned fastEmit_AArch64ISD_FRSQRTE_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1089 if (RetVT.SimpleTy != MVT::v2f32) 1090 return 0; 1091 return fastEmitInst_r(AArch64::FRSQRTEv2f32, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1092} 1093 1094unsigned fastEmit_AArch64ISD_FRSQRTE_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1095 if (RetVT.SimpleTy != MVT::v4f32) 1096 return 0; 1097 return fastEmitInst_r(AArch64::FRSQRTEv4f32, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1098} 1099 1100unsigned fastEmit_AArch64ISD_FRSQRTE_MVT_v1f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1101 if (RetVT.SimpleTy != MVT::v1f64) 1102 return 0; 1103 return fastEmitInst_r(AArch64::FRSQRTEv1i64, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1104} 1105 1106unsigned fastEmit_AArch64ISD_FRSQRTE_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1107 if (RetVT.SimpleTy != MVT::v2f64) 1108 return 0; 1109 return fastEmitInst_r(AArch64::FRSQRTEv2f64, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1110} 1111 1112unsigned fastEmit_AArch64ISD_FRSQRTE_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 1113 switch (VT.SimpleTy) { 1114 case MVT::f32: return fastEmit_AArch64ISD_FRSQRTE_MVT_f32_r(RetVT, Op0, Op0IsKill); 1115 case MVT::f64: return fastEmit_AArch64ISD_FRSQRTE_MVT_f64_r(RetVT, Op0, Op0IsKill); 1116 case MVT::v2f32: return fastEmit_AArch64ISD_FRSQRTE_MVT_v2f32_r(RetVT, Op0, Op0IsKill); 1117 case MVT::v4f32: return fastEmit_AArch64ISD_FRSQRTE_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 1118 case MVT::v1f64: return fastEmit_AArch64ISD_FRSQRTE_MVT_v1f64_r(RetVT, Op0, Op0IsKill); 1119 case MVT::v2f64: return fastEmit_AArch64ISD_FRSQRTE_MVT_v2f64_r(RetVT, Op0, Op0IsKill); 1120 default: return 0; 1121 } 1122} 1123 1124// FastEmit functions for AArch64ISD::NEG. 1125 1126unsigned fastEmit_AArch64ISD_NEG_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1127 if (RetVT.SimpleTy != MVT::v8i8) 1128 return 0; 1129 return fastEmitInst_r(AArch64::NEGv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1130} 1131 1132unsigned fastEmit_AArch64ISD_NEG_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1133 if (RetVT.SimpleTy != MVT::v16i8) 1134 return 0; 1135 return fastEmitInst_r(AArch64::NEGv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1136} 1137 1138unsigned fastEmit_AArch64ISD_NEG_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1139 if (RetVT.SimpleTy != MVT::v4i16) 1140 return 0; 1141 return fastEmitInst_r(AArch64::NEGv4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1142} 1143 1144unsigned fastEmit_AArch64ISD_NEG_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1145 if (RetVT.SimpleTy != MVT::v8i16) 1146 return 0; 1147 return fastEmitInst_r(AArch64::NEGv8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1148} 1149 1150unsigned fastEmit_AArch64ISD_NEG_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1151 if (RetVT.SimpleTy != MVT::v2i32) 1152 return 0; 1153 return fastEmitInst_r(AArch64::NEGv2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1154} 1155 1156unsigned fastEmit_AArch64ISD_NEG_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1157 if (RetVT.SimpleTy != MVT::v4i32) 1158 return 0; 1159 return fastEmitInst_r(AArch64::NEGv4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1160} 1161 1162unsigned fastEmit_AArch64ISD_NEG_MVT_v1i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1163 if (RetVT.SimpleTy != MVT::v1i64) 1164 return 0; 1165 return fastEmitInst_r(AArch64::NEGv1i64, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1166} 1167 1168unsigned fastEmit_AArch64ISD_NEG_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1169 if (RetVT.SimpleTy != MVT::v2i64) 1170 return 0; 1171 return fastEmitInst_r(AArch64::NEGv2i64, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1172} 1173 1174unsigned fastEmit_AArch64ISD_NEG_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 1175 switch (VT.SimpleTy) { 1176 case MVT::v8i8: return fastEmit_AArch64ISD_NEG_MVT_v8i8_r(RetVT, Op0, Op0IsKill); 1177 case MVT::v16i8: return fastEmit_AArch64ISD_NEG_MVT_v16i8_r(RetVT, Op0, Op0IsKill); 1178 case MVT::v4i16: return fastEmit_AArch64ISD_NEG_MVT_v4i16_r(RetVT, Op0, Op0IsKill); 1179 case MVT::v8i16: return fastEmit_AArch64ISD_NEG_MVT_v8i16_r(RetVT, Op0, Op0IsKill); 1180 case MVT::v2i32: return fastEmit_AArch64ISD_NEG_MVT_v2i32_r(RetVT, Op0, Op0IsKill); 1181 case MVT::v4i32: return fastEmit_AArch64ISD_NEG_MVT_v4i32_r(RetVT, Op0, Op0IsKill); 1182 case MVT::v1i64: return fastEmit_AArch64ISD_NEG_MVT_v1i64_r(RetVT, Op0, Op0IsKill); 1183 case MVT::v2i64: return fastEmit_AArch64ISD_NEG_MVT_v2i64_r(RetVT, Op0, Op0IsKill); 1184 default: return 0; 1185 } 1186} 1187 1188// FastEmit functions for AArch64ISD::NOT. 1189 1190unsigned fastEmit_AArch64ISD_NOT_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1191 if (RetVT.SimpleTy != MVT::v8i8) 1192 return 0; 1193 return fastEmitInst_r(AArch64::NOTv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1194} 1195 1196unsigned fastEmit_AArch64ISD_NOT_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1197 if (RetVT.SimpleTy != MVT::v16i8) 1198 return 0; 1199 return fastEmitInst_r(AArch64::NOTv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1200} 1201 1202unsigned fastEmit_AArch64ISD_NOT_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1203 if (RetVT.SimpleTy != MVT::v4i16) 1204 return 0; 1205 return fastEmitInst_r(AArch64::NOTv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1206} 1207 1208unsigned fastEmit_AArch64ISD_NOT_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1209 if (RetVT.SimpleTy != MVT::v8i16) 1210 return 0; 1211 return fastEmitInst_r(AArch64::NOTv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1212} 1213 1214unsigned fastEmit_AArch64ISD_NOT_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1215 if (RetVT.SimpleTy != MVT::v2i32) 1216 return 0; 1217 return fastEmitInst_r(AArch64::NOTv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1218} 1219 1220unsigned fastEmit_AArch64ISD_NOT_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1221 if (RetVT.SimpleTy != MVT::v4i32) 1222 return 0; 1223 return fastEmitInst_r(AArch64::NOTv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1224} 1225 1226unsigned fastEmit_AArch64ISD_NOT_MVT_v1i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1227 if (RetVT.SimpleTy != MVT::v1i64) 1228 return 0; 1229 return fastEmitInst_r(AArch64::NOTv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1230} 1231 1232unsigned fastEmit_AArch64ISD_NOT_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1233 if (RetVT.SimpleTy != MVT::v2i64) 1234 return 0; 1235 return fastEmitInst_r(AArch64::NOTv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1236} 1237 1238unsigned fastEmit_AArch64ISD_NOT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 1239 switch (VT.SimpleTy) { 1240 case MVT::v8i8: return fastEmit_AArch64ISD_NOT_MVT_v8i8_r(RetVT, Op0, Op0IsKill); 1241 case MVT::v16i8: return fastEmit_AArch64ISD_NOT_MVT_v16i8_r(RetVT, Op0, Op0IsKill); 1242 case MVT::v4i16: return fastEmit_AArch64ISD_NOT_MVT_v4i16_r(RetVT, Op0, Op0IsKill); 1243 case MVT::v8i16: return fastEmit_AArch64ISD_NOT_MVT_v8i16_r(RetVT, Op0, Op0IsKill); 1244 case MVT::v2i32: return fastEmit_AArch64ISD_NOT_MVT_v2i32_r(RetVT, Op0, Op0IsKill); 1245 case MVT::v4i32: return fastEmit_AArch64ISD_NOT_MVT_v4i32_r(RetVT, Op0, Op0IsKill); 1246 case MVT::v1i64: return fastEmit_AArch64ISD_NOT_MVT_v1i64_r(RetVT, Op0, Op0IsKill); 1247 case MVT::v2i64: return fastEmit_AArch64ISD_NOT_MVT_v2i64_r(RetVT, Op0, Op0IsKill); 1248 default: return 0; 1249 } 1250} 1251 1252// FastEmit functions for AArch64ISD::REV. 1253 1254unsigned fastEmit_AArch64ISD_REV_MVT_nxv2i1_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1255 if (RetVT.SimpleTy != MVT::nxv2i1) 1256 return 0; 1257 if ((Subtarget->hasSVE())) { 1258 return fastEmitInst_r(AArch64::REV_PP_D, &AArch64::PPRRegClass, Op0, Op0IsKill); 1259 } 1260 return 0; 1261} 1262 1263unsigned fastEmit_AArch64ISD_REV_MVT_nxv4i1_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1264 if (RetVT.SimpleTy != MVT::nxv4i1) 1265 return 0; 1266 if ((Subtarget->hasSVE())) { 1267 return fastEmitInst_r(AArch64::REV_PP_S, &AArch64::PPRRegClass, Op0, Op0IsKill); 1268 } 1269 return 0; 1270} 1271 1272unsigned fastEmit_AArch64ISD_REV_MVT_nxv8i1_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1273 if (RetVT.SimpleTy != MVT::nxv8i1) 1274 return 0; 1275 if ((Subtarget->hasSVE())) { 1276 return fastEmitInst_r(AArch64::REV_PP_H, &AArch64::PPRRegClass, Op0, Op0IsKill); 1277 } 1278 return 0; 1279} 1280 1281unsigned fastEmit_AArch64ISD_REV_MVT_nxv16i1_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1282 if (RetVT.SimpleTy != MVT::nxv16i1) 1283 return 0; 1284 if ((Subtarget->hasSVE())) { 1285 return fastEmitInst_r(AArch64::REV_PP_B, &AArch64::PPRRegClass, Op0, Op0IsKill); 1286 } 1287 return 0; 1288} 1289 1290unsigned fastEmit_AArch64ISD_REV_MVT_nxv16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1291 if (RetVT.SimpleTy != MVT::nxv16i8) 1292 return 0; 1293 if ((Subtarget->hasSVE())) { 1294 return fastEmitInst_r(AArch64::REV_ZZ_B, &AArch64::ZPRRegClass, Op0, Op0IsKill); 1295 } 1296 return 0; 1297} 1298 1299unsigned fastEmit_AArch64ISD_REV_MVT_nxv8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1300 if (RetVT.SimpleTy != MVT::nxv8i16) 1301 return 0; 1302 if ((Subtarget->hasSVE())) { 1303 return fastEmitInst_r(AArch64::REV_ZZ_H, &AArch64::ZPRRegClass, Op0, Op0IsKill); 1304 } 1305 return 0; 1306} 1307 1308unsigned fastEmit_AArch64ISD_REV_MVT_nxv4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1309 if (RetVT.SimpleTy != MVT::nxv4i32) 1310 return 0; 1311 if ((Subtarget->hasSVE())) { 1312 return fastEmitInst_r(AArch64::REV_ZZ_S, &AArch64::ZPRRegClass, Op0, Op0IsKill); 1313 } 1314 return 0; 1315} 1316 1317unsigned fastEmit_AArch64ISD_REV_MVT_nxv2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1318 if (RetVT.SimpleTy != MVT::nxv2i64) 1319 return 0; 1320 if ((Subtarget->hasSVE())) { 1321 return fastEmitInst_r(AArch64::REV_ZZ_D, &AArch64::ZPRRegClass, Op0, Op0IsKill); 1322 } 1323 return 0; 1324} 1325 1326unsigned fastEmit_AArch64ISD_REV_MVT_nxv8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1327 if (RetVT.SimpleTy != MVT::nxv8f16) 1328 return 0; 1329 if ((Subtarget->hasSVE())) { 1330 return fastEmitInst_r(AArch64::REV_ZZ_H, &AArch64::ZPRRegClass, Op0, Op0IsKill); 1331 } 1332 return 0; 1333} 1334 1335unsigned fastEmit_AArch64ISD_REV_MVT_nxv4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1336 if (RetVT.SimpleTy != MVT::nxv4f32) 1337 return 0; 1338 if ((Subtarget->hasSVE())) { 1339 return fastEmitInst_r(AArch64::REV_ZZ_S, &AArch64::ZPRRegClass, Op0, Op0IsKill); 1340 } 1341 return 0; 1342} 1343 1344unsigned fastEmit_AArch64ISD_REV_MVT_nxv2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1345 if (RetVT.SimpleTy != MVT::nxv2f64) 1346 return 0; 1347 if ((Subtarget->hasSVE())) { 1348 return fastEmitInst_r(AArch64::REV_ZZ_D, &AArch64::ZPRRegClass, Op0, Op0IsKill); 1349 } 1350 return 0; 1351} 1352 1353unsigned fastEmit_AArch64ISD_REV_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 1354 switch (VT.SimpleTy) { 1355 case MVT::nxv2i1: return fastEmit_AArch64ISD_REV_MVT_nxv2i1_r(RetVT, Op0, Op0IsKill); 1356 case MVT::nxv4i1: return fastEmit_AArch64ISD_REV_MVT_nxv4i1_r(RetVT, Op0, Op0IsKill); 1357 case MVT::nxv8i1: return fastEmit_AArch64ISD_REV_MVT_nxv8i1_r(RetVT, Op0, Op0IsKill); 1358 case MVT::nxv16i1: return fastEmit_AArch64ISD_REV_MVT_nxv16i1_r(RetVT, Op0, Op0IsKill); 1359 case MVT::nxv16i8: return fastEmit_AArch64ISD_REV_MVT_nxv16i8_r(RetVT, Op0, Op0IsKill); 1360 case MVT::nxv8i16: return fastEmit_AArch64ISD_REV_MVT_nxv8i16_r(RetVT, Op0, Op0IsKill); 1361 case MVT::nxv4i32: return fastEmit_AArch64ISD_REV_MVT_nxv4i32_r(RetVT, Op0, Op0IsKill); 1362 case MVT::nxv2i64: return fastEmit_AArch64ISD_REV_MVT_nxv2i64_r(RetVT, Op0, Op0IsKill); 1363 case MVT::nxv8f16: return fastEmit_AArch64ISD_REV_MVT_nxv8f16_r(RetVT, Op0, Op0IsKill); 1364 case MVT::nxv4f32: return fastEmit_AArch64ISD_REV_MVT_nxv4f32_r(RetVT, Op0, Op0IsKill); 1365 case MVT::nxv2f64: return fastEmit_AArch64ISD_REV_MVT_nxv2f64_r(RetVT, Op0, Op0IsKill); 1366 default: return 0; 1367 } 1368} 1369 1370// FastEmit functions for AArch64ISD::REV16. 1371 1372unsigned fastEmit_AArch64ISD_REV16_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1373 if (RetVT.SimpleTy != MVT::v8i8) 1374 return 0; 1375 if ((Subtarget->hasNEON())) { 1376 return fastEmitInst_r(AArch64::REV16v8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1377 } 1378 return 0; 1379} 1380 1381unsigned fastEmit_AArch64ISD_REV16_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1382 if (RetVT.SimpleTy != MVT::v16i8) 1383 return 0; 1384 if ((Subtarget->hasNEON())) { 1385 return fastEmitInst_r(AArch64::REV16v16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1386 } 1387 return 0; 1388} 1389 1390unsigned fastEmit_AArch64ISD_REV16_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 1391 switch (VT.SimpleTy) { 1392 case MVT::v8i8: return fastEmit_AArch64ISD_REV16_MVT_v8i8_r(RetVT, Op0, Op0IsKill); 1393 case MVT::v16i8: return fastEmit_AArch64ISD_REV16_MVT_v16i8_r(RetVT, Op0, Op0IsKill); 1394 default: return 0; 1395 } 1396} 1397 1398// FastEmit functions for AArch64ISD::REV32. 1399 1400unsigned fastEmit_AArch64ISD_REV32_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1401 if (RetVT.SimpleTy != MVT::v8i8) 1402 return 0; 1403 if ((Subtarget->hasNEON())) { 1404 return fastEmitInst_r(AArch64::REV32v8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1405 } 1406 return 0; 1407} 1408 1409unsigned fastEmit_AArch64ISD_REV32_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1410 if (RetVT.SimpleTy != MVT::v16i8) 1411 return 0; 1412 if ((Subtarget->hasNEON())) { 1413 return fastEmitInst_r(AArch64::REV32v16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1414 } 1415 return 0; 1416} 1417 1418unsigned fastEmit_AArch64ISD_REV32_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1419 if (RetVT.SimpleTy != MVT::v4i16) 1420 return 0; 1421 if ((Subtarget->hasNEON())) { 1422 return fastEmitInst_r(AArch64::REV32v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1423 } 1424 return 0; 1425} 1426 1427unsigned fastEmit_AArch64ISD_REV32_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1428 if (RetVT.SimpleTy != MVT::v8i16) 1429 return 0; 1430 if ((Subtarget->hasNEON())) { 1431 return fastEmitInst_r(AArch64::REV32v8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1432 } 1433 return 0; 1434} 1435 1436unsigned fastEmit_AArch64ISD_REV32_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1437 if (RetVT.SimpleTy != MVT::v4f16) 1438 return 0; 1439 return fastEmitInst_r(AArch64::REV32v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1440} 1441 1442unsigned fastEmit_AArch64ISD_REV32_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1443 if (RetVT.SimpleTy != MVT::v8f16) 1444 return 0; 1445 return fastEmitInst_r(AArch64::REV32v8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1446} 1447 1448unsigned fastEmit_AArch64ISD_REV32_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 1449 switch (VT.SimpleTy) { 1450 case MVT::v8i8: return fastEmit_AArch64ISD_REV32_MVT_v8i8_r(RetVT, Op0, Op0IsKill); 1451 case MVT::v16i8: return fastEmit_AArch64ISD_REV32_MVT_v16i8_r(RetVT, Op0, Op0IsKill); 1452 case MVT::v4i16: return fastEmit_AArch64ISD_REV32_MVT_v4i16_r(RetVT, Op0, Op0IsKill); 1453 case MVT::v8i16: return fastEmit_AArch64ISD_REV32_MVT_v8i16_r(RetVT, Op0, Op0IsKill); 1454 case MVT::v4f16: return fastEmit_AArch64ISD_REV32_MVT_v4f16_r(RetVT, Op0, Op0IsKill); 1455 case MVT::v8f16: return fastEmit_AArch64ISD_REV32_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 1456 default: return 0; 1457 } 1458} 1459 1460// FastEmit functions for AArch64ISD::REV64. 1461 1462unsigned fastEmit_AArch64ISD_REV64_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1463 if (RetVT.SimpleTy != MVT::v8i8) 1464 return 0; 1465 if ((Subtarget->hasNEON())) { 1466 return fastEmitInst_r(AArch64::REV64v8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1467 } 1468 return 0; 1469} 1470 1471unsigned fastEmit_AArch64ISD_REV64_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1472 if (RetVT.SimpleTy != MVT::v16i8) 1473 return 0; 1474 if ((Subtarget->hasNEON())) { 1475 return fastEmitInst_r(AArch64::REV64v16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1476 } 1477 return 0; 1478} 1479 1480unsigned fastEmit_AArch64ISD_REV64_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1481 if (RetVT.SimpleTy != MVT::v4i16) 1482 return 0; 1483 if ((Subtarget->hasNEON())) { 1484 return fastEmitInst_r(AArch64::REV64v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1485 } 1486 return 0; 1487} 1488 1489unsigned fastEmit_AArch64ISD_REV64_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1490 if (RetVT.SimpleTy != MVT::v8i16) 1491 return 0; 1492 if ((Subtarget->hasNEON())) { 1493 return fastEmitInst_r(AArch64::REV64v8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1494 } 1495 return 0; 1496} 1497 1498unsigned fastEmit_AArch64ISD_REV64_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1499 if (RetVT.SimpleTy != MVT::v2i32) 1500 return 0; 1501 if ((Subtarget->hasNEON())) { 1502 return fastEmitInst_r(AArch64::REV64v2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1503 } 1504 return 0; 1505} 1506 1507unsigned fastEmit_AArch64ISD_REV64_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1508 if (RetVT.SimpleTy != MVT::v4i32) 1509 return 0; 1510 if ((Subtarget->hasNEON())) { 1511 return fastEmitInst_r(AArch64::REV64v4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1512 } 1513 return 0; 1514} 1515 1516unsigned fastEmit_AArch64ISD_REV64_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1517 if (RetVT.SimpleTy != MVT::v4f16) 1518 return 0; 1519 return fastEmitInst_r(AArch64::REV64v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1520} 1521 1522unsigned fastEmit_AArch64ISD_REV64_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1523 if (RetVT.SimpleTy != MVT::v8f16) 1524 return 0; 1525 return fastEmitInst_r(AArch64::REV64v8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1526} 1527 1528unsigned fastEmit_AArch64ISD_REV64_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1529 if (RetVT.SimpleTy != MVT::v2f32) 1530 return 0; 1531 return fastEmitInst_r(AArch64::REV64v2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1532} 1533 1534unsigned fastEmit_AArch64ISD_REV64_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1535 if (RetVT.SimpleTy != MVT::v4f32) 1536 return 0; 1537 return fastEmitInst_r(AArch64::REV64v4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1538} 1539 1540unsigned fastEmit_AArch64ISD_REV64_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 1541 switch (VT.SimpleTy) { 1542 case MVT::v8i8: return fastEmit_AArch64ISD_REV64_MVT_v8i8_r(RetVT, Op0, Op0IsKill); 1543 case MVT::v16i8: return fastEmit_AArch64ISD_REV64_MVT_v16i8_r(RetVT, Op0, Op0IsKill); 1544 case MVT::v4i16: return fastEmit_AArch64ISD_REV64_MVT_v4i16_r(RetVT, Op0, Op0IsKill); 1545 case MVT::v8i16: return fastEmit_AArch64ISD_REV64_MVT_v8i16_r(RetVT, Op0, Op0IsKill); 1546 case MVT::v2i32: return fastEmit_AArch64ISD_REV64_MVT_v2i32_r(RetVT, Op0, Op0IsKill); 1547 case MVT::v4i32: return fastEmit_AArch64ISD_REV64_MVT_v4i32_r(RetVT, Op0, Op0IsKill); 1548 case MVT::v4f16: return fastEmit_AArch64ISD_REV64_MVT_v4f16_r(RetVT, Op0, Op0IsKill); 1549 case MVT::v8f16: return fastEmit_AArch64ISD_REV64_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 1550 case MVT::v2f32: return fastEmit_AArch64ISD_REV64_MVT_v2f32_r(RetVT, Op0, Op0IsKill); 1551 case MVT::v4f32: return fastEmit_AArch64ISD_REV64_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 1552 default: return 0; 1553 } 1554} 1555 1556// FastEmit functions for AArch64ISD::SITOF. 1557 1558unsigned fastEmit_AArch64ISD_SITOF_MVT_f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1559 if (RetVT.SimpleTy != MVT::f16) 1560 return 0; 1561 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 1562 return fastEmitInst_r(AArch64::SCVTFv1i16, &AArch64::FPR16RegClass, Op0, Op0IsKill); 1563 } 1564 return 0; 1565} 1566 1567unsigned fastEmit_AArch64ISD_SITOF_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1568 if (RetVT.SimpleTy != MVT::f32) 1569 return 0; 1570 if ((Subtarget->hasNEON())) { 1571 return fastEmitInst_r(AArch64::SCVTFv1i32, &AArch64::FPR32RegClass, Op0, Op0IsKill); 1572 } 1573 return 0; 1574} 1575 1576unsigned fastEmit_AArch64ISD_SITOF_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1577 if (RetVT.SimpleTy != MVT::f64) 1578 return 0; 1579 if ((Subtarget->hasNEON())) { 1580 return fastEmitInst_r(AArch64::SCVTFv1i64, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1581 } 1582 return 0; 1583} 1584 1585unsigned fastEmit_AArch64ISD_SITOF_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 1586 switch (VT.SimpleTy) { 1587 case MVT::f16: return fastEmit_AArch64ISD_SITOF_MVT_f16_r(RetVT, Op0, Op0IsKill); 1588 case MVT::f32: return fastEmit_AArch64ISD_SITOF_MVT_f32_r(RetVT, Op0, Op0IsKill); 1589 case MVT::f64: return fastEmit_AArch64ISD_SITOF_MVT_f64_r(RetVT, Op0, Op0IsKill); 1590 default: return 0; 1591 } 1592} 1593 1594// FastEmit functions for AArch64ISD::SUNPKHI. 1595 1596unsigned fastEmit_AArch64ISD_SUNPKHI_MVT_nxv16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1597 if (RetVT.SimpleTy != MVT::nxv8i16) 1598 return 0; 1599 if ((Subtarget->hasSVE())) { 1600 return fastEmitInst_r(AArch64::SUNPKHI_ZZ_H, &AArch64::ZPRRegClass, Op0, Op0IsKill); 1601 } 1602 return 0; 1603} 1604 1605unsigned fastEmit_AArch64ISD_SUNPKHI_MVT_nxv8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1606 if (RetVT.SimpleTy != MVT::nxv4i32) 1607 return 0; 1608 if ((Subtarget->hasSVE())) { 1609 return fastEmitInst_r(AArch64::SUNPKHI_ZZ_S, &AArch64::ZPRRegClass, Op0, Op0IsKill); 1610 } 1611 return 0; 1612} 1613 1614unsigned fastEmit_AArch64ISD_SUNPKHI_MVT_nxv4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1615 if (RetVT.SimpleTy != MVT::nxv2i64) 1616 return 0; 1617 if ((Subtarget->hasSVE())) { 1618 return fastEmitInst_r(AArch64::SUNPKHI_ZZ_D, &AArch64::ZPRRegClass, Op0, Op0IsKill); 1619 } 1620 return 0; 1621} 1622 1623unsigned fastEmit_AArch64ISD_SUNPKHI_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 1624 switch (VT.SimpleTy) { 1625 case MVT::nxv16i8: return fastEmit_AArch64ISD_SUNPKHI_MVT_nxv16i8_r(RetVT, Op0, Op0IsKill); 1626 case MVT::nxv8i16: return fastEmit_AArch64ISD_SUNPKHI_MVT_nxv8i16_r(RetVT, Op0, Op0IsKill); 1627 case MVT::nxv4i32: return fastEmit_AArch64ISD_SUNPKHI_MVT_nxv4i32_r(RetVT, Op0, Op0IsKill); 1628 default: return 0; 1629 } 1630} 1631 1632// FastEmit functions for AArch64ISD::SUNPKLO. 1633 1634unsigned fastEmit_AArch64ISD_SUNPKLO_MVT_nxv16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1635 if (RetVT.SimpleTy != MVT::nxv8i16) 1636 return 0; 1637 if ((Subtarget->hasSVE())) { 1638 return fastEmitInst_r(AArch64::SUNPKLO_ZZ_H, &AArch64::ZPRRegClass, Op0, Op0IsKill); 1639 } 1640 return 0; 1641} 1642 1643unsigned fastEmit_AArch64ISD_SUNPKLO_MVT_nxv8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1644 if (RetVT.SimpleTy != MVT::nxv4i32) 1645 return 0; 1646 if ((Subtarget->hasSVE())) { 1647 return fastEmitInst_r(AArch64::SUNPKLO_ZZ_S, &AArch64::ZPRRegClass, Op0, Op0IsKill); 1648 } 1649 return 0; 1650} 1651 1652unsigned fastEmit_AArch64ISD_SUNPKLO_MVT_nxv4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1653 if (RetVT.SimpleTy != MVT::nxv2i64) 1654 return 0; 1655 if ((Subtarget->hasSVE())) { 1656 return fastEmitInst_r(AArch64::SUNPKLO_ZZ_D, &AArch64::ZPRRegClass, Op0, Op0IsKill); 1657 } 1658 return 0; 1659} 1660 1661unsigned fastEmit_AArch64ISD_SUNPKLO_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 1662 switch (VT.SimpleTy) { 1663 case MVT::nxv16i8: return fastEmit_AArch64ISD_SUNPKLO_MVT_nxv16i8_r(RetVT, Op0, Op0IsKill); 1664 case MVT::nxv8i16: return fastEmit_AArch64ISD_SUNPKLO_MVT_nxv8i16_r(RetVT, Op0, Op0IsKill); 1665 case MVT::nxv4i32: return fastEmit_AArch64ISD_SUNPKLO_MVT_nxv4i32_r(RetVT, Op0, Op0IsKill); 1666 default: return 0; 1667 } 1668} 1669 1670// FastEmit functions for AArch64ISD::UITOF. 1671 1672unsigned fastEmit_AArch64ISD_UITOF_MVT_f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1673 if (RetVT.SimpleTy != MVT::f16) 1674 return 0; 1675 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 1676 return fastEmitInst_r(AArch64::UCVTFv1i16, &AArch64::FPR16RegClass, Op0, Op0IsKill); 1677 } 1678 return 0; 1679} 1680 1681unsigned fastEmit_AArch64ISD_UITOF_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1682 if (RetVT.SimpleTy != MVT::f32) 1683 return 0; 1684 if ((Subtarget->hasNEON())) { 1685 return fastEmitInst_r(AArch64::UCVTFv1i32, &AArch64::FPR32RegClass, Op0, Op0IsKill); 1686 } 1687 return 0; 1688} 1689 1690unsigned fastEmit_AArch64ISD_UITOF_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1691 if (RetVT.SimpleTy != MVT::f64) 1692 return 0; 1693 if ((Subtarget->hasNEON())) { 1694 return fastEmitInst_r(AArch64::UCVTFv1i64, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1695 } 1696 return 0; 1697} 1698 1699unsigned fastEmit_AArch64ISD_UITOF_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 1700 switch (VT.SimpleTy) { 1701 case MVT::f16: return fastEmit_AArch64ISD_UITOF_MVT_f16_r(RetVT, Op0, Op0IsKill); 1702 case MVT::f32: return fastEmit_AArch64ISD_UITOF_MVT_f32_r(RetVT, Op0, Op0IsKill); 1703 case MVT::f64: return fastEmit_AArch64ISD_UITOF_MVT_f64_r(RetVT, Op0, Op0IsKill); 1704 default: return 0; 1705 } 1706} 1707 1708// FastEmit functions for AArch64ISD::UUNPKHI. 1709 1710unsigned fastEmit_AArch64ISD_UUNPKHI_MVT_nxv16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1711 if (RetVT.SimpleTy != MVT::nxv8i16) 1712 return 0; 1713 if ((Subtarget->hasSVE())) { 1714 return fastEmitInst_r(AArch64::UUNPKHI_ZZ_H, &AArch64::ZPRRegClass, Op0, Op0IsKill); 1715 } 1716 return 0; 1717} 1718 1719unsigned fastEmit_AArch64ISD_UUNPKHI_MVT_nxv8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1720 if (RetVT.SimpleTy != MVT::nxv4i32) 1721 return 0; 1722 if ((Subtarget->hasSVE())) { 1723 return fastEmitInst_r(AArch64::UUNPKHI_ZZ_S, &AArch64::ZPRRegClass, Op0, Op0IsKill); 1724 } 1725 return 0; 1726} 1727 1728unsigned fastEmit_AArch64ISD_UUNPKHI_MVT_nxv4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1729 if (RetVT.SimpleTy != MVT::nxv2i64) 1730 return 0; 1731 if ((Subtarget->hasSVE())) { 1732 return fastEmitInst_r(AArch64::UUNPKHI_ZZ_D, &AArch64::ZPRRegClass, Op0, Op0IsKill); 1733 } 1734 return 0; 1735} 1736 1737unsigned fastEmit_AArch64ISD_UUNPKHI_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 1738 switch (VT.SimpleTy) { 1739 case MVT::nxv16i8: return fastEmit_AArch64ISD_UUNPKHI_MVT_nxv16i8_r(RetVT, Op0, Op0IsKill); 1740 case MVT::nxv8i16: return fastEmit_AArch64ISD_UUNPKHI_MVT_nxv8i16_r(RetVT, Op0, Op0IsKill); 1741 case MVT::nxv4i32: return fastEmit_AArch64ISD_UUNPKHI_MVT_nxv4i32_r(RetVT, Op0, Op0IsKill); 1742 default: return 0; 1743 } 1744} 1745 1746// FastEmit functions for AArch64ISD::UUNPKLO. 1747 1748unsigned fastEmit_AArch64ISD_UUNPKLO_MVT_nxv16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1749 if (RetVT.SimpleTy != MVT::nxv8i16) 1750 return 0; 1751 if ((Subtarget->hasSVE())) { 1752 return fastEmitInst_r(AArch64::UUNPKLO_ZZ_H, &AArch64::ZPRRegClass, Op0, Op0IsKill); 1753 } 1754 return 0; 1755} 1756 1757unsigned fastEmit_AArch64ISD_UUNPKLO_MVT_nxv8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1758 if (RetVT.SimpleTy != MVT::nxv4i32) 1759 return 0; 1760 if ((Subtarget->hasSVE())) { 1761 return fastEmitInst_r(AArch64::UUNPKLO_ZZ_S, &AArch64::ZPRRegClass, Op0, Op0IsKill); 1762 } 1763 return 0; 1764} 1765 1766unsigned fastEmit_AArch64ISD_UUNPKLO_MVT_nxv4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1767 if (RetVT.SimpleTy != MVT::nxv2i64) 1768 return 0; 1769 if ((Subtarget->hasSVE())) { 1770 return fastEmitInst_r(AArch64::UUNPKLO_ZZ_D, &AArch64::ZPRRegClass, Op0, Op0IsKill); 1771 } 1772 return 0; 1773} 1774 1775unsigned fastEmit_AArch64ISD_UUNPKLO_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 1776 switch (VT.SimpleTy) { 1777 case MVT::nxv16i8: return fastEmit_AArch64ISD_UUNPKLO_MVT_nxv16i8_r(RetVT, Op0, Op0IsKill); 1778 case MVT::nxv8i16: return fastEmit_AArch64ISD_UUNPKLO_MVT_nxv8i16_r(RetVT, Op0, Op0IsKill); 1779 case MVT::nxv4i32: return fastEmit_AArch64ISD_UUNPKLO_MVT_nxv4i32_r(RetVT, Op0, Op0IsKill); 1780 default: return 0; 1781 } 1782} 1783 1784// FastEmit functions for ISD::ABS. 1785 1786unsigned fastEmit_ISD_ABS_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1787 if (RetVT.SimpleTy != MVT::i64) 1788 return 0; 1789 if ((Subtarget->hasNEON())) { 1790 return fastEmitInst_r(AArch64::ABSv1i64, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1791 } 1792 return 0; 1793} 1794 1795unsigned fastEmit_ISD_ABS_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1796 if (RetVT.SimpleTy != MVT::v8i8) 1797 return 0; 1798 if ((Subtarget->hasNEON())) { 1799 return fastEmitInst_r(AArch64::ABSv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1800 } 1801 return 0; 1802} 1803 1804unsigned fastEmit_ISD_ABS_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1805 if (RetVT.SimpleTy != MVT::v16i8) 1806 return 0; 1807 if ((Subtarget->hasNEON())) { 1808 return fastEmitInst_r(AArch64::ABSv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1809 } 1810 return 0; 1811} 1812 1813unsigned fastEmit_ISD_ABS_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1814 if (RetVT.SimpleTy != MVT::v4i16) 1815 return 0; 1816 if ((Subtarget->hasNEON())) { 1817 return fastEmitInst_r(AArch64::ABSv4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1818 } 1819 return 0; 1820} 1821 1822unsigned fastEmit_ISD_ABS_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1823 if (RetVT.SimpleTy != MVT::v8i16) 1824 return 0; 1825 if ((Subtarget->hasNEON())) { 1826 return fastEmitInst_r(AArch64::ABSv8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1827 } 1828 return 0; 1829} 1830 1831unsigned fastEmit_ISD_ABS_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1832 if (RetVT.SimpleTy != MVT::v2i32) 1833 return 0; 1834 if ((Subtarget->hasNEON())) { 1835 return fastEmitInst_r(AArch64::ABSv2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1836 } 1837 return 0; 1838} 1839 1840unsigned fastEmit_ISD_ABS_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1841 if (RetVT.SimpleTy != MVT::v4i32) 1842 return 0; 1843 if ((Subtarget->hasNEON())) { 1844 return fastEmitInst_r(AArch64::ABSv4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1845 } 1846 return 0; 1847} 1848 1849unsigned fastEmit_ISD_ABS_MVT_v1i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1850 if (RetVT.SimpleTy != MVT::v1i64) 1851 return 0; 1852 if ((Subtarget->hasNEON())) { 1853 return fastEmitInst_r(AArch64::ABSv1i64, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1854 } 1855 return 0; 1856} 1857 1858unsigned fastEmit_ISD_ABS_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1859 if (RetVT.SimpleTy != MVT::v2i64) 1860 return 0; 1861 if ((Subtarget->hasNEON())) { 1862 return fastEmitInst_r(AArch64::ABSv2i64, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1863 } 1864 return 0; 1865} 1866 1867unsigned fastEmit_ISD_ABS_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 1868 switch (VT.SimpleTy) { 1869 case MVT::i64: return fastEmit_ISD_ABS_MVT_i64_r(RetVT, Op0, Op0IsKill); 1870 case MVT::v8i8: return fastEmit_ISD_ABS_MVT_v8i8_r(RetVT, Op0, Op0IsKill); 1871 case MVT::v16i8: return fastEmit_ISD_ABS_MVT_v16i8_r(RetVT, Op0, Op0IsKill); 1872 case MVT::v4i16: return fastEmit_ISD_ABS_MVT_v4i16_r(RetVT, Op0, Op0IsKill); 1873 case MVT::v8i16: return fastEmit_ISD_ABS_MVT_v8i16_r(RetVT, Op0, Op0IsKill); 1874 case MVT::v2i32: return fastEmit_ISD_ABS_MVT_v2i32_r(RetVT, Op0, Op0IsKill); 1875 case MVT::v4i32: return fastEmit_ISD_ABS_MVT_v4i32_r(RetVT, Op0, Op0IsKill); 1876 case MVT::v1i64: return fastEmit_ISD_ABS_MVT_v1i64_r(RetVT, Op0, Op0IsKill); 1877 case MVT::v2i64: return fastEmit_ISD_ABS_MVT_v2i64_r(RetVT, Op0, Op0IsKill); 1878 default: return 0; 1879 } 1880} 1881 1882// FastEmit functions for ISD::BITCAST. 1883 1884unsigned fastEmit_ISD_BITCAST_MVT_f64_MVT_v8i8_r(unsigned Op0, bool Op0IsKill) { 1885 if ((!Subtarget->isLittleEndian())) { 1886 return fastEmitInst_r(AArch64::REV64v8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1887 } 1888 return 0; 1889} 1890 1891unsigned fastEmit_ISD_BITCAST_MVT_f64_MVT_v4i16_r(unsigned Op0, bool Op0IsKill) { 1892 if ((!Subtarget->isLittleEndian())) { 1893 return fastEmitInst_r(AArch64::REV64v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1894 } 1895 return 0; 1896} 1897 1898unsigned fastEmit_ISD_BITCAST_MVT_f64_MVT_v2i32_r(unsigned Op0, bool Op0IsKill) { 1899 if ((!Subtarget->isLittleEndian())) { 1900 return fastEmitInst_r(AArch64::REV64v2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1901 } 1902 return 0; 1903} 1904 1905unsigned fastEmit_ISD_BITCAST_MVT_f64_MVT_v4f16_r(unsigned Op0, bool Op0IsKill) { 1906 if ((!Subtarget->isLittleEndian())) { 1907 return fastEmitInst_r(AArch64::REV64v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1908 } 1909 return 0; 1910} 1911 1912unsigned fastEmit_ISD_BITCAST_MVT_f64_MVT_v2f32_r(unsigned Op0, bool Op0IsKill) { 1913 if ((!Subtarget->isLittleEndian())) { 1914 return fastEmitInst_r(AArch64::REV64v2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1915 } 1916 return 0; 1917} 1918 1919unsigned fastEmit_ISD_BITCAST_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1920switch (RetVT.SimpleTy) { 1921 case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_f64_MVT_v8i8_r(Op0, Op0IsKill); 1922 case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_f64_MVT_v4i16_r(Op0, Op0IsKill); 1923 case MVT::v2i32: return fastEmit_ISD_BITCAST_MVT_f64_MVT_v2i32_r(Op0, Op0IsKill); 1924 case MVT::v4f16: return fastEmit_ISD_BITCAST_MVT_f64_MVT_v4f16_r(Op0, Op0IsKill); 1925 case MVT::v2f32: return fastEmit_ISD_BITCAST_MVT_f64_MVT_v2f32_r(Op0, Op0IsKill); 1926 default: return 0; 1927} 1928} 1929 1930unsigned fastEmit_ISD_BITCAST_MVT_v8i8_MVT_f64_r(unsigned Op0, bool Op0IsKill) { 1931 if ((!Subtarget->isLittleEndian())) { 1932 return fastEmitInst_r(AArch64::REV64v8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1933 } 1934 return 0; 1935} 1936 1937unsigned fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v4i16_r(unsigned Op0, bool Op0IsKill) { 1938 if ((!Subtarget->isLittleEndian())) { 1939 return fastEmitInst_r(AArch64::REV16v8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1940 } 1941 return 0; 1942} 1943 1944unsigned fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v2i32_r(unsigned Op0, bool Op0IsKill) { 1945 if ((!Subtarget->isLittleEndian())) { 1946 return fastEmitInst_r(AArch64::REV32v8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1947 } 1948 return 0; 1949} 1950 1951unsigned fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v1i64_r(unsigned Op0, bool Op0IsKill) { 1952 if ((!Subtarget->isLittleEndian())) { 1953 return fastEmitInst_r(AArch64::REV64v8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1954 } 1955 return 0; 1956} 1957 1958unsigned fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v4f16_r(unsigned Op0, bool Op0IsKill) { 1959 if ((!Subtarget->isLittleEndian())) { 1960 return fastEmitInst_r(AArch64::REV16v8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1961 } 1962 return 0; 1963} 1964 1965unsigned fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v2f32_r(unsigned Op0, bool Op0IsKill) { 1966 if ((!Subtarget->isLittleEndian())) { 1967 return fastEmitInst_r(AArch64::REV32v8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1968 } 1969 return 0; 1970} 1971 1972unsigned fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v1f64_r(unsigned Op0, bool Op0IsKill) { 1973 if ((!Subtarget->isLittleEndian())) { 1974 return fastEmitInst_r(AArch64::REV64v8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1975 } 1976 return 0; 1977} 1978 1979unsigned fastEmit_ISD_BITCAST_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1980switch (RetVT.SimpleTy) { 1981 case MVT::f64: return fastEmit_ISD_BITCAST_MVT_v8i8_MVT_f64_r(Op0, Op0IsKill); 1982 case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v4i16_r(Op0, Op0IsKill); 1983 case MVT::v2i32: return fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v2i32_r(Op0, Op0IsKill); 1984 case MVT::v1i64: return fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v1i64_r(Op0, Op0IsKill); 1985 case MVT::v4f16: return fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v4f16_r(Op0, Op0IsKill); 1986 case MVT::v2f32: return fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v2f32_r(Op0, Op0IsKill); 1987 case MVT::v1f64: return fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v1f64_r(Op0, Op0IsKill); 1988 default: return 0; 1989} 1990} 1991 1992unsigned fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) { 1993 if ((!Subtarget->isLittleEndian())) { 1994 return fastEmitInst_r(AArch64::REV16v16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1995 } 1996 return 0; 1997} 1998 1999unsigned fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) { 2000 if ((!Subtarget->isLittleEndian())) { 2001 return fastEmitInst_r(AArch64::REV32v16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2002 } 2003 return 0; 2004} 2005 2006unsigned fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v2i64_r(unsigned Op0, bool Op0IsKill) { 2007 if ((!Subtarget->isLittleEndian())) { 2008 return fastEmitInst_r(AArch64::REV64v16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2009 } 2010 return 0; 2011} 2012 2013unsigned fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v8f16_r(unsigned Op0, bool Op0IsKill) { 2014 if ((!Subtarget->isLittleEndian())) { 2015 return fastEmitInst_r(AArch64::REV16v16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2016 } 2017 return 0; 2018} 2019 2020unsigned fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v4f32_r(unsigned Op0, bool Op0IsKill) { 2021 if ((!Subtarget->isLittleEndian())) { 2022 return fastEmitInst_r(AArch64::REV32v16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2023 } 2024 return 0; 2025} 2026 2027unsigned fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v2f64_r(unsigned Op0, bool Op0IsKill) { 2028 if ((!Subtarget->isLittleEndian())) { 2029 return fastEmitInst_r(AArch64::REV64v16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2030 } 2031 return 0; 2032} 2033 2034unsigned fastEmit_ISD_BITCAST_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2035switch (RetVT.SimpleTy) { 2036 case MVT::v8i16: return fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v8i16_r(Op0, Op0IsKill); 2037 case MVT::v4i32: return fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v4i32_r(Op0, Op0IsKill); 2038 case MVT::v2i64: return fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v2i64_r(Op0, Op0IsKill); 2039 case MVT::v8f16: return fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v8f16_r(Op0, Op0IsKill); 2040 case MVT::v4f32: return fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v4f32_r(Op0, Op0IsKill); 2041 case MVT::v2f64: return fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v2f64_r(Op0, Op0IsKill); 2042 default: return 0; 2043} 2044} 2045 2046unsigned fastEmit_ISD_BITCAST_MVT_v4i16_MVT_f64_r(unsigned Op0, bool Op0IsKill) { 2047 if ((!Subtarget->isLittleEndian())) { 2048 return fastEmitInst_r(AArch64::REV64v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2049 } 2050 return 0; 2051} 2052 2053unsigned fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v8i8_r(unsigned Op0, bool Op0IsKill) { 2054 if ((!Subtarget->isLittleEndian())) { 2055 return fastEmitInst_r(AArch64::REV16v8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2056 } 2057 return 0; 2058} 2059 2060unsigned fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v2i32_r(unsigned Op0, bool Op0IsKill) { 2061 if ((!Subtarget->isLittleEndian())) { 2062 return fastEmitInst_r(AArch64::REV32v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2063 } 2064 return 0; 2065} 2066 2067unsigned fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v1i64_r(unsigned Op0, bool Op0IsKill) { 2068 if ((!Subtarget->isLittleEndian())) { 2069 return fastEmitInst_r(AArch64::REV64v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2070 } 2071 return 0; 2072} 2073 2074unsigned fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v2f32_r(unsigned Op0, bool Op0IsKill) { 2075 if ((!Subtarget->isLittleEndian())) { 2076 return fastEmitInst_r(AArch64::REV32v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2077 } 2078 return 0; 2079} 2080 2081unsigned fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v1f64_r(unsigned Op0, bool Op0IsKill) { 2082 if ((!Subtarget->isLittleEndian())) { 2083 return fastEmitInst_r(AArch64::REV64v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2084 } 2085 return 0; 2086} 2087 2088unsigned fastEmit_ISD_BITCAST_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2089switch (RetVT.SimpleTy) { 2090 case MVT::f64: return fastEmit_ISD_BITCAST_MVT_v4i16_MVT_f64_r(Op0, Op0IsKill); 2091 case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v8i8_r(Op0, Op0IsKill); 2092 case MVT::v2i32: return fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v2i32_r(Op0, Op0IsKill); 2093 case MVT::v1i64: return fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v1i64_r(Op0, Op0IsKill); 2094 case MVT::v2f32: return fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v2f32_r(Op0, Op0IsKill); 2095 case MVT::v1f64: return fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v1f64_r(Op0, Op0IsKill); 2096 default: return 0; 2097} 2098} 2099 2100unsigned fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) { 2101 if ((!Subtarget->isLittleEndian())) { 2102 return fastEmitInst_r(AArch64::REV16v16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2103 } 2104 return 0; 2105} 2106 2107unsigned fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) { 2108 if ((!Subtarget->isLittleEndian())) { 2109 return fastEmitInst_r(AArch64::REV32v8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2110 } 2111 return 0; 2112} 2113 2114unsigned fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v2i64_r(unsigned Op0, bool Op0IsKill) { 2115 if ((!Subtarget->isLittleEndian())) { 2116 return fastEmitInst_r(AArch64::REV64v8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2117 } 2118 return 0; 2119} 2120 2121unsigned fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v4f32_r(unsigned Op0, bool Op0IsKill) { 2122 if ((!Subtarget->isLittleEndian())) { 2123 return fastEmitInst_r(AArch64::REV32v8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2124 } 2125 return 0; 2126} 2127 2128unsigned fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v2f64_r(unsigned Op0, bool Op0IsKill) { 2129 if ((!Subtarget->isLittleEndian())) { 2130 return fastEmitInst_r(AArch64::REV64v8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2131 } 2132 return 0; 2133} 2134 2135unsigned fastEmit_ISD_BITCAST_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2136switch (RetVT.SimpleTy) { 2137 case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v16i8_r(Op0, Op0IsKill); 2138 case MVT::v4i32: return fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v4i32_r(Op0, Op0IsKill); 2139 case MVT::v2i64: return fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v2i64_r(Op0, Op0IsKill); 2140 case MVT::v4f32: return fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v4f32_r(Op0, Op0IsKill); 2141 case MVT::v2f64: return fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v2f64_r(Op0, Op0IsKill); 2142 default: return 0; 2143} 2144} 2145 2146unsigned fastEmit_ISD_BITCAST_MVT_v2i32_MVT_f64_r(unsigned Op0, bool Op0IsKill) { 2147 if ((!Subtarget->isLittleEndian())) { 2148 return fastEmitInst_r(AArch64::REV64v2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2149 } 2150 return 0; 2151} 2152 2153unsigned fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v8i8_r(unsigned Op0, bool Op0IsKill) { 2154 if ((!Subtarget->isLittleEndian())) { 2155 return fastEmitInst_r(AArch64::REV32v8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2156 } 2157 return 0; 2158} 2159 2160unsigned fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v4i16_r(unsigned Op0, bool Op0IsKill) { 2161 if ((!Subtarget->isLittleEndian())) { 2162 return fastEmitInst_r(AArch64::REV32v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2163 } 2164 return 0; 2165} 2166 2167unsigned fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v1i64_r(unsigned Op0, bool Op0IsKill) { 2168 if ((!Subtarget->isLittleEndian())) { 2169 return fastEmitInst_r(AArch64::REV64v2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2170 } 2171 return 0; 2172} 2173 2174unsigned fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v4f16_r(unsigned Op0, bool Op0IsKill) { 2175 if ((!Subtarget->isLittleEndian())) { 2176 return fastEmitInst_r(AArch64::REV32v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2177 } 2178 return 0; 2179} 2180 2181unsigned fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v1f64_r(unsigned Op0, bool Op0IsKill) { 2182 if ((!Subtarget->isLittleEndian())) { 2183 return fastEmitInst_r(AArch64::REV64v2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2184 } 2185 return 0; 2186} 2187 2188unsigned fastEmit_ISD_BITCAST_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2189switch (RetVT.SimpleTy) { 2190 case MVT::f64: return fastEmit_ISD_BITCAST_MVT_v2i32_MVT_f64_r(Op0, Op0IsKill); 2191 case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v8i8_r(Op0, Op0IsKill); 2192 case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v4i16_r(Op0, Op0IsKill); 2193 case MVT::v1i64: return fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v1i64_r(Op0, Op0IsKill); 2194 case MVT::v4f16: return fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v4f16_r(Op0, Op0IsKill); 2195 case MVT::v1f64: return fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v1f64_r(Op0, Op0IsKill); 2196 default: return 0; 2197} 2198} 2199 2200unsigned fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) { 2201 if ((!Subtarget->isLittleEndian())) { 2202 return fastEmitInst_r(AArch64::REV32v16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2203 } 2204 return 0; 2205} 2206 2207unsigned fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) { 2208 if ((!Subtarget->isLittleEndian())) { 2209 return fastEmitInst_r(AArch64::REV32v8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2210 } 2211 return 0; 2212} 2213 2214unsigned fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v2i64_r(unsigned Op0, bool Op0IsKill) { 2215 if ((!Subtarget->isLittleEndian())) { 2216 return fastEmitInst_r(AArch64::REV64v4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2217 } 2218 return 0; 2219} 2220 2221unsigned fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v8f16_r(unsigned Op0, bool Op0IsKill) { 2222 if ((!Subtarget->isLittleEndian())) { 2223 return fastEmitInst_r(AArch64::REV32v8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2224 } 2225 return 0; 2226} 2227 2228unsigned fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v2f64_r(unsigned Op0, bool Op0IsKill) { 2229 if ((!Subtarget->isLittleEndian())) { 2230 return fastEmitInst_r(AArch64::REV64v4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2231 } 2232 return 0; 2233} 2234 2235unsigned fastEmit_ISD_BITCAST_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2236switch (RetVT.SimpleTy) { 2237 case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v16i8_r(Op0, Op0IsKill); 2238 case MVT::v8i16: return fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v8i16_r(Op0, Op0IsKill); 2239 case MVT::v2i64: return fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v2i64_r(Op0, Op0IsKill); 2240 case MVT::v8f16: return fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v8f16_r(Op0, Op0IsKill); 2241 case MVT::v2f64: return fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v2f64_r(Op0, Op0IsKill); 2242 default: return 0; 2243} 2244} 2245 2246unsigned fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v8i8_r(unsigned Op0, bool Op0IsKill) { 2247 if ((!Subtarget->isLittleEndian())) { 2248 return fastEmitInst_r(AArch64::REV64v8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2249 } 2250 return 0; 2251} 2252 2253unsigned fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v4i16_r(unsigned Op0, bool Op0IsKill) { 2254 if ((!Subtarget->isLittleEndian())) { 2255 return fastEmitInst_r(AArch64::REV64v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2256 } 2257 return 0; 2258} 2259 2260unsigned fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v2i32_r(unsigned Op0, bool Op0IsKill) { 2261 if ((!Subtarget->isLittleEndian())) { 2262 return fastEmitInst_r(AArch64::REV64v2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2263 } 2264 return 0; 2265} 2266 2267unsigned fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v4f16_r(unsigned Op0, bool Op0IsKill) { 2268 if ((!Subtarget->isLittleEndian())) { 2269 return fastEmitInst_r(AArch64::REV64v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2270 } 2271 return 0; 2272} 2273 2274unsigned fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v2f32_r(unsigned Op0, bool Op0IsKill) { 2275 if ((!Subtarget->isLittleEndian())) { 2276 return fastEmitInst_r(AArch64::REV64v2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2277 } 2278 return 0; 2279} 2280 2281unsigned fastEmit_ISD_BITCAST_MVT_v1i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2282switch (RetVT.SimpleTy) { 2283 case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v8i8_r(Op0, Op0IsKill); 2284 case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v4i16_r(Op0, Op0IsKill); 2285 case MVT::v2i32: return fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v2i32_r(Op0, Op0IsKill); 2286 case MVT::v4f16: return fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v4f16_r(Op0, Op0IsKill); 2287 case MVT::v2f32: return fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v2f32_r(Op0, Op0IsKill); 2288 default: return 0; 2289} 2290} 2291 2292unsigned fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) { 2293 if ((!Subtarget->isLittleEndian())) { 2294 return fastEmitInst_r(AArch64::REV64v16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2295 } 2296 return 0; 2297} 2298 2299unsigned fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) { 2300 if ((!Subtarget->isLittleEndian())) { 2301 return fastEmitInst_r(AArch64::REV64v8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2302 } 2303 return 0; 2304} 2305 2306unsigned fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) { 2307 if ((!Subtarget->isLittleEndian())) { 2308 return fastEmitInst_r(AArch64::REV64v4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2309 } 2310 return 0; 2311} 2312 2313unsigned fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v8f16_r(unsigned Op0, bool Op0IsKill) { 2314 if ((!Subtarget->isLittleEndian())) { 2315 return fastEmitInst_r(AArch64::REV64v8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2316 } 2317 return 0; 2318} 2319 2320unsigned fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v4f32_r(unsigned Op0, bool Op0IsKill) { 2321 if ((!Subtarget->isLittleEndian())) { 2322 return fastEmitInst_r(AArch64::REV64v4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2323 } 2324 return 0; 2325} 2326 2327unsigned fastEmit_ISD_BITCAST_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2328switch (RetVT.SimpleTy) { 2329 case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v16i8_r(Op0, Op0IsKill); 2330 case MVT::v8i16: return fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v8i16_r(Op0, Op0IsKill); 2331 case MVT::v4i32: return fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v4i32_r(Op0, Op0IsKill); 2332 case MVT::v8f16: return fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v8f16_r(Op0, Op0IsKill); 2333 case MVT::v4f32: return fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v4f32_r(Op0, Op0IsKill); 2334 default: return 0; 2335} 2336} 2337 2338unsigned fastEmit_ISD_BITCAST_MVT_v4f16_MVT_f64_r(unsigned Op0, bool Op0IsKill) { 2339 if ((!Subtarget->isLittleEndian())) { 2340 return fastEmitInst_r(AArch64::REV64v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2341 } 2342 return 0; 2343} 2344 2345unsigned fastEmit_ISD_BITCAST_MVT_v4f16_MVT_v8i8_r(unsigned Op0, bool Op0IsKill) { 2346 if ((!Subtarget->isLittleEndian())) { 2347 return fastEmitInst_r(AArch64::REV16v8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2348 } 2349 return 0; 2350} 2351 2352unsigned fastEmit_ISD_BITCAST_MVT_v4f16_MVT_v2i32_r(unsigned Op0, bool Op0IsKill) { 2353 if ((!Subtarget->isLittleEndian())) { 2354 return fastEmitInst_r(AArch64::REV32v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2355 } 2356 return 0; 2357} 2358 2359unsigned fastEmit_ISD_BITCAST_MVT_v4f16_MVT_v1i64_r(unsigned Op0, bool Op0IsKill) { 2360 if ((!Subtarget->isLittleEndian())) { 2361 return fastEmitInst_r(AArch64::REV64v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2362 } 2363 return 0; 2364} 2365 2366unsigned fastEmit_ISD_BITCAST_MVT_v4f16_MVT_v2f32_r(unsigned Op0, bool Op0IsKill) { 2367 if ((!Subtarget->isLittleEndian())) { 2368 return fastEmitInst_r(AArch64::REV32v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2369 } 2370 return 0; 2371} 2372 2373unsigned fastEmit_ISD_BITCAST_MVT_v4f16_MVT_v1f64_r(unsigned Op0, bool Op0IsKill) { 2374 if ((!Subtarget->isLittleEndian())) { 2375 return fastEmitInst_r(AArch64::REV64v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2376 } 2377 return 0; 2378} 2379 2380unsigned fastEmit_ISD_BITCAST_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2381switch (RetVT.SimpleTy) { 2382 case MVT::f64: return fastEmit_ISD_BITCAST_MVT_v4f16_MVT_f64_r(Op0, Op0IsKill); 2383 case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_v4f16_MVT_v8i8_r(Op0, Op0IsKill); 2384 case MVT::v2i32: return fastEmit_ISD_BITCAST_MVT_v4f16_MVT_v2i32_r(Op0, Op0IsKill); 2385 case MVT::v1i64: return fastEmit_ISD_BITCAST_MVT_v4f16_MVT_v1i64_r(Op0, Op0IsKill); 2386 case MVT::v2f32: return fastEmit_ISD_BITCAST_MVT_v4f16_MVT_v2f32_r(Op0, Op0IsKill); 2387 case MVT::v1f64: return fastEmit_ISD_BITCAST_MVT_v4f16_MVT_v1f64_r(Op0, Op0IsKill); 2388 default: return 0; 2389} 2390} 2391 2392unsigned fastEmit_ISD_BITCAST_MVT_v8f16_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) { 2393 if ((!Subtarget->isLittleEndian())) { 2394 return fastEmitInst_r(AArch64::REV16v16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2395 } 2396 return 0; 2397} 2398 2399unsigned fastEmit_ISD_BITCAST_MVT_v8f16_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) { 2400 if ((!Subtarget->isLittleEndian())) { 2401 return fastEmitInst_r(AArch64::REV32v8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2402 } 2403 return 0; 2404} 2405 2406unsigned fastEmit_ISD_BITCAST_MVT_v8f16_MVT_v2i64_r(unsigned Op0, bool Op0IsKill) { 2407 if ((!Subtarget->isLittleEndian())) { 2408 return fastEmitInst_r(AArch64::REV64v8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2409 } 2410 return 0; 2411} 2412 2413unsigned fastEmit_ISD_BITCAST_MVT_v8f16_MVT_v4f32_r(unsigned Op0, bool Op0IsKill) { 2414 if ((!Subtarget->isLittleEndian())) { 2415 return fastEmitInst_r(AArch64::REV32v8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2416 } 2417 return 0; 2418} 2419 2420unsigned fastEmit_ISD_BITCAST_MVT_v8f16_MVT_v2f64_r(unsigned Op0, bool Op0IsKill) { 2421 if ((!Subtarget->isLittleEndian())) { 2422 return fastEmitInst_r(AArch64::REV64v8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2423 } 2424 return 0; 2425} 2426 2427unsigned fastEmit_ISD_BITCAST_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2428switch (RetVT.SimpleTy) { 2429 case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v8f16_MVT_v16i8_r(Op0, Op0IsKill); 2430 case MVT::v4i32: return fastEmit_ISD_BITCAST_MVT_v8f16_MVT_v4i32_r(Op0, Op0IsKill); 2431 case MVT::v2i64: return fastEmit_ISD_BITCAST_MVT_v8f16_MVT_v2i64_r(Op0, Op0IsKill); 2432 case MVT::v4f32: return fastEmit_ISD_BITCAST_MVT_v8f16_MVT_v4f32_r(Op0, Op0IsKill); 2433 case MVT::v2f64: return fastEmit_ISD_BITCAST_MVT_v8f16_MVT_v2f64_r(Op0, Op0IsKill); 2434 default: return 0; 2435} 2436} 2437 2438unsigned fastEmit_ISD_BITCAST_MVT_v2f32_MVT_f64_r(unsigned Op0, bool Op0IsKill) { 2439 if ((!Subtarget->isLittleEndian())) { 2440 return fastEmitInst_r(AArch64::REV64v2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2441 } 2442 return 0; 2443} 2444 2445unsigned fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v8i8_r(unsigned Op0, bool Op0IsKill) { 2446 if ((!Subtarget->isLittleEndian())) { 2447 return fastEmitInst_r(AArch64::REV32v8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2448 } 2449 return 0; 2450} 2451 2452unsigned fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v4i16_r(unsigned Op0, bool Op0IsKill) { 2453 if ((!Subtarget->isLittleEndian())) { 2454 return fastEmitInst_r(AArch64::REV32v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2455 } 2456 return 0; 2457} 2458 2459unsigned fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v1i64_r(unsigned Op0, bool Op0IsKill) { 2460 if ((!Subtarget->isLittleEndian())) { 2461 return fastEmitInst_r(AArch64::REV64v2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2462 } 2463 return 0; 2464} 2465 2466unsigned fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v4f16_r(unsigned Op0, bool Op0IsKill) { 2467 if ((!Subtarget->isLittleEndian())) { 2468 return fastEmitInst_r(AArch64::REV32v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2469 } 2470 return 0; 2471} 2472 2473unsigned fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v1f64_r(unsigned Op0, bool Op0IsKill) { 2474 if ((!Subtarget->isLittleEndian())) { 2475 return fastEmitInst_r(AArch64::REV64v2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2476 } 2477 return 0; 2478} 2479 2480unsigned fastEmit_ISD_BITCAST_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2481switch (RetVT.SimpleTy) { 2482 case MVT::f64: return fastEmit_ISD_BITCAST_MVT_v2f32_MVT_f64_r(Op0, Op0IsKill); 2483 case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v8i8_r(Op0, Op0IsKill); 2484 case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v4i16_r(Op0, Op0IsKill); 2485 case MVT::v1i64: return fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v1i64_r(Op0, Op0IsKill); 2486 case MVT::v4f16: return fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v4f16_r(Op0, Op0IsKill); 2487 case MVT::v1f64: return fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v1f64_r(Op0, Op0IsKill); 2488 default: return 0; 2489} 2490} 2491 2492unsigned fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) { 2493 if ((!Subtarget->isLittleEndian())) { 2494 return fastEmitInst_r(AArch64::REV32v16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2495 } 2496 return 0; 2497} 2498 2499unsigned fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) { 2500 if ((!Subtarget->isLittleEndian())) { 2501 return fastEmitInst_r(AArch64::REV32v8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2502 } 2503 return 0; 2504} 2505 2506unsigned fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v2i64_r(unsigned Op0, bool Op0IsKill) { 2507 if ((!Subtarget->isLittleEndian())) { 2508 return fastEmitInst_r(AArch64::REV64v4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2509 } 2510 return 0; 2511} 2512 2513unsigned fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v8f16_r(unsigned Op0, bool Op0IsKill) { 2514 if ((!Subtarget->isLittleEndian())) { 2515 return fastEmitInst_r(AArch64::REV32v8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2516 } 2517 return 0; 2518} 2519 2520unsigned fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v2f64_r(unsigned Op0, bool Op0IsKill) { 2521 if ((!Subtarget->isLittleEndian())) { 2522 return fastEmitInst_r(AArch64::REV64v4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2523 } 2524 return 0; 2525} 2526 2527unsigned fastEmit_ISD_BITCAST_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2528switch (RetVT.SimpleTy) { 2529 case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v16i8_r(Op0, Op0IsKill); 2530 case MVT::v8i16: return fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v8i16_r(Op0, Op0IsKill); 2531 case MVT::v2i64: return fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v2i64_r(Op0, Op0IsKill); 2532 case MVT::v8f16: return fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v8f16_r(Op0, Op0IsKill); 2533 case MVT::v2f64: return fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v2f64_r(Op0, Op0IsKill); 2534 default: return 0; 2535} 2536} 2537 2538unsigned fastEmit_ISD_BITCAST_MVT_v1f64_MVT_v8i8_r(unsigned Op0, bool Op0IsKill) { 2539 if ((!Subtarget->isLittleEndian())) { 2540 return fastEmitInst_r(AArch64::REV64v8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2541 } 2542 return 0; 2543} 2544 2545unsigned fastEmit_ISD_BITCAST_MVT_v1f64_MVT_v4i16_r(unsigned Op0, bool Op0IsKill) { 2546 if ((!Subtarget->isLittleEndian())) { 2547 return fastEmitInst_r(AArch64::REV64v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2548 } 2549 return 0; 2550} 2551 2552unsigned fastEmit_ISD_BITCAST_MVT_v1f64_MVT_v2i32_r(unsigned Op0, bool Op0IsKill) { 2553 if ((!Subtarget->isLittleEndian())) { 2554 return fastEmitInst_r(AArch64::REV64v2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2555 } 2556 return 0; 2557} 2558 2559unsigned fastEmit_ISD_BITCAST_MVT_v1f64_MVT_v4f16_r(unsigned Op0, bool Op0IsKill) { 2560 if ((!Subtarget->isLittleEndian())) { 2561 return fastEmitInst_r(AArch64::REV64v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2562 } 2563 return 0; 2564} 2565 2566unsigned fastEmit_ISD_BITCAST_MVT_v1f64_MVT_v2f32_r(unsigned Op0, bool Op0IsKill) { 2567 if ((!Subtarget->isLittleEndian())) { 2568 return fastEmitInst_r(AArch64::REV64v2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2569 } 2570 return 0; 2571} 2572 2573unsigned fastEmit_ISD_BITCAST_MVT_v1f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2574switch (RetVT.SimpleTy) { 2575 case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_v1f64_MVT_v8i8_r(Op0, Op0IsKill); 2576 case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_v1f64_MVT_v4i16_r(Op0, Op0IsKill); 2577 case MVT::v2i32: return fastEmit_ISD_BITCAST_MVT_v1f64_MVT_v2i32_r(Op0, Op0IsKill); 2578 case MVT::v4f16: return fastEmit_ISD_BITCAST_MVT_v1f64_MVT_v4f16_r(Op0, Op0IsKill); 2579 case MVT::v2f32: return fastEmit_ISD_BITCAST_MVT_v1f64_MVT_v2f32_r(Op0, Op0IsKill); 2580 default: return 0; 2581} 2582} 2583 2584unsigned fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) { 2585 if ((!Subtarget->isLittleEndian())) { 2586 return fastEmitInst_r(AArch64::REV64v16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2587 } 2588 return 0; 2589} 2590 2591unsigned fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) { 2592 if ((!Subtarget->isLittleEndian())) { 2593 return fastEmitInst_r(AArch64::REV64v8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2594 } 2595 return 0; 2596} 2597 2598unsigned fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) { 2599 if ((!Subtarget->isLittleEndian())) { 2600 return fastEmitInst_r(AArch64::REV64v4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2601 } 2602 return 0; 2603} 2604 2605unsigned fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v8f16_r(unsigned Op0, bool Op0IsKill) { 2606 if ((!Subtarget->isLittleEndian())) { 2607 return fastEmitInst_r(AArch64::REV64v8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2608 } 2609 return 0; 2610} 2611 2612unsigned fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v4f32_r(unsigned Op0, bool Op0IsKill) { 2613 if ((!Subtarget->isLittleEndian())) { 2614 return fastEmitInst_r(AArch64::REV64v4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2615 } 2616 return 0; 2617} 2618 2619unsigned fastEmit_ISD_BITCAST_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2620switch (RetVT.SimpleTy) { 2621 case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v16i8_r(Op0, Op0IsKill); 2622 case MVT::v8i16: return fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v8i16_r(Op0, Op0IsKill); 2623 case MVT::v4i32: return fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v4i32_r(Op0, Op0IsKill); 2624 case MVT::v8f16: return fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v8f16_r(Op0, Op0IsKill); 2625 case MVT::v4f32: return fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v4f32_r(Op0, Op0IsKill); 2626 default: return 0; 2627} 2628} 2629 2630unsigned fastEmit_ISD_BITCAST_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 2631 switch (VT.SimpleTy) { 2632 case MVT::f64: return fastEmit_ISD_BITCAST_MVT_f64_r(RetVT, Op0, Op0IsKill); 2633 case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_v8i8_r(RetVT, Op0, Op0IsKill); 2634 case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v16i8_r(RetVT, Op0, Op0IsKill); 2635 case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_v4i16_r(RetVT, Op0, Op0IsKill); 2636 case MVT::v8i16: return fastEmit_ISD_BITCAST_MVT_v8i16_r(RetVT, Op0, Op0IsKill); 2637 case MVT::v2i32: return fastEmit_ISD_BITCAST_MVT_v2i32_r(RetVT, Op0, Op0IsKill); 2638 case MVT::v4i32: return fastEmit_ISD_BITCAST_MVT_v4i32_r(RetVT, Op0, Op0IsKill); 2639 case MVT::v1i64: return fastEmit_ISD_BITCAST_MVT_v1i64_r(RetVT, Op0, Op0IsKill); 2640 case MVT::v2i64: return fastEmit_ISD_BITCAST_MVT_v2i64_r(RetVT, Op0, Op0IsKill); 2641 case MVT::v4f16: return fastEmit_ISD_BITCAST_MVT_v4f16_r(RetVT, Op0, Op0IsKill); 2642 case MVT::v8f16: return fastEmit_ISD_BITCAST_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 2643 case MVT::v2f32: return fastEmit_ISD_BITCAST_MVT_v2f32_r(RetVT, Op0, Op0IsKill); 2644 case MVT::v4f32: return fastEmit_ISD_BITCAST_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 2645 case MVT::v1f64: return fastEmit_ISD_BITCAST_MVT_v1f64_r(RetVT, Op0, Op0IsKill); 2646 case MVT::v2f64: return fastEmit_ISD_BITCAST_MVT_v2f64_r(RetVT, Op0, Op0IsKill); 2647 default: return 0; 2648 } 2649} 2650 2651// FastEmit functions for ISD::BITREVERSE. 2652 2653unsigned fastEmit_ISD_BITREVERSE_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2654 if (RetVT.SimpleTy != MVT::i32) 2655 return 0; 2656 return fastEmitInst_r(AArch64::RBITWr, &AArch64::GPR32RegClass, Op0, Op0IsKill); 2657} 2658 2659unsigned fastEmit_ISD_BITREVERSE_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2660 if (RetVT.SimpleTy != MVT::i64) 2661 return 0; 2662 return fastEmitInst_r(AArch64::RBITXr, &AArch64::GPR64RegClass, Op0, Op0IsKill); 2663} 2664 2665unsigned fastEmit_ISD_BITREVERSE_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 2666 switch (VT.SimpleTy) { 2667 case MVT::i32: return fastEmit_ISD_BITREVERSE_MVT_i32_r(RetVT, Op0, Op0IsKill); 2668 case MVT::i64: return fastEmit_ISD_BITREVERSE_MVT_i64_r(RetVT, Op0, Op0IsKill); 2669 default: return 0; 2670 } 2671} 2672 2673// FastEmit functions for ISD::BRIND. 2674 2675unsigned fastEmit_ISD_BRIND_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2676 if (RetVT.SimpleTy != MVT::isVoid) 2677 return 0; 2678 return fastEmitInst_r(AArch64::BR, &AArch64::GPR64RegClass, Op0, Op0IsKill); 2679} 2680 2681unsigned fastEmit_ISD_BRIND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 2682 switch (VT.SimpleTy) { 2683 case MVT::i64: return fastEmit_ISD_BRIND_MVT_i64_r(RetVT, Op0, Op0IsKill); 2684 default: return 0; 2685 } 2686} 2687 2688// FastEmit functions for ISD::BSWAP. 2689 2690unsigned fastEmit_ISD_BSWAP_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2691 if (RetVT.SimpleTy != MVT::i32) 2692 return 0; 2693 return fastEmitInst_r(AArch64::REVWr, &AArch64::GPR32RegClass, Op0, Op0IsKill); 2694} 2695 2696unsigned fastEmit_ISD_BSWAP_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2697 if (RetVT.SimpleTy != MVT::i64) 2698 return 0; 2699 return fastEmitInst_r(AArch64::REVXr, &AArch64::GPR64RegClass, Op0, Op0IsKill); 2700} 2701 2702unsigned fastEmit_ISD_BSWAP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 2703 switch (VT.SimpleTy) { 2704 case MVT::i32: return fastEmit_ISD_BSWAP_MVT_i32_r(RetVT, Op0, Op0IsKill); 2705 case MVT::i64: return fastEmit_ISD_BSWAP_MVT_i64_r(RetVT, Op0, Op0IsKill); 2706 default: return 0; 2707 } 2708} 2709 2710// FastEmit functions for ISD::CTLZ. 2711 2712unsigned fastEmit_ISD_CTLZ_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2713 if (RetVT.SimpleTy != MVT::i32) 2714 return 0; 2715 return fastEmitInst_r(AArch64::CLZWr, &AArch64::GPR32RegClass, Op0, Op0IsKill); 2716} 2717 2718unsigned fastEmit_ISD_CTLZ_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2719 if (RetVT.SimpleTy != MVT::i64) 2720 return 0; 2721 return fastEmitInst_r(AArch64::CLZXr, &AArch64::GPR64RegClass, Op0, Op0IsKill); 2722} 2723 2724unsigned fastEmit_ISD_CTLZ_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2725 if (RetVT.SimpleTy != MVT::v8i8) 2726 return 0; 2727 if ((Subtarget->hasNEON())) { 2728 return fastEmitInst_r(AArch64::CLZv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2729 } 2730 return 0; 2731} 2732 2733unsigned fastEmit_ISD_CTLZ_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2734 if (RetVT.SimpleTy != MVT::v16i8) 2735 return 0; 2736 if ((Subtarget->hasNEON())) { 2737 return fastEmitInst_r(AArch64::CLZv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2738 } 2739 return 0; 2740} 2741 2742unsigned fastEmit_ISD_CTLZ_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2743 if (RetVT.SimpleTy != MVT::v4i16) 2744 return 0; 2745 if ((Subtarget->hasNEON())) { 2746 return fastEmitInst_r(AArch64::CLZv4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2747 } 2748 return 0; 2749} 2750 2751unsigned fastEmit_ISD_CTLZ_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2752 if (RetVT.SimpleTy != MVT::v8i16) 2753 return 0; 2754 if ((Subtarget->hasNEON())) { 2755 return fastEmitInst_r(AArch64::CLZv8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2756 } 2757 return 0; 2758} 2759 2760unsigned fastEmit_ISD_CTLZ_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2761 if (RetVT.SimpleTy != MVT::v2i32) 2762 return 0; 2763 if ((Subtarget->hasNEON())) { 2764 return fastEmitInst_r(AArch64::CLZv2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2765 } 2766 return 0; 2767} 2768 2769unsigned fastEmit_ISD_CTLZ_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2770 if (RetVT.SimpleTy != MVT::v4i32) 2771 return 0; 2772 if ((Subtarget->hasNEON())) { 2773 return fastEmitInst_r(AArch64::CLZv4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2774 } 2775 return 0; 2776} 2777 2778unsigned fastEmit_ISD_CTLZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 2779 switch (VT.SimpleTy) { 2780 case MVT::i32: return fastEmit_ISD_CTLZ_MVT_i32_r(RetVT, Op0, Op0IsKill); 2781 case MVT::i64: return fastEmit_ISD_CTLZ_MVT_i64_r(RetVT, Op0, Op0IsKill); 2782 case MVT::v8i8: return fastEmit_ISD_CTLZ_MVT_v8i8_r(RetVT, Op0, Op0IsKill); 2783 case MVT::v16i8: return fastEmit_ISD_CTLZ_MVT_v16i8_r(RetVT, Op0, Op0IsKill); 2784 case MVT::v4i16: return fastEmit_ISD_CTLZ_MVT_v4i16_r(RetVT, Op0, Op0IsKill); 2785 case MVT::v8i16: return fastEmit_ISD_CTLZ_MVT_v8i16_r(RetVT, Op0, Op0IsKill); 2786 case MVT::v2i32: return fastEmit_ISD_CTLZ_MVT_v2i32_r(RetVT, Op0, Op0IsKill); 2787 case MVT::v4i32: return fastEmit_ISD_CTLZ_MVT_v4i32_r(RetVT, Op0, Op0IsKill); 2788 default: return 0; 2789 } 2790} 2791 2792// FastEmit functions for ISD::CTPOP. 2793 2794unsigned fastEmit_ISD_CTPOP_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2795 if (RetVT.SimpleTy != MVT::v8i8) 2796 return 0; 2797 if ((Subtarget->hasNEON())) { 2798 return fastEmitInst_r(AArch64::CNTv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2799 } 2800 return 0; 2801} 2802 2803unsigned fastEmit_ISD_CTPOP_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2804 if (RetVT.SimpleTy != MVT::v16i8) 2805 return 0; 2806 if ((Subtarget->hasNEON())) { 2807 return fastEmitInst_r(AArch64::CNTv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2808 } 2809 return 0; 2810} 2811 2812unsigned fastEmit_ISD_CTPOP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 2813 switch (VT.SimpleTy) { 2814 case MVT::v8i8: return fastEmit_ISD_CTPOP_MVT_v8i8_r(RetVT, Op0, Op0IsKill); 2815 case MVT::v16i8: return fastEmit_ISD_CTPOP_MVT_v16i8_r(RetVT, Op0, Op0IsKill); 2816 default: return 0; 2817 } 2818} 2819 2820// FastEmit functions for ISD::FABS. 2821 2822unsigned fastEmit_ISD_FABS_MVT_f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2823 if (RetVT.SimpleTy != MVT::f16) 2824 return 0; 2825 if ((Subtarget->hasFullFP16())) { 2826 return fastEmitInst_r(AArch64::FABSHr, &AArch64::FPR16RegClass, Op0, Op0IsKill); 2827 } 2828 return 0; 2829} 2830 2831unsigned fastEmit_ISD_FABS_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2832 if (RetVT.SimpleTy != MVT::f32) 2833 return 0; 2834 if ((Subtarget->hasFPARMv8())) { 2835 return fastEmitInst_r(AArch64::FABSSr, &AArch64::FPR32RegClass, Op0, Op0IsKill); 2836 } 2837 return 0; 2838} 2839 2840unsigned fastEmit_ISD_FABS_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2841 if (RetVT.SimpleTy != MVT::f64) 2842 return 0; 2843 if ((Subtarget->hasFPARMv8())) { 2844 return fastEmitInst_r(AArch64::FABSDr, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2845 } 2846 return 0; 2847} 2848 2849unsigned fastEmit_ISD_FABS_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2850 if (RetVT.SimpleTy != MVT::v4f16) 2851 return 0; 2852 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 2853 return fastEmitInst_r(AArch64::FABSv4f16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2854 } 2855 return 0; 2856} 2857 2858unsigned fastEmit_ISD_FABS_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2859 if (RetVT.SimpleTy != MVT::v8f16) 2860 return 0; 2861 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 2862 return fastEmitInst_r(AArch64::FABSv8f16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2863 } 2864 return 0; 2865} 2866 2867unsigned fastEmit_ISD_FABS_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2868 if (RetVT.SimpleTy != MVT::v2f32) 2869 return 0; 2870 if ((Subtarget->hasNEON())) { 2871 return fastEmitInst_r(AArch64::FABSv2f32, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2872 } 2873 return 0; 2874} 2875 2876unsigned fastEmit_ISD_FABS_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2877 if (RetVT.SimpleTy != MVT::v4f32) 2878 return 0; 2879 if ((Subtarget->hasNEON())) { 2880 return fastEmitInst_r(AArch64::FABSv4f32, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2881 } 2882 return 0; 2883} 2884 2885unsigned fastEmit_ISD_FABS_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2886 if (RetVT.SimpleTy != MVT::v2f64) 2887 return 0; 2888 if ((Subtarget->hasNEON())) { 2889 return fastEmitInst_r(AArch64::FABSv2f64, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2890 } 2891 return 0; 2892} 2893 2894unsigned fastEmit_ISD_FABS_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 2895 switch (VT.SimpleTy) { 2896 case MVT::f16: return fastEmit_ISD_FABS_MVT_f16_r(RetVT, Op0, Op0IsKill); 2897 case MVT::f32: return fastEmit_ISD_FABS_MVT_f32_r(RetVT, Op0, Op0IsKill); 2898 case MVT::f64: return fastEmit_ISD_FABS_MVT_f64_r(RetVT, Op0, Op0IsKill); 2899 case MVT::v4f16: return fastEmit_ISD_FABS_MVT_v4f16_r(RetVT, Op0, Op0IsKill); 2900 case MVT::v8f16: return fastEmit_ISD_FABS_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 2901 case MVT::v2f32: return fastEmit_ISD_FABS_MVT_v2f32_r(RetVT, Op0, Op0IsKill); 2902 case MVT::v4f32: return fastEmit_ISD_FABS_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 2903 case MVT::v2f64: return fastEmit_ISD_FABS_MVT_v2f64_r(RetVT, Op0, Op0IsKill); 2904 default: return 0; 2905 } 2906} 2907 2908// FastEmit functions for ISD::FCEIL. 2909 2910unsigned fastEmit_ISD_FCEIL_MVT_f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2911 if (RetVT.SimpleTy != MVT::f16) 2912 return 0; 2913 if ((Subtarget->hasFullFP16())) { 2914 return fastEmitInst_r(AArch64::FRINTPHr, &AArch64::FPR16RegClass, Op0, Op0IsKill); 2915 } 2916 return 0; 2917} 2918 2919unsigned fastEmit_ISD_FCEIL_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2920 if (RetVT.SimpleTy != MVT::f32) 2921 return 0; 2922 if ((Subtarget->hasFPARMv8())) { 2923 return fastEmitInst_r(AArch64::FRINTPSr, &AArch64::FPR32RegClass, Op0, Op0IsKill); 2924 } 2925 return 0; 2926} 2927 2928unsigned fastEmit_ISD_FCEIL_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2929 if (RetVT.SimpleTy != MVT::f64) 2930 return 0; 2931 if ((Subtarget->hasFPARMv8())) { 2932 return fastEmitInst_r(AArch64::FRINTPDr, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2933 } 2934 return 0; 2935} 2936 2937unsigned fastEmit_ISD_FCEIL_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2938 if (RetVT.SimpleTy != MVT::v4f16) 2939 return 0; 2940 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 2941 return fastEmitInst_r(AArch64::FRINTPv4f16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2942 } 2943 return 0; 2944} 2945 2946unsigned fastEmit_ISD_FCEIL_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2947 if (RetVT.SimpleTy != MVT::v8f16) 2948 return 0; 2949 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 2950 return fastEmitInst_r(AArch64::FRINTPv8f16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2951 } 2952 return 0; 2953} 2954 2955unsigned fastEmit_ISD_FCEIL_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2956 if (RetVT.SimpleTy != MVT::v2f32) 2957 return 0; 2958 if ((Subtarget->hasNEON())) { 2959 return fastEmitInst_r(AArch64::FRINTPv2f32, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2960 } 2961 return 0; 2962} 2963 2964unsigned fastEmit_ISD_FCEIL_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2965 if (RetVT.SimpleTy != MVT::v4f32) 2966 return 0; 2967 if ((Subtarget->hasNEON())) { 2968 return fastEmitInst_r(AArch64::FRINTPv4f32, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2969 } 2970 return 0; 2971} 2972 2973unsigned fastEmit_ISD_FCEIL_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2974 if (RetVT.SimpleTy != MVT::v2f64) 2975 return 0; 2976 if ((Subtarget->hasNEON())) { 2977 return fastEmitInst_r(AArch64::FRINTPv2f64, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2978 } 2979 return 0; 2980} 2981 2982unsigned fastEmit_ISD_FCEIL_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 2983 switch (VT.SimpleTy) { 2984 case MVT::f16: return fastEmit_ISD_FCEIL_MVT_f16_r(RetVT, Op0, Op0IsKill); 2985 case MVT::f32: return fastEmit_ISD_FCEIL_MVT_f32_r(RetVT, Op0, Op0IsKill); 2986 case MVT::f64: return fastEmit_ISD_FCEIL_MVT_f64_r(RetVT, Op0, Op0IsKill); 2987 case MVT::v4f16: return fastEmit_ISD_FCEIL_MVT_v4f16_r(RetVT, Op0, Op0IsKill); 2988 case MVT::v8f16: return fastEmit_ISD_FCEIL_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 2989 case MVT::v2f32: return fastEmit_ISD_FCEIL_MVT_v2f32_r(RetVT, Op0, Op0IsKill); 2990 case MVT::v4f32: return fastEmit_ISD_FCEIL_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 2991 case MVT::v2f64: return fastEmit_ISD_FCEIL_MVT_v2f64_r(RetVT, Op0, Op0IsKill); 2992 default: return 0; 2993 } 2994} 2995 2996// FastEmit functions for ISD::FFLOOR. 2997 2998unsigned fastEmit_ISD_FFLOOR_MVT_f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2999 if (RetVT.SimpleTy != MVT::f16) 3000 return 0; 3001 if ((Subtarget->hasFullFP16())) { 3002 return fastEmitInst_r(AArch64::FRINTMHr, &AArch64::FPR16RegClass, Op0, Op0IsKill); 3003 } 3004 return 0; 3005} 3006 3007unsigned fastEmit_ISD_FFLOOR_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3008 if (RetVT.SimpleTy != MVT::f32) 3009 return 0; 3010 if ((Subtarget->hasFPARMv8())) { 3011 return fastEmitInst_r(AArch64::FRINTMSr, &AArch64::FPR32RegClass, Op0, Op0IsKill); 3012 } 3013 return 0; 3014} 3015 3016unsigned fastEmit_ISD_FFLOOR_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3017 if (RetVT.SimpleTy != MVT::f64) 3018 return 0; 3019 if ((Subtarget->hasFPARMv8())) { 3020 return fastEmitInst_r(AArch64::FRINTMDr, &AArch64::FPR64RegClass, Op0, Op0IsKill); 3021 } 3022 return 0; 3023} 3024 3025unsigned fastEmit_ISD_FFLOOR_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3026 if (RetVT.SimpleTy != MVT::v4f16) 3027 return 0; 3028 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 3029 return fastEmitInst_r(AArch64::FRINTMv4f16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 3030 } 3031 return 0; 3032} 3033 3034unsigned fastEmit_ISD_FFLOOR_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3035 if (RetVT.SimpleTy != MVT::v8f16) 3036 return 0; 3037 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 3038 return fastEmitInst_r(AArch64::FRINTMv8f16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 3039 } 3040 return 0; 3041} 3042 3043unsigned fastEmit_ISD_FFLOOR_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3044 if (RetVT.SimpleTy != MVT::v2f32) 3045 return 0; 3046 if ((Subtarget->hasNEON())) { 3047 return fastEmitInst_r(AArch64::FRINTMv2f32, &AArch64::FPR64RegClass, Op0, Op0IsKill); 3048 } 3049 return 0; 3050} 3051 3052unsigned fastEmit_ISD_FFLOOR_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3053 if (RetVT.SimpleTy != MVT::v4f32) 3054 return 0; 3055 if ((Subtarget->hasNEON())) { 3056 return fastEmitInst_r(AArch64::FRINTMv4f32, &AArch64::FPR128RegClass, Op0, Op0IsKill); 3057 } 3058 return 0; 3059} 3060 3061unsigned fastEmit_ISD_FFLOOR_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3062 if (RetVT.SimpleTy != MVT::v2f64) 3063 return 0; 3064 if ((Subtarget->hasNEON())) { 3065 return fastEmitInst_r(AArch64::FRINTMv2f64, &AArch64::FPR128RegClass, Op0, Op0IsKill); 3066 } 3067 return 0; 3068} 3069 3070unsigned fastEmit_ISD_FFLOOR_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 3071 switch (VT.SimpleTy) { 3072 case MVT::f16: return fastEmit_ISD_FFLOOR_MVT_f16_r(RetVT, Op0, Op0IsKill); 3073 case MVT::f32: return fastEmit_ISD_FFLOOR_MVT_f32_r(RetVT, Op0, Op0IsKill); 3074 case MVT::f64: return fastEmit_ISD_FFLOOR_MVT_f64_r(RetVT, Op0, Op0IsKill); 3075 case MVT::v4f16: return fastEmit_ISD_FFLOOR_MVT_v4f16_r(RetVT, Op0, Op0IsKill); 3076 case MVT::v8f16: return fastEmit_ISD_FFLOOR_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 3077 case MVT::v2f32: return fastEmit_ISD_FFLOOR_MVT_v2f32_r(RetVT, Op0, Op0IsKill); 3078 case MVT::v4f32: return fastEmit_ISD_FFLOOR_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 3079 case MVT::v2f64: return fastEmit_ISD_FFLOOR_MVT_v2f64_r(RetVT, Op0, Op0IsKill); 3080 default: return 0; 3081 } 3082} 3083 3084// FastEmit functions for ISD::FNEARBYINT. 3085 3086unsigned fastEmit_ISD_FNEARBYINT_MVT_f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3087 if (RetVT.SimpleTy != MVT::f16) 3088 return 0; 3089 if ((Subtarget->hasFullFP16())) { 3090 return fastEmitInst_r(AArch64::FRINTIHr, &AArch64::FPR16RegClass, Op0, Op0IsKill); 3091 } 3092 return 0; 3093} 3094 3095unsigned fastEmit_ISD_FNEARBYINT_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3096 if (RetVT.SimpleTy != MVT::f32) 3097 return 0; 3098 if ((Subtarget->hasFPARMv8())) { 3099 return fastEmitInst_r(AArch64::FRINTISr, &AArch64::FPR32RegClass, Op0, Op0IsKill); 3100 } 3101 return 0; 3102} 3103 3104unsigned fastEmit_ISD_FNEARBYINT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3105 if (RetVT.SimpleTy != MVT::f64) 3106 return 0; 3107 if ((Subtarget->hasFPARMv8())) { 3108 return fastEmitInst_r(AArch64::FRINTIDr, &AArch64::FPR64RegClass, Op0, Op0IsKill); 3109 } 3110 return 0; 3111} 3112 3113unsigned fastEmit_ISD_FNEARBYINT_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3114 if (RetVT.SimpleTy != MVT::v4f16) 3115 return 0; 3116 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 3117 return fastEmitInst_r(AArch64::FRINTIv4f16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 3118 } 3119 return 0; 3120} 3121 3122unsigned fastEmit_ISD_FNEARBYINT_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3123 if (RetVT.SimpleTy != MVT::v8f16) 3124 return 0; 3125 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 3126 return fastEmitInst_r(AArch64::FRINTIv8f16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 3127 } 3128 return 0; 3129} 3130 3131unsigned fastEmit_ISD_FNEARBYINT_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3132 if (RetVT.SimpleTy != MVT::v2f32) 3133 return 0; 3134 if ((Subtarget->hasNEON())) { 3135 return fastEmitInst_r(AArch64::FRINTIv2f32, &AArch64::FPR64RegClass, Op0, Op0IsKill); 3136 } 3137 return 0; 3138} 3139 3140unsigned fastEmit_ISD_FNEARBYINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3141 if (RetVT.SimpleTy != MVT::v4f32) 3142 return 0; 3143 if ((Subtarget->hasNEON())) { 3144 return fastEmitInst_r(AArch64::FRINTIv4f32, &AArch64::FPR128RegClass, Op0, Op0IsKill); 3145 } 3146 return 0; 3147} 3148 3149unsigned fastEmit_ISD_FNEARBYINT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3150 if (RetVT.SimpleTy != MVT::v2f64) 3151 return 0; 3152 if ((Subtarget->hasNEON())) { 3153 return fastEmitInst_r(AArch64::FRINTIv2f64, &AArch64::FPR128RegClass, Op0, Op0IsKill); 3154 } 3155 return 0; 3156} 3157 3158unsigned fastEmit_ISD_FNEARBYINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 3159 switch (VT.SimpleTy) { 3160 case MVT::f16: return fastEmit_ISD_FNEARBYINT_MVT_f16_r(RetVT, Op0, Op0IsKill); 3161 case MVT::f32: return fastEmit_ISD_FNEARBYINT_MVT_f32_r(RetVT, Op0, Op0IsKill); 3162 case MVT::f64: return fastEmit_ISD_FNEARBYINT_MVT_f64_r(RetVT, Op0, Op0IsKill); 3163 case MVT::v4f16: return fastEmit_ISD_FNEARBYINT_MVT_v4f16_r(RetVT, Op0, Op0IsKill); 3164 case MVT::v8f16: return fastEmit_ISD_FNEARBYINT_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 3165 case MVT::v2f32: return fastEmit_ISD_FNEARBYINT_MVT_v2f32_r(RetVT, Op0, Op0IsKill); 3166 case MVT::v4f32: return fastEmit_ISD_FNEARBYINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 3167 case MVT::v2f64: return fastEmit_ISD_FNEARBYINT_MVT_v2f64_r(RetVT, Op0, Op0IsKill); 3168 default: return 0; 3169 } 3170} 3171 3172// FastEmit functions for ISD::FNEG. 3173 3174unsigned fastEmit_ISD_FNEG_MVT_f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3175 if (RetVT.SimpleTy != MVT::f16) 3176 return 0; 3177 if ((Subtarget->hasFullFP16())) { 3178 return fastEmitInst_r(AArch64::FNEGHr, &AArch64::FPR16RegClass, Op0, Op0IsKill); 3179 } 3180 return 0; 3181} 3182 3183unsigned fastEmit_ISD_FNEG_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3184 if (RetVT.SimpleTy != MVT::f32) 3185 return 0; 3186 if ((Subtarget->hasFPARMv8())) { 3187 return fastEmitInst_r(AArch64::FNEGSr, &AArch64::FPR32RegClass, Op0, Op0IsKill); 3188 } 3189 return 0; 3190} 3191 3192unsigned fastEmit_ISD_FNEG_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3193 if (RetVT.SimpleTy != MVT::f64) 3194 return 0; 3195 if ((Subtarget->hasFPARMv8())) { 3196 return fastEmitInst_r(AArch64::FNEGDr, &AArch64::FPR64RegClass, Op0, Op0IsKill); 3197 } 3198 return 0; 3199} 3200 3201unsigned fastEmit_ISD_FNEG_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3202 if (RetVT.SimpleTy != MVT::v4f16) 3203 return 0; 3204 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 3205 return fastEmitInst_r(AArch64::FNEGv4f16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 3206 } 3207 return 0; 3208} 3209 3210unsigned fastEmit_ISD_FNEG_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3211 if (RetVT.SimpleTy != MVT::v8f16) 3212 return 0; 3213 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 3214 return fastEmitInst_r(AArch64::FNEGv8f16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 3215 } 3216 return 0; 3217} 3218 3219unsigned fastEmit_ISD_FNEG_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3220 if (RetVT.SimpleTy != MVT::v2f32) 3221 return 0; 3222 if ((Subtarget->hasNEON())) { 3223 return fastEmitInst_r(AArch64::FNEGv2f32, &AArch64::FPR64RegClass, Op0, Op0IsKill); 3224 } 3225 return 0; 3226} 3227 3228unsigned fastEmit_ISD_FNEG_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3229 if (RetVT.SimpleTy != MVT::v4f32) 3230 return 0; 3231 if ((Subtarget->hasNEON())) { 3232 return fastEmitInst_r(AArch64::FNEGv4f32, &AArch64::FPR128RegClass, Op0, Op0IsKill); 3233 } 3234 return 0; 3235} 3236 3237unsigned fastEmit_ISD_FNEG_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3238 if (RetVT.SimpleTy != MVT::v2f64) 3239 return 0; 3240 if ((Subtarget->hasNEON())) { 3241 return fastEmitInst_r(AArch64::FNEGv2f64, &AArch64::FPR128RegClass, Op0, Op0IsKill); 3242 } 3243 return 0; 3244} 3245 3246unsigned fastEmit_ISD_FNEG_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 3247 switch (VT.SimpleTy) { 3248 case MVT::f16: return fastEmit_ISD_FNEG_MVT_f16_r(RetVT, Op0, Op0IsKill); 3249 case MVT::f32: return fastEmit_ISD_FNEG_MVT_f32_r(RetVT, Op0, Op0IsKill); 3250 case MVT::f64: return fastEmit_ISD_FNEG_MVT_f64_r(RetVT, Op0, Op0IsKill); 3251 case MVT::v4f16: return fastEmit_ISD_FNEG_MVT_v4f16_r(RetVT, Op0, Op0IsKill); 3252 case MVT::v8f16: return fastEmit_ISD_FNEG_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 3253 case MVT::v2f32: return fastEmit_ISD_FNEG_MVT_v2f32_r(RetVT, Op0, Op0IsKill); 3254 case MVT::v4f32: return fastEmit_ISD_FNEG_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 3255 case MVT::v2f64: return fastEmit_ISD_FNEG_MVT_v2f64_r(RetVT, Op0, Op0IsKill); 3256 default: return 0; 3257 } 3258} 3259 3260// FastEmit functions for ISD::FP_EXTEND. 3261 3262unsigned fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f32_r(unsigned Op0, bool Op0IsKill) { 3263 if ((Subtarget->hasFPARMv8())) { 3264 return fastEmitInst_r(AArch64::FCVTSHr, &AArch64::FPR32RegClass, Op0, Op0IsKill); 3265 } 3266 return 0; 3267} 3268 3269unsigned fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f64_r(unsigned Op0, bool Op0IsKill) { 3270 if ((Subtarget->hasFPARMv8())) { 3271 return fastEmitInst_r(AArch64::FCVTDHr, &AArch64::FPR64RegClass, Op0, Op0IsKill); 3272 } 3273 return 0; 3274} 3275 3276unsigned fastEmit_ISD_FP_EXTEND_MVT_f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3277switch (RetVT.SimpleTy) { 3278 case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f32_r(Op0, Op0IsKill); 3279 case MVT::f64: return fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f64_r(Op0, Op0IsKill); 3280 default: return 0; 3281} 3282} 3283 3284unsigned fastEmit_ISD_FP_EXTEND_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3285 if (RetVT.SimpleTy != MVT::f64) 3286 return 0; 3287 if ((Subtarget->hasFPARMv8())) { 3288 return fastEmitInst_r(AArch64::FCVTDSr, &AArch64::FPR64RegClass, Op0, Op0IsKill); 3289 } 3290 return 0; 3291} 3292 3293unsigned fastEmit_ISD_FP_EXTEND_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3294 if (RetVT.SimpleTy != MVT::v4f32) 3295 return 0; 3296 return fastEmitInst_r(AArch64::FCVTLv4i16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 3297} 3298 3299unsigned fastEmit_ISD_FP_EXTEND_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3300 if (RetVT.SimpleTy != MVT::v2f64) 3301 return 0; 3302 return fastEmitInst_r(AArch64::FCVTLv2i32, &AArch64::FPR128RegClass, Op0, Op0IsKill); 3303} 3304 3305unsigned fastEmit_ISD_FP_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 3306 switch (VT.SimpleTy) { 3307 case MVT::f16: return fastEmit_ISD_FP_EXTEND_MVT_f16_r(RetVT, Op0, Op0IsKill); 3308 case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f32_r(RetVT, Op0, Op0IsKill); 3309 case MVT::v4f16: return fastEmit_ISD_FP_EXTEND_MVT_v4f16_r(RetVT, Op0, Op0IsKill); 3310 case MVT::v2f32: return fastEmit_ISD_FP_EXTEND_MVT_v2f32_r(RetVT, Op0, Op0IsKill); 3311 default: return 0; 3312 } 3313} 3314 3315// FastEmit functions for ISD::FP_ROUND. 3316 3317unsigned fastEmit_ISD_FP_ROUND_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3318 if (RetVT.SimpleTy != MVT::f16) 3319 return 0; 3320 if ((Subtarget->hasFPARMv8())) { 3321 return fastEmitInst_r(AArch64::FCVTHSr, &AArch64::FPR16RegClass, Op0, Op0IsKill); 3322 } 3323 return 0; 3324} 3325 3326unsigned fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f16_r(unsigned Op0, bool Op0IsKill) { 3327 if ((Subtarget->hasFPARMv8())) { 3328 return fastEmitInst_r(AArch64::FCVTHDr, &AArch64::FPR16RegClass, Op0, Op0IsKill); 3329 } 3330 return 0; 3331} 3332 3333unsigned fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f32_r(unsigned Op0, bool Op0IsKill) { 3334 if ((Subtarget->hasFPARMv8())) { 3335 return fastEmitInst_r(AArch64::FCVTSDr, &AArch64::FPR32RegClass, Op0, Op0IsKill); 3336 } 3337 return 0; 3338} 3339 3340unsigned fastEmit_ISD_FP_ROUND_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3341switch (RetVT.SimpleTy) { 3342 case MVT::f16: return fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f16_r(Op0, Op0IsKill); 3343 case MVT::f32: return fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f32_r(Op0, Op0IsKill); 3344 default: return 0; 3345} 3346} 3347 3348unsigned fastEmit_ISD_FP_ROUND_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3349 if (RetVT.SimpleTy != MVT::v4f16) 3350 return 0; 3351 return fastEmitInst_r(AArch64::FCVTNv4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 3352} 3353 3354unsigned fastEmit_ISD_FP_ROUND_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3355 if (RetVT.SimpleTy != MVT::v2f32) 3356 return 0; 3357 return fastEmitInst_r(AArch64::FCVTNv2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill); 3358} 3359 3360unsigned fastEmit_ISD_FP_ROUND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 3361 switch (VT.SimpleTy) { 3362 case MVT::f32: return fastEmit_ISD_FP_ROUND_MVT_f32_r(RetVT, Op0, Op0IsKill); 3363 case MVT::f64: return fastEmit_ISD_FP_ROUND_MVT_f64_r(RetVT, Op0, Op0IsKill); 3364 case MVT::v4f32: return fastEmit_ISD_FP_ROUND_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 3365 case MVT::v2f64: return fastEmit_ISD_FP_ROUND_MVT_v2f64_r(RetVT, Op0, Op0IsKill); 3366 default: return 0; 3367 } 3368} 3369 3370// FastEmit functions for ISD::FP_TO_SINT. 3371 3372unsigned fastEmit_ISD_FP_TO_SINT_MVT_f16_MVT_i32_r(unsigned Op0, bool Op0IsKill) { 3373 if ((Subtarget->hasFullFP16())) { 3374 return fastEmitInst_r(AArch64::FCVTZSUWHr, &AArch64::GPR32RegClass, Op0, Op0IsKill); 3375 } 3376 return 0; 3377} 3378 3379unsigned fastEmit_ISD_FP_TO_SINT_MVT_f16_MVT_i64_r(unsigned Op0, bool Op0IsKill) { 3380 if ((Subtarget->hasFullFP16())) { 3381 return fastEmitInst_r(AArch64::FCVTZSUXHr, &AArch64::GPR64RegClass, Op0, Op0IsKill); 3382 } 3383 return 0; 3384} 3385 3386unsigned fastEmit_ISD_FP_TO_SINT_MVT_f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3387switch (RetVT.SimpleTy) { 3388 case MVT::i32: return fastEmit_ISD_FP_TO_SINT_MVT_f16_MVT_i32_r(Op0, Op0IsKill); 3389 case MVT::i64: return fastEmit_ISD_FP_TO_SINT_MVT_f16_MVT_i64_r(Op0, Op0IsKill); 3390 default: return 0; 3391} 3392} 3393 3394unsigned fastEmit_ISD_FP_TO_SINT_MVT_f32_MVT_i32_r(unsigned Op0, bool Op0IsKill) { 3395 if ((Subtarget->hasFPARMv8())) { 3396 return fastEmitInst_r(AArch64::FCVTZSUWSr, &AArch64::GPR32RegClass, Op0, Op0IsKill); 3397 } 3398 return 0; 3399} 3400 3401unsigned fastEmit_ISD_FP_TO_SINT_MVT_f32_MVT_i64_r(unsigned Op0, bool Op0IsKill) { 3402 if ((Subtarget->hasFPARMv8())) { 3403 return fastEmitInst_r(AArch64::FCVTZSUXSr, &AArch64::GPR64RegClass, Op0, Op0IsKill); 3404 } 3405 return 0; 3406} 3407 3408unsigned fastEmit_ISD_FP_TO_SINT_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3409switch (RetVT.SimpleTy) { 3410 case MVT::i32: return fastEmit_ISD_FP_TO_SINT_MVT_f32_MVT_i32_r(Op0, Op0IsKill); 3411 case MVT::i64: return fastEmit_ISD_FP_TO_SINT_MVT_f32_MVT_i64_r(Op0, Op0IsKill); 3412 default: return 0; 3413} 3414} 3415 3416unsigned fastEmit_ISD_FP_TO_SINT_MVT_f64_MVT_i32_r(unsigned Op0, bool Op0IsKill) { 3417 if ((Subtarget->hasFPARMv8())) { 3418 return fastEmitInst_r(AArch64::FCVTZSUWDr, &AArch64::GPR32RegClass, Op0, Op0IsKill); 3419 } 3420 return 0; 3421} 3422 3423unsigned fastEmit_ISD_FP_TO_SINT_MVT_f64_MVT_i64_r(unsigned Op0, bool Op0IsKill) { 3424 if ((Subtarget->hasFPARMv8())) { 3425 return fastEmitInst_r(AArch64::FCVTZSUXDr, &AArch64::GPR64RegClass, Op0, Op0IsKill); 3426 } 3427 return 0; 3428} 3429 3430unsigned fastEmit_ISD_FP_TO_SINT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3431switch (RetVT.SimpleTy) { 3432 case MVT::i32: return fastEmit_ISD_FP_TO_SINT_MVT_f64_MVT_i32_r(Op0, Op0IsKill); 3433 case MVT::i64: return fastEmit_ISD_FP_TO_SINT_MVT_f64_MVT_i64_r(Op0, Op0IsKill); 3434 default: return 0; 3435} 3436} 3437 3438unsigned fastEmit_ISD_FP_TO_SINT_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3439 if (RetVT.SimpleTy != MVT::v4i16) 3440 return 0; 3441 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 3442 return fastEmitInst_r(AArch64::FCVTZSv4f16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 3443 } 3444 return 0; 3445} 3446 3447unsigned fastEmit_ISD_FP_TO_SINT_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3448 if (RetVT.SimpleTy != MVT::v8i16) 3449 return 0; 3450 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 3451 return fastEmitInst_r(AArch64::FCVTZSv8f16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 3452 } 3453 return 0; 3454} 3455 3456unsigned fastEmit_ISD_FP_TO_SINT_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3457 if (RetVT.SimpleTy != MVT::v2i32) 3458 return 0; 3459 if ((Subtarget->hasNEON())) { 3460 return fastEmitInst_r(AArch64::FCVTZSv2f32, &AArch64::FPR64RegClass, Op0, Op0IsKill); 3461 } 3462 return 0; 3463} 3464 3465unsigned fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3466 if (RetVT.SimpleTy != MVT::v4i32) 3467 return 0; 3468 if ((Subtarget->hasNEON())) { 3469 return fastEmitInst_r(AArch64::FCVTZSv4f32, &AArch64::FPR128RegClass, Op0, Op0IsKill); 3470 } 3471 return 0; 3472} 3473 3474unsigned fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3475 if (RetVT.SimpleTy != MVT::v2i64) 3476 return 0; 3477 if ((Subtarget->hasNEON())) { 3478 return fastEmitInst_r(AArch64::FCVTZSv2f64, &AArch64::FPR128RegClass, Op0, Op0IsKill); 3479 } 3480 return 0; 3481} 3482 3483unsigned fastEmit_ISD_FP_TO_SINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 3484 switch (VT.SimpleTy) { 3485 case MVT::f16: return fastEmit_ISD_FP_TO_SINT_MVT_f16_r(RetVT, Op0, Op0IsKill); 3486 case MVT::f32: return fastEmit_ISD_FP_TO_SINT_MVT_f32_r(RetVT, Op0, Op0IsKill); 3487 case MVT::f64: return fastEmit_ISD_FP_TO_SINT_MVT_f64_r(RetVT, Op0, Op0IsKill); 3488 case MVT::v4f16: return fastEmit_ISD_FP_TO_SINT_MVT_v4f16_r(RetVT, Op0, Op0IsKill); 3489 case MVT::v8f16: return fastEmit_ISD_FP_TO_SINT_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 3490 case MVT::v2f32: return fastEmit_ISD_FP_TO_SINT_MVT_v2f32_r(RetVT, Op0, Op0IsKill); 3491 case MVT::v4f32: return fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 3492 case MVT::v2f64: return fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(RetVT, Op0, Op0IsKill); 3493 default: return 0; 3494 } 3495} 3496 3497// FastEmit functions for ISD::FP_TO_UINT. 3498 3499unsigned fastEmit_ISD_FP_TO_UINT_MVT_f16_MVT_i32_r(unsigned Op0, bool Op0IsKill) { 3500 if ((Subtarget->hasFullFP16())) { 3501 return fastEmitInst_r(AArch64::FCVTZUUWHr, &AArch64::GPR32RegClass, Op0, Op0IsKill); 3502 } 3503 return 0; 3504} 3505 3506unsigned fastEmit_ISD_FP_TO_UINT_MVT_f16_MVT_i64_r(unsigned Op0, bool Op0IsKill) { 3507 if ((Subtarget->hasFullFP16())) { 3508 return fastEmitInst_r(AArch64::FCVTZUUXHr, &AArch64::GPR64RegClass, Op0, Op0IsKill); 3509 } 3510 return 0; 3511} 3512 3513unsigned fastEmit_ISD_FP_TO_UINT_MVT_f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3514switch (RetVT.SimpleTy) { 3515 case MVT::i32: return fastEmit_ISD_FP_TO_UINT_MVT_f16_MVT_i32_r(Op0, Op0IsKill); 3516 case MVT::i64: return fastEmit_ISD_FP_TO_UINT_MVT_f16_MVT_i64_r(Op0, Op0IsKill); 3517 default: return 0; 3518} 3519} 3520 3521unsigned fastEmit_ISD_FP_TO_UINT_MVT_f32_MVT_i32_r(unsigned Op0, bool Op0IsKill) { 3522 if ((Subtarget->hasFPARMv8())) { 3523 return fastEmitInst_r(AArch64::FCVTZUUWSr, &AArch64::GPR32RegClass, Op0, Op0IsKill); 3524 } 3525 return 0; 3526} 3527 3528unsigned fastEmit_ISD_FP_TO_UINT_MVT_f32_MVT_i64_r(unsigned Op0, bool Op0IsKill) { 3529 if ((Subtarget->hasFPARMv8())) { 3530 return fastEmitInst_r(AArch64::FCVTZUUXSr, &AArch64::GPR64RegClass, Op0, Op0IsKill); 3531 } 3532 return 0; 3533} 3534 3535unsigned fastEmit_ISD_FP_TO_UINT_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3536switch (RetVT.SimpleTy) { 3537 case MVT::i32: return fastEmit_ISD_FP_TO_UINT_MVT_f32_MVT_i32_r(Op0, Op0IsKill); 3538 case MVT::i64: return fastEmit_ISD_FP_TO_UINT_MVT_f32_MVT_i64_r(Op0, Op0IsKill); 3539 default: return 0; 3540} 3541} 3542 3543unsigned fastEmit_ISD_FP_TO_UINT_MVT_f64_MVT_i32_r(unsigned Op0, bool Op0IsKill) { 3544 if ((Subtarget->hasFPARMv8())) { 3545 return fastEmitInst_r(AArch64::FCVTZUUWDr, &AArch64::GPR32RegClass, Op0, Op0IsKill); 3546 } 3547 return 0; 3548} 3549 3550unsigned fastEmit_ISD_FP_TO_UINT_MVT_f64_MVT_i64_r(unsigned Op0, bool Op0IsKill) { 3551 if ((Subtarget->hasFPARMv8())) { 3552 return fastEmitInst_r(AArch64::FCVTZUUXDr, &AArch64::GPR64RegClass, Op0, Op0IsKill); 3553 } 3554 return 0; 3555} 3556 3557unsigned fastEmit_ISD_FP_TO_UINT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3558switch (RetVT.SimpleTy) { 3559 case MVT::i32: return fastEmit_ISD_FP_TO_UINT_MVT_f64_MVT_i32_r(Op0, Op0IsKill); 3560 case MVT::i64: return fastEmit_ISD_FP_TO_UINT_MVT_f64_MVT_i64_r(Op0, Op0IsKill); 3561 default: return 0; 3562} 3563} 3564 3565unsigned fastEmit_ISD_FP_TO_UINT_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3566 if (RetVT.SimpleTy != MVT::v4i16) 3567 return 0; 3568 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 3569 return fastEmitInst_r(AArch64::FCVTZUv4f16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 3570 } 3571 return 0; 3572} 3573 3574unsigned fastEmit_ISD_FP_TO_UINT_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3575 if (RetVT.SimpleTy != MVT::v8i16) 3576 return 0; 3577 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 3578 return fastEmitInst_r(AArch64::FCVTZUv8f16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 3579 } 3580 return 0; 3581} 3582 3583unsigned fastEmit_ISD_FP_TO_UINT_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3584 if (RetVT.SimpleTy != MVT::v2i32) 3585 return 0; 3586 if ((Subtarget->hasNEON())) { 3587 return fastEmitInst_r(AArch64::FCVTZUv2f32, &AArch64::FPR64RegClass, Op0, Op0IsKill); 3588 } 3589 return 0; 3590} 3591 3592unsigned fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3593 if (RetVT.SimpleTy != MVT::v4i32) 3594 return 0; 3595 if ((Subtarget->hasNEON())) { 3596 return fastEmitInst_r(AArch64::FCVTZUv4f32, &AArch64::FPR128RegClass, Op0, Op0IsKill); 3597 } 3598 return 0; 3599} 3600 3601unsigned fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3602 if (RetVT.SimpleTy != MVT::v2i64) 3603 return 0; 3604 if ((Subtarget->hasNEON())) { 3605 return fastEmitInst_r(AArch64::FCVTZUv2f64, &AArch64::FPR128RegClass, Op0, Op0IsKill); 3606 } 3607 return 0; 3608} 3609 3610unsigned fastEmit_ISD_FP_TO_UINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 3611 switch (VT.SimpleTy) { 3612 case MVT::f16: return fastEmit_ISD_FP_TO_UINT_MVT_f16_r(RetVT, Op0, Op0IsKill); 3613 case MVT::f32: return fastEmit_ISD_FP_TO_UINT_MVT_f32_r(RetVT, Op0, Op0IsKill); 3614 case MVT::f64: return fastEmit_ISD_FP_TO_UINT_MVT_f64_r(RetVT, Op0, Op0IsKill); 3615 case MVT::v4f16: return fastEmit_ISD_FP_TO_UINT_MVT_v4f16_r(RetVT, Op0, Op0IsKill); 3616 case MVT::v8f16: return fastEmit_ISD_FP_TO_UINT_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 3617 case MVT::v2f32: return fastEmit_ISD_FP_TO_UINT_MVT_v2f32_r(RetVT, Op0, Op0IsKill); 3618 case MVT::v4f32: return fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 3619 case MVT::v2f64: return fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(RetVT, Op0, Op0IsKill); 3620 default: return 0; 3621 } 3622} 3623 3624// FastEmit functions for ISD::FRINT. 3625 3626unsigned fastEmit_ISD_FRINT_MVT_f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3627 if (RetVT.SimpleTy != MVT::f16) 3628 return 0; 3629 if ((Subtarget->hasFullFP16())) { 3630 return fastEmitInst_r(AArch64::FRINTXHr, &AArch64::FPR16RegClass, Op0, Op0IsKill); 3631 } 3632 return 0; 3633} 3634 3635unsigned fastEmit_ISD_FRINT_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3636 if (RetVT.SimpleTy != MVT::f32) 3637 return 0; 3638 if ((Subtarget->hasFPARMv8())) { 3639 return fastEmitInst_r(AArch64::FRINTXSr, &AArch64::FPR32RegClass, Op0, Op0IsKill); 3640 } 3641 return 0; 3642} 3643 3644unsigned fastEmit_ISD_FRINT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3645 if (RetVT.SimpleTy != MVT::f64) 3646 return 0; 3647 if ((Subtarget->hasFPARMv8())) { 3648 return fastEmitInst_r(AArch64::FRINTXDr, &AArch64::FPR64RegClass, Op0, Op0IsKill); 3649 } 3650 return 0; 3651} 3652 3653unsigned fastEmit_ISD_FRINT_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3654 if (RetVT.SimpleTy != MVT::v4f16) 3655 return 0; 3656 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 3657 return fastEmitInst_r(AArch64::FRINTXv4f16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 3658 } 3659 return 0; 3660} 3661 3662unsigned fastEmit_ISD_FRINT_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3663 if (RetVT.SimpleTy != MVT::v8f16) 3664 return 0; 3665 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 3666 return fastEmitInst_r(AArch64::FRINTXv8f16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 3667 } 3668 return 0; 3669} 3670 3671unsigned fastEmit_ISD_FRINT_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3672 if (RetVT.SimpleTy != MVT::v2f32) 3673 return 0; 3674 if ((Subtarget->hasNEON())) { 3675 return fastEmitInst_r(AArch64::FRINTXv2f32, &AArch64::FPR64RegClass, Op0, Op0IsKill); 3676 } 3677 return 0; 3678} 3679 3680unsigned fastEmit_ISD_FRINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3681 if (RetVT.SimpleTy != MVT::v4f32) 3682 return 0; 3683 if ((Subtarget->hasNEON())) { 3684 return fastEmitInst_r(AArch64::FRINTXv4f32, &AArch64::FPR128RegClass, Op0, Op0IsKill); 3685 } 3686 return 0; 3687} 3688 3689unsigned fastEmit_ISD_FRINT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3690 if (RetVT.SimpleTy != MVT::v2f64) 3691 return 0; 3692 if ((Subtarget->hasNEON())) { 3693 return fastEmitInst_r(AArch64::FRINTXv2f64, &AArch64::FPR128RegClass, Op0, Op0IsKill); 3694 } 3695 return 0; 3696} 3697 3698unsigned fastEmit_ISD_FRINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 3699 switch (VT.SimpleTy) { 3700 case MVT::f16: return fastEmit_ISD_FRINT_MVT_f16_r(RetVT, Op0, Op0IsKill); 3701 case MVT::f32: return fastEmit_ISD_FRINT_MVT_f32_r(RetVT, Op0, Op0IsKill); 3702 case MVT::f64: return fastEmit_ISD_FRINT_MVT_f64_r(RetVT, Op0, Op0IsKill); 3703 case MVT::v4f16: return fastEmit_ISD_FRINT_MVT_v4f16_r(RetVT, Op0, Op0IsKill); 3704 case MVT::v8f16: return fastEmit_ISD_FRINT_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 3705 case MVT::v2f32: return fastEmit_ISD_FRINT_MVT_v2f32_r(RetVT, Op0, Op0IsKill); 3706 case MVT::v4f32: return fastEmit_ISD_FRINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 3707 case MVT::v2f64: return fastEmit_ISD_FRINT_MVT_v2f64_r(RetVT, Op0, Op0IsKill); 3708 default: return 0; 3709 } 3710} 3711 3712// FastEmit functions for ISD::FROUND. 3713 3714unsigned fastEmit_ISD_FROUND_MVT_f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3715 if (RetVT.SimpleTy != MVT::f16) 3716 return 0; 3717 if ((Subtarget->hasFullFP16())) { 3718 return fastEmitInst_r(AArch64::FRINTAHr, &AArch64::FPR16RegClass, Op0, Op0IsKill); 3719 } 3720 return 0; 3721} 3722 3723unsigned fastEmit_ISD_FROUND_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3724 if (RetVT.SimpleTy != MVT::f32) 3725 return 0; 3726 if ((Subtarget->hasFPARMv8())) { 3727 return fastEmitInst_r(AArch64::FRINTASr, &AArch64::FPR32RegClass, Op0, Op0IsKill); 3728 } 3729 return 0; 3730} 3731 3732unsigned fastEmit_ISD_FROUND_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3733 if (RetVT.SimpleTy != MVT::f64) 3734 return 0; 3735 if ((Subtarget->hasFPARMv8())) { 3736 return fastEmitInst_r(AArch64::FRINTADr, &AArch64::FPR64RegClass, Op0, Op0IsKill); 3737 } 3738 return 0; 3739} 3740 3741unsigned fastEmit_ISD_FROUND_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3742 if (RetVT.SimpleTy != MVT::v4f16) 3743 return 0; 3744 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 3745 return fastEmitInst_r(AArch64::FRINTAv4f16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 3746 } 3747 return 0; 3748} 3749 3750unsigned fastEmit_ISD_FROUND_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3751 if (RetVT.SimpleTy != MVT::v8f16) 3752 return 0; 3753 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 3754 return fastEmitInst_r(AArch64::FRINTAv8f16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 3755 } 3756 return 0; 3757} 3758 3759unsigned fastEmit_ISD_FROUND_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3760 if (RetVT.SimpleTy != MVT::v2f32) 3761 return 0; 3762 if ((Subtarget->hasNEON())) { 3763 return fastEmitInst_r(AArch64::FRINTAv2f32, &AArch64::FPR64RegClass, Op0, Op0IsKill); 3764 } 3765 return 0; 3766} 3767 3768unsigned fastEmit_ISD_FROUND_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3769 if (RetVT.SimpleTy != MVT::v4f32) 3770 return 0; 3771 if ((Subtarget->hasNEON())) { 3772 return fastEmitInst_r(AArch64::FRINTAv4f32, &AArch64::FPR128RegClass, Op0, Op0IsKill); 3773 } 3774 return 0; 3775} 3776 3777unsigned fastEmit_ISD_FROUND_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3778 if (RetVT.SimpleTy != MVT::v2f64) 3779 return 0; 3780 if ((Subtarget->hasNEON())) { 3781 return fastEmitInst_r(AArch64::FRINTAv2f64, &AArch64::FPR128RegClass, Op0, Op0IsKill); 3782 } 3783 return 0; 3784} 3785 3786unsigned fastEmit_ISD_FROUND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 3787 switch (VT.SimpleTy) { 3788 case MVT::f16: return fastEmit_ISD_FROUND_MVT_f16_r(RetVT, Op0, Op0IsKill); 3789 case MVT::f32: return fastEmit_ISD_FROUND_MVT_f32_r(RetVT, Op0, Op0IsKill); 3790 case MVT::f64: return fastEmit_ISD_FROUND_MVT_f64_r(RetVT, Op0, Op0IsKill); 3791 case MVT::v4f16: return fastEmit_ISD_FROUND_MVT_v4f16_r(RetVT, Op0, Op0IsKill); 3792 case MVT::v8f16: return fastEmit_ISD_FROUND_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 3793 case MVT::v2f32: return fastEmit_ISD_FROUND_MVT_v2f32_r(RetVT, Op0, Op0IsKill); 3794 case MVT::v4f32: return fastEmit_ISD_FROUND_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 3795 case MVT::v2f64: return fastEmit_ISD_FROUND_MVT_v2f64_r(RetVT, Op0, Op0IsKill); 3796 default: return 0; 3797 } 3798} 3799 3800// FastEmit functions for ISD::FSQRT. 3801 3802unsigned fastEmit_ISD_FSQRT_MVT_f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3803 if (RetVT.SimpleTy != MVT::f16) 3804 return 0; 3805 if ((Subtarget->hasFullFP16())) { 3806 return fastEmitInst_r(AArch64::FSQRTHr, &AArch64::FPR16RegClass, Op0, Op0IsKill); 3807 } 3808 return 0; 3809} 3810 3811unsigned fastEmit_ISD_FSQRT_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3812 if (RetVT.SimpleTy != MVT::f32) 3813 return 0; 3814 if ((Subtarget->hasFPARMv8())) { 3815 return fastEmitInst_r(AArch64::FSQRTSr, &AArch64::FPR32RegClass, Op0, Op0IsKill); 3816 } 3817 return 0; 3818} 3819 3820unsigned fastEmit_ISD_FSQRT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3821 if (RetVT.SimpleTy != MVT::f64) 3822 return 0; 3823 if ((Subtarget->hasFPARMv8())) { 3824 return fastEmitInst_r(AArch64::FSQRTDr, &AArch64::FPR64RegClass, Op0, Op0IsKill); 3825 } 3826 return 0; 3827} 3828 3829unsigned fastEmit_ISD_FSQRT_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3830 if (RetVT.SimpleTy != MVT::v4f16) 3831 return 0; 3832 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 3833 return fastEmitInst_r(AArch64::FSQRTv4f16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 3834 } 3835 return 0; 3836} 3837 3838unsigned fastEmit_ISD_FSQRT_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3839 if (RetVT.SimpleTy != MVT::v8f16) 3840 return 0; 3841 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 3842 return fastEmitInst_r(AArch64::FSQRTv8f16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 3843 } 3844 return 0; 3845} 3846 3847unsigned fastEmit_ISD_FSQRT_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3848 if (RetVT.SimpleTy != MVT::v2f32) 3849 return 0; 3850 if ((Subtarget->hasNEON())) { 3851 return fastEmitInst_r(AArch64::FSQRTv2f32, &AArch64::FPR64RegClass, Op0, Op0IsKill); 3852 } 3853 return 0; 3854} 3855 3856unsigned fastEmit_ISD_FSQRT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3857 if (RetVT.SimpleTy != MVT::v4f32) 3858 return 0; 3859 if ((Subtarget->hasNEON())) { 3860 return fastEmitInst_r(AArch64::FSQRTv4f32, &AArch64::FPR128RegClass, Op0, Op0IsKill); 3861 } 3862 return 0; 3863} 3864 3865unsigned fastEmit_ISD_FSQRT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3866 if (RetVT.SimpleTy != MVT::v2f64) 3867 return 0; 3868 if ((Subtarget->hasNEON())) { 3869 return fastEmitInst_r(AArch64::FSQRTv2f64, &AArch64::FPR128RegClass, Op0, Op0IsKill); 3870 } 3871 return 0; 3872} 3873 3874unsigned fastEmit_ISD_FSQRT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 3875 switch (VT.SimpleTy) { 3876 case MVT::f16: return fastEmit_ISD_FSQRT_MVT_f16_r(RetVT, Op0, Op0IsKill); 3877 case MVT::f32: return fastEmit_ISD_FSQRT_MVT_f32_r(RetVT, Op0, Op0IsKill); 3878 case MVT::f64: return fastEmit_ISD_FSQRT_MVT_f64_r(RetVT, Op0, Op0IsKill); 3879 case MVT::v4f16: return fastEmit_ISD_FSQRT_MVT_v4f16_r(RetVT, Op0, Op0IsKill); 3880 case MVT::v8f16: return fastEmit_ISD_FSQRT_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 3881 case MVT::v2f32: return fastEmit_ISD_FSQRT_MVT_v2f32_r(RetVT, Op0, Op0IsKill); 3882 case MVT::v4f32: return fastEmit_ISD_FSQRT_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 3883 case MVT::v2f64: return fastEmit_ISD_FSQRT_MVT_v2f64_r(RetVT, Op0, Op0IsKill); 3884 default: return 0; 3885 } 3886} 3887 3888// FastEmit functions for ISD::FTRUNC. 3889 3890unsigned fastEmit_ISD_FTRUNC_MVT_f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3891 if (RetVT.SimpleTy != MVT::f16) 3892 return 0; 3893 if ((Subtarget->hasFullFP16())) { 3894 return fastEmitInst_r(AArch64::FRINTZHr, &AArch64::FPR16RegClass, Op0, Op0IsKill); 3895 } 3896 return 0; 3897} 3898 3899unsigned fastEmit_ISD_FTRUNC_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3900 if (RetVT.SimpleTy != MVT::f32) 3901 return 0; 3902 if ((Subtarget->hasFPARMv8())) { 3903 return fastEmitInst_r(AArch64::FRINTZSr, &AArch64::FPR32RegClass, Op0, Op0IsKill); 3904 } 3905 return 0; 3906} 3907 3908unsigned fastEmit_ISD_FTRUNC_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3909 if (RetVT.SimpleTy != MVT::f64) 3910 return 0; 3911 if ((Subtarget->hasFPARMv8())) { 3912 return fastEmitInst_r(AArch64::FRINTZDr, &AArch64::FPR64RegClass, Op0, Op0IsKill); 3913 } 3914 return 0; 3915} 3916 3917unsigned fastEmit_ISD_FTRUNC_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3918 if (RetVT.SimpleTy != MVT::v4f16) 3919 return 0; 3920 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 3921 return fastEmitInst_r(AArch64::FRINTZv4f16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 3922 } 3923 return 0; 3924} 3925 3926unsigned fastEmit_ISD_FTRUNC_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3927 if (RetVT.SimpleTy != MVT::v8f16) 3928 return 0; 3929 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 3930 return fastEmitInst_r(AArch64::FRINTZv8f16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 3931 } 3932 return 0; 3933} 3934 3935unsigned fastEmit_ISD_FTRUNC_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3936 if (RetVT.SimpleTy != MVT::v2f32) 3937 return 0; 3938 if ((Subtarget->hasNEON())) { 3939 return fastEmitInst_r(AArch64::FRINTZv2f32, &AArch64::FPR64RegClass, Op0, Op0IsKill); 3940 } 3941 return 0; 3942} 3943 3944unsigned fastEmit_ISD_FTRUNC_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3945 if (RetVT.SimpleTy != MVT::v4f32) 3946 return 0; 3947 if ((Subtarget->hasNEON())) { 3948 return fastEmitInst_r(AArch64::FRINTZv4f32, &AArch64::FPR128RegClass, Op0, Op0IsKill); 3949 } 3950 return 0; 3951} 3952 3953unsigned fastEmit_ISD_FTRUNC_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3954 if (RetVT.SimpleTy != MVT::v2f64) 3955 return 0; 3956 if ((Subtarget->hasNEON())) { 3957 return fastEmitInst_r(AArch64::FRINTZv2f64, &AArch64::FPR128RegClass, Op0, Op0IsKill); 3958 } 3959 return 0; 3960} 3961 3962unsigned fastEmit_ISD_FTRUNC_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 3963 switch (VT.SimpleTy) { 3964 case MVT::f16: return fastEmit_ISD_FTRUNC_MVT_f16_r(RetVT, Op0, Op0IsKill); 3965 case MVT::f32: return fastEmit_ISD_FTRUNC_MVT_f32_r(RetVT, Op0, Op0IsKill); 3966 case MVT::f64: return fastEmit_ISD_FTRUNC_MVT_f64_r(RetVT, Op0, Op0IsKill); 3967 case MVT::v4f16: return fastEmit_ISD_FTRUNC_MVT_v4f16_r(RetVT, Op0, Op0IsKill); 3968 case MVT::v8f16: return fastEmit_ISD_FTRUNC_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 3969 case MVT::v2f32: return fastEmit_ISD_FTRUNC_MVT_v2f32_r(RetVT, Op0, Op0IsKill); 3970 case MVT::v4f32: return fastEmit_ISD_FTRUNC_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 3971 case MVT::v2f64: return fastEmit_ISD_FTRUNC_MVT_v2f64_r(RetVT, Op0, Op0IsKill); 3972 default: return 0; 3973 } 3974} 3975 3976// FastEmit functions for ISD::LLROUND. 3977 3978unsigned fastEmit_ISD_LLROUND_MVT_f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3979 if (RetVT.SimpleTy != MVT::i64) 3980 return 0; 3981 if ((Subtarget->hasFullFP16())) { 3982 return fastEmitInst_r(AArch64::FCVTASUXHr, &AArch64::GPR64RegClass, Op0, Op0IsKill); 3983 } 3984 return 0; 3985} 3986 3987unsigned fastEmit_ISD_LLROUND_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3988 if (RetVT.SimpleTy != MVT::i64) 3989 return 0; 3990 return fastEmitInst_r(AArch64::FCVTASUXSr, &AArch64::GPR64RegClass, Op0, Op0IsKill); 3991} 3992 3993unsigned fastEmit_ISD_LLROUND_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3994 if (RetVT.SimpleTy != MVT::i64) 3995 return 0; 3996 return fastEmitInst_r(AArch64::FCVTASUXDr, &AArch64::GPR64RegClass, Op0, Op0IsKill); 3997} 3998 3999unsigned fastEmit_ISD_LLROUND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 4000 switch (VT.SimpleTy) { 4001 case MVT::f16: return fastEmit_ISD_LLROUND_MVT_f16_r(RetVT, Op0, Op0IsKill); 4002 case MVT::f32: return fastEmit_ISD_LLROUND_MVT_f32_r(RetVT, Op0, Op0IsKill); 4003 case MVT::f64: return fastEmit_ISD_LLROUND_MVT_f64_r(RetVT, Op0, Op0IsKill); 4004 default: return 0; 4005 } 4006} 4007 4008// FastEmit functions for ISD::LROUND. 4009 4010unsigned fastEmit_ISD_LROUND_MVT_f16_MVT_i32_r(unsigned Op0, bool Op0IsKill) { 4011 if ((Subtarget->hasFullFP16())) { 4012 return fastEmitInst_r(AArch64::FCVTASUWHr, &AArch64::GPR32RegClass, Op0, Op0IsKill); 4013 } 4014 return 0; 4015} 4016 4017unsigned fastEmit_ISD_LROUND_MVT_f16_MVT_i64_r(unsigned Op0, bool Op0IsKill) { 4018 if ((Subtarget->hasFullFP16())) { 4019 return fastEmitInst_r(AArch64::FCVTASUXHr, &AArch64::GPR64RegClass, Op0, Op0IsKill); 4020 } 4021 return 0; 4022} 4023 4024unsigned fastEmit_ISD_LROUND_MVT_f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 4025switch (RetVT.SimpleTy) { 4026 case MVT::i32: return fastEmit_ISD_LROUND_MVT_f16_MVT_i32_r(Op0, Op0IsKill); 4027 case MVT::i64: return fastEmit_ISD_LROUND_MVT_f16_MVT_i64_r(Op0, Op0IsKill); 4028 default: return 0; 4029} 4030} 4031 4032unsigned fastEmit_ISD_LROUND_MVT_f32_MVT_i32_r(unsigned Op0, bool Op0IsKill) { 4033 return fastEmitInst_r(AArch64::FCVTASUWSr, &AArch64::GPR32RegClass, Op0, Op0IsKill); 4034} 4035 4036unsigned fastEmit_ISD_LROUND_MVT_f32_MVT_i64_r(unsigned Op0, bool Op0IsKill) { 4037 return fastEmitInst_r(AArch64::FCVTASUXSr, &AArch64::GPR64RegClass, Op0, Op0IsKill); 4038} 4039 4040unsigned fastEmit_ISD_LROUND_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 4041switch (RetVT.SimpleTy) { 4042 case MVT::i32: return fastEmit_ISD_LROUND_MVT_f32_MVT_i32_r(Op0, Op0IsKill); 4043 case MVT::i64: return fastEmit_ISD_LROUND_MVT_f32_MVT_i64_r(Op0, Op0IsKill); 4044 default: return 0; 4045} 4046} 4047 4048unsigned fastEmit_ISD_LROUND_MVT_f64_MVT_i32_r(unsigned Op0, bool Op0IsKill) { 4049 return fastEmitInst_r(AArch64::FCVTASUWDr, &AArch64::GPR32RegClass, Op0, Op0IsKill); 4050} 4051 4052unsigned fastEmit_ISD_LROUND_MVT_f64_MVT_i64_r(unsigned Op0, bool Op0IsKill) { 4053 return fastEmitInst_r(AArch64::FCVTASUXDr, &AArch64::GPR64RegClass, Op0, Op0IsKill); 4054} 4055 4056unsigned fastEmit_ISD_LROUND_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 4057switch (RetVT.SimpleTy) { 4058 case MVT::i32: return fastEmit_ISD_LROUND_MVT_f64_MVT_i32_r(Op0, Op0IsKill); 4059 case MVT::i64: return fastEmit_ISD_LROUND_MVT_f64_MVT_i64_r(Op0, Op0IsKill); 4060 default: return 0; 4061} 4062} 4063 4064unsigned fastEmit_ISD_LROUND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 4065 switch (VT.SimpleTy) { 4066 case MVT::f16: return fastEmit_ISD_LROUND_MVT_f16_r(RetVT, Op0, Op0IsKill); 4067 case MVT::f32: return fastEmit_ISD_LROUND_MVT_f32_r(RetVT, Op0, Op0IsKill); 4068 case MVT::f64: return fastEmit_ISD_LROUND_MVT_f64_r(RetVT, Op0, Op0IsKill); 4069 default: return 0; 4070 } 4071} 4072 4073// FastEmit functions for ISD::SINT_TO_FP. 4074 4075unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f16_r(unsigned Op0, bool Op0IsKill) { 4076 if ((Subtarget->hasFullFP16())) { 4077 return fastEmitInst_r(AArch64::SCVTFUWHri, &AArch64::FPR16RegClass, Op0, Op0IsKill); 4078 } 4079 return 0; 4080} 4081 4082unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(unsigned Op0, bool Op0IsKill) { 4083 if ((Subtarget->hasFPARMv8())) { 4084 return fastEmitInst_r(AArch64::SCVTFUWSri, &AArch64::FPR32RegClass, Op0, Op0IsKill); 4085 } 4086 return 0; 4087} 4088 4089unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(unsigned Op0, bool Op0IsKill) { 4090 if ((Subtarget->hasFPARMv8())) { 4091 return fastEmitInst_r(AArch64::SCVTFUWDri, &AArch64::FPR64RegClass, Op0, Op0IsKill); 4092 } 4093 return 0; 4094} 4095 4096unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 4097switch (RetVT.SimpleTy) { 4098 case MVT::f16: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f16_r(Op0, Op0IsKill); 4099 case MVT::f32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(Op0, Op0IsKill); 4100 case MVT::f64: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(Op0, Op0IsKill); 4101 default: return 0; 4102} 4103} 4104 4105unsigned fastEmit_ISD_SINT_TO_FP_MVT_i64_MVT_f16_r(unsigned Op0, bool Op0IsKill) { 4106 if ((Subtarget->hasFullFP16())) { 4107 return fastEmitInst_r(AArch64::SCVTFUXHri, &AArch64::FPR16RegClass, Op0, Op0IsKill); 4108 } 4109 return 0; 4110} 4111 4112unsigned fastEmit_ISD_SINT_TO_FP_MVT_i64_MVT_f32_r(unsigned Op0, bool Op0IsKill) { 4113 if ((Subtarget->hasFPARMv8())) { 4114 return fastEmitInst_r(AArch64::SCVTFUXSri, &AArch64::FPR32RegClass, Op0, Op0IsKill); 4115 } 4116 return 0; 4117} 4118 4119unsigned fastEmit_ISD_SINT_TO_FP_MVT_i64_MVT_f64_r(unsigned Op0, bool Op0IsKill) { 4120 if ((Subtarget->hasFPARMv8())) { 4121 return fastEmitInst_r(AArch64::SCVTFUXDri, &AArch64::FPR64RegClass, Op0, Op0IsKill); 4122 } 4123 return 0; 4124} 4125 4126unsigned fastEmit_ISD_SINT_TO_FP_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 4127switch (RetVT.SimpleTy) { 4128 case MVT::f16: return fastEmit_ISD_SINT_TO_FP_MVT_i64_MVT_f16_r(Op0, Op0IsKill); 4129 case MVT::f32: return fastEmit_ISD_SINT_TO_FP_MVT_i64_MVT_f32_r(Op0, Op0IsKill); 4130 case MVT::f64: return fastEmit_ISD_SINT_TO_FP_MVT_i64_MVT_f64_r(Op0, Op0IsKill); 4131 default: return 0; 4132} 4133} 4134 4135unsigned fastEmit_ISD_SINT_TO_FP_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 4136 if (RetVT.SimpleTy != MVT::v4f16) 4137 return 0; 4138 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 4139 return fastEmitInst_r(AArch64::SCVTFv4f16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 4140 } 4141 return 0; 4142} 4143 4144unsigned fastEmit_ISD_SINT_TO_FP_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 4145 if (RetVT.SimpleTy != MVT::v8f16) 4146 return 0; 4147 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 4148 return fastEmitInst_r(AArch64::SCVTFv8f16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 4149 } 4150 return 0; 4151} 4152 4153unsigned fastEmit_ISD_SINT_TO_FP_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 4154 if (RetVT.SimpleTy != MVT::v2f32) 4155 return 0; 4156 if ((Subtarget->hasNEON())) { 4157 return fastEmitInst_r(AArch64::SCVTFv2f32, &AArch64::FPR64RegClass, Op0, Op0IsKill); 4158 } 4159 return 0; 4160} 4161 4162unsigned fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 4163 if (RetVT.SimpleTy != MVT::v4f32) 4164 return 0; 4165 if ((Subtarget->hasNEON())) { 4166 return fastEmitInst_r(AArch64::SCVTFv4f32, &AArch64::FPR128RegClass, Op0, Op0IsKill); 4167 } 4168 return 0; 4169} 4170 4171unsigned fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 4172 if (RetVT.SimpleTy != MVT::v2f64) 4173 return 0; 4174 if ((Subtarget->hasNEON())) { 4175 return fastEmitInst_r(AArch64::SCVTFv2f64, &AArch64::FPR128RegClass, Op0, Op0IsKill); 4176 } 4177 return 0; 4178} 4179 4180unsigned fastEmit_ISD_SINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 4181 switch (VT.SimpleTy) { 4182 case MVT::i32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_r(RetVT, Op0, Op0IsKill); 4183 case MVT::i64: return fastEmit_ISD_SINT_TO_FP_MVT_i64_r(RetVT, Op0, Op0IsKill); 4184 case MVT::v4i16: return fastEmit_ISD_SINT_TO_FP_MVT_v4i16_r(RetVT, Op0, Op0IsKill); 4185 case MVT::v8i16: return fastEmit_ISD_SINT_TO_FP_MVT_v8i16_r(RetVT, Op0, Op0IsKill); 4186 case MVT::v2i32: return fastEmit_ISD_SINT_TO_FP_MVT_v2i32_r(RetVT, Op0, Op0IsKill); 4187 case MVT::v4i32: return fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(RetVT, Op0, Op0IsKill); 4188 case MVT::v2i64: return fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(RetVT, Op0, Op0IsKill); 4189 default: return 0; 4190 } 4191} 4192 4193// FastEmit functions for ISD::STRICT_FP_ROUND. 4194 4195unsigned fastEmit_ISD_STRICT_FP_ROUND_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 4196 if (RetVT.SimpleTy != MVT::f16) 4197 return 0; 4198 if ((Subtarget->hasFPARMv8())) { 4199 return fastEmitInst_r(AArch64::FCVTHSr, &AArch64::FPR16RegClass, Op0, Op0IsKill); 4200 } 4201 return 0; 4202} 4203 4204unsigned fastEmit_ISD_STRICT_FP_ROUND_MVT_f64_MVT_f16_r(unsigned Op0, bool Op0IsKill) { 4205 if ((Subtarget->hasFPARMv8())) { 4206 return fastEmitInst_r(AArch64::FCVTHDr, &AArch64::FPR16RegClass, Op0, Op0IsKill); 4207 } 4208 return 0; 4209} 4210 4211unsigned fastEmit_ISD_STRICT_FP_ROUND_MVT_f64_MVT_f32_r(unsigned Op0, bool Op0IsKill) { 4212 if ((Subtarget->hasFPARMv8())) { 4213 return fastEmitInst_r(AArch64::FCVTSDr, &AArch64::FPR32RegClass, Op0, Op0IsKill); 4214 } 4215 return 0; 4216} 4217 4218unsigned fastEmit_ISD_STRICT_FP_ROUND_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 4219switch (RetVT.SimpleTy) { 4220 case MVT::f16: return fastEmit_ISD_STRICT_FP_ROUND_MVT_f64_MVT_f16_r(Op0, Op0IsKill); 4221 case MVT::f32: return fastEmit_ISD_STRICT_FP_ROUND_MVT_f64_MVT_f32_r(Op0, Op0IsKill); 4222 default: return 0; 4223} 4224} 4225 4226unsigned fastEmit_ISD_STRICT_FP_ROUND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 4227 switch (VT.SimpleTy) { 4228 case MVT::f32: return fastEmit_ISD_STRICT_FP_ROUND_MVT_f32_r(RetVT, Op0, Op0IsKill); 4229 case MVT::f64: return fastEmit_ISD_STRICT_FP_ROUND_MVT_f64_r(RetVT, Op0, Op0IsKill); 4230 default: return 0; 4231 } 4232} 4233 4234// FastEmit functions for ISD::STRICT_FP_TO_SINT. 4235 4236unsigned fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f16_MVT_i32_r(unsigned Op0, bool Op0IsKill) { 4237 if ((Subtarget->hasFullFP16())) { 4238 return fastEmitInst_r(AArch64::FCVTZSUWHr, &AArch64::GPR32RegClass, Op0, Op0IsKill); 4239 } 4240 return 0; 4241} 4242 4243unsigned fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f16_MVT_i64_r(unsigned Op0, bool Op0IsKill) { 4244 if ((Subtarget->hasFullFP16())) { 4245 return fastEmitInst_r(AArch64::FCVTZSUXHr, &AArch64::GPR64RegClass, Op0, Op0IsKill); 4246 } 4247 return 0; 4248} 4249 4250unsigned fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 4251switch (RetVT.SimpleTy) { 4252 case MVT::i32: return fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f16_MVT_i32_r(Op0, Op0IsKill); 4253 case MVT::i64: return fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f16_MVT_i64_r(Op0, Op0IsKill); 4254 default: return 0; 4255} 4256} 4257 4258unsigned fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f32_MVT_i32_r(unsigned Op0, bool Op0IsKill) { 4259 if ((Subtarget->hasFPARMv8())) { 4260 return fastEmitInst_r(AArch64::FCVTZSUWSr, &AArch64::GPR32RegClass, Op0, Op0IsKill); 4261 } 4262 return 0; 4263} 4264 4265unsigned fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f32_MVT_i64_r(unsigned Op0, bool Op0IsKill) { 4266 if ((Subtarget->hasFPARMv8())) { 4267 return fastEmitInst_r(AArch64::FCVTZSUXSr, &AArch64::GPR64RegClass, Op0, Op0IsKill); 4268 } 4269 return 0; 4270} 4271 4272unsigned fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 4273switch (RetVT.SimpleTy) { 4274 case MVT::i32: return fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f32_MVT_i32_r(Op0, Op0IsKill); 4275 case MVT::i64: return fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f32_MVT_i64_r(Op0, Op0IsKill); 4276 default: return 0; 4277} 4278} 4279 4280unsigned fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f64_MVT_i32_r(unsigned Op0, bool Op0IsKill) { 4281 if ((Subtarget->hasFPARMv8())) { 4282 return fastEmitInst_r(AArch64::FCVTZSUWDr, &AArch64::GPR32RegClass, Op0, Op0IsKill); 4283 } 4284 return 0; 4285} 4286 4287unsigned fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f64_MVT_i64_r(unsigned Op0, bool Op0IsKill) { 4288 if ((Subtarget->hasFPARMv8())) { 4289 return fastEmitInst_r(AArch64::FCVTZSUXDr, &AArch64::GPR64RegClass, Op0, Op0IsKill); 4290 } 4291 return 0; 4292} 4293 4294unsigned fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 4295switch (RetVT.SimpleTy) { 4296 case MVT::i32: return fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f64_MVT_i32_r(Op0, Op0IsKill); 4297 case MVT::i64: return fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f64_MVT_i64_r(Op0, Op0IsKill); 4298 default: return 0; 4299} 4300} 4301 4302unsigned fastEmit_ISD_STRICT_FP_TO_SINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 4303 switch (VT.SimpleTy) { 4304 case MVT::f16: return fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f16_r(RetVT, Op0, Op0IsKill); 4305 case MVT::f32: return fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f32_r(RetVT, Op0, Op0IsKill); 4306 case MVT::f64: return fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f64_r(RetVT, Op0, Op0IsKill); 4307 default: return 0; 4308 } 4309} 4310 4311// FastEmit functions for ISD::STRICT_FP_TO_UINT. 4312 4313unsigned fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f16_MVT_i32_r(unsigned Op0, bool Op0IsKill) { 4314 if ((Subtarget->hasFullFP16())) { 4315 return fastEmitInst_r(AArch64::FCVTZUUWHr, &AArch64::GPR32RegClass, Op0, Op0IsKill); 4316 } 4317 return 0; 4318} 4319 4320unsigned fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f16_MVT_i64_r(unsigned Op0, bool Op0IsKill) { 4321 if ((Subtarget->hasFullFP16())) { 4322 return fastEmitInst_r(AArch64::FCVTZUUXHr, &AArch64::GPR64RegClass, Op0, Op0IsKill); 4323 } 4324 return 0; 4325} 4326 4327unsigned fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 4328switch (RetVT.SimpleTy) { 4329 case MVT::i32: return fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f16_MVT_i32_r(Op0, Op0IsKill); 4330 case MVT::i64: return fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f16_MVT_i64_r(Op0, Op0IsKill); 4331 default: return 0; 4332} 4333} 4334 4335unsigned fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f32_MVT_i32_r(unsigned Op0, bool Op0IsKill) { 4336 if ((Subtarget->hasFPARMv8())) { 4337 return fastEmitInst_r(AArch64::FCVTZUUWSr, &AArch64::GPR32RegClass, Op0, Op0IsKill); 4338 } 4339 return 0; 4340} 4341 4342unsigned fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f32_MVT_i64_r(unsigned Op0, bool Op0IsKill) { 4343 if ((Subtarget->hasFPARMv8())) { 4344 return fastEmitInst_r(AArch64::FCVTZUUXSr, &AArch64::GPR64RegClass, Op0, Op0IsKill); 4345 } 4346 return 0; 4347} 4348 4349unsigned fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 4350switch (RetVT.SimpleTy) { 4351 case MVT::i32: return fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f32_MVT_i32_r(Op0, Op0IsKill); 4352 case MVT::i64: return fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f32_MVT_i64_r(Op0, Op0IsKill); 4353 default: return 0; 4354} 4355} 4356 4357unsigned fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f64_MVT_i32_r(unsigned Op0, bool Op0IsKill) { 4358 if ((Subtarget->hasFPARMv8())) { 4359 return fastEmitInst_r(AArch64::FCVTZUUWDr, &AArch64::GPR32RegClass, Op0, Op0IsKill); 4360 } 4361 return 0; 4362} 4363 4364unsigned fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f64_MVT_i64_r(unsigned Op0, bool Op0IsKill) { 4365 if ((Subtarget->hasFPARMv8())) { 4366 return fastEmitInst_r(AArch64::FCVTZUUXDr, &AArch64::GPR64RegClass, Op0, Op0IsKill); 4367 } 4368 return 0; 4369} 4370 4371unsigned fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 4372switch (RetVT.SimpleTy) { 4373 case MVT::i32: return fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f64_MVT_i32_r(Op0, Op0IsKill); 4374 case MVT::i64: return fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f64_MVT_i64_r(Op0, Op0IsKill); 4375 default: return 0; 4376} 4377} 4378 4379unsigned fastEmit_ISD_STRICT_FP_TO_UINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 4380 switch (VT.SimpleTy) { 4381 case MVT::f16: return fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f16_r(RetVT, Op0, Op0IsKill); 4382 case MVT::f32: return fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f32_r(RetVT, Op0, Op0IsKill); 4383 case MVT::f64: return fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f64_r(RetVT, Op0, Op0IsKill); 4384 default: return 0; 4385 } 4386} 4387 4388// FastEmit functions for ISD::STRICT_SINT_TO_FP. 4389 4390unsigned fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_MVT_f16_r(unsigned Op0, bool Op0IsKill) { 4391 if ((Subtarget->hasFullFP16())) { 4392 return fastEmitInst_r(AArch64::SCVTFUWHri, &AArch64::FPR16RegClass, Op0, Op0IsKill); 4393 } 4394 return 0; 4395} 4396 4397unsigned fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_MVT_f32_r(unsigned Op0, bool Op0IsKill) { 4398 if ((Subtarget->hasFPARMv8())) { 4399 return fastEmitInst_r(AArch64::SCVTFUWSri, &AArch64::FPR32RegClass, Op0, Op0IsKill); 4400 } 4401 return 0; 4402} 4403 4404unsigned fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_MVT_f64_r(unsigned Op0, bool Op0IsKill) { 4405 if ((Subtarget->hasFPARMv8())) { 4406 return fastEmitInst_r(AArch64::SCVTFUWDri, &AArch64::FPR64RegClass, Op0, Op0IsKill); 4407 } 4408 return 0; 4409} 4410 4411unsigned fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 4412switch (RetVT.SimpleTy) { 4413 case MVT::f16: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_MVT_f16_r(Op0, Op0IsKill); 4414 case MVT::f32: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_MVT_f32_r(Op0, Op0IsKill); 4415 case MVT::f64: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_MVT_f64_r(Op0, Op0IsKill); 4416 default: return 0; 4417} 4418} 4419 4420unsigned fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i64_MVT_f16_r(unsigned Op0, bool Op0IsKill) { 4421 if ((Subtarget->hasFullFP16())) { 4422 return fastEmitInst_r(AArch64::SCVTFUXHri, &AArch64::FPR16RegClass, Op0, Op0IsKill); 4423 } 4424 return 0; 4425} 4426 4427unsigned fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i64_MVT_f32_r(unsigned Op0, bool Op0IsKill) { 4428 if ((Subtarget->hasFPARMv8())) { 4429 return fastEmitInst_r(AArch64::SCVTFUXSri, &AArch64::FPR32RegClass, Op0, Op0IsKill); 4430 } 4431 return 0; 4432} 4433 4434unsigned fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i64_MVT_f64_r(unsigned Op0, bool Op0IsKill) { 4435 if ((Subtarget->hasFPARMv8())) { 4436 return fastEmitInst_r(AArch64::SCVTFUXDri, &AArch64::FPR64RegClass, Op0, Op0IsKill); 4437 } 4438 return 0; 4439} 4440 4441unsigned fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 4442switch (RetVT.SimpleTy) { 4443 case MVT::f16: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i64_MVT_f16_r(Op0, Op0IsKill); 4444 case MVT::f32: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i64_MVT_f32_r(Op0, Op0IsKill); 4445 case MVT::f64: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i64_MVT_f64_r(Op0, Op0IsKill); 4446 default: return 0; 4447} 4448} 4449 4450unsigned fastEmit_ISD_STRICT_SINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 4451 switch (VT.SimpleTy) { 4452 case MVT::i32: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_r(RetVT, Op0, Op0IsKill); 4453 case MVT::i64: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i64_r(RetVT, Op0, Op0IsKill); 4454 default: return 0; 4455 } 4456} 4457 4458// FastEmit functions for ISD::STRICT_UINT_TO_FP. 4459 4460unsigned fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i32_MVT_f16_r(unsigned Op0, bool Op0IsKill) { 4461 if ((Subtarget->hasFullFP16())) { 4462 return fastEmitInst_r(AArch64::UCVTFUWHri, &AArch64::FPR16RegClass, Op0, Op0IsKill); 4463 } 4464 return 0; 4465} 4466 4467unsigned fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i32_MVT_f32_r(unsigned Op0, bool Op0IsKill) { 4468 if ((Subtarget->hasFPARMv8())) { 4469 return fastEmitInst_r(AArch64::UCVTFUWSri, &AArch64::FPR32RegClass, Op0, Op0IsKill); 4470 } 4471 return 0; 4472} 4473 4474unsigned fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i32_MVT_f64_r(unsigned Op0, bool Op0IsKill) { 4475 if ((Subtarget->hasFPARMv8())) { 4476 return fastEmitInst_r(AArch64::UCVTFUWDri, &AArch64::FPR64RegClass, Op0, Op0IsKill); 4477 } 4478 return 0; 4479} 4480 4481unsigned fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 4482switch (RetVT.SimpleTy) { 4483 case MVT::f16: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i32_MVT_f16_r(Op0, Op0IsKill); 4484 case MVT::f32: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i32_MVT_f32_r(Op0, Op0IsKill); 4485 case MVT::f64: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i32_MVT_f64_r(Op0, Op0IsKill); 4486 default: return 0; 4487} 4488} 4489 4490unsigned fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i64_MVT_f16_r(unsigned Op0, bool Op0IsKill) { 4491 if ((Subtarget->hasFullFP16())) { 4492 return fastEmitInst_r(AArch64::UCVTFUXHri, &AArch64::FPR16RegClass, Op0, Op0IsKill); 4493 } 4494 return 0; 4495} 4496 4497unsigned fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i64_MVT_f32_r(unsigned Op0, bool Op0IsKill) { 4498 if ((Subtarget->hasFPARMv8())) { 4499 return fastEmitInst_r(AArch64::UCVTFUXSri, &AArch64::FPR32RegClass, Op0, Op0IsKill); 4500 } 4501 return 0; 4502} 4503 4504unsigned fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i64_MVT_f64_r(unsigned Op0, bool Op0IsKill) { 4505 if ((Subtarget->hasFPARMv8())) { 4506 return fastEmitInst_r(AArch64::UCVTFUXDri, &AArch64::FPR64RegClass, Op0, Op0IsKill); 4507 } 4508 return 0; 4509} 4510 4511unsigned fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 4512switch (RetVT.SimpleTy) { 4513 case MVT::f16: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i64_MVT_f16_r(Op0, Op0IsKill); 4514 case MVT::f32: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i64_MVT_f32_r(Op0, Op0IsKill); 4515 case MVT::f64: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i64_MVT_f64_r(Op0, Op0IsKill); 4516 default: return 0; 4517} 4518} 4519 4520unsigned fastEmit_ISD_STRICT_UINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 4521 switch (VT.SimpleTy) { 4522 case MVT::i32: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i32_r(RetVT, Op0, Op0IsKill); 4523 case MVT::i64: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i64_r(RetVT, Op0, Op0IsKill); 4524 default: return 0; 4525 } 4526} 4527 4528// FastEmit functions for ISD::TRUNCATE. 4529 4530unsigned fastEmit_ISD_TRUNCATE_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 4531 if (RetVT.SimpleTy != MVT::i32) 4532 return 0; 4533 return fastEmitInst_extractsubreg(RetVT, Op0, Op0IsKill, AArch64::sub_32); 4534} 4535 4536unsigned fastEmit_ISD_TRUNCATE_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 4537 if (RetVT.SimpleTy != MVT::v8i8) 4538 return 0; 4539 if ((Subtarget->hasNEON())) { 4540 return fastEmitInst_r(AArch64::XTNv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill); 4541 } 4542 return 0; 4543} 4544 4545unsigned fastEmit_ISD_TRUNCATE_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 4546 if (RetVT.SimpleTy != MVT::v4i16) 4547 return 0; 4548 if ((Subtarget->hasNEON())) { 4549 return fastEmitInst_r(AArch64::XTNv4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 4550 } 4551 return 0; 4552} 4553 4554unsigned fastEmit_ISD_TRUNCATE_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 4555 if (RetVT.SimpleTy != MVT::v2i32) 4556 return 0; 4557 if ((Subtarget->hasNEON())) { 4558 return fastEmitInst_r(AArch64::XTNv2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill); 4559 } 4560 return 0; 4561} 4562 4563unsigned fastEmit_ISD_TRUNCATE_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 4564 switch (VT.SimpleTy) { 4565 case MVT::i64: return fastEmit_ISD_TRUNCATE_MVT_i64_r(RetVT, Op0, Op0IsKill); 4566 case MVT::v8i16: return fastEmit_ISD_TRUNCATE_MVT_v8i16_r(RetVT, Op0, Op0IsKill); 4567 case MVT::v4i32: return fastEmit_ISD_TRUNCATE_MVT_v4i32_r(RetVT, Op0, Op0IsKill); 4568 case MVT::v2i64: return fastEmit_ISD_TRUNCATE_MVT_v2i64_r(RetVT, Op0, Op0IsKill); 4569 default: return 0; 4570 } 4571} 4572 4573// FastEmit functions for ISD::UINT_TO_FP. 4574 4575unsigned fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f16_r(unsigned Op0, bool Op0IsKill) { 4576 if ((Subtarget->hasFullFP16())) { 4577 return fastEmitInst_r(AArch64::UCVTFUWHri, &AArch64::FPR16RegClass, Op0, Op0IsKill); 4578 } 4579 return 0; 4580} 4581 4582unsigned fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f32_r(unsigned Op0, bool Op0IsKill) { 4583 if ((Subtarget->hasFPARMv8())) { 4584 return fastEmitInst_r(AArch64::UCVTFUWSri, &AArch64::FPR32RegClass, Op0, Op0IsKill); 4585 } 4586 return 0; 4587} 4588 4589unsigned fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f64_r(unsigned Op0, bool Op0IsKill) { 4590 if ((Subtarget->hasFPARMv8())) { 4591 return fastEmitInst_r(AArch64::UCVTFUWDri, &AArch64::FPR64RegClass, Op0, Op0IsKill); 4592 } 4593 return 0; 4594} 4595 4596unsigned fastEmit_ISD_UINT_TO_FP_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 4597switch (RetVT.SimpleTy) { 4598 case MVT::f16: return fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f16_r(Op0, Op0IsKill); 4599 case MVT::f32: return fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f32_r(Op0, Op0IsKill); 4600 case MVT::f64: return fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f64_r(Op0, Op0IsKill); 4601 default: return 0; 4602} 4603} 4604 4605unsigned fastEmit_ISD_UINT_TO_FP_MVT_i64_MVT_f16_r(unsigned Op0, bool Op0IsKill) { 4606 if ((Subtarget->hasFullFP16())) { 4607 return fastEmitInst_r(AArch64::UCVTFUXHri, &AArch64::FPR16RegClass, Op0, Op0IsKill); 4608 } 4609 return 0; 4610} 4611 4612unsigned fastEmit_ISD_UINT_TO_FP_MVT_i64_MVT_f32_r(unsigned Op0, bool Op0IsKill) { 4613 if ((Subtarget->hasFPARMv8())) { 4614 return fastEmitInst_r(AArch64::UCVTFUXSri, &AArch64::FPR32RegClass, Op0, Op0IsKill); 4615 } 4616 return 0; 4617} 4618 4619unsigned fastEmit_ISD_UINT_TO_FP_MVT_i64_MVT_f64_r(unsigned Op0, bool Op0IsKill) { 4620 if ((Subtarget->hasFPARMv8())) { 4621 return fastEmitInst_r(AArch64::UCVTFUXDri, &AArch64::FPR64RegClass, Op0, Op0IsKill); 4622 } 4623 return 0; 4624} 4625 4626unsigned fastEmit_ISD_UINT_TO_FP_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 4627switch (RetVT.SimpleTy) { 4628 case MVT::f16: return fastEmit_ISD_UINT_TO_FP_MVT_i64_MVT_f16_r(Op0, Op0IsKill); 4629 case MVT::f32: return fastEmit_ISD_UINT_TO_FP_MVT_i64_MVT_f32_r(Op0, Op0IsKill); 4630 case MVT::f64: return fastEmit_ISD_UINT_TO_FP_MVT_i64_MVT_f64_r(Op0, Op0IsKill); 4631 default: return 0; 4632} 4633} 4634 4635unsigned fastEmit_ISD_UINT_TO_FP_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 4636 if (RetVT.SimpleTy != MVT::v4f16) 4637 return 0; 4638 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 4639 return fastEmitInst_r(AArch64::UCVTFv4f16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 4640 } 4641 return 0; 4642} 4643 4644unsigned fastEmit_ISD_UINT_TO_FP_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 4645 if (RetVT.SimpleTy != MVT::v8f16) 4646 return 0; 4647 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 4648 return fastEmitInst_r(AArch64::UCVTFv8f16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 4649 } 4650 return 0; 4651} 4652 4653unsigned fastEmit_ISD_UINT_TO_FP_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 4654 if (RetVT.SimpleTy != MVT::v2f32) 4655 return 0; 4656 if ((Subtarget->hasNEON())) { 4657 return fastEmitInst_r(AArch64::UCVTFv2f32, &AArch64::FPR64RegClass, Op0, Op0IsKill); 4658 } 4659 return 0; 4660} 4661 4662unsigned fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 4663 if (RetVT.SimpleTy != MVT::v4f32) 4664 return 0; 4665 if ((Subtarget->hasNEON())) { 4666 return fastEmitInst_r(AArch64::UCVTFv4f32, &AArch64::FPR128RegClass, Op0, Op0IsKill); 4667 } 4668 return 0; 4669} 4670 4671unsigned fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 4672 if (RetVT.SimpleTy != MVT::v2f64) 4673 return 0; 4674 if ((Subtarget->hasNEON())) { 4675 return fastEmitInst_r(AArch64::UCVTFv2f64, &AArch64::FPR128RegClass, Op0, Op0IsKill); 4676 } 4677 return 0; 4678} 4679 4680unsigned fastEmit_ISD_UINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 4681 switch (VT.SimpleTy) { 4682 case MVT::i32: return fastEmit_ISD_UINT_TO_FP_MVT_i32_r(RetVT, Op0, Op0IsKill); 4683 case MVT::i64: return fastEmit_ISD_UINT_TO_FP_MVT_i64_r(RetVT, Op0, Op0IsKill); 4684 case MVT::v4i16: return fastEmit_ISD_UINT_TO_FP_MVT_v4i16_r(RetVT, Op0, Op0IsKill); 4685 case MVT::v8i16: return fastEmit_ISD_UINT_TO_FP_MVT_v8i16_r(RetVT, Op0, Op0IsKill); 4686 case MVT::v2i32: return fastEmit_ISD_UINT_TO_FP_MVT_v2i32_r(RetVT, Op0, Op0IsKill); 4687 case MVT::v4i32: return fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(RetVT, Op0, Op0IsKill); 4688 case MVT::v2i64: return fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(RetVT, Op0, Op0IsKill); 4689 default: return 0; 4690 } 4691} 4692 4693// Top-level FastEmit function. 4694 4695unsigned fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill) override { 4696 switch (Opcode) { 4697 case AArch64ISD::CALL: return fastEmit_AArch64ISD_CALL_r(VT, RetVT, Op0, Op0IsKill); 4698 case AArch64ISD::CMEQz: return fastEmit_AArch64ISD_CMEQz_r(VT, RetVT, Op0, Op0IsKill); 4699 case AArch64ISD::CMGEz: return fastEmit_AArch64ISD_CMGEz_r(VT, RetVT, Op0, Op0IsKill); 4700 case AArch64ISD::CMGTz: return fastEmit_AArch64ISD_CMGTz_r(VT, RetVT, Op0, Op0IsKill); 4701 case AArch64ISD::CMLEz: return fastEmit_AArch64ISD_CMLEz_r(VT, RetVT, Op0, Op0IsKill); 4702 case AArch64ISD::CMLTz: return fastEmit_AArch64ISD_CMLTz_r(VT, RetVT, Op0, Op0IsKill); 4703 case AArch64ISD::DUP: return fastEmit_AArch64ISD_DUP_r(VT, RetVT, Op0, Op0IsKill); 4704 case AArch64ISD::FCMEQz: return fastEmit_AArch64ISD_FCMEQz_r(VT, RetVT, Op0, Op0IsKill); 4705 case AArch64ISD::FCMGEz: return fastEmit_AArch64ISD_FCMGEz_r(VT, RetVT, Op0, Op0IsKill); 4706 case AArch64ISD::FCMGTz: return fastEmit_AArch64ISD_FCMGTz_r(VT, RetVT, Op0, Op0IsKill); 4707 case AArch64ISD::FCMLEz: return fastEmit_AArch64ISD_FCMLEz_r(VT, RetVT, Op0, Op0IsKill); 4708 case AArch64ISD::FCMLTz: return fastEmit_AArch64ISD_FCMLTz_r(VT, RetVT, Op0, Op0IsKill); 4709 case AArch64ISD::FRECPE: return fastEmit_AArch64ISD_FRECPE_r(VT, RetVT, Op0, Op0IsKill); 4710 case AArch64ISD::FRSQRTE: return fastEmit_AArch64ISD_FRSQRTE_r(VT, RetVT, Op0, Op0IsKill); 4711 case AArch64ISD::NEG: return fastEmit_AArch64ISD_NEG_r(VT, RetVT, Op0, Op0IsKill); 4712 case AArch64ISD::NOT: return fastEmit_AArch64ISD_NOT_r(VT, RetVT, Op0, Op0IsKill); 4713 case AArch64ISD::REV: return fastEmit_AArch64ISD_REV_r(VT, RetVT, Op0, Op0IsKill); 4714 case AArch64ISD::REV16: return fastEmit_AArch64ISD_REV16_r(VT, RetVT, Op0, Op0IsKill); 4715 case AArch64ISD::REV32: return fastEmit_AArch64ISD_REV32_r(VT, RetVT, Op0, Op0IsKill); 4716 case AArch64ISD::REV64: return fastEmit_AArch64ISD_REV64_r(VT, RetVT, Op0, Op0IsKill); 4717 case AArch64ISD::SITOF: return fastEmit_AArch64ISD_SITOF_r(VT, RetVT, Op0, Op0IsKill); 4718 case AArch64ISD::SUNPKHI: return fastEmit_AArch64ISD_SUNPKHI_r(VT, RetVT, Op0, Op0IsKill); 4719 case AArch64ISD::SUNPKLO: return fastEmit_AArch64ISD_SUNPKLO_r(VT, RetVT, Op0, Op0IsKill); 4720 case AArch64ISD::UITOF: return fastEmit_AArch64ISD_UITOF_r(VT, RetVT, Op0, Op0IsKill); 4721 case AArch64ISD::UUNPKHI: return fastEmit_AArch64ISD_UUNPKHI_r(VT, RetVT, Op0, Op0IsKill); 4722 case AArch64ISD::UUNPKLO: return fastEmit_AArch64ISD_UUNPKLO_r(VT, RetVT, Op0, Op0IsKill); 4723 case ISD::ABS: return fastEmit_ISD_ABS_r(VT, RetVT, Op0, Op0IsKill); 4724 case ISD::BITCAST: return fastEmit_ISD_BITCAST_r(VT, RetVT, Op0, Op0IsKill); 4725 case ISD::BITREVERSE: return fastEmit_ISD_BITREVERSE_r(VT, RetVT, Op0, Op0IsKill); 4726 case ISD::BRIND: return fastEmit_ISD_BRIND_r(VT, RetVT, Op0, Op0IsKill); 4727 case ISD::BSWAP: return fastEmit_ISD_BSWAP_r(VT, RetVT, Op0, Op0IsKill); 4728 case ISD::CTLZ: return fastEmit_ISD_CTLZ_r(VT, RetVT, Op0, Op0IsKill); 4729 case ISD::CTPOP: return fastEmit_ISD_CTPOP_r(VT, RetVT, Op0, Op0IsKill); 4730 case ISD::FABS: return fastEmit_ISD_FABS_r(VT, RetVT, Op0, Op0IsKill); 4731 case ISD::FCEIL: return fastEmit_ISD_FCEIL_r(VT, RetVT, Op0, Op0IsKill); 4732 case ISD::FFLOOR: return fastEmit_ISD_FFLOOR_r(VT, RetVT, Op0, Op0IsKill); 4733 case ISD::FNEARBYINT: return fastEmit_ISD_FNEARBYINT_r(VT, RetVT, Op0, Op0IsKill); 4734 case ISD::FNEG: return fastEmit_ISD_FNEG_r(VT, RetVT, Op0, Op0IsKill); 4735 case ISD::FP_EXTEND: return fastEmit_ISD_FP_EXTEND_r(VT, RetVT, Op0, Op0IsKill); 4736 case ISD::FP_ROUND: return fastEmit_ISD_FP_ROUND_r(VT, RetVT, Op0, Op0IsKill); 4737 case ISD::FP_TO_SINT: return fastEmit_ISD_FP_TO_SINT_r(VT, RetVT, Op0, Op0IsKill); 4738 case ISD::FP_TO_UINT: return fastEmit_ISD_FP_TO_UINT_r(VT, RetVT, Op0, Op0IsKill); 4739 case ISD::FRINT: return fastEmit_ISD_FRINT_r(VT, RetVT, Op0, Op0IsKill); 4740 case ISD::FROUND: return fastEmit_ISD_FROUND_r(VT, RetVT, Op0, Op0IsKill); 4741 case ISD::FSQRT: return fastEmit_ISD_FSQRT_r(VT, RetVT, Op0, Op0IsKill); 4742 case ISD::FTRUNC: return fastEmit_ISD_FTRUNC_r(VT, RetVT, Op0, Op0IsKill); 4743 case ISD::LLROUND: return fastEmit_ISD_LLROUND_r(VT, RetVT, Op0, Op0IsKill); 4744 case ISD::LROUND: return fastEmit_ISD_LROUND_r(VT, RetVT, Op0, Op0IsKill); 4745 case ISD::SINT_TO_FP: return fastEmit_ISD_SINT_TO_FP_r(VT, RetVT, Op0, Op0IsKill); 4746 case ISD::STRICT_FP_ROUND: return fastEmit_ISD_STRICT_FP_ROUND_r(VT, RetVT, Op0, Op0IsKill); 4747 case ISD::STRICT_FP_TO_SINT: return fastEmit_ISD_STRICT_FP_TO_SINT_r(VT, RetVT, Op0, Op0IsKill); 4748 case ISD::STRICT_FP_TO_UINT: return fastEmit_ISD_STRICT_FP_TO_UINT_r(VT, RetVT, Op0, Op0IsKill); 4749 case ISD::STRICT_SINT_TO_FP: return fastEmit_ISD_STRICT_SINT_TO_FP_r(VT, RetVT, Op0, Op0IsKill); 4750 case ISD::STRICT_UINT_TO_FP: return fastEmit_ISD_STRICT_UINT_TO_FP_r(VT, RetVT, Op0, Op0IsKill); 4751 case ISD::TRUNCATE: return fastEmit_ISD_TRUNCATE_r(VT, RetVT, Op0, Op0IsKill); 4752 case ISD::UINT_TO_FP: return fastEmit_ISD_UINT_TO_FP_r(VT, RetVT, Op0, Op0IsKill); 4753 default: return 0; 4754 } 4755} 4756 4757// FastEmit functions for AArch64ISD::CMEQ. 4758 4759unsigned fastEmit_AArch64ISD_CMEQ_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4760 if (RetVT.SimpleTy != MVT::v8i8) 4761 return 0; 4762 if ((Subtarget->hasNEON())) { 4763 return fastEmitInst_rr(AArch64::CMEQv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4764 } 4765 return 0; 4766} 4767 4768unsigned fastEmit_AArch64ISD_CMEQ_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4769 if (RetVT.SimpleTy != MVT::v16i8) 4770 return 0; 4771 if ((Subtarget->hasNEON())) { 4772 return fastEmitInst_rr(AArch64::CMEQv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4773 } 4774 return 0; 4775} 4776 4777unsigned fastEmit_AArch64ISD_CMEQ_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4778 if (RetVT.SimpleTy != MVT::v4i16) 4779 return 0; 4780 if ((Subtarget->hasNEON())) { 4781 return fastEmitInst_rr(AArch64::CMEQv4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4782 } 4783 return 0; 4784} 4785 4786unsigned fastEmit_AArch64ISD_CMEQ_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4787 if (RetVT.SimpleTy != MVT::v8i16) 4788 return 0; 4789 if ((Subtarget->hasNEON())) { 4790 return fastEmitInst_rr(AArch64::CMEQv8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4791 } 4792 return 0; 4793} 4794 4795unsigned fastEmit_AArch64ISD_CMEQ_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4796 if (RetVT.SimpleTy != MVT::v2i32) 4797 return 0; 4798 if ((Subtarget->hasNEON())) { 4799 return fastEmitInst_rr(AArch64::CMEQv2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4800 } 4801 return 0; 4802} 4803 4804unsigned fastEmit_AArch64ISD_CMEQ_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4805 if (RetVT.SimpleTy != MVT::v4i32) 4806 return 0; 4807 if ((Subtarget->hasNEON())) { 4808 return fastEmitInst_rr(AArch64::CMEQv4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4809 } 4810 return 0; 4811} 4812 4813unsigned fastEmit_AArch64ISD_CMEQ_MVT_v1i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4814 if (RetVT.SimpleTy != MVT::v1i64) 4815 return 0; 4816 if ((Subtarget->hasNEON())) { 4817 return fastEmitInst_rr(AArch64::CMEQv1i64, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4818 } 4819 return 0; 4820} 4821 4822unsigned fastEmit_AArch64ISD_CMEQ_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4823 if (RetVT.SimpleTy != MVT::v2i64) 4824 return 0; 4825 if ((Subtarget->hasNEON())) { 4826 return fastEmitInst_rr(AArch64::CMEQv2i64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4827 } 4828 return 0; 4829} 4830 4831unsigned fastEmit_AArch64ISD_CMEQ_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4832 switch (VT.SimpleTy) { 4833 case MVT::v8i8: return fastEmit_AArch64ISD_CMEQ_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4834 case MVT::v16i8: return fastEmit_AArch64ISD_CMEQ_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4835 case MVT::v4i16: return fastEmit_AArch64ISD_CMEQ_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4836 case MVT::v8i16: return fastEmit_AArch64ISD_CMEQ_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4837 case MVT::v2i32: return fastEmit_AArch64ISD_CMEQ_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4838 case MVT::v4i32: return fastEmit_AArch64ISD_CMEQ_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4839 case MVT::v1i64: return fastEmit_AArch64ISD_CMEQ_MVT_v1i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4840 case MVT::v2i64: return fastEmit_AArch64ISD_CMEQ_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4841 default: return 0; 4842 } 4843} 4844 4845// FastEmit functions for AArch64ISD::CMGE. 4846 4847unsigned fastEmit_AArch64ISD_CMGE_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4848 if (RetVT.SimpleTy != MVT::v8i8) 4849 return 0; 4850 if ((Subtarget->hasNEON())) { 4851 return fastEmitInst_rr(AArch64::CMGEv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4852 } 4853 return 0; 4854} 4855 4856unsigned fastEmit_AArch64ISD_CMGE_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4857 if (RetVT.SimpleTy != MVT::v16i8) 4858 return 0; 4859 if ((Subtarget->hasNEON())) { 4860 return fastEmitInst_rr(AArch64::CMGEv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4861 } 4862 return 0; 4863} 4864 4865unsigned fastEmit_AArch64ISD_CMGE_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4866 if (RetVT.SimpleTy != MVT::v4i16) 4867 return 0; 4868 if ((Subtarget->hasNEON())) { 4869 return fastEmitInst_rr(AArch64::CMGEv4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4870 } 4871 return 0; 4872} 4873 4874unsigned fastEmit_AArch64ISD_CMGE_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4875 if (RetVT.SimpleTy != MVT::v8i16) 4876 return 0; 4877 if ((Subtarget->hasNEON())) { 4878 return fastEmitInst_rr(AArch64::CMGEv8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4879 } 4880 return 0; 4881} 4882 4883unsigned fastEmit_AArch64ISD_CMGE_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4884 if (RetVT.SimpleTy != MVT::v2i32) 4885 return 0; 4886 if ((Subtarget->hasNEON())) { 4887 return fastEmitInst_rr(AArch64::CMGEv2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4888 } 4889 return 0; 4890} 4891 4892unsigned fastEmit_AArch64ISD_CMGE_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4893 if (RetVT.SimpleTy != MVT::v4i32) 4894 return 0; 4895 if ((Subtarget->hasNEON())) { 4896 return fastEmitInst_rr(AArch64::CMGEv4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4897 } 4898 return 0; 4899} 4900 4901unsigned fastEmit_AArch64ISD_CMGE_MVT_v1i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4902 if (RetVT.SimpleTy != MVT::v1i64) 4903 return 0; 4904 if ((Subtarget->hasNEON())) { 4905 return fastEmitInst_rr(AArch64::CMGEv1i64, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4906 } 4907 return 0; 4908} 4909 4910unsigned fastEmit_AArch64ISD_CMGE_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4911 if (RetVT.SimpleTy != MVT::v2i64) 4912 return 0; 4913 if ((Subtarget->hasNEON())) { 4914 return fastEmitInst_rr(AArch64::CMGEv2i64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4915 } 4916 return 0; 4917} 4918 4919unsigned fastEmit_AArch64ISD_CMGE_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4920 switch (VT.SimpleTy) { 4921 case MVT::v8i8: return fastEmit_AArch64ISD_CMGE_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4922 case MVT::v16i8: return fastEmit_AArch64ISD_CMGE_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4923 case MVT::v4i16: return fastEmit_AArch64ISD_CMGE_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4924 case MVT::v8i16: return fastEmit_AArch64ISD_CMGE_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4925 case MVT::v2i32: return fastEmit_AArch64ISD_CMGE_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4926 case MVT::v4i32: return fastEmit_AArch64ISD_CMGE_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4927 case MVT::v1i64: return fastEmit_AArch64ISD_CMGE_MVT_v1i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4928 case MVT::v2i64: return fastEmit_AArch64ISD_CMGE_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4929 default: return 0; 4930 } 4931} 4932 4933// FastEmit functions for AArch64ISD::CMGT. 4934 4935unsigned fastEmit_AArch64ISD_CMGT_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4936 if (RetVT.SimpleTy != MVT::v8i8) 4937 return 0; 4938 if ((Subtarget->hasNEON())) { 4939 return fastEmitInst_rr(AArch64::CMGTv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4940 } 4941 return 0; 4942} 4943 4944unsigned fastEmit_AArch64ISD_CMGT_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4945 if (RetVT.SimpleTy != MVT::v16i8) 4946 return 0; 4947 if ((Subtarget->hasNEON())) { 4948 return fastEmitInst_rr(AArch64::CMGTv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4949 } 4950 return 0; 4951} 4952 4953unsigned fastEmit_AArch64ISD_CMGT_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4954 if (RetVT.SimpleTy != MVT::v4i16) 4955 return 0; 4956 if ((Subtarget->hasNEON())) { 4957 return fastEmitInst_rr(AArch64::CMGTv4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4958 } 4959 return 0; 4960} 4961 4962unsigned fastEmit_AArch64ISD_CMGT_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4963 if (RetVT.SimpleTy != MVT::v8i16) 4964 return 0; 4965 if ((Subtarget->hasNEON())) { 4966 return fastEmitInst_rr(AArch64::CMGTv8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4967 } 4968 return 0; 4969} 4970 4971unsigned fastEmit_AArch64ISD_CMGT_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4972 if (RetVT.SimpleTy != MVT::v2i32) 4973 return 0; 4974 if ((Subtarget->hasNEON())) { 4975 return fastEmitInst_rr(AArch64::CMGTv2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4976 } 4977 return 0; 4978} 4979 4980unsigned fastEmit_AArch64ISD_CMGT_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4981 if (RetVT.SimpleTy != MVT::v4i32) 4982 return 0; 4983 if ((Subtarget->hasNEON())) { 4984 return fastEmitInst_rr(AArch64::CMGTv4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4985 } 4986 return 0; 4987} 4988 4989unsigned fastEmit_AArch64ISD_CMGT_MVT_v1i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4990 if (RetVT.SimpleTy != MVT::v1i64) 4991 return 0; 4992 if ((Subtarget->hasNEON())) { 4993 return fastEmitInst_rr(AArch64::CMGTv1i64, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4994 } 4995 return 0; 4996} 4997 4998unsigned fastEmit_AArch64ISD_CMGT_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4999 if (RetVT.SimpleTy != MVT::v2i64) 5000 return 0; 5001 if ((Subtarget->hasNEON())) { 5002 return fastEmitInst_rr(AArch64::CMGTv2i64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5003 } 5004 return 0; 5005} 5006 5007unsigned fastEmit_AArch64ISD_CMGT_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5008 switch (VT.SimpleTy) { 5009 case MVT::v8i8: return fastEmit_AArch64ISD_CMGT_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5010 case MVT::v16i8: return fastEmit_AArch64ISD_CMGT_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5011 case MVT::v4i16: return fastEmit_AArch64ISD_CMGT_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5012 case MVT::v8i16: return fastEmit_AArch64ISD_CMGT_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5013 case MVT::v2i32: return fastEmit_AArch64ISD_CMGT_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5014 case MVT::v4i32: return fastEmit_AArch64ISD_CMGT_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5015 case MVT::v1i64: return fastEmit_AArch64ISD_CMGT_MVT_v1i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5016 case MVT::v2i64: return fastEmit_AArch64ISD_CMGT_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5017 default: return 0; 5018 } 5019} 5020 5021// FastEmit functions for AArch64ISD::CMHI. 5022 5023unsigned fastEmit_AArch64ISD_CMHI_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5024 if (RetVT.SimpleTy != MVT::v8i8) 5025 return 0; 5026 if ((Subtarget->hasNEON())) { 5027 return fastEmitInst_rr(AArch64::CMHIv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5028 } 5029 return 0; 5030} 5031 5032unsigned fastEmit_AArch64ISD_CMHI_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5033 if (RetVT.SimpleTy != MVT::v16i8) 5034 return 0; 5035 if ((Subtarget->hasNEON())) { 5036 return fastEmitInst_rr(AArch64::CMHIv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5037 } 5038 return 0; 5039} 5040 5041unsigned fastEmit_AArch64ISD_CMHI_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5042 if (RetVT.SimpleTy != MVT::v4i16) 5043 return 0; 5044 if ((Subtarget->hasNEON())) { 5045 return fastEmitInst_rr(AArch64::CMHIv4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5046 } 5047 return 0; 5048} 5049 5050unsigned fastEmit_AArch64ISD_CMHI_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5051 if (RetVT.SimpleTy != MVT::v8i16) 5052 return 0; 5053 if ((Subtarget->hasNEON())) { 5054 return fastEmitInst_rr(AArch64::CMHIv8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5055 } 5056 return 0; 5057} 5058 5059unsigned fastEmit_AArch64ISD_CMHI_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5060 if (RetVT.SimpleTy != MVT::v2i32) 5061 return 0; 5062 if ((Subtarget->hasNEON())) { 5063 return fastEmitInst_rr(AArch64::CMHIv2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5064 } 5065 return 0; 5066} 5067 5068unsigned fastEmit_AArch64ISD_CMHI_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5069 if (RetVT.SimpleTy != MVT::v4i32) 5070 return 0; 5071 if ((Subtarget->hasNEON())) { 5072 return fastEmitInst_rr(AArch64::CMHIv4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5073 } 5074 return 0; 5075} 5076 5077unsigned fastEmit_AArch64ISD_CMHI_MVT_v1i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5078 if (RetVT.SimpleTy != MVT::v1i64) 5079 return 0; 5080 if ((Subtarget->hasNEON())) { 5081 return fastEmitInst_rr(AArch64::CMHIv1i64, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5082 } 5083 return 0; 5084} 5085 5086unsigned fastEmit_AArch64ISD_CMHI_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5087 if (RetVT.SimpleTy != MVT::v2i64) 5088 return 0; 5089 if ((Subtarget->hasNEON())) { 5090 return fastEmitInst_rr(AArch64::CMHIv2i64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5091 } 5092 return 0; 5093} 5094 5095unsigned fastEmit_AArch64ISD_CMHI_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5096 switch (VT.SimpleTy) { 5097 case MVT::v8i8: return fastEmit_AArch64ISD_CMHI_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5098 case MVT::v16i8: return fastEmit_AArch64ISD_CMHI_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5099 case MVT::v4i16: return fastEmit_AArch64ISD_CMHI_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5100 case MVT::v8i16: return fastEmit_AArch64ISD_CMHI_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5101 case MVT::v2i32: return fastEmit_AArch64ISD_CMHI_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5102 case MVT::v4i32: return fastEmit_AArch64ISD_CMHI_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5103 case MVT::v1i64: return fastEmit_AArch64ISD_CMHI_MVT_v1i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5104 case MVT::v2i64: return fastEmit_AArch64ISD_CMHI_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5105 default: return 0; 5106 } 5107} 5108 5109// FastEmit functions for AArch64ISD::CMHS. 5110 5111unsigned fastEmit_AArch64ISD_CMHS_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5112 if (RetVT.SimpleTy != MVT::v8i8) 5113 return 0; 5114 if ((Subtarget->hasNEON())) { 5115 return fastEmitInst_rr(AArch64::CMHSv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5116 } 5117 return 0; 5118} 5119 5120unsigned fastEmit_AArch64ISD_CMHS_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5121 if (RetVT.SimpleTy != MVT::v16i8) 5122 return 0; 5123 if ((Subtarget->hasNEON())) { 5124 return fastEmitInst_rr(AArch64::CMHSv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5125 } 5126 return 0; 5127} 5128 5129unsigned fastEmit_AArch64ISD_CMHS_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5130 if (RetVT.SimpleTy != MVT::v4i16) 5131 return 0; 5132 if ((Subtarget->hasNEON())) { 5133 return fastEmitInst_rr(AArch64::CMHSv4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5134 } 5135 return 0; 5136} 5137 5138unsigned fastEmit_AArch64ISD_CMHS_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5139 if (RetVT.SimpleTy != MVT::v8i16) 5140 return 0; 5141 if ((Subtarget->hasNEON())) { 5142 return fastEmitInst_rr(AArch64::CMHSv8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5143 } 5144 return 0; 5145} 5146 5147unsigned fastEmit_AArch64ISD_CMHS_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5148 if (RetVT.SimpleTy != MVT::v2i32) 5149 return 0; 5150 if ((Subtarget->hasNEON())) { 5151 return fastEmitInst_rr(AArch64::CMHSv2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5152 } 5153 return 0; 5154} 5155 5156unsigned fastEmit_AArch64ISD_CMHS_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5157 if (RetVT.SimpleTy != MVT::v4i32) 5158 return 0; 5159 if ((Subtarget->hasNEON())) { 5160 return fastEmitInst_rr(AArch64::CMHSv4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5161 } 5162 return 0; 5163} 5164 5165unsigned fastEmit_AArch64ISD_CMHS_MVT_v1i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5166 if (RetVT.SimpleTy != MVT::v1i64) 5167 return 0; 5168 if ((Subtarget->hasNEON())) { 5169 return fastEmitInst_rr(AArch64::CMHSv1i64, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5170 } 5171 return 0; 5172} 5173 5174unsigned fastEmit_AArch64ISD_CMHS_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5175 if (RetVT.SimpleTy != MVT::v2i64) 5176 return 0; 5177 if ((Subtarget->hasNEON())) { 5178 return fastEmitInst_rr(AArch64::CMHSv2i64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5179 } 5180 return 0; 5181} 5182 5183unsigned fastEmit_AArch64ISD_CMHS_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5184 switch (VT.SimpleTy) { 5185 case MVT::v8i8: return fastEmit_AArch64ISD_CMHS_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5186 case MVT::v16i8: return fastEmit_AArch64ISD_CMHS_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5187 case MVT::v4i16: return fastEmit_AArch64ISD_CMHS_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5188 case MVT::v8i16: return fastEmit_AArch64ISD_CMHS_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5189 case MVT::v2i32: return fastEmit_AArch64ISD_CMHS_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5190 case MVT::v4i32: return fastEmit_AArch64ISD_CMHS_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5191 case MVT::v1i64: return fastEmit_AArch64ISD_CMHS_MVT_v1i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5192 case MVT::v2i64: return fastEmit_AArch64ISD_CMHS_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5193 default: return 0; 5194 } 5195} 5196 5197// FastEmit functions for AArch64ISD::FCMEQ. 5198 5199unsigned fastEmit_AArch64ISD_FCMEQ_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5200 if (RetVT.SimpleTy != MVT::i32) 5201 return 0; 5202 if ((Subtarget->hasNEON())) { 5203 return fastEmitInst_rr(AArch64::FCMEQ32, &AArch64::FPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5204 } 5205 return 0; 5206} 5207 5208unsigned fastEmit_AArch64ISD_FCMEQ_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5209 if (RetVT.SimpleTy != MVT::i64) 5210 return 0; 5211 if ((Subtarget->hasNEON())) { 5212 return fastEmitInst_rr(AArch64::FCMEQ64, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5213 } 5214 return 0; 5215} 5216 5217unsigned fastEmit_AArch64ISD_FCMEQ_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5218 if (RetVT.SimpleTy != MVT::v4i16) 5219 return 0; 5220 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 5221 return fastEmitInst_rr(AArch64::FCMEQv4f16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5222 } 5223 return 0; 5224} 5225 5226unsigned fastEmit_AArch64ISD_FCMEQ_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5227 if (RetVT.SimpleTy != MVT::v8i16) 5228 return 0; 5229 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 5230 return fastEmitInst_rr(AArch64::FCMEQv8f16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5231 } 5232 return 0; 5233} 5234 5235unsigned fastEmit_AArch64ISD_FCMEQ_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5236 if (RetVT.SimpleTy != MVT::v2i32) 5237 return 0; 5238 if ((Subtarget->hasNEON())) { 5239 return fastEmitInst_rr(AArch64::FCMEQv2f32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5240 } 5241 return 0; 5242} 5243 5244unsigned fastEmit_AArch64ISD_FCMEQ_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5245 if (RetVT.SimpleTy != MVT::v4i32) 5246 return 0; 5247 if ((Subtarget->hasNEON())) { 5248 return fastEmitInst_rr(AArch64::FCMEQv4f32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5249 } 5250 return 0; 5251} 5252 5253unsigned fastEmit_AArch64ISD_FCMEQ_MVT_v1f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5254 if (RetVT.SimpleTy != MVT::v1i64) 5255 return 0; 5256 if ((Subtarget->hasNEON())) { 5257 return fastEmitInst_rr(AArch64::FCMEQ64, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5258 } 5259 return 0; 5260} 5261 5262unsigned fastEmit_AArch64ISD_FCMEQ_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5263 if (RetVT.SimpleTy != MVT::v2i64) 5264 return 0; 5265 if ((Subtarget->hasNEON())) { 5266 return fastEmitInst_rr(AArch64::FCMEQv2f64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5267 } 5268 return 0; 5269} 5270 5271unsigned fastEmit_AArch64ISD_FCMEQ_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5272 switch (VT.SimpleTy) { 5273 case MVT::f32: return fastEmit_AArch64ISD_FCMEQ_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5274 case MVT::f64: return fastEmit_AArch64ISD_FCMEQ_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5275 case MVT::v4f16: return fastEmit_AArch64ISD_FCMEQ_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5276 case MVT::v8f16: return fastEmit_AArch64ISD_FCMEQ_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5277 case MVT::v2f32: return fastEmit_AArch64ISD_FCMEQ_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5278 case MVT::v4f32: return fastEmit_AArch64ISD_FCMEQ_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5279 case MVT::v1f64: return fastEmit_AArch64ISD_FCMEQ_MVT_v1f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5280 case MVT::v2f64: return fastEmit_AArch64ISD_FCMEQ_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5281 default: return 0; 5282 } 5283} 5284 5285// FastEmit functions for AArch64ISD::FCMGE. 5286 5287unsigned fastEmit_AArch64ISD_FCMGE_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5288 if (RetVT.SimpleTy != MVT::i32) 5289 return 0; 5290 if ((Subtarget->hasNEON())) { 5291 return fastEmitInst_rr(AArch64::FCMGE32, &AArch64::FPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5292 } 5293 return 0; 5294} 5295 5296unsigned fastEmit_AArch64ISD_FCMGE_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5297 if (RetVT.SimpleTy != MVT::i64) 5298 return 0; 5299 if ((Subtarget->hasNEON())) { 5300 return fastEmitInst_rr(AArch64::FCMGE64, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5301 } 5302 return 0; 5303} 5304 5305unsigned fastEmit_AArch64ISD_FCMGE_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5306 if (RetVT.SimpleTy != MVT::v4i16) 5307 return 0; 5308 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 5309 return fastEmitInst_rr(AArch64::FCMGEv4f16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5310 } 5311 return 0; 5312} 5313 5314unsigned fastEmit_AArch64ISD_FCMGE_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5315 if (RetVT.SimpleTy != MVT::v8i16) 5316 return 0; 5317 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 5318 return fastEmitInst_rr(AArch64::FCMGEv8f16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5319 } 5320 return 0; 5321} 5322 5323unsigned fastEmit_AArch64ISD_FCMGE_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5324 if (RetVT.SimpleTy != MVT::v2i32) 5325 return 0; 5326 if ((Subtarget->hasNEON())) { 5327 return fastEmitInst_rr(AArch64::FCMGEv2f32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5328 } 5329 return 0; 5330} 5331 5332unsigned fastEmit_AArch64ISD_FCMGE_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5333 if (RetVT.SimpleTy != MVT::v4i32) 5334 return 0; 5335 if ((Subtarget->hasNEON())) { 5336 return fastEmitInst_rr(AArch64::FCMGEv4f32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5337 } 5338 return 0; 5339} 5340 5341unsigned fastEmit_AArch64ISD_FCMGE_MVT_v1f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5342 if (RetVT.SimpleTy != MVT::v1i64) 5343 return 0; 5344 if ((Subtarget->hasNEON())) { 5345 return fastEmitInst_rr(AArch64::FCMGE64, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5346 } 5347 return 0; 5348} 5349 5350unsigned fastEmit_AArch64ISD_FCMGE_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5351 if (RetVT.SimpleTy != MVT::v2i64) 5352 return 0; 5353 if ((Subtarget->hasNEON())) { 5354 return fastEmitInst_rr(AArch64::FCMGEv2f64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5355 } 5356 return 0; 5357} 5358 5359unsigned fastEmit_AArch64ISD_FCMGE_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5360 switch (VT.SimpleTy) { 5361 case MVT::f32: return fastEmit_AArch64ISD_FCMGE_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5362 case MVT::f64: return fastEmit_AArch64ISD_FCMGE_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5363 case MVT::v4f16: return fastEmit_AArch64ISD_FCMGE_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5364 case MVT::v8f16: return fastEmit_AArch64ISD_FCMGE_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5365 case MVT::v2f32: return fastEmit_AArch64ISD_FCMGE_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5366 case MVT::v4f32: return fastEmit_AArch64ISD_FCMGE_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5367 case MVT::v1f64: return fastEmit_AArch64ISD_FCMGE_MVT_v1f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5368 case MVT::v2f64: return fastEmit_AArch64ISD_FCMGE_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5369 default: return 0; 5370 } 5371} 5372 5373// FastEmit functions for AArch64ISD::FCMGT. 5374 5375unsigned fastEmit_AArch64ISD_FCMGT_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5376 if (RetVT.SimpleTy != MVT::i32) 5377 return 0; 5378 if ((Subtarget->hasNEON())) { 5379 return fastEmitInst_rr(AArch64::FCMGT32, &AArch64::FPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5380 } 5381 return 0; 5382} 5383 5384unsigned fastEmit_AArch64ISD_FCMGT_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5385 if (RetVT.SimpleTy != MVT::i64) 5386 return 0; 5387 if ((Subtarget->hasNEON())) { 5388 return fastEmitInst_rr(AArch64::FCMGT64, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5389 } 5390 return 0; 5391} 5392 5393unsigned fastEmit_AArch64ISD_FCMGT_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5394 if (RetVT.SimpleTy != MVT::v4i16) 5395 return 0; 5396 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 5397 return fastEmitInst_rr(AArch64::FCMGTv4f16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5398 } 5399 return 0; 5400} 5401 5402unsigned fastEmit_AArch64ISD_FCMGT_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5403 if (RetVT.SimpleTy != MVT::v8i16) 5404 return 0; 5405 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 5406 return fastEmitInst_rr(AArch64::FCMGTv8f16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5407 } 5408 return 0; 5409} 5410 5411unsigned fastEmit_AArch64ISD_FCMGT_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5412 if (RetVT.SimpleTy != MVT::v2i32) 5413 return 0; 5414 if ((Subtarget->hasNEON())) { 5415 return fastEmitInst_rr(AArch64::FCMGTv2f32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5416 } 5417 return 0; 5418} 5419 5420unsigned fastEmit_AArch64ISD_FCMGT_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5421 if (RetVT.SimpleTy != MVT::v4i32) 5422 return 0; 5423 if ((Subtarget->hasNEON())) { 5424 return fastEmitInst_rr(AArch64::FCMGTv4f32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5425 } 5426 return 0; 5427} 5428 5429unsigned fastEmit_AArch64ISD_FCMGT_MVT_v1f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5430 if (RetVT.SimpleTy != MVT::v1i64) 5431 return 0; 5432 if ((Subtarget->hasNEON())) { 5433 return fastEmitInst_rr(AArch64::FCMGT64, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5434 } 5435 return 0; 5436} 5437 5438unsigned fastEmit_AArch64ISD_FCMGT_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5439 if (RetVT.SimpleTy != MVT::v2i64) 5440 return 0; 5441 if ((Subtarget->hasNEON())) { 5442 return fastEmitInst_rr(AArch64::FCMGTv2f64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5443 } 5444 return 0; 5445} 5446 5447unsigned fastEmit_AArch64ISD_FCMGT_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5448 switch (VT.SimpleTy) { 5449 case MVT::f32: return fastEmit_AArch64ISD_FCMGT_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5450 case MVT::f64: return fastEmit_AArch64ISD_FCMGT_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5451 case MVT::v4f16: return fastEmit_AArch64ISD_FCMGT_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5452 case MVT::v8f16: return fastEmit_AArch64ISD_FCMGT_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5453 case MVT::v2f32: return fastEmit_AArch64ISD_FCMGT_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5454 case MVT::v4f32: return fastEmit_AArch64ISD_FCMGT_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5455 case MVT::v1f64: return fastEmit_AArch64ISD_FCMGT_MVT_v1f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5456 case MVT::v2f64: return fastEmit_AArch64ISD_FCMGT_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5457 default: return 0; 5458 } 5459} 5460 5461// FastEmit functions for AArch64ISD::FCMP. 5462 5463unsigned fastEmit_AArch64ISD_FCMP_MVT_f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5464 if (RetVT.SimpleTy != MVT::isVoid) 5465 return 0; 5466 if ((Subtarget->hasFullFP16())) { 5467 return fastEmitInst_rr(AArch64::FCMPHrr, &AArch64::FPR16RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5468 } 5469 return 0; 5470} 5471 5472unsigned fastEmit_AArch64ISD_FCMP_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5473 if (RetVT.SimpleTy != MVT::isVoid) 5474 return 0; 5475 if ((Subtarget->hasFPARMv8())) { 5476 return fastEmitInst_rr(AArch64::FCMPSrr, &AArch64::FPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5477 } 5478 return 0; 5479} 5480 5481unsigned fastEmit_AArch64ISD_FCMP_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5482 if (RetVT.SimpleTy != MVT::isVoid) 5483 return 0; 5484 if ((Subtarget->hasFPARMv8())) { 5485 return fastEmitInst_rr(AArch64::FCMPDrr, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5486 } 5487 return 0; 5488} 5489 5490unsigned fastEmit_AArch64ISD_FCMP_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5491 switch (VT.SimpleTy) { 5492 case MVT::f16: return fastEmit_AArch64ISD_FCMP_MVT_f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5493 case MVT::f32: return fastEmit_AArch64ISD_FCMP_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5494 case MVT::f64: return fastEmit_AArch64ISD_FCMP_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5495 default: return 0; 5496 } 5497} 5498 5499// FastEmit functions for AArch64ISD::FRECPS. 5500 5501unsigned fastEmit_AArch64ISD_FRECPS_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5502 if (RetVT.SimpleTy != MVT::f32) 5503 return 0; 5504 return fastEmitInst_rr(AArch64::FRECPS32, &AArch64::FPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5505} 5506 5507unsigned fastEmit_AArch64ISD_FRECPS_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5508 if (RetVT.SimpleTy != MVT::f64) 5509 return 0; 5510 return fastEmitInst_rr(AArch64::FRECPS64, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5511} 5512 5513unsigned fastEmit_AArch64ISD_FRECPS_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5514 if (RetVT.SimpleTy != MVT::v2f32) 5515 return 0; 5516 return fastEmitInst_rr(AArch64::FRECPSv2f32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5517} 5518 5519unsigned fastEmit_AArch64ISD_FRECPS_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5520 if (RetVT.SimpleTy != MVT::v4f32) 5521 return 0; 5522 return fastEmitInst_rr(AArch64::FRECPSv4f32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5523} 5524 5525unsigned fastEmit_AArch64ISD_FRECPS_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5526 if (RetVT.SimpleTy != MVT::v2f64) 5527 return 0; 5528 return fastEmitInst_rr(AArch64::FRECPSv2f64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5529} 5530 5531unsigned fastEmit_AArch64ISD_FRECPS_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5532 switch (VT.SimpleTy) { 5533 case MVT::f32: return fastEmit_AArch64ISD_FRECPS_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5534 case MVT::f64: return fastEmit_AArch64ISD_FRECPS_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5535 case MVT::v2f32: return fastEmit_AArch64ISD_FRECPS_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5536 case MVT::v4f32: return fastEmit_AArch64ISD_FRECPS_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5537 case MVT::v2f64: return fastEmit_AArch64ISD_FRECPS_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5538 default: return 0; 5539 } 5540} 5541 5542// FastEmit functions for AArch64ISD::FRSQRTS. 5543 5544unsigned fastEmit_AArch64ISD_FRSQRTS_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5545 if (RetVT.SimpleTy != MVT::f32) 5546 return 0; 5547 return fastEmitInst_rr(AArch64::FRSQRTS32, &AArch64::FPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5548} 5549 5550unsigned fastEmit_AArch64ISD_FRSQRTS_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5551 if (RetVT.SimpleTy != MVT::f64) 5552 return 0; 5553 return fastEmitInst_rr(AArch64::FRSQRTS64, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5554} 5555 5556unsigned fastEmit_AArch64ISD_FRSQRTS_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5557 if (RetVT.SimpleTy != MVT::v2f32) 5558 return 0; 5559 return fastEmitInst_rr(AArch64::FRSQRTSv2f32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5560} 5561 5562unsigned fastEmit_AArch64ISD_FRSQRTS_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5563 if (RetVT.SimpleTy != MVT::v4f32) 5564 return 0; 5565 return fastEmitInst_rr(AArch64::FRSQRTSv4f32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5566} 5567 5568unsigned fastEmit_AArch64ISD_FRSQRTS_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5569 if (RetVT.SimpleTy != MVT::v2f64) 5570 return 0; 5571 return fastEmitInst_rr(AArch64::FRSQRTSv2f64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5572} 5573 5574unsigned fastEmit_AArch64ISD_FRSQRTS_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5575 switch (VT.SimpleTy) { 5576 case MVT::f32: return fastEmit_AArch64ISD_FRSQRTS_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5577 case MVT::f64: return fastEmit_AArch64ISD_FRSQRTS_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5578 case MVT::v2f32: return fastEmit_AArch64ISD_FRSQRTS_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5579 case MVT::v4f32: return fastEmit_AArch64ISD_FRSQRTS_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5580 case MVT::v2f64: return fastEmit_AArch64ISD_FRSQRTS_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5581 default: return 0; 5582 } 5583} 5584 5585// FastEmit functions for AArch64ISD::PTEST. 5586 5587unsigned fastEmit_AArch64ISD_PTEST_MVT_nxv2i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5588 if (RetVT.SimpleTy != MVT::isVoid) 5589 return 0; 5590 if ((Subtarget->hasSVE())) { 5591 return fastEmitInst_rr(AArch64::PTEST_PP, &AArch64::PPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5592 } 5593 return 0; 5594} 5595 5596unsigned fastEmit_AArch64ISD_PTEST_MVT_nxv4i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5597 if (RetVT.SimpleTy != MVT::isVoid) 5598 return 0; 5599 if ((Subtarget->hasSVE())) { 5600 return fastEmitInst_rr(AArch64::PTEST_PP, &AArch64::PPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5601 } 5602 return 0; 5603} 5604 5605unsigned fastEmit_AArch64ISD_PTEST_MVT_nxv8i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5606 if (RetVT.SimpleTy != MVT::isVoid) 5607 return 0; 5608 if ((Subtarget->hasSVE())) { 5609 return fastEmitInst_rr(AArch64::PTEST_PP, &AArch64::PPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5610 } 5611 return 0; 5612} 5613 5614unsigned fastEmit_AArch64ISD_PTEST_MVT_nxv16i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5615 if (RetVT.SimpleTy != MVT::isVoid) 5616 return 0; 5617 if ((Subtarget->hasSVE())) { 5618 return fastEmitInst_rr(AArch64::PTEST_PP, &AArch64::PPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5619 } 5620 return 0; 5621} 5622 5623unsigned fastEmit_AArch64ISD_PTEST_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5624 switch (VT.SimpleTy) { 5625 case MVT::nxv2i1: return fastEmit_AArch64ISD_PTEST_MVT_nxv2i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5626 case MVT::nxv4i1: return fastEmit_AArch64ISD_PTEST_MVT_nxv4i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5627 case MVT::nxv8i1: return fastEmit_AArch64ISD_PTEST_MVT_nxv8i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5628 case MVT::nxv16i1: return fastEmit_AArch64ISD_PTEST_MVT_nxv16i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5629 default: return 0; 5630 } 5631} 5632 5633// FastEmit functions for AArch64ISD::SMULL. 5634 5635unsigned fastEmit_AArch64ISD_SMULL_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5636 if (RetVT.SimpleTy != MVT::v8i16) 5637 return 0; 5638 return fastEmitInst_rr(AArch64::SMULLv8i8_v8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5639} 5640 5641unsigned fastEmit_AArch64ISD_SMULL_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5642 if (RetVT.SimpleTy != MVT::v4i32) 5643 return 0; 5644 return fastEmitInst_rr(AArch64::SMULLv4i16_v4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5645} 5646 5647unsigned fastEmit_AArch64ISD_SMULL_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5648 if (RetVT.SimpleTy != MVT::v2i64) 5649 return 0; 5650 return fastEmitInst_rr(AArch64::SMULLv2i32_v2i64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5651} 5652 5653unsigned fastEmit_AArch64ISD_SMULL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5654 switch (VT.SimpleTy) { 5655 case MVT::v8i8: return fastEmit_AArch64ISD_SMULL_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5656 case MVT::v4i16: return fastEmit_AArch64ISD_SMULL_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5657 case MVT::v2i32: return fastEmit_AArch64ISD_SMULL_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5658 default: return 0; 5659 } 5660} 5661 5662// FastEmit functions for AArch64ISD::STRICT_FCMP. 5663 5664unsigned fastEmit_AArch64ISD_STRICT_FCMP_MVT_f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5665 if (RetVT.SimpleTy != MVT::isVoid) 5666 return 0; 5667 if ((Subtarget->hasFullFP16())) { 5668 return fastEmitInst_rr(AArch64::FCMPHrr, &AArch64::FPR16RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5669 } 5670 return 0; 5671} 5672 5673unsigned fastEmit_AArch64ISD_STRICT_FCMP_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5674 if (RetVT.SimpleTy != MVT::isVoid) 5675 return 0; 5676 if ((Subtarget->hasFPARMv8())) { 5677 return fastEmitInst_rr(AArch64::FCMPSrr, &AArch64::FPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5678 } 5679 return 0; 5680} 5681 5682unsigned fastEmit_AArch64ISD_STRICT_FCMP_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5683 if (RetVT.SimpleTy != MVT::isVoid) 5684 return 0; 5685 if ((Subtarget->hasFPARMv8())) { 5686 return fastEmitInst_rr(AArch64::FCMPDrr, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5687 } 5688 return 0; 5689} 5690 5691unsigned fastEmit_AArch64ISD_STRICT_FCMP_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5692 switch (VT.SimpleTy) { 5693 case MVT::f16: return fastEmit_AArch64ISD_STRICT_FCMP_MVT_f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5694 case MVT::f32: return fastEmit_AArch64ISD_STRICT_FCMP_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5695 case MVT::f64: return fastEmit_AArch64ISD_STRICT_FCMP_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5696 default: return 0; 5697 } 5698} 5699 5700// FastEmit functions for AArch64ISD::STRICT_FCMPE. 5701 5702unsigned fastEmit_AArch64ISD_STRICT_FCMPE_MVT_f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5703 if (RetVT.SimpleTy != MVT::isVoid) 5704 return 0; 5705 if ((Subtarget->hasFullFP16())) { 5706 return fastEmitInst_rr(AArch64::FCMPEHrr, &AArch64::FPR16RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5707 } 5708 return 0; 5709} 5710 5711unsigned fastEmit_AArch64ISD_STRICT_FCMPE_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5712 if (RetVT.SimpleTy != MVT::isVoid) 5713 return 0; 5714 if ((Subtarget->hasFPARMv8())) { 5715 return fastEmitInst_rr(AArch64::FCMPESrr, &AArch64::FPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5716 } 5717 return 0; 5718} 5719 5720unsigned fastEmit_AArch64ISD_STRICT_FCMPE_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5721 if (RetVT.SimpleTy != MVT::isVoid) 5722 return 0; 5723 if ((Subtarget->hasFPARMv8())) { 5724 return fastEmitInst_rr(AArch64::FCMPEDrr, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5725 } 5726 return 0; 5727} 5728 5729unsigned fastEmit_AArch64ISD_STRICT_FCMPE_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5730 switch (VT.SimpleTy) { 5731 case MVT::f16: return fastEmit_AArch64ISD_STRICT_FCMPE_MVT_f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5732 case MVT::f32: return fastEmit_AArch64ISD_STRICT_FCMPE_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5733 case MVT::f64: return fastEmit_AArch64ISD_STRICT_FCMPE_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5734 default: return 0; 5735 } 5736} 5737 5738// FastEmit functions for AArch64ISD::TBL. 5739 5740unsigned fastEmit_AArch64ISD_TBL_MVT_nxv16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5741 if (RetVT.SimpleTy != MVT::nxv16i8) 5742 return 0; 5743 if ((Subtarget->hasSVE())) { 5744 return fastEmitInst_rr(AArch64::TBL_ZZZ_B, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5745 } 5746 return 0; 5747} 5748 5749unsigned fastEmit_AArch64ISD_TBL_MVT_nxv8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5750 if (RetVT.SimpleTy != MVT::nxv8i16) 5751 return 0; 5752 if ((Subtarget->hasSVE())) { 5753 return fastEmitInst_rr(AArch64::TBL_ZZZ_H, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5754 } 5755 return 0; 5756} 5757 5758unsigned fastEmit_AArch64ISD_TBL_MVT_nxv4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5759 if (RetVT.SimpleTy != MVT::nxv4i32) 5760 return 0; 5761 if ((Subtarget->hasSVE())) { 5762 return fastEmitInst_rr(AArch64::TBL_ZZZ_S, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5763 } 5764 return 0; 5765} 5766 5767unsigned fastEmit_AArch64ISD_TBL_MVT_nxv2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5768 if (RetVT.SimpleTy != MVT::nxv2i64) 5769 return 0; 5770 if ((Subtarget->hasSVE())) { 5771 return fastEmitInst_rr(AArch64::TBL_ZZZ_D, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5772 } 5773 return 0; 5774} 5775 5776unsigned fastEmit_AArch64ISD_TBL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5777 switch (VT.SimpleTy) { 5778 case MVT::nxv16i8: return fastEmit_AArch64ISD_TBL_MVT_nxv16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5779 case MVT::nxv8i16: return fastEmit_AArch64ISD_TBL_MVT_nxv8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5780 case MVT::nxv4i32: return fastEmit_AArch64ISD_TBL_MVT_nxv4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5781 case MVT::nxv2i64: return fastEmit_AArch64ISD_TBL_MVT_nxv2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5782 default: return 0; 5783 } 5784} 5785 5786// FastEmit functions for AArch64ISD::TRN1. 5787 5788unsigned fastEmit_AArch64ISD_TRN1_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5789 if (RetVT.SimpleTy != MVT::v8i8) 5790 return 0; 5791 if ((Subtarget->hasNEON())) { 5792 return fastEmitInst_rr(AArch64::TRN1v8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5793 } 5794 return 0; 5795} 5796 5797unsigned fastEmit_AArch64ISD_TRN1_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5798 if (RetVT.SimpleTy != MVT::v16i8) 5799 return 0; 5800 if ((Subtarget->hasNEON())) { 5801 return fastEmitInst_rr(AArch64::TRN1v16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5802 } 5803 return 0; 5804} 5805 5806unsigned fastEmit_AArch64ISD_TRN1_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5807 if (RetVT.SimpleTy != MVT::v4i16) 5808 return 0; 5809 if ((Subtarget->hasNEON())) { 5810 return fastEmitInst_rr(AArch64::TRN1v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5811 } 5812 return 0; 5813} 5814 5815unsigned fastEmit_AArch64ISD_TRN1_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5816 if (RetVT.SimpleTy != MVT::v8i16) 5817 return 0; 5818 if ((Subtarget->hasNEON())) { 5819 return fastEmitInst_rr(AArch64::TRN1v8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5820 } 5821 return 0; 5822} 5823 5824unsigned fastEmit_AArch64ISD_TRN1_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5825 if (RetVT.SimpleTy != MVT::v2i32) 5826 return 0; 5827 if ((Subtarget->hasNEON())) { 5828 return fastEmitInst_rr(AArch64::TRN1v2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5829 } 5830 return 0; 5831} 5832 5833unsigned fastEmit_AArch64ISD_TRN1_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5834 if (RetVT.SimpleTy != MVT::v4i32) 5835 return 0; 5836 if ((Subtarget->hasNEON())) { 5837 return fastEmitInst_rr(AArch64::TRN1v4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5838 } 5839 return 0; 5840} 5841 5842unsigned fastEmit_AArch64ISD_TRN1_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5843 if (RetVT.SimpleTy != MVT::v2i64) 5844 return 0; 5845 if ((Subtarget->hasNEON())) { 5846 return fastEmitInst_rr(AArch64::TRN1v2i64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5847 } 5848 return 0; 5849} 5850 5851unsigned fastEmit_AArch64ISD_TRN1_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5852 if (RetVT.SimpleTy != MVT::v4f16) 5853 return 0; 5854 if ((Subtarget->hasNEON())) { 5855 return fastEmitInst_rr(AArch64::TRN1v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5856 } 5857 return 0; 5858} 5859 5860unsigned fastEmit_AArch64ISD_TRN1_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5861 if (RetVT.SimpleTy != MVT::v8f16) 5862 return 0; 5863 if ((Subtarget->hasNEON())) { 5864 return fastEmitInst_rr(AArch64::TRN1v8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5865 } 5866 return 0; 5867} 5868 5869unsigned fastEmit_AArch64ISD_TRN1_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5870 if (RetVT.SimpleTy != MVT::v2f32) 5871 return 0; 5872 if ((Subtarget->hasNEON())) { 5873 return fastEmitInst_rr(AArch64::TRN1v2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5874 } 5875 return 0; 5876} 5877 5878unsigned fastEmit_AArch64ISD_TRN1_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5879 if (RetVT.SimpleTy != MVT::v4f32) 5880 return 0; 5881 if ((Subtarget->hasNEON())) { 5882 return fastEmitInst_rr(AArch64::TRN1v4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5883 } 5884 return 0; 5885} 5886 5887unsigned fastEmit_AArch64ISD_TRN1_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5888 if (RetVT.SimpleTy != MVT::v2f64) 5889 return 0; 5890 if ((Subtarget->hasNEON())) { 5891 return fastEmitInst_rr(AArch64::TRN1v2i64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5892 } 5893 return 0; 5894} 5895 5896unsigned fastEmit_AArch64ISD_TRN1_MVT_nxv2i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5897 if (RetVT.SimpleTy != MVT::nxv2i1) 5898 return 0; 5899 if ((Subtarget->hasSVE())) { 5900 return fastEmitInst_rr(AArch64::TRN1_PPP_D, &AArch64::PPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5901 } 5902 return 0; 5903} 5904 5905unsigned fastEmit_AArch64ISD_TRN1_MVT_nxv4i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5906 if (RetVT.SimpleTy != MVT::nxv4i1) 5907 return 0; 5908 if ((Subtarget->hasSVE())) { 5909 return fastEmitInst_rr(AArch64::TRN1_PPP_S, &AArch64::PPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5910 } 5911 return 0; 5912} 5913 5914unsigned fastEmit_AArch64ISD_TRN1_MVT_nxv8i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5915 if (RetVT.SimpleTy != MVT::nxv8i1) 5916 return 0; 5917 if ((Subtarget->hasSVE())) { 5918 return fastEmitInst_rr(AArch64::TRN1_PPP_H, &AArch64::PPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5919 } 5920 return 0; 5921} 5922 5923unsigned fastEmit_AArch64ISD_TRN1_MVT_nxv16i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5924 if (RetVT.SimpleTy != MVT::nxv16i1) 5925 return 0; 5926 if ((Subtarget->hasSVE())) { 5927 return fastEmitInst_rr(AArch64::TRN1_PPP_B, &AArch64::PPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5928 } 5929 return 0; 5930} 5931 5932unsigned fastEmit_AArch64ISD_TRN1_MVT_nxv16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5933 if (RetVT.SimpleTy != MVT::nxv16i8) 5934 return 0; 5935 if ((Subtarget->hasSVE())) { 5936 return fastEmitInst_rr(AArch64::TRN1_ZZZ_B, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5937 } 5938 return 0; 5939} 5940 5941unsigned fastEmit_AArch64ISD_TRN1_MVT_nxv8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5942 if (RetVT.SimpleTy != MVT::nxv8i16) 5943 return 0; 5944 if ((Subtarget->hasSVE())) { 5945 return fastEmitInst_rr(AArch64::TRN1_ZZZ_H, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5946 } 5947 return 0; 5948} 5949 5950unsigned fastEmit_AArch64ISD_TRN1_MVT_nxv4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5951 if (RetVT.SimpleTy != MVT::nxv4i32) 5952 return 0; 5953 if ((Subtarget->hasSVE())) { 5954 return fastEmitInst_rr(AArch64::TRN1_ZZZ_S, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5955 } 5956 return 0; 5957} 5958 5959unsigned fastEmit_AArch64ISD_TRN1_MVT_nxv2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5960 if (RetVT.SimpleTy != MVT::nxv2i64) 5961 return 0; 5962 if ((Subtarget->hasSVE())) { 5963 return fastEmitInst_rr(AArch64::TRN1_ZZZ_D, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5964 } 5965 return 0; 5966} 5967 5968unsigned fastEmit_AArch64ISD_TRN1_MVT_nxv4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5969 if (RetVT.SimpleTy != MVT::nxv4f16) 5970 return 0; 5971 if ((Subtarget->hasSVE())) { 5972 return fastEmitInst_rr(AArch64::TRN1_ZZZ_S, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5973 } 5974 return 0; 5975} 5976 5977unsigned fastEmit_AArch64ISD_TRN1_MVT_nxv8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5978 if (RetVT.SimpleTy != MVT::nxv8f16) 5979 return 0; 5980 if ((Subtarget->hasSVE())) { 5981 return fastEmitInst_rr(AArch64::TRN1_ZZZ_H, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5982 } 5983 return 0; 5984} 5985 5986unsigned fastEmit_AArch64ISD_TRN1_MVT_nxv4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5987 if (RetVT.SimpleTy != MVT::nxv4f32) 5988 return 0; 5989 if ((Subtarget->hasSVE())) { 5990 return fastEmitInst_rr(AArch64::TRN1_ZZZ_S, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5991 } 5992 return 0; 5993} 5994 5995unsigned fastEmit_AArch64ISD_TRN1_MVT_nxv2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5996 if (RetVT.SimpleTy != MVT::nxv2f64) 5997 return 0; 5998 if ((Subtarget->hasSVE())) { 5999 return fastEmitInst_rr(AArch64::TRN1_ZZZ_D, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6000 } 6001 return 0; 6002} 6003 6004unsigned fastEmit_AArch64ISD_TRN1_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6005 switch (VT.SimpleTy) { 6006 case MVT::v8i8: return fastEmit_AArch64ISD_TRN1_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6007 case MVT::v16i8: return fastEmit_AArch64ISD_TRN1_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6008 case MVT::v4i16: return fastEmit_AArch64ISD_TRN1_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6009 case MVT::v8i16: return fastEmit_AArch64ISD_TRN1_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6010 case MVT::v2i32: return fastEmit_AArch64ISD_TRN1_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6011 case MVT::v4i32: return fastEmit_AArch64ISD_TRN1_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6012 case MVT::v2i64: return fastEmit_AArch64ISD_TRN1_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6013 case MVT::v4f16: return fastEmit_AArch64ISD_TRN1_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6014 case MVT::v8f16: return fastEmit_AArch64ISD_TRN1_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6015 case MVT::v2f32: return fastEmit_AArch64ISD_TRN1_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6016 case MVT::v4f32: return fastEmit_AArch64ISD_TRN1_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6017 case MVT::v2f64: return fastEmit_AArch64ISD_TRN1_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6018 case MVT::nxv2i1: return fastEmit_AArch64ISD_TRN1_MVT_nxv2i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6019 case MVT::nxv4i1: return fastEmit_AArch64ISD_TRN1_MVT_nxv4i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6020 case MVT::nxv8i1: return fastEmit_AArch64ISD_TRN1_MVT_nxv8i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6021 case MVT::nxv16i1: return fastEmit_AArch64ISD_TRN1_MVT_nxv16i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6022 case MVT::nxv16i8: return fastEmit_AArch64ISD_TRN1_MVT_nxv16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6023 case MVT::nxv8i16: return fastEmit_AArch64ISD_TRN1_MVT_nxv8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6024 case MVT::nxv4i32: return fastEmit_AArch64ISD_TRN1_MVT_nxv4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6025 case MVT::nxv2i64: return fastEmit_AArch64ISD_TRN1_MVT_nxv2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6026 case MVT::nxv4f16: return fastEmit_AArch64ISD_TRN1_MVT_nxv4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6027 case MVT::nxv8f16: return fastEmit_AArch64ISD_TRN1_MVT_nxv8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6028 case MVT::nxv4f32: return fastEmit_AArch64ISD_TRN1_MVT_nxv4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6029 case MVT::nxv2f64: return fastEmit_AArch64ISD_TRN1_MVT_nxv2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6030 default: return 0; 6031 } 6032} 6033 6034// FastEmit functions for AArch64ISD::TRN2. 6035 6036unsigned fastEmit_AArch64ISD_TRN2_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6037 if (RetVT.SimpleTy != MVT::v8i8) 6038 return 0; 6039 if ((Subtarget->hasNEON())) { 6040 return fastEmitInst_rr(AArch64::TRN2v8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6041 } 6042 return 0; 6043} 6044 6045unsigned fastEmit_AArch64ISD_TRN2_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6046 if (RetVT.SimpleTy != MVT::v16i8) 6047 return 0; 6048 if ((Subtarget->hasNEON())) { 6049 return fastEmitInst_rr(AArch64::TRN2v16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6050 } 6051 return 0; 6052} 6053 6054unsigned fastEmit_AArch64ISD_TRN2_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6055 if (RetVT.SimpleTy != MVT::v4i16) 6056 return 0; 6057 if ((Subtarget->hasNEON())) { 6058 return fastEmitInst_rr(AArch64::TRN2v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6059 } 6060 return 0; 6061} 6062 6063unsigned fastEmit_AArch64ISD_TRN2_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6064 if (RetVT.SimpleTy != MVT::v8i16) 6065 return 0; 6066 if ((Subtarget->hasNEON())) { 6067 return fastEmitInst_rr(AArch64::TRN2v8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6068 } 6069 return 0; 6070} 6071 6072unsigned fastEmit_AArch64ISD_TRN2_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6073 if (RetVT.SimpleTy != MVT::v2i32) 6074 return 0; 6075 if ((Subtarget->hasNEON())) { 6076 return fastEmitInst_rr(AArch64::TRN2v2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6077 } 6078 return 0; 6079} 6080 6081unsigned fastEmit_AArch64ISD_TRN2_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6082 if (RetVT.SimpleTy != MVT::v4i32) 6083 return 0; 6084 if ((Subtarget->hasNEON())) { 6085 return fastEmitInst_rr(AArch64::TRN2v4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6086 } 6087 return 0; 6088} 6089 6090unsigned fastEmit_AArch64ISD_TRN2_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6091 if (RetVT.SimpleTy != MVT::v2i64) 6092 return 0; 6093 if ((Subtarget->hasNEON())) { 6094 return fastEmitInst_rr(AArch64::TRN2v2i64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6095 } 6096 return 0; 6097} 6098 6099unsigned fastEmit_AArch64ISD_TRN2_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6100 if (RetVT.SimpleTy != MVT::v4f16) 6101 return 0; 6102 if ((Subtarget->hasNEON())) { 6103 return fastEmitInst_rr(AArch64::TRN2v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6104 } 6105 return 0; 6106} 6107 6108unsigned fastEmit_AArch64ISD_TRN2_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6109 if (RetVT.SimpleTy != MVT::v8f16) 6110 return 0; 6111 if ((Subtarget->hasNEON())) { 6112 return fastEmitInst_rr(AArch64::TRN2v8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6113 } 6114 return 0; 6115} 6116 6117unsigned fastEmit_AArch64ISD_TRN2_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6118 if (RetVT.SimpleTy != MVT::v2f32) 6119 return 0; 6120 if ((Subtarget->hasNEON())) { 6121 return fastEmitInst_rr(AArch64::TRN2v2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6122 } 6123 return 0; 6124} 6125 6126unsigned fastEmit_AArch64ISD_TRN2_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6127 if (RetVT.SimpleTy != MVT::v4f32) 6128 return 0; 6129 if ((Subtarget->hasNEON())) { 6130 return fastEmitInst_rr(AArch64::TRN2v4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6131 } 6132 return 0; 6133} 6134 6135unsigned fastEmit_AArch64ISD_TRN2_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6136 if (RetVT.SimpleTy != MVT::v2f64) 6137 return 0; 6138 if ((Subtarget->hasNEON())) { 6139 return fastEmitInst_rr(AArch64::TRN2v2i64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6140 } 6141 return 0; 6142} 6143 6144unsigned fastEmit_AArch64ISD_TRN2_MVT_nxv2i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6145 if (RetVT.SimpleTy != MVT::nxv2i1) 6146 return 0; 6147 if ((Subtarget->hasSVE())) { 6148 return fastEmitInst_rr(AArch64::TRN2_PPP_D, &AArch64::PPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6149 } 6150 return 0; 6151} 6152 6153unsigned fastEmit_AArch64ISD_TRN2_MVT_nxv4i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6154 if (RetVT.SimpleTy != MVT::nxv4i1) 6155 return 0; 6156 if ((Subtarget->hasSVE())) { 6157 return fastEmitInst_rr(AArch64::TRN2_PPP_S, &AArch64::PPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6158 } 6159 return 0; 6160} 6161 6162unsigned fastEmit_AArch64ISD_TRN2_MVT_nxv8i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6163 if (RetVT.SimpleTy != MVT::nxv8i1) 6164 return 0; 6165 if ((Subtarget->hasSVE())) { 6166 return fastEmitInst_rr(AArch64::TRN2_PPP_H, &AArch64::PPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6167 } 6168 return 0; 6169} 6170 6171unsigned fastEmit_AArch64ISD_TRN2_MVT_nxv16i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6172 if (RetVT.SimpleTy != MVT::nxv16i1) 6173 return 0; 6174 if ((Subtarget->hasSVE())) { 6175 return fastEmitInst_rr(AArch64::TRN2_PPP_B, &AArch64::PPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6176 } 6177 return 0; 6178} 6179 6180unsigned fastEmit_AArch64ISD_TRN2_MVT_nxv16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6181 if (RetVT.SimpleTy != MVT::nxv16i8) 6182 return 0; 6183 if ((Subtarget->hasSVE())) { 6184 return fastEmitInst_rr(AArch64::TRN2_ZZZ_B, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6185 } 6186 return 0; 6187} 6188 6189unsigned fastEmit_AArch64ISD_TRN2_MVT_nxv8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6190 if (RetVT.SimpleTy != MVT::nxv8i16) 6191 return 0; 6192 if ((Subtarget->hasSVE())) { 6193 return fastEmitInst_rr(AArch64::TRN2_ZZZ_H, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6194 } 6195 return 0; 6196} 6197 6198unsigned fastEmit_AArch64ISD_TRN2_MVT_nxv4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6199 if (RetVT.SimpleTy != MVT::nxv4i32) 6200 return 0; 6201 if ((Subtarget->hasSVE())) { 6202 return fastEmitInst_rr(AArch64::TRN2_ZZZ_S, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6203 } 6204 return 0; 6205} 6206 6207unsigned fastEmit_AArch64ISD_TRN2_MVT_nxv2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6208 if (RetVT.SimpleTy != MVT::nxv2i64) 6209 return 0; 6210 if ((Subtarget->hasSVE())) { 6211 return fastEmitInst_rr(AArch64::TRN2_ZZZ_D, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6212 } 6213 return 0; 6214} 6215 6216unsigned fastEmit_AArch64ISD_TRN2_MVT_nxv4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6217 if (RetVT.SimpleTy != MVT::nxv4f16) 6218 return 0; 6219 if ((Subtarget->hasSVE())) { 6220 return fastEmitInst_rr(AArch64::TRN2_ZZZ_S, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6221 } 6222 return 0; 6223} 6224 6225unsigned fastEmit_AArch64ISD_TRN2_MVT_nxv8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6226 if (RetVT.SimpleTy != MVT::nxv8f16) 6227 return 0; 6228 if ((Subtarget->hasSVE())) { 6229 return fastEmitInst_rr(AArch64::TRN2_ZZZ_H, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6230 } 6231 return 0; 6232} 6233 6234unsigned fastEmit_AArch64ISD_TRN2_MVT_nxv4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6235 if (RetVT.SimpleTy != MVT::nxv4f32) 6236 return 0; 6237 if ((Subtarget->hasSVE())) { 6238 return fastEmitInst_rr(AArch64::TRN2_ZZZ_S, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6239 } 6240 return 0; 6241} 6242 6243unsigned fastEmit_AArch64ISD_TRN2_MVT_nxv2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6244 if (RetVT.SimpleTy != MVT::nxv2f64) 6245 return 0; 6246 if ((Subtarget->hasSVE())) { 6247 return fastEmitInst_rr(AArch64::TRN2_ZZZ_D, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6248 } 6249 return 0; 6250} 6251 6252unsigned fastEmit_AArch64ISD_TRN2_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6253 switch (VT.SimpleTy) { 6254 case MVT::v8i8: return fastEmit_AArch64ISD_TRN2_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6255 case MVT::v16i8: return fastEmit_AArch64ISD_TRN2_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6256 case MVT::v4i16: return fastEmit_AArch64ISD_TRN2_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6257 case MVT::v8i16: return fastEmit_AArch64ISD_TRN2_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6258 case MVT::v2i32: return fastEmit_AArch64ISD_TRN2_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6259 case MVT::v4i32: return fastEmit_AArch64ISD_TRN2_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6260 case MVT::v2i64: return fastEmit_AArch64ISD_TRN2_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6261 case MVT::v4f16: return fastEmit_AArch64ISD_TRN2_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6262 case MVT::v8f16: return fastEmit_AArch64ISD_TRN2_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6263 case MVT::v2f32: return fastEmit_AArch64ISD_TRN2_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6264 case MVT::v4f32: return fastEmit_AArch64ISD_TRN2_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6265 case MVT::v2f64: return fastEmit_AArch64ISD_TRN2_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6266 case MVT::nxv2i1: return fastEmit_AArch64ISD_TRN2_MVT_nxv2i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6267 case MVT::nxv4i1: return fastEmit_AArch64ISD_TRN2_MVT_nxv4i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6268 case MVT::nxv8i1: return fastEmit_AArch64ISD_TRN2_MVT_nxv8i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6269 case MVT::nxv16i1: return fastEmit_AArch64ISD_TRN2_MVT_nxv16i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6270 case MVT::nxv16i8: return fastEmit_AArch64ISD_TRN2_MVT_nxv16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6271 case MVT::nxv8i16: return fastEmit_AArch64ISD_TRN2_MVT_nxv8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6272 case MVT::nxv4i32: return fastEmit_AArch64ISD_TRN2_MVT_nxv4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6273 case MVT::nxv2i64: return fastEmit_AArch64ISD_TRN2_MVT_nxv2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6274 case MVT::nxv4f16: return fastEmit_AArch64ISD_TRN2_MVT_nxv4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6275 case MVT::nxv8f16: return fastEmit_AArch64ISD_TRN2_MVT_nxv8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6276 case MVT::nxv4f32: return fastEmit_AArch64ISD_TRN2_MVT_nxv4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6277 case MVT::nxv2f64: return fastEmit_AArch64ISD_TRN2_MVT_nxv2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6278 default: return 0; 6279 } 6280} 6281 6282// FastEmit functions for AArch64ISD::UMULL. 6283 6284unsigned fastEmit_AArch64ISD_UMULL_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6285 if (RetVT.SimpleTy != MVT::v8i16) 6286 return 0; 6287 return fastEmitInst_rr(AArch64::UMULLv8i8_v8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6288} 6289 6290unsigned fastEmit_AArch64ISD_UMULL_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6291 if (RetVT.SimpleTy != MVT::v4i32) 6292 return 0; 6293 return fastEmitInst_rr(AArch64::UMULLv4i16_v4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6294} 6295 6296unsigned fastEmit_AArch64ISD_UMULL_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6297 if (RetVT.SimpleTy != MVT::v2i64) 6298 return 0; 6299 return fastEmitInst_rr(AArch64::UMULLv2i32_v2i64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6300} 6301 6302unsigned fastEmit_AArch64ISD_UMULL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6303 switch (VT.SimpleTy) { 6304 case MVT::v8i8: return fastEmit_AArch64ISD_UMULL_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6305 case MVT::v4i16: return fastEmit_AArch64ISD_UMULL_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6306 case MVT::v2i32: return fastEmit_AArch64ISD_UMULL_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6307 default: return 0; 6308 } 6309} 6310 6311// FastEmit functions for AArch64ISD::UZP1. 6312 6313unsigned fastEmit_AArch64ISD_UZP1_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6314 if (RetVT.SimpleTy != MVT::v8i8) 6315 return 0; 6316 if ((Subtarget->hasNEON())) { 6317 return fastEmitInst_rr(AArch64::UZP1v8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6318 } 6319 return 0; 6320} 6321 6322unsigned fastEmit_AArch64ISD_UZP1_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6323 if (RetVT.SimpleTy != MVT::v16i8) 6324 return 0; 6325 if ((Subtarget->hasNEON())) { 6326 return fastEmitInst_rr(AArch64::UZP1v16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6327 } 6328 return 0; 6329} 6330 6331unsigned fastEmit_AArch64ISD_UZP1_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6332 if (RetVT.SimpleTy != MVT::v4i16) 6333 return 0; 6334 if ((Subtarget->hasNEON())) { 6335 return fastEmitInst_rr(AArch64::UZP1v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6336 } 6337 return 0; 6338} 6339 6340unsigned fastEmit_AArch64ISD_UZP1_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6341 if (RetVT.SimpleTy != MVT::v8i16) 6342 return 0; 6343 if ((Subtarget->hasNEON())) { 6344 return fastEmitInst_rr(AArch64::UZP1v8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6345 } 6346 return 0; 6347} 6348 6349unsigned fastEmit_AArch64ISD_UZP1_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6350 if (RetVT.SimpleTy != MVT::v2i32) 6351 return 0; 6352 if ((Subtarget->hasNEON())) { 6353 return fastEmitInst_rr(AArch64::UZP1v2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6354 } 6355 return 0; 6356} 6357 6358unsigned fastEmit_AArch64ISD_UZP1_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6359 if (RetVT.SimpleTy != MVT::v4i32) 6360 return 0; 6361 if ((Subtarget->hasNEON())) { 6362 return fastEmitInst_rr(AArch64::UZP1v4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6363 } 6364 return 0; 6365} 6366 6367unsigned fastEmit_AArch64ISD_UZP1_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6368 if (RetVT.SimpleTy != MVT::v2i64) 6369 return 0; 6370 if ((Subtarget->hasNEON())) { 6371 return fastEmitInst_rr(AArch64::UZP1v2i64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6372 } 6373 return 0; 6374} 6375 6376unsigned fastEmit_AArch64ISD_UZP1_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6377 if (RetVT.SimpleTy != MVT::v4f16) 6378 return 0; 6379 if ((Subtarget->hasNEON())) { 6380 return fastEmitInst_rr(AArch64::UZP1v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6381 } 6382 return 0; 6383} 6384 6385unsigned fastEmit_AArch64ISD_UZP1_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6386 if (RetVT.SimpleTy != MVT::v8f16) 6387 return 0; 6388 if ((Subtarget->hasNEON())) { 6389 return fastEmitInst_rr(AArch64::UZP1v8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6390 } 6391 return 0; 6392} 6393 6394unsigned fastEmit_AArch64ISD_UZP1_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6395 if (RetVT.SimpleTy != MVT::v2f32) 6396 return 0; 6397 if ((Subtarget->hasNEON())) { 6398 return fastEmitInst_rr(AArch64::UZP1v2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6399 } 6400 return 0; 6401} 6402 6403unsigned fastEmit_AArch64ISD_UZP1_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6404 if (RetVT.SimpleTy != MVT::v4f32) 6405 return 0; 6406 if ((Subtarget->hasNEON())) { 6407 return fastEmitInst_rr(AArch64::UZP1v4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6408 } 6409 return 0; 6410} 6411 6412unsigned fastEmit_AArch64ISD_UZP1_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6413 if (RetVT.SimpleTy != MVT::v2f64) 6414 return 0; 6415 if ((Subtarget->hasNEON())) { 6416 return fastEmitInst_rr(AArch64::UZP1v2i64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6417 } 6418 return 0; 6419} 6420 6421unsigned fastEmit_AArch64ISD_UZP1_MVT_nxv2i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6422 if (RetVT.SimpleTy != MVT::nxv2i1) 6423 return 0; 6424 if ((Subtarget->hasSVE())) { 6425 return fastEmitInst_rr(AArch64::UZP1_PPP_D, &AArch64::PPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6426 } 6427 return 0; 6428} 6429 6430unsigned fastEmit_AArch64ISD_UZP1_MVT_nxv4i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6431 if (RetVT.SimpleTy != MVT::nxv4i1) 6432 return 0; 6433 if ((Subtarget->hasSVE())) { 6434 return fastEmitInst_rr(AArch64::UZP1_PPP_S, &AArch64::PPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6435 } 6436 return 0; 6437} 6438 6439unsigned fastEmit_AArch64ISD_UZP1_MVT_nxv8i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6440 if (RetVT.SimpleTy != MVT::nxv8i1) 6441 return 0; 6442 if ((Subtarget->hasSVE())) { 6443 return fastEmitInst_rr(AArch64::UZP1_PPP_H, &AArch64::PPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6444 } 6445 return 0; 6446} 6447 6448unsigned fastEmit_AArch64ISD_UZP1_MVT_nxv16i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6449 if (RetVT.SimpleTy != MVT::nxv16i1) 6450 return 0; 6451 if ((Subtarget->hasSVE())) { 6452 return fastEmitInst_rr(AArch64::UZP1_PPP_B, &AArch64::PPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6453 } 6454 return 0; 6455} 6456 6457unsigned fastEmit_AArch64ISD_UZP1_MVT_nxv16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6458 if (RetVT.SimpleTy != MVT::nxv16i8) 6459 return 0; 6460 if ((Subtarget->hasSVE())) { 6461 return fastEmitInst_rr(AArch64::UZP1_ZZZ_B, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6462 } 6463 return 0; 6464} 6465 6466unsigned fastEmit_AArch64ISD_UZP1_MVT_nxv8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6467 if (RetVT.SimpleTy != MVT::nxv8i16) 6468 return 0; 6469 if ((Subtarget->hasSVE())) { 6470 return fastEmitInst_rr(AArch64::UZP1_ZZZ_H, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6471 } 6472 return 0; 6473} 6474 6475unsigned fastEmit_AArch64ISD_UZP1_MVT_nxv4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6476 if (RetVT.SimpleTy != MVT::nxv4i32) 6477 return 0; 6478 if ((Subtarget->hasSVE())) { 6479 return fastEmitInst_rr(AArch64::UZP1_ZZZ_S, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6480 } 6481 return 0; 6482} 6483 6484unsigned fastEmit_AArch64ISD_UZP1_MVT_nxv2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6485 if (RetVT.SimpleTy != MVT::nxv2i64) 6486 return 0; 6487 if ((Subtarget->hasSVE())) { 6488 return fastEmitInst_rr(AArch64::UZP1_ZZZ_D, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6489 } 6490 return 0; 6491} 6492 6493unsigned fastEmit_AArch64ISD_UZP1_MVT_nxv4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6494 if (RetVT.SimpleTy != MVT::nxv4f16) 6495 return 0; 6496 if ((Subtarget->hasSVE())) { 6497 return fastEmitInst_rr(AArch64::UZP1_ZZZ_S, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6498 } 6499 return 0; 6500} 6501 6502unsigned fastEmit_AArch64ISD_UZP1_MVT_nxv8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6503 if (RetVT.SimpleTy != MVT::nxv8f16) 6504 return 0; 6505 if ((Subtarget->hasSVE())) { 6506 return fastEmitInst_rr(AArch64::UZP1_ZZZ_H, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6507 } 6508 return 0; 6509} 6510 6511unsigned fastEmit_AArch64ISD_UZP1_MVT_nxv4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6512 if (RetVT.SimpleTy != MVT::nxv4f32) 6513 return 0; 6514 if ((Subtarget->hasSVE())) { 6515 return fastEmitInst_rr(AArch64::UZP1_ZZZ_S, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6516 } 6517 return 0; 6518} 6519 6520unsigned fastEmit_AArch64ISD_UZP1_MVT_nxv2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6521 if (RetVT.SimpleTy != MVT::nxv2f64) 6522 return 0; 6523 if ((Subtarget->hasSVE())) { 6524 return fastEmitInst_rr(AArch64::UZP1_ZZZ_D, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6525 } 6526 return 0; 6527} 6528 6529unsigned fastEmit_AArch64ISD_UZP1_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6530 switch (VT.SimpleTy) { 6531 case MVT::v8i8: return fastEmit_AArch64ISD_UZP1_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6532 case MVT::v16i8: return fastEmit_AArch64ISD_UZP1_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6533 case MVT::v4i16: return fastEmit_AArch64ISD_UZP1_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6534 case MVT::v8i16: return fastEmit_AArch64ISD_UZP1_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6535 case MVT::v2i32: return fastEmit_AArch64ISD_UZP1_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6536 case MVT::v4i32: return fastEmit_AArch64ISD_UZP1_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6537 case MVT::v2i64: return fastEmit_AArch64ISD_UZP1_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6538 case MVT::v4f16: return fastEmit_AArch64ISD_UZP1_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6539 case MVT::v8f16: return fastEmit_AArch64ISD_UZP1_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6540 case MVT::v2f32: return fastEmit_AArch64ISD_UZP1_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6541 case MVT::v4f32: return fastEmit_AArch64ISD_UZP1_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6542 case MVT::v2f64: return fastEmit_AArch64ISD_UZP1_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6543 case MVT::nxv2i1: return fastEmit_AArch64ISD_UZP1_MVT_nxv2i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6544 case MVT::nxv4i1: return fastEmit_AArch64ISD_UZP1_MVT_nxv4i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6545 case MVT::nxv8i1: return fastEmit_AArch64ISD_UZP1_MVT_nxv8i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6546 case MVT::nxv16i1: return fastEmit_AArch64ISD_UZP1_MVT_nxv16i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6547 case MVT::nxv16i8: return fastEmit_AArch64ISD_UZP1_MVT_nxv16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6548 case MVT::nxv8i16: return fastEmit_AArch64ISD_UZP1_MVT_nxv8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6549 case MVT::nxv4i32: return fastEmit_AArch64ISD_UZP1_MVT_nxv4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6550 case MVT::nxv2i64: return fastEmit_AArch64ISD_UZP1_MVT_nxv2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6551 case MVT::nxv4f16: return fastEmit_AArch64ISD_UZP1_MVT_nxv4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6552 case MVT::nxv8f16: return fastEmit_AArch64ISD_UZP1_MVT_nxv8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6553 case MVT::nxv4f32: return fastEmit_AArch64ISD_UZP1_MVT_nxv4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6554 case MVT::nxv2f64: return fastEmit_AArch64ISD_UZP1_MVT_nxv2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6555 default: return 0; 6556 } 6557} 6558 6559// FastEmit functions for AArch64ISD::UZP2. 6560 6561unsigned fastEmit_AArch64ISD_UZP2_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6562 if (RetVT.SimpleTy != MVT::v8i8) 6563 return 0; 6564 if ((Subtarget->hasNEON())) { 6565 return fastEmitInst_rr(AArch64::UZP2v8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6566 } 6567 return 0; 6568} 6569 6570unsigned fastEmit_AArch64ISD_UZP2_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6571 if (RetVT.SimpleTy != MVT::v16i8) 6572 return 0; 6573 if ((Subtarget->hasNEON())) { 6574 return fastEmitInst_rr(AArch64::UZP2v16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6575 } 6576 return 0; 6577} 6578 6579unsigned fastEmit_AArch64ISD_UZP2_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6580 if (RetVT.SimpleTy != MVT::v4i16) 6581 return 0; 6582 if ((Subtarget->hasNEON())) { 6583 return fastEmitInst_rr(AArch64::UZP2v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6584 } 6585 return 0; 6586} 6587 6588unsigned fastEmit_AArch64ISD_UZP2_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6589 if (RetVT.SimpleTy != MVT::v8i16) 6590 return 0; 6591 if ((Subtarget->hasNEON())) { 6592 return fastEmitInst_rr(AArch64::UZP2v8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6593 } 6594 return 0; 6595} 6596 6597unsigned fastEmit_AArch64ISD_UZP2_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6598 if (RetVT.SimpleTy != MVT::v2i32) 6599 return 0; 6600 if ((Subtarget->hasNEON())) { 6601 return fastEmitInst_rr(AArch64::UZP2v2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6602 } 6603 return 0; 6604} 6605 6606unsigned fastEmit_AArch64ISD_UZP2_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6607 if (RetVT.SimpleTy != MVT::v4i32) 6608 return 0; 6609 if ((Subtarget->hasNEON())) { 6610 return fastEmitInst_rr(AArch64::UZP2v4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6611 } 6612 return 0; 6613} 6614 6615unsigned fastEmit_AArch64ISD_UZP2_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6616 if (RetVT.SimpleTy != MVT::v2i64) 6617 return 0; 6618 if ((Subtarget->hasNEON())) { 6619 return fastEmitInst_rr(AArch64::UZP2v2i64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6620 } 6621 return 0; 6622} 6623 6624unsigned fastEmit_AArch64ISD_UZP2_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6625 if (RetVT.SimpleTy != MVT::v4f16) 6626 return 0; 6627 if ((Subtarget->hasNEON())) { 6628 return fastEmitInst_rr(AArch64::UZP2v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6629 } 6630 return 0; 6631} 6632 6633unsigned fastEmit_AArch64ISD_UZP2_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6634 if (RetVT.SimpleTy != MVT::v8f16) 6635 return 0; 6636 if ((Subtarget->hasNEON())) { 6637 return fastEmitInst_rr(AArch64::UZP2v8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6638 } 6639 return 0; 6640} 6641 6642unsigned fastEmit_AArch64ISD_UZP2_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6643 if (RetVT.SimpleTy != MVT::v2f32) 6644 return 0; 6645 if ((Subtarget->hasNEON())) { 6646 return fastEmitInst_rr(AArch64::UZP2v2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6647 } 6648 return 0; 6649} 6650 6651unsigned fastEmit_AArch64ISD_UZP2_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6652 if (RetVT.SimpleTy != MVT::v4f32) 6653 return 0; 6654 if ((Subtarget->hasNEON())) { 6655 return fastEmitInst_rr(AArch64::UZP2v4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6656 } 6657 return 0; 6658} 6659 6660unsigned fastEmit_AArch64ISD_UZP2_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6661 if (RetVT.SimpleTy != MVT::v2f64) 6662 return 0; 6663 if ((Subtarget->hasNEON())) { 6664 return fastEmitInst_rr(AArch64::UZP2v2i64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6665 } 6666 return 0; 6667} 6668 6669unsigned fastEmit_AArch64ISD_UZP2_MVT_nxv2i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6670 if (RetVT.SimpleTy != MVT::nxv2i1) 6671 return 0; 6672 if ((Subtarget->hasSVE())) { 6673 return fastEmitInst_rr(AArch64::UZP2_PPP_D, &AArch64::PPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6674 } 6675 return 0; 6676} 6677 6678unsigned fastEmit_AArch64ISD_UZP2_MVT_nxv4i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6679 if (RetVT.SimpleTy != MVT::nxv4i1) 6680 return 0; 6681 if ((Subtarget->hasSVE())) { 6682 return fastEmitInst_rr(AArch64::UZP2_PPP_S, &AArch64::PPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6683 } 6684 return 0; 6685} 6686 6687unsigned fastEmit_AArch64ISD_UZP2_MVT_nxv8i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6688 if (RetVT.SimpleTy != MVT::nxv8i1) 6689 return 0; 6690 if ((Subtarget->hasSVE())) { 6691 return fastEmitInst_rr(AArch64::UZP2_PPP_H, &AArch64::PPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6692 } 6693 return 0; 6694} 6695 6696unsigned fastEmit_AArch64ISD_UZP2_MVT_nxv16i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6697 if (RetVT.SimpleTy != MVT::nxv16i1) 6698 return 0; 6699 if ((Subtarget->hasSVE())) { 6700 return fastEmitInst_rr(AArch64::UZP2_PPP_B, &AArch64::PPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6701 } 6702 return 0; 6703} 6704 6705unsigned fastEmit_AArch64ISD_UZP2_MVT_nxv16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6706 if (RetVT.SimpleTy != MVT::nxv16i8) 6707 return 0; 6708 if ((Subtarget->hasSVE())) { 6709 return fastEmitInst_rr(AArch64::UZP2_ZZZ_B, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6710 } 6711 return 0; 6712} 6713 6714unsigned fastEmit_AArch64ISD_UZP2_MVT_nxv8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6715 if (RetVT.SimpleTy != MVT::nxv8i16) 6716 return 0; 6717 if ((Subtarget->hasSVE())) { 6718 return fastEmitInst_rr(AArch64::UZP2_ZZZ_H, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6719 } 6720 return 0; 6721} 6722 6723unsigned fastEmit_AArch64ISD_UZP2_MVT_nxv4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6724 if (RetVT.SimpleTy != MVT::nxv4i32) 6725 return 0; 6726 if ((Subtarget->hasSVE())) { 6727 return fastEmitInst_rr(AArch64::UZP2_ZZZ_S, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6728 } 6729 return 0; 6730} 6731 6732unsigned fastEmit_AArch64ISD_UZP2_MVT_nxv2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6733 if (RetVT.SimpleTy != MVT::nxv2i64) 6734 return 0; 6735 if ((Subtarget->hasSVE())) { 6736 return fastEmitInst_rr(AArch64::UZP2_ZZZ_D, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6737 } 6738 return 0; 6739} 6740 6741unsigned fastEmit_AArch64ISD_UZP2_MVT_nxv4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6742 if (RetVT.SimpleTy != MVT::nxv4f16) 6743 return 0; 6744 if ((Subtarget->hasSVE())) { 6745 return fastEmitInst_rr(AArch64::UZP2_ZZZ_S, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6746 } 6747 return 0; 6748} 6749 6750unsigned fastEmit_AArch64ISD_UZP2_MVT_nxv8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6751 if (RetVT.SimpleTy != MVT::nxv8f16) 6752 return 0; 6753 if ((Subtarget->hasSVE())) { 6754 return fastEmitInst_rr(AArch64::UZP2_ZZZ_H, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6755 } 6756 return 0; 6757} 6758 6759unsigned fastEmit_AArch64ISD_UZP2_MVT_nxv4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6760 if (RetVT.SimpleTy != MVT::nxv4f32) 6761 return 0; 6762 if ((Subtarget->hasSVE())) { 6763 return fastEmitInst_rr(AArch64::UZP2_ZZZ_S, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6764 } 6765 return 0; 6766} 6767 6768unsigned fastEmit_AArch64ISD_UZP2_MVT_nxv2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6769 if (RetVT.SimpleTy != MVT::nxv2f64) 6770 return 0; 6771 if ((Subtarget->hasSVE())) { 6772 return fastEmitInst_rr(AArch64::UZP2_ZZZ_D, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6773 } 6774 return 0; 6775} 6776 6777unsigned fastEmit_AArch64ISD_UZP2_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6778 switch (VT.SimpleTy) { 6779 case MVT::v8i8: return fastEmit_AArch64ISD_UZP2_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6780 case MVT::v16i8: return fastEmit_AArch64ISD_UZP2_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6781 case MVT::v4i16: return fastEmit_AArch64ISD_UZP2_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6782 case MVT::v8i16: return fastEmit_AArch64ISD_UZP2_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6783 case MVT::v2i32: return fastEmit_AArch64ISD_UZP2_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6784 case MVT::v4i32: return fastEmit_AArch64ISD_UZP2_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6785 case MVT::v2i64: return fastEmit_AArch64ISD_UZP2_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6786 case MVT::v4f16: return fastEmit_AArch64ISD_UZP2_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6787 case MVT::v8f16: return fastEmit_AArch64ISD_UZP2_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6788 case MVT::v2f32: return fastEmit_AArch64ISD_UZP2_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6789 case MVT::v4f32: return fastEmit_AArch64ISD_UZP2_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6790 case MVT::v2f64: return fastEmit_AArch64ISD_UZP2_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6791 case MVT::nxv2i1: return fastEmit_AArch64ISD_UZP2_MVT_nxv2i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6792 case MVT::nxv4i1: return fastEmit_AArch64ISD_UZP2_MVT_nxv4i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6793 case MVT::nxv8i1: return fastEmit_AArch64ISD_UZP2_MVT_nxv8i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6794 case MVT::nxv16i1: return fastEmit_AArch64ISD_UZP2_MVT_nxv16i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6795 case MVT::nxv16i8: return fastEmit_AArch64ISD_UZP2_MVT_nxv16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6796 case MVT::nxv8i16: return fastEmit_AArch64ISD_UZP2_MVT_nxv8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6797 case MVT::nxv4i32: return fastEmit_AArch64ISD_UZP2_MVT_nxv4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6798 case MVT::nxv2i64: return fastEmit_AArch64ISD_UZP2_MVT_nxv2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6799 case MVT::nxv4f16: return fastEmit_AArch64ISD_UZP2_MVT_nxv4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6800 case MVT::nxv8f16: return fastEmit_AArch64ISD_UZP2_MVT_nxv8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6801 case MVT::nxv4f32: return fastEmit_AArch64ISD_UZP2_MVT_nxv4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6802 case MVT::nxv2f64: return fastEmit_AArch64ISD_UZP2_MVT_nxv2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6803 default: return 0; 6804 } 6805} 6806 6807// FastEmit functions for AArch64ISD::ZIP1. 6808 6809unsigned fastEmit_AArch64ISD_ZIP1_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6810 if (RetVT.SimpleTy != MVT::v8i8) 6811 return 0; 6812 if ((Subtarget->hasNEON())) { 6813 return fastEmitInst_rr(AArch64::ZIP1v8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6814 } 6815 return 0; 6816} 6817 6818unsigned fastEmit_AArch64ISD_ZIP1_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6819 if (RetVT.SimpleTy != MVT::v16i8) 6820 return 0; 6821 if ((Subtarget->hasNEON())) { 6822 return fastEmitInst_rr(AArch64::ZIP1v16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6823 } 6824 return 0; 6825} 6826 6827unsigned fastEmit_AArch64ISD_ZIP1_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6828 if (RetVT.SimpleTy != MVT::v4i16) 6829 return 0; 6830 if ((Subtarget->hasNEON())) { 6831 return fastEmitInst_rr(AArch64::ZIP1v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6832 } 6833 return 0; 6834} 6835 6836unsigned fastEmit_AArch64ISD_ZIP1_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6837 if (RetVT.SimpleTy != MVT::v8i16) 6838 return 0; 6839 if ((Subtarget->hasNEON())) { 6840 return fastEmitInst_rr(AArch64::ZIP1v8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6841 } 6842 return 0; 6843} 6844 6845unsigned fastEmit_AArch64ISD_ZIP1_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6846 if (RetVT.SimpleTy != MVT::v2i32) 6847 return 0; 6848 if ((Subtarget->hasNEON())) { 6849 return fastEmitInst_rr(AArch64::ZIP1v2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6850 } 6851 return 0; 6852} 6853 6854unsigned fastEmit_AArch64ISD_ZIP1_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6855 if (RetVT.SimpleTy != MVT::v4i32) 6856 return 0; 6857 if ((Subtarget->hasNEON())) { 6858 return fastEmitInst_rr(AArch64::ZIP1v4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6859 } 6860 return 0; 6861} 6862 6863unsigned fastEmit_AArch64ISD_ZIP1_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6864 if (RetVT.SimpleTy != MVT::v2i64) 6865 return 0; 6866 if ((Subtarget->hasNEON())) { 6867 return fastEmitInst_rr(AArch64::ZIP1v2i64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6868 } 6869 return 0; 6870} 6871 6872unsigned fastEmit_AArch64ISD_ZIP1_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6873 if (RetVT.SimpleTy != MVT::v4f16) 6874 return 0; 6875 if ((Subtarget->hasNEON())) { 6876 return fastEmitInst_rr(AArch64::ZIP1v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6877 } 6878 return 0; 6879} 6880 6881unsigned fastEmit_AArch64ISD_ZIP1_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6882 if (RetVT.SimpleTy != MVT::v8f16) 6883 return 0; 6884 if ((Subtarget->hasNEON())) { 6885 return fastEmitInst_rr(AArch64::ZIP1v8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6886 } 6887 return 0; 6888} 6889 6890unsigned fastEmit_AArch64ISD_ZIP1_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6891 if (RetVT.SimpleTy != MVT::v2f32) 6892 return 0; 6893 if ((Subtarget->hasNEON())) { 6894 return fastEmitInst_rr(AArch64::ZIP1v2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6895 } 6896 return 0; 6897} 6898 6899unsigned fastEmit_AArch64ISD_ZIP1_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6900 if (RetVT.SimpleTy != MVT::v4f32) 6901 return 0; 6902 if ((Subtarget->hasNEON())) { 6903 return fastEmitInst_rr(AArch64::ZIP1v4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6904 } 6905 return 0; 6906} 6907 6908unsigned fastEmit_AArch64ISD_ZIP1_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6909 if (RetVT.SimpleTy != MVT::v2f64) 6910 return 0; 6911 if ((Subtarget->hasNEON())) { 6912 return fastEmitInst_rr(AArch64::ZIP1v2i64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6913 } 6914 return 0; 6915} 6916 6917unsigned fastEmit_AArch64ISD_ZIP1_MVT_nxv2i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6918 if (RetVT.SimpleTy != MVT::nxv2i1) 6919 return 0; 6920 if ((Subtarget->hasSVE())) { 6921 return fastEmitInst_rr(AArch64::ZIP1_PPP_D, &AArch64::PPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6922 } 6923 return 0; 6924} 6925 6926unsigned fastEmit_AArch64ISD_ZIP1_MVT_nxv4i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6927 if (RetVT.SimpleTy != MVT::nxv4i1) 6928 return 0; 6929 if ((Subtarget->hasSVE())) { 6930 return fastEmitInst_rr(AArch64::ZIP1_PPP_S, &AArch64::PPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6931 } 6932 return 0; 6933} 6934 6935unsigned fastEmit_AArch64ISD_ZIP1_MVT_nxv8i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6936 if (RetVT.SimpleTy != MVT::nxv8i1) 6937 return 0; 6938 if ((Subtarget->hasSVE())) { 6939 return fastEmitInst_rr(AArch64::ZIP1_PPP_H, &AArch64::PPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6940 } 6941 return 0; 6942} 6943 6944unsigned fastEmit_AArch64ISD_ZIP1_MVT_nxv16i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6945 if (RetVT.SimpleTy != MVT::nxv16i1) 6946 return 0; 6947 if ((Subtarget->hasSVE())) { 6948 return fastEmitInst_rr(AArch64::ZIP1_PPP_B, &AArch64::PPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6949 } 6950 return 0; 6951} 6952 6953unsigned fastEmit_AArch64ISD_ZIP1_MVT_nxv16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6954 if (RetVT.SimpleTy != MVT::nxv16i8) 6955 return 0; 6956 if ((Subtarget->hasSVE())) { 6957 return fastEmitInst_rr(AArch64::ZIP1_ZZZ_B, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6958 } 6959 return 0; 6960} 6961 6962unsigned fastEmit_AArch64ISD_ZIP1_MVT_nxv8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6963 if (RetVT.SimpleTy != MVT::nxv8i16) 6964 return 0; 6965 if ((Subtarget->hasSVE())) { 6966 return fastEmitInst_rr(AArch64::ZIP1_ZZZ_H, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6967 } 6968 return 0; 6969} 6970 6971unsigned fastEmit_AArch64ISD_ZIP1_MVT_nxv4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6972 if (RetVT.SimpleTy != MVT::nxv4i32) 6973 return 0; 6974 if ((Subtarget->hasSVE())) { 6975 return fastEmitInst_rr(AArch64::ZIP1_ZZZ_S, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6976 } 6977 return 0; 6978} 6979 6980unsigned fastEmit_AArch64ISD_ZIP1_MVT_nxv2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6981 if (RetVT.SimpleTy != MVT::nxv2i64) 6982 return 0; 6983 if ((Subtarget->hasSVE())) { 6984 return fastEmitInst_rr(AArch64::ZIP1_ZZZ_D, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6985 } 6986 return 0; 6987} 6988 6989unsigned fastEmit_AArch64ISD_ZIP1_MVT_nxv4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6990 if (RetVT.SimpleTy != MVT::nxv4f16) 6991 return 0; 6992 if ((Subtarget->hasSVE())) { 6993 return fastEmitInst_rr(AArch64::ZIP1_ZZZ_S, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6994 } 6995 return 0; 6996} 6997 6998unsigned fastEmit_AArch64ISD_ZIP1_MVT_nxv8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6999 if (RetVT.SimpleTy != MVT::nxv8f16) 7000 return 0; 7001 if ((Subtarget->hasSVE())) { 7002 return fastEmitInst_rr(AArch64::ZIP1_ZZZ_H, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7003 } 7004 return 0; 7005} 7006 7007unsigned fastEmit_AArch64ISD_ZIP1_MVT_nxv4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7008 if (RetVT.SimpleTy != MVT::nxv4f32) 7009 return 0; 7010 if ((Subtarget->hasSVE())) { 7011 return fastEmitInst_rr(AArch64::ZIP1_ZZZ_S, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7012 } 7013 return 0; 7014} 7015 7016unsigned fastEmit_AArch64ISD_ZIP1_MVT_nxv2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7017 if (RetVT.SimpleTy != MVT::nxv2f64) 7018 return 0; 7019 if ((Subtarget->hasSVE())) { 7020 return fastEmitInst_rr(AArch64::ZIP1_ZZZ_D, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7021 } 7022 return 0; 7023} 7024 7025unsigned fastEmit_AArch64ISD_ZIP1_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7026 switch (VT.SimpleTy) { 7027 case MVT::v8i8: return fastEmit_AArch64ISD_ZIP1_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7028 case MVT::v16i8: return fastEmit_AArch64ISD_ZIP1_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7029 case MVT::v4i16: return fastEmit_AArch64ISD_ZIP1_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7030 case MVT::v8i16: return fastEmit_AArch64ISD_ZIP1_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7031 case MVT::v2i32: return fastEmit_AArch64ISD_ZIP1_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7032 case MVT::v4i32: return fastEmit_AArch64ISD_ZIP1_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7033 case MVT::v2i64: return fastEmit_AArch64ISD_ZIP1_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7034 case MVT::v4f16: return fastEmit_AArch64ISD_ZIP1_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7035 case MVT::v8f16: return fastEmit_AArch64ISD_ZIP1_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7036 case MVT::v2f32: return fastEmit_AArch64ISD_ZIP1_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7037 case MVT::v4f32: return fastEmit_AArch64ISD_ZIP1_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7038 case MVT::v2f64: return fastEmit_AArch64ISD_ZIP1_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7039 case MVT::nxv2i1: return fastEmit_AArch64ISD_ZIP1_MVT_nxv2i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7040 case MVT::nxv4i1: return fastEmit_AArch64ISD_ZIP1_MVT_nxv4i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7041 case MVT::nxv8i1: return fastEmit_AArch64ISD_ZIP1_MVT_nxv8i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7042 case MVT::nxv16i1: return fastEmit_AArch64ISD_ZIP1_MVT_nxv16i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7043 case MVT::nxv16i8: return fastEmit_AArch64ISD_ZIP1_MVT_nxv16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7044 case MVT::nxv8i16: return fastEmit_AArch64ISD_ZIP1_MVT_nxv8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7045 case MVT::nxv4i32: return fastEmit_AArch64ISD_ZIP1_MVT_nxv4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7046 case MVT::nxv2i64: return fastEmit_AArch64ISD_ZIP1_MVT_nxv2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7047 case MVT::nxv4f16: return fastEmit_AArch64ISD_ZIP1_MVT_nxv4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7048 case MVT::nxv8f16: return fastEmit_AArch64ISD_ZIP1_MVT_nxv8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7049 case MVT::nxv4f32: return fastEmit_AArch64ISD_ZIP1_MVT_nxv4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7050 case MVT::nxv2f64: return fastEmit_AArch64ISD_ZIP1_MVT_nxv2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7051 default: return 0; 7052 } 7053} 7054 7055// FastEmit functions for AArch64ISD::ZIP2. 7056 7057unsigned fastEmit_AArch64ISD_ZIP2_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7058 if (RetVT.SimpleTy != MVT::v8i8) 7059 return 0; 7060 if ((Subtarget->hasNEON())) { 7061 return fastEmitInst_rr(AArch64::ZIP2v8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7062 } 7063 return 0; 7064} 7065 7066unsigned fastEmit_AArch64ISD_ZIP2_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7067 if (RetVT.SimpleTy != MVT::v16i8) 7068 return 0; 7069 if ((Subtarget->hasNEON())) { 7070 return fastEmitInst_rr(AArch64::ZIP2v16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7071 } 7072 return 0; 7073} 7074 7075unsigned fastEmit_AArch64ISD_ZIP2_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7076 if (RetVT.SimpleTy != MVT::v4i16) 7077 return 0; 7078 if ((Subtarget->hasNEON())) { 7079 return fastEmitInst_rr(AArch64::ZIP2v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7080 } 7081 return 0; 7082} 7083 7084unsigned fastEmit_AArch64ISD_ZIP2_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7085 if (RetVT.SimpleTy != MVT::v8i16) 7086 return 0; 7087 if ((Subtarget->hasNEON())) { 7088 return fastEmitInst_rr(AArch64::ZIP2v8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7089 } 7090 return 0; 7091} 7092 7093unsigned fastEmit_AArch64ISD_ZIP2_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7094 if (RetVT.SimpleTy != MVT::v2i32) 7095 return 0; 7096 if ((Subtarget->hasNEON())) { 7097 return fastEmitInst_rr(AArch64::ZIP2v2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7098 } 7099 return 0; 7100} 7101 7102unsigned fastEmit_AArch64ISD_ZIP2_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7103 if (RetVT.SimpleTy != MVT::v4i32) 7104 return 0; 7105 if ((Subtarget->hasNEON())) { 7106 return fastEmitInst_rr(AArch64::ZIP2v4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7107 } 7108 return 0; 7109} 7110 7111unsigned fastEmit_AArch64ISD_ZIP2_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7112 if (RetVT.SimpleTy != MVT::v2i64) 7113 return 0; 7114 if ((Subtarget->hasNEON())) { 7115 return fastEmitInst_rr(AArch64::ZIP2v2i64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7116 } 7117 return 0; 7118} 7119 7120unsigned fastEmit_AArch64ISD_ZIP2_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7121 if (RetVT.SimpleTy != MVT::v4f16) 7122 return 0; 7123 if ((Subtarget->hasNEON())) { 7124 return fastEmitInst_rr(AArch64::ZIP2v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7125 } 7126 return 0; 7127} 7128 7129unsigned fastEmit_AArch64ISD_ZIP2_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7130 if (RetVT.SimpleTy != MVT::v8f16) 7131 return 0; 7132 if ((Subtarget->hasNEON())) { 7133 return fastEmitInst_rr(AArch64::ZIP2v8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7134 } 7135 return 0; 7136} 7137 7138unsigned fastEmit_AArch64ISD_ZIP2_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7139 if (RetVT.SimpleTy != MVT::v2f32) 7140 return 0; 7141 if ((Subtarget->hasNEON())) { 7142 return fastEmitInst_rr(AArch64::ZIP2v2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7143 } 7144 return 0; 7145} 7146 7147unsigned fastEmit_AArch64ISD_ZIP2_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7148 if (RetVT.SimpleTy != MVT::v4f32) 7149 return 0; 7150 if ((Subtarget->hasNEON())) { 7151 return fastEmitInst_rr(AArch64::ZIP2v4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7152 } 7153 return 0; 7154} 7155 7156unsigned fastEmit_AArch64ISD_ZIP2_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7157 if (RetVT.SimpleTy != MVT::v2f64) 7158 return 0; 7159 if ((Subtarget->hasNEON())) { 7160 return fastEmitInst_rr(AArch64::ZIP2v2i64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7161 } 7162 return 0; 7163} 7164 7165unsigned fastEmit_AArch64ISD_ZIP2_MVT_nxv2i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7166 if (RetVT.SimpleTy != MVT::nxv2i1) 7167 return 0; 7168 if ((Subtarget->hasSVE())) { 7169 return fastEmitInst_rr(AArch64::ZIP2_PPP_D, &AArch64::PPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7170 } 7171 return 0; 7172} 7173 7174unsigned fastEmit_AArch64ISD_ZIP2_MVT_nxv4i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7175 if (RetVT.SimpleTy != MVT::nxv4i1) 7176 return 0; 7177 if ((Subtarget->hasSVE())) { 7178 return fastEmitInst_rr(AArch64::ZIP2_PPP_S, &AArch64::PPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7179 } 7180 return 0; 7181} 7182 7183unsigned fastEmit_AArch64ISD_ZIP2_MVT_nxv8i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7184 if (RetVT.SimpleTy != MVT::nxv8i1) 7185 return 0; 7186 if ((Subtarget->hasSVE())) { 7187 return fastEmitInst_rr(AArch64::ZIP2_PPP_H, &AArch64::PPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7188 } 7189 return 0; 7190} 7191 7192unsigned fastEmit_AArch64ISD_ZIP2_MVT_nxv16i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7193 if (RetVT.SimpleTy != MVT::nxv16i1) 7194 return 0; 7195 if ((Subtarget->hasSVE())) { 7196 return fastEmitInst_rr(AArch64::ZIP2_PPP_B, &AArch64::PPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7197 } 7198 return 0; 7199} 7200 7201unsigned fastEmit_AArch64ISD_ZIP2_MVT_nxv16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7202 if (RetVT.SimpleTy != MVT::nxv16i8) 7203 return 0; 7204 if ((Subtarget->hasSVE())) { 7205 return fastEmitInst_rr(AArch64::ZIP2_ZZZ_B, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7206 } 7207 return 0; 7208} 7209 7210unsigned fastEmit_AArch64ISD_ZIP2_MVT_nxv8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7211 if (RetVT.SimpleTy != MVT::nxv8i16) 7212 return 0; 7213 if ((Subtarget->hasSVE())) { 7214 return fastEmitInst_rr(AArch64::ZIP2_ZZZ_H, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7215 } 7216 return 0; 7217} 7218 7219unsigned fastEmit_AArch64ISD_ZIP2_MVT_nxv4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7220 if (RetVT.SimpleTy != MVT::nxv4i32) 7221 return 0; 7222 if ((Subtarget->hasSVE())) { 7223 return fastEmitInst_rr(AArch64::ZIP2_ZZZ_S, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7224 } 7225 return 0; 7226} 7227 7228unsigned fastEmit_AArch64ISD_ZIP2_MVT_nxv2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7229 if (RetVT.SimpleTy != MVT::nxv2i64) 7230 return 0; 7231 if ((Subtarget->hasSVE())) { 7232 return fastEmitInst_rr(AArch64::ZIP2_ZZZ_D, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7233 } 7234 return 0; 7235} 7236 7237unsigned fastEmit_AArch64ISD_ZIP2_MVT_nxv4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7238 if (RetVT.SimpleTy != MVT::nxv4f16) 7239 return 0; 7240 if ((Subtarget->hasSVE())) { 7241 return fastEmitInst_rr(AArch64::ZIP2_ZZZ_S, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7242 } 7243 return 0; 7244} 7245 7246unsigned fastEmit_AArch64ISD_ZIP2_MVT_nxv8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7247 if (RetVT.SimpleTy != MVT::nxv8f16) 7248 return 0; 7249 if ((Subtarget->hasSVE())) { 7250 return fastEmitInst_rr(AArch64::ZIP2_ZZZ_H, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7251 } 7252 return 0; 7253} 7254 7255unsigned fastEmit_AArch64ISD_ZIP2_MVT_nxv4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7256 if (RetVT.SimpleTy != MVT::nxv4f32) 7257 return 0; 7258 if ((Subtarget->hasSVE())) { 7259 return fastEmitInst_rr(AArch64::ZIP2_ZZZ_S, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7260 } 7261 return 0; 7262} 7263 7264unsigned fastEmit_AArch64ISD_ZIP2_MVT_nxv2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7265 if (RetVT.SimpleTy != MVT::nxv2f64) 7266 return 0; 7267 if ((Subtarget->hasSVE())) { 7268 return fastEmitInst_rr(AArch64::ZIP2_ZZZ_D, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7269 } 7270 return 0; 7271} 7272 7273unsigned fastEmit_AArch64ISD_ZIP2_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7274 switch (VT.SimpleTy) { 7275 case MVT::v8i8: return fastEmit_AArch64ISD_ZIP2_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7276 case MVT::v16i8: return fastEmit_AArch64ISD_ZIP2_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7277 case MVT::v4i16: return fastEmit_AArch64ISD_ZIP2_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7278 case MVT::v8i16: return fastEmit_AArch64ISD_ZIP2_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7279 case MVT::v2i32: return fastEmit_AArch64ISD_ZIP2_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7280 case MVT::v4i32: return fastEmit_AArch64ISD_ZIP2_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7281 case MVT::v2i64: return fastEmit_AArch64ISD_ZIP2_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7282 case MVT::v4f16: return fastEmit_AArch64ISD_ZIP2_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7283 case MVT::v8f16: return fastEmit_AArch64ISD_ZIP2_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7284 case MVT::v2f32: return fastEmit_AArch64ISD_ZIP2_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7285 case MVT::v4f32: return fastEmit_AArch64ISD_ZIP2_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7286 case MVT::v2f64: return fastEmit_AArch64ISD_ZIP2_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7287 case MVT::nxv2i1: return fastEmit_AArch64ISD_ZIP2_MVT_nxv2i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7288 case MVT::nxv4i1: return fastEmit_AArch64ISD_ZIP2_MVT_nxv4i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7289 case MVT::nxv8i1: return fastEmit_AArch64ISD_ZIP2_MVT_nxv8i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7290 case MVT::nxv16i1: return fastEmit_AArch64ISD_ZIP2_MVT_nxv16i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7291 case MVT::nxv16i8: return fastEmit_AArch64ISD_ZIP2_MVT_nxv16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7292 case MVT::nxv8i16: return fastEmit_AArch64ISD_ZIP2_MVT_nxv8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7293 case MVT::nxv4i32: return fastEmit_AArch64ISD_ZIP2_MVT_nxv4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7294 case MVT::nxv2i64: return fastEmit_AArch64ISD_ZIP2_MVT_nxv2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7295 case MVT::nxv4f16: return fastEmit_AArch64ISD_ZIP2_MVT_nxv4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7296 case MVT::nxv8f16: return fastEmit_AArch64ISD_ZIP2_MVT_nxv8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7297 case MVT::nxv4f32: return fastEmit_AArch64ISD_ZIP2_MVT_nxv4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7298 case MVT::nxv2f64: return fastEmit_AArch64ISD_ZIP2_MVT_nxv2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7299 default: return 0; 7300 } 7301} 7302 7303// FastEmit functions for ISD::ADD. 7304 7305unsigned fastEmit_ISD_ADD_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7306 if (RetVT.SimpleTy != MVT::i32) 7307 return 0; 7308 return fastEmitInst_rr(AArch64::ADDWrr, &AArch64::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7309} 7310 7311unsigned fastEmit_ISD_ADD_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7312 if (RetVT.SimpleTy != MVT::i64) 7313 return 0; 7314 return fastEmitInst_rr(AArch64::ADDXrr, &AArch64::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7315} 7316 7317unsigned fastEmit_ISD_ADD_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7318 if (RetVT.SimpleTy != MVT::v8i8) 7319 return 0; 7320 if ((Subtarget->hasNEON())) { 7321 return fastEmitInst_rr(AArch64::ADDv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7322 } 7323 return 0; 7324} 7325 7326unsigned fastEmit_ISD_ADD_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7327 if (RetVT.SimpleTy != MVT::v16i8) 7328 return 0; 7329 if ((Subtarget->hasNEON())) { 7330 return fastEmitInst_rr(AArch64::ADDv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7331 } 7332 return 0; 7333} 7334 7335unsigned fastEmit_ISD_ADD_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7336 if (RetVT.SimpleTy != MVT::v4i16) 7337 return 0; 7338 if ((Subtarget->hasNEON())) { 7339 return fastEmitInst_rr(AArch64::ADDv4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7340 } 7341 return 0; 7342} 7343 7344unsigned fastEmit_ISD_ADD_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7345 if (RetVT.SimpleTy != MVT::v8i16) 7346 return 0; 7347 if ((Subtarget->hasNEON())) { 7348 return fastEmitInst_rr(AArch64::ADDv8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7349 } 7350 return 0; 7351} 7352 7353unsigned fastEmit_ISD_ADD_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7354 if (RetVT.SimpleTy != MVT::v2i32) 7355 return 0; 7356 if ((Subtarget->hasNEON())) { 7357 return fastEmitInst_rr(AArch64::ADDv2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7358 } 7359 return 0; 7360} 7361 7362unsigned fastEmit_ISD_ADD_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7363 if (RetVT.SimpleTy != MVT::v4i32) 7364 return 0; 7365 if ((Subtarget->hasNEON())) { 7366 return fastEmitInst_rr(AArch64::ADDv4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7367 } 7368 return 0; 7369} 7370 7371unsigned fastEmit_ISD_ADD_MVT_v1i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7372 if (RetVT.SimpleTy != MVT::v1i64) 7373 return 0; 7374 if ((Subtarget->hasNEON())) { 7375 return fastEmitInst_rr(AArch64::ADDv1i64, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7376 } 7377 return 0; 7378} 7379 7380unsigned fastEmit_ISD_ADD_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7381 if (RetVT.SimpleTy != MVT::v2i64) 7382 return 0; 7383 if ((Subtarget->hasNEON())) { 7384 return fastEmitInst_rr(AArch64::ADDv2i64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7385 } 7386 return 0; 7387} 7388 7389unsigned fastEmit_ISD_ADD_MVT_nxv16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7390 if (RetVT.SimpleTy != MVT::nxv16i8) 7391 return 0; 7392 if ((Subtarget->hasSVE())) { 7393 return fastEmitInst_rr(AArch64::ADD_ZZZ_B, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7394 } 7395 return 0; 7396} 7397 7398unsigned fastEmit_ISD_ADD_MVT_nxv8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7399 if (RetVT.SimpleTy != MVT::nxv8i16) 7400 return 0; 7401 if ((Subtarget->hasSVE())) { 7402 return fastEmitInst_rr(AArch64::ADD_ZZZ_H, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7403 } 7404 return 0; 7405} 7406 7407unsigned fastEmit_ISD_ADD_MVT_nxv4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7408 if (RetVT.SimpleTy != MVT::nxv4i32) 7409 return 0; 7410 if ((Subtarget->hasSVE())) { 7411 return fastEmitInst_rr(AArch64::ADD_ZZZ_S, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7412 } 7413 return 0; 7414} 7415 7416unsigned fastEmit_ISD_ADD_MVT_nxv2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7417 if (RetVT.SimpleTy != MVT::nxv2i64) 7418 return 0; 7419 if ((Subtarget->hasSVE())) { 7420 return fastEmitInst_rr(AArch64::ADD_ZZZ_D, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7421 } 7422 return 0; 7423} 7424 7425unsigned fastEmit_ISD_ADD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7426 switch (VT.SimpleTy) { 7427 case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7428 case MVT::i64: return fastEmit_ISD_ADD_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7429 case MVT::v8i8: return fastEmit_ISD_ADD_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7430 case MVT::v16i8: return fastEmit_ISD_ADD_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7431 case MVT::v4i16: return fastEmit_ISD_ADD_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7432 case MVT::v8i16: return fastEmit_ISD_ADD_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7433 case MVT::v2i32: return fastEmit_ISD_ADD_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7434 case MVT::v4i32: return fastEmit_ISD_ADD_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7435 case MVT::v1i64: return fastEmit_ISD_ADD_MVT_v1i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7436 case MVT::v2i64: return fastEmit_ISD_ADD_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7437 case MVT::nxv16i8: return fastEmit_ISD_ADD_MVT_nxv16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7438 case MVT::nxv8i16: return fastEmit_ISD_ADD_MVT_nxv8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7439 case MVT::nxv4i32: return fastEmit_ISD_ADD_MVT_nxv4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7440 case MVT::nxv2i64: return fastEmit_ISD_ADD_MVT_nxv2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7441 default: return 0; 7442 } 7443} 7444 7445// FastEmit functions for ISD::AND. 7446 7447unsigned fastEmit_ISD_AND_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7448 if (RetVT.SimpleTy != MVT::i32) 7449 return 0; 7450 return fastEmitInst_rr(AArch64::ANDWrr, &AArch64::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7451} 7452 7453unsigned fastEmit_ISD_AND_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7454 if (RetVT.SimpleTy != MVT::i64) 7455 return 0; 7456 return fastEmitInst_rr(AArch64::ANDXrr, &AArch64::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7457} 7458 7459unsigned fastEmit_ISD_AND_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7460 if (RetVT.SimpleTy != MVT::v8i8) 7461 return 0; 7462 if ((Subtarget->hasNEON())) { 7463 return fastEmitInst_rr(AArch64::ANDv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7464 } 7465 return 0; 7466} 7467 7468unsigned fastEmit_ISD_AND_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7469 if (RetVT.SimpleTy != MVT::v16i8) 7470 return 0; 7471 if ((Subtarget->hasNEON())) { 7472 return fastEmitInst_rr(AArch64::ANDv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7473 } 7474 return 0; 7475} 7476 7477unsigned fastEmit_ISD_AND_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7478 if (RetVT.SimpleTy != MVT::v4i16) 7479 return 0; 7480 if ((Subtarget->hasNEON())) { 7481 return fastEmitInst_rr(AArch64::ANDv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7482 } 7483 return 0; 7484} 7485 7486unsigned fastEmit_ISD_AND_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7487 if (RetVT.SimpleTy != MVT::v8i16) 7488 return 0; 7489 if ((Subtarget->hasNEON())) { 7490 return fastEmitInst_rr(AArch64::ANDv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7491 } 7492 return 0; 7493} 7494 7495unsigned fastEmit_ISD_AND_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7496 if (RetVT.SimpleTy != MVT::v2i32) 7497 return 0; 7498 if ((Subtarget->hasNEON())) { 7499 return fastEmitInst_rr(AArch64::ANDv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7500 } 7501 return 0; 7502} 7503 7504unsigned fastEmit_ISD_AND_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7505 if (RetVT.SimpleTy != MVT::v4i32) 7506 return 0; 7507 if ((Subtarget->hasNEON())) { 7508 return fastEmitInst_rr(AArch64::ANDv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7509 } 7510 return 0; 7511} 7512 7513unsigned fastEmit_ISD_AND_MVT_v1i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7514 if (RetVT.SimpleTy != MVT::v1i64) 7515 return 0; 7516 if ((Subtarget->hasNEON())) { 7517 return fastEmitInst_rr(AArch64::ANDv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7518 } 7519 return 0; 7520} 7521 7522unsigned fastEmit_ISD_AND_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7523 if (RetVT.SimpleTy != MVT::v2i64) 7524 return 0; 7525 if ((Subtarget->hasNEON())) { 7526 return fastEmitInst_rr(AArch64::ANDv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7527 } 7528 return 0; 7529} 7530 7531unsigned fastEmit_ISD_AND_MVT_nxv16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7532 if (RetVT.SimpleTy != MVT::nxv16i8) 7533 return 0; 7534 if ((Subtarget->hasSVE())) { 7535 return fastEmitInst_rr(AArch64::AND_ZZZ, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7536 } 7537 return 0; 7538} 7539 7540unsigned fastEmit_ISD_AND_MVT_nxv8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7541 if (RetVT.SimpleTy != MVT::nxv8i16) 7542 return 0; 7543 if ((Subtarget->hasSVE())) { 7544 return fastEmitInst_rr(AArch64::AND_ZZZ, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7545 } 7546 return 0; 7547} 7548 7549unsigned fastEmit_ISD_AND_MVT_nxv4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7550 if (RetVT.SimpleTy != MVT::nxv4i32) 7551 return 0; 7552 if ((Subtarget->hasSVE())) { 7553 return fastEmitInst_rr(AArch64::AND_ZZZ, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7554 } 7555 return 0; 7556} 7557 7558unsigned fastEmit_ISD_AND_MVT_nxv2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7559 if (RetVT.SimpleTy != MVT::nxv2i64) 7560 return 0; 7561 if ((Subtarget->hasSVE())) { 7562 return fastEmitInst_rr(AArch64::AND_ZZZ, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7563 } 7564 return 0; 7565} 7566 7567unsigned fastEmit_ISD_AND_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7568 switch (VT.SimpleTy) { 7569 case MVT::i32: return fastEmit_ISD_AND_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7570 case MVT::i64: return fastEmit_ISD_AND_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7571 case MVT::v8i8: return fastEmit_ISD_AND_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7572 case MVT::v16i8: return fastEmit_ISD_AND_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7573 case MVT::v4i16: return fastEmit_ISD_AND_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7574 case MVT::v8i16: return fastEmit_ISD_AND_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7575 case MVT::v2i32: return fastEmit_ISD_AND_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7576 case MVT::v4i32: return fastEmit_ISD_AND_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7577 case MVT::v1i64: return fastEmit_ISD_AND_MVT_v1i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7578 case MVT::v2i64: return fastEmit_ISD_AND_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7579 case MVT::nxv16i8: return fastEmit_ISD_AND_MVT_nxv16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7580 case MVT::nxv8i16: return fastEmit_ISD_AND_MVT_nxv8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7581 case MVT::nxv4i32: return fastEmit_ISD_AND_MVT_nxv4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7582 case MVT::nxv2i64: return fastEmit_ISD_AND_MVT_nxv2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7583 default: return 0; 7584 } 7585} 7586 7587// FastEmit functions for ISD::FADD. 7588 7589unsigned fastEmit_ISD_FADD_MVT_f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7590 if (RetVT.SimpleTy != MVT::f16) 7591 return 0; 7592 if ((Subtarget->hasFullFP16())) { 7593 return fastEmitInst_rr(AArch64::FADDHrr, &AArch64::FPR16RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7594 } 7595 return 0; 7596} 7597 7598unsigned fastEmit_ISD_FADD_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7599 if (RetVT.SimpleTy != MVT::f32) 7600 return 0; 7601 if ((Subtarget->hasFPARMv8())) { 7602 return fastEmitInst_rr(AArch64::FADDSrr, &AArch64::FPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7603 } 7604 return 0; 7605} 7606 7607unsigned fastEmit_ISD_FADD_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7608 if (RetVT.SimpleTy != MVT::f64) 7609 return 0; 7610 if ((Subtarget->hasFPARMv8())) { 7611 return fastEmitInst_rr(AArch64::FADDDrr, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7612 } 7613 return 0; 7614} 7615 7616unsigned fastEmit_ISD_FADD_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7617 if (RetVT.SimpleTy != MVT::v4f16) 7618 return 0; 7619 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 7620 return fastEmitInst_rr(AArch64::FADDv4f16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7621 } 7622 return 0; 7623} 7624 7625unsigned fastEmit_ISD_FADD_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7626 if (RetVT.SimpleTy != MVT::v8f16) 7627 return 0; 7628 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 7629 return fastEmitInst_rr(AArch64::FADDv8f16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7630 } 7631 return 0; 7632} 7633 7634unsigned fastEmit_ISD_FADD_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7635 if (RetVT.SimpleTy != MVT::v2f32) 7636 return 0; 7637 if ((Subtarget->hasNEON())) { 7638 return fastEmitInst_rr(AArch64::FADDv2f32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7639 } 7640 return 0; 7641} 7642 7643unsigned fastEmit_ISD_FADD_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7644 if (RetVT.SimpleTy != MVT::v4f32) 7645 return 0; 7646 if ((Subtarget->hasNEON())) { 7647 return fastEmitInst_rr(AArch64::FADDv4f32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7648 } 7649 return 0; 7650} 7651 7652unsigned fastEmit_ISD_FADD_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7653 if (RetVT.SimpleTy != MVT::v2f64) 7654 return 0; 7655 if ((Subtarget->hasNEON())) { 7656 return fastEmitInst_rr(AArch64::FADDv2f64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7657 } 7658 return 0; 7659} 7660 7661unsigned fastEmit_ISD_FADD_MVT_nxv8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7662 if (RetVT.SimpleTy != MVT::nxv8f16) 7663 return 0; 7664 if ((Subtarget->hasSVE())) { 7665 return fastEmitInst_rr(AArch64::FADD_ZZZ_H, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7666 } 7667 return 0; 7668} 7669 7670unsigned fastEmit_ISD_FADD_MVT_nxv4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7671 if (RetVT.SimpleTy != MVT::nxv4f32) 7672 return 0; 7673 if ((Subtarget->hasSVE())) { 7674 return fastEmitInst_rr(AArch64::FADD_ZZZ_S, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7675 } 7676 return 0; 7677} 7678 7679unsigned fastEmit_ISD_FADD_MVT_nxv2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7680 if (RetVT.SimpleTy != MVT::nxv2f64) 7681 return 0; 7682 if ((Subtarget->hasSVE())) { 7683 return fastEmitInst_rr(AArch64::FADD_ZZZ_D, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7684 } 7685 return 0; 7686} 7687 7688unsigned fastEmit_ISD_FADD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7689 switch (VT.SimpleTy) { 7690 case MVT::f16: return fastEmit_ISD_FADD_MVT_f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7691 case MVT::f32: return fastEmit_ISD_FADD_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7692 case MVT::f64: return fastEmit_ISD_FADD_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7693 case MVT::v4f16: return fastEmit_ISD_FADD_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7694 case MVT::v8f16: return fastEmit_ISD_FADD_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7695 case MVT::v2f32: return fastEmit_ISD_FADD_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7696 case MVT::v4f32: return fastEmit_ISD_FADD_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7697 case MVT::v2f64: return fastEmit_ISD_FADD_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7698 case MVT::nxv8f16: return fastEmit_ISD_FADD_MVT_nxv8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7699 case MVT::nxv4f32: return fastEmit_ISD_FADD_MVT_nxv4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7700 case MVT::nxv2f64: return fastEmit_ISD_FADD_MVT_nxv2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7701 default: return 0; 7702 } 7703} 7704 7705// FastEmit functions for ISD::FDIV. 7706 7707unsigned fastEmit_ISD_FDIV_MVT_f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7708 if (RetVT.SimpleTy != MVT::f16) 7709 return 0; 7710 if ((Subtarget->hasFullFP16())) { 7711 return fastEmitInst_rr(AArch64::FDIVHrr, &AArch64::FPR16RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7712 } 7713 return 0; 7714} 7715 7716unsigned fastEmit_ISD_FDIV_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7717 if (RetVT.SimpleTy != MVT::f32) 7718 return 0; 7719 if ((Subtarget->hasFPARMv8())) { 7720 return fastEmitInst_rr(AArch64::FDIVSrr, &AArch64::FPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7721 } 7722 return 0; 7723} 7724 7725unsigned fastEmit_ISD_FDIV_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7726 if (RetVT.SimpleTy != MVT::f64) 7727 return 0; 7728 if ((Subtarget->hasFPARMv8())) { 7729 return fastEmitInst_rr(AArch64::FDIVDrr, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7730 } 7731 return 0; 7732} 7733 7734unsigned fastEmit_ISD_FDIV_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7735 if (RetVT.SimpleTy != MVT::v4f16) 7736 return 0; 7737 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 7738 return fastEmitInst_rr(AArch64::FDIVv4f16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7739 } 7740 return 0; 7741} 7742 7743unsigned fastEmit_ISD_FDIV_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7744 if (RetVT.SimpleTy != MVT::v8f16) 7745 return 0; 7746 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 7747 return fastEmitInst_rr(AArch64::FDIVv8f16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7748 } 7749 return 0; 7750} 7751 7752unsigned fastEmit_ISD_FDIV_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7753 if (RetVT.SimpleTy != MVT::v2f32) 7754 return 0; 7755 if ((Subtarget->hasNEON())) { 7756 return fastEmitInst_rr(AArch64::FDIVv2f32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7757 } 7758 return 0; 7759} 7760 7761unsigned fastEmit_ISD_FDIV_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7762 if (RetVT.SimpleTy != MVT::v4f32) 7763 return 0; 7764 if ((Subtarget->hasNEON())) { 7765 return fastEmitInst_rr(AArch64::FDIVv4f32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7766 } 7767 return 0; 7768} 7769 7770unsigned fastEmit_ISD_FDIV_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7771 if (RetVT.SimpleTy != MVT::v2f64) 7772 return 0; 7773 if ((Subtarget->hasNEON())) { 7774 return fastEmitInst_rr(AArch64::FDIVv2f64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7775 } 7776 return 0; 7777} 7778 7779unsigned fastEmit_ISD_FDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7780 switch (VT.SimpleTy) { 7781 case MVT::f16: return fastEmit_ISD_FDIV_MVT_f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7782 case MVT::f32: return fastEmit_ISD_FDIV_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7783 case MVT::f64: return fastEmit_ISD_FDIV_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7784 case MVT::v4f16: return fastEmit_ISD_FDIV_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7785 case MVT::v8f16: return fastEmit_ISD_FDIV_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7786 case MVT::v2f32: return fastEmit_ISD_FDIV_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7787 case MVT::v4f32: return fastEmit_ISD_FDIV_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7788 case MVT::v2f64: return fastEmit_ISD_FDIV_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7789 default: return 0; 7790 } 7791} 7792 7793// FastEmit functions for ISD::FMAXIMUM. 7794 7795unsigned fastEmit_ISD_FMAXIMUM_MVT_f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7796 if (RetVT.SimpleTy != MVT::f16) 7797 return 0; 7798 if ((Subtarget->hasFullFP16())) { 7799 return fastEmitInst_rr(AArch64::FMAXHrr, &AArch64::FPR16RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7800 } 7801 return 0; 7802} 7803 7804unsigned fastEmit_ISD_FMAXIMUM_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7805 if (RetVT.SimpleTy != MVT::f32) 7806 return 0; 7807 if ((Subtarget->hasFPARMv8())) { 7808 return fastEmitInst_rr(AArch64::FMAXSrr, &AArch64::FPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7809 } 7810 return 0; 7811} 7812 7813unsigned fastEmit_ISD_FMAXIMUM_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7814 if (RetVT.SimpleTy != MVT::f64) 7815 return 0; 7816 if ((Subtarget->hasFPARMv8())) { 7817 return fastEmitInst_rr(AArch64::FMAXDrr, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7818 } 7819 return 0; 7820} 7821 7822unsigned fastEmit_ISD_FMAXIMUM_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7823 if (RetVT.SimpleTy != MVT::v4f16) 7824 return 0; 7825 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 7826 return fastEmitInst_rr(AArch64::FMAXv4f16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7827 } 7828 return 0; 7829} 7830 7831unsigned fastEmit_ISD_FMAXIMUM_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7832 if (RetVT.SimpleTy != MVT::v8f16) 7833 return 0; 7834 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 7835 return fastEmitInst_rr(AArch64::FMAXv8f16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7836 } 7837 return 0; 7838} 7839 7840unsigned fastEmit_ISD_FMAXIMUM_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7841 if (RetVT.SimpleTy != MVT::v2f32) 7842 return 0; 7843 if ((Subtarget->hasNEON())) { 7844 return fastEmitInst_rr(AArch64::FMAXv2f32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7845 } 7846 return 0; 7847} 7848 7849unsigned fastEmit_ISD_FMAXIMUM_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7850 if (RetVT.SimpleTy != MVT::v4f32) 7851 return 0; 7852 if ((Subtarget->hasNEON())) { 7853 return fastEmitInst_rr(AArch64::FMAXv4f32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7854 } 7855 return 0; 7856} 7857 7858unsigned fastEmit_ISD_FMAXIMUM_MVT_v1f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7859 if (RetVT.SimpleTy != MVT::v1f64) 7860 return 0; 7861 return fastEmitInst_rr(AArch64::FMAXDrr, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7862} 7863 7864unsigned fastEmit_ISD_FMAXIMUM_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7865 if (RetVT.SimpleTy != MVT::v2f64) 7866 return 0; 7867 if ((Subtarget->hasNEON())) { 7868 return fastEmitInst_rr(AArch64::FMAXv2f64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7869 } 7870 return 0; 7871} 7872 7873unsigned fastEmit_ISD_FMAXIMUM_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7874 switch (VT.SimpleTy) { 7875 case MVT::f16: return fastEmit_ISD_FMAXIMUM_MVT_f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7876 case MVT::f32: return fastEmit_ISD_FMAXIMUM_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7877 case MVT::f64: return fastEmit_ISD_FMAXIMUM_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7878 case MVT::v4f16: return fastEmit_ISD_FMAXIMUM_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7879 case MVT::v8f16: return fastEmit_ISD_FMAXIMUM_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7880 case MVT::v2f32: return fastEmit_ISD_FMAXIMUM_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7881 case MVT::v4f32: return fastEmit_ISD_FMAXIMUM_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7882 case MVT::v1f64: return fastEmit_ISD_FMAXIMUM_MVT_v1f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7883 case MVT::v2f64: return fastEmit_ISD_FMAXIMUM_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7884 default: return 0; 7885 } 7886} 7887 7888// FastEmit functions for ISD::FMAXNUM. 7889 7890unsigned fastEmit_ISD_FMAXNUM_MVT_f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7891 if (RetVT.SimpleTy != MVT::f16) 7892 return 0; 7893 if ((Subtarget->hasFullFP16())) { 7894 return fastEmitInst_rr(AArch64::FMAXNMHrr, &AArch64::FPR16RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7895 } 7896 return 0; 7897} 7898 7899unsigned fastEmit_ISD_FMAXNUM_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7900 if (RetVT.SimpleTy != MVT::f32) 7901 return 0; 7902 if ((Subtarget->hasFPARMv8())) { 7903 return fastEmitInst_rr(AArch64::FMAXNMSrr, &AArch64::FPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7904 } 7905 return 0; 7906} 7907 7908unsigned fastEmit_ISD_FMAXNUM_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7909 if (RetVT.SimpleTy != MVT::f64) 7910 return 0; 7911 if ((Subtarget->hasFPARMv8())) { 7912 return fastEmitInst_rr(AArch64::FMAXNMDrr, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7913 } 7914 return 0; 7915} 7916 7917unsigned fastEmit_ISD_FMAXNUM_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7918 if (RetVT.SimpleTy != MVT::v4f16) 7919 return 0; 7920 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 7921 return fastEmitInst_rr(AArch64::FMAXNMv4f16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7922 } 7923 return 0; 7924} 7925 7926unsigned fastEmit_ISD_FMAXNUM_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7927 if (RetVT.SimpleTy != MVT::v8f16) 7928 return 0; 7929 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 7930 return fastEmitInst_rr(AArch64::FMAXNMv8f16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7931 } 7932 return 0; 7933} 7934 7935unsigned fastEmit_ISD_FMAXNUM_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7936 if (RetVT.SimpleTy != MVT::v2f32) 7937 return 0; 7938 if ((Subtarget->hasNEON())) { 7939 return fastEmitInst_rr(AArch64::FMAXNMv2f32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7940 } 7941 return 0; 7942} 7943 7944unsigned fastEmit_ISD_FMAXNUM_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7945 if (RetVT.SimpleTy != MVT::v4f32) 7946 return 0; 7947 if ((Subtarget->hasNEON())) { 7948 return fastEmitInst_rr(AArch64::FMAXNMv4f32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7949 } 7950 return 0; 7951} 7952 7953unsigned fastEmit_ISD_FMAXNUM_MVT_v1f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7954 if (RetVT.SimpleTy != MVT::v1f64) 7955 return 0; 7956 return fastEmitInst_rr(AArch64::FMAXNMDrr, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7957} 7958 7959unsigned fastEmit_ISD_FMAXNUM_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7960 if (RetVT.SimpleTy != MVT::v2f64) 7961 return 0; 7962 if ((Subtarget->hasNEON())) { 7963 return fastEmitInst_rr(AArch64::FMAXNMv2f64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7964 } 7965 return 0; 7966} 7967 7968unsigned fastEmit_ISD_FMAXNUM_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7969 switch (VT.SimpleTy) { 7970 case MVT::f16: return fastEmit_ISD_FMAXNUM_MVT_f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7971 case MVT::f32: return fastEmit_ISD_FMAXNUM_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7972 case MVT::f64: return fastEmit_ISD_FMAXNUM_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7973 case MVT::v4f16: return fastEmit_ISD_FMAXNUM_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7974 case MVT::v8f16: return fastEmit_ISD_FMAXNUM_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7975 case MVT::v2f32: return fastEmit_ISD_FMAXNUM_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7976 case MVT::v4f32: return fastEmit_ISD_FMAXNUM_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7977 case MVT::v1f64: return fastEmit_ISD_FMAXNUM_MVT_v1f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7978 case MVT::v2f64: return fastEmit_ISD_FMAXNUM_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7979 default: return 0; 7980 } 7981} 7982 7983// FastEmit functions for ISD::FMINIMUM. 7984 7985unsigned fastEmit_ISD_FMINIMUM_MVT_f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7986 if (RetVT.SimpleTy != MVT::f16) 7987 return 0; 7988 if ((Subtarget->hasFullFP16())) { 7989 return fastEmitInst_rr(AArch64::FMINHrr, &AArch64::FPR16RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7990 } 7991 return 0; 7992} 7993 7994unsigned fastEmit_ISD_FMINIMUM_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7995 if (RetVT.SimpleTy != MVT::f32) 7996 return 0; 7997 if ((Subtarget->hasFPARMv8())) { 7998 return fastEmitInst_rr(AArch64::FMINSrr, &AArch64::FPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7999 } 8000 return 0; 8001} 8002 8003unsigned fastEmit_ISD_FMINIMUM_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8004 if (RetVT.SimpleTy != MVT::f64) 8005 return 0; 8006 if ((Subtarget->hasFPARMv8())) { 8007 return fastEmitInst_rr(AArch64::FMINDrr, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8008 } 8009 return 0; 8010} 8011 8012unsigned fastEmit_ISD_FMINIMUM_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8013 if (RetVT.SimpleTy != MVT::v4f16) 8014 return 0; 8015 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 8016 return fastEmitInst_rr(AArch64::FMINv4f16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8017 } 8018 return 0; 8019} 8020 8021unsigned fastEmit_ISD_FMINIMUM_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8022 if (RetVT.SimpleTy != MVT::v8f16) 8023 return 0; 8024 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 8025 return fastEmitInst_rr(AArch64::FMINv8f16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8026 } 8027 return 0; 8028} 8029 8030unsigned fastEmit_ISD_FMINIMUM_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8031 if (RetVT.SimpleTy != MVT::v2f32) 8032 return 0; 8033 if ((Subtarget->hasNEON())) { 8034 return fastEmitInst_rr(AArch64::FMINv2f32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8035 } 8036 return 0; 8037} 8038 8039unsigned fastEmit_ISD_FMINIMUM_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8040 if (RetVT.SimpleTy != MVT::v4f32) 8041 return 0; 8042 if ((Subtarget->hasNEON())) { 8043 return fastEmitInst_rr(AArch64::FMINv4f32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8044 } 8045 return 0; 8046} 8047 8048unsigned fastEmit_ISD_FMINIMUM_MVT_v1f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8049 if (RetVT.SimpleTy != MVT::v1f64) 8050 return 0; 8051 return fastEmitInst_rr(AArch64::FMINDrr, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8052} 8053 8054unsigned fastEmit_ISD_FMINIMUM_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8055 if (RetVT.SimpleTy != MVT::v2f64) 8056 return 0; 8057 if ((Subtarget->hasNEON())) { 8058 return fastEmitInst_rr(AArch64::FMINv2f64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8059 } 8060 return 0; 8061} 8062 8063unsigned fastEmit_ISD_FMINIMUM_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8064 switch (VT.SimpleTy) { 8065 case MVT::f16: return fastEmit_ISD_FMINIMUM_MVT_f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8066 case MVT::f32: return fastEmit_ISD_FMINIMUM_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8067 case MVT::f64: return fastEmit_ISD_FMINIMUM_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8068 case MVT::v4f16: return fastEmit_ISD_FMINIMUM_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8069 case MVT::v8f16: return fastEmit_ISD_FMINIMUM_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8070 case MVT::v2f32: return fastEmit_ISD_FMINIMUM_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8071 case MVT::v4f32: return fastEmit_ISD_FMINIMUM_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8072 case MVT::v1f64: return fastEmit_ISD_FMINIMUM_MVT_v1f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8073 case MVT::v2f64: return fastEmit_ISD_FMINIMUM_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8074 default: return 0; 8075 } 8076} 8077 8078// FastEmit functions for ISD::FMINNUM. 8079 8080unsigned fastEmit_ISD_FMINNUM_MVT_f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8081 if (RetVT.SimpleTy != MVT::f16) 8082 return 0; 8083 if ((Subtarget->hasFullFP16())) { 8084 return fastEmitInst_rr(AArch64::FMINNMHrr, &AArch64::FPR16RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8085 } 8086 return 0; 8087} 8088 8089unsigned fastEmit_ISD_FMINNUM_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8090 if (RetVT.SimpleTy != MVT::f32) 8091 return 0; 8092 if ((Subtarget->hasFPARMv8())) { 8093 return fastEmitInst_rr(AArch64::FMINNMSrr, &AArch64::FPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8094 } 8095 return 0; 8096} 8097 8098unsigned fastEmit_ISD_FMINNUM_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8099 if (RetVT.SimpleTy != MVT::f64) 8100 return 0; 8101 if ((Subtarget->hasFPARMv8())) { 8102 return fastEmitInst_rr(AArch64::FMINNMDrr, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8103 } 8104 return 0; 8105} 8106 8107unsigned fastEmit_ISD_FMINNUM_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8108 if (RetVT.SimpleTy != MVT::v4f16) 8109 return 0; 8110 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 8111 return fastEmitInst_rr(AArch64::FMINNMv4f16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8112 } 8113 return 0; 8114} 8115 8116unsigned fastEmit_ISD_FMINNUM_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8117 if (RetVT.SimpleTy != MVT::v8f16) 8118 return 0; 8119 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 8120 return fastEmitInst_rr(AArch64::FMINNMv8f16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8121 } 8122 return 0; 8123} 8124 8125unsigned fastEmit_ISD_FMINNUM_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8126 if (RetVT.SimpleTy != MVT::v2f32) 8127 return 0; 8128 if ((Subtarget->hasNEON())) { 8129 return fastEmitInst_rr(AArch64::FMINNMv2f32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8130 } 8131 return 0; 8132} 8133 8134unsigned fastEmit_ISD_FMINNUM_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8135 if (RetVT.SimpleTy != MVT::v4f32) 8136 return 0; 8137 if ((Subtarget->hasNEON())) { 8138 return fastEmitInst_rr(AArch64::FMINNMv4f32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8139 } 8140 return 0; 8141} 8142 8143unsigned fastEmit_ISD_FMINNUM_MVT_v1f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8144 if (RetVT.SimpleTy != MVT::v1f64) 8145 return 0; 8146 return fastEmitInst_rr(AArch64::FMINNMDrr, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8147} 8148 8149unsigned fastEmit_ISD_FMINNUM_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8150 if (RetVT.SimpleTy != MVT::v2f64) 8151 return 0; 8152 if ((Subtarget->hasNEON())) { 8153 return fastEmitInst_rr(AArch64::FMINNMv2f64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8154 } 8155 return 0; 8156} 8157 8158unsigned fastEmit_ISD_FMINNUM_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8159 switch (VT.SimpleTy) { 8160 case MVT::f16: return fastEmit_ISD_FMINNUM_MVT_f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8161 case MVT::f32: return fastEmit_ISD_FMINNUM_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8162 case MVT::f64: return fastEmit_ISD_FMINNUM_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8163 case MVT::v4f16: return fastEmit_ISD_FMINNUM_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8164 case MVT::v8f16: return fastEmit_ISD_FMINNUM_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8165 case MVT::v2f32: return fastEmit_ISD_FMINNUM_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8166 case MVT::v4f32: return fastEmit_ISD_FMINNUM_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8167 case MVT::v1f64: return fastEmit_ISD_FMINNUM_MVT_v1f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8168 case MVT::v2f64: return fastEmit_ISD_FMINNUM_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8169 default: return 0; 8170 } 8171} 8172 8173// FastEmit functions for ISD::FMUL. 8174 8175unsigned fastEmit_ISD_FMUL_MVT_f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8176 if (RetVT.SimpleTy != MVT::f16) 8177 return 0; 8178 if ((Subtarget->hasFullFP16())) { 8179 return fastEmitInst_rr(AArch64::FMULHrr, &AArch64::FPR16RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8180 } 8181 return 0; 8182} 8183 8184unsigned fastEmit_ISD_FMUL_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8185 if (RetVT.SimpleTy != MVT::f32) 8186 return 0; 8187 if ((Subtarget->hasFPARMv8())) { 8188 return fastEmitInst_rr(AArch64::FMULSrr, &AArch64::FPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8189 } 8190 return 0; 8191} 8192 8193unsigned fastEmit_ISD_FMUL_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8194 if (RetVT.SimpleTy != MVT::f64) 8195 return 0; 8196 if ((Subtarget->hasFPARMv8())) { 8197 return fastEmitInst_rr(AArch64::FMULDrr, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8198 } 8199 return 0; 8200} 8201 8202unsigned fastEmit_ISD_FMUL_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8203 if (RetVT.SimpleTy != MVT::v4f16) 8204 return 0; 8205 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 8206 return fastEmitInst_rr(AArch64::FMULv4f16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8207 } 8208 return 0; 8209} 8210 8211unsigned fastEmit_ISD_FMUL_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8212 if (RetVT.SimpleTy != MVT::v8f16) 8213 return 0; 8214 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 8215 return fastEmitInst_rr(AArch64::FMULv8f16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8216 } 8217 return 0; 8218} 8219 8220unsigned fastEmit_ISD_FMUL_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8221 if (RetVT.SimpleTy != MVT::v2f32) 8222 return 0; 8223 if ((Subtarget->hasNEON())) { 8224 return fastEmitInst_rr(AArch64::FMULv2f32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8225 } 8226 return 0; 8227} 8228 8229unsigned fastEmit_ISD_FMUL_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8230 if (RetVT.SimpleTy != MVT::v4f32) 8231 return 0; 8232 if ((Subtarget->hasNEON())) { 8233 return fastEmitInst_rr(AArch64::FMULv4f32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8234 } 8235 return 0; 8236} 8237 8238unsigned fastEmit_ISD_FMUL_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8239 if (RetVT.SimpleTy != MVT::v2f64) 8240 return 0; 8241 if ((Subtarget->hasNEON())) { 8242 return fastEmitInst_rr(AArch64::FMULv2f64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8243 } 8244 return 0; 8245} 8246 8247unsigned fastEmit_ISD_FMUL_MVT_nxv8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8248 if (RetVT.SimpleTy != MVT::nxv8f16) 8249 return 0; 8250 if ((Subtarget->hasSVE())) { 8251 return fastEmitInst_rr(AArch64::FMUL_ZZZ_H, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8252 } 8253 return 0; 8254} 8255 8256unsigned fastEmit_ISD_FMUL_MVT_nxv4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8257 if (RetVT.SimpleTy != MVT::nxv4f32) 8258 return 0; 8259 if ((Subtarget->hasSVE())) { 8260 return fastEmitInst_rr(AArch64::FMUL_ZZZ_S, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8261 } 8262 return 0; 8263} 8264 8265unsigned fastEmit_ISD_FMUL_MVT_nxv2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8266 if (RetVT.SimpleTy != MVT::nxv2f64) 8267 return 0; 8268 if ((Subtarget->hasSVE())) { 8269 return fastEmitInst_rr(AArch64::FMUL_ZZZ_D, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8270 } 8271 return 0; 8272} 8273 8274unsigned fastEmit_ISD_FMUL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8275 switch (VT.SimpleTy) { 8276 case MVT::f16: return fastEmit_ISD_FMUL_MVT_f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8277 case MVT::f32: return fastEmit_ISD_FMUL_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8278 case MVT::f64: return fastEmit_ISD_FMUL_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8279 case MVT::v4f16: return fastEmit_ISD_FMUL_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8280 case MVT::v8f16: return fastEmit_ISD_FMUL_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8281 case MVT::v2f32: return fastEmit_ISD_FMUL_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8282 case MVT::v4f32: return fastEmit_ISD_FMUL_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8283 case MVT::v2f64: return fastEmit_ISD_FMUL_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8284 case MVT::nxv8f16: return fastEmit_ISD_FMUL_MVT_nxv8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8285 case MVT::nxv4f32: return fastEmit_ISD_FMUL_MVT_nxv4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8286 case MVT::nxv2f64: return fastEmit_ISD_FMUL_MVT_nxv2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8287 default: return 0; 8288 } 8289} 8290 8291// FastEmit functions for ISD::FSUB. 8292 8293unsigned fastEmit_ISD_FSUB_MVT_f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8294 if (RetVT.SimpleTy != MVT::f16) 8295 return 0; 8296 if ((Subtarget->hasFullFP16())) { 8297 return fastEmitInst_rr(AArch64::FSUBHrr, &AArch64::FPR16RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8298 } 8299 return 0; 8300} 8301 8302unsigned fastEmit_ISD_FSUB_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8303 if (RetVT.SimpleTy != MVT::f32) 8304 return 0; 8305 if ((Subtarget->hasFPARMv8())) { 8306 return fastEmitInst_rr(AArch64::FSUBSrr, &AArch64::FPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8307 } 8308 return 0; 8309} 8310 8311unsigned fastEmit_ISD_FSUB_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8312 if (RetVT.SimpleTy != MVT::f64) 8313 return 0; 8314 if ((Subtarget->hasFPARMv8())) { 8315 return fastEmitInst_rr(AArch64::FSUBDrr, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8316 } 8317 return 0; 8318} 8319 8320unsigned fastEmit_ISD_FSUB_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8321 if (RetVT.SimpleTy != MVT::v4f16) 8322 return 0; 8323 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 8324 return fastEmitInst_rr(AArch64::FSUBv4f16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8325 } 8326 return 0; 8327} 8328 8329unsigned fastEmit_ISD_FSUB_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8330 if (RetVT.SimpleTy != MVT::v8f16) 8331 return 0; 8332 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 8333 return fastEmitInst_rr(AArch64::FSUBv8f16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8334 } 8335 return 0; 8336} 8337 8338unsigned fastEmit_ISD_FSUB_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8339 if (RetVT.SimpleTy != MVT::v2f32) 8340 return 0; 8341 if ((Subtarget->hasNEON())) { 8342 return fastEmitInst_rr(AArch64::FSUBv2f32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8343 } 8344 return 0; 8345} 8346 8347unsigned fastEmit_ISD_FSUB_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8348 if (RetVT.SimpleTy != MVT::v4f32) 8349 return 0; 8350 if ((Subtarget->hasNEON())) { 8351 return fastEmitInst_rr(AArch64::FSUBv4f32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8352 } 8353 return 0; 8354} 8355 8356unsigned fastEmit_ISD_FSUB_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8357 if (RetVT.SimpleTy != MVT::v2f64) 8358 return 0; 8359 if ((Subtarget->hasNEON())) { 8360 return fastEmitInst_rr(AArch64::FSUBv2f64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8361 } 8362 return 0; 8363} 8364 8365unsigned fastEmit_ISD_FSUB_MVT_nxv8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8366 if (RetVT.SimpleTy != MVT::nxv8f16) 8367 return 0; 8368 if ((Subtarget->hasSVE())) { 8369 return fastEmitInst_rr(AArch64::FSUB_ZZZ_H, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8370 } 8371 return 0; 8372} 8373 8374unsigned fastEmit_ISD_FSUB_MVT_nxv4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8375 if (RetVT.SimpleTy != MVT::nxv4f32) 8376 return 0; 8377 if ((Subtarget->hasSVE())) { 8378 return fastEmitInst_rr(AArch64::FSUB_ZZZ_S, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8379 } 8380 return 0; 8381} 8382 8383unsigned fastEmit_ISD_FSUB_MVT_nxv2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8384 if (RetVT.SimpleTy != MVT::nxv2f64) 8385 return 0; 8386 if ((Subtarget->hasSVE())) { 8387 return fastEmitInst_rr(AArch64::FSUB_ZZZ_D, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8388 } 8389 return 0; 8390} 8391 8392unsigned fastEmit_ISD_FSUB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8393 switch (VT.SimpleTy) { 8394 case MVT::f16: return fastEmit_ISD_FSUB_MVT_f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8395 case MVT::f32: return fastEmit_ISD_FSUB_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8396 case MVT::f64: return fastEmit_ISD_FSUB_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8397 case MVT::v4f16: return fastEmit_ISD_FSUB_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8398 case MVT::v8f16: return fastEmit_ISD_FSUB_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8399 case MVT::v2f32: return fastEmit_ISD_FSUB_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8400 case MVT::v4f32: return fastEmit_ISD_FSUB_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8401 case MVT::v2f64: return fastEmit_ISD_FSUB_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8402 case MVT::nxv8f16: return fastEmit_ISD_FSUB_MVT_nxv8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8403 case MVT::nxv4f32: return fastEmit_ISD_FSUB_MVT_nxv4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8404 case MVT::nxv2f64: return fastEmit_ISD_FSUB_MVT_nxv2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8405 default: return 0; 8406 } 8407} 8408 8409// FastEmit functions for ISD::MUL. 8410 8411unsigned fastEmit_ISD_MUL_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8412 if (RetVT.SimpleTy != MVT::v8i8) 8413 return 0; 8414 if ((Subtarget->hasNEON())) { 8415 return fastEmitInst_rr(AArch64::MULv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8416 } 8417 return 0; 8418} 8419 8420unsigned fastEmit_ISD_MUL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8421 if (RetVT.SimpleTy != MVT::v16i8) 8422 return 0; 8423 if ((Subtarget->hasNEON())) { 8424 return fastEmitInst_rr(AArch64::MULv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8425 } 8426 return 0; 8427} 8428 8429unsigned fastEmit_ISD_MUL_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8430 if (RetVT.SimpleTy != MVT::v4i16) 8431 return 0; 8432 if ((Subtarget->hasNEON())) { 8433 return fastEmitInst_rr(AArch64::MULv4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8434 } 8435 return 0; 8436} 8437 8438unsigned fastEmit_ISD_MUL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8439 if (RetVT.SimpleTy != MVT::v8i16) 8440 return 0; 8441 if ((Subtarget->hasNEON())) { 8442 return fastEmitInst_rr(AArch64::MULv8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8443 } 8444 return 0; 8445} 8446 8447unsigned fastEmit_ISD_MUL_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8448 if (RetVT.SimpleTy != MVT::v2i32) 8449 return 0; 8450 if ((Subtarget->hasNEON())) { 8451 return fastEmitInst_rr(AArch64::MULv2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8452 } 8453 return 0; 8454} 8455 8456unsigned fastEmit_ISD_MUL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8457 if (RetVT.SimpleTy != MVT::v4i32) 8458 return 0; 8459 if ((Subtarget->hasNEON())) { 8460 return fastEmitInst_rr(AArch64::MULv4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8461 } 8462 return 0; 8463} 8464 8465unsigned fastEmit_ISD_MUL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8466 switch (VT.SimpleTy) { 8467 case MVT::v8i8: return fastEmit_ISD_MUL_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8468 case MVT::v16i8: return fastEmit_ISD_MUL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8469 case MVT::v4i16: return fastEmit_ISD_MUL_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8470 case MVT::v8i16: return fastEmit_ISD_MUL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8471 case MVT::v2i32: return fastEmit_ISD_MUL_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8472 case MVT::v4i32: return fastEmit_ISD_MUL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8473 default: return 0; 8474 } 8475} 8476 8477// FastEmit functions for ISD::MULHS. 8478 8479unsigned fastEmit_ISD_MULHS_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8480 if (RetVT.SimpleTy != MVT::i64) 8481 return 0; 8482 return fastEmitInst_rr(AArch64::SMULHrr, &AArch64::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8483} 8484 8485unsigned fastEmit_ISD_MULHS_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8486 switch (VT.SimpleTy) { 8487 case MVT::i64: return fastEmit_ISD_MULHS_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8488 default: return 0; 8489 } 8490} 8491 8492// FastEmit functions for ISD::MULHU. 8493 8494unsigned fastEmit_ISD_MULHU_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8495 if (RetVT.SimpleTy != MVT::i64) 8496 return 0; 8497 return fastEmitInst_rr(AArch64::UMULHrr, &AArch64::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8498} 8499 8500unsigned fastEmit_ISD_MULHU_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8501 switch (VT.SimpleTy) { 8502 case MVT::i64: return fastEmit_ISD_MULHU_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8503 default: return 0; 8504 } 8505} 8506 8507// FastEmit functions for ISD::OR. 8508 8509unsigned fastEmit_ISD_OR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8510 if (RetVT.SimpleTy != MVT::i32) 8511 return 0; 8512 return fastEmitInst_rr(AArch64::ORRWrr, &AArch64::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8513} 8514 8515unsigned fastEmit_ISD_OR_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8516 if (RetVT.SimpleTy != MVT::i64) 8517 return 0; 8518 return fastEmitInst_rr(AArch64::ORRXrr, &AArch64::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8519} 8520 8521unsigned fastEmit_ISD_OR_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8522 if (RetVT.SimpleTy != MVT::v8i8) 8523 return 0; 8524 if ((Subtarget->hasNEON())) { 8525 return fastEmitInst_rr(AArch64::ORRv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8526 } 8527 return 0; 8528} 8529 8530unsigned fastEmit_ISD_OR_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8531 if (RetVT.SimpleTy != MVT::v16i8) 8532 return 0; 8533 if ((Subtarget->hasNEON())) { 8534 return fastEmitInst_rr(AArch64::ORRv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8535 } 8536 return 0; 8537} 8538 8539unsigned fastEmit_ISD_OR_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8540 if (RetVT.SimpleTy != MVT::v4i16) 8541 return 0; 8542 if ((Subtarget->hasNEON())) { 8543 return fastEmitInst_rr(AArch64::ORRv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8544 } 8545 return 0; 8546} 8547 8548unsigned fastEmit_ISD_OR_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8549 if (RetVT.SimpleTy != MVT::v8i16) 8550 return 0; 8551 if ((Subtarget->hasNEON())) { 8552 return fastEmitInst_rr(AArch64::ORRv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8553 } 8554 return 0; 8555} 8556 8557unsigned fastEmit_ISD_OR_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8558 if (RetVT.SimpleTy != MVT::v2i32) 8559 return 0; 8560 if ((Subtarget->hasNEON())) { 8561 return fastEmitInst_rr(AArch64::ORRv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8562 } 8563 return 0; 8564} 8565 8566unsigned fastEmit_ISD_OR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8567 if (RetVT.SimpleTy != MVT::v4i32) 8568 return 0; 8569 if ((Subtarget->hasNEON())) { 8570 return fastEmitInst_rr(AArch64::ORRv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8571 } 8572 return 0; 8573} 8574 8575unsigned fastEmit_ISD_OR_MVT_v1i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8576 if (RetVT.SimpleTy != MVT::v1i64) 8577 return 0; 8578 if ((Subtarget->hasNEON())) { 8579 return fastEmitInst_rr(AArch64::ORRv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8580 } 8581 return 0; 8582} 8583 8584unsigned fastEmit_ISD_OR_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8585 if (RetVT.SimpleTy != MVT::v2i64) 8586 return 0; 8587 if ((Subtarget->hasNEON())) { 8588 return fastEmitInst_rr(AArch64::ORRv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8589 } 8590 return 0; 8591} 8592 8593unsigned fastEmit_ISD_OR_MVT_nxv16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8594 if (RetVT.SimpleTy != MVT::nxv16i8) 8595 return 0; 8596 if ((Subtarget->hasSVE())) { 8597 return fastEmitInst_rr(AArch64::ORR_ZZZ, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8598 } 8599 return 0; 8600} 8601 8602unsigned fastEmit_ISD_OR_MVT_nxv8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8603 if (RetVT.SimpleTy != MVT::nxv8i16) 8604 return 0; 8605 if ((Subtarget->hasSVE())) { 8606 return fastEmitInst_rr(AArch64::ORR_ZZZ, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8607 } 8608 return 0; 8609} 8610 8611unsigned fastEmit_ISD_OR_MVT_nxv4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8612 if (RetVT.SimpleTy != MVT::nxv4i32) 8613 return 0; 8614 if ((Subtarget->hasSVE())) { 8615 return fastEmitInst_rr(AArch64::ORR_ZZZ, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8616 } 8617 return 0; 8618} 8619 8620unsigned fastEmit_ISD_OR_MVT_nxv2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8621 if (RetVT.SimpleTy != MVT::nxv2i64) 8622 return 0; 8623 if ((Subtarget->hasSVE())) { 8624 return fastEmitInst_rr(AArch64::ORR_ZZZ, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8625 } 8626 return 0; 8627} 8628 8629unsigned fastEmit_ISD_OR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8630 switch (VT.SimpleTy) { 8631 case MVT::i32: return fastEmit_ISD_OR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8632 case MVT::i64: return fastEmit_ISD_OR_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8633 case MVT::v8i8: return fastEmit_ISD_OR_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8634 case MVT::v16i8: return fastEmit_ISD_OR_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8635 case MVT::v4i16: return fastEmit_ISD_OR_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8636 case MVT::v8i16: return fastEmit_ISD_OR_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8637 case MVT::v2i32: return fastEmit_ISD_OR_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8638 case MVT::v4i32: return fastEmit_ISD_OR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8639 case MVT::v1i64: return fastEmit_ISD_OR_MVT_v1i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8640 case MVT::v2i64: return fastEmit_ISD_OR_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8641 case MVT::nxv16i8: return fastEmit_ISD_OR_MVT_nxv16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8642 case MVT::nxv8i16: return fastEmit_ISD_OR_MVT_nxv8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8643 case MVT::nxv4i32: return fastEmit_ISD_OR_MVT_nxv4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8644 case MVT::nxv2i64: return fastEmit_ISD_OR_MVT_nxv2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8645 default: return 0; 8646 } 8647} 8648 8649// FastEmit functions for ISD::ROTR. 8650 8651unsigned fastEmit_ISD_ROTR_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8652 if (RetVT.SimpleTy != MVT::i64) 8653 return 0; 8654 return fastEmitInst_rr(AArch64::RORVXr, &AArch64::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8655} 8656 8657unsigned fastEmit_ISD_ROTR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8658 switch (VT.SimpleTy) { 8659 case MVT::i64: return fastEmit_ISD_ROTR_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8660 default: return 0; 8661 } 8662} 8663 8664// FastEmit functions for ISD::SADDSAT. 8665 8666unsigned fastEmit_ISD_SADDSAT_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8667 if (RetVT.SimpleTy != MVT::v8i8) 8668 return 0; 8669 if ((Subtarget->hasNEON())) { 8670 return fastEmitInst_rr(AArch64::SQADDv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8671 } 8672 return 0; 8673} 8674 8675unsigned fastEmit_ISD_SADDSAT_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8676 if (RetVT.SimpleTy != MVT::v16i8) 8677 return 0; 8678 if ((Subtarget->hasNEON())) { 8679 return fastEmitInst_rr(AArch64::SQADDv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8680 } 8681 return 0; 8682} 8683 8684unsigned fastEmit_ISD_SADDSAT_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8685 if (RetVT.SimpleTy != MVT::v4i16) 8686 return 0; 8687 if ((Subtarget->hasNEON())) { 8688 return fastEmitInst_rr(AArch64::SQADDv4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8689 } 8690 return 0; 8691} 8692 8693unsigned fastEmit_ISD_SADDSAT_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8694 if (RetVT.SimpleTy != MVT::v8i16) 8695 return 0; 8696 if ((Subtarget->hasNEON())) { 8697 return fastEmitInst_rr(AArch64::SQADDv8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8698 } 8699 return 0; 8700} 8701 8702unsigned fastEmit_ISD_SADDSAT_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8703 if (RetVT.SimpleTy != MVT::v2i32) 8704 return 0; 8705 if ((Subtarget->hasNEON())) { 8706 return fastEmitInst_rr(AArch64::SQADDv2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8707 } 8708 return 0; 8709} 8710 8711unsigned fastEmit_ISD_SADDSAT_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8712 if (RetVT.SimpleTy != MVT::v4i32) 8713 return 0; 8714 if ((Subtarget->hasNEON())) { 8715 return fastEmitInst_rr(AArch64::SQADDv4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8716 } 8717 return 0; 8718} 8719 8720unsigned fastEmit_ISD_SADDSAT_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8721 if (RetVT.SimpleTy != MVT::v2i64) 8722 return 0; 8723 if ((Subtarget->hasNEON())) { 8724 return fastEmitInst_rr(AArch64::SQADDv2i64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8725 } 8726 return 0; 8727} 8728 8729unsigned fastEmit_ISD_SADDSAT_MVT_nxv16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8730 if (RetVT.SimpleTy != MVT::nxv16i8) 8731 return 0; 8732 if ((Subtarget->hasSVE())) { 8733 return fastEmitInst_rr(AArch64::SQADD_ZZZ_B, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8734 } 8735 return 0; 8736} 8737 8738unsigned fastEmit_ISD_SADDSAT_MVT_nxv8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8739 if (RetVT.SimpleTy != MVT::nxv8i16) 8740 return 0; 8741 if ((Subtarget->hasSVE())) { 8742 return fastEmitInst_rr(AArch64::SQADD_ZZZ_H, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8743 } 8744 return 0; 8745} 8746 8747unsigned fastEmit_ISD_SADDSAT_MVT_nxv4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8748 if (RetVT.SimpleTy != MVT::nxv4i32) 8749 return 0; 8750 if ((Subtarget->hasSVE())) { 8751 return fastEmitInst_rr(AArch64::SQADD_ZZZ_S, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8752 } 8753 return 0; 8754} 8755 8756unsigned fastEmit_ISD_SADDSAT_MVT_nxv2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8757 if (RetVT.SimpleTy != MVT::nxv2i64) 8758 return 0; 8759 if ((Subtarget->hasSVE())) { 8760 return fastEmitInst_rr(AArch64::SQADD_ZZZ_D, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8761 } 8762 return 0; 8763} 8764 8765unsigned fastEmit_ISD_SADDSAT_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8766 switch (VT.SimpleTy) { 8767 case MVT::v8i8: return fastEmit_ISD_SADDSAT_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8768 case MVT::v16i8: return fastEmit_ISD_SADDSAT_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8769 case MVT::v4i16: return fastEmit_ISD_SADDSAT_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8770 case MVT::v8i16: return fastEmit_ISD_SADDSAT_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8771 case MVT::v2i32: return fastEmit_ISD_SADDSAT_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8772 case MVT::v4i32: return fastEmit_ISD_SADDSAT_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8773 case MVT::v2i64: return fastEmit_ISD_SADDSAT_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8774 case MVT::nxv16i8: return fastEmit_ISD_SADDSAT_MVT_nxv16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8775 case MVT::nxv8i16: return fastEmit_ISD_SADDSAT_MVT_nxv8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8776 case MVT::nxv4i32: return fastEmit_ISD_SADDSAT_MVT_nxv4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8777 case MVT::nxv2i64: return fastEmit_ISD_SADDSAT_MVT_nxv2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8778 default: return 0; 8779 } 8780} 8781 8782// FastEmit functions for ISD::SDIV. 8783 8784unsigned fastEmit_ISD_SDIV_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8785 if (RetVT.SimpleTy != MVT::i32) 8786 return 0; 8787 return fastEmitInst_rr(AArch64::SDIVWr, &AArch64::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8788} 8789 8790unsigned fastEmit_ISD_SDIV_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8791 if (RetVT.SimpleTy != MVT::i64) 8792 return 0; 8793 return fastEmitInst_rr(AArch64::SDIVXr, &AArch64::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8794} 8795 8796unsigned fastEmit_ISD_SDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8797 switch (VT.SimpleTy) { 8798 case MVT::i32: return fastEmit_ISD_SDIV_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8799 case MVT::i64: return fastEmit_ISD_SDIV_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8800 default: return 0; 8801 } 8802} 8803 8804// FastEmit functions for ISD::SHL. 8805 8806unsigned fastEmit_ISD_SHL_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8807 if (RetVT.SimpleTy != MVT::i64) 8808 return 0; 8809 return fastEmitInst_rr(AArch64::LSLVXr, &AArch64::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8810} 8811 8812unsigned fastEmit_ISD_SHL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8813 switch (VT.SimpleTy) { 8814 case MVT::i64: return fastEmit_ISD_SHL_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8815 default: return 0; 8816 } 8817} 8818 8819// FastEmit functions for ISD::SMAX. 8820 8821unsigned fastEmit_ISD_SMAX_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8822 if (RetVT.SimpleTy != MVT::v8i8) 8823 return 0; 8824 if ((Subtarget->hasNEON())) { 8825 return fastEmitInst_rr(AArch64::SMAXv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8826 } 8827 return 0; 8828} 8829 8830unsigned fastEmit_ISD_SMAX_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8831 if (RetVT.SimpleTy != MVT::v16i8) 8832 return 0; 8833 if ((Subtarget->hasNEON())) { 8834 return fastEmitInst_rr(AArch64::SMAXv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8835 } 8836 return 0; 8837} 8838 8839unsigned fastEmit_ISD_SMAX_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8840 if (RetVT.SimpleTy != MVT::v4i16) 8841 return 0; 8842 if ((Subtarget->hasNEON())) { 8843 return fastEmitInst_rr(AArch64::SMAXv4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8844 } 8845 return 0; 8846} 8847 8848unsigned fastEmit_ISD_SMAX_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8849 if (RetVT.SimpleTy != MVT::v8i16) 8850 return 0; 8851 if ((Subtarget->hasNEON())) { 8852 return fastEmitInst_rr(AArch64::SMAXv8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8853 } 8854 return 0; 8855} 8856 8857unsigned fastEmit_ISD_SMAX_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8858 if (RetVT.SimpleTy != MVT::v2i32) 8859 return 0; 8860 if ((Subtarget->hasNEON())) { 8861 return fastEmitInst_rr(AArch64::SMAXv2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8862 } 8863 return 0; 8864} 8865 8866unsigned fastEmit_ISD_SMAX_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8867 if (RetVT.SimpleTy != MVT::v4i32) 8868 return 0; 8869 if ((Subtarget->hasNEON())) { 8870 return fastEmitInst_rr(AArch64::SMAXv4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8871 } 8872 return 0; 8873} 8874 8875unsigned fastEmit_ISD_SMAX_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8876 switch (VT.SimpleTy) { 8877 case MVT::v8i8: return fastEmit_ISD_SMAX_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8878 case MVT::v16i8: return fastEmit_ISD_SMAX_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8879 case MVT::v4i16: return fastEmit_ISD_SMAX_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8880 case MVT::v8i16: return fastEmit_ISD_SMAX_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8881 case MVT::v2i32: return fastEmit_ISD_SMAX_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8882 case MVT::v4i32: return fastEmit_ISD_SMAX_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8883 default: return 0; 8884 } 8885} 8886 8887// FastEmit functions for ISD::SMIN. 8888 8889unsigned fastEmit_ISD_SMIN_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8890 if (RetVT.SimpleTy != MVT::v8i8) 8891 return 0; 8892 if ((Subtarget->hasNEON())) { 8893 return fastEmitInst_rr(AArch64::SMINv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8894 } 8895 return 0; 8896} 8897 8898unsigned fastEmit_ISD_SMIN_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8899 if (RetVT.SimpleTy != MVT::v16i8) 8900 return 0; 8901 if ((Subtarget->hasNEON())) { 8902 return fastEmitInst_rr(AArch64::SMINv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8903 } 8904 return 0; 8905} 8906 8907unsigned fastEmit_ISD_SMIN_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8908 if (RetVT.SimpleTy != MVT::v4i16) 8909 return 0; 8910 if ((Subtarget->hasNEON())) { 8911 return fastEmitInst_rr(AArch64::SMINv4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8912 } 8913 return 0; 8914} 8915 8916unsigned fastEmit_ISD_SMIN_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8917 if (RetVT.SimpleTy != MVT::v8i16) 8918 return 0; 8919 if ((Subtarget->hasNEON())) { 8920 return fastEmitInst_rr(AArch64::SMINv8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8921 } 8922 return 0; 8923} 8924 8925unsigned fastEmit_ISD_SMIN_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8926 if (RetVT.SimpleTy != MVT::v2i32) 8927 return 0; 8928 if ((Subtarget->hasNEON())) { 8929 return fastEmitInst_rr(AArch64::SMINv2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8930 } 8931 return 0; 8932} 8933 8934unsigned fastEmit_ISD_SMIN_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8935 if (RetVT.SimpleTy != MVT::v4i32) 8936 return 0; 8937 if ((Subtarget->hasNEON())) { 8938 return fastEmitInst_rr(AArch64::SMINv4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8939 } 8940 return 0; 8941} 8942 8943unsigned fastEmit_ISD_SMIN_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8944 switch (VT.SimpleTy) { 8945 case MVT::v8i8: return fastEmit_ISD_SMIN_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8946 case MVT::v16i8: return fastEmit_ISD_SMIN_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8947 case MVT::v4i16: return fastEmit_ISD_SMIN_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8948 case MVT::v8i16: return fastEmit_ISD_SMIN_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8949 case MVT::v2i32: return fastEmit_ISD_SMIN_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8950 case MVT::v4i32: return fastEmit_ISD_SMIN_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8951 default: return 0; 8952 } 8953} 8954 8955// FastEmit functions for ISD::SRA. 8956 8957unsigned fastEmit_ISD_SRA_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8958 if (RetVT.SimpleTy != MVT::i64) 8959 return 0; 8960 return fastEmitInst_rr(AArch64::ASRVXr, &AArch64::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8961} 8962 8963unsigned fastEmit_ISD_SRA_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8964 switch (VT.SimpleTy) { 8965 case MVT::i64: return fastEmit_ISD_SRA_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8966 default: return 0; 8967 } 8968} 8969 8970// FastEmit functions for ISD::SRL. 8971 8972unsigned fastEmit_ISD_SRL_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8973 if (RetVT.SimpleTy != MVT::i64) 8974 return 0; 8975 return fastEmitInst_rr(AArch64::LSRVXr, &AArch64::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8976} 8977 8978unsigned fastEmit_ISD_SRL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8979 switch (VT.SimpleTy) { 8980 case MVT::i64: return fastEmit_ISD_SRL_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 8981 default: return 0; 8982 } 8983} 8984 8985// FastEmit functions for ISD::SSUBSAT. 8986 8987unsigned fastEmit_ISD_SSUBSAT_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8988 if (RetVT.SimpleTy != MVT::v8i8) 8989 return 0; 8990 if ((Subtarget->hasNEON())) { 8991 return fastEmitInst_rr(AArch64::SQSUBv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 8992 } 8993 return 0; 8994} 8995 8996unsigned fastEmit_ISD_SSUBSAT_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 8997 if (RetVT.SimpleTy != MVT::v16i8) 8998 return 0; 8999 if ((Subtarget->hasNEON())) { 9000 return fastEmitInst_rr(AArch64::SQSUBv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9001 } 9002 return 0; 9003} 9004 9005unsigned fastEmit_ISD_SSUBSAT_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9006 if (RetVT.SimpleTy != MVT::v4i16) 9007 return 0; 9008 if ((Subtarget->hasNEON())) { 9009 return fastEmitInst_rr(AArch64::SQSUBv4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9010 } 9011 return 0; 9012} 9013 9014unsigned fastEmit_ISD_SSUBSAT_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9015 if (RetVT.SimpleTy != MVT::v8i16) 9016 return 0; 9017 if ((Subtarget->hasNEON())) { 9018 return fastEmitInst_rr(AArch64::SQSUBv8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9019 } 9020 return 0; 9021} 9022 9023unsigned fastEmit_ISD_SSUBSAT_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9024 if (RetVT.SimpleTy != MVT::v2i32) 9025 return 0; 9026 if ((Subtarget->hasNEON())) { 9027 return fastEmitInst_rr(AArch64::SQSUBv2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9028 } 9029 return 0; 9030} 9031 9032unsigned fastEmit_ISD_SSUBSAT_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9033 if (RetVT.SimpleTy != MVT::v4i32) 9034 return 0; 9035 if ((Subtarget->hasNEON())) { 9036 return fastEmitInst_rr(AArch64::SQSUBv4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9037 } 9038 return 0; 9039} 9040 9041unsigned fastEmit_ISD_SSUBSAT_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9042 if (RetVT.SimpleTy != MVT::v2i64) 9043 return 0; 9044 if ((Subtarget->hasNEON())) { 9045 return fastEmitInst_rr(AArch64::SQSUBv2i64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9046 } 9047 return 0; 9048} 9049 9050unsigned fastEmit_ISD_SSUBSAT_MVT_nxv16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9051 if (RetVT.SimpleTy != MVT::nxv16i8) 9052 return 0; 9053 if ((Subtarget->hasSVE())) { 9054 return fastEmitInst_rr(AArch64::SQSUB_ZZZ_B, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9055 } 9056 return 0; 9057} 9058 9059unsigned fastEmit_ISD_SSUBSAT_MVT_nxv8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9060 if (RetVT.SimpleTy != MVT::nxv8i16) 9061 return 0; 9062 if ((Subtarget->hasSVE())) { 9063 return fastEmitInst_rr(AArch64::SQSUB_ZZZ_H, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9064 } 9065 return 0; 9066} 9067 9068unsigned fastEmit_ISD_SSUBSAT_MVT_nxv4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9069 if (RetVT.SimpleTy != MVT::nxv4i32) 9070 return 0; 9071 if ((Subtarget->hasSVE())) { 9072 return fastEmitInst_rr(AArch64::SQSUB_ZZZ_S, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9073 } 9074 return 0; 9075} 9076 9077unsigned fastEmit_ISD_SSUBSAT_MVT_nxv2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9078 if (RetVT.SimpleTy != MVT::nxv2i64) 9079 return 0; 9080 if ((Subtarget->hasSVE())) { 9081 return fastEmitInst_rr(AArch64::SQSUB_ZZZ_D, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9082 } 9083 return 0; 9084} 9085 9086unsigned fastEmit_ISD_SSUBSAT_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9087 switch (VT.SimpleTy) { 9088 case MVT::v8i8: return fastEmit_ISD_SSUBSAT_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9089 case MVT::v16i8: return fastEmit_ISD_SSUBSAT_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9090 case MVT::v4i16: return fastEmit_ISD_SSUBSAT_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9091 case MVT::v8i16: return fastEmit_ISD_SSUBSAT_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9092 case MVT::v2i32: return fastEmit_ISD_SSUBSAT_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9093 case MVT::v4i32: return fastEmit_ISD_SSUBSAT_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9094 case MVT::v2i64: return fastEmit_ISD_SSUBSAT_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9095 case MVT::nxv16i8: return fastEmit_ISD_SSUBSAT_MVT_nxv16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9096 case MVT::nxv8i16: return fastEmit_ISD_SSUBSAT_MVT_nxv8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9097 case MVT::nxv4i32: return fastEmit_ISD_SSUBSAT_MVT_nxv4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9098 case MVT::nxv2i64: return fastEmit_ISD_SSUBSAT_MVT_nxv2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9099 default: return 0; 9100 } 9101} 9102 9103// FastEmit functions for ISD::SUB. 9104 9105unsigned fastEmit_ISD_SUB_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9106 if (RetVT.SimpleTy != MVT::i32) 9107 return 0; 9108 return fastEmitInst_rr(AArch64::SUBSWrr, &AArch64::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9109} 9110 9111unsigned fastEmit_ISD_SUB_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9112 if (RetVT.SimpleTy != MVT::i64) 9113 return 0; 9114 return fastEmitInst_rr(AArch64::SUBSXrr, &AArch64::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9115} 9116 9117unsigned fastEmit_ISD_SUB_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9118 if (RetVT.SimpleTy != MVT::v8i8) 9119 return 0; 9120 if ((Subtarget->hasNEON())) { 9121 return fastEmitInst_rr(AArch64::SUBv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9122 } 9123 return 0; 9124} 9125 9126unsigned fastEmit_ISD_SUB_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9127 if (RetVT.SimpleTy != MVT::v16i8) 9128 return 0; 9129 if ((Subtarget->hasNEON())) { 9130 return fastEmitInst_rr(AArch64::SUBv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9131 } 9132 return 0; 9133} 9134 9135unsigned fastEmit_ISD_SUB_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9136 if (RetVT.SimpleTy != MVT::v4i16) 9137 return 0; 9138 if ((Subtarget->hasNEON())) { 9139 return fastEmitInst_rr(AArch64::SUBv4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9140 } 9141 return 0; 9142} 9143 9144unsigned fastEmit_ISD_SUB_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9145 if (RetVT.SimpleTy != MVT::v8i16) 9146 return 0; 9147 if ((Subtarget->hasNEON())) { 9148 return fastEmitInst_rr(AArch64::SUBv8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9149 } 9150 return 0; 9151} 9152 9153unsigned fastEmit_ISD_SUB_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9154 if (RetVT.SimpleTy != MVT::v2i32) 9155 return 0; 9156 if ((Subtarget->hasNEON())) { 9157 return fastEmitInst_rr(AArch64::SUBv2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9158 } 9159 return 0; 9160} 9161 9162unsigned fastEmit_ISD_SUB_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9163 if (RetVT.SimpleTy != MVT::v4i32) 9164 return 0; 9165 if ((Subtarget->hasNEON())) { 9166 return fastEmitInst_rr(AArch64::SUBv4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9167 } 9168 return 0; 9169} 9170 9171unsigned fastEmit_ISD_SUB_MVT_v1i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9172 if (RetVT.SimpleTy != MVT::v1i64) 9173 return 0; 9174 if ((Subtarget->hasNEON())) { 9175 return fastEmitInst_rr(AArch64::SUBv1i64, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9176 } 9177 return 0; 9178} 9179 9180unsigned fastEmit_ISD_SUB_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9181 if (RetVT.SimpleTy != MVT::v2i64) 9182 return 0; 9183 if ((Subtarget->hasNEON())) { 9184 return fastEmitInst_rr(AArch64::SUBv2i64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9185 } 9186 return 0; 9187} 9188 9189unsigned fastEmit_ISD_SUB_MVT_nxv16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9190 if (RetVT.SimpleTy != MVT::nxv16i8) 9191 return 0; 9192 if ((Subtarget->hasSVE())) { 9193 return fastEmitInst_rr(AArch64::SUB_ZZZ_B, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9194 } 9195 return 0; 9196} 9197 9198unsigned fastEmit_ISD_SUB_MVT_nxv8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9199 if (RetVT.SimpleTy != MVT::nxv8i16) 9200 return 0; 9201 if ((Subtarget->hasSVE())) { 9202 return fastEmitInst_rr(AArch64::SUB_ZZZ_H, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9203 } 9204 return 0; 9205} 9206 9207unsigned fastEmit_ISD_SUB_MVT_nxv4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9208 if (RetVT.SimpleTy != MVT::nxv4i32) 9209 return 0; 9210 if ((Subtarget->hasSVE())) { 9211 return fastEmitInst_rr(AArch64::SUB_ZZZ_S, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9212 } 9213 return 0; 9214} 9215 9216unsigned fastEmit_ISD_SUB_MVT_nxv2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9217 if (RetVT.SimpleTy != MVT::nxv2i64) 9218 return 0; 9219 if ((Subtarget->hasSVE())) { 9220 return fastEmitInst_rr(AArch64::SUB_ZZZ_D, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9221 } 9222 return 0; 9223} 9224 9225unsigned fastEmit_ISD_SUB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9226 switch (VT.SimpleTy) { 9227 case MVT::i32: return fastEmit_ISD_SUB_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9228 case MVT::i64: return fastEmit_ISD_SUB_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9229 case MVT::v8i8: return fastEmit_ISD_SUB_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9230 case MVT::v16i8: return fastEmit_ISD_SUB_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9231 case MVT::v4i16: return fastEmit_ISD_SUB_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9232 case MVT::v8i16: return fastEmit_ISD_SUB_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9233 case MVT::v2i32: return fastEmit_ISD_SUB_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9234 case MVT::v4i32: return fastEmit_ISD_SUB_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9235 case MVT::v1i64: return fastEmit_ISD_SUB_MVT_v1i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9236 case MVT::v2i64: return fastEmit_ISD_SUB_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9237 case MVT::nxv16i8: return fastEmit_ISD_SUB_MVT_nxv16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9238 case MVT::nxv8i16: return fastEmit_ISD_SUB_MVT_nxv8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9239 case MVT::nxv4i32: return fastEmit_ISD_SUB_MVT_nxv4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9240 case MVT::nxv2i64: return fastEmit_ISD_SUB_MVT_nxv2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9241 default: return 0; 9242 } 9243} 9244 9245// FastEmit functions for ISD::UADDSAT. 9246 9247unsigned fastEmit_ISD_UADDSAT_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9248 if (RetVT.SimpleTy != MVT::v8i8) 9249 return 0; 9250 if ((Subtarget->hasNEON())) { 9251 return fastEmitInst_rr(AArch64::UQADDv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9252 } 9253 return 0; 9254} 9255 9256unsigned fastEmit_ISD_UADDSAT_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9257 if (RetVT.SimpleTy != MVT::v16i8) 9258 return 0; 9259 if ((Subtarget->hasNEON())) { 9260 return fastEmitInst_rr(AArch64::UQADDv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9261 } 9262 return 0; 9263} 9264 9265unsigned fastEmit_ISD_UADDSAT_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9266 if (RetVT.SimpleTy != MVT::v4i16) 9267 return 0; 9268 if ((Subtarget->hasNEON())) { 9269 return fastEmitInst_rr(AArch64::UQADDv4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9270 } 9271 return 0; 9272} 9273 9274unsigned fastEmit_ISD_UADDSAT_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9275 if (RetVT.SimpleTy != MVT::v8i16) 9276 return 0; 9277 if ((Subtarget->hasNEON())) { 9278 return fastEmitInst_rr(AArch64::UQADDv8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9279 } 9280 return 0; 9281} 9282 9283unsigned fastEmit_ISD_UADDSAT_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9284 if (RetVT.SimpleTy != MVT::v2i32) 9285 return 0; 9286 if ((Subtarget->hasNEON())) { 9287 return fastEmitInst_rr(AArch64::UQADDv2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9288 } 9289 return 0; 9290} 9291 9292unsigned fastEmit_ISD_UADDSAT_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9293 if (RetVT.SimpleTy != MVT::v4i32) 9294 return 0; 9295 if ((Subtarget->hasNEON())) { 9296 return fastEmitInst_rr(AArch64::UQADDv4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9297 } 9298 return 0; 9299} 9300 9301unsigned fastEmit_ISD_UADDSAT_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9302 if (RetVT.SimpleTy != MVT::v2i64) 9303 return 0; 9304 if ((Subtarget->hasNEON())) { 9305 return fastEmitInst_rr(AArch64::UQADDv2i64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9306 } 9307 return 0; 9308} 9309 9310unsigned fastEmit_ISD_UADDSAT_MVT_nxv16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9311 if (RetVT.SimpleTy != MVT::nxv16i8) 9312 return 0; 9313 if ((Subtarget->hasSVE())) { 9314 return fastEmitInst_rr(AArch64::UQADD_ZZZ_B, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9315 } 9316 return 0; 9317} 9318 9319unsigned fastEmit_ISD_UADDSAT_MVT_nxv8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9320 if (RetVT.SimpleTy != MVT::nxv8i16) 9321 return 0; 9322 if ((Subtarget->hasSVE())) { 9323 return fastEmitInst_rr(AArch64::UQADD_ZZZ_H, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9324 } 9325 return 0; 9326} 9327 9328unsigned fastEmit_ISD_UADDSAT_MVT_nxv4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9329 if (RetVT.SimpleTy != MVT::nxv4i32) 9330 return 0; 9331 if ((Subtarget->hasSVE())) { 9332 return fastEmitInst_rr(AArch64::UQADD_ZZZ_S, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9333 } 9334 return 0; 9335} 9336 9337unsigned fastEmit_ISD_UADDSAT_MVT_nxv2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9338 if (RetVT.SimpleTy != MVT::nxv2i64) 9339 return 0; 9340 if ((Subtarget->hasSVE())) { 9341 return fastEmitInst_rr(AArch64::UQADD_ZZZ_D, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9342 } 9343 return 0; 9344} 9345 9346unsigned fastEmit_ISD_UADDSAT_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9347 switch (VT.SimpleTy) { 9348 case MVT::v8i8: return fastEmit_ISD_UADDSAT_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9349 case MVT::v16i8: return fastEmit_ISD_UADDSAT_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9350 case MVT::v4i16: return fastEmit_ISD_UADDSAT_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9351 case MVT::v8i16: return fastEmit_ISD_UADDSAT_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9352 case MVT::v2i32: return fastEmit_ISD_UADDSAT_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9353 case MVT::v4i32: return fastEmit_ISD_UADDSAT_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9354 case MVT::v2i64: return fastEmit_ISD_UADDSAT_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9355 case MVT::nxv16i8: return fastEmit_ISD_UADDSAT_MVT_nxv16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9356 case MVT::nxv8i16: return fastEmit_ISD_UADDSAT_MVT_nxv8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9357 case MVT::nxv4i32: return fastEmit_ISD_UADDSAT_MVT_nxv4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9358 case MVT::nxv2i64: return fastEmit_ISD_UADDSAT_MVT_nxv2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9359 default: return 0; 9360 } 9361} 9362 9363// FastEmit functions for ISD::UDIV. 9364 9365unsigned fastEmit_ISD_UDIV_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9366 if (RetVT.SimpleTy != MVT::i32) 9367 return 0; 9368 return fastEmitInst_rr(AArch64::UDIVWr, &AArch64::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9369} 9370 9371unsigned fastEmit_ISD_UDIV_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9372 if (RetVT.SimpleTy != MVT::i64) 9373 return 0; 9374 return fastEmitInst_rr(AArch64::UDIVXr, &AArch64::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9375} 9376 9377unsigned fastEmit_ISD_UDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9378 switch (VT.SimpleTy) { 9379 case MVT::i32: return fastEmit_ISD_UDIV_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9380 case MVT::i64: return fastEmit_ISD_UDIV_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9381 default: return 0; 9382 } 9383} 9384 9385// FastEmit functions for ISD::UMAX. 9386 9387unsigned fastEmit_ISD_UMAX_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9388 if (RetVT.SimpleTy != MVT::v8i8) 9389 return 0; 9390 if ((Subtarget->hasNEON())) { 9391 return fastEmitInst_rr(AArch64::UMAXv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9392 } 9393 return 0; 9394} 9395 9396unsigned fastEmit_ISD_UMAX_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9397 if (RetVT.SimpleTy != MVT::v16i8) 9398 return 0; 9399 if ((Subtarget->hasNEON())) { 9400 return fastEmitInst_rr(AArch64::UMAXv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9401 } 9402 return 0; 9403} 9404 9405unsigned fastEmit_ISD_UMAX_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9406 if (RetVT.SimpleTy != MVT::v4i16) 9407 return 0; 9408 if ((Subtarget->hasNEON())) { 9409 return fastEmitInst_rr(AArch64::UMAXv4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9410 } 9411 return 0; 9412} 9413 9414unsigned fastEmit_ISD_UMAX_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9415 if (RetVT.SimpleTy != MVT::v8i16) 9416 return 0; 9417 if ((Subtarget->hasNEON())) { 9418 return fastEmitInst_rr(AArch64::UMAXv8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9419 } 9420 return 0; 9421} 9422 9423unsigned fastEmit_ISD_UMAX_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9424 if (RetVT.SimpleTy != MVT::v2i32) 9425 return 0; 9426 if ((Subtarget->hasNEON())) { 9427 return fastEmitInst_rr(AArch64::UMAXv2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9428 } 9429 return 0; 9430} 9431 9432unsigned fastEmit_ISD_UMAX_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9433 if (RetVT.SimpleTy != MVT::v4i32) 9434 return 0; 9435 if ((Subtarget->hasNEON())) { 9436 return fastEmitInst_rr(AArch64::UMAXv4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9437 } 9438 return 0; 9439} 9440 9441unsigned fastEmit_ISD_UMAX_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9442 switch (VT.SimpleTy) { 9443 case MVT::v8i8: return fastEmit_ISD_UMAX_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9444 case MVT::v16i8: return fastEmit_ISD_UMAX_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9445 case MVT::v4i16: return fastEmit_ISD_UMAX_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9446 case MVT::v8i16: return fastEmit_ISD_UMAX_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9447 case MVT::v2i32: return fastEmit_ISD_UMAX_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9448 case MVT::v4i32: return fastEmit_ISD_UMAX_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9449 default: return 0; 9450 } 9451} 9452 9453// FastEmit functions for ISD::UMIN. 9454 9455unsigned fastEmit_ISD_UMIN_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9456 if (RetVT.SimpleTy != MVT::v8i8) 9457 return 0; 9458 if ((Subtarget->hasNEON())) { 9459 return fastEmitInst_rr(AArch64::UMINv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9460 } 9461 return 0; 9462} 9463 9464unsigned fastEmit_ISD_UMIN_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9465 if (RetVT.SimpleTy != MVT::v16i8) 9466 return 0; 9467 if ((Subtarget->hasNEON())) { 9468 return fastEmitInst_rr(AArch64::UMINv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9469 } 9470 return 0; 9471} 9472 9473unsigned fastEmit_ISD_UMIN_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9474 if (RetVT.SimpleTy != MVT::v4i16) 9475 return 0; 9476 if ((Subtarget->hasNEON())) { 9477 return fastEmitInst_rr(AArch64::UMINv4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9478 } 9479 return 0; 9480} 9481 9482unsigned fastEmit_ISD_UMIN_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9483 if (RetVT.SimpleTy != MVT::v8i16) 9484 return 0; 9485 if ((Subtarget->hasNEON())) { 9486 return fastEmitInst_rr(AArch64::UMINv8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9487 } 9488 return 0; 9489} 9490 9491unsigned fastEmit_ISD_UMIN_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9492 if (RetVT.SimpleTy != MVT::v2i32) 9493 return 0; 9494 if ((Subtarget->hasNEON())) { 9495 return fastEmitInst_rr(AArch64::UMINv2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9496 } 9497 return 0; 9498} 9499 9500unsigned fastEmit_ISD_UMIN_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9501 if (RetVT.SimpleTy != MVT::v4i32) 9502 return 0; 9503 if ((Subtarget->hasNEON())) { 9504 return fastEmitInst_rr(AArch64::UMINv4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9505 } 9506 return 0; 9507} 9508 9509unsigned fastEmit_ISD_UMIN_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9510 switch (VT.SimpleTy) { 9511 case MVT::v8i8: return fastEmit_ISD_UMIN_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9512 case MVT::v16i8: return fastEmit_ISD_UMIN_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9513 case MVT::v4i16: return fastEmit_ISD_UMIN_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9514 case MVT::v8i16: return fastEmit_ISD_UMIN_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9515 case MVT::v2i32: return fastEmit_ISD_UMIN_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9516 case MVT::v4i32: return fastEmit_ISD_UMIN_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9517 default: return 0; 9518 } 9519} 9520 9521// FastEmit functions for ISD::USUBSAT. 9522 9523unsigned fastEmit_ISD_USUBSAT_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9524 if (RetVT.SimpleTy != MVT::v8i8) 9525 return 0; 9526 if ((Subtarget->hasNEON())) { 9527 return fastEmitInst_rr(AArch64::UQSUBv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9528 } 9529 return 0; 9530} 9531 9532unsigned fastEmit_ISD_USUBSAT_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9533 if (RetVT.SimpleTy != MVT::v16i8) 9534 return 0; 9535 if ((Subtarget->hasNEON())) { 9536 return fastEmitInst_rr(AArch64::UQSUBv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9537 } 9538 return 0; 9539} 9540 9541unsigned fastEmit_ISD_USUBSAT_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9542 if (RetVT.SimpleTy != MVT::v4i16) 9543 return 0; 9544 if ((Subtarget->hasNEON())) { 9545 return fastEmitInst_rr(AArch64::UQSUBv4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9546 } 9547 return 0; 9548} 9549 9550unsigned fastEmit_ISD_USUBSAT_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9551 if (RetVT.SimpleTy != MVT::v8i16) 9552 return 0; 9553 if ((Subtarget->hasNEON())) { 9554 return fastEmitInst_rr(AArch64::UQSUBv8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9555 } 9556 return 0; 9557} 9558 9559unsigned fastEmit_ISD_USUBSAT_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9560 if (RetVT.SimpleTy != MVT::v2i32) 9561 return 0; 9562 if ((Subtarget->hasNEON())) { 9563 return fastEmitInst_rr(AArch64::UQSUBv2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9564 } 9565 return 0; 9566} 9567 9568unsigned fastEmit_ISD_USUBSAT_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9569 if (RetVT.SimpleTy != MVT::v4i32) 9570 return 0; 9571 if ((Subtarget->hasNEON())) { 9572 return fastEmitInst_rr(AArch64::UQSUBv4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9573 } 9574 return 0; 9575} 9576 9577unsigned fastEmit_ISD_USUBSAT_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9578 if (RetVT.SimpleTy != MVT::v2i64) 9579 return 0; 9580 if ((Subtarget->hasNEON())) { 9581 return fastEmitInst_rr(AArch64::UQSUBv2i64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9582 } 9583 return 0; 9584} 9585 9586unsigned fastEmit_ISD_USUBSAT_MVT_nxv16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9587 if (RetVT.SimpleTy != MVT::nxv16i8) 9588 return 0; 9589 if ((Subtarget->hasSVE())) { 9590 return fastEmitInst_rr(AArch64::UQSUB_ZZZ_B, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9591 } 9592 return 0; 9593} 9594 9595unsigned fastEmit_ISD_USUBSAT_MVT_nxv8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9596 if (RetVT.SimpleTy != MVT::nxv8i16) 9597 return 0; 9598 if ((Subtarget->hasSVE())) { 9599 return fastEmitInst_rr(AArch64::UQSUB_ZZZ_H, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9600 } 9601 return 0; 9602} 9603 9604unsigned fastEmit_ISD_USUBSAT_MVT_nxv4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9605 if (RetVT.SimpleTy != MVT::nxv4i32) 9606 return 0; 9607 if ((Subtarget->hasSVE())) { 9608 return fastEmitInst_rr(AArch64::UQSUB_ZZZ_S, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9609 } 9610 return 0; 9611} 9612 9613unsigned fastEmit_ISD_USUBSAT_MVT_nxv2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9614 if (RetVT.SimpleTy != MVT::nxv2i64) 9615 return 0; 9616 if ((Subtarget->hasSVE())) { 9617 return fastEmitInst_rr(AArch64::UQSUB_ZZZ_D, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9618 } 9619 return 0; 9620} 9621 9622unsigned fastEmit_ISD_USUBSAT_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9623 switch (VT.SimpleTy) { 9624 case MVT::v8i8: return fastEmit_ISD_USUBSAT_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9625 case MVT::v16i8: return fastEmit_ISD_USUBSAT_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9626 case MVT::v4i16: return fastEmit_ISD_USUBSAT_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9627 case MVT::v8i16: return fastEmit_ISD_USUBSAT_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9628 case MVT::v2i32: return fastEmit_ISD_USUBSAT_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9629 case MVT::v4i32: return fastEmit_ISD_USUBSAT_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9630 case MVT::v2i64: return fastEmit_ISD_USUBSAT_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9631 case MVT::nxv16i8: return fastEmit_ISD_USUBSAT_MVT_nxv16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9632 case MVT::nxv8i16: return fastEmit_ISD_USUBSAT_MVT_nxv8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9633 case MVT::nxv4i32: return fastEmit_ISD_USUBSAT_MVT_nxv4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9634 case MVT::nxv2i64: return fastEmit_ISD_USUBSAT_MVT_nxv2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9635 default: return 0; 9636 } 9637} 9638 9639// FastEmit functions for ISD::XOR. 9640 9641unsigned fastEmit_ISD_XOR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9642 if (RetVT.SimpleTy != MVT::i32) 9643 return 0; 9644 return fastEmitInst_rr(AArch64::EORWrr, &AArch64::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9645} 9646 9647unsigned fastEmit_ISD_XOR_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9648 if (RetVT.SimpleTy != MVT::i64) 9649 return 0; 9650 return fastEmitInst_rr(AArch64::EORXrr, &AArch64::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9651} 9652 9653unsigned fastEmit_ISD_XOR_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9654 if (RetVT.SimpleTy != MVT::v8i8) 9655 return 0; 9656 if ((Subtarget->hasNEON())) { 9657 return fastEmitInst_rr(AArch64::EORv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9658 } 9659 return 0; 9660} 9661 9662unsigned fastEmit_ISD_XOR_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9663 if (RetVT.SimpleTy != MVT::v16i8) 9664 return 0; 9665 if ((Subtarget->hasNEON())) { 9666 return fastEmitInst_rr(AArch64::EORv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9667 } 9668 return 0; 9669} 9670 9671unsigned fastEmit_ISD_XOR_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9672 if (RetVT.SimpleTy != MVT::v4i16) 9673 return 0; 9674 if ((Subtarget->hasNEON())) { 9675 return fastEmitInst_rr(AArch64::EORv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9676 } 9677 return 0; 9678} 9679 9680unsigned fastEmit_ISD_XOR_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9681 if (RetVT.SimpleTy != MVT::v8i16) 9682 return 0; 9683 if ((Subtarget->hasNEON())) { 9684 return fastEmitInst_rr(AArch64::EORv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9685 } 9686 return 0; 9687} 9688 9689unsigned fastEmit_ISD_XOR_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9690 if (RetVT.SimpleTy != MVT::v2i32) 9691 return 0; 9692 if ((Subtarget->hasNEON())) { 9693 return fastEmitInst_rr(AArch64::EORv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9694 } 9695 return 0; 9696} 9697 9698unsigned fastEmit_ISD_XOR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9699 if (RetVT.SimpleTy != MVT::v4i32) 9700 return 0; 9701 if ((Subtarget->hasNEON())) { 9702 return fastEmitInst_rr(AArch64::EORv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9703 } 9704 return 0; 9705} 9706 9707unsigned fastEmit_ISD_XOR_MVT_v1i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9708 if (RetVT.SimpleTy != MVT::v1i64) 9709 return 0; 9710 if ((Subtarget->hasNEON())) { 9711 return fastEmitInst_rr(AArch64::EORv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9712 } 9713 return 0; 9714} 9715 9716unsigned fastEmit_ISD_XOR_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9717 if (RetVT.SimpleTy != MVT::v2i64) 9718 return 0; 9719 if ((Subtarget->hasNEON())) { 9720 return fastEmitInst_rr(AArch64::EORv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9721 } 9722 return 0; 9723} 9724 9725unsigned fastEmit_ISD_XOR_MVT_nxv16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9726 if (RetVT.SimpleTy != MVT::nxv16i8) 9727 return 0; 9728 if ((Subtarget->hasSVE())) { 9729 return fastEmitInst_rr(AArch64::EOR_ZZZ, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9730 } 9731 return 0; 9732} 9733 9734unsigned fastEmit_ISD_XOR_MVT_nxv8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9735 if (RetVT.SimpleTy != MVT::nxv8i16) 9736 return 0; 9737 if ((Subtarget->hasSVE())) { 9738 return fastEmitInst_rr(AArch64::EOR_ZZZ, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9739 } 9740 return 0; 9741} 9742 9743unsigned fastEmit_ISD_XOR_MVT_nxv4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9744 if (RetVT.SimpleTy != MVT::nxv4i32) 9745 return 0; 9746 if ((Subtarget->hasSVE())) { 9747 return fastEmitInst_rr(AArch64::EOR_ZZZ, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9748 } 9749 return 0; 9750} 9751 9752unsigned fastEmit_ISD_XOR_MVT_nxv2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9753 if (RetVT.SimpleTy != MVT::nxv2i64) 9754 return 0; 9755 if ((Subtarget->hasSVE())) { 9756 return fastEmitInst_rr(AArch64::EOR_ZZZ, &AArch64::ZPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 9757 } 9758 return 0; 9759} 9760 9761unsigned fastEmit_ISD_XOR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 9762 switch (VT.SimpleTy) { 9763 case MVT::i32: return fastEmit_ISD_XOR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9764 case MVT::i64: return fastEmit_ISD_XOR_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9765 case MVT::v8i8: return fastEmit_ISD_XOR_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9766 case MVT::v16i8: return fastEmit_ISD_XOR_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9767 case MVT::v4i16: return fastEmit_ISD_XOR_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9768 case MVT::v8i16: return fastEmit_ISD_XOR_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9769 case MVT::v2i32: return fastEmit_ISD_XOR_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9770 case MVT::v4i32: return fastEmit_ISD_XOR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9771 case MVT::v1i64: return fastEmit_ISD_XOR_MVT_v1i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9772 case MVT::v2i64: return fastEmit_ISD_XOR_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9773 case MVT::nxv16i8: return fastEmit_ISD_XOR_MVT_nxv16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9774 case MVT::nxv8i16: return fastEmit_ISD_XOR_MVT_nxv8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9775 case MVT::nxv4i32: return fastEmit_ISD_XOR_MVT_nxv4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9776 case MVT::nxv2i64: return fastEmit_ISD_XOR_MVT_nxv2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9777 default: return 0; 9778 } 9779} 9780 9781// Top-level FastEmit function. 9782 9783unsigned fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) override { 9784 switch (Opcode) { 9785 case AArch64ISD::CMEQ: return fastEmit_AArch64ISD_CMEQ_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9786 case AArch64ISD::CMGE: return fastEmit_AArch64ISD_CMGE_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9787 case AArch64ISD::CMGT: return fastEmit_AArch64ISD_CMGT_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9788 case AArch64ISD::CMHI: return fastEmit_AArch64ISD_CMHI_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9789 case AArch64ISD::CMHS: return fastEmit_AArch64ISD_CMHS_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9790 case AArch64ISD::FCMEQ: return fastEmit_AArch64ISD_FCMEQ_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9791 case AArch64ISD::FCMGE: return fastEmit_AArch64ISD_FCMGE_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9792 case AArch64ISD::FCMGT: return fastEmit_AArch64ISD_FCMGT_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9793 case AArch64ISD::FCMP: return fastEmit_AArch64ISD_FCMP_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9794 case AArch64ISD::FRECPS: return fastEmit_AArch64ISD_FRECPS_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9795 case AArch64ISD::FRSQRTS: return fastEmit_AArch64ISD_FRSQRTS_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9796 case AArch64ISD::PTEST: return fastEmit_AArch64ISD_PTEST_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9797 case AArch64ISD::SMULL: return fastEmit_AArch64ISD_SMULL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9798 case AArch64ISD::STRICT_FCMP: return fastEmit_AArch64ISD_STRICT_FCMP_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9799 case AArch64ISD::STRICT_FCMPE: return fastEmit_AArch64ISD_STRICT_FCMPE_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9800 case AArch64ISD::TBL: return fastEmit_AArch64ISD_TBL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9801 case AArch64ISD::TRN1: return fastEmit_AArch64ISD_TRN1_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9802 case AArch64ISD::TRN2: return fastEmit_AArch64ISD_TRN2_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9803 case AArch64ISD::UMULL: return fastEmit_AArch64ISD_UMULL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9804 case AArch64ISD::UZP1: return fastEmit_AArch64ISD_UZP1_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9805 case AArch64ISD::UZP2: return fastEmit_AArch64ISD_UZP2_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9806 case AArch64ISD::ZIP1: return fastEmit_AArch64ISD_ZIP1_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9807 case AArch64ISD::ZIP2: return fastEmit_AArch64ISD_ZIP2_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9808 case ISD::ADD: return fastEmit_ISD_ADD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9809 case ISD::AND: return fastEmit_ISD_AND_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9810 case ISD::FADD: return fastEmit_ISD_FADD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9811 case ISD::FDIV: return fastEmit_ISD_FDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9812 case ISD::FMAXIMUM: return fastEmit_ISD_FMAXIMUM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9813 case ISD::FMAXNUM: return fastEmit_ISD_FMAXNUM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9814 case ISD::FMINIMUM: return fastEmit_ISD_FMINIMUM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9815 case ISD::FMINNUM: return fastEmit_ISD_FMINNUM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9816 case ISD::FMUL: return fastEmit_ISD_FMUL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9817 case ISD::FSUB: return fastEmit_ISD_FSUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9818 case ISD::MUL: return fastEmit_ISD_MUL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9819 case ISD::MULHS: return fastEmit_ISD_MULHS_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9820 case ISD::MULHU: return fastEmit_ISD_MULHU_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9821 case ISD::OR: return fastEmit_ISD_OR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9822 case ISD::ROTR: return fastEmit_ISD_ROTR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9823 case ISD::SADDSAT: return fastEmit_ISD_SADDSAT_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9824 case ISD::SDIV: return fastEmit_ISD_SDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9825 case ISD::SHL: return fastEmit_ISD_SHL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9826 case ISD::SMAX: return fastEmit_ISD_SMAX_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9827 case ISD::SMIN: return fastEmit_ISD_SMIN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9828 case ISD::SRA: return fastEmit_ISD_SRA_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9829 case ISD::SRL: return fastEmit_ISD_SRL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9830 case ISD::SSUBSAT: return fastEmit_ISD_SSUBSAT_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9831 case ISD::SUB: return fastEmit_ISD_SUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9832 case ISD::UADDSAT: return fastEmit_ISD_UADDSAT_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9833 case ISD::UDIV: return fastEmit_ISD_UDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9834 case ISD::UMAX: return fastEmit_ISD_UMAX_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9835 case ISD::UMIN: return fastEmit_ISD_UMIN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9836 case ISD::USUBSAT: return fastEmit_ISD_USUBSAT_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9837 case ISD::XOR: return fastEmit_ISD_XOR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 9838 default: return 0; 9839 } 9840} 9841 9842// FastEmit functions for AArch64ISD::DUPLANE64. 9843 9844unsigned fastEmit_AArch64ISD_DUPLANE64_MVT_v2i64_ri_Predicate_VectorIndexD(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 9845 if (RetVT.SimpleTy != MVT::v2i64) 9846 return 0; 9847 if ((Subtarget->hasNEON())) { 9848 return fastEmitInst_ri(AArch64::DUPv2i64lane, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 9849 } 9850 return 0; 9851} 9852 9853unsigned fastEmit_AArch64ISD_DUPLANE64_MVT_v2f64_ri_Predicate_VectorIndexD(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 9854 if (RetVT.SimpleTy != MVT::v2f64) 9855 return 0; 9856 return fastEmitInst_ri(AArch64::DUPv2i64lane, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 9857} 9858 9859unsigned fastEmit_AArch64ISD_DUPLANE64_ri_Predicate_VectorIndexD(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 9860 switch (VT.SimpleTy) { 9861 case MVT::v2i64: return fastEmit_AArch64ISD_DUPLANE64_MVT_v2i64_ri_Predicate_VectorIndexD(RetVT, Op0, Op0IsKill, imm1); 9862 case MVT::v2f64: return fastEmit_AArch64ISD_DUPLANE64_MVT_v2f64_ri_Predicate_VectorIndexD(RetVT, Op0, Op0IsKill, imm1); 9863 default: return 0; 9864 } 9865} 9866 9867// FastEmit functions for ISD::EXTRACT_VECTOR_ELT. 9868 9869unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2i64_ri_Predicate_VectorIndexD(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 9870 if (RetVT.SimpleTy != MVT::i64) 9871 return 0; 9872 if ((Subtarget->hasNEON())) { 9873 return fastEmitInst_ri(AArch64::UMOVvi64, &AArch64::GPR64RegClass, Op0, Op0IsKill, imm1); 9874 } 9875 return 0; 9876} 9877 9878unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2f64_ri_Predicate_VectorIndexD(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 9879 if (RetVT.SimpleTy != MVT::f64) 9880 return 0; 9881 return fastEmitInst_ri(AArch64::CPYi64, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 9882} 9883 9884unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_VectorIndexD(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 9885 switch (VT.SimpleTy) { 9886 case MVT::v2i64: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2i64_ri_Predicate_VectorIndexD(RetVT, Op0, Op0IsKill, imm1); 9887 case MVT::v2f64: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2f64_ri_Predicate_VectorIndexD(RetVT, Op0, Op0IsKill, imm1); 9888 default: return 0; 9889 } 9890} 9891 9892// Top-level FastEmit function. 9893 9894unsigned fastEmit_ri_Predicate_VectorIndexD(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 9895 switch (Opcode) { 9896 case AArch64ISD::DUPLANE64: return fastEmit_AArch64ISD_DUPLANE64_ri_Predicate_VectorIndexD(VT, RetVT, Op0, Op0IsKill, imm1); 9897 case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_VectorIndexD(VT, RetVT, Op0, Op0IsKill, imm1); 9898 default: return 0; 9899 } 9900} 9901 9902// FastEmit functions for AArch64ISD::DUPLANE32. 9903 9904unsigned fastEmit_AArch64ISD_DUPLANE32_MVT_v4i32_MVT_v2i32_ri_Predicate_VectorIndexS(unsigned Op0, bool Op0IsKill, uint64_t imm1) { 9905 if ((Subtarget->hasNEON())) { 9906 return fastEmitInst_ri(AArch64::DUPv2i32lane, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 9907 } 9908 return 0; 9909} 9910 9911unsigned fastEmit_AArch64ISD_DUPLANE32_MVT_v4i32_MVT_v4i32_ri_Predicate_VectorIndexS(unsigned Op0, bool Op0IsKill, uint64_t imm1) { 9912 if ((Subtarget->hasNEON())) { 9913 return fastEmitInst_ri(AArch64::DUPv4i32lane, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 9914 } 9915 return 0; 9916} 9917 9918unsigned fastEmit_AArch64ISD_DUPLANE32_MVT_v4i32_ri_Predicate_VectorIndexS(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 9919switch (RetVT.SimpleTy) { 9920 case MVT::v2i32: return fastEmit_AArch64ISD_DUPLANE32_MVT_v4i32_MVT_v2i32_ri_Predicate_VectorIndexS(Op0, Op0IsKill, imm1); 9921 case MVT::v4i32: return fastEmit_AArch64ISD_DUPLANE32_MVT_v4i32_MVT_v4i32_ri_Predicate_VectorIndexS(Op0, Op0IsKill, imm1); 9922 default: return 0; 9923} 9924} 9925 9926unsigned fastEmit_AArch64ISD_DUPLANE32_MVT_v4f32_MVT_v2f32_ri_Predicate_VectorIndexS(unsigned Op0, bool Op0IsKill, uint64_t imm1) { 9927 return fastEmitInst_ri(AArch64::DUPv2i32lane, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 9928} 9929 9930unsigned fastEmit_AArch64ISD_DUPLANE32_MVT_v4f32_MVT_v4f32_ri_Predicate_VectorIndexS(unsigned Op0, bool Op0IsKill, uint64_t imm1) { 9931 return fastEmitInst_ri(AArch64::DUPv4i32lane, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 9932} 9933 9934unsigned fastEmit_AArch64ISD_DUPLANE32_MVT_v4f32_ri_Predicate_VectorIndexS(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 9935switch (RetVT.SimpleTy) { 9936 case MVT::v2f32: return fastEmit_AArch64ISD_DUPLANE32_MVT_v4f32_MVT_v2f32_ri_Predicate_VectorIndexS(Op0, Op0IsKill, imm1); 9937 case MVT::v4f32: return fastEmit_AArch64ISD_DUPLANE32_MVT_v4f32_MVT_v4f32_ri_Predicate_VectorIndexS(Op0, Op0IsKill, imm1); 9938 default: return 0; 9939} 9940} 9941 9942unsigned fastEmit_AArch64ISD_DUPLANE32_ri_Predicate_VectorIndexS(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 9943 switch (VT.SimpleTy) { 9944 case MVT::v4i32: return fastEmit_AArch64ISD_DUPLANE32_MVT_v4i32_ri_Predicate_VectorIndexS(RetVT, Op0, Op0IsKill, imm1); 9945 case MVT::v4f32: return fastEmit_AArch64ISD_DUPLANE32_MVT_v4f32_ri_Predicate_VectorIndexS(RetVT, Op0, Op0IsKill, imm1); 9946 default: return 0; 9947 } 9948} 9949 9950// FastEmit functions for ISD::EXTRACT_VECTOR_ELT. 9951 9952unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4i32_ri_Predicate_VectorIndexS(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 9953 if (RetVT.SimpleTy != MVT::i32) 9954 return 0; 9955 if ((Subtarget->hasNEON())) { 9956 return fastEmitInst_ri(AArch64::UMOVvi32, &AArch64::GPR32RegClass, Op0, Op0IsKill, imm1); 9957 } 9958 return 0; 9959} 9960 9961unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4f32_ri_Predicate_VectorIndexS(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 9962 if (RetVT.SimpleTy != MVT::f32) 9963 return 0; 9964 return fastEmitInst_ri(AArch64::CPYi32, &AArch64::FPR32RegClass, Op0, Op0IsKill, imm1); 9965} 9966 9967unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_VectorIndexS(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 9968 switch (VT.SimpleTy) { 9969 case MVT::v4i32: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4i32_ri_Predicate_VectorIndexS(RetVT, Op0, Op0IsKill, imm1); 9970 case MVT::v4f32: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4f32_ri_Predicate_VectorIndexS(RetVT, Op0, Op0IsKill, imm1); 9971 default: return 0; 9972 } 9973} 9974 9975// Top-level FastEmit function. 9976 9977unsigned fastEmit_ri_Predicate_VectorIndexS(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 9978 switch (Opcode) { 9979 case AArch64ISD::DUPLANE32: return fastEmit_AArch64ISD_DUPLANE32_ri_Predicate_VectorIndexS(VT, RetVT, Op0, Op0IsKill, imm1); 9980 case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_VectorIndexS(VT, RetVT, Op0, Op0IsKill, imm1); 9981 default: return 0; 9982 } 9983} 9984 9985// FastEmit functions for AArch64ISD::DUPLANE16. 9986 9987unsigned fastEmit_AArch64ISD_DUPLANE16_MVT_v8i16_MVT_v4i16_ri_Predicate_VectorIndexH(unsigned Op0, bool Op0IsKill, uint64_t imm1) { 9988 if ((Subtarget->hasNEON())) { 9989 return fastEmitInst_ri(AArch64::DUPv4i16lane, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 9990 } 9991 return 0; 9992} 9993 9994unsigned fastEmit_AArch64ISD_DUPLANE16_MVT_v8i16_MVT_v8i16_ri_Predicate_VectorIndexH(unsigned Op0, bool Op0IsKill, uint64_t imm1) { 9995 if ((Subtarget->hasNEON())) { 9996 return fastEmitInst_ri(AArch64::DUPv8i16lane, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 9997 } 9998 return 0; 9999} 10000 10001unsigned fastEmit_AArch64ISD_DUPLANE16_MVT_v8i16_ri_Predicate_VectorIndexH(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10002switch (RetVT.SimpleTy) { 10003 case MVT::v4i16: return fastEmit_AArch64ISD_DUPLANE16_MVT_v8i16_MVT_v4i16_ri_Predicate_VectorIndexH(Op0, Op0IsKill, imm1); 10004 case MVT::v8i16: return fastEmit_AArch64ISD_DUPLANE16_MVT_v8i16_MVT_v8i16_ri_Predicate_VectorIndexH(Op0, Op0IsKill, imm1); 10005 default: return 0; 10006} 10007} 10008 10009unsigned fastEmit_AArch64ISD_DUPLANE16_MVT_v8f16_MVT_v4f16_ri_Predicate_VectorIndexH(unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10010 return fastEmitInst_ri(AArch64::DUPv4i16lane, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 10011} 10012 10013unsigned fastEmit_AArch64ISD_DUPLANE16_MVT_v8f16_MVT_v8f16_ri_Predicate_VectorIndexH(unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10014 return fastEmitInst_ri(AArch64::DUPv8i16lane, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 10015} 10016 10017unsigned fastEmit_AArch64ISD_DUPLANE16_MVT_v8f16_ri_Predicate_VectorIndexH(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10018switch (RetVT.SimpleTy) { 10019 case MVT::v4f16: return fastEmit_AArch64ISD_DUPLANE16_MVT_v8f16_MVT_v4f16_ri_Predicate_VectorIndexH(Op0, Op0IsKill, imm1); 10020 case MVT::v8f16: return fastEmit_AArch64ISD_DUPLANE16_MVT_v8f16_MVT_v8f16_ri_Predicate_VectorIndexH(Op0, Op0IsKill, imm1); 10021 default: return 0; 10022} 10023} 10024 10025unsigned fastEmit_AArch64ISD_DUPLANE16_ri_Predicate_VectorIndexH(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10026 switch (VT.SimpleTy) { 10027 case MVT::v8i16: return fastEmit_AArch64ISD_DUPLANE16_MVT_v8i16_ri_Predicate_VectorIndexH(RetVT, Op0, Op0IsKill, imm1); 10028 case MVT::v8f16: return fastEmit_AArch64ISD_DUPLANE16_MVT_v8f16_ri_Predicate_VectorIndexH(RetVT, Op0, Op0IsKill, imm1); 10029 default: return 0; 10030 } 10031} 10032 10033// FastEmit functions for ISD::EXTRACT_VECTOR_ELT. 10034 10035unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v8i16_ri_Predicate_VectorIndexH(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10036 if (RetVT.SimpleTy != MVT::i32) 10037 return 0; 10038 if ((Subtarget->hasNEON())) { 10039 return fastEmitInst_ri(AArch64::UMOVvi16, &AArch64::GPR32RegClass, Op0, Op0IsKill, imm1); 10040 } 10041 return 0; 10042} 10043 10044unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v8f16_ri_Predicate_VectorIndexH(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10045 if (RetVT.SimpleTy != MVT::f16) 10046 return 0; 10047 return fastEmitInst_ri(AArch64::CPYi16, &AArch64::FPR16RegClass, Op0, Op0IsKill, imm1); 10048} 10049 10050unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_VectorIndexH(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10051 switch (VT.SimpleTy) { 10052 case MVT::v8i16: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v8i16_ri_Predicate_VectorIndexH(RetVT, Op0, Op0IsKill, imm1); 10053 case MVT::v8f16: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v8f16_ri_Predicate_VectorIndexH(RetVT, Op0, Op0IsKill, imm1); 10054 default: return 0; 10055 } 10056} 10057 10058// Top-level FastEmit function. 10059 10060unsigned fastEmit_ri_Predicate_VectorIndexH(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10061 switch (Opcode) { 10062 case AArch64ISD::DUPLANE16: return fastEmit_AArch64ISD_DUPLANE16_ri_Predicate_VectorIndexH(VT, RetVT, Op0, Op0IsKill, imm1); 10063 case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_VectorIndexH(VT, RetVT, Op0, Op0IsKill, imm1); 10064 default: return 0; 10065 } 10066} 10067 10068// FastEmit functions for AArch64ISD::DUPLANE8. 10069 10070unsigned fastEmit_AArch64ISD_DUPLANE8_MVT_v16i8_MVT_v8i8_ri_Predicate_VectorIndexB(unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10071 if ((Subtarget->hasNEON())) { 10072 return fastEmitInst_ri(AArch64::DUPv8i8lane, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 10073 } 10074 return 0; 10075} 10076 10077unsigned fastEmit_AArch64ISD_DUPLANE8_MVT_v16i8_MVT_v16i8_ri_Predicate_VectorIndexB(unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10078 if ((Subtarget->hasNEON())) { 10079 return fastEmitInst_ri(AArch64::DUPv16i8lane, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 10080 } 10081 return 0; 10082} 10083 10084unsigned fastEmit_AArch64ISD_DUPLANE8_MVT_v16i8_ri_Predicate_VectorIndexB(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10085switch (RetVT.SimpleTy) { 10086 case MVT::v8i8: return fastEmit_AArch64ISD_DUPLANE8_MVT_v16i8_MVT_v8i8_ri_Predicate_VectorIndexB(Op0, Op0IsKill, imm1); 10087 case MVT::v16i8: return fastEmit_AArch64ISD_DUPLANE8_MVT_v16i8_MVT_v16i8_ri_Predicate_VectorIndexB(Op0, Op0IsKill, imm1); 10088 default: return 0; 10089} 10090} 10091 10092unsigned fastEmit_AArch64ISD_DUPLANE8_ri_Predicate_VectorIndexB(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10093 switch (VT.SimpleTy) { 10094 case MVT::v16i8: return fastEmit_AArch64ISD_DUPLANE8_MVT_v16i8_ri_Predicate_VectorIndexB(RetVT, Op0, Op0IsKill, imm1); 10095 default: return 0; 10096 } 10097} 10098 10099// FastEmit functions for ISD::EXTRACT_VECTOR_ELT. 10100 10101unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v16i8_ri_Predicate_VectorIndexB(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10102 if (RetVT.SimpleTy != MVT::i32) 10103 return 0; 10104 if ((Subtarget->hasNEON())) { 10105 return fastEmitInst_ri(AArch64::UMOVvi8, &AArch64::GPR32RegClass, Op0, Op0IsKill, imm1); 10106 } 10107 return 0; 10108} 10109 10110unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_VectorIndexB(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10111 switch (VT.SimpleTy) { 10112 case MVT::v16i8: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v16i8_ri_Predicate_VectorIndexB(RetVT, Op0, Op0IsKill, imm1); 10113 default: return 0; 10114 } 10115} 10116 10117// Top-level FastEmit function. 10118 10119unsigned fastEmit_ri_Predicate_VectorIndexB(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10120 switch (Opcode) { 10121 case AArch64ISD::DUPLANE8: return fastEmit_AArch64ISD_DUPLANE8_ri_Predicate_VectorIndexB(VT, RetVT, Op0, Op0IsKill, imm1); 10122 case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_VectorIndexB(VT, RetVT, Op0, Op0IsKill, imm1); 10123 default: return 0; 10124 } 10125} 10126 10127// FastEmit functions for AArch64ISD::SQSHLU_I. 10128 10129unsigned fastEmit_AArch64ISD_SQSHLU_I_MVT_i64_ri_Predicate_vecshiftL64(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10130 if (RetVT.SimpleTy != MVT::i64) 10131 return 0; 10132 if ((Subtarget->hasNEON())) { 10133 return fastEmitInst_ri(AArch64::SQSHLUd, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 10134 } 10135 return 0; 10136} 10137 10138unsigned fastEmit_AArch64ISD_SQSHLU_I_MVT_v1i64_ri_Predicate_vecshiftL64(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10139 if (RetVT.SimpleTy != MVT::v1i64) 10140 return 0; 10141 if ((Subtarget->hasNEON())) { 10142 return fastEmitInst_ri(AArch64::SQSHLUd, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 10143 } 10144 return 0; 10145} 10146 10147unsigned fastEmit_AArch64ISD_SQSHLU_I_MVT_v2i64_ri_Predicate_vecshiftL64(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10148 if (RetVT.SimpleTy != MVT::v2i64) 10149 return 0; 10150 if ((Subtarget->hasNEON())) { 10151 return fastEmitInst_ri(AArch64::SQSHLUv2i64_shift, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 10152 } 10153 return 0; 10154} 10155 10156unsigned fastEmit_AArch64ISD_SQSHLU_I_ri_Predicate_vecshiftL64(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10157 switch (VT.SimpleTy) { 10158 case MVT::i64: return fastEmit_AArch64ISD_SQSHLU_I_MVT_i64_ri_Predicate_vecshiftL64(RetVT, Op0, Op0IsKill, imm1); 10159 case MVT::v1i64: return fastEmit_AArch64ISD_SQSHLU_I_MVT_v1i64_ri_Predicate_vecshiftL64(RetVT, Op0, Op0IsKill, imm1); 10160 case MVT::v2i64: return fastEmit_AArch64ISD_SQSHLU_I_MVT_v2i64_ri_Predicate_vecshiftL64(RetVT, Op0, Op0IsKill, imm1); 10161 default: return 0; 10162 } 10163} 10164 10165// FastEmit functions for AArch64ISD::SQSHL_I. 10166 10167unsigned fastEmit_AArch64ISD_SQSHL_I_MVT_i64_ri_Predicate_vecshiftL64(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10168 if (RetVT.SimpleTy != MVT::i64) 10169 return 0; 10170 if ((Subtarget->hasNEON())) { 10171 return fastEmitInst_ri(AArch64::SQSHLd, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 10172 } 10173 return 0; 10174} 10175 10176unsigned fastEmit_AArch64ISD_SQSHL_I_MVT_v1i64_ri_Predicate_vecshiftL64(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10177 if (RetVT.SimpleTy != MVT::v1i64) 10178 return 0; 10179 if ((Subtarget->hasNEON())) { 10180 return fastEmitInst_ri(AArch64::SQSHLd, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 10181 } 10182 return 0; 10183} 10184 10185unsigned fastEmit_AArch64ISD_SQSHL_I_MVT_v2i64_ri_Predicate_vecshiftL64(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10186 if (RetVT.SimpleTy != MVT::v2i64) 10187 return 0; 10188 if ((Subtarget->hasNEON())) { 10189 return fastEmitInst_ri(AArch64::SQSHLv2i64_shift, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 10190 } 10191 return 0; 10192} 10193 10194unsigned fastEmit_AArch64ISD_SQSHL_I_ri_Predicate_vecshiftL64(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10195 switch (VT.SimpleTy) { 10196 case MVT::i64: return fastEmit_AArch64ISD_SQSHL_I_MVT_i64_ri_Predicate_vecshiftL64(RetVT, Op0, Op0IsKill, imm1); 10197 case MVT::v1i64: return fastEmit_AArch64ISD_SQSHL_I_MVT_v1i64_ri_Predicate_vecshiftL64(RetVT, Op0, Op0IsKill, imm1); 10198 case MVT::v2i64: return fastEmit_AArch64ISD_SQSHL_I_MVT_v2i64_ri_Predicate_vecshiftL64(RetVT, Op0, Op0IsKill, imm1); 10199 default: return 0; 10200 } 10201} 10202 10203// FastEmit functions for AArch64ISD::UQSHL_I. 10204 10205unsigned fastEmit_AArch64ISD_UQSHL_I_MVT_i64_ri_Predicate_vecshiftL64(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10206 if (RetVT.SimpleTy != MVT::i64) 10207 return 0; 10208 if ((Subtarget->hasNEON())) { 10209 return fastEmitInst_ri(AArch64::UQSHLd, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 10210 } 10211 return 0; 10212} 10213 10214unsigned fastEmit_AArch64ISD_UQSHL_I_MVT_v1i64_ri_Predicate_vecshiftL64(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10215 if (RetVT.SimpleTy != MVT::v1i64) 10216 return 0; 10217 if ((Subtarget->hasNEON())) { 10218 return fastEmitInst_ri(AArch64::UQSHLd, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 10219 } 10220 return 0; 10221} 10222 10223unsigned fastEmit_AArch64ISD_UQSHL_I_MVT_v2i64_ri_Predicate_vecshiftL64(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10224 if (RetVT.SimpleTy != MVT::v2i64) 10225 return 0; 10226 if ((Subtarget->hasNEON())) { 10227 return fastEmitInst_ri(AArch64::UQSHLv2i64_shift, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 10228 } 10229 return 0; 10230} 10231 10232unsigned fastEmit_AArch64ISD_UQSHL_I_ri_Predicate_vecshiftL64(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10233 switch (VT.SimpleTy) { 10234 case MVT::i64: return fastEmit_AArch64ISD_UQSHL_I_MVT_i64_ri_Predicate_vecshiftL64(RetVT, Op0, Op0IsKill, imm1); 10235 case MVT::v1i64: return fastEmit_AArch64ISD_UQSHL_I_MVT_v1i64_ri_Predicate_vecshiftL64(RetVT, Op0, Op0IsKill, imm1); 10236 case MVT::v2i64: return fastEmit_AArch64ISD_UQSHL_I_MVT_v2i64_ri_Predicate_vecshiftL64(RetVT, Op0, Op0IsKill, imm1); 10237 default: return 0; 10238 } 10239} 10240 10241// FastEmit functions for AArch64ISD::VSHL. 10242 10243unsigned fastEmit_AArch64ISD_VSHL_MVT_v1i64_ri_Predicate_vecshiftL64(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10244 if (RetVT.SimpleTy != MVT::v1i64) 10245 return 0; 10246 if ((Subtarget->hasNEON())) { 10247 return fastEmitInst_ri(AArch64::SHLd, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 10248 } 10249 return 0; 10250} 10251 10252unsigned fastEmit_AArch64ISD_VSHL_MVT_v2i64_ri_Predicate_vecshiftL64(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10253 if (RetVT.SimpleTy != MVT::v2i64) 10254 return 0; 10255 if ((Subtarget->hasNEON())) { 10256 return fastEmitInst_ri(AArch64::SHLv2i64_shift, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 10257 } 10258 return 0; 10259} 10260 10261unsigned fastEmit_AArch64ISD_VSHL_ri_Predicate_vecshiftL64(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10262 switch (VT.SimpleTy) { 10263 case MVT::v1i64: return fastEmit_AArch64ISD_VSHL_MVT_v1i64_ri_Predicate_vecshiftL64(RetVT, Op0, Op0IsKill, imm1); 10264 case MVT::v2i64: return fastEmit_AArch64ISD_VSHL_MVT_v2i64_ri_Predicate_vecshiftL64(RetVT, Op0, Op0IsKill, imm1); 10265 default: return 0; 10266 } 10267} 10268 10269// Top-level FastEmit function. 10270 10271unsigned fastEmit_ri_Predicate_vecshiftL64(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10272 switch (Opcode) { 10273 case AArch64ISD::SQSHLU_I: return fastEmit_AArch64ISD_SQSHLU_I_ri_Predicate_vecshiftL64(VT, RetVT, Op0, Op0IsKill, imm1); 10274 case AArch64ISD::SQSHL_I: return fastEmit_AArch64ISD_SQSHL_I_ri_Predicate_vecshiftL64(VT, RetVT, Op0, Op0IsKill, imm1); 10275 case AArch64ISD::UQSHL_I: return fastEmit_AArch64ISD_UQSHL_I_ri_Predicate_vecshiftL64(VT, RetVT, Op0, Op0IsKill, imm1); 10276 case AArch64ISD::VSHL: return fastEmit_AArch64ISD_VSHL_ri_Predicate_vecshiftL64(VT, RetVT, Op0, Op0IsKill, imm1); 10277 default: return 0; 10278 } 10279} 10280 10281// FastEmit functions for AArch64ISD::SQSHLU_I. 10282 10283unsigned fastEmit_AArch64ISD_SQSHLU_I_MVT_i32_ri_Predicate_vecshiftL32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10284 if (RetVT.SimpleTy != MVT::i32) 10285 return 0; 10286 if ((Subtarget->hasNEON())) { 10287 return fastEmitInst_ri(AArch64::SQSHLUs, &AArch64::FPR32RegClass, Op0, Op0IsKill, imm1); 10288 } 10289 return 0; 10290} 10291 10292unsigned fastEmit_AArch64ISD_SQSHLU_I_MVT_v2i32_ri_Predicate_vecshiftL32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10293 if (RetVT.SimpleTy != MVT::v2i32) 10294 return 0; 10295 if ((Subtarget->hasNEON())) { 10296 return fastEmitInst_ri(AArch64::SQSHLUv2i32_shift, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 10297 } 10298 return 0; 10299} 10300 10301unsigned fastEmit_AArch64ISD_SQSHLU_I_MVT_v4i32_ri_Predicate_vecshiftL32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10302 if (RetVT.SimpleTy != MVT::v4i32) 10303 return 0; 10304 if ((Subtarget->hasNEON())) { 10305 return fastEmitInst_ri(AArch64::SQSHLUv4i32_shift, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 10306 } 10307 return 0; 10308} 10309 10310unsigned fastEmit_AArch64ISD_SQSHLU_I_ri_Predicate_vecshiftL32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10311 switch (VT.SimpleTy) { 10312 case MVT::i32: return fastEmit_AArch64ISD_SQSHLU_I_MVT_i32_ri_Predicate_vecshiftL32(RetVT, Op0, Op0IsKill, imm1); 10313 case MVT::v2i32: return fastEmit_AArch64ISD_SQSHLU_I_MVT_v2i32_ri_Predicate_vecshiftL32(RetVT, Op0, Op0IsKill, imm1); 10314 case MVT::v4i32: return fastEmit_AArch64ISD_SQSHLU_I_MVT_v4i32_ri_Predicate_vecshiftL32(RetVT, Op0, Op0IsKill, imm1); 10315 default: return 0; 10316 } 10317} 10318 10319// FastEmit functions for AArch64ISD::SQSHL_I. 10320 10321unsigned fastEmit_AArch64ISD_SQSHL_I_MVT_i32_ri_Predicate_vecshiftL32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10322 if (RetVT.SimpleTy != MVT::i32) 10323 return 0; 10324 if ((Subtarget->hasNEON())) { 10325 return fastEmitInst_ri(AArch64::SQSHLs, &AArch64::FPR32RegClass, Op0, Op0IsKill, imm1); 10326 } 10327 return 0; 10328} 10329 10330unsigned fastEmit_AArch64ISD_SQSHL_I_MVT_v2i32_ri_Predicate_vecshiftL32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10331 if (RetVT.SimpleTy != MVT::v2i32) 10332 return 0; 10333 if ((Subtarget->hasNEON())) { 10334 return fastEmitInst_ri(AArch64::SQSHLv2i32_shift, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 10335 } 10336 return 0; 10337} 10338 10339unsigned fastEmit_AArch64ISD_SQSHL_I_MVT_v4i32_ri_Predicate_vecshiftL32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10340 if (RetVT.SimpleTy != MVT::v4i32) 10341 return 0; 10342 if ((Subtarget->hasNEON())) { 10343 return fastEmitInst_ri(AArch64::SQSHLv4i32_shift, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 10344 } 10345 return 0; 10346} 10347 10348unsigned fastEmit_AArch64ISD_SQSHL_I_ri_Predicate_vecshiftL32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10349 switch (VT.SimpleTy) { 10350 case MVT::i32: return fastEmit_AArch64ISD_SQSHL_I_MVT_i32_ri_Predicate_vecshiftL32(RetVT, Op0, Op0IsKill, imm1); 10351 case MVT::v2i32: return fastEmit_AArch64ISD_SQSHL_I_MVT_v2i32_ri_Predicate_vecshiftL32(RetVT, Op0, Op0IsKill, imm1); 10352 case MVT::v4i32: return fastEmit_AArch64ISD_SQSHL_I_MVT_v4i32_ri_Predicate_vecshiftL32(RetVT, Op0, Op0IsKill, imm1); 10353 default: return 0; 10354 } 10355} 10356 10357// FastEmit functions for AArch64ISD::UQSHL_I. 10358 10359unsigned fastEmit_AArch64ISD_UQSHL_I_MVT_i32_ri_Predicate_vecshiftL32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10360 if (RetVT.SimpleTy != MVT::i32) 10361 return 0; 10362 if ((Subtarget->hasNEON())) { 10363 return fastEmitInst_ri(AArch64::UQSHLs, &AArch64::FPR32RegClass, Op0, Op0IsKill, imm1); 10364 } 10365 return 0; 10366} 10367 10368unsigned fastEmit_AArch64ISD_UQSHL_I_MVT_v2i32_ri_Predicate_vecshiftL32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10369 if (RetVT.SimpleTy != MVT::v2i32) 10370 return 0; 10371 if ((Subtarget->hasNEON())) { 10372 return fastEmitInst_ri(AArch64::UQSHLv2i32_shift, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 10373 } 10374 return 0; 10375} 10376 10377unsigned fastEmit_AArch64ISD_UQSHL_I_MVT_v4i32_ri_Predicate_vecshiftL32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10378 if (RetVT.SimpleTy != MVT::v4i32) 10379 return 0; 10380 if ((Subtarget->hasNEON())) { 10381 return fastEmitInst_ri(AArch64::UQSHLv4i32_shift, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 10382 } 10383 return 0; 10384} 10385 10386unsigned fastEmit_AArch64ISD_UQSHL_I_ri_Predicate_vecshiftL32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10387 switch (VT.SimpleTy) { 10388 case MVT::i32: return fastEmit_AArch64ISD_UQSHL_I_MVT_i32_ri_Predicate_vecshiftL32(RetVT, Op0, Op0IsKill, imm1); 10389 case MVT::v2i32: return fastEmit_AArch64ISD_UQSHL_I_MVT_v2i32_ri_Predicate_vecshiftL32(RetVT, Op0, Op0IsKill, imm1); 10390 case MVT::v4i32: return fastEmit_AArch64ISD_UQSHL_I_MVT_v4i32_ri_Predicate_vecshiftL32(RetVT, Op0, Op0IsKill, imm1); 10391 default: return 0; 10392 } 10393} 10394 10395// FastEmit functions for AArch64ISD::VSHL. 10396 10397unsigned fastEmit_AArch64ISD_VSHL_MVT_v2i32_ri_Predicate_vecshiftL32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10398 if (RetVT.SimpleTy != MVT::v2i32) 10399 return 0; 10400 if ((Subtarget->hasNEON())) { 10401 return fastEmitInst_ri(AArch64::SHLv2i32_shift, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 10402 } 10403 return 0; 10404} 10405 10406unsigned fastEmit_AArch64ISD_VSHL_MVT_v4i32_ri_Predicate_vecshiftL32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10407 if (RetVT.SimpleTy != MVT::v4i32) 10408 return 0; 10409 if ((Subtarget->hasNEON())) { 10410 return fastEmitInst_ri(AArch64::SHLv4i32_shift, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 10411 } 10412 return 0; 10413} 10414 10415unsigned fastEmit_AArch64ISD_VSHL_ri_Predicate_vecshiftL32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10416 switch (VT.SimpleTy) { 10417 case MVT::v2i32: return fastEmit_AArch64ISD_VSHL_MVT_v2i32_ri_Predicate_vecshiftL32(RetVT, Op0, Op0IsKill, imm1); 10418 case MVT::v4i32: return fastEmit_AArch64ISD_VSHL_MVT_v4i32_ri_Predicate_vecshiftL32(RetVT, Op0, Op0IsKill, imm1); 10419 default: return 0; 10420 } 10421} 10422 10423// Top-level FastEmit function. 10424 10425unsigned fastEmit_ri_Predicate_vecshiftL32(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10426 switch (Opcode) { 10427 case AArch64ISD::SQSHLU_I: return fastEmit_AArch64ISD_SQSHLU_I_ri_Predicate_vecshiftL32(VT, RetVT, Op0, Op0IsKill, imm1); 10428 case AArch64ISD::SQSHL_I: return fastEmit_AArch64ISD_SQSHL_I_ri_Predicate_vecshiftL32(VT, RetVT, Op0, Op0IsKill, imm1); 10429 case AArch64ISD::UQSHL_I: return fastEmit_AArch64ISD_UQSHL_I_ri_Predicate_vecshiftL32(VT, RetVT, Op0, Op0IsKill, imm1); 10430 case AArch64ISD::VSHL: return fastEmit_AArch64ISD_VSHL_ri_Predicate_vecshiftL32(VT, RetVT, Op0, Op0IsKill, imm1); 10431 default: return 0; 10432 } 10433} 10434 10435// FastEmit functions for AArch64ISD::SRSHR_I. 10436 10437unsigned fastEmit_AArch64ISD_SRSHR_I_MVT_i64_ri_Predicate_vecshiftR64(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10438 if (RetVT.SimpleTy != MVT::i64) 10439 return 0; 10440 if ((Subtarget->hasNEON())) { 10441 return fastEmitInst_ri(AArch64::SRSHRd, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 10442 } 10443 return 0; 10444} 10445 10446unsigned fastEmit_AArch64ISD_SRSHR_I_MVT_v1i64_ri_Predicate_vecshiftR64(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10447 if (RetVT.SimpleTy != MVT::v1i64) 10448 return 0; 10449 if ((Subtarget->hasNEON())) { 10450 return fastEmitInst_ri(AArch64::SRSHRd, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 10451 } 10452 return 0; 10453} 10454 10455unsigned fastEmit_AArch64ISD_SRSHR_I_MVT_v2i64_ri_Predicate_vecshiftR64(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10456 if (RetVT.SimpleTy != MVT::v2i64) 10457 return 0; 10458 if ((Subtarget->hasNEON())) { 10459 return fastEmitInst_ri(AArch64::SRSHRv2i64_shift, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 10460 } 10461 return 0; 10462} 10463 10464unsigned fastEmit_AArch64ISD_SRSHR_I_ri_Predicate_vecshiftR64(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10465 switch (VT.SimpleTy) { 10466 case MVT::i64: return fastEmit_AArch64ISD_SRSHR_I_MVT_i64_ri_Predicate_vecshiftR64(RetVT, Op0, Op0IsKill, imm1); 10467 case MVT::v1i64: return fastEmit_AArch64ISD_SRSHR_I_MVT_v1i64_ri_Predicate_vecshiftR64(RetVT, Op0, Op0IsKill, imm1); 10468 case MVT::v2i64: return fastEmit_AArch64ISD_SRSHR_I_MVT_v2i64_ri_Predicate_vecshiftR64(RetVT, Op0, Op0IsKill, imm1); 10469 default: return 0; 10470 } 10471} 10472 10473// FastEmit functions for AArch64ISD::URSHR_I. 10474 10475unsigned fastEmit_AArch64ISD_URSHR_I_MVT_i64_ri_Predicate_vecshiftR64(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10476 if (RetVT.SimpleTy != MVT::i64) 10477 return 0; 10478 if ((Subtarget->hasNEON())) { 10479 return fastEmitInst_ri(AArch64::URSHRd, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 10480 } 10481 return 0; 10482} 10483 10484unsigned fastEmit_AArch64ISD_URSHR_I_MVT_v1i64_ri_Predicate_vecshiftR64(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10485 if (RetVT.SimpleTy != MVT::v1i64) 10486 return 0; 10487 if ((Subtarget->hasNEON())) { 10488 return fastEmitInst_ri(AArch64::URSHRd, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 10489 } 10490 return 0; 10491} 10492 10493unsigned fastEmit_AArch64ISD_URSHR_I_MVT_v2i64_ri_Predicate_vecshiftR64(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10494 if (RetVT.SimpleTy != MVT::v2i64) 10495 return 0; 10496 if ((Subtarget->hasNEON())) { 10497 return fastEmitInst_ri(AArch64::URSHRv2i64_shift, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 10498 } 10499 return 0; 10500} 10501 10502unsigned fastEmit_AArch64ISD_URSHR_I_ri_Predicate_vecshiftR64(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10503 switch (VT.SimpleTy) { 10504 case MVT::i64: return fastEmit_AArch64ISD_URSHR_I_MVT_i64_ri_Predicate_vecshiftR64(RetVT, Op0, Op0IsKill, imm1); 10505 case MVT::v1i64: return fastEmit_AArch64ISD_URSHR_I_MVT_v1i64_ri_Predicate_vecshiftR64(RetVT, Op0, Op0IsKill, imm1); 10506 case MVT::v2i64: return fastEmit_AArch64ISD_URSHR_I_MVT_v2i64_ri_Predicate_vecshiftR64(RetVT, Op0, Op0IsKill, imm1); 10507 default: return 0; 10508 } 10509} 10510 10511// FastEmit functions for AArch64ISD::VASHR. 10512 10513unsigned fastEmit_AArch64ISD_VASHR_MVT_i64_ri_Predicate_vecshiftR64(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10514 if (RetVT.SimpleTy != MVT::i64) 10515 return 0; 10516 if ((Subtarget->hasNEON())) { 10517 return fastEmitInst_ri(AArch64::SSHRd, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 10518 } 10519 return 0; 10520} 10521 10522unsigned fastEmit_AArch64ISD_VASHR_MVT_v1i64_ri_Predicate_vecshiftR64(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10523 if (RetVT.SimpleTy != MVT::v1i64) 10524 return 0; 10525 if ((Subtarget->hasNEON())) { 10526 return fastEmitInst_ri(AArch64::SSHRd, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 10527 } 10528 return 0; 10529} 10530 10531unsigned fastEmit_AArch64ISD_VASHR_MVT_v2i64_ri_Predicate_vecshiftR64(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10532 if (RetVT.SimpleTy != MVT::v2i64) 10533 return 0; 10534 if ((Subtarget->hasNEON())) { 10535 return fastEmitInst_ri(AArch64::SSHRv2i64_shift, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 10536 } 10537 return 0; 10538} 10539 10540unsigned fastEmit_AArch64ISD_VASHR_ri_Predicate_vecshiftR64(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10541 switch (VT.SimpleTy) { 10542 case MVT::i64: return fastEmit_AArch64ISD_VASHR_MVT_i64_ri_Predicate_vecshiftR64(RetVT, Op0, Op0IsKill, imm1); 10543 case MVT::v1i64: return fastEmit_AArch64ISD_VASHR_MVT_v1i64_ri_Predicate_vecshiftR64(RetVT, Op0, Op0IsKill, imm1); 10544 case MVT::v2i64: return fastEmit_AArch64ISD_VASHR_MVT_v2i64_ri_Predicate_vecshiftR64(RetVT, Op0, Op0IsKill, imm1); 10545 default: return 0; 10546 } 10547} 10548 10549// FastEmit functions for AArch64ISD::VLSHR. 10550 10551unsigned fastEmit_AArch64ISD_VLSHR_MVT_i64_ri_Predicate_vecshiftR64(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10552 if (RetVT.SimpleTy != MVT::i64) 10553 return 0; 10554 if ((Subtarget->hasNEON())) { 10555 return fastEmitInst_ri(AArch64::USHRd, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 10556 } 10557 return 0; 10558} 10559 10560unsigned fastEmit_AArch64ISD_VLSHR_MVT_v1i64_ri_Predicate_vecshiftR64(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10561 if (RetVT.SimpleTy != MVT::v1i64) 10562 return 0; 10563 if ((Subtarget->hasNEON())) { 10564 return fastEmitInst_ri(AArch64::USHRd, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 10565 } 10566 return 0; 10567} 10568 10569unsigned fastEmit_AArch64ISD_VLSHR_MVT_v2i64_ri_Predicate_vecshiftR64(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10570 if (RetVT.SimpleTy != MVT::v2i64) 10571 return 0; 10572 if ((Subtarget->hasNEON())) { 10573 return fastEmitInst_ri(AArch64::USHRv2i64_shift, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 10574 } 10575 return 0; 10576} 10577 10578unsigned fastEmit_AArch64ISD_VLSHR_ri_Predicate_vecshiftR64(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10579 switch (VT.SimpleTy) { 10580 case MVT::i64: return fastEmit_AArch64ISD_VLSHR_MVT_i64_ri_Predicate_vecshiftR64(RetVT, Op0, Op0IsKill, imm1); 10581 case MVT::v1i64: return fastEmit_AArch64ISD_VLSHR_MVT_v1i64_ri_Predicate_vecshiftR64(RetVT, Op0, Op0IsKill, imm1); 10582 case MVT::v2i64: return fastEmit_AArch64ISD_VLSHR_MVT_v2i64_ri_Predicate_vecshiftR64(RetVT, Op0, Op0IsKill, imm1); 10583 default: return 0; 10584 } 10585} 10586 10587// Top-level FastEmit function. 10588 10589unsigned fastEmit_ri_Predicate_vecshiftR64(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10590 switch (Opcode) { 10591 case AArch64ISD::SRSHR_I: return fastEmit_AArch64ISD_SRSHR_I_ri_Predicate_vecshiftR64(VT, RetVT, Op0, Op0IsKill, imm1); 10592 case AArch64ISD::URSHR_I: return fastEmit_AArch64ISD_URSHR_I_ri_Predicate_vecshiftR64(VT, RetVT, Op0, Op0IsKill, imm1); 10593 case AArch64ISD::VASHR: return fastEmit_AArch64ISD_VASHR_ri_Predicate_vecshiftR64(VT, RetVT, Op0, Op0IsKill, imm1); 10594 case AArch64ISD::VLSHR: return fastEmit_AArch64ISD_VLSHR_ri_Predicate_vecshiftR64(VT, RetVT, Op0, Op0IsKill, imm1); 10595 default: return 0; 10596 } 10597} 10598 10599// FastEmit functions for AArch64ISD::SQSHLU_I. 10600 10601unsigned fastEmit_AArch64ISD_SQSHLU_I_MVT_v8i8_ri_Predicate_vecshiftL8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10602 if (RetVT.SimpleTy != MVT::v8i8) 10603 return 0; 10604 if ((Subtarget->hasNEON())) { 10605 return fastEmitInst_ri(AArch64::SQSHLUv8i8_shift, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 10606 } 10607 return 0; 10608} 10609 10610unsigned fastEmit_AArch64ISD_SQSHLU_I_MVT_v16i8_ri_Predicate_vecshiftL8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10611 if (RetVT.SimpleTy != MVT::v16i8) 10612 return 0; 10613 if ((Subtarget->hasNEON())) { 10614 return fastEmitInst_ri(AArch64::SQSHLUv16i8_shift, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 10615 } 10616 return 0; 10617} 10618 10619unsigned fastEmit_AArch64ISD_SQSHLU_I_ri_Predicate_vecshiftL8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10620 switch (VT.SimpleTy) { 10621 case MVT::v8i8: return fastEmit_AArch64ISD_SQSHLU_I_MVT_v8i8_ri_Predicate_vecshiftL8(RetVT, Op0, Op0IsKill, imm1); 10622 case MVT::v16i8: return fastEmit_AArch64ISD_SQSHLU_I_MVT_v16i8_ri_Predicate_vecshiftL8(RetVT, Op0, Op0IsKill, imm1); 10623 default: return 0; 10624 } 10625} 10626 10627// FastEmit functions for AArch64ISD::SQSHL_I. 10628 10629unsigned fastEmit_AArch64ISD_SQSHL_I_MVT_v8i8_ri_Predicate_vecshiftL8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10630 if (RetVT.SimpleTy != MVT::v8i8) 10631 return 0; 10632 if ((Subtarget->hasNEON())) { 10633 return fastEmitInst_ri(AArch64::SQSHLv8i8_shift, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 10634 } 10635 return 0; 10636} 10637 10638unsigned fastEmit_AArch64ISD_SQSHL_I_MVT_v16i8_ri_Predicate_vecshiftL8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10639 if (RetVT.SimpleTy != MVT::v16i8) 10640 return 0; 10641 if ((Subtarget->hasNEON())) { 10642 return fastEmitInst_ri(AArch64::SQSHLv16i8_shift, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 10643 } 10644 return 0; 10645} 10646 10647unsigned fastEmit_AArch64ISD_SQSHL_I_ri_Predicate_vecshiftL8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10648 switch (VT.SimpleTy) { 10649 case MVT::v8i8: return fastEmit_AArch64ISD_SQSHL_I_MVT_v8i8_ri_Predicate_vecshiftL8(RetVT, Op0, Op0IsKill, imm1); 10650 case MVT::v16i8: return fastEmit_AArch64ISD_SQSHL_I_MVT_v16i8_ri_Predicate_vecshiftL8(RetVT, Op0, Op0IsKill, imm1); 10651 default: return 0; 10652 } 10653} 10654 10655// FastEmit functions for AArch64ISD::UQSHL_I. 10656 10657unsigned fastEmit_AArch64ISD_UQSHL_I_MVT_v8i8_ri_Predicate_vecshiftL8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10658 if (RetVT.SimpleTy != MVT::v8i8) 10659 return 0; 10660 if ((Subtarget->hasNEON())) { 10661 return fastEmitInst_ri(AArch64::UQSHLv8i8_shift, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 10662 } 10663 return 0; 10664} 10665 10666unsigned fastEmit_AArch64ISD_UQSHL_I_MVT_v16i8_ri_Predicate_vecshiftL8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10667 if (RetVT.SimpleTy != MVT::v16i8) 10668 return 0; 10669 if ((Subtarget->hasNEON())) { 10670 return fastEmitInst_ri(AArch64::UQSHLv16i8_shift, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 10671 } 10672 return 0; 10673} 10674 10675unsigned fastEmit_AArch64ISD_UQSHL_I_ri_Predicate_vecshiftL8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10676 switch (VT.SimpleTy) { 10677 case MVT::v8i8: return fastEmit_AArch64ISD_UQSHL_I_MVT_v8i8_ri_Predicate_vecshiftL8(RetVT, Op0, Op0IsKill, imm1); 10678 case MVT::v16i8: return fastEmit_AArch64ISD_UQSHL_I_MVT_v16i8_ri_Predicate_vecshiftL8(RetVT, Op0, Op0IsKill, imm1); 10679 default: return 0; 10680 } 10681} 10682 10683// FastEmit functions for AArch64ISD::VSHL. 10684 10685unsigned fastEmit_AArch64ISD_VSHL_MVT_v8i8_ri_Predicate_vecshiftL8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10686 if (RetVT.SimpleTy != MVT::v8i8) 10687 return 0; 10688 if ((Subtarget->hasNEON())) { 10689 return fastEmitInst_ri(AArch64::SHLv8i8_shift, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 10690 } 10691 return 0; 10692} 10693 10694unsigned fastEmit_AArch64ISD_VSHL_MVT_v16i8_ri_Predicate_vecshiftL8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10695 if (RetVT.SimpleTy != MVT::v16i8) 10696 return 0; 10697 if ((Subtarget->hasNEON())) { 10698 return fastEmitInst_ri(AArch64::SHLv16i8_shift, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 10699 } 10700 return 0; 10701} 10702 10703unsigned fastEmit_AArch64ISD_VSHL_ri_Predicate_vecshiftL8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10704 switch (VT.SimpleTy) { 10705 case MVT::v8i8: return fastEmit_AArch64ISD_VSHL_MVT_v8i8_ri_Predicate_vecshiftL8(RetVT, Op0, Op0IsKill, imm1); 10706 case MVT::v16i8: return fastEmit_AArch64ISD_VSHL_MVT_v16i8_ri_Predicate_vecshiftL8(RetVT, Op0, Op0IsKill, imm1); 10707 default: return 0; 10708 } 10709} 10710 10711// Top-level FastEmit function. 10712 10713unsigned fastEmit_ri_Predicate_vecshiftL8(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10714 switch (Opcode) { 10715 case AArch64ISD::SQSHLU_I: return fastEmit_AArch64ISD_SQSHLU_I_ri_Predicate_vecshiftL8(VT, RetVT, Op0, Op0IsKill, imm1); 10716 case AArch64ISD::SQSHL_I: return fastEmit_AArch64ISD_SQSHL_I_ri_Predicate_vecshiftL8(VT, RetVT, Op0, Op0IsKill, imm1); 10717 case AArch64ISD::UQSHL_I: return fastEmit_AArch64ISD_UQSHL_I_ri_Predicate_vecshiftL8(VT, RetVT, Op0, Op0IsKill, imm1); 10718 case AArch64ISD::VSHL: return fastEmit_AArch64ISD_VSHL_ri_Predicate_vecshiftL8(VT, RetVT, Op0, Op0IsKill, imm1); 10719 default: return 0; 10720 } 10721} 10722 10723// FastEmit functions for AArch64ISD::SQSHLU_I. 10724 10725unsigned fastEmit_AArch64ISD_SQSHLU_I_MVT_v4i16_ri_Predicate_vecshiftL16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10726 if (RetVT.SimpleTy != MVT::v4i16) 10727 return 0; 10728 if ((Subtarget->hasNEON())) { 10729 return fastEmitInst_ri(AArch64::SQSHLUv4i16_shift, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 10730 } 10731 return 0; 10732} 10733 10734unsigned fastEmit_AArch64ISD_SQSHLU_I_MVT_v8i16_ri_Predicate_vecshiftL16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10735 if (RetVT.SimpleTy != MVT::v8i16) 10736 return 0; 10737 if ((Subtarget->hasNEON())) { 10738 return fastEmitInst_ri(AArch64::SQSHLUv8i16_shift, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 10739 } 10740 return 0; 10741} 10742 10743unsigned fastEmit_AArch64ISD_SQSHLU_I_ri_Predicate_vecshiftL16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10744 switch (VT.SimpleTy) { 10745 case MVT::v4i16: return fastEmit_AArch64ISD_SQSHLU_I_MVT_v4i16_ri_Predicate_vecshiftL16(RetVT, Op0, Op0IsKill, imm1); 10746 case MVT::v8i16: return fastEmit_AArch64ISD_SQSHLU_I_MVT_v8i16_ri_Predicate_vecshiftL16(RetVT, Op0, Op0IsKill, imm1); 10747 default: return 0; 10748 } 10749} 10750 10751// FastEmit functions for AArch64ISD::SQSHL_I. 10752 10753unsigned fastEmit_AArch64ISD_SQSHL_I_MVT_v4i16_ri_Predicate_vecshiftL16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10754 if (RetVT.SimpleTy != MVT::v4i16) 10755 return 0; 10756 if ((Subtarget->hasNEON())) { 10757 return fastEmitInst_ri(AArch64::SQSHLv4i16_shift, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 10758 } 10759 return 0; 10760} 10761 10762unsigned fastEmit_AArch64ISD_SQSHL_I_MVT_v8i16_ri_Predicate_vecshiftL16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10763 if (RetVT.SimpleTy != MVT::v8i16) 10764 return 0; 10765 if ((Subtarget->hasNEON())) { 10766 return fastEmitInst_ri(AArch64::SQSHLv8i16_shift, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 10767 } 10768 return 0; 10769} 10770 10771unsigned fastEmit_AArch64ISD_SQSHL_I_ri_Predicate_vecshiftL16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10772 switch (VT.SimpleTy) { 10773 case MVT::v4i16: return fastEmit_AArch64ISD_SQSHL_I_MVT_v4i16_ri_Predicate_vecshiftL16(RetVT, Op0, Op0IsKill, imm1); 10774 case MVT::v8i16: return fastEmit_AArch64ISD_SQSHL_I_MVT_v8i16_ri_Predicate_vecshiftL16(RetVT, Op0, Op0IsKill, imm1); 10775 default: return 0; 10776 } 10777} 10778 10779// FastEmit functions for AArch64ISD::UQSHL_I. 10780 10781unsigned fastEmit_AArch64ISD_UQSHL_I_MVT_v4i16_ri_Predicate_vecshiftL16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10782 if (RetVT.SimpleTy != MVT::v4i16) 10783 return 0; 10784 if ((Subtarget->hasNEON())) { 10785 return fastEmitInst_ri(AArch64::UQSHLv4i16_shift, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 10786 } 10787 return 0; 10788} 10789 10790unsigned fastEmit_AArch64ISD_UQSHL_I_MVT_v8i16_ri_Predicate_vecshiftL16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10791 if (RetVT.SimpleTy != MVT::v8i16) 10792 return 0; 10793 if ((Subtarget->hasNEON())) { 10794 return fastEmitInst_ri(AArch64::UQSHLv8i16_shift, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 10795 } 10796 return 0; 10797} 10798 10799unsigned fastEmit_AArch64ISD_UQSHL_I_ri_Predicate_vecshiftL16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10800 switch (VT.SimpleTy) { 10801 case MVT::v4i16: return fastEmit_AArch64ISD_UQSHL_I_MVT_v4i16_ri_Predicate_vecshiftL16(RetVT, Op0, Op0IsKill, imm1); 10802 case MVT::v8i16: return fastEmit_AArch64ISD_UQSHL_I_MVT_v8i16_ri_Predicate_vecshiftL16(RetVT, Op0, Op0IsKill, imm1); 10803 default: return 0; 10804 } 10805} 10806 10807// FastEmit functions for AArch64ISD::VSHL. 10808 10809unsigned fastEmit_AArch64ISD_VSHL_MVT_v4i16_ri_Predicate_vecshiftL16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10810 if (RetVT.SimpleTy != MVT::v4i16) 10811 return 0; 10812 if ((Subtarget->hasNEON())) { 10813 return fastEmitInst_ri(AArch64::SHLv4i16_shift, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 10814 } 10815 return 0; 10816} 10817 10818unsigned fastEmit_AArch64ISD_VSHL_MVT_v8i16_ri_Predicate_vecshiftL16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10819 if (RetVT.SimpleTy != MVT::v8i16) 10820 return 0; 10821 if ((Subtarget->hasNEON())) { 10822 return fastEmitInst_ri(AArch64::SHLv8i16_shift, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 10823 } 10824 return 0; 10825} 10826 10827unsigned fastEmit_AArch64ISD_VSHL_ri_Predicate_vecshiftL16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10828 switch (VT.SimpleTy) { 10829 case MVT::v4i16: return fastEmit_AArch64ISD_VSHL_MVT_v4i16_ri_Predicate_vecshiftL16(RetVT, Op0, Op0IsKill, imm1); 10830 case MVT::v8i16: return fastEmit_AArch64ISD_VSHL_MVT_v8i16_ri_Predicate_vecshiftL16(RetVT, Op0, Op0IsKill, imm1); 10831 default: return 0; 10832 } 10833} 10834 10835// Top-level FastEmit function. 10836 10837unsigned fastEmit_ri_Predicate_vecshiftL16(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10838 switch (Opcode) { 10839 case AArch64ISD::SQSHLU_I: return fastEmit_AArch64ISD_SQSHLU_I_ri_Predicate_vecshiftL16(VT, RetVT, Op0, Op0IsKill, imm1); 10840 case AArch64ISD::SQSHL_I: return fastEmit_AArch64ISD_SQSHL_I_ri_Predicate_vecshiftL16(VT, RetVT, Op0, Op0IsKill, imm1); 10841 case AArch64ISD::UQSHL_I: return fastEmit_AArch64ISD_UQSHL_I_ri_Predicate_vecshiftL16(VT, RetVT, Op0, Op0IsKill, imm1); 10842 case AArch64ISD::VSHL: return fastEmit_AArch64ISD_VSHL_ri_Predicate_vecshiftL16(VT, RetVT, Op0, Op0IsKill, imm1); 10843 default: return 0; 10844 } 10845} 10846 10847// FastEmit functions for AArch64ISD::SRSHR_I. 10848 10849unsigned fastEmit_AArch64ISD_SRSHR_I_MVT_v8i8_ri_Predicate_vecshiftR8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10850 if (RetVT.SimpleTy != MVT::v8i8) 10851 return 0; 10852 if ((Subtarget->hasNEON())) { 10853 return fastEmitInst_ri(AArch64::SRSHRv8i8_shift, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 10854 } 10855 return 0; 10856} 10857 10858unsigned fastEmit_AArch64ISD_SRSHR_I_MVT_v16i8_ri_Predicate_vecshiftR8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10859 if (RetVT.SimpleTy != MVT::v16i8) 10860 return 0; 10861 if ((Subtarget->hasNEON())) { 10862 return fastEmitInst_ri(AArch64::SRSHRv16i8_shift, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 10863 } 10864 return 0; 10865} 10866 10867unsigned fastEmit_AArch64ISD_SRSHR_I_ri_Predicate_vecshiftR8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10868 switch (VT.SimpleTy) { 10869 case MVT::v8i8: return fastEmit_AArch64ISD_SRSHR_I_MVT_v8i8_ri_Predicate_vecshiftR8(RetVT, Op0, Op0IsKill, imm1); 10870 case MVT::v16i8: return fastEmit_AArch64ISD_SRSHR_I_MVT_v16i8_ri_Predicate_vecshiftR8(RetVT, Op0, Op0IsKill, imm1); 10871 default: return 0; 10872 } 10873} 10874 10875// FastEmit functions for AArch64ISD::URSHR_I. 10876 10877unsigned fastEmit_AArch64ISD_URSHR_I_MVT_v8i8_ri_Predicate_vecshiftR8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10878 if (RetVT.SimpleTy != MVT::v8i8) 10879 return 0; 10880 if ((Subtarget->hasNEON())) { 10881 return fastEmitInst_ri(AArch64::URSHRv8i8_shift, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 10882 } 10883 return 0; 10884} 10885 10886unsigned fastEmit_AArch64ISD_URSHR_I_MVT_v16i8_ri_Predicate_vecshiftR8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10887 if (RetVT.SimpleTy != MVT::v16i8) 10888 return 0; 10889 if ((Subtarget->hasNEON())) { 10890 return fastEmitInst_ri(AArch64::URSHRv16i8_shift, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 10891 } 10892 return 0; 10893} 10894 10895unsigned fastEmit_AArch64ISD_URSHR_I_ri_Predicate_vecshiftR8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10896 switch (VT.SimpleTy) { 10897 case MVT::v8i8: return fastEmit_AArch64ISD_URSHR_I_MVT_v8i8_ri_Predicate_vecshiftR8(RetVT, Op0, Op0IsKill, imm1); 10898 case MVT::v16i8: return fastEmit_AArch64ISD_URSHR_I_MVT_v16i8_ri_Predicate_vecshiftR8(RetVT, Op0, Op0IsKill, imm1); 10899 default: return 0; 10900 } 10901} 10902 10903// FastEmit functions for AArch64ISD::VASHR. 10904 10905unsigned fastEmit_AArch64ISD_VASHR_MVT_v8i8_ri_Predicate_vecshiftR8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10906 if (RetVT.SimpleTy != MVT::v8i8) 10907 return 0; 10908 if ((Subtarget->hasNEON())) { 10909 return fastEmitInst_ri(AArch64::SSHRv8i8_shift, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 10910 } 10911 return 0; 10912} 10913 10914unsigned fastEmit_AArch64ISD_VASHR_MVT_v16i8_ri_Predicate_vecshiftR8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10915 if (RetVT.SimpleTy != MVT::v16i8) 10916 return 0; 10917 if ((Subtarget->hasNEON())) { 10918 return fastEmitInst_ri(AArch64::SSHRv16i8_shift, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 10919 } 10920 return 0; 10921} 10922 10923unsigned fastEmit_AArch64ISD_VASHR_ri_Predicate_vecshiftR8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10924 switch (VT.SimpleTy) { 10925 case MVT::v8i8: return fastEmit_AArch64ISD_VASHR_MVT_v8i8_ri_Predicate_vecshiftR8(RetVT, Op0, Op0IsKill, imm1); 10926 case MVT::v16i8: return fastEmit_AArch64ISD_VASHR_MVT_v16i8_ri_Predicate_vecshiftR8(RetVT, Op0, Op0IsKill, imm1); 10927 default: return 0; 10928 } 10929} 10930 10931// FastEmit functions for AArch64ISD::VLSHR. 10932 10933unsigned fastEmit_AArch64ISD_VLSHR_MVT_v8i8_ri_Predicate_vecshiftR8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10934 if (RetVT.SimpleTy != MVT::v8i8) 10935 return 0; 10936 if ((Subtarget->hasNEON())) { 10937 return fastEmitInst_ri(AArch64::USHRv8i8_shift, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 10938 } 10939 return 0; 10940} 10941 10942unsigned fastEmit_AArch64ISD_VLSHR_MVT_v16i8_ri_Predicate_vecshiftR8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10943 if (RetVT.SimpleTy != MVT::v16i8) 10944 return 0; 10945 if ((Subtarget->hasNEON())) { 10946 return fastEmitInst_ri(AArch64::USHRv16i8_shift, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 10947 } 10948 return 0; 10949} 10950 10951unsigned fastEmit_AArch64ISD_VLSHR_ri_Predicate_vecshiftR8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10952 switch (VT.SimpleTy) { 10953 case MVT::v8i8: return fastEmit_AArch64ISD_VLSHR_MVT_v8i8_ri_Predicate_vecshiftR8(RetVT, Op0, Op0IsKill, imm1); 10954 case MVT::v16i8: return fastEmit_AArch64ISD_VLSHR_MVT_v16i8_ri_Predicate_vecshiftR8(RetVT, Op0, Op0IsKill, imm1); 10955 default: return 0; 10956 } 10957} 10958 10959// Top-level FastEmit function. 10960 10961unsigned fastEmit_ri_Predicate_vecshiftR8(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10962 switch (Opcode) { 10963 case AArch64ISD::SRSHR_I: return fastEmit_AArch64ISD_SRSHR_I_ri_Predicate_vecshiftR8(VT, RetVT, Op0, Op0IsKill, imm1); 10964 case AArch64ISD::URSHR_I: return fastEmit_AArch64ISD_URSHR_I_ri_Predicate_vecshiftR8(VT, RetVT, Op0, Op0IsKill, imm1); 10965 case AArch64ISD::VASHR: return fastEmit_AArch64ISD_VASHR_ri_Predicate_vecshiftR8(VT, RetVT, Op0, Op0IsKill, imm1); 10966 case AArch64ISD::VLSHR: return fastEmit_AArch64ISD_VLSHR_ri_Predicate_vecshiftR8(VT, RetVT, Op0, Op0IsKill, imm1); 10967 default: return 0; 10968 } 10969} 10970 10971// FastEmit functions for AArch64ISD::SRSHR_I. 10972 10973unsigned fastEmit_AArch64ISD_SRSHR_I_MVT_v4i16_ri_Predicate_vecshiftR16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10974 if (RetVT.SimpleTy != MVT::v4i16) 10975 return 0; 10976 if ((Subtarget->hasNEON())) { 10977 return fastEmitInst_ri(AArch64::SRSHRv4i16_shift, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 10978 } 10979 return 0; 10980} 10981 10982unsigned fastEmit_AArch64ISD_SRSHR_I_MVT_v8i16_ri_Predicate_vecshiftR16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10983 if (RetVT.SimpleTy != MVT::v8i16) 10984 return 0; 10985 if ((Subtarget->hasNEON())) { 10986 return fastEmitInst_ri(AArch64::SRSHRv8i16_shift, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 10987 } 10988 return 0; 10989} 10990 10991unsigned fastEmit_AArch64ISD_SRSHR_I_ri_Predicate_vecshiftR16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 10992 switch (VT.SimpleTy) { 10993 case MVT::v4i16: return fastEmit_AArch64ISD_SRSHR_I_MVT_v4i16_ri_Predicate_vecshiftR16(RetVT, Op0, Op0IsKill, imm1); 10994 case MVT::v8i16: return fastEmit_AArch64ISD_SRSHR_I_MVT_v8i16_ri_Predicate_vecshiftR16(RetVT, Op0, Op0IsKill, imm1); 10995 default: return 0; 10996 } 10997} 10998 10999// FastEmit functions for AArch64ISD::URSHR_I. 11000 11001unsigned fastEmit_AArch64ISD_URSHR_I_MVT_v4i16_ri_Predicate_vecshiftR16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 11002 if (RetVT.SimpleTy != MVT::v4i16) 11003 return 0; 11004 if ((Subtarget->hasNEON())) { 11005 return fastEmitInst_ri(AArch64::URSHRv4i16_shift, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 11006 } 11007 return 0; 11008} 11009 11010unsigned fastEmit_AArch64ISD_URSHR_I_MVT_v8i16_ri_Predicate_vecshiftR16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 11011 if (RetVT.SimpleTy != MVT::v8i16) 11012 return 0; 11013 if ((Subtarget->hasNEON())) { 11014 return fastEmitInst_ri(AArch64::URSHRv8i16_shift, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 11015 } 11016 return 0; 11017} 11018 11019unsigned fastEmit_AArch64ISD_URSHR_I_ri_Predicate_vecshiftR16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 11020 switch (VT.SimpleTy) { 11021 case MVT::v4i16: return fastEmit_AArch64ISD_URSHR_I_MVT_v4i16_ri_Predicate_vecshiftR16(RetVT, Op0, Op0IsKill, imm1); 11022 case MVT::v8i16: return fastEmit_AArch64ISD_URSHR_I_MVT_v8i16_ri_Predicate_vecshiftR16(RetVT, Op0, Op0IsKill, imm1); 11023 default: return 0; 11024 } 11025} 11026 11027// FastEmit functions for AArch64ISD::VASHR. 11028 11029unsigned fastEmit_AArch64ISD_VASHR_MVT_v4i16_ri_Predicate_vecshiftR16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 11030 if (RetVT.SimpleTy != MVT::v4i16) 11031 return 0; 11032 if ((Subtarget->hasNEON())) { 11033 return fastEmitInst_ri(AArch64::SSHRv4i16_shift, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 11034 } 11035 return 0; 11036} 11037 11038unsigned fastEmit_AArch64ISD_VASHR_MVT_v8i16_ri_Predicate_vecshiftR16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 11039 if (RetVT.SimpleTy != MVT::v8i16) 11040 return 0; 11041 if ((Subtarget->hasNEON())) { 11042 return fastEmitInst_ri(AArch64::SSHRv8i16_shift, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 11043 } 11044 return 0; 11045} 11046 11047unsigned fastEmit_AArch64ISD_VASHR_ri_Predicate_vecshiftR16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 11048 switch (VT.SimpleTy) { 11049 case MVT::v4i16: return fastEmit_AArch64ISD_VASHR_MVT_v4i16_ri_Predicate_vecshiftR16(RetVT, Op0, Op0IsKill, imm1); 11050 case MVT::v8i16: return fastEmit_AArch64ISD_VASHR_MVT_v8i16_ri_Predicate_vecshiftR16(RetVT, Op0, Op0IsKill, imm1); 11051 default: return 0; 11052 } 11053} 11054 11055// FastEmit functions for AArch64ISD::VLSHR. 11056 11057unsigned fastEmit_AArch64ISD_VLSHR_MVT_v4i16_ri_Predicate_vecshiftR16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 11058 if (RetVT.SimpleTy != MVT::v4i16) 11059 return 0; 11060 if ((Subtarget->hasNEON())) { 11061 return fastEmitInst_ri(AArch64::USHRv4i16_shift, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 11062 } 11063 return 0; 11064} 11065 11066unsigned fastEmit_AArch64ISD_VLSHR_MVT_v8i16_ri_Predicate_vecshiftR16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 11067 if (RetVT.SimpleTy != MVT::v8i16) 11068 return 0; 11069 if ((Subtarget->hasNEON())) { 11070 return fastEmitInst_ri(AArch64::USHRv8i16_shift, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 11071 } 11072 return 0; 11073} 11074 11075unsigned fastEmit_AArch64ISD_VLSHR_ri_Predicate_vecshiftR16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 11076 switch (VT.SimpleTy) { 11077 case MVT::v4i16: return fastEmit_AArch64ISD_VLSHR_MVT_v4i16_ri_Predicate_vecshiftR16(RetVT, Op0, Op0IsKill, imm1); 11078 case MVT::v8i16: return fastEmit_AArch64ISD_VLSHR_MVT_v8i16_ri_Predicate_vecshiftR16(RetVT, Op0, Op0IsKill, imm1); 11079 default: return 0; 11080 } 11081} 11082 11083// Top-level FastEmit function. 11084 11085unsigned fastEmit_ri_Predicate_vecshiftR16(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 11086 switch (Opcode) { 11087 case AArch64ISD::SRSHR_I: return fastEmit_AArch64ISD_SRSHR_I_ri_Predicate_vecshiftR16(VT, RetVT, Op0, Op0IsKill, imm1); 11088 case AArch64ISD::URSHR_I: return fastEmit_AArch64ISD_URSHR_I_ri_Predicate_vecshiftR16(VT, RetVT, Op0, Op0IsKill, imm1); 11089 case AArch64ISD::VASHR: return fastEmit_AArch64ISD_VASHR_ri_Predicate_vecshiftR16(VT, RetVT, Op0, Op0IsKill, imm1); 11090 case AArch64ISD::VLSHR: return fastEmit_AArch64ISD_VLSHR_ri_Predicate_vecshiftR16(VT, RetVT, Op0, Op0IsKill, imm1); 11091 default: return 0; 11092 } 11093} 11094 11095// FastEmit functions for AArch64ISD::SRSHR_I. 11096 11097unsigned fastEmit_AArch64ISD_SRSHR_I_MVT_v2i32_ri_Predicate_vecshiftR32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 11098 if (RetVT.SimpleTy != MVT::v2i32) 11099 return 0; 11100 if ((Subtarget->hasNEON())) { 11101 return fastEmitInst_ri(AArch64::SRSHRv2i32_shift, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 11102 } 11103 return 0; 11104} 11105 11106unsigned fastEmit_AArch64ISD_SRSHR_I_MVT_v4i32_ri_Predicate_vecshiftR32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 11107 if (RetVT.SimpleTy != MVT::v4i32) 11108 return 0; 11109 if ((Subtarget->hasNEON())) { 11110 return fastEmitInst_ri(AArch64::SRSHRv4i32_shift, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 11111 } 11112 return 0; 11113} 11114 11115unsigned fastEmit_AArch64ISD_SRSHR_I_ri_Predicate_vecshiftR32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 11116 switch (VT.SimpleTy) { 11117 case MVT::v2i32: return fastEmit_AArch64ISD_SRSHR_I_MVT_v2i32_ri_Predicate_vecshiftR32(RetVT, Op0, Op0IsKill, imm1); 11118 case MVT::v4i32: return fastEmit_AArch64ISD_SRSHR_I_MVT_v4i32_ri_Predicate_vecshiftR32(RetVT, Op0, Op0IsKill, imm1); 11119 default: return 0; 11120 } 11121} 11122 11123// FastEmit functions for AArch64ISD::URSHR_I. 11124 11125unsigned fastEmit_AArch64ISD_URSHR_I_MVT_v2i32_ri_Predicate_vecshiftR32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 11126 if (RetVT.SimpleTy != MVT::v2i32) 11127 return 0; 11128 if ((Subtarget->hasNEON())) { 11129 return fastEmitInst_ri(AArch64::URSHRv2i32_shift, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 11130 } 11131 return 0; 11132} 11133 11134unsigned fastEmit_AArch64ISD_URSHR_I_MVT_v4i32_ri_Predicate_vecshiftR32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 11135 if (RetVT.SimpleTy != MVT::v4i32) 11136 return 0; 11137 if ((Subtarget->hasNEON())) { 11138 return fastEmitInst_ri(AArch64::URSHRv4i32_shift, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 11139 } 11140 return 0; 11141} 11142 11143unsigned fastEmit_AArch64ISD_URSHR_I_ri_Predicate_vecshiftR32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 11144 switch (VT.SimpleTy) { 11145 case MVT::v2i32: return fastEmit_AArch64ISD_URSHR_I_MVT_v2i32_ri_Predicate_vecshiftR32(RetVT, Op0, Op0IsKill, imm1); 11146 case MVT::v4i32: return fastEmit_AArch64ISD_URSHR_I_MVT_v4i32_ri_Predicate_vecshiftR32(RetVT, Op0, Op0IsKill, imm1); 11147 default: return 0; 11148 } 11149} 11150 11151// FastEmit functions for AArch64ISD::VASHR. 11152 11153unsigned fastEmit_AArch64ISD_VASHR_MVT_v2i32_ri_Predicate_vecshiftR32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 11154 if (RetVT.SimpleTy != MVT::v2i32) 11155 return 0; 11156 if ((Subtarget->hasNEON())) { 11157 return fastEmitInst_ri(AArch64::SSHRv2i32_shift, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 11158 } 11159 return 0; 11160} 11161 11162unsigned fastEmit_AArch64ISD_VASHR_MVT_v4i32_ri_Predicate_vecshiftR32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 11163 if (RetVT.SimpleTy != MVT::v4i32) 11164 return 0; 11165 if ((Subtarget->hasNEON())) { 11166 return fastEmitInst_ri(AArch64::SSHRv4i32_shift, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 11167 } 11168 return 0; 11169} 11170 11171unsigned fastEmit_AArch64ISD_VASHR_ri_Predicate_vecshiftR32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 11172 switch (VT.SimpleTy) { 11173 case MVT::v2i32: return fastEmit_AArch64ISD_VASHR_MVT_v2i32_ri_Predicate_vecshiftR32(RetVT, Op0, Op0IsKill, imm1); 11174 case MVT::v4i32: return fastEmit_AArch64ISD_VASHR_MVT_v4i32_ri_Predicate_vecshiftR32(RetVT, Op0, Op0IsKill, imm1); 11175 default: return 0; 11176 } 11177} 11178 11179// FastEmit functions for AArch64ISD::VLSHR. 11180 11181unsigned fastEmit_AArch64ISD_VLSHR_MVT_v2i32_ri_Predicate_vecshiftR32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 11182 if (RetVT.SimpleTy != MVT::v2i32) 11183 return 0; 11184 if ((Subtarget->hasNEON())) { 11185 return fastEmitInst_ri(AArch64::USHRv2i32_shift, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 11186 } 11187 return 0; 11188} 11189 11190unsigned fastEmit_AArch64ISD_VLSHR_MVT_v4i32_ri_Predicate_vecshiftR32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 11191 if (RetVT.SimpleTy != MVT::v4i32) 11192 return 0; 11193 if ((Subtarget->hasNEON())) { 11194 return fastEmitInst_ri(AArch64::USHRv4i32_shift, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 11195 } 11196 return 0; 11197} 11198 11199unsigned fastEmit_AArch64ISD_VLSHR_ri_Predicate_vecshiftR32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 11200 switch (VT.SimpleTy) { 11201 case MVT::v2i32: return fastEmit_AArch64ISD_VLSHR_MVT_v2i32_ri_Predicate_vecshiftR32(RetVT, Op0, Op0IsKill, imm1); 11202 case MVT::v4i32: return fastEmit_AArch64ISD_VLSHR_MVT_v4i32_ri_Predicate_vecshiftR32(RetVT, Op0, Op0IsKill, imm1); 11203 default: return 0; 11204 } 11205} 11206 11207// Top-level FastEmit function. 11208 11209unsigned fastEmit_ri_Predicate_vecshiftR32(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 11210 switch (Opcode) { 11211 case AArch64ISD::SRSHR_I: return fastEmit_AArch64ISD_SRSHR_I_ri_Predicate_vecshiftR32(VT, RetVT, Op0, Op0IsKill, imm1); 11212 case AArch64ISD::URSHR_I: return fastEmit_AArch64ISD_URSHR_I_ri_Predicate_vecshiftR32(VT, RetVT, Op0, Op0IsKill, imm1); 11213 case AArch64ISD::VASHR: return fastEmit_AArch64ISD_VASHR_ri_Predicate_vecshiftR32(VT, RetVT, Op0, Op0IsKill, imm1); 11214 case AArch64ISD::VLSHR: return fastEmit_AArch64ISD_VLSHR_ri_Predicate_vecshiftR32(VT, RetVT, Op0, Op0IsKill, imm1); 11215 default: return 0; 11216 } 11217} 11218 11219// FastEmit functions for ISD::Constant. 11220 11221unsigned fastEmit_ISD_Constant_MVT_i32_i(MVT RetVT, uint64_t imm0) { 11222 if (RetVT.SimpleTy != MVT::i32) 11223 return 0; 11224 return fastEmitInst_i(AArch64::MOVi32imm, &AArch64::GPR32RegClass, imm0); 11225} 11226 11227unsigned fastEmit_ISD_Constant_MVT_i64_i(MVT RetVT, uint64_t imm0) { 11228 if (RetVT.SimpleTy != MVT::i64) 11229 return 0; 11230 return fastEmitInst_i(AArch64::MOVi64imm, &AArch64::GPR64RegClass, imm0); 11231} 11232 11233unsigned fastEmit_ISD_Constant_i(MVT VT, MVT RetVT, uint64_t imm0) { 11234 switch (VT.SimpleTy) { 11235 case MVT::i32: return fastEmit_ISD_Constant_MVT_i32_i(RetVT, imm0); 11236 case MVT::i64: return fastEmit_ISD_Constant_MVT_i64_i(RetVT, imm0); 11237 default: return 0; 11238 } 11239} 11240 11241// Top-level FastEmit function. 11242 11243unsigned fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t imm0) override { 11244 if (VT == MVT::i32 && Predicate_imm0_255(imm0)) 11245 if (unsigned Reg = fastEmit_i_Predicate_imm0_255(VT, RetVT, Opcode, imm0)) 11246 return Reg; 11247 11248 switch (Opcode) { 11249 case ISD::Constant: return fastEmit_ISD_Constant_i(VT, RetVT, imm0); 11250 default: return 0; 11251 } 11252} 11253 11254// FastEmit functions for AArch64ISD::FMOV. 11255 11256unsigned fastEmit_AArch64ISD_FMOV_MVT_i32_MVT_v4f16_i_Predicate_imm0_255(uint64_t imm0) { 11257 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 11258 return fastEmitInst_i(AArch64::FMOVv4f16_ns, &AArch64::FPR64RegClass, imm0); 11259 } 11260 return 0; 11261} 11262 11263unsigned fastEmit_AArch64ISD_FMOV_MVT_i32_MVT_v8f16_i_Predicate_imm0_255(uint64_t imm0) { 11264 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 11265 return fastEmitInst_i(AArch64::FMOVv8f16_ns, &AArch64::FPR128RegClass, imm0); 11266 } 11267 return 0; 11268} 11269 11270unsigned fastEmit_AArch64ISD_FMOV_MVT_i32_MVT_v2f32_i_Predicate_imm0_255(uint64_t imm0) { 11271 if ((Subtarget->hasNEON())) { 11272 return fastEmitInst_i(AArch64::FMOVv2f32_ns, &AArch64::FPR64RegClass, imm0); 11273 } 11274 return 0; 11275} 11276 11277unsigned fastEmit_AArch64ISD_FMOV_MVT_i32_MVT_v4f32_i_Predicate_imm0_255(uint64_t imm0) { 11278 if ((Subtarget->hasNEON())) { 11279 return fastEmitInst_i(AArch64::FMOVv4f32_ns, &AArch64::FPR128RegClass, imm0); 11280 } 11281 return 0; 11282} 11283 11284unsigned fastEmit_AArch64ISD_FMOV_MVT_i32_MVT_v2f64_i_Predicate_imm0_255(uint64_t imm0) { 11285 if ((Subtarget->hasNEON())) { 11286 return fastEmitInst_i(AArch64::FMOVv2f64_ns, &AArch64::FPR128RegClass, imm0); 11287 } 11288 return 0; 11289} 11290 11291unsigned fastEmit_AArch64ISD_FMOV_MVT_i32_i_Predicate_imm0_255(MVT RetVT, uint64_t imm0) { 11292switch (RetVT.SimpleTy) { 11293 case MVT::v4f16: return fastEmit_AArch64ISD_FMOV_MVT_i32_MVT_v4f16_i_Predicate_imm0_255(imm0); 11294 case MVT::v8f16: return fastEmit_AArch64ISD_FMOV_MVT_i32_MVT_v8f16_i_Predicate_imm0_255(imm0); 11295 case MVT::v2f32: return fastEmit_AArch64ISD_FMOV_MVT_i32_MVT_v2f32_i_Predicate_imm0_255(imm0); 11296 case MVT::v4f32: return fastEmit_AArch64ISD_FMOV_MVT_i32_MVT_v4f32_i_Predicate_imm0_255(imm0); 11297 case MVT::v2f64: return fastEmit_AArch64ISD_FMOV_MVT_i32_MVT_v2f64_i_Predicate_imm0_255(imm0); 11298 default: return 0; 11299} 11300} 11301 11302unsigned fastEmit_AArch64ISD_FMOV_i_Predicate_imm0_255(MVT VT, MVT RetVT, uint64_t imm0) { 11303 switch (VT.SimpleTy) { 11304 case MVT::i32: return fastEmit_AArch64ISD_FMOV_MVT_i32_i_Predicate_imm0_255(RetVT, imm0); 11305 default: return 0; 11306 } 11307} 11308 11309// FastEmit functions for AArch64ISD::MOVI. 11310 11311unsigned fastEmit_AArch64ISD_MOVI_MVT_i32_MVT_v8i8_i_Predicate_imm0_255(uint64_t imm0) { 11312 if ((Subtarget->hasNEON())) { 11313 return fastEmitInst_i(AArch64::MOVIv8b_ns, &AArch64::FPR64RegClass, imm0); 11314 } 11315 return 0; 11316} 11317 11318unsigned fastEmit_AArch64ISD_MOVI_MVT_i32_MVT_v16i8_i_Predicate_imm0_255(uint64_t imm0) { 11319 if ((Subtarget->hasNEON())) { 11320 return fastEmitInst_i(AArch64::MOVIv16b_ns, &AArch64::FPR128RegClass, imm0); 11321 } 11322 return 0; 11323} 11324 11325unsigned fastEmit_AArch64ISD_MOVI_MVT_i32_i_Predicate_imm0_255(MVT RetVT, uint64_t imm0) { 11326switch (RetVT.SimpleTy) { 11327 case MVT::v8i8: return fastEmit_AArch64ISD_MOVI_MVT_i32_MVT_v8i8_i_Predicate_imm0_255(imm0); 11328 case MVT::v16i8: return fastEmit_AArch64ISD_MOVI_MVT_i32_MVT_v16i8_i_Predicate_imm0_255(imm0); 11329 default: return 0; 11330} 11331} 11332 11333unsigned fastEmit_AArch64ISD_MOVI_i_Predicate_imm0_255(MVT VT, MVT RetVT, uint64_t imm0) { 11334 switch (VT.SimpleTy) { 11335 case MVT::i32: return fastEmit_AArch64ISD_MOVI_MVT_i32_i_Predicate_imm0_255(RetVT, imm0); 11336 default: return 0; 11337 } 11338} 11339 11340// FastEmit functions for AArch64ISD::MOVIedit. 11341 11342unsigned fastEmit_AArch64ISD_MOVIedit_MVT_i32_MVT_f64_i_Predicate_imm0_255(uint64_t imm0) { 11343 return fastEmitInst_i(AArch64::MOVID, &AArch64::FPR64RegClass, imm0); 11344} 11345 11346unsigned fastEmit_AArch64ISD_MOVIedit_MVT_i32_MVT_v2i64_i_Predicate_imm0_255(uint64_t imm0) { 11347 if ((Subtarget->hasNEON())) { 11348 return fastEmitInst_i(AArch64::MOVIv2d_ns, &AArch64::FPR128RegClass, imm0); 11349 } 11350 return 0; 11351} 11352 11353unsigned fastEmit_AArch64ISD_MOVIedit_MVT_i32_i_Predicate_imm0_255(MVT RetVT, uint64_t imm0) { 11354switch (RetVT.SimpleTy) { 11355 case MVT::f64: return fastEmit_AArch64ISD_MOVIedit_MVT_i32_MVT_f64_i_Predicate_imm0_255(imm0); 11356 case MVT::v2i64: return fastEmit_AArch64ISD_MOVIedit_MVT_i32_MVT_v2i64_i_Predicate_imm0_255(imm0); 11357 default: return 0; 11358} 11359} 11360 11361unsigned fastEmit_AArch64ISD_MOVIedit_i_Predicate_imm0_255(MVT VT, MVT RetVT, uint64_t imm0) { 11362 switch (VT.SimpleTy) { 11363 case MVT::i32: return fastEmit_AArch64ISD_MOVIedit_MVT_i32_i_Predicate_imm0_255(RetVT, imm0); 11364 default: return 0; 11365 } 11366} 11367 11368// Top-level FastEmit function. 11369 11370unsigned fastEmit_i_Predicate_imm0_255(MVT VT, MVT RetVT, unsigned Opcode, uint64_t imm0) { 11371 switch (Opcode) { 11372 case AArch64ISD::FMOV: return fastEmit_AArch64ISD_FMOV_i_Predicate_imm0_255(VT, RetVT, imm0); 11373 case AArch64ISD::MOVI: return fastEmit_AArch64ISD_MOVI_i_Predicate_imm0_255(VT, RetVT, imm0); 11374 case AArch64ISD::MOVIedit: return fastEmit_AArch64ISD_MOVIedit_i_Predicate_imm0_255(VT, RetVT, imm0); 11375 default: return 0; 11376 } 11377} 11378 11379