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1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|*                                                                            *|
3|* Global Instruction Selector for the Mips target                            *|
4|*                                                                            *|
5|* Automatically generated file, do not edit!                                 *|
6|*                                                                            *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_GLOBALISEL_PREDICATE_BITSET
10const unsigned MAX_SUBTARGET_PREDICATES = 44;
11using PredicateBitset = llvm::PredicateBitsetImpl<MAX_SUBTARGET_PREDICATES>;
12#endif // ifdef GET_GLOBALISEL_PREDICATE_BITSET
13
14#ifdef GET_GLOBALISEL_TEMPORARIES_DECL
15  mutable MatcherState State;
16  typedef ComplexRendererFns(MipsInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const;
17  typedef void(MipsInstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr&, int) const;
18  const ISelInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ISelInfo;
19  static MipsInstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[];
20  static MipsInstructionSelector::CustomRendererFn CustomRenderers[];
21  bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override;
22  bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override;
23  bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override;
24  const int64_t *getMatchTable() const override;
25  bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI) const override;
26#endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL
27
28#ifdef GET_GLOBALISEL_TEMPORARIES_INIT
29, State(0),
30ISelInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers)
31#endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT
32
33#ifdef GET_GLOBALISEL_IMPL
34// Bits for subtarget features that participate in instruction matching.
35enum SubtargetFeatureBits : uint8_t {
36  Feature_HasMips2Bit = 7,
37  Feature_HasMips3Bit = 17,
38  Feature_HasMips4_32Bit = 27,
39  Feature_NotMips4_32Bit = 28,
40  Feature_HasMips4_32r2Bit = 18,
41  Feature_HasMips32Bit = 3,
42  Feature_HasMips32r2Bit = 6,
43  Feature_HasMips32r6Bit = 29,
44  Feature_NotMips32r6Bit = 4,
45  Feature_IsGP64bitBit = 22,
46  Feature_IsPTR64bitBit = 24,
47  Feature_HasMips64Bit = 25,
48  Feature_HasMips64r2Bit = 23,
49  Feature_HasMips64r6Bit = 30,
50  Feature_NotMips64r6Bit = 5,
51  Feature_InMips16ModeBit = 31,
52  Feature_NotInMips16ModeBit = 0,
53  Feature_HasCnMipsBit = 26,
54  Feature_NotCnMipsBit = 8,
55  Feature_IsSym32Bit = 38,
56  Feature_IsSym64Bit = 39,
57  Feature_IsN64Bit = 40,
58  Feature_RelocNotPICBit = 9,
59  Feature_RelocPICBit = 37,
60  Feature_NoNaNsFPMathBit = 21,
61  Feature_UseAbsBit = 14,
62  Feature_HasStdEncBit = 1,
63  Feature_NotDSPBit = 11,
64  Feature_InMicroMipsBit = 35,
65  Feature_NotInMicroMipsBit = 2,
66  Feature_IsLEBit = 42,
67  Feature_IsBEBit = 43,
68  Feature_IsNotNaClBit = 19,
69  Feature_HasEVABit = 36,
70  Feature_HasMSABit = 34,
71  Feature_HasMadd4Bit = 20,
72  Feature_UseIndirectJumpsHazardBit = 12,
73  Feature_NoIndirectJumpGuardsBit = 10,
74  Feature_AllowFPOpFusionBit = 41,
75  Feature_IsFP64bitBit = 16,
76  Feature_NotFP64bitBit = 15,
77  Feature_IsNotSoftFloatBit = 13,
78  Feature_HasDSPBit = 32,
79  Feature_HasDSPR2Bit = 33,
80};
81
82PredicateBitset MipsInstructionSelector::
83computeAvailableModuleFeatures(const MipsSubtarget *Subtarget) const {
84  PredicateBitset Features;
85  if (Subtarget->hasMips2())
86    Features.set(Feature_HasMips2Bit);
87  if (Subtarget->hasMips3())
88    Features.set(Feature_HasMips3Bit);
89  if (Subtarget->hasMips4_32())
90    Features.set(Feature_HasMips4_32Bit);
91  if (!Subtarget->hasMips4_32())
92    Features.set(Feature_NotMips4_32Bit);
93  if (Subtarget->hasMips4_32r2())
94    Features.set(Feature_HasMips4_32r2Bit);
95  if (Subtarget->hasMips32())
96    Features.set(Feature_HasMips32Bit);
97  if (Subtarget->hasMips32r2())
98    Features.set(Feature_HasMips32r2Bit);
99  if (Subtarget->hasMips32r6())
100    Features.set(Feature_HasMips32r6Bit);
101  if (!Subtarget->hasMips32r6())
102    Features.set(Feature_NotMips32r6Bit);
103  if (Subtarget->isGP64bit())
104    Features.set(Feature_IsGP64bitBit);
105  if (Subtarget->isABI_N64())
106    Features.set(Feature_IsPTR64bitBit);
107  if (Subtarget->hasMips64())
108    Features.set(Feature_HasMips64Bit);
109  if (Subtarget->hasMips64r2())
110    Features.set(Feature_HasMips64r2Bit);
111  if (Subtarget->hasMips64r6())
112    Features.set(Feature_HasMips64r6Bit);
113  if (!Subtarget->hasMips64r6())
114    Features.set(Feature_NotMips64r6Bit);
115  if (Subtarget->inMips16Mode())
116    Features.set(Feature_InMips16ModeBit);
117  if (!Subtarget->inMips16Mode())
118    Features.set(Feature_NotInMips16ModeBit);
119  if (Subtarget->hasCnMips())
120    Features.set(Feature_HasCnMipsBit);
121  if (!Subtarget->hasCnMips())
122    Features.set(Feature_NotCnMipsBit);
123  if (Subtarget->hasSym32())
124    Features.set(Feature_IsSym32Bit);
125  if (!Subtarget->hasSym32())
126    Features.set(Feature_IsSym64Bit);
127  if (Subtarget->isABI_N64())
128    Features.set(Feature_IsN64Bit);
129  if (!TM.isPositionIndependent())
130    Features.set(Feature_RelocNotPICBit);
131  if (TM.isPositionIndependent())
132    Features.set(Feature_RelocPICBit);
133  if (TM.Options.NoNaNsFPMath)
134    Features.set(Feature_NoNaNsFPMathBit);
135  if (Subtarget->inAbs2008Mode() ||TM.Options.NoNaNsFPMath)
136    Features.set(Feature_UseAbsBit);
137  if (Subtarget->hasStandardEncoding())
138    Features.set(Feature_HasStdEncBit);
139  if (!Subtarget->hasDSP())
140    Features.set(Feature_NotDSPBit);
141  if (Subtarget->inMicroMipsMode())
142    Features.set(Feature_InMicroMipsBit);
143  if (!Subtarget->inMicroMipsMode())
144    Features.set(Feature_NotInMicroMipsBit);
145  if (Subtarget->isLittle())
146    Features.set(Feature_IsLEBit);
147  if (!Subtarget->isLittle())
148    Features.set(Feature_IsBEBit);
149  if (!Subtarget->isTargetNaCl())
150    Features.set(Feature_IsNotNaClBit);
151  if (Subtarget->hasEVA())
152    Features.set(Feature_HasEVABit);
153  if (Subtarget->hasMSA())
154    Features.set(Feature_HasMSABit);
155  if (!Subtarget->disableMadd4())
156    Features.set(Feature_HasMadd4Bit);
157  if (Subtarget->useIndirectJumpsHazard())
158    Features.set(Feature_UseIndirectJumpsHazardBit);
159  if (!Subtarget->useIndirectJumpsHazard())
160    Features.set(Feature_NoIndirectJumpGuardsBit);
161  if (TM.Options.AllowFPOpFusion == FPOpFusion::Fast)
162    Features.set(Feature_AllowFPOpFusionBit);
163  if (Subtarget->isFP64bit())
164    Features.set(Feature_IsFP64bitBit);
165  if (!Subtarget->isFP64bit())
166    Features.set(Feature_NotFP64bitBit);
167  if (!Subtarget->useSoftFloat())
168    Features.set(Feature_IsNotSoftFloatBit);
169  if (Subtarget->hasDSP())
170    Features.set(Feature_HasDSPBit);
171  if (Subtarget->hasDSPR2())
172    Features.set(Feature_HasDSPR2Bit);
173  return Features;
174}
175
176void MipsInstructionSelector::setupGeneratedPerFunctionState(MachineFunction &MF) {
177  AvailableFunctionFeatures = computeAvailableFunctionFeatures((const MipsSubtarget*)&MF.getSubtarget(), &MF);
178}
179PredicateBitset MipsInstructionSelector::
180computeAvailableFunctionFeatures(const MipsSubtarget *Subtarget, const MachineFunction *MF) const {
181  PredicateBitset Features;
182  return Features;
183}
184
185// LLT Objects.
186enum {
187  GILLT_s16,
188  GILLT_s32,
189  GILLT_s64,
190  GILLT_v2s16,
191  GILLT_v2s64,
192  GILLT_v4s8,
193  GILLT_v4s32,
194  GILLT_v8s16,
195  GILLT_v16s8,
196};
197const static size_t NumTypeObjects = 9;
198const static LLT TypeObjects[] = {
199  LLT::scalar(16),
200  LLT::scalar(32),
201  LLT::scalar(64),
202  LLT::vector(2, 16),
203  LLT::vector(2, 64),
204  LLT::vector(4, 8),
205  LLT::vector(4, 32),
206  LLT::vector(8, 16),
207  LLT::vector(16, 8),
208};
209
210// Feature bitsets.
211enum {
212  GIFBS_Invalid,
213  GIFBS_HasCnMips,
214  GIFBS_HasDSP,
215  GIFBS_HasDSPR2,
216  GIFBS_HasMSA,
217  GIFBS_InMicroMips,
218  GIFBS_InMips16Mode,
219  GIFBS_IsFP64bit,
220  GIFBS_NotFP64bit,
221  GIFBS_HasDSP_InMicroMips,
222  GIFBS_HasDSP_NotInMicroMips,
223  GIFBS_HasDSPR2_InMicroMips,
224  GIFBS_HasMSA_HasStdEnc,
225  GIFBS_HasMSA_IsBE,
226  GIFBS_HasMSA_IsLE,
227  GIFBS_HasMips32r6_HasStdEnc,
228  GIFBS_HasMips32r6_InMicroMips,
229  GIFBS_HasMips64r2_HasStdEnc,
230  GIFBS_HasMips64r6_HasStdEnc,
231  GIFBS_HasStdEnc_IsNotSoftFloat,
232  GIFBS_HasStdEnc_NotInMicroMips,
233  GIFBS_HasStdEnc_NotMips4_32,
234  GIFBS_InMicroMips_IsFP64bit,
235  GIFBS_InMicroMips_IsNotSoftFloat,
236  GIFBS_InMicroMips_NotFP64bit,
237  GIFBS_InMicroMips_NotMips32r6,
238  GIFBS_IsGP64bit_NotInMips16Mode,
239  GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc,
240  GIFBS_HasMSA_HasMips64_HasStdEnc,
241  GIFBS_HasMips3_HasStdEnc_IsGP64bit,
242  GIFBS_HasMips3_HasStdEnc_NotInMicroMips,
243  GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips,
244  GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
245  GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
246  GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
247  GIFBS_HasStdEnc_IsFP64bit_NotInMicroMips,
248  GIFBS_HasStdEnc_IsFP64bit_NotMips4_32,
249  GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
250  GIFBS_HasStdEnc_NotFP64bit_NotInMicroMips,
251  GIFBS_HasStdEnc_NotFP64bit_NotMips4_32,
252  GIFBS_HasStdEnc_NotInMicroMips_RelocNotPIC,
253  GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat,
254  GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit,
255  GIFBS_InMicroMips_IsNotSoftFloat_UseAbs,
256  GIFBS_InMicroMips_NotFP64bit_NotMips32r6,
257  GIFBS_InMicroMips_NotMips32r6_RelocNotPIC,
258  GIFBS_InMicroMips_NotMips32r6_RelocPIC,
259  GIFBS_HasMips2_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
260  GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips,
261  GIFBS_HasMips3_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
262  GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
263  GIFBS_HasMips4_32_HasStdEnc_NotMips32r6_NotMips64r6,
264  GIFBS_HasMips64r2_HasStdEnc_IsGP64bit_NotInMicroMips,
265  GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips,
266  GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips,
267  GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips_UseAbs,
268  GIFBS_HasMips2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips,
269  GIFBS_HasMips2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips,
270  GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
271  GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
272  GIFBS_HasMips64_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips64r6,
273  GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_UseAbs,
274  GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_UseAbs,
275  GIFBS_HasMadd4_InMicroMips_InMicroMips_NoNaNsFPMath_NotMips32r6_NotMips32r6,
276  GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
277  GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
278  GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
279  GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6,
280  GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6,
281  GIFBS_HasMadd4_InMicroMips_InMicroMips_NoNaNsFPMath_NotFP64bit_NotMips32r6_NotMips32r6,
282  GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6,
283  GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6,
284  GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
285  GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
286};
287const static PredicateBitset FeatureBitsets[] {
288  {}, // GIFBS_Invalid
289  {Feature_HasCnMipsBit, },
290  {Feature_HasDSPBit, },
291  {Feature_HasDSPR2Bit, },
292  {Feature_HasMSABit, },
293  {Feature_InMicroMipsBit, },
294  {Feature_InMips16ModeBit, },
295  {Feature_IsFP64bitBit, },
296  {Feature_NotFP64bitBit, },
297  {Feature_HasDSPBit, Feature_InMicroMipsBit, },
298  {Feature_HasDSPBit, Feature_NotInMicroMipsBit, },
299  {Feature_HasDSPR2Bit, Feature_InMicroMipsBit, },
300  {Feature_HasMSABit, Feature_HasStdEncBit, },
301  {Feature_HasMSABit, Feature_IsBEBit, },
302  {Feature_HasMSABit, Feature_IsLEBit, },
303  {Feature_HasMips32r6Bit, Feature_HasStdEncBit, },
304  {Feature_HasMips32r6Bit, Feature_InMicroMipsBit, },
305  {Feature_HasMips64r2Bit, Feature_HasStdEncBit, },
306  {Feature_HasMips64r6Bit, Feature_HasStdEncBit, },
307  {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, },
308  {Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
309  {Feature_HasStdEncBit, Feature_NotMips4_32Bit, },
310  {Feature_InMicroMipsBit, Feature_IsFP64bitBit, },
311  {Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, },
312  {Feature_InMicroMipsBit, Feature_NotFP64bitBit, },
313  {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, },
314  {Feature_IsGP64bitBit, Feature_NotInMips16ModeBit, },
315  {Feature_AllowFPOpFusionBit, Feature_HasMSABit, Feature_HasStdEncBit, },
316  {Feature_HasMSABit, Feature_HasMips64Bit, Feature_HasStdEncBit, },
317  {Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, },
318  {Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
319  {Feature_HasMips32r2Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
320  {Feature_HasMips32r6Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
321  {Feature_HasMips32r6Bit, Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, },
322  {Feature_HasMips64r6Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
323  {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotInMicroMipsBit, },
324  {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotMips4_32Bit, },
325  {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
326  {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, },
327  {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotMips4_32Bit, },
328  {Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_RelocNotPICBit, },
329  {Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, },
330  {Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, },
331  {Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, Feature_UseAbsBit, },
332  {Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, },
333  {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_RelocNotPICBit, },
334  {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_RelocPICBit, },
335  {Feature_HasMips2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
336  {Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, },
337  {Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
338  {Feature_HasMips32r6Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
339  {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
340  {Feature_HasMips64r2Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, },
341  {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
342  {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, },
343  {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_UseAbsBit, },
344  {Feature_HasMips2Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
345  {Feature_HasMips2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, },
346  {Feature_HasMips32Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
347  {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
348  {Feature_HasMips64Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips64r6Bit, },
349  {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_UseAbsBit, },
350  {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_UseAbsBit, },
351  {Feature_HasMadd4Bit, Feature_InMicroMipsBit, Feature_InMicroMipsBit, Feature_NoNaNsFPMathBit, Feature_NotMips32r6Bit, Feature_NotMips32r6Bit, },
352  {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
353  {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
354  {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
355  {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
356  {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_NoNaNsFPMathBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
357  {Feature_HasMadd4Bit, Feature_InMicroMipsBit, Feature_InMicroMipsBit, Feature_NoNaNsFPMathBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, Feature_NotMips32r6Bit, },
358  {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
359  {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NoNaNsFPMathBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
360  {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
361  {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_NoNaNsFPMathBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
362};
363
364// ComplexPattern predicates.
365enum {
366  GICP_Invalid,
367};
368// See constructor for table contents
369
370// PatFrag predicates.
371enum {
372  GIPFP_I64_Predicate_immLi16 = GIPFP_I64_Invalid + 1,
373  GIPFP_I64_Predicate_immSExt10,
374  GIPFP_I64_Predicate_immSExt6,
375  GIPFP_I64_Predicate_immSExtAddiur2,
376  GIPFP_I64_Predicate_immSExtAddius5,
377  GIPFP_I64_Predicate_immZExt1,
378  GIPFP_I64_Predicate_immZExt10,
379  GIPFP_I64_Predicate_immZExt1Ptr,
380  GIPFP_I64_Predicate_immZExt2,
381  GIPFP_I64_Predicate_immZExt2Lsa,
382  GIPFP_I64_Predicate_immZExt2Ptr,
383  GIPFP_I64_Predicate_immZExt2Shift,
384  GIPFP_I64_Predicate_immZExt3,
385  GIPFP_I64_Predicate_immZExt3Ptr,
386  GIPFP_I64_Predicate_immZExt4,
387  GIPFP_I64_Predicate_immZExt4Ptr,
388  GIPFP_I64_Predicate_immZExt5,
389  GIPFP_I64_Predicate_immZExt5_64,
390  GIPFP_I64_Predicate_immZExt6,
391  GIPFP_I64_Predicate_immZExt8,
392  GIPFP_I64_Predicate_immZExtAndi16,
393  GIPFP_I64_Predicate_immi32Cst15,
394  GIPFP_I64_Predicate_immi32Cst31,
395  GIPFP_I64_Predicate_immi32Cst7,
396  GIPFP_I64_Predicate_timmSExt6,
397  GIPFP_I64_Predicate_timmZExt1,
398  GIPFP_I64_Predicate_timmZExt10,
399  GIPFP_I64_Predicate_timmZExt1Ptr,
400  GIPFP_I64_Predicate_timmZExt2,
401  GIPFP_I64_Predicate_timmZExt2Ptr,
402  GIPFP_I64_Predicate_timmZExt3,
403  GIPFP_I64_Predicate_timmZExt3Ptr,
404  GIPFP_I64_Predicate_timmZExt4,
405  GIPFP_I64_Predicate_timmZExt4Ptr,
406  GIPFP_I64_Predicate_timmZExt5,
407  GIPFP_I64_Predicate_timmZExt6,
408  GIPFP_I64_Predicate_timmZExt8,
409};
410bool MipsInstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const {
411  switch (PredicateID) {
412  case GIPFP_I64_Predicate_immLi16: {
413    return Imm >= -1 && Imm <= 126;
414    llvm_unreachable("ImmediateCode should have returned");
415    return false;
416  }
417  case GIPFP_I64_Predicate_immSExt10: {
418    return isInt<10>(Imm);
419    llvm_unreachable("ImmediateCode should have returned");
420    return false;
421  }
422  case GIPFP_I64_Predicate_immSExt6: {
423    return isInt<6>(Imm);
424    llvm_unreachable("ImmediateCode should have returned");
425    return false;
426  }
427  case GIPFP_I64_Predicate_immSExtAddiur2: {
428    return Imm == 1 || Imm == -1 ||
429                                           ((Imm % 4 == 0) &&
430                                            Imm < 28 && Imm > 0);
431    llvm_unreachable("ImmediateCode should have returned");
432    return false;
433  }
434  case GIPFP_I64_Predicate_immSExtAddius5: {
435    return Imm >= -8 && Imm <= 7;
436    llvm_unreachable("ImmediateCode should have returned");
437    return false;
438  }
439  case GIPFP_I64_Predicate_immZExt1: {
440    return isUInt<1>(Imm);
441    llvm_unreachable("ImmediateCode should have returned");
442    return false;
443  }
444  case GIPFP_I64_Predicate_immZExt10: {
445    return isUInt<10>(Imm);
446    llvm_unreachable("ImmediateCode should have returned");
447    return false;
448  }
449  case GIPFP_I64_Predicate_immZExt1Ptr: {
450    return isUInt<1>(Imm);
451    llvm_unreachable("ImmediateCode should have returned");
452    return false;
453  }
454  case GIPFP_I64_Predicate_immZExt2: {
455    return isUInt<2>(Imm);
456    llvm_unreachable("ImmediateCode should have returned");
457    return false;
458  }
459  case GIPFP_I64_Predicate_immZExt2Lsa: {
460    return isUInt<2>(Imm - 1);
461    llvm_unreachable("ImmediateCode should have returned");
462    return false;
463  }
464  case GIPFP_I64_Predicate_immZExt2Ptr: {
465    return isUInt<2>(Imm);
466    llvm_unreachable("ImmediateCode should have returned");
467    return false;
468  }
469  case GIPFP_I64_Predicate_immZExt2Shift: {
470    return Imm >= 1 && Imm <= 8;
471    llvm_unreachable("ImmediateCode should have returned");
472    return false;
473  }
474  case GIPFP_I64_Predicate_immZExt3: {
475    return isUInt<3>(Imm);
476    llvm_unreachable("ImmediateCode should have returned");
477    return false;
478  }
479  case GIPFP_I64_Predicate_immZExt3Ptr: {
480    return isUInt<3>(Imm);
481    llvm_unreachable("ImmediateCode should have returned");
482    return false;
483  }
484  case GIPFP_I64_Predicate_immZExt4: {
485    return isUInt<4>(Imm);
486    llvm_unreachable("ImmediateCode should have returned");
487    return false;
488  }
489  case GIPFP_I64_Predicate_immZExt4Ptr: {
490    return isUInt<4>(Imm);
491    llvm_unreachable("ImmediateCode should have returned");
492    return false;
493  }
494  case GIPFP_I64_Predicate_immZExt5: {
495    return Imm == (Imm & 0x1f);
496    llvm_unreachable("ImmediateCode should have returned");
497    return false;
498  }
499  case GIPFP_I64_Predicate_immZExt5_64: {
500     return Imm == (Imm & 0x1f);
501    llvm_unreachable("ImmediateCode should have returned");
502    return false;
503  }
504  case GIPFP_I64_Predicate_immZExt6: {
505    return Imm == (Imm & 0x3f);
506    llvm_unreachable("ImmediateCode should have returned");
507    return false;
508  }
509  case GIPFP_I64_Predicate_immZExt8: {
510    return isUInt<8>(Imm);
511    llvm_unreachable("ImmediateCode should have returned");
512    return false;
513  }
514  case GIPFP_I64_Predicate_immZExtAndi16: {
515    return (Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 ||
516            Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 ||
517            Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535 );
518    llvm_unreachable("ImmediateCode should have returned");
519    return false;
520  }
521  case GIPFP_I64_Predicate_immi32Cst15: {
522    return isUInt<32>(Imm) && Imm == 15;
523    llvm_unreachable("ImmediateCode should have returned");
524    return false;
525  }
526  case GIPFP_I64_Predicate_immi32Cst31: {
527    return isUInt<32>(Imm) && Imm == 31;
528    llvm_unreachable("ImmediateCode should have returned");
529    return false;
530  }
531  case GIPFP_I64_Predicate_immi32Cst7: {
532    return isUInt<32>(Imm) && Imm == 7;
533    llvm_unreachable("ImmediateCode should have returned");
534    return false;
535  }
536  case GIPFP_I64_Predicate_timmSExt6: {
537    return isInt<6>(Imm);
538    llvm_unreachable("ImmediateCode should have returned");
539    return false;
540  }
541  case GIPFP_I64_Predicate_timmZExt1: {
542    return isUInt<1>(Imm);
543    llvm_unreachable("ImmediateCode should have returned");
544    return false;
545  }
546  case GIPFP_I64_Predicate_timmZExt10: {
547    return isUInt<10>(Imm);
548    llvm_unreachable("ImmediateCode should have returned");
549    return false;
550  }
551  case GIPFP_I64_Predicate_timmZExt1Ptr: {
552    return isUInt<1>(Imm);
553    llvm_unreachable("ImmediateCode should have returned");
554    return false;
555  }
556  case GIPFP_I64_Predicate_timmZExt2: {
557    return isUInt<2>(Imm);
558    llvm_unreachable("ImmediateCode should have returned");
559    return false;
560  }
561  case GIPFP_I64_Predicate_timmZExt2Ptr: {
562    return isUInt<2>(Imm);
563    llvm_unreachable("ImmediateCode should have returned");
564    return false;
565  }
566  case GIPFP_I64_Predicate_timmZExt3: {
567    return isUInt<3>(Imm);
568    llvm_unreachable("ImmediateCode should have returned");
569    return false;
570  }
571  case GIPFP_I64_Predicate_timmZExt3Ptr: {
572    return isUInt<3>(Imm);
573    llvm_unreachable("ImmediateCode should have returned");
574    return false;
575  }
576  case GIPFP_I64_Predicate_timmZExt4: {
577    return isUInt<4>(Imm);
578    llvm_unreachable("ImmediateCode should have returned");
579    return false;
580  }
581  case GIPFP_I64_Predicate_timmZExt4Ptr: {
582    return isUInt<4>(Imm);
583    llvm_unreachable("ImmediateCode should have returned");
584    return false;
585  }
586  case GIPFP_I64_Predicate_timmZExt5: {
587    return Imm == (Imm & 0x1f);
588    llvm_unreachable("ImmediateCode should have returned");
589    return false;
590  }
591  case GIPFP_I64_Predicate_timmZExt6: {
592    return Imm == (Imm & 0x3f);
593    llvm_unreachable("ImmediateCode should have returned");
594    return false;
595  }
596  case GIPFP_I64_Predicate_timmZExt8: {
597    return isUInt<8>(Imm);
598    llvm_unreachable("ImmediateCode should have returned");
599    return false;
600  }
601  }
602  llvm_unreachable("Unknown predicate");
603  return false;
604}
605bool MipsInstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const {
606  llvm_unreachable("Unknown predicate");
607  return false;
608}
609// PatFrag predicates.
610enum {
611  GIPFP_APInt_Predicate_imm32SExt16 = GIPFP_APInt_Invalid + 1,
612  GIPFP_APInt_Predicate_imm32ZExt16,
613};
614bool MipsInstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const {
615  switch (PredicateID) {
616  case GIPFP_APInt_Predicate_imm32SExt16: {
617     return isInt<16>(Imm.getSExtValue());
618    llvm_unreachable("ImmediateCode should have returned");
619    return false;
620  }
621  case GIPFP_APInt_Predicate_imm32ZExt16: {
622
623  return (uint32_t)Imm.getZExtValue() == (unsigned short)Imm.getZExtValue();
624
625    llvm_unreachable("ImmediateCode should have returned");
626    return false;
627  }
628  }
629  llvm_unreachable("Unknown predicate");
630  return false;
631}
632bool MipsInstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI) const {
633  const MachineFunction &MF = *MI.getParent()->getParent();
634  const MachineRegisterInfo &MRI = MF.getRegInfo();
635  (void)MRI;
636  llvm_unreachable("Unknown predicate");
637  return false;
638}
639
640MipsInstructionSelector::ComplexMatcherMemFn
641MipsInstructionSelector::ComplexPredicateFns[] = {
642  nullptr, // GICP_Invalid
643};
644
645// Custom renderers.
646enum {
647  GICR_Invalid,
648};
649MipsInstructionSelector::CustomRendererFn
650MipsInstructionSelector::CustomRenderers[] = {
651  nullptr, // GICR_Invalid
652};
653
654bool MipsInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const {
655  MachineFunction &MF = *I.getParent()->getParent();
656  MachineRegisterInfo &MRI = MF.getRegInfo();
657  const PredicateBitset AvailableFeatures = getAvailableFeatures();
658  NewMIVector OutMIs;
659  State.MIs.clear();
660  State.MIs.push_back(&I);
661
662  if (executeMatchTable(*this, OutMIs, State, ISelInfo, getMatchTable(), TII, MRI, TRI, RBI, AvailableFeatures, CoverageInfo)) {
663    return true;
664  }
665
666  return false;
667}
668
669const int64_t *MipsInstructionSelector::getMatchTable() const {
670  constexpr static int64_t MatchTable0[] = {
671    GIM_SwitchOpcode, /*MI*/0, /*[*/35, 170, /*)*//*default:*//*Label 55*/ 59850,
672    /*TargetOpcode::G_ADD*//*Label 0*/ 140,
673    /*TargetOpcode::G_SUB*//*Label 1*/ 1360,
674    /*TargetOpcode::G_MUL*//*Label 2*/ 1972,
675    /*TargetOpcode::G_SDIV*//*Label 3*/ 2348,
676    /*TargetOpcode::G_UDIV*//*Label 4*/ 2569,
677    /*TargetOpcode::G_SREM*//*Label 5*/ 2790,
678    /*TargetOpcode::G_UREM*//*Label 6*/ 3011,
679    /*TargetOpcode::G_AND*//*Label 7*/ 3232,
680    /*TargetOpcode::G_OR*//*Label 8*/ 3719,
681    /*TargetOpcode::G_XOR*//*Label 9*/ 4064, 0, 0, 0, 0, 0, 0, 0, 0,
682    /*TargetOpcode::G_BUILD_VECTOR*//*Label 10*/ 4904, 0, 0, 0, 0,
683    /*TargetOpcode::G_BITCAST*//*Label 11*/ 5265, 0, 0, 0,
684    /*TargetOpcode::G_LOAD*//*Label 12*/ 8918,
685    /*TargetOpcode::G_SEXTLOAD*//*Label 13*/ 8984,
686    /*TargetOpcode::G_ZEXTLOAD*//*Label 14*/ 9050, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
687    /*TargetOpcode::G_INTRINSIC*//*Label 15*/ 9116,
688    /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 16*/ 25275,
689    /*TargetOpcode::G_ANYEXT*//*Label 17*/ 30251,
690    /*TargetOpcode::G_TRUNC*//*Label 18*/ 30317,
691    /*TargetOpcode::G_CONSTANT*//*Label 19*/ 30380, 0, 0, 0,
692    /*TargetOpcode::G_SEXT*//*Label 20*/ 30440, 0,
693    /*TargetOpcode::G_ZEXT*//*Label 21*/ 31698,
694    /*TargetOpcode::G_SHL*//*Label 22*/ 31892,
695    /*TargetOpcode::G_LSHR*//*Label 23*/ 33645,
696    /*TargetOpcode::G_ASHR*//*Label 24*/ 35398,
697    /*TargetOpcode::G_ICMP*//*Label 25*/ 37108,
698    /*TargetOpcode::G_FCMP*//*Label 26*/ 39612,
699    /*TargetOpcode::G_SELECT*//*Label 27*/ 41332, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
700    /*TargetOpcode::G_UMULH*//*Label 28*/ 53612,
701    /*TargetOpcode::G_SMULH*//*Label 29*/ 53699,
702    /*TargetOpcode::G_FADD*//*Label 30*/ 53786,
703    /*TargetOpcode::G_FSUB*//*Label 31*/ 54665,
704    /*TargetOpcode::G_FMUL*//*Label 32*/ 55241,
705    /*TargetOpcode::G_FMA*//*Label 33*/ 55678, 0,
706    /*TargetOpcode::G_FDIV*//*Label 34*/ 55768, 0, 0, 0,
707    /*TargetOpcode::G_FEXP2*//*Label 35*/ 56019, 0,
708    /*TargetOpcode::G_FLOG2*//*Label 36*/ 56077, 0,
709    /*TargetOpcode::G_FNEG*//*Label 37*/ 56135,
710    /*TargetOpcode::G_FPEXT*//*Label 38*/ 57431,
711    /*TargetOpcode::G_FPTRUNC*//*Label 39*/ 57580,
712    /*TargetOpcode::G_FPTOSI*//*Label 40*/ 57708,
713    /*TargetOpcode::G_FPTOUI*//*Label 41*/ 57766,
714    /*TargetOpcode::G_SITOFP*//*Label 42*/ 57824,
715    /*TargetOpcode::G_UITOFP*//*Label 43*/ 57977,
716    /*TargetOpcode::G_FABS*//*Label 44*/ 58035, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
717    /*TargetOpcode::G_SMIN*//*Label 45*/ 58218,
718    /*TargetOpcode::G_SMAX*//*Label 46*/ 58358,
719    /*TargetOpcode::G_UMIN*//*Label 47*/ 58498,
720    /*TargetOpcode::G_UMAX*//*Label 48*/ 58638,
721    /*TargetOpcode::G_BR*//*Label 49*/ 58778, 0, 0, 0, 0, 0, 0,
722    /*TargetOpcode::G_CTLZ*//*Label 50*/ 58863, 0,
723    /*TargetOpcode::G_CTPOP*//*Label 51*/ 59298,
724    /*TargetOpcode::G_BSWAP*//*Label 52*/ 59457, 0, 0, 0, 0,
725    /*TargetOpcode::G_FSQRT*//*Label 53*/ 59609, 0,
726    /*TargetOpcode::G_FRINT*//*Label 54*/ 59792,
727    // Label 0: @140
728    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 64*/ 1359,
729    /*GILLT_s32*//*Label 56*/ 154,
730    /*GILLT_s64*//*Label 57*/ 546,
731    /*GILLT_v2s16*//*Label 58*/ 709,
732    /*GILLT_v2s64*//*Label 59*/ 736,
733    /*GILLT_v4s8*//*Label 60*/ 885,
734    /*GILLT_v4s32*//*Label 61*/ 912,
735    /*GILLT_v8s16*//*Label 62*/ 1061,
736    /*GILLT_v16s8*//*Label 63*/ 1210,
737    // Label 56: @154
738    GIM_Try, /*On fail goto*//*Label 65*/ 545,
739      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
740      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
741      GIM_Try, /*On fail goto*//*Label 66*/ 232, // Rule ID 2348 //
742        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
743        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
744        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
745        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
746        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
747        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
748        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
749        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
750        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
751        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_immZExt2Lsa,
752        // MIs[2] Operand 1
753        // No operand predicates
754        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
755        GIM_CheckIsSafeToFold, /*InsnID*/1,
756        GIM_CheckIsSafeToFold, /*InsnID*/2,
757        // (add:{ *:[i32] } (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa), GPR32Opnd:{ *:[i32] }:$rt)  =>  (LSA:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$sa)
758        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LSA,
759        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
760        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
761        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
762        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
763        GIR_EraseFromParent, /*InsnID*/0,
764        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
765        // GIR_Coverage, 2348,
766        GIR_Done,
767      // Label 66: @232
768      GIM_Try, /*On fail goto*//*Label 67*/ 300, // Rule ID 818 //
769        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
770        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
771        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
772        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
773        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
774        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
775        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
776        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
777        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
778        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
779        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_immZExt2Lsa,
780        // MIs[2] Operand 1
781        // No operand predicates
782        GIM_CheckIsSafeToFold, /*InsnID*/1,
783        GIM_CheckIsSafeToFold, /*InsnID*/2,
784        // (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa))  =>  (LSA:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$sa)
785        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LSA,
786        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
787        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
788        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt
789        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
790        GIR_EraseFromParent, /*InsnID*/0,
791        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
792        // GIR_Coverage, 818,
793        GIR_Done,
794      // Label 67: @300
795      GIM_Try, /*On fail goto*//*Label 68*/ 343, // Rule ID 40 //
796        GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
797        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
798        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
799        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
800        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
801        GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIPFP_APInt_Predicate_imm32SExt16,
802        // MIs[1] Operand 1
803        // No operand predicates
804        GIM_CheckIsSafeToFold, /*InsnID*/1,
805        // (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm16)  =>  (ADDiu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$imm16)
806        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDiu,
807        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
808        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
809        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16
810        GIR_EraseFromParent, /*InsnID*/0,
811        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
812        // GIR_Coverage, 40,
813        GIR_Done,
814      // Label 68: @343
815      GIM_Try, /*On fail goto*//*Label 69*/ 386, // Rule ID 2117 //
816        GIM_CheckFeatures, GIFBS_InMicroMips,
817        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
818        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
819        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
820        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
821        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immSExtAddiur2,
822        // MIs[1] Operand 1
823        // No operand predicates
824        GIM_CheckIsSafeToFold, /*InsnID*/1,
825        // (add:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddiur2>>:$imm)  =>  (ADDIUR2_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddiur2>>:$imm)
826        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDIUR2_MM,
827        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
828        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
829        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
830        GIR_EraseFromParent, /*InsnID*/0,
831        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
832        // GIR_Coverage, 2117,
833        GIR_Done,
834      // Label 69: @386
835      GIM_Try, /*On fail goto*//*Label 70*/ 429, // Rule ID 2118 //
836        GIM_CheckFeatures, GIFBS_InMicroMips,
837        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
838        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
839        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
840        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
841        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immSExtAddius5,
842        // MIs[1] Operand 1
843        // No operand predicates
844        GIM_CheckIsSafeToFold, /*InsnID*/1,
845        // (add:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddius5>>:$imm)  =>  (ADDIUS5_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddius5>>:$imm)
846        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDIUS5_MM,
847        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
848        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
849        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
850        GIR_EraseFromParent, /*InsnID*/0,
851        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
852        // GIR_Coverage, 2118,
853        GIR_Done,
854      // Label 70: @429
855      GIM_Try, /*On fail goto*//*Label 71*/ 452, // Rule ID 1190 //
856        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
857        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
858        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
859        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID,
860        // (add:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)  =>  (ADDU16_MMR6:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
861        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDU16_MMR6,
862        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
863        // GIR_Coverage, 1190,
864        GIR_Done,
865      // Label 71: @452
866      GIM_Try, /*On fail goto*//*Label 72*/ 475, // Rule ID 46 //
867        GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
868        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
869        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
870        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
871        // (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (ADDu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
872        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDu,
873        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
874        // GIR_Coverage, 46,
875        GIR_Done,
876      // Label 72: @475
877      GIM_Try, /*On fail goto*//*Label 73*/ 498, // Rule ID 1044 //
878        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
879        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
880        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
881        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID,
882        // (add:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)  =>  (ADDU16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
883        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDU16_MM,
884        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
885        // GIR_Coverage, 1044,
886        GIR_Done,
887      // Label 73: @498
888      GIM_Try, /*On fail goto*//*Label 74*/ 521, // Rule ID 1056 //
889        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
890        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
891        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
892        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
893        // (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (ADDu_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
894        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDu_MM,
895        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
896        // GIR_Coverage, 1056,
897        GIR_Done,
898      // Label 74: @521
899      GIM_Try, /*On fail goto*//*Label 75*/ 544, // Rule ID 1777 //
900        GIM_CheckFeatures, GIFBS_InMips16Mode,
901        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
902        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
903        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
904        // (add:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)  =>  (AdduRxRyRz16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
905        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AdduRxRyRz16,
906        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
907        // GIR_Coverage, 1777,
908        GIR_Done,
909      // Label 75: @544
910      GIM_Reject,
911    // Label 65: @545
912    GIM_Reject,
913    // Label 57: @546
914    GIM_Try, /*On fail goto*//*Label 76*/ 708,
915      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
916      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
917      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
918      GIM_Try, /*On fail goto*//*Label 77*/ 624, // Rule ID 2349 //
919        GIM_CheckFeatures, GIFBS_HasMSA_HasMips64_HasStdEnc,
920        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
921        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
922        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
923        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
924        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
925        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
926        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
927        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_immZExt2Lsa,
928        // MIs[2] Operand 1
929        // No operand predicates
930        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
931        GIM_CheckIsSafeToFold, /*InsnID*/1,
932        GIM_CheckIsSafeToFold, /*InsnID*/2,
933        // (add:{ *:[i64] } (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa), GPR64Opnd:{ *:[i64] }:$rt)  =>  (DLSA:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$sa)
934        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DLSA,
935        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
936        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
937        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
938        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
939        GIR_EraseFromParent, /*InsnID*/0,
940        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
941        // GIR_Coverage, 2349,
942        GIR_Done,
943      // Label 77: @624
944      GIM_Try, /*On fail goto*//*Label 78*/ 688, // Rule ID 819 //
945        GIM_CheckFeatures, GIFBS_HasMSA_HasMips64_HasStdEnc,
946        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
947        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
948        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
949        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
950        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
951        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
952        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
953        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
954        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_immZExt2Lsa,
955        // MIs[2] Operand 1
956        // No operand predicates
957        GIM_CheckIsSafeToFold, /*InsnID*/1,
958        GIM_CheckIsSafeToFold, /*InsnID*/2,
959        // (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa))  =>  (DLSA:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$sa)
960        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DLSA,
961        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
962        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
963        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt
964        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
965        GIR_EraseFromParent, /*InsnID*/0,
966        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
967        // GIR_Coverage, 819,
968        GIR_Done,
969      // Label 78: @688
970      GIM_Try, /*On fail goto*//*Label 79*/ 707, // Rule ID 196 //
971        GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_NotInMicroMips,
972        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
973        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
974        // (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DADDu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
975        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DADDu,
976        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
977        // GIR_Coverage, 196,
978        GIR_Done,
979      // Label 79: @707
980      GIM_Reject,
981    // Label 76: @708
982    GIM_Reject,
983    // Label 58: @709
984    GIM_Try, /*On fail goto*//*Label 80*/ 735, // Rule ID 1876 //
985      GIM_CheckFeatures, GIFBS_HasDSP,
986      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
987      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
988      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
989      // (add:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)  =>  (ADDQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
990      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDQ_PH,
991      GIR_AddImplicitDef, /*InsnID*/0, Mips::DSPOutFlag20,
992      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
993      // GIR_Coverage, 1876,
994      GIR_Done,
995    // Label 80: @735
996    GIM_Reject,
997    // Label 59: @736
998    GIM_Try, /*On fail goto*//*Label 81*/ 884,
999      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1000      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
1001      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
1002      GIM_Try, /*On fail goto*//*Label 82*/ 807, // Rule ID 2353 //
1003        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1004        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1005        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1006        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
1007        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
1008        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
1009        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
1010        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
1011        GIM_CheckIsSafeToFold, /*InsnID*/1,
1012        // (add:{ *:[v2i64] } (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt), MSA128DOpnd:{ *:[v2i64] }:$wd_in)  =>  (MADDV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1013        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_D,
1014        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
1015        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
1016        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1017        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1018        GIR_EraseFromParent, /*InsnID*/0,
1019        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1020        // GIR_Coverage, 2353,
1021        GIR_Done,
1022      // Label 82: @807
1023      GIM_Try, /*On fail goto*//*Label 83*/ 864, // Rule ID 827 //
1024        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1025        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
1026        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1027        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1028        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
1029        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
1030        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
1031        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
1032        GIM_CheckIsSafeToFold, /*InsnID*/1,
1033        // (add:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt))  =>  (MADDV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1034        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_D,
1035        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
1036        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
1037        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1038        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1039        GIR_EraseFromParent, /*InsnID*/0,
1040        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1041        // GIR_Coverage, 827,
1042        GIR_Done,
1043      // Label 83: @864
1044      GIM_Try, /*On fail goto*//*Label 84*/ 883, // Rule ID 494 //
1045        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1046        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
1047        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
1048        // (add:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (ADDV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1049        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDV_D,
1050        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1051        // GIR_Coverage, 494,
1052        GIR_Done,
1053      // Label 84: @883
1054      GIM_Reject,
1055    // Label 81: @884
1056    GIM_Reject,
1057    // Label 60: @885
1058    GIM_Try, /*On fail goto*//*Label 85*/ 911, // Rule ID 1882 //
1059      GIM_CheckFeatures, GIFBS_HasDSP,
1060      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8,
1061      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
1062      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
1063      // (add:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)  =>  (ADDU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)
1064      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDU_QB,
1065      GIR_AddImplicitDef, /*InsnID*/0, Mips::DSPOutFlag20,
1066      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1067      // GIR_Coverage, 1882,
1068      GIR_Done,
1069    // Label 85: @911
1070    GIM_Reject,
1071    // Label 61: @912
1072    GIM_Try, /*On fail goto*//*Label 86*/ 1060,
1073      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1074      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
1075      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
1076      GIM_Try, /*On fail goto*//*Label 87*/ 983, // Rule ID 2352 //
1077        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1078        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1079        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1080        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
1081        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1082        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
1083        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
1084        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
1085        GIM_CheckIsSafeToFold, /*InsnID*/1,
1086        // (add:{ *:[v4i32] } (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt), MSA128WOpnd:{ *:[v4i32] }:$wd_in)  =>  (MADDV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1087        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_W,
1088        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
1089        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
1090        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1091        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1092        GIR_EraseFromParent, /*InsnID*/0,
1093        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1094        // GIR_Coverage, 2352,
1095        GIR_Done,
1096      // Label 87: @983
1097      GIM_Try, /*On fail goto*//*Label 88*/ 1040, // Rule ID 826 //
1098        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1099        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
1100        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1101        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1102        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
1103        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1104        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
1105        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
1106        GIM_CheckIsSafeToFold, /*InsnID*/1,
1107        // (add:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt))  =>  (MADDV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1108        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_W,
1109        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
1110        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
1111        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1112        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1113        GIR_EraseFromParent, /*InsnID*/0,
1114        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1115        // GIR_Coverage, 826,
1116        GIR_Done,
1117      // Label 88: @1040
1118      GIM_Try, /*On fail goto*//*Label 89*/ 1059, // Rule ID 493 //
1119        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1120        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
1121        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
1122        // (add:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (ADDV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1123        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDV_W,
1124        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1125        // GIR_Coverage, 493,
1126        GIR_Done,
1127      // Label 89: @1059
1128      GIM_Reject,
1129    // Label 86: @1060
1130    GIM_Reject,
1131    // Label 62: @1061
1132    GIM_Try, /*On fail goto*//*Label 90*/ 1209,
1133      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
1134      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
1135      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
1136      GIM_Try, /*On fail goto*//*Label 91*/ 1132, // Rule ID 2351 //
1137        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1138        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1139        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1140        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
1141        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
1142        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1143        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1144        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1145        GIM_CheckIsSafeToFold, /*InsnID*/1,
1146        // (add:{ *:[v8i16] } (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt), MSA128HOpnd:{ *:[v8i16] }:$wd_in)  =>  (MADDV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1147        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_H,
1148        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
1149        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
1150        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1151        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1152        GIR_EraseFromParent, /*InsnID*/0,
1153        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1154        // GIR_Coverage, 2351,
1155        GIR_Done,
1156      // Label 91: @1132
1157      GIM_Try, /*On fail goto*//*Label 92*/ 1189, // Rule ID 825 //
1158        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1159        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1160        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1161        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1162        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
1163        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
1164        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1165        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1166        GIM_CheckIsSafeToFold, /*InsnID*/1,
1167        // (add:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt))  =>  (MADDV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1168        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_H,
1169        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
1170        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
1171        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1172        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1173        GIR_EraseFromParent, /*InsnID*/0,
1174        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1175        // GIR_Coverage, 825,
1176        GIR_Done,
1177      // Label 92: @1189
1178      GIM_Try, /*On fail goto*//*Label 93*/ 1208, // Rule ID 492 //
1179        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1180        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1181        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1182        // (add:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (ADDV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1183        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDV_H,
1184        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1185        // GIR_Coverage, 492,
1186        GIR_Done,
1187      // Label 93: @1208
1188      GIM_Reject,
1189    // Label 90: @1209
1190    GIM_Reject,
1191    // Label 63: @1210
1192    GIM_Try, /*On fail goto*//*Label 94*/ 1358,
1193      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
1194      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
1195      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
1196      GIM_Try, /*On fail goto*//*Label 95*/ 1281, // Rule ID 2350 //
1197        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1198        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1199        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1200        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
1201        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
1202        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1203        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1204        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1205        GIM_CheckIsSafeToFold, /*InsnID*/1,
1206        // (add:{ *:[v16i8] } (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt), MSA128BOpnd:{ *:[v16i8] }:$wd_in)  =>  (MADDV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1207        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_B,
1208        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
1209        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
1210        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1211        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1212        GIR_EraseFromParent, /*InsnID*/0,
1213        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1214        // GIR_Coverage, 2350,
1215        GIR_Done,
1216      // Label 95: @1281
1217      GIM_Try, /*On fail goto*//*Label 96*/ 1338, // Rule ID 824 //
1218        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1219        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1220        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1221        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1222        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
1223        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
1224        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1225        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1226        GIM_CheckIsSafeToFold, /*InsnID*/1,
1227        // (add:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt))  =>  (MADDV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1228        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_B,
1229        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
1230        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
1231        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1232        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1233        GIR_EraseFromParent, /*InsnID*/0,
1234        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1235        // GIR_Coverage, 824,
1236        GIR_Done,
1237      // Label 96: @1338
1238      GIM_Try, /*On fail goto*//*Label 97*/ 1357, // Rule ID 491 //
1239        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1240        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1241        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1242        // (add:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (ADDV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1243        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDV_B,
1244        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1245        // GIR_Coverage, 491,
1246        GIR_Done,
1247      // Label 97: @1357
1248      GIM_Reject,
1249    // Label 94: @1358
1250    GIM_Reject,
1251    // Label 64: @1359
1252    GIM_Reject,
1253    // Label 1: @1360
1254    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 106*/ 1971,
1255    /*GILLT_s32*//*Label 98*/ 1374,
1256    /*GILLT_s64*//*Label 99*/ 1533,
1257    /*GILLT_v2s16*//*Label 100*/ 1565,
1258    /*GILLT_v2s64*//*Label 101*/ 1592,
1259    /*GILLT_v4s8*//*Label 102*/ 1680,
1260    /*GILLT_v4s32*//*Label 103*/ 1707,
1261    /*GILLT_v8s16*//*Label 104*/ 1795,
1262    /*GILLT_v16s8*//*Label 105*/ 1883,
1263    // Label 98: @1374
1264    GIM_Try, /*On fail goto*//*Label 107*/ 1532,
1265      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1266      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
1267      GIM_Try, /*On fail goto*//*Label 108*/ 1416, // Rule ID 1776 //
1268        GIM_CheckFeatures, GIFBS_InMips16Mode,
1269        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
1270        GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0,
1271        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
1272        // (sub:{ *:[i32] } 0:{ *:[i32] }, CPU16Regs:{ *:[i32] }:$r)  =>  (NegRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r)
1273        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NegRxRy16,
1274        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rx
1275        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // r
1276        GIR_EraseFromParent, /*InsnID*/0,
1277        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1278        // GIR_Coverage, 1776,
1279        GIR_Done,
1280      // Label 108: @1416
1281      GIM_Try, /*On fail goto*//*Label 109*/ 1439, // Rule ID 1192 //
1282        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
1283        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
1284        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
1285        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID,
1286        // (sub:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)  =>  (SUBU16_MMR6:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
1287        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBU16_MMR6,
1288        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1289        // GIR_Coverage, 1192,
1290        GIR_Done,
1291      // Label 109: @1439
1292      GIM_Try, /*On fail goto*//*Label 110*/ 1462, // Rule ID 47 //
1293        GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
1294        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1295        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1296        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1297        // (sub:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (SUBu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1298        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBu,
1299        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1300        // GIR_Coverage, 47,
1301        GIR_Done,
1302      // Label 110: @1462
1303      GIM_Try, /*On fail goto*//*Label 111*/ 1485, // Rule ID 1048 //
1304        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
1305        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
1306        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
1307        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID,
1308        // (sub:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)  =>  (SUBU16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
1309        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBU16_MM,
1310        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1311        // GIR_Coverage, 1048,
1312        GIR_Done,
1313      // Label 111: @1485
1314      GIM_Try, /*On fail goto*//*Label 112*/ 1508, // Rule ID 1057 //
1315        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
1316        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1317        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1318        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1319        // (sub:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (SUBu_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1320        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBu_MM,
1321        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1322        // GIR_Coverage, 1057,
1323        GIR_Done,
1324      // Label 112: @1508
1325      GIM_Try, /*On fail goto*//*Label 113*/ 1531, // Rule ID 1781 //
1326        GIM_CheckFeatures, GIFBS_InMips16Mode,
1327        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
1328        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
1329        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
1330        // (sub:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)  =>  (SubuRxRyRz16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
1331        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SubuRxRyRz16,
1332        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1333        // GIR_Coverage, 1781,
1334        GIR_Done,
1335      // Label 113: @1531
1336      GIM_Reject,
1337    // Label 107: @1532
1338    GIM_Reject,
1339    // Label 99: @1533
1340    GIM_Try, /*On fail goto*//*Label 114*/ 1564, // Rule ID 197 //
1341      GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_NotInMicroMips,
1342      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1343      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
1344      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
1345      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
1346      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
1347      // (sub:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DSUBu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1348      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DSUBu,
1349      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1350      // GIR_Coverage, 197,
1351      GIR_Done,
1352    // Label 114: @1564
1353    GIM_Reject,
1354    // Label 100: @1565
1355    GIM_Try, /*On fail goto*//*Label 115*/ 1591, // Rule ID 1878 //
1356      GIM_CheckFeatures, GIFBS_HasDSP,
1357      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
1358      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
1359      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
1360      // (sub:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)  =>  (SUBQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
1361      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBQ_PH,
1362      GIR_AddImplicitDef, /*InsnID*/0, Mips::DSPOutFlag20,
1363      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1364      // GIR_Coverage, 1878,
1365      GIR_Done,
1366    // Label 115: @1591
1367    GIM_Reject,
1368    // Label 101: @1592
1369    GIM_Try, /*On fail goto*//*Label 116*/ 1679,
1370      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1371      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
1372      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
1373      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
1374      GIM_Try, /*On fail goto*//*Label 117*/ 1663, // Rule ID 883 //
1375        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1376        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1377        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1378        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
1379        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
1380        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
1381        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
1382        GIM_CheckIsSafeToFold, /*InsnID*/1,
1383        // (sub:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt))  =>  (MSUBV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1384        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBV_D,
1385        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
1386        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
1387        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1388        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1389        GIR_EraseFromParent, /*InsnID*/0,
1390        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1391        // GIR_Coverage, 883,
1392        GIR_Done,
1393      // Label 117: @1663
1394      GIM_Try, /*On fail goto*//*Label 118*/ 1678, // Rule ID 1012 //
1395        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1396        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
1397        // (sub:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (SUBV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1398        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBV_D,
1399        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1400        // GIR_Coverage, 1012,
1401        GIR_Done,
1402      // Label 118: @1678
1403      GIM_Reject,
1404    // Label 116: @1679
1405    GIM_Reject,
1406    // Label 102: @1680
1407    GIM_Try, /*On fail goto*//*Label 119*/ 1706, // Rule ID 1884 //
1408      GIM_CheckFeatures, GIFBS_HasDSP,
1409      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8,
1410      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
1411      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
1412      // (sub:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)  =>  (SUBU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)
1413      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBU_QB,
1414      GIR_AddImplicitDef, /*InsnID*/0, Mips::DSPOutFlag20,
1415      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1416      // GIR_Coverage, 1884,
1417      GIR_Done,
1418    // Label 119: @1706
1419    GIM_Reject,
1420    // Label 103: @1707
1421    GIM_Try, /*On fail goto*//*Label 120*/ 1794,
1422      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1423      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
1424      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
1425      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
1426      GIM_Try, /*On fail goto*//*Label 121*/ 1778, // Rule ID 882 //
1427        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1428        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1429        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1430        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
1431        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1432        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
1433        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
1434        GIM_CheckIsSafeToFold, /*InsnID*/1,
1435        // (sub:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt))  =>  (MSUBV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1436        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBV_W,
1437        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
1438        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
1439        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1440        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1441        GIR_EraseFromParent, /*InsnID*/0,
1442        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1443        // GIR_Coverage, 882,
1444        GIR_Done,
1445      // Label 121: @1778
1446      GIM_Try, /*On fail goto*//*Label 122*/ 1793, // Rule ID 1011 //
1447        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1448        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
1449        // (sub:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (SUBV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1450        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBV_W,
1451        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1452        // GIR_Coverage, 1011,
1453        GIR_Done,
1454      // Label 122: @1793
1455      GIM_Reject,
1456    // Label 120: @1794
1457    GIM_Reject,
1458    // Label 104: @1795
1459    GIM_Try, /*On fail goto*//*Label 123*/ 1882,
1460      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
1461      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
1462      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
1463      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1464      GIM_Try, /*On fail goto*//*Label 124*/ 1866, // Rule ID 881 //
1465        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1466        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1467        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1468        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
1469        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
1470        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1471        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1472        GIM_CheckIsSafeToFold, /*InsnID*/1,
1473        // (sub:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt))  =>  (MSUBV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1474        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBV_H,
1475        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
1476        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
1477        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1478        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1479        GIR_EraseFromParent, /*InsnID*/0,
1480        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1481        // GIR_Coverage, 881,
1482        GIR_Done,
1483      // Label 124: @1866
1484      GIM_Try, /*On fail goto*//*Label 125*/ 1881, // Rule ID 1010 //
1485        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1486        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1487        // (sub:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (SUBV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1488        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBV_H,
1489        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1490        // GIR_Coverage, 1010,
1491        GIR_Done,
1492      // Label 125: @1881
1493      GIM_Reject,
1494    // Label 123: @1882
1495    GIM_Reject,
1496    // Label 105: @1883
1497    GIM_Try, /*On fail goto*//*Label 126*/ 1970,
1498      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
1499      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
1500      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
1501      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1502      GIM_Try, /*On fail goto*//*Label 127*/ 1954, // Rule ID 880 //
1503        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1504        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1505        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1506        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
1507        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
1508        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1509        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1510        GIM_CheckIsSafeToFold, /*InsnID*/1,
1511        // (sub:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt))  =>  (MSUBV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1512        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBV_B,
1513        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
1514        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
1515        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1516        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1517        GIR_EraseFromParent, /*InsnID*/0,
1518        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1519        // GIR_Coverage, 880,
1520        GIR_Done,
1521      // Label 127: @1954
1522      GIM_Try, /*On fail goto*//*Label 128*/ 1969, // Rule ID 1009 //
1523        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1524        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1525        // (sub:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (SUBV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1526        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBV_B,
1527        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1528        // GIR_Coverage, 1009,
1529        GIR_Done,
1530      // Label 128: @1969
1531      GIM_Reject,
1532    // Label 126: @1970
1533    GIM_Reject,
1534    // Label 106: @1971
1535    GIM_Reject,
1536    // Label 2: @1972
1537    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 136*/ 2347,
1538    /*GILLT_s32*//*Label 129*/ 1986,
1539    /*GILLT_s64*//*Label 130*/ 2131,
1540    /*GILLT_v2s16*//*Label 131*/ 2192,
1541    /*GILLT_v2s64*//*Label 132*/ 2219, 0,
1542    /*GILLT_v4s32*//*Label 133*/ 2251,
1543    /*GILLT_v8s16*//*Label 134*/ 2283,
1544    /*GILLT_v16s8*//*Label 135*/ 2315,
1545    // Label 129: @1986
1546    GIM_Try, /*On fail goto*//*Label 137*/ 2130,
1547      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1548      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
1549      GIM_Try, /*On fail goto*//*Label 138*/ 2025, // Rule ID 48 //
1550        GIM_CheckFeatures, GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
1551        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1552        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1553        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1554        // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MUL:{ *:[i32] }:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1555        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUL,
1556        GIR_AddImplicitDef, /*InsnID*/0, Mips::HI0,
1557        GIR_AddImplicitDef, /*InsnID*/0, Mips::LO0,
1558        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1559        // GIR_Coverage, 48,
1560        GIR_Done,
1561      // Label 138: @2025
1562      GIM_Try, /*On fail goto*//*Label 139*/ 2048, // Rule ID 320 //
1563        GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
1564        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1565        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1566        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1567        // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MUL_R6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1568        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUL_R6,
1569        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1570        // GIR_Coverage, 320,
1571        GIR_Done,
1572      // Label 139: @2048
1573      GIM_Try, /*On fail goto*//*Label 140*/ 2077, // Rule ID 1058 //
1574        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
1575        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1576        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1577        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1578        // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MUL_MM:{ *:[i32] }:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1579        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUL_MM,
1580        GIR_AddImplicitDef, /*InsnID*/0, Mips::HI0,
1581        GIR_AddImplicitDef, /*InsnID*/0, Mips::LO0,
1582        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1583        // GIR_Coverage, 1058,
1584        GIR_Done,
1585      // Label 140: @2077
1586      GIM_Try, /*On fail goto*//*Label 141*/ 2100, // Rule ID 1161 //
1587        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
1588        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1589        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1590        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1591        // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MUL_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1592        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUL_MMR6,
1593        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1594        // GIR_Coverage, 1161,
1595        GIR_Done,
1596      // Label 141: @2100
1597      GIM_Try, /*On fail goto*//*Label 142*/ 2129, // Rule ID 1779 //
1598        GIM_CheckFeatures, GIFBS_InMips16Mode,
1599        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
1600        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
1601        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
1602        // (mul:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)  =>  (MultRxRyRz16:{ *:[i32] }:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
1603        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MultRxRyRz16,
1604        GIR_AddImplicitDef, /*InsnID*/0, Mips::HI0,
1605        GIR_AddImplicitDef, /*InsnID*/0, Mips::LO0,
1606        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1607        // GIR_Coverage, 1779,
1608        GIR_Done,
1609      // Label 142: @2129
1610      GIM_Reject,
1611    // Label 137: @2130
1612    GIM_Reject,
1613    // Label 130: @2131
1614    GIM_Try, /*On fail goto*//*Label 143*/ 2191,
1615      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1616      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
1617      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
1618      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
1619      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
1620      GIM_Try, /*On fail goto*//*Label 144*/ 2179, // Rule ID 262 //
1621        GIM_CheckFeatures, GIFBS_HasCnMips,
1622        // (mul:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DMUL:{ *:[i64] }:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1623        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMUL,
1624        GIR_AddImplicitDef, /*InsnID*/0, Mips::HI0,
1625        GIR_AddImplicitDef, /*InsnID*/0, Mips::LO0,
1626        GIR_AddImplicitDef, /*InsnID*/0, Mips::P0,
1627        GIR_AddImplicitDef, /*InsnID*/0, Mips::P1,
1628        GIR_AddImplicitDef, /*InsnID*/0, Mips::P2,
1629        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1630        // GIR_Coverage, 262,
1631        GIR_Done,
1632      // Label 144: @2179
1633      GIM_Try, /*On fail goto*//*Label 145*/ 2190, // Rule ID 335 //
1634        GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
1635        // (mul:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DMUL_R6:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1636        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMUL_R6,
1637        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1638        // GIR_Coverage, 335,
1639        GIR_Done,
1640      // Label 145: @2190
1641      GIM_Reject,
1642    // Label 143: @2191
1643    GIM_Reject,
1644    // Label 131: @2192
1645    GIM_Try, /*On fail goto*//*Label 146*/ 2218, // Rule ID 1880 //
1646      GIM_CheckFeatures, GIFBS_HasDSPR2,
1647      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
1648      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
1649      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
1650      // (mul:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)  =>  (MUL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
1651      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUL_PH,
1652      GIR_AddImplicitDef, /*InsnID*/0, Mips::DSPOutFlag21,
1653      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1654      // GIR_Coverage, 1880,
1655      GIR_Done,
1656    // Label 146: @2218
1657    GIM_Reject,
1658    // Label 132: @2219
1659    GIM_Try, /*On fail goto*//*Label 147*/ 2250, // Rule ID 891 //
1660      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1661      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1662      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
1663      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
1664      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
1665      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
1666      // (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (MULV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1667      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MULV_D,
1668      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1669      // GIR_Coverage, 891,
1670      GIR_Done,
1671    // Label 147: @2250
1672    GIM_Reject,
1673    // Label 133: @2251
1674    GIM_Try, /*On fail goto*//*Label 148*/ 2282, // Rule ID 890 //
1675      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1676      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1677      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
1678      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
1679      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
1680      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
1681      // (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (MULV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1682      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MULV_W,
1683      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1684      // GIR_Coverage, 890,
1685      GIR_Done,
1686    // Label 148: @2282
1687    GIM_Reject,
1688    // Label 134: @2283
1689    GIM_Try, /*On fail goto*//*Label 149*/ 2314, // Rule ID 889 //
1690      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1691      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
1692      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
1693      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
1694      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1695      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1696      // (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (MULV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1697      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MULV_H,
1698      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1699      // GIR_Coverage, 889,
1700      GIR_Done,
1701    // Label 149: @2314
1702    GIM_Reject,
1703    // Label 135: @2315
1704    GIM_Try, /*On fail goto*//*Label 150*/ 2346, // Rule ID 888 //
1705      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1706      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
1707      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
1708      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
1709      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1710      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1711      // (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (MULV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1712      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MULV_B,
1713      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1714      // GIR_Coverage, 888,
1715      GIR_Done,
1716    // Label 150: @2346
1717    GIM_Reject,
1718    // Label 136: @2347
1719    GIM_Reject,
1720    // Label 3: @2348
1721    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 157*/ 2568,
1722    /*GILLT_s32*//*Label 151*/ 2362,
1723    /*GILLT_s64*//*Label 152*/ 2408, 0,
1724    /*GILLT_v2s64*//*Label 153*/ 2440, 0,
1725    /*GILLT_v4s32*//*Label 154*/ 2472,
1726    /*GILLT_v8s16*//*Label 155*/ 2504,
1727    /*GILLT_v16s8*//*Label 156*/ 2536,
1728    // Label 151: @2362
1729    GIM_Try, /*On fail goto*//*Label 158*/ 2407,
1730      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1731      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
1732      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1733      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1734      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1735      GIM_Try, /*On fail goto*//*Label 159*/ 2395, // Rule ID 314 //
1736        GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
1737        // (sdiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (DIV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1738        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV,
1739        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1740        // GIR_Coverage, 314,
1741        GIR_Done,
1742      // Label 159: @2395
1743      GIM_Try, /*On fail goto*//*Label 160*/ 2406, // Rule ID 1154 //
1744        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
1745        // (sdiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (DIV_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1746        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_MMR6,
1747        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1748        // GIR_Coverage, 1154,
1749        GIR_Done,
1750      // Label 160: @2406
1751      GIM_Reject,
1752    // Label 158: @2407
1753    GIM_Reject,
1754    // Label 152: @2408
1755    GIM_Try, /*On fail goto*//*Label 161*/ 2439, // Rule ID 329 //
1756      GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
1757      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1758      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
1759      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
1760      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
1761      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
1762      // (sdiv:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DDIV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1763      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DDIV,
1764      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1765      // GIR_Coverage, 329,
1766      GIR_Done,
1767    // Label 161: @2439
1768    GIM_Reject,
1769    // Label 153: @2440
1770    GIM_Try, /*On fail goto*//*Label 162*/ 2471, // Rule ID 631 //
1771      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1772      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1773      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
1774      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
1775      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
1776      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
1777      // (sdiv:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (DIV_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1778      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_S_D,
1779      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1780      // GIR_Coverage, 631,
1781      GIR_Done,
1782    // Label 162: @2471
1783    GIM_Reject,
1784    // Label 154: @2472
1785    GIM_Try, /*On fail goto*//*Label 163*/ 2503, // Rule ID 630 //
1786      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1787      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1788      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
1789      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
1790      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
1791      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
1792      // (sdiv:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (DIV_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1793      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_S_W,
1794      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1795      // GIR_Coverage, 630,
1796      GIR_Done,
1797    // Label 163: @2503
1798    GIM_Reject,
1799    // Label 155: @2504
1800    GIM_Try, /*On fail goto*//*Label 164*/ 2535, // Rule ID 629 //
1801      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1802      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
1803      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
1804      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
1805      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1806      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1807      // (sdiv:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (DIV_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1808      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_S_H,
1809      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1810      // GIR_Coverage, 629,
1811      GIR_Done,
1812    // Label 164: @2535
1813    GIM_Reject,
1814    // Label 156: @2536
1815    GIM_Try, /*On fail goto*//*Label 165*/ 2567, // Rule ID 628 //
1816      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1817      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
1818      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
1819      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
1820      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1821      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1822      // (sdiv:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (DIV_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1823      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_S_B,
1824      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1825      // GIR_Coverage, 628,
1826      GIR_Done,
1827    // Label 165: @2567
1828    GIM_Reject,
1829    // Label 157: @2568
1830    GIM_Reject,
1831    // Label 4: @2569
1832    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 172*/ 2789,
1833    /*GILLT_s32*//*Label 166*/ 2583,
1834    /*GILLT_s64*//*Label 167*/ 2629, 0,
1835    /*GILLT_v2s64*//*Label 168*/ 2661, 0,
1836    /*GILLT_v4s32*//*Label 169*/ 2693,
1837    /*GILLT_v8s16*//*Label 170*/ 2725,
1838    /*GILLT_v16s8*//*Label 171*/ 2757,
1839    // Label 166: @2583
1840    GIM_Try, /*On fail goto*//*Label 173*/ 2628,
1841      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1842      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
1843      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1844      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1845      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1846      GIM_Try, /*On fail goto*//*Label 174*/ 2616, // Rule ID 315 //
1847        GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
1848        // (udiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (DIVU:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1849        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIVU,
1850        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1851        // GIR_Coverage, 315,
1852        GIR_Done,
1853      // Label 174: @2616
1854      GIM_Try, /*On fail goto*//*Label 175*/ 2627, // Rule ID 1155 //
1855        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
1856        // (udiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (DIVU_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1857        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIVU_MMR6,
1858        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1859        // GIR_Coverage, 1155,
1860        GIR_Done,
1861      // Label 175: @2627
1862      GIM_Reject,
1863    // Label 173: @2628
1864    GIM_Reject,
1865    // Label 167: @2629
1866    GIM_Try, /*On fail goto*//*Label 176*/ 2660, // Rule ID 330 //
1867      GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
1868      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1869      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
1870      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
1871      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
1872      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
1873      // (udiv:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DDIVU:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1874      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DDIVU,
1875      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1876      // GIR_Coverage, 330,
1877      GIR_Done,
1878    // Label 176: @2660
1879    GIM_Reject,
1880    // Label 168: @2661
1881    GIM_Try, /*On fail goto*//*Label 177*/ 2692, // Rule ID 635 //
1882      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1883      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1884      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
1885      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
1886      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
1887      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
1888      // (udiv:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (DIV_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1889      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_U_D,
1890      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1891      // GIR_Coverage, 635,
1892      GIR_Done,
1893    // Label 177: @2692
1894    GIM_Reject,
1895    // Label 169: @2693
1896    GIM_Try, /*On fail goto*//*Label 178*/ 2724, // Rule ID 634 //
1897      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1898      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1899      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
1900      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
1901      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
1902      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
1903      // (udiv:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (DIV_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1904      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_U_W,
1905      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1906      // GIR_Coverage, 634,
1907      GIR_Done,
1908    // Label 178: @2724
1909    GIM_Reject,
1910    // Label 170: @2725
1911    GIM_Try, /*On fail goto*//*Label 179*/ 2756, // Rule ID 633 //
1912      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1913      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
1914      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
1915      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
1916      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1917      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1918      // (udiv:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (DIV_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1919      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_U_H,
1920      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1921      // GIR_Coverage, 633,
1922      GIR_Done,
1923    // Label 179: @2756
1924    GIM_Reject,
1925    // Label 171: @2757
1926    GIM_Try, /*On fail goto*//*Label 180*/ 2788, // Rule ID 632 //
1927      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1928      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
1929      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
1930      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
1931      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1932      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1933      // (udiv:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (DIV_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1934      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_U_B,
1935      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1936      // GIR_Coverage, 632,
1937      GIR_Done,
1938    // Label 180: @2788
1939    GIM_Reject,
1940    // Label 172: @2789
1941    GIM_Reject,
1942    // Label 5: @2790
1943    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 187*/ 3010,
1944    /*GILLT_s32*//*Label 181*/ 2804,
1945    /*GILLT_s64*//*Label 182*/ 2850, 0,
1946    /*GILLT_v2s64*//*Label 183*/ 2882, 0,
1947    /*GILLT_v4s32*//*Label 184*/ 2914,
1948    /*GILLT_v8s16*//*Label 185*/ 2946,
1949    /*GILLT_v16s8*//*Label 186*/ 2978,
1950    // Label 181: @2804
1951    GIM_Try, /*On fail goto*//*Label 188*/ 2849,
1952      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1953      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
1954      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1955      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1956      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1957      GIM_Try, /*On fail goto*//*Label 189*/ 2837, // Rule ID 316 //
1958        GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
1959        // (srem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MOD:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1960        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD,
1961        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1962        // GIR_Coverage, 316,
1963        GIR_Done,
1964      // Label 189: @2837
1965      GIM_Try, /*On fail goto*//*Label 190*/ 2848, // Rule ID 1159 //
1966        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
1967        // (srem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MOD_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1968        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_MMR6,
1969        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1970        // GIR_Coverage, 1159,
1971        GIR_Done,
1972      // Label 190: @2848
1973      GIM_Reject,
1974    // Label 188: @2849
1975    GIM_Reject,
1976    // Label 182: @2850
1977    GIM_Try, /*On fail goto*//*Label 191*/ 2881, // Rule ID 331 //
1978      GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
1979      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1980      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
1981      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
1982      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
1983      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
1984      // (srem:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DMOD:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1985      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMOD,
1986      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1987      // GIR_Coverage, 331,
1988      GIR_Done,
1989    // Label 191: @2881
1990    GIM_Reject,
1991    // Label 183: @2882
1992    GIM_Try, /*On fail goto*//*Label 192*/ 2913, // Rule ID 871 //
1993      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1994      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1995      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
1996      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
1997      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
1998      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
1999      // (srem:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (MOD_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
2000      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_S_D,
2001      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2002      // GIR_Coverage, 871,
2003      GIR_Done,
2004    // Label 192: @2913
2005    GIM_Reject,
2006    // Label 184: @2914
2007    GIM_Try, /*On fail goto*//*Label 193*/ 2945, // Rule ID 870 //
2008      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2009      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
2010      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
2011      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
2012      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
2013      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
2014      // (srem:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (MOD_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
2015      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_S_W,
2016      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2017      // GIR_Coverage, 870,
2018      GIR_Done,
2019    // Label 193: @2945
2020    GIM_Reject,
2021    // Label 185: @2946
2022    GIM_Try, /*On fail goto*//*Label 194*/ 2977, // Rule ID 869 //
2023      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2024      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
2025      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
2026      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
2027      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
2028      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
2029      // (srem:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (MOD_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
2030      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_S_H,
2031      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2032      // GIR_Coverage, 869,
2033      GIR_Done,
2034    // Label 194: @2977
2035    GIM_Reject,
2036    // Label 186: @2978
2037    GIM_Try, /*On fail goto*//*Label 195*/ 3009, // Rule ID 868 //
2038      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2039      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
2040      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
2041      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
2042      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
2043      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
2044      // (srem:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (MOD_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
2045      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_S_B,
2046      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2047      // GIR_Coverage, 868,
2048      GIR_Done,
2049    // Label 195: @3009
2050    GIM_Reject,
2051    // Label 187: @3010
2052    GIM_Reject,
2053    // Label 6: @3011
2054    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 202*/ 3231,
2055    /*GILLT_s32*//*Label 196*/ 3025,
2056    /*GILLT_s64*//*Label 197*/ 3071, 0,
2057    /*GILLT_v2s64*//*Label 198*/ 3103, 0,
2058    /*GILLT_v4s32*//*Label 199*/ 3135,
2059    /*GILLT_v8s16*//*Label 200*/ 3167,
2060    /*GILLT_v16s8*//*Label 201*/ 3199,
2061    // Label 196: @3025
2062    GIM_Try, /*On fail goto*//*Label 203*/ 3070,
2063      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2064      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2065      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2066      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2067      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2068      GIM_Try, /*On fail goto*//*Label 204*/ 3058, // Rule ID 317 //
2069        GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
2070        // (urem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MODU:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2071        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MODU,
2072        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2073        // GIR_Coverage, 317,
2074        GIR_Done,
2075      // Label 204: @3058
2076      GIM_Try, /*On fail goto*//*Label 205*/ 3069, // Rule ID 1160 //
2077        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
2078        // (urem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MODU_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2079        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MODU_MMR6,
2080        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2081        // GIR_Coverage, 1160,
2082        GIR_Done,
2083      // Label 205: @3069
2084      GIM_Reject,
2085    // Label 203: @3070
2086    GIM_Reject,
2087    // Label 197: @3071
2088    GIM_Try, /*On fail goto*//*Label 206*/ 3102, // Rule ID 332 //
2089      GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
2090      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
2091      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2092      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
2093      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
2094      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
2095      // (urem:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DMODU:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2096      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMODU,
2097      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2098      // GIR_Coverage, 332,
2099      GIR_Done,
2100    // Label 206: @3102
2101    GIM_Reject,
2102    // Label 198: @3103
2103    GIM_Try, /*On fail goto*//*Label 207*/ 3134, // Rule ID 875 //
2104      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2105      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
2106      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
2107      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2108      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
2109      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
2110      // (urem:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (MOD_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
2111      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_U_D,
2112      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2113      // GIR_Coverage, 875,
2114      GIR_Done,
2115    // Label 207: @3134
2116    GIM_Reject,
2117    // Label 199: @3135
2118    GIM_Try, /*On fail goto*//*Label 208*/ 3166, // Rule ID 874 //
2119      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2120      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
2121      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
2122      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
2123      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
2124      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
2125      // (urem:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (MOD_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
2126      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_U_W,
2127      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2128      // GIR_Coverage, 874,
2129      GIR_Done,
2130    // Label 208: @3166
2131    GIM_Reject,
2132    // Label 200: @3167
2133    GIM_Try, /*On fail goto*//*Label 209*/ 3198, // Rule ID 873 //
2134      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2135      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
2136      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
2137      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
2138      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
2139      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
2140      // (urem:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (MOD_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
2141      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_U_H,
2142      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2143      // GIR_Coverage, 873,
2144      GIR_Done,
2145    // Label 209: @3198
2146    GIM_Reject,
2147    // Label 201: @3199
2148    GIM_Try, /*On fail goto*//*Label 210*/ 3230, // Rule ID 872 //
2149      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2150      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
2151      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
2152      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
2153      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
2154      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
2155      // (urem:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (MOD_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
2156      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_U_B,
2157      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2158      // GIR_Coverage, 872,
2159      GIR_Done,
2160    // Label 210: @3230
2161    GIM_Reject,
2162    // Label 202: @3231
2163    GIM_Reject,
2164    // Label 7: @3232
2165    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 217*/ 3718,
2166    /*GILLT_s32*//*Label 211*/ 3246,
2167    /*GILLT_s64*//*Label 212*/ 3502, 0,
2168    /*GILLT_v2s64*//*Label 213*/ 3590, 0,
2169    /*GILLT_v4s32*//*Label 214*/ 3622,
2170    /*GILLT_v8s16*//*Label 215*/ 3654,
2171    /*GILLT_v16s8*//*Label 216*/ 3686,
2172    // Label 211: @3246
2173    GIM_Try, /*On fail goto*//*Label 218*/ 3501,
2174      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2175      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2176      GIM_Try, /*On fail goto*//*Label 219*/ 3299, // Rule ID 41 //
2177        GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
2178        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2179        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2180        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2181        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
2182        GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIPFP_APInt_Predicate_imm32ZExt16,
2183        // MIs[1] Operand 1
2184        // No operand predicates
2185        GIM_CheckIsSafeToFold, /*InsnID*/1,
2186        // (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_imm32ZExt16>>:$imm16)  =>  (ANDi:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$imm16)
2187        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ANDi,
2188        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
2189        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
2190        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16
2191        GIR_EraseFromParent, /*InsnID*/0,
2192        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2193        // GIR_Coverage, 41,
2194        GIR_Done,
2195      // Label 219: @3299
2196      GIM_Try, /*On fail goto*//*Label 220*/ 3342, // Rule ID 2120 //
2197        GIM_CheckFeatures, GIFBS_InMicroMips,
2198        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2199        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2200        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2201        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
2202        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExtAndi16,
2203        // MIs[1] Operand 1
2204        // No operand predicates
2205        GIM_CheckIsSafeToFold, /*InsnID*/1,
2206        // (and:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm)  =>  (ANDI16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm)
2207        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ANDI16_MM,
2208        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2209        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
2210        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
2211        GIR_EraseFromParent, /*InsnID*/0,
2212        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2213        // GIR_Coverage, 2120,
2214        GIR_Done,
2215      // Label 220: @3342
2216      GIM_Try, /*On fail goto*//*Label 221*/ 3385, // Rule ID 2277 //
2217        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
2218        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2219        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2220        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2221        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
2222        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExtAndi16,
2223        // MIs[1] Operand 1
2224        // No operand predicates
2225        GIM_CheckIsSafeToFold, /*InsnID*/1,
2226        // (and:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm)  =>  (ANDI16_MMR6:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm)
2227        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ANDI16_MMR6,
2228        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2229        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
2230        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
2231        GIR_EraseFromParent, /*InsnID*/0,
2232        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2233        // GIR_Coverage, 2277,
2234        GIR_Done,
2235      // Label 221: @3385
2236      GIM_Try, /*On fail goto*//*Label 222*/ 3408, // Rule ID 51 //
2237        GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
2238        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2239        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2240        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2241        // (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (AND:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2242        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND,
2243        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2244        // GIR_Coverage, 51,
2245        GIR_Done,
2246      // Label 222: @3408
2247      GIM_Try, /*On fail goto*//*Label 223*/ 3431, // Rule ID 1045 //
2248        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
2249        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2250        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2251        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID,
2252        // (and:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)  =>  (AND16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
2253        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND16_MM,
2254        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2255        // GIR_Coverage, 1045,
2256        GIR_Done,
2257      // Label 223: @3431
2258      GIM_Try, /*On fail goto*//*Label 224*/ 3454, // Rule ID 1061 //
2259        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
2260        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2261        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2262        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2263        // (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (AND_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2264        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_MM,
2265        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2266        // GIR_Coverage, 1061,
2267        GIR_Done,
2268      // Label 224: @3454
2269      GIM_Try, /*On fail goto*//*Label 225*/ 3477, // Rule ID 1152 //
2270        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
2271        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2272        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2273        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2274        // (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (AND_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2275        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_MMR6,
2276        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2277        // GIR_Coverage, 1152,
2278        GIR_Done,
2279      // Label 225: @3477
2280      GIM_Try, /*On fail goto*//*Label 226*/ 3500, // Rule ID 1778 //
2281        GIM_CheckFeatures, GIFBS_InMips16Mode,
2282        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
2283        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
2284        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
2285        // (and:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)  =>  (AndRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
2286        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AndRxRxRy16,
2287        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2288        // GIR_Coverage, 1778,
2289        GIR_Done,
2290      // Label 226: @3500
2291      GIM_Reject,
2292    // Label 218: @3501
2293    GIM_Reject,
2294    // Label 212: @3502
2295    GIM_Try, /*On fail goto*//*Label 227*/ 3589,
2296      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
2297      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2298      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
2299      GIM_Try, /*On fail goto*//*Label 228*/ 3569, // Rule ID 257 //
2300        GIM_CheckFeatures, GIFBS_HasCnMips,
2301        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2302        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
2303        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
2304        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
2305        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
2306        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
2307        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 255,
2308        GIM_CheckIsSafeToFold, /*InsnID*/1,
2309        // (and:{ *:[i64] } (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt), 255:{ *:[i64] })  =>  (BADDu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2310        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BADDu,
2311        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2312        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2313        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2314        GIR_EraseFromParent, /*InsnID*/0,
2315        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2316        // GIR_Coverage, 257,
2317        GIR_Done,
2318      // Label 228: @3569
2319      GIM_Try, /*On fail goto*//*Label 229*/ 3588, // Rule ID 200 //
2320        GIM_CheckFeatures, GIFBS_IsGP64bit_NotInMips16Mode,
2321        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
2322        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
2323        // (and:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (AND64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2324        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND64,
2325        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2326        // GIR_Coverage, 200,
2327        GIR_Done,
2328      // Label 229: @3588
2329      GIM_Reject,
2330    // Label 227: @3589
2331    GIM_Reject,
2332    // Label 213: @3590
2333    GIM_Try, /*On fail goto*//*Label 230*/ 3621, // Rule ID 502 //
2334      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2335      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
2336      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
2337      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2338      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
2339      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
2340      // (and:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (AND_V_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
2341      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_V_D_PSEUDO,
2342      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2343      // GIR_Coverage, 502,
2344      GIR_Done,
2345    // Label 230: @3621
2346    GIM_Reject,
2347    // Label 214: @3622
2348    GIM_Try, /*On fail goto*//*Label 231*/ 3653, // Rule ID 501 //
2349      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2350      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
2351      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
2352      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
2353      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
2354      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
2355      // (and:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (AND_V_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
2356      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_V_W_PSEUDO,
2357      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2358      // GIR_Coverage, 501,
2359      GIR_Done,
2360    // Label 231: @3653
2361    GIM_Reject,
2362    // Label 215: @3654
2363    GIM_Try, /*On fail goto*//*Label 232*/ 3685, // Rule ID 500 //
2364      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2365      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
2366      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
2367      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
2368      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
2369      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
2370      // (and:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (AND_V_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
2371      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_V_H_PSEUDO,
2372      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2373      // GIR_Coverage, 500,
2374      GIR_Done,
2375    // Label 232: @3685
2376    GIM_Reject,
2377    // Label 216: @3686
2378    GIM_Try, /*On fail goto*//*Label 233*/ 3717, // Rule ID 499 //
2379      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2380      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
2381      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
2382      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
2383      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
2384      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
2385      // (and:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (AND_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
2386      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_V,
2387      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2388      // GIR_Coverage, 499,
2389      GIR_Done,
2390    // Label 233: @3717
2391    GIM_Reject,
2392    // Label 217: @3718
2393    GIM_Reject,
2394    // Label 8: @3719
2395    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 240*/ 4063,
2396    /*GILLT_s32*//*Label 234*/ 3733,
2397    /*GILLT_s64*//*Label 235*/ 3903, 0,
2398    /*GILLT_v2s64*//*Label 236*/ 3935, 0,
2399    /*GILLT_v4s32*//*Label 237*/ 3967,
2400    /*GILLT_v8s16*//*Label 238*/ 3999,
2401    /*GILLT_v16s8*//*Label 239*/ 4031,
2402    // Label 234: @3733
2403    GIM_Try, /*On fail goto*//*Label 241*/ 3902,
2404      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2405      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2406      GIM_Try, /*On fail goto*//*Label 242*/ 3786, // Rule ID 42 //
2407        GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
2408        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2409        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2410        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2411        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
2412        GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIPFP_APInt_Predicate_imm32ZExt16,
2413        // MIs[1] Operand 1
2414        // No operand predicates
2415        GIM_CheckIsSafeToFold, /*InsnID*/1,
2416        // (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_imm32ZExt16>>:$imm16)  =>  (ORi:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$imm16)
2417        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ORi,
2418        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
2419        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
2420        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16
2421        GIR_EraseFromParent, /*InsnID*/0,
2422        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2423        // GIR_Coverage, 42,
2424        GIR_Done,
2425      // Label 242: @3786
2426      GIM_Try, /*On fail goto*//*Label 243*/ 3809, // Rule ID 52 //
2427        GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
2428        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2429        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2430        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2431        // (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (OR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2432        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR,
2433        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2434        // GIR_Coverage, 52,
2435        GIR_Done,
2436      // Label 243: @3809
2437      GIM_Try, /*On fail goto*//*Label 244*/ 3832, // Rule ID 1047 //
2438        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
2439        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2440        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2441        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID,
2442        // (or:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)  =>  (OR16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
2443        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR16_MM,
2444        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2445        // GIR_Coverage, 1047,
2446        GIR_Done,
2447      // Label 244: @3832
2448      GIM_Try, /*On fail goto*//*Label 245*/ 3855, // Rule ID 1062 //
2449        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
2450        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2451        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2452        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2453        // (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (OR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2454        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_MM,
2455        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2456        // GIR_Coverage, 1062,
2457        GIR_Done,
2458      // Label 245: @3855
2459      GIM_Try, /*On fail goto*//*Label 246*/ 3878, // Rule ID 1165 //
2460        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
2461        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2462        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2463        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2464        // (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (OR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2465        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_MMR6,
2466        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2467        // GIR_Coverage, 1165,
2468        GIR_Done,
2469      // Label 246: @3878
2470      GIM_Try, /*On fail goto*//*Label 247*/ 3901, // Rule ID 1780 //
2471        GIM_CheckFeatures, GIFBS_InMips16Mode,
2472        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
2473        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
2474        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
2475        // (or:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)  =>  (OrRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
2476        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OrRxRxRy16,
2477        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2478        // GIR_Coverage, 1780,
2479        GIR_Done,
2480      // Label 247: @3901
2481      GIM_Reject,
2482    // Label 241: @3902
2483    GIM_Reject,
2484    // Label 235: @3903
2485    GIM_Try, /*On fail goto*//*Label 248*/ 3934, // Rule ID 201 //
2486      GIM_CheckFeatures, GIFBS_IsGP64bit_NotInMips16Mode,
2487      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
2488      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2489      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
2490      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
2491      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
2492      // (or:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (OR64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2493      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR64,
2494      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2495      // GIR_Coverage, 201,
2496      GIR_Done,
2497    // Label 248: @3934
2498    GIM_Reject,
2499    // Label 236: @3935
2500    GIM_Try, /*On fail goto*//*Label 249*/ 3966, // Rule ID 908 //
2501      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2502      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
2503      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
2504      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2505      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
2506      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
2507      // (or:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (OR_V_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
2508      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_V_D_PSEUDO,
2509      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2510      // GIR_Coverage, 908,
2511      GIR_Done,
2512    // Label 249: @3966
2513    GIM_Reject,
2514    // Label 237: @3967
2515    GIM_Try, /*On fail goto*//*Label 250*/ 3998, // Rule ID 907 //
2516      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2517      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
2518      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
2519      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
2520      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
2521      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
2522      // (or:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (OR_V_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
2523      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_V_W_PSEUDO,
2524      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2525      // GIR_Coverage, 907,
2526      GIR_Done,
2527    // Label 250: @3998
2528    GIM_Reject,
2529    // Label 238: @3999
2530    GIM_Try, /*On fail goto*//*Label 251*/ 4030, // Rule ID 906 //
2531      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2532      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
2533      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
2534      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
2535      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
2536      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
2537      // (or:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (OR_V_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
2538      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_V_H_PSEUDO,
2539      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2540      // GIR_Coverage, 906,
2541      GIR_Done,
2542    // Label 251: @4030
2543    GIM_Reject,
2544    // Label 239: @4031
2545    GIM_Try, /*On fail goto*//*Label 252*/ 4062, // Rule ID 905 //
2546      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2547      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
2548      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
2549      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
2550      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
2551      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
2552      // (or:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (OR_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
2553      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_V,
2554      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2555      // GIR_Coverage, 905,
2556      GIR_Done,
2557    // Label 252: @4062
2558    GIM_Reject,
2559    // Label 240: @4063
2560    GIM_Reject,
2561    // Label 9: @4064
2562    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 259*/ 4903,
2563    /*GILLT_s32*//*Label 253*/ 4078,
2564    /*GILLT_s64*//*Label 254*/ 4687, 0,
2565    /*GILLT_v2s64*//*Label 255*/ 4775, 0,
2566    /*GILLT_v4s32*//*Label 256*/ 4807,
2567    /*GILLT_v8s16*//*Label 257*/ 4839,
2568    /*GILLT_v16s8*//*Label 258*/ 4871,
2569    // Label 253: @4078
2570    GIM_Try, /*On fail goto*//*Label 260*/ 4686,
2571      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2572      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2573      GIM_Try, /*On fail goto*//*Label 261*/ 4145, // Rule ID 54 //
2574        GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
2575        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2576        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2577        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR,
2578        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2579        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2580        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2581        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2582        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2583        GIM_CheckIsSafeToFold, /*InsnID*/1,
2584        // (xor:{ *:[i32] } (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt), -1:{ *:[i32] })  =>  (NOR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2585        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR,
2586        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2587        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2588        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2589        GIR_EraseFromParent, /*InsnID*/0,
2590        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2591        // GIR_Coverage, 54,
2592        GIR_Done,
2593      // Label 261: @4145
2594      GIM_Try, /*On fail goto*//*Label 262*/ 4202, // Rule ID 1064 //
2595        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
2596        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2597        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2598        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR,
2599        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2600        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2601        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2602        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2603        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2604        GIM_CheckIsSafeToFold, /*InsnID*/1,
2605        // (xor:{ *:[i32] } (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt), -1:{ *:[i32] })  =>  (NOR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2606        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MM,
2607        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2608        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2609        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2610        GIR_EraseFromParent, /*InsnID*/0,
2611        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2612        // GIR_Coverage, 1064,
2613        GIR_Done,
2614      // Label 262: @4202
2615      GIM_Try, /*On fail goto*//*Label 263*/ 4259, // Rule ID 1164 //
2616        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
2617        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2618        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2619        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR,
2620        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2621        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2622        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2623        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2624        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2625        GIM_CheckIsSafeToFold, /*InsnID*/1,
2626        // (xor:{ *:[i32] } (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt), -1:{ *:[i32] })  =>  (NOR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2627        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MMR6,
2628        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2629        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2630        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2631        GIR_EraseFromParent, /*InsnID*/0,
2632        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2633        // GIR_Coverage, 1164,
2634        GIR_Done,
2635      // Label 263: @4259
2636      GIM_Try, /*On fail goto*//*Label 264*/ 4291, // Rule ID 1191 //
2637        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
2638        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2639        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2640        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2641        // (xor:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] })  =>  (NOT16_MMR6:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs)
2642        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOT16_MMR6,
2643        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
2644        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
2645        GIR_EraseFromParent, /*InsnID*/0,
2646        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2647        // GIR_Coverage, 1191,
2648        GIR_Done,
2649      // Label 264: @4291
2650      GIM_Try, /*On fail goto*//*Label 265*/ 4323, // Rule ID 1046 //
2651        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
2652        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2653        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2654        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2655        // (xor:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] })  =>  (NOT16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs)
2656        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOT16_MM,
2657        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
2658        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
2659        GIR_EraseFromParent, /*InsnID*/0,
2660        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2661        // GIR_Coverage, 1046,
2662        GIR_Done,
2663      // Label 265: @4323
2664      GIM_Try, /*On fail goto*//*Label 266*/ 4359, // Rule ID 1379 //
2665        GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
2666        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2667        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2668        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2669        // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$in, -1:{ *:[i32] })  =>  (NOR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$in, ZERO:{ *:[i32] })
2670        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR,
2671        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2672        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in
2673        GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0,
2674        GIR_EraseFromParent, /*InsnID*/0,
2675        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2676        // GIR_Coverage, 1379,
2677        GIR_Done,
2678      // Label 266: @4359
2679      GIM_Try, /*On fail goto*//*Label 267*/ 4391, // Rule ID 1775 //
2680        GIM_CheckFeatures, GIFBS_InMips16Mode,
2681        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
2682        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
2683        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2684        // (xor:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, -1:{ *:[i32] })  =>  (NotRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r)
2685        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NotRxRy16,
2686        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rx
2687        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // r
2688        GIR_EraseFromParent, /*InsnID*/0,
2689        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2690        // GIR_Coverage, 1775,
2691        GIR_Done,
2692      // Label 267: @4391
2693      GIM_Try, /*On fail goto*//*Label 268*/ 4423, // Rule ID 2115 //
2694        GIM_CheckFeatures, GIFBS_InMicroMips,
2695        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2696        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2697        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2698        // (xor:{ *:[i32] } GPRMM16:{ *:[i32] }:$in, -1:{ *:[i32] })  =>  (NOT16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$in)
2699        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOT16_MM,
2700        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
2701        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in
2702        GIR_EraseFromParent, /*InsnID*/0,
2703        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2704        // GIR_Coverage, 2115,
2705        GIR_Done,
2706      // Label 268: @4423
2707      GIM_Try, /*On fail goto*//*Label 269*/ 4459, // Rule ID 2116 //
2708        GIM_CheckFeatures, GIFBS_InMicroMips,
2709        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2710        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2711        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2712        // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$in, -1:{ *:[i32] })  =>  (NOR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$in, ZERO:{ *:[i32] })
2713        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MM,
2714        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2715        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in
2716        GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0,
2717        GIR_EraseFromParent, /*InsnID*/0,
2718        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2719        // GIR_Coverage, 2116,
2720        GIR_Done,
2721      // Label 269: @4459
2722      GIM_Try, /*On fail goto*//*Label 270*/ 4491, // Rule ID 2280 //
2723        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
2724        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2725        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2726        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2727        // (xor:{ *:[i32] } GPRMM16:{ *:[i32] }:$in, -1:{ *:[i32] })  =>  (NOT16_MMR6:{ *:[i32] } GPRMM16:{ *:[i32] }:$in)
2728        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOT16_MMR6,
2729        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
2730        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in
2731        GIR_EraseFromParent, /*InsnID*/0,
2732        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2733        // GIR_Coverage, 2280,
2734        GIR_Done,
2735      // Label 270: @4491
2736      GIM_Try, /*On fail goto*//*Label 271*/ 4527, // Rule ID 2281 //
2737        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
2738        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2739        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2740        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2741        // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$in, -1:{ *:[i32] })  =>  (NOR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$in, ZERO:{ *:[i32] })
2742        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MMR6,
2743        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2744        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in
2745        GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0,
2746        GIR_EraseFromParent, /*InsnID*/0,
2747        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2748        // GIR_Coverage, 2281,
2749        GIR_Done,
2750      // Label 271: @4527
2751      GIM_Try, /*On fail goto*//*Label 272*/ 4570, // Rule ID 43 //
2752        GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
2753        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2754        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2755        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2756        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
2757        GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIPFP_APInt_Predicate_imm32ZExt16,
2758        // MIs[1] Operand 1
2759        // No operand predicates
2760        GIM_CheckIsSafeToFold, /*InsnID*/1,
2761        // (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_imm32ZExt16>>:$imm16)  =>  (XORi:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$imm16)
2762        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi,
2763        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
2764        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
2765        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16
2766        GIR_EraseFromParent, /*InsnID*/0,
2767        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2768        // GIR_Coverage, 43,
2769        GIR_Done,
2770      // Label 272: @4570
2771      GIM_Try, /*On fail goto*//*Label 273*/ 4593, // Rule ID 53 //
2772        GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
2773        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2774        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2775        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2776        // (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (XOR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2777        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR,
2778        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2779        // GIR_Coverage, 53,
2780        GIR_Done,
2781      // Label 273: @4593
2782      GIM_Try, /*On fail goto*//*Label 274*/ 4616, // Rule ID 1049 //
2783        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
2784        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2785        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2786        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID,
2787        // (xor:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)  =>  (XOR16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
2788        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR16_MM,
2789        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2790        // GIR_Coverage, 1049,
2791        GIR_Done,
2792      // Label 274: @4616
2793      GIM_Try, /*On fail goto*//*Label 275*/ 4639, // Rule ID 1063 //
2794        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
2795        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2796        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2797        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2798        // (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (XOR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2799        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_MM,
2800        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2801        // GIR_Coverage, 1063,
2802        GIR_Done,
2803      // Label 275: @4639
2804      GIM_Try, /*On fail goto*//*Label 276*/ 4662, // Rule ID 1168 //
2805        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
2806        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2807        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2808        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2809        // (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (XOR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2810        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_MMR6,
2811        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2812        // GIR_Coverage, 1168,
2813        GIR_Done,
2814      // Label 276: @4662
2815      GIM_Try, /*On fail goto*//*Label 277*/ 4685, // Rule ID 1782 //
2816        GIM_CheckFeatures, GIFBS_InMips16Mode,
2817        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
2818        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
2819        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
2820        // (xor:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)  =>  (XorRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
2821        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XorRxRxRy16,
2822        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2823        // GIR_Coverage, 1782,
2824        GIR_Done,
2825      // Label 277: @4685
2826      GIM_Reject,
2827    // Label 260: @4686
2828    GIM_Reject,
2829    // Label 254: @4687
2830    GIM_Try, /*On fail goto*//*Label 278*/ 4774,
2831      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
2832      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2833      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
2834      GIM_Try, /*On fail goto*//*Label 279*/ 4754, // Rule ID 203 //
2835        GIM_CheckFeatures, GIFBS_IsGP64bit_NotInMips16Mode,
2836        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2837        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR,
2838        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
2839        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
2840        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
2841        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
2842        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2843        GIM_CheckIsSafeToFold, /*InsnID*/1,
2844        // (xor:{ *:[i64] } (or:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt), -1:{ *:[i64] })  =>  (NOR64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2845        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR64,
2846        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2847        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2848        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2849        GIR_EraseFromParent, /*InsnID*/0,
2850        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2851        // GIR_Coverage, 203,
2852        GIR_Done,
2853      // Label 279: @4754
2854      GIM_Try, /*On fail goto*//*Label 280*/ 4773, // Rule ID 202 //
2855        GIM_CheckFeatures, GIFBS_IsGP64bit_NotInMips16Mode,
2856        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
2857        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
2858        // (xor:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (XOR64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2859        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR64,
2860        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2861        // GIR_Coverage, 202,
2862        GIR_Done,
2863      // Label 280: @4773
2864      GIM_Reject,
2865    // Label 278: @4774
2866    GIM_Reject,
2867    // Label 255: @4775
2868    GIM_Try, /*On fail goto*//*Label 281*/ 4806, // Rule ID 1024 //
2869      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2870      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
2871      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
2872      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2873      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
2874      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
2875      // (xor:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (XOR_V_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
2876      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_V_D_PSEUDO,
2877      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2878      // GIR_Coverage, 1024,
2879      GIR_Done,
2880    // Label 281: @4806
2881    GIM_Reject,
2882    // Label 256: @4807
2883    GIM_Try, /*On fail goto*//*Label 282*/ 4838, // Rule ID 1023 //
2884      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2885      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
2886      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
2887      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
2888      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
2889      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
2890      // (xor:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (XOR_V_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
2891      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_V_W_PSEUDO,
2892      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2893      // GIR_Coverage, 1023,
2894      GIR_Done,
2895    // Label 282: @4838
2896    GIM_Reject,
2897    // Label 257: @4839
2898    GIM_Try, /*On fail goto*//*Label 283*/ 4870, // Rule ID 1022 //
2899      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2900      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
2901      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
2902      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
2903      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
2904      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
2905      // (xor:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (XOR_V_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
2906      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_V_H_PSEUDO,
2907      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2908      // GIR_Coverage, 1022,
2909      GIR_Done,
2910    // Label 283: @4870
2911    GIM_Reject,
2912    // Label 258: @4871
2913    GIM_Try, /*On fail goto*//*Label 284*/ 4902, // Rule ID 1021 //
2914      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2915      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
2916      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
2917      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
2918      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
2919      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
2920      // (xor:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (XOR_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
2921      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_V,
2922      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2923      // GIR_Coverage, 1021,
2924      GIR_Done,
2925    // Label 284: @4902
2926    GIM_Reject,
2927    // Label 259: @4903
2928    GIM_Reject,
2929    // Label 10: @4904
2930    GIM_Try, /*On fail goto*//*Label 285*/ 4980,
2931      GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
2932      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
2933      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
2934      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2935      GIM_Try, /*On fail goto*//*Label 286*/ 4950, // Rule ID 703 //
2936        GIM_CheckFeatures, GIFBS_HasMSA_HasMips64_HasStdEnc,
2937        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
2938        // MIs[0] rs
2939        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
2940        // (build_vector:{ *:[v2i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rs)  =>  (FILL_D:{ *:[v2i64] } GPR64Opnd:{ *:[i64] }:$rs)
2941        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FILL_D,
2942        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
2943        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
2944        GIR_EraseFromParent, /*InsnID*/0,
2945        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2946        // GIR_Coverage, 703,
2947        GIR_Done,
2948      // Label 286: @4950
2949      GIM_Try, /*On fail goto*//*Label 287*/ 4979, // Rule ID 705 //
2950        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2951        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
2952        // MIs[0] fs
2953        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
2954        // (build_vector:{ *:[v2f64] } FGR64:{ *:[f64] }:$fs, FGR64:{ *:[f64] }:$fs)  =>  (FILL_FD_PSEUDO:{ *:[v2f64] } FGR64:{ *:[f64] }:$fs)
2955        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FILL_FD_PSEUDO,
2956        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
2957        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fs
2958        GIR_EraseFromParent, /*InsnID*/0,
2959        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2960        // GIR_Coverage, 705,
2961        GIR_Done,
2962      // Label 287: @4979
2963      GIM_Reject,
2964    // Label 285: @4980
2965    GIM_Try, /*On fail goto*//*Label 288*/ 5076,
2966      GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
2967      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
2968      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2969      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
2970      GIM_Try, /*On fail goto*//*Label 289*/ 5036, // Rule ID 702 //
2971        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2972        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2973        // MIs[0] rs
2974        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
2975        // MIs[0] rs
2976        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1,
2977        // MIs[0] rs
2978        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1,
2979        // (build_vector:{ *:[v4i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs)  =>  (FILL_W:{ *:[v4i32] } GPR32Opnd:{ *:[i32] }:$rs)
2980        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FILL_W,
2981        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
2982        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
2983        GIR_EraseFromParent, /*InsnID*/0,
2984        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2985        // GIR_Coverage, 702,
2986        GIR_Done,
2987      // Label 289: @5036
2988      GIM_Try, /*On fail goto*//*Label 290*/ 5075, // Rule ID 704 //
2989        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2990        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
2991        // MIs[0] fs
2992        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
2993        // MIs[0] fs
2994        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1,
2995        // MIs[0] fs
2996        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1,
2997        // (build_vector:{ *:[v4f32] } FGR32:{ *:[f32] }:$fs, FGR32:{ *:[f32] }:$fs, FGR32:{ *:[f32] }:$fs, FGR32:{ *:[f32] }:$fs)  =>  (FILL_FW_PSEUDO:{ *:[v4f32] } FGR32:{ *:[f32] }:$fs)
2998        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FILL_FW_PSEUDO,
2999        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
3000        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fs
3001        GIR_EraseFromParent, /*InsnID*/0,
3002        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3003        // GIR_Coverage, 704,
3004        GIR_Done,
3005      // Label 290: @5075
3006      GIM_Reject,
3007    // Label 288: @5076
3008    GIM_Try, /*On fail goto*//*Label 291*/ 5150, // Rule ID 701 //
3009      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
3010      GIM_CheckNumOperands, /*MI*/0, /*Expected*/9,
3011      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
3012      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3013      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3014      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
3015      // MIs[0] rs
3016      GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
3017      // MIs[0] rs
3018      GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1,
3019      // MIs[0] rs
3020      GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1,
3021      // MIs[0] rs
3022      GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/5, /*OtherMI*/0, /*OtherOpIdx*/1,
3023      // MIs[0] rs
3024      GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/6, /*OtherMI*/0, /*OtherOpIdx*/1,
3025      // MIs[0] rs
3026      GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/7, /*OtherMI*/0, /*OtherOpIdx*/1,
3027      // MIs[0] rs
3028      GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/8, /*OtherMI*/0, /*OtherOpIdx*/1,
3029      // (build_vector:{ *:[v8i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs)  =>  (FILL_H:{ *:[v8i16] } GPR32Opnd:{ *:[i32] }:$rs)
3030      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FILL_H,
3031      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
3032      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
3033      GIR_EraseFromParent, /*InsnID*/0,
3034      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3035      // GIR_Coverage, 701,
3036      GIR_Done,
3037    // Label 291: @5150
3038    GIM_Try, /*On fail goto*//*Label 292*/ 5264, // Rule ID 700 //
3039      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
3040      GIM_CheckNumOperands, /*MI*/0, /*Expected*/17,
3041      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
3042      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3043      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
3044      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
3045      // MIs[0] rs
3046      GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
3047      // MIs[0] rs
3048      GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1,
3049      // MIs[0] rs
3050      GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1,
3051      // MIs[0] rs
3052      GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/5, /*OtherMI*/0, /*OtherOpIdx*/1,
3053      // MIs[0] rs
3054      GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/6, /*OtherMI*/0, /*OtherOpIdx*/1,
3055      // MIs[0] rs
3056      GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/7, /*OtherMI*/0, /*OtherOpIdx*/1,
3057      // MIs[0] rs
3058      GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/8, /*OtherMI*/0, /*OtherOpIdx*/1,
3059      // MIs[0] rs
3060      GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/9, /*OtherMI*/0, /*OtherOpIdx*/1,
3061      // MIs[0] rs
3062      GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/10, /*OtherMI*/0, /*OtherOpIdx*/1,
3063      // MIs[0] rs
3064      GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/11, /*OtherMI*/0, /*OtherOpIdx*/1,
3065      // MIs[0] rs
3066      GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/12, /*OtherMI*/0, /*OtherOpIdx*/1,
3067      // MIs[0] rs
3068      GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/13, /*OtherMI*/0, /*OtherOpIdx*/1,
3069      // MIs[0] rs
3070      GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/14, /*OtherMI*/0, /*OtherOpIdx*/1,
3071      // MIs[0] rs
3072      GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/15, /*OtherMI*/0, /*OtherOpIdx*/1,
3073      // MIs[0] rs
3074      GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/16, /*OtherMI*/0, /*OtherOpIdx*/1,
3075      // (build_vector:{ *:[v16i8] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs)  =>  (FILL_B:{ *:[v16i8] } GPR32Opnd:{ *:[i32] }:$rs)
3076      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FILL_B,
3077      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
3078      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
3079      GIR_EraseFromParent, /*InsnID*/0,
3080      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3081      // GIR_Coverage, 700,
3082      GIR_Done,
3083    // Label 292: @5264
3084    GIM_Reject,
3085    // Label 11: @5265
3086    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 301*/ 8917,
3087    /*GILLT_s32*//*Label 293*/ 5279,
3088    /*GILLT_s64*//*Label 294*/ 5518,
3089    /*GILLT_v2s16*//*Label 295*/ 5564,
3090    /*GILLT_v2s64*//*Label 296*/ 5610,
3091    /*GILLT_v4s8*//*Label 297*/ 6583,
3092    /*GILLT_v4s32*//*Label 298*/ 6629,
3093    /*GILLT_v8s16*//*Label 299*/ 7532,
3094    /*GILLT_v16s8*//*Label 300*/ 8330,
3095    // Label 293: @5279
3096    GIM_Try, /*On fail goto*//*Label 302*/ 5302, // Rule ID 129 //
3097      GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
3098      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3099      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
3100      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
3101      // (bitconvert:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)  =>  (MFC1:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)
3102      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MFC1,
3103      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3104      // GIR_Coverage, 129,
3105      GIR_Done,
3106    // Label 302: @5302
3107    GIM_Try, /*On fail goto*//*Label 303*/ 5325, // Rule ID 130 //
3108      GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
3109      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3110      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
3111      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
3112      // (bitconvert:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)  =>  (MTC1:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)
3113      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MTC1,
3114      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3115      // GIR_Coverage, 130,
3116      GIR_Done,
3117    // Label 303: @5325
3118    GIM_Try, /*On fail goto*//*Label 304*/ 5348, // Rule ID 1144 //
3119      GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat,
3120      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3121      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
3122      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
3123      // (bitconvert:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)  =>  (MFC1_MM:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)
3124      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MFC1_MM,
3125      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3126      // GIR_Coverage, 1144,
3127      GIR_Done,
3128    // Label 304: @5348
3129    GIM_Try, /*On fail goto*//*Label 305*/ 5371, // Rule ID 1145 //
3130      GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat,
3131      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3132      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
3133      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
3134      // (bitconvert:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)  =>  (MTC1_MM:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)
3135      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MTC1_MM,
3136      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3137      // GIR_Coverage, 1145,
3138      GIR_Done,
3139    // Label 305: @5371
3140    GIM_Try, /*On fail goto*//*Label 306*/ 5394, // Rule ID 1157 //
3141      GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
3142      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3143      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
3144      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
3145      // (bitconvert:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)  =>  (MTC1_MMR6:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)
3146      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MTC1_MMR6,
3147      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3148      // GIR_Coverage, 1157,
3149      GIR_Done,
3150    // Label 306: @5394
3151    GIM_Try, /*On fail goto*//*Label 307*/ 5417, // Rule ID 1158 //
3152      GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
3153      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3154      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
3155      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
3156      // (bitconvert:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)  =>  (MFC1_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)
3157      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MFC1_MMR6,
3158      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3159      // GIR_Coverage, 1158,
3160      GIR_Done,
3161    // Label 307: @5417
3162    GIM_Try, /*On fail goto*//*Label 308*/ 5442, // Rule ID 1863 //
3163      GIM_CheckFeatures, GIFBS_HasDSP,
3164      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
3165      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
3166      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
3167      // (bitconvert:{ *:[i32] } DSPR:{ *:[v2i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[i32] } DSPR:{ *:[v2i16] }:$src, GPR32:{ *:[i32] })
3168      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3169      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR32*/8,
3170      // GIR_Coverage, 1863,
3171      GIR_Done,
3172    // Label 308: @5442
3173    GIM_Try, /*On fail goto*//*Label 309*/ 5467, // Rule ID 1864 //
3174      GIM_CheckFeatures, GIFBS_HasDSP,
3175      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8,
3176      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
3177      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
3178      // (bitconvert:{ *:[i32] } DSPR:{ *:[v4i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[i32] } DSPR:{ *:[v4i8] }:$src, GPR32:{ *:[i32] })
3179      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3180      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR32*/8,
3181      // GIR_Coverage, 1864,
3182      GIR_Done,
3183    // Label 309: @5467
3184    GIM_Try, /*On fail goto*//*Label 310*/ 5492, // Rule ID 1867 //
3185      GIM_CheckFeatures, GIFBS_HasDSP,
3186      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
3187      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
3188      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
3189      // (bitconvert:{ *:[f32] } DSPR:{ *:[v2i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[f32] } DSPR:{ *:[v2i16] }:$src, FGR32:{ *:[i32] })
3190      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3191      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FGR32*/6,
3192      // GIR_Coverage, 1867,
3193      GIR_Done,
3194    // Label 310: @5492
3195    GIM_Try, /*On fail goto*//*Label 311*/ 5517, // Rule ID 1868 //
3196      GIM_CheckFeatures, GIFBS_HasDSP,
3197      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8,
3198      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
3199      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
3200      // (bitconvert:{ *:[f32] } DSPR:{ *:[v4i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[f32] } DSPR:{ *:[v4i8] }:$src, FGR32:{ *:[i32] })
3201      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3202      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FGR32*/6,
3203      // GIR_Coverage, 1868,
3204      GIR_Done,
3205    // Label 311: @5517
3206    GIM_Reject,
3207    // Label 294: @5518
3208    GIM_Try, /*On fail goto*//*Label 312*/ 5563,
3209      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
3210      GIM_Try, /*On fail goto*//*Label 313*/ 5543, // Rule ID 131 //
3211        GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
3212        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
3213        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
3214        // (bitconvert:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$rt)  =>  (DMTC1:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$rt)
3215        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMTC1,
3216        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3217        // GIR_Coverage, 131,
3218        GIR_Done,
3219      // Label 313: @5543
3220      GIM_Try, /*On fail goto*//*Label 314*/ 5562, // Rule ID 132 //
3221        GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
3222        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
3223        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
3224        // (bitconvert:{ *:[i64] } FGR64Opnd:{ *:[f64] }:$fs)  =>  (DMFC1:{ *:[i64] } FGR64Opnd:{ *:[f64] }:$fs)
3225        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMFC1,
3226        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3227        // GIR_Coverage, 132,
3228        GIR_Done,
3229      // Label 314: @5562
3230      GIM_Reject,
3231    // Label 312: @5563
3232    GIM_Reject,
3233    // Label 295: @5564
3234    GIM_Try, /*On fail goto*//*Label 315*/ 5609,
3235      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3236      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
3237      GIM_Try, /*On fail goto*//*Label 316*/ 5591, // Rule ID 1865 //
3238        GIM_CheckFeatures, GIFBS_HasDSP,
3239        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
3240        // (bitconvert:{ *:[v2i16] } GPR32:{ *:[i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i16] } GPR32:{ *:[i32] }:$src, DSPR:{ *:[i32] })
3241        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3242        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DSPR*/5,
3243        // GIR_Coverage, 1865,
3244        GIR_Done,
3245      // Label 316: @5591
3246      GIM_Try, /*On fail goto*//*Label 317*/ 5608, // Rule ID 1869 //
3247        GIM_CheckFeatures, GIFBS_HasDSP,
3248        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
3249        // (bitconvert:{ *:[v2i16] } FGR32:{ *:[f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i16] } FGR32:{ *:[f32] }:$src, DSPR:{ *:[i32] })
3250        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3251        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DSPR*/5,
3252        // GIR_Coverage, 1869,
3253        GIR_Done,
3254      // Label 317: @5608
3255      GIM_Reject,
3256    // Label 315: @5609
3257    GIM_Reject,
3258    // Label 296: @5610
3259    GIM_Try, /*On fail goto*//*Label 318*/ 5631, // Rule ID 1950 //
3260      GIM_CheckFeatures, GIFBS_HasMSA,
3261      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3262      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3263      // (bitconvert:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$src, MSA128D:{ *:[i32] })
3264      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3265      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/65,
3266      // GIR_Coverage, 1950,
3267      GIR_Done,
3268    // Label 318: @5631
3269    GIM_Try, /*On fail goto*//*Label 319*/ 5652, // Rule ID 1953 //
3270      GIM_CheckFeatures, GIFBS_HasMSA,
3271      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3272      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3273      // (bitconvert:{ *:[v2f64] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } v2i64:{ *:[v2i64] }:$src, MSA128D:{ *:[i32] })
3274      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3275      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/65,
3276      // GIR_Coverage, 1953,
3277      GIR_Done,
3278    // Label 319: @5652
3279    GIM_Try, /*On fail goto*//*Label 320*/ 5673, // Rule ID 1970 //
3280      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3281      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3282      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3283      // (bitconvert:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$src, MSA128D:{ *:[i32] })
3284      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3285      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/65,
3286      // GIR_Coverage, 1970,
3287      GIR_Done,
3288    // Label 320: @5673
3289    GIM_Try, /*On fail goto*//*Label 321*/ 5694, // Rule ID 1971 //
3290      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3291      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3292      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3293      // (bitconvert:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$src, MSA128D:{ *:[i32] })
3294      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3295      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/65,
3296      // GIR_Coverage, 1971,
3297      GIR_Done,
3298    // Label 321: @5694
3299    GIM_Try, /*On fail goto*//*Label 322*/ 5715, // Rule ID 1972 //
3300      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3301      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3302      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3303      // (bitconvert:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$src, MSA128D:{ *:[i32] })
3304      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3305      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/65,
3306      // GIR_Coverage, 1972,
3307      GIR_Done,
3308    // Label 322: @5715
3309    GIM_Try, /*On fail goto*//*Label 323*/ 5736, // Rule ID 1973 //
3310      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3311      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3312      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3313      // (bitconvert:{ *:[v2i64] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } v8f16:{ *:[v8f16] }:$src, MSA128D:{ *:[i32] })
3314      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3315      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/65,
3316      // GIR_Coverage, 1973,
3317      GIR_Done,
3318    // Label 323: @5736
3319    GIM_Try, /*On fail goto*//*Label 324*/ 5757, // Rule ID 1974 //
3320      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3321      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3322      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3323      // (bitconvert:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$src, MSA128D:{ *:[i32] })
3324      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3325      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/65,
3326      // GIR_Coverage, 1974,
3327      GIR_Done,
3328    // Label 324: @5757
3329    GIM_Try, /*On fail goto*//*Label 325*/ 5778, // Rule ID 1980 //
3330      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3331      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3332      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3333      // (bitconvert:{ *:[v2f64] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } v16i8:{ *:[v16i8] }:$src, MSA128D:{ *:[i32] })
3334      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3335      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/65,
3336      // GIR_Coverage, 1980,
3337      GIR_Done,
3338    // Label 325: @5778
3339    GIM_Try, /*On fail goto*//*Label 326*/ 5799, // Rule ID 1981 //
3340      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3341      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3342      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3343      // (bitconvert:{ *:[v2f64] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } v8i16:{ *:[v8i16] }:$src, MSA128D:{ *:[i32] })
3344      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3345      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/65,
3346      // GIR_Coverage, 1981,
3347      GIR_Done,
3348    // Label 326: @5799
3349    GIM_Try, /*On fail goto*//*Label 327*/ 5820, // Rule ID 1982 //
3350      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3351      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3352      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3353      // (bitconvert:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$src, MSA128D:{ *:[i32] })
3354      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3355      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/65,
3356      // GIR_Coverage, 1982,
3357      GIR_Done,
3358    // Label 327: @5820
3359    GIM_Try, /*On fail goto*//*Label 328*/ 5841, // Rule ID 1983 //
3360      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3361      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3362      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3363      // (bitconvert:{ *:[v2f64] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } v8f16:{ *:[v8f16] }:$src, MSA128D:{ *:[i32] })
3364      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3365      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/65,
3366      // GIR_Coverage, 1983,
3367      GIR_Done,
3368    // Label 328: @5841
3369    GIM_Try, /*On fail goto*//*Label 329*/ 5862, // Rule ID 1984 //
3370      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3371      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3372      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3373      // (bitconvert:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$src, MSA128D:{ *:[i32] })
3374      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3375      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/65,
3376      // GIR_Coverage, 1984,
3377      GIR_Done,
3378    // Label 329: @5862
3379    GIM_Try, /*On fail goto*//*Label 330*/ 5962, // Rule ID 1989 //
3380      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3381      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3382      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3383      // (bitconvert:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
3384      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3385      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3386      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
3387      GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
3388      GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
3389      GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
3390      GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
3391      GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
3392      GIR_BuildMI, /*InsnID*/3, /*Opcode*/Mips::SHF_B,
3393      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
3394      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
3395      GIR_AddImm, /*InsnID*/3, /*Imm*/27,
3396      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
3397      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3398      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3399      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
3400      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3401      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3402      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3403      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3404      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3405      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3406      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3407      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3408      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3409      GIR_EraseFromParent, /*InsnID*/0,
3410      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/65,
3411      // GIR_Coverage, 1989,
3412      GIR_Done,
3413    // Label 330: @5962
3414    GIM_Try, /*On fail goto*//*Label 331*/ 6062, // Rule ID 1990 //
3415      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3416      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3417      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3418      // (bitconvert:{ *:[v2f64] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
3419      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3420      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3421      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
3422      GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
3423      GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
3424      GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
3425      GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
3426      GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
3427      GIR_BuildMI, /*InsnID*/3, /*Opcode*/Mips::SHF_B,
3428      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
3429      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
3430      GIR_AddImm, /*InsnID*/3, /*Imm*/27,
3431      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
3432      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3433      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3434      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
3435      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3436      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3437      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3438      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3439      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3440      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3441      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3442      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3443      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3444      GIR_EraseFromParent, /*InsnID*/0,
3445      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/65,
3446      // GIR_Coverage, 1990,
3447      GIR_Done,
3448    // Label 331: @6062
3449    GIM_Try, /*On fail goto*//*Label 332*/ 6127, // Rule ID 1994 //
3450      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3451      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3452      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3453      // (bitconvert:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
3454      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3455      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3456      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3457      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3458      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3459      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3460      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3461      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3462      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3463      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3464      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3465      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3466      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3467      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3468      GIR_EraseFromParent, /*InsnID*/0,
3469      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/65,
3470      // GIR_Coverage, 1994,
3471      GIR_Done,
3472    // Label 332: @6127
3473    GIM_Try, /*On fail goto*//*Label 333*/ 6192, // Rule ID 1995 //
3474      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3475      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3476      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3477      // (bitconvert:{ *:[v2f64] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
3478      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3479      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3480      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3481      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3482      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3483      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3484      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3485      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3486      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3487      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3488      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3489      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3490      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3491      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3492      GIR_EraseFromParent, /*InsnID*/0,
3493      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/65,
3494      // GIR_Coverage, 1995,
3495      GIR_Done,
3496    // Label 333: @6192
3497    GIM_Try, /*On fail goto*//*Label 334*/ 6257, // Rule ID 1999 //
3498      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3499      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3500      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3501      // (bitconvert:{ *:[v2i64] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
3502      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3503      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3504      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3505      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3506      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3507      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3508      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3509      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3510      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3511      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3512      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3513      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3514      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3515      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3516      GIR_EraseFromParent, /*InsnID*/0,
3517      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/65,
3518      // GIR_Coverage, 1999,
3519      GIR_Done,
3520    // Label 334: @6257
3521    GIM_Try, /*On fail goto*//*Label 335*/ 6322, // Rule ID 2000 //
3522      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3523      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3524      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3525      // (bitconvert:{ *:[v2f64] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
3526      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3527      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3528      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3529      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3530      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3531      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3532      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3533      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3534      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3535      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3536      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3537      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3538      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3539      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3540      GIR_EraseFromParent, /*InsnID*/0,
3541      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/65,
3542      // GIR_Coverage, 2000,
3543      GIR_Done,
3544    // Label 335: @6322
3545    GIM_Try, /*On fail goto*//*Label 336*/ 6387, // Rule ID 2004 //
3546      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3547      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3548      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3549      // (bitconvert:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
3550      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3551      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3552      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3553      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3554      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3555      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3556      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3557      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3558      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3559      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3560      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3561      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3562      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3563      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3564      GIR_EraseFromParent, /*InsnID*/0,
3565      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/65,
3566      // GIR_Coverage, 2004,
3567      GIR_Done,
3568    // Label 336: @6387
3569    GIM_Try, /*On fail goto*//*Label 337*/ 6452, // Rule ID 2005 //
3570      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3571      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3572      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3573      // (bitconvert:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
3574      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3575      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3576      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3577      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3578      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3579      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3580      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3581      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3582      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3583      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3584      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3585      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3586      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3587      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3588      GIR_EraseFromParent, /*InsnID*/0,
3589      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/65,
3590      // GIR_Coverage, 2005,
3591      GIR_Done,
3592    // Label 337: @6452
3593    GIM_Try, /*On fail goto*//*Label 338*/ 6517, // Rule ID 2009 //
3594      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3595      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3596      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3597      // (bitconvert:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
3598      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3599      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3600      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3601      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3602      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3603      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3604      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3605      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3606      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3607      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3608      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3609      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3610      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3611      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3612      GIR_EraseFromParent, /*InsnID*/0,
3613      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/65,
3614      // GIR_Coverage, 2009,
3615      GIR_Done,
3616    // Label 338: @6517
3617    GIM_Try, /*On fail goto*//*Label 339*/ 6582, // Rule ID 2010 //
3618      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3619      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3620      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3621      // (bitconvert:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
3622      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3623      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3624      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3625      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3626      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3627      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3628      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3629      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3630      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3631      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3632      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3633      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3634      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3635      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3636      GIR_EraseFromParent, /*InsnID*/0,
3637      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/65,
3638      // GIR_Coverage, 2010,
3639      GIR_Done,
3640    // Label 339: @6582
3641    GIM_Reject,
3642    // Label 297: @6583
3643    GIM_Try, /*On fail goto*//*Label 340*/ 6628,
3644      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3645      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
3646      GIM_Try, /*On fail goto*//*Label 341*/ 6610, // Rule ID 1866 //
3647        GIM_CheckFeatures, GIFBS_HasDSP,
3648        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
3649        // (bitconvert:{ *:[v4i8] } GPR32:{ *:[i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i8] } GPR32:{ *:[i32] }:$src, DSPR:{ *:[i32] })
3650        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3651        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DSPR*/5,
3652        // GIR_Coverage, 1866,
3653        GIR_Done,
3654      // Label 341: @6610
3655      GIM_Try, /*On fail goto*//*Label 342*/ 6627, // Rule ID 1870 //
3656        GIM_CheckFeatures, GIFBS_HasDSP,
3657        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
3658        // (bitconvert:{ *:[v4i8] } FGR32:{ *:[f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i8] } FGR32:{ *:[f32] }:$src, DSPR:{ *:[i32] })
3659        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3660        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DSPR*/5,
3661        // GIR_Coverage, 1870,
3662        GIR_Done,
3663      // Label 342: @6627
3664      GIM_Reject,
3665    // Label 340: @6628
3666    GIM_Reject,
3667    // Label 298: @6629
3668    GIM_Try, /*On fail goto*//*Label 343*/ 6650, // Rule ID 1949 //
3669      GIM_CheckFeatures, GIFBS_HasMSA,
3670      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3671      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3672      // (bitconvert:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, MSA128W:{ *:[i32] })
3673      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3674      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/67,
3675      // GIR_Coverage, 1949,
3676      GIR_Done,
3677    // Label 343: @6650
3678    GIM_Try, /*On fail goto*//*Label 344*/ 6671, // Rule ID 1952 //
3679      GIM_CheckFeatures, GIFBS_HasMSA,
3680      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3681      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3682      // (bitconvert:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src, MSA128W:{ *:[i32] })
3683      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3684      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/67,
3685      // GIR_Coverage, 1952,
3686      GIR_Done,
3687    // Label 344: @6671
3688    GIM_Try, /*On fail goto*//*Label 345*/ 6692, // Rule ID 1965 //
3689      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3690      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3691      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3692      // (bitconvert:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$src, MSA128W:{ *:[i32] })
3693      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3694      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/67,
3695      // GIR_Coverage, 1965,
3696      GIR_Done,
3697    // Label 345: @6692
3698    GIM_Try, /*On fail goto*//*Label 346*/ 6713, // Rule ID 1966 //
3699      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3700      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3701      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3702      // (bitconvert:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$src, MSA128W:{ *:[i32] })
3703      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3704      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/67,
3705      // GIR_Coverage, 1966,
3706      GIR_Done,
3707    // Label 346: @6713
3708    GIM_Try, /*On fail goto*//*Label 347*/ 6734, // Rule ID 1967 //
3709      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3710      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3711      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3712      // (bitconvert:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] })
3713      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3714      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/67,
3715      // GIR_Coverage, 1967,
3716      GIR_Done,
3717    // Label 347: @6734
3718    GIM_Try, /*On fail goto*//*Label 348*/ 6755, // Rule ID 1968 //
3719      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3720      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3721      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3722      // (bitconvert:{ *:[v4i32] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } v8f16:{ *:[v8f16] }:$src, MSA128W:{ *:[i32] })
3723      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3724      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/67,
3725      // GIR_Coverage, 1968,
3726      GIR_Done,
3727    // Label 348: @6755
3728    GIM_Try, /*On fail goto*//*Label 349*/ 6776, // Rule ID 1969 //
3729      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3730      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3731      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3732      // (bitconvert:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] })
3733      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3734      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/67,
3735      // GIR_Coverage, 1969,
3736      GIR_Done,
3737    // Label 349: @6776
3738    GIM_Try, /*On fail goto*//*Label 350*/ 6797, // Rule ID 1975 //
3739      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3740      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3741      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3742      // (bitconvert:{ *:[v4f32] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } v16i8:{ *:[v16i8] }:$src, MSA128W:{ *:[i32] })
3743      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3744      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/67,
3745      // GIR_Coverage, 1975,
3746      GIR_Done,
3747    // Label 350: @6797
3748    GIM_Try, /*On fail goto*//*Label 351*/ 6818, // Rule ID 1976 //
3749      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3750      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3751      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3752      // (bitconvert:{ *:[v4f32] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } v8i16:{ *:[v8i16] }:$src, MSA128W:{ *:[i32] })
3753      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3754      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/67,
3755      // GIR_Coverage, 1976,
3756      GIR_Done,
3757    // Label 351: @6818
3758    GIM_Try, /*On fail goto*//*Label 352*/ 6839, // Rule ID 1977 //
3759      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3760      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3761      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3762      // (bitconvert:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] })
3763      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3764      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/67,
3765      // GIR_Coverage, 1977,
3766      GIR_Done,
3767    // Label 352: @6839
3768    GIM_Try, /*On fail goto*//*Label 353*/ 6860, // Rule ID 1978 //
3769      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3770      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3771      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3772      // (bitconvert:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src, MSA128W:{ *:[i32] })
3773      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3774      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/67,
3775      // GIR_Coverage, 1978,
3776      GIR_Done,
3777    // Label 353: @6860
3778    GIM_Try, /*On fail goto*//*Label 354*/ 6881, // Rule ID 1979 //
3779      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3780      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3781      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3782      // (bitconvert:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] })
3783      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3784      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/67,
3785      // GIR_Coverage, 1979,
3786      GIR_Done,
3787    // Label 354: @6881
3788    GIM_Try, /*On fail goto*//*Label 355*/ 6946, // Rule ID 1987 //
3789      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3790      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3791      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3792      // (bitconvert:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] })
3793      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
3794      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
3795      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3796      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3797      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3798      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3799      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
3800      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3801      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3802      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3803      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3804      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3805      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3806      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3807      GIR_EraseFromParent, /*InsnID*/0,
3808      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/67,
3809      // GIR_Coverage, 1987,
3810      GIR_Done,
3811    // Label 355: @6946
3812    GIM_Try, /*On fail goto*//*Label 356*/ 7011, // Rule ID 1988 //
3813      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3814      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3815      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3816      // (bitconvert:{ *:[v4f32] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] })
3817      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
3818      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
3819      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3820      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3821      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3822      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3823      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
3824      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3825      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3826      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3827      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3828      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3829      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3830      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3831      GIR_EraseFromParent, /*InsnID*/0,
3832      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/67,
3833      // GIR_Coverage, 1988,
3834      GIR_Done,
3835    // Label 356: @7011
3836    GIM_Try, /*On fail goto*//*Label 357*/ 7076, // Rule ID 1992 //
3837      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3838      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3839      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3840      // (bitconvert:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3841      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3842      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3843      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3844      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3845      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3846      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3847      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3848      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3849      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3850      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3851      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3852      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3853      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3854      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3855      GIR_EraseFromParent, /*InsnID*/0,
3856      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/67,
3857      // GIR_Coverage, 1992,
3858      GIR_Done,
3859    // Label 357: @7076
3860    GIM_Try, /*On fail goto*//*Label 358*/ 7141, // Rule ID 1993 //
3861      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3862      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3863      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3864      // (bitconvert:{ *:[v4f32] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3865      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3866      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3867      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3868      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3869      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3870      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3871      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3872      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3873      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3874      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3875      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3876      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3877      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3878      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3879      GIR_EraseFromParent, /*InsnID*/0,
3880      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/67,
3881      // GIR_Coverage, 1993,
3882      GIR_Done,
3883    // Label 358: @7141
3884    GIM_Try, /*On fail goto*//*Label 359*/ 7206, // Rule ID 1997 //
3885      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3886      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3887      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3888      // (bitconvert:{ *:[v4i32] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3889      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3890      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3891      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3892      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3893      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3894      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3895      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3896      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3897      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3898      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3899      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3900      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3901      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3902      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3903      GIR_EraseFromParent, /*InsnID*/0,
3904      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/67,
3905      // GIR_Coverage, 1997,
3906      GIR_Done,
3907    // Label 359: @7206
3908    GIM_Try, /*On fail goto*//*Label 360*/ 7271, // Rule ID 1998 //
3909      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3910      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3911      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3912      // (bitconvert:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3913      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3914      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3915      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3916      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3917      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3918      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3919      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3920      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3921      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3922      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3923      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3924      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3925      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3926      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3927      GIR_EraseFromParent, /*InsnID*/0,
3928      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/67,
3929      // GIR_Coverage, 1998,
3930      GIR_Done,
3931    // Label 360: @7271
3932    GIM_Try, /*On fail goto*//*Label 361*/ 7336, // Rule ID 2014 //
3933      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3934      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3935      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3936      // (bitconvert:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3937      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3938      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3939      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3940      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3941      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3942      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3943      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3944      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3945      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3946      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3947      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3948      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3949      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3950      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3951      GIR_EraseFromParent, /*InsnID*/0,
3952      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/67,
3953      // GIR_Coverage, 2014,
3954      GIR_Done,
3955    // Label 361: @7336
3956    GIM_Try, /*On fail goto*//*Label 362*/ 7401, // Rule ID 2015 //
3957      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3958      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3959      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3960      // (bitconvert:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3961      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3962      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3963      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3964      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3965      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3966      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3967      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3968      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3969      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3970      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3971      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3972      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3973      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3974      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3975      GIR_EraseFromParent, /*InsnID*/0,
3976      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/67,
3977      // GIR_Coverage, 2015,
3978      GIR_Done,
3979    // Label 362: @7401
3980    GIM_Try, /*On fail goto*//*Label 363*/ 7466, // Rule ID 2019 //
3981      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3982      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3983      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3984      // (bitconvert:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3985      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3986      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3987      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3988      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3989      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3990      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3991      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3992      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3993      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3994      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3995      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3996      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3997      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3998      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3999      GIR_EraseFromParent, /*InsnID*/0,
4000      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/67,
4001      // GIR_Coverage, 2019,
4002      GIR_Done,
4003    // Label 363: @7466
4004    GIM_Try, /*On fail goto*//*Label 364*/ 7531, // Rule ID 2020 //
4005      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4006      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
4007      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
4008      // (bitconvert:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
4009      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
4010      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
4011      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4012      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4013      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4014      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4015      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
4016      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4017      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4018      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
4019      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4020      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4021      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4022      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4023      GIR_EraseFromParent, /*InsnID*/0,
4024      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/67,
4025      // GIR_Coverage, 2020,
4026      GIR_Done,
4027    // Label 364: @7531
4028    GIM_Reject,
4029    // Label 299: @7532
4030    GIM_Try, /*On fail goto*//*Label 365*/ 7553, // Rule ID 1948 //
4031      GIM_CheckFeatures, GIFBS_HasMSA,
4032      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
4033      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
4034      // (bitconvert:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] })
4035      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
4036      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/66,
4037      // GIR_Coverage, 1948,
4038      GIR_Done,
4039    // Label 365: @7553
4040    GIM_Try, /*On fail goto*//*Label 366*/ 7574, // Rule ID 1951 //
4041      GIM_CheckFeatures, GIFBS_HasMSA,
4042      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
4043      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
4044      // (bitconvert:{ *:[v8f16] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8f16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] })
4045      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
4046      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/66,
4047      // GIR_Coverage, 1951,
4048      GIR_Done,
4049    // Label 366: @7574
4050    GIM_Try, /*On fail goto*//*Label 367*/ 7595, // Rule ID 1960 //
4051      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
4052      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
4053      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
4054      // (bitconvert:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$src, MSA128H:{ *:[i32] })
4055      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
4056      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/66,
4057      // GIR_Coverage, 1960,
4058      GIR_Done,
4059    // Label 367: @7595
4060    GIM_Try, /*On fail goto*//*Label 368*/ 7616, // Rule ID 1961 //
4061      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
4062      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
4063      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
4064      // (bitconvert:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src, MSA128H:{ *:[i32] })
4065      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
4066      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/66,
4067      // GIR_Coverage, 1961,
4068      GIR_Done,
4069    // Label 368: @7616
4070    GIM_Try, /*On fail goto*//*Label 369*/ 7637, // Rule ID 1962 //
4071      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
4072      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
4073      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
4074      // (bitconvert:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src, MSA128H:{ *:[i32] })
4075      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
4076      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/66,
4077      // GIR_Coverage, 1962,
4078      GIR_Done,
4079    // Label 369: @7637
4080    GIM_Try, /*On fail goto*//*Label 370*/ 7658, // Rule ID 1963 //
4081      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
4082      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
4083      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
4084      // (bitconvert:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src, MSA128H:{ *:[i32] })
4085      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
4086      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/66,
4087      // GIR_Coverage, 1963,
4088      GIR_Done,
4089    // Label 370: @7658
4090    GIM_Try, /*On fail goto*//*Label 371*/ 7679, // Rule ID 1964 //
4091      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
4092      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
4093      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
4094      // (bitconvert:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src, MSA128H:{ *:[i32] })
4095      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
4096      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/66,
4097      // GIR_Coverage, 1964,
4098      GIR_Done,
4099    // Label 371: @7679
4100    GIM_Try, /*On fail goto*//*Label 372*/ 7744, // Rule ID 1985 //
4101      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4102      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
4103      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
4104      // (bitconvert:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
4105      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
4106      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
4107      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4108      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4109      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4110      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4111      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
4112      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4113      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4114      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
4115      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4116      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4117      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4118      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4119      GIR_EraseFromParent, /*InsnID*/0,
4120      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/66,
4121      // GIR_Coverage, 1985,
4122      GIR_Done,
4123    // Label 372: @7744
4124    GIM_Try, /*On fail goto*//*Label 373*/ 7809, // Rule ID 1986 //
4125      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4126      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
4127      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
4128      // (bitconvert:{ *:[v8f16] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
4129      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
4130      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
4131      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4132      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4133      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4134      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4135      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
4136      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4137      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4138      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
4139      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4140      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4141      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4142      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4143      GIR_EraseFromParent, /*InsnID*/0,
4144      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/66,
4145      // GIR_Coverage, 1986,
4146      GIR_Done,
4147    // Label 373: @7809
4148    GIM_Try, /*On fail goto*//*Label 374*/ 7874, // Rule ID 2002 //
4149      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4150      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
4151      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
4152      // (bitconvert:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
4153      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
4154      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
4155      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4156      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4157      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4158      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4159      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
4160      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4161      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4162      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
4163      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4164      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4165      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4166      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4167      GIR_EraseFromParent, /*InsnID*/0,
4168      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/66,
4169      // GIR_Coverage, 2002,
4170      GIR_Done,
4171    // Label 374: @7874
4172    GIM_Try, /*On fail goto*//*Label 375*/ 7939, // Rule ID 2003 //
4173      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4174      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
4175      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
4176      // (bitconvert:{ *:[v8f16] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
4177      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
4178      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
4179      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4180      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4181      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4182      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4183      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
4184      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4185      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4186      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
4187      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4188      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4189      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4190      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4191      GIR_EraseFromParent, /*InsnID*/0,
4192      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/66,
4193      // GIR_Coverage, 2003,
4194      GIR_Done,
4195    // Label 375: @7939
4196    GIM_Try, /*On fail goto*//*Label 376*/ 8004, // Rule ID 2007 //
4197      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4198      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
4199      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
4200      // (bitconvert:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
4201      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
4202      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
4203      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4204      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4205      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4206      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4207      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
4208      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4209      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4210      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
4211      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4212      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4213      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4214      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4215      GIR_EraseFromParent, /*InsnID*/0,
4216      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/66,
4217      // GIR_Coverage, 2007,
4218      GIR_Done,
4219    // Label 376: @8004
4220    GIM_Try, /*On fail goto*//*Label 377*/ 8069, // Rule ID 2008 //
4221      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4222      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
4223      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
4224      // (bitconvert:{ *:[v8f16] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
4225      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
4226      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
4227      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4228      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4229      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4230      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4231      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
4232      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4233      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4234      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
4235      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4236      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4237      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4238      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4239      GIR_EraseFromParent, /*InsnID*/0,
4240      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/66,
4241      // GIR_Coverage, 2008,
4242      GIR_Done,
4243    // Label 377: @8069
4244    GIM_Try, /*On fail goto*//*Label 378*/ 8134, // Rule ID 2012 //
4245      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4246      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
4247      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
4248      // (bitconvert:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
4249      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
4250      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
4251      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4252      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4253      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4254      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4255      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
4256      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4257      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4258      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
4259      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4260      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4261      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4262      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4263      GIR_EraseFromParent, /*InsnID*/0,
4264      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/66,
4265      // GIR_Coverage, 2012,
4266      GIR_Done,
4267    // Label 378: @8134
4268    GIM_Try, /*On fail goto*//*Label 379*/ 8199, // Rule ID 2013 //
4269      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4270      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
4271      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
4272      // (bitconvert:{ *:[v8f16] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
4273      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
4274      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
4275      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4276      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4277      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4278      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4279      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
4280      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4281      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4282      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
4283      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4284      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4285      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4286      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4287      GIR_EraseFromParent, /*InsnID*/0,
4288      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/66,
4289      // GIR_Coverage, 2013,
4290      GIR_Done,
4291    // Label 379: @8199
4292    GIM_Try, /*On fail goto*//*Label 380*/ 8264, // Rule ID 2017 //
4293      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4294      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
4295      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
4296      // (bitconvert:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
4297      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
4298      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
4299      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4300      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4301      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4302      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4303      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
4304      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4305      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4306      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
4307      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4308      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4309      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4310      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4311      GIR_EraseFromParent, /*InsnID*/0,
4312      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/66,
4313      // GIR_Coverage, 2017,
4314      GIR_Done,
4315    // Label 380: @8264
4316    GIM_Try, /*On fail goto*//*Label 381*/ 8329, // Rule ID 2018 //
4317      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4318      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
4319      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
4320      // (bitconvert:{ *:[v8f16] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
4321      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
4322      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
4323      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4324      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4325      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4326      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4327      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
4328      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4329      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4330      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
4331      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4332      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4333      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4334      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4335      GIR_EraseFromParent, /*InsnID*/0,
4336      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/66,
4337      // GIR_Coverage, 2018,
4338      GIR_Done,
4339    // Label 381: @8329
4340    GIM_Reject,
4341    // Label 300: @8330
4342    GIM_Try, /*On fail goto*//*Label 382*/ 8351, // Rule ID 1954 //
4343      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
4344      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
4345      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4346      // (bitconvert:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src, MSA128B:{ *:[i32] })
4347      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
4348      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/64,
4349      // GIR_Coverage, 1954,
4350      GIR_Done,
4351    // Label 382: @8351
4352    GIM_Try, /*On fail goto*//*Label 383*/ 8372, // Rule ID 1955 //
4353      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
4354      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
4355      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4356      // (bitconvert:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src, MSA128B:{ *:[i32] })
4357      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
4358      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/64,
4359      // GIR_Coverage, 1955,
4360      GIR_Done,
4361    // Label 383: @8372
4362    GIM_Try, /*On fail goto*//*Label 384*/ 8393, // Rule ID 1956 //
4363      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
4364      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
4365      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4366      // (bitconvert:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src, MSA128B:{ *:[i32] })
4367      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
4368      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/64,
4369      // GIR_Coverage, 1956,
4370      GIR_Done,
4371    // Label 384: @8393
4372    GIM_Try, /*On fail goto*//*Label 385*/ 8414, // Rule ID 1957 //
4373      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
4374      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
4375      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4376      // (bitconvert:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src, MSA128B:{ *:[i32] })
4377      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
4378      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/64,
4379      // GIR_Coverage, 1957,
4380      GIR_Done,
4381    // Label 385: @8414
4382    GIM_Try, /*On fail goto*//*Label 386*/ 8435, // Rule ID 1958 //
4383      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
4384      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
4385      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4386      // (bitconvert:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src, MSA128B:{ *:[i32] })
4387      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
4388      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/64,
4389      // GIR_Coverage, 1958,
4390      GIR_Done,
4391    // Label 386: @8435
4392    GIM_Try, /*On fail goto*//*Label 387*/ 8456, // Rule ID 1959 //
4393      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
4394      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
4395      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4396      // (bitconvert:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src, MSA128B:{ *:[i32] })
4397      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
4398      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/64,
4399      // GIR_Coverage, 1959,
4400      GIR_Done,
4401    // Label 387: @8456
4402    GIM_Try, /*On fail goto*//*Label 388*/ 8521, // Rule ID 1991 //
4403      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4404      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
4405      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4406      // (bitconvert:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
4407      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
4408      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
4409      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4410      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4411      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4412      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4413      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
4414      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4415      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4416      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
4417      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4418      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4419      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4420      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4421      GIR_EraseFromParent, /*InsnID*/0,
4422      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/64,
4423      // GIR_Coverage, 1991,
4424      GIR_Done,
4425    // Label 388: @8521
4426    GIM_Try, /*On fail goto*//*Label 389*/ 8586, // Rule ID 1996 //
4427      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4428      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
4429      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4430      // (bitconvert:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
4431      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
4432      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
4433      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4434      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4435      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4436      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4437      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
4438      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4439      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4440      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
4441      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4442      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4443      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4444      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4445      GIR_EraseFromParent, /*InsnID*/0,
4446      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/64,
4447      // GIR_Coverage, 1996,
4448      GIR_Done,
4449    // Label 389: @8586
4450    GIM_Try, /*On fail goto*//*Label 390*/ 8651, // Rule ID 2001 //
4451      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4452      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
4453      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4454      // (bitconvert:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128B:{ *:[i32] })
4455      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
4456      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
4457      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4458      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4459      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4460      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4461      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
4462      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4463      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4464      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
4465      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4466      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4467      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4468      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4469      GIR_EraseFromParent, /*InsnID*/0,
4470      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/64,
4471      // GIR_Coverage, 2001,
4472      GIR_Done,
4473    // Label 390: @8651
4474    GIM_Try, /*On fail goto*//*Label 391*/ 8716, // Rule ID 2006 //
4475      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4476      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
4477      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4478      // (bitconvert:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128B:{ *:[i32] })
4479      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
4480      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
4481      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4482      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4483      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4484      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4485      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
4486      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4487      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4488      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
4489      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4490      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4491      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4492      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4493      GIR_EraseFromParent, /*InsnID*/0,
4494      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/64,
4495      // GIR_Coverage, 2006,
4496      GIR_Done,
4497    // Label 391: @8716
4498    GIM_Try, /*On fail goto*//*Label 392*/ 8816, // Rule ID 2011 //
4499      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4500      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
4501      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4502      // (bitconvert:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
4503      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
4504      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
4505      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
4506      GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
4507      GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
4508      GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
4509      GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
4510      GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
4511      GIR_BuildMI, /*InsnID*/3, /*Opcode*/Mips::SHF_B,
4512      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
4513      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
4514      GIR_AddImm, /*InsnID*/3, /*Imm*/27,
4515      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
4516      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4517      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4518      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
4519      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4520      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
4521      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4522      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4523      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
4524      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4525      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4526      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4527      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4528      GIR_EraseFromParent, /*InsnID*/0,
4529      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/64,
4530      // GIR_Coverage, 2011,
4531      GIR_Done,
4532    // Label 392: @8816
4533    GIM_Try, /*On fail goto*//*Label 393*/ 8916, // Rule ID 2016 //
4534      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4535      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
4536      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4537      // (bitconvert:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
4538      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
4539      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
4540      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
4541      GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
4542      GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
4543      GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
4544      GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
4545      GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
4546      GIR_BuildMI, /*InsnID*/3, /*Opcode*/Mips::SHF_B,
4547      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
4548      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
4549      GIR_AddImm, /*InsnID*/3, /*Imm*/27,
4550      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
4551      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4552      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4553      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
4554      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4555      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
4556      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4557      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4558      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
4559      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4560      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4561      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4562      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4563      GIR_EraseFromParent, /*InsnID*/0,
4564      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/64,
4565      // GIR_Coverage, 2016,
4566      GIR_Done,
4567    // Label 393: @8916
4568    GIM_Reject,
4569    // Label 301: @8917
4570    GIM_Reject,
4571    // Label 12: @8918
4572    GIM_Try, /*On fail goto*//*Label 394*/ 8983, // Rule ID 1939 //
4573      GIM_CheckFeatures, GIFBS_HasDSP,
4574      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4575      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
4576      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
4577      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
4578      // MIs[0] Operand 1
4579      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
4580      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4581      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
4582      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4583      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4584      GIM_CheckIsSafeToFold, /*InsnID*/1,
4585      // (ld:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LWX:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index)
4586      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LWX,
4587      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4588      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // base
4589      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // index
4590      GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
4591      GIR_EraseFromParent, /*InsnID*/0,
4592      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4593      // GIR_Coverage, 1939,
4594      GIR_Done,
4595    // Label 394: @8983
4596    GIM_Reject,
4597    // Label 13: @8984
4598    GIM_Try, /*On fail goto*//*Label 395*/ 9049, // Rule ID 1938 //
4599      GIM_CheckFeatures, GIFBS_HasDSP,
4600      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4601      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2,
4602      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
4603      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
4604      // MIs[0] Operand 1
4605      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
4606      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4607      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
4608      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4609      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4610      GIM_CheckIsSafeToFold, /*InsnID*/1,
4611      // (ld:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>  =>  (LHX:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index)
4612      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LHX,
4613      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4614      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // base
4615      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // index
4616      GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
4617      GIR_EraseFromParent, /*InsnID*/0,
4618      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4619      // GIR_Coverage, 1938,
4620      GIR_Done,
4621    // Label 395: @9049
4622    GIM_Reject,
4623    // Label 14: @9050
4624    GIM_Try, /*On fail goto*//*Label 396*/ 9115, // Rule ID 1937 //
4625      GIM_CheckFeatures, GIFBS_HasDSP,
4626      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4627      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1,
4628      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
4629      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
4630      // MIs[0] Operand 1
4631      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
4632      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4633      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
4634      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4635      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4636      GIM_CheckIsSafeToFold, /*InsnID*/1,
4637      // (ld:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>  =>  (LBUX:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index)
4638      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LBUX,
4639      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4640      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // base
4641      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // index
4642      GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
4643      GIR_EraseFromParent, /*InsnID*/0,
4644      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4645      // GIR_Coverage, 1937,
4646      GIR_Done,
4647    // Label 396: @9115
4648    GIM_Reject,
4649    // Label 15: @9116
4650    GIM_Try, /*On fail goto*//*Label 397*/ 11310,
4651      GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
4652      GIM_Try, /*On fail goto*//*Label 398*/ 9168, // Rule ID 416 //
4653        GIM_CheckFeatures, GIFBS_HasDSP,
4654        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_qb,
4655        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
4656        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4657        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4658        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4659        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
4660        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt8,
4661        // MIs[1] Operand 1
4662        // No operand predicates
4663        GIM_CheckIsSafeToFold, /*InsnID*/1,
4664        // (intrinsic_wo_chain:{ *:[v4i8] } 4174:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immZExt8>>:$imm)  =>  (REPL_QB:{ *:[v4i8] } (imm:{ *:[i32] }):$imm)
4665        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPL_QB,
4666        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4667        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
4668        GIR_EraseFromParent, /*InsnID*/0,
4669        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4670        // GIR_Coverage, 416,
4671        GIR_Done,
4672      // Label 398: @9168
4673      GIM_Try, /*On fail goto*//*Label 399*/ 9215, // Rule ID 417 //
4674        GIM_CheckFeatures, GIFBS_HasDSP,
4675        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_ph,
4676        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4677        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4678        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4679        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4680        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
4681        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immSExt10,
4682        // MIs[1] Operand 1
4683        // No operand predicates
4684        GIM_CheckIsSafeToFold, /*InsnID*/1,
4685        // (intrinsic_wo_chain:{ *:[v2i16] } 4173:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immSExt10>>:$imm)  =>  (REPL_PH:{ *:[v2i16] } (imm:{ *:[i32] }):$imm)
4686        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPL_PH,
4687        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4688        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
4689        GIR_EraseFromParent, /*InsnID*/0,
4690        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4691        // GIR_Coverage, 417,
4692        GIR_Done,
4693      // Label 399: @9215
4694      GIM_Try, /*On fail goto*//*Label 400*/ 9262, // Rule ID 1270 //
4695        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
4696        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_ph,
4697        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4698        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4699        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4700        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4701        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
4702        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immSExt10,
4703        // MIs[1] Operand 1
4704        // No operand predicates
4705        GIM_CheckIsSafeToFold, /*InsnID*/1,
4706        // (intrinsic_wo_chain:{ *:[v2i16] } 4173:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immSExt10>>:$imm)  =>  (REPL_PH_MM:{ *:[v2i16] } (imm:{ *:[i32] }):$imm)
4707        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPL_PH_MM,
4708        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4709        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
4710        GIR_EraseFromParent, /*InsnID*/0,
4711        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4712        // GIR_Coverage, 1270,
4713        GIR_Done,
4714      // Label 400: @9262
4715      GIM_Try, /*On fail goto*//*Label 401*/ 9309, // Rule ID 1271 //
4716        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
4717        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_qb,
4718        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
4719        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4720        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4721        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4722        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
4723        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt8,
4724        // MIs[1] Operand 1
4725        // No operand predicates
4726        GIM_CheckIsSafeToFold, /*InsnID*/1,
4727        // (intrinsic_wo_chain:{ *:[v4i8] } 4174:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immZExt8>>:$imm)  =>  (REPL_QB_MM:{ *:[v4i8] } (imm:{ *:[i32] }):$imm)
4728        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPL_QB_MM,
4729        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
4730        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
4731        GIR_EraseFromParent, /*InsnID*/0,
4732        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4733        // GIR_Coverage, 1271,
4734        GIR_Done,
4735      // Label 401: @9309
4736      GIM_Try, /*On fail goto*//*Label 402*/ 9349, // Rule ID 350 //
4737        GIM_CheckFeatures, GIFBS_HasDSP,
4738        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_raddu_w_qb,
4739        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4740        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4741        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
4742        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4743        // (intrinsic_wo_chain:{ *:[i32] } 4171:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs)  =>  (RADDU_W_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs)
4744        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::RADDU_W_QB,
4745        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4746        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
4747        GIR_EraseFromParent, /*InsnID*/0,
4748        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4749        // GIR_Coverage, 350,
4750        GIR_Done,
4751      // Label 402: @9349
4752      GIM_Try, /*On fail goto*//*Label 403*/ 9389, // Rule ID 357 //
4753        GIM_CheckFeatures, GIFBS_HasDSP,
4754        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceq_w_phl,
4755        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4756        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
4757        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
4758        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4759        // (intrinsic_wo_chain:{ *:[i32] } 4153:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (PRECEQ_W_PHL:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rt)
4760        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQ_W_PHL,
4761        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4762        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4763        GIR_EraseFromParent, /*InsnID*/0,
4764        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4765        // GIR_Coverage, 357,
4766        GIR_Done,
4767      // Label 403: @9389
4768      GIM_Try, /*On fail goto*//*Label 404*/ 9429, // Rule ID 358 //
4769        GIM_CheckFeatures, GIFBS_HasDSP,
4770        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceq_w_phr,
4771        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4772        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
4773        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
4774        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4775        // (intrinsic_wo_chain:{ *:[i32] } 4154:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (PRECEQ_W_PHR:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rt)
4776        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQ_W_PHR,
4777        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4778        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4779        GIR_EraseFromParent, /*InsnID*/0,
4780        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4781        // GIR_Coverage, 358,
4782        GIR_Done,
4783      // Label 404: @9429
4784      GIM_Try, /*On fail goto*//*Label 405*/ 9469, // Rule ID 359 //
4785        GIM_CheckFeatures, GIFBS_HasDSP,
4786        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbl,
4787        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4788        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4789        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4790        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4791        // (intrinsic_wo_chain:{ *:[v2i16] } 4155:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PRECEQU_PH_QBL:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
4792        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBL,
4793        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4794        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4795        GIR_EraseFromParent, /*InsnID*/0,
4796        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4797        // GIR_Coverage, 359,
4798        GIR_Done,
4799      // Label 405: @9469
4800      GIM_Try, /*On fail goto*//*Label 406*/ 9509, // Rule ID 360 //
4801        GIM_CheckFeatures, GIFBS_HasDSP,
4802        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbr,
4803        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4804        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4805        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4806        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4807        // (intrinsic_wo_chain:{ *:[v2i16] } 4157:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PRECEQU_PH_QBR:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
4808        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBR,
4809        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4810        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4811        GIR_EraseFromParent, /*InsnID*/0,
4812        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4813        // GIR_Coverage, 360,
4814        GIR_Done,
4815      // Label 406: @9509
4816      GIM_Try, /*On fail goto*//*Label 407*/ 9549, // Rule ID 361 //
4817        GIM_CheckFeatures, GIFBS_HasDSP,
4818        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbla,
4819        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4820        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4821        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4822        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4823        // (intrinsic_wo_chain:{ *:[v2i16] } 4156:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PRECEQU_PH_QBLA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
4824        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBLA,
4825        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4826        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4827        GIR_EraseFromParent, /*InsnID*/0,
4828        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4829        // GIR_Coverage, 361,
4830        GIR_Done,
4831      // Label 407: @9549
4832      GIM_Try, /*On fail goto*//*Label 408*/ 9589, // Rule ID 362 //
4833        GIM_CheckFeatures, GIFBS_HasDSP,
4834        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbra,
4835        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4836        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4837        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4838        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4839        // (intrinsic_wo_chain:{ *:[v2i16] } 4158:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PRECEQU_PH_QBRA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
4840        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBRA,
4841        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4842        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4843        GIR_EraseFromParent, /*InsnID*/0,
4844        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4845        // GIR_Coverage, 362,
4846        GIR_Done,
4847      // Label 408: @9589
4848      GIM_Try, /*On fail goto*//*Label 409*/ 9629, // Rule ID 363 //
4849        GIM_CheckFeatures, GIFBS_HasDSP,
4850        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbl,
4851        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4852        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4853        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4854        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4855        // (intrinsic_wo_chain:{ *:[v2i16] } 4159:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PRECEU_PH_QBL:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
4856        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBL,
4857        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4858        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4859        GIR_EraseFromParent, /*InsnID*/0,
4860        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4861        // GIR_Coverage, 363,
4862        GIR_Done,
4863      // Label 409: @9629
4864      GIM_Try, /*On fail goto*//*Label 410*/ 9669, // Rule ID 364 //
4865        GIM_CheckFeatures, GIFBS_HasDSP,
4866        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbr,
4867        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4868        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4869        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4870        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4871        // (intrinsic_wo_chain:{ *:[v2i16] } 4161:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PRECEU_PH_QBR:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
4872        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBR,
4873        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4874        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4875        GIR_EraseFromParent, /*InsnID*/0,
4876        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4877        // GIR_Coverage, 364,
4878        GIR_Done,
4879      // Label 410: @9669
4880      GIM_Try, /*On fail goto*//*Label 411*/ 9709, // Rule ID 365 //
4881        GIM_CheckFeatures, GIFBS_HasDSP,
4882        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbla,
4883        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4884        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4885        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4886        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4887        // (intrinsic_wo_chain:{ *:[v2i16] } 4160:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PRECEU_PH_QBLA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
4888        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBLA,
4889        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4890        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4891        GIR_EraseFromParent, /*InsnID*/0,
4892        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4893        // GIR_Coverage, 365,
4894        GIR_Done,
4895      // Label 411: @9709
4896      GIM_Try, /*On fail goto*//*Label 412*/ 9749, // Rule ID 366 //
4897        GIM_CheckFeatures, GIFBS_HasDSP,
4898        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbra,
4899        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4900        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4901        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4902        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4903        // (intrinsic_wo_chain:{ *:[v2i16] } 4162:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PRECEU_PH_QBRA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
4904        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBRA,
4905        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4906        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4907        GIR_EraseFromParent, /*InsnID*/0,
4908        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4909        // GIR_Coverage, 366,
4910        GIR_Done,
4911      // Label 412: @9749
4912      GIM_Try, /*On fail goto*//*Label 413*/ 9789, // Rule ID 414 //
4913        GIM_CheckFeatures, GIFBS_HasDSP,
4914        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_bitrev,
4915        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4916        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4917        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
4918        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
4919        // (intrinsic_wo_chain:{ *:[i32] } 3729:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt)  =>  (BITREV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt)
4920        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BITREV,
4921        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4922        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4923        GIR_EraseFromParent, /*InsnID*/0,
4924        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4925        // GIR_Coverage, 414,
4926        GIR_Done,
4927      // Label 413: @9789
4928      GIM_Try, /*On fail goto*//*Label 414*/ 9829, // Rule ID 418 //
4929        GIM_CheckFeatures, GIFBS_HasDSP,
4930        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_qb,
4931        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
4932        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4933        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4934        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
4935        // (intrinsic_wo_chain:{ *:[v4i8] } 4174:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt)  =>  (REPLV_QB:{ *:[v4i8] } GPR32Opnd:{ *:[i32] }:$rt)
4936        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPLV_QB,
4937        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4938        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4939        GIR_EraseFromParent, /*InsnID*/0,
4940        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4941        // GIR_Coverage, 418,
4942        GIR_Done,
4943      // Label 414: @9829
4944      GIM_Try, /*On fail goto*//*Label 415*/ 9869, // Rule ID 419 //
4945        GIM_CheckFeatures, GIFBS_HasDSP,
4946        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_ph,
4947        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4948        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4949        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4950        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
4951        // (intrinsic_wo_chain:{ *:[v2i16] } 4173:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt)  =>  (REPLV_PH:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rt)
4952        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPLV_PH,
4953        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4954        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4955        GIR_EraseFromParent, /*InsnID*/0,
4956        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4957        // GIR_Coverage, 419,
4958        GIR_Done,
4959      // Label 415: @9869
4960      GIM_Try, /*On fail goto*//*Label 416*/ 9909, // Rule ID 664 //
4961        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4962        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fclass_w,
4963        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
4964        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
4965        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
4966        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
4967        // (intrinsic_wo_chain:{ *:[v4i32] } 3881:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws)  =>  (FCLASS_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
4968        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FCLASS_W,
4969        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4970        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4971        GIR_EraseFromParent, /*InsnID*/0,
4972        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4973        // GIR_Coverage, 664,
4974        GIR_Done,
4975      // Label 416: @9909
4976      GIM_Try, /*On fail goto*//*Label 417*/ 9949, // Rule ID 665 //
4977        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4978        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fclass_d,
4979        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
4980        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
4981        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
4982        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
4983        // (intrinsic_wo_chain:{ *:[v2i64] } 3880:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws)  =>  (FCLASS_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
4984        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FCLASS_D,
4985        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4986        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4987        GIR_EraseFromParent, /*InsnID*/0,
4988        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4989        // GIR_Coverage, 665,
4990        GIR_Done,
4991      // Label 417: @9949
4992      GIM_Try, /*On fail goto*//*Label 418*/ 9989, // Rule ID 688 //
4993        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4994        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fexupl_w,
4995        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
4996        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
4997        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
4998        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
4999        // (intrinsic_wo_chain:{ *:[v4f32] } 3907:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8f16] }:$ws)  =>  (FEXUPL_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8f16] }:$ws)
5000        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXUPL_W,
5001        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5002        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5003        GIR_EraseFromParent, /*InsnID*/0,
5004        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5005        // GIR_Coverage, 688,
5006        GIR_Done,
5007      // Label 418: @9989
5008      GIM_Try, /*On fail goto*//*Label 419*/ 10029, // Rule ID 689 //
5009        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5010        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fexupl_d,
5011        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
5012        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
5013        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
5014        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
5015        // (intrinsic_wo_chain:{ *:[v2f64] } 3906:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws)  =>  (FEXUPL_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4f32] }:$ws)
5016        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXUPL_D,
5017        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5018        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5019        GIR_EraseFromParent, /*InsnID*/0,
5020        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5021        // GIR_Coverage, 689,
5022        GIR_Done,
5023      // Label 419: @10029
5024      GIM_Try, /*On fail goto*//*Label 420*/ 10069, // Rule ID 690 //
5025        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5026        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fexupr_w,
5027        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
5028        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
5029        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
5030        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
5031        // (intrinsic_wo_chain:{ *:[v4f32] } 3909:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8f16] }:$ws)  =>  (FEXUPR_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8f16] }:$ws)
5032        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXUPR_W,
5033        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5034        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5035        GIR_EraseFromParent, /*InsnID*/0,
5036        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5037        // GIR_Coverage, 690,
5038        GIR_Done,
5039      // Label 420: @10069
5040      GIM_Try, /*On fail goto*//*Label 421*/ 10109, // Rule ID 691 //
5041        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5042        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fexupr_d,
5043        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
5044        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
5045        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
5046        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
5047        // (intrinsic_wo_chain:{ *:[v2f64] } 3908:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws)  =>  (FEXUPR_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4f32] }:$ws)
5048        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXUPR_D,
5049        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5050        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5051        GIR_EraseFromParent, /*InsnID*/0,
5052        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5053        // GIR_Coverage, 691,
5054        GIR_Done,
5055      // Label 421: @10109
5056      GIM_Try, /*On fail goto*//*Label 422*/ 10149, // Rule ID 696 //
5057        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5058        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ffql_w,
5059        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
5060        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
5061        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
5062        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
5063        // (intrinsic_wo_chain:{ *:[v4f32] } 3915:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws)  =>  (FFQL_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8i16] }:$ws)
5064        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FFQL_W,
5065        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5066        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5067        GIR_EraseFromParent, /*InsnID*/0,
5068        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5069        // GIR_Coverage, 696,
5070        GIR_Done,
5071      // Label 422: @10149
5072      GIM_Try, /*On fail goto*//*Label 423*/ 10189, // Rule ID 697 //
5073        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5074        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ffql_d,
5075        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
5076        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
5077        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
5078        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
5079        // (intrinsic_wo_chain:{ *:[v2f64] } 3914:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws)  =>  (FFQL_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4i32] }:$ws)
5080        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FFQL_D,
5081        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5082        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5083        GIR_EraseFromParent, /*InsnID*/0,
5084        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5085        // GIR_Coverage, 697,
5086        GIR_Done,
5087      // Label 423: @10189
5088      GIM_Try, /*On fail goto*//*Label 424*/ 10229, // Rule ID 698 //
5089        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5090        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ffqr_w,
5091        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
5092        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
5093        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
5094        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
5095        // (intrinsic_wo_chain:{ *:[v4f32] } 3917:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws)  =>  (FFQR_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8i16] }:$ws)
5096        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FFQR_W,
5097        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5098        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5099        GIR_EraseFromParent, /*InsnID*/0,
5100        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5101        // GIR_Coverage, 698,
5102        GIR_Done,
5103      // Label 424: @10229
5104      GIM_Try, /*On fail goto*//*Label 425*/ 10269, // Rule ID 699 //
5105        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5106        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ffqr_d,
5107        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
5108        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
5109        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
5110        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
5111        // (intrinsic_wo_chain:{ *:[v2f64] } 3916:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws)  =>  (FFQR_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4i32] }:$ws)
5112        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FFQR_D,
5113        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5114        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5115        GIR_EraseFromParent, /*InsnID*/0,
5116        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5117        // GIR_Coverage, 699,
5118        GIR_Done,
5119      // Label 425: @10269
5120      GIM_Try, /*On fail goto*//*Label 426*/ 10309, // Rule ID 724 //
5121        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5122        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_frcp_w,
5123        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
5124        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
5125        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
5126        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
5127        // (intrinsic_wo_chain:{ *:[v4f32] } 3939:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws)  =>  (FRCP_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
5128        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FRCP_W,
5129        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5130        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5131        GIR_EraseFromParent, /*InsnID*/0,
5132        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5133        // GIR_Coverage, 724,
5134        GIR_Done,
5135      // Label 426: @10309
5136      GIM_Try, /*On fail goto*//*Label 427*/ 10349, // Rule ID 725 //
5137        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5138        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_frcp_d,
5139        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
5140        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
5141        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
5142        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
5143        // (intrinsic_wo_chain:{ *:[v2f64] } 3938:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws)  =>  (FRCP_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
5144        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FRCP_D,
5145        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5146        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5147        GIR_EraseFromParent, /*InsnID*/0,
5148        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5149        // GIR_Coverage, 725,
5150        GIR_Done,
5151      // Label 427: @10349
5152      GIM_Try, /*On fail goto*//*Label 428*/ 10389, // Rule ID 726 //
5153        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5154        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_frsqrt_w,
5155        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
5156        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
5157        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
5158        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
5159        // (intrinsic_wo_chain:{ *:[v4f32] } 3943:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws)  =>  (FRSQRT_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
5160        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FRSQRT_W,
5161        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5162        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5163        GIR_EraseFromParent, /*InsnID*/0,
5164        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5165        // GIR_Coverage, 726,
5166        GIR_Done,
5167      // Label 428: @10389
5168      GIM_Try, /*On fail goto*//*Label 429*/ 10429, // Rule ID 727 //
5169        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5170        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_frsqrt_d,
5171        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
5172        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
5173        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
5174        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
5175        // (intrinsic_wo_chain:{ *:[v2f64] } 3942:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws)  =>  (FRSQRT_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
5176        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FRSQRT_D,
5177        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5178        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5179        GIR_EraseFromParent, /*InsnID*/0,
5180        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5181        // GIR_Coverage, 727,
5182        GIR_Done,
5183      // Label 429: @10429
5184      GIM_Try, /*On fail goto*//*Label 430*/ 10469, // Rule ID 754 //
5185        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5186        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ftint_s_w,
5187        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
5188        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
5189        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
5190        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
5191        // (intrinsic_wo_chain:{ *:[v4i32] } 3971:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws)  =>  (FTINT_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
5192        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FTINT_S_W,
5193        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5194        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5195        GIR_EraseFromParent, /*InsnID*/0,
5196        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5197        // GIR_Coverage, 754,
5198        GIR_Done,
5199      // Label 430: @10469
5200      GIM_Try, /*On fail goto*//*Label 431*/ 10509, // Rule ID 755 //
5201        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5202        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ftint_s_d,
5203        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
5204        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
5205        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
5206        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
5207        // (intrinsic_wo_chain:{ *:[v2i64] } 3970:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws)  =>  (FTINT_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
5208        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FTINT_S_D,
5209        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5210        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5211        GIR_EraseFromParent, /*InsnID*/0,
5212        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5213        // GIR_Coverage, 755,
5214        GIR_Done,
5215      // Label 431: @10509
5216      GIM_Try, /*On fail goto*//*Label 432*/ 10549, // Rule ID 756 //
5217        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5218        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ftint_u_w,
5219        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
5220        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
5221        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
5222        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
5223        // (intrinsic_wo_chain:{ *:[v4i32] } 3973:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws)  =>  (FTINT_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
5224        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FTINT_U_W,
5225        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5226        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5227        GIR_EraseFromParent, /*InsnID*/0,
5228        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5229        // GIR_Coverage, 756,
5230        GIR_Done,
5231      // Label 432: @10549
5232      GIM_Try, /*On fail goto*//*Label 433*/ 10589, // Rule ID 757 //
5233        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5234        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ftint_u_d,
5235        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
5236        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
5237        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
5238        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
5239        // (intrinsic_wo_chain:{ *:[v2i64] } 3972:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws)  =>  (FTINT_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
5240        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FTINT_U_D,
5241        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5242        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5243        GIR_EraseFromParent, /*InsnID*/0,
5244        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5245        // GIR_Coverage, 757,
5246        GIR_Done,
5247      // Label 433: @10589
5248      GIM_Try, /*On fail goto*//*Label 434*/ 10629, // Rule ID 892 //
5249        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5250        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_nloc_b,
5251        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
5252        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
5253        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
5254        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
5255        // (intrinsic_wo_chain:{ *:[v16i8] } 4126:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws)  =>  (NLOC_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws)
5256        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NLOC_B,
5257        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5258        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5259        GIR_EraseFromParent, /*InsnID*/0,
5260        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5261        // GIR_Coverage, 892,
5262        GIR_Done,
5263      // Label 434: @10629
5264      GIM_Try, /*On fail goto*//*Label 435*/ 10669, // Rule ID 893 //
5265        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5266        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_nloc_h,
5267        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
5268        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
5269        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
5270        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
5271        // (intrinsic_wo_chain:{ *:[v8i16] } 4128:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws)  =>  (NLOC_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws)
5272        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NLOC_H,
5273        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5274        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5275        GIR_EraseFromParent, /*InsnID*/0,
5276        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5277        // GIR_Coverage, 893,
5278        GIR_Done,
5279      // Label 435: @10669
5280      GIM_Try, /*On fail goto*//*Label 436*/ 10709, // Rule ID 894 //
5281        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5282        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_nloc_w,
5283        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
5284        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
5285        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
5286        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
5287        // (intrinsic_wo_chain:{ *:[v4i32] } 4129:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws)  =>  (NLOC_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws)
5288        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NLOC_W,
5289        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5290        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5291        GIR_EraseFromParent, /*InsnID*/0,
5292        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5293        // GIR_Coverage, 894,
5294        GIR_Done,
5295      // Label 436: @10709
5296      GIM_Try, /*On fail goto*//*Label 437*/ 10749, // Rule ID 895 //
5297        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5298        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_nloc_d,
5299        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
5300        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
5301        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
5302        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
5303        // (intrinsic_wo_chain:{ *:[v2i64] } 4127:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws)  =>  (NLOC_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws)
5304        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NLOC_D,
5305        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5306        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5307        GIR_EraseFromParent, /*InsnID*/0,
5308        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5309        // GIR_Coverage, 895,
5310        GIR_Done,
5311      // Label 437: @10749
5312      GIM_Try, /*On fail goto*//*Label 438*/ 10789, // Rule ID 1233 //
5313        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
5314        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceq_w_phl,
5315        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
5316        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
5317        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
5318        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
5319        // (intrinsic_wo_chain:{ *:[i32] } 4153:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs)  =>  (PRECEQ_W_PHL_MM:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs)
5320        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQ_W_PHL_MM,
5321        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
5322        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5323        GIR_EraseFromParent, /*InsnID*/0,
5324        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5325        // GIR_Coverage, 1233,
5326        GIR_Done,
5327      // Label 438: @10789
5328      GIM_Try, /*On fail goto*//*Label 439*/ 10829, // Rule ID 1234 //
5329        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
5330        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceq_w_phr,
5331        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
5332        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
5333        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
5334        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
5335        // (intrinsic_wo_chain:{ *:[i32] } 4154:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs)  =>  (PRECEQ_W_PHR_MM:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs)
5336        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQ_W_PHR_MM,
5337        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
5338        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5339        GIR_EraseFromParent, /*InsnID*/0,
5340        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5341        // GIR_Coverage, 1234,
5342        GIR_Done,
5343      // Label 439: @10829
5344      GIM_Try, /*On fail goto*//*Label 440*/ 10869, // Rule ID 1235 //
5345        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
5346        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbl,
5347        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
5348        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
5349        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5350        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
5351        // (intrinsic_wo_chain:{ *:[v2i16] } 4155:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs)  =>  (PRECEQU_PH_QBL_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
5352        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBL_MM,
5353        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
5354        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5355        GIR_EraseFromParent, /*InsnID*/0,
5356        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5357        // GIR_Coverage, 1235,
5358        GIR_Done,
5359      // Label 440: @10869
5360      GIM_Try, /*On fail goto*//*Label 441*/ 10909, // Rule ID 1236 //
5361        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
5362        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbla,
5363        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
5364        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
5365        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5366        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
5367        // (intrinsic_wo_chain:{ *:[v2i16] } 4156:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs)  =>  (PRECEQU_PH_QBLA_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
5368        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBLA_MM,
5369        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
5370        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5371        GIR_EraseFromParent, /*InsnID*/0,
5372        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5373        // GIR_Coverage, 1236,
5374        GIR_Done,
5375      // Label 441: @10909
5376      GIM_Try, /*On fail goto*//*Label 442*/ 10949, // Rule ID 1237 //
5377        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
5378        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbr,
5379        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
5380        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
5381        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5382        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
5383        // (intrinsic_wo_chain:{ *:[v2i16] } 4157:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs)  =>  (PRECEQU_PH_QBR_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
5384        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBR_MM,
5385        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
5386        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5387        GIR_EraseFromParent, /*InsnID*/0,
5388        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5389        // GIR_Coverage, 1237,
5390        GIR_Done,
5391      // Label 442: @10949
5392      GIM_Try, /*On fail goto*//*Label 443*/ 10989, // Rule ID 1238 //
5393        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
5394        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbra,
5395        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
5396        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
5397        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5398        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
5399        // (intrinsic_wo_chain:{ *:[v2i16] } 4158:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs)  =>  (PRECEQU_PH_QBRA_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
5400        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBRA_MM,
5401        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
5402        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5403        GIR_EraseFromParent, /*InsnID*/0,
5404        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5405        // GIR_Coverage, 1238,
5406        GIR_Done,
5407      // Label 443: @10989
5408      GIM_Try, /*On fail goto*//*Label 444*/ 11029, // Rule ID 1239 //
5409        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
5410        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbl,
5411        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
5412        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
5413        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5414        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
5415        // (intrinsic_wo_chain:{ *:[v2i16] } 4159:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs)  =>  (PRECEU_PH_QBL_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
5416        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBL_MM,
5417        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
5418        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5419        GIR_EraseFromParent, /*InsnID*/0,
5420        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5421        // GIR_Coverage, 1239,
5422        GIR_Done,
5423      // Label 444: @11029
5424      GIM_Try, /*On fail goto*//*Label 445*/ 11069, // Rule ID 1240 //
5425        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
5426        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbla,
5427        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
5428        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
5429        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5430        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
5431        // (intrinsic_wo_chain:{ *:[v2i16] } 4160:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs)  =>  (PRECEU_PH_QBLA_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
5432        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBLA_MM,
5433        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
5434        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5435        GIR_EraseFromParent, /*InsnID*/0,
5436        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5437        // GIR_Coverage, 1240,
5438        GIR_Done,
5439      // Label 445: @11069
5440      GIM_Try, /*On fail goto*//*Label 446*/ 11109, // Rule ID 1241 //
5441        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
5442        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbr,
5443        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
5444        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
5445        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5446        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
5447        // (intrinsic_wo_chain:{ *:[v2i16] } 4161:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs)  =>  (PRECEU_PH_QBR_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
5448        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBR_MM,
5449        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
5450        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5451        GIR_EraseFromParent, /*InsnID*/0,
5452        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5453        // GIR_Coverage, 1241,
5454        GIR_Done,
5455      // Label 446: @11109
5456      GIM_Try, /*On fail goto*//*Label 447*/ 11149, // Rule ID 1242 //
5457        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
5458        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbra,
5459        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
5460        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
5461        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5462        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
5463        // (intrinsic_wo_chain:{ *:[v2i16] } 4162:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs)  =>  (PRECEU_PH_QBRA_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
5464        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBRA_MM,
5465        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
5466        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5467        GIR_EraseFromParent, /*InsnID*/0,
5468        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5469        // GIR_Coverage, 1242,
5470        GIR_Done,
5471      // Label 447: @11149
5472      GIM_Try, /*On fail goto*//*Label 448*/ 11189, // Rule ID 1268 //
5473        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
5474        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_raddu_w_qb,
5475        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
5476        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
5477        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
5478        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
5479        // (intrinsic_wo_chain:{ *:[i32] } 4171:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs)  =>  (RADDU_W_QB_MM:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs)
5480        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::RADDU_W_QB_MM,
5481        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
5482        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5483        GIR_EraseFromParent, /*InsnID*/0,
5484        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5485        // GIR_Coverage, 1268,
5486        GIR_Done,
5487      // Label 448: @11189
5488      GIM_Try, /*On fail goto*//*Label 449*/ 11229, // Rule ID 1272 //
5489        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
5490        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_ph,
5491        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
5492        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
5493        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5494        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
5495        // (intrinsic_wo_chain:{ *:[v2i16] } 4173:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs)  =>  (REPLV_PH_MM:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs)
5496        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPLV_PH_MM,
5497        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
5498        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5499        GIR_EraseFromParent, /*InsnID*/0,
5500        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5501        // GIR_Coverage, 1272,
5502        GIR_Done,
5503      // Label 449: @11229
5504      GIM_Try, /*On fail goto*//*Label 450*/ 11269, // Rule ID 1273 //
5505        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
5506        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_qb,
5507        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
5508        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
5509        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5510        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
5511        // (intrinsic_wo_chain:{ *:[v4i8] } 4174:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs)  =>  (REPLV_QB_MM:{ *:[v4i8] } GPR32Opnd:{ *:[i32] }:$rs)
5512        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPLV_QB_MM,
5513        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
5514        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5515        GIR_EraseFromParent, /*InsnID*/0,
5516        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5517        // GIR_Coverage, 1273,
5518        GIR_Done,
5519      // Label 450: @11269
5520      GIM_Try, /*On fail goto*//*Label 451*/ 11309, // Rule ID 1283 //
5521        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
5522        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_bitrev,
5523        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
5524        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
5525        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
5526        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
5527        // (intrinsic_wo_chain:{ *:[i32] } 3729:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs)  =>  (BITREV_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
5528        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BITREV_MM,
5529        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
5530        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5531        GIR_EraseFromParent, /*InsnID*/0,
5532        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5533        // GIR_Coverage, 1283,
5534        GIR_Done,
5535      // Label 451: @11309
5536      GIM_Reject,
5537    // Label 397: @11310
5538    GIM_Try, /*On fail goto*//*Label 452*/ 22386,
5539      GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
5540      GIM_Try, /*On fail goto*//*Label 453*/ 11374, // Rule ID 373 //
5541        GIM_CheckFeatures, GIFBS_HasDSP,
5542        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_ph,
5543        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
5544        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
5545        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5546        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5547        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
5548        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
5549        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
5550        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt4,
5551        // MIs[1] Operand 1
5552        // No operand predicates
5553        GIM_CheckIsSafeToFold, /*InsnID*/1,
5554        // (intrinsic_wo_chain:{ *:[v2i16] } 4193:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$rs_sa)  =>  (SHRA_R_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, (imm:{ *:[i32] }):$rs_sa)
5555        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_R_PH,
5556        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
5557        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
5558        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa
5559        GIR_EraseFromParent, /*InsnID*/0,
5560        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5561        // GIR_Coverage, 373,
5562        GIR_Done,
5563      // Label 453: @11374
5564      GIM_Try, /*On fail goto*//*Label 454*/ 11433, // Rule ID 377 //
5565        GIM_CheckFeatures, GIFBS_HasDSP,
5566        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_w,
5567        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
5568        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
5569        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5570        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
5571        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
5572        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
5573        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
5574        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
5575        // MIs[1] Operand 1
5576        // No operand predicates
5577        GIM_CheckIsSafeToFold, /*InsnID*/1,
5578        // (intrinsic_wo_chain:{ *:[i32] } 4195:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$rs_sa)  =>  (SHRA_R_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$rs_sa)
5579        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_R_W,
5580        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
5581        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
5582        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa
5583        GIR_EraseFromParent, /*InsnID*/0,
5584        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5585        // GIR_Coverage, 377,
5586        GIR_Done,
5587      // Label 454: @11433
5588      GIM_Try, /*On fail goto*//*Label 455*/ 11492, // Rule ID 468 //
5589        GIM_CheckFeatures, GIFBS_HasDSPR2,
5590        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_qb,
5591        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
5592        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
5593        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5594        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5595        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
5596        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
5597        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
5598        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt3,
5599        // MIs[1] Operand 1
5600        // No operand predicates
5601        GIM_CheckIsSafeToFold, /*InsnID*/1,
5602        // (intrinsic_wo_chain:{ *:[v4i8] } 4194:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$rs_sa)  =>  (SHRA_R_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, (imm:{ *:[i32] }):$rs_sa)
5603        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_R_QB,
5604        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
5605        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
5606        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa
5607        GIR_EraseFromParent, /*InsnID*/0,
5608        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5609        // GIR_Coverage, 468,
5610        GIR_Done,
5611      // Label 455: @11492
5612      GIM_Try, /*On fail goto*//*Label 456*/ 11551, // Rule ID 1227 //
5613        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
5614        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_ph,
5615        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
5616        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
5617        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5618        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5619        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
5620        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
5621        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
5622        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt4,
5623        // MIs[1] Operand 1
5624        // No operand predicates
5625        GIM_CheckIsSafeToFold, /*InsnID*/1,
5626        // (intrinsic_wo_chain:{ *:[v2i16] } 4193:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$sa)  =>  (SHRA_R_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, (imm:{ *:[i32] }):$sa)
5627        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_R_PH_MM,
5628        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
5629        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5630        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
5631        GIR_EraseFromParent, /*InsnID*/0,
5632        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5633        // GIR_Coverage, 1227,
5634        GIR_Done,
5635      // Label 456: @11551
5636      GIM_Try, /*On fail goto*//*Label 457*/ 11610, // Rule ID 1231 //
5637        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
5638        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_w,
5639        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
5640        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
5641        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5642        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
5643        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
5644        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
5645        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
5646        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
5647        // MIs[1] Operand 1
5648        // No operand predicates
5649        GIM_CheckIsSafeToFold, /*InsnID*/1,
5650        // (intrinsic_wo_chain:{ *:[i32] } 4195:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$sa)  =>  (SHRA_R_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa)
5651        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_R_W_MM,
5652        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
5653        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5654        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
5655        GIR_EraseFromParent, /*InsnID*/0,
5656        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5657        // GIR_Coverage, 1231,
5658        GIR_Done,
5659      // Label 457: @11610
5660      GIM_Try, /*On fail goto*//*Label 458*/ 11669, // Rule ID 1306 //
5661        GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
5662        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_qb,
5663        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
5664        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
5665        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5666        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5667        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
5668        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
5669        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
5670        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt3,
5671        // MIs[1] Operand 1
5672        // No operand predicates
5673        GIM_CheckIsSafeToFold, /*InsnID*/1,
5674        // (intrinsic_wo_chain:{ *:[v4i8] } 4194:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$sa)  =>  (SHRA_R_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, (imm:{ *:[i32] }):$sa)
5675        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_R_QB_MMR2,
5676        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
5677        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5678        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
5679        GIR_EraseFromParent, /*InsnID*/0,
5680        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5681        // GIR_Coverage, 1306,
5682        GIR_Done,
5683      // Label 458: @11669
5684      GIM_Try, /*On fail goto*//*Label 459*/ 11716, // Rule ID 922 //
5685        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5686        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sat_s_b,
5687        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
5688        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
5689        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
5690        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
5691        // MIs[0] m
5692        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
5693        // (intrinsic_wo_chain:{ *:[v16i8] } 4175:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt3>>:$m)  =>  (SAT_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] }):$m)
5694        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_S_B,
5695        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5696        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5697        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // m
5698        GIR_EraseFromParent, /*InsnID*/0,
5699        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5700        // GIR_Coverage, 922,
5701        GIR_Done,
5702      // Label 459: @11716
5703      GIM_Try, /*On fail goto*//*Label 460*/ 11763, // Rule ID 923 //
5704        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5705        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sat_s_h,
5706        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
5707        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
5708        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
5709        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
5710        // MIs[0] m
5711        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
5712        // (intrinsic_wo_chain:{ *:[v8i16] } 4177:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt4>>:$m)  =>  (SAT_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] }):$m)
5713        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_S_H,
5714        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5715        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5716        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // m
5717        GIR_EraseFromParent, /*InsnID*/0,
5718        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5719        // GIR_Coverage, 923,
5720        GIR_Done,
5721      // Label 460: @11763
5722      GIM_Try, /*On fail goto*//*Label 461*/ 11810, // Rule ID 924 //
5723        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5724        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sat_s_w,
5725        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
5726        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
5727        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
5728        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
5729        // MIs[0] m
5730        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
5731        // (intrinsic_wo_chain:{ *:[v4i32] } 4178:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$m)  =>  (SAT_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] }):$m)
5732        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_S_W,
5733        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5734        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5735        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // m
5736        GIR_EraseFromParent, /*InsnID*/0,
5737        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5738        // GIR_Coverage, 924,
5739        GIR_Done,
5740      // Label 461: @11810
5741      GIM_Try, /*On fail goto*//*Label 462*/ 11857, // Rule ID 925 //
5742        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5743        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sat_s_d,
5744        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
5745        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
5746        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
5747        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
5748        // MIs[0] m
5749        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
5750        // (intrinsic_wo_chain:{ *:[v2i64] } 4176:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt6>>:$m)  =>  (SAT_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] }):$m)
5751        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_S_D,
5752        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5753        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5754        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // m
5755        GIR_EraseFromParent, /*InsnID*/0,
5756        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5757        // GIR_Coverage, 925,
5758        GIR_Done,
5759      // Label 462: @11857
5760      GIM_Try, /*On fail goto*//*Label 463*/ 11904, // Rule ID 926 //
5761        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5762        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sat_u_b,
5763        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
5764        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
5765        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
5766        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
5767        // MIs[0] m
5768        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
5769        // (intrinsic_wo_chain:{ *:[v16i8] } 4179:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt3>>:$m)  =>  (SAT_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] }):$m)
5770        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_U_B,
5771        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5772        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5773        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // m
5774        GIR_EraseFromParent, /*InsnID*/0,
5775        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5776        // GIR_Coverage, 926,
5777        GIR_Done,
5778      // Label 463: @11904
5779      GIM_Try, /*On fail goto*//*Label 464*/ 11951, // Rule ID 927 //
5780        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5781        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sat_u_h,
5782        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
5783        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
5784        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
5785        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
5786        // MIs[0] m
5787        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
5788        // (intrinsic_wo_chain:{ *:[v8i16] } 4181:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt4>>:$m)  =>  (SAT_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] }):$m)
5789        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_U_H,
5790        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5791        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5792        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // m
5793        GIR_EraseFromParent, /*InsnID*/0,
5794        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5795        // GIR_Coverage, 927,
5796        GIR_Done,
5797      // Label 464: @11951
5798      GIM_Try, /*On fail goto*//*Label 465*/ 11998, // Rule ID 928 //
5799        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5800        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sat_u_w,
5801        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
5802        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
5803        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
5804        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
5805        // MIs[0] m
5806        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
5807        // (intrinsic_wo_chain:{ *:[v4i32] } 4182:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$m)  =>  (SAT_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] }):$m)
5808        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_U_W,
5809        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5810        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5811        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // m
5812        GIR_EraseFromParent, /*InsnID*/0,
5813        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5814        // GIR_Coverage, 928,
5815        GIR_Done,
5816      // Label 465: @11998
5817      GIM_Try, /*On fail goto*//*Label 466*/ 12045, // Rule ID 929 //
5818        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5819        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sat_u_d,
5820        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
5821        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
5822        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
5823        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
5824        // MIs[0] m
5825        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
5826        // (intrinsic_wo_chain:{ *:[v2i64] } 4180:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt6>>:$m)  =>  (SAT_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] }):$m)
5827        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_U_D,
5828        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5829        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5830        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // m
5831        GIR_EraseFromParent, /*InsnID*/0,
5832        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5833        // GIR_Coverage, 929,
5834        GIR_Done,
5835      // Label 466: @12045
5836      GIM_Try, /*On fail goto*//*Label 467*/ 12092, // Rule ID 969 //
5837        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5838        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srari_b,
5839        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
5840        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
5841        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
5842        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
5843        // MIs[0] m
5844        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
5845        // (intrinsic_wo_chain:{ *:[v16i8] } 4234:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt3>>:$m)  =>  (SRARI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] }):$m)
5846        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRARI_B,
5847        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5848        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5849        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // m
5850        GIR_EraseFromParent, /*InsnID*/0,
5851        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5852        // GIR_Coverage, 969,
5853        GIR_Done,
5854      // Label 467: @12092
5855      GIM_Try, /*On fail goto*//*Label 468*/ 12139, // Rule ID 970 //
5856        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5857        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srari_h,
5858        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
5859        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
5860        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
5861        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
5862        // MIs[0] m
5863        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
5864        // (intrinsic_wo_chain:{ *:[v8i16] } 4236:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt4>>:$m)  =>  (SRARI_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] }):$m)
5865        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRARI_H,
5866        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5867        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5868        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // m
5869        GIR_EraseFromParent, /*InsnID*/0,
5870        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5871        // GIR_Coverage, 970,
5872        GIR_Done,
5873      // Label 468: @12139
5874      GIM_Try, /*On fail goto*//*Label 469*/ 12186, // Rule ID 971 //
5875        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5876        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srari_w,
5877        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
5878        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
5879        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
5880        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
5881        // MIs[0] m
5882        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
5883        // (intrinsic_wo_chain:{ *:[v4i32] } 4237:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$m)  =>  (SRARI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] }):$m)
5884        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRARI_W,
5885        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5886        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5887        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // m
5888        GIR_EraseFromParent, /*InsnID*/0,
5889        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5890        // GIR_Coverage, 971,
5891        GIR_Done,
5892      // Label 469: @12186
5893      GIM_Try, /*On fail goto*//*Label 470*/ 12233, // Rule ID 972 //
5894        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5895        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srari_d,
5896        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
5897        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
5898        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
5899        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
5900        // MIs[0] m
5901        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
5902        // (intrinsic_wo_chain:{ *:[v2i64] } 4235:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt6>>:$m)  =>  (SRARI_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] }):$m)
5903        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRARI_D,
5904        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5905        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5906        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // m
5907        GIR_EraseFromParent, /*InsnID*/0,
5908        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5909        // GIR_Coverage, 972,
5910        GIR_Done,
5911      // Label 470: @12233
5912      GIM_Try, /*On fail goto*//*Label 471*/ 12280, // Rule ID 985 //
5913        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5914        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srlri_b,
5915        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
5916        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
5917        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
5918        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
5919        // MIs[0] m
5920        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
5921        // (intrinsic_wo_chain:{ *:[v16i8] } 4250:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt3>>:$m)  =>  (SRLRI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] }):$m)
5922        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLRI_B,
5923        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5924        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5925        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // m
5926        GIR_EraseFromParent, /*InsnID*/0,
5927        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5928        // GIR_Coverage, 985,
5929        GIR_Done,
5930      // Label 471: @12280
5931      GIM_Try, /*On fail goto*//*Label 472*/ 12327, // Rule ID 986 //
5932        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5933        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srlri_h,
5934        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
5935        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
5936        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
5937        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
5938        // MIs[0] m
5939        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
5940        // (intrinsic_wo_chain:{ *:[v8i16] } 4252:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt4>>:$m)  =>  (SRLRI_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] }):$m)
5941        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLRI_H,
5942        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5943        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5944        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // m
5945        GIR_EraseFromParent, /*InsnID*/0,
5946        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5947        // GIR_Coverage, 986,
5948        GIR_Done,
5949      // Label 472: @12327
5950      GIM_Try, /*On fail goto*//*Label 473*/ 12374, // Rule ID 987 //
5951        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5952        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srlri_w,
5953        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
5954        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
5955        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
5956        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
5957        // MIs[0] m
5958        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
5959        // (intrinsic_wo_chain:{ *:[v4i32] } 4253:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$m)  =>  (SRLRI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] }):$m)
5960        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLRI_W,
5961        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5962        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5963        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // m
5964        GIR_EraseFromParent, /*InsnID*/0,
5965        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5966        // GIR_Coverage, 987,
5967        GIR_Done,
5968      // Label 473: @12374
5969      GIM_Try, /*On fail goto*//*Label 474*/ 12421, // Rule ID 988 //
5970        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5971        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srlri_d,
5972        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
5973        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
5974        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
5975        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
5976        // MIs[0] m
5977        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
5978        // (intrinsic_wo_chain:{ *:[v2i64] } 4251:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt6>>:$m)  =>  (SRLRI_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] }):$m)
5979        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLRI_D,
5980        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5981        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5982        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // m
5983        GIR_EraseFromParent, /*InsnID*/0,
5984        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5985        // GIR_Coverage, 988,
5986        GIR_Done,
5987      // Label 474: @12421
5988      GIM_Try, /*On fail goto*//*Label 475*/ 12476, // Rule ID 1893 //
5989        GIM_CheckFeatures, GIFBS_HasDSP,
5990        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_ph,
5991        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
5992        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
5993        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5994        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5995        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
5996        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
5997        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt4,
5998        // MIs[1] Operand 1
5999        // No operand predicates
6000        GIM_CheckIsSafeToFold, /*InsnID*/1,
6001        // (intrinsic_wo_chain:{ *:[v2i16] } 4191:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt)  =>  (SHRA_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt)
6002        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_PH,
6003        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6004        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
6005        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
6006        GIR_EraseFromParent, /*InsnID*/0,
6007        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6008        // GIR_Coverage, 1893,
6009        GIR_Done,
6010      // Label 475: @12476
6011      GIM_Try, /*On fail goto*//*Label 476*/ 12531, // Rule ID 1894 //
6012        GIM_CheckFeatures, GIFBS_HasDSPR2,
6013        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shrl_ph,
6014        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
6015        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
6016        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
6017        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6018        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
6019        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
6020        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt4,
6021        // MIs[1] Operand 1
6022        // No operand predicates
6023        GIM_CheckIsSafeToFold, /*InsnID*/1,
6024        // (intrinsic_wo_chain:{ *:[v2i16] } 4196:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt)  =>  (SHRL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt)
6025        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRL_PH,
6026        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6027        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
6028        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
6029        GIR_EraseFromParent, /*InsnID*/0,
6030        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6031        // GIR_Coverage, 1894,
6032        GIR_Done,
6033      // Label 476: @12531
6034      GIM_Try, /*On fail goto*//*Label 477*/ 12586, // Rule ID 1899 //
6035        GIM_CheckFeatures, GIFBS_HasDSPR2,
6036        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_qb,
6037        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
6038        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
6039        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
6040        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6041        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
6042        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
6043        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt3,
6044        // MIs[1] Operand 1
6045        // No operand predicates
6046        GIM_CheckIsSafeToFold, /*InsnID*/1,
6047        // (intrinsic_wo_chain:{ *:[v4i8] } 4192:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt)  =>  (SHRA_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt)
6048        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_QB,
6049        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6050        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
6051        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
6052        GIR_EraseFromParent, /*InsnID*/0,
6053        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6054        // GIR_Coverage, 1899,
6055        GIR_Done,
6056      // Label 477: @12586
6057      GIM_Try, /*On fail goto*//*Label 478*/ 12641, // Rule ID 1900 //
6058        GIM_CheckFeatures, GIFBS_HasDSP,
6059        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shrl_qb,
6060        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
6061        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
6062        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
6063        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6064        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
6065        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
6066        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt3,
6067        // MIs[1] Operand 1
6068        // No operand predicates
6069        GIM_CheckIsSafeToFold, /*InsnID*/1,
6070        // (intrinsic_wo_chain:{ *:[v4i8] } 4197:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt)  =>  (SHRL_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt)
6071        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRL_QB,
6072        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6073        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
6074        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
6075        GIR_EraseFromParent, /*InsnID*/0,
6076        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6077        // GIR_Coverage, 1900,
6078        GIR_Done,
6079      // Label 478: @12641
6080      GIM_Try, /*On fail goto*//*Label 479*/ 12693, // Rule ID 343 //
6081        GIM_CheckFeatures, GIFBS_HasDSP,
6082        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addu_s_qb,
6083        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
6084        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
6085        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
6086        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6087        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
6088        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
6089        // (intrinsic_wo_chain:{ *:[v4i8] } 3665:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (ADDU_S_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
6090        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDU_S_QB,
6091        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6092        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
6093        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
6094        GIR_EraseFromParent, /*InsnID*/0,
6095        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6096        // GIR_Coverage, 343,
6097        GIR_Done,
6098      // Label 479: @12693
6099      GIM_Try, /*On fail goto*//*Label 480*/ 12745, // Rule ID 344 //
6100        GIM_CheckFeatures, GIFBS_HasDSP,
6101        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subu_s_qb,
6102        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
6103        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
6104        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
6105        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6106        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
6107        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
6108        // (intrinsic_wo_chain:{ *:[v4i8] } 4284:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (SUBU_S_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
6109        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBU_S_QB,
6110        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6111        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
6112        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
6113        GIR_EraseFromParent, /*InsnID*/0,
6114        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6115        // GIR_Coverage, 344,
6116        GIR_Done,
6117      // Label 480: @12745
6118      GIM_Try, /*On fail goto*//*Label 481*/ 12797, // Rule ID 345 //
6119        GIM_CheckFeatures, GIFBS_HasDSP,
6120        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addq_s_ph,
6121        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
6122        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
6123        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
6124        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6125        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
6126        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
6127        // (intrinsic_wo_chain:{ *:[v2i16] } 3643:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (ADDQ_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
6128        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQ_S_PH,
6129        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6130        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
6131        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
6132        GIR_EraseFromParent, /*InsnID*/0,
6133        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6134        // GIR_Coverage, 345,
6135        GIR_Done,
6136      // Label 481: @12797
6137      GIM_Try, /*On fail goto*//*Label 482*/ 12849, // Rule ID 346 //
6138        GIM_CheckFeatures, GIFBS_HasDSP,
6139        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subq_s_ph,
6140        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
6141        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
6142        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
6143        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6144        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
6145        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
6146        // (intrinsic_wo_chain:{ *:[v2i16] } 4259:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (SUBQ_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
6147        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQ_S_PH,
6148        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6149        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
6150        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
6151        GIR_EraseFromParent, /*InsnID*/0,
6152        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6153        // GIR_Coverage, 346,
6154        GIR_Done,
6155      // Label 482: @12849
6156      GIM_Try, /*On fail goto*//*Label 483*/ 12901, // Rule ID 349 //
6157        GIM_CheckFeatures, GIFBS_HasDSP,
6158        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_modsub,
6159        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
6160        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
6161        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
6162        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
6163        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
6164        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
6165        // (intrinsic_wo_chain:{ *:[i32] } 4091:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MODSUB:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
6166        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MODSUB,
6167        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6168        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
6169        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
6170        GIR_EraseFromParent, /*InsnID*/0,
6171        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6172        // GIR_Coverage, 349,
6173        GIR_Done,
6174      // Label 483: @12901
6175      GIM_Try, /*On fail goto*//*Label 484*/ 12953, // Rule ID 353 //
6176        GIM_CheckFeatures, GIFBS_HasDSP,
6177        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precrq_qb_ph,
6178        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
6179        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
6180        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
6181        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6182        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
6183        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
6184        // (intrinsic_wo_chain:{ *:[v4i8] } 4167:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (PRECRQ_QB_PH:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
6185        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECRQ_QB_PH,
6186        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6187        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
6188        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
6189        GIR_EraseFromParent, /*InsnID*/0,
6190        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6191        // GIR_Coverage, 353,
6192        GIR_Done,
6193      // Label 484: @12953
6194      GIM_Try, /*On fail goto*//*Label 485*/ 13005, // Rule ID 354 //
6195        GIM_CheckFeatures, GIFBS_HasDSP,
6196        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precrq_ph_w,
6197        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
6198        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
6199        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
6200        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6201        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
6202        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
6203        // (intrinsic_wo_chain:{ *:[v2i16] } 4166:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (PRECRQ_PH_W:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
6204        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECRQ_PH_W,
6205        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6206        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
6207        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
6208        GIR_EraseFromParent, /*InsnID*/0,
6209        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6210        // GIR_Coverage, 354,
6211        GIR_Done,
6212      // Label 485: @13005
6213      GIM_Try, /*On fail goto*//*Label 486*/ 13057, // Rule ID 368 //
6214        GIM_CheckFeatures, GIFBS_HasDSP,
6215        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shrl_qb,
6216        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
6217        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
6218        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
6219        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6220        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
6221        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
6222        // (intrinsic_wo_chain:{ *:[v4i8] } 4197:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)  =>  (SHRLV_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
6223        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRLV_QB,
6224        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6225        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
6226        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa
6227        GIR_EraseFromParent, /*InsnID*/0,
6228        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6229        // GIR_Coverage, 368,
6230        GIR_Done,
6231      // Label 486: @13057
6232      GIM_Try, /*On fail goto*//*Label 487*/ 13109, // Rule ID 372 //
6233        GIM_CheckFeatures, GIFBS_HasDSP,
6234        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_ph,
6235        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
6236        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
6237        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
6238        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6239        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
6240        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
6241        // (intrinsic_wo_chain:{ *:[v2i16] } 4191:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)  =>  (SHRAV_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
6242        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_PH,
6243        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6244        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
6245        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa
6246        GIR_EraseFromParent, /*InsnID*/0,
6247        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6248        // GIR_Coverage, 372,
6249        GIR_Done,
6250      // Label 487: @13109
6251      GIM_Try, /*On fail goto*//*Label 488*/ 13161, // Rule ID 374 //
6252        GIM_CheckFeatures, GIFBS_HasDSP,
6253        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_ph,
6254        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
6255        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
6256        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
6257        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6258        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
6259        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
6260        // (intrinsic_wo_chain:{ *:[v2i16] } 4193:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)  =>  (SHRAV_R_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
6261        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_R_PH,
6262        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6263        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
6264        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa
6265        GIR_EraseFromParent, /*InsnID*/0,
6266        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6267        // GIR_Coverage, 374,
6268        GIR_Done,
6269      // Label 488: @13161
6270      GIM_Try, /*On fail goto*//*Label 489*/ 13213, // Rule ID 378 //
6271        GIM_CheckFeatures, GIFBS_HasDSP,
6272        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_w,
6273        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
6274        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
6275        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
6276        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
6277        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
6278        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
6279        // (intrinsic_wo_chain:{ *:[i32] } 4195:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)  =>  (SHRAV_R_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
6280        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_R_W,
6281        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6282        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
6283        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa
6284        GIR_EraseFromParent, /*InsnID*/0,
6285        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6286        // GIR_Coverage, 378,
6287        GIR_Done,
6288      // Label 489: @13213
6289      GIM_Try, /*On fail goto*//*Label 490*/ 13265, // Rule ID 415 //
6290        GIM_CheckFeatures, GIFBS_HasDSP,
6291        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_packrl_ph,
6292        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
6293        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
6294        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
6295        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6296        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
6297        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
6298        // (intrinsic_wo_chain:{ *:[v2i16] } 4138:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (PACKRL_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
6299        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PACKRL_PH,
6300        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6301        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
6302        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
6303        GIR_EraseFromParent, /*InsnID*/0,
6304        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6305        // GIR_Coverage, 415,
6306        GIR_Done,
6307      // Label 490: @13265
6308      GIM_Try, /*On fail goto*//*Label 491*/ 13317, // Rule ID 439 //
6309        GIM_CheckFeatures, GIFBS_HasDSPR2,
6310        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adduh_qb,
6311        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
6312        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
6313        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
6314        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6315        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
6316        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
6317        // (intrinsic_wo_chain:{ *:[v4i8] } 3666:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (ADDUH_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
6318        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDUH_QB,
6319        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6320        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
6321        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
6322        GIR_EraseFromParent, /*InsnID*/0,
6323        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6324        // GIR_Coverage, 439,
6325        GIR_Done,
6326      // Label 491: @13317
6327      GIM_Try, /*On fail goto*//*Label 492*/ 13369, // Rule ID 440 //
6328        GIM_CheckFeatures, GIFBS_HasDSPR2,
6329        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adduh_r_qb,
6330        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
6331        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
6332        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
6333        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6334        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
6335        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
6336        // (intrinsic_wo_chain:{ *:[v4i8] } 3667:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (ADDUH_R_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
6337        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDUH_R_QB,
6338        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6339        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
6340        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
6341        GIR_EraseFromParent, /*InsnID*/0,
6342        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6343        // GIR_Coverage, 440,
6344        GIR_Done,
6345      // Label 492: @13369
6346      GIM_Try, /*On fail goto*//*Label 493*/ 13421, // Rule ID 441 //
6347        GIM_CheckFeatures, GIFBS_HasDSPR2,
6348        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subuh_qb,
6349        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
6350        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
6351        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
6352        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6353        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
6354        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
6355        // (intrinsic_wo_chain:{ *:[v4i8] } 4285:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (SUBUH_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
6356        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBUH_QB,
6357        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6358        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
6359        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
6360        GIR_EraseFromParent, /*InsnID*/0,
6361        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6362        // GIR_Coverage, 441,
6363        GIR_Done,
6364      // Label 493: @13421
6365      GIM_Try, /*On fail goto*//*Label 494*/ 13473, // Rule ID 442 //
6366        GIM_CheckFeatures, GIFBS_HasDSPR2,
6367        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subuh_r_qb,
6368        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
6369        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
6370        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
6371        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6372        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
6373        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
6374        // (intrinsic_wo_chain:{ *:[v4i8] } 4286:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (SUBUH_R_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
6375        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBUH_R_QB,
6376        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6377        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
6378        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
6379        GIR_EraseFromParent, /*InsnID*/0,
6380        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6381        // GIR_Coverage, 442,
6382        GIR_Done,
6383      // Label 494: @13473
6384      GIM_Try, /*On fail goto*//*Label 495*/ 13525, // Rule ID 443 //
6385        GIM_CheckFeatures, GIFBS_HasDSPR2,
6386        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addqh_ph,
6387        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
6388        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
6389        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
6390        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6391        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
6392        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
6393        // (intrinsic_wo_chain:{ *:[v2i16] } 3645:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (ADDQH_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
6394        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_PH,
6395        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6396        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
6397        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
6398        GIR_EraseFromParent, /*InsnID*/0,
6399        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6400        // GIR_Coverage, 443,
6401        GIR_Done,
6402      // Label 495: @13525
6403      GIM_Try, /*On fail goto*//*Label 496*/ 13577, // Rule ID 444 //
6404        GIM_CheckFeatures, GIFBS_HasDSPR2,
6405        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addqh_r_ph,
6406        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
6407        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
6408        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
6409        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6410        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
6411        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
6412        // (intrinsic_wo_chain:{ *:[v2i16] } 3646:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (ADDQH_R_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
6413        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_R_PH,
6414        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6415        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
6416        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
6417        GIR_EraseFromParent, /*InsnID*/0,
6418        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6419        // GIR_Coverage, 444,
6420        GIR_Done,
6421      // Label 496: @13577
6422      GIM_Try, /*On fail goto*//*Label 497*/ 13629, // Rule ID 445 //
6423        GIM_CheckFeatures, GIFBS_HasDSPR2,
6424        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subqh_ph,
6425        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
6426        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
6427        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
6428        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6429        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
6430        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
6431        // (intrinsic_wo_chain:{ *:[v2i16] } 4261:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (SUBQH_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
6432        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQH_PH,
6433        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6434        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
6435        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
6436        GIR_EraseFromParent, /*InsnID*/0,
6437        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6438        // GIR_Coverage, 445,
6439        GIR_Done,
6440      // Label 497: @13629
6441      GIM_Try, /*On fail goto*//*Label 498*/ 13681, // Rule ID 446 //
6442        GIM_CheckFeatures, GIFBS_HasDSPR2,
6443        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subqh_r_ph,
6444        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
6445        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
6446        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
6447        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6448        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
6449        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
6450        // (intrinsic_wo_chain:{ *:[v2i16] } 4262:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (SUBQH_R_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
6451        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQH_R_PH,
6452        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6453        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
6454        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
6455        GIR_EraseFromParent, /*InsnID*/0,
6456        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6457        // GIR_Coverage, 446,
6458        GIR_Done,
6459      // Label 498: @13681
6460      GIM_Try, /*On fail goto*//*Label 499*/ 13733, // Rule ID 447 //
6461        GIM_CheckFeatures, GIFBS_HasDSPR2,
6462        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addqh_w,
6463        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
6464        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
6465        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
6466        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
6467        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
6468        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
6469        // (intrinsic_wo_chain:{ *:[i32] } 3648:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (ADDQH_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
6470        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_W,
6471        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6472        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
6473        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
6474        GIR_EraseFromParent, /*InsnID*/0,
6475        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6476        // GIR_Coverage, 447,
6477        GIR_Done,
6478      // Label 499: @13733
6479      GIM_Try, /*On fail goto*//*Label 500*/ 13785, // Rule ID 448 //
6480        GIM_CheckFeatures, GIFBS_HasDSPR2,
6481        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addqh_r_w,
6482        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
6483        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
6484        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
6485        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
6486        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
6487        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
6488        // (intrinsic_wo_chain:{ *:[i32] } 3647:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (ADDQH_R_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
6489        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_R_W,
6490        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6491        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
6492        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
6493        GIR_EraseFromParent, /*InsnID*/0,
6494        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6495        // GIR_Coverage, 448,
6496        GIR_Done,
6497      // Label 500: @13785
6498      GIM_Try, /*On fail goto*//*Label 501*/ 13837, // Rule ID 449 //
6499        GIM_CheckFeatures, GIFBS_HasDSPR2,
6500        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subqh_w,
6501        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
6502        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
6503        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
6504        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
6505        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
6506        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
6507        // (intrinsic_wo_chain:{ *:[i32] } 4264:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (SUBQH_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
6508        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQH_W,
6509        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6510        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
6511        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
6512        GIR_EraseFromParent, /*InsnID*/0,
6513        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6514        // GIR_Coverage, 449,
6515        GIR_Done,
6516      // Label 501: @13837
6517      GIM_Try, /*On fail goto*//*Label 502*/ 13889, // Rule ID 450 //
6518        GIM_CheckFeatures, GIFBS_HasDSPR2,
6519        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subqh_r_w,
6520        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
6521        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
6522        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
6523        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
6524        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
6525        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
6526        // (intrinsic_wo_chain:{ *:[i32] } 4263:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (SUBQH_R_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
6527        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQH_R_W,
6528        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6529        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
6530        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
6531        GIR_EraseFromParent, /*InsnID*/0,
6532        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6533        // GIR_Coverage, 450,
6534        GIR_Done,
6535      // Label 502: @13889
6536      GIM_Try, /*On fail goto*//*Label 503*/ 13941, // Rule ID 467 //
6537        GIM_CheckFeatures, GIFBS_HasDSPR2,
6538        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_qb,
6539        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
6540        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
6541        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
6542        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6543        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
6544        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
6545        // (intrinsic_wo_chain:{ *:[v4i8] } 4192:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)  =>  (SHRAV_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
6546        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_QB,
6547        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6548        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
6549        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa
6550        GIR_EraseFromParent, /*InsnID*/0,
6551        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6552        // GIR_Coverage, 467,
6553        GIR_Done,
6554      // Label 503: @13941
6555      GIM_Try, /*On fail goto*//*Label 504*/ 13993, // Rule ID 469 //
6556        GIM_CheckFeatures, GIFBS_HasDSPR2,
6557        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_qb,
6558        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
6559        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
6560        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
6561        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6562        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
6563        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
6564        // (intrinsic_wo_chain:{ *:[v4i8] } 4194:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)  =>  (SHRAV_R_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
6565        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_R_QB,
6566        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6567        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
6568        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa
6569        GIR_EraseFromParent, /*InsnID*/0,
6570        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6571        // GIR_Coverage, 469,
6572        GIR_Done,
6573      // Label 504: @13993
6574      GIM_Try, /*On fail goto*//*Label 505*/ 14045, // Rule ID 470 //
6575        GIM_CheckFeatures, GIFBS_HasDSPR2,
6576        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shrl_ph,
6577        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
6578        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
6579        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
6580        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6581        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
6582        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
6583        // (intrinsic_wo_chain:{ *:[v2i16] } 4196:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)  =>  (SHRLV_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
6584        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRLV_PH,
6585        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6586        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
6587        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa
6588        GIR_EraseFromParent, /*InsnID*/0,
6589        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6590        // GIR_Coverage, 470,
6591        GIR_Done,
6592      // Label 505: @14045
6593      GIM_Try, /*On fail goto*//*Label 506*/ 14097, // Rule ID 475 //
6594        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6595        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_add_a_b,
6596        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
6597        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
6598        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
6599        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
6600        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
6601        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
6602        // (intrinsic_wo_chain:{ *:[v16i8] } 3638:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (ADD_A_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
6603        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADD_A_B,
6604        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6605        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6606        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6607        GIR_EraseFromParent, /*InsnID*/0,
6608        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6609        // GIR_Coverage, 475,
6610        GIR_Done,
6611      // Label 506: @14097
6612      GIM_Try, /*On fail goto*//*Label 507*/ 14149, // Rule ID 476 //
6613        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6614        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_add_a_h,
6615        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
6616        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
6617        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
6618        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
6619        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
6620        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
6621        // (intrinsic_wo_chain:{ *:[v8i16] } 3640:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (ADD_A_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
6622        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADD_A_H,
6623        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6624        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6625        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6626        GIR_EraseFromParent, /*InsnID*/0,
6627        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6628        // GIR_Coverage, 476,
6629        GIR_Done,
6630      // Label 507: @14149
6631      GIM_Try, /*On fail goto*//*Label 508*/ 14201, // Rule ID 477 //
6632        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6633        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_add_a_w,
6634        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
6635        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
6636        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
6637        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
6638        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
6639        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
6640        // (intrinsic_wo_chain:{ *:[v4i32] } 3641:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (ADD_A_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
6641        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADD_A_W,
6642        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6643        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6644        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6645        GIR_EraseFromParent, /*InsnID*/0,
6646        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6647        // GIR_Coverage, 477,
6648        GIR_Done,
6649      // Label 508: @14201
6650      GIM_Try, /*On fail goto*//*Label 509*/ 14253, // Rule ID 478 //
6651        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6652        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_add_a_d,
6653        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
6654        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
6655        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
6656        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
6657        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
6658        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
6659        // (intrinsic_wo_chain:{ *:[v2i64] } 3639:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (ADD_A_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
6660        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADD_A_D,
6661        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6662        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6663        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6664        GIR_EraseFromParent, /*InsnID*/0,
6665        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6666        // GIR_Coverage, 478,
6667        GIR_Done,
6668      // Label 509: @14253
6669      GIM_Try, /*On fail goto*//*Label 510*/ 14305, // Rule ID 479 //
6670        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6671        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_a_b,
6672        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
6673        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
6674        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
6675        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
6676        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
6677        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
6678        // (intrinsic_wo_chain:{ *:[v16i8] } 3649:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (ADDS_A_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
6679        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_A_B,
6680        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6681        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6682        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6683        GIR_EraseFromParent, /*InsnID*/0,
6684        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6685        // GIR_Coverage, 479,
6686        GIR_Done,
6687      // Label 510: @14305
6688      GIM_Try, /*On fail goto*//*Label 511*/ 14357, // Rule ID 480 //
6689        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6690        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_a_h,
6691        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
6692        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
6693        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
6694        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
6695        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
6696        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
6697        // (intrinsic_wo_chain:{ *:[v8i16] } 3651:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (ADDS_A_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
6698        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_A_H,
6699        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6700        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6701        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6702        GIR_EraseFromParent, /*InsnID*/0,
6703        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6704        // GIR_Coverage, 480,
6705        GIR_Done,
6706      // Label 511: @14357
6707      GIM_Try, /*On fail goto*//*Label 512*/ 14409, // Rule ID 481 //
6708        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6709        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_a_w,
6710        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
6711        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
6712        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
6713        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
6714        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
6715        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
6716        // (intrinsic_wo_chain:{ *:[v4i32] } 3652:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (ADDS_A_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
6717        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_A_W,
6718        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6719        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6720        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6721        GIR_EraseFromParent, /*InsnID*/0,
6722        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6723        // GIR_Coverage, 481,
6724        GIR_Done,
6725      // Label 512: @14409
6726      GIM_Try, /*On fail goto*//*Label 513*/ 14461, // Rule ID 482 //
6727        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6728        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_a_d,
6729        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
6730        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
6731        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
6732        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
6733        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
6734        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
6735        // (intrinsic_wo_chain:{ *:[v2i64] } 3650:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (ADDS_A_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
6736        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_A_D,
6737        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6738        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6739        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6740        GIR_EraseFromParent, /*InsnID*/0,
6741        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6742        // GIR_Coverage, 482,
6743        GIR_Done,
6744      // Label 513: @14461
6745      GIM_Try, /*On fail goto*//*Label 514*/ 14513, // Rule ID 483 //
6746        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6747        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_s_b,
6748        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
6749        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
6750        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
6751        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
6752        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
6753        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
6754        // (intrinsic_wo_chain:{ *:[v16i8] } 3653:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (ADDS_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
6755        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_S_B,
6756        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6757        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6758        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6759        GIR_EraseFromParent, /*InsnID*/0,
6760        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6761        // GIR_Coverage, 483,
6762        GIR_Done,
6763      // Label 514: @14513
6764      GIM_Try, /*On fail goto*//*Label 515*/ 14565, // Rule ID 484 //
6765        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6766        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_s_h,
6767        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
6768        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
6769        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
6770        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
6771        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
6772        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
6773        // (intrinsic_wo_chain:{ *:[v8i16] } 3655:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (ADDS_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
6774        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_S_H,
6775        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6776        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6777        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6778        GIR_EraseFromParent, /*InsnID*/0,
6779        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6780        // GIR_Coverage, 484,
6781        GIR_Done,
6782      // Label 515: @14565
6783      GIM_Try, /*On fail goto*//*Label 516*/ 14617, // Rule ID 485 //
6784        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6785        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_s_w,
6786        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
6787        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
6788        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
6789        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
6790        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
6791        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
6792        // (intrinsic_wo_chain:{ *:[v4i32] } 3656:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (ADDS_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
6793        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_S_W,
6794        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6795        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6796        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6797        GIR_EraseFromParent, /*InsnID*/0,
6798        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6799        // GIR_Coverage, 485,
6800        GIR_Done,
6801      // Label 516: @14617
6802      GIM_Try, /*On fail goto*//*Label 517*/ 14669, // Rule ID 486 //
6803        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6804        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_s_d,
6805        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
6806        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
6807        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
6808        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
6809        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
6810        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
6811        // (intrinsic_wo_chain:{ *:[v2i64] } 3654:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (ADDS_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
6812        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_S_D,
6813        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6814        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6815        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6816        GIR_EraseFromParent, /*InsnID*/0,
6817        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6818        // GIR_Coverage, 486,
6819        GIR_Done,
6820      // Label 517: @14669
6821      GIM_Try, /*On fail goto*//*Label 518*/ 14721, // Rule ID 487 //
6822        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6823        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_u_b,
6824        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
6825        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
6826        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
6827        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
6828        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
6829        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
6830        // (intrinsic_wo_chain:{ *:[v16i8] } 3657:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (ADDS_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
6831        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_U_B,
6832        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6833        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6834        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6835        GIR_EraseFromParent, /*InsnID*/0,
6836        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6837        // GIR_Coverage, 487,
6838        GIR_Done,
6839      // Label 518: @14721
6840      GIM_Try, /*On fail goto*//*Label 519*/ 14773, // Rule ID 488 //
6841        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6842        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_u_h,
6843        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
6844        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
6845        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
6846        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
6847        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
6848        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
6849        // (intrinsic_wo_chain:{ *:[v8i16] } 3659:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (ADDS_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
6850        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_U_H,
6851        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6852        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6853        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6854        GIR_EraseFromParent, /*InsnID*/0,
6855        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6856        // GIR_Coverage, 488,
6857        GIR_Done,
6858      // Label 519: @14773
6859      GIM_Try, /*On fail goto*//*Label 520*/ 14825, // Rule ID 489 //
6860        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6861        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_u_w,
6862        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
6863        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
6864        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
6865        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
6866        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
6867        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
6868        // (intrinsic_wo_chain:{ *:[v4i32] } 3660:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (ADDS_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
6869        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_U_W,
6870        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6871        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6872        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6873        GIR_EraseFromParent, /*InsnID*/0,
6874        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6875        // GIR_Coverage, 489,
6876        GIR_Done,
6877      // Label 520: @14825
6878      GIM_Try, /*On fail goto*//*Label 521*/ 14877, // Rule ID 490 //
6879        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6880        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_u_d,
6881        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
6882        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
6883        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
6884        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
6885        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
6886        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
6887        // (intrinsic_wo_chain:{ *:[v2i64] } 3658:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (ADDS_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
6888        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_U_D,
6889        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6890        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6891        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6892        GIR_EraseFromParent, /*InsnID*/0,
6893        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6894        // GIR_Coverage, 490,
6895        GIR_Done,
6896      // Label 521: @14877
6897      GIM_Try, /*On fail goto*//*Label 522*/ 14929, // Rule ID 504 //
6898        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6899        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_asub_s_b,
6900        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
6901        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
6902        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
6903        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
6904        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
6905        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
6906        // (intrinsic_wo_chain:{ *:[v16i8] } 3680:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (ASUB_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
6907        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_S_B,
6908        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6909        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6910        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6911        GIR_EraseFromParent, /*InsnID*/0,
6912        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6913        // GIR_Coverage, 504,
6914        GIR_Done,
6915      // Label 522: @14929
6916      GIM_Try, /*On fail goto*//*Label 523*/ 14981, // Rule ID 505 //
6917        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6918        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_asub_s_h,
6919        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
6920        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
6921        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
6922        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
6923        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
6924        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
6925        // (intrinsic_wo_chain:{ *:[v8i16] } 3682:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (ASUB_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
6926        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_S_H,
6927        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6928        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6929        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6930        GIR_EraseFromParent, /*InsnID*/0,
6931        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6932        // GIR_Coverage, 505,
6933        GIR_Done,
6934      // Label 523: @14981
6935      GIM_Try, /*On fail goto*//*Label 524*/ 15033, // Rule ID 506 //
6936        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6937        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_asub_s_w,
6938        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
6939        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
6940        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
6941        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
6942        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
6943        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
6944        // (intrinsic_wo_chain:{ *:[v4i32] } 3683:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (ASUB_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
6945        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_S_W,
6946        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6947        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6948        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6949        GIR_EraseFromParent, /*InsnID*/0,
6950        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6951        // GIR_Coverage, 506,
6952        GIR_Done,
6953      // Label 524: @15033
6954      GIM_Try, /*On fail goto*//*Label 525*/ 15085, // Rule ID 507 //
6955        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6956        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_asub_s_d,
6957        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
6958        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
6959        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
6960        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
6961        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
6962        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
6963        // (intrinsic_wo_chain:{ *:[v2i64] } 3681:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (ASUB_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
6964        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_S_D,
6965        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6966        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6967        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6968        GIR_EraseFromParent, /*InsnID*/0,
6969        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6970        // GIR_Coverage, 507,
6971        GIR_Done,
6972      // Label 525: @15085
6973      GIM_Try, /*On fail goto*//*Label 526*/ 15137, // Rule ID 508 //
6974        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6975        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_asub_u_b,
6976        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
6977        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
6978        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
6979        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
6980        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
6981        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
6982        // (intrinsic_wo_chain:{ *:[v16i8] } 3684:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (ASUB_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
6983        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_U_B,
6984        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6985        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6986        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6987        GIR_EraseFromParent, /*InsnID*/0,
6988        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6989        // GIR_Coverage, 508,
6990        GIR_Done,
6991      // Label 526: @15137
6992      GIM_Try, /*On fail goto*//*Label 527*/ 15189, // Rule ID 509 //
6993        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6994        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_asub_u_h,
6995        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
6996        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
6997        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
6998        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
6999        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
7000        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
7001        // (intrinsic_wo_chain:{ *:[v8i16] } 3686:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (ASUB_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
7002        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_U_H,
7003        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7004        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7005        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7006        GIR_EraseFromParent, /*InsnID*/0,
7007        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7008        // GIR_Coverage, 509,
7009        GIR_Done,
7010      // Label 527: @15189
7011      GIM_Try, /*On fail goto*//*Label 528*/ 15241, // Rule ID 510 //
7012        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7013        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_asub_u_w,
7014        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7015        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7016        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7017        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7018        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7019        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7020        // (intrinsic_wo_chain:{ *:[v4i32] } 3687:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (ASUB_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
7021        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_U_W,
7022        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7023        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7024        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7025        GIR_EraseFromParent, /*InsnID*/0,
7026        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7027        // GIR_Coverage, 510,
7028        GIR_Done,
7029      // Label 528: @15241
7030      GIM_Try, /*On fail goto*//*Label 529*/ 15293, // Rule ID 511 //
7031        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7032        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_asub_u_d,
7033        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7034        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7035        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7036        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7037        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7038        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7039        // (intrinsic_wo_chain:{ *:[v2i64] } 3685:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (ASUB_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
7040        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_U_D,
7041        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7042        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7043        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7044        GIR_EraseFromParent, /*InsnID*/0,
7045        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7046        // GIR_Coverage, 511,
7047        GIR_Done,
7048      // Label 529: @15293
7049      GIM_Try, /*On fail goto*//*Label 530*/ 15345, // Rule ID 512 //
7050        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7051        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ave_s_b,
7052        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
7053        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
7054        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
7055        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
7056        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
7057        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
7058        // (intrinsic_wo_chain:{ *:[v16i8] } 3688:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (AVE_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
7059        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_S_B,
7060        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7061        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7062        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7063        GIR_EraseFromParent, /*InsnID*/0,
7064        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7065        // GIR_Coverage, 512,
7066        GIR_Done,
7067      // Label 530: @15345
7068      GIM_Try, /*On fail goto*//*Label 531*/ 15397, // Rule ID 513 //
7069        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7070        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ave_s_h,
7071        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
7072        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
7073        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
7074        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
7075        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
7076        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
7077        // (intrinsic_wo_chain:{ *:[v8i16] } 3690:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (AVE_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
7078        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_S_H,
7079        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7080        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7081        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7082        GIR_EraseFromParent, /*InsnID*/0,
7083        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7084        // GIR_Coverage, 513,
7085        GIR_Done,
7086      // Label 531: @15397
7087      GIM_Try, /*On fail goto*//*Label 532*/ 15449, // Rule ID 514 //
7088        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7089        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ave_s_w,
7090        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7091        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7092        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7093        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7094        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7095        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7096        // (intrinsic_wo_chain:{ *:[v4i32] } 3691:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (AVE_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
7097        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_S_W,
7098        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7099        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7100        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7101        GIR_EraseFromParent, /*InsnID*/0,
7102        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7103        // GIR_Coverage, 514,
7104        GIR_Done,
7105      // Label 532: @15449
7106      GIM_Try, /*On fail goto*//*Label 533*/ 15501, // Rule ID 515 //
7107        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7108        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ave_s_d,
7109        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7110        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7111        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7112        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7113        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7114        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7115        // (intrinsic_wo_chain:{ *:[v2i64] } 3689:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (AVE_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
7116        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_S_D,
7117        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7118        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7119        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7120        GIR_EraseFromParent, /*InsnID*/0,
7121        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7122        // GIR_Coverage, 515,
7123        GIR_Done,
7124      // Label 533: @15501
7125      GIM_Try, /*On fail goto*//*Label 534*/ 15553, // Rule ID 516 //
7126        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7127        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ave_u_b,
7128        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
7129        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
7130        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
7131        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
7132        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
7133        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
7134        // (intrinsic_wo_chain:{ *:[v16i8] } 3692:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (AVE_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
7135        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_U_B,
7136        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7137        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7138        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7139        GIR_EraseFromParent, /*InsnID*/0,
7140        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7141        // GIR_Coverage, 516,
7142        GIR_Done,
7143      // Label 534: @15553
7144      GIM_Try, /*On fail goto*//*Label 535*/ 15605, // Rule ID 517 //
7145        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7146        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ave_u_h,
7147        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
7148        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
7149        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
7150        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
7151        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
7152        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
7153        // (intrinsic_wo_chain:{ *:[v8i16] } 3694:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (AVE_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
7154        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_U_H,
7155        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7156        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7157        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7158        GIR_EraseFromParent, /*InsnID*/0,
7159        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7160        // GIR_Coverage, 517,
7161        GIR_Done,
7162      // Label 535: @15605
7163      GIM_Try, /*On fail goto*//*Label 536*/ 15657, // Rule ID 518 //
7164        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7165        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ave_u_w,
7166        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7167        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7168        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7169        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7170        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7171        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7172        // (intrinsic_wo_chain:{ *:[v4i32] } 3695:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (AVE_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
7173        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_U_W,
7174        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7175        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7176        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7177        GIR_EraseFromParent, /*InsnID*/0,
7178        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7179        // GIR_Coverage, 518,
7180        GIR_Done,
7181      // Label 536: @15657
7182      GIM_Try, /*On fail goto*//*Label 537*/ 15709, // Rule ID 519 //
7183        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7184        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ave_u_d,
7185        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7186        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7187        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7188        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7189        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7190        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7191        // (intrinsic_wo_chain:{ *:[v2i64] } 3693:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (AVE_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
7192        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_U_D,
7193        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7194        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7195        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7196        GIR_EraseFromParent, /*InsnID*/0,
7197        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7198        // GIR_Coverage, 519,
7199        GIR_Done,
7200      // Label 537: @15709
7201      GIM_Try, /*On fail goto*//*Label 538*/ 15761, // Rule ID 520 //
7202        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7203        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_aver_s_b,
7204        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
7205        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
7206        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
7207        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
7208        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
7209        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
7210        // (intrinsic_wo_chain:{ *:[v16i8] } 3696:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (AVER_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
7211        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_S_B,
7212        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7213        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7214        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7215        GIR_EraseFromParent, /*InsnID*/0,
7216        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7217        // GIR_Coverage, 520,
7218        GIR_Done,
7219      // Label 538: @15761
7220      GIM_Try, /*On fail goto*//*Label 539*/ 15813, // Rule ID 521 //
7221        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7222        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_aver_s_h,
7223        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
7224        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
7225        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
7226        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
7227        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
7228        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
7229        // (intrinsic_wo_chain:{ *:[v8i16] } 3698:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (AVER_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
7230        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_S_H,
7231        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7232        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7233        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7234        GIR_EraseFromParent, /*InsnID*/0,
7235        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7236        // GIR_Coverage, 521,
7237        GIR_Done,
7238      // Label 539: @15813
7239      GIM_Try, /*On fail goto*//*Label 540*/ 15865, // Rule ID 522 //
7240        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7241        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_aver_s_w,
7242        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7243        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7244        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7245        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7246        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7247        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7248        // (intrinsic_wo_chain:{ *:[v4i32] } 3699:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (AVER_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
7249        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_S_W,
7250        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7251        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7252        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7253        GIR_EraseFromParent, /*InsnID*/0,
7254        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7255        // GIR_Coverage, 522,
7256        GIR_Done,
7257      // Label 540: @15865
7258      GIM_Try, /*On fail goto*//*Label 541*/ 15917, // Rule ID 523 //
7259        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7260        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_aver_s_d,
7261        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7262        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7263        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7264        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7265        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7266        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7267        // (intrinsic_wo_chain:{ *:[v2i64] } 3697:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (AVER_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
7268        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_S_D,
7269        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7270        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7271        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7272        GIR_EraseFromParent, /*InsnID*/0,
7273        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7274        // GIR_Coverage, 523,
7275        GIR_Done,
7276      // Label 541: @15917
7277      GIM_Try, /*On fail goto*//*Label 542*/ 15969, // Rule ID 524 //
7278        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7279        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_aver_u_b,
7280        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
7281        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
7282        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
7283        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
7284        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
7285        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
7286        // (intrinsic_wo_chain:{ *:[v16i8] } 3700:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (AVER_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
7287        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_U_B,
7288        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7289        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7290        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7291        GIR_EraseFromParent, /*InsnID*/0,
7292        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7293        // GIR_Coverage, 524,
7294        GIR_Done,
7295      // Label 542: @15969
7296      GIM_Try, /*On fail goto*//*Label 543*/ 16021, // Rule ID 525 //
7297        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7298        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_aver_u_h,
7299        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
7300        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
7301        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
7302        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
7303        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
7304        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
7305        // (intrinsic_wo_chain:{ *:[v8i16] } 3702:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (AVER_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
7306        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_U_H,
7307        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7308        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7309        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7310        GIR_EraseFromParent, /*InsnID*/0,
7311        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7312        // GIR_Coverage, 525,
7313        GIR_Done,
7314      // Label 543: @16021
7315      GIM_Try, /*On fail goto*//*Label 544*/ 16073, // Rule ID 526 //
7316        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7317        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_aver_u_w,
7318        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7319        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7320        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7321        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7322        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7323        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7324        // (intrinsic_wo_chain:{ *:[v4i32] } 3703:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (AVER_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
7325        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_U_W,
7326        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7327        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7328        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7329        GIR_EraseFromParent, /*InsnID*/0,
7330        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7331        // GIR_Coverage, 526,
7332        GIR_Done,
7333      // Label 544: @16073
7334      GIM_Try, /*On fail goto*//*Label 545*/ 16125, // Rule ID 527 //
7335        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7336        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_aver_u_d,
7337        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7338        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7339        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7340        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7341        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7342        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7343        // (intrinsic_wo_chain:{ *:[v2i64] } 3701:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (AVER_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
7344        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_U_D,
7345        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7346        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7347        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7348        GIR_EraseFromParent, /*InsnID*/0,
7349        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7350        // GIR_Coverage, 527,
7351        GIR_Done,
7352      // Label 545: @16125
7353      GIM_Try, /*On fail goto*//*Label 546*/ 16177, // Rule ID 636 //
7354        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7355        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dotp_s_h,
7356        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
7357        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
7358        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
7359        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
7360        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
7361        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
7362        // (intrinsic_wo_chain:{ *:[v8i16] } 3835:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (DOTP_S_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
7363        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DOTP_S_H,
7364        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7365        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7366        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7367        GIR_EraseFromParent, /*InsnID*/0,
7368        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7369        // GIR_Coverage, 636,
7370        GIR_Done,
7371      // Label 546: @16177
7372      GIM_Try, /*On fail goto*//*Label 547*/ 16229, // Rule ID 637 //
7373        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7374        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dotp_s_w,
7375        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7376        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
7377        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
7378        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7379        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
7380        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
7381        // (intrinsic_wo_chain:{ *:[v4i32] } 3836:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (DOTP_S_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
7382        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DOTP_S_W,
7383        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7384        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7385        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7386        GIR_EraseFromParent, /*InsnID*/0,
7387        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7388        // GIR_Coverage, 637,
7389        GIR_Done,
7390      // Label 547: @16229
7391      GIM_Try, /*On fail goto*//*Label 548*/ 16281, // Rule ID 638 //
7392        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7393        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dotp_s_d,
7394        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7395        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7396        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7397        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7398        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7399        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7400        // (intrinsic_wo_chain:{ *:[v2i64] } 3834:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (DOTP_S_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
7401        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DOTP_S_D,
7402        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7403        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7404        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7405        GIR_EraseFromParent, /*InsnID*/0,
7406        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7407        // GIR_Coverage, 638,
7408        GIR_Done,
7409      // Label 548: @16281
7410      GIM_Try, /*On fail goto*//*Label 549*/ 16333, // Rule ID 639 //
7411        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7412        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dotp_u_h,
7413        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
7414        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
7415        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
7416        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
7417        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
7418        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
7419        // (intrinsic_wo_chain:{ *:[v8i16] } 3838:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (DOTP_U_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
7420        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DOTP_U_H,
7421        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7422        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7423        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7424        GIR_EraseFromParent, /*InsnID*/0,
7425        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7426        // GIR_Coverage, 639,
7427        GIR_Done,
7428      // Label 549: @16333
7429      GIM_Try, /*On fail goto*//*Label 550*/ 16385, // Rule ID 640 //
7430        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7431        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dotp_u_w,
7432        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7433        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
7434        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
7435        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7436        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
7437        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
7438        // (intrinsic_wo_chain:{ *:[v4i32] } 3839:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (DOTP_U_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
7439        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DOTP_U_W,
7440        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7441        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7442        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7443        GIR_EraseFromParent, /*InsnID*/0,
7444        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7445        // GIR_Coverage, 640,
7446        GIR_Done,
7447      // Label 550: @16385
7448      GIM_Try, /*On fail goto*//*Label 551*/ 16437, // Rule ID 641 //
7449        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7450        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dotp_u_d,
7451        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7452        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7453        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7454        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7455        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7456        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7457        // (intrinsic_wo_chain:{ *:[v2i64] } 3837:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (DOTP_U_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
7458        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DOTP_U_D,
7459        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7460        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7461        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7462        GIR_EraseFromParent, /*InsnID*/0,
7463        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7464        // GIR_Coverage, 641,
7465        GIR_Done,
7466      // Label 551: @16437
7467      GIM_Try, /*On fail goto*//*Label 552*/ 16489, // Rule ID 656 //
7468        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7469        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fcaf_w,
7470        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7471        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7472        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7473        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7474        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7475        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7476        // (intrinsic_wo_chain:{ *:[v4i32] } 3877:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FCAF_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
7477        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FCAF_W,
7478        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7479        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7480        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7481        GIR_EraseFromParent, /*InsnID*/0,
7482        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7483        // GIR_Coverage, 656,
7484        GIR_Done,
7485      // Label 552: @16489
7486      GIM_Try, /*On fail goto*//*Label 553*/ 16541, // Rule ID 657 //
7487        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7488        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fcaf_d,
7489        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7490        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7491        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7492        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7493        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7494        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7495        // (intrinsic_wo_chain:{ *:[v2i64] } 3876:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FCAF_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
7496        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FCAF_D,
7497        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7498        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7499        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7500        GIR_EraseFromParent, /*InsnID*/0,
7501        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7502        // GIR_Coverage, 657,
7503        GIR_Done,
7504      // Label 553: @16541
7505      GIM_Try, /*On fail goto*//*Label 554*/ 16593, // Rule ID 682 //
7506        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7507        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fexdo_h,
7508        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
7509        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7510        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7511        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
7512        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7513        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7514        // (intrinsic_wo_chain:{ *:[v8f16] } 3902:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FEXDO_H:{ *:[v8f16] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
7515        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXDO_H,
7516        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7517        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7518        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7519        GIR_EraseFromParent, /*InsnID*/0,
7520        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7521        // GIR_Coverage, 682,
7522        GIR_Done,
7523      // Label 554: @16593
7524      GIM_Try, /*On fail goto*//*Label 555*/ 16645, // Rule ID 683 //
7525        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7526        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fexdo_w,
7527        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7528        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7529        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7530        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7531        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7532        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7533        // (intrinsic_wo_chain:{ *:[v4f32] } 3903:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FEXDO_W:{ *:[v4f32] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
7534        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXDO_W,
7535        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7536        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7537        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7538        GIR_EraseFromParent, /*InsnID*/0,
7539        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7540        // GIR_Coverage, 683,
7541        GIR_Done,
7542      // Label 555: @16645
7543      GIM_Try, /*On fail goto*//*Label 556*/ 16697, // Rule ID 710 //
7544        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7545        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fmax_w,
7546        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7547        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7548        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7549        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7550        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7551        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7552        // (intrinsic_wo_chain:{ *:[v4f32] } 3929:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FMAX_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
7553        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMAX_W,
7554        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7555        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7556        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7557        GIR_EraseFromParent, /*InsnID*/0,
7558        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7559        // GIR_Coverage, 710,
7560        GIR_Done,
7561      // Label 556: @16697
7562      GIM_Try, /*On fail goto*//*Label 557*/ 16749, // Rule ID 711 //
7563        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7564        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fmax_d,
7565        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7566        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7567        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7568        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7569        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7570        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7571        // (intrinsic_wo_chain:{ *:[v2f64] } 3928:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FMAX_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
7572        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMAX_D,
7573        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7574        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7575        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7576        GIR_EraseFromParent, /*InsnID*/0,
7577        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7578        // GIR_Coverage, 711,
7579        GIR_Done,
7580      // Label 557: @16749
7581      GIM_Try, /*On fail goto*//*Label 558*/ 16801, // Rule ID 712 //
7582        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7583        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fmax_a_w,
7584        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7585        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7586        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7587        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7588        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7589        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7590        // (intrinsic_wo_chain:{ *:[v4f32] } 3927:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FMAX_A_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
7591        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMAX_A_W,
7592        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7593        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7594        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7595        GIR_EraseFromParent, /*InsnID*/0,
7596        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7597        // GIR_Coverage, 712,
7598        GIR_Done,
7599      // Label 558: @16801
7600      GIM_Try, /*On fail goto*//*Label 559*/ 16853, // Rule ID 713 //
7601        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7602        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fmax_a_d,
7603        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7604        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7605        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7606        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7607        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7608        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7609        // (intrinsic_wo_chain:{ *:[v2f64] } 3926:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FMAX_A_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
7610        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMAX_A_D,
7611        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7612        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7613        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7614        GIR_EraseFromParent, /*InsnID*/0,
7615        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7616        // GIR_Coverage, 713,
7617        GIR_Done,
7618      // Label 559: @16853
7619      GIM_Try, /*On fail goto*//*Label 560*/ 16905, // Rule ID 714 //
7620        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7621        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fmin_w,
7622        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7623        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7624        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7625        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7626        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7627        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7628        // (intrinsic_wo_chain:{ *:[v4f32] } 3933:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FMIN_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
7629        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMIN_W,
7630        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7631        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7632        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7633        GIR_EraseFromParent, /*InsnID*/0,
7634        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7635        // GIR_Coverage, 714,
7636        GIR_Done,
7637      // Label 560: @16905
7638      GIM_Try, /*On fail goto*//*Label 561*/ 16957, // Rule ID 715 //
7639        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7640        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fmin_d,
7641        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7642        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7643        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7644        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7645        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7646        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7647        // (intrinsic_wo_chain:{ *:[v2f64] } 3932:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FMIN_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
7648        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMIN_D,
7649        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7650        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7651        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7652        GIR_EraseFromParent, /*InsnID*/0,
7653        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7654        // GIR_Coverage, 715,
7655        GIR_Done,
7656      // Label 561: @16957
7657      GIM_Try, /*On fail goto*//*Label 562*/ 17009, // Rule ID 716 //
7658        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7659        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fmin_a_w,
7660        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7661        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7662        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7663        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7664        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7665        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7666        // (intrinsic_wo_chain:{ *:[v4f32] } 3931:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FMIN_A_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
7667        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMIN_A_W,
7668        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7669        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7670        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7671        GIR_EraseFromParent, /*InsnID*/0,
7672        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7673        // GIR_Coverage, 716,
7674        GIR_Done,
7675      // Label 562: @17009
7676      GIM_Try, /*On fail goto*//*Label 563*/ 17061, // Rule ID 717 //
7677        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7678        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fmin_a_d,
7679        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7680        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7681        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7682        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7683        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7684        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7685        // (intrinsic_wo_chain:{ *:[v2f64] } 3930:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FMIN_A_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
7686        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMIN_A_D,
7687        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7688        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7689        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7690        GIR_EraseFromParent, /*InsnID*/0,
7691        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7692        // GIR_Coverage, 717,
7693        GIR_Done,
7694      // Label 563: @17061
7695      GIM_Try, /*On fail goto*//*Label 564*/ 17113, // Rule ID 728 //
7696        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7697        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsaf_w,
7698        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7699        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7700        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7701        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7702        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7703        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7704        // (intrinsic_wo_chain:{ *:[v4i32] } 3945:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FSAF_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
7705        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSAF_W,
7706        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7707        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7708        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7709        GIR_EraseFromParent, /*InsnID*/0,
7710        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7711        // GIR_Coverage, 728,
7712        GIR_Done,
7713      // Label 564: @17113
7714      GIM_Try, /*On fail goto*//*Label 565*/ 17165, // Rule ID 729 //
7715        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7716        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsaf_d,
7717        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7718        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7719        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7720        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7721        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7722        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7723        // (intrinsic_wo_chain:{ *:[v2i64] } 3944:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FSAF_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
7724        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSAF_D,
7725        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7726        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7727        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7728        GIR_EraseFromParent, /*InsnID*/0,
7729        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7730        // GIR_Coverage, 729,
7731        GIR_Done,
7732      // Label 565: @17165
7733      GIM_Try, /*On fail goto*//*Label 566*/ 17217, // Rule ID 730 //
7734        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7735        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fseq_w,
7736        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7737        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7738        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7739        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7740        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7741        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7742        // (intrinsic_wo_chain:{ *:[v4i32] } 3947:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FSEQ_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
7743        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSEQ_W,
7744        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7745        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7746        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7747        GIR_EraseFromParent, /*InsnID*/0,
7748        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7749        // GIR_Coverage, 730,
7750        GIR_Done,
7751      // Label 566: @17217
7752      GIM_Try, /*On fail goto*//*Label 567*/ 17269, // Rule ID 731 //
7753        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7754        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fseq_d,
7755        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7756        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7757        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7758        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7759        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7760        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7761        // (intrinsic_wo_chain:{ *:[v2i64] } 3946:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FSEQ_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
7762        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSEQ_D,
7763        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7764        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7765        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7766        GIR_EraseFromParent, /*InsnID*/0,
7767        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7768        // GIR_Coverage, 731,
7769        GIR_Done,
7770      // Label 567: @17269
7771      GIM_Try, /*On fail goto*//*Label 568*/ 17321, // Rule ID 732 //
7772        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7773        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsle_w,
7774        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7775        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7776        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7777        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7778        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7779        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7780        // (intrinsic_wo_chain:{ *:[v4i32] } 3949:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FSLE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
7781        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSLE_W,
7782        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7783        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7784        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7785        GIR_EraseFromParent, /*InsnID*/0,
7786        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7787        // GIR_Coverage, 732,
7788        GIR_Done,
7789      // Label 568: @17321
7790      GIM_Try, /*On fail goto*//*Label 569*/ 17373, // Rule ID 733 //
7791        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7792        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsle_d,
7793        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7794        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7795        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7796        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7797        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7798        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7799        // (intrinsic_wo_chain:{ *:[v2i64] } 3948:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FSLE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
7800        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSLE_D,
7801        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7802        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7803        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7804        GIR_EraseFromParent, /*InsnID*/0,
7805        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7806        // GIR_Coverage, 733,
7807        GIR_Done,
7808      // Label 569: @17373
7809      GIM_Try, /*On fail goto*//*Label 570*/ 17425, // Rule ID 734 //
7810        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7811        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fslt_w,
7812        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7813        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7814        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7815        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7816        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7817        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7818        // (intrinsic_wo_chain:{ *:[v4i32] } 3951:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FSLT_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
7819        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSLT_W,
7820        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7821        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7822        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7823        GIR_EraseFromParent, /*InsnID*/0,
7824        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7825        // GIR_Coverage, 734,
7826        GIR_Done,
7827      // Label 570: @17425
7828      GIM_Try, /*On fail goto*//*Label 571*/ 17477, // Rule ID 735 //
7829        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7830        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fslt_d,
7831        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7832        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7833        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7834        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7835        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7836        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7837        // (intrinsic_wo_chain:{ *:[v2i64] } 3950:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FSLT_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
7838        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSLT_D,
7839        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7840        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7841        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7842        GIR_EraseFromParent, /*InsnID*/0,
7843        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7844        // GIR_Coverage, 735,
7845        GIR_Done,
7846      // Label 571: @17477
7847      GIM_Try, /*On fail goto*//*Label 572*/ 17529, // Rule ID 736 //
7848        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7849        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsne_w,
7850        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7851        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7852        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7853        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7854        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7855        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7856        // (intrinsic_wo_chain:{ *:[v4i32] } 3953:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FSNE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
7857        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSNE_W,
7858        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7859        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7860        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7861        GIR_EraseFromParent, /*InsnID*/0,
7862        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7863        // GIR_Coverage, 736,
7864        GIR_Done,
7865      // Label 572: @17529
7866      GIM_Try, /*On fail goto*//*Label 573*/ 17581, // Rule ID 737 //
7867        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7868        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsne_d,
7869        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7870        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7871        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7872        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7873        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7874        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7875        // (intrinsic_wo_chain:{ *:[v2i64] } 3952:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FSNE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
7876        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSNE_D,
7877        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7878        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7879        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7880        GIR_EraseFromParent, /*InsnID*/0,
7881        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7882        // GIR_Coverage, 737,
7883        GIR_Done,
7884      // Label 573: @17581
7885      GIM_Try, /*On fail goto*//*Label 574*/ 17633, // Rule ID 738 //
7886        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7887        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsor_w,
7888        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7889        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7890        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7891        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7892        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7893        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7894        // (intrinsic_wo_chain:{ *:[v4i32] } 3955:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FSOR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
7895        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSOR_W,
7896        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7897        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7898        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7899        GIR_EraseFromParent, /*InsnID*/0,
7900        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7901        // GIR_Coverage, 738,
7902        GIR_Done,
7903      // Label 574: @17633
7904      GIM_Try, /*On fail goto*//*Label 575*/ 17685, // Rule ID 739 //
7905        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7906        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsor_d,
7907        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7908        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7909        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7910        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7911        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7912        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7913        // (intrinsic_wo_chain:{ *:[v2i64] } 3954:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FSOR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
7914        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSOR_D,
7915        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7916        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7917        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7918        GIR_EraseFromParent, /*InsnID*/0,
7919        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7920        // GIR_Coverage, 739,
7921        GIR_Done,
7922      // Label 575: @17685
7923      GIM_Try, /*On fail goto*//*Label 576*/ 17737, // Rule ID 744 //
7924        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7925        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsueq_w,
7926        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7927        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7928        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7929        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7930        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7931        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7932        // (intrinsic_wo_chain:{ *:[v4i32] } 3961:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FSUEQ_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
7933        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSUEQ_W,
7934        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7935        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7936        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7937        GIR_EraseFromParent, /*InsnID*/0,
7938        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7939        // GIR_Coverage, 744,
7940        GIR_Done,
7941      // Label 576: @17737
7942      GIM_Try, /*On fail goto*//*Label 577*/ 17789, // Rule ID 745 //
7943        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7944        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsueq_d,
7945        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7946        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7947        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7948        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7949        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7950        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7951        // (intrinsic_wo_chain:{ *:[v2i64] } 3960:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FSUEQ_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
7952        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSUEQ_D,
7953        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7954        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7955        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7956        GIR_EraseFromParent, /*InsnID*/0,
7957        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7958        // GIR_Coverage, 745,
7959        GIR_Done,
7960      // Label 577: @17789
7961      GIM_Try, /*On fail goto*//*Label 578*/ 17841, // Rule ID 746 //
7962        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7963        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsule_w,
7964        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7965        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7966        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7967        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7968        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7969        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7970        // (intrinsic_wo_chain:{ *:[v4i32] } 3963:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FSULE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
7971        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSULE_W,
7972        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7973        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7974        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7975        GIR_EraseFromParent, /*InsnID*/0,
7976        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7977        // GIR_Coverage, 746,
7978        GIR_Done,
7979      // Label 578: @17841
7980      GIM_Try, /*On fail goto*//*Label 579*/ 17893, // Rule ID 747 //
7981        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7982        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsule_d,
7983        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7984        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7985        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7986        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7987        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7988        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7989        // (intrinsic_wo_chain:{ *:[v2i64] } 3962:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FSULE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
7990        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSULE_D,
7991        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7992        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7993        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7994        GIR_EraseFromParent, /*InsnID*/0,
7995        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7996        // GIR_Coverage, 747,
7997        GIR_Done,
7998      // Label 579: @17893
7999      GIM_Try, /*On fail goto*//*Label 580*/ 17945, // Rule ID 748 //
8000        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8001        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsult_w,
8002        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
8003        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
8004        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
8005        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
8006        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
8007        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
8008        // (intrinsic_wo_chain:{ *:[v4i32] } 3965:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FSULT_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
8009        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSULT_W,
8010        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8011        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8012        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8013        GIR_EraseFromParent, /*InsnID*/0,
8014        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8015        // GIR_Coverage, 748,
8016        GIR_Done,
8017      // Label 580: @17945
8018      GIM_Try, /*On fail goto*//*Label 581*/ 17997, // Rule ID 749 //
8019        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8020        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsult_d,
8021        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
8022        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
8023        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
8024        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
8025        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
8026        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
8027        // (intrinsic_wo_chain:{ *:[v2i64] } 3964:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FSULT_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
8028        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSULT_D,
8029        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8030        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8031        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8032        GIR_EraseFromParent, /*InsnID*/0,
8033        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8034        // GIR_Coverage, 749,
8035        GIR_Done,
8036      // Label 581: @17997
8037      GIM_Try, /*On fail goto*//*Label 582*/ 18049, // Rule ID 750 //
8038        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8039        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsun_w,
8040        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
8041        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
8042        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
8043        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
8044        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
8045        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
8046        // (intrinsic_wo_chain:{ *:[v4i32] } 3967:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FSUN_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
8047        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSUN_W,
8048        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8049        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8050        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8051        GIR_EraseFromParent, /*InsnID*/0,
8052        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8053        // GIR_Coverage, 750,
8054        GIR_Done,
8055      // Label 582: @18049
8056      GIM_Try, /*On fail goto*//*Label 583*/ 18101, // Rule ID 751 //
8057        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8058        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsun_d,
8059        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
8060        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
8061        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
8062        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
8063        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
8064        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
8065        // (intrinsic_wo_chain:{ *:[v2i64] } 3966:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FSUN_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
8066        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSUN_D,
8067        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8068        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8069        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8070        GIR_EraseFromParent, /*InsnID*/0,
8071        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8072        // GIR_Coverage, 751,
8073        GIR_Done,
8074      // Label 583: @18101
8075      GIM_Try, /*On fail goto*//*Label 584*/ 18153, // Rule ID 752 //
8076        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8077        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsune_w,
8078        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
8079        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
8080        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
8081        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
8082        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
8083        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
8084        // (intrinsic_wo_chain:{ *:[v4i32] } 3969:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FSUNE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
8085        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSUNE_W,
8086        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8087        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8088        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8089        GIR_EraseFromParent, /*InsnID*/0,
8090        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8091        // GIR_Coverage, 752,
8092        GIR_Done,
8093      // Label 584: @18153
8094      GIM_Try, /*On fail goto*//*Label 585*/ 18205, // Rule ID 753 //
8095        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8096        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsune_d,
8097        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
8098        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
8099        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
8100        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
8101        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
8102        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
8103        // (intrinsic_wo_chain:{ *:[v2i64] } 3968:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FSUNE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
8104        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSUNE_D,
8105        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8106        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8107        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8108        GIR_EraseFromParent, /*InsnID*/0,
8109        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8110        // GIR_Coverage, 753,
8111        GIR_Done,
8112      // Label 585: @18205
8113      GIM_Try, /*On fail goto*//*Label 586*/ 18257, // Rule ID 758 //
8114        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8115        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ftq_h,
8116        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
8117        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
8118        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
8119        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
8120        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
8121        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
8122        // (intrinsic_wo_chain:{ *:[v8i16] } 3974:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FTQ_H:{ *:[v8i16] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
8123        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FTQ_H,
8124        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8125        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8126        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8127        GIR_EraseFromParent, /*InsnID*/0,
8128        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8129        // GIR_Coverage, 758,
8130        GIR_Done,
8131      // Label 586: @18257
8132      GIM_Try, /*On fail goto*//*Label 587*/ 18309, // Rule ID 759 //
8133        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8134        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ftq_w,
8135        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
8136        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
8137        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
8138        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
8139        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
8140        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
8141        // (intrinsic_wo_chain:{ *:[v4i32] } 3975:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FTQ_W:{ *:[v4i32] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
8142        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FTQ_W,
8143        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8144        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8145        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8146        GIR_EraseFromParent, /*InsnID*/0,
8147        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8148        // GIR_Coverage, 759,
8149        GIR_Done,
8150      // Label 587: @18309
8151      GIM_Try, /*On fail goto*//*Label 588*/ 18361, // Rule ID 764 //
8152        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8153        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hadd_s_h,
8154        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
8155        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
8156        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
8157        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
8158        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
8159        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
8160        // (intrinsic_wo_chain:{ *:[v8i16] } 3981:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (HADD_S_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
8161        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HADD_S_H,
8162        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8163        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8164        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8165        GIR_EraseFromParent, /*InsnID*/0,
8166        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8167        // GIR_Coverage, 764,
8168        GIR_Done,
8169      // Label 588: @18361
8170      GIM_Try, /*On fail goto*//*Label 589*/ 18413, // Rule ID 765 //
8171        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8172        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hadd_s_w,
8173        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
8174        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
8175        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
8176        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
8177        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
8178        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
8179        // (intrinsic_wo_chain:{ *:[v4i32] } 3982:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (HADD_S_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
8180        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HADD_S_W,
8181        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8182        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8183        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8184        GIR_EraseFromParent, /*InsnID*/0,
8185        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8186        // GIR_Coverage, 765,
8187        GIR_Done,
8188      // Label 589: @18413
8189      GIM_Try, /*On fail goto*//*Label 590*/ 18465, // Rule ID 766 //
8190        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8191        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hadd_s_d,
8192        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
8193        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
8194        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
8195        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
8196        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
8197        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
8198        // (intrinsic_wo_chain:{ *:[v2i64] } 3980:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (HADD_S_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
8199        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HADD_S_D,
8200        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8201        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8202        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8203        GIR_EraseFromParent, /*InsnID*/0,
8204        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8205        // GIR_Coverage, 766,
8206        GIR_Done,
8207      // Label 590: @18465
8208      GIM_Try, /*On fail goto*//*Label 591*/ 18517, // Rule ID 767 //
8209        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8210        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hadd_u_h,
8211        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
8212        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
8213        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
8214        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
8215        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
8216        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
8217        // (intrinsic_wo_chain:{ *:[v8i16] } 3984:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (HADD_U_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
8218        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HADD_U_H,
8219        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8220        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8221        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8222        GIR_EraseFromParent, /*InsnID*/0,
8223        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8224        // GIR_Coverage, 767,
8225        GIR_Done,
8226      // Label 591: @18517
8227      GIM_Try, /*On fail goto*//*Label 592*/ 18569, // Rule ID 768 //
8228        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8229        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hadd_u_w,
8230        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
8231        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
8232        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
8233        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
8234        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
8235        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
8236        // (intrinsic_wo_chain:{ *:[v4i32] } 3985:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (HADD_U_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
8237        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HADD_U_W,
8238        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8239        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8240        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8241        GIR_EraseFromParent, /*InsnID*/0,
8242        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8243        // GIR_Coverage, 768,
8244        GIR_Done,
8245      // Label 592: @18569
8246      GIM_Try, /*On fail goto*//*Label 593*/ 18621, // Rule ID 769 //
8247        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8248        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hadd_u_d,
8249        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
8250        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
8251        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
8252        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
8253        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
8254        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
8255        // (intrinsic_wo_chain:{ *:[v2i64] } 3983:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (HADD_U_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
8256        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HADD_U_D,
8257        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8258        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8259        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8260        GIR_EraseFromParent, /*InsnID*/0,
8261        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8262        // GIR_Coverage, 769,
8263        GIR_Done,
8264      // Label 593: @18621
8265      GIM_Try, /*On fail goto*//*Label 594*/ 18673, // Rule ID 770 //
8266        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8267        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hsub_s_h,
8268        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
8269        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
8270        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
8271        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
8272        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
8273        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
8274        // (intrinsic_wo_chain:{ *:[v8i16] } 3987:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (HSUB_S_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
8275        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HSUB_S_H,
8276        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8277        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8278        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8279        GIR_EraseFromParent, /*InsnID*/0,
8280        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8281        // GIR_Coverage, 770,
8282        GIR_Done,
8283      // Label 594: @18673
8284      GIM_Try, /*On fail goto*//*Label 595*/ 18725, // Rule ID 771 //
8285        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8286        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hsub_s_w,
8287        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
8288        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
8289        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
8290        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
8291        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
8292        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
8293        // (intrinsic_wo_chain:{ *:[v4i32] } 3988:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (HSUB_S_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
8294        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HSUB_S_W,
8295        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8296        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8297        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8298        GIR_EraseFromParent, /*InsnID*/0,
8299        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8300        // GIR_Coverage, 771,
8301        GIR_Done,
8302      // Label 595: @18725
8303      GIM_Try, /*On fail goto*//*Label 596*/ 18777, // Rule ID 772 //
8304        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8305        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hsub_s_d,
8306        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
8307        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
8308        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
8309        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
8310        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
8311        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
8312        // (intrinsic_wo_chain:{ *:[v2i64] } 3986:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (HSUB_S_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
8313        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HSUB_S_D,
8314        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8315        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8316        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8317        GIR_EraseFromParent, /*InsnID*/0,
8318        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8319        // GIR_Coverage, 772,
8320        GIR_Done,
8321      // Label 596: @18777
8322      GIM_Try, /*On fail goto*//*Label 597*/ 18829, // Rule ID 773 //
8323        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8324        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hsub_u_h,
8325        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
8326        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
8327        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
8328        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
8329        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
8330        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
8331        // (intrinsic_wo_chain:{ *:[v8i16] } 3990:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (HSUB_U_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
8332        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HSUB_U_H,
8333        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8334        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8335        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8336        GIR_EraseFromParent, /*InsnID*/0,
8337        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8338        // GIR_Coverage, 773,
8339        GIR_Done,
8340      // Label 597: @18829
8341      GIM_Try, /*On fail goto*//*Label 598*/ 18881, // Rule ID 774 //
8342        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8343        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hsub_u_w,
8344        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
8345        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
8346        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
8347        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
8348        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
8349        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
8350        // (intrinsic_wo_chain:{ *:[v4i32] } 3991:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (HSUB_U_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
8351        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HSUB_U_W,
8352        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8353        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8354        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8355        GIR_EraseFromParent, /*InsnID*/0,
8356        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8357        // GIR_Coverage, 774,
8358        GIR_Done,
8359      // Label 598: @18881
8360      GIM_Try, /*On fail goto*//*Label 599*/ 18933, // Rule ID 775 //
8361        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8362        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hsub_u_d,
8363        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
8364        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
8365        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
8366        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
8367        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
8368        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
8369        // (intrinsic_wo_chain:{ *:[v2i64] } 3989:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (HSUB_U_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
8370        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HSUB_U_D,
8371        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8372        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8373        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8374        GIR_EraseFromParent, /*InsnID*/0,
8375        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8376        // GIR_Coverage, 775,
8377        GIR_Done,
8378      // Label 599: @18933
8379      GIM_Try, /*On fail goto*//*Label 600*/ 18985, // Rule ID 828 //
8380        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8381        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_max_a_b,
8382        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
8383        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
8384        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
8385        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
8386        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
8387        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
8388        // (intrinsic_wo_chain:{ *:[v16i8] } 4043:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (MAX_A_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
8389        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MAX_A_B,
8390        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8391        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8392        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8393        GIR_EraseFromParent, /*InsnID*/0,
8394        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8395        // GIR_Coverage, 828,
8396        GIR_Done,
8397      // Label 600: @18985
8398      GIM_Try, /*On fail goto*//*Label 601*/ 19037, // Rule ID 829 //
8399        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8400        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_max_a_h,
8401        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
8402        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
8403        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
8404        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
8405        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
8406        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
8407        // (intrinsic_wo_chain:{ *:[v8i16] } 4045:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (MAX_A_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
8408        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MAX_A_H,
8409        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8410        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8411        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8412        GIR_EraseFromParent, /*InsnID*/0,
8413        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8414        // GIR_Coverage, 829,
8415        GIR_Done,
8416      // Label 601: @19037
8417      GIM_Try, /*On fail goto*//*Label 602*/ 19089, // Rule ID 830 //
8418        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8419        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_max_a_w,
8420        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
8421        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
8422        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
8423        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
8424        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
8425        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
8426        // (intrinsic_wo_chain:{ *:[v4i32] } 4046:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (MAX_A_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
8427        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MAX_A_W,
8428        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8429        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8430        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8431        GIR_EraseFromParent, /*InsnID*/0,
8432        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8433        // GIR_Coverage, 830,
8434        GIR_Done,
8435      // Label 602: @19089
8436      GIM_Try, /*On fail goto*//*Label 603*/ 19141, // Rule ID 831 //
8437        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8438        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_max_a_d,
8439        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
8440        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
8441        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
8442        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
8443        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
8444        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
8445        // (intrinsic_wo_chain:{ *:[v2i64] } 4044:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (MAX_A_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
8446        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MAX_A_D,
8447        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8448        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8449        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8450        GIR_EraseFromParent, /*InsnID*/0,
8451        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8452        // GIR_Coverage, 831,
8453        GIR_Done,
8454      // Label 603: @19141
8455      GIM_Try, /*On fail goto*//*Label 604*/ 19193, // Rule ID 848 //
8456        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8457        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_min_a_b,
8458        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
8459        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
8460        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
8461        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
8462        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
8463        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
8464        // (intrinsic_wo_chain:{ *:[v16i8] } 4063:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (MIN_A_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
8465        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MIN_A_B,
8466        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8467        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8468        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8469        GIR_EraseFromParent, /*InsnID*/0,
8470        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8471        // GIR_Coverage, 848,
8472        GIR_Done,
8473      // Label 604: @19193
8474      GIM_Try, /*On fail goto*//*Label 605*/ 19245, // Rule ID 849 //
8475        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8476        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_min_a_h,
8477        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
8478        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
8479        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
8480        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
8481        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
8482        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
8483        // (intrinsic_wo_chain:{ *:[v8i16] } 4065:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (MIN_A_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
8484        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MIN_A_H,
8485        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8486        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8487        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8488        GIR_EraseFromParent, /*InsnID*/0,
8489        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8490        // GIR_Coverage, 849,
8491        GIR_Done,
8492      // Label 605: @19245
8493      GIM_Try, /*On fail goto*//*Label 606*/ 19297, // Rule ID 850 //
8494        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8495        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_min_a_w,
8496        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
8497        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
8498        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
8499        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
8500        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
8501        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
8502        // (intrinsic_wo_chain:{ *:[v4i32] } 4066:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (MIN_A_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
8503        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MIN_A_W,
8504        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8505        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8506        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8507        GIR_EraseFromParent, /*InsnID*/0,
8508        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8509        // GIR_Coverage, 850,
8510        GIR_Done,
8511      // Label 606: @19297
8512      GIM_Try, /*On fail goto*//*Label 607*/ 19349, // Rule ID 851 //
8513        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8514        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_min_a_d,
8515        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
8516        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
8517        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
8518        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
8519        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
8520        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
8521        // (intrinsic_wo_chain:{ *:[v2i64] } 4064:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (MIN_A_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
8522        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MIN_A_D,
8523        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8524        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8525        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8526        GIR_EraseFromParent, /*InsnID*/0,
8527        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8528        // GIR_Coverage, 851,
8529        GIR_Done,
8530      // Label 607: @19349
8531      GIM_Try, /*On fail goto*//*Label 608*/ 19401, // Rule ID 884 //
8532        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8533        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mul_q_h,
8534        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
8535        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
8536        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
8537        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
8538        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
8539        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
8540        // (intrinsic_wo_chain:{ *:[v8i16] } 4105:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (MUL_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
8541        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MUL_Q_H,
8542        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8543        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8544        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8545        GIR_EraseFromParent, /*InsnID*/0,
8546        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8547        // GIR_Coverage, 884,
8548        GIR_Done,
8549      // Label 608: @19401
8550      GIM_Try, /*On fail goto*//*Label 609*/ 19453, // Rule ID 885 //
8551        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8552        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mul_q_w,
8553        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
8554        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
8555        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
8556        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
8557        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
8558        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
8559        // (intrinsic_wo_chain:{ *:[v4i32] } 4106:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (MUL_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
8560        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MUL_Q_W,
8561        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8562        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8563        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8564        GIR_EraseFromParent, /*InsnID*/0,
8565        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8566        // GIR_Coverage, 885,
8567        GIR_Done,
8568      // Label 609: @19453
8569      GIM_Try, /*On fail goto*//*Label 610*/ 19505, // Rule ID 886 //
8570        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8571        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulr_q_h,
8572        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
8573        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
8574        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
8575        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
8576        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
8577        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
8578        // (intrinsic_wo_chain:{ *:[v8i16] } 4116:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (MULR_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
8579        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULR_Q_H,
8580        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8581        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8582        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8583        GIR_EraseFromParent, /*InsnID*/0,
8584        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8585        // GIR_Coverage, 886,
8586        GIR_Done,
8587      // Label 610: @19505
8588      GIM_Try, /*On fail goto*//*Label 611*/ 19557, // Rule ID 887 //
8589        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8590        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulr_q_w,
8591        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
8592        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
8593        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
8594        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
8595        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
8596        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
8597        // (intrinsic_wo_chain:{ *:[v4i32] } 4117:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (MULR_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
8598        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULR_Q_W,
8599        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8600        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8601        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8602        GIR_EraseFromParent, /*InsnID*/0,
8603        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8604        // GIR_Coverage, 887,
8605        GIR_Done,
8606      // Label 611: @19557
8607      GIM_Try, /*On fail goto*//*Label 612*/ 19609, // Rule ID 965 //
8608        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8609        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srar_b,
8610        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
8611        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
8612        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
8613        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
8614        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
8615        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
8616        // (intrinsic_wo_chain:{ *:[v16i8] } 4230:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (SRAR_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
8617        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRAR_B,
8618        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8619        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8620        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8621        GIR_EraseFromParent, /*InsnID*/0,
8622        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8623        // GIR_Coverage, 965,
8624        GIR_Done,
8625      // Label 612: @19609
8626      GIM_Try, /*On fail goto*//*Label 613*/ 19661, // Rule ID 966 //
8627        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8628        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srar_h,
8629        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
8630        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
8631        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
8632        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
8633        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
8634        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
8635        // (intrinsic_wo_chain:{ *:[v8i16] } 4232:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (SRAR_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
8636        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRAR_H,
8637        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8638        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8639        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8640        GIR_EraseFromParent, /*InsnID*/0,
8641        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8642        // GIR_Coverage, 966,
8643        GIR_Done,
8644      // Label 613: @19661
8645      GIM_Try, /*On fail goto*//*Label 614*/ 19713, // Rule ID 967 //
8646        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8647        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srar_w,
8648        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
8649        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
8650        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
8651        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
8652        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
8653        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
8654        // (intrinsic_wo_chain:{ *:[v4i32] } 4233:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (SRAR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
8655        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRAR_W,
8656        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8657        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8658        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8659        GIR_EraseFromParent, /*InsnID*/0,
8660        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8661        // GIR_Coverage, 967,
8662        GIR_Done,
8663      // Label 614: @19713
8664      GIM_Try, /*On fail goto*//*Label 615*/ 19765, // Rule ID 968 //
8665        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8666        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srar_d,
8667        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
8668        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
8669        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
8670        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
8671        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
8672        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
8673        // (intrinsic_wo_chain:{ *:[v2i64] } 4231:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (SRAR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
8674        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRAR_D,
8675        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8676        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8677        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8678        GIR_EraseFromParent, /*InsnID*/0,
8679        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8680        // GIR_Coverage, 968,
8681        GIR_Done,
8682      // Label 615: @19765
8683      GIM_Try, /*On fail goto*//*Label 616*/ 19817, // Rule ID 981 //
8684        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8685        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srlr_b,
8686        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
8687        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
8688        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
8689        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
8690        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
8691        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
8692        // (intrinsic_wo_chain:{ *:[v16i8] } 4246:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (SRLR_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
8693        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLR_B,
8694        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8695        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8696        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8697        GIR_EraseFromParent, /*InsnID*/0,
8698        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8699        // GIR_Coverage, 981,
8700        GIR_Done,
8701      // Label 616: @19817
8702      GIM_Try, /*On fail goto*//*Label 617*/ 19869, // Rule ID 982 //
8703        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8704        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srlr_h,
8705        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
8706        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
8707        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
8708        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
8709        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
8710        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
8711        // (intrinsic_wo_chain:{ *:[v8i16] } 4248:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (SRLR_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
8712        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLR_H,
8713        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8714        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8715        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8716        GIR_EraseFromParent, /*InsnID*/0,
8717        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8718        // GIR_Coverage, 982,
8719        GIR_Done,
8720      // Label 617: @19869
8721      GIM_Try, /*On fail goto*//*Label 618*/ 19921, // Rule ID 983 //
8722        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8723        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srlr_w,
8724        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
8725        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
8726        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
8727        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
8728        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
8729        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
8730        // (intrinsic_wo_chain:{ *:[v4i32] } 4249:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (SRLR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
8731        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLR_W,
8732        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8733        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8734        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8735        GIR_EraseFromParent, /*InsnID*/0,
8736        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8737        // GIR_Coverage, 983,
8738        GIR_Done,
8739      // Label 618: @19921
8740      GIM_Try, /*On fail goto*//*Label 619*/ 19973, // Rule ID 984 //
8741        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8742        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srlr_d,
8743        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
8744        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
8745        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
8746        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
8747        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
8748        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
8749        // (intrinsic_wo_chain:{ *:[v2i64] } 4247:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (SRLR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
8750        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLR_D,
8751        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8752        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8753        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8754        GIR_EraseFromParent, /*InsnID*/0,
8755        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8756        // GIR_Coverage, 984,
8757        GIR_Done,
8758      // Label 619: @19973
8759      GIM_Try, /*On fail goto*//*Label 620*/ 20025, // Rule ID 993 //
8760        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8761        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subs_s_b,
8762        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
8763        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
8764        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
8765        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
8766        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
8767        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
8768        // (intrinsic_wo_chain:{ *:[v16i8] } 4265:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (SUBS_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
8769        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_S_B,
8770        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8771        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8772        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8773        GIR_EraseFromParent, /*InsnID*/0,
8774        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8775        // GIR_Coverage, 993,
8776        GIR_Done,
8777      // Label 620: @20025
8778      GIM_Try, /*On fail goto*//*Label 621*/ 20077, // Rule ID 994 //
8779        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8780        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subs_s_h,
8781        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
8782        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
8783        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
8784        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
8785        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
8786        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
8787        // (intrinsic_wo_chain:{ *:[v8i16] } 4267:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (SUBS_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
8788        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_S_H,
8789        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8790        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8791        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8792        GIR_EraseFromParent, /*InsnID*/0,
8793        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8794        // GIR_Coverage, 994,
8795        GIR_Done,
8796      // Label 621: @20077
8797      GIM_Try, /*On fail goto*//*Label 622*/ 20129, // Rule ID 995 //
8798        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8799        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subs_s_w,
8800        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
8801        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
8802        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
8803        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
8804        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
8805        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
8806        // (intrinsic_wo_chain:{ *:[v4i32] } 4268:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (SUBS_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
8807        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_S_W,
8808        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8809        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8810        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8811        GIR_EraseFromParent, /*InsnID*/0,
8812        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8813        // GIR_Coverage, 995,
8814        GIR_Done,
8815      // Label 622: @20129
8816      GIM_Try, /*On fail goto*//*Label 623*/ 20181, // Rule ID 996 //
8817        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8818        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subs_s_d,
8819        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
8820        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
8821        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
8822        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
8823        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
8824        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
8825        // (intrinsic_wo_chain:{ *:[v2i64] } 4266:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (SUBS_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
8826        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_S_D,
8827        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8828        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8829        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8830        GIR_EraseFromParent, /*InsnID*/0,
8831        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8832        // GIR_Coverage, 996,
8833        GIR_Done,
8834      // Label 623: @20181
8835      GIM_Try, /*On fail goto*//*Label 624*/ 20233, // Rule ID 997 //
8836        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8837        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subs_u_b,
8838        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
8839        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
8840        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
8841        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
8842        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
8843        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
8844        // (intrinsic_wo_chain:{ *:[v16i8] } 4269:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (SUBS_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
8845        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_U_B,
8846        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8847        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8848        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8849        GIR_EraseFromParent, /*InsnID*/0,
8850        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8851        // GIR_Coverage, 997,
8852        GIR_Done,
8853      // Label 624: @20233
8854      GIM_Try, /*On fail goto*//*Label 625*/ 20285, // Rule ID 998 //
8855        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8856        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subs_u_h,
8857        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
8858        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
8859        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
8860        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
8861        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
8862        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
8863        // (intrinsic_wo_chain:{ *:[v8i16] } 4271:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (SUBS_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
8864        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_U_H,
8865        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8866        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8867        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8868        GIR_EraseFromParent, /*InsnID*/0,
8869        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8870        // GIR_Coverage, 998,
8871        GIR_Done,
8872      // Label 625: @20285
8873      GIM_Try, /*On fail goto*//*Label 626*/ 20337, // Rule ID 999 //
8874        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8875        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subs_u_w,
8876        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
8877        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
8878        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
8879        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
8880        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
8881        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
8882        // (intrinsic_wo_chain:{ *:[v4i32] } 4272:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (SUBS_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
8883        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_U_W,
8884        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8885        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8886        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8887        GIR_EraseFromParent, /*InsnID*/0,
8888        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8889        // GIR_Coverage, 999,
8890        GIR_Done,
8891      // Label 626: @20337
8892      GIM_Try, /*On fail goto*//*Label 627*/ 20389, // Rule ID 1000 //
8893        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8894        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subs_u_d,
8895        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
8896        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
8897        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
8898        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
8899        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
8900        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
8901        // (intrinsic_wo_chain:{ *:[v2i64] } 4270:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (SUBS_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
8902        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_U_D,
8903        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8904        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8905        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8906        GIR_EraseFromParent, /*InsnID*/0,
8907        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8908        // GIR_Coverage, 1000,
8909        GIR_Done,
8910      // Label 627: @20389
8911      GIM_Try, /*On fail goto*//*Label 628*/ 20441, // Rule ID 1001 //
8912        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8913        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subsus_u_b,
8914        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
8915        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
8916        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
8917        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
8918        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
8919        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
8920        // (intrinsic_wo_chain:{ *:[v16i8] } 4273:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (SUBSUS_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
8921        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUS_U_B,
8922        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8923        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8924        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8925        GIR_EraseFromParent, /*InsnID*/0,
8926        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8927        // GIR_Coverage, 1001,
8928        GIR_Done,
8929      // Label 628: @20441
8930      GIM_Try, /*On fail goto*//*Label 629*/ 20493, // Rule ID 1002 //
8931        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8932        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subsus_u_h,
8933        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
8934        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
8935        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
8936        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
8937        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
8938        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
8939        // (intrinsic_wo_chain:{ *:[v8i16] } 4275:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (SUBSUS_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
8940        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUS_U_H,
8941        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8942        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8943        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8944        GIR_EraseFromParent, /*InsnID*/0,
8945        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8946        // GIR_Coverage, 1002,
8947        GIR_Done,
8948      // Label 629: @20493
8949      GIM_Try, /*On fail goto*//*Label 630*/ 20545, // Rule ID 1003 //
8950        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8951        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subsus_u_w,
8952        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
8953        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
8954        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
8955        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
8956        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
8957        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
8958        // (intrinsic_wo_chain:{ *:[v4i32] } 4276:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (SUBSUS_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
8959        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUS_U_W,
8960        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8961        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8962        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8963        GIR_EraseFromParent, /*InsnID*/0,
8964        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8965        // GIR_Coverage, 1003,
8966        GIR_Done,
8967      // Label 630: @20545
8968      GIM_Try, /*On fail goto*//*Label 631*/ 20597, // Rule ID 1004 //
8969        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8970        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subsus_u_d,
8971        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
8972        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
8973        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
8974        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
8975        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
8976        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
8977        // (intrinsic_wo_chain:{ *:[v2i64] } 4274:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (SUBSUS_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
8978        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUS_U_D,
8979        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8980        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8981        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8982        GIR_EraseFromParent, /*InsnID*/0,
8983        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8984        // GIR_Coverage, 1004,
8985        GIR_Done,
8986      // Label 631: @20597
8987      GIM_Try, /*On fail goto*//*Label 632*/ 20649, // Rule ID 1005 //
8988        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8989        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subsuu_s_b,
8990        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
8991        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
8992        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
8993        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
8994        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
8995        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
8996        // (intrinsic_wo_chain:{ *:[v16i8] } 4277:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (SUBSUU_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
8997        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUU_S_B,
8998        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8999        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
9000        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
9001        GIR_EraseFromParent, /*InsnID*/0,
9002        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9003        // GIR_Coverage, 1005,
9004        GIR_Done,
9005      // Label 632: @20649
9006      GIM_Try, /*On fail goto*//*Label 633*/ 20701, // Rule ID 1006 //
9007        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
9008        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subsuu_s_h,
9009        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
9010        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
9011        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
9012        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
9013        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
9014        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
9015        // (intrinsic_wo_chain:{ *:[v8i16] } 4279:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (SUBSUU_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
9016        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUU_S_H,
9017        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
9018        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
9019        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
9020        GIR_EraseFromParent, /*InsnID*/0,
9021        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9022        // GIR_Coverage, 1006,
9023        GIR_Done,
9024      // Label 633: @20701
9025      GIM_Try, /*On fail goto*//*Label 634*/ 20753, // Rule ID 1007 //
9026        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
9027        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subsuu_s_w,
9028        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
9029        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
9030        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
9031        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
9032        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
9033        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
9034        // (intrinsic_wo_chain:{ *:[v4i32] } 4280:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (SUBSUU_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
9035        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUU_S_W,
9036        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
9037        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
9038        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
9039        GIR_EraseFromParent, /*InsnID*/0,
9040        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9041        // GIR_Coverage, 1007,
9042        GIR_Done,
9043      // Label 634: @20753
9044      GIM_Try, /*On fail goto*//*Label 635*/ 20805, // Rule ID 1008 //
9045        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
9046        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subsuu_s_d,
9047        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
9048        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
9049        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
9050        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
9051        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
9052        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
9053        // (intrinsic_wo_chain:{ *:[v2i64] } 4278:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (SUBSUU_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
9054        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUU_S_D,
9055        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
9056        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
9057        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
9058        GIR_EraseFromParent, /*InsnID*/0,
9059        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9060        // GIR_Coverage, 1008,
9061        GIR_Done,
9062      // Label 635: @20805
9063      GIM_Try, /*On fail goto*//*Label 636*/ 20857, // Rule ID 1205 //
9064        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
9065        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addq_s_ph,
9066        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
9067        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
9068        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
9069        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9070        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
9071        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
9072        // (intrinsic_wo_chain:{ *:[v2i16] } 3643:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (ADDQ_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
9073        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQ_S_PH_MM,
9074        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9075        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
9076        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
9077        GIR_EraseFromParent, /*InsnID*/0,
9078        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9079        // GIR_Coverage, 1205,
9080        GIR_Done,
9081      // Label 636: @20857
9082      GIM_Try, /*On fail goto*//*Label 637*/ 20909, // Rule ID 1207 //
9083        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
9084        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addu_s_qb,
9085        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
9086        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
9087        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
9088        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9089        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
9090        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
9091        // (intrinsic_wo_chain:{ *:[v4i8] } 3665:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (ADDU_S_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
9092        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDU_S_QB_MM,
9093        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9094        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
9095        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
9096        GIR_EraseFromParent, /*InsnID*/0,
9097        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9098        // GIR_Coverage, 1207,
9099        GIR_Done,
9100      // Label 637: @20909
9101      GIM_Try, /*On fail goto*//*Label 638*/ 20961, // Rule ID 1228 //
9102        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
9103        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_ph,
9104        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
9105        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
9106        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
9107        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9108        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
9109        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
9110        // (intrinsic_wo_chain:{ *:[v2i16] } 4191:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)  =>  (SHRAV_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
9111        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_PH_MM,
9112        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9113        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
9114        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
9115        GIR_EraseFromParent, /*InsnID*/0,
9116        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9117        // GIR_Coverage, 1228,
9118        GIR_Done,
9119      // Label 638: @20961
9120      GIM_Try, /*On fail goto*//*Label 639*/ 21013, // Rule ID 1229 //
9121        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
9122        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_ph,
9123        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
9124        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
9125        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
9126        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9127        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
9128        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
9129        // (intrinsic_wo_chain:{ *:[v2i16] } 4193:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)  =>  (SHRAV_R_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
9130        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_R_PH_MM,
9131        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9132        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
9133        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
9134        GIR_EraseFromParent, /*InsnID*/0,
9135        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9136        // GIR_Coverage, 1229,
9137        GIR_Done,
9138      // Label 639: @21013
9139      GIM_Try, /*On fail goto*//*Label 640*/ 21065, // Rule ID 1230 //
9140        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
9141        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_w,
9142        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
9143        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
9144        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
9145        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
9146        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
9147        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
9148        // (intrinsic_wo_chain:{ *:[i32] } 4195:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)  =>  (SHRAV_R_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
9149        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_R_W_MM,
9150        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9151        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
9152        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
9153        GIR_EraseFromParent, /*InsnID*/0,
9154        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9155        // GIR_Coverage, 1230,
9156        GIR_Done,
9157      // Label 640: @21065
9158      GIM_Try, /*On fail goto*//*Label 641*/ 21117, // Rule ID 1232 //
9159        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
9160        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shrl_qb,
9161        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
9162        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
9163        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
9164        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9165        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
9166        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
9167        // (intrinsic_wo_chain:{ *:[v4i8] } 4197:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)  =>  (SHRLV_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
9168        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRLV_QB_MM,
9169        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9170        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
9171        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
9172        GIR_EraseFromParent, /*InsnID*/0,
9173        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9174        // GIR_Coverage, 1232,
9175        GIR_Done,
9176      // Label 641: @21117
9177      GIM_Try, /*On fail goto*//*Label 642*/ 21169, // Rule ID 1243 //
9178        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
9179        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subq_s_ph,
9180        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
9181        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
9182        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
9183        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9184        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
9185        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
9186        // (intrinsic_wo_chain:{ *:[v2i16] } 4259:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (SUBQ_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
9187        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQ_S_PH_MM,
9188        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9189        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
9190        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
9191        GIR_EraseFromParent, /*InsnID*/0,
9192        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9193        // GIR_Coverage, 1243,
9194        GIR_Done,
9195      // Label 642: @21169
9196      GIM_Try, /*On fail goto*//*Label 643*/ 21221, // Rule ID 1245 //
9197        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
9198        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subu_s_qb,
9199        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
9200        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
9201        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
9202        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9203        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
9204        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
9205        // (intrinsic_wo_chain:{ *:[v4i8] } 4284:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (SUBU_S_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
9206        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBU_S_QB_MM,
9207        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9208        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
9209        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
9210        GIR_EraseFromParent, /*InsnID*/0,
9211        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9212        // GIR_Coverage, 1245,
9213        GIR_Done,
9214      // Label 643: @21221
9215      GIM_Try, /*On fail goto*//*Label 644*/ 21273, // Rule ID 1255 //
9216        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
9217        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precrq_ph_w,
9218        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
9219        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
9220        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
9221        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9222        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
9223        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
9224        // (intrinsic_wo_chain:{ *:[v2i16] } 4166:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (PRECRQ_PH_W_MM:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
9225        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECRQ_PH_W_MM,
9226        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9227        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
9228        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
9229        GIR_EraseFromParent, /*InsnID*/0,
9230        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9231        // GIR_Coverage, 1255,
9232        GIR_Done,
9233      // Label 644: @21273
9234      GIM_Try, /*On fail goto*//*Label 645*/ 21325, // Rule ID 1256 //
9235        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
9236        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precrq_qb_ph,
9237        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
9238        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
9239        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
9240        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9241        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
9242        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
9243        // (intrinsic_wo_chain:{ *:[v4i8] } 4167:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (PRECRQ_QB_PH_MM:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
9244        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECRQ_QB_PH_MM,
9245        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9246        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
9247        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
9248        GIR_EraseFromParent, /*InsnID*/0,
9249        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9250        // GIR_Coverage, 1256,
9251        GIR_Done,
9252      // Label 645: @21325
9253      GIM_Try, /*On fail goto*//*Label 646*/ 21377, // Rule ID 1275 //
9254        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
9255        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_packrl_ph,
9256        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
9257        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
9258        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
9259        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9260        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
9261        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
9262        // (intrinsic_wo_chain:{ *:[v2i16] } 4138:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (PACKRL_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
9263        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PACKRL_PH_MM,
9264        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9265        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
9266        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
9267        GIR_EraseFromParent, /*InsnID*/0,
9268        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9269        // GIR_Coverage, 1275,
9270        GIR_Done,
9271      // Label 646: @21377
9272      GIM_Try, /*On fail goto*//*Label 647*/ 21429, // Rule ID 1281 //
9273        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
9274        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_modsub,
9275        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
9276        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
9277        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
9278        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
9279        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
9280        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
9281        // (intrinsic_wo_chain:{ *:[i32] } 4091:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MODSUB_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
9282        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MODSUB_MM,
9283        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9284        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
9285        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
9286        GIR_EraseFromParent, /*InsnID*/0,
9287        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9288        // GIR_Coverage, 1281,
9289        GIR_Done,
9290      // Label 647: @21429
9291      GIM_Try, /*On fail goto*//*Label 648*/ 21481, // Rule ID 1294 //
9292        GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
9293        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addqh_ph,
9294        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
9295        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
9296        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
9297        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9298        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
9299        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
9300        // (intrinsic_wo_chain:{ *:[v2i16] } 3645:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (ADDQH_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
9301        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_PH_MMR2,
9302        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9303        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
9304        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
9305        GIR_EraseFromParent, /*InsnID*/0,
9306        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9307        // GIR_Coverage, 1294,
9308        GIR_Done,
9309      // Label 648: @21481
9310      GIM_Try, /*On fail goto*//*Label 649*/ 21533, // Rule ID 1295 //
9311        GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
9312        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addqh_r_ph,
9313        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
9314        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
9315        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
9316        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9317        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
9318        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
9319        // (intrinsic_wo_chain:{ *:[v2i16] } 3646:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (ADDQH_R_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
9320        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_R_PH_MMR2,
9321        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9322        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
9323        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
9324        GIR_EraseFromParent, /*InsnID*/0,
9325        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9326        // GIR_Coverage, 1295,
9327        GIR_Done,
9328      // Label 649: @21533
9329      GIM_Try, /*On fail goto*//*Label 650*/ 21585, // Rule ID 1296 //
9330        GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
9331        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addqh_w,
9332        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
9333        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
9334        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
9335        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
9336        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
9337        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
9338        // (intrinsic_wo_chain:{ *:[i32] } 3648:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (ADDQH_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
9339        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_W_MMR2,
9340        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9341        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
9342        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
9343        GIR_EraseFromParent, /*InsnID*/0,
9344        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9345        // GIR_Coverage, 1296,
9346        GIR_Done,
9347      // Label 650: @21585
9348      GIM_Try, /*On fail goto*//*Label 651*/ 21637, // Rule ID 1297 //
9349        GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
9350        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addqh_r_w,
9351        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
9352        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
9353        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
9354        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
9355        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
9356        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
9357        // (intrinsic_wo_chain:{ *:[i32] } 3647:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (ADDQH_R_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
9358        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_R_W_MMR2,
9359        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9360        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
9361        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
9362        GIR_EraseFromParent, /*InsnID*/0,
9363        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9364        // GIR_Coverage, 1297,
9365        GIR_Done,
9366      // Label 651: @21637
9367      GIM_Try, /*On fail goto*//*Label 652*/ 21689, // Rule ID 1300 //
9368        GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
9369        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adduh_qb,
9370        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
9371        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
9372        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
9373        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9374        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
9375        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
9376        // (intrinsic_wo_chain:{ *:[v4i8] } 3666:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (ADDUH_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
9377        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDUH_QB_MMR2,
9378        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9379        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
9380        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
9381        GIR_EraseFromParent, /*InsnID*/0,
9382        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9383        // GIR_Coverage, 1300,
9384        GIR_Done,
9385      // Label 652: @21689
9386      GIM_Try, /*On fail goto*//*Label 653*/ 21741, // Rule ID 1301 //
9387        GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
9388        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adduh_r_qb,
9389        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
9390        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
9391        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
9392        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9393        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
9394        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
9395        // (intrinsic_wo_chain:{ *:[v4i8] } 3667:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (ADDUH_R_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
9396        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDUH_R_QB_MMR2,
9397        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9398        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
9399        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
9400        GIR_EraseFromParent, /*InsnID*/0,
9401        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9402        // GIR_Coverage, 1301,
9403        GIR_Done,
9404      // Label 653: @21741
9405      GIM_Try, /*On fail goto*//*Label 654*/ 21793, // Rule ID 1307 //
9406        GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
9407        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_qb,
9408        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
9409        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
9410        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
9411        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9412        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
9413        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
9414        // (intrinsic_wo_chain:{ *:[v4i8] } 4192:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)  =>  (SHRAV_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
9415        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_QB_MMR2,
9416        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9417        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
9418        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
9419        GIR_EraseFromParent, /*InsnID*/0,
9420        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9421        // GIR_Coverage, 1307,
9422        GIR_Done,
9423      // Label 654: @21793
9424      GIM_Try, /*On fail goto*//*Label 655*/ 21845, // Rule ID 1308 //
9425        GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
9426        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_qb,
9427        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
9428        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
9429        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
9430        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9431        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
9432        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
9433        // (intrinsic_wo_chain:{ *:[v4i8] } 4194:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)  =>  (SHRAV_R_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
9434        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_R_QB_MMR2,
9435        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9436        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
9437        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
9438        GIR_EraseFromParent, /*InsnID*/0,
9439        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9440        // GIR_Coverage, 1308,
9441        GIR_Done,
9442      // Label 655: @21845
9443      GIM_Try, /*On fail goto*//*Label 656*/ 21897, // Rule ID 1313 //
9444        GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
9445        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shrl_ph,
9446        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
9447        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
9448        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
9449        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9450        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
9451        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
9452        // (intrinsic_wo_chain:{ *:[v2i16] } 4196:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)  =>  (SHRLV_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
9453        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRLV_PH_MMR2,
9454        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9455        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
9456        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
9457        GIR_EraseFromParent, /*InsnID*/0,
9458        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9459        // GIR_Coverage, 1313,
9460        GIR_Done,
9461      // Label 656: @21897
9462      GIM_Try, /*On fail goto*//*Label 657*/ 21949, // Rule ID 1314 //
9463        GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
9464        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subqh_ph,
9465        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
9466        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
9467        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
9468        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9469        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
9470        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
9471        // (intrinsic_wo_chain:{ *:[v2i16] } 4261:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (SUBQH_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
9472        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQH_PH_MMR2,
9473        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9474        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
9475        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
9476        GIR_EraseFromParent, /*InsnID*/0,
9477        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9478        // GIR_Coverage, 1314,
9479        GIR_Done,
9480      // Label 657: @21949
9481      GIM_Try, /*On fail goto*//*Label 658*/ 22001, // Rule ID 1315 //
9482        GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
9483        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subqh_r_ph,
9484        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
9485        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
9486        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
9487        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9488        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
9489        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
9490        // (intrinsic_wo_chain:{ *:[v2i16] } 4262:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (SUBQH_R_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
9491        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQH_R_PH_MMR2,
9492        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9493        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
9494        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
9495        GIR_EraseFromParent, /*InsnID*/0,
9496        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9497        // GIR_Coverage, 1315,
9498        GIR_Done,
9499      // Label 658: @22001
9500      GIM_Try, /*On fail goto*//*Label 659*/ 22053, // Rule ID 1316 //
9501        GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
9502        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subqh_w,
9503        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
9504        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
9505        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
9506        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
9507        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
9508        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
9509        // (intrinsic_wo_chain:{ *:[i32] } 4264:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (SUBQH_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
9510        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQH_W_MMR2,
9511        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9512        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
9513        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
9514        GIR_EraseFromParent, /*InsnID*/0,
9515        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9516        // GIR_Coverage, 1316,
9517        GIR_Done,
9518      // Label 659: @22053
9519      GIM_Try, /*On fail goto*//*Label 660*/ 22105, // Rule ID 1317 //
9520        GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
9521        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subqh_r_w,
9522        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
9523        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
9524        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
9525        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
9526        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
9527        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
9528        // (intrinsic_wo_chain:{ *:[i32] } 4263:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (SUBQH_R_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
9529        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQH_R_W_MMR2,
9530        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9531        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
9532        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
9533        GIR_EraseFromParent, /*InsnID*/0,
9534        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9535        // GIR_Coverage, 1317,
9536        GIR_Done,
9537      // Label 660: @22105
9538      GIM_Try, /*On fail goto*//*Label 661*/ 22157, // Rule ID 1320 //
9539        GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
9540        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subuh_qb,
9541        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
9542        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
9543        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
9544        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9545        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
9546        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
9547        // (intrinsic_wo_chain:{ *:[v4i8] } 4285:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (SUBUH_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
9548        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBUH_QB_MMR2,
9549        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9550        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
9551        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
9552        GIR_EraseFromParent, /*InsnID*/0,
9553        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9554        // GIR_Coverage, 1320,
9555        GIR_Done,
9556      // Label 661: @22157
9557      GIM_Try, /*On fail goto*//*Label 662*/ 22209, // Rule ID 1321 //
9558        GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
9559        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subuh_r_qb,
9560        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
9561        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
9562        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
9563        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9564        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
9565        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
9566        // (intrinsic_wo_chain:{ *:[v4i8] } 4286:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (SUBUH_R_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
9567        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBUH_R_QB_MMR2,
9568        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9569        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
9570        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
9571        GIR_EraseFromParent, /*InsnID*/0,
9572        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9573        // GIR_Coverage, 1321,
9574        GIR_Done,
9575      // Label 662: @22209
9576      GIM_Try, /*On fail goto*//*Label 663*/ 22253, // Rule ID 1875 //
9577        GIM_CheckFeatures, GIFBS_HasDSP,
9578        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addq_ph,
9579        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
9580        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
9581        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
9582        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9583        // (intrinsic_wo_chain:{ *:[v2i16] } 3642:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)  =>  (ADDQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
9584        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQ_PH,
9585        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9586        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
9587        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
9588        GIR_EraseFromParent, /*InsnID*/0,
9589        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9590        // GIR_Coverage, 1875,
9591        GIR_Done,
9592      // Label 663: @22253
9593      GIM_Try, /*On fail goto*//*Label 664*/ 22297, // Rule ID 1877 //
9594        GIM_CheckFeatures, GIFBS_HasDSP,
9595        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subq_ph,
9596        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
9597        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
9598        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
9599        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9600        // (intrinsic_wo_chain:{ *:[v2i16] } 4258:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)  =>  (SUBQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
9601        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQ_PH,
9602        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9603        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
9604        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
9605        GIR_EraseFromParent, /*InsnID*/0,
9606        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9607        // GIR_Coverage, 1877,
9608        GIR_Done,
9609      // Label 664: @22297
9610      GIM_Try, /*On fail goto*//*Label 665*/ 22341, // Rule ID 1881 //
9611        GIM_CheckFeatures, GIFBS_HasDSP,
9612        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addu_qb,
9613        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
9614        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
9615        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
9616        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9617        // (intrinsic_wo_chain:{ *:[v4i8] } 3663:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)  =>  (ADDU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)
9618        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDU_QB,
9619        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9620        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
9621        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
9622        GIR_EraseFromParent, /*InsnID*/0,
9623        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9624        // GIR_Coverage, 1881,
9625        GIR_Done,
9626      // Label 665: @22341
9627      GIM_Try, /*On fail goto*//*Label 666*/ 22385, // Rule ID 1883 //
9628        GIM_CheckFeatures, GIFBS_HasDSP,
9629        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subu_qb,
9630        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
9631        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
9632        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
9633        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9634        // (intrinsic_wo_chain:{ *:[v4i8] } 4282:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)  =>  (SUBU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)
9635        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBU_QB,
9636        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9637        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
9638        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
9639        GIR_EraseFromParent, /*InsnID*/0,
9640        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9641        // GIR_Coverage, 1883,
9642        GIR_Done,
9643      // Label 666: @22385
9644      GIM_Reject,
9645    // Label 452: @22386
9646    GIM_Try, /*On fail goto*//*Label 667*/ 25274,
9647      GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
9648      GIM_Try, /*On fail goto*//*Label 668*/ 22450, // Rule ID 465 //
9649        GIM_CheckFeatures, GIFBS_HasDSPR2,
9650        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precr_sra_ph_w,
9651        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
9652        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
9653        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
9654        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9655        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
9656        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
9657        // MIs[0] sa
9658        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
9659        // (intrinsic_wo_chain:{ *:[v2i16] } 4164:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa)  =>  (PRECR_SRA_PH_W:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
9660        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECR_SRA_PH_W,
9661        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
9662        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
9663        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // sa
9664        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
9665        GIR_EraseFromParent, /*InsnID*/0,
9666        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9667        // GIR_Coverage, 465,
9668        GIR_Done,
9669      // Label 668: @22450
9670      GIM_Try, /*On fail goto*//*Label 669*/ 22509, // Rule ID 466 //
9671        GIM_CheckFeatures, GIFBS_HasDSPR2,
9672        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precr_sra_r_ph_w,
9673        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
9674        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
9675        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
9676        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9677        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
9678        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
9679        // MIs[0] sa
9680        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
9681        // (intrinsic_wo_chain:{ *:[v2i16] } 4165:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa)  =>  (PRECR_SRA_R_PH_W:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
9682        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECR_SRA_R_PH_W,
9683        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
9684        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
9685        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // sa
9686        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
9687        GIR_EraseFromParent, /*InsnID*/0,
9688        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9689        // GIR_Coverage, 466,
9690        GIR_Done,
9691      // Label 669: @22509
9692      GIM_Try, /*On fail goto*//*Label 670*/ 22568, // Rule ID 471 //
9693        GIM_CheckFeatures, GIFBS_HasDSPR2,
9694        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_append,
9695        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
9696        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
9697        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
9698        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
9699        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
9700        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
9701        // MIs[0] sa
9702        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
9703        // (intrinsic_wo_chain:{ *:[i32] } 3679:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa)  =>  (APPEND:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
9704        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::APPEND,
9705        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
9706        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
9707        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // sa
9708        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
9709        GIR_EraseFromParent, /*InsnID*/0,
9710        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9711        // GIR_Coverage, 471,
9712        GIR_Done,
9713      // Label 670: @22568
9714      GIM_Try, /*On fail goto*//*Label 671*/ 22627, // Rule ID 472 //
9715        GIM_CheckFeatures, GIFBS_HasDSPR2,
9716        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_balign,
9717        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
9718        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
9719        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
9720        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
9721        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
9722        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
9723        // MIs[0] sa
9724        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
9725        // (intrinsic_wo_chain:{ *:[i32] } 3704:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt2>>:$sa)  =>  (BALIGN:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
9726        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BALIGN,
9727        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
9728        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
9729        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // sa
9730        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
9731        GIR_EraseFromParent, /*InsnID*/0,
9732        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9733        // GIR_Coverage, 472,
9734        GIR_Done,
9735      // Label 671: @22627
9736      GIM_Try, /*On fail goto*//*Label 672*/ 22686, // Rule ID 473 //
9737        GIM_CheckFeatures, GIFBS_HasDSPR2,
9738        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_prepend,
9739        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
9740        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
9741        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
9742        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
9743        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
9744        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
9745        // MIs[0] sa
9746        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
9747        // (intrinsic_wo_chain:{ *:[i32] } 4170:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa)  =>  (PREPEND:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
9748        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PREPEND,
9749        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
9750        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
9751        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // sa
9752        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
9753        GIR_EraseFromParent, /*InsnID*/0,
9754        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9755        // GIR_Coverage, 473,
9756        GIR_Done,
9757      // Label 672: @22686
9758      GIM_Try, /*On fail goto*//*Label 673*/ 22745, // Rule ID 937 //
9759        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
9760        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sldi_b,
9761        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
9762        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
9763        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
9764        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
9765        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
9766        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
9767        // MIs[0] n
9768        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
9769        // (intrinsic_wo_chain:{ *:[v16i8] } 4202:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt4>>:$n)  =>  (SLDI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] }):$n)
9770        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLDI_B,
9771        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
9772        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
9773        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
9774        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // n
9775        GIR_EraseFromParent, /*InsnID*/0,
9776        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9777        // GIR_Coverage, 937,
9778        GIR_Done,
9779      // Label 673: @22745
9780      GIM_Try, /*On fail goto*//*Label 674*/ 22804, // Rule ID 938 //
9781        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
9782        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sldi_h,
9783        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
9784        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
9785        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
9786        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
9787        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
9788        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
9789        // MIs[0] n
9790        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
9791        // (intrinsic_wo_chain:{ *:[v8i16] } 4204:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt3>>:$n)  =>  (SLDI_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] }):$n)
9792        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLDI_H,
9793        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
9794        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
9795        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
9796        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // n
9797        GIR_EraseFromParent, /*InsnID*/0,
9798        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9799        // GIR_Coverage, 938,
9800        GIR_Done,
9801      // Label 674: @22804
9802      GIM_Try, /*On fail goto*//*Label 675*/ 22863, // Rule ID 939 //
9803        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
9804        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sldi_w,
9805        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
9806        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
9807        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
9808        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
9809        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
9810        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
9811        // MIs[0] n
9812        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
9813        // (intrinsic_wo_chain:{ *:[v4i32] } 4205:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt2>>:$n)  =>  (SLDI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] }):$n)
9814        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLDI_W,
9815        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
9816        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
9817        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
9818        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // n
9819        GIR_EraseFromParent, /*InsnID*/0,
9820        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9821        // GIR_Coverage, 939,
9822        GIR_Done,
9823      // Label 675: @22863
9824      GIM_Try, /*On fail goto*//*Label 676*/ 22922, // Rule ID 940 //
9825        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
9826        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sldi_d,
9827        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
9828        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
9829        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
9830        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
9831        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
9832        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
9833        // MIs[0] n
9834        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
9835        // (intrinsic_wo_chain:{ *:[v2i64] } 4203:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt1>>:$n)  =>  (SLDI_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] }):$n)
9836        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLDI_D,
9837        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
9838        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
9839        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
9840        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // n
9841        GIR_EraseFromParent, /*InsnID*/0,
9842        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9843        // GIR_Coverage, 940,
9844        GIR_Done,
9845      // Label 676: @22922
9846      GIM_Try, /*On fail goto*//*Label 677*/ 22981, // Rule ID 1331 //
9847        GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
9848        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precr_sra_ph_w,
9849        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
9850        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
9851        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
9852        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9853        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
9854        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
9855        // MIs[0] sa
9856        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
9857        // (intrinsic_wo_chain:{ *:[v2i16] } 4164:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa)  =>  (PRECR_SRA_PH_W_MMR2:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
9858        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECR_SRA_PH_W_MMR2,
9859        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
9860        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
9861        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // sa
9862        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
9863        GIR_EraseFromParent, /*InsnID*/0,
9864        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9865        // GIR_Coverage, 1331,
9866        GIR_Done,
9867      // Label 677: @22981
9868      GIM_Try, /*On fail goto*//*Label 678*/ 23040, // Rule ID 1332 //
9869        GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
9870        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precr_sra_r_ph_w,
9871        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
9872        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
9873        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
9874        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9875        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
9876        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
9877        // MIs[0] sa
9878        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
9879        // (intrinsic_wo_chain:{ *:[v2i16] } 4165:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa)  =>  (PRECR_SRA_R_PH_W_MMR2:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
9880        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECR_SRA_R_PH_W_MMR2,
9881        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
9882        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
9883        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // sa
9884        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
9885        GIR_EraseFromParent, /*InsnID*/0,
9886        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9887        // GIR_Coverage, 1332,
9888        GIR_Done,
9889      // Label 678: @23040
9890      GIM_Try, /*On fail goto*//*Label 679*/ 23099, // Rule ID 1333 //
9891        GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
9892        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_prepend,
9893        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
9894        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
9895        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
9896        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
9897        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
9898        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
9899        // MIs[0] sa
9900        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
9901        // (intrinsic_wo_chain:{ *:[i32] } 4170:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa)  =>  (PREPEND_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
9902        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PREPEND_MMR2,
9903        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
9904        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
9905        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // sa
9906        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
9907        GIR_EraseFromParent, /*InsnID*/0,
9908        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9909        // GIR_Coverage, 1333,
9910        GIR_Done,
9911      // Label 679: @23099
9912      GIM_Try, /*On fail goto*//*Label 680*/ 23158, // Rule ID 1334 //
9913        GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
9914        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_append,
9915        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
9916        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
9917        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
9918        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
9919        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
9920        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
9921        // MIs[0] sa
9922        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
9923        // (intrinsic_wo_chain:{ *:[i32] } 3679:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa)  =>  (APPEND_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
9924        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::APPEND_MMR2,
9925        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
9926        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
9927        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // sa
9928        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
9929        GIR_EraseFromParent, /*InsnID*/0,
9930        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9931        // GIR_Coverage, 1334,
9932        GIR_Done,
9933      // Label 680: @23158
9934      GIM_Try, /*On fail goto*//*Label 681*/ 23225, // Rule ID 1309 //
9935        GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
9936        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_balign,
9937        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
9938        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
9939        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
9940        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
9941        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
9942        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
9943        // MIs[0] bp
9944        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
9945        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
9946        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt2,
9947        // MIs[1] Operand 1
9948        // No operand predicates
9949        GIM_CheckIsSafeToFold, /*InsnID*/1,
9950        // (intrinsic_wo_chain:{ *:[i32] } 3704:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2>>:$bp)  =>  (BALIGN_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$bp, GPR32Opnd:{ *:[i32] }:$src)
9951        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BALIGN_MMR2,
9952        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
9953        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
9954        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // bp
9955        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
9956        GIR_EraseFromParent, /*InsnID*/0,
9957        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9958        // GIR_Coverage, 1309,
9959        GIR_Done,
9960      // Label 681: @23225
9961      GIM_Try, /*On fail goto*//*Label 682*/ 23289, // Rule ID 536 //
9962        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
9963        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_binsl_b,
9964        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
9965        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
9966        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
9967        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
9968        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
9969        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
9970        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
9971        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128BRegClassID,
9972        // (intrinsic_wo_chain:{ *:[v16i8] } 3713:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (BINSL_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
9973        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BINSL_B,
9974        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
9975        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
9976        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
9977        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
9978        GIR_EraseFromParent, /*InsnID*/0,
9979        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9980        // GIR_Coverage, 536,
9981        GIR_Done,
9982      // Label 682: @23289
9983      GIM_Try, /*On fail goto*//*Label 683*/ 23353, // Rule ID 537 //
9984        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
9985        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_binsl_h,
9986        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
9987        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
9988        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
9989        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
9990        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
9991        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
9992        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
9993        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID,
9994        // (intrinsic_wo_chain:{ *:[v8i16] } 3715:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (BINSL_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
9995        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BINSL_H,
9996        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
9997        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
9998        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
9999        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10000        GIR_EraseFromParent, /*InsnID*/0,
10001        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10002        // GIR_Coverage, 537,
10003        GIR_Done,
10004      // Label 683: @23353
10005      GIM_Try, /*On fail goto*//*Label 684*/ 23417, // Rule ID 538 //
10006        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10007        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_binsl_w,
10008        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
10009        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
10010        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
10011        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
10012        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
10013        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
10014        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
10015        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID,
10016        // (intrinsic_wo_chain:{ *:[v4i32] } 3716:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (BINSL_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10017        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BINSL_W,
10018        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10019        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10020        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10021        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10022        GIR_EraseFromParent, /*InsnID*/0,
10023        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10024        // GIR_Coverage, 538,
10025        GIR_Done,
10026      // Label 684: @23417
10027      GIM_Try, /*On fail goto*//*Label 685*/ 23481, // Rule ID 539 //
10028        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10029        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_binsl_d,
10030        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
10031        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
10032        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
10033        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s64,
10034        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
10035        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
10036        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
10037        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128DRegClassID,
10038        // (intrinsic_wo_chain:{ *:[v2i64] } 3714:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (BINSL_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
10039        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BINSL_D,
10040        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10041        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10042        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10043        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10044        GIR_EraseFromParent, /*InsnID*/0,
10045        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10046        // GIR_Coverage, 539,
10047        GIR_Done,
10048      // Label 685: @23481
10049      GIM_Try, /*On fail goto*//*Label 686*/ 23545, // Rule ID 544 //
10050        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10051        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_binsr_b,
10052        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
10053        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
10054        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
10055        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
10056        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
10057        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
10058        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
10059        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128BRegClassID,
10060        // (intrinsic_wo_chain:{ *:[v16i8] } 3721:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (BINSR_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
10061        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BINSR_B,
10062        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10063        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10064        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10065        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10066        GIR_EraseFromParent, /*InsnID*/0,
10067        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10068        // GIR_Coverage, 544,
10069        GIR_Done,
10070      // Label 686: @23545
10071      GIM_Try, /*On fail goto*//*Label 687*/ 23609, // Rule ID 545 //
10072        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10073        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_binsr_h,
10074        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
10075        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
10076        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
10077        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
10078        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
10079        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
10080        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
10081        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID,
10082        // (intrinsic_wo_chain:{ *:[v8i16] } 3723:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (BINSR_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10083        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BINSR_H,
10084        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10085        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10086        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10087        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10088        GIR_EraseFromParent, /*InsnID*/0,
10089        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10090        // GIR_Coverage, 545,
10091        GIR_Done,
10092      // Label 687: @23609
10093      GIM_Try, /*On fail goto*//*Label 688*/ 23673, // Rule ID 546 //
10094        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10095        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_binsr_w,
10096        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
10097        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
10098        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
10099        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
10100        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
10101        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
10102        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
10103        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID,
10104        // (intrinsic_wo_chain:{ *:[v4i32] } 3724:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (BINSR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10105        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BINSR_W,
10106        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10107        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10108        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10109        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10110        GIR_EraseFromParent, /*InsnID*/0,
10111        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10112        // GIR_Coverage, 546,
10113        GIR_Done,
10114      // Label 688: @23673
10115      GIM_Try, /*On fail goto*//*Label 689*/ 23737, // Rule ID 547 //
10116        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10117        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_binsr_d,
10118        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
10119        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
10120        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
10121        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s64,
10122        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
10123        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
10124        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
10125        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128DRegClassID,
10126        // (intrinsic_wo_chain:{ *:[v2i64] } 3722:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (BINSR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
10127        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BINSR_D,
10128        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10129        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10130        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10131        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10132        GIR_EraseFromParent, /*InsnID*/0,
10133        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10134        // GIR_Coverage, 547,
10135        GIR_Done,
10136      // Label 689: @23737
10137      GIM_Try, /*On fail goto*//*Label 690*/ 23801, // Rule ID 642 //
10138        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10139        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpadd_s_h,
10140        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
10141        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
10142        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
10143        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
10144        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
10145        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
10146        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
10147        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128BRegClassID,
10148        // (intrinsic_wo_chain:{ *:[v8i16] } 3842:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (DPADD_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
10149        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPADD_S_H,
10150        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10151        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10152        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10153        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10154        GIR_EraseFromParent, /*InsnID*/0,
10155        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10156        // GIR_Coverage, 642,
10157        GIR_Done,
10158      // Label 690: @23801
10159      GIM_Try, /*On fail goto*//*Label 691*/ 23865, // Rule ID 643 //
10160        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10161        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpadd_s_w,
10162        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
10163        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
10164        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
10165        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
10166        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
10167        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
10168        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
10169        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID,
10170        // (intrinsic_wo_chain:{ *:[v4i32] } 3843:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (DPADD_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10171        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPADD_S_W,
10172        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10173        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10174        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10175        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10176        GIR_EraseFromParent, /*InsnID*/0,
10177        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10178        // GIR_Coverage, 643,
10179        GIR_Done,
10180      // Label 691: @23865
10181      GIM_Try, /*On fail goto*//*Label 692*/ 23929, // Rule ID 644 //
10182        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10183        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpadd_s_d,
10184        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
10185        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
10186        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
10187        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
10188        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
10189        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
10190        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
10191        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID,
10192        // (intrinsic_wo_chain:{ *:[v2i64] } 3841:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (DPADD_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10193        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPADD_S_D,
10194        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10195        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10196        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10197        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10198        GIR_EraseFromParent, /*InsnID*/0,
10199        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10200        // GIR_Coverage, 644,
10201        GIR_Done,
10202      // Label 692: @23929
10203      GIM_Try, /*On fail goto*//*Label 693*/ 23993, // Rule ID 645 //
10204        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10205        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpadd_u_h,
10206        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
10207        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
10208        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
10209        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
10210        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
10211        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
10212        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
10213        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128BRegClassID,
10214        // (intrinsic_wo_chain:{ *:[v8i16] } 3845:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (DPADD_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
10215        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPADD_U_H,
10216        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10217        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10218        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10219        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10220        GIR_EraseFromParent, /*InsnID*/0,
10221        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10222        // GIR_Coverage, 645,
10223        GIR_Done,
10224      // Label 693: @23993
10225      GIM_Try, /*On fail goto*//*Label 694*/ 24057, // Rule ID 646 //
10226        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10227        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpadd_u_w,
10228        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
10229        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
10230        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
10231        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
10232        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
10233        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
10234        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
10235        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID,
10236        // (intrinsic_wo_chain:{ *:[v4i32] } 3846:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (DPADD_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10237        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPADD_U_W,
10238        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10239        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10240        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10241        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10242        GIR_EraseFromParent, /*InsnID*/0,
10243        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10244        // GIR_Coverage, 646,
10245        GIR_Done,
10246      // Label 694: @24057
10247      GIM_Try, /*On fail goto*//*Label 695*/ 24121, // Rule ID 647 //
10248        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10249        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpadd_u_d,
10250        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
10251        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
10252        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
10253        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
10254        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
10255        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
10256        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
10257        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID,
10258        // (intrinsic_wo_chain:{ *:[v2i64] } 3844:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (DPADD_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10259        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPADD_U_D,
10260        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10261        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10262        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10263        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10264        GIR_EraseFromParent, /*InsnID*/0,
10265        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10266        // GIR_Coverage, 647,
10267        GIR_Done,
10268      // Label 695: @24121
10269      GIM_Try, /*On fail goto*//*Label 696*/ 24185, // Rule ID 648 //
10270        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10271        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpsub_s_h,
10272        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
10273        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
10274        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
10275        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
10276        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
10277        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
10278        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
10279        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128BRegClassID,
10280        // (intrinsic_wo_chain:{ *:[v8i16] } 3862:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (DPSUB_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
10281        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPSUB_S_H,
10282        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10283        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10284        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10285        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10286        GIR_EraseFromParent, /*InsnID*/0,
10287        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10288        // GIR_Coverage, 648,
10289        GIR_Done,
10290      // Label 696: @24185
10291      GIM_Try, /*On fail goto*//*Label 697*/ 24249, // Rule ID 649 //
10292        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10293        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpsub_s_w,
10294        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
10295        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
10296        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
10297        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
10298        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
10299        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
10300        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
10301        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID,
10302        // (intrinsic_wo_chain:{ *:[v4i32] } 3863:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (DPSUB_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10303        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPSUB_S_W,
10304        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10305        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10306        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10307        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10308        GIR_EraseFromParent, /*InsnID*/0,
10309        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10310        // GIR_Coverage, 649,
10311        GIR_Done,
10312      // Label 697: @24249
10313      GIM_Try, /*On fail goto*//*Label 698*/ 24313, // Rule ID 650 //
10314        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10315        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpsub_s_d,
10316        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
10317        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
10318        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
10319        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
10320        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
10321        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
10322        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
10323        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID,
10324        // (intrinsic_wo_chain:{ *:[v2i64] } 3861:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (DPSUB_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10325        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPSUB_S_D,
10326        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10327        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10328        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10329        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10330        GIR_EraseFromParent, /*InsnID*/0,
10331        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10332        // GIR_Coverage, 650,
10333        GIR_Done,
10334      // Label 698: @24313
10335      GIM_Try, /*On fail goto*//*Label 699*/ 24377, // Rule ID 651 //
10336        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10337        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpsub_u_h,
10338        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
10339        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
10340        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
10341        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
10342        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
10343        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
10344        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
10345        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128BRegClassID,
10346        // (intrinsic_wo_chain:{ *:[v8i16] } 3865:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (DPSUB_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
10347        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPSUB_U_H,
10348        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10349        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10350        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10351        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10352        GIR_EraseFromParent, /*InsnID*/0,
10353        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10354        // GIR_Coverage, 651,
10355        GIR_Done,
10356      // Label 699: @24377
10357      GIM_Try, /*On fail goto*//*Label 700*/ 24441, // Rule ID 652 //
10358        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10359        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpsub_u_w,
10360        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
10361        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
10362        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
10363        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
10364        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
10365        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
10366        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
10367        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID,
10368        // (intrinsic_wo_chain:{ *:[v4i32] } 3866:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (DPSUB_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10369        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPSUB_U_W,
10370        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10371        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10372        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10373        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10374        GIR_EraseFromParent, /*InsnID*/0,
10375        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10376        // GIR_Coverage, 652,
10377        GIR_Done,
10378      // Label 700: @24441
10379      GIM_Try, /*On fail goto*//*Label 701*/ 24505, // Rule ID 653 //
10380        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10381        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpsub_u_d,
10382        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
10383        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
10384        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
10385        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
10386        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
10387        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
10388        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
10389        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID,
10390        // (intrinsic_wo_chain:{ *:[v2i64] } 3864:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (DPSUB_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10391        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPSUB_U_D,
10392        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10393        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10394        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10395        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10396        GIR_EraseFromParent, /*InsnID*/0,
10397        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10398        // GIR_Coverage, 653,
10399        GIR_Done,
10400      // Label 701: @24505
10401      GIM_Try, /*On fail goto*//*Label 702*/ 24569, // Rule ID 820 //
10402        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10403        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_madd_q_h,
10404        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
10405        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
10406        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
10407        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
10408        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
10409        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
10410        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
10411        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID,
10412        // (intrinsic_wo_chain:{ *:[v8i16] } 4030:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (MADD_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10413        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADD_Q_H,
10414        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10415        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10416        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10417        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10418        GIR_EraseFromParent, /*InsnID*/0,
10419        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10420        // GIR_Coverage, 820,
10421        GIR_Done,
10422      // Label 702: @24569
10423      GIM_Try, /*On fail goto*//*Label 703*/ 24633, // Rule ID 821 //
10424        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10425        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_madd_q_w,
10426        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
10427        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
10428        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
10429        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
10430        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
10431        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
10432        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
10433        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID,
10434        // (intrinsic_wo_chain:{ *:[v4i32] } 4031:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (MADD_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10435        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADD_Q_W,
10436        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10437        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10438        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10439        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10440        GIR_EraseFromParent, /*InsnID*/0,
10441        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10442        // GIR_Coverage, 821,
10443        GIR_Done,
10444      // Label 703: @24633
10445      GIM_Try, /*On fail goto*//*Label 704*/ 24697, // Rule ID 822 //
10446        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10447        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_maddr_q_h,
10448        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
10449        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
10450        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
10451        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
10452        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
10453        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
10454        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
10455        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID,
10456        // (intrinsic_wo_chain:{ *:[v8i16] } 4032:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (MADDR_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10457        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDR_Q_H,
10458        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10459        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10460        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10461        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10462        GIR_EraseFromParent, /*InsnID*/0,
10463        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10464        // GIR_Coverage, 822,
10465        GIR_Done,
10466      // Label 704: @24697
10467      GIM_Try, /*On fail goto*//*Label 705*/ 24761, // Rule ID 823 //
10468        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10469        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_maddr_q_w,
10470        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
10471        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
10472        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
10473        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
10474        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
10475        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
10476        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
10477        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID,
10478        // (intrinsic_wo_chain:{ *:[v4i32] } 4033:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (MADDR_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10479        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDR_Q_W,
10480        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10481        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10482        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10483        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10484        GIR_EraseFromParent, /*InsnID*/0,
10485        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10486        // GIR_Coverage, 823,
10487        GIR_Done,
10488      // Label 705: @24761
10489      GIM_Try, /*On fail goto*//*Label 706*/ 24825, // Rule ID 876 //
10490        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10491        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_msub_q_h,
10492        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
10493        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
10494        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
10495        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
10496        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
10497        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
10498        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
10499        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID,
10500        // (intrinsic_wo_chain:{ *:[v8i16] } 4094:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (MSUB_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10501        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUB_Q_H,
10502        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10503        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10504        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10505        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10506        GIR_EraseFromParent, /*InsnID*/0,
10507        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10508        // GIR_Coverage, 876,
10509        GIR_Done,
10510      // Label 706: @24825
10511      GIM_Try, /*On fail goto*//*Label 707*/ 24889, // Rule ID 877 //
10512        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10513        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_msub_q_w,
10514        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
10515        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
10516        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
10517        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
10518        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
10519        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
10520        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
10521        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID,
10522        // (intrinsic_wo_chain:{ *:[v4i32] } 4095:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (MSUB_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10523        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUB_Q_W,
10524        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10525        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10526        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10527        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10528        GIR_EraseFromParent, /*InsnID*/0,
10529        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10530        // GIR_Coverage, 877,
10531        GIR_Done,
10532      // Label 707: @24889
10533      GIM_Try, /*On fail goto*//*Label 708*/ 24953, // Rule ID 878 //
10534        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10535        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_msubr_q_h,
10536        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
10537        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
10538        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
10539        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
10540        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
10541        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
10542        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
10543        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID,
10544        // (intrinsic_wo_chain:{ *:[v8i16] } 4096:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (MSUBR_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10545        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBR_Q_H,
10546        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10547        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10548        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10549        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10550        GIR_EraseFromParent, /*InsnID*/0,
10551        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10552        // GIR_Coverage, 878,
10553        GIR_Done,
10554      // Label 708: @24953
10555      GIM_Try, /*On fail goto*//*Label 709*/ 25017, // Rule ID 879 //
10556        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10557        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_msubr_q_w,
10558        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
10559        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
10560        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
10561        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
10562        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
10563        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
10564        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
10565        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID,
10566        // (intrinsic_wo_chain:{ *:[v4i32] } 4097:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (MSUBR_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10567        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBR_Q_W,
10568        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10569        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10570        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10571        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10572        GIR_EraseFromParent, /*InsnID*/0,
10573        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10574        // GIR_Coverage, 879,
10575        GIR_Done,
10576      // Label 709: @25017
10577      GIM_Try, /*On fail goto*//*Label 710*/ 25081, // Rule ID 933 //
10578        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10579        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sld_b,
10580        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
10581        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
10582        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
10583        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
10584        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
10585        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
10586        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
10587        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::GPR32RegClassID,
10588        // (intrinsic_wo_chain:{ *:[v16i8] } 4198:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)  =>  (SLD_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)
10589        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLD_B,
10590        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10591        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10592        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10593        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // rt
10594        GIR_EraseFromParent, /*InsnID*/0,
10595        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10596        // GIR_Coverage, 933,
10597        GIR_Done,
10598      // Label 710: @25081
10599      GIM_Try, /*On fail goto*//*Label 711*/ 25145, // Rule ID 934 //
10600        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10601        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sld_h,
10602        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
10603        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
10604        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
10605        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
10606        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
10607        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
10608        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
10609        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::GPR32RegClassID,
10610        // (intrinsic_wo_chain:{ *:[v8i16] } 4200:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)  =>  (SLD_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)
10611        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLD_H,
10612        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10613        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10614        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10615        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // rt
10616        GIR_EraseFromParent, /*InsnID*/0,
10617        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10618        // GIR_Coverage, 934,
10619        GIR_Done,
10620      // Label 711: @25145
10621      GIM_Try, /*On fail goto*//*Label 712*/ 25209, // Rule ID 935 //
10622        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10623        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sld_w,
10624        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
10625        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
10626        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
10627        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
10628        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
10629        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
10630        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
10631        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::GPR32RegClassID,
10632        // (intrinsic_wo_chain:{ *:[v4i32] } 4201:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)  =>  (SLD_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)
10633        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLD_W,
10634        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10635        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10636        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10637        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // rt
10638        GIR_EraseFromParent, /*InsnID*/0,
10639        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10640        // GIR_Coverage, 935,
10641        GIR_Done,
10642      // Label 712: @25209
10643      GIM_Try, /*On fail goto*//*Label 713*/ 25273, // Rule ID 936 //
10644        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10645        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sld_d,
10646        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
10647        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
10648        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
10649        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
10650        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
10651        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
10652        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
10653        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::GPR32RegClassID,
10654        // (intrinsic_wo_chain:{ *:[v2i64] } 4199:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)  =>  (SLD_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)
10655        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLD_D,
10656        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10657        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10658        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10659        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // rt
10660        GIR_EraseFromParent, /*InsnID*/0,
10661        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10662        // GIR_Coverage, 936,
10663        GIR_Done,
10664      // Label 713: @25273
10665      GIM_Reject,
10666    // Label 667: @25274
10667    GIM_Reject,
10668    // Label 16: @25275
10669    GIM_Try, /*On fail goto*//*Label 714*/ 25308, // Rule ID 342 //
10670      GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
10671      GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_bposge32,
10672      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
10673      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
10674      // (intrinsic_w_chain:{ *:[i32] } 3747:{ *:[iPTR] })  =>  (BPOSGE32_PSEUDO:{ *:[i32] })
10675      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BPOSGE32_PSEUDO,
10676      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10677      GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
10678      GIR_EraseFromParent, /*InsnID*/0,
10679      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10680      // GIR_Coverage, 342,
10681      GIR_Done,
10682    // Label 714: @25308
10683    GIM_Try, /*On fail goto*//*Label 715*/ 26262,
10684      GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
10685      GIM_Try, /*On fail goto*//*Label 716*/ 25352, // Rule ID 429 //
10686        GIM_CheckFeatures, GIFBS_HasDSP,
10687        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_rddsp,
10688        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
10689        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
10690        // MIs[0] mask
10691        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
10692        // (intrinsic_w_chain:{ *:[i32] } 4172:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timmZExt10>>:$mask)  =>  (RDDSP:{ *:[i32] } (timm:{ *:[i32] }):$mask)
10693        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::RDDSP,
10694        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
10695        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // mask
10696        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
10697        GIR_EraseFromParent, /*InsnID*/0,
10698        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10699        // GIR_Coverage, 429,
10700        GIR_Done,
10701      // Label 716: @25352
10702      GIM_Try, /*On fail goto*//*Label 717*/ 25391, // Rule ID 1269 //
10703        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
10704        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_rddsp,
10705        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
10706        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
10707        // MIs[0] mask
10708        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
10709        // (intrinsic_w_chain:{ *:[i32] } 4172:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timmZExt7>>:$mask)  =>  (RDDSP_MM:{ *:[i32] } (timm:{ *:[i32] }):$mask)
10710        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::RDDSP_MM,
10711        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
10712        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // mask
10713        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
10714        GIR_EraseFromParent, /*InsnID*/0,
10715        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10716        // GIR_Coverage, 1269,
10717        GIR_Done,
10718      // Label 717: @25391
10719      GIM_Try, /*On fail goto*//*Label 718*/ 25430, // Rule ID 430 //
10720        GIM_CheckFeatures, GIFBS_HasDSP_NotInMicroMips,
10721        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_wrdsp,
10722        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
10723        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
10724        // MIs[0] mask
10725        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
10726        // (intrinsic_void 4299:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt10>>:$mask)  =>  (WRDSP GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$mask)
10727        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::WRDSP,
10728        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
10729        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // mask
10730        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
10731        GIR_EraseFromParent, /*InsnID*/0,
10732        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10733        // GIR_Coverage, 430,
10734        GIR_Done,
10735      // Label 718: @25430
10736      GIM_Try, /*On fail goto*//*Label 719*/ 25469, // Rule ID 1280 //
10737        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
10738        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_wrdsp,
10739        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
10740        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
10741        // MIs[0] mask
10742        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
10743        // (intrinsic_void 4299:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, (timm:{ *:[i32] })<<P:Predicate_timmZExt7>>:$mask)  =>  (WRDSP_MM GPR32Opnd:{ *:[i32] }:$rt, (timm:{ *:[i32] }):$mask)
10744        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::WRDSP_MM,
10745        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt
10746        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // mask
10747        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
10748        GIR_EraseFromParent, /*InsnID*/0,
10749        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10750        // GIR_Coverage, 1280,
10751        GIR_Done,
10752      // Label 719: @25469
10753      GIM_Try, /*On fail goto*//*Label 720*/ 25513, // Rule ID 351 //
10754        GIM_CheckFeatures, GIFBS_HasDSP,
10755        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_absq_s_ph,
10756        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
10757        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
10758        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
10759        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
10760        // (intrinsic_w_chain:{ *:[v2i16] } 3635:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (ABSQ_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt)
10761        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ABSQ_S_PH,
10762        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
10763        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
10764        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
10765        GIR_EraseFromParent, /*InsnID*/0,
10766        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10767        // GIR_Coverage, 351,
10768        GIR_Done,
10769      // Label 720: @25513
10770      GIM_Try, /*On fail goto*//*Label 721*/ 25557, // Rule ID 352 //
10771        GIM_CheckFeatures, GIFBS_HasDSP,
10772        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_absq_s_w,
10773        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
10774        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
10775        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
10776        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
10777        // (intrinsic_w_chain:{ *:[i32] } 3637:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt)  =>  (ABSQ_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt)
10778        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ABSQ_S_W,
10779        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
10780        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
10781        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
10782        GIR_EraseFromParent, /*InsnID*/0,
10783        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10784        // GIR_Coverage, 352,
10785        GIR_Done,
10786      // Label 721: @25557
10787      GIM_Try, /*On fail goto*//*Label 722*/ 25601, // Rule ID 438 //
10788        GIM_CheckFeatures, GIFBS_HasDSPR2,
10789        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_absq_s_qb,
10790        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
10791        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
10792        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
10793        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
10794        // (intrinsic_w_chain:{ *:[v4i8] } 3636:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (ABSQ_S_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt)
10795        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ABSQ_S_QB,
10796        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
10797        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
10798        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
10799        GIR_EraseFromParent, /*InsnID*/0,
10800        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10801        // GIR_Coverage, 438,
10802        GIR_Done,
10803      // Label 722: @25601
10804      GIM_Try, /*On fail goto*//*Label 723*/ 25645, // Rule ID 1212 //
10805        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
10806        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_absq_s_ph,
10807        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
10808        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
10809        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
10810        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
10811        // (intrinsic_w_chain:{ *:[v2i16] } 3635:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs)  =>  (ABSQ_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs)
10812        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ABSQ_S_PH_MM,
10813        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
10814        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
10815        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
10816        GIR_EraseFromParent, /*InsnID*/0,
10817        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10818        // GIR_Coverage, 1212,
10819        GIR_Done,
10820      // Label 723: @25645
10821      GIM_Try, /*On fail goto*//*Label 724*/ 25689, // Rule ID 1213 //
10822        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
10823        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_absq_s_w,
10824        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
10825        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
10826        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
10827        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
10828        // (intrinsic_w_chain:{ *:[i32] } 3637:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs)  =>  (ABSQ_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
10829        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ABSQ_S_W_MM,
10830        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
10831        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
10832        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
10833        GIR_EraseFromParent, /*InsnID*/0,
10834        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10835        // GIR_Coverage, 1213,
10836        GIR_Done,
10837      // Label 724: @25689
10838      GIM_Try, /*On fail goto*//*Label 725*/ 25733, // Rule ID 1293 //
10839        GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
10840        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_absq_s_qb,
10841        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
10842        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
10843        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
10844        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
10845        // (intrinsic_w_chain:{ *:[v4i8] } 3636:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs)  =>  (ABSQ_S_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs)
10846        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ABSQ_S_QB_MMR2,
10847        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
10848        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
10849        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
10850        GIR_EraseFromParent, /*InsnID*/0,
10851        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10852        // GIR_Coverage, 1293,
10853        GIR_Done,
10854      // Label 725: @25733
10855      GIM_Try, /*On fail goto*//*Label 726*/ 25777, // Rule ID 405 //
10856        GIM_CheckFeatures, GIFBS_HasDSP,
10857        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmpu_eq_qb,
10858        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8,
10859        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
10860        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
10861        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
10862        // (intrinsic_void 3813:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPU_EQ_QB DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
10863        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPU_EQ_QB,
10864        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
10865        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
10866        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
10867        GIR_EraseFromParent, /*InsnID*/0,
10868        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10869        // GIR_Coverage, 405,
10870        GIR_Done,
10871      // Label 726: @25777
10872      GIM_Try, /*On fail goto*//*Label 727*/ 25821, // Rule ID 406 //
10873        GIM_CheckFeatures, GIFBS_HasDSP,
10874        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmpu_lt_qb,
10875        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8,
10876        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
10877        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
10878        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
10879        // (intrinsic_void 3815:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPU_LT_QB DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
10880        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPU_LT_QB,
10881        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
10882        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
10883        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
10884        GIR_EraseFromParent, /*InsnID*/0,
10885        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10886        // GIR_Coverage, 406,
10887        GIR_Done,
10888      // Label 727: @25821
10889      GIM_Try, /*On fail goto*//*Label 728*/ 25865, // Rule ID 407 //
10890        GIM_CheckFeatures, GIFBS_HasDSP,
10891        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmpu_le_qb,
10892        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8,
10893        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
10894        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
10895        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
10896        // (intrinsic_void 3814:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPU_LE_QB DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
10897        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPU_LE_QB,
10898        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
10899        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
10900        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
10901        GIR_EraseFromParent, /*InsnID*/0,
10902        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10903        // GIR_Coverage, 407,
10904        GIR_Done,
10905      // Label 728: @25865
10906      GIM_Try, /*On fail goto*//*Label 729*/ 25909, // Rule ID 411 //
10907        GIM_CheckFeatures, GIFBS_HasDSP,
10908        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmp_eq_ph,
10909        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
10910        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
10911        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
10912        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
10913        // (intrinsic_void 3804:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (CMP_EQ_PH DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
10914        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_EQ_PH,
10915        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
10916        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
10917        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
10918        GIR_EraseFromParent, /*InsnID*/0,
10919        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10920        // GIR_Coverage, 411,
10921        GIR_Done,
10922      // Label 729: @25909
10923      GIM_Try, /*On fail goto*//*Label 730*/ 25953, // Rule ID 412 //
10924        GIM_CheckFeatures, GIFBS_HasDSP,
10925        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmp_lt_ph,
10926        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
10927        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
10928        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
10929        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
10930        // (intrinsic_void 3806:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (CMP_LT_PH DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
10931        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LT_PH,
10932        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
10933        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
10934        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
10935        GIR_EraseFromParent, /*InsnID*/0,
10936        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10937        // GIR_Coverage, 412,
10938        GIR_Done,
10939      // Label 730: @25953
10940      GIM_Try, /*On fail goto*//*Label 731*/ 25997, // Rule ID 413 //
10941        GIM_CheckFeatures, GIFBS_HasDSP,
10942        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmp_le_ph,
10943        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
10944        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
10945        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
10946        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
10947        // (intrinsic_void 3805:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (CMP_LE_PH DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
10948        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LE_PH,
10949        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
10950        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
10951        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
10952        GIR_EraseFromParent, /*InsnID*/0,
10953        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10954        // GIR_Coverage, 413,
10955        GIR_Done,
10956      // Label 731: @25997
10957      GIM_Try, /*On fail goto*//*Label 732*/ 26041, // Rule ID 1284 //
10958        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
10959        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmp_eq_ph,
10960        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
10961        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
10962        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
10963        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
10964        // (intrinsic_void 3804:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (CMP_EQ_PH_MM DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
10965        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_EQ_PH_MM,
10966        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
10967        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
10968        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
10969        GIR_EraseFromParent, /*InsnID*/0,
10970        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10971        // GIR_Coverage, 1284,
10972        GIR_Done,
10973      // Label 732: @26041
10974      GIM_Try, /*On fail goto*//*Label 733*/ 26085, // Rule ID 1285 //
10975        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
10976        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmp_lt_ph,
10977        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
10978        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
10979        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
10980        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
10981        // (intrinsic_void 3806:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (CMP_LT_PH_MM DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
10982        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LT_PH_MM,
10983        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
10984        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
10985        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
10986        GIR_EraseFromParent, /*InsnID*/0,
10987        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10988        // GIR_Coverage, 1285,
10989        GIR_Done,
10990      // Label 733: @26085
10991      GIM_Try, /*On fail goto*//*Label 734*/ 26129, // Rule ID 1286 //
10992        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
10993        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmp_le_ph,
10994        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
10995        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
10996        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
10997        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
10998        // (intrinsic_void 3805:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (CMP_LE_PH_MM DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
10999        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LE_PH_MM,
11000        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
11001        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
11002        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11003        GIR_EraseFromParent, /*InsnID*/0,
11004        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11005        // GIR_Coverage, 1286,
11006        GIR_Done,
11007      // Label 734: @26129
11008      GIM_Try, /*On fail goto*//*Label 735*/ 26173, // Rule ID 1290 //
11009        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
11010        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmpu_eq_qb,
11011        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8,
11012        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
11013        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
11014        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11015        // (intrinsic_void 3813:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPU_EQ_QB_MM DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
11016        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPU_EQ_QB_MM,
11017        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
11018        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
11019        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11020        GIR_EraseFromParent, /*InsnID*/0,
11021        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11022        // GIR_Coverage, 1290,
11023        GIR_Done,
11024      // Label 735: @26173
11025      GIM_Try, /*On fail goto*//*Label 736*/ 26217, // Rule ID 1291 //
11026        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
11027        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmpu_lt_qb,
11028        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8,
11029        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
11030        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
11031        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11032        // (intrinsic_void 3815:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPU_LT_QB_MM DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
11033        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPU_LT_QB_MM,
11034        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
11035        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
11036        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11037        GIR_EraseFromParent, /*InsnID*/0,
11038        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11039        // GIR_Coverage, 1291,
11040        GIR_Done,
11041      // Label 736: @26217
11042      GIM_Try, /*On fail goto*//*Label 737*/ 26261, // Rule ID 1292 //
11043        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
11044        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmpu_le_qb,
11045        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8,
11046        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
11047        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
11048        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11049        // (intrinsic_void 3814:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPU_LE_QB_MM DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
11050        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPU_LE_QB_MM,
11051        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
11052        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
11053        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11054        GIR_EraseFromParent, /*InsnID*/0,
11055        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11056        // GIR_Coverage, 1292,
11057        GIR_Done,
11058      // Label 737: @26261
11059      GIM_Reject,
11060    // Label 715: @26262
11061    GIM_Try, /*On fail goto*//*Label 738*/ 30250,
11062      GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
11063      GIM_Try, /*On fail goto*//*Label 739*/ 26331, // Rule ID 370 //
11064        GIM_CheckFeatures, GIFBS_HasDSP,
11065        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_s_ph,
11066        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
11067        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
11068        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11069        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11070        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11071        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
11072        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
11073        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt4,
11074        // MIs[1] Operand 1
11075        // No operand predicates
11076        GIM_CheckIsSafeToFold, /*InsnID*/1,
11077        // (intrinsic_w_chain:{ *:[v2i16] } 4189:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$rs_sa)  =>  (SHLL_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, (imm:{ *:[i32] }):$rs_sa)
11078        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLL_S_PH,
11079        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11080        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
11081        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa
11082        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
11083        GIR_EraseFromParent, /*InsnID*/0,
11084        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11085        // GIR_Coverage, 370,
11086        GIR_Done,
11087      // Label 739: @26331
11088      GIM_Try, /*On fail goto*//*Label 740*/ 26395, // Rule ID 375 //
11089        GIM_CheckFeatures, GIFBS_HasDSP,
11090        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_s_w,
11091        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11092        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
11093        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11094        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
11095        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
11096        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
11097        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
11098        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
11099        // MIs[1] Operand 1
11100        // No operand predicates
11101        GIM_CheckIsSafeToFold, /*InsnID*/1,
11102        // (intrinsic_w_chain:{ *:[i32] } 4190:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$rs_sa)  =>  (SHLL_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$rs_sa)
11103        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLL_S_W,
11104        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11105        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
11106        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa
11107        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
11108        GIR_EraseFromParent, /*InsnID*/0,
11109        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11110        // GIR_Coverage, 375,
11111        GIR_Done,
11112      // Label 740: @26395
11113      GIM_Try, /*On fail goto*//*Label 741*/ 26459, // Rule ID 1221 //
11114        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
11115        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_s_ph,
11116        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
11117        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
11118        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11119        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11120        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11121        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
11122        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
11123        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt4,
11124        // MIs[1] Operand 1
11125        // No operand predicates
11126        GIM_CheckIsSafeToFold, /*InsnID*/1,
11127        // (intrinsic_w_chain:{ *:[v2i16] } 4189:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$sa)  =>  (SHLL_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, (imm:{ *:[i32] }):$sa)
11128        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLL_S_PH_MM,
11129        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
11130        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11131        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
11132        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
11133        GIR_EraseFromParent, /*InsnID*/0,
11134        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11135        // GIR_Coverage, 1221,
11136        GIR_Done,
11137      // Label 741: @26459
11138      GIM_Try, /*On fail goto*//*Label 742*/ 26523, // Rule ID 1226 //
11139        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
11140        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_s_w,
11141        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11142        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
11143        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11144        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
11145        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
11146        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
11147        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
11148        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
11149        // MIs[1] Operand 1
11150        // No operand predicates
11151        GIM_CheckIsSafeToFold, /*InsnID*/1,
11152        // (intrinsic_w_chain:{ *:[i32] } 4190:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$sa)  =>  (SHLL_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa)
11153        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLL_S_W_MM,
11154        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
11155        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11156        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
11157        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
11158        GIR_EraseFromParent, /*InsnID*/0,
11159        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11160        // GIR_Coverage, 1226,
11161        GIR_Done,
11162      // Label 742: @26523
11163      GIM_Try, /*On fail goto*//*Label 743*/ 26578, // Rule ID 1892 //
11164        GIM_CheckFeatures, GIFBS_HasDSP,
11165        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_ph,
11166        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
11167        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
11168        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11169        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11170        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
11171        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
11172        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt4,
11173        // MIs[1] Operand 1
11174        // No operand predicates
11175        GIM_CheckIsSafeToFold, /*InsnID*/1,
11176        // (intrinsic_w_chain:{ *:[v2i16] } 4187:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt)  =>  (SHLL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt)
11177        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLL_PH,
11178        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11179        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
11180        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
11181        GIR_EraseFromParent, /*InsnID*/0,
11182        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11183        // GIR_Coverage, 1892,
11184        GIR_Done,
11185      // Label 743: @26578
11186      GIM_Try, /*On fail goto*//*Label 744*/ 26633, // Rule ID 1898 //
11187        GIM_CheckFeatures, GIFBS_HasDSP,
11188        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_qb,
11189        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
11190        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
11191        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11192        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11193        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
11194        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
11195        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt3,
11196        // MIs[1] Operand 1
11197        // No operand predicates
11198        GIM_CheckIsSafeToFold, /*InsnID*/1,
11199        // (intrinsic_w_chain:{ *:[v4i8] } 4188:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt)  =>  (SHLL_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt)
11200        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLL_QB,
11201        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11202        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
11203        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
11204        GIR_EraseFromParent, /*InsnID*/0,
11205        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11206        // GIR_Coverage, 1898,
11207        GIR_Done,
11208      // Label 744: @26633
11209      GIM_Try, /*On fail goto*//*Label 745*/ 26689, // Rule ID 347 //
11210        GIM_CheckFeatures, GIFBS_HasDSP,
11211        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addq_s_w,
11212        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11213        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
11214        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11215        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
11216        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
11217        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
11218        // (intrinsic_w_chain:{ *:[i32] } 3644:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (ADDQ_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
11219        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQ_S_W,
11220        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11221        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11222        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11223        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11224        GIR_EraseFromParent, /*InsnID*/0,
11225        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11226        // GIR_Coverage, 347,
11227        GIR_Done,
11228      // Label 745: @26689
11229      GIM_Try, /*On fail goto*//*Label 746*/ 26745, // Rule ID 348 //
11230        GIM_CheckFeatures, GIFBS_HasDSP,
11231        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subq_s_w,
11232        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11233        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
11234        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11235        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
11236        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
11237        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
11238        // (intrinsic_w_chain:{ *:[i32] } 4260:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (SUBQ_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
11239        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQ_S_W,
11240        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11241        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11242        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11243        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11244        GIR_EraseFromParent, /*InsnID*/0,
11245        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11246        // GIR_Coverage, 348,
11247        GIR_Done,
11248      // Label 746: @26745
11249      GIM_Try, /*On fail goto*//*Label 747*/ 26801, // Rule ID 355 //
11250        GIM_CheckFeatures, GIFBS_HasDSP,
11251        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precrq_rs_ph_w,
11252        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
11253        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
11254        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11255        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11256        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
11257        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
11258        // (intrinsic_w_chain:{ *:[v2i16] } 4168:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (PRECRQ_RS_PH_W:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
11259        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECRQ_RS_PH_W,
11260        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11261        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11262        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11263        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11264        GIR_EraseFromParent, /*InsnID*/0,
11265        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11266        // GIR_Coverage, 355,
11267        GIR_Done,
11268      // Label 747: @26801
11269      GIM_Try, /*On fail goto*//*Label 748*/ 26857, // Rule ID 356 //
11270        GIM_CheckFeatures, GIFBS_HasDSP,
11271        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precrqu_s_qb_ph,
11272        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
11273        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
11274        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
11275        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11276        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11277        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11278        // (intrinsic_w_chain:{ *:[v4i8] } 4169:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (PRECRQU_S_QB_PH:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11279        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECRQU_S_QB_PH,
11280        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11281        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11282        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11283        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11284        GIR_EraseFromParent, /*InsnID*/0,
11285        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11286        // GIR_Coverage, 356,
11287        GIR_Done,
11288      // Label 748: @26857
11289      GIM_Try, /*On fail goto*//*Label 749*/ 26913, // Rule ID 367 //
11290        GIM_CheckFeatures, GIFBS_HasDSP,
11291        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_qb,
11292        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
11293        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
11294        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11295        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11296        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11297        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
11298        // (intrinsic_w_chain:{ *:[v4i8] } 4188:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)  =>  (SHLLV_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
11299        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLLV_QB,
11300        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11301        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
11302        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa
11303        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11304        GIR_EraseFromParent, /*InsnID*/0,
11305        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11306        // GIR_Coverage, 367,
11307        GIR_Done,
11308      // Label 749: @26913
11309      GIM_Try, /*On fail goto*//*Label 750*/ 26969, // Rule ID 369 //
11310        GIM_CheckFeatures, GIFBS_HasDSP,
11311        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_ph,
11312        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
11313        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
11314        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11315        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11316        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11317        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
11318        // (intrinsic_w_chain:{ *:[v2i16] } 4187:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)  =>  (SHLLV_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
11319        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLLV_PH,
11320        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11321        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
11322        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa
11323        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11324        GIR_EraseFromParent, /*InsnID*/0,
11325        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11326        // GIR_Coverage, 369,
11327        GIR_Done,
11328      // Label 750: @26969
11329      GIM_Try, /*On fail goto*//*Label 751*/ 27025, // Rule ID 371 //
11330        GIM_CheckFeatures, GIFBS_HasDSP,
11331        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_s_ph,
11332        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
11333        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
11334        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11335        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11336        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11337        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
11338        // (intrinsic_w_chain:{ *:[v2i16] } 4189:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)  =>  (SHLLV_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
11339        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLLV_S_PH,
11340        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11341        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
11342        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa
11343        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11344        GIR_EraseFromParent, /*InsnID*/0,
11345        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11346        // GIR_Coverage, 371,
11347        GIR_Done,
11348      // Label 751: @27025
11349      GIM_Try, /*On fail goto*//*Label 752*/ 27081, // Rule ID 376 //
11350        GIM_CheckFeatures, GIFBS_HasDSP,
11351        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_s_w,
11352        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11353        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
11354        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11355        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
11356        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
11357        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
11358        // (intrinsic_w_chain:{ *:[i32] } 4190:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)  =>  (SHLLV_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
11359        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLLV_S_W,
11360        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11361        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
11362        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa
11363        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11364        GIR_EraseFromParent, /*InsnID*/0,
11365        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11366        // GIR_Coverage, 376,
11367        GIR_Done,
11368      // Label 752: @27081
11369      GIM_Try, /*On fail goto*//*Label 753*/ 27137, // Rule ID 379 //
11370        GIM_CheckFeatures, GIFBS_HasDSP,
11371        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_muleu_s_ph_qbl,
11372        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
11373        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
11374        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
11375        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11376        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11377        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11378        // (intrinsic_w_chain:{ *:[v2i16] } 4110:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (MULEU_S_PH_QBL:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11379        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULEU_S_PH_QBL,
11380        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11381        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11382        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11383        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11384        GIR_EraseFromParent, /*InsnID*/0,
11385        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11386        // GIR_Coverage, 379,
11387        GIR_Done,
11388      // Label 753: @27137
11389      GIM_Try, /*On fail goto*//*Label 754*/ 27193, // Rule ID 380 //
11390        GIM_CheckFeatures, GIFBS_HasDSP,
11391        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_muleu_s_ph_qbr,
11392        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
11393        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
11394        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
11395        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11396        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11397        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11398        // (intrinsic_w_chain:{ *:[v2i16] } 4111:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (MULEU_S_PH_QBR:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11399        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULEU_S_PH_QBR,
11400        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11401        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11402        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11403        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11404        GIR_EraseFromParent, /*InsnID*/0,
11405        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11406        // GIR_Coverage, 380,
11407        GIR_Done,
11408      // Label 754: @27193
11409      GIM_Try, /*On fail goto*//*Label 755*/ 27249, // Rule ID 381 //
11410        GIM_CheckFeatures, GIFBS_HasDSP,
11411        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_muleq_s_w_phl,
11412        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11413        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
11414        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
11415        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
11416        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11417        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11418        // (intrinsic_w_chain:{ *:[i32] } 4108:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (MULEQ_S_W_PHL:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11419        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULEQ_S_W_PHL,
11420        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11421        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11422        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11423        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11424        GIR_EraseFromParent, /*InsnID*/0,
11425        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11426        // GIR_Coverage, 381,
11427        GIR_Done,
11428      // Label 755: @27249
11429      GIM_Try, /*On fail goto*//*Label 756*/ 27305, // Rule ID 382 //
11430        GIM_CheckFeatures, GIFBS_HasDSP,
11431        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_muleq_s_w_phr,
11432        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11433        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
11434        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
11435        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
11436        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11437        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11438        // (intrinsic_w_chain:{ *:[i32] } 4109:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (MULEQ_S_W_PHR:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11439        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULEQ_S_W_PHR,
11440        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11441        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11442        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11443        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11444        GIR_EraseFromParent, /*InsnID*/0,
11445        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11446        // GIR_Coverage, 382,
11447        GIR_Done,
11448      // Label 756: @27305
11449      GIM_Try, /*On fail goto*//*Label 757*/ 27361, // Rule ID 383 //
11450        GIM_CheckFeatures, GIFBS_HasDSP,
11451        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulq_rs_ph,
11452        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
11453        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
11454        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
11455        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11456        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11457        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11458        // (intrinsic_w_chain:{ *:[v2i16] } 4112:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (MULQ_RS_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11459        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULQ_RS_PH,
11460        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11461        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11462        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11463        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11464        GIR_EraseFromParent, /*InsnID*/0,
11465        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11466        // GIR_Coverage, 383,
11467        GIR_Done,
11468      // Label 757: @27361
11469      GIM_Try, /*On fail goto*//*Label 758*/ 27417, // Rule ID 408 //
11470        GIM_CheckFeatures, GIFBS_HasDSP,
11471        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgu_eq_qb,
11472        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11473        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
11474        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
11475        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
11476        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11477        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11478        // (intrinsic_w_chain:{ *:[i32] } 3810:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPGU_EQ_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
11479        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGU_EQ_QB,
11480        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11481        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11482        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11483        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11484        GIR_EraseFromParent, /*InsnID*/0,
11485        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11486        // GIR_Coverage, 408,
11487        GIR_Done,
11488      // Label 758: @27417
11489      GIM_Try, /*On fail goto*//*Label 759*/ 27473, // Rule ID 409 //
11490        GIM_CheckFeatures, GIFBS_HasDSP,
11491        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgu_lt_qb,
11492        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11493        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
11494        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
11495        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
11496        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11497        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11498        // (intrinsic_w_chain:{ *:[i32] } 3812:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPGU_LT_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
11499        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGU_LT_QB,
11500        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11501        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11502        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11503        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11504        GIR_EraseFromParent, /*InsnID*/0,
11505        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11506        // GIR_Coverage, 409,
11507        GIR_Done,
11508      // Label 759: @27473
11509      GIM_Try, /*On fail goto*//*Label 760*/ 27529, // Rule ID 410 //
11510        GIM_CheckFeatures, GIFBS_HasDSP,
11511        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgu_le_qb,
11512        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11513        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
11514        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
11515        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
11516        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11517        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11518        // (intrinsic_w_chain:{ *:[i32] } 3811:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPGU_LE_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
11519        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGU_LE_QB,
11520        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11521        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11522        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11523        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11524        GIR_EraseFromParent, /*InsnID*/0,
11525        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11526        // GIR_Coverage, 410,
11527        GIR_Done,
11528      // Label 760: @27529
11529      GIM_Try, /*On fail goto*//*Label 761*/ 27585, // Rule ID 420 //
11530        GIM_CheckFeatures, GIFBS_HasDSP,
11531        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_pick_qb,
11532        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
11533        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
11534        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
11535        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11536        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11537        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11538        // (intrinsic_w_chain:{ *:[v4i8] } 4152:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PICK_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
11539        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PICK_QB,
11540        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11541        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11542        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11543        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11544        GIR_EraseFromParent, /*InsnID*/0,
11545        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11546        // GIR_Coverage, 420,
11547        GIR_Done,
11548      // Label 761: @27585
11549      GIM_Try, /*On fail goto*//*Label 762*/ 27641, // Rule ID 421 //
11550        GIM_CheckFeatures, GIFBS_HasDSP,
11551        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_pick_ph,
11552        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
11553        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
11554        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
11555        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11556        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11557        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11558        // (intrinsic_w_chain:{ *:[v2i16] } 4151:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (PICK_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11559        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PICK_PH,
11560        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11561        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11562        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11563        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11564        GIR_EraseFromParent, /*InsnID*/0,
11565        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11566        // GIR_Coverage, 421,
11567        GIR_Done,
11568      // Label 762: @27641
11569      GIM_Try, /*On fail goto*//*Label 763*/ 27697, // Rule ID 425 //
11570        GIM_CheckFeatures, GIFBS_HasDSP,
11571        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_insv,
11572        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11573        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
11574        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11575        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
11576        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
11577        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
11578        // (intrinsic_w_chain:{ *:[i32] } 4012:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs)  =>  (INSV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs)
11579        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::INSV,
11580        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
11581        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
11582        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
11583        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11584        GIR_EraseFromParent, /*InsnID*/0,
11585        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11586        // GIR_Coverage, 425,
11587        GIR_Done,
11588      // Label 763: @27697
11589      GIM_Try, /*On fail goto*//*Label 764*/ 27753, // Rule ID 431 //
11590        GIM_CheckFeatures, GIFBS_HasDSPR2,
11591        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addu_ph,
11592        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
11593        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
11594        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
11595        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11596        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11597        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11598        // (intrinsic_w_chain:{ *:[v2i16] } 3662:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (ADDU_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11599        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDU_PH,
11600        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11601        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11602        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11603        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11604        GIR_EraseFromParent, /*InsnID*/0,
11605        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11606        // GIR_Coverage, 431,
11607        GIR_Done,
11608      // Label 764: @27753
11609      GIM_Try, /*On fail goto*//*Label 765*/ 27809, // Rule ID 432 //
11610        GIM_CheckFeatures, GIFBS_HasDSPR2,
11611        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addu_s_ph,
11612        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
11613        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
11614        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
11615        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11616        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11617        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11618        // (intrinsic_w_chain:{ *:[v2i16] } 3664:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (ADDU_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11619        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDU_S_PH,
11620        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11621        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11622        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11623        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11624        GIR_EraseFromParent, /*InsnID*/0,
11625        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11626        // GIR_Coverage, 432,
11627        GIR_Done,
11628      // Label 765: @27809
11629      GIM_Try, /*On fail goto*//*Label 766*/ 27865, // Rule ID 433 //
11630        GIM_CheckFeatures, GIFBS_HasDSPR2,
11631        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subu_ph,
11632        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
11633        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
11634        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
11635        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11636        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11637        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11638        // (intrinsic_w_chain:{ *:[v2i16] } 4281:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (SUBU_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11639        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBU_PH,
11640        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11641        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11642        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11643        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11644        GIR_EraseFromParent, /*InsnID*/0,
11645        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11646        // GIR_Coverage, 433,
11647        GIR_Done,
11648      // Label 766: @27865
11649      GIM_Try, /*On fail goto*//*Label 767*/ 27921, // Rule ID 434 //
11650        GIM_CheckFeatures, GIFBS_HasDSPR2,
11651        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subu_s_ph,
11652        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
11653        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
11654        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
11655        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11656        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11657        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11658        // (intrinsic_w_chain:{ *:[v2i16] } 4283:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (SUBU_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11659        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBU_S_PH,
11660        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11661        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11662        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11663        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11664        GIR_EraseFromParent, /*InsnID*/0,
11665        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11666        // GIR_Coverage, 434,
11667        GIR_Done,
11668      // Label 767: @27921
11669      GIM_Try, /*On fail goto*//*Label 768*/ 27977, // Rule ID 435 //
11670        GIM_CheckFeatures, GIFBS_HasDSPR2,
11671        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgdu_eq_qb,
11672        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11673        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
11674        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
11675        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
11676        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11677        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11678        // (intrinsic_w_chain:{ *:[i32] } 3807:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPGDU_EQ_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
11679        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGDU_EQ_QB,
11680        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11681        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11682        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11683        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11684        GIR_EraseFromParent, /*InsnID*/0,
11685        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11686        // GIR_Coverage, 435,
11687        GIR_Done,
11688      // Label 768: @27977
11689      GIM_Try, /*On fail goto*//*Label 769*/ 28033, // Rule ID 436 //
11690        GIM_CheckFeatures, GIFBS_HasDSPR2,
11691        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgdu_lt_qb,
11692        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11693        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
11694        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
11695        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
11696        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11697        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11698        // (intrinsic_w_chain:{ *:[i32] } 3809:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPGDU_LT_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
11699        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGDU_LT_QB,
11700        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11701        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11702        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11703        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11704        GIR_EraseFromParent, /*InsnID*/0,
11705        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11706        // GIR_Coverage, 436,
11707        GIR_Done,
11708      // Label 769: @28033
11709      GIM_Try, /*On fail goto*//*Label 770*/ 28089, // Rule ID 437 //
11710        GIM_CheckFeatures, GIFBS_HasDSPR2,
11711        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgdu_le_qb,
11712        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11713        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
11714        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
11715        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
11716        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11717        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11718        // (intrinsic_w_chain:{ *:[i32] } 3808:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPGDU_LE_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
11719        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGDU_LE_QB,
11720        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11721        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11722        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11723        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11724        GIR_EraseFromParent, /*InsnID*/0,
11725        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11726        // GIR_Coverage, 437,
11727        GIR_Done,
11728      // Label 770: @28089
11729      GIM_Try, /*On fail goto*//*Label 771*/ 28145, // Rule ID 451 //
11730        GIM_CheckFeatures, GIFBS_HasDSPR2,
11731        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mul_s_ph,
11732        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
11733        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
11734        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
11735        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11736        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11737        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11738        // (intrinsic_w_chain:{ *:[v2i16] } 4107:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (MUL_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11739        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MUL_S_PH,
11740        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11741        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11742        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11743        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11744        GIR_EraseFromParent, /*InsnID*/0,
11745        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11746        // GIR_Coverage, 451,
11747        GIR_Done,
11748      // Label 771: @28145
11749      GIM_Try, /*On fail goto*//*Label 772*/ 28201, // Rule ID 452 //
11750        GIM_CheckFeatures, GIFBS_HasDSPR2,
11751        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulq_s_w,
11752        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11753        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
11754        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11755        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
11756        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
11757        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
11758        // (intrinsic_w_chain:{ *:[i32] } 4115:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MULQ_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
11759        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULQ_S_W,
11760        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11761        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11762        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11763        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11764        GIR_EraseFromParent, /*InsnID*/0,
11765        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11766        // GIR_Coverage, 452,
11767        GIR_Done,
11768      // Label 772: @28201
11769      GIM_Try, /*On fail goto*//*Label 773*/ 28257, // Rule ID 453 //
11770        GIM_CheckFeatures, GIFBS_HasDSPR2,
11771        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulq_rs_w,
11772        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11773        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
11774        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11775        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
11776        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
11777        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
11778        // (intrinsic_w_chain:{ *:[i32] } 4113:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MULQ_RS_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
11779        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULQ_RS_W,
11780        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11781        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11782        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11783        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11784        GIR_EraseFromParent, /*InsnID*/0,
11785        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11786        // GIR_Coverage, 453,
11787        GIR_Done,
11788      // Label 773: @28257
11789      GIM_Try, /*On fail goto*//*Label 774*/ 28313, // Rule ID 454 //
11790        GIM_CheckFeatures, GIFBS_HasDSPR2,
11791        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulq_s_ph,
11792        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
11793        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
11794        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
11795        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11796        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11797        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11798        // (intrinsic_w_chain:{ *:[v2i16] } 4114:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (MULQ_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11799        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULQ_S_PH,
11800        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11801        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11802        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11803        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11804        GIR_EraseFromParent, /*InsnID*/0,
11805        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11806        // GIR_Coverage, 454,
11807        GIR_Done,
11808      // Label 774: @28313
11809      GIM_Try, /*On fail goto*//*Label 775*/ 28369, // Rule ID 464 //
11810        GIM_CheckFeatures, GIFBS_HasDSPR2,
11811        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precr_qb_ph,
11812        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
11813        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
11814        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
11815        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11816        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11817        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11818        // (intrinsic_w_chain:{ *:[v4i8] } 4163:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (PRECR_QB_PH:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11819        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECR_QB_PH,
11820        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11821        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11822        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11823        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11824        GIR_EraseFromParent, /*InsnID*/0,
11825        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11826        // GIR_Coverage, 464,
11827        GIR_Done,
11828      // Label 775: @28369
11829      GIM_Try, /*On fail goto*//*Label 776*/ 28425, // Rule ID 1206 //
11830        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
11831        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addq_s_w,
11832        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11833        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
11834        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11835        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
11836        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
11837        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
11838        // (intrinsic_w_chain:{ *:[i32] } 3644:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (ADDQ_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
11839        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQ_S_W_MM,
11840        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11841        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11842        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11843        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11844        GIR_EraseFromParent, /*InsnID*/0,
11845        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11846        // GIR_Coverage, 1206,
11847        GIR_Done,
11848      // Label 776: @28425
11849      GIM_Try, /*On fail goto*//*Label 777*/ 28481, // Rule ID 1214 //
11850        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
11851        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_insv,
11852        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11853        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
11854        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11855        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
11856        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
11857        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
11858        // (intrinsic_w_chain:{ *:[i32] } 4012:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs)  =>  (INSV_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs)
11859        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::INSV_MM,
11860        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
11861        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
11862        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
11863        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11864        GIR_EraseFromParent, /*InsnID*/0,
11865        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11866        // GIR_Coverage, 1214,
11867        GIR_Done,
11868      // Label 777: @28481
11869      GIM_Try, /*On fail goto*//*Label 778*/ 28537, // Rule ID 1222 //
11870        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
11871        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_ph,
11872        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
11873        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
11874        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11875        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11876        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11877        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
11878        // (intrinsic_w_chain:{ *:[v2i16] } 4187:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)  =>  (SHLLV_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
11879        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLLV_PH_MM,
11880        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11881        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
11882        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
11883        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11884        GIR_EraseFromParent, /*InsnID*/0,
11885        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11886        // GIR_Coverage, 1222,
11887        GIR_Done,
11888      // Label 778: @28537
11889      GIM_Try, /*On fail goto*//*Label 779*/ 28593, // Rule ID 1223 //
11890        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
11891        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_s_ph,
11892        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
11893        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
11894        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11895        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11896        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11897        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
11898        // (intrinsic_w_chain:{ *:[v2i16] } 4189:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)  =>  (SHLLV_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
11899        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLLV_S_PH_MM,
11900        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11901        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
11902        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
11903        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11904        GIR_EraseFromParent, /*InsnID*/0,
11905        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11906        // GIR_Coverage, 1223,
11907        GIR_Done,
11908      // Label 779: @28593
11909      GIM_Try, /*On fail goto*//*Label 780*/ 28649, // Rule ID 1224 //
11910        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
11911        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_qb,
11912        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
11913        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
11914        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11915        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11916        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11917        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
11918        // (intrinsic_w_chain:{ *:[v4i8] } 4188:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)  =>  (SHLLV_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
11919        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLLV_QB_MM,
11920        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11921        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
11922        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
11923        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11924        GIR_EraseFromParent, /*InsnID*/0,
11925        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11926        // GIR_Coverage, 1224,
11927        GIR_Done,
11928      // Label 780: @28649
11929      GIM_Try, /*On fail goto*//*Label 781*/ 28705, // Rule ID 1225 //
11930        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
11931        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_s_w,
11932        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11933        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
11934        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11935        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
11936        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
11937        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
11938        // (intrinsic_w_chain:{ *:[i32] } 4190:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)  =>  (SHLLV_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
11939        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLLV_S_W_MM,
11940        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11941        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
11942        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
11943        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11944        GIR_EraseFromParent, /*InsnID*/0,
11945        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11946        // GIR_Coverage, 1225,
11947        GIR_Done,
11948      // Label 781: @28705
11949      GIM_Try, /*On fail goto*//*Label 782*/ 28761, // Rule ID 1244 //
11950        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
11951        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subq_s_w,
11952        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11953        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
11954        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11955        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
11956        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
11957        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
11958        // (intrinsic_w_chain:{ *:[i32] } 4260:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (SUBQ_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
11959        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQ_S_W_MM,
11960        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11961        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11962        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11963        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11964        GIR_EraseFromParent, /*InsnID*/0,
11965        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11966        // GIR_Coverage, 1244,
11967        GIR_Done,
11968      // Label 782: @28761
11969      GIM_Try, /*On fail goto*//*Label 783*/ 28817, // Rule ID 1250 //
11970        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
11971        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_muleq_s_w_phl,
11972        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11973        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
11974        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
11975        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
11976        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11977        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11978        // (intrinsic_w_chain:{ *:[i32] } 4108:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (MULEQ_S_W_PHL_MM:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11979        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULEQ_S_W_PHL_MM,
11980        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11981        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11982        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11983        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11984        GIR_EraseFromParent, /*InsnID*/0,
11985        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11986        // GIR_Coverage, 1250,
11987        GIR_Done,
11988      // Label 783: @28817
11989      GIM_Try, /*On fail goto*//*Label 784*/ 28873, // Rule ID 1251 //
11990        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
11991        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_muleq_s_w_phr,
11992        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11993        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
11994        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
11995        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
11996        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11997        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11998        // (intrinsic_w_chain:{ *:[i32] } 4109:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (MULEQ_S_W_PHR_MM:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11999        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULEQ_S_W_PHR_MM,
12000        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12001        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
12002        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
12003        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
12004        GIR_EraseFromParent, /*InsnID*/0,
12005        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12006        // GIR_Coverage, 1251,
12007        GIR_Done,
12008      // Label 784: @28873
12009      GIM_Try, /*On fail goto*//*Label 785*/ 28929, // Rule ID 1252 //
12010        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
12011        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_muleu_s_ph_qbl,
12012        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
12013        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
12014        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
12015        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
12016        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
12017        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
12018        // (intrinsic_w_chain:{ *:[v2i16] } 4110:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (MULEU_S_PH_QBL_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12019        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULEU_S_PH_QBL_MM,
12020        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12021        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
12022        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
12023        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
12024        GIR_EraseFromParent, /*InsnID*/0,
12025        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12026        // GIR_Coverage, 1252,
12027        GIR_Done,
12028      // Label 785: @28929
12029      GIM_Try, /*On fail goto*//*Label 786*/ 28985, // Rule ID 1253 //
12030        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
12031        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_muleu_s_ph_qbr,
12032        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
12033        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
12034        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
12035        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
12036        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
12037        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
12038        // (intrinsic_w_chain:{ *:[v2i16] } 4111:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (MULEU_S_PH_QBR_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12039        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULEU_S_PH_QBR_MM,
12040        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12041        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
12042        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
12043        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
12044        GIR_EraseFromParent, /*InsnID*/0,
12045        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12046        // GIR_Coverage, 1253,
12047        GIR_Done,
12048      // Label 786: @28985
12049      GIM_Try, /*On fail goto*//*Label 787*/ 29041, // Rule ID 1254 //
12050        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
12051        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulq_rs_ph,
12052        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
12053        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
12054        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
12055        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
12056        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
12057        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
12058        // (intrinsic_w_chain:{ *:[v2i16] } 4112:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (MULQ_RS_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12059        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULQ_RS_PH_MM,
12060        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12061        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
12062        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
12063        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
12064        GIR_EraseFromParent, /*InsnID*/0,
12065        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12066        // GIR_Coverage, 1254,
12067        GIR_Done,
12068      // Label 787: @29041
12069      GIM_Try, /*On fail goto*//*Label 788*/ 29097, // Rule ID 1257 //
12070        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
12071        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precrqu_s_qb_ph,
12072        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
12073        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
12074        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
12075        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
12076        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
12077        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
12078        // (intrinsic_w_chain:{ *:[v4i8] } 4169:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (PRECRQU_S_QB_PH_MM:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12079        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECRQU_S_QB_PH_MM,
12080        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12081        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
12082        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
12083        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
12084        GIR_EraseFromParent, /*InsnID*/0,
12085        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12086        // GIR_Coverage, 1257,
12087        GIR_Done,
12088      // Label 788: @29097
12089      GIM_Try, /*On fail goto*//*Label 789*/ 29153, // Rule ID 1258 //
12090        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
12091        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precrq_rs_ph_w,
12092        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
12093        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12094        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
12095        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
12096        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
12097        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
12098        // (intrinsic_w_chain:{ *:[v2i16] } 4168:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (PRECRQ_RS_PH_W_MM:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
12099        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECRQ_RS_PH_W_MM,
12100        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12101        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
12102        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
12103        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
12104        GIR_EraseFromParent, /*InsnID*/0,
12105        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12106        // GIR_Coverage, 1258,
12107        GIR_Done,
12108      // Label 789: @29153
12109      GIM_Try, /*On fail goto*//*Label 790*/ 29209, // Rule ID 1276 //
12110        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
12111        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_pick_ph,
12112        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
12113        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
12114        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
12115        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
12116        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
12117        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
12118        // (intrinsic_w_chain:{ *:[v2i16] } 4151:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (PICK_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12119        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PICK_PH_MM,
12120        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12121        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
12122        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
12123        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
12124        GIR_EraseFromParent, /*InsnID*/0,
12125        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12126        // GIR_Coverage, 1276,
12127        GIR_Done,
12128      // Label 790: @29209
12129      GIM_Try, /*On fail goto*//*Label 791*/ 29265, // Rule ID 1277 //
12130        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
12131        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_pick_qb,
12132        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
12133        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
12134        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
12135        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
12136        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
12137        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
12138        // (intrinsic_w_chain:{ *:[v4i8] } 4152:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PICK_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
12139        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PICK_QB_MM,
12140        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12141        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
12142        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
12143        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
12144        GIR_EraseFromParent, /*InsnID*/0,
12145        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12146        // GIR_Coverage, 1277,
12147        GIR_Done,
12148      // Label 791: @29265
12149      GIM_Try, /*On fail goto*//*Label 792*/ 29321, // Rule ID 1287 //
12150        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
12151        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgu_eq_qb,
12152        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12153        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
12154        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
12155        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
12156        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
12157        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
12158        // (intrinsic_w_chain:{ *:[i32] } 3810:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPGU_EQ_QB_MM:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
12159        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGU_EQ_QB_MM,
12160        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12161        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
12162        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
12163        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
12164        GIR_EraseFromParent, /*InsnID*/0,
12165        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12166        // GIR_Coverage, 1287,
12167        GIR_Done,
12168      // Label 792: @29321
12169      GIM_Try, /*On fail goto*//*Label 793*/ 29377, // Rule ID 1288 //
12170        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
12171        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgu_lt_qb,
12172        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12173        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
12174        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
12175        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
12176        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
12177        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
12178        // (intrinsic_w_chain:{ *:[i32] } 3812:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPGU_LT_QB_MM:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
12179        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGU_LT_QB_MM,
12180        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12181        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
12182        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
12183        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
12184        GIR_EraseFromParent, /*InsnID*/0,
12185        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12186        // GIR_Coverage, 1288,
12187        GIR_Done,
12188      // Label 793: @29377
12189      GIM_Try, /*On fail goto*//*Label 794*/ 29433, // Rule ID 1289 //
12190        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
12191        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgu_le_qb,
12192        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12193        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
12194        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
12195        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
12196        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
12197        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
12198        // (intrinsic_w_chain:{ *:[i32] } 3811:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPGU_LE_QB_MM:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
12199        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGU_LE_QB_MM,
12200        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12201        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
12202        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
12203        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
12204        GIR_EraseFromParent, /*InsnID*/0,
12205        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12206        // GIR_Coverage, 1289,
12207        GIR_Done,
12208      // Label 794: @29433
12209      GIM_Try, /*On fail goto*//*Label 795*/ 29489, // Rule ID 1298 //
12210        GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
12211        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addu_ph,
12212        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
12213        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
12214        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
12215        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
12216        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
12217        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
12218        // (intrinsic_w_chain:{ *:[v2i16] } 3662:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (ADDU_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12219        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDU_PH_MMR2,
12220        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12221        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
12222        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
12223        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
12224        GIR_EraseFromParent, /*InsnID*/0,
12225        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12226        // GIR_Coverage, 1298,
12227        GIR_Done,
12228      // Label 795: @29489
12229      GIM_Try, /*On fail goto*//*Label 796*/ 29545, // Rule ID 1299 //
12230        GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
12231        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addu_s_ph,
12232        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
12233        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
12234        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
12235        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
12236        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
12237        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
12238        // (intrinsic_w_chain:{ *:[v2i16] } 3664:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (ADDU_S_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12239        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDU_S_PH_MMR2,
12240        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12241        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
12242        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
12243        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
12244        GIR_EraseFromParent, /*InsnID*/0,
12245        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12246        // GIR_Coverage, 1299,
12247        GIR_Done,
12248      // Label 796: @29545
12249      GIM_Try, /*On fail goto*//*Label 797*/ 29601, // Rule ID 1310 //
12250        GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
12251        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgdu_eq_qb,
12252        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12253        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
12254        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
12255        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
12256        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
12257        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
12258        // (intrinsic_w_chain:{ *:[i32] } 3807:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPGDU_EQ_QB_MMR2:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
12259        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGDU_EQ_QB_MMR2,
12260        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12261        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
12262        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
12263        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
12264        GIR_EraseFromParent, /*InsnID*/0,
12265        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12266        // GIR_Coverage, 1310,
12267        GIR_Done,
12268      // Label 797: @29601
12269      GIM_Try, /*On fail goto*//*Label 798*/ 29657, // Rule ID 1311 //
12270        GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
12271        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgdu_lt_qb,
12272        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12273        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
12274        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
12275        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
12276        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
12277        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
12278        // (intrinsic_w_chain:{ *:[i32] } 3809:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPGDU_LT_QB_MMR2:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
12279        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGDU_LT_QB_MMR2,
12280        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12281        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
12282        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
12283        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
12284        GIR_EraseFromParent, /*InsnID*/0,
12285        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12286        // GIR_Coverage, 1311,
12287        GIR_Done,
12288      // Label 798: @29657
12289      GIM_Try, /*On fail goto*//*Label 799*/ 29713, // Rule ID 1312 //
12290        GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
12291        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgdu_le_qb,
12292        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12293        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
12294        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
12295        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
12296        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
12297        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
12298        // (intrinsic_w_chain:{ *:[i32] } 3808:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPGDU_LE_QB_MMR2:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
12299        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGDU_LE_QB_MMR2,
12300        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12301        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
12302        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
12303        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
12304        GIR_EraseFromParent, /*InsnID*/0,
12305        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12306        // GIR_Coverage, 1312,
12307        GIR_Done,
12308      // Label 799: @29713
12309      GIM_Try, /*On fail goto*//*Label 800*/ 29769, // Rule ID 1318 //
12310        GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
12311        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subu_ph,
12312        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
12313        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
12314        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
12315        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
12316        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
12317        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
12318        // (intrinsic_w_chain:{ *:[v2i16] } 4281:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (SUBU_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12319        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBU_PH_MMR2,
12320        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12321        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
12322        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
12323        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
12324        GIR_EraseFromParent, /*InsnID*/0,
12325        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12326        // GIR_Coverage, 1318,
12327        GIR_Done,
12328      // Label 800: @29769
12329      GIM_Try, /*On fail goto*//*Label 801*/ 29825, // Rule ID 1319 //
12330        GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
12331        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subu_s_ph,
12332        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
12333        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
12334        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
12335        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
12336        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
12337        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
12338        // (intrinsic_w_chain:{ *:[v2i16] } 4283:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (SUBU_S_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12339        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBU_S_PH_MMR2,
12340        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12341        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
12342        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
12343        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
12344        GIR_EraseFromParent, /*InsnID*/0,
12345        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12346        // GIR_Coverage, 1319,
12347        GIR_Done,
12348      // Label 801: @29825
12349      GIM_Try, /*On fail goto*//*Label 802*/ 29881, // Rule ID 1326 //
12350        GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
12351        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mul_s_ph,
12352        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
12353        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
12354        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
12355        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
12356        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
12357        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
12358        // (intrinsic_w_chain:{ *:[v2i16] } 4107:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (MUL_S_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12359        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MUL_S_PH_MMR2,
12360        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12361        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
12362        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
12363        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
12364        GIR_EraseFromParent, /*InsnID*/0,
12365        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12366        // GIR_Coverage, 1326,
12367        GIR_Done,
12368      // Label 802: @29881
12369      GIM_Try, /*On fail goto*//*Label 803*/ 29937, // Rule ID 1327 //
12370        GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
12371        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulq_rs_w,
12372        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12373        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12374        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
12375        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
12376        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
12377        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
12378        // (intrinsic_w_chain:{ *:[i32] } 4113:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MULQ_RS_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
12379        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULQ_RS_W_MMR2,
12380        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12381        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
12382        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
12383        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
12384        GIR_EraseFromParent, /*InsnID*/0,
12385        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12386        // GIR_Coverage, 1327,
12387        GIR_Done,
12388      // Label 803: @29937
12389      GIM_Try, /*On fail goto*//*Label 804*/ 29993, // Rule ID 1328 //
12390        GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
12391        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulq_s_ph,
12392        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
12393        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
12394        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
12395        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
12396        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
12397        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
12398        // (intrinsic_w_chain:{ *:[v2i16] } 4114:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (MULQ_S_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12399        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULQ_S_PH_MMR2,
12400        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12401        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
12402        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
12403        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
12404        GIR_EraseFromParent, /*InsnID*/0,
12405        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12406        // GIR_Coverage, 1328,
12407        GIR_Done,
12408      // Label 804: @29993
12409      GIM_Try, /*On fail goto*//*Label 805*/ 30049, // Rule ID 1329 //
12410        GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
12411        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulq_s_w,
12412        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12413        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12414        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
12415        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
12416        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
12417        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
12418        // (intrinsic_w_chain:{ *:[i32] } 4115:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MULQ_S_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
12419        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULQ_S_W_MMR2,
12420        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12421        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
12422        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
12423        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
12424        GIR_EraseFromParent, /*InsnID*/0,
12425        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12426        // GIR_Coverage, 1329,
12427        GIR_Done,
12428      // Label 805: @30049
12429      GIM_Try, /*On fail goto*//*Label 806*/ 30105, // Rule ID 1330 //
12430        GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
12431        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precr_qb_ph,
12432        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
12433        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
12434        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
12435        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
12436        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
12437        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
12438        // (intrinsic_w_chain:{ *:[v4i8] } 4163:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (PRECR_QB_PH_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12439        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECR_QB_PH_MMR2,
12440        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12441        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
12442        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
12443        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
12444        GIR_EraseFromParent, /*InsnID*/0,
12445        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12446        // GIR_Coverage, 1330,
12447        GIR_Done,
12448      // Label 806: @30105
12449      GIM_Try, /*On fail goto*//*Label 807*/ 30153, // Rule ID 1879 //
12450        GIM_CheckFeatures, GIFBS_HasDSPR2,
12451        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mul_ph,
12452        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
12453        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
12454        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
12455        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
12456        // (intrinsic_w_chain:{ *:[v2i16] } 4104:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)  =>  (MUL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
12457        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MUL_PH,
12458        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12459        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
12460        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
12461        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
12462        GIR_EraseFromParent, /*InsnID*/0,
12463        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12464        // GIR_Coverage, 1879,
12465        GIR_Done,
12466      // Label 807: @30153
12467      GIM_Try, /*On fail goto*//*Label 808*/ 30201, // Rule ID 1885 //
12468        GIM_CheckFeatures, GIFBS_HasDSP,
12469        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addsc,
12470        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12471        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12472        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
12473        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
12474        // (intrinsic_w_chain:{ *:[i32] } 3661:{ *:[iPTR] }, i32:{ *:[i32] }:$a, i32:{ *:[i32] }:$b)  =>  (ADDSC:{ *:[i32] } i32:{ *:[i32] }:$a, i32:{ *:[i32] }:$b)
12475        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDSC,
12476        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12477        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
12478        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
12479        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
12480        GIR_EraseFromParent, /*InsnID*/0,
12481        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12482        // GIR_Coverage, 1885,
12483        GIR_Done,
12484      // Label 808: @30201
12485      GIM_Try, /*On fail goto*//*Label 809*/ 30249, // Rule ID 1887 //
12486        GIM_CheckFeatures, GIFBS_HasDSP,
12487        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addwc,
12488        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12489        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12490        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
12491        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
12492        // (intrinsic_w_chain:{ *:[i32] } 3676:{ *:[iPTR] }, i32:{ *:[i32] }:$a, i32:{ *:[i32] }:$b)  =>  (ADDWC:{ *:[i32] } i32:{ *:[i32] }:$a, i32:{ *:[i32] }:$b)
12493        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDWC,
12494        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12495        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
12496        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
12497        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
12498        GIR_EraseFromParent, /*InsnID*/0,
12499        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12500        // GIR_Coverage, 1887,
12501        GIR_Done,
12502      // Label 809: @30249
12503      GIM_Reject,
12504    // Label 738: @30250
12505    GIM_Reject,
12506    // Label 17: @30251
12507    GIM_Try, /*On fail goto*//*Label 810*/ 30316, // Rule ID 1560 //
12508      GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit,
12509      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
12510      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
12511      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
12512      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
12513      // (anyext:{ *:[i64] } GPR32:{ *:[i32] }:$src)  =>  (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$src, sub_32:{ *:[i32] })
12514      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
12515      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
12516      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
12517      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
12518      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG,
12519      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12520      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
12521      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12522      GIR_AddImm, /*InsnID*/0, /*Imm*/1,
12523      GIR_EraseFromParent, /*InsnID*/0,
12524      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64*/38,
12525      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, /*RC GPR64*/38,
12526      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GPR32*/8,
12527      // GIR_Coverage, 1560,
12528      GIR_Done,
12529    // Label 810: @30316
12530    GIM_Reject,
12531    // Label 18: @30317
12532    GIM_Try, /*On fail goto*//*Label 811*/ 30379, // Rule ID 1555 //
12533      GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit,
12534      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12535      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
12536      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
12537      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
12538      // (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$src)  =>  (SLL:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$src, sub_32:{ *:[i32] }), 0:{ *:[i32] })
12539      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
12540      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
12541      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
12542      GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/1, // src
12543      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC GPR32*/8,
12544      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC GPR64*/38,
12545      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLL,
12546      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12547      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
12548      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
12549      GIR_EraseFromParent, /*InsnID*/0,
12550      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12551      // GIR_Coverage, 1555,
12552      GIR_Done,
12553    // Label 811: @30379
12554    GIM_Reject,
12555    // Label 19: @30380
12556    GIM_Try, /*On fail goto*//*Label 812*/ 30439,
12557      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12558      GIM_Try, /*On fail goto*//*Label 813*/ 30412, // Rule ID 2110 //
12559        GIM_CheckFeatures, GIFBS_InMicroMips,
12560        GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIPFP_I64_Predicate_immLi16,
12561        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
12562        // MIs[0] Operand 1
12563        // No operand predicates
12564        // (imm:{ *:[i32] })<<P:Predicate_immLi16>>:$imm  =>  (LI16_MM:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_immLi16>>:$imm)
12565        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LI16_MM,
12566        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12567        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
12568        GIR_EraseFromParent, /*InsnID*/0,
12569        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12570        // GIR_Coverage, 2110,
12571        GIR_Done,
12572      // Label 813: @30412
12573      GIM_Try, /*On fail goto*//*Label 814*/ 30438, // Rule ID 1803 //
12574        GIM_CheckFeatures, GIFBS_InMips16Mode,
12575        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
12576        // MIs[0] Operand 1
12577        // No operand predicates
12578        // (imm:{ *:[i32] }):$imm  =>  (LwConstant32:{ *:[i32] } (imm:{ *:[i32] }):$imm, -1:{ *:[i32] })
12579        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LwConstant32,
12580        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rx
12581        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
12582        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
12583        GIR_EraseFromParent, /*InsnID*/0,
12584        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12585        // GIR_Coverage, 1803,
12586        GIR_Done,
12587      // Label 814: @30438
12588      GIM_Reject,
12589    // Label 812: @30439
12590    GIM_Reject,
12591    // Label 20: @30440
12592    GIM_Try, /*On fail goto*//*Label 815*/ 31697,
12593      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
12594      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
12595      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
12596      GIM_Try, /*On fail goto*//*Label 816*/ 30553, // Rule ID 1594 //
12597        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
12598        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ASHR,
12599        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
12600        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
12601        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
12602        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
12603        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
12604        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
12605        // MIs[2] Operand 1
12606        // No operand predicates
12607        GIM_CheckIsSafeToFold, /*InsnID*/1,
12608        GIM_CheckIsSafeToFold, /*InsnID*/2,
12609        // (sext:{ *:[i64] } (sra:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm5))  =>  (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SRA:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm5), sub_32:{ *:[i32] })
12610        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
12611        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
12612        GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SRA,
12613        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
12614        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
12615        GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm5
12616        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
12617        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
12618        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
12619        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
12620        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG,
12621        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12622        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
12623        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
12624        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
12625        GIR_EraseFromParent, /*InsnID*/0,
12626        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64*/38,
12627        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, /*RC GPR64*/38,
12628        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GPR32*/8,
12629        // GIR_Coverage, 1594,
12630        GIR_Done,
12631      // Label 816: @30553
12632      GIM_Try, /*On fail goto*//*Label 817*/ 30652, // Rule ID 1592 //
12633        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
12634        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LSHR,
12635        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
12636        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
12637        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
12638        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
12639        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
12640        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
12641        // MIs[2] Operand 1
12642        // No operand predicates
12643        GIM_CheckIsSafeToFold, /*InsnID*/1,
12644        GIM_CheckIsSafeToFold, /*InsnID*/2,
12645        // (sext:{ *:[i64] } (srl:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm5))  =>  (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SRL:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm5), sub_32:{ *:[i32] })
12646        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
12647        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
12648        GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SRL,
12649        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
12650        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
12651        GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm5
12652        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
12653        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
12654        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
12655        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
12656        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG,
12657        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12658        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
12659        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
12660        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
12661        GIR_EraseFromParent, /*InsnID*/0,
12662        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64*/38,
12663        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, /*RC GPR64*/38,
12664        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GPR32*/8,
12665        // GIR_Coverage, 1592,
12666        GIR_Done,
12667      // Label 817: @30652
12668      GIM_Try, /*On fail goto*//*Label 818*/ 30751, // Rule ID 1590 //
12669        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
12670        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
12671        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
12672        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
12673        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
12674        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
12675        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
12676        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
12677        // MIs[2] Operand 1
12678        // No operand predicates
12679        GIM_CheckIsSafeToFold, /*InsnID*/1,
12680        GIM_CheckIsSafeToFold, /*InsnID*/2,
12681        // (sext:{ *:[i64] } (shl:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm5))  =>  (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SLL:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm5), sub_32:{ *:[i32] })
12682        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
12683        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
12684        GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SLL,
12685        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
12686        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
12687        GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm5
12688        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
12689        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
12690        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
12691        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
12692        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG,
12693        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12694        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
12695        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
12696        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
12697        GIR_EraseFromParent, /*InsnID*/0,
12698        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64*/38,
12699        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, /*RC GPR64*/38,
12700        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GPR32*/8,
12701        // GIR_Coverage, 1590,
12702        GIR_Done,
12703      // Label 818: @30751
12704      GIM_Try, /*On fail goto*//*Label 819*/ 30843, // Rule ID 1585 //
12705        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
12706        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
12707        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
12708        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
12709        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
12710        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
12711        GIM_CheckIsSafeToFold, /*InsnID*/1,
12712        // (sext:{ *:[i64] } (add:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2))  =>  (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ADDu:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
12713        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
12714        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
12715        GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::ADDu,
12716        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
12717        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
12718        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
12719        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
12720        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
12721        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
12722        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
12723        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG,
12724        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12725        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
12726        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
12727        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
12728        GIR_EraseFromParent, /*InsnID*/0,
12729        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64*/38,
12730        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, /*RC GPR64*/38,
12731        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GPR32*/8,
12732        // GIR_Coverage, 1585,
12733        GIR_Done,
12734      // Label 819: @30843
12735      GIM_Try, /*On fail goto*//*Label 820*/ 30935, // Rule ID 1595 //
12736        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
12737        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ASHR,
12738        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
12739        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
12740        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
12741        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
12742        GIM_CheckIsSafeToFold, /*InsnID*/1,
12743        // (sext:{ *:[i64] } (sra:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2))  =>  (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SRAV:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
12744        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
12745        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
12746        GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SRAV,
12747        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
12748        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
12749        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
12750        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
12751        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
12752        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
12753        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
12754        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG,
12755        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12756        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
12757        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
12758        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
12759        GIR_EraseFromParent, /*InsnID*/0,
12760        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64*/38,
12761        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, /*RC GPR64*/38,
12762        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GPR32*/8,
12763        // GIR_Coverage, 1595,
12764        GIR_Done,
12765      // Label 820: @30935
12766      GIM_Try, /*On fail goto*//*Label 821*/ 31027, // Rule ID 1593 //
12767        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
12768        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LSHR,
12769        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
12770        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
12771        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
12772        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
12773        GIM_CheckIsSafeToFold, /*InsnID*/1,
12774        // (sext:{ *:[i64] } (srl:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2))  =>  (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SRLV:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
12775        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
12776        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
12777        GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SRLV,
12778        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
12779        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
12780        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
12781        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
12782        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
12783        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
12784        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
12785        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG,
12786        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12787        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
12788        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
12789        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
12790        GIR_EraseFromParent, /*InsnID*/0,
12791        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64*/38,
12792        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, /*RC GPR64*/38,
12793        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GPR32*/8,
12794        // GIR_Coverage, 1593,
12795        GIR_Done,
12796      // Label 821: @31027
12797      GIM_Try, /*On fail goto*//*Label 822*/ 31121, // Rule ID 1770 //
12798        GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc,
12799        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
12800        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
12801        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
12802        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
12803        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
12804        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
12805        GIM_CheckIsSafeToFold, /*InsnID*/1,
12806        // (sext:{ *:[i64] } (mul:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2))  =>  (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (MUL_R6:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
12807        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
12808        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
12809        GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::MUL_R6,
12810        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
12811        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
12812        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
12813        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
12814        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
12815        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
12816        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
12817        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG,
12818        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12819        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
12820        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
12821        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
12822        GIR_EraseFromParent, /*InsnID*/0,
12823        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64*/38,
12824        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, /*RC GPR64*/38,
12825        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GPR32*/8,
12826        // GIR_Coverage, 1770,
12827        GIR_Done,
12828      // Label 822: @31121
12829      GIM_Try, /*On fail goto*//*Label 823*/ 31215, // Rule ID 1771 //
12830        GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc,
12831        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
12832        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SDIV,
12833        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
12834        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
12835        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
12836        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
12837        GIM_CheckIsSafeToFold, /*InsnID*/1,
12838        // (sext:{ *:[i64] } (sdiv:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2))  =>  (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (DIV:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
12839        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
12840        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
12841        GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::DIV,
12842        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
12843        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
12844        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
12845        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
12846        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
12847        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
12848        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
12849        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG,
12850        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12851        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
12852        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
12853        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
12854        GIR_EraseFromParent, /*InsnID*/0,
12855        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64*/38,
12856        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, /*RC GPR64*/38,
12857        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GPR32*/8,
12858        // GIR_Coverage, 1771,
12859        GIR_Done,
12860      // Label 823: @31215
12861      GIM_Try, /*On fail goto*//*Label 824*/ 31307, // Rule ID 1591 //
12862        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
12863        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
12864        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
12865        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
12866        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
12867        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
12868        GIM_CheckIsSafeToFold, /*InsnID*/1,
12869        // (sext:{ *:[i64] } (shl:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2))  =>  (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SLLV:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
12870        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
12871        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
12872        GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SLLV,
12873        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
12874        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
12875        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
12876        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
12877        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
12878        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
12879        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
12880        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG,
12881        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12882        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
12883        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
12884        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
12885        GIR_EraseFromParent, /*InsnID*/0,
12886        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64*/38,
12887        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, /*RC GPR64*/38,
12888        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GPR32*/8,
12889        // GIR_Coverage, 1591,
12890        GIR_Done,
12891      // Label 824: @31307
12892      GIM_Try, /*On fail goto*//*Label 825*/ 31401, // Rule ID 1773 //
12893        GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc,
12894        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
12895        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SREM,
12896        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
12897        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
12898        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
12899        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
12900        GIM_CheckIsSafeToFold, /*InsnID*/1,
12901        // (sext:{ *:[i64] } (srem:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2))  =>  (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (MOD:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
12902        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
12903        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
12904        GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::MOD,
12905        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
12906        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
12907        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
12908        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
12909        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
12910        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
12911        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
12912        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG,
12913        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12914        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
12915        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
12916        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
12917        GIR_EraseFromParent, /*InsnID*/0,
12918        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64*/38,
12919        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, /*RC GPR64*/38,
12920        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GPR32*/8,
12921        // GIR_Coverage, 1773,
12922        GIR_Done,
12923      // Label 825: @31401
12924      GIM_Try, /*On fail goto*//*Label 826*/ 31493, // Rule ID 1586 //
12925        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
12926        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB,
12927        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
12928        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
12929        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
12930        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
12931        GIM_CheckIsSafeToFold, /*InsnID*/1,
12932        // (sext:{ *:[i64] } (sub:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2))  =>  (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SUBu:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
12933        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
12934        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
12935        GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SUBu,
12936        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
12937        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
12938        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
12939        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
12940        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
12941        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
12942        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
12943        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG,
12944        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12945        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
12946        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
12947        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
12948        GIR_EraseFromParent, /*InsnID*/0,
12949        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64*/38,
12950        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, /*RC GPR64*/38,
12951        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GPR32*/8,
12952        // GIR_Coverage, 1586,
12953        GIR_Done,
12954      // Label 826: @31493
12955      GIM_Try, /*On fail goto*//*Label 827*/ 31587, // Rule ID 1772 //
12956        GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc,
12957        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
12958        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_UDIV,
12959        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
12960        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
12961        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
12962        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
12963        GIM_CheckIsSafeToFold, /*InsnID*/1,
12964        // (sext:{ *:[i64] } (udiv:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2))  =>  (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (DIVU:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
12965        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
12966        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
12967        GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::DIVU,
12968        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
12969        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
12970        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
12971        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
12972        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
12973        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
12974        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
12975        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG,
12976        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12977        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
12978        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
12979        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
12980        GIR_EraseFromParent, /*InsnID*/0,
12981        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64*/38,
12982        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, /*RC GPR64*/38,
12983        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GPR32*/8,
12984        // GIR_Coverage, 1772,
12985        GIR_Done,
12986      // Label 827: @31587
12987      GIM_Try, /*On fail goto*//*Label 828*/ 31681, // Rule ID 1774 //
12988        GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc,
12989        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
12990        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_UREM,
12991        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
12992        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
12993        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
12994        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
12995        GIM_CheckIsSafeToFold, /*InsnID*/1,
12996        // (sext:{ *:[i64] } (urem:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2))  =>  (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (MODU:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
12997        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
12998        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
12999        GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::MODU,
13000        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
13001        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
13002        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
13003        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
13004        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
13005        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
13006        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
13007        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG,
13008        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
13009        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
13010        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
13011        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
13012        GIR_EraseFromParent, /*InsnID*/0,
13013        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64*/38,
13014        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, /*RC GPR64*/38,
13015        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GPR32*/8,
13016        // GIR_Coverage, 1774,
13017        GIR_Done,
13018      // Label 828: @31681
13019      GIM_Try, /*On fail goto*//*Label 829*/ 31696, // Rule ID 1562 //
13020        GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit,
13021        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
13022        // (sext:{ *:[i64] } GPR32:{ *:[i32] }:$src)  =>  (SLL64_32:{ *:[i64] } GPR32:{ *:[i32] }:$src)
13023        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SLL64_32,
13024        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13025        // GIR_Coverage, 1562,
13026        GIR_Done,
13027      // Label 829: @31696
13028      GIM_Reject,
13029    // Label 815: @31697
13030    GIM_Reject,
13031    // Label 21: @31698
13032    GIM_Try, /*On fail goto*//*Label 830*/ 31891,
13033      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
13034      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
13035      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
13036      GIM_Try, /*On fail goto*//*Label 831*/ 31765, // Rule ID 268 //
13037        GIM_CheckFeatures, GIFBS_HasCnMips,
13038        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
13039        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
13040        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
13041        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
13042        // MIs[1] Operand 1
13043        GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
13044        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
13045        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
13046        GIM_CheckIsSafeToFold, /*InsnID*/1,
13047        // (zext:{ *:[i64] } (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, SETEQ:{ *:[Other] }))  =>  (SEQ:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
13048        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SEQ,
13049        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
13050        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
13051        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
13052        GIR_EraseFromParent, /*InsnID*/0,
13053        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13054        // GIR_Coverage, 268,
13055        GIR_Done,
13056      // Label 831: @31765
13057      GIM_Try, /*On fail goto*//*Label 832*/ 31818, // Rule ID 270 //
13058        GIM_CheckFeatures, GIFBS_HasCnMips,
13059        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
13060        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
13061        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
13062        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
13063        // MIs[1] Operand 1
13064        GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
13065        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
13066        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
13067        GIM_CheckIsSafeToFold, /*InsnID*/1,
13068        // (zext:{ *:[i64] } (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, SETNE:{ *:[Other] }))  =>  (SNE:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
13069        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SNE,
13070        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
13071        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
13072        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
13073        GIR_EraseFromParent, /*InsnID*/0,
13074        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13075        // GIR_Coverage, 270,
13076        GIR_Done,
13077      // Label 832: @31818
13078      GIM_Try, /*On fail goto*//*Label 833*/ 31890,
13079        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
13080        GIM_Try, /*On fail goto*//*Label 834*/ 31863, // Rule ID 1561 //
13081          GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit,
13082          // (zext:{ *:[i64] } GPR32:{ *:[i32] }:$src)  =>  (DSRL:{ *:[i64] } (DSLL64_32:{ *:[i64] } GPR32:{ *:[i32] }:$src), 32:{ *:[i32] })
13083          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
13084          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::DSLL64_32,
13085          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
13086          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
13087          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
13088          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSRL,
13089          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
13090          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
13091          GIR_AddImm, /*InsnID*/0, /*Imm*/32,
13092          GIR_EraseFromParent, /*InsnID*/0,
13093          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13094          // GIR_Coverage, 1561,
13095          GIR_Done,
13096        // Label 834: @31863
13097        GIM_Try, /*On fail goto*//*Label 835*/ 31889, // Rule ID 1563 //
13098          GIM_CheckFeatures, GIFBS_HasMips64r2_HasStdEnc_IsGP64bit_NotInMicroMips,
13099          // (zext:{ *:[i64] } GPR32:{ *:[i32] }:$src)  =>  (DEXT64_32:{ *:[i64] } GPR32:{ *:[i32] }:$src, 0:{ *:[i32] }, 32:{ *:[i32] })
13100          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DEXT64_32,
13101          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
13102          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13103          GIR_AddImm, /*InsnID*/0, /*Imm*/0,
13104          GIR_AddImm, /*InsnID*/0, /*Imm*/32,
13105          GIR_EraseFromParent, /*InsnID*/0,
13106          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13107          // GIR_Coverage, 1563,
13108          GIR_Done,
13109        // Label 835: @31889
13110        GIM_Reject,
13111      // Label 833: @31890
13112      GIM_Reject,
13113    // Label 830: @31891
13114    GIM_Reject,
13115    // Label 22: @31892
13116    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 842*/ 33644,
13117    /*GILLT_s32*//*Label 836*/ 31906,
13118    /*GILLT_s64*//*Label 837*/ 32159, 0,
13119    /*GILLT_v2s64*//*Label 838*/ 32293, 0,
13120    /*GILLT_v4s32*//*Label 839*/ 32325,
13121    /*GILLT_v8s16*//*Label 840*/ 32594,
13122    /*GILLT_v16s8*//*Label 841*/ 32991,
13123    // Label 836: @31906
13124    GIM_Try, /*On fail goto*//*Label 843*/ 32158,
13125      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
13126      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
13127      GIM_Try, /*On fail goto*//*Label 844*/ 31959, // Rule ID 55 //
13128        GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
13129        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
13130        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
13131        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
13132        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
13133        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
13134        // MIs[1] Operand 1
13135        // No operand predicates
13136        GIM_CheckIsSafeToFold, /*InsnID*/1,
13137        // (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shamt)  =>  (SLL:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$shamt)
13138        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLL,
13139        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
13140        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt
13141        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
13142        GIR_EraseFromParent, /*InsnID*/0,
13143        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13144        // GIR_Coverage, 55,
13145        GIR_Done,
13146      // Label 844: @31959
13147      GIM_Try, /*On fail goto*//*Label 845*/ 32002, // Rule ID 1785 //
13148        GIM_CheckFeatures, GIFBS_InMips16Mode,
13149        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
13150        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
13151        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
13152        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
13153        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
13154        // MIs[1] Operand 1
13155        // No operand predicates
13156        GIM_CheckIsSafeToFold, /*InsnID*/1,
13157        // (shl:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)  =>  (SllX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
13158        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SllX16,
13159        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rx
13160        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in
13161        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
13162        GIR_EraseFromParent, /*InsnID*/0,
13163        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13164        // GIR_Coverage, 1785,
13165        GIR_Done,
13166      // Label 845: @32002
13167      GIM_Try, /*On fail goto*//*Label 846*/ 32045, // Rule ID 2122 //
13168        GIM_CheckFeatures, GIFBS_InMicroMips,
13169        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
13170        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
13171        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
13172        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
13173        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt2Shift,
13174        // MIs[1] Operand 1
13175        // No operand predicates
13176        GIM_CheckIsSafeToFold, /*InsnID*/1,
13177        // (shl:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt2Shift>>:$imm)  =>  (SLL16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt2Shift>>:$imm)
13178        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLL16_MM,
13179        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
13180        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13181        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
13182        GIR_EraseFromParent, /*InsnID*/0,
13183        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13184        // GIR_Coverage, 2122,
13185        GIR_Done,
13186      // Label 846: @32045
13187      GIM_Try, /*On fail goto*//*Label 847*/ 32088, // Rule ID 2123 //
13188        GIM_CheckFeatures, GIFBS_InMicroMips,
13189        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
13190        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
13191        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
13192        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
13193        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
13194        // MIs[1] Operand 1
13195        // No operand predicates
13196        GIM_CheckIsSafeToFold, /*InsnID*/1,
13197        // (shl:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)  =>  (SLL_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
13198        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLL_MM,
13199        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
13200        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13201        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
13202        GIR_EraseFromParent, /*InsnID*/0,
13203        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13204        // GIR_Coverage, 2123,
13205        GIR_Done,
13206      // Label 847: @32088
13207      GIM_Try, /*On fail goto*//*Label 848*/ 32111, // Rule ID 58 //
13208        GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
13209        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
13210        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
13211        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
13212        // (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)  =>  (SLLV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
13213        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SLLV,
13214        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13215        // GIR_Coverage, 58,
13216        GIR_Done,
13217      // Label 848: @32111
13218      GIM_Try, /*On fail goto*//*Label 849*/ 32134, // Rule ID 1788 //
13219        GIM_CheckFeatures, GIFBS_InMips16Mode,
13220        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
13221        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
13222        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
13223        // (shl:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra)  =>  (SllvRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra)
13224        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SllvRxRy16,
13225        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13226        // GIR_Coverage, 1788,
13227        GIR_Done,
13228      // Label 849: @32134
13229      GIM_Try, /*On fail goto*//*Label 850*/ 32157, // Rule ID 2124 //
13230        GIM_CheckFeatures, GIFBS_InMicroMips,
13231        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
13232        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
13233        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
13234        // (shl:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs)  =>  (SLLV_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs)
13235        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SLLV_MM,
13236        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13237        // GIR_Coverage, 2124,
13238        GIR_Done,
13239      // Label 850: @32157
13240      GIM_Reject,
13241    // Label 843: @32158
13242    GIM_Reject,
13243    // Label 837: @32159
13244    GIM_Try, /*On fail goto*//*Label 851*/ 32292,
13245      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
13246      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
13247      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
13248      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
13249      GIM_Try, /*On fail goto*//*Label 852*/ 32212, // Rule ID 204 //
13250        GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_NotInMicroMips,
13251        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
13252        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
13253        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt6,
13254        // MIs[1] Operand 1
13255        // No operand predicates
13256        GIM_CheckIsSafeToFold, /*InsnID*/1,
13257        // (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$shamt)  =>  (DSLL:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$shamt)
13258        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSLL,
13259        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
13260        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt
13261        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
13262        GIR_EraseFromParent, /*InsnID*/0,
13263        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13264        // GIR_Coverage, 204,
13265        GIR_Done,
13266      // Label 852: @32212
13267      GIM_Try, /*On fail goto*//*Label 853*/ 32276, // Rule ID 1556 //
13268        GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit,
13269        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
13270        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC,
13271        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
13272        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
13273        GIM_CheckIsSafeToFold, /*InsnID*/1,
13274        // (shl:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$rs))  =>  (DSLLV:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$rs, sub_32:{ *:[i32] }))
13275        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
13276        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
13277        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
13278        GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/1, // rs
13279        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC GPR32*/8,
13280        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC GPR64*/38,
13281        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSLLV,
13282        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
13283        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt
13284        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
13285        GIR_EraseFromParent, /*InsnID*/0,
13286        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13287        // GIR_Coverage, 1556,
13288        GIR_Done,
13289      // Label 853: @32276
13290      GIM_Try, /*On fail goto*//*Label 854*/ 32291, // Rule ID 207 //
13291        GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_NotInMicroMips,
13292        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
13293        // (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)  =>  (DSLLV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
13294        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DSLLV,
13295        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13296        // GIR_Coverage, 207,
13297        GIR_Done,
13298      // Label 854: @32291
13299      GIM_Reject,
13300    // Label 851: @32292
13301    GIM_Reject,
13302    // Label 838: @32293
13303    GIM_Try, /*On fail goto*//*Label 855*/ 32324, // Rule ID 944 //
13304      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
13305      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
13306      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
13307      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
13308      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
13309      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
13310      // (shl:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (SLL_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
13311      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SLL_D,
13312      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13313      // GIR_Coverage, 944,
13314      GIR_Done,
13315    // Label 855: @32324
13316    GIM_Reject,
13317    // Label 839: @32325
13318    GIM_Try, /*On fail goto*//*Label 856*/ 32593,
13319      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
13320      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
13321      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
13322      GIM_Try, /*On fail goto*//*Label 857*/ 32456, // Rule ID 2414 //
13323        GIM_CheckFeatures, GIFBS_HasMSA,
13324        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
13325        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
13326        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
13327        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
13328        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
13329        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR,
13330        GIM_CheckNumOperands, /*MI*/2, /*Expected*/5,
13331        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
13332        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
13333        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
13334        GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
13335        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
13336        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
13337        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_immi32Cst31,
13338        // MIs[3] Operand 1
13339        // No operand predicates
13340        GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
13341        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
13342        GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_immi32Cst31,
13343        // MIs[4] Operand 1
13344        // No operand predicates
13345        GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
13346        GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT,
13347        GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIPFP_I64_Predicate_immi32Cst31,
13348        // MIs[5] Operand 1
13349        // No operand predicates
13350        GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
13351        GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT,
13352        GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIPFP_I64_Predicate_immi32Cst31,
13353        // MIs[6] Operand 1
13354        // No operand predicates
13355        GIM_CheckIsSafeToFold, /*InsnID*/1,
13356        GIM_CheckIsSafeToFold, /*InsnID*/2,
13357        GIM_CheckIsSafeToFold, /*InsnID*/3,
13358        GIM_CheckIsSafeToFold, /*InsnID*/4,
13359        GIM_CheckIsSafeToFold, /*InsnID*/5,
13360        GIM_CheckIsSafeToFold, /*InsnID*/6,
13361        // (shl:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>), v4i32:{ *:[v4i32] }:$wt))  =>  (SLL_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
13362        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLL_W,
13363        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
13364        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws
13365        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
13366        GIR_EraseFromParent, /*InsnID*/0,
13367        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13368        // GIR_Coverage, 2414,
13369        GIR_Done,
13370      // Label 857: @32456
13371      GIM_Try, /*On fail goto*//*Label 858*/ 32573, // Rule ID 2025 //
13372        GIM_CheckFeatures, GIFBS_HasMSA,
13373        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
13374        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
13375        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
13376        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
13377        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
13378        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR,
13379        GIM_CheckNumOperands, /*MI*/2, /*Expected*/5,
13380        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
13381        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
13382        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
13383        GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
13384        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
13385        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
13386        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_immi32Cst31,
13387        // MIs[3] Operand 1
13388        // No operand predicates
13389        GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
13390        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
13391        GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_immi32Cst31,
13392        // MIs[4] Operand 1
13393        // No operand predicates
13394        GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
13395        GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT,
13396        GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIPFP_I64_Predicate_immi32Cst31,
13397        // MIs[5] Operand 1
13398        // No operand predicates
13399        GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
13400        GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT,
13401        GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIPFP_I64_Predicate_immi32Cst31,
13402        // MIs[6] Operand 1
13403        // No operand predicates
13404        GIM_CheckIsSafeToFold, /*InsnID*/1,
13405        GIM_CheckIsSafeToFold, /*InsnID*/2,
13406        GIM_CheckIsSafeToFold, /*InsnID*/3,
13407        GIM_CheckIsSafeToFold, /*InsnID*/4,
13408        GIM_CheckIsSafeToFold, /*InsnID*/5,
13409        GIM_CheckIsSafeToFold, /*InsnID*/6,
13410        // (shl:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$wt, (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>)))  =>  (SLL_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
13411        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLL_W,
13412        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
13413        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws
13414        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
13415        GIR_EraseFromParent, /*InsnID*/0,
13416        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13417        // GIR_Coverage, 2025,
13418        GIR_Done,
13419      // Label 858: @32573
13420      GIM_Try, /*On fail goto*//*Label 859*/ 32592, // Rule ID 943 //
13421        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
13422        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
13423        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
13424        // (shl:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (SLL_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
13425        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SLL_W,
13426        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13427        // GIR_Coverage, 943,
13428        GIR_Done,
13429      // Label 859: @32592
13430      GIM_Reject,
13431    // Label 856: @32593
13432    GIM_Reject,
13433    // Label 840: @32594
13434    GIM_Try, /*On fail goto*//*Label 860*/ 32990,
13435      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
13436      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
13437      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
13438      GIM_Try, /*On fail goto*//*Label 861*/ 32789, // Rule ID 2413 //
13439        GIM_CheckFeatures, GIFBS_HasMSA,
13440        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
13441        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
13442        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
13443        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
13444        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
13445        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR,
13446        GIM_CheckNumOperands, /*MI*/2, /*Expected*/9,
13447        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
13448        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
13449        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
13450        GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
13451        GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
13452        GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
13453        GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
13454        GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
13455        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
13456        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
13457        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
13458        // MIs[3] Operand 1
13459        // No operand predicates
13460        GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
13461        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
13462        GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
13463        // MIs[4] Operand 1
13464        // No operand predicates
13465        GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
13466        GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT,
13467        GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
13468        // MIs[5] Operand 1
13469        // No operand predicates
13470        GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
13471        GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT,
13472        GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
13473        // MIs[6] Operand 1
13474        // No operand predicates
13475        GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
13476        GIM_CheckOpcode, /*MI*/7, TargetOpcode::G_CONSTANT,
13477        GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
13478        // MIs[7] Operand 1
13479        // No operand predicates
13480        GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
13481        GIM_CheckOpcode, /*MI*/8, TargetOpcode::G_CONSTANT,
13482        GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
13483        // MIs[8] Operand 1
13484        // No operand predicates
13485        GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
13486        GIM_CheckOpcode, /*MI*/9, TargetOpcode::G_CONSTANT,
13487        GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
13488        // MIs[9] Operand 1
13489        // No operand predicates
13490        GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
13491        GIM_CheckOpcode, /*MI*/10, TargetOpcode::G_CONSTANT,
13492        GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
13493        // MIs[10] Operand 1
13494        // No operand predicates
13495        GIM_CheckIsSafeToFold, /*InsnID*/1,
13496        GIM_CheckIsSafeToFold, /*InsnID*/2,
13497        GIM_CheckIsSafeToFold, /*InsnID*/3,
13498        GIM_CheckIsSafeToFold, /*InsnID*/4,
13499        GIM_CheckIsSafeToFold, /*InsnID*/5,
13500        GIM_CheckIsSafeToFold, /*InsnID*/6,
13501        GIM_CheckIsSafeToFold, /*InsnID*/7,
13502        GIM_CheckIsSafeToFold, /*InsnID*/8,
13503        GIM_CheckIsSafeToFold, /*InsnID*/9,
13504        GIM_CheckIsSafeToFold, /*InsnID*/10,
13505        // (shl:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>), v8i16:{ *:[v8i16] }:$wt))  =>  (SLL_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
13506        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLL_H,
13507        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
13508        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws
13509        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
13510        GIR_EraseFromParent, /*InsnID*/0,
13511        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13512        // GIR_Coverage, 2413,
13513        GIR_Done,
13514      // Label 861: @32789
13515      GIM_Try, /*On fail goto*//*Label 862*/ 32970, // Rule ID 2024 //
13516        GIM_CheckFeatures, GIFBS_HasMSA,
13517        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
13518        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
13519        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
13520        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
13521        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
13522        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR,
13523        GIM_CheckNumOperands, /*MI*/2, /*Expected*/9,
13524        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
13525        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
13526        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
13527        GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
13528        GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
13529        GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
13530        GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
13531        GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
13532        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
13533        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
13534        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
13535        // MIs[3] Operand 1
13536        // No operand predicates
13537        GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
13538        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
13539        GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
13540        // MIs[4] Operand 1
13541        // No operand predicates
13542        GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
13543        GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT,
13544        GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
13545        // MIs[5] Operand 1
13546        // No operand predicates
13547        GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
13548        GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT,
13549        GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
13550        // MIs[6] Operand 1
13551        // No operand predicates
13552        GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
13553        GIM_CheckOpcode, /*MI*/7, TargetOpcode::G_CONSTANT,
13554        GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
13555        // MIs[7] Operand 1
13556        // No operand predicates
13557        GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
13558        GIM_CheckOpcode, /*MI*/8, TargetOpcode::G_CONSTANT,
13559        GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
13560        // MIs[8] Operand 1
13561        // No operand predicates
13562        GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
13563        GIM_CheckOpcode, /*MI*/9, TargetOpcode::G_CONSTANT,
13564        GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
13565        // MIs[9] Operand 1
13566        // No operand predicates
13567        GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
13568        GIM_CheckOpcode, /*MI*/10, TargetOpcode::G_CONSTANT,
13569        GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
13570        // MIs[10] Operand 1
13571        // No operand predicates
13572        GIM_CheckIsSafeToFold, /*InsnID*/1,
13573        GIM_CheckIsSafeToFold, /*InsnID*/2,
13574        GIM_CheckIsSafeToFold, /*InsnID*/3,
13575        GIM_CheckIsSafeToFold, /*InsnID*/4,
13576        GIM_CheckIsSafeToFold, /*InsnID*/5,
13577        GIM_CheckIsSafeToFold, /*InsnID*/6,
13578        GIM_CheckIsSafeToFold, /*InsnID*/7,
13579        GIM_CheckIsSafeToFold, /*InsnID*/8,
13580        GIM_CheckIsSafeToFold, /*InsnID*/9,
13581        GIM_CheckIsSafeToFold, /*InsnID*/10,
13582        // (shl:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$wt, (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>)))  =>  (SLL_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
13583        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLL_H,
13584        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
13585        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws
13586        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
13587        GIR_EraseFromParent, /*InsnID*/0,
13588        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13589        // GIR_Coverage, 2024,
13590        GIR_Done,
13591      // Label 862: @32970
13592      GIM_Try, /*On fail goto*//*Label 863*/ 32989, // Rule ID 942 //
13593        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
13594        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
13595        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
13596        // (shl:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (SLL_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
13597        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SLL_H,
13598        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13599        // GIR_Coverage, 942,
13600        GIR_Done,
13601      // Label 863: @32989
13602      GIM_Reject,
13603    // Label 860: @32990
13604    GIM_Reject,
13605    // Label 841: @32991
13606    GIM_Try, /*On fail goto*//*Label 864*/ 33643,
13607      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
13608      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
13609      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
13610      GIM_Try, /*On fail goto*//*Label 865*/ 33314, // Rule ID 2412 //
13611        GIM_CheckFeatures, GIFBS_HasMSA,
13612        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
13613        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
13614        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
13615        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
13616        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
13617        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR,
13618        GIM_CheckNumOperands, /*MI*/2, /*Expected*/17,
13619        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
13620        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
13621        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
13622        GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
13623        GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
13624        GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
13625        GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
13626        GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
13627        GIM_CheckType, /*MI*/2, /*Op*/9, /*Type*/GILLT_s32,
13628        GIM_CheckType, /*MI*/2, /*Op*/10, /*Type*/GILLT_s32,
13629        GIM_CheckType, /*MI*/2, /*Op*/11, /*Type*/GILLT_s32,
13630        GIM_CheckType, /*MI*/2, /*Op*/12, /*Type*/GILLT_s32,
13631        GIM_CheckType, /*MI*/2, /*Op*/13, /*Type*/GILLT_s32,
13632        GIM_CheckType, /*MI*/2, /*Op*/14, /*Type*/GILLT_s32,
13633        GIM_CheckType, /*MI*/2, /*Op*/15, /*Type*/GILLT_s32,
13634        GIM_CheckType, /*MI*/2, /*Op*/16, /*Type*/GILLT_s32,
13635        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
13636        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
13637        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
13638        // MIs[3] Operand 1
13639        // No operand predicates
13640        GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
13641        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
13642        GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
13643        // MIs[4] Operand 1
13644        // No operand predicates
13645        GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
13646        GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT,
13647        GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
13648        // MIs[5] Operand 1
13649        // No operand predicates
13650        GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
13651        GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT,
13652        GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
13653        // MIs[6] Operand 1
13654        // No operand predicates
13655        GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
13656        GIM_CheckOpcode, /*MI*/7, TargetOpcode::G_CONSTANT,
13657        GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
13658        // MIs[7] Operand 1
13659        // No operand predicates
13660        GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
13661        GIM_CheckOpcode, /*MI*/8, TargetOpcode::G_CONSTANT,
13662        GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
13663        // MIs[8] Operand 1
13664        // No operand predicates
13665        GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
13666        GIM_CheckOpcode, /*MI*/9, TargetOpcode::G_CONSTANT,
13667        GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
13668        // MIs[9] Operand 1
13669        // No operand predicates
13670        GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
13671        GIM_CheckOpcode, /*MI*/10, TargetOpcode::G_CONSTANT,
13672        GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
13673        // MIs[10] Operand 1
13674        // No operand predicates
13675        GIM_RecordInsn, /*DefineMI*/11, /*MI*/2, /*OpIdx*/9, // MIs[11]
13676        GIM_CheckOpcode, /*MI*/11, TargetOpcode::G_CONSTANT,
13677        GIM_CheckI64ImmPredicate, /*MI*/11, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
13678        // MIs[11] Operand 1
13679        // No operand predicates
13680        GIM_RecordInsn, /*DefineMI*/12, /*MI*/2, /*OpIdx*/10, // MIs[12]
13681        GIM_CheckOpcode, /*MI*/12, TargetOpcode::G_CONSTANT,
13682        GIM_CheckI64ImmPredicate, /*MI*/12, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
13683        // MIs[12] Operand 1
13684        // No operand predicates
13685        GIM_RecordInsn, /*DefineMI*/13, /*MI*/2, /*OpIdx*/11, // MIs[13]
13686        GIM_CheckOpcode, /*MI*/13, TargetOpcode::G_CONSTANT,
13687        GIM_CheckI64ImmPredicate, /*MI*/13, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
13688        // MIs[13] Operand 1
13689        // No operand predicates
13690        GIM_RecordInsn, /*DefineMI*/14, /*MI*/2, /*OpIdx*/12, // MIs[14]
13691        GIM_CheckOpcode, /*MI*/14, TargetOpcode::G_CONSTANT,
13692        GIM_CheckI64ImmPredicate, /*MI*/14, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
13693        // MIs[14] Operand 1
13694        // No operand predicates
13695        GIM_RecordInsn, /*DefineMI*/15, /*MI*/2, /*OpIdx*/13, // MIs[15]
13696        GIM_CheckOpcode, /*MI*/15, TargetOpcode::G_CONSTANT,
13697        GIM_CheckI64ImmPredicate, /*MI*/15, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
13698        // MIs[15] Operand 1
13699        // No operand predicates
13700        GIM_RecordInsn, /*DefineMI*/16, /*MI*/2, /*OpIdx*/14, // MIs[16]
13701        GIM_CheckOpcode, /*MI*/16, TargetOpcode::G_CONSTANT,
13702        GIM_CheckI64ImmPredicate, /*MI*/16, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
13703        // MIs[16] Operand 1
13704        // No operand predicates
13705        GIM_RecordInsn, /*DefineMI*/17, /*MI*/2, /*OpIdx*/15, // MIs[17]
13706        GIM_CheckOpcode, /*MI*/17, TargetOpcode::G_CONSTANT,
13707        GIM_CheckI64ImmPredicate, /*MI*/17, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
13708        // MIs[17] Operand 1
13709        // No operand predicates
13710        GIM_RecordInsn, /*DefineMI*/18, /*MI*/2, /*OpIdx*/16, // MIs[18]
13711        GIM_CheckOpcode, /*MI*/18, TargetOpcode::G_CONSTANT,
13712        GIM_CheckI64ImmPredicate, /*MI*/18, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
13713        // MIs[18] Operand 1
13714        // No operand predicates
13715        GIM_CheckIsSafeToFold, /*InsnID*/1,
13716        GIM_CheckIsSafeToFold, /*InsnID*/2,
13717        GIM_CheckIsSafeToFold, /*InsnID*/3,
13718        GIM_CheckIsSafeToFold, /*InsnID*/4,
13719        GIM_CheckIsSafeToFold, /*InsnID*/5,
13720        GIM_CheckIsSafeToFold, /*InsnID*/6,
13721        GIM_CheckIsSafeToFold, /*InsnID*/7,
13722        GIM_CheckIsSafeToFold, /*InsnID*/8,
13723        GIM_CheckIsSafeToFold, /*InsnID*/9,
13724        GIM_CheckIsSafeToFold, /*InsnID*/10,
13725        GIM_CheckIsSafeToFold, /*InsnID*/11,
13726        GIM_CheckIsSafeToFold, /*InsnID*/12,
13727        GIM_CheckIsSafeToFold, /*InsnID*/13,
13728        GIM_CheckIsSafeToFold, /*InsnID*/14,
13729        GIM_CheckIsSafeToFold, /*InsnID*/15,
13730        GIM_CheckIsSafeToFold, /*InsnID*/16,
13731        GIM_CheckIsSafeToFold, /*InsnID*/17,
13732        GIM_CheckIsSafeToFold, /*InsnID*/18,
13733        // (shl:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>), v16i8:{ *:[v16i8] }:$wt))  =>  (SLL_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
13734        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLL_B,
13735        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
13736        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws
13737        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
13738        GIR_EraseFromParent, /*InsnID*/0,
13739        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13740        // GIR_Coverage, 2412,
13741        GIR_Done,
13742      // Label 865: @33314
13743      GIM_Try, /*On fail goto*//*Label 866*/ 33623, // Rule ID 2023 //
13744        GIM_CheckFeatures, GIFBS_HasMSA,
13745        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
13746        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
13747        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
13748        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
13749        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
13750        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR,
13751        GIM_CheckNumOperands, /*MI*/2, /*Expected*/17,
13752        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
13753        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
13754        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
13755        GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
13756        GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
13757        GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
13758        GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
13759        GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
13760        GIM_CheckType, /*MI*/2, /*Op*/9, /*Type*/GILLT_s32,
13761        GIM_CheckType, /*MI*/2, /*Op*/10, /*Type*/GILLT_s32,
13762        GIM_CheckType, /*MI*/2, /*Op*/11, /*Type*/GILLT_s32,
13763        GIM_CheckType, /*MI*/2, /*Op*/12, /*Type*/GILLT_s32,
13764        GIM_CheckType, /*MI*/2, /*Op*/13, /*Type*/GILLT_s32,
13765        GIM_CheckType, /*MI*/2, /*Op*/14, /*Type*/GILLT_s32,
13766        GIM_CheckType, /*MI*/2, /*Op*/15, /*Type*/GILLT_s32,
13767        GIM_CheckType, /*MI*/2, /*Op*/16, /*Type*/GILLT_s32,
13768        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
13769        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
13770        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
13771        // MIs[3] Operand 1
13772        // No operand predicates
13773        GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
13774        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
13775        GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
13776        // MIs[4] Operand 1
13777        // No operand predicates
13778        GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
13779        GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT,
13780        GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
13781        // MIs[5] Operand 1
13782        // No operand predicates
13783        GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
13784        GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT,
13785        GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
13786        // MIs[6] Operand 1
13787        // No operand predicates
13788        GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
13789        GIM_CheckOpcode, /*MI*/7, TargetOpcode::G_CONSTANT,
13790        GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
13791        // MIs[7] Operand 1
13792        // No operand predicates
13793        GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
13794        GIM_CheckOpcode, /*MI*/8, TargetOpcode::G_CONSTANT,
13795        GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
13796        // MIs[8] Operand 1
13797        // No operand predicates
13798        GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
13799        GIM_CheckOpcode, /*MI*/9, TargetOpcode::G_CONSTANT,
13800        GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
13801        // MIs[9] Operand 1
13802        // No operand predicates
13803        GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
13804        GIM_CheckOpcode, /*MI*/10, TargetOpcode::G_CONSTANT,
13805        GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
13806        // MIs[10] Operand 1
13807        // No operand predicates
13808        GIM_RecordInsn, /*DefineMI*/11, /*MI*/2, /*OpIdx*/9, // MIs[11]
13809        GIM_CheckOpcode, /*MI*/11, TargetOpcode::G_CONSTANT,
13810        GIM_CheckI64ImmPredicate, /*MI*/11, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
13811        // MIs[11] Operand 1
13812        // No operand predicates
13813        GIM_RecordInsn, /*DefineMI*/12, /*MI*/2, /*OpIdx*/10, // MIs[12]
13814        GIM_CheckOpcode, /*MI*/12, TargetOpcode::G_CONSTANT,
13815        GIM_CheckI64ImmPredicate, /*MI*/12, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
13816        // MIs[12] Operand 1
13817        // No operand predicates
13818        GIM_RecordInsn, /*DefineMI*/13, /*MI*/2, /*OpIdx*/11, // MIs[13]
13819        GIM_CheckOpcode, /*MI*/13, TargetOpcode::G_CONSTANT,
13820        GIM_CheckI64ImmPredicate, /*MI*/13, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
13821        // MIs[13] Operand 1
13822        // No operand predicates
13823        GIM_RecordInsn, /*DefineMI*/14, /*MI*/2, /*OpIdx*/12, // MIs[14]
13824        GIM_CheckOpcode, /*MI*/14, TargetOpcode::G_CONSTANT,
13825        GIM_CheckI64ImmPredicate, /*MI*/14, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
13826        // MIs[14] Operand 1
13827        // No operand predicates
13828        GIM_RecordInsn, /*DefineMI*/15, /*MI*/2, /*OpIdx*/13, // MIs[15]
13829        GIM_CheckOpcode, /*MI*/15, TargetOpcode::G_CONSTANT,
13830        GIM_CheckI64ImmPredicate, /*MI*/15, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
13831        // MIs[15] Operand 1
13832        // No operand predicates
13833        GIM_RecordInsn, /*DefineMI*/16, /*MI*/2, /*OpIdx*/14, // MIs[16]
13834        GIM_CheckOpcode, /*MI*/16, TargetOpcode::G_CONSTANT,
13835        GIM_CheckI64ImmPredicate, /*MI*/16, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
13836        // MIs[16] Operand 1
13837        // No operand predicates
13838        GIM_RecordInsn, /*DefineMI*/17, /*MI*/2, /*OpIdx*/15, // MIs[17]
13839        GIM_CheckOpcode, /*MI*/17, TargetOpcode::G_CONSTANT,
13840        GIM_CheckI64ImmPredicate, /*MI*/17, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
13841        // MIs[17] Operand 1
13842        // No operand predicates
13843        GIM_RecordInsn, /*DefineMI*/18, /*MI*/2, /*OpIdx*/16, // MIs[18]
13844        GIM_CheckOpcode, /*MI*/18, TargetOpcode::G_CONSTANT,
13845        GIM_CheckI64ImmPredicate, /*MI*/18, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
13846        // MIs[18] Operand 1
13847        // No operand predicates
13848        GIM_CheckIsSafeToFold, /*InsnID*/1,
13849        GIM_CheckIsSafeToFold, /*InsnID*/2,
13850        GIM_CheckIsSafeToFold, /*InsnID*/3,
13851        GIM_CheckIsSafeToFold, /*InsnID*/4,
13852        GIM_CheckIsSafeToFold, /*InsnID*/5,
13853        GIM_CheckIsSafeToFold, /*InsnID*/6,
13854        GIM_CheckIsSafeToFold, /*InsnID*/7,
13855        GIM_CheckIsSafeToFold, /*InsnID*/8,
13856        GIM_CheckIsSafeToFold, /*InsnID*/9,
13857        GIM_CheckIsSafeToFold, /*InsnID*/10,
13858        GIM_CheckIsSafeToFold, /*InsnID*/11,
13859        GIM_CheckIsSafeToFold, /*InsnID*/12,
13860        GIM_CheckIsSafeToFold, /*InsnID*/13,
13861        GIM_CheckIsSafeToFold, /*InsnID*/14,
13862        GIM_CheckIsSafeToFold, /*InsnID*/15,
13863        GIM_CheckIsSafeToFold, /*InsnID*/16,
13864        GIM_CheckIsSafeToFold, /*InsnID*/17,
13865        GIM_CheckIsSafeToFold, /*InsnID*/18,
13866        // (shl:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$wt, (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>)))  =>  (SLL_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
13867        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLL_B,
13868        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
13869        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws
13870        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
13871        GIR_EraseFromParent, /*InsnID*/0,
13872        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13873        // GIR_Coverage, 2023,
13874        GIR_Done,
13875      // Label 866: @33623
13876      GIM_Try, /*On fail goto*//*Label 867*/ 33642, // Rule ID 941 //
13877        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
13878        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
13879        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
13880        // (shl:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (SLL_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
13881        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SLL_B,
13882        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13883        // GIR_Coverage, 941,
13884        GIR_Done,
13885      // Label 867: @33642
13886      GIM_Reject,
13887    // Label 864: @33643
13888    GIM_Reject,
13889    // Label 842: @33644
13890    GIM_Reject,
13891    // Label 23: @33645
13892    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 874*/ 35397,
13893    /*GILLT_s32*//*Label 868*/ 33659,
13894    /*GILLT_s64*//*Label 869*/ 33912, 0,
13895    /*GILLT_v2s64*//*Label 870*/ 34046, 0,
13896    /*GILLT_v4s32*//*Label 871*/ 34078,
13897    /*GILLT_v8s16*//*Label 872*/ 34347,
13898    /*GILLT_v16s8*//*Label 873*/ 34744,
13899    // Label 868: @33659
13900    GIM_Try, /*On fail goto*//*Label 875*/ 33911,
13901      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
13902      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
13903      GIM_Try, /*On fail goto*//*Label 876*/ 33712, // Rule ID 56 //
13904        GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
13905        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
13906        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
13907        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
13908        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
13909        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
13910        // MIs[1] Operand 1
13911        // No operand predicates
13912        GIM_CheckIsSafeToFold, /*InsnID*/1,
13913        // (srl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shamt)  =>  (SRL:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$shamt)
13914        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRL,
13915        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
13916        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt
13917        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
13918        GIR_EraseFromParent, /*InsnID*/0,
13919        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13920        // GIR_Coverage, 56,
13921        GIR_Done,
13922      // Label 876: @33712
13923      GIM_Try, /*On fail goto*//*Label 877*/ 33755, // Rule ID 1786 //
13924        GIM_CheckFeatures, GIFBS_InMips16Mode,
13925        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
13926        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
13927        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
13928        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
13929        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
13930        // MIs[1] Operand 1
13931        // No operand predicates
13932        GIM_CheckIsSafeToFold, /*InsnID*/1,
13933        // (srl:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)  =>  (SrlX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
13934        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SrlX16,
13935        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rx
13936        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in
13937        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
13938        GIR_EraseFromParent, /*InsnID*/0,
13939        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13940        // GIR_Coverage, 1786,
13941        GIR_Done,
13942      // Label 877: @33755
13943      GIM_Try, /*On fail goto*//*Label 878*/ 33798, // Rule ID 2125 //
13944        GIM_CheckFeatures, GIFBS_InMicroMips,
13945        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
13946        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
13947        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
13948        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
13949        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt2Shift,
13950        // MIs[1] Operand 1
13951        // No operand predicates
13952        GIM_CheckIsSafeToFold, /*InsnID*/1,
13953        // (srl:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt2Shift>>:$imm)  =>  (SRL16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt2Shift>>:$imm)
13954        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRL16_MM,
13955        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
13956        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13957        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
13958        GIR_EraseFromParent, /*InsnID*/0,
13959        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13960        // GIR_Coverage, 2125,
13961        GIR_Done,
13962      // Label 878: @33798
13963      GIM_Try, /*On fail goto*//*Label 879*/ 33841, // Rule ID 2126 //
13964        GIM_CheckFeatures, GIFBS_InMicroMips,
13965        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
13966        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
13967        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
13968        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
13969        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
13970        // MIs[1] Operand 1
13971        // No operand predicates
13972        GIM_CheckIsSafeToFold, /*InsnID*/1,
13973        // (srl:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)  =>  (SRL_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
13974        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRL_MM,
13975        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
13976        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13977        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
13978        GIR_EraseFromParent, /*InsnID*/0,
13979        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13980        // GIR_Coverage, 2126,
13981        GIR_Done,
13982      // Label 879: @33841
13983      GIM_Try, /*On fail goto*//*Label 880*/ 33864, // Rule ID 59 //
13984        GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
13985        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
13986        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
13987        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
13988        // (srl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)  =>  (SRLV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
13989        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRLV,
13990        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13991        // GIR_Coverage, 59,
13992        GIR_Done,
13993      // Label 880: @33864
13994      GIM_Try, /*On fail goto*//*Label 881*/ 33887, // Rule ID 1790 //
13995        GIM_CheckFeatures, GIFBS_InMips16Mode,
13996        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
13997        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
13998        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
13999        // (srl:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra)  =>  (SrlvRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra)
14000        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SrlvRxRy16,
14001        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14002        // GIR_Coverage, 1790,
14003        GIR_Done,
14004      // Label 881: @33887
14005      GIM_Try, /*On fail goto*//*Label 882*/ 33910, // Rule ID 2127 //
14006        GIM_CheckFeatures, GIFBS_InMicroMips,
14007        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
14008        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
14009        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
14010        // (srl:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs)  =>  (SRLV_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs)
14011        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRLV_MM,
14012        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14013        // GIR_Coverage, 2127,
14014        GIR_Done,
14015      // Label 882: @33910
14016      GIM_Reject,
14017    // Label 875: @33911
14018    GIM_Reject,
14019    // Label 869: @33912
14020    GIM_Try, /*On fail goto*//*Label 883*/ 34045,
14021      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
14022      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
14023      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
14024      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
14025      GIM_Try, /*On fail goto*//*Label 884*/ 33965, // Rule ID 205 //
14026        GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_NotInMicroMips,
14027        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
14028        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
14029        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt6,
14030        // MIs[1] Operand 1
14031        // No operand predicates
14032        GIM_CheckIsSafeToFold, /*InsnID*/1,
14033        // (srl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$shamt)  =>  (DSRL:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$shamt)
14034        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSRL,
14035        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
14036        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt
14037        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
14038        GIR_EraseFromParent, /*InsnID*/0,
14039        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14040        // GIR_Coverage, 205,
14041        GIR_Done,
14042      // Label 884: @33965
14043      GIM_Try, /*On fail goto*//*Label 885*/ 34029, // Rule ID 1557 //
14044        GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit,
14045        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
14046        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC,
14047        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
14048        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
14049        GIM_CheckIsSafeToFold, /*InsnID*/1,
14050        // (srl:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$rs))  =>  (DSRLV:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$rs, sub_32:{ *:[i32] }))
14051        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
14052        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
14053        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
14054        GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/1, // rs
14055        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC GPR32*/8,
14056        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC GPR64*/38,
14057        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSRLV,
14058        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
14059        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt
14060        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
14061        GIR_EraseFromParent, /*InsnID*/0,
14062        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14063        // GIR_Coverage, 1557,
14064        GIR_Done,
14065      // Label 885: @34029
14066      GIM_Try, /*On fail goto*//*Label 886*/ 34044, // Rule ID 209 //
14067        GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_NotInMicroMips,
14068        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
14069        // (srl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)  =>  (DSRLV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
14070        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DSRLV,
14071        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14072        // GIR_Coverage, 209,
14073        GIR_Done,
14074      // Label 886: @34044
14075      GIM_Reject,
14076    // Label 883: @34045
14077    GIM_Reject,
14078    // Label 870: @34046
14079    GIM_Try, /*On fail goto*//*Label 887*/ 34077, // Rule ID 976 //
14080      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
14081      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
14082      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
14083      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
14084      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
14085      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
14086      // (srl:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (SRL_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
14087      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRL_D,
14088      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14089      // GIR_Coverage, 976,
14090      GIR_Done,
14091    // Label 887: @34077
14092    GIM_Reject,
14093    // Label 871: @34078
14094    GIM_Try, /*On fail goto*//*Label 888*/ 34346,
14095      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
14096      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
14097      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
14098      GIM_Try, /*On fail goto*//*Label 889*/ 34209, // Rule ID 2430 //
14099        GIM_CheckFeatures, GIFBS_HasMSA,
14100        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
14101        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
14102        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
14103        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
14104        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
14105        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR,
14106        GIM_CheckNumOperands, /*MI*/2, /*Expected*/5,
14107        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
14108        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
14109        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
14110        GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
14111        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
14112        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
14113        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_immi32Cst31,
14114        // MIs[3] Operand 1
14115        // No operand predicates
14116        GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
14117        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
14118        GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_immi32Cst31,
14119        // MIs[4] Operand 1
14120        // No operand predicates
14121        GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
14122        GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT,
14123        GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIPFP_I64_Predicate_immi32Cst31,
14124        // MIs[5] Operand 1
14125        // No operand predicates
14126        GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
14127        GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT,
14128        GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIPFP_I64_Predicate_immi32Cst31,
14129        // MIs[6] Operand 1
14130        // No operand predicates
14131        GIM_CheckIsSafeToFold, /*InsnID*/1,
14132        GIM_CheckIsSafeToFold, /*InsnID*/2,
14133        GIM_CheckIsSafeToFold, /*InsnID*/3,
14134        GIM_CheckIsSafeToFold, /*InsnID*/4,
14135        GIM_CheckIsSafeToFold, /*InsnID*/5,
14136        GIM_CheckIsSafeToFold, /*InsnID*/6,
14137        // (srl:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>), v4i32:{ *:[v4i32] }:$wt))  =>  (SRL_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
14138        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRL_W,
14139        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
14140        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws
14141        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
14142        GIR_EraseFromParent, /*InsnID*/0,
14143        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14144        // GIR_Coverage, 2430,
14145        GIR_Done,
14146      // Label 889: @34209
14147      GIM_Try, /*On fail goto*//*Label 890*/ 34326, // Rule ID 2033 //
14148        GIM_CheckFeatures, GIFBS_HasMSA,
14149        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
14150        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
14151        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
14152        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
14153        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
14154        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR,
14155        GIM_CheckNumOperands, /*MI*/2, /*Expected*/5,
14156        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
14157        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
14158        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
14159        GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
14160        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
14161        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
14162        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_immi32Cst31,
14163        // MIs[3] Operand 1
14164        // No operand predicates
14165        GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
14166        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
14167        GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_immi32Cst31,
14168        // MIs[4] Operand 1
14169        // No operand predicates
14170        GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
14171        GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT,
14172        GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIPFP_I64_Predicate_immi32Cst31,
14173        // MIs[5] Operand 1
14174        // No operand predicates
14175        GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
14176        GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT,
14177        GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIPFP_I64_Predicate_immi32Cst31,
14178        // MIs[6] Operand 1
14179        // No operand predicates
14180        GIM_CheckIsSafeToFold, /*InsnID*/1,
14181        GIM_CheckIsSafeToFold, /*InsnID*/2,
14182        GIM_CheckIsSafeToFold, /*InsnID*/3,
14183        GIM_CheckIsSafeToFold, /*InsnID*/4,
14184        GIM_CheckIsSafeToFold, /*InsnID*/5,
14185        GIM_CheckIsSafeToFold, /*InsnID*/6,
14186        // (srl:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$wt, (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>)))  =>  (SRL_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
14187        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRL_W,
14188        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
14189        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws
14190        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
14191        GIR_EraseFromParent, /*InsnID*/0,
14192        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14193        // GIR_Coverage, 2033,
14194        GIR_Done,
14195      // Label 890: @34326
14196      GIM_Try, /*On fail goto*//*Label 891*/ 34345, // Rule ID 975 //
14197        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
14198        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
14199        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
14200        // (srl:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (SRL_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
14201        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRL_W,
14202        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14203        // GIR_Coverage, 975,
14204        GIR_Done,
14205      // Label 891: @34345
14206      GIM_Reject,
14207    // Label 888: @34346
14208    GIM_Reject,
14209    // Label 872: @34347
14210    GIM_Try, /*On fail goto*//*Label 892*/ 34743,
14211      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
14212      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
14213      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
14214      GIM_Try, /*On fail goto*//*Label 893*/ 34542, // Rule ID 2429 //
14215        GIM_CheckFeatures, GIFBS_HasMSA,
14216        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
14217        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
14218        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
14219        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
14220        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
14221        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR,
14222        GIM_CheckNumOperands, /*MI*/2, /*Expected*/9,
14223        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
14224        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
14225        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
14226        GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
14227        GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
14228        GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
14229        GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
14230        GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
14231        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
14232        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
14233        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
14234        // MIs[3] Operand 1
14235        // No operand predicates
14236        GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
14237        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
14238        GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
14239        // MIs[4] Operand 1
14240        // No operand predicates
14241        GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
14242        GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT,
14243        GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
14244        // MIs[5] Operand 1
14245        // No operand predicates
14246        GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
14247        GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT,
14248        GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
14249        // MIs[6] Operand 1
14250        // No operand predicates
14251        GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
14252        GIM_CheckOpcode, /*MI*/7, TargetOpcode::G_CONSTANT,
14253        GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
14254        // MIs[7] Operand 1
14255        // No operand predicates
14256        GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
14257        GIM_CheckOpcode, /*MI*/8, TargetOpcode::G_CONSTANT,
14258        GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
14259        // MIs[8] Operand 1
14260        // No operand predicates
14261        GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
14262        GIM_CheckOpcode, /*MI*/9, TargetOpcode::G_CONSTANT,
14263        GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
14264        // MIs[9] Operand 1
14265        // No operand predicates
14266        GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
14267        GIM_CheckOpcode, /*MI*/10, TargetOpcode::G_CONSTANT,
14268        GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
14269        // MIs[10] Operand 1
14270        // No operand predicates
14271        GIM_CheckIsSafeToFold, /*InsnID*/1,
14272        GIM_CheckIsSafeToFold, /*InsnID*/2,
14273        GIM_CheckIsSafeToFold, /*InsnID*/3,
14274        GIM_CheckIsSafeToFold, /*InsnID*/4,
14275        GIM_CheckIsSafeToFold, /*InsnID*/5,
14276        GIM_CheckIsSafeToFold, /*InsnID*/6,
14277        GIM_CheckIsSafeToFold, /*InsnID*/7,
14278        GIM_CheckIsSafeToFold, /*InsnID*/8,
14279        GIM_CheckIsSafeToFold, /*InsnID*/9,
14280        GIM_CheckIsSafeToFold, /*InsnID*/10,
14281        // (srl:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>), v8i16:{ *:[v8i16] }:$wt))  =>  (SRL_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
14282        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRL_H,
14283        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
14284        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws
14285        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
14286        GIR_EraseFromParent, /*InsnID*/0,
14287        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14288        // GIR_Coverage, 2429,
14289        GIR_Done,
14290      // Label 893: @34542
14291      GIM_Try, /*On fail goto*//*Label 894*/ 34723, // Rule ID 2032 //
14292        GIM_CheckFeatures, GIFBS_HasMSA,
14293        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
14294        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
14295        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
14296        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
14297        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
14298        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR,
14299        GIM_CheckNumOperands, /*MI*/2, /*Expected*/9,
14300        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
14301        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
14302        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
14303        GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
14304        GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
14305        GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
14306        GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
14307        GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
14308        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
14309        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
14310        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
14311        // MIs[3] Operand 1
14312        // No operand predicates
14313        GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
14314        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
14315        GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
14316        // MIs[4] Operand 1
14317        // No operand predicates
14318        GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
14319        GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT,
14320        GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
14321        // MIs[5] Operand 1
14322        // No operand predicates
14323        GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
14324        GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT,
14325        GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
14326        // MIs[6] Operand 1
14327        // No operand predicates
14328        GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
14329        GIM_CheckOpcode, /*MI*/7, TargetOpcode::G_CONSTANT,
14330        GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
14331        // MIs[7] Operand 1
14332        // No operand predicates
14333        GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
14334        GIM_CheckOpcode, /*MI*/8, TargetOpcode::G_CONSTANT,
14335        GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
14336        // MIs[8] Operand 1
14337        // No operand predicates
14338        GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
14339        GIM_CheckOpcode, /*MI*/9, TargetOpcode::G_CONSTANT,
14340        GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
14341        // MIs[9] Operand 1
14342        // No operand predicates
14343        GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
14344        GIM_CheckOpcode, /*MI*/10, TargetOpcode::G_CONSTANT,
14345        GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
14346        // MIs[10] Operand 1
14347        // No operand predicates
14348        GIM_CheckIsSafeToFold, /*InsnID*/1,
14349        GIM_CheckIsSafeToFold, /*InsnID*/2,
14350        GIM_CheckIsSafeToFold, /*InsnID*/3,
14351        GIM_CheckIsSafeToFold, /*InsnID*/4,
14352        GIM_CheckIsSafeToFold, /*InsnID*/5,
14353        GIM_CheckIsSafeToFold, /*InsnID*/6,
14354        GIM_CheckIsSafeToFold, /*InsnID*/7,
14355        GIM_CheckIsSafeToFold, /*InsnID*/8,
14356        GIM_CheckIsSafeToFold, /*InsnID*/9,
14357        GIM_CheckIsSafeToFold, /*InsnID*/10,
14358        // (srl:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$wt, (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>)))  =>  (SRL_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
14359        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRL_H,
14360        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
14361        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws
14362        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
14363        GIR_EraseFromParent, /*InsnID*/0,
14364        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14365        // GIR_Coverage, 2032,
14366        GIR_Done,
14367      // Label 894: @34723
14368      GIM_Try, /*On fail goto*//*Label 895*/ 34742, // Rule ID 974 //
14369        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
14370        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
14371        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
14372        // (srl:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (SRL_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
14373        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRL_H,
14374        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14375        // GIR_Coverage, 974,
14376        GIR_Done,
14377      // Label 895: @34742
14378      GIM_Reject,
14379    // Label 892: @34743
14380    GIM_Reject,
14381    // Label 873: @34744
14382    GIM_Try, /*On fail goto*//*Label 896*/ 35396,
14383      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
14384      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
14385      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
14386      GIM_Try, /*On fail goto*//*Label 897*/ 35067, // Rule ID 2428 //
14387        GIM_CheckFeatures, GIFBS_HasMSA,
14388        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
14389        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
14390        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
14391        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
14392        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
14393        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR,
14394        GIM_CheckNumOperands, /*MI*/2, /*Expected*/17,
14395        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
14396        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
14397        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
14398        GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
14399        GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
14400        GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
14401        GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
14402        GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
14403        GIM_CheckType, /*MI*/2, /*Op*/9, /*Type*/GILLT_s32,
14404        GIM_CheckType, /*MI*/2, /*Op*/10, /*Type*/GILLT_s32,
14405        GIM_CheckType, /*MI*/2, /*Op*/11, /*Type*/GILLT_s32,
14406        GIM_CheckType, /*MI*/2, /*Op*/12, /*Type*/GILLT_s32,
14407        GIM_CheckType, /*MI*/2, /*Op*/13, /*Type*/GILLT_s32,
14408        GIM_CheckType, /*MI*/2, /*Op*/14, /*Type*/GILLT_s32,
14409        GIM_CheckType, /*MI*/2, /*Op*/15, /*Type*/GILLT_s32,
14410        GIM_CheckType, /*MI*/2, /*Op*/16, /*Type*/GILLT_s32,
14411        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
14412        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
14413        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
14414        // MIs[3] Operand 1
14415        // No operand predicates
14416        GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
14417        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
14418        GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
14419        // MIs[4] Operand 1
14420        // No operand predicates
14421        GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
14422        GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT,
14423        GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
14424        // MIs[5] Operand 1
14425        // No operand predicates
14426        GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
14427        GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT,
14428        GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
14429        // MIs[6] Operand 1
14430        // No operand predicates
14431        GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
14432        GIM_CheckOpcode, /*MI*/7, TargetOpcode::G_CONSTANT,
14433        GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
14434        // MIs[7] Operand 1
14435        // No operand predicates
14436        GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
14437        GIM_CheckOpcode, /*MI*/8, TargetOpcode::G_CONSTANT,
14438        GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
14439        // MIs[8] Operand 1
14440        // No operand predicates
14441        GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
14442        GIM_CheckOpcode, /*MI*/9, TargetOpcode::G_CONSTANT,
14443        GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
14444        // MIs[9] Operand 1
14445        // No operand predicates
14446        GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
14447        GIM_CheckOpcode, /*MI*/10, TargetOpcode::G_CONSTANT,
14448        GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
14449        // MIs[10] Operand 1
14450        // No operand predicates
14451        GIM_RecordInsn, /*DefineMI*/11, /*MI*/2, /*OpIdx*/9, // MIs[11]
14452        GIM_CheckOpcode, /*MI*/11, TargetOpcode::G_CONSTANT,
14453        GIM_CheckI64ImmPredicate, /*MI*/11, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
14454        // MIs[11] Operand 1
14455        // No operand predicates
14456        GIM_RecordInsn, /*DefineMI*/12, /*MI*/2, /*OpIdx*/10, // MIs[12]
14457        GIM_CheckOpcode, /*MI*/12, TargetOpcode::G_CONSTANT,
14458        GIM_CheckI64ImmPredicate, /*MI*/12, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
14459        // MIs[12] Operand 1
14460        // No operand predicates
14461        GIM_RecordInsn, /*DefineMI*/13, /*MI*/2, /*OpIdx*/11, // MIs[13]
14462        GIM_CheckOpcode, /*MI*/13, TargetOpcode::G_CONSTANT,
14463        GIM_CheckI64ImmPredicate, /*MI*/13, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
14464        // MIs[13] Operand 1
14465        // No operand predicates
14466        GIM_RecordInsn, /*DefineMI*/14, /*MI*/2, /*OpIdx*/12, // MIs[14]
14467        GIM_CheckOpcode, /*MI*/14, TargetOpcode::G_CONSTANT,
14468        GIM_CheckI64ImmPredicate, /*MI*/14, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
14469        // MIs[14] Operand 1
14470        // No operand predicates
14471        GIM_RecordInsn, /*DefineMI*/15, /*MI*/2, /*OpIdx*/13, // MIs[15]
14472        GIM_CheckOpcode, /*MI*/15, TargetOpcode::G_CONSTANT,
14473        GIM_CheckI64ImmPredicate, /*MI*/15, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
14474        // MIs[15] Operand 1
14475        // No operand predicates
14476        GIM_RecordInsn, /*DefineMI*/16, /*MI*/2, /*OpIdx*/14, // MIs[16]
14477        GIM_CheckOpcode, /*MI*/16, TargetOpcode::G_CONSTANT,
14478        GIM_CheckI64ImmPredicate, /*MI*/16, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
14479        // MIs[16] Operand 1
14480        // No operand predicates
14481        GIM_RecordInsn, /*DefineMI*/17, /*MI*/2, /*OpIdx*/15, // MIs[17]
14482        GIM_CheckOpcode, /*MI*/17, TargetOpcode::G_CONSTANT,
14483        GIM_CheckI64ImmPredicate, /*MI*/17, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
14484        // MIs[17] Operand 1
14485        // No operand predicates
14486        GIM_RecordInsn, /*DefineMI*/18, /*MI*/2, /*OpIdx*/16, // MIs[18]
14487        GIM_CheckOpcode, /*MI*/18, TargetOpcode::G_CONSTANT,
14488        GIM_CheckI64ImmPredicate, /*MI*/18, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
14489        // MIs[18] Operand 1
14490        // No operand predicates
14491        GIM_CheckIsSafeToFold, /*InsnID*/1,
14492        GIM_CheckIsSafeToFold, /*InsnID*/2,
14493        GIM_CheckIsSafeToFold, /*InsnID*/3,
14494        GIM_CheckIsSafeToFold, /*InsnID*/4,
14495        GIM_CheckIsSafeToFold, /*InsnID*/5,
14496        GIM_CheckIsSafeToFold, /*InsnID*/6,
14497        GIM_CheckIsSafeToFold, /*InsnID*/7,
14498        GIM_CheckIsSafeToFold, /*InsnID*/8,
14499        GIM_CheckIsSafeToFold, /*InsnID*/9,
14500        GIM_CheckIsSafeToFold, /*InsnID*/10,
14501        GIM_CheckIsSafeToFold, /*InsnID*/11,
14502        GIM_CheckIsSafeToFold, /*InsnID*/12,
14503        GIM_CheckIsSafeToFold, /*InsnID*/13,
14504        GIM_CheckIsSafeToFold, /*InsnID*/14,
14505        GIM_CheckIsSafeToFold, /*InsnID*/15,
14506        GIM_CheckIsSafeToFold, /*InsnID*/16,
14507        GIM_CheckIsSafeToFold, /*InsnID*/17,
14508        GIM_CheckIsSafeToFold, /*InsnID*/18,
14509        // (srl:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>), v16i8:{ *:[v16i8] }:$wt))  =>  (SRL_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
14510        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRL_B,
14511        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
14512        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws
14513        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
14514        GIR_EraseFromParent, /*InsnID*/0,
14515        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14516        // GIR_Coverage, 2428,
14517        GIR_Done,
14518      // Label 897: @35067
14519      GIM_Try, /*On fail goto*//*Label 898*/ 35376, // Rule ID 2031 //
14520        GIM_CheckFeatures, GIFBS_HasMSA,
14521        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
14522        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
14523        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
14524        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
14525        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
14526        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR,
14527        GIM_CheckNumOperands, /*MI*/2, /*Expected*/17,
14528        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
14529        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
14530        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
14531        GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
14532        GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
14533        GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
14534        GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
14535        GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
14536        GIM_CheckType, /*MI*/2, /*Op*/9, /*Type*/GILLT_s32,
14537        GIM_CheckType, /*MI*/2, /*Op*/10, /*Type*/GILLT_s32,
14538        GIM_CheckType, /*MI*/2, /*Op*/11, /*Type*/GILLT_s32,
14539        GIM_CheckType, /*MI*/2, /*Op*/12, /*Type*/GILLT_s32,
14540        GIM_CheckType, /*MI*/2, /*Op*/13, /*Type*/GILLT_s32,
14541        GIM_CheckType, /*MI*/2, /*Op*/14, /*Type*/GILLT_s32,
14542        GIM_CheckType, /*MI*/2, /*Op*/15, /*Type*/GILLT_s32,
14543        GIM_CheckType, /*MI*/2, /*Op*/16, /*Type*/GILLT_s32,
14544        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
14545        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
14546        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
14547        // MIs[3] Operand 1
14548        // No operand predicates
14549        GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
14550        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
14551        GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
14552        // MIs[4] Operand 1
14553        // No operand predicates
14554        GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
14555        GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT,
14556        GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
14557        // MIs[5] Operand 1
14558        // No operand predicates
14559        GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
14560        GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT,
14561        GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
14562        // MIs[6] Operand 1
14563        // No operand predicates
14564        GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
14565        GIM_CheckOpcode, /*MI*/7, TargetOpcode::G_CONSTANT,
14566        GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
14567        // MIs[7] Operand 1
14568        // No operand predicates
14569        GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
14570        GIM_CheckOpcode, /*MI*/8, TargetOpcode::G_CONSTANT,
14571        GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
14572        // MIs[8] Operand 1
14573        // No operand predicates
14574        GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
14575        GIM_CheckOpcode, /*MI*/9, TargetOpcode::G_CONSTANT,
14576        GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
14577        // MIs[9] Operand 1
14578        // No operand predicates
14579        GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
14580        GIM_CheckOpcode, /*MI*/10, TargetOpcode::G_CONSTANT,
14581        GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
14582        // MIs[10] Operand 1
14583        // No operand predicates
14584        GIM_RecordInsn, /*DefineMI*/11, /*MI*/2, /*OpIdx*/9, // MIs[11]
14585        GIM_CheckOpcode, /*MI*/11, TargetOpcode::G_CONSTANT,
14586        GIM_CheckI64ImmPredicate, /*MI*/11, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
14587        // MIs[11] Operand 1
14588        // No operand predicates
14589        GIM_RecordInsn, /*DefineMI*/12, /*MI*/2, /*OpIdx*/10, // MIs[12]
14590        GIM_CheckOpcode, /*MI*/12, TargetOpcode::G_CONSTANT,
14591        GIM_CheckI64ImmPredicate, /*MI*/12, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
14592        // MIs[12] Operand 1
14593        // No operand predicates
14594        GIM_RecordInsn, /*DefineMI*/13, /*MI*/2, /*OpIdx*/11, // MIs[13]
14595        GIM_CheckOpcode, /*MI*/13, TargetOpcode::G_CONSTANT,
14596        GIM_CheckI64ImmPredicate, /*MI*/13, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
14597        // MIs[13] Operand 1
14598        // No operand predicates
14599        GIM_RecordInsn, /*DefineMI*/14, /*MI*/2, /*OpIdx*/12, // MIs[14]
14600        GIM_CheckOpcode, /*MI*/14, TargetOpcode::G_CONSTANT,
14601        GIM_CheckI64ImmPredicate, /*MI*/14, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
14602        // MIs[14] Operand 1
14603        // No operand predicates
14604        GIM_RecordInsn, /*DefineMI*/15, /*MI*/2, /*OpIdx*/13, // MIs[15]
14605        GIM_CheckOpcode, /*MI*/15, TargetOpcode::G_CONSTANT,
14606        GIM_CheckI64ImmPredicate, /*MI*/15, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
14607        // MIs[15] Operand 1
14608        // No operand predicates
14609        GIM_RecordInsn, /*DefineMI*/16, /*MI*/2, /*OpIdx*/14, // MIs[16]
14610        GIM_CheckOpcode, /*MI*/16, TargetOpcode::G_CONSTANT,
14611        GIM_CheckI64ImmPredicate, /*MI*/16, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
14612        // MIs[16] Operand 1
14613        // No operand predicates
14614        GIM_RecordInsn, /*DefineMI*/17, /*MI*/2, /*OpIdx*/15, // MIs[17]
14615        GIM_CheckOpcode, /*MI*/17, TargetOpcode::G_CONSTANT,
14616        GIM_CheckI64ImmPredicate, /*MI*/17, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
14617        // MIs[17] Operand 1
14618        // No operand predicates
14619        GIM_RecordInsn, /*DefineMI*/18, /*MI*/2, /*OpIdx*/16, // MIs[18]
14620        GIM_CheckOpcode, /*MI*/18, TargetOpcode::G_CONSTANT,
14621        GIM_CheckI64ImmPredicate, /*MI*/18, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
14622        // MIs[18] Operand 1
14623        // No operand predicates
14624        GIM_CheckIsSafeToFold, /*InsnID*/1,
14625        GIM_CheckIsSafeToFold, /*InsnID*/2,
14626        GIM_CheckIsSafeToFold, /*InsnID*/3,
14627        GIM_CheckIsSafeToFold, /*InsnID*/4,
14628        GIM_CheckIsSafeToFold, /*InsnID*/5,
14629        GIM_CheckIsSafeToFold, /*InsnID*/6,
14630        GIM_CheckIsSafeToFold, /*InsnID*/7,
14631        GIM_CheckIsSafeToFold, /*InsnID*/8,
14632        GIM_CheckIsSafeToFold, /*InsnID*/9,
14633        GIM_CheckIsSafeToFold, /*InsnID*/10,
14634        GIM_CheckIsSafeToFold, /*InsnID*/11,
14635        GIM_CheckIsSafeToFold, /*InsnID*/12,
14636        GIM_CheckIsSafeToFold, /*InsnID*/13,
14637        GIM_CheckIsSafeToFold, /*InsnID*/14,
14638        GIM_CheckIsSafeToFold, /*InsnID*/15,
14639        GIM_CheckIsSafeToFold, /*InsnID*/16,
14640        GIM_CheckIsSafeToFold, /*InsnID*/17,
14641        GIM_CheckIsSafeToFold, /*InsnID*/18,
14642        // (srl:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$wt, (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>)))  =>  (SRL_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
14643        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRL_B,
14644        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
14645        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws
14646        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
14647        GIR_EraseFromParent, /*InsnID*/0,
14648        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14649        // GIR_Coverage, 2031,
14650        GIR_Done,
14651      // Label 898: @35376
14652      GIM_Try, /*On fail goto*//*Label 899*/ 35395, // Rule ID 973 //
14653        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
14654        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
14655        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
14656        // (srl:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (SRL_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
14657        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRL_B,
14658        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14659        // GIR_Coverage, 973,
14660        GIR_Done,
14661      // Label 899: @35395
14662      GIM_Reject,
14663    // Label 896: @35396
14664    GIM_Reject,
14665    // Label 874: @35397
14666    GIM_Reject,
14667    // Label 24: @35398
14668    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 906*/ 37107,
14669    /*GILLT_s32*//*Label 900*/ 35412,
14670    /*GILLT_s64*//*Label 901*/ 35622, 0,
14671    /*GILLT_v2s64*//*Label 902*/ 35756, 0,
14672    /*GILLT_v4s32*//*Label 903*/ 35788,
14673    /*GILLT_v8s16*//*Label 904*/ 36057,
14674    /*GILLT_v16s8*//*Label 905*/ 36454,
14675    // Label 900: @35412
14676    GIM_Try, /*On fail goto*//*Label 907*/ 35621,
14677      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
14678      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
14679      GIM_Try, /*On fail goto*//*Label 908*/ 35465, // Rule ID 57 //
14680        GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
14681        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
14682        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
14683        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
14684        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
14685        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
14686        // MIs[1] Operand 1
14687        // No operand predicates
14688        GIM_CheckIsSafeToFold, /*InsnID*/1,
14689        // (sra:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shamt)  =>  (SRA:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$shamt)
14690        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRA,
14691        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
14692        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt
14693        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
14694        GIR_EraseFromParent, /*InsnID*/0,
14695        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14696        // GIR_Coverage, 57,
14697        GIR_Done,
14698      // Label 908: @35465
14699      GIM_Try, /*On fail goto*//*Label 909*/ 35508, // Rule ID 1787 //
14700        GIM_CheckFeatures, GIFBS_InMips16Mode,
14701        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
14702        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
14703        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
14704        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
14705        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
14706        // MIs[1] Operand 1
14707        // No operand predicates
14708        GIM_CheckIsSafeToFold, /*InsnID*/1,
14709        // (sra:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)  =>  (SraX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
14710        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SraX16,
14711        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rx
14712        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in
14713        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
14714        GIR_EraseFromParent, /*InsnID*/0,
14715        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14716        // GIR_Coverage, 1787,
14717        GIR_Done,
14718      // Label 909: @35508
14719      GIM_Try, /*On fail goto*//*Label 910*/ 35551, // Rule ID 2128 //
14720        GIM_CheckFeatures, GIFBS_InMicroMips,
14721        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
14722        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
14723        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
14724        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
14725        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
14726        // MIs[1] Operand 1
14727        // No operand predicates
14728        GIM_CheckIsSafeToFold, /*InsnID*/1,
14729        // (sra:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)  =>  (SRA_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
14730        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRA_MM,
14731        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
14732        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
14733        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
14734        GIR_EraseFromParent, /*InsnID*/0,
14735        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14736        // GIR_Coverage, 2128,
14737        GIR_Done,
14738      // Label 910: @35551
14739      GIM_Try, /*On fail goto*//*Label 911*/ 35574, // Rule ID 60 //
14740        GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
14741        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
14742        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
14743        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
14744        // (sra:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)  =>  (SRAV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
14745        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRAV,
14746        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14747        // GIR_Coverage, 60,
14748        GIR_Done,
14749      // Label 911: @35574
14750      GIM_Try, /*On fail goto*//*Label 912*/ 35597, // Rule ID 1789 //
14751        GIM_CheckFeatures, GIFBS_InMips16Mode,
14752        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
14753        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
14754        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
14755        // (sra:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra)  =>  (SravRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra)
14756        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SravRxRy16,
14757        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14758        // GIR_Coverage, 1789,
14759        GIR_Done,
14760      // Label 912: @35597
14761      GIM_Try, /*On fail goto*//*Label 913*/ 35620, // Rule ID 2129 //
14762        GIM_CheckFeatures, GIFBS_InMicroMips,
14763        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
14764        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
14765        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
14766        // (sra:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs)  =>  (SRAV_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs)
14767        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRAV_MM,
14768        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14769        // GIR_Coverage, 2129,
14770        GIR_Done,
14771      // Label 913: @35620
14772      GIM_Reject,
14773    // Label 907: @35621
14774    GIM_Reject,
14775    // Label 901: @35622
14776    GIM_Try, /*On fail goto*//*Label 914*/ 35755,
14777      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
14778      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
14779      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
14780      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
14781      GIM_Try, /*On fail goto*//*Label 915*/ 35675, // Rule ID 206 //
14782        GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_NotInMicroMips,
14783        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
14784        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
14785        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt6,
14786        // MIs[1] Operand 1
14787        // No operand predicates
14788        GIM_CheckIsSafeToFold, /*InsnID*/1,
14789        // (sra:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$shamt)  =>  (DSRA:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$shamt)
14790        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSRA,
14791        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
14792        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt
14793        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
14794        GIR_EraseFromParent, /*InsnID*/0,
14795        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14796        // GIR_Coverage, 206,
14797        GIR_Done,
14798      // Label 915: @35675
14799      GIM_Try, /*On fail goto*//*Label 916*/ 35739, // Rule ID 1558 //
14800        GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit,
14801        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
14802        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC,
14803        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
14804        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
14805        GIM_CheckIsSafeToFold, /*InsnID*/1,
14806        // (sra:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$rs))  =>  (DSRAV:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$rs, sub_32:{ *:[i32] }))
14807        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
14808        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
14809        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
14810        GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/1, // rs
14811        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC GPR32*/8,
14812        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC GPR64*/38,
14813        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSRAV,
14814        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
14815        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt
14816        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
14817        GIR_EraseFromParent, /*InsnID*/0,
14818        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14819        // GIR_Coverage, 1558,
14820        GIR_Done,
14821      // Label 916: @35739
14822      GIM_Try, /*On fail goto*//*Label 917*/ 35754, // Rule ID 208 //
14823        GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_NotInMicroMips,
14824        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
14825        // (sra:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)  =>  (DSRAV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
14826        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DSRAV,
14827        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14828        // GIR_Coverage, 208,
14829        GIR_Done,
14830      // Label 917: @35754
14831      GIM_Reject,
14832    // Label 914: @35755
14833    GIM_Reject,
14834    // Label 902: @35756
14835    GIM_Try, /*On fail goto*//*Label 918*/ 35787, // Rule ID 960 //
14836      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
14837      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
14838      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
14839      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
14840      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
14841      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
14842      // (sra:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (SRA_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
14843      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRA_D,
14844      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14845      // GIR_Coverage, 960,
14846      GIR_Done,
14847    // Label 918: @35787
14848    GIM_Reject,
14849    // Label 903: @35788
14850    GIM_Try, /*On fail goto*//*Label 919*/ 36056,
14851      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
14852      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
14853      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
14854      GIM_Try, /*On fail goto*//*Label 920*/ 35919, // Rule ID 2434 //
14855        GIM_CheckFeatures, GIFBS_HasMSA,
14856        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
14857        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
14858        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
14859        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
14860        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
14861        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR,
14862        GIM_CheckNumOperands, /*MI*/2, /*Expected*/5,
14863        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
14864        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
14865        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
14866        GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
14867        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
14868        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
14869        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_immi32Cst31,
14870        // MIs[3] Operand 1
14871        // No operand predicates
14872        GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
14873        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
14874        GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_immi32Cst31,
14875        // MIs[4] Operand 1
14876        // No operand predicates
14877        GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
14878        GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT,
14879        GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIPFP_I64_Predicate_immi32Cst31,
14880        // MIs[5] Operand 1
14881        // No operand predicates
14882        GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
14883        GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT,
14884        GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIPFP_I64_Predicate_immi32Cst31,
14885        // MIs[6] Operand 1
14886        // No operand predicates
14887        GIM_CheckIsSafeToFold, /*InsnID*/1,
14888        GIM_CheckIsSafeToFold, /*InsnID*/2,
14889        GIM_CheckIsSafeToFold, /*InsnID*/3,
14890        GIM_CheckIsSafeToFold, /*InsnID*/4,
14891        GIM_CheckIsSafeToFold, /*InsnID*/5,
14892        GIM_CheckIsSafeToFold, /*InsnID*/6,
14893        // (sra:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>), v4i32:{ *:[v4i32] }:$wt))  =>  (SRA_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
14894        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRA_W,
14895        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
14896        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws
14897        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
14898        GIR_EraseFromParent, /*InsnID*/0,
14899        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14900        // GIR_Coverage, 2434,
14901        GIR_Done,
14902      // Label 920: @35919
14903      GIM_Try, /*On fail goto*//*Label 921*/ 36036, // Rule ID 2037 //
14904        GIM_CheckFeatures, GIFBS_HasMSA,
14905        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
14906        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
14907        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
14908        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
14909        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
14910        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR,
14911        GIM_CheckNumOperands, /*MI*/2, /*Expected*/5,
14912        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
14913        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
14914        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
14915        GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
14916        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
14917        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
14918        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_immi32Cst31,
14919        // MIs[3] Operand 1
14920        // No operand predicates
14921        GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
14922        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
14923        GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_immi32Cst31,
14924        // MIs[4] Operand 1
14925        // No operand predicates
14926        GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
14927        GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT,
14928        GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIPFP_I64_Predicate_immi32Cst31,
14929        // MIs[5] Operand 1
14930        // No operand predicates
14931        GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
14932        GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT,
14933        GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIPFP_I64_Predicate_immi32Cst31,
14934        // MIs[6] Operand 1
14935        // No operand predicates
14936        GIM_CheckIsSafeToFold, /*InsnID*/1,
14937        GIM_CheckIsSafeToFold, /*InsnID*/2,
14938        GIM_CheckIsSafeToFold, /*InsnID*/3,
14939        GIM_CheckIsSafeToFold, /*InsnID*/4,
14940        GIM_CheckIsSafeToFold, /*InsnID*/5,
14941        GIM_CheckIsSafeToFold, /*InsnID*/6,
14942        // (sra:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$wt, (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>)))  =>  (SRA_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
14943        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRA_W,
14944        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
14945        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws
14946        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
14947        GIR_EraseFromParent, /*InsnID*/0,
14948        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14949        // GIR_Coverage, 2037,
14950        GIR_Done,
14951      // Label 921: @36036
14952      GIM_Try, /*On fail goto*//*Label 922*/ 36055, // Rule ID 959 //
14953        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
14954        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
14955        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
14956        // (sra:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (SRA_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
14957        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRA_W,
14958        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14959        // GIR_Coverage, 959,
14960        GIR_Done,
14961      // Label 922: @36055
14962      GIM_Reject,
14963    // Label 919: @36056
14964    GIM_Reject,
14965    // Label 904: @36057
14966    GIM_Try, /*On fail goto*//*Label 923*/ 36453,
14967      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
14968      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
14969      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
14970      GIM_Try, /*On fail goto*//*Label 924*/ 36252, // Rule ID 2433 //
14971        GIM_CheckFeatures, GIFBS_HasMSA,
14972        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
14973        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
14974        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
14975        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
14976        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
14977        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR,
14978        GIM_CheckNumOperands, /*MI*/2, /*Expected*/9,
14979        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
14980        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
14981        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
14982        GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
14983        GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
14984        GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
14985        GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
14986        GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
14987        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
14988        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
14989        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
14990        // MIs[3] Operand 1
14991        // No operand predicates
14992        GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
14993        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
14994        GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
14995        // MIs[4] Operand 1
14996        // No operand predicates
14997        GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
14998        GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT,
14999        GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
15000        // MIs[5] Operand 1
15001        // No operand predicates
15002        GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
15003        GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT,
15004        GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
15005        // MIs[6] Operand 1
15006        // No operand predicates
15007        GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
15008        GIM_CheckOpcode, /*MI*/7, TargetOpcode::G_CONSTANT,
15009        GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
15010        // MIs[7] Operand 1
15011        // No operand predicates
15012        GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
15013        GIM_CheckOpcode, /*MI*/8, TargetOpcode::G_CONSTANT,
15014        GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
15015        // MIs[8] Operand 1
15016        // No operand predicates
15017        GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
15018        GIM_CheckOpcode, /*MI*/9, TargetOpcode::G_CONSTANT,
15019        GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
15020        // MIs[9] Operand 1
15021        // No operand predicates
15022        GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
15023        GIM_CheckOpcode, /*MI*/10, TargetOpcode::G_CONSTANT,
15024        GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
15025        // MIs[10] Operand 1
15026        // No operand predicates
15027        GIM_CheckIsSafeToFold, /*InsnID*/1,
15028        GIM_CheckIsSafeToFold, /*InsnID*/2,
15029        GIM_CheckIsSafeToFold, /*InsnID*/3,
15030        GIM_CheckIsSafeToFold, /*InsnID*/4,
15031        GIM_CheckIsSafeToFold, /*InsnID*/5,
15032        GIM_CheckIsSafeToFold, /*InsnID*/6,
15033        GIM_CheckIsSafeToFold, /*InsnID*/7,
15034        GIM_CheckIsSafeToFold, /*InsnID*/8,
15035        GIM_CheckIsSafeToFold, /*InsnID*/9,
15036        GIM_CheckIsSafeToFold, /*InsnID*/10,
15037        // (sra:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>), v8i16:{ *:[v8i16] }:$wt))  =>  (SRA_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
15038        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRA_H,
15039        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
15040        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws
15041        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
15042        GIR_EraseFromParent, /*InsnID*/0,
15043        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15044        // GIR_Coverage, 2433,
15045        GIR_Done,
15046      // Label 924: @36252
15047      GIM_Try, /*On fail goto*//*Label 925*/ 36433, // Rule ID 2036 //
15048        GIM_CheckFeatures, GIFBS_HasMSA,
15049        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15050        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
15051        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
15052        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
15053        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
15054        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR,
15055        GIM_CheckNumOperands, /*MI*/2, /*Expected*/9,
15056        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
15057        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
15058        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
15059        GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
15060        GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
15061        GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
15062        GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
15063        GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
15064        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
15065        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
15066        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
15067        // MIs[3] Operand 1
15068        // No operand predicates
15069        GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
15070        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
15071        GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
15072        // MIs[4] Operand 1
15073        // No operand predicates
15074        GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
15075        GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT,
15076        GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
15077        // MIs[5] Operand 1
15078        // No operand predicates
15079        GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
15080        GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT,
15081        GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
15082        // MIs[6] Operand 1
15083        // No operand predicates
15084        GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
15085        GIM_CheckOpcode, /*MI*/7, TargetOpcode::G_CONSTANT,
15086        GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
15087        // MIs[7] Operand 1
15088        // No operand predicates
15089        GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
15090        GIM_CheckOpcode, /*MI*/8, TargetOpcode::G_CONSTANT,
15091        GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
15092        // MIs[8] Operand 1
15093        // No operand predicates
15094        GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
15095        GIM_CheckOpcode, /*MI*/9, TargetOpcode::G_CONSTANT,
15096        GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
15097        // MIs[9] Operand 1
15098        // No operand predicates
15099        GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
15100        GIM_CheckOpcode, /*MI*/10, TargetOpcode::G_CONSTANT,
15101        GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
15102        // MIs[10] Operand 1
15103        // No operand predicates
15104        GIM_CheckIsSafeToFold, /*InsnID*/1,
15105        GIM_CheckIsSafeToFold, /*InsnID*/2,
15106        GIM_CheckIsSafeToFold, /*InsnID*/3,
15107        GIM_CheckIsSafeToFold, /*InsnID*/4,
15108        GIM_CheckIsSafeToFold, /*InsnID*/5,
15109        GIM_CheckIsSafeToFold, /*InsnID*/6,
15110        GIM_CheckIsSafeToFold, /*InsnID*/7,
15111        GIM_CheckIsSafeToFold, /*InsnID*/8,
15112        GIM_CheckIsSafeToFold, /*InsnID*/9,
15113        GIM_CheckIsSafeToFold, /*InsnID*/10,
15114        // (sra:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$wt, (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>)))  =>  (SRA_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
15115        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRA_H,
15116        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
15117        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws
15118        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
15119        GIR_EraseFromParent, /*InsnID*/0,
15120        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15121        // GIR_Coverage, 2036,
15122        GIR_Done,
15123      // Label 925: @36433
15124      GIM_Try, /*On fail goto*//*Label 926*/ 36452, // Rule ID 958 //
15125        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
15126        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
15127        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
15128        // (sra:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (SRA_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
15129        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRA_H,
15130        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15131        // GIR_Coverage, 958,
15132        GIR_Done,
15133      // Label 926: @36452
15134      GIM_Reject,
15135    // Label 923: @36453
15136    GIM_Reject,
15137    // Label 905: @36454
15138    GIM_Try, /*On fail goto*//*Label 927*/ 37106,
15139      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
15140      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
15141      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
15142      GIM_Try, /*On fail goto*//*Label 928*/ 36777, // Rule ID 2432 //
15143        GIM_CheckFeatures, GIFBS_HasMSA,
15144        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15145        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
15146        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
15147        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
15148        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
15149        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR,
15150        GIM_CheckNumOperands, /*MI*/2, /*Expected*/17,
15151        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
15152        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
15153        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
15154        GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
15155        GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
15156        GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
15157        GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
15158        GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
15159        GIM_CheckType, /*MI*/2, /*Op*/9, /*Type*/GILLT_s32,
15160        GIM_CheckType, /*MI*/2, /*Op*/10, /*Type*/GILLT_s32,
15161        GIM_CheckType, /*MI*/2, /*Op*/11, /*Type*/GILLT_s32,
15162        GIM_CheckType, /*MI*/2, /*Op*/12, /*Type*/GILLT_s32,
15163        GIM_CheckType, /*MI*/2, /*Op*/13, /*Type*/GILLT_s32,
15164        GIM_CheckType, /*MI*/2, /*Op*/14, /*Type*/GILLT_s32,
15165        GIM_CheckType, /*MI*/2, /*Op*/15, /*Type*/GILLT_s32,
15166        GIM_CheckType, /*MI*/2, /*Op*/16, /*Type*/GILLT_s32,
15167        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
15168        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
15169        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
15170        // MIs[3] Operand 1
15171        // No operand predicates
15172        GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
15173        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
15174        GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
15175        // MIs[4] Operand 1
15176        // No operand predicates
15177        GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
15178        GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT,
15179        GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
15180        // MIs[5] Operand 1
15181        // No operand predicates
15182        GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
15183        GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT,
15184        GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
15185        // MIs[6] Operand 1
15186        // No operand predicates
15187        GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
15188        GIM_CheckOpcode, /*MI*/7, TargetOpcode::G_CONSTANT,
15189        GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
15190        // MIs[7] Operand 1
15191        // No operand predicates
15192        GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
15193        GIM_CheckOpcode, /*MI*/8, TargetOpcode::G_CONSTANT,
15194        GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
15195        // MIs[8] Operand 1
15196        // No operand predicates
15197        GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
15198        GIM_CheckOpcode, /*MI*/9, TargetOpcode::G_CONSTANT,
15199        GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
15200        // MIs[9] Operand 1
15201        // No operand predicates
15202        GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
15203        GIM_CheckOpcode, /*MI*/10, TargetOpcode::G_CONSTANT,
15204        GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
15205        // MIs[10] Operand 1
15206        // No operand predicates
15207        GIM_RecordInsn, /*DefineMI*/11, /*MI*/2, /*OpIdx*/9, // MIs[11]
15208        GIM_CheckOpcode, /*MI*/11, TargetOpcode::G_CONSTANT,
15209        GIM_CheckI64ImmPredicate, /*MI*/11, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
15210        // MIs[11] Operand 1
15211        // No operand predicates
15212        GIM_RecordInsn, /*DefineMI*/12, /*MI*/2, /*OpIdx*/10, // MIs[12]
15213        GIM_CheckOpcode, /*MI*/12, TargetOpcode::G_CONSTANT,
15214        GIM_CheckI64ImmPredicate, /*MI*/12, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
15215        // MIs[12] Operand 1
15216        // No operand predicates
15217        GIM_RecordInsn, /*DefineMI*/13, /*MI*/2, /*OpIdx*/11, // MIs[13]
15218        GIM_CheckOpcode, /*MI*/13, TargetOpcode::G_CONSTANT,
15219        GIM_CheckI64ImmPredicate, /*MI*/13, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
15220        // MIs[13] Operand 1
15221        // No operand predicates
15222        GIM_RecordInsn, /*DefineMI*/14, /*MI*/2, /*OpIdx*/12, // MIs[14]
15223        GIM_CheckOpcode, /*MI*/14, TargetOpcode::G_CONSTANT,
15224        GIM_CheckI64ImmPredicate, /*MI*/14, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
15225        // MIs[14] Operand 1
15226        // No operand predicates
15227        GIM_RecordInsn, /*DefineMI*/15, /*MI*/2, /*OpIdx*/13, // MIs[15]
15228        GIM_CheckOpcode, /*MI*/15, TargetOpcode::G_CONSTANT,
15229        GIM_CheckI64ImmPredicate, /*MI*/15, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
15230        // MIs[15] Operand 1
15231        // No operand predicates
15232        GIM_RecordInsn, /*DefineMI*/16, /*MI*/2, /*OpIdx*/14, // MIs[16]
15233        GIM_CheckOpcode, /*MI*/16, TargetOpcode::G_CONSTANT,
15234        GIM_CheckI64ImmPredicate, /*MI*/16, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
15235        // MIs[16] Operand 1
15236        // No operand predicates
15237        GIM_RecordInsn, /*DefineMI*/17, /*MI*/2, /*OpIdx*/15, // MIs[17]
15238        GIM_CheckOpcode, /*MI*/17, TargetOpcode::G_CONSTANT,
15239        GIM_CheckI64ImmPredicate, /*MI*/17, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
15240        // MIs[17] Operand 1
15241        // No operand predicates
15242        GIM_RecordInsn, /*DefineMI*/18, /*MI*/2, /*OpIdx*/16, // MIs[18]
15243        GIM_CheckOpcode, /*MI*/18, TargetOpcode::G_CONSTANT,
15244        GIM_CheckI64ImmPredicate, /*MI*/18, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
15245        // MIs[18] Operand 1
15246        // No operand predicates
15247        GIM_CheckIsSafeToFold, /*InsnID*/1,
15248        GIM_CheckIsSafeToFold, /*InsnID*/2,
15249        GIM_CheckIsSafeToFold, /*InsnID*/3,
15250        GIM_CheckIsSafeToFold, /*InsnID*/4,
15251        GIM_CheckIsSafeToFold, /*InsnID*/5,
15252        GIM_CheckIsSafeToFold, /*InsnID*/6,
15253        GIM_CheckIsSafeToFold, /*InsnID*/7,
15254        GIM_CheckIsSafeToFold, /*InsnID*/8,
15255        GIM_CheckIsSafeToFold, /*InsnID*/9,
15256        GIM_CheckIsSafeToFold, /*InsnID*/10,
15257        GIM_CheckIsSafeToFold, /*InsnID*/11,
15258        GIM_CheckIsSafeToFold, /*InsnID*/12,
15259        GIM_CheckIsSafeToFold, /*InsnID*/13,
15260        GIM_CheckIsSafeToFold, /*InsnID*/14,
15261        GIM_CheckIsSafeToFold, /*InsnID*/15,
15262        GIM_CheckIsSafeToFold, /*InsnID*/16,
15263        GIM_CheckIsSafeToFold, /*InsnID*/17,
15264        GIM_CheckIsSafeToFold, /*InsnID*/18,
15265        // (sra:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>), v16i8:{ *:[v16i8] }:$wt))  =>  (SRA_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
15266        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRA_B,
15267        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
15268        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws
15269        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
15270        GIR_EraseFromParent, /*InsnID*/0,
15271        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15272        // GIR_Coverage, 2432,
15273        GIR_Done,
15274      // Label 928: @36777
15275      GIM_Try, /*On fail goto*//*Label 929*/ 37086, // Rule ID 2035 //
15276        GIM_CheckFeatures, GIFBS_HasMSA,
15277        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15278        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
15279        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
15280        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
15281        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
15282        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR,
15283        GIM_CheckNumOperands, /*MI*/2, /*Expected*/17,
15284        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
15285        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
15286        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
15287        GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
15288        GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
15289        GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
15290        GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
15291        GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
15292        GIM_CheckType, /*MI*/2, /*Op*/9, /*Type*/GILLT_s32,
15293        GIM_CheckType, /*MI*/2, /*Op*/10, /*Type*/GILLT_s32,
15294        GIM_CheckType, /*MI*/2, /*Op*/11, /*Type*/GILLT_s32,
15295        GIM_CheckType, /*MI*/2, /*Op*/12, /*Type*/GILLT_s32,
15296        GIM_CheckType, /*MI*/2, /*Op*/13, /*Type*/GILLT_s32,
15297        GIM_CheckType, /*MI*/2, /*Op*/14, /*Type*/GILLT_s32,
15298        GIM_CheckType, /*MI*/2, /*Op*/15, /*Type*/GILLT_s32,
15299        GIM_CheckType, /*MI*/2, /*Op*/16, /*Type*/GILLT_s32,
15300        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
15301        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
15302        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
15303        // MIs[3] Operand 1
15304        // No operand predicates
15305        GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
15306        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
15307        GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
15308        // MIs[4] Operand 1
15309        // No operand predicates
15310        GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
15311        GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT,
15312        GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
15313        // MIs[5] Operand 1
15314        // No operand predicates
15315        GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
15316        GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT,
15317        GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
15318        // MIs[6] Operand 1
15319        // No operand predicates
15320        GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
15321        GIM_CheckOpcode, /*MI*/7, TargetOpcode::G_CONSTANT,
15322        GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
15323        // MIs[7] Operand 1
15324        // No operand predicates
15325        GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
15326        GIM_CheckOpcode, /*MI*/8, TargetOpcode::G_CONSTANT,
15327        GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
15328        // MIs[8] Operand 1
15329        // No operand predicates
15330        GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
15331        GIM_CheckOpcode, /*MI*/9, TargetOpcode::G_CONSTANT,
15332        GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
15333        // MIs[9] Operand 1
15334        // No operand predicates
15335        GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
15336        GIM_CheckOpcode, /*MI*/10, TargetOpcode::G_CONSTANT,
15337        GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
15338        // MIs[10] Operand 1
15339        // No operand predicates
15340        GIM_RecordInsn, /*DefineMI*/11, /*MI*/2, /*OpIdx*/9, // MIs[11]
15341        GIM_CheckOpcode, /*MI*/11, TargetOpcode::G_CONSTANT,
15342        GIM_CheckI64ImmPredicate, /*MI*/11, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
15343        // MIs[11] Operand 1
15344        // No operand predicates
15345        GIM_RecordInsn, /*DefineMI*/12, /*MI*/2, /*OpIdx*/10, // MIs[12]
15346        GIM_CheckOpcode, /*MI*/12, TargetOpcode::G_CONSTANT,
15347        GIM_CheckI64ImmPredicate, /*MI*/12, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
15348        // MIs[12] Operand 1
15349        // No operand predicates
15350        GIM_RecordInsn, /*DefineMI*/13, /*MI*/2, /*OpIdx*/11, // MIs[13]
15351        GIM_CheckOpcode, /*MI*/13, TargetOpcode::G_CONSTANT,
15352        GIM_CheckI64ImmPredicate, /*MI*/13, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
15353        // MIs[13] Operand 1
15354        // No operand predicates
15355        GIM_RecordInsn, /*DefineMI*/14, /*MI*/2, /*OpIdx*/12, // MIs[14]
15356        GIM_CheckOpcode, /*MI*/14, TargetOpcode::G_CONSTANT,
15357        GIM_CheckI64ImmPredicate, /*MI*/14, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
15358        // MIs[14] Operand 1
15359        // No operand predicates
15360        GIM_RecordInsn, /*DefineMI*/15, /*MI*/2, /*OpIdx*/13, // MIs[15]
15361        GIM_CheckOpcode, /*MI*/15, TargetOpcode::G_CONSTANT,
15362        GIM_CheckI64ImmPredicate, /*MI*/15, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
15363        // MIs[15] Operand 1
15364        // No operand predicates
15365        GIM_RecordInsn, /*DefineMI*/16, /*MI*/2, /*OpIdx*/14, // MIs[16]
15366        GIM_CheckOpcode, /*MI*/16, TargetOpcode::G_CONSTANT,
15367        GIM_CheckI64ImmPredicate, /*MI*/16, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
15368        // MIs[16] Operand 1
15369        // No operand predicates
15370        GIM_RecordInsn, /*DefineMI*/17, /*MI*/2, /*OpIdx*/15, // MIs[17]
15371        GIM_CheckOpcode, /*MI*/17, TargetOpcode::G_CONSTANT,
15372        GIM_CheckI64ImmPredicate, /*MI*/17, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
15373        // MIs[17] Operand 1
15374        // No operand predicates
15375        GIM_RecordInsn, /*DefineMI*/18, /*MI*/2, /*OpIdx*/16, // MIs[18]
15376        GIM_CheckOpcode, /*MI*/18, TargetOpcode::G_CONSTANT,
15377        GIM_CheckI64ImmPredicate, /*MI*/18, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
15378        // MIs[18] Operand 1
15379        // No operand predicates
15380        GIM_CheckIsSafeToFold, /*InsnID*/1,
15381        GIM_CheckIsSafeToFold, /*InsnID*/2,
15382        GIM_CheckIsSafeToFold, /*InsnID*/3,
15383        GIM_CheckIsSafeToFold, /*InsnID*/4,
15384        GIM_CheckIsSafeToFold, /*InsnID*/5,
15385        GIM_CheckIsSafeToFold, /*InsnID*/6,
15386        GIM_CheckIsSafeToFold, /*InsnID*/7,
15387        GIM_CheckIsSafeToFold, /*InsnID*/8,
15388        GIM_CheckIsSafeToFold, /*InsnID*/9,
15389        GIM_CheckIsSafeToFold, /*InsnID*/10,
15390        GIM_CheckIsSafeToFold, /*InsnID*/11,
15391        GIM_CheckIsSafeToFold, /*InsnID*/12,
15392        GIM_CheckIsSafeToFold, /*InsnID*/13,
15393        GIM_CheckIsSafeToFold, /*InsnID*/14,
15394        GIM_CheckIsSafeToFold, /*InsnID*/15,
15395        GIM_CheckIsSafeToFold, /*InsnID*/16,
15396        GIM_CheckIsSafeToFold, /*InsnID*/17,
15397        GIM_CheckIsSafeToFold, /*InsnID*/18,
15398        // (sra:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$wt, (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>)))  =>  (SRA_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
15399        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRA_B,
15400        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
15401        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws
15402        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
15403        GIR_EraseFromParent, /*InsnID*/0,
15404        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15405        // GIR_Coverage, 2035,
15406        GIR_Done,
15407      // Label 929: @37086
15408      GIM_Try, /*On fail goto*//*Label 930*/ 37105, // Rule ID 957 //
15409        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
15410        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
15411        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
15412        // (sra:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (SRA_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
15413        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRA_B,
15414        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15415        // GIR_Coverage, 957,
15416        GIR_Done,
15417      // Label 930: @37105
15418      GIM_Reject,
15419    // Label 927: @37106
15420    GIM_Reject,
15421    // Label 906: @37107
15422    GIM_Reject,
15423    // Label 25: @37108
15424    GIM_Try, /*On fail goto*//*Label 931*/ 39611,
15425      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
15426      GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/1, 3, /*)*//*default:*//*Label 934*/ 37288,
15427      /*GILLT_s32*//*Label 932*/ 37122,
15428      /*GILLT_s64*//*Label 933*/ 37205,
15429      // Label 932: @37122
15430      GIM_Try, /*On fail goto*//*Label 935*/ 37204,
15431        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
15432        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
15433        GIM_Try, /*On fail goto*//*Label 936*/ 37167, // Rule ID 1397 //
15434          GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
15435          // MIs[0] Operand 1
15436          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
15437          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
15438          GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
15439          // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] })  =>  (SLTiu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 1:{ *:[i32] })
15440          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTiu,
15441          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
15442          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // lhs
15443          GIR_AddImm, /*InsnID*/0, /*Imm*/1,
15444          GIR_EraseFromParent, /*InsnID*/0,
15445          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15446          // GIR_Coverage, 1397,
15447          GIR_Done,
15448        // Label 936: @37167
15449        GIM_Try, /*On fail goto*//*Label 937*/ 37203, // Rule ID 1398 //
15450          GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
15451          // MIs[0] Operand 1
15452          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
15453          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
15454          GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
15455          // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] })  =>  (SLTu:{ *:[i32] } ZERO:{ *:[i32] }, GPR32:{ *:[i32] }:$lhs)
15456          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTu,
15457          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
15458          GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0,
15459          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // lhs
15460          GIR_EraseFromParent, /*InsnID*/0,
15461          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15462          // GIR_Coverage, 1398,
15463          GIR_Done,
15464        // Label 937: @37203
15465        GIM_Reject,
15466      // Label 935: @37204
15467      GIM_Reject,
15468      // Label 933: @37205
15469      GIM_Try, /*On fail goto*//*Label 938*/ 37287,
15470        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
15471        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
15472        GIM_Try, /*On fail goto*//*Label 939*/ 37250, // Rule ID 1541 //
15473          GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips,
15474          // MIs[0] Operand 1
15475          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
15476          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
15477          GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
15478          // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] })  =>  (SLTiu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 1:{ *:[i64] })
15479          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTiu64,
15480          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
15481          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // lhs
15482          GIR_AddImm, /*InsnID*/0, /*Imm*/1,
15483          GIR_EraseFromParent, /*InsnID*/0,
15484          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15485          // GIR_Coverage, 1541,
15486          GIR_Done,
15487        // Label 939: @37250
15488        GIM_Try, /*On fail goto*//*Label 940*/ 37286, // Rule ID 1542 //
15489          GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips,
15490          // MIs[0] Operand 1
15491          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
15492          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
15493          GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
15494          // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] })  =>  (SLTu64:{ *:[i32] } ZERO_64:{ *:[i64] }, GPR64:{ *:[i64] }:$lhs)
15495          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTu64,
15496          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
15497          GIR_AddRegister, /*InsnID*/0, Mips::ZERO_64, /*AddRegisterRegFlags*/0,
15498          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // lhs
15499          GIR_EraseFromParent, /*InsnID*/0,
15500          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15501          // GIR_Coverage, 1542,
15502          GIR_Done,
15503        // Label 940: @37286
15504        GIM_Reject,
15505      // Label 938: @37287
15506      GIM_Reject,
15507      // Label 934: @37288
15508      GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/1, 3, /*)*//*default:*//*Label 943*/ 37660,
15509      /*GILLT_s32*//*Label 941*/ 37296,
15510      /*GILLT_s64*//*Label 942*/ 37576,
15511      // Label 941: @37296
15512      GIM_Try, /*On fail goto*//*Label 944*/ 37575,
15513        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
15514        GIM_Try, /*On fail goto*//*Label 945*/ 37341, // Rule ID 1837 //
15515          GIM_CheckFeatures, GIFBS_InMips16Mode,
15516          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
15517          // MIs[0] Operand 1
15518          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
15519          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
15520          GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
15521          // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] })  =>  (SltiuCCRxImmX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, 1:{ *:[i32] })
15522          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SltiuCCRxImmX16,
15523          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // cc
15524          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // lhs
15525          GIR_AddImm, /*InsnID*/0, /*Imm*/1,
15526          GIR_EraseFromParent, /*InsnID*/0,
15527          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15528          // GIR_Coverage, 1837,
15529          GIR_Done,
15530        // Label 945: @37341
15531        GIM_Try, /*On fail goto*//*Label 946*/ 37415, // Rule ID 1839 //
15532          GIM_CheckFeatures, GIFBS_InMips16Mode,
15533          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
15534          // MIs[0] Operand 1
15535          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT,
15536          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
15537          GIM_CheckConstantInt, /*MI*/0, /*Op*/3, -32769,
15538          // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, -32769:{ *:[i32] }, SETGT:{ *:[Other] })  =>  (XorRxRxRy16:{ *:[i32] } (SltiCCRxImmX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, -32768:{ *:[i32] }), (LiRxImmX16:{ *:[i32] } 1:{ *:[i32] }))
15539          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
15540          GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
15541          GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::LiRxImmX16,
15542          GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
15543          GIR_AddImm, /*InsnID*/2, /*Imm*/1,
15544          GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
15545          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SltiCCRxImmX16,
15546          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
15547          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
15548          GIR_AddImm, /*InsnID*/1, /*Imm*/-32768,
15549          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15550          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XorRxRxRy16,
15551          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rz
15552          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
15553          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
15554          GIR_EraseFromParent, /*InsnID*/0,
15555          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15556          // GIR_Coverage, 1839,
15557          GIR_Done,
15558        // Label 946: @37415
15559        GIM_Try, /*On fail goto*//*Label 947*/ 37454, // Rule ID 2156 //
15560          GIM_CheckFeatures, GIFBS_InMicroMips,
15561          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
15562          // MIs[0] Operand 1
15563          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
15564          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
15565          GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
15566          // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] })  =>  (SLTiu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 1:{ *:[i32] })
15567          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTiu_MM,
15568          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
15569          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // lhs
15570          GIR_AddImm, /*InsnID*/0, /*Imm*/1,
15571          GIR_EraseFromParent, /*InsnID*/0,
15572          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15573          // GIR_Coverage, 2156,
15574          GIR_Done,
15575        // Label 947: @37454
15576        GIM_Try, /*On fail goto*//*Label 948*/ 37494, // Rule ID 2157 //
15577          GIM_CheckFeatures, GIFBS_InMicroMips,
15578          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
15579          // MIs[0] Operand 1
15580          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
15581          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
15582          GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
15583          // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] })  =>  (SLTu_MM:{ *:[i32] } ZERO:{ *:[i32] }, GPR32:{ *:[i32] }:$lhs)
15584          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTu_MM,
15585          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
15586          GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0,
15587          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // lhs
15588          GIR_EraseFromParent, /*InsnID*/0,
15589          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15590          // GIR_Coverage, 2157,
15591          GIR_Done,
15592        // Label 948: @37494
15593        GIM_Try, /*On fail goto*//*Label 949*/ 37534, // Rule ID 49 //
15594          GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
15595          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
15596          // MIs[0] Operand 1
15597          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT,
15598          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
15599          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
15600          // (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETLT:{ *:[Other] })  =>  (SLT:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
15601          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLT,
15602          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
15603          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
15604          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
15605          GIR_EraseFromParent, /*InsnID*/0,
15606          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15607          // GIR_Coverage, 49,
15608          GIR_Done,
15609        // Label 949: @37534
15610        GIM_Try, /*On fail goto*//*Label 950*/ 37574, // Rule ID 50 //
15611          GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
15612          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
15613          // MIs[0] Operand 1
15614          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT,
15615          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
15616          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
15617          // (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETULT:{ *:[Other] })  =>  (SLTu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
15618          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTu,
15619          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
15620          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
15621          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
15622          GIR_EraseFromParent, /*InsnID*/0,
15623          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15624          // GIR_Coverage, 50,
15625          GIR_Done,
15626        // Label 950: @37574
15627        GIM_Reject,
15628      // Label 944: @37575
15629      GIM_Reject,
15630      // Label 942: @37576
15631      GIM_Try, /*On fail goto*//*Label 951*/ 37659,
15632        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
15633        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
15634        GIM_Try, /*On fail goto*//*Label 952*/ 37622, // Rule ID 198 //
15635          GIM_CheckFeatures, GIFBS_IsGP64bit_NotInMips16Mode,
15636          // MIs[0] Operand 1
15637          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT,
15638          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
15639          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
15640          // (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, SETLT:{ *:[Other] })  =>  (SLT64:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
15641          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLT64,
15642          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
15643          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
15644          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
15645          GIR_EraseFromParent, /*InsnID*/0,
15646          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15647          // GIR_Coverage, 198,
15648          GIR_Done,
15649        // Label 952: @37622
15650        GIM_Try, /*On fail goto*//*Label 953*/ 37658, // Rule ID 199 //
15651          GIM_CheckFeatures, GIFBS_IsGP64bit_NotInMips16Mode,
15652          // MIs[0] Operand 1
15653          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT,
15654          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
15655          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
15656          // (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, SETULT:{ *:[Other] })  =>  (SLTu64:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
15657          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTu64,
15658          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
15659          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
15660          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
15661          GIR_EraseFromParent, /*InsnID*/0,
15662          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15663          // GIR_Coverage, 199,
15664          GIR_Done,
15665        // Label 953: @37658
15666        GIM_Reject,
15667      // Label 951: @37659
15668      GIM_Reject,
15669      // Label 943: @37660
15670      GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/1, 3, /*)*//*default:*//*Label 956*/ 38570,
15671      /*GILLT_s32*//*Label 954*/ 37668,
15672      /*GILLT_s64*//*Label 955*/ 38155,
15673      // Label 954: @37668
15674      GIM_Try, /*On fail goto*//*Label 957*/ 38154,
15675        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
15676        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
15677        GIM_Try, /*On fail goto*//*Label 958*/ 37714, // Rule ID 1059 //
15678          GIM_CheckFeatures, GIFBS_InMicroMips,
15679          // MIs[0] Operand 1
15680          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT,
15681          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
15682          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
15683          // (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETLT:{ *:[Other] })  =>  (SLT_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
15684          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLT_MM,
15685          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
15686          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
15687          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
15688          GIR_EraseFromParent, /*InsnID*/0,
15689          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15690          // GIR_Coverage, 1059,
15691          GIR_Done,
15692        // Label 958: @37714
15693        GIM_Try, /*On fail goto*//*Label 959*/ 37750, // Rule ID 1060 //
15694          GIM_CheckFeatures, GIFBS_InMicroMips,
15695          // MIs[0] Operand 1
15696          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT,
15697          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
15698          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
15699          // (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETULT:{ *:[Other] })  =>  (SLTu_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
15700          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTu_MM,
15701          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
15702          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
15703          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
15704          GIR_EraseFromParent, /*InsnID*/0,
15705          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15706          // GIR_Coverage, 1060,
15707          GIR_Done,
15708        // Label 959: @37750
15709        GIM_Try, /*On fail goto*//*Label 960*/ 37805, // Rule ID 1399 //
15710          GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
15711          // MIs[0] Operand 1
15712          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
15713          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
15714          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
15715          // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] })  =>  (SLTiu:{ *:[i32] } (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] })
15716          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
15717          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR,
15718          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
15719          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
15720          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
15721          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15722          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTiu,
15723          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
15724          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
15725          GIR_AddImm, /*InsnID*/0, /*Imm*/1,
15726          GIR_EraseFromParent, /*InsnID*/0,
15727          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15728          // GIR_Coverage, 1399,
15729          GIR_Done,
15730        // Label 960: @37805
15731        GIM_Try, /*On fail goto*//*Label 961*/ 37861, // Rule ID 1400 //
15732          GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
15733          // MIs[0] Operand 1
15734          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
15735          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
15736          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
15737          // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] })  =>  (SLTu:{ *:[i32] } ZERO:{ *:[i32] }, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs))
15738          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
15739          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR,
15740          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
15741          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
15742          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
15743          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15744          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTu,
15745          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
15746          GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0,
15747          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
15748          GIR_EraseFromParent, /*InsnID*/0,
15749          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15750          // GIR_Coverage, 1400,
15751          GIR_Done,
15752        // Label 961: @37861
15753        GIM_Try, /*On fail goto*//*Label 962*/ 37916, // Rule ID 1401 //
15754          GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
15755          // MIs[0] Operand 1
15756          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
15757          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
15758          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
15759          // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] })  =>  (XORi:{ *:[i32] } (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), 1:{ *:[i32] })
15760          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
15761          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT,
15762          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
15763          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
15764          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
15765          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15766          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi,
15767          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
15768          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
15769          GIR_AddImm, /*InsnID*/0, /*Imm*/1,
15770          GIR_EraseFromParent, /*InsnID*/0,
15771          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15772          // GIR_Coverage, 1401,
15773          GIR_Done,
15774        // Label 962: @37916
15775        GIM_Try, /*On fail goto*//*Label 963*/ 37971, // Rule ID 1402 //
15776          GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
15777          // MIs[0] Operand 1
15778          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
15779          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
15780          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
15781          // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] })  =>  (XORi:{ *:[i32] } (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), 1:{ *:[i32] })
15782          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
15783          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu,
15784          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
15785          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
15786          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
15787          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15788          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi,
15789          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
15790          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
15791          GIR_AddImm, /*InsnID*/0, /*Imm*/1,
15792          GIR_EraseFromParent, /*InsnID*/0,
15793          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15794          // GIR_Coverage, 1402,
15795          GIR_Done,
15796        // Label 963: @37971
15797        GIM_Try, /*On fail goto*//*Label 964*/ 38007, // Rule ID 1403 //
15798          GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
15799          // MIs[0] Operand 1
15800          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT,
15801          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
15802          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
15803          // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGT:{ *:[Other] })  =>  (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs)
15804          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLT,
15805          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
15806          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rhs
15807          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // lhs
15808          GIR_EraseFromParent, /*InsnID*/0,
15809          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15810          // GIR_Coverage, 1403,
15811          GIR_Done,
15812        // Label 964: @38007
15813        GIM_Try, /*On fail goto*//*Label 965*/ 38043, // Rule ID 1404 //
15814          GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
15815          // MIs[0] Operand 1
15816          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT,
15817          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
15818          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
15819          // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGT:{ *:[Other] })  =>  (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs)
15820          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTu,
15821          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
15822          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rhs
15823          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // lhs
15824          GIR_EraseFromParent, /*InsnID*/0,
15825          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15826          // GIR_Coverage, 1404,
15827          GIR_Done,
15828        // Label 965: @38043
15829        GIM_Try, /*On fail goto*//*Label 966*/ 38098, // Rule ID 1405 //
15830          GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
15831          // MIs[0] Operand 1
15832          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
15833          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
15834          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
15835          // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] })  =>  (XORi:{ *:[i32] } (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] })
15836          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
15837          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT,
15838          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
15839          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
15840          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
15841          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15842          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi,
15843          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
15844          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
15845          GIR_AddImm, /*InsnID*/0, /*Imm*/1,
15846          GIR_EraseFromParent, /*InsnID*/0,
15847          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15848          // GIR_Coverage, 1405,
15849          GIR_Done,
15850        // Label 966: @38098
15851        GIM_Try, /*On fail goto*//*Label 967*/ 38153, // Rule ID 1406 //
15852          GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
15853          // MIs[0] Operand 1
15854          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
15855          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
15856          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
15857          // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] })  =>  (XORi:{ *:[i32] } (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] })
15858          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
15859          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu,
15860          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
15861          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
15862          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
15863          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15864          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi,
15865          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
15866          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
15867          GIR_AddImm, /*InsnID*/0, /*Imm*/1,
15868          GIR_EraseFromParent, /*InsnID*/0,
15869          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15870          // GIR_Coverage, 1406,
15871          GIR_Done,
15872        // Label 967: @38153
15873        GIM_Reject,
15874      // Label 957: @38154
15875      GIM_Reject,
15876      // Label 955: @38155
15877      GIM_Try, /*On fail goto*//*Label 968*/ 38569,
15878        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
15879        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
15880        GIM_Try, /*On fail goto*//*Label 969*/ 38220, // Rule ID 1543 //
15881          GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips,
15882          // MIs[0] Operand 1
15883          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
15884          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
15885          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
15886          // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETEQ:{ *:[Other] })  =>  (SLTiu64:{ *:[i32] } (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), 1:{ *:[i64] })
15887          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
15888          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR64,
15889          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
15890          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
15891          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
15892          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15893          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTiu64,
15894          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
15895          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
15896          GIR_AddImm, /*InsnID*/0, /*Imm*/1,
15897          GIR_EraseFromParent, /*InsnID*/0,
15898          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15899          // GIR_Coverage, 1543,
15900          GIR_Done,
15901        // Label 969: @38220
15902        GIM_Try, /*On fail goto*//*Label 970*/ 38276, // Rule ID 1544 //
15903          GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips,
15904          // MIs[0] Operand 1
15905          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
15906          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
15907          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
15908          // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETNE:{ *:[Other] })  =>  (SLTu64:{ *:[i32] } ZERO_64:{ *:[i64] }, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs))
15909          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
15910          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR64,
15911          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
15912          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
15913          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
15914          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15915          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTu64,
15916          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
15917          GIR_AddRegister, /*InsnID*/0, Mips::ZERO_64, /*AddRegisterRegFlags*/0,
15918          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
15919          GIR_EraseFromParent, /*InsnID*/0,
15920          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15921          // GIR_Coverage, 1544,
15922          GIR_Done,
15923        // Label 970: @38276
15924        GIM_Try, /*On fail goto*//*Label 971*/ 38331, // Rule ID 1545 //
15925          GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips,
15926          // MIs[0] Operand 1
15927          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
15928          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
15929          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
15930          // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] })  =>  (XORi:{ *:[i32] } (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), 1:{ *:[i32] })
15931          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
15932          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT64,
15933          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
15934          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
15935          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
15936          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15937          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi,
15938          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
15939          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
15940          GIR_AddImm, /*InsnID*/0, /*Imm*/1,
15941          GIR_EraseFromParent, /*InsnID*/0,
15942          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15943          // GIR_Coverage, 1545,
15944          GIR_Done,
15945        // Label 971: @38331
15946        GIM_Try, /*On fail goto*//*Label 972*/ 38386, // Rule ID 1546 //
15947          GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips,
15948          // MIs[0] Operand 1
15949          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
15950          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
15951          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
15952          // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] })  =>  (XORi:{ *:[i32] } (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), 1:{ *:[i32] })
15953          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
15954          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu64,
15955          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
15956          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
15957          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
15958          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15959          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi,
15960          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
15961          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
15962          GIR_AddImm, /*InsnID*/0, /*Imm*/1,
15963          GIR_EraseFromParent, /*InsnID*/0,
15964          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15965          // GIR_Coverage, 1546,
15966          GIR_Done,
15967        // Label 972: @38386
15968        GIM_Try, /*On fail goto*//*Label 973*/ 38422, // Rule ID 1547 //
15969          GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips,
15970          // MIs[0] Operand 1
15971          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT,
15972          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
15973          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
15974          // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGT:{ *:[Other] })  =>  (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs)
15975          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLT64,
15976          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
15977          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rhs
15978          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // lhs
15979          GIR_EraseFromParent, /*InsnID*/0,
15980          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15981          // GIR_Coverage, 1547,
15982          GIR_Done,
15983        // Label 973: @38422
15984        GIM_Try, /*On fail goto*//*Label 974*/ 38458, // Rule ID 1548 //
15985          GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips,
15986          // MIs[0] Operand 1
15987          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT,
15988          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
15989          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
15990          // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGT:{ *:[Other] })  =>  (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs)
15991          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTu64,
15992          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
15993          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rhs
15994          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // lhs
15995          GIR_EraseFromParent, /*InsnID*/0,
15996          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15997          // GIR_Coverage, 1548,
15998          GIR_Done,
15999        // Label 974: @38458
16000        GIM_Try, /*On fail goto*//*Label 975*/ 38513, // Rule ID 1549 //
16001          GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips,
16002          // MIs[0] Operand 1
16003          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
16004          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
16005          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
16006          // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] })  =>  (XORi:{ *:[i32] } (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), 1:{ *:[i32] })
16007          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16008          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT64,
16009          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
16010          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
16011          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
16012          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16013          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi,
16014          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
16015          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16016          GIR_AddImm, /*InsnID*/0, /*Imm*/1,
16017          GIR_EraseFromParent, /*InsnID*/0,
16018          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16019          // GIR_Coverage, 1549,
16020          GIR_Done,
16021        // Label 975: @38513
16022        GIM_Try, /*On fail goto*//*Label 976*/ 38568, // Rule ID 1550 //
16023          GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips,
16024          // MIs[0] Operand 1
16025          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
16026          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
16027          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
16028          // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] })  =>  (XORi:{ *:[i32] } (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), 1:{ *:[i32] })
16029          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16030          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu64,
16031          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
16032          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
16033          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
16034          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16035          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi,
16036          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
16037          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16038          GIR_AddImm, /*InsnID*/0, /*Imm*/1,
16039          GIR_EraseFromParent, /*InsnID*/0,
16040          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16041          // GIR_Coverage, 1550,
16042          GIR_Done,
16043        // Label 976: @38568
16044        GIM_Reject,
16045      // Label 968: @38569
16046      GIM_Reject,
16047      // Label 956: @38570
16048      GIM_Try, /*On fail goto*//*Label 977*/ 39610,
16049        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16050        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16051        GIM_Try, /*On fail goto*//*Label 978*/ 38639, // Rule ID 1836 //
16052          GIM_CheckFeatures, GIFBS_InMips16Mode,
16053          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
16054          // MIs[0] Operand 1
16055          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
16056          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
16057          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID,
16058          // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] })  =>  (SltiuCCRxImmX16:{ *:[i32] } (XorRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs), 1:{ *:[i32] })
16059          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16060          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XorRxRxRy16,
16061          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
16062          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
16063          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
16064          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16065          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SltiuCCRxImmX16,
16066          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // cc
16067          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16068          GIR_AddImm, /*InsnID*/0, /*Imm*/1,
16069          GIR_EraseFromParent, /*InsnID*/0,
16070          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16071          // GIR_Coverage, 1836,
16072          GIR_Done,
16073        // Label 978: @38639
16074        GIM_Try, /*On fail goto*//*Label 979*/ 38714, // Rule ID 1838 //
16075          GIM_CheckFeatures, GIFBS_InMips16Mode,
16076          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
16077          // MIs[0] Operand 1
16078          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
16079          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
16080          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID,
16081          // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETGE:{ *:[Other] })  =>  (XorRxRxRy16:{ *:[i32] } (SltCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs), (LiRxImmX16:{ *:[i32] } 1:{ *:[i32] }))
16082          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16083          GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
16084          GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::LiRxImmX16,
16085          GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
16086          GIR_AddImm, /*InsnID*/2, /*Imm*/1,
16087          GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
16088          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SltCCRxRy16,
16089          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
16090          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
16091          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
16092          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16093          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XorRxRxRy16,
16094          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rz
16095          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16096          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
16097          GIR_EraseFromParent, /*InsnID*/0,
16098          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16099          // GIR_Coverage, 1838,
16100          GIR_Done,
16101        // Label 979: @38714
16102        GIM_Try, /*On fail goto*//*Label 980*/ 38754, // Rule ID 1840 //
16103          GIM_CheckFeatures, GIFBS_InMips16Mode,
16104          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
16105          // MIs[0] Operand 1
16106          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT,
16107          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
16108          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID,
16109          // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETGT:{ *:[Other] })  =>  (SltCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rhs, CPU16Regs:{ *:[i32] }:$lhs)
16110          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SltCCRxRy16,
16111          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // cc
16112          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rhs
16113          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // lhs
16114          GIR_EraseFromParent, /*InsnID*/0,
16115          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16116          // GIR_Coverage, 1840,
16117          GIR_Done,
16118        // Label 980: @38754
16119        GIM_Try, /*On fail goto*//*Label 981*/ 38829, // Rule ID 1841 //
16120          GIM_CheckFeatures, GIFBS_InMips16Mode,
16121          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
16122          // MIs[0] Operand 1
16123          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
16124          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
16125          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID,
16126          // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETLE:{ *:[Other] })  =>  (XorRxRxRy16:{ *:[i32] } (SltCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rhs, CPU16Regs:{ *:[i32] }:$lhs), (LiRxImm16:{ *:[i32] } 1:{ *:[i32] }))
16127          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16128          GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
16129          GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::LiRxImm16,
16130          GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
16131          GIR_AddImm, /*InsnID*/2, /*Imm*/1,
16132          GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
16133          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SltCCRxRy16,
16134          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
16135          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
16136          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
16137          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16138          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XorRxRxRy16,
16139          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rz
16140          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16141          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
16142          GIR_EraseFromParent, /*InsnID*/0,
16143          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16144          // GIR_Coverage, 1841,
16145          GIR_Done,
16146        // Label 981: @38829
16147        GIM_Try, /*On fail goto*//*Label 982*/ 38869, // Rule ID 1842 //
16148          GIM_CheckFeatures, GIFBS_InMips16Mode,
16149          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
16150          // MIs[0] Operand 1
16151          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT,
16152          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
16153          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID,
16154          // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETLT:{ *:[Other] })  =>  (SltCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry)
16155          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SltCCRxRy16,
16156          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // cc
16157          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rx
16158          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ry
16159          GIR_EraseFromParent, /*InsnID*/0,
16160          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16161          // GIR_Coverage, 1842,
16162          GIR_Done,
16163        // Label 982: @38869
16164        GIM_Try, /*On fail goto*//*Label 983*/ 38944, // Rule ID 1844 //
16165          GIM_CheckFeatures, GIFBS_InMips16Mode,
16166          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
16167          // MIs[0] Operand 1
16168          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
16169          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
16170          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID,
16171          // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETNE:{ *:[Other] })  =>  (SltuCCRxRy16:{ *:[i32] } (LiRxImmX16:{ *:[i32] } 0:{ *:[i32] }), (XorRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs))
16172          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16173          GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
16174          GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::XorRxRxRy16,
16175          GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
16176          GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // lhs
16177          GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // rhs
16178          GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
16179          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::LiRxImmX16,
16180          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
16181          GIR_AddImm, /*InsnID*/1, /*Imm*/0,
16182          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16183          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SltuCCRxRy16,
16184          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // cc
16185          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16186          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
16187          GIR_EraseFromParent, /*InsnID*/0,
16188          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16189          // GIR_Coverage, 1844,
16190          GIR_Done,
16191        // Label 983: @38944
16192        GIM_Try, /*On fail goto*//*Label 984*/ 39019, // Rule ID 1845 //
16193          GIM_CheckFeatures, GIFBS_InMips16Mode,
16194          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
16195          // MIs[0] Operand 1
16196          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
16197          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
16198          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID,
16199          // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] })  =>  (XorRxRxRy16:{ *:[i32] } (SltuCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs), (LiRxImmX16:{ *:[i32] } 1:{ *:[i32] }))
16200          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16201          GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
16202          GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::LiRxImmX16,
16203          GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
16204          GIR_AddImm, /*InsnID*/2, /*Imm*/1,
16205          GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
16206          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SltuCCRxRy16,
16207          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
16208          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
16209          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
16210          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16211          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XorRxRxRy16,
16212          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rz
16213          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16214          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
16215          GIR_EraseFromParent, /*InsnID*/0,
16216          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16217          // GIR_Coverage, 1845,
16218          GIR_Done,
16219        // Label 984: @39019
16220        GIM_Try, /*On fail goto*//*Label 985*/ 39059, // Rule ID 1846 //
16221          GIM_CheckFeatures, GIFBS_InMips16Mode,
16222          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
16223          // MIs[0] Operand 1
16224          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT,
16225          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
16226          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID,
16227          // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETUGT:{ *:[Other] })  =>  (SltuCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rhs, CPU16Regs:{ *:[i32] }:$lhs)
16228          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SltuCCRxRy16,
16229          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // cc
16230          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rhs
16231          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // lhs
16232          GIR_EraseFromParent, /*InsnID*/0,
16233          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16234          // GIR_Coverage, 1846,
16235          GIR_Done,
16236        // Label 985: @39059
16237        GIM_Try, /*On fail goto*//*Label 986*/ 39134, // Rule ID 1847 //
16238          GIM_CheckFeatures, GIFBS_InMips16Mode,
16239          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
16240          // MIs[0] Operand 1
16241          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
16242          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
16243          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID,
16244          // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETULE:{ *:[Other] })  =>  (XorRxRxRy16:{ *:[i32] } (SltuCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rhs, CPU16Regs:{ *:[i32] }:$lhs), (LiRxImmX16:{ *:[i32] } 1:{ *:[i32] }))
16245          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16246          GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
16247          GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::LiRxImmX16,
16248          GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
16249          GIR_AddImm, /*InsnID*/2, /*Imm*/1,
16250          GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
16251          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SltuCCRxRy16,
16252          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
16253          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
16254          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
16255          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16256          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XorRxRxRy16,
16257          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rz
16258          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16259          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
16260          GIR_EraseFromParent, /*InsnID*/0,
16261          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16262          // GIR_Coverage, 1847,
16263          GIR_Done,
16264        // Label 986: @39134
16265        GIM_Try, /*On fail goto*//*Label 987*/ 39174, // Rule ID 1848 //
16266          GIM_CheckFeatures, GIFBS_InMips16Mode,
16267          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
16268          // MIs[0] Operand 1
16269          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT,
16270          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
16271          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID,
16272          // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETULT:{ *:[Other] })  =>  (SltuCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry)
16273          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SltuCCRxRy16,
16274          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // cc
16275          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rx
16276          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ry
16277          GIR_EraseFromParent, /*InsnID*/0,
16278          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16279          // GIR_Coverage, 1848,
16280          GIR_Done,
16281        // Label 987: @39174
16282        GIM_Try, /*On fail goto*//*Label 988*/ 39233, // Rule ID 2158 //
16283          GIM_CheckFeatures, GIFBS_InMicroMips,
16284          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
16285          // MIs[0] Operand 1
16286          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
16287          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
16288          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
16289          // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] })  =>  (SLTiu_MM:{ *:[i32] } (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] })
16290          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16291          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR_MM,
16292          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
16293          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
16294          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
16295          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16296          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTiu_MM,
16297          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
16298          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16299          GIR_AddImm, /*InsnID*/0, /*Imm*/1,
16300          GIR_EraseFromParent, /*InsnID*/0,
16301          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16302          // GIR_Coverage, 2158,
16303          GIR_Done,
16304        // Label 988: @39233
16305        GIM_Try, /*On fail goto*//*Label 989*/ 39293, // Rule ID 2159 //
16306          GIM_CheckFeatures, GIFBS_InMicroMips,
16307          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
16308          // MIs[0] Operand 1
16309          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
16310          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
16311          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
16312          // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] })  =>  (SLTu_MM:{ *:[i32] } ZERO:{ *:[i32] }, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs))
16313          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16314          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR_MM,
16315          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
16316          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
16317          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
16318          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16319          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTu_MM,
16320          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
16321          GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0,
16322          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16323          GIR_EraseFromParent, /*InsnID*/0,
16324          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16325          // GIR_Coverage, 2159,
16326          GIR_Done,
16327        // Label 989: @39293
16328        GIM_Try, /*On fail goto*//*Label 990*/ 39352, // Rule ID 2160 //
16329          GIM_CheckFeatures, GIFBS_InMicroMips,
16330          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
16331          // MIs[0] Operand 1
16332          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
16333          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
16334          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
16335          // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] })  =>  (XORi_MM:{ *:[i32] } (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), 1:{ *:[i32] })
16336          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16337          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT_MM,
16338          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
16339          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
16340          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
16341          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16342          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi_MM,
16343          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
16344          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16345          GIR_AddImm, /*InsnID*/0, /*Imm*/1,
16346          GIR_EraseFromParent, /*InsnID*/0,
16347          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16348          // GIR_Coverage, 2160,
16349          GIR_Done,
16350        // Label 990: @39352
16351        GIM_Try, /*On fail goto*//*Label 991*/ 39411, // Rule ID 2161 //
16352          GIM_CheckFeatures, GIFBS_InMicroMips,
16353          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
16354          // MIs[0] Operand 1
16355          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
16356          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
16357          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
16358          // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] })  =>  (XORi_MM:{ *:[i32] } (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), 1:{ *:[i32] })
16359          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16360          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu_MM,
16361          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
16362          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
16363          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
16364          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16365          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi_MM,
16366          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
16367          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16368          GIR_AddImm, /*InsnID*/0, /*Imm*/1,
16369          GIR_EraseFromParent, /*InsnID*/0,
16370          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16371          // GIR_Coverage, 2161,
16372          GIR_Done,
16373        // Label 991: @39411
16374        GIM_Try, /*On fail goto*//*Label 992*/ 39451, // Rule ID 2162 //
16375          GIM_CheckFeatures, GIFBS_InMicroMips,
16376          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
16377          // MIs[0] Operand 1
16378          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT,
16379          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
16380          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
16381          // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGT:{ *:[Other] })  =>  (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs)
16382          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLT_MM,
16383          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
16384          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rhs
16385          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // lhs
16386          GIR_EraseFromParent, /*InsnID*/0,
16387          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16388          // GIR_Coverage, 2162,
16389          GIR_Done,
16390        // Label 992: @39451
16391        GIM_Try, /*On fail goto*//*Label 993*/ 39491, // Rule ID 2163 //
16392          GIM_CheckFeatures, GIFBS_InMicroMips,
16393          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
16394          // MIs[0] Operand 1
16395          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT,
16396          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
16397          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
16398          // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGT:{ *:[Other] })  =>  (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs)
16399          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTu_MM,
16400          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
16401          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rhs
16402          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // lhs
16403          GIR_EraseFromParent, /*InsnID*/0,
16404          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16405          // GIR_Coverage, 2163,
16406          GIR_Done,
16407        // Label 993: @39491
16408        GIM_Try, /*On fail goto*//*Label 994*/ 39550, // Rule ID 2164 //
16409          GIM_CheckFeatures, GIFBS_InMicroMips,
16410          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
16411          // MIs[0] Operand 1
16412          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
16413          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
16414          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
16415          // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] })  =>  (XORi_MM:{ *:[i32] } (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] })
16416          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16417          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT_MM,
16418          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
16419          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
16420          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
16421          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16422          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi_MM,
16423          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
16424          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16425          GIR_AddImm, /*InsnID*/0, /*Imm*/1,
16426          GIR_EraseFromParent, /*InsnID*/0,
16427          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16428          // GIR_Coverage, 2164,
16429          GIR_Done,
16430        // Label 994: @39550
16431        GIM_Try, /*On fail goto*//*Label 995*/ 39609, // Rule ID 2165 //
16432          GIM_CheckFeatures, GIFBS_InMicroMips,
16433          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
16434          // MIs[0] Operand 1
16435          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
16436          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
16437          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
16438          // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] })  =>  (XORi_MM:{ *:[i32] } (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] })
16439          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16440          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu_MM,
16441          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
16442          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
16443          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
16444          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16445          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi_MM,
16446          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
16447          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16448          GIR_AddImm, /*InsnID*/0, /*Imm*/1,
16449          GIR_EraseFromParent, /*InsnID*/0,
16450          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16451          // GIR_Coverage, 2165,
16452          GIR_Done,
16453        // Label 995: @39609
16454        GIM_Reject,
16455      // Label 977: @39610
16456      GIM_Reject,
16457    // Label 931: @39611
16458    GIM_Reject,
16459    // Label 26: @39612
16460    GIM_Try, /*On fail goto*//*Label 996*/ 41331,
16461      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
16462      GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/1, 3, /*)*//*default:*//*Label 999*/ 40154,
16463      /*GILLT_s32*//*Label 997*/ 39626,
16464      /*GILLT_s64*//*Label 998*/ 39890,
16465      // Label 997: @39626
16466      GIM_Try, /*On fail goto*//*Label 1000*/ 39889,
16467        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16468        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGRCCRegClassID,
16469        GIM_Try, /*On fail goto*//*Label 1001*/ 39672, // Rule ID 300 //
16470          GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
16471          // MIs[0] Operand 1
16472          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNO,
16473          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
16474          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
16475          // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETUO:{ *:[Other] })  =>  (CMP_UN_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
16476          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_UN_S,
16477          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
16478          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs
16479          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft
16480          GIR_EraseFromParent, /*InsnID*/0,
16481          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16482          // GIR_Coverage, 300,
16483          GIR_Done,
16484        // Label 1001: @39672
16485        GIM_Try, /*On fail goto*//*Label 1002*/ 39708, // Rule ID 301 //
16486          GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
16487          // MIs[0] Operand 1
16488          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OEQ,
16489          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
16490          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
16491          // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETOEQ:{ *:[Other] })  =>  (CMP_EQ_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
16492          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_EQ_S,
16493          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
16494          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs
16495          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft
16496          GIR_EraseFromParent, /*InsnID*/0,
16497          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16498          // GIR_Coverage, 301,
16499          GIR_Done,
16500        // Label 1002: @39708
16501        GIM_Try, /*On fail goto*//*Label 1003*/ 39744, // Rule ID 302 //
16502          GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
16503          // MIs[0] Operand 1
16504          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UEQ,
16505          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
16506          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
16507          // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETUEQ:{ *:[Other] })  =>  (CMP_UEQ_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
16508          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_UEQ_S,
16509          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
16510          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs
16511          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft
16512          GIR_EraseFromParent, /*InsnID*/0,
16513          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16514          // GIR_Coverage, 302,
16515          GIR_Done,
16516        // Label 1003: @39744
16517        GIM_Try, /*On fail goto*//*Label 1004*/ 39780, // Rule ID 303 //
16518          GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
16519          // MIs[0] Operand 1
16520          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLT,
16521          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
16522          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
16523          // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETOLT:{ *:[Other] })  =>  (CMP_LT_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
16524          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LT_S,
16525          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
16526          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs
16527          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft
16528          GIR_EraseFromParent, /*InsnID*/0,
16529          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16530          // GIR_Coverage, 303,
16531          GIR_Done,
16532        // Label 1004: @39780
16533        GIM_Try, /*On fail goto*//*Label 1005*/ 39816, // Rule ID 304 //
16534          GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
16535          // MIs[0] Operand 1
16536          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ULT,
16537          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
16538          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
16539          // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETULT:{ *:[Other] })  =>  (CMP_ULT_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
16540          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_ULT_S,
16541          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
16542          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs
16543          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft
16544          GIR_EraseFromParent, /*InsnID*/0,
16545          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16546          // GIR_Coverage, 304,
16547          GIR_Done,
16548        // Label 1005: @39816
16549        GIM_Try, /*On fail goto*//*Label 1006*/ 39852, // Rule ID 305 //
16550          GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
16551          // MIs[0] Operand 1
16552          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLE,
16553          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
16554          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
16555          // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETOLE:{ *:[Other] })  =>  (CMP_LE_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
16556          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LE_S,
16557          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
16558          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs
16559          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft
16560          GIR_EraseFromParent, /*InsnID*/0,
16561          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16562          // GIR_Coverage, 305,
16563          GIR_Done,
16564        // Label 1006: @39852
16565        GIM_Try, /*On fail goto*//*Label 1007*/ 39888, // Rule ID 306 //
16566          GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
16567          // MIs[0] Operand 1
16568          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ULE,
16569          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
16570          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
16571          // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETULE:{ *:[Other] })  =>  (CMP_ULE_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
16572          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_ULE_S,
16573          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
16574          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs
16575          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft
16576          GIR_EraseFromParent, /*InsnID*/0,
16577          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16578          // GIR_Coverage, 306,
16579          GIR_Done,
16580        // Label 1007: @39888
16581        GIM_Reject,
16582      // Label 1000: @39889
16583      GIM_Reject,
16584      // Label 998: @39890
16585      GIM_Try, /*On fail goto*//*Label 1008*/ 40153,
16586        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
16587        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGRCCRegClassID,
16588        GIM_Try, /*On fail goto*//*Label 1009*/ 39936, // Rule ID 307 //
16589          GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
16590          // MIs[0] Operand 1
16591          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNO,
16592          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
16593          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
16594          // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETUO:{ *:[Other] })  =>  (CMP_UN_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
16595          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_UN_D,
16596          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
16597          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs
16598          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft
16599          GIR_EraseFromParent, /*InsnID*/0,
16600          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16601          // GIR_Coverage, 307,
16602          GIR_Done,
16603        // Label 1009: @39936
16604        GIM_Try, /*On fail goto*//*Label 1010*/ 39972, // Rule ID 308 //
16605          GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
16606          // MIs[0] Operand 1
16607          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OEQ,
16608          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
16609          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
16610          // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETOEQ:{ *:[Other] })  =>  (CMP_EQ_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
16611          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_EQ_D,
16612          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
16613          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs
16614          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft
16615          GIR_EraseFromParent, /*InsnID*/0,
16616          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16617          // GIR_Coverage, 308,
16618          GIR_Done,
16619        // Label 1010: @39972
16620        GIM_Try, /*On fail goto*//*Label 1011*/ 40008, // Rule ID 309 //
16621          GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
16622          // MIs[0] Operand 1
16623          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UEQ,
16624          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
16625          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
16626          // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETUEQ:{ *:[Other] })  =>  (CMP_UEQ_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
16627          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_UEQ_D,
16628          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
16629          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs
16630          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft
16631          GIR_EraseFromParent, /*InsnID*/0,
16632          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16633          // GIR_Coverage, 309,
16634          GIR_Done,
16635        // Label 1011: @40008
16636        GIM_Try, /*On fail goto*//*Label 1012*/ 40044, // Rule ID 310 //
16637          GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
16638          // MIs[0] Operand 1
16639          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLT,
16640          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
16641          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
16642          // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETOLT:{ *:[Other] })  =>  (CMP_LT_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
16643          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LT_D,
16644          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
16645          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs
16646          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft
16647          GIR_EraseFromParent, /*InsnID*/0,
16648          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16649          // GIR_Coverage, 310,
16650          GIR_Done,
16651        // Label 1012: @40044
16652        GIM_Try, /*On fail goto*//*Label 1013*/ 40080, // Rule ID 311 //
16653          GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
16654          // MIs[0] Operand 1
16655          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ULT,
16656          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
16657          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
16658          // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETULT:{ *:[Other] })  =>  (CMP_ULT_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
16659          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_ULT_D,
16660          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
16661          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs
16662          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft
16663          GIR_EraseFromParent, /*InsnID*/0,
16664          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16665          // GIR_Coverage, 311,
16666          GIR_Done,
16667        // Label 1013: @40080
16668        GIM_Try, /*On fail goto*//*Label 1014*/ 40116, // Rule ID 312 //
16669          GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
16670          // MIs[0] Operand 1
16671          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLE,
16672          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
16673          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
16674          // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETOLE:{ *:[Other] })  =>  (CMP_LE_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
16675          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LE_D,
16676          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
16677          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs
16678          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft
16679          GIR_EraseFromParent, /*InsnID*/0,
16680          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16681          // GIR_Coverage, 312,
16682          GIR_Done,
16683        // Label 1014: @40116
16684        GIM_Try, /*On fail goto*//*Label 1015*/ 40152, // Rule ID 313 //
16685          GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
16686          // MIs[0] Operand 1
16687          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ULE,
16688          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
16689          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
16690          // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETULE:{ *:[Other] })  =>  (CMP_ULE_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
16691          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_ULE_D,
16692          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
16693          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs
16694          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft
16695          GIR_EraseFromParent, /*InsnID*/0,
16696          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16697          // GIR_Coverage, 313,
16698          GIR_Done,
16699        // Label 1015: @40152
16700        GIM_Reject,
16701      // Label 1008: @40153
16702      GIM_Reject,
16703      // Label 999: @40154
16704      GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/1, 3, /*)*//*default:*//*Label 1018*/ 40690,
16705      /*GILLT_s32*//*Label 1016*/ 40162,
16706      /*GILLT_s64*//*Label 1017*/ 40426,
16707      // Label 1016: @40162
16708      GIM_Try, /*On fail goto*//*Label 1019*/ 40425,
16709        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16710        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGRCCRegClassID,
16711        GIM_Try, /*On fail goto*//*Label 1020*/ 40208, // Rule ID 1175 //
16712          GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
16713          // MIs[0] Operand 1
16714          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNO,
16715          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
16716          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
16717          // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETUO:{ *:[Other] })  =>  (CMP_UN_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
16718          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_UN_S_MMR6,
16719          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
16720          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs
16721          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft
16722          GIR_EraseFromParent, /*InsnID*/0,
16723          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16724          // GIR_Coverage, 1175,
16725          GIR_Done,
16726        // Label 1020: @40208
16727        GIM_Try, /*On fail goto*//*Label 1021*/ 40244, // Rule ID 1176 //
16728          GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
16729          // MIs[0] Operand 1
16730          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OEQ,
16731          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
16732          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
16733          // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETOEQ:{ *:[Other] })  =>  (CMP_EQ_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
16734          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_EQ_S_MMR6,
16735          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
16736          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs
16737          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft
16738          GIR_EraseFromParent, /*InsnID*/0,
16739          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16740          // GIR_Coverage, 1176,
16741          GIR_Done,
16742        // Label 1021: @40244
16743        GIM_Try, /*On fail goto*//*Label 1022*/ 40280, // Rule ID 1177 //
16744          GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
16745          // MIs[0] Operand 1
16746          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UEQ,
16747          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
16748          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
16749          // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETUEQ:{ *:[Other] })  =>  (CMP_UEQ_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
16750          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_UEQ_S_MMR6,
16751          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
16752          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs
16753          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft
16754          GIR_EraseFromParent, /*InsnID*/0,
16755          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16756          // GIR_Coverage, 1177,
16757          GIR_Done,
16758        // Label 1022: @40280
16759        GIM_Try, /*On fail goto*//*Label 1023*/ 40316, // Rule ID 1178 //
16760          GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
16761          // MIs[0] Operand 1
16762          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLT,
16763          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
16764          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
16765          // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETOLT:{ *:[Other] })  =>  (CMP_LT_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
16766          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LT_S_MMR6,
16767          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
16768          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs
16769          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft
16770          GIR_EraseFromParent, /*InsnID*/0,
16771          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16772          // GIR_Coverage, 1178,
16773          GIR_Done,
16774        // Label 1023: @40316
16775        GIM_Try, /*On fail goto*//*Label 1024*/ 40352, // Rule ID 1179 //
16776          GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
16777          // MIs[0] Operand 1
16778          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ULT,
16779          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
16780          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
16781          // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETULT:{ *:[Other] })  =>  (CMP_ULT_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
16782          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_ULT_S_MMR6,
16783          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
16784          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs
16785          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft
16786          GIR_EraseFromParent, /*InsnID*/0,
16787          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16788          // GIR_Coverage, 1179,
16789          GIR_Done,
16790        // Label 1024: @40352
16791        GIM_Try, /*On fail goto*//*Label 1025*/ 40388, // Rule ID 1180 //
16792          GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
16793          // MIs[0] Operand 1
16794          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLE,
16795          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
16796          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
16797          // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETOLE:{ *:[Other] })  =>  (CMP_LE_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
16798          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LE_S_MMR6,
16799          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
16800          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs
16801          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft
16802          GIR_EraseFromParent, /*InsnID*/0,
16803          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16804          // GIR_Coverage, 1180,
16805          GIR_Done,
16806        // Label 1025: @40388
16807        GIM_Try, /*On fail goto*//*Label 1026*/ 40424, // Rule ID 1181 //
16808          GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
16809          // MIs[0] Operand 1
16810          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ULE,
16811          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
16812          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
16813          // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETULE:{ *:[Other] })  =>  (CMP_ULE_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
16814          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_ULE_S_MMR6,
16815          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
16816          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs
16817          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft
16818          GIR_EraseFromParent, /*InsnID*/0,
16819          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16820          // GIR_Coverage, 1181,
16821          GIR_Done,
16822        // Label 1026: @40424
16823        GIM_Reject,
16824      // Label 1019: @40425
16825      GIM_Reject,
16826      // Label 1017: @40426
16827      GIM_Try, /*On fail goto*//*Label 1027*/ 40689,
16828        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
16829        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGRCCRegClassID,
16830        GIM_Try, /*On fail goto*//*Label 1028*/ 40472, // Rule ID 1182 //
16831          GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
16832          // MIs[0] Operand 1
16833          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNO,
16834          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
16835          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
16836          // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETUO:{ *:[Other] })  =>  (CMP_UN_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
16837          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_UN_D_MMR6,
16838          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
16839          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs
16840          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft
16841          GIR_EraseFromParent, /*InsnID*/0,
16842          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16843          // GIR_Coverage, 1182,
16844          GIR_Done,
16845        // Label 1028: @40472
16846        GIM_Try, /*On fail goto*//*Label 1029*/ 40508, // Rule ID 1183 //
16847          GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
16848          // MIs[0] Operand 1
16849          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OEQ,
16850          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
16851          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
16852          // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETOEQ:{ *:[Other] })  =>  (CMP_EQ_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
16853          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_EQ_D_MMR6,
16854          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
16855          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs
16856          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft
16857          GIR_EraseFromParent, /*InsnID*/0,
16858          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16859          // GIR_Coverage, 1183,
16860          GIR_Done,
16861        // Label 1029: @40508
16862        GIM_Try, /*On fail goto*//*Label 1030*/ 40544, // Rule ID 1184 //
16863          GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
16864          // MIs[0] Operand 1
16865          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UEQ,
16866          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
16867          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
16868          // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETUEQ:{ *:[Other] })  =>  (CMP_UEQ_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
16869          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_UEQ_D_MMR6,
16870          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
16871          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs
16872          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft
16873          GIR_EraseFromParent, /*InsnID*/0,
16874          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16875          // GIR_Coverage, 1184,
16876          GIR_Done,
16877        // Label 1030: @40544
16878        GIM_Try, /*On fail goto*//*Label 1031*/ 40580, // Rule ID 1185 //
16879          GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
16880          // MIs[0] Operand 1
16881          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLT,
16882          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
16883          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
16884          // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETOLT:{ *:[Other] })  =>  (CMP_LT_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
16885          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LT_D_MMR6,
16886          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
16887          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs
16888          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft
16889          GIR_EraseFromParent, /*InsnID*/0,
16890          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16891          // GIR_Coverage, 1185,
16892          GIR_Done,
16893        // Label 1031: @40580
16894        GIM_Try, /*On fail goto*//*Label 1032*/ 40616, // Rule ID 1186 //
16895          GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
16896          // MIs[0] Operand 1
16897          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ULT,
16898          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
16899          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
16900          // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETULT:{ *:[Other] })  =>  (CMP_ULT_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
16901          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_ULT_D_MMR6,
16902          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
16903          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs
16904          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft
16905          GIR_EraseFromParent, /*InsnID*/0,
16906          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16907          // GIR_Coverage, 1186,
16908          GIR_Done,
16909        // Label 1032: @40616
16910        GIM_Try, /*On fail goto*//*Label 1033*/ 40652, // Rule ID 1187 //
16911          GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
16912          // MIs[0] Operand 1
16913          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLE,
16914          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
16915          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
16916          // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETOLE:{ *:[Other] })  =>  (CMP_LE_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
16917          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LE_D_MMR6,
16918          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
16919          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs
16920          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft
16921          GIR_EraseFromParent, /*InsnID*/0,
16922          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16923          // GIR_Coverage, 1187,
16924          GIR_Done,
16925        // Label 1033: @40652
16926        GIM_Try, /*On fail goto*//*Label 1034*/ 40688, // Rule ID 1188 //
16927          GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
16928          // MIs[0] Operand 1
16929          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ULE,
16930          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
16931          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
16932          // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETULE:{ *:[Other] })  =>  (CMP_ULE_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
16933          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_ULE_D_MMR6,
16934          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
16935          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs
16936          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft
16937          GIR_EraseFromParent, /*InsnID*/0,
16938          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16939          // GIR_Coverage, 1188,
16940          GIR_Done,
16941        // Label 1034: @40688
16942        GIM_Reject,
16943      // Label 1027: @40689
16944      GIM_Reject,
16945      // Label 1018: @40690
16946      GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/1, 3, /*)*//*default:*//*Label 1037*/ 41010,
16947      /*GILLT_s32*//*Label 1035*/ 40698,
16948      /*GILLT_s64*//*Label 1036*/ 40854,
16949      // Label 1035: @40698
16950      GIM_Try, /*On fail goto*//*Label 1038*/ 40853,
16951        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16952        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
16953        GIM_Try, /*On fail goto*//*Label 1039*/ 40756, // Rule ID 1717 //
16954          GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
16955          // MIs[0] Operand 1
16956          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ONE,
16957          // (setcc:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs, SETONE:{ *:[Other] })  =>  (NOR:{ *:[i32] } (CMP_UEQ_S:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs), ZERO:{ *:[i32] })
16958          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16959          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::CMP_UEQ_S,
16960          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
16961          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
16962          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
16963          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16964          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR,
16965          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
16966          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16967          GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0,
16968          GIR_EraseFromParent, /*InsnID*/0,
16969          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16970          // GIR_Coverage, 1717,
16971          GIR_Done,
16972        // Label 1039: @40756
16973        GIM_Try, /*On fail goto*//*Label 1040*/ 40804, // Rule ID 1718 //
16974          GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
16975          // MIs[0] Operand 1
16976          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ORD,
16977          // (setcc:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs, SETO:{ *:[Other] })  =>  (NOR:{ *:[i32] } (CMP_UN_S:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs), ZERO:{ *:[i32] })
16978          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16979          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::CMP_UN_S,
16980          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
16981          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
16982          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
16983          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16984          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR,
16985          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
16986          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16987          GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0,
16988          GIR_EraseFromParent, /*InsnID*/0,
16989          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16990          // GIR_Coverage, 1718,
16991          GIR_Done,
16992        // Label 1040: @40804
16993        GIM_Try, /*On fail goto*//*Label 1041*/ 40852, // Rule ID 1719 //
16994          GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
16995          // MIs[0] Operand 1
16996          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE,
16997          // (setcc:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs, SETUNE:{ *:[Other] })  =>  (NOR:{ *:[i32] } (CMP_EQ_S:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs), ZERO:{ *:[i32] })
16998          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16999          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::CMP_EQ_S,
17000          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
17001          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
17002          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
17003          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17004          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR,
17005          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
17006          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
17007          GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0,
17008          GIR_EraseFromParent, /*InsnID*/0,
17009          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17010          // GIR_Coverage, 1719,
17011          GIR_Done,
17012        // Label 1041: @40852
17013        GIM_Reject,
17014      // Label 1038: @40853
17015      GIM_Reject,
17016      // Label 1036: @40854
17017      GIM_Try, /*On fail goto*//*Label 1042*/ 41009,
17018        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
17019        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
17020        GIM_Try, /*On fail goto*//*Label 1043*/ 40912, // Rule ID 1726 //
17021          GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
17022          // MIs[0] Operand 1
17023          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ONE,
17024          // (setcc:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs, SETONE:{ *:[Other] })  =>  (NOR:{ *:[i32] } (CMP_UEQ_D:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs), ZERO:{ *:[i32] })
17025          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17026          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::CMP_UEQ_D,
17027          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
17028          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
17029          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
17030          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17031          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR,
17032          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
17033          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
17034          GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0,
17035          GIR_EraseFromParent, /*InsnID*/0,
17036          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17037          // GIR_Coverage, 1726,
17038          GIR_Done,
17039        // Label 1043: @40912
17040        GIM_Try, /*On fail goto*//*Label 1044*/ 40960, // Rule ID 1727 //
17041          GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
17042          // MIs[0] Operand 1
17043          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ORD,
17044          // (setcc:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs, SETO:{ *:[Other] })  =>  (NOR:{ *:[i32] } (CMP_UN_D:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs), ZERO:{ *:[i32] })
17045          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17046          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::CMP_UN_D,
17047          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
17048          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
17049          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
17050          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17051          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR,
17052          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
17053          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
17054          GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0,
17055          GIR_EraseFromParent, /*InsnID*/0,
17056          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17057          // GIR_Coverage, 1727,
17058          GIR_Done,
17059        // Label 1044: @40960
17060        GIM_Try, /*On fail goto*//*Label 1045*/ 41008, // Rule ID 1728 //
17061          GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
17062          // MIs[0] Operand 1
17063          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE,
17064          // (setcc:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs, SETUNE:{ *:[Other] })  =>  (NOR:{ *:[i32] } (CMP_EQ_D:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs), ZERO:{ *:[i32] })
17065          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17066          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::CMP_EQ_D,
17067          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
17068          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
17069          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
17070          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17071          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR,
17072          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
17073          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
17074          GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0,
17075          GIR_EraseFromParent, /*InsnID*/0,
17076          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17077          // GIR_Coverage, 1728,
17078          GIR_Done,
17079        // Label 1045: @41008
17080        GIM_Reject,
17081      // Label 1042: @41009
17082      GIM_Reject,
17083      // Label 1037: @41010
17084      GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/1, 3, /*)*//*default:*//*Label 1048*/ 41330,
17085      /*GILLT_s32*//*Label 1046*/ 41018,
17086      /*GILLT_s64*//*Label 1047*/ 41174,
17087      // Label 1046: @41018
17088      GIM_Try, /*On fail goto*//*Label 1049*/ 41173,
17089        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17090        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
17091        GIM_Try, /*On fail goto*//*Label 1050*/ 41076, // Rule ID 2255 //
17092          GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
17093          // MIs[0] Operand 1
17094          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ONE,
17095          // (setcc:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs, SETONE:{ *:[Other] })  =>  (NOR_MMR6:{ *:[i32] } (CMP_UEQ_S_MMR6:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs), ZERO:{ *:[i32] })
17096          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17097          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::CMP_UEQ_S_MMR6,
17098          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
17099          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
17100          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
17101          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17102          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MMR6,
17103          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
17104          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
17105          GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0,
17106          GIR_EraseFromParent, /*InsnID*/0,
17107          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17108          // GIR_Coverage, 2255,
17109          GIR_Done,
17110        // Label 1050: @41076
17111        GIM_Try, /*On fail goto*//*Label 1051*/ 41124, // Rule ID 2256 //
17112          GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
17113          // MIs[0] Operand 1
17114          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ORD,
17115          // (setcc:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs, SETO:{ *:[Other] })  =>  (NOR_MMR6:{ *:[i32] } (CMP_UN_S_MMR6:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs), ZERO:{ *:[i32] })
17116          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17117          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::CMP_UN_S_MMR6,
17118          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
17119          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
17120          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
17121          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17122          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MMR6,
17123          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
17124          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
17125          GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0,
17126          GIR_EraseFromParent, /*InsnID*/0,
17127          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17128          // GIR_Coverage, 2256,
17129          GIR_Done,
17130        // Label 1051: @41124
17131        GIM_Try, /*On fail goto*//*Label 1052*/ 41172, // Rule ID 2257 //
17132          GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
17133          // MIs[0] Operand 1
17134          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE,
17135          // (setcc:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs, SETUNE:{ *:[Other] })  =>  (NOR_MMR6:{ *:[i32] } (CMP_EQ_S_MMR6:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs), ZERO:{ *:[i32] })
17136          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17137          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::CMP_EQ_S_MMR6,
17138          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
17139          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
17140          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
17141          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17142          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MMR6,
17143          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
17144          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
17145          GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0,
17146          GIR_EraseFromParent, /*InsnID*/0,
17147          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17148          // GIR_Coverage, 2257,
17149          GIR_Done,
17150        // Label 1052: @41172
17151        GIM_Reject,
17152      // Label 1049: @41173
17153      GIM_Reject,
17154      // Label 1047: @41174
17155      GIM_Try, /*On fail goto*//*Label 1053*/ 41329,
17156        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
17157        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
17158        GIM_Try, /*On fail goto*//*Label 1054*/ 41232, // Rule ID 2264 //
17159          GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
17160          // MIs[0] Operand 1
17161          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ONE,
17162          // (setcc:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs, SETONE:{ *:[Other] })  =>  (NOR_MMR6:{ *:[i32] } (CMP_UEQ_D_MMR6:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs), ZERO:{ *:[i32] })
17163          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17164          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::CMP_UEQ_D_MMR6,
17165          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
17166          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
17167          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
17168          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17169          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MMR6,
17170          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
17171          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
17172          GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0,
17173          GIR_EraseFromParent, /*InsnID*/0,
17174          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17175          // GIR_Coverage, 2264,
17176          GIR_Done,
17177        // Label 1054: @41232
17178        GIM_Try, /*On fail goto*//*Label 1055*/ 41280, // Rule ID 2265 //
17179          GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
17180          // MIs[0] Operand 1
17181          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ORD,
17182          // (setcc:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs, SETO:{ *:[Other] })  =>  (NOR_MMR6:{ *:[i32] } (CMP_UN_D_MMR6:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs), ZERO:{ *:[i32] })
17183          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17184          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::CMP_UN_D_MMR6,
17185          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
17186          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
17187          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
17188          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17189          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MMR6,
17190          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
17191          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
17192          GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0,
17193          GIR_EraseFromParent, /*InsnID*/0,
17194          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17195          // GIR_Coverage, 2265,
17196          GIR_Done,
17197        // Label 1055: @41280
17198        GIM_Try, /*On fail goto*//*Label 1056*/ 41328, // Rule ID 2266 //
17199          GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
17200          // MIs[0] Operand 1
17201          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE,
17202          // (setcc:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs, SETUNE:{ *:[Other] })  =>  (NOR_MMR6:{ *:[i32] } (CMP_EQ_D_MMR6:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs), ZERO:{ *:[i32] })
17203          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17204          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::CMP_EQ_D_MMR6,
17205          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
17206          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
17207          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
17208          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17209          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MMR6,
17210          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
17211          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
17212          GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0,
17213          GIR_EraseFromParent, /*InsnID*/0,
17214          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17215          // GIR_Coverage, 2266,
17216          GIR_Done,
17217        // Label 1056: @41328
17218        GIM_Reject,
17219      // Label 1053: @41329
17220      GIM_Reject,
17221      // Label 1048: @41330
17222      GIM_Reject,
17223    // Label 996: @41331
17224    GIM_Reject,
17225    // Label 27: @41332
17226    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1059*/ 53611,
17227    /*GILLT_s32*//*Label 1057*/ 41340,
17228    /*GILLT_s64*//*Label 1058*/ 48357,
17229    // Label 1057: @41340
17230    GIM_Try, /*On fail goto*//*Label 1060*/ 41421, // Rule ID 1605 //
17231      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
17232      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
17233      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17234      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17235      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
17236      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17237      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
17238      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
17239      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
17240      // MIs[1] Operand 1
17241      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
17242      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
17243      GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0,
17244      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
17245      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
17246      GIM_CheckIsSafeToFold, /*InsnID*/1,
17247      // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F)
17248      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I,
17249      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
17250      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
17251      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
17252      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
17253      GIR_EraseFromParent, /*InsnID*/0,
17254      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17255      // GIR_Coverage, 1605,
17256      GIR_Done,
17257    // Label 1060: @41421
17258    GIM_Try, /*On fail goto*//*Label 1061*/ 41502, // Rule ID 1609 //
17259      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
17260      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
17261      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17262      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17263      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
17264      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17265      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
17266      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
17267      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
17268      // MIs[1] Operand 1
17269      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
17270      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
17271      GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0,
17272      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
17273      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
17274      GIM_CheckIsSafeToFold, /*InsnID*/1,
17275      // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVN_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F)
17276      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_I,
17277      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
17278      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
17279      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
17280      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
17281      GIR_EraseFromParent, /*InsnID*/0,
17282      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17283      // GIR_Coverage, 1609,
17284      GIR_Done,
17285    // Label 1061: @41502
17286    GIM_Try, /*On fail goto*//*Label 1062*/ 41583, // Rule ID 1637 //
17287      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
17288      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
17289      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17290      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17291      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
17292      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17293      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
17294      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
17295      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
17296      // MIs[1] Operand 1
17297      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
17298      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
17299      GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0,
17300      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
17301      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
17302      GIM_CheckIsSafeToFold, /*InsnID*/1,
17303      // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I64_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR64:{ *:[i64] }:$lhs, GPR32:{ *:[i32] }:$F)
17304      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I64_I,
17305      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
17306      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
17307      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
17308      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
17309      GIR_EraseFromParent, /*InsnID*/0,
17310      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17311      // GIR_Coverage, 1637,
17312      GIR_Done,
17313    // Label 1062: @41583
17314    GIM_Try, /*On fail goto*//*Label 1063*/ 41664, // Rule ID 1648 //
17315      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
17316      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
17317      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17318      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17319      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
17320      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17321      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
17322      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
17323      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
17324      // MIs[1] Operand 1
17325      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
17326      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
17327      GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0,
17328      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
17329      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
17330      GIM_CheckIsSafeToFold, /*InsnID*/1,
17331      // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVN_I64_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR64:{ *:[i64] }:$lhs, GPR32:{ *:[i32] }:$F)
17332      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_I,
17333      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
17334      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
17335      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
17336      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
17337      GIR_EraseFromParent, /*InsnID*/0,
17338      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17339      // GIR_Coverage, 1648,
17340      GIR_Done,
17341    // Label 1063: @41664
17342    GIM_Try, /*On fail goto*//*Label 1064*/ 41745, // Rule ID 1661 //
17343      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
17344      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
17345      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17346      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17347      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
17348      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17349      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
17350      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
17351      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
17352      // MIs[1] Operand 1
17353      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
17354      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
17355      GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0,
17356      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
17357      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
17358      GIM_CheckIsSafeToFold, /*InsnID*/1,
17359      // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$lhs, FGR32:{ *:[f32] }:$F)
17360      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S,
17361      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
17362      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
17363      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
17364      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
17365      GIR_EraseFromParent, /*InsnID*/0,
17366      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17367      // GIR_Coverage, 1661,
17368      GIR_Done,
17369    // Label 1064: @41745
17370    GIM_Try, /*On fail goto*//*Label 1065*/ 41826, // Rule ID 1664 //
17371      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
17372      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
17373      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17374      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17375      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
17376      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17377      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
17378      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
17379      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
17380      // MIs[1] Operand 1
17381      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
17382      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
17383      GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0,
17384      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
17385      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
17386      GIM_CheckIsSafeToFold, /*InsnID*/1,
17387      // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVN_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$lhs, FGR32:{ *:[f32] }:$F)
17388      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_S,
17389      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
17390      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
17391      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
17392      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
17393      GIR_EraseFromParent, /*InsnID*/0,
17394      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17395      // GIR_Coverage, 1664,
17396      GIR_Done,
17397    // Label 1065: @41826
17398    GIM_Try, /*On fail goto*//*Label 1066*/ 41907, // Rule ID 1674 //
17399      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
17400      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
17401      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17402      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17403      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
17404      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17405      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
17406      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
17407      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
17408      // MIs[1] Operand 1
17409      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
17410      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
17411      GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0,
17412      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
17413      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
17414      GIM_CheckIsSafeToFold, /*InsnID*/1,
17415      // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVZ_I64_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR64:{ *:[i64] }:$lhs, FGR32:{ *:[f32] }:$F)
17416      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I64_S,
17417      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
17418      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
17419      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
17420      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
17421      GIR_EraseFromParent, /*InsnID*/0,
17422      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17423      // GIR_Coverage, 1674,
17424      GIR_Done,
17425    // Label 1066: @41907
17426    GIM_Try, /*On fail goto*//*Label 1067*/ 41988, // Rule ID 1677 //
17427      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
17428      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
17429      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17430      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17431      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
17432      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17433      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
17434      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
17435      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
17436      // MIs[1] Operand 1
17437      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
17438      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
17439      GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0,
17440      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
17441      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
17442      GIM_CheckIsSafeToFold, /*InsnID*/1,
17443      // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVN_I64_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR64:{ *:[i64] }:$lhs, FGR32:{ *:[f32] }:$F)
17444      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_S,
17445      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
17446      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
17447      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
17448      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
17449      GIR_EraseFromParent, /*InsnID*/0,
17450      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17451      // GIR_Coverage, 1677,
17452      GIR_Done,
17453    // Label 1067: @41988
17454    GIM_Try, /*On fail goto*//*Label 1068*/ 42069, // Rule ID 1830 //
17455      GIM_CheckFeatures, GIFBS_InMips16Mode,
17456      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
17457      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17458      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17459      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
17460      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17461      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
17462      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
17463      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
17464      // MIs[1] Operand 1
17465      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
17466      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
17467      GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0,
17468      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
17469      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID,
17470      GIM_CheckIsSafeToFold, /*InsnID*/1,
17471      // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y)  =>  (SelBeqZ:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$a)
17472      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SelBeqZ,
17473      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd_
17474      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // x
17475      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // y
17476      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
17477      GIR_EraseFromParent, /*InsnID*/0,
17478      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17479      // GIR_Coverage, 1830,
17480      GIR_Done,
17481    // Label 1068: @42069
17482    GIM_Try, /*On fail goto*//*Label 1069*/ 42150, // Rule ID 1833 //
17483      GIM_CheckFeatures, GIFBS_InMips16Mode,
17484      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
17485      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17486      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17487      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
17488      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17489      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
17490      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
17491      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
17492      // MIs[1] Operand 1
17493      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
17494      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
17495      GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0,
17496      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
17497      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID,
17498      GIM_CheckIsSafeToFold, /*InsnID*/1,
17499      // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, 0:{ *:[i32] }, SETNE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y)  =>  (SelBneZ:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$a)
17500      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SelBneZ,
17501      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd_
17502      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // x
17503      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // y
17504      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
17505      GIR_EraseFromParent, /*InsnID*/0,
17506      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17507      // GIR_Coverage, 1833,
17508      GIR_Done,
17509    // Label 1069: @42150
17510    GIM_Try, /*On fail goto*//*Label 1070*/ 42231, // Rule ID 2177 //
17511      GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
17512      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
17513      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17514      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17515      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
17516      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17517      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
17518      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
17519      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
17520      // MIs[1] Operand 1
17521      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
17522      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
17523      GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0,
17524      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
17525      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
17526      GIM_CheckIsSafeToFold, /*InsnID*/1,
17527      // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F)
17528      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_MM,
17529      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
17530      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
17531      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
17532      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
17533      GIR_EraseFromParent, /*InsnID*/0,
17534      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17535      // GIR_Coverage, 2177,
17536      GIR_Done,
17537    // Label 1070: @42231
17538    GIM_Try, /*On fail goto*//*Label 1071*/ 42312, // Rule ID 2181 //
17539      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotMips32r6_NotMips64r6,
17540      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
17541      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17542      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17543      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
17544      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17545      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
17546      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
17547      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
17548      // MIs[1] Operand 1
17549      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
17550      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
17551      GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0,
17552      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
17553      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
17554      GIM_CheckIsSafeToFold, /*InsnID*/1,
17555      // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F)
17556      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_MM,
17557      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
17558      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
17559      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
17560      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
17561      GIR_EraseFromParent, /*InsnID*/0,
17562      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17563      // GIR_Coverage, 2181,
17564      GIR_Done,
17565    // Label 1071: @42312
17566    GIM_Try, /*On fail goto*//*Label 1072*/ 42393, // Rule ID 2191 //
17567      GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
17568      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
17569      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17570      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17571      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
17572      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17573      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
17574      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
17575      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
17576      // MIs[1] Operand 1
17577      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
17578      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
17579      GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0,
17580      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
17581      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
17582      GIM_CheckIsSafeToFold, /*InsnID*/1,
17583      // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F)
17584      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_MM,
17585      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
17586      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
17587      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
17588      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
17589      GIR_EraseFromParent, /*InsnID*/0,
17590      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17591      // GIR_Coverage, 2191,
17592      GIR_Done,
17593    // Label 1072: @42393
17594    GIM_Try, /*On fail goto*//*Label 1073*/ 42474, // Rule ID 2195 //
17595      GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
17596      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
17597      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17598      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17599      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
17600      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17601      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
17602      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
17603      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
17604      // MIs[1] Operand 1
17605      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
17606      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
17607      GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0,
17608      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
17609      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
17610      GIM_CheckIsSafeToFold, /*InsnID*/1,
17611      // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F)
17612      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_MM,
17613      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
17614      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
17615      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
17616      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
17617      GIR_EraseFromParent, /*InsnID*/0,
17618      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17619      // GIR_Coverage, 2195,
17620      GIR_Done,
17621    // Label 1073: @42474
17622    GIM_Try, /*On fail goto*//*Label 1074*/ 42555, // Rule ID 2223 //
17623      GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
17624      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
17625      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17626      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17627      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
17628      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17629      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
17630      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
17631      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
17632      // MIs[1] Operand 1
17633      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
17634      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
17635      GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0,
17636      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
17637      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
17638      GIM_CheckIsSafeToFold, /*InsnID*/1,
17639      // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$lhs, FGR32:{ *:[f32] }:$F)
17640      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S_MM,
17641      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
17642      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
17643      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
17644      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
17645      GIR_EraseFromParent, /*InsnID*/0,
17646      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17647      // GIR_Coverage, 2223,
17648      GIR_Done,
17649    // Label 1074: @42555
17650    GIM_Try, /*On fail goto*//*Label 1075*/ 42636, // Rule ID 2226 //
17651      GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
17652      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
17653      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17654      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17655      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
17656      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17657      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
17658      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
17659      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
17660      // MIs[1] Operand 1
17661      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
17662      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
17663      GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0,
17664      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
17665      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
17666      GIM_CheckIsSafeToFold, /*InsnID*/1,
17667      // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVN_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$lhs, FGR32:{ *:[f32] }:$F)
17668      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_S_MM,
17669      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
17670      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
17671      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
17672      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
17673      GIR_EraseFromParent, /*InsnID*/0,
17674      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17675      // GIR_Coverage, 2226,
17676      GIR_Done,
17677    // Label 1075: @42636
17678    GIM_Try, /*On fail goto*//*Label 1076*/ 42737, // Rule ID 1596 //
17679      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
17680      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
17681      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17682      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17683      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
17684      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17685      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
17686      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
17687      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
17688      // MIs[1] Operand 1
17689      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
17690      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
17691      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
17692      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
17693      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
17694      GIM_CheckIsSafeToFold, /*InsnID*/1,
17695      // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
17696      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17697      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT,
17698      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
17699      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
17700      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
17701      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17702      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I,
17703      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
17704      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
17705      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
17706      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
17707      GIR_EraseFromParent, /*InsnID*/0,
17708      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17709      // GIR_Coverage, 1596,
17710      GIR_Done,
17711    // Label 1076: @42737
17712    GIM_Try, /*On fail goto*//*Label 1077*/ 42838, // Rule ID 1597 //
17713      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
17714      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
17715      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17716      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17717      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
17718      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17719      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
17720      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
17721      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
17722      // MIs[1] Operand 1
17723      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
17724      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
17725      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
17726      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
17727      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
17728      GIM_CheckIsSafeToFold, /*InsnID*/1,
17729      // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
17730      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17731      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu,
17732      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
17733      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
17734      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
17735      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17736      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I,
17737      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
17738      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
17739      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
17740      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
17741      GIR_EraseFromParent, /*InsnID*/0,
17742      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17743      // GIR_Coverage, 1597,
17744      GIR_Done,
17745    // Label 1077: @42838
17746    GIM_Try, /*On fail goto*//*Label 1078*/ 42939, // Rule ID 1600 //
17747      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
17748      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
17749      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17750      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17751      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
17752      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17753      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
17754      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
17755      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
17756      // MIs[1] Operand 1
17757      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
17758      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
17759      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
17760      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
17761      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
17762      GIM_CheckIsSafeToFold, /*InsnID*/1,
17763      // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F)
17764      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17765      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT,
17766      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
17767      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
17768      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
17769      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17770      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I,
17771      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
17772      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
17773      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
17774      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
17775      GIR_EraseFromParent, /*InsnID*/0,
17776      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17777      // GIR_Coverage, 1600,
17778      GIR_Done,
17779    // Label 1078: @42939
17780    GIM_Try, /*On fail goto*//*Label 1079*/ 43040, // Rule ID 1601 //
17781      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
17782      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
17783      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17784      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17785      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
17786      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17787      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
17788      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
17789      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
17790      // MIs[1] Operand 1
17791      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
17792      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
17793      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
17794      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
17795      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
17796      GIM_CheckIsSafeToFold, /*InsnID*/1,
17797      // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F)
17798      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17799      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu,
17800      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
17801      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
17802      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
17803      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17804      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I,
17805      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
17806      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
17807      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
17808      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
17809      GIR_EraseFromParent, /*InsnID*/0,
17810      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17811      // GIR_Coverage, 1601,
17812      GIR_Done,
17813    // Label 1079: @43040
17814    GIM_Try, /*On fail goto*//*Label 1080*/ 43141, // Rule ID 1604 //
17815      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
17816      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
17817      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17818      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17819      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
17820      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17821      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
17822      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
17823      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
17824      // MIs[1] Operand 1
17825      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
17826      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
17827      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
17828      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
17829      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
17830      GIM_CheckIsSafeToFold, /*InsnID*/1,
17831      // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
17832      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17833      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR,
17834      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
17835      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
17836      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
17837      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17838      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I,
17839      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
17840      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
17841      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
17842      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
17843      GIR_EraseFromParent, /*InsnID*/0,
17844      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17845      // GIR_Coverage, 1604,
17846      GIR_Done,
17847    // Label 1080: @43141
17848    GIM_Try, /*On fail goto*//*Label 1081*/ 43242, // Rule ID 1607 //
17849      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
17850      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
17851      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17852      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17853      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
17854      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17855      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
17856      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
17857      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
17858      // MIs[1] Operand 1
17859      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
17860      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
17861      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
17862      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
17863      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
17864      GIM_CheckIsSafeToFold, /*InsnID*/1,
17865      // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVN_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
17866      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17867      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR,
17868      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
17869      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
17870      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
17871      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17872      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_I,
17873      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
17874      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
17875      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
17876      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
17877      GIR_EraseFromParent, /*InsnID*/0,
17878      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17879      // GIR_Coverage, 1607,
17880      GIR_Done,
17881    // Label 1081: @43242
17882    GIM_Try, /*On fail goto*//*Label 1082*/ 43343, // Rule ID 1618 //
17883      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
17884      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
17885      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17886      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17887      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
17888      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17889      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
17890      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
17891      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
17892      // MIs[1] Operand 1
17893      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
17894      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
17895      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
17896      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
17897      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
17898      GIM_CheckIsSafeToFold, /*InsnID*/1,
17899      // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR32:{ *:[i32] }:$F)
17900      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17901      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT64,
17902      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
17903      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
17904      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
17905      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17906      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I,
17907      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
17908      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
17909      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
17910      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
17911      GIR_EraseFromParent, /*InsnID*/0,
17912      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17913      // GIR_Coverage, 1618,
17914      GIR_Done,
17915    // Label 1082: @43343
17916    GIM_Try, /*On fail goto*//*Label 1083*/ 43444, // Rule ID 1619 //
17917      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
17918      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
17919      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17920      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17921      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
17922      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17923      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
17924      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
17925      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
17926      // MIs[1] Operand 1
17927      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
17928      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
17929      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
17930      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
17931      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
17932      GIM_CheckIsSafeToFold, /*InsnID*/1,
17933      // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR32:{ *:[i32] }:$F)
17934      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17935      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu64,
17936      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
17937      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
17938      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
17939      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17940      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I,
17941      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
17942      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
17943      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
17944      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
17945      GIR_EraseFromParent, /*InsnID*/0,
17946      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17947      // GIR_Coverage, 1619,
17948      GIR_Done,
17949    // Label 1083: @43444
17950    GIM_Try, /*On fail goto*//*Label 1084*/ 43545, // Rule ID 1622 //
17951      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
17952      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
17953      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17954      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17955      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
17956      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17957      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
17958      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
17959      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
17960      // MIs[1] Operand 1
17961      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
17962      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
17963      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
17964      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
17965      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
17966      GIM_CheckIsSafeToFold, /*InsnID*/1,
17967      // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), GPR32:{ *:[i32] }:$F)
17968      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17969      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT64,
17970      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
17971      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
17972      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
17973      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17974      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I,
17975      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
17976      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
17977      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
17978      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
17979      GIR_EraseFromParent, /*InsnID*/0,
17980      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17981      // GIR_Coverage, 1622,
17982      GIR_Done,
17983    // Label 1084: @43545
17984    GIM_Try, /*On fail goto*//*Label 1085*/ 43646, // Rule ID 1623 //
17985      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
17986      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
17987      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17988      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17989      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
17990      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17991      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
17992      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
17993      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
17994      // MIs[1] Operand 1
17995      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
17996      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
17997      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
17998      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
17999      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
18000      GIM_CheckIsSafeToFold, /*InsnID*/1,
18001      // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), GPR32:{ *:[i32] }:$F)
18002      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18003      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu64,
18004      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
18005      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
18006      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18007      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18008      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I,
18009      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
18010      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
18011      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
18012      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
18013      GIR_EraseFromParent, /*InsnID*/0,
18014      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18015      // GIR_Coverage, 1623,
18016      GIR_Done,
18017    // Label 1085: @43646
18018    GIM_Try, /*On fail goto*//*Label 1086*/ 43747, // Rule ID 1636 //
18019      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
18020      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
18021      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18022      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18023      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
18024      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18025      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
18026      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
18027      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
18028      // MIs[1] Operand 1
18029      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
18030      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
18031      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
18032      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
18033      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
18034      GIM_CheckIsSafeToFold, /*InsnID*/1,
18035      // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I64_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR32:{ *:[i32] }:$F)
18036      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
18037      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR64,
18038      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
18039      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18040      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
18041      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18042      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I64_I,
18043      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
18044      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
18045      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
18046      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
18047      GIR_EraseFromParent, /*InsnID*/0,
18048      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18049      // GIR_Coverage, 1636,
18050      GIR_Done,
18051    // Label 1086: @43747
18052    GIM_Try, /*On fail goto*//*Label 1087*/ 43848, // Rule ID 1646 //
18053      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
18054      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
18055      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18056      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18057      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
18058      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18059      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
18060      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
18061      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
18062      // MIs[1] Operand 1
18063      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
18064      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
18065      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
18066      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
18067      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
18068      GIM_CheckIsSafeToFold, /*InsnID*/1,
18069      // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVN_I64_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR32:{ *:[i32] }:$F)
18070      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
18071      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR64,
18072      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
18073      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18074      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
18075      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18076      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_I,
18077      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
18078      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
18079      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
18080      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
18081      GIR_EraseFromParent, /*InsnID*/0,
18082      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18083      // GIR_Coverage, 1646,
18084      GIR_Done,
18085    // Label 1087: @43848
18086    GIM_Try, /*On fail goto*//*Label 1088*/ 43949, // Rule ID 1652 //
18087      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
18088      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
18089      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18090      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18091      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
18092      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18093      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
18094      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
18095      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18096      // MIs[1] Operand 1
18097      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
18098      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
18099      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
18100      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
18101      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
18102      GIM_CheckIsSafeToFold, /*InsnID*/1,
18103      // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
18104      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18105      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT,
18106      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
18107      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18108      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
18109      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18110      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S,
18111      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
18112      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
18113      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
18114      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
18115      GIR_EraseFromParent, /*InsnID*/0,
18116      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18117      // GIR_Coverage, 1652,
18118      GIR_Done,
18119    // Label 1088: @43949
18120    GIM_Try, /*On fail goto*//*Label 1089*/ 44050, // Rule ID 1653 //
18121      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
18122      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
18123      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18124      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18125      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
18126      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18127      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
18128      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
18129      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18130      // MIs[1] Operand 1
18131      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
18132      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
18133      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
18134      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
18135      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
18136      GIM_CheckIsSafeToFold, /*InsnID*/1,
18137      // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
18138      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18139      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu,
18140      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
18141      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18142      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
18143      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18144      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S,
18145      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
18146      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
18147      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
18148      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
18149      GIR_EraseFromParent, /*InsnID*/0,
18150      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18151      // GIR_Coverage, 1653,
18152      GIR_Done,
18153    // Label 1089: @44050
18154    GIM_Try, /*On fail goto*//*Label 1090*/ 44151, // Rule ID 1656 //
18155      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
18156      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
18157      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18158      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18159      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
18160      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18161      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
18162      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
18163      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18164      // MIs[1] Operand 1
18165      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
18166      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
18167      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
18168      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
18169      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
18170      GIM_CheckIsSafeToFold, /*InsnID*/1,
18171      // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR32:{ *:[f32] }:$F)
18172      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18173      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT,
18174      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
18175      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
18176      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18177      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18178      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S,
18179      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
18180      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
18181      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
18182      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
18183      GIR_EraseFromParent, /*InsnID*/0,
18184      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18185      // GIR_Coverage, 1656,
18186      GIR_Done,
18187    // Label 1090: @44151
18188    GIM_Try, /*On fail goto*//*Label 1091*/ 44252, // Rule ID 1657 //
18189      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
18190      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
18191      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18192      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18193      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
18194      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18195      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
18196      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
18197      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18198      // MIs[1] Operand 1
18199      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
18200      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
18201      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
18202      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
18203      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
18204      GIM_CheckIsSafeToFold, /*InsnID*/1,
18205      // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR32:{ *:[f32] }:$F)
18206      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18207      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu,
18208      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
18209      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
18210      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18211      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18212      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S,
18213      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
18214      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
18215      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
18216      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
18217      GIR_EraseFromParent, /*InsnID*/0,
18218      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18219      // GIR_Coverage, 1657,
18220      GIR_Done,
18221    // Label 1091: @44252
18222    GIM_Try, /*On fail goto*//*Label 1092*/ 44353, // Rule ID 1660 //
18223      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
18224      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
18225      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18226      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18227      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
18228      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18229      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
18230      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
18231      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18232      // MIs[1] Operand 1
18233      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
18234      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
18235      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
18236      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
18237      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
18238      GIM_CheckIsSafeToFold, /*InsnID*/1,
18239      // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
18240      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18241      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR,
18242      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
18243      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18244      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
18245      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18246      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S,
18247      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
18248      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
18249      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
18250      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
18251      GIR_EraseFromParent, /*InsnID*/0,
18252      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18253      // GIR_Coverage, 1660,
18254      GIR_Done,
18255    // Label 1092: @44353
18256    GIM_Try, /*On fail goto*//*Label 1093*/ 44454, // Rule ID 1662 //
18257      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
18258      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
18259      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18260      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18261      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
18262      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18263      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
18264      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
18265      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18266      // MIs[1] Operand 1
18267      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
18268      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
18269      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
18270      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
18271      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
18272      GIM_CheckIsSafeToFold, /*InsnID*/1,
18273      // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVN_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
18274      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18275      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR,
18276      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
18277      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18278      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
18279      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18280      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_S,
18281      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
18282      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
18283      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
18284      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
18285      GIR_EraseFromParent, /*InsnID*/0,
18286      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18287      // GIR_Coverage, 1662,
18288      GIR_Done,
18289    // Label 1093: @44454
18290    GIM_Try, /*On fail goto*//*Label 1094*/ 44555, // Rule ID 1665 //
18291      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
18292      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
18293      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18294      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18295      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
18296      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18297      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
18298      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
18299      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
18300      // MIs[1] Operand 1
18301      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
18302      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
18303      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
18304      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
18305      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
18306      GIM_CheckIsSafeToFold, /*InsnID*/1,
18307      // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR32:{ *:[f32] }:$F)
18308      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18309      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT64,
18310      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
18311      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18312      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
18313      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18314      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S,
18315      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
18316      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
18317      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
18318      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
18319      GIR_EraseFromParent, /*InsnID*/0,
18320      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18321      // GIR_Coverage, 1665,
18322      GIR_Done,
18323    // Label 1094: @44555
18324    GIM_Try, /*On fail goto*//*Label 1095*/ 44656, // Rule ID 1666 //
18325      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
18326      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
18327      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18328      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18329      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
18330      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18331      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
18332      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
18333      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
18334      // MIs[1] Operand 1
18335      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
18336      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
18337      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
18338      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
18339      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
18340      GIM_CheckIsSafeToFold, /*InsnID*/1,
18341      // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR32:{ *:[f32] }:$F)
18342      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18343      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu64,
18344      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
18345      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18346      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
18347      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18348      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S,
18349      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
18350      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
18351      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
18352      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
18353      GIR_EraseFromParent, /*InsnID*/0,
18354      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18355      // GIR_Coverage, 1666,
18356      GIR_Done,
18357    // Label 1095: @44656
18358    GIM_Try, /*On fail goto*//*Label 1096*/ 44757, // Rule ID 1669 //
18359      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
18360      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
18361      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18362      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18363      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
18364      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18365      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
18366      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
18367      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
18368      // MIs[1] Operand 1
18369      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
18370      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
18371      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
18372      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
18373      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
18374      GIM_CheckIsSafeToFold, /*InsnID*/1,
18375      // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), FGR32:{ *:[f32] }:$F)
18376      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18377      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT64,
18378      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
18379      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
18380      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18381      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18382      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S,
18383      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
18384      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
18385      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
18386      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
18387      GIR_EraseFromParent, /*InsnID*/0,
18388      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18389      // GIR_Coverage, 1669,
18390      GIR_Done,
18391    // Label 1096: @44757
18392    GIM_Try, /*On fail goto*//*Label 1097*/ 44858, // Rule ID 1670 //
18393      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
18394      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
18395      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18396      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18397      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
18398      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18399      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
18400      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
18401      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
18402      // MIs[1] Operand 1
18403      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
18404      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
18405      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
18406      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
18407      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
18408      GIM_CheckIsSafeToFold, /*InsnID*/1,
18409      // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), FGR32:{ *:[f32] }:$F)
18410      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18411      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu64,
18412      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
18413      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
18414      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18415      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18416      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S,
18417      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
18418      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
18419      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
18420      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
18421      GIR_EraseFromParent, /*InsnID*/0,
18422      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18423      // GIR_Coverage, 1670,
18424      GIR_Done,
18425    // Label 1097: @44858
18426    GIM_Try, /*On fail goto*//*Label 1098*/ 44959, // Rule ID 1673 //
18427      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
18428      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
18429      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18430      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18431      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
18432      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18433      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
18434      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
18435      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
18436      // MIs[1] Operand 1
18437      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
18438      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
18439      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
18440      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
18441      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
18442      GIM_CheckIsSafeToFold, /*InsnID*/1,
18443      // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVZ_I64_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR32:{ *:[f32] }:$F)
18444      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
18445      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR64,
18446      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
18447      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18448      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
18449      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18450      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I64_S,
18451      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
18452      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
18453      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
18454      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
18455      GIR_EraseFromParent, /*InsnID*/0,
18456      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18457      // GIR_Coverage, 1673,
18458      GIR_Done,
18459    // Label 1098: @44959
18460    GIM_Try, /*On fail goto*//*Label 1099*/ 45060, // Rule ID 1675 //
18461      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
18462      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
18463      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18464      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18465      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
18466      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18467      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
18468      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
18469      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
18470      // MIs[1] Operand 1
18471      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
18472      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
18473      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
18474      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
18475      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
18476      GIM_CheckIsSafeToFold, /*InsnID*/1,
18477      // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVN_I64_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR32:{ *:[f32] }:$F)
18478      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
18479      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR64,
18480      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
18481      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18482      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
18483      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18484      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_S,
18485      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
18486      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
18487      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
18488      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
18489      GIR_EraseFromParent, /*InsnID*/0,
18490      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18491      // GIR_Coverage, 1675,
18492      GIR_Done,
18493    // Label 1099: @45060
18494    GIM_Try, /*On fail goto*//*Label 1100*/ 45145, // Rule ID 1822 //
18495      GIM_CheckFeatures, GIFBS_InMips16Mode,
18496      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
18497      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18498      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18499      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
18500      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18501      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
18502      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
18503      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18504      // MIs[1] Operand 1
18505      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
18506      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
18507      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID,
18508      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
18509      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID,
18510      GIM_CheckIsSafeToFold, /*InsnID*/1,
18511      // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETGE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y)  =>  (SelTBteqZSlt:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b)
18512      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SelTBteqZSlt,
18513      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd_
18514      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // x
18515      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // y
18516      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
18517      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
18518      GIR_EraseFromParent, /*InsnID*/0,
18519      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18520      // GIR_Coverage, 1822,
18521      GIR_Done,
18522    // Label 1100: @45145
18523    GIM_Try, /*On fail goto*//*Label 1101*/ 45230, // Rule ID 1823 //
18524      GIM_CheckFeatures, GIFBS_InMips16Mode,
18525      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
18526      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18527      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18528      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
18529      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18530      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
18531      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
18532      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18533      // MIs[1] Operand 1
18534      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT,
18535      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
18536      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID,
18537      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
18538      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID,
18539      GIM_CheckIsSafeToFold, /*InsnID*/1,
18540      // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETGT:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y)  =>  (SelTBtneZSlt:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a)
18541      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SelTBtneZSlt,
18542      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd_
18543      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // x
18544      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // y
18545      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
18546      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
18547      GIR_EraseFromParent, /*InsnID*/0,
18548      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18549      // GIR_Coverage, 1823,
18550      GIR_Done,
18551    // Label 1101: @45230
18552    GIM_Try, /*On fail goto*//*Label 1102*/ 45315, // Rule ID 1824 //
18553      GIM_CheckFeatures, GIFBS_InMips16Mode,
18554      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
18555      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18556      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18557      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
18558      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18559      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
18560      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
18561      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18562      // MIs[1] Operand 1
18563      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
18564      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
18565      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID,
18566      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
18567      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID,
18568      GIM_CheckIsSafeToFold, /*InsnID*/1,
18569      // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETUGE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y)  =>  (SelTBteqZSltu:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b)
18570      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SelTBteqZSltu,
18571      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd_
18572      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // x
18573      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // y
18574      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
18575      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
18576      GIR_EraseFromParent, /*InsnID*/0,
18577      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18578      // GIR_Coverage, 1824,
18579      GIR_Done,
18580    // Label 1102: @45315
18581    GIM_Try, /*On fail goto*//*Label 1103*/ 45400, // Rule ID 1825 //
18582      GIM_CheckFeatures, GIFBS_InMips16Mode,
18583      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
18584      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18585      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18586      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
18587      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18588      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
18589      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
18590      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18591      // MIs[1] Operand 1
18592      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT,
18593      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
18594      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID,
18595      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
18596      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID,
18597      GIM_CheckIsSafeToFold, /*InsnID*/1,
18598      // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETUGT:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y)  =>  (SelTBtneZSltu:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a)
18599      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SelTBtneZSltu,
18600      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd_
18601      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // x
18602      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // y
18603      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
18604      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
18605      GIR_EraseFromParent, /*InsnID*/0,
18606      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18607      // GIR_Coverage, 1825,
18608      GIR_Done,
18609    // Label 1103: @45400
18610    GIM_Try, /*On fail goto*//*Label 1104*/ 45485, // Rule ID 1827 //
18611      GIM_CheckFeatures, GIFBS_InMips16Mode,
18612      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
18613      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18614      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18615      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
18616      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18617      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
18618      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
18619      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18620      // MIs[1] Operand 1
18621      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
18622      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
18623      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID,
18624      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
18625      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID,
18626      GIM_CheckIsSafeToFold, /*InsnID*/1,
18627      // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETLE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y)  =>  (SelTBteqZSlt:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a)
18628      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SelTBteqZSlt,
18629      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd_
18630      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // x
18631      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // y
18632      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
18633      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
18634      GIR_EraseFromParent, /*InsnID*/0,
18635      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18636      // GIR_Coverage, 1827,
18637      GIR_Done,
18638    // Label 1104: @45485
18639    GIM_Try, /*On fail goto*//*Label 1105*/ 45570, // Rule ID 1828 //
18640      GIM_CheckFeatures, GIFBS_InMips16Mode,
18641      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
18642      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18643      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18644      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
18645      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18646      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
18647      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
18648      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18649      // MIs[1] Operand 1
18650      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
18651      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
18652      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID,
18653      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
18654      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID,
18655      GIM_CheckIsSafeToFold, /*InsnID*/1,
18656      // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETULE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y)  =>  (SelTBteqZSltu:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a)
18657      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SelTBteqZSltu,
18658      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd_
18659      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // x
18660      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // y
18661      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
18662      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
18663      GIR_EraseFromParent, /*InsnID*/0,
18664      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18665      // GIR_Coverage, 1828,
18666      GIR_Done,
18667    // Label 1105: @45570
18668    GIM_Try, /*On fail goto*//*Label 1106*/ 45655, // Rule ID 1829 //
18669      GIM_CheckFeatures, GIFBS_InMips16Mode,
18670      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
18671      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18672      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18673      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
18674      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18675      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
18676      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
18677      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18678      // MIs[1] Operand 1
18679      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
18680      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
18681      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID,
18682      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
18683      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID,
18684      GIM_CheckIsSafeToFold, /*InsnID*/1,
18685      // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETEQ:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y)  =>  (SelTBteqZCmp:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a)
18686      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SelTBteqZCmp,
18687      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd_
18688      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // x
18689      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // y
18690      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
18691      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
18692      GIR_EraseFromParent, /*InsnID*/0,
18693      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18694      // GIR_Coverage, 1829,
18695      GIR_Done,
18696    // Label 1106: @45655
18697    GIM_Try, /*On fail goto*//*Label 1107*/ 45740, // Rule ID 1832 //
18698      GIM_CheckFeatures, GIFBS_InMips16Mode,
18699      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
18700      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18701      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18702      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
18703      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18704      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
18705      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
18706      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18707      // MIs[1] Operand 1
18708      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
18709      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
18710      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID,
18711      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
18712      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID,
18713      GIM_CheckIsSafeToFold, /*InsnID*/1,
18714      // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETNE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y)  =>  (SelTBtneZCmp:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a)
18715      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SelTBtneZCmp,
18716      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd_
18717      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // x
18718      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // y
18719      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
18720      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
18721      GIR_EraseFromParent, /*InsnID*/0,
18722      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18723      // GIR_Coverage, 1832,
18724      GIR_Done,
18725    // Label 1107: @45740
18726    GIM_Try, /*On fail goto*//*Label 1108*/ 45841, // Rule ID 2168 //
18727      GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
18728      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
18729      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18730      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18731      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
18732      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18733      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
18734      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
18735      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18736      // MIs[1] Operand 1
18737      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
18738      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
18739      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
18740      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
18741      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
18742      GIM_CheckIsSafeToFold, /*InsnID*/1,
18743      // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
18744      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18745      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT_MM,
18746      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
18747      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18748      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
18749      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18750      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_MM,
18751      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
18752      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
18753      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
18754      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
18755      GIR_EraseFromParent, /*InsnID*/0,
18756      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18757      // GIR_Coverage, 2168,
18758      GIR_Done,
18759    // Label 1108: @45841
18760    GIM_Try, /*On fail goto*//*Label 1109*/ 45942, // Rule ID 2169 //
18761      GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
18762      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
18763      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18764      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18765      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
18766      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18767      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
18768      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
18769      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18770      // MIs[1] Operand 1
18771      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
18772      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
18773      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
18774      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
18775      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
18776      GIM_CheckIsSafeToFold, /*InsnID*/1,
18777      // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
18778      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18779      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu_MM,
18780      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
18781      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18782      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
18783      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18784      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_MM,
18785      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
18786      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
18787      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
18788      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
18789      GIR_EraseFromParent, /*InsnID*/0,
18790      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18791      // GIR_Coverage, 2169,
18792      GIR_Done,
18793    // Label 1109: @45942
18794    GIM_Try, /*On fail goto*//*Label 1110*/ 46043, // Rule ID 2172 //
18795      GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
18796      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
18797      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18798      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18799      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
18800      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18801      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
18802      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
18803      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18804      // MIs[1] Operand 1
18805      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
18806      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
18807      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
18808      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
18809      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
18810      GIM_CheckIsSafeToFold, /*InsnID*/1,
18811      // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F)
18812      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18813      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT_MM,
18814      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
18815      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
18816      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18817      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18818      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_MM,
18819      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
18820      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
18821      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
18822      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
18823      GIR_EraseFromParent, /*InsnID*/0,
18824      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18825      // GIR_Coverage, 2172,
18826      GIR_Done,
18827    // Label 1110: @46043
18828    GIM_Try, /*On fail goto*//*Label 1111*/ 46144, // Rule ID 2173 //
18829      GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
18830      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
18831      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18832      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18833      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
18834      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18835      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
18836      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
18837      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18838      // MIs[1] Operand 1
18839      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
18840      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
18841      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
18842      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
18843      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
18844      GIM_CheckIsSafeToFold, /*InsnID*/1,
18845      // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F)
18846      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18847      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu_MM,
18848      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
18849      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
18850      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18851      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18852      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_MM,
18853      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
18854      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
18855      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
18856      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
18857      GIR_EraseFromParent, /*InsnID*/0,
18858      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18859      // GIR_Coverage, 2173,
18860      GIR_Done,
18861    // Label 1111: @46144
18862    GIM_Try, /*On fail goto*//*Label 1112*/ 46245, // Rule ID 2176 //
18863      GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
18864      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
18865      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18866      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18867      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
18868      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18869      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
18870      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
18871      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18872      // MIs[1] Operand 1
18873      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
18874      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
18875      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
18876      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
18877      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
18878      GIM_CheckIsSafeToFold, /*InsnID*/1,
18879      // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
18880      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18881      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR_MM,
18882      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
18883      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18884      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
18885      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18886      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_MM,
18887      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
18888      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
18889      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
18890      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
18891      GIR_EraseFromParent, /*InsnID*/0,
18892      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18893      // GIR_Coverage, 2176,
18894      GIR_Done,
18895    // Label 1112: @46245
18896    GIM_Try, /*On fail goto*//*Label 1113*/ 46346, // Rule ID 2179 //
18897      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotMips32r6_NotMips64r6,
18898      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
18899      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18900      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18901      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
18902      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18903      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
18904      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
18905      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18906      // MIs[1] Operand 1
18907      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
18908      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
18909      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
18910      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
18911      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
18912      GIM_CheckIsSafeToFold, /*InsnID*/1,
18913      // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
18914      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18915      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR_MM,
18916      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
18917      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18918      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
18919      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18920      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_MM,
18921      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
18922      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
18923      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
18924      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
18925      GIR_EraseFromParent, /*InsnID*/0,
18926      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18927      // GIR_Coverage, 2179,
18928      GIR_Done,
18929    // Label 1113: @46346
18930    GIM_Try, /*On fail goto*//*Label 1114*/ 46447, // Rule ID 2182 //
18931      GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
18932      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
18933      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18934      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18935      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
18936      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18937      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
18938      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
18939      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18940      // MIs[1] Operand 1
18941      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
18942      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
18943      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
18944      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
18945      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
18946      GIM_CheckIsSafeToFold, /*InsnID*/1,
18947      // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
18948      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18949      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT_MM,
18950      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
18951      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18952      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
18953      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18954      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_MM,
18955      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
18956      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
18957      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
18958      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
18959      GIR_EraseFromParent, /*InsnID*/0,
18960      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18961      // GIR_Coverage, 2182,
18962      GIR_Done,
18963    // Label 1114: @46447
18964    GIM_Try, /*On fail goto*//*Label 1115*/ 46548, // Rule ID 2183 //
18965      GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
18966      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
18967      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18968      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18969      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
18970      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18971      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
18972      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
18973      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18974      // MIs[1] Operand 1
18975      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
18976      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
18977      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
18978      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
18979      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
18980      GIM_CheckIsSafeToFold, /*InsnID*/1,
18981      // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
18982      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18983      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu_MM,
18984      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
18985      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18986      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
18987      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18988      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_MM,
18989      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
18990      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
18991      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
18992      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
18993      GIR_EraseFromParent, /*InsnID*/0,
18994      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18995      // GIR_Coverage, 2183,
18996      GIR_Done,
18997    // Label 1115: @46548
18998    GIM_Try, /*On fail goto*//*Label 1116*/ 46649, // Rule ID 2186 //
18999      GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
19000      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19001      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19002      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19003      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
19004      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19005      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
19006      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19007      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19008      // MIs[1] Operand 1
19009      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
19010      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
19011      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
19012      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
19013      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
19014      GIM_CheckIsSafeToFold, /*InsnID*/1,
19015      // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F)
19016      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19017      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT_MM,
19018      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
19019      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19020      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19021      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19022      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_MM,
19023      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
19024      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
19025      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
19026      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
19027      GIR_EraseFromParent, /*InsnID*/0,
19028      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19029      // GIR_Coverage, 2186,
19030      GIR_Done,
19031    // Label 1116: @46649
19032    GIM_Try, /*On fail goto*//*Label 1117*/ 46750, // Rule ID 2187 //
19033      GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
19034      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19035      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19036      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19037      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
19038      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19039      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
19040      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19041      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19042      // MIs[1] Operand 1
19043      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
19044      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
19045      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
19046      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
19047      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
19048      GIM_CheckIsSafeToFold, /*InsnID*/1,
19049      // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F)
19050      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19051      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu_MM,
19052      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
19053      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19054      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19055      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19056      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_MM,
19057      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
19058      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
19059      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
19060      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
19061      GIR_EraseFromParent, /*InsnID*/0,
19062      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19063      // GIR_Coverage, 2187,
19064      GIR_Done,
19065    // Label 1117: @46750
19066    GIM_Try, /*On fail goto*//*Label 1118*/ 46851, // Rule ID 2190 //
19067      GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
19068      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19069      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19070      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19071      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
19072      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19073      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
19074      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19075      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19076      // MIs[1] Operand 1
19077      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
19078      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
19079      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
19080      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
19081      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
19082      GIM_CheckIsSafeToFold, /*InsnID*/1,
19083      // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
19084      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19085      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR_MM,
19086      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
19087      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19088      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19089      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19090      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_MM,
19091      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
19092      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
19093      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
19094      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
19095      GIR_EraseFromParent, /*InsnID*/0,
19096      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19097      // GIR_Coverage, 2190,
19098      GIR_Done,
19099    // Label 1118: @46851
19100    GIM_Try, /*On fail goto*//*Label 1119*/ 46952, // Rule ID 2193 //
19101      GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
19102      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19103      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19104      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19105      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
19106      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19107      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
19108      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19109      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19110      // MIs[1] Operand 1
19111      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
19112      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
19113      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
19114      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
19115      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
19116      GIM_CheckIsSafeToFold, /*InsnID*/1,
19117      // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
19118      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19119      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR_MM,
19120      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
19121      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19122      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19123      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19124      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_MM,
19125      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
19126      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
19127      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
19128      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
19129      GIR_EraseFromParent, /*InsnID*/0,
19130      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19131      // GIR_Coverage, 2193,
19132      GIR_Done,
19133    // Label 1119: @46952
19134    GIM_Try, /*On fail goto*//*Label 1120*/ 47053, // Rule ID 2214 //
19135      GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
19136      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19137      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19138      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19139      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
19140      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19141      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
19142      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19143      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19144      // MIs[1] Operand 1
19145      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
19146      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
19147      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
19148      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
19149      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
19150      GIM_CheckIsSafeToFold, /*InsnID*/1,
19151      // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
19152      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19153      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT_MM,
19154      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
19155      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19156      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19157      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19158      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S_MM,
19159      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
19160      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
19161      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
19162      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
19163      GIR_EraseFromParent, /*InsnID*/0,
19164      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19165      // GIR_Coverage, 2214,
19166      GIR_Done,
19167    // Label 1120: @47053
19168    GIM_Try, /*On fail goto*//*Label 1121*/ 47154, // Rule ID 2215 //
19169      GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
19170      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19171      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19172      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19173      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
19174      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19175      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
19176      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19177      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19178      // MIs[1] Operand 1
19179      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
19180      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
19181      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
19182      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
19183      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
19184      GIM_CheckIsSafeToFold, /*InsnID*/1,
19185      // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
19186      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19187      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu_MM,
19188      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
19189      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19190      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19191      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19192      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S_MM,
19193      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
19194      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
19195      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
19196      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
19197      GIR_EraseFromParent, /*InsnID*/0,
19198      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19199      // GIR_Coverage, 2215,
19200      GIR_Done,
19201    // Label 1121: @47154
19202    GIM_Try, /*On fail goto*//*Label 1122*/ 47255, // Rule ID 2218 //
19203      GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
19204      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19205      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19206      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19207      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
19208      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19209      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
19210      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19211      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19212      // MIs[1] Operand 1
19213      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
19214      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
19215      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
19216      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
19217      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
19218      GIM_CheckIsSafeToFold, /*InsnID*/1,
19219      // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR32:{ *:[f32] }:$F)
19220      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19221      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT_MM,
19222      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
19223      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19224      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19225      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19226      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S_MM,
19227      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
19228      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
19229      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
19230      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
19231      GIR_EraseFromParent, /*InsnID*/0,
19232      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19233      // GIR_Coverage, 2218,
19234      GIR_Done,
19235    // Label 1122: @47255
19236    GIM_Try, /*On fail goto*//*Label 1123*/ 47356, // Rule ID 2219 //
19237      GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
19238      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19239      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19240      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19241      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
19242      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19243      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
19244      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19245      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19246      // MIs[1] Operand 1
19247      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
19248      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
19249      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
19250      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
19251      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
19252      GIM_CheckIsSafeToFold, /*InsnID*/1,
19253      // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR32:{ *:[f32] }:$F)
19254      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19255      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu_MM,
19256      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
19257      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19258      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19259      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19260      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S_MM,
19261      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
19262      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
19263      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
19264      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
19265      GIR_EraseFromParent, /*InsnID*/0,
19266      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19267      // GIR_Coverage, 2219,
19268      GIR_Done,
19269    // Label 1123: @47356
19270    GIM_Try, /*On fail goto*//*Label 1124*/ 47457, // Rule ID 2222 //
19271      GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
19272      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19273      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19274      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19275      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
19276      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19277      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
19278      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19279      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19280      // MIs[1] Operand 1
19281      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
19282      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
19283      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
19284      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
19285      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
19286      GIM_CheckIsSafeToFold, /*InsnID*/1,
19287      // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
19288      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19289      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR_MM,
19290      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
19291      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19292      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19293      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19294      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S_MM,
19295      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
19296      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
19297      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
19298      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
19299      GIR_EraseFromParent, /*InsnID*/0,
19300      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19301      // GIR_Coverage, 2222,
19302      GIR_Done,
19303    // Label 1124: @47457
19304    GIM_Try, /*On fail goto*//*Label 1125*/ 47558, // Rule ID 2224 //
19305      GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
19306      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19307      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19308      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19309      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
19310      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19311      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
19312      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19313      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19314      // MIs[1] Operand 1
19315      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
19316      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
19317      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
19318      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
19319      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
19320      GIM_CheckIsSafeToFold, /*InsnID*/1,
19321      // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVN_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
19322      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19323      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR_MM,
19324      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
19325      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19326      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19327      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19328      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_S_MM,
19329      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
19330      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
19331      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
19332      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
19333      GIR_EraseFromParent, /*InsnID*/0,
19334      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19335      // GIR_Coverage, 2224,
19336      GIR_Done,
19337    // Label 1125: @47558
19338    GIM_Try, /*On fail goto*//*Label 1126*/ 47597, // Rule ID 283 //
19339      GIM_CheckFeatures, GIFBS_HasStdEnc_NotMips4_32,
19340      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19341      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19342      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19343      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
19344      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
19345      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
19346      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
19347      // (select:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$cond, GPR32Opnd:{ *:[i32] }:$T, GPR32Opnd:{ *:[i32] }:$F)  =>  (PseudoSELECT_I:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$cond, GPR32Opnd:{ *:[i32] }:$T, GPR32Opnd:{ *:[i32] }:$F)
19348      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PseudoSELECT_I,
19349      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19350      // GIR_Coverage, 283,
19351      GIR_Done,
19352    // Label 1126: @47597
19353    GIM_Try, /*On fail goto*//*Label 1127*/ 47636, // Rule ID 285 //
19354      GIM_CheckFeatures, GIFBS_HasStdEnc_NotMips4_32,
19355      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19356      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19357      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19358      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
19359      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
19360      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
19361      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
19362      // (select:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$cond, FGR32Opnd:{ *:[f32] }:$T, FGR32Opnd:{ *:[f32] }:$F)  =>  (PseudoSELECT_S:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$cond, FGR32Opnd:{ *:[f32] }:$T, FGR32Opnd:{ *:[f32] }:$F)
19363      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PseudoSELECT_S,
19364      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19365      // GIR_Coverage, 285,
19366      GIR_Done,
19367    // Label 1127: @47636
19368    GIM_Try, /*On fail goto*//*Label 1128*/ 47692, // Rule ID 322 //
19369      GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
19370      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19371      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19372      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19373      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
19374      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGRCCRegClassID,
19375      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
19376      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
19377      // (select:{ *:[f32] } FGRCCOpnd:{ *:[i32] }:$fd_in, FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs)  =>  (SEL_S:{ *:[f32] } FGRCCOpnd:{ *:[i32] }:$fd_in, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
19378      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SEL_S,
19379      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
19380      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fd_in
19381      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // fs
19382      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ft
19383      GIR_EraseFromParent, /*InsnID*/0,
19384      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19385      // GIR_Coverage, 322,
19386      GIR_Done,
19387    // Label 1128: @47692
19388    GIM_Try, /*On fail goto*//*Label 1129*/ 47748, // Rule ID 1195 //
19389      GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
19390      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19391      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19392      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19393      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
19394      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGRCCRegClassID,
19395      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
19396      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
19397      // (select:{ *:[f32] } FGRCCOpnd:{ *:[i32] }:$fd_in, FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs)  =>  (SEL_S_MMR6:{ *:[f32] } FGRCCOpnd:{ *:[i32] }:$fd_in, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
19398      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SEL_S_MMR6,
19399      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
19400      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fd_in
19401      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // fs
19402      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ft
19403      GIR_EraseFromParent, /*InsnID*/0,
19404      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19405      // GIR_Coverage, 1195,
19406      GIR_Done,
19407    // Label 1129: @47748
19408    GIM_Try, /*On fail goto*//*Label 1130*/ 47804, // Rule ID 1608 //
19409      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
19410      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19411      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19412      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19413      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
19414      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
19415      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
19416      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
19417      // (select:{ *:[i32] } GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVN_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$F)
19418      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_I,
19419      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
19420      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
19421      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond
19422      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
19423      GIR_EraseFromParent, /*InsnID*/0,
19424      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19425      // GIR_Coverage, 1608,
19426      GIR_Done,
19427    // Label 1130: @47804
19428    GIM_Try, /*On fail goto*//*Label 1131*/ 47860, // Rule ID 1647 //
19429      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
19430      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
19431      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19432      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19433      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
19434      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
19435      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
19436      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
19437      // (select:{ *:[i32] } GPR64:{ *:[i64] }:$cond, GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVN_I64_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR64:{ *:[i64] }:$cond, GPR32:{ *:[i32] }:$F)
19438      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_I,
19439      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
19440      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
19441      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond
19442      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
19443      GIR_EraseFromParent, /*InsnID*/0,
19444      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19445      // GIR_Coverage, 1647,
19446      GIR_Done,
19447    // Label 1131: @47860
19448    GIM_Try, /*On fail goto*//*Label 1132*/ 47916, // Rule ID 1663 //
19449      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
19450      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19451      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19452      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19453      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
19454      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
19455      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
19456      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
19457      // (select:{ *:[f32] } GPR32:{ *:[i32] }:$cond, FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVN_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$cond, FGR32:{ *:[f32] }:$F)
19458      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_S,
19459      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
19460      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
19461      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond
19462      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
19463      GIR_EraseFromParent, /*InsnID*/0,
19464      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19465      // GIR_Coverage, 1663,
19466      GIR_Done,
19467    // Label 1132: @47916
19468    GIM_Try, /*On fail goto*//*Label 1133*/ 47972, // Rule ID 1676 //
19469      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
19470      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
19471      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19472      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19473      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
19474      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
19475      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
19476      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
19477      // (select:{ *:[f32] } GPR64:{ *:[i64] }:$cond, FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVN_I64_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR64:{ *:[i64] }:$cond, FGR32:{ *:[f32] }:$F)
19478      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_S,
19479      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
19480      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
19481      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond
19482      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
19483      GIR_EraseFromParent, /*InsnID*/0,
19484      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19485      // GIR_Coverage, 1676,
19486      GIR_Done,
19487    // Label 1133: @47972
19488    GIM_Try, /*On fail goto*//*Label 1134*/ 48028, // Rule ID 1834 //
19489      GIM_CheckFeatures, GIFBS_InMips16Mode,
19490      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19491      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19492      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19493      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
19494      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
19495      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
19496      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID,
19497      // (select:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y)  =>  (SelBneZ:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$a)
19498      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SelBneZ,
19499      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd_
19500      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // x
19501      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // y
19502      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // a
19503      GIR_EraseFromParent, /*InsnID*/0,
19504      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19505      // GIR_Coverage, 1834,
19506      GIR_Done,
19507    // Label 1134: @48028
19508    GIM_Try, /*On fail goto*//*Label 1135*/ 48084, // Rule ID 2180 //
19509      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotMips32r6_NotMips64r6,
19510      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19511      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19512      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19513      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
19514      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
19515      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
19516      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
19517      // (select:{ *:[i32] } GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$F)
19518      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_MM,
19519      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
19520      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
19521      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond
19522      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
19523      GIR_EraseFromParent, /*InsnID*/0,
19524      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19525      // GIR_Coverage, 2180,
19526      GIR_Done,
19527    // Label 1135: @48084
19528    GIM_Try, /*On fail goto*//*Label 1136*/ 48140, // Rule ID 2194 //
19529      GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
19530      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19531      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19532      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19533      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
19534      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
19535      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
19536      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
19537      // (select:{ *:[i32] } GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$F)
19538      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_MM,
19539      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
19540      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
19541      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond
19542      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
19543      GIR_EraseFromParent, /*InsnID*/0,
19544      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19545      // GIR_Coverage, 2194,
19546      GIR_Done,
19547    // Label 1136: @48140
19548    GIM_Try, /*On fail goto*//*Label 1137*/ 48196, // Rule ID 2225 //
19549      GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
19550      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19551      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19552      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19553      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
19554      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
19555      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
19556      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
19557      // (select:{ *:[f32] } GPR32:{ *:[i32] }:$cond, FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVN_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$cond, FGR32:{ *:[f32] }:$F)
19558      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_S_MM,
19559      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
19560      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
19561      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond
19562      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
19563      GIR_EraseFromParent, /*InsnID*/0,
19564      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19565      // GIR_Coverage, 2225,
19566      GIR_Done,
19567    // Label 1137: @48196
19568    GIM_Try, /*On fail goto*//*Label 1138*/ 48276, // Rule ID 1745 //
19569      GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
19570      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19571      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19572      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19573      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
19574      // (select:{ *:[i32] } i32:{ *:[i32] }:$cond, i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$f)  =>  (OR:{ *:[i32] } (SELNEZ:{ *:[i32] } i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$cond), (SELEQZ:{ *:[i32] } i32:{ *:[i32] }:$f, i32:{ *:[i32] }:$cond))
19575      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19576      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
19577      GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SELEQZ,
19578      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
19579      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // f
19580      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // cond
19581      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
19582      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SELNEZ,
19583      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
19584      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // t
19585      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // cond
19586      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19587      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::OR,
19588      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
19589      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
19590      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
19591      GIR_EraseFromParent, /*InsnID*/0,
19592      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19593      // GIR_Coverage, 1745,
19594      GIR_Done,
19595    // Label 1138: @48276
19596    GIM_Try, /*On fail goto*//*Label 1139*/ 48356, // Rule ID 2242 //
19597      GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
19598      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19599      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19600      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19601      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
19602      // (select:{ *:[i32] } i32:{ *:[i32] }:$cond, i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$f)  =>  (OR_MM:{ *:[i32] } (SELNEZ_MMR6:{ *:[i32] } i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$cond), (SELEQZ_MMR6:{ *:[i32] } i32:{ *:[i32] }:$f, i32:{ *:[i32] }:$cond))
19603      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19604      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
19605      GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SELEQZ_MMR6,
19606      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
19607      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // f
19608      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // cond
19609      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
19610      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SELNEZ_MMR6,
19611      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
19612      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // t
19613      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // cond
19614      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19615      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::OR_MM,
19616      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
19617      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
19618      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
19619      GIR_EraseFromParent, /*InsnID*/0,
19620      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19621      // GIR_Coverage, 2242,
19622      GIR_Done,
19623    // Label 1139: @48356
19624    GIM_Reject,
19625    // Label 1058: @48357
19626    GIM_Try, /*On fail goto*//*Label 1140*/ 48438, // Rule ID 1635 //
19627      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
19628      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19629      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
19630      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
19631      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
19632      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19633      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
19634      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19635      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19636      // MIs[1] Operand 1
19637      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
19638      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
19639      GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0,
19640      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
19641      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
19642      GIM_CheckIsSafeToFold, /*InsnID*/1,
19643      // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F)  =>  (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR32:{ *:[i32] }:$lhs, GPR64:{ *:[i64] }:$F)
19644      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I64,
19645      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
19646      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
19647      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19648      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
19649      GIR_EraseFromParent, /*InsnID*/0,
19650      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19651      // GIR_Coverage, 1635,
19652      GIR_Done,
19653    // Label 1140: @48438
19654    GIM_Try, /*On fail goto*//*Label 1141*/ 48519, // Rule ID 1639 //
19655      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
19656      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19657      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
19658      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
19659      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
19660      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19661      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
19662      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
19663      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
19664      // MIs[1] Operand 1
19665      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
19666      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
19667      GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0,
19668      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
19669      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
19670      GIM_CheckIsSafeToFold, /*InsnID*/1,
19671      // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F)  =>  (MOVZ_I64_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$F)
19672      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I64_I64,
19673      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
19674      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
19675      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19676      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
19677      GIR_EraseFromParent, /*InsnID*/0,
19678      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19679      // GIR_Coverage, 1639,
19680      GIR_Done,
19681    // Label 1141: @48519
19682    GIM_Try, /*On fail goto*//*Label 1142*/ 48600, // Rule ID 1645 //
19683      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
19684      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19685      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
19686      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
19687      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
19688      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19689      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
19690      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19691      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19692      // MIs[1] Operand 1
19693      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
19694      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
19695      GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0,
19696      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
19697      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
19698      GIM_CheckIsSafeToFold, /*InsnID*/1,
19699      // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F)  =>  (MOVN_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR32:{ *:[i32] }:$lhs, GPR64:{ *:[i64] }:$F)
19700      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_I64,
19701      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
19702      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
19703      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19704      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
19705      GIR_EraseFromParent, /*InsnID*/0,
19706      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19707      // GIR_Coverage, 1645,
19708      GIR_Done,
19709    // Label 1142: @48600
19710    GIM_Try, /*On fail goto*//*Label 1143*/ 48681, // Rule ID 1651 //
19711      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
19712      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19713      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
19714      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
19715      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
19716      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19717      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
19718      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
19719      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
19720      // MIs[1] Operand 1
19721      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
19722      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
19723      GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0,
19724      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
19725      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
19726      GIM_CheckIsSafeToFold, /*InsnID*/1,
19727      // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F)  =>  (MOVN_I64_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$F)
19728      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_I64,
19729      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
19730      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
19731      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19732      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
19733      GIR_EraseFromParent, /*InsnID*/0,
19734      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19735      // GIR_Coverage, 1651,
19736      GIR_Done,
19737    // Label 1143: @48681
19738    GIM_Try, /*On fail goto*//*Label 1144*/ 48762, // Rule ID 1687 //
19739      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
19740      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19741      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
19742      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
19743      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
19744      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19745      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
19746      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19747      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19748      // MIs[1] Operand 1
19749      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
19750      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
19751      GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0,
19752      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
19753      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID,
19754      GIM_CheckIsSafeToFold, /*InsnID*/1,
19755      // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F)  =>  (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, AFGR64:{ *:[f64] }:$F)
19756      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D32,
19757      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
19758      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
19759      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19760      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
19761      GIR_EraseFromParent, /*InsnID*/0,
19762      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19763      // GIR_Coverage, 1687,
19764      GIR_Done,
19765    // Label 1144: @48762
19766    GIM_Try, /*On fail goto*//*Label 1145*/ 48843, // Rule ID 1690 //
19767      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
19768      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19769      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
19770      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
19771      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
19772      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19773      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
19774      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19775      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19776      // MIs[1] Operand 1
19777      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
19778      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
19779      GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0,
19780      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
19781      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID,
19782      GIM_CheckIsSafeToFold, /*InsnID*/1,
19783      // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F)  =>  (MOVN_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, AFGR64:{ *:[f64] }:$F)
19784      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_D32,
19785      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
19786      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
19787      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19788      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
19789      GIR_EraseFromParent, /*InsnID*/0,
19790      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19791      // GIR_Coverage, 1690,
19792      GIR_Done,
19793    // Label 1145: @48843
19794    GIM_Try, /*On fail goto*//*Label 1146*/ 48924, // Rule ID 1708 //
19795      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
19796      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19797      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
19798      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
19799      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
19800      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19801      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
19802      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19803      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19804      // MIs[1] Operand 1
19805      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
19806      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
19807      GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0,
19808      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
19809      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
19810      GIM_CheckIsSafeToFold, /*InsnID*/1,
19811      // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F)  =>  (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, FGR64:{ *:[f64] }:$F)
19812      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D64,
19813      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
19814      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
19815      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19816      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
19817      GIR_EraseFromParent, /*InsnID*/0,
19818      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19819      // GIR_Coverage, 1708,
19820      GIR_Done,
19821    // Label 1146: @48924
19822    GIM_Try, /*On fail goto*//*Label 1147*/ 49005, // Rule ID 1710 //
19823      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
19824      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19825      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
19826      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
19827      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
19828      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19829      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
19830      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
19831      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
19832      // MIs[1] Operand 1
19833      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
19834      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
19835      GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0,
19836      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
19837      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
19838      GIM_CheckIsSafeToFold, /*InsnID*/1,
19839      // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F)  =>  (MOVZ_I64_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR64:{ *:[i64] }:$lhs, FGR64:{ *:[f64] }:$F)
19840      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I64_D64,
19841      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
19842      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
19843      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19844      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
19845      GIR_EraseFromParent, /*InsnID*/0,
19846      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19847      // GIR_Coverage, 1710,
19848      GIR_Done,
19849    // Label 1147: @49005
19850    GIM_Try, /*On fail goto*//*Label 1148*/ 49086, // Rule ID 1713 //
19851      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
19852      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19853      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
19854      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
19855      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
19856      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19857      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
19858      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19859      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19860      // MIs[1] Operand 1
19861      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
19862      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
19863      GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0,
19864      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
19865      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
19866      GIM_CheckIsSafeToFold, /*InsnID*/1,
19867      // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F)  =>  (MOVN_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, FGR64:{ *:[f64] }:$F)
19868      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_D64,
19869      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
19870      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
19871      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19872      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
19873      GIR_EraseFromParent, /*InsnID*/0,
19874      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19875      // GIR_Coverage, 1713,
19876      GIR_Done,
19877    // Label 1148: @49086
19878    GIM_Try, /*On fail goto*//*Label 1149*/ 49167, // Rule ID 1716 //
19879      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
19880      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19881      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
19882      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
19883      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
19884      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19885      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
19886      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
19887      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
19888      // MIs[1] Operand 1
19889      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
19890      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
19891      GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0,
19892      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
19893      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
19894      GIM_CheckIsSafeToFold, /*InsnID*/1,
19895      // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F)  =>  (MOVN_I64_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR64:{ *:[i64] }:$lhs, FGR64:{ *:[f64] }:$F)
19896      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_D64,
19897      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
19898      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
19899      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19900      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
19901      GIR_EraseFromParent, /*InsnID*/0,
19902      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19903      // GIR_Coverage, 1716,
19904      GIR_Done,
19905    // Label 1149: @49167
19906    GIM_Try, /*On fail goto*//*Label 1150*/ 49248, // Rule ID 2236 //
19907      GIM_CheckFeatures, GIFBS_InMicroMips_NotFP64bit_NotMips32r6,
19908      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19909      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
19910      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
19911      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
19912      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19913      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
19914      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19915      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19916      // MIs[1] Operand 1
19917      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
19918      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
19919      GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0,
19920      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
19921      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID,
19922      GIM_CheckIsSafeToFold, /*InsnID*/1,
19923      // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F)  =>  (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, AFGR64:{ *:[f64] }:$F)
19924      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D32_MM,
19925      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
19926      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
19927      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19928      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
19929      GIR_EraseFromParent, /*InsnID*/0,
19930      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19931      // GIR_Coverage, 2236,
19932      GIR_Done,
19933    // Label 1150: @49248
19934    GIM_Try, /*On fail goto*//*Label 1151*/ 49329, // Rule ID 2239 //
19935      GIM_CheckFeatures, GIFBS_InMicroMips_NotFP64bit_NotMips32r6,
19936      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19937      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
19938      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
19939      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
19940      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19941      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
19942      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19943      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19944      // MIs[1] Operand 1
19945      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
19946      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
19947      GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0,
19948      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
19949      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID,
19950      GIM_CheckIsSafeToFold, /*InsnID*/1,
19951      // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F)  =>  (MOVN_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, AFGR64:{ *:[f64] }:$F)
19952      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_D32_MM,
19953      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
19954      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
19955      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19956      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
19957      GIR_EraseFromParent, /*InsnID*/0,
19958      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19959      // GIR_Coverage, 2239,
19960      GIR_Done,
19961    // Label 1151: @49329
19962    GIM_Try, /*On fail goto*//*Label 1152*/ 49430, // Rule ID 1610 //
19963      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
19964      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19965      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
19966      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
19967      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
19968      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19969      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
19970      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19971      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19972      // MIs[1] Operand 1
19973      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
19974      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
19975      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
19976      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
19977      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
19978      GIM_CheckIsSafeToFold, /*InsnID*/1,
19979      // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F)  =>  (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR64:{ *:[i64] }:$F)
19980      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19981      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT,
19982      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
19983      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19984      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19985      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19986      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I64,
19987      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
19988      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
19989      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
19990      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
19991      GIR_EraseFromParent, /*InsnID*/0,
19992      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19993      // GIR_Coverage, 1610,
19994      GIR_Done,
19995    // Label 1152: @49430
19996    GIM_Try, /*On fail goto*//*Label 1153*/ 49531, // Rule ID 1611 //
19997      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
19998      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19999      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
20000      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
20001      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
20002      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20003      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
20004      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20005      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20006      // MIs[1] Operand 1
20007      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
20008      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
20009      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
20010      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
20011      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
20012      GIM_CheckIsSafeToFold, /*InsnID*/1,
20013      // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F)  =>  (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR64:{ *:[i64] }:$F)
20014      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20015      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu,
20016      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
20017      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20018      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20019      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20020      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I64,
20021      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
20022      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
20023      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
20024      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
20025      GIR_EraseFromParent, /*InsnID*/0,
20026      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20027      // GIR_Coverage, 1611,
20028      GIR_Done,
20029    // Label 1153: @49531
20030    GIM_Try, /*On fail goto*//*Label 1154*/ 49632, // Rule ID 1614 //
20031      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
20032      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20033      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
20034      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
20035      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
20036      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20037      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
20038      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20039      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20040      // MIs[1] Operand 1
20041      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
20042      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
20043      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
20044      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
20045      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
20046      GIM_CheckIsSafeToFold, /*InsnID*/1,
20047      // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F)  =>  (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR64:{ *:[i64] }:$F)
20048      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20049      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT,
20050      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
20051      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20052      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20053      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20054      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I64,
20055      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
20056      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
20057      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
20058      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
20059      GIR_EraseFromParent, /*InsnID*/0,
20060      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20061      // GIR_Coverage, 1614,
20062      GIR_Done,
20063    // Label 1154: @49632
20064    GIM_Try, /*On fail goto*//*Label 1155*/ 49733, // Rule ID 1615 //
20065      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
20066      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20067      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
20068      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
20069      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
20070      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20071      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
20072      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20073      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20074      // MIs[1] Operand 1
20075      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
20076      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
20077      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
20078      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
20079      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
20080      GIM_CheckIsSafeToFold, /*InsnID*/1,
20081      // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F)  =>  (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR64:{ *:[i64] }:$F)
20082      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20083      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu,
20084      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
20085      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20086      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20087      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20088      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I64,
20089      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
20090      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
20091      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
20092      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
20093      GIR_EraseFromParent, /*InsnID*/0,
20094      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20095      // GIR_Coverage, 1615,
20096      GIR_Done,
20097    // Label 1155: @49733
20098    GIM_Try, /*On fail goto*//*Label 1156*/ 49834, // Rule ID 1626 //
20099      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
20100      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20101      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
20102      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
20103      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
20104      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20105      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
20106      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
20107      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
20108      // MIs[1] Operand 1
20109      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
20110      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
20111      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
20112      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
20113      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
20114      GIM_CheckIsSafeToFold, /*InsnID*/1,
20115      // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F)  =>  (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR64:{ *:[i64] }:$F)
20116      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20117      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT64,
20118      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
20119      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20120      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20121      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20122      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I64,
20123      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
20124      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
20125      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
20126      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
20127      GIR_EraseFromParent, /*InsnID*/0,
20128      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20129      // GIR_Coverage, 1626,
20130      GIR_Done,
20131    // Label 1156: @49834
20132    GIM_Try, /*On fail goto*//*Label 1157*/ 49935, // Rule ID 1627 //
20133      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
20134      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20135      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
20136      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
20137      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
20138      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20139      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
20140      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
20141      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
20142      // MIs[1] Operand 1
20143      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
20144      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
20145      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
20146      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
20147      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
20148      GIM_CheckIsSafeToFold, /*InsnID*/1,
20149      // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F)  =>  (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR64:{ *:[i64] }:$F)
20150      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20151      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu64,
20152      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
20153      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20154      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20155      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20156      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I64,
20157      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
20158      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
20159      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
20160      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
20161      GIR_EraseFromParent, /*InsnID*/0,
20162      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20163      // GIR_Coverage, 1627,
20164      GIR_Done,
20165    // Label 1157: @49935
20166    GIM_Try, /*On fail goto*//*Label 1158*/ 50036, // Rule ID 1630 //
20167      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
20168      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20169      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
20170      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
20171      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
20172      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20173      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
20174      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
20175      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
20176      // MIs[1] Operand 1
20177      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
20178      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
20179      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
20180      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
20181      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
20182      GIM_CheckIsSafeToFold, /*InsnID*/1,
20183      // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F)  =>  (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), GPR64:{ *:[i64] }:$F)
20184      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20185      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT64,
20186      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
20187      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20188      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20189      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20190      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I64,
20191      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
20192      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
20193      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
20194      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
20195      GIR_EraseFromParent, /*InsnID*/0,
20196      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20197      // GIR_Coverage, 1630,
20198      GIR_Done,
20199    // Label 1158: @50036
20200    GIM_Try, /*On fail goto*//*Label 1159*/ 50137, // Rule ID 1631 //
20201      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
20202      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20203      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
20204      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
20205      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
20206      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20207      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
20208      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
20209      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
20210      // MIs[1] Operand 1
20211      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
20212      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
20213      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
20214      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
20215      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
20216      GIM_CheckIsSafeToFold, /*InsnID*/1,
20217      // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F)  =>  (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), GPR64:{ *:[i64] }:$F)
20218      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20219      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu64,
20220      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
20221      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20222      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20223      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20224      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I64,
20225      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
20226      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
20227      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
20228      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
20229      GIR_EraseFromParent, /*InsnID*/0,
20230      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20231      // GIR_Coverage, 1631,
20232      GIR_Done,
20233    // Label 1159: @50137
20234    GIM_Try, /*On fail goto*//*Label 1160*/ 50238, // Rule ID 1634 //
20235      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
20236      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20237      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
20238      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
20239      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
20240      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20241      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
20242      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20243      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20244      // MIs[1] Operand 1
20245      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
20246      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
20247      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
20248      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
20249      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
20250      GIM_CheckIsSafeToFold, /*InsnID*/1,
20251      // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F)  =>  (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR64:{ *:[i64] }:$F)
20252      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20253      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR,
20254      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
20255      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20256      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20257      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20258      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I64,
20259      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
20260      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
20261      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
20262      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
20263      GIR_EraseFromParent, /*InsnID*/0,
20264      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20265      // GIR_Coverage, 1634,
20266      GIR_Done,
20267    // Label 1160: @50238
20268    GIM_Try, /*On fail goto*//*Label 1161*/ 50339, // Rule ID 1638 //
20269      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
20270      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20271      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
20272      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
20273      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
20274      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20275      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
20276      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
20277      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
20278      // MIs[1] Operand 1
20279      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
20280      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
20281      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
20282      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
20283      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
20284      GIM_CheckIsSafeToFold, /*InsnID*/1,
20285      // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETEQ:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F)  =>  (MOVZ_I64_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR64:{ *:[i64] }:$F)
20286      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
20287      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR64,
20288      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
20289      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20290      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20291      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20292      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I64_I64,
20293      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
20294      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
20295      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
20296      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
20297      GIR_EraseFromParent, /*InsnID*/0,
20298      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20299      // GIR_Coverage, 1638,
20300      GIR_Done,
20301    // Label 1161: @50339
20302    GIM_Try, /*On fail goto*//*Label 1162*/ 50440, // Rule ID 1643 //
20303      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
20304      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20305      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
20306      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
20307      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
20308      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20309      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
20310      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20311      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20312      // MIs[1] Operand 1
20313      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
20314      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
20315      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
20316      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
20317      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
20318      GIM_CheckIsSafeToFold, /*InsnID*/1,
20319      // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F)  =>  (MOVN_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR64:{ *:[i64] }:$F)
20320      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20321      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR,
20322      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
20323      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20324      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20325      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20326      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_I64,
20327      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
20328      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
20329      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
20330      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
20331      GIR_EraseFromParent, /*InsnID*/0,
20332      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20333      // GIR_Coverage, 1643,
20334      GIR_Done,
20335    // Label 1162: @50440
20336    GIM_Try, /*On fail goto*//*Label 1163*/ 50541, // Rule ID 1649 //
20337      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
20338      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20339      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
20340      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
20341      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
20342      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20343      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
20344      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
20345      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
20346      // MIs[1] Operand 1
20347      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
20348      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
20349      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
20350      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
20351      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
20352      GIM_CheckIsSafeToFold, /*InsnID*/1,
20353      // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETNE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F)  =>  (MOVN_I64_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR64:{ *:[i64] }:$F)
20354      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
20355      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR64,
20356      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
20357      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20358      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20359      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20360      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_I64,
20361      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
20362      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
20363      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
20364      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
20365      GIR_EraseFromParent, /*InsnID*/0,
20366      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20367      // GIR_Coverage, 1649,
20368      GIR_Done,
20369    // Label 1163: @50541
20370    GIM_Try, /*On fail goto*//*Label 1164*/ 50642, // Rule ID 1678 //
20371      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
20372      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20373      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
20374      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
20375      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
20376      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20377      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
20378      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20379      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20380      // MIs[1] Operand 1
20381      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
20382      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
20383      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
20384      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
20385      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID,
20386      GIM_CheckIsSafeToFold, /*InsnID*/1,
20387      // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F)  =>  (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
20388      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20389      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT,
20390      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
20391      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20392      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20393      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20394      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D32,
20395      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
20396      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
20397      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
20398      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
20399      GIR_EraseFromParent, /*InsnID*/0,
20400      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20401      // GIR_Coverage, 1678,
20402      GIR_Done,
20403    // Label 1164: @50642
20404    GIM_Try, /*On fail goto*//*Label 1165*/ 50743, // Rule ID 1679 //
20405      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
20406      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20407      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
20408      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
20409      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
20410      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20411      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
20412      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20413      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20414      // MIs[1] Operand 1
20415      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
20416      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
20417      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
20418      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
20419      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID,
20420      GIM_CheckIsSafeToFold, /*InsnID*/1,
20421      // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F)  =>  (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
20422      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20423      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu,
20424      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
20425      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20426      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20427      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20428      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D32,
20429      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
20430      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
20431      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
20432      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
20433      GIR_EraseFromParent, /*InsnID*/0,
20434      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20435      // GIR_Coverage, 1679,
20436      GIR_Done,
20437    // Label 1165: @50743
20438    GIM_Try, /*On fail goto*//*Label 1166*/ 50844, // Rule ID 1682 //
20439      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
20440      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20441      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
20442      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
20443      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
20444      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20445      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
20446      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20447      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20448      // MIs[1] Operand 1
20449      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
20450      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
20451      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
20452      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
20453      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID,
20454      GIM_CheckIsSafeToFold, /*InsnID*/1,
20455      // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F)  =>  (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), AFGR64:{ *:[f64] }:$F)
20456      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20457      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT,
20458      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
20459      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20460      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20461      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20462      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D32,
20463      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
20464      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
20465      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
20466      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
20467      GIR_EraseFromParent, /*InsnID*/0,
20468      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20469      // GIR_Coverage, 1682,
20470      GIR_Done,
20471    // Label 1166: @50844
20472    GIM_Try, /*On fail goto*//*Label 1167*/ 50945, // Rule ID 1683 //
20473      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
20474      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20475      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
20476      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
20477      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
20478      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20479      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
20480      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20481      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20482      // MIs[1] Operand 1
20483      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
20484      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
20485      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
20486      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
20487      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID,
20488      GIM_CheckIsSafeToFold, /*InsnID*/1,
20489      // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F)  =>  (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), AFGR64:{ *:[f64] }:$F)
20490      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20491      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu,
20492      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
20493      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20494      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20495      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20496      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D32,
20497      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
20498      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
20499      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
20500      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
20501      GIR_EraseFromParent, /*InsnID*/0,
20502      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20503      // GIR_Coverage, 1683,
20504      GIR_Done,
20505    // Label 1167: @50945
20506    GIM_Try, /*On fail goto*//*Label 1168*/ 51046, // Rule ID 1686 //
20507      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
20508      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20509      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
20510      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
20511      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
20512      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20513      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
20514      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20515      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20516      // MIs[1] Operand 1
20517      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
20518      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
20519      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
20520      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
20521      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID,
20522      GIM_CheckIsSafeToFold, /*InsnID*/1,
20523      // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F)  =>  (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
20524      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20525      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR,
20526      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
20527      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20528      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20529      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20530      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D32,
20531      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
20532      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
20533      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
20534      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
20535      GIR_EraseFromParent, /*InsnID*/0,
20536      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20537      // GIR_Coverage, 1686,
20538      GIR_Done,
20539    // Label 1168: @51046
20540    GIM_Try, /*On fail goto*//*Label 1169*/ 51147, // Rule ID 1688 //
20541      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
20542      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20543      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
20544      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
20545      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
20546      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20547      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
20548      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20549      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20550      // MIs[1] Operand 1
20551      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
20552      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
20553      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
20554      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
20555      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID,
20556      GIM_CheckIsSafeToFold, /*InsnID*/1,
20557      // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F)  =>  (MOVN_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
20558      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20559      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR,
20560      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
20561      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20562      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20563      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20564      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_D32,
20565      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
20566      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
20567      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
20568      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
20569      GIR_EraseFromParent, /*InsnID*/0,
20570      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20571      // GIR_Coverage, 1688,
20572      GIR_Done,
20573    // Label 1169: @51147
20574    GIM_Try, /*On fail goto*//*Label 1170*/ 51248, // Rule ID 1691 //
20575      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
20576      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20577      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
20578      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
20579      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
20580      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20581      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
20582      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20583      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20584      // MIs[1] Operand 1
20585      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
20586      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
20587      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
20588      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
20589      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
20590      GIM_CheckIsSafeToFold, /*InsnID*/1,
20591      // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F)  =>  (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR64:{ *:[f64] }:$F)
20592      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20593      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT,
20594      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
20595      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20596      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20597      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20598      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D64,
20599      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
20600      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
20601      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
20602      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
20603      GIR_EraseFromParent, /*InsnID*/0,
20604      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20605      // GIR_Coverage, 1691,
20606      GIR_Done,
20607    // Label 1170: @51248
20608    GIM_Try, /*On fail goto*//*Label 1171*/ 51349, // Rule ID 1692 //
20609      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
20610      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20611      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
20612      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
20613      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
20614      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20615      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
20616      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20617      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20618      // MIs[1] Operand 1
20619      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
20620      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
20621      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
20622      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
20623      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
20624      GIM_CheckIsSafeToFold, /*InsnID*/1,
20625      // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F)  =>  (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR64:{ *:[f64] }:$F)
20626      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20627      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu,
20628      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
20629      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20630      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20631      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20632      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D64,
20633      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
20634      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
20635      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
20636      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
20637      GIR_EraseFromParent, /*InsnID*/0,
20638      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20639      // GIR_Coverage, 1692,
20640      GIR_Done,
20641    // Label 1171: @51349
20642    GIM_Try, /*On fail goto*//*Label 1172*/ 51450, // Rule ID 1695 //
20643      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
20644      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20645      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
20646      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
20647      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
20648      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20649      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
20650      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20651      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20652      // MIs[1] Operand 1
20653      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
20654      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
20655      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
20656      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
20657      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
20658      GIM_CheckIsSafeToFold, /*InsnID*/1,
20659      // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F)  =>  (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR64:{ *:[f64] }:$F)
20660      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20661      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT,
20662      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
20663      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20664      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20665      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20666      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D64,
20667      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
20668      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
20669      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
20670      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
20671      GIR_EraseFromParent, /*InsnID*/0,
20672      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20673      // GIR_Coverage, 1695,
20674      GIR_Done,
20675    // Label 1172: @51450
20676    GIM_Try, /*On fail goto*//*Label 1173*/ 51551, // Rule ID 1696 //
20677      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
20678      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20679      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
20680      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
20681      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
20682      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20683      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
20684      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20685      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20686      // MIs[1] Operand 1
20687      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
20688      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
20689      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
20690      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
20691      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
20692      GIM_CheckIsSafeToFold, /*InsnID*/1,
20693      // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F)  =>  (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR64:{ *:[f64] }:$F)
20694      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20695      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu,
20696      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
20697      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20698      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20699      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20700      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D64,
20701      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
20702      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
20703      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
20704      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
20705      GIR_EraseFromParent, /*InsnID*/0,
20706      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20707      // GIR_Coverage, 1696,
20708      GIR_Done,
20709    // Label 1173: @51551
20710    GIM_Try, /*On fail goto*//*Label 1174*/ 51652, // Rule ID 1699 //
20711      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
20712      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20713      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
20714      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
20715      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
20716      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20717      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
20718      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
20719      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
20720      // MIs[1] Operand 1
20721      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
20722      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
20723      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
20724      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
20725      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
20726      GIM_CheckIsSafeToFold, /*InsnID*/1,
20727      // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F)  =>  (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR64:{ *:[f64] }:$F)
20728      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20729      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT64,
20730      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
20731      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20732      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20733      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20734      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D64,
20735      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
20736      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
20737      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
20738      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
20739      GIR_EraseFromParent, /*InsnID*/0,
20740      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20741      // GIR_Coverage, 1699,
20742      GIR_Done,
20743    // Label 1174: @51652
20744    GIM_Try, /*On fail goto*//*Label 1175*/ 51753, // Rule ID 1700 //
20745      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
20746      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20747      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
20748      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
20749      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
20750      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20751      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
20752      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
20753      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
20754      // MIs[1] Operand 1
20755      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
20756      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
20757      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
20758      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
20759      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
20760      GIM_CheckIsSafeToFold, /*InsnID*/1,
20761      // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F)  =>  (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR64:{ *:[f64] }:$F)
20762      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20763      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu64,
20764      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
20765      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20766      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20767      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20768      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D64,
20769      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
20770      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
20771      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
20772      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
20773      GIR_EraseFromParent, /*InsnID*/0,
20774      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20775      // GIR_Coverage, 1700,
20776      GIR_Done,
20777    // Label 1175: @51753
20778    GIM_Try, /*On fail goto*//*Label 1176*/ 51854, // Rule ID 1703 //
20779      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
20780      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20781      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
20782      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
20783      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
20784      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20785      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
20786      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
20787      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
20788      // MIs[1] Operand 1
20789      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
20790      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
20791      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
20792      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
20793      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
20794      GIM_CheckIsSafeToFold, /*InsnID*/1,
20795      // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F)  =>  (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), FGR64:{ *:[f64] }:$F)
20796      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20797      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT64,
20798      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
20799      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20800      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20801      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20802      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D64,
20803      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
20804      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
20805      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
20806      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
20807      GIR_EraseFromParent, /*InsnID*/0,
20808      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20809      // GIR_Coverage, 1703,
20810      GIR_Done,
20811    // Label 1176: @51854
20812    GIM_Try, /*On fail goto*//*Label 1177*/ 51955, // Rule ID 1704 //
20813      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
20814      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20815      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
20816      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
20817      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
20818      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20819      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
20820      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
20821      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
20822      // MIs[1] Operand 1
20823      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
20824      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
20825      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
20826      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
20827      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
20828      GIM_CheckIsSafeToFold, /*InsnID*/1,
20829      // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F)  =>  (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), FGR64:{ *:[f64] }:$F)
20830      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20831      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu64,
20832      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
20833      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20834      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20835      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20836      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D64,
20837      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
20838      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
20839      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
20840      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
20841      GIR_EraseFromParent, /*InsnID*/0,
20842      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20843      // GIR_Coverage, 1704,
20844      GIR_Done,
20845    // Label 1177: @51955
20846    GIM_Try, /*On fail goto*//*Label 1178*/ 52056, // Rule ID 1707 //
20847      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
20848      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20849      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
20850      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
20851      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
20852      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20853      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
20854      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20855      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20856      // MIs[1] Operand 1
20857      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
20858      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
20859      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
20860      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
20861      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
20862      GIM_CheckIsSafeToFold, /*InsnID*/1,
20863      // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F)  =>  (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR64:{ *:[f64] }:$F)
20864      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20865      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR,
20866      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
20867      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20868      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20869      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20870      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D64,
20871      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
20872      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
20873      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
20874      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
20875      GIR_EraseFromParent, /*InsnID*/0,
20876      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20877      // GIR_Coverage, 1707,
20878      GIR_Done,
20879    // Label 1178: @52056
20880    GIM_Try, /*On fail goto*//*Label 1179*/ 52157, // Rule ID 1709 //
20881      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
20882      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20883      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
20884      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
20885      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
20886      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20887      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
20888      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
20889      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
20890      // MIs[1] Operand 1
20891      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
20892      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
20893      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
20894      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
20895      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
20896      GIM_CheckIsSafeToFold, /*InsnID*/1,
20897      // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETEQ:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F)  =>  (MOVZ_I64_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR64:{ *:[f64] }:$F)
20898      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
20899      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR64,
20900      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
20901      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20902      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20903      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20904      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I64_D64,
20905      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
20906      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
20907      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
20908      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
20909      GIR_EraseFromParent, /*InsnID*/0,
20910      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20911      // GIR_Coverage, 1709,
20912      GIR_Done,
20913    // Label 1179: @52157
20914    GIM_Try, /*On fail goto*//*Label 1180*/ 52258, // Rule ID 1711 //
20915      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
20916      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20917      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
20918      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
20919      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
20920      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20921      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
20922      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20923      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20924      // MIs[1] Operand 1
20925      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
20926      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
20927      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
20928      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
20929      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
20930      GIM_CheckIsSafeToFold, /*InsnID*/1,
20931      // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F)  =>  (MOVN_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR64:{ *:[f64] }:$F)
20932      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20933      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR,
20934      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
20935      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20936      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20937      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20938      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_D64,
20939      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
20940      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
20941      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
20942      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
20943      GIR_EraseFromParent, /*InsnID*/0,
20944      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20945      // GIR_Coverage, 1711,
20946      GIR_Done,
20947    // Label 1180: @52258
20948    GIM_Try, /*On fail goto*//*Label 1181*/ 52359, // Rule ID 1714 //
20949      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
20950      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20951      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
20952      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
20953      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
20954      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20955      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
20956      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
20957      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
20958      // MIs[1] Operand 1
20959      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
20960      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
20961      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
20962      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
20963      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
20964      GIM_CheckIsSafeToFold, /*InsnID*/1,
20965      // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETNE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F)  =>  (MOVN_I64_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR64:{ *:[f64] }:$F)
20966      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
20967      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR64,
20968      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
20969      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20970      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20971      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20972      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_D64,
20973      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
20974      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
20975      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
20976      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
20977      GIR_EraseFromParent, /*InsnID*/0,
20978      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20979      // GIR_Coverage, 1714,
20980      GIR_Done,
20981    // Label 1181: @52359
20982    GIM_Try, /*On fail goto*//*Label 1182*/ 52460, // Rule ID 2227 //
20983      GIM_CheckFeatures, GIFBS_InMicroMips_NotFP64bit_NotMips32r6,
20984      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20985      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
20986      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
20987      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
20988      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20989      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
20990      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20991      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20992      // MIs[1] Operand 1
20993      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
20994      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
20995      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
20996      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
20997      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID,
20998      GIM_CheckIsSafeToFold, /*InsnID*/1,
20999      // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F)  =>  (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
21000      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21001      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT_MM,
21002      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
21003      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21004      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21005      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21006      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D32_MM,
21007      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
21008      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
21009      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
21010      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
21011      GIR_EraseFromParent, /*InsnID*/0,
21012      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21013      // GIR_Coverage, 2227,
21014      GIR_Done,
21015    // Label 1182: @52460
21016    GIM_Try, /*On fail goto*//*Label 1183*/ 52561, // Rule ID 2228 //
21017      GIM_CheckFeatures, GIFBS_InMicroMips_NotFP64bit_NotMips32r6,
21018      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
21019      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
21020      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
21021      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
21022      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21023      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
21024      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21025      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21026      // MIs[1] Operand 1
21027      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
21028      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
21029      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
21030      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
21031      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID,
21032      GIM_CheckIsSafeToFold, /*InsnID*/1,
21033      // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F)  =>  (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
21034      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21035      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu_MM,
21036      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
21037      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21038      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21039      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21040      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D32_MM,
21041      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
21042      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
21043      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
21044      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
21045      GIR_EraseFromParent, /*InsnID*/0,
21046      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21047      // GIR_Coverage, 2228,
21048      GIR_Done,
21049    // Label 1183: @52561
21050    GIM_Try, /*On fail goto*//*Label 1184*/ 52662, // Rule ID 2231 //
21051      GIM_CheckFeatures, GIFBS_InMicroMips_NotFP64bit_NotMips32r6,
21052      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
21053      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
21054      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
21055      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
21056      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21057      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
21058      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21059      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21060      // MIs[1] Operand 1
21061      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
21062      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
21063      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
21064      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
21065      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID,
21066      GIM_CheckIsSafeToFold, /*InsnID*/1,
21067      // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F)  =>  (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), AFGR64:{ *:[f64] }:$F)
21068      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21069      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT_MM,
21070      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
21071      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21072      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21073      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21074      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D32_MM,
21075      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
21076      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
21077      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
21078      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
21079      GIR_EraseFromParent, /*InsnID*/0,
21080      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21081      // GIR_Coverage, 2231,
21082      GIR_Done,
21083    // Label 1184: @52662
21084    GIM_Try, /*On fail goto*//*Label 1185*/ 52763, // Rule ID 2232 //
21085      GIM_CheckFeatures, GIFBS_InMicroMips_NotFP64bit_NotMips32r6,
21086      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
21087      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
21088      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
21089      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
21090      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21091      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
21092      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21093      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21094      // MIs[1] Operand 1
21095      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
21096      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
21097      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
21098      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
21099      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID,
21100      GIM_CheckIsSafeToFold, /*InsnID*/1,
21101      // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F)  =>  (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), AFGR64:{ *:[f64] }:$F)
21102      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21103      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu_MM,
21104      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
21105      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21106      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21107      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21108      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D32_MM,
21109      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
21110      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
21111      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
21112      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
21113      GIR_EraseFromParent, /*InsnID*/0,
21114      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21115      // GIR_Coverage, 2232,
21116      GIR_Done,
21117    // Label 1185: @52763
21118    GIM_Try, /*On fail goto*//*Label 1186*/ 52864, // Rule ID 2235 //
21119      GIM_CheckFeatures, GIFBS_InMicroMips_NotFP64bit_NotMips32r6,
21120      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
21121      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
21122      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
21123      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
21124      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21125      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
21126      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21127      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21128      // MIs[1] Operand 1
21129      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
21130      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
21131      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
21132      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
21133      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID,
21134      GIM_CheckIsSafeToFold, /*InsnID*/1,
21135      // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F)  =>  (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
21136      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21137      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR_MM,
21138      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
21139      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21140      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21141      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21142      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D32_MM,
21143      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
21144      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
21145      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
21146      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
21147      GIR_EraseFromParent, /*InsnID*/0,
21148      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21149      // GIR_Coverage, 2235,
21150      GIR_Done,
21151    // Label 1186: @52864
21152    GIM_Try, /*On fail goto*//*Label 1187*/ 52965, // Rule ID 2237 //
21153      GIM_CheckFeatures, GIFBS_InMicroMips_NotFP64bit_NotMips32r6,
21154      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
21155      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
21156      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
21157      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
21158      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21159      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
21160      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21161      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21162      // MIs[1] Operand 1
21163      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
21164      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
21165      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
21166      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
21167      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID,
21168      GIM_CheckIsSafeToFold, /*InsnID*/1,
21169      // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F)  =>  (MOVN_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
21170      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21171      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR_MM,
21172      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
21173      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21174      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21175      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21176      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_D32_MM,
21177      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
21178      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
21179      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
21180      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
21181      GIR_EraseFromParent, /*InsnID*/0,
21182      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21183      // GIR_Coverage, 2237,
21184      GIR_Done,
21185    // Label 1187: @52965
21186    GIM_Try, /*On fail goto*//*Label 1188*/ 53004, // Rule ID 284 //
21187      GIM_CheckFeatures, GIFBS_HasStdEnc_NotMips4_32,
21188      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
21189      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
21190      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
21191      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
21192      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
21193      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
21194      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
21195      // (select:{ *:[i64] } GPR32Opnd:{ *:[i32] }:$cond, GPR64Opnd:{ *:[i64] }:$T, GPR64Opnd:{ *:[i64] }:$F)  =>  (PseudoSELECT_I64:{ *:[i64] } GPR32Opnd:{ *:[i32] }:$cond, GPR64Opnd:{ *:[i64] }:$T, GPR64Opnd:{ *:[i64] }:$F)
21196      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PseudoSELECT_I64,
21197      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21198      // GIR_Coverage, 284,
21199      GIR_Done,
21200    // Label 1188: @53004
21201    GIM_Try, /*On fail goto*//*Label 1189*/ 53043, // Rule ID 286 //
21202      GIM_CheckFeatures, GIFBS_HasStdEnc_NotFP64bit_NotMips4_32,
21203      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
21204      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
21205      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
21206      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
21207      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
21208      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
21209      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID,
21210      // (select:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$cond, AFGR64Opnd:{ *:[f64] }:$T, AFGR64Opnd:{ *:[f64] }:$F)  =>  (PseudoSELECT_D32:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$cond, AFGR64Opnd:{ *:[f64] }:$T, AFGR64Opnd:{ *:[f64] }:$F)
21211      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PseudoSELECT_D32,
21212      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21213      // GIR_Coverage, 286,
21214      GIR_Done,
21215    // Label 1189: @53043
21216    GIM_Try, /*On fail goto*//*Label 1190*/ 53082, // Rule ID 287 //
21217      GIM_CheckFeatures, GIFBS_HasStdEnc_IsFP64bit_NotMips4_32,
21218      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
21219      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
21220      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
21221      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
21222      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
21223      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
21224      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
21225      // (select:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$cond, FGR64Opnd:{ *:[f64] }:$T, FGR64Opnd:{ *:[f64] }:$F)  =>  (PseudoSELECT_D64:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$cond, FGR64Opnd:{ *:[f64] }:$T, FGR64Opnd:{ *:[f64] }:$F)
21226      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PseudoSELECT_D64,
21227      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21228      // GIR_Coverage, 287,
21229      GIR_Done,
21230    // Label 1190: @53082
21231    GIM_Try, /*On fail goto*//*Label 1191*/ 53138, // Rule ID 1644 //
21232      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
21233      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
21234      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
21235      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
21236      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
21237      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
21238      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
21239      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
21240      // (select:{ *:[i64] } GPR32:{ *:[i32] }:$cond, GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F)  =>  (MOVN_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR32:{ *:[i32] }:$cond, GPR64:{ *:[i64] }:$F)
21241      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_I64,
21242      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
21243      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
21244      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond
21245      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
21246      GIR_EraseFromParent, /*InsnID*/0,
21247      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21248      // GIR_Coverage, 1644,
21249      GIR_Done,
21250    // Label 1191: @53138
21251    GIM_Try, /*On fail goto*//*Label 1192*/ 53194, // Rule ID 1650 //
21252      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
21253      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
21254      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
21255      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
21256      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
21257      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
21258      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
21259      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
21260      // (select:{ *:[i64] } GPR64:{ *:[i64] }:$cond, GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F)  =>  (MOVN_I64_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$cond, GPR64:{ *:[i64] }:$F)
21261      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_I64,
21262      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
21263      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
21264      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond
21265      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
21266      GIR_EraseFromParent, /*InsnID*/0,
21267      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21268      // GIR_Coverage, 1650,
21269      GIR_Done,
21270    // Label 1192: @53194
21271    GIM_Try, /*On fail goto*//*Label 1193*/ 53250, // Rule ID 1689 //
21272      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
21273      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
21274      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
21275      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
21276      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
21277      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
21278      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
21279      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID,
21280      // (select:{ *:[f64] } GPR32:{ *:[i32] }:$cond, AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F)  =>  (MOVN_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$cond, AFGR64:{ *:[f64] }:$F)
21281      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_D32,
21282      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
21283      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
21284      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond
21285      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
21286      GIR_EraseFromParent, /*InsnID*/0,
21287      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21288      // GIR_Coverage, 1689,
21289      GIR_Done,
21290    // Label 1193: @53250
21291    GIM_Try, /*On fail goto*//*Label 1194*/ 53306, // Rule ID 1712 //
21292      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
21293      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
21294      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
21295      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
21296      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
21297      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
21298      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
21299      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
21300      // (select:{ *:[f64] } GPR32:{ *:[i32] }:$cond, FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F)  =>  (MOVN_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$cond, FGR64:{ *:[f64] }:$F)
21301      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_D64,
21302      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
21303      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
21304      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond
21305      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
21306      GIR_EraseFromParent, /*InsnID*/0,
21307      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21308      // GIR_Coverage, 1712,
21309      GIR_Done,
21310    // Label 1194: @53306
21311    GIM_Try, /*On fail goto*//*Label 1195*/ 53362, // Rule ID 1715 //
21312      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
21313      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
21314      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
21315      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
21316      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
21317      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
21318      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
21319      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
21320      // (select:{ *:[f64] } GPR64:{ *:[i64] }:$cond, FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F)  =>  (MOVN_I64_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR64:{ *:[i64] }:$cond, FGR64:{ *:[f64] }:$F)
21321      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_D64,
21322      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
21323      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
21324      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond
21325      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
21326      GIR_EraseFromParent, /*InsnID*/0,
21327      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21328      // GIR_Coverage, 1715,
21329      GIR_Done,
21330    // Label 1195: @53362
21331    GIM_Try, /*On fail goto*//*Label 1196*/ 53418, // Rule ID 2238 //
21332      GIM_CheckFeatures, GIFBS_InMicroMips_NotFP64bit_NotMips32r6,
21333      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
21334      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
21335      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
21336      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
21337      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
21338      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
21339      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID,
21340      // (select:{ *:[f64] } GPR32:{ *:[i32] }:$cond, AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F)  =>  (MOVN_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$cond, AFGR64:{ *:[f64] }:$F)
21341      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_D32_MM,
21342      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
21343      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
21344      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond
21345      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
21346      GIR_EraseFromParent, /*InsnID*/0,
21347      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21348      // GIR_Coverage, 2238,
21349      GIR_Done,
21350    // Label 1196: @53418
21351    GIM_Try, /*On fail goto*//*Label 1197*/ 53498, // Rule ID 1748 //
21352      GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc,
21353      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
21354      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
21355      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
21356      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
21357      // (select:{ *:[i64] } i64:{ *:[i64] }:$cond, i64:{ *:[i64] }:$t, i64:{ *:[i64] }:$f)  =>  (OR64:{ *:[i64] } (SELNEZ64:{ *:[i64] } i64:{ *:[i64] }:$t, i64:{ *:[i64] }:$cond), (SELEQZ64:{ *:[i64] } i64:{ *:[i64] }:$f, i64:{ *:[i64] }:$cond))
21358      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
21359      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
21360      GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SELEQZ64,
21361      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
21362      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // f
21363      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // cond
21364      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
21365      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SELNEZ64,
21366      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
21367      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // t
21368      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // cond
21369      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21370      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::OR64,
21371      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
21372      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
21373      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
21374      GIR_EraseFromParent, /*InsnID*/0,
21375      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21376      // GIR_Coverage, 1748,
21377      GIR_Done,
21378    // Label 1197: @53498
21379    GIM_Try, /*On fail goto*//*Label 1198*/ 53610, // Rule ID 1759 //
21380      GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc,
21381      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
21382      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
21383      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
21384      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
21385      // (select:{ *:[i64] } i32:{ *:[i32] }:$cond, i64:{ *:[i64] }:$t, i64:{ *:[i64] }:$f)  =>  (OR64:{ *:[i64] } (SELNEZ64:{ *:[i64] } i64:{ *:[i64] }:$t, (SLL64_32:{ *:[i64] } i32:{ *:[i32] }:$cond)), (SELEQZ64:{ *:[i64] } i64:{ *:[i64] }:$f, (SLL64_32:{ *:[i64] } i32:{ *:[i32] }:$cond)))
21386      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
21387      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
21388      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
21389      GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
21390      GIR_BuildMI, /*InsnID*/4, /*Opcode*/Mips::SLL64_32,
21391      GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
21392      GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // cond
21393      GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
21394      GIR_BuildMI, /*InsnID*/3, /*Opcode*/Mips::SELEQZ64,
21395      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
21396      GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // f
21397      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
21398      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
21399      GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SLL64_32,
21400      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
21401      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // cond
21402      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
21403      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SELNEZ64,
21404      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
21405      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // t
21406      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
21407      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21408      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::OR64,
21409      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
21410      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
21411      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0,
21412      GIR_EraseFromParent, /*InsnID*/0,
21413      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21414      // GIR_Coverage, 1759,
21415      GIR_Done,
21416    // Label 1198: @53610
21417    GIM_Reject,
21418    // Label 1059: @53611
21419    GIM_Reject,
21420    // Label 28: @53612
21421    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1201*/ 53698,
21422    /*GILLT_s32*//*Label 1199*/ 53620,
21423    /*GILLT_s64*//*Label 1200*/ 53666,
21424    // Label 1199: @53620
21425    GIM_Try, /*On fail goto*//*Label 1202*/ 53665,
21426      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
21427      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
21428      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
21429      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
21430      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
21431      GIM_Try, /*On fail goto*//*Label 1203*/ 53653, // Rule ID 319 //
21432        GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
21433        // (mulhu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MUHU:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
21434        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUHU,
21435        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21436        // GIR_Coverage, 319,
21437        GIR_Done,
21438      // Label 1203: @53653
21439      GIM_Try, /*On fail goto*//*Label 1204*/ 53664, // Rule ID 1163 //
21440        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
21441        // (mulhu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MUHU_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
21442        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUHU_MMR6,
21443        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21444        // GIR_Coverage, 1163,
21445        GIR_Done,
21446      // Label 1204: @53664
21447      GIM_Reject,
21448    // Label 1202: @53665
21449    GIM_Reject,
21450    // Label 1200: @53666
21451    GIM_Try, /*On fail goto*//*Label 1205*/ 53697, // Rule ID 334 //
21452      GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
21453      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
21454      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
21455      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
21456      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
21457      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
21458      // (mulhu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DMUHU:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
21459      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMUHU,
21460      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21461      // GIR_Coverage, 334,
21462      GIR_Done,
21463    // Label 1205: @53697
21464    GIM_Reject,
21465    // Label 1201: @53698
21466    GIM_Reject,
21467    // Label 29: @53699
21468    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1208*/ 53785,
21469    /*GILLT_s32*//*Label 1206*/ 53707,
21470    /*GILLT_s64*//*Label 1207*/ 53753,
21471    // Label 1206: @53707
21472    GIM_Try, /*On fail goto*//*Label 1209*/ 53752,
21473      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
21474      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
21475      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
21476      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
21477      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
21478      GIM_Try, /*On fail goto*//*Label 1210*/ 53740, // Rule ID 318 //
21479        GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
21480        // (mulhs:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MUH:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
21481        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUH,
21482        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21483        // GIR_Coverage, 318,
21484        GIR_Done,
21485      // Label 1210: @53740
21486      GIM_Try, /*On fail goto*//*Label 1211*/ 53751, // Rule ID 1162 //
21487        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
21488        // (mulhs:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MUH_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
21489        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUH_MMR6,
21490        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21491        // GIR_Coverage, 1162,
21492        GIR_Done,
21493      // Label 1211: @53751
21494      GIM_Reject,
21495    // Label 1209: @53752
21496    GIM_Reject,
21497    // Label 1207: @53753
21498    GIM_Try, /*On fail goto*//*Label 1212*/ 53784, // Rule ID 333 //
21499      GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
21500      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
21501      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
21502      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
21503      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
21504      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
21505      // (mulhs:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DMUH:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
21506      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMUH,
21507      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21508      // GIR_Coverage, 333,
21509      GIR_Done,
21510    // Label 1212: @53784
21511    GIM_Reject,
21512    // Label 1208: @53785
21513    GIM_Reject,
21514    // Label 30: @53786
21515    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 7, /*)*//*default:*//*Label 1217*/ 54664,
21516    /*GILLT_s32*//*Label 1213*/ 53798,
21517    /*GILLT_s64*//*Label 1214*/ 53998, 0,
21518    /*GILLT_v2s64*//*Label 1215*/ 54346, 0,
21519    /*GILLT_v4s32*//*Label 1216*/ 54505,
21520    // Label 1213: @53798
21521    GIM_Try, /*On fail goto*//*Label 1218*/ 53997,
21522      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
21523      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
21524      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
21525      GIM_Try, /*On fail goto*//*Label 1219*/ 53869, // Rule ID 157 //
21526        GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6,
21527        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21528        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
21529        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
21530        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21531        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
21532        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
21533        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
21534        GIM_CheckIsSafeToFold, /*InsnID*/1,
21535        // (fadd:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr)  =>  (MADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
21536        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADD_S,
21537        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
21538        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fr
21539        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
21540        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
21541        GIR_EraseFromParent, /*InsnID*/0,
21542        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21543        // GIR_Coverage, 157,
21544        GIR_Done,
21545      // Label 1219: @53869
21546      GIM_Try, /*On fail goto*//*Label 1220*/ 53926, // Rule ID 2299 //
21547        GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6,
21548        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
21549        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
21550        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
21551        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
21552        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21553        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
21554        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
21555        GIM_CheckIsSafeToFold, /*InsnID*/1,
21556        // (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft))  =>  (MADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
21557        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADD_S,
21558        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
21559        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fr
21560        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
21561        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
21562        GIR_EraseFromParent, /*InsnID*/0,
21563        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21564        // GIR_Coverage, 2299,
21565        GIR_Done,
21566      // Label 1220: @53926
21567      GIM_Try, /*On fail goto*//*Label 1221*/ 53945, // Rule ID 145 //
21568        GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
21569        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
21570        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
21571        // (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)  =>  (FADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
21572        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FADD_S,
21573        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21574        // GIR_Coverage, 145,
21575        GIR_Done,
21576      // Label 1221: @53945
21577      GIM_Try, /*On fail goto*//*Label 1222*/ 53964, // Rule ID 1114 //
21578        GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat,
21579        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
21580        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
21581        // (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)  =>  (FADD_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
21582        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FADD_S_MM,
21583        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21584        // GIR_Coverage, 1114,
21585        GIR_Done,
21586      // Label 1222: @53964
21587      GIM_Try, /*On fail goto*//*Label 1223*/ 53996, // Rule ID 1170 //
21588        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
21589        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
21590        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
21591        // (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)  =>  (FADD_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs)
21592        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FADD_S_MMR6,
21593        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
21594        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ft
21595        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fs
21596        GIR_EraseFromParent, /*InsnID*/0,
21597        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21598        // GIR_Coverage, 1170,
21599        GIR_Done,
21600      // Label 1223: @53996
21601      GIM_Reject,
21602    // Label 1218: @53997
21603    GIM_Reject,
21604    // Label 1214: @53998
21605    GIM_Try, /*On fail goto*//*Label 1224*/ 54345,
21606      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
21607      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
21608      GIM_Try, /*On fail goto*//*Label 1225*/ 54069, // Rule ID 159 //
21609        GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
21610        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
21611        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21612        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
21613        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
21614        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
21615        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
21616        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
21617        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
21618        GIM_CheckIsSafeToFold, /*InsnID*/1,
21619        // (fadd:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr)  =>  (MADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
21620        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADD_D32,
21621        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
21622        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fr
21623        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
21624        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
21625        GIR_EraseFromParent, /*InsnID*/0,
21626        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21627        // GIR_Coverage, 159,
21628        GIR_Done,
21629      // Label 1225: @54069
21630      GIM_Try, /*On fail goto*//*Label 1226*/ 54130, // Rule ID 161 //
21631        GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6,
21632        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
21633        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21634        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
21635        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
21636        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
21637        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
21638        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
21639        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
21640        GIM_CheckIsSafeToFold, /*InsnID*/1,
21641        // (fadd:{ *:[f64] } (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr)  =>  (MADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
21642        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADD_D64,
21643        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
21644        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fr
21645        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
21646        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
21647        GIR_EraseFromParent, /*InsnID*/0,
21648        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21649        // GIR_Coverage, 161,
21650        GIR_Done,
21651      // Label 1226: @54130
21652      GIM_Try, /*On fail goto*//*Label 1227*/ 54191, // Rule ID 2300 //
21653        GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
21654        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
21655        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
21656        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
21657        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
21658        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
21659        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
21660        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
21661        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
21662        GIM_CheckIsSafeToFold, /*InsnID*/1,
21663        // (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft))  =>  (MADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
21664        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADD_D32,
21665        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
21666        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fr
21667        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
21668        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
21669        GIR_EraseFromParent, /*InsnID*/0,
21670        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21671        // GIR_Coverage, 2300,
21672        GIR_Done,
21673      // Label 1227: @54191
21674      GIM_Try, /*On fail goto*//*Label 1228*/ 54252, // Rule ID 2301 //
21675        GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6,
21676        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
21677        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
21678        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
21679        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
21680        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
21681        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
21682        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
21683        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
21684        GIM_CheckIsSafeToFold, /*InsnID*/1,
21685        // (fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft))  =>  (MADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
21686        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADD_D64,
21687        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
21688        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fr
21689        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
21690        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
21691        GIR_EraseFromParent, /*InsnID*/0,
21692        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21693        // GIR_Coverage, 2301,
21694        GIR_Done,
21695      // Label 1228: @54252
21696      GIM_Try, /*On fail goto*//*Label 1229*/ 54275, // Rule ID 146 //
21697        GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips,
21698        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
21699        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
21700        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
21701        // (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)  =>  (FADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
21702        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FADD_D32,
21703        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21704        // GIR_Coverage, 146,
21705        GIR_Done,
21706      // Label 1229: @54275
21707      GIM_Try, /*On fail goto*//*Label 1230*/ 54298, // Rule ID 147 //
21708        GIM_CheckFeatures, GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips,
21709        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
21710        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
21711        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
21712        // (fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)  =>  (FADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
21713        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FADD_D64,
21714        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21715        // GIR_Coverage, 147,
21716        GIR_Done,
21717      // Label 1230: @54298
21718      GIM_Try, /*On fail goto*//*Label 1231*/ 54321, // Rule ID 1118 //
21719        GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit,
21720        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
21721        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
21722        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
21723        // (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)  =>  (FADD_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
21724        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FADD_D32_MM,
21725        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21726        // GIR_Coverage, 1118,
21727        GIR_Done,
21728      // Label 1231: @54321
21729      GIM_Try, /*On fail goto*//*Label 1232*/ 54344, // Rule ID 1119 //
21730        GIM_CheckFeatures, GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat,
21731        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
21732        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
21733        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
21734        // (fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)  =>  (FADD_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
21735        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FADD_D64_MM,
21736        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21737        // GIR_Coverage, 1119,
21738        GIR_Done,
21739      // Label 1232: @54344
21740      GIM_Reject,
21741    // Label 1224: @54345
21742    GIM_Reject,
21743    // Label 1215: @54346
21744    GIM_Try, /*On fail goto*//*Label 1233*/ 54504,
21745      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
21746      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
21747      GIM_Try, /*On fail goto*//*Label 1234*/ 54418, // Rule ID 2411 //
21748        GIM_CheckFeatures, GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc,
21749        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
21750        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21751        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
21752        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
21753        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
21754        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
21755        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
21756        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
21757        GIM_CheckIsSafeToFold, /*InsnID*/1,
21758        // (fadd:{ *:[v2f64] } (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt), MSA128DOpnd:{ *:[v2f64] }:$wd)  =>  (FMADD_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
21759        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMADD_D,
21760        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd
21761        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd
21762        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
21763        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
21764        GIR_EraseFromParent, /*InsnID*/0,
21765        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21766        // GIR_Coverage, 2411,
21767        GIR_Done,
21768      // Label 1234: @54418
21769      GIM_Try, /*On fail goto*//*Label 1235*/ 54480, // Rule ID 1943 //
21770        GIM_CheckFeatures, GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc,
21771        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
21772        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
21773        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
21774        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
21775        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
21776        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
21777        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
21778        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
21779        GIM_CheckIsSafeToFold, /*InsnID*/1,
21780        // (fadd:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt))  =>  (FMADD_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
21781        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMADD_D,
21782        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd
21783        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd
21784        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
21785        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
21786        GIR_EraseFromParent, /*InsnID*/0,
21787        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21788        // GIR_Coverage, 1943,
21789        GIR_Done,
21790      // Label 1235: @54480
21791      GIM_Try, /*On fail goto*//*Label 1236*/ 54503, // Rule ID 655 //
21792        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
21793        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
21794        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
21795        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
21796        // (fadd:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FADD_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
21797        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FADD_D,
21798        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21799        // GIR_Coverage, 655,
21800        GIR_Done,
21801      // Label 1236: @54503
21802      GIM_Reject,
21803    // Label 1233: @54504
21804    GIM_Reject,
21805    // Label 1216: @54505
21806    GIM_Try, /*On fail goto*//*Label 1237*/ 54663,
21807      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
21808      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
21809      GIM_Try, /*On fail goto*//*Label 1238*/ 54577, // Rule ID 2410 //
21810        GIM_CheckFeatures, GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc,
21811        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
21812        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21813        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
21814        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
21815        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
21816        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
21817        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
21818        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
21819        GIM_CheckIsSafeToFold, /*InsnID*/1,
21820        // (fadd:{ *:[v4f32] } (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt), MSA128WOpnd:{ *:[v4f32] }:$wd)  =>  (FMADD_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
21821        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMADD_W,
21822        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd
21823        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd
21824        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
21825        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
21826        GIR_EraseFromParent, /*InsnID*/0,
21827        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21828        // GIR_Coverage, 2410,
21829        GIR_Done,
21830      // Label 1238: @54577
21831      GIM_Try, /*On fail goto*//*Label 1239*/ 54639, // Rule ID 1942 //
21832        GIM_CheckFeatures, GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc,
21833        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
21834        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
21835        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
21836        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
21837        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
21838        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
21839        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
21840        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
21841        GIM_CheckIsSafeToFold, /*InsnID*/1,
21842        // (fadd:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt))  =>  (FMADD_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
21843        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMADD_W,
21844        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd
21845        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd
21846        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
21847        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
21848        GIR_EraseFromParent, /*InsnID*/0,
21849        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21850        // GIR_Coverage, 1942,
21851        GIR_Done,
21852      // Label 1239: @54639
21853      GIM_Try, /*On fail goto*//*Label 1240*/ 54662, // Rule ID 654 //
21854        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
21855        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
21856        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
21857        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
21858        // (fadd:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FADD_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
21859        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FADD_W,
21860        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21861        // GIR_Coverage, 654,
21862        GIR_Done,
21863      // Label 1240: @54662
21864      GIM_Reject,
21865    // Label 1237: @54663
21866    GIM_Reject,
21867    // Label 1217: @54664
21868    GIM_Reject,
21869    // Label 31: @54665
21870    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 7, /*)*//*default:*//*Label 1245*/ 55240,
21871    /*GILLT_s32*//*Label 1241*/ 54677,
21872    /*GILLT_s64*//*Label 1242*/ 54820, 0,
21873    /*GILLT_v2s64*//*Label 1243*/ 55046, 0,
21874    /*GILLT_v4s32*//*Label 1244*/ 55143,
21875    // Label 1241: @54677
21876    GIM_Try, /*On fail goto*//*Label 1246*/ 54819,
21877      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
21878      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
21879      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
21880      GIM_Try, /*On fail goto*//*Label 1247*/ 54748, // Rule ID 158 //
21881        GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6,
21882        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21883        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
21884        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
21885        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21886        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
21887        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
21888        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
21889        GIM_CheckIsSafeToFold, /*InsnID*/1,
21890        // (fsub:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr)  =>  (MSUB_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
21891        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUB_S,
21892        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
21893        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fr
21894        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
21895        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
21896        GIR_EraseFromParent, /*InsnID*/0,
21897        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21898        // GIR_Coverage, 158,
21899        GIR_Done,
21900      // Label 1247: @54748
21901      GIM_Try, /*On fail goto*//*Label 1248*/ 54767, // Rule ID 154 //
21902        GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
21903        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
21904        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
21905        // (fsub:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)  =>  (FSUB_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
21906        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSUB_S,
21907        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21908        // GIR_Coverage, 154,
21909        GIR_Done,
21910      // Label 1248: @54767
21911      GIM_Try, /*On fail goto*//*Label 1249*/ 54786, // Rule ID 1117 //
21912        GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat,
21913        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
21914        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
21915        // (fsub:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)  =>  (FSUB_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
21916        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSUB_S_MM,
21917        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21918        // GIR_Coverage, 1117,
21919        GIR_Done,
21920      // Label 1249: @54786
21921      GIM_Try, /*On fail goto*//*Label 1250*/ 54818, // Rule ID 1171 //
21922        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
21923        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
21924        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
21925        // (fsub:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)  =>  (FSUB_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs)
21926        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSUB_S_MMR6,
21927        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
21928        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ft
21929        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fs
21930        GIR_EraseFromParent, /*InsnID*/0,
21931        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21932        // GIR_Coverage, 1171,
21933        GIR_Done,
21934      // Label 1250: @54818
21935      GIM_Reject,
21936    // Label 1246: @54819
21937    GIM_Reject,
21938    // Label 1242: @54820
21939    GIM_Try, /*On fail goto*//*Label 1251*/ 55045,
21940      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
21941      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
21942      GIM_Try, /*On fail goto*//*Label 1252*/ 54891, // Rule ID 160 //
21943        GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
21944        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
21945        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21946        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
21947        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
21948        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
21949        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
21950        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
21951        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
21952        GIM_CheckIsSafeToFold, /*InsnID*/1,
21953        // (fsub:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr)  =>  (MSUB_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
21954        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUB_D32,
21955        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
21956        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fr
21957        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
21958        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
21959        GIR_EraseFromParent, /*InsnID*/0,
21960        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21961        // GIR_Coverage, 160,
21962        GIR_Done,
21963      // Label 1252: @54891
21964      GIM_Try, /*On fail goto*//*Label 1253*/ 54952, // Rule ID 162 //
21965        GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6,
21966        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
21967        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21968        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
21969        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
21970        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
21971        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
21972        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
21973        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
21974        GIM_CheckIsSafeToFold, /*InsnID*/1,
21975        // (fsub:{ *:[f64] } (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr)  =>  (MSUB_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
21976        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUB_D64,
21977        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
21978        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fr
21979        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
21980        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
21981        GIR_EraseFromParent, /*InsnID*/0,
21982        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21983        // GIR_Coverage, 162,
21984        GIR_Done,
21985      // Label 1253: @54952
21986      GIM_Try, /*On fail goto*//*Label 1254*/ 54975, // Rule ID 155 //
21987        GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips,
21988        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
21989        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
21990        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
21991        // (fsub:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)  =>  (FSUB_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
21992        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSUB_D32,
21993        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21994        // GIR_Coverage, 155,
21995        GIR_Done,
21996      // Label 1254: @54975
21997      GIM_Try, /*On fail goto*//*Label 1255*/ 54998, // Rule ID 156 //
21998        GIM_CheckFeatures, GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips,
21999        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
22000        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
22001        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
22002        // (fsub:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)  =>  (FSUB_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
22003        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSUB_D64,
22004        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22005        // GIR_Coverage, 156,
22006        GIR_Done,
22007      // Label 1255: @54998
22008      GIM_Try, /*On fail goto*//*Label 1256*/ 55021, // Rule ID 1124 //
22009        GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit,
22010        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
22011        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
22012        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
22013        // (fsub:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)  =>  (FSUB_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
22014        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSUB_D32_MM,
22015        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22016        // GIR_Coverage, 1124,
22017        GIR_Done,
22018      // Label 1256: @55021
22019      GIM_Try, /*On fail goto*//*Label 1257*/ 55044, // Rule ID 1125 //
22020        GIM_CheckFeatures, GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat,
22021        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
22022        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
22023        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
22024        // (fsub:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)  =>  (FSUB_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
22025        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSUB_D64_MM,
22026        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22027        // GIR_Coverage, 1125,
22028        GIR_Done,
22029      // Label 1257: @55044
22030      GIM_Reject,
22031    // Label 1251: @55045
22032    GIM_Reject,
22033    // Label 1243: @55046
22034    GIM_Try, /*On fail goto*//*Label 1258*/ 55142,
22035      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
22036      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
22037      GIM_Try, /*On fail goto*//*Label 1259*/ 55118, // Rule ID 1941 //
22038        GIM_CheckFeatures, GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc,
22039        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
22040        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
22041        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
22042        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
22043        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
22044        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
22045        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
22046        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
22047        GIM_CheckIsSafeToFold, /*InsnID*/1,
22048        // (fsub:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt))  =>  (FMSUB_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
22049        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMSUB_D,
22050        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd
22051        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd
22052        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
22053        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
22054        GIR_EraseFromParent, /*InsnID*/0,
22055        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22056        // GIR_Coverage, 1941,
22057        GIR_Done,
22058      // Label 1259: @55118
22059      GIM_Try, /*On fail goto*//*Label 1260*/ 55141, // Rule ID 743 //
22060        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
22061        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
22062        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
22063        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
22064        // (fsub:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FSUB_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
22065        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSUB_D,
22066        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22067        // GIR_Coverage, 743,
22068        GIR_Done,
22069      // Label 1260: @55141
22070      GIM_Reject,
22071    // Label 1258: @55142
22072    GIM_Reject,
22073    // Label 1244: @55143
22074    GIM_Try, /*On fail goto*//*Label 1261*/ 55239,
22075      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
22076      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
22077      GIM_Try, /*On fail goto*//*Label 1262*/ 55215, // Rule ID 1940 //
22078        GIM_CheckFeatures, GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc,
22079        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
22080        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
22081        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
22082        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
22083        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
22084        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
22085        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
22086        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
22087        GIM_CheckIsSafeToFold, /*InsnID*/1,
22088        // (fsub:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt))  =>  (FMSUB_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
22089        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMSUB_W,
22090        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd
22091        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd
22092        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
22093        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
22094        GIR_EraseFromParent, /*InsnID*/0,
22095        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22096        // GIR_Coverage, 1940,
22097        GIR_Done,
22098      // Label 1262: @55215
22099      GIM_Try, /*On fail goto*//*Label 1263*/ 55238, // Rule ID 742 //
22100        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
22101        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
22102        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
22103        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
22104        // (fsub:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FSUB_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
22105        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSUB_W,
22106        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22107        // GIR_Coverage, 742,
22108        GIR_Done,
22109      // Label 1263: @55238
22110      GIM_Reject,
22111    // Label 1261: @55239
22112    GIM_Reject,
22113    // Label 1245: @55240
22114    GIM_Reject,
22115    // Label 32: @55241
22116    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 7, /*)*//*default:*//*Label 1268*/ 55677,
22117    /*GILLT_s32*//*Label 1264*/ 55253,
22118    /*GILLT_s64*//*Label 1265*/ 55323, 0,
22119    /*GILLT_v2s64*//*Label 1266*/ 55427, 0,
22120    /*GILLT_v4s32*//*Label 1267*/ 55552,
22121    // Label 1264: @55253
22122    GIM_Try, /*On fail goto*//*Label 1269*/ 55322,
22123      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
22124      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
22125      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
22126      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
22127      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
22128      GIM_Try, /*On fail goto*//*Label 1270*/ 55286, // Rule ID 151 //
22129        GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
22130        // (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)  =>  (FMUL_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
22131        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMUL_S,
22132        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22133        // GIR_Coverage, 151,
22134        GIR_Done,
22135      // Label 1270: @55286
22136      GIM_Try, /*On fail goto*//*Label 1271*/ 55297, // Rule ID 1116 //
22137        GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat,
22138        // (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)  =>  (FMUL_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
22139        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMUL_S_MM,
22140        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22141        // GIR_Coverage, 1116,
22142        GIR_Done,
22143      // Label 1271: @55297
22144      GIM_Try, /*On fail goto*//*Label 1272*/ 55321, // Rule ID 1172 //
22145        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
22146        // (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)  =>  (FMUL_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs)
22147        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMUL_S_MMR6,
22148        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
22149        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ft
22150        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fs
22151        GIR_EraseFromParent, /*InsnID*/0,
22152        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22153        // GIR_Coverage, 1172,
22154        GIR_Done,
22155      // Label 1272: @55321
22156      GIM_Reject,
22157    // Label 1269: @55322
22158    GIM_Reject,
22159    // Label 1265: @55323
22160    GIM_Try, /*On fail goto*//*Label 1273*/ 55426,
22161      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
22162      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
22163      GIM_Try, /*On fail goto*//*Label 1274*/ 55356, // Rule ID 152 //
22164        GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips,
22165        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
22166        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
22167        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
22168        // (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)  =>  (FMUL_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
22169        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMUL_D32,
22170        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22171        // GIR_Coverage, 152,
22172        GIR_Done,
22173      // Label 1274: @55356
22174      GIM_Try, /*On fail goto*//*Label 1275*/ 55379, // Rule ID 153 //
22175        GIM_CheckFeatures, GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips,
22176        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
22177        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
22178        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
22179        // (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)  =>  (FMUL_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
22180        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMUL_D64,
22181        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22182        // GIR_Coverage, 153,
22183        GIR_Done,
22184      // Label 1275: @55379
22185      GIM_Try, /*On fail goto*//*Label 1276*/ 55402, // Rule ID 1122 //
22186        GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit,
22187        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
22188        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
22189        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
22190        // (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)  =>  (FMUL_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
22191        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMUL_D32_MM,
22192        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22193        // GIR_Coverage, 1122,
22194        GIR_Done,
22195      // Label 1276: @55402
22196      GIM_Try, /*On fail goto*//*Label 1277*/ 55425, // Rule ID 1123 //
22197        GIM_CheckFeatures, GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat,
22198        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
22199        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
22200        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
22201        // (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)  =>  (FMUL_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
22202        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMUL_D64_MM,
22203        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22204        // GIR_Coverage, 1123,
22205        GIR_Done,
22206      // Label 1277: @55425
22207      GIM_Reject,
22208    // Label 1273: @55426
22209    GIM_Reject,
22210    // Label 1266: @55427
22211    GIM_Try, /*On fail goto*//*Label 1278*/ 55551,
22212      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
22213      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
22214      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
22215      GIM_Try, /*On fail goto*//*Label 1279*/ 55486, // Rule ID 2347 //
22216        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
22217        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22218        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FEXP2,
22219        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
22220        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
22221        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
22222        GIM_CheckIsSafeToFold, /*InsnID*/1,
22223        // (fmul:{ *:[v2f64] } (fexp2:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wt), MSA128DOpnd:{ *:[v2f64] }:$ws)  =>  (FEXP2_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
22224        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXP2_D,
22225        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
22226        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
22227        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
22228        GIR_EraseFromParent, /*InsnID*/0,
22229        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22230        // GIR_Coverage, 2347,
22231        GIR_Done,
22232      // Label 1279: @55486
22233      GIM_Try, /*On fail goto*//*Label 1280*/ 55531, // Rule ID 685 //
22234        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
22235        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
22236        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
22237        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FEXP2,
22238        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
22239        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
22240        GIM_CheckIsSafeToFold, /*InsnID*/1,
22241        // (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, (fexp2:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wt))  =>  (FEXP2_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
22242        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXP2_D,
22243        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
22244        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws
22245        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
22246        GIR_EraseFromParent, /*InsnID*/0,
22247        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22248        // GIR_Coverage, 685,
22249        GIR_Done,
22250      // Label 1280: @55531
22251      GIM_Try, /*On fail goto*//*Label 1281*/ 55550, // Rule ID 721 //
22252        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
22253        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
22254        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
22255        // (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FMUL_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
22256        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMUL_D,
22257        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22258        // GIR_Coverage, 721,
22259        GIR_Done,
22260      // Label 1281: @55550
22261      GIM_Reject,
22262    // Label 1278: @55551
22263    GIM_Reject,
22264    // Label 1267: @55552
22265    GIM_Try, /*On fail goto*//*Label 1282*/ 55676,
22266      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
22267      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
22268      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
22269      GIM_Try, /*On fail goto*//*Label 1283*/ 55611, // Rule ID 2346 //
22270        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
22271        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22272        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FEXP2,
22273        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
22274        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
22275        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
22276        GIM_CheckIsSafeToFold, /*InsnID*/1,
22277        // (fmul:{ *:[v4f32] } (fexp2:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wt), MSA128WOpnd:{ *:[v4f32] }:$ws)  =>  (FEXP2_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
22278        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXP2_W,
22279        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
22280        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
22281        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
22282        GIR_EraseFromParent, /*InsnID*/0,
22283        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22284        // GIR_Coverage, 2346,
22285        GIR_Done,
22286      // Label 1283: @55611
22287      GIM_Try, /*On fail goto*//*Label 1284*/ 55656, // Rule ID 684 //
22288        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
22289        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
22290        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
22291        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FEXP2,
22292        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
22293        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
22294        GIM_CheckIsSafeToFold, /*InsnID*/1,
22295        // (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, (fexp2:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wt))  =>  (FEXP2_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
22296        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXP2_W,
22297        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
22298        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws
22299        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
22300        GIR_EraseFromParent, /*InsnID*/0,
22301        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22302        // GIR_Coverage, 684,
22303        GIR_Done,
22304      // Label 1284: @55656
22305      GIM_Try, /*On fail goto*//*Label 1285*/ 55675, // Rule ID 720 //
22306        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
22307        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
22308        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
22309        // (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FMUL_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
22310        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMUL_W,
22311        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22312        // GIR_Coverage, 720,
22313        GIR_Done,
22314      // Label 1285: @55675
22315      GIM_Reject,
22316    // Label 1282: @55676
22317    GIM_Reject,
22318    // Label 1268: @55677
22319    GIM_Reject,
22320    // Label 33: @55678
22321    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 7, /*)*//*default:*//*Label 1288*/ 55767,
22322    /*GILLT_v2s64*//*Label 1286*/ 55687, 0,
22323    /*GILLT_v4s32*//*Label 1287*/ 55727,
22324    // Label 1286: @55687
22325    GIM_Try, /*On fail goto*//*Label 1289*/ 55726, // Rule ID 709 //
22326      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
22327      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
22328      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
22329      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
22330      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
22331      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
22332      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
22333      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
22334      // (fma:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd_in, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FMADD_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd_in, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
22335      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMADD_D,
22336      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22337      // GIR_Coverage, 709,
22338      GIR_Done,
22339    // Label 1289: @55726
22340    GIM_Reject,
22341    // Label 1287: @55727
22342    GIM_Try, /*On fail goto*//*Label 1290*/ 55766, // Rule ID 708 //
22343      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
22344      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
22345      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
22346      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
22347      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
22348      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
22349      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
22350      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
22351      // (fma:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd_in, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FMADD_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd_in, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
22352      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMADD_W,
22353      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22354      // GIR_Coverage, 708,
22355      GIR_Done,
22356    // Label 1290: @55766
22357    GIM_Reject,
22358    // Label 1288: @55767
22359    GIM_Reject,
22360    // Label 34: @55768
22361    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 7, /*)*//*default:*//*Label 1295*/ 56018,
22362    /*GILLT_s32*//*Label 1291*/ 55780,
22363    /*GILLT_s64*//*Label 1292*/ 55850, 0,
22364    /*GILLT_v2s64*//*Label 1293*/ 55954, 0,
22365    /*GILLT_v4s32*//*Label 1294*/ 55986,
22366    // Label 1291: @55780
22367    GIM_Try, /*On fail goto*//*Label 1296*/ 55849,
22368      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
22369      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
22370      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
22371      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
22372      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
22373      GIM_Try, /*On fail goto*//*Label 1297*/ 55813, // Rule ID 148 //
22374        GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
22375        // (fdiv:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)  =>  (FDIV_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
22376        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FDIV_S,
22377        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22378        // GIR_Coverage, 148,
22379        GIR_Done,
22380      // Label 1297: @55813
22381      GIM_Try, /*On fail goto*//*Label 1298*/ 55824, // Rule ID 1115 //
22382        GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat,
22383        // (fdiv:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)  =>  (FDIV_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
22384        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FDIV_S_MM,
22385        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22386        // GIR_Coverage, 1115,
22387        GIR_Done,
22388      // Label 1298: @55824
22389      GIM_Try, /*On fail goto*//*Label 1299*/ 55848, // Rule ID 1173 //
22390        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
22391        // (fdiv:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)  =>  (FDIV_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs)
22392        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FDIV_S_MMR6,
22393        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
22394        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ft
22395        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fs
22396        GIR_EraseFromParent, /*InsnID*/0,
22397        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22398        // GIR_Coverage, 1173,
22399        GIR_Done,
22400      // Label 1299: @55848
22401      GIM_Reject,
22402    // Label 1296: @55849
22403    GIM_Reject,
22404    // Label 1292: @55850
22405    GIM_Try, /*On fail goto*//*Label 1300*/ 55953,
22406      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
22407      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
22408      GIM_Try, /*On fail goto*//*Label 1301*/ 55883, // Rule ID 149 //
22409        GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips,
22410        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
22411        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
22412        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
22413        // (fdiv:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)  =>  (FDIV_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
22414        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FDIV_D32,
22415        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22416        // GIR_Coverage, 149,
22417        GIR_Done,
22418      // Label 1301: @55883
22419      GIM_Try, /*On fail goto*//*Label 1302*/ 55906, // Rule ID 150 //
22420        GIM_CheckFeatures, GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips,
22421        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
22422        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
22423        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
22424        // (fdiv:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)  =>  (FDIV_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
22425        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FDIV_D64,
22426        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22427        // GIR_Coverage, 150,
22428        GIR_Done,
22429      // Label 1302: @55906
22430      GIM_Try, /*On fail goto*//*Label 1303*/ 55929, // Rule ID 1120 //
22431        GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit,
22432        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
22433        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
22434        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
22435        // (fdiv:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)  =>  (FDIV_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
22436        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FDIV_D32_MM,
22437        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22438        // GIR_Coverage, 1120,
22439        GIR_Done,
22440      // Label 1303: @55929
22441      GIM_Try, /*On fail goto*//*Label 1304*/ 55952, // Rule ID 1121 //
22442        GIM_CheckFeatures, GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat,
22443        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
22444        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
22445        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
22446        // (fdiv:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)  =>  (FDIV_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
22447        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FDIV_D64_MM,
22448        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22449        // GIR_Coverage, 1121,
22450        GIR_Done,
22451      // Label 1304: @55952
22452      GIM_Reject,
22453    // Label 1300: @55953
22454    GIM_Reject,
22455    // Label 1293: @55954
22456    GIM_Try, /*On fail goto*//*Label 1305*/ 55985, // Rule ID 681 //
22457      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
22458      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
22459      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
22460      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
22461      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
22462      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
22463      // (fdiv:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FDIV_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
22464      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FDIV_D,
22465      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22466      // GIR_Coverage, 681,
22467      GIR_Done,
22468    // Label 1305: @55985
22469    GIM_Reject,
22470    // Label 1294: @55986
22471    GIM_Try, /*On fail goto*//*Label 1306*/ 56017, // Rule ID 680 //
22472      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
22473      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
22474      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
22475      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
22476      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
22477      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
22478      // (fdiv:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FDIV_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
22479      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FDIV_W,
22480      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22481      // GIR_Coverage, 680,
22482      GIR_Done,
22483    // Label 1306: @56017
22484    GIM_Reject,
22485    // Label 1295: @56018
22486    GIM_Reject,
22487    // Label 35: @56019
22488    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 7, /*)*//*default:*//*Label 1309*/ 56076,
22489    /*GILLT_v2s64*//*Label 1307*/ 56028, 0,
22490    /*GILLT_v4s32*//*Label 1308*/ 56052,
22491    // Label 1307: @56028
22492    GIM_Try, /*On fail goto*//*Label 1310*/ 56051, // Rule ID 687 //
22493      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
22494      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
22495      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
22496      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
22497      // (fexp2:{ *:[v2f64] } MSA128D:{ *:[v2f64] }:$ws)  =>  (FEXP2_D_1_PSEUDO:{ *:[v2f64] } MSA128D:{ *:[v2f64] }:$ws)
22498      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FEXP2_D_1_PSEUDO,
22499      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22500      // GIR_Coverage, 687,
22501      GIR_Done,
22502    // Label 1310: @56051
22503    GIM_Reject,
22504    // Label 1308: @56052
22505    GIM_Try, /*On fail goto*//*Label 1311*/ 56075, // Rule ID 686 //
22506      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
22507      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
22508      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
22509      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
22510      // (fexp2:{ *:[v4f32] } MSA128W:{ *:[v4f32] }:$ws)  =>  (FEXP2_W_1_PSEUDO:{ *:[v4f32] } MSA128W:{ *:[v4f32] }:$ws)
22511      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FEXP2_W_1_PSEUDO,
22512      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22513      // GIR_Coverage, 686,
22514      GIR_Done,
22515    // Label 1311: @56075
22516    GIM_Reject,
22517    // Label 1309: @56076
22518    GIM_Reject,
22519    // Label 36: @56077
22520    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 7, /*)*//*default:*//*Label 1314*/ 56134,
22521    /*GILLT_v2s64*//*Label 1312*/ 56086, 0,
22522    /*GILLT_v4s32*//*Label 1313*/ 56110,
22523    // Label 1312: @56086
22524    GIM_Try, /*On fail goto*//*Label 1315*/ 56109, // Rule ID 707 //
22525      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
22526      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
22527      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
22528      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
22529      // (flog2:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)  =>  (FLOG2_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
22530      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FLOG2_D,
22531      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22532      // GIR_Coverage, 707,
22533      GIR_Done,
22534    // Label 1315: @56109
22535    GIM_Reject,
22536    // Label 1313: @56110
22537    GIM_Try, /*On fail goto*//*Label 1316*/ 56133, // Rule ID 706 //
22538      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
22539      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
22540      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
22541      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
22542      // (flog2:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)  =>  (FLOG2_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
22543      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FLOG2_W,
22544      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22545      // GIR_Coverage, 706,
22546      GIR_Done,
22547    // Label 1316: @56133
22548    GIM_Reject,
22549    // Label 1314: @56134
22550    GIM_Reject,
22551    // Label 37: @56135
22552    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1319*/ 57430,
22553    /*GILLT_s32*//*Label 1317*/ 56143,
22554    /*GILLT_s64*//*Label 1318*/ 56644,
22555    // Label 1317: @56143
22556    GIM_Try, /*On fail goto*//*Label 1320*/ 56643,
22557      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
22558      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
22559      GIM_Try, /*On fail goto*//*Label 1321*/ 56227, // Rule ID 1440 //
22560        GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6,
22561        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22562        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD,
22563        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
22564        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22565        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
22566        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL,
22567        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
22568        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
22569        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
22570        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
22571        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
22572        GIM_CheckIsSafeToFold, /*InsnID*/1,
22573        GIM_CheckIsSafeToFold, /*InsnID*/2,
22574        // (fneg:{ *:[f32] } (fadd:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr))  =>  (NMADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
22575        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_S,
22576        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
22577        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
22578        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
22579        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
22580        GIR_EraseFromParent, /*InsnID*/0,
22581        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22582        // GIR_Coverage, 1440,
22583        GIR_Done,
22584      // Label 1321: @56227
22585      GIM_Try, /*On fail goto*//*Label 1322*/ 56301, // Rule ID 2196 //
22586        GIM_CheckFeatures, GIFBS_HasMadd4_InMicroMips_InMicroMips_NoNaNsFPMath_NotMips32r6_NotMips32r6,
22587        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22588        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD,
22589        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
22590        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22591        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
22592        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL,
22593        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
22594        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
22595        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
22596        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
22597        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
22598        GIM_CheckIsSafeToFold, /*InsnID*/1,
22599        GIM_CheckIsSafeToFold, /*InsnID*/2,
22600        // (fneg:{ *:[f32] } (fadd:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr))  =>  (NMADD_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
22601        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_S_MM,
22602        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
22603        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
22604        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
22605        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
22606        GIR_EraseFromParent, /*InsnID*/0,
22607        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22608        // GIR_Coverage, 2196,
22609        GIR_Done,
22610      // Label 1322: @56301
22611      GIM_Try, /*On fail goto*//*Label 1323*/ 56375, // Rule ID 2382 //
22612        GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6,
22613        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22614        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD,
22615        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
22616        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22617        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
22618        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
22619        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL,
22620        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
22621        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
22622        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
22623        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
22624        GIM_CheckIsSafeToFold, /*InsnID*/1,
22625        GIM_CheckIsSafeToFold, /*InsnID*/2,
22626        // (fneg:{ *:[f32] } (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)))  =>  (NMADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
22627        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_S,
22628        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
22629        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fr
22630        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
22631        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
22632        GIR_EraseFromParent, /*InsnID*/0,
22633        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22634        // GIR_Coverage, 2382,
22635        GIR_Done,
22636      // Label 1323: @56375
22637      GIM_Try, /*On fail goto*//*Label 1324*/ 56449, // Rule ID 2484 //
22638        GIM_CheckFeatures, GIFBS_HasMadd4_InMicroMips_InMicroMips_NoNaNsFPMath_NotMips32r6_NotMips32r6,
22639        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22640        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD,
22641        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
22642        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22643        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
22644        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
22645        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL,
22646        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
22647        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
22648        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
22649        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
22650        GIM_CheckIsSafeToFold, /*InsnID*/1,
22651        GIM_CheckIsSafeToFold, /*InsnID*/2,
22652        // (fneg:{ *:[f32] } (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)))  =>  (NMADD_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
22653        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_S_MM,
22654        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
22655        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fr
22656        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
22657        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
22658        GIR_EraseFromParent, /*InsnID*/0,
22659        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22660        // GIR_Coverage, 2484,
22661        GIR_Done,
22662      // Label 1324: @56449
22663      GIM_Try, /*On fail goto*//*Label 1325*/ 56523, // Rule ID 1441 //
22664        GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6,
22665        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22666        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB,
22667        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
22668        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22669        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
22670        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL,
22671        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
22672        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
22673        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
22674        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
22675        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
22676        GIM_CheckIsSafeToFold, /*InsnID*/1,
22677        GIM_CheckIsSafeToFold, /*InsnID*/2,
22678        // (fneg:{ *:[f32] } (fsub:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr))  =>  (NMSUB_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
22679        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMSUB_S,
22680        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
22681        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
22682        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
22683        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
22684        GIR_EraseFromParent, /*InsnID*/0,
22685        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22686        // GIR_Coverage, 1441,
22687        GIR_Done,
22688      // Label 1325: @56523
22689      GIM_Try, /*On fail goto*//*Label 1326*/ 56597, // Rule ID 2197 //
22690        GIM_CheckFeatures, GIFBS_HasMadd4_InMicroMips_InMicroMips_NoNaNsFPMath_NotMips32r6_NotMips32r6,
22691        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22692        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB,
22693        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
22694        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22695        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
22696        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL,
22697        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
22698        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
22699        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
22700        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
22701        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
22702        GIM_CheckIsSafeToFold, /*InsnID*/1,
22703        GIM_CheckIsSafeToFold, /*InsnID*/2,
22704        // (fneg:{ *:[f32] } (fsub:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr))  =>  (NMSUB_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
22705        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMSUB_S_MM,
22706        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
22707        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
22708        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
22709        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
22710        GIR_EraseFromParent, /*InsnID*/0,
22711        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22712        // GIR_Coverage, 2197,
22713        GIR_Done,
22714      // Label 1326: @56597
22715      GIM_Try, /*On fail goto*//*Label 1327*/ 56612, // Rule ID 123 //
22716        GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat,
22717        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
22718        // (fneg:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)  =>  (FNEG_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
22719        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FNEG_S,
22720        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22721        // GIR_Coverage, 123,
22722        GIR_Done,
22723      // Label 1327: @56612
22724      GIM_Try, /*On fail goto*//*Label 1328*/ 56627, // Rule ID 1137 //
22725        GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat,
22726        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
22727        // (fneg:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)  =>  (FNEG_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
22728        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FNEG_S_MM,
22729        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22730        // GIR_Coverage, 1137,
22731        GIR_Done,
22732      // Label 1328: @56627
22733      GIM_Try, /*On fail goto*//*Label 1329*/ 56642, // Rule ID 1174 //
22734        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
22735        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
22736        // (fneg:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)  =>  (FNEG_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
22737        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FNEG_S_MMR6,
22738        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22739        // GIR_Coverage, 1174,
22740        GIR_Done,
22741      // Label 1329: @56642
22742      GIM_Reject,
22743    // Label 1320: @56643
22744    GIM_Reject,
22745    // Label 1318: @56644
22746    GIM_Try, /*On fail goto*//*Label 1330*/ 57429,
22747      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
22748      GIM_Try, /*On fail goto*//*Label 1331*/ 56728, // Rule ID 1442 //
22749        GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
22750        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
22751        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22752        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD,
22753        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
22754        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
22755        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
22756        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL,
22757        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
22758        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
22759        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
22760        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
22761        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
22762        GIM_CheckIsSafeToFold, /*InsnID*/1,
22763        GIM_CheckIsSafeToFold, /*InsnID*/2,
22764        // (fneg:{ *:[f64] } (fadd:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr))  =>  (NMADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
22765        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_D32,
22766        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
22767        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
22768        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
22769        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
22770        GIR_EraseFromParent, /*InsnID*/0,
22771        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22772        // GIR_Coverage, 1442,
22773        GIR_Done,
22774      // Label 1331: @56728
22775      GIM_Try, /*On fail goto*//*Label 1332*/ 56806, // Rule ID 1444 //
22776        GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6,
22777        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
22778        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22779        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD,
22780        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
22781        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
22782        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
22783        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL,
22784        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
22785        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
22786        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
22787        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
22788        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
22789        GIM_CheckIsSafeToFold, /*InsnID*/1,
22790        GIM_CheckIsSafeToFold, /*InsnID*/2,
22791        // (fneg:{ *:[f64] } (fadd:{ *:[f64] } (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr))  =>  (NMADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
22792        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_D64,
22793        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
22794        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
22795        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
22796        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
22797        GIR_EraseFromParent, /*InsnID*/0,
22798        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22799        // GIR_Coverage, 1444,
22800        GIR_Done,
22801      // Label 1332: @56806
22802      GIM_Try, /*On fail goto*//*Label 1333*/ 56884, // Rule ID 2198 //
22803        GIM_CheckFeatures, GIFBS_HasMadd4_InMicroMips_InMicroMips_NoNaNsFPMath_NotFP64bit_NotMips32r6_NotMips32r6,
22804        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
22805        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22806        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD,
22807        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
22808        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
22809        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
22810        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL,
22811        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
22812        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
22813        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
22814        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
22815        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
22816        GIM_CheckIsSafeToFold, /*InsnID*/1,
22817        GIM_CheckIsSafeToFold, /*InsnID*/2,
22818        // (fneg:{ *:[f64] } (fadd:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr))  =>  (NMADD_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
22819        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_D32_MM,
22820        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
22821        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
22822        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
22823        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
22824        GIR_EraseFromParent, /*InsnID*/0,
22825        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22826        // GIR_Coverage, 2198,
22827        GIR_Done,
22828      // Label 1333: @56884
22829      GIM_Try, /*On fail goto*//*Label 1334*/ 56962, // Rule ID 2383 //
22830        GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
22831        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
22832        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22833        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD,
22834        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
22835        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
22836        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
22837        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
22838        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL,
22839        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
22840        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
22841        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
22842        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
22843        GIM_CheckIsSafeToFold, /*InsnID*/1,
22844        GIM_CheckIsSafeToFold, /*InsnID*/2,
22845        // (fneg:{ *:[f64] } (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)))  =>  (NMADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
22846        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_D32,
22847        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
22848        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fr
22849        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
22850        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
22851        GIR_EraseFromParent, /*InsnID*/0,
22852        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22853        // GIR_Coverage, 2383,
22854        GIR_Done,
22855      // Label 1334: @56962
22856      GIM_Try, /*On fail goto*//*Label 1335*/ 57040, // Rule ID 2384 //
22857        GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6,
22858        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
22859        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22860        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD,
22861        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
22862        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
22863        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
22864        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
22865        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL,
22866        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
22867        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
22868        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
22869        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
22870        GIM_CheckIsSafeToFold, /*InsnID*/1,
22871        GIM_CheckIsSafeToFold, /*InsnID*/2,
22872        // (fneg:{ *:[f64] } (fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)))  =>  (NMADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
22873        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_D64,
22874        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
22875        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fr
22876        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
22877        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
22878        GIR_EraseFromParent, /*InsnID*/0,
22879        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22880        // GIR_Coverage, 2384,
22881        GIR_Done,
22882      // Label 1335: @57040
22883      GIM_Try, /*On fail goto*//*Label 1336*/ 57118, // Rule ID 2485 //
22884        GIM_CheckFeatures, GIFBS_HasMadd4_InMicroMips_InMicroMips_NoNaNsFPMath_NotFP64bit_NotMips32r6_NotMips32r6,
22885        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
22886        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22887        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD,
22888        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
22889        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
22890        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
22891        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
22892        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL,
22893        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
22894        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
22895        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
22896        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
22897        GIM_CheckIsSafeToFold, /*InsnID*/1,
22898        GIM_CheckIsSafeToFold, /*InsnID*/2,
22899        // (fneg:{ *:[f64] } (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)))  =>  (NMADD_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
22900        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_D32_MM,
22901        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
22902        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fr
22903        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
22904        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
22905        GIR_EraseFromParent, /*InsnID*/0,
22906        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22907        // GIR_Coverage, 2485,
22908        GIR_Done,
22909      // Label 1336: @57118
22910      GIM_Try, /*On fail goto*//*Label 1337*/ 57196, // Rule ID 1443 //
22911        GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
22912        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
22913        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22914        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB,
22915        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
22916        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
22917        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
22918        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL,
22919        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
22920        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
22921        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
22922        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
22923        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
22924        GIM_CheckIsSafeToFold, /*InsnID*/1,
22925        GIM_CheckIsSafeToFold, /*InsnID*/2,
22926        // (fneg:{ *:[f64] } (fsub:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr))  =>  (NMSUB_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
22927        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMSUB_D32,
22928        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
22929        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
22930        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
22931        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
22932        GIR_EraseFromParent, /*InsnID*/0,
22933        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22934        // GIR_Coverage, 1443,
22935        GIR_Done,
22936      // Label 1337: @57196
22937      GIM_Try, /*On fail goto*//*Label 1338*/ 57274, // Rule ID 1445 //
22938        GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6,
22939        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
22940        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22941        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB,
22942        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
22943        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
22944        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
22945        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL,
22946        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
22947        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
22948        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
22949        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
22950        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
22951        GIM_CheckIsSafeToFold, /*InsnID*/1,
22952        GIM_CheckIsSafeToFold, /*InsnID*/2,
22953        // (fneg:{ *:[f64] } (fsub:{ *:[f64] } (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr))  =>  (NMSUB_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
22954        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMSUB_D64,
22955        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
22956        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
22957        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
22958        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
22959        GIR_EraseFromParent, /*InsnID*/0,
22960        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22961        // GIR_Coverage, 1445,
22962        GIR_Done,
22963      // Label 1338: @57274
22964      GIM_Try, /*On fail goto*//*Label 1339*/ 57352, // Rule ID 2199 //
22965        GIM_CheckFeatures, GIFBS_HasMadd4_InMicroMips_InMicroMips_NoNaNsFPMath_NotFP64bit_NotMips32r6_NotMips32r6,
22966        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
22967        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22968        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB,
22969        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
22970        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
22971        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
22972        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL,
22973        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
22974        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
22975        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
22976        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
22977        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
22978        GIM_CheckIsSafeToFold, /*InsnID*/1,
22979        GIM_CheckIsSafeToFold, /*InsnID*/2,
22980        // (fneg:{ *:[f64] } (fsub:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr))  =>  (NMSUB_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
22981        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMSUB_D32_MM,
22982        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
22983        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
22984        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
22985        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
22986        GIR_EraseFromParent, /*InsnID*/0,
22987        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22988        // GIR_Coverage, 2199,
22989        GIR_Done,
22990      // Label 1339: @57352
22991      GIM_Try, /*On fail goto*//*Label 1340*/ 57371, // Rule ID 124 //
22992        GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips,
22993        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
22994        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
22995        // (fneg:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)  =>  (FNEG_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)
22996        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FNEG_D32,
22997        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22998        // GIR_Coverage, 124,
22999        GIR_Done,
23000      // Label 1340: @57371
23001      GIM_Try, /*On fail goto*//*Label 1341*/ 57390, // Rule ID 125 //
23002        GIM_CheckFeatures, GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips,
23003        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
23004        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
23005        // (fneg:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)  =>  (FNEG_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)
23006        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FNEG_D64,
23007        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23008        // GIR_Coverage, 125,
23009        GIR_Done,
23010      // Label 1341: @57390
23011      GIM_Try, /*On fail goto*//*Label 1342*/ 57409, // Rule ID 1138 //
23012        GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit,
23013        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
23014        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
23015        // (fneg:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)  =>  (FNEG_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)
23016        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FNEG_D32_MM,
23017        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23018        // GIR_Coverage, 1138,
23019        GIR_Done,
23020      // Label 1342: @57409
23021      GIM_Try, /*On fail goto*//*Label 1343*/ 57428, // Rule ID 1139 //
23022        GIM_CheckFeatures, GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat,
23023        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
23024        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
23025        // (fneg:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)  =>  (FNEG_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)
23026        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FNEG_D64_MM,
23027        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23028        // GIR_Coverage, 1139,
23029        GIR_Done,
23030      // Label 1343: @57428
23031      GIM_Reject,
23032    // Label 1330: @57429
23033    GIM_Reject,
23034    // Label 1319: @57430
23035    GIM_Reject,
23036    // Label 38: @57431
23037    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1346*/ 57579,
23038    /*GILLT_s32*//*Label 1344*/ 57439,
23039    /*GILLT_s64*//*Label 1345*/ 57463,
23040    // Label 1344: @57439
23041    GIM_Try, /*On fail goto*//*Label 1347*/ 57462, // Rule ID 1040 //
23042      GIM_CheckFeatures, GIFBS_HasMSA,
23043      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
23044      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
23045      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128F16RegClassID,
23046      // (fpextend:{ *:[f32] } MSA128F16:{ *:[f16] }:$ws)  =>  (MSA_FP_EXTEND_W_PSEUDO:{ *:[f32] } MSA128F16:{ *:[f16] }:$ws)
23047      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MSA_FP_EXTEND_W_PSEUDO,
23048      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23049      // GIR_Coverage, 1040,
23050      GIR_Done,
23051    // Label 1347: @57462
23052    GIM_Reject,
23053    // Label 1345: @57463
23054    GIM_Try, /*On fail goto*//*Label 1348*/ 57486, // Rule ID 1042 //
23055      GIM_CheckFeatures, GIFBS_HasMSA,
23056      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
23057      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
23058      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128F16RegClassID,
23059      // (fpextend:{ *:[f64] } MSA128F16:{ *:[f16] }:$ws)  =>  (MSA_FP_EXTEND_D_PSEUDO:{ *:[f64] } MSA128F16:{ *:[f16] }:$ws)
23060      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MSA_FP_EXTEND_D_PSEUDO,
23061      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23062      // GIR_Coverage, 1042,
23063      GIR_Done,
23064    // Label 1348: @57486
23065    GIM_Try, /*On fail goto*//*Label 1349*/ 57509, // Rule ID 1429 //
23066      GIM_CheckFeatures, GIFBS_HasStdEnc_NotFP64bit_NotInMicroMips,
23067      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
23068      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
23069      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
23070      // (fpextend:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src)  =>  (CVT_D32_S:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src)
23071      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CVT_D32_S,
23072      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23073      // GIR_Coverage, 1429,
23074      GIR_Done,
23075    // Label 1349: @57509
23076    GIM_Try, /*On fail goto*//*Label 1350*/ 57532, // Rule ID 1439 //
23077      GIM_CheckFeatures, GIFBS_HasStdEnc_IsFP64bit_NotInMicroMips,
23078      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
23079      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
23080      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
23081      // (fpextend:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src)  =>  (CVT_D64_S:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src)
23082      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CVT_D64_S,
23083      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23084      // GIR_Coverage, 1439,
23085      GIR_Done,
23086    // Label 1350: @57532
23087    GIM_Try, /*On fail goto*//*Label 1351*/ 57555, // Rule ID 2208 //
23088      GIM_CheckFeatures, GIFBS_InMicroMips_IsFP64bit,
23089      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
23090      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
23091      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
23092      // (fpextend:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src)  =>  (CVT_D64_S_MM:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src)
23093      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CVT_D64_S_MM,
23094      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23095      // GIR_Coverage, 2208,
23096      GIR_Done,
23097    // Label 1351: @57555
23098    GIM_Try, /*On fail goto*//*Label 1352*/ 57578, // Rule ID 2210 //
23099      GIM_CheckFeatures, GIFBS_InMicroMips_NotFP64bit,
23100      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
23101      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
23102      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
23103      // (fpextend:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src)  =>  (CVT_D32_S_MM:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src)
23104      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CVT_D32_S_MM,
23105      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23106      // GIR_Coverage, 2210,
23107      GIR_Done,
23108    // Label 1352: @57578
23109    GIM_Reject,
23110    // Label 1346: @57579
23111    GIM_Reject,
23112    // Label 39: @57580
23113    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 1355*/ 57707,
23114    /*GILLT_s16*//*Label 1353*/ 57588,
23115    /*GILLT_s32*//*Label 1354*/ 57635,
23116    // Label 1353: @57588
23117    GIM_Try, /*On fail goto*//*Label 1356*/ 57611, // Rule ID 1041 //
23118      GIM_CheckFeatures, GIFBS_HasMSA,
23119      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
23120      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128F16RegClassID,
23121      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
23122      // (fpround:{ *:[f16] } FGR32Opnd:{ *:[f32] }:$fs)  =>  (MSA_FP_ROUND_W_PSEUDO:{ *:[f16] } FGR32Opnd:{ *:[f32] }:$fs)
23123      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MSA_FP_ROUND_W_PSEUDO,
23124      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23125      // GIR_Coverage, 1041,
23126      GIR_Done,
23127    // Label 1356: @57611
23128    GIM_Try, /*On fail goto*//*Label 1357*/ 57634, // Rule ID 1043 //
23129      GIM_CheckFeatures, GIFBS_HasMSA,
23130      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
23131      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128F16RegClassID,
23132      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
23133      // (fpround:{ *:[f16] } FGR64Opnd:{ *:[f64] }:$fs)  =>  (MSA_FP_ROUND_D_PSEUDO:{ *:[f16] } FGR64Opnd:{ *:[f64] }:$fs)
23134      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MSA_FP_ROUND_D_PSEUDO,
23135      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23136      // GIR_Coverage, 1043,
23137      GIR_Done,
23138    // Label 1357: @57634
23139    GIM_Reject,
23140    // Label 1354: @57635
23141    GIM_Try, /*On fail goto*//*Label 1358*/ 57706,
23142      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
23143      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
23144      GIM_Try, /*On fail goto*//*Label 1359*/ 57660, // Rule ID 1428 //
23145        GIM_CheckFeatures, GIFBS_HasStdEnc_NotFP64bit_NotInMicroMips,
23146        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
23147        // (fpround:{ *:[f32] } AFGR64Opnd:{ *:[f64] }:$src)  =>  (CVT_S_D32:{ *:[f32] } AFGR64Opnd:{ *:[f64] }:$src)
23148        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CVT_S_D32,
23149        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23150        // GIR_Coverage, 1428,
23151        GIR_Done,
23152      // Label 1359: @57660
23153      GIM_Try, /*On fail goto*//*Label 1360*/ 57675, // Rule ID 1438 //
23154        GIM_CheckFeatures, GIFBS_HasStdEnc_IsFP64bit_NotInMicroMips,
23155        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
23156        // (fpround:{ *:[f32] } FGR64Opnd:{ *:[f64] }:$src)  =>  (CVT_S_D64:{ *:[f32] } FGR64Opnd:{ *:[f64] }:$src)
23157        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CVT_S_D64,
23158        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23159        // GIR_Coverage, 1438,
23160        GIR_Done,
23161      // Label 1360: @57675
23162      GIM_Try, /*On fail goto*//*Label 1361*/ 57690, // Rule ID 2207 //
23163        GIM_CheckFeatures, GIFBS_InMicroMips_IsFP64bit,
23164        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
23165        // (fpround:{ *:[f32] } FGR64Opnd:{ *:[f64] }:$src)  =>  (CVT_S_D64_MM:{ *:[f32] } FGR64Opnd:{ *:[f64] }:$src)
23166        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CVT_S_D64_MM,
23167        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23168        // GIR_Coverage, 2207,
23169        GIR_Done,
23170      // Label 1361: @57690
23171      GIM_Try, /*On fail goto*//*Label 1362*/ 57705, // Rule ID 2209 //
23172        GIM_CheckFeatures, GIFBS_InMicroMips_NotFP64bit,
23173        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
23174        // (fpround:{ *:[f32] } AFGR64Opnd:{ *:[f64] }:$src)  =>  (CVT_S_D32_MM:{ *:[f32] } AFGR64Opnd:{ *:[f64] }:$src)
23175        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CVT_S_D32_MM,
23176        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23177        // GIR_Coverage, 2209,
23178        GIR_Done,
23179      // Label 1362: @57705
23180      GIM_Reject,
23181    // Label 1358: @57706
23182    GIM_Reject,
23183    // Label 1355: @57707
23184    GIM_Reject,
23185    // Label 40: @57708
23186    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 7, /*)*//*default:*//*Label 1365*/ 57765,
23187    /*GILLT_v2s64*//*Label 1363*/ 57717, 0,
23188    /*GILLT_v4s32*//*Label 1364*/ 57741,
23189    // Label 1363: @57717
23190    GIM_Try, /*On fail goto*//*Label 1366*/ 57740, // Rule ID 761 //
23191      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
23192      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
23193      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
23194      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
23195      // (fp_to_sint:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)  =>  (FTRUNC_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
23196      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FTRUNC_S_D,
23197      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23198      // GIR_Coverage, 761,
23199      GIR_Done,
23200    // Label 1366: @57740
23201    GIM_Reject,
23202    // Label 1364: @57741
23203    GIM_Try, /*On fail goto*//*Label 1367*/ 57764, // Rule ID 760 //
23204      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
23205      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
23206      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
23207      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
23208      // (fp_to_sint:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)  =>  (FTRUNC_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
23209      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FTRUNC_S_W,
23210      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23211      // GIR_Coverage, 760,
23212      GIR_Done,
23213    // Label 1367: @57764
23214    GIM_Reject,
23215    // Label 1365: @57765
23216    GIM_Reject,
23217    // Label 41: @57766
23218    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 7, /*)*//*default:*//*Label 1370*/ 57823,
23219    /*GILLT_v2s64*//*Label 1368*/ 57775, 0,
23220    /*GILLT_v4s32*//*Label 1369*/ 57799,
23221    // Label 1368: @57775
23222    GIM_Try, /*On fail goto*//*Label 1371*/ 57798, // Rule ID 763 //
23223      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
23224      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
23225      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
23226      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
23227      // (fp_to_uint:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)  =>  (FTRUNC_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
23228      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FTRUNC_U_D,
23229      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23230      // GIR_Coverage, 763,
23231      GIR_Done,
23232    // Label 1371: @57798
23233    GIM_Reject,
23234    // Label 1369: @57799
23235    GIM_Try, /*On fail goto*//*Label 1372*/ 57822, // Rule ID 762 //
23236      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
23237      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
23238      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
23239      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
23240      // (fp_to_uint:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)  =>  (FTRUNC_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
23241      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FTRUNC_U_W,
23242      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23243      // GIR_Coverage, 762,
23244      GIR_Done,
23245    // Label 1372: @57822
23246    GIM_Reject,
23247    // Label 1370: @57823
23248    GIM_Reject,
23249    // Label 42: @57824
23250    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 7, /*)*//*default:*//*Label 1377*/ 57976,
23251    /*GILLT_s32*//*Label 1373*/ 57836,
23252    /*GILLT_s64*//*Label 1374*/ 57858, 0,
23253    /*GILLT_v2s64*//*Label 1375*/ 57928, 0,
23254    /*GILLT_v4s32*//*Label 1376*/ 57952,
23255    // Label 1373: @57836
23256    GIM_Try, /*On fail goto*//*Label 1378*/ 57857, // Rule ID 1423 //
23257      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
23258      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
23259      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
23260      // (sint_to_fp:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$src)  =>  (PseudoCVT_S_W:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$src)
23261      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PseudoCVT_S_W,
23262      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23263      // GIR_Coverage, 1423,
23264      GIR_Done,
23265    // Label 1378: @57857
23266    GIM_Reject,
23267    // Label 1374: @57858
23268    GIM_Try, /*On fail goto*//*Label 1379*/ 57881, // Rule ID 1426 //
23269      GIM_CheckFeatures, GIFBS_NotFP64bit,
23270      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
23271      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
23272      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
23273      // (sint_to_fp:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$src)  =>  (PseudoCVT_D32_W:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$src)
23274      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PseudoCVT_D32_W,
23275      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23276      // GIR_Coverage, 1426,
23277      GIR_Done,
23278    // Label 1379: @57881
23279    GIM_Try, /*On fail goto*//*Label 1380*/ 57904, // Rule ID 1432 //
23280      GIM_CheckFeatures, GIFBS_IsFP64bit,
23281      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
23282      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
23283      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
23284      // (sint_to_fp:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$src)  =>  (PseudoCVT_D64_W:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$src)
23285      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PseudoCVT_D64_W,
23286      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23287      // GIR_Coverage, 1432,
23288      GIR_Done,
23289    // Label 1380: @57904
23290    GIM_Try, /*On fail goto*//*Label 1381*/ 57927, // Rule ID 1434 //
23291      GIM_CheckFeatures, GIFBS_IsFP64bit,
23292      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
23293      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
23294      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
23295      // (sint_to_fp:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$src)  =>  (PseudoCVT_D64_L:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$src)
23296      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PseudoCVT_D64_L,
23297      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23298      // GIR_Coverage, 1434,
23299      GIR_Done,
23300    // Label 1381: @57927
23301    GIM_Reject,
23302    // Label 1375: @57928
23303    GIM_Try, /*On fail goto*//*Label 1382*/ 57951, // Rule ID 693 //
23304      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
23305      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
23306      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
23307      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
23308      // (sint_to_fp:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$ws)  =>  (FFINT_S_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$ws)
23309      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FFINT_S_D,
23310      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23311      // GIR_Coverage, 693,
23312      GIR_Done,
23313    // Label 1382: @57951
23314    GIM_Reject,
23315    // Label 1376: @57952
23316    GIM_Try, /*On fail goto*//*Label 1383*/ 57975, // Rule ID 692 //
23317      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
23318      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
23319      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
23320      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
23321      // (sint_to_fp:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$ws)  =>  (FFINT_S_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$ws)
23322      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FFINT_S_W,
23323      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23324      // GIR_Coverage, 692,
23325      GIR_Done,
23326    // Label 1383: @57975
23327    GIM_Reject,
23328    // Label 1377: @57976
23329    GIM_Reject,
23330    // Label 43: @57977
23331    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 7, /*)*//*default:*//*Label 1386*/ 58034,
23332    /*GILLT_v2s64*//*Label 1384*/ 57986, 0,
23333    /*GILLT_v4s32*//*Label 1385*/ 58010,
23334    // Label 1384: @57986
23335    GIM_Try, /*On fail goto*//*Label 1387*/ 58009, // Rule ID 695 //
23336      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
23337      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
23338      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
23339      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
23340      // (uint_to_fp:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$ws)  =>  (FFINT_U_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$ws)
23341      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FFINT_U_D,
23342      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23343      // GIR_Coverage, 695,
23344      GIR_Done,
23345    // Label 1387: @58009
23346    GIM_Reject,
23347    // Label 1385: @58010
23348    GIM_Try, /*On fail goto*//*Label 1388*/ 58033, // Rule ID 694 //
23349      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
23350      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
23351      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
23352      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
23353      // (uint_to_fp:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$ws)  =>  (FFINT_U_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$ws)
23354      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FFINT_U_W,
23355      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23356      // GIR_Coverage, 694,
23357      GIR_Done,
23358    // Label 1388: @58033
23359    GIM_Reject,
23360    // Label 1386: @58034
23361    GIM_Reject,
23362    // Label 44: @58035
23363    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 7, /*)*//*default:*//*Label 1393*/ 58217,
23364    /*GILLT_s32*//*Label 1389*/ 58047,
23365    /*GILLT_s64*//*Label 1390*/ 58085, 0,
23366    /*GILLT_v2s64*//*Label 1391*/ 58169, 0,
23367    /*GILLT_v4s32*//*Label 1392*/ 58193,
23368    // Label 1389: @58047
23369    GIM_Try, /*On fail goto*//*Label 1394*/ 58084,
23370      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
23371      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
23372      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
23373      GIM_Try, /*On fail goto*//*Label 1395*/ 58072, // Rule ID 120 //
23374        GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips_UseAbs,
23375        // (fabs:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)  =>  (FABS_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
23376        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FABS_S,
23377        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23378        // GIR_Coverage, 120,
23379        GIR_Done,
23380      // Label 1395: @58072
23381      GIM_Try, /*On fail goto*//*Label 1396*/ 58083, // Rule ID 1136 //
23382        GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat_UseAbs,
23383        // (fabs:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)  =>  (FABS_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
23384        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FABS_S_MM,
23385        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23386        // GIR_Coverage, 1136,
23387        GIR_Done,
23388      // Label 1396: @58083
23389      GIM_Reject,
23390    // Label 1394: @58084
23391    GIM_Reject,
23392    // Label 1390: @58085
23393    GIM_Try, /*On fail goto*//*Label 1397*/ 58168,
23394      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
23395      GIM_Try, /*On fail goto*//*Label 1398*/ 58110, // Rule ID 121 //
23396        GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_UseAbs,
23397        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
23398        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
23399        // (fabs:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)  =>  (FABS_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)
23400        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FABS_D32,
23401        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23402        // GIR_Coverage, 121,
23403        GIR_Done,
23404      // Label 1398: @58110
23405      GIM_Try, /*On fail goto*//*Label 1399*/ 58129, // Rule ID 122 //
23406        GIM_CheckFeatures, GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_UseAbs,
23407        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
23408        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
23409        // (fabs:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)  =>  (FABS_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)
23410        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FABS_D64,
23411        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23412        // GIR_Coverage, 122,
23413        GIR_Done,
23414      // Label 1399: @58129
23415      GIM_Try, /*On fail goto*//*Label 1400*/ 58148, // Rule ID 1134 //
23416        GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit,
23417        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
23418        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
23419        // (fabs:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)  =>  (FABS_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)
23420        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FABS_D32_MM,
23421        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23422        // GIR_Coverage, 1134,
23423        GIR_Done,
23424      // Label 1400: @58148
23425      GIM_Try, /*On fail goto*//*Label 1401*/ 58167, // Rule ID 1135 //
23426        GIM_CheckFeatures, GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat,
23427        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
23428        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
23429        // (fabs:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)  =>  (FABS_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)
23430        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FABS_D64_MM,
23431        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23432        // GIR_Coverage, 1135,
23433        GIR_Done,
23434      // Label 1401: @58167
23435      GIM_Reject,
23436    // Label 1397: @58168
23437    GIM_Reject,
23438    // Label 1391: @58169
23439    GIM_Try, /*On fail goto*//*Label 1402*/ 58192, // Rule ID 1027 //
23440      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
23441      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
23442      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
23443      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
23444      // (fabs:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)  =>  (FABS_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
23445      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FABS_D,
23446      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23447      // GIR_Coverage, 1027,
23448      GIR_Done,
23449    // Label 1402: @58192
23450    GIM_Reject,
23451    // Label 1392: @58193
23452    GIM_Try, /*On fail goto*//*Label 1403*/ 58216, // Rule ID 1026 //
23453      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
23454      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
23455      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
23456      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
23457      // (fabs:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)  =>  (FABS_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
23458      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FABS_W,
23459      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23460      // GIR_Coverage, 1026,
23461      GIR_Done,
23462    // Label 1403: @58216
23463    GIM_Reject,
23464    // Label 1393: @58217
23465    GIM_Reject,
23466    // Label 45: @58218
23467    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 9, /*)*//*default:*//*Label 1408*/ 58357,
23468    /*GILLT_v2s64*//*Label 1404*/ 58229, 0,
23469    /*GILLT_v4s32*//*Label 1405*/ 58261,
23470    /*GILLT_v8s16*//*Label 1406*/ 58293,
23471    /*GILLT_v16s8*//*Label 1407*/ 58325,
23472    // Label 1404: @58229
23473    GIM_Try, /*On fail goto*//*Label 1409*/ 58260, // Rule ID 855 //
23474      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
23475      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
23476      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
23477      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
23478      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
23479      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
23480      // (smin:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (MIN_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
23481      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MIN_S_D,
23482      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23483      // GIR_Coverage, 855,
23484      GIR_Done,
23485    // Label 1409: @58260
23486    GIM_Reject,
23487    // Label 1405: @58261
23488    GIM_Try, /*On fail goto*//*Label 1410*/ 58292, // Rule ID 854 //
23489      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
23490      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
23491      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
23492      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
23493      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
23494      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
23495      // (smin:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (MIN_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
23496      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MIN_S_W,
23497      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23498      // GIR_Coverage, 854,
23499      GIR_Done,
23500    // Label 1410: @58292
23501    GIM_Reject,
23502    // Label 1406: @58293
23503    GIM_Try, /*On fail goto*//*Label 1411*/ 58324, // Rule ID 853 //
23504      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
23505      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
23506      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
23507      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
23508      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
23509      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
23510      // (smin:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (MIN_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
23511      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MIN_S_H,
23512      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23513      // GIR_Coverage, 853,
23514      GIR_Done,
23515    // Label 1411: @58324
23516    GIM_Reject,
23517    // Label 1407: @58325
23518    GIM_Try, /*On fail goto*//*Label 1412*/ 58356, // Rule ID 852 //
23519      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
23520      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
23521      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
23522      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
23523      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
23524      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
23525      // (smin:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (MIN_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
23526      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MIN_S_B,
23527      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23528      // GIR_Coverage, 852,
23529      GIR_Done,
23530    // Label 1412: @58356
23531    GIM_Reject,
23532    // Label 1408: @58357
23533    GIM_Reject,
23534    // Label 46: @58358
23535    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 9, /*)*//*default:*//*Label 1417*/ 58497,
23536    /*GILLT_v2s64*//*Label 1413*/ 58369, 0,
23537    /*GILLT_v4s32*//*Label 1414*/ 58401,
23538    /*GILLT_v8s16*//*Label 1415*/ 58433,
23539    /*GILLT_v16s8*//*Label 1416*/ 58465,
23540    // Label 1413: @58369
23541    GIM_Try, /*On fail goto*//*Label 1418*/ 58400, // Rule ID 835 //
23542      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
23543      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
23544      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
23545      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
23546      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
23547      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
23548      // (smax:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (MAX_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
23549      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MAX_S_D,
23550      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23551      // GIR_Coverage, 835,
23552      GIR_Done,
23553    // Label 1418: @58400
23554    GIM_Reject,
23555    // Label 1414: @58401
23556    GIM_Try, /*On fail goto*//*Label 1419*/ 58432, // Rule ID 834 //
23557      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
23558      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
23559      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
23560      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
23561      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
23562      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
23563      // (smax:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (MAX_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
23564      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MAX_S_W,
23565      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23566      // GIR_Coverage, 834,
23567      GIR_Done,
23568    // Label 1419: @58432
23569    GIM_Reject,
23570    // Label 1415: @58433
23571    GIM_Try, /*On fail goto*//*Label 1420*/ 58464, // Rule ID 833 //
23572      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
23573      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
23574      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
23575      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
23576      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
23577      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
23578      // (smax:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (MAX_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
23579      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MAX_S_H,
23580      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23581      // GIR_Coverage, 833,
23582      GIR_Done,
23583    // Label 1420: @58464
23584    GIM_Reject,
23585    // Label 1416: @58465
23586    GIM_Try, /*On fail goto*//*Label 1421*/ 58496, // Rule ID 832 //
23587      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
23588      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
23589      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
23590      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
23591      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
23592      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
23593      // (smax:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (MAX_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
23594      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MAX_S_B,
23595      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23596      // GIR_Coverage, 832,
23597      GIR_Done,
23598    // Label 1421: @58496
23599    GIM_Reject,
23600    // Label 1417: @58497
23601    GIM_Reject,
23602    // Label 47: @58498
23603    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 9, /*)*//*default:*//*Label 1426*/ 58637,
23604    /*GILLT_v2s64*//*Label 1422*/ 58509, 0,
23605    /*GILLT_v4s32*//*Label 1423*/ 58541,
23606    /*GILLT_v8s16*//*Label 1424*/ 58573,
23607    /*GILLT_v16s8*//*Label 1425*/ 58605,
23608    // Label 1422: @58509
23609    GIM_Try, /*On fail goto*//*Label 1427*/ 58540, // Rule ID 859 //
23610      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
23611      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
23612      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
23613      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
23614      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
23615      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
23616      // (umin:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (MIN_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
23617      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MIN_U_D,
23618      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23619      // GIR_Coverage, 859,
23620      GIR_Done,
23621    // Label 1427: @58540
23622    GIM_Reject,
23623    // Label 1423: @58541
23624    GIM_Try, /*On fail goto*//*Label 1428*/ 58572, // Rule ID 858 //
23625      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
23626      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
23627      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
23628      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
23629      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
23630      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
23631      // (umin:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (MIN_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
23632      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MIN_U_W,
23633      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23634      // GIR_Coverage, 858,
23635      GIR_Done,
23636    // Label 1428: @58572
23637    GIM_Reject,
23638    // Label 1424: @58573
23639    GIM_Try, /*On fail goto*//*Label 1429*/ 58604, // Rule ID 857 //
23640      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
23641      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
23642      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
23643      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
23644      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
23645      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
23646      // (umin:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (MIN_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
23647      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MIN_U_H,
23648      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23649      // GIR_Coverage, 857,
23650      GIR_Done,
23651    // Label 1429: @58604
23652    GIM_Reject,
23653    // Label 1425: @58605
23654    GIM_Try, /*On fail goto*//*Label 1430*/ 58636, // Rule ID 856 //
23655      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
23656      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
23657      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
23658      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
23659      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
23660      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
23661      // (umin:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (MIN_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
23662      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MIN_U_B,
23663      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23664      // GIR_Coverage, 856,
23665      GIR_Done,
23666    // Label 1430: @58636
23667    GIM_Reject,
23668    // Label 1426: @58637
23669    GIM_Reject,
23670    // Label 48: @58638
23671    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 9, /*)*//*default:*//*Label 1435*/ 58777,
23672    /*GILLT_v2s64*//*Label 1431*/ 58649, 0,
23673    /*GILLT_v4s32*//*Label 1432*/ 58681,
23674    /*GILLT_v8s16*//*Label 1433*/ 58713,
23675    /*GILLT_v16s8*//*Label 1434*/ 58745,
23676    // Label 1431: @58649
23677    GIM_Try, /*On fail goto*//*Label 1436*/ 58680, // Rule ID 839 //
23678      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
23679      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
23680      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
23681      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
23682      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
23683      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
23684      // (umax:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (MAX_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
23685      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MAX_U_D,
23686      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23687      // GIR_Coverage, 839,
23688      GIR_Done,
23689    // Label 1436: @58680
23690    GIM_Reject,
23691    // Label 1432: @58681
23692    GIM_Try, /*On fail goto*//*Label 1437*/ 58712, // Rule ID 838 //
23693      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
23694      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
23695      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
23696      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
23697      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
23698      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
23699      // (umax:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (MAX_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
23700      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MAX_U_W,
23701      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23702      // GIR_Coverage, 838,
23703      GIR_Done,
23704    // Label 1437: @58712
23705    GIM_Reject,
23706    // Label 1433: @58713
23707    GIM_Try, /*On fail goto*//*Label 1438*/ 58744, // Rule ID 837 //
23708      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
23709      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
23710      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
23711      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
23712      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
23713      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
23714      // (umax:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (MAX_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
23715      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MAX_U_H,
23716      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23717      // GIR_Coverage, 837,
23718      GIR_Done,
23719    // Label 1438: @58744
23720    GIM_Reject,
23721    // Label 1434: @58745
23722    GIM_Try, /*On fail goto*//*Label 1439*/ 58776, // Rule ID 836 //
23723      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
23724      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
23725      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
23726      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
23727      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
23728      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
23729      // (umax:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (MAX_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
23730      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MAX_U_B,
23731      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23732      // GIR_Coverage, 836,
23733      GIR_Done,
23734    // Label 1439: @58776
23735    GIM_Reject,
23736    // Label 1435: @58777
23737    GIM_Reject,
23738    // Label 49: @58778
23739    GIM_Try, /*On fail goto*//*Label 1440*/ 58862,
23740      GIM_CheckIsMBB, /*MI*/0, /*Op*/0,
23741      GIM_Try, /*On fail goto*//*Label 1441*/ 58797, // Rule ID 85 //
23742        GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips_RelocNotPIC,
23743        // (br (bb:{ *:[Other] }):$target)  =>  (J (bb:{ *:[Other] }):$target)
23744        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::J,
23745        GIR_AddImplicitDef, /*InsnID*/0, Mips::AT,
23746        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23747        // GIR_Coverage, 85,
23748        GIR_Done,
23749      // Label 1441: @58797
23750      GIM_Try, /*On fail goto*//*Label 1442*/ 58811, // Rule ID 92 //
23751        GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
23752        // (br (bb:{ *:[Other] }):$offset)  =>  (B (bb:{ *:[Other] }):$offset)
23753        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::B,
23754        GIR_AddImplicitDef, /*InsnID*/0, Mips::AT,
23755        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23756        // GIR_Coverage, 92,
23757        GIR_Done,
23758      // Label 1442: @58811
23759      GIM_Try, /*On fail goto*//*Label 1443*/ 58825, // Rule ID 1088 //
23760        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6_RelocNotPIC,
23761        // (br (bb:{ *:[Other] }):$target)  =>  (J_MM (bb:{ *:[Other] }):$target)
23762        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::J_MM,
23763        GIR_AddImplicitDef, /*InsnID*/0, Mips::AT,
23764        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23765        // GIR_Coverage, 1088,
23766        GIR_Done,
23767      // Label 1443: @58825
23768      GIM_Try, /*On fail goto*//*Label 1444*/ 58839, // Rule ID 1097 //
23769        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6_RelocPIC,
23770        // (br (bb:{ *:[Other] }):$offset)  =>  (B_MM (bb:{ *:[Other] }):$offset)
23771        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::B_MM,
23772        GIR_AddImplicitDef, /*InsnID*/0, Mips::AT,
23773        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23774        // GIR_Coverage, 1097,
23775        GIR_Done,
23776      // Label 1444: @58839
23777      GIM_Try, /*On fail goto*//*Label 1445*/ 58850, // Rule ID 1153 //
23778        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
23779        // (br (bb:{ *:[Other] }):$offset)  =>  (BC_MMR6 (bb:{ *:[Other] }):$offset)
23780        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::BC_MMR6,
23781        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23782        // GIR_Coverage, 1153,
23783        GIR_Done,
23784      // Label 1445: @58850
23785      GIM_Try, /*On fail goto*//*Label 1446*/ 58861, // Rule ID 1817 //
23786        GIM_CheckFeatures, GIFBS_InMips16Mode,
23787        // (br (bb:{ *:[Other] }):$imm16)  =>  (Bimm16 (bb:{ *:[Other] }):$imm16)
23788        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::Bimm16,
23789        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23790        // GIR_Coverage, 1817,
23791        GIR_Done,
23792      // Label 1446: @58861
23793      GIM_Reject,
23794    // Label 1440: @58862
23795    GIM_Reject,
23796    // Label 50: @58863
23797    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 1453*/ 59297,
23798    /*GILLT_s32*//*Label 1447*/ 58877,
23799    /*GILLT_s64*//*Label 1448*/ 59069, 0,
23800    /*GILLT_v2s64*//*Label 1449*/ 59201, 0,
23801    /*GILLT_v4s32*//*Label 1450*/ 59225,
23802    /*GILLT_v8s16*//*Label 1451*/ 59249,
23803    /*GILLT_v16s8*//*Label 1452*/ 59273,
23804    // Label 1447: @58877
23805    GIM_Try, /*On fail goto*//*Label 1454*/ 59068,
23806      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
23807      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
23808      GIM_Try, /*On fail goto*//*Label 1455*/ 58932, // Rule ID 103 //
23809        GIM_CheckFeatures, GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
23810        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23811        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
23812        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
23813        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
23814        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
23815        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
23816        GIM_CheckIsSafeToFold, /*InsnID*/1,
23817        // (ctlz:{ *:[i32] } (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] }))  =>  (CLO:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
23818        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CLO,
23819        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
23820        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
23821        GIR_EraseFromParent, /*InsnID*/0,
23822        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23823        // GIR_Coverage, 103,
23824        GIR_Done,
23825      // Label 1455: @58932
23826      GIM_Try, /*On fail goto*//*Label 1456*/ 58977, // Rule ID 298 //
23827        GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc,
23828        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23829        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
23830        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
23831        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
23832        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
23833        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
23834        GIM_CheckIsSafeToFold, /*InsnID*/1,
23835        // (ctlz:{ *:[i32] } (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] }))  =>  (CLO_R6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
23836        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CLO_R6,
23837        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
23838        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
23839        GIR_EraseFromParent, /*InsnID*/0,
23840        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23841        // GIR_Coverage, 298,
23842        GIR_Done,
23843      // Label 1456: @58977
23844      GIM_Try, /*On fail goto*//*Label 1457*/ 59022, // Rule ID 1084 //
23845        GIM_CheckFeatures, GIFBS_InMicroMips,
23846        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23847        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
23848        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
23849        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
23850        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
23851        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
23852        GIM_CheckIsSafeToFold, /*InsnID*/1,
23853        // (ctlz:{ *:[i32] } (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] }))  =>  (CLO_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
23854        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CLO_MM,
23855        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
23856        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
23857        GIR_EraseFromParent, /*InsnID*/0,
23858        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23859        // GIR_Coverage, 1084,
23860        GIR_Done,
23861      // Label 1457: @59022
23862      GIM_Try, /*On fail goto*//*Label 1458*/ 59037, // Rule ID 102 //
23863        GIM_CheckFeatures, GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
23864        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
23865        // (ctlz:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)  =>  (CLZ:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
23866        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CLZ,
23867        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23868        // GIR_Coverage, 102,
23869        GIR_Done,
23870      // Label 1458: @59037
23871      GIM_Try, /*On fail goto*//*Label 1459*/ 59052, // Rule ID 299 //
23872        GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc,
23873        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
23874        // (ctlz:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)  =>  (CLZ_R6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
23875        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CLZ_R6,
23876        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23877        // GIR_Coverage, 299,
23878        GIR_Done,
23879      // Label 1459: @59052
23880      GIM_Try, /*On fail goto*//*Label 1460*/ 59067, // Rule ID 1083 //
23881        GIM_CheckFeatures, GIFBS_InMicroMips,
23882        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
23883        // (ctlz:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)  =>  (CLZ_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
23884        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CLZ_MM,
23885        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23886        // GIR_Coverage, 1083,
23887        GIR_Done,
23888      // Label 1460: @59067
23889      GIM_Reject,
23890    // Label 1454: @59068
23891    GIM_Reject,
23892    // Label 1448: @59069
23893    GIM_Try, /*On fail goto*//*Label 1461*/ 59200,
23894      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
23895      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
23896      GIM_Try, /*On fail goto*//*Label 1462*/ 59124, // Rule ID 252 //
23897        GIM_CheckFeatures, GIFBS_HasMips64_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips64r6,
23898        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23899        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
23900        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
23901        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
23902        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
23903        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
23904        GIM_CheckIsSafeToFold, /*InsnID*/1,
23905        // (ctlz:{ *:[i64] } (xor:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, -1:{ *:[i64] }))  =>  (DCLO:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs)
23906        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DCLO,
23907        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
23908        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
23909        GIR_EraseFromParent, /*InsnID*/0,
23910        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23911        // GIR_Coverage, 252,
23912        GIR_Done,
23913      // Label 1462: @59124
23914      GIM_Try, /*On fail goto*//*Label 1463*/ 59169, // Rule ID 327 //
23915        GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
23916        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23917        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
23918        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
23919        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
23920        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
23921        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
23922        GIM_CheckIsSafeToFold, /*InsnID*/1,
23923        // (ctlz:{ *:[i64] } (xor:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, -1:{ *:[i64] }))  =>  (DCLO_R6:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs)
23924        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DCLO_R6,
23925        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
23926        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
23927        GIR_EraseFromParent, /*InsnID*/0,
23928        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23929        // GIR_Coverage, 327,
23930        GIR_Done,
23931      // Label 1463: @59169
23932      GIM_Try, /*On fail goto*//*Label 1464*/ 59184, // Rule ID 251 //
23933        GIM_CheckFeatures, GIFBS_HasMips64_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips64r6,
23934        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
23935        // (ctlz:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs)  =>  (DCLZ:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs)
23936        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DCLZ,
23937        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23938        // GIR_Coverage, 251,
23939        GIR_Done,
23940      // Label 1464: @59184
23941      GIM_Try, /*On fail goto*//*Label 1465*/ 59199, // Rule ID 328 //
23942        GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
23943        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
23944        // (ctlz:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs)  =>  (DCLZ_R6:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs)
23945        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DCLZ_R6,
23946        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23947        // GIR_Coverage, 328,
23948        GIR_Done,
23949      // Label 1465: @59199
23950      GIM_Reject,
23951    // Label 1461: @59200
23952    GIM_Reject,
23953    // Label 1449: @59201
23954    GIM_Try, /*On fail goto*//*Label 1466*/ 59224, // Rule ID 899 //
23955      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
23956      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
23957      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
23958      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
23959      // (ctlz:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws)  =>  (NLZC_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws)
23960      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::NLZC_D,
23961      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23962      // GIR_Coverage, 899,
23963      GIR_Done,
23964    // Label 1466: @59224
23965    GIM_Reject,
23966    // Label 1450: @59225
23967    GIM_Try, /*On fail goto*//*Label 1467*/ 59248, // Rule ID 898 //
23968      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
23969      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
23970      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
23971      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
23972      // (ctlz:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws)  =>  (NLZC_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws)
23973      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::NLZC_W,
23974      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23975      // GIR_Coverage, 898,
23976      GIR_Done,
23977    // Label 1467: @59248
23978    GIM_Reject,
23979    // Label 1451: @59249
23980    GIM_Try, /*On fail goto*//*Label 1468*/ 59272, // Rule ID 897 //
23981      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
23982      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
23983      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
23984      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
23985      // (ctlz:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws)  =>  (NLZC_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws)
23986      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::NLZC_H,
23987      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23988      // GIR_Coverage, 897,
23989      GIR_Done,
23990    // Label 1468: @59272
23991    GIM_Reject,
23992    // Label 1452: @59273
23993    GIM_Try, /*On fail goto*//*Label 1469*/ 59296, // Rule ID 896 //
23994      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
23995      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
23996      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
23997      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
23998      // (ctlz:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws)  =>  (NLZC_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws)
23999      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::NLZC_B,
24000      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24001      // GIR_Coverage, 896,
24002      GIR_Done,
24003    // Label 1469: @59296
24004    GIM_Reject,
24005    // Label 1453: @59297
24006    GIM_Reject,
24007    // Label 51: @59298
24008    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 1476*/ 59456,
24009    /*GILLT_s32*//*Label 1470*/ 59312,
24010    /*GILLT_s64*//*Label 1471*/ 59336, 0,
24011    /*GILLT_v2s64*//*Label 1472*/ 59360, 0,
24012    /*GILLT_v4s32*//*Label 1473*/ 59384,
24013    /*GILLT_v8s16*//*Label 1474*/ 59408,
24014    /*GILLT_v16s8*//*Label 1475*/ 59432,
24015    // Label 1470: @59312
24016    GIM_Try, /*On fail goto*//*Label 1477*/ 59335, // Rule ID 266 //
24017      GIM_CheckFeatures, GIFBS_HasCnMips,
24018      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
24019      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
24020      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
24021      // (ctpop:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)  =>  (POP:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
24022      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::POP,
24023      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24024      // GIR_Coverage, 266,
24025      GIR_Done,
24026    // Label 1477: @59335
24027    GIM_Reject,
24028    // Label 1471: @59336
24029    GIM_Try, /*On fail goto*//*Label 1478*/ 59359, // Rule ID 267 //
24030      GIM_CheckFeatures, GIFBS_HasCnMips,
24031      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
24032      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
24033      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
24034      // (ctpop:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs)  =>  (DPOP:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs)
24035      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DPOP,
24036      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24037      // GIR_Coverage, 267,
24038      GIR_Done,
24039    // Label 1478: @59359
24040    GIM_Reject,
24041    // Label 1472: @59360
24042    GIM_Try, /*On fail goto*//*Label 1479*/ 59383, // Rule ID 921 //
24043      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
24044      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
24045      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
24046      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
24047      // (ctpop:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws)  =>  (PCNT_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws)
24048      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PCNT_D,
24049      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24050      // GIR_Coverage, 921,
24051      GIR_Done,
24052    // Label 1479: @59383
24053    GIM_Reject,
24054    // Label 1473: @59384
24055    GIM_Try, /*On fail goto*//*Label 1480*/ 59407, // Rule ID 920 //
24056      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
24057      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
24058      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
24059      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
24060      // (ctpop:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws)  =>  (PCNT_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws)
24061      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PCNT_W,
24062      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24063      // GIR_Coverage, 920,
24064      GIR_Done,
24065    // Label 1480: @59407
24066    GIM_Reject,
24067    // Label 1474: @59408
24068    GIM_Try, /*On fail goto*//*Label 1481*/ 59431, // Rule ID 919 //
24069      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
24070      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
24071      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
24072      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
24073      // (ctpop:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws)  =>  (PCNT_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws)
24074      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PCNT_H,
24075      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24076      // GIR_Coverage, 919,
24077      GIR_Done,
24078    // Label 1481: @59431
24079    GIM_Reject,
24080    // Label 1475: @59432
24081    GIM_Try, /*On fail goto*//*Label 1482*/ 59455, // Rule ID 918 //
24082      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
24083      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
24084      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
24085      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
24086      // (ctpop:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws)  =>  (PCNT_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws)
24087      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PCNT_B,
24088      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24089      // GIR_Coverage, 918,
24090      GIR_Done,
24091    // Label 1482: @59455
24092    GIM_Reject,
24093    // Label 1476: @59456
24094    GIM_Reject,
24095    // Label 52: @59457
24096    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1485*/ 59608,
24097    /*GILLT_s32*//*Label 1483*/ 59465,
24098    /*GILLT_s64*//*Label 1484*/ 59559,
24099    // Label 1483: @59465
24100    GIM_Try, /*On fail goto*//*Label 1486*/ 59558,
24101      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
24102      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
24103      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
24104      GIM_Try, /*On fail goto*//*Label 1487*/ 59518, // Rule ID 1409 //
24105        GIM_CheckFeatures, GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips,
24106        // (bswap:{ *:[i32] } GPR32:{ *:[i32] }:$rt)  =>  (ROTR:{ *:[i32] } (WSBH:{ *:[i32] } GPR32:{ *:[i32] }:$rt), 16:{ *:[i32] })
24107        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
24108        GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::WSBH,
24109        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
24110        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rt
24111        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
24112        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ROTR,
24113        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
24114        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24115        GIR_AddImm, /*InsnID*/0, /*Imm*/16,
24116        GIR_EraseFromParent, /*InsnID*/0,
24117        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24118        // GIR_Coverage, 1409,
24119        GIR_Done,
24120      // Label 1487: @59518
24121      GIM_Try, /*On fail goto*//*Label 1488*/ 59557, // Rule ID 2139 //
24122        GIM_CheckFeatures, GIFBS_InMicroMips,
24123        // (bswap:{ *:[i32] } GPR32:{ *:[i32] }:$rt)  =>  (ROTR_MM:{ *:[i32] } (WSBH_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rt), 16:{ *:[i32] })
24124        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
24125        GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::WSBH_MM,
24126        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
24127        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rt
24128        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
24129        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ROTR_MM,
24130        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
24131        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24132        GIR_AddImm, /*InsnID*/0, /*Imm*/16,
24133        GIR_EraseFromParent, /*InsnID*/0,
24134        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24135        // GIR_Coverage, 2139,
24136        GIR_Done,
24137      // Label 1488: @59557
24138      GIM_Reject,
24139    // Label 1486: @59558
24140    GIM_Reject,
24141    // Label 1484: @59559
24142    GIM_Try, /*On fail goto*//*Label 1489*/ 59607, // Rule ID 1566 //
24143      GIM_CheckFeatures, GIFBS_HasMips64r2_HasStdEnc,
24144      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
24145      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
24146      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
24147      // (bswap:{ *:[i64] } GPR64:{ *:[i64] }:$rt)  =>  (DSHD:{ *:[i64] } (DSBH:{ *:[i64] } GPR64:{ *:[i64] }:$rt))
24148      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
24149      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::DSBH,
24150      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
24151      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rt
24152      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
24153      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSHD,
24154      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
24155      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24156      GIR_EraseFromParent, /*InsnID*/0,
24157      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24158      // GIR_Coverage, 1566,
24159      GIR_Done,
24160    // Label 1489: @59607
24161    GIM_Reject,
24162    // Label 1485: @59608
24163    GIM_Reject,
24164    // Label 53: @59609
24165    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 7, /*)*//*default:*//*Label 1494*/ 59791,
24166    /*GILLT_s32*//*Label 1490*/ 59621,
24167    /*GILLT_s64*//*Label 1491*/ 59659, 0,
24168    /*GILLT_v2s64*//*Label 1492*/ 59743, 0,
24169    /*GILLT_v4s32*//*Label 1493*/ 59767,
24170    // Label 1490: @59621
24171    GIM_Try, /*On fail goto*//*Label 1495*/ 59658,
24172      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
24173      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
24174      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
24175      GIM_Try, /*On fail goto*//*Label 1496*/ 59646, // Rule ID 126 //
24176        GIM_CheckFeatures, GIFBS_HasMips2_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
24177        // (fsqrt:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)  =>  (FSQRT_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
24178        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSQRT_S,
24179        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24180        // GIR_Coverage, 126,
24181        GIR_Done,
24182      // Label 1496: @59646
24183      GIM_Try, /*On fail goto*//*Label 1497*/ 59657, // Rule ID 1146 //
24184        GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat,
24185        // (fsqrt:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)  =>  (FSQRT_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
24186        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSQRT_S_MM,
24187        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24188        // GIR_Coverage, 1146,
24189        GIR_Done,
24190      // Label 1497: @59657
24191      GIM_Reject,
24192    // Label 1495: @59658
24193    GIM_Reject,
24194    // Label 1491: @59659
24195    GIM_Try, /*On fail goto*//*Label 1498*/ 59742,
24196      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
24197      GIM_Try, /*On fail goto*//*Label 1499*/ 59684, // Rule ID 127 //
24198        GIM_CheckFeatures, GIFBS_HasMips2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips,
24199        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
24200        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
24201        // (fsqrt:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)  =>  (FSQRT_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)
24202        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSQRT_D32,
24203        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24204        // GIR_Coverage, 127,
24205        GIR_Done,
24206      // Label 1499: @59684
24207      GIM_Try, /*On fail goto*//*Label 1500*/ 59703, // Rule ID 128 //
24208        GIM_CheckFeatures, GIFBS_HasMips2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips,
24209        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
24210        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
24211        // (fsqrt:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)  =>  (FSQRT_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)
24212        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSQRT_D64,
24213        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24214        // GIR_Coverage, 128,
24215        GIR_Done,
24216      // Label 1500: @59703
24217      GIM_Try, /*On fail goto*//*Label 1501*/ 59722, // Rule ID 1132 //
24218        GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit,
24219        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
24220        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
24221        // (fsqrt:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)  =>  (FSQRT_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)
24222        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSQRT_D32_MM,
24223        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24224        // GIR_Coverage, 1132,
24225        GIR_Done,
24226      // Label 1501: @59722
24227      GIM_Try, /*On fail goto*//*Label 1502*/ 59741, // Rule ID 1133 //
24228        GIM_CheckFeatures, GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat,
24229        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
24230        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
24231        // (fsqrt:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)  =>  (FSQRT_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)
24232        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSQRT_D64_MM,
24233        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24234        // GIR_Coverage, 1133,
24235        GIR_Done,
24236      // Label 1502: @59741
24237      GIM_Reject,
24238    // Label 1498: @59742
24239    GIM_Reject,
24240    // Label 1492: @59743
24241    GIM_Try, /*On fail goto*//*Label 1503*/ 59766, // Rule ID 741 //
24242      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
24243      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
24244      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
24245      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
24246      // (fsqrt:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)  =>  (FSQRT_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
24247      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSQRT_D,
24248      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24249      // GIR_Coverage, 741,
24250      GIR_Done,
24251    // Label 1503: @59766
24252    GIM_Reject,
24253    // Label 1493: @59767
24254    GIM_Try, /*On fail goto*//*Label 1504*/ 59790, // Rule ID 740 //
24255      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
24256      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
24257      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
24258      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
24259      // (fsqrt:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)  =>  (FSQRT_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
24260      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSQRT_W,
24261      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24262      // GIR_Coverage, 740,
24263      GIR_Done,
24264    // Label 1504: @59790
24265    GIM_Reject,
24266    // Label 1494: @59791
24267    GIM_Reject,
24268    // Label 54: @59792
24269    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 7, /*)*//*default:*//*Label 1507*/ 59849,
24270    /*GILLT_v2s64*//*Label 1505*/ 59801, 0,
24271    /*GILLT_v4s32*//*Label 1506*/ 59825,
24272    // Label 1505: @59801
24273    GIM_Try, /*On fail goto*//*Label 1508*/ 59824, // Rule ID 723 //
24274      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
24275      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
24276      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
24277      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
24278      // (frint:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)  =>  (FRINT_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
24279      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FRINT_D,
24280      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24281      // GIR_Coverage, 723,
24282      GIR_Done,
24283    // Label 1508: @59824
24284    GIM_Reject,
24285    // Label 1506: @59825
24286    GIM_Try, /*On fail goto*//*Label 1509*/ 59848, // Rule ID 722 //
24287      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
24288      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
24289      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
24290      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
24291      // (frint:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)  =>  (FRINT_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
24292      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FRINT_W,
24293      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24294      // GIR_Coverage, 722,
24295      GIR_Done,
24296    // Label 1509: @59848
24297    GIM_Reject,
24298    // Label 1507: @59849
24299    GIM_Reject,
24300    // Label 55: @59850
24301    GIM_Reject,
24302    };
24303  return MatchTable0;
24304}
24305#endif // ifdef GET_GLOBALISEL_IMPL
24306#ifdef GET_GLOBALISEL_PREDICATES_DECL
24307PredicateBitset AvailableModuleFeatures;
24308mutable PredicateBitset AvailableFunctionFeatures;
24309PredicateBitset getAvailableFeatures() const {
24310  return AvailableModuleFeatures | AvailableFunctionFeatures;
24311}
24312PredicateBitset
24313computeAvailableModuleFeatures(const MipsSubtarget *Subtarget) const;
24314PredicateBitset
24315computeAvailableFunctionFeatures(const MipsSubtarget *Subtarget,
24316                                 const MachineFunction *MF) const;
24317void setupGeneratedPerFunctionState(MachineFunction &MF) override;
24318#endif // ifdef GET_GLOBALISEL_PREDICATES_DECL
24319#ifdef GET_GLOBALISEL_PREDICATES_INIT
24320AvailableModuleFeatures(computeAvailableModuleFeatures(&STI)),
24321AvailableFunctionFeatures()
24322#endif // ifdef GET_GLOBALISEL_PREDICATES_INIT
24323