1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2|* *| 3|* Target Register Enum Values *| 4|* *| 5|* Automatically generated file, do not edit! *| 6|* *| 7\*===----------------------------------------------------------------------===*/ 8 9 10#ifdef GET_REGINFO_ENUM 11#undef GET_REGINFO_ENUM 12 13namespace llvm { 14 15class MCRegisterClass; 16extern const MCRegisterClass RISCVMCRegisterClasses[]; 17 18namespace RISCV { 19enum { 20 NoRegister, 21 X0 = 1, 22 X1 = 2, 23 X2 = 3, 24 X3 = 4, 25 X4 = 5, 26 X5 = 6, 27 X6 = 7, 28 X7 = 8, 29 X8 = 9, 30 X9 = 10, 31 X10 = 11, 32 X11 = 12, 33 X12 = 13, 34 X13 = 14, 35 X14 = 15, 36 X15 = 16, 37 X16 = 17, 38 X17 = 18, 39 X18 = 19, 40 X19 = 20, 41 X20 = 21, 42 X21 = 22, 43 X22 = 23, 44 X23 = 24, 45 X24 = 25, 46 X25 = 26, 47 X26 = 27, 48 X27 = 28, 49 X28 = 29, 50 X29 = 30, 51 X30 = 31, 52 X31 = 32, 53 F0_D = 33, 54 F1_D = 34, 55 F2_D = 35, 56 F3_D = 36, 57 F4_D = 37, 58 F5_D = 38, 59 F6_D = 39, 60 F7_D = 40, 61 F8_D = 41, 62 F9_D = 42, 63 F10_D = 43, 64 F11_D = 44, 65 F12_D = 45, 66 F13_D = 46, 67 F14_D = 47, 68 F15_D = 48, 69 F16_D = 49, 70 F17_D = 50, 71 F18_D = 51, 72 F19_D = 52, 73 F20_D = 53, 74 F21_D = 54, 75 F22_D = 55, 76 F23_D = 56, 77 F24_D = 57, 78 F25_D = 58, 79 F26_D = 59, 80 F27_D = 60, 81 F28_D = 61, 82 F29_D = 62, 83 F30_D = 63, 84 F31_D = 64, 85 F0_F = 65, 86 F1_F = 66, 87 F2_F = 67, 88 F3_F = 68, 89 F4_F = 69, 90 F5_F = 70, 91 F6_F = 71, 92 F7_F = 72, 93 F8_F = 73, 94 F9_F = 74, 95 F10_F = 75, 96 F11_F = 76, 97 F12_F = 77, 98 F13_F = 78, 99 F14_F = 79, 100 F15_F = 80, 101 F16_F = 81, 102 F17_F = 82, 103 F18_F = 83, 104 F19_F = 84, 105 F20_F = 85, 106 F21_F = 86, 107 F22_F = 87, 108 F23_F = 88, 109 F24_F = 89, 110 F25_F = 90, 111 F26_F = 91, 112 F27_F = 92, 113 F28_F = 93, 114 F29_F = 94, 115 F30_F = 95, 116 F31_F = 96, 117 NUM_TARGET_REGS // 97 118}; 119} // end namespace RISCV 120 121// Register classes 122 123namespace RISCV { 124enum { 125 FPR32RegClassID = 0, 126 GPRRegClassID = 1, 127 GPRNoX0RegClassID = 2, 128 GPRNoX0X2RegClassID = 3, 129 GPRTCRegClassID = 4, 130 FPR32CRegClassID = 5, 131 GPRCRegClassID = 6, 132 GPRC_and_GPRTCRegClassID = 7, 133 GPRX0RegClassID = 8, 134 SPRegClassID = 9, 135 FPR64RegClassID = 10, 136 FPR64CRegClassID = 11, 137 138 }; 139} // end namespace RISCV 140 141 142// Register alternate name indices 143 144namespace RISCV { 145enum { 146 ABIRegAltName, // 0 147 NoRegAltName, // 1 148 NUM_TARGET_REG_ALT_NAMES = 2 149}; 150} // end namespace RISCV 151 152 153// Subregister indices 154 155namespace RISCV { 156enum { 157 NoSubRegister, 158 sub_32, // 1 159 NUM_TARGET_SUBREGS 160}; 161} // end namespace RISCV 162 163} // end namespace llvm 164 165#endif // GET_REGINFO_ENUM 166 167/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 168|* *| 169|* MC Register Information *| 170|* *| 171|* Automatically generated file, do not edit! *| 172|* *| 173\*===----------------------------------------------------------------------===*/ 174 175 176#ifdef GET_REGINFO_MC_DESC 177#undef GET_REGINFO_MC_DESC 178 179namespace llvm { 180 181extern const MCPhysReg RISCVRegDiffLists[] = { 182 /* 0 */ 32, 0, 183 /* 2 */ 65503, 0, 184 /* 4 */ 65504, 0, 185 /* 6 */ 65535, 0, 186}; 187 188extern const LaneBitmask RISCVLaneMaskLists[] = { 189 /* 0 */ LaneBitmask(0x00000000), LaneBitmask::getAll(), 190 /* 2 */ LaneBitmask(0x00000001), LaneBitmask::getAll(), 191}; 192 193extern const uint16_t RISCVSubRegIdxLists[] = { 194 /* 0 */ 1, 0, 195}; 196 197extern const MCRegisterInfo::SubRegCoveredBits RISCVSubRegIdxRanges[] = { 198 { 65535, 65535 }, 199 { 0, 32 }, // sub_32 200}; 201 202extern const char RISCVRegStrings[] = { 203 /* 0 */ 'X', '1', '0', 0, 204 /* 4 */ 'X', '2', '0', 0, 205 /* 8 */ 'X', '3', '0', 0, 206 /* 12 */ 'X', '0', 0, 207 /* 15 */ 'X', '1', '1', 0, 208 /* 19 */ 'X', '2', '1', 0, 209 /* 23 */ 'X', '3', '1', 0, 210 /* 27 */ 'X', '1', 0, 211 /* 30 */ 'X', '1', '2', 0, 212 /* 34 */ 'X', '2', '2', 0, 213 /* 38 */ 'X', '2', 0, 214 /* 41 */ 'X', '1', '3', 0, 215 /* 45 */ 'X', '2', '3', 0, 216 /* 49 */ 'X', '3', 0, 217 /* 52 */ 'X', '1', '4', 0, 218 /* 56 */ 'X', '2', '4', 0, 219 /* 60 */ 'X', '4', 0, 220 /* 63 */ 'X', '1', '5', 0, 221 /* 67 */ 'X', '2', '5', 0, 222 /* 71 */ 'X', '5', 0, 223 /* 74 */ 'X', '1', '6', 0, 224 /* 78 */ 'X', '2', '6', 0, 225 /* 82 */ 'X', '6', 0, 226 /* 85 */ 'X', '1', '7', 0, 227 /* 89 */ 'X', '2', '7', 0, 228 /* 93 */ 'X', '7', 0, 229 /* 96 */ 'X', '1', '8', 0, 230 /* 100 */ 'X', '2', '8', 0, 231 /* 104 */ 'X', '8', 0, 232 /* 107 */ 'X', '1', '9', 0, 233 /* 111 */ 'X', '2', '9', 0, 234 /* 115 */ 'X', '9', 0, 235 /* 118 */ 'F', '1', '0', '_', 'D', 0, 236 /* 124 */ 'F', '2', '0', '_', 'D', 0, 237 /* 130 */ 'F', '3', '0', '_', 'D', 0, 238 /* 136 */ 'F', '0', '_', 'D', 0, 239 /* 141 */ 'F', '1', '1', '_', 'D', 0, 240 /* 147 */ 'F', '2', '1', '_', 'D', 0, 241 /* 153 */ 'F', '3', '1', '_', 'D', 0, 242 /* 159 */ 'F', '1', '_', 'D', 0, 243 /* 164 */ 'F', '1', '2', '_', 'D', 0, 244 /* 170 */ 'F', '2', '2', '_', 'D', 0, 245 /* 176 */ 'F', '2', '_', 'D', 0, 246 /* 181 */ 'F', '1', '3', '_', 'D', 0, 247 /* 187 */ 'F', '2', '3', '_', 'D', 0, 248 /* 193 */ 'F', '3', '_', 'D', 0, 249 /* 198 */ 'F', '1', '4', '_', 'D', 0, 250 /* 204 */ 'F', '2', '4', '_', 'D', 0, 251 /* 210 */ 'F', '4', '_', 'D', 0, 252 /* 215 */ 'F', '1', '5', '_', 'D', 0, 253 /* 221 */ 'F', '2', '5', '_', 'D', 0, 254 /* 227 */ 'F', '5', '_', 'D', 0, 255 /* 232 */ 'F', '1', '6', '_', 'D', 0, 256 /* 238 */ 'F', '2', '6', '_', 'D', 0, 257 /* 244 */ 'F', '6', '_', 'D', 0, 258 /* 249 */ 'F', '1', '7', '_', 'D', 0, 259 /* 255 */ 'F', '2', '7', '_', 'D', 0, 260 /* 261 */ 'F', '7', '_', 'D', 0, 261 /* 266 */ 'F', '1', '8', '_', 'D', 0, 262 /* 272 */ 'F', '2', '8', '_', 'D', 0, 263 /* 278 */ 'F', '8', '_', 'D', 0, 264 /* 283 */ 'F', '1', '9', '_', 'D', 0, 265 /* 289 */ 'F', '2', '9', '_', 'D', 0, 266 /* 295 */ 'F', '9', '_', 'D', 0, 267 /* 300 */ 'F', '1', '0', '_', 'F', 0, 268 /* 306 */ 'F', '2', '0', '_', 'F', 0, 269 /* 312 */ 'F', '3', '0', '_', 'F', 0, 270 /* 318 */ 'F', '0', '_', 'F', 0, 271 /* 323 */ 'F', '1', '1', '_', 'F', 0, 272 /* 329 */ 'F', '2', '1', '_', 'F', 0, 273 /* 335 */ 'F', '3', '1', '_', 'F', 0, 274 /* 341 */ 'F', '1', '_', 'F', 0, 275 /* 346 */ 'F', '1', '2', '_', 'F', 0, 276 /* 352 */ 'F', '2', '2', '_', 'F', 0, 277 /* 358 */ 'F', '2', '_', 'F', 0, 278 /* 363 */ 'F', '1', '3', '_', 'F', 0, 279 /* 369 */ 'F', '2', '3', '_', 'F', 0, 280 /* 375 */ 'F', '3', '_', 'F', 0, 281 /* 380 */ 'F', '1', '4', '_', 'F', 0, 282 /* 386 */ 'F', '2', '4', '_', 'F', 0, 283 /* 392 */ 'F', '4', '_', 'F', 0, 284 /* 397 */ 'F', '1', '5', '_', 'F', 0, 285 /* 403 */ 'F', '2', '5', '_', 'F', 0, 286 /* 409 */ 'F', '5', '_', 'F', 0, 287 /* 414 */ 'F', '1', '6', '_', 'F', 0, 288 /* 420 */ 'F', '2', '6', '_', 'F', 0, 289 /* 426 */ 'F', '6', '_', 'F', 0, 290 /* 431 */ 'F', '1', '7', '_', 'F', 0, 291 /* 437 */ 'F', '2', '7', '_', 'F', 0, 292 /* 443 */ 'F', '7', '_', 'F', 0, 293 /* 448 */ 'F', '1', '8', '_', 'F', 0, 294 /* 454 */ 'F', '2', '8', '_', 'F', 0, 295 /* 460 */ 'F', '8', '_', 'F', 0, 296 /* 465 */ 'F', '1', '9', '_', 'F', 0, 297 /* 471 */ 'F', '2', '9', '_', 'F', 0, 298 /* 477 */ 'F', '9', '_', 'F', 0, 299}; 300 301extern const MCRegisterDesc RISCVRegDesc[] = { // Descriptors 302 { 3, 0, 0, 0, 0, 0 }, 303 { 12, 1, 1, 1, 97, 0 }, 304 { 27, 1, 1, 1, 97, 0 }, 305 { 38, 1, 1, 1, 97, 0 }, 306 { 49, 1, 1, 1, 97, 0 }, 307 { 60, 1, 1, 1, 97, 0 }, 308 { 71, 1, 1, 1, 97, 0 }, 309 { 82, 1, 1, 1, 97, 0 }, 310 { 93, 1, 1, 1, 97, 0 }, 311 { 104, 1, 1, 1, 97, 0 }, 312 { 115, 1, 1, 1, 97, 0 }, 313 { 0, 1, 1, 1, 97, 0 }, 314 { 15, 1, 1, 1, 97, 0 }, 315 { 30, 1, 1, 1, 97, 0 }, 316 { 41, 1, 1, 1, 97, 0 }, 317 { 52, 1, 1, 1, 97, 0 }, 318 { 63, 1, 1, 1, 97, 0 }, 319 { 74, 1, 1, 1, 97, 0 }, 320 { 85, 1, 1, 1, 97, 0 }, 321 { 96, 1, 1, 1, 97, 0 }, 322 { 107, 1, 1, 1, 97, 0 }, 323 { 4, 1, 1, 1, 97, 0 }, 324 { 19, 1, 1, 1, 97, 0 }, 325 { 34, 1, 1, 1, 97, 0 }, 326 { 45, 1, 1, 1, 97, 0 }, 327 { 56, 1, 1, 1, 97, 0 }, 328 { 67, 1, 1, 1, 97, 0 }, 329 { 78, 1, 1, 1, 97, 0 }, 330 { 89, 1, 1, 1, 97, 0 }, 331 { 100, 1, 1, 1, 97, 0 }, 332 { 111, 1, 1, 1, 97, 0 }, 333 { 8, 1, 1, 1, 97, 0 }, 334 { 23, 1, 1, 1, 97, 0 }, 335 { 136, 0, 1, 0, 97, 2 }, 336 { 159, 0, 1, 0, 97, 2 }, 337 { 176, 0, 1, 0, 97, 2 }, 338 { 193, 0, 1, 0, 97, 2 }, 339 { 210, 0, 1, 0, 97, 2 }, 340 { 227, 0, 1, 0, 97, 2 }, 341 { 244, 0, 1, 0, 97, 2 }, 342 { 261, 0, 1, 0, 97, 2 }, 343 { 278, 0, 1, 0, 97, 2 }, 344 { 295, 0, 1, 0, 97, 2 }, 345 { 118, 0, 1, 0, 97, 2 }, 346 { 141, 0, 1, 0, 97, 2 }, 347 { 164, 0, 1, 0, 97, 2 }, 348 { 181, 0, 1, 0, 97, 2 }, 349 { 198, 0, 1, 0, 97, 2 }, 350 { 215, 0, 1, 0, 97, 2 }, 351 { 232, 0, 1, 0, 97, 2 }, 352 { 249, 0, 1, 0, 97, 2 }, 353 { 266, 0, 1, 0, 97, 2 }, 354 { 283, 0, 1, 0, 97, 2 }, 355 { 124, 0, 1, 0, 97, 2 }, 356 { 147, 0, 1, 0, 97, 2 }, 357 { 170, 0, 1, 0, 97, 2 }, 358 { 187, 0, 1, 0, 97, 2 }, 359 { 204, 0, 1, 0, 97, 2 }, 360 { 221, 0, 1, 0, 97, 2 }, 361 { 238, 0, 1, 0, 97, 2 }, 362 { 255, 0, 1, 0, 97, 2 }, 363 { 272, 0, 1, 0, 97, 2 }, 364 { 289, 0, 1, 0, 97, 2 }, 365 { 130, 0, 1, 0, 97, 2 }, 366 { 153, 0, 1, 0, 97, 2 }, 367 { 318, 1, 4, 1, 33, 0 }, 368 { 341, 1, 4, 1, 33, 0 }, 369 { 358, 1, 4, 1, 33, 0 }, 370 { 375, 1, 4, 1, 33, 0 }, 371 { 392, 1, 4, 1, 33, 0 }, 372 { 409, 1, 4, 1, 33, 0 }, 373 { 426, 1, 4, 1, 33, 0 }, 374 { 443, 1, 4, 1, 33, 0 }, 375 { 460, 1, 4, 1, 33, 0 }, 376 { 477, 1, 4, 1, 33, 0 }, 377 { 300, 1, 4, 1, 33, 0 }, 378 { 323, 1, 4, 1, 33, 0 }, 379 { 346, 1, 4, 1, 33, 0 }, 380 { 363, 1, 4, 1, 33, 0 }, 381 { 380, 1, 4, 1, 33, 0 }, 382 { 397, 1, 4, 1, 33, 0 }, 383 { 414, 1, 4, 1, 33, 0 }, 384 { 431, 1, 4, 1, 33, 0 }, 385 { 448, 1, 4, 1, 33, 0 }, 386 { 465, 1, 4, 1, 33, 0 }, 387 { 306, 1, 4, 1, 33, 0 }, 388 { 329, 1, 4, 1, 33, 0 }, 389 { 352, 1, 4, 1, 33, 0 }, 390 { 369, 1, 4, 1, 33, 0 }, 391 { 386, 1, 4, 1, 33, 0 }, 392 { 403, 1, 4, 1, 33, 0 }, 393 { 420, 1, 4, 1, 33, 0 }, 394 { 437, 1, 4, 1, 33, 0 }, 395 { 454, 1, 4, 1, 33, 0 }, 396 { 471, 1, 4, 1, 33, 0 }, 397 { 312, 1, 4, 1, 33, 0 }, 398 { 335, 1, 4, 1, 33, 0 }, 399}; 400 401extern const MCPhysReg RISCVRegUnitRoots[][2] = { 402 { RISCV::X0 }, 403 { RISCV::X1 }, 404 { RISCV::X2 }, 405 { RISCV::X3 }, 406 { RISCV::X4 }, 407 { RISCV::X5 }, 408 { RISCV::X6 }, 409 { RISCV::X7 }, 410 { RISCV::X8 }, 411 { RISCV::X9 }, 412 { RISCV::X10 }, 413 { RISCV::X11 }, 414 { RISCV::X12 }, 415 { RISCV::X13 }, 416 { RISCV::X14 }, 417 { RISCV::X15 }, 418 { RISCV::X16 }, 419 { RISCV::X17 }, 420 { RISCV::X18 }, 421 { RISCV::X19 }, 422 { RISCV::X20 }, 423 { RISCV::X21 }, 424 { RISCV::X22 }, 425 { RISCV::X23 }, 426 { RISCV::X24 }, 427 { RISCV::X25 }, 428 { RISCV::X26 }, 429 { RISCV::X27 }, 430 { RISCV::X28 }, 431 { RISCV::X29 }, 432 { RISCV::X30 }, 433 { RISCV::X31 }, 434 { RISCV::F0_F }, 435 { RISCV::F1_F }, 436 { RISCV::F2_F }, 437 { RISCV::F3_F }, 438 { RISCV::F4_F }, 439 { RISCV::F5_F }, 440 { RISCV::F6_F }, 441 { RISCV::F7_F }, 442 { RISCV::F8_F }, 443 { RISCV::F9_F }, 444 { RISCV::F10_F }, 445 { RISCV::F11_F }, 446 { RISCV::F12_F }, 447 { RISCV::F13_F }, 448 { RISCV::F14_F }, 449 { RISCV::F15_F }, 450 { RISCV::F16_F }, 451 { RISCV::F17_F }, 452 { RISCV::F18_F }, 453 { RISCV::F19_F }, 454 { RISCV::F20_F }, 455 { RISCV::F21_F }, 456 { RISCV::F22_F }, 457 { RISCV::F23_F }, 458 { RISCV::F24_F }, 459 { RISCV::F25_F }, 460 { RISCV::F26_F }, 461 { RISCV::F27_F }, 462 { RISCV::F28_F }, 463 { RISCV::F29_F }, 464 { RISCV::F30_F }, 465 { RISCV::F31_F }, 466}; 467 468namespace { // Register classes... 469 // FPR32 Register Class... 470 const MCPhysReg FPR32[] = { 471 RISCV::F0_F, RISCV::F1_F, RISCV::F2_F, RISCV::F3_F, RISCV::F4_F, RISCV::F5_F, RISCV::F6_F, RISCV::F7_F, RISCV::F10_F, RISCV::F11_F, RISCV::F12_F, RISCV::F13_F, RISCV::F14_F, RISCV::F15_F, RISCV::F16_F, RISCV::F17_F, RISCV::F28_F, RISCV::F29_F, RISCV::F30_F, RISCV::F31_F, RISCV::F8_F, RISCV::F9_F, RISCV::F18_F, RISCV::F19_F, RISCV::F20_F, RISCV::F21_F, RISCV::F22_F, RISCV::F23_F, RISCV::F24_F, RISCV::F25_F, RISCV::F26_F, RISCV::F27_F, 472 }; 473 474 // FPR32 Bit set. 475 const uint8_t FPR32Bits[] = { 476 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, 477 }; 478 479 // GPR Register Class... 480 const MCPhysReg GPR[] = { 481 RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X5, RISCV::X6, RISCV::X7, RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31, RISCV::X8, RISCV::X9, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27, RISCV::X0, RISCV::X1, RISCV::X2, RISCV::X3, RISCV::X4, 482 }; 483 484 // GPR Bit set. 485 const uint8_t GPRBits[] = { 486 0xfe, 0xff, 0xff, 0xff, 0x01, 487 }; 488 489 // GPRNoX0 Register Class... 490 const MCPhysReg GPRNoX0[] = { 491 RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X5, RISCV::X6, RISCV::X7, RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31, RISCV::X8, RISCV::X9, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27, RISCV::X1, RISCV::X2, RISCV::X3, RISCV::X4, 492 }; 493 494 // GPRNoX0 Bit set. 495 const uint8_t GPRNoX0Bits[] = { 496 0xfc, 0xff, 0xff, 0xff, 0x01, 497 }; 498 499 // GPRNoX0X2 Register Class... 500 const MCPhysReg GPRNoX0X2[] = { 501 RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X5, RISCV::X6, RISCV::X7, RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31, RISCV::X8, RISCV::X9, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27, RISCV::X1, RISCV::X3, RISCV::X4, 502 }; 503 504 // GPRNoX0X2 Bit set. 505 const uint8_t GPRNoX0X2Bits[] = { 506 0xf4, 0xff, 0xff, 0xff, 0x01, 507 }; 508 509 // GPRTC Register Class... 510 const MCPhysReg GPRTC[] = { 511 RISCV::X5, RISCV::X6, RISCV::X7, RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31, 512 }; 513 514 // GPRTC Bit set. 515 const uint8_t GPRTCBits[] = { 516 0xc0, 0xf9, 0x07, 0xe0, 0x01, 517 }; 518 519 // FPR32C Register Class... 520 const MCPhysReg FPR32C[] = { 521 RISCV::F10_F, RISCV::F11_F, RISCV::F12_F, RISCV::F13_F, RISCV::F14_F, RISCV::F15_F, RISCV::F8_F, RISCV::F9_F, 522 }; 523 524 // FPR32C Bit set. 525 const uint8_t FPR32CBits[] = { 526 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01, 527 }; 528 529 // GPRC Register Class... 530 const MCPhysReg GPRC[] = { 531 RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X8, RISCV::X9, 532 }; 533 534 // GPRC Bit set. 535 const uint8_t GPRCBits[] = { 536 0x00, 0xfe, 0x01, 537 }; 538 539 // GPRC_and_GPRTC Register Class... 540 const MCPhysReg GPRC_and_GPRTC[] = { 541 RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, 542 }; 543 544 // GPRC_and_GPRTC Bit set. 545 const uint8_t GPRC_and_GPRTCBits[] = { 546 0x00, 0xf8, 0x01, 547 }; 548 549 // GPRX0 Register Class... 550 const MCPhysReg GPRX0[] = { 551 RISCV::X0, 552 }; 553 554 // GPRX0 Bit set. 555 const uint8_t GPRX0Bits[] = { 556 0x02, 557 }; 558 559 // SP Register Class... 560 const MCPhysReg SP[] = { 561 RISCV::X2, 562 }; 563 564 // SP Bit set. 565 const uint8_t SPBits[] = { 566 0x08, 567 }; 568 569 // FPR64 Register Class... 570 const MCPhysReg FPR64[] = { 571 RISCV::F0_D, RISCV::F1_D, RISCV::F2_D, RISCV::F3_D, RISCV::F4_D, RISCV::F5_D, RISCV::F6_D, RISCV::F7_D, RISCV::F10_D, RISCV::F11_D, RISCV::F12_D, RISCV::F13_D, RISCV::F14_D, RISCV::F15_D, RISCV::F16_D, RISCV::F17_D, RISCV::F28_D, RISCV::F29_D, RISCV::F30_D, RISCV::F31_D, RISCV::F8_D, RISCV::F9_D, RISCV::F18_D, RISCV::F19_D, RISCV::F20_D, RISCV::F21_D, RISCV::F22_D, RISCV::F23_D, RISCV::F24_D, RISCV::F25_D, RISCV::F26_D, RISCV::F27_D, 572 }; 573 574 // FPR64 Bit set. 575 const uint8_t FPR64Bits[] = { 576 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, 577 }; 578 579 // FPR64C Register Class... 580 const MCPhysReg FPR64C[] = { 581 RISCV::F10_D, RISCV::F11_D, RISCV::F12_D, RISCV::F13_D, RISCV::F14_D, RISCV::F15_D, RISCV::F8_D, RISCV::F9_D, 582 }; 583 584 // FPR64C Bit set. 585 const uint8_t FPR64CBits[] = { 586 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01, 587 }; 588 589} // end anonymous namespace 590 591extern const char RISCVRegClassStrings[] = { 592 /* 0 */ 'G', 'P', 'R', 'X', '0', 0, 593 /* 6 */ 'G', 'P', 'R', 'N', 'o', 'X', '0', 0, 594 /* 14 */ 'F', 'P', 'R', '3', '2', 0, 595 /* 20 */ 'G', 'P', 'R', 'N', 'o', 'X', '0', 'X', '2', 0, 596 /* 30 */ 'F', 'P', 'R', '6', '4', 0, 597 /* 36 */ 'F', 'P', 'R', '3', '2', 'C', 0, 598 /* 43 */ 'F', 'P', 'R', '6', '4', 'C', 0, 599 /* 50 */ 'G', 'P', 'R', 'C', 0, 600 /* 55 */ 'G', 'P', 'R', 'C', '_', 'a', 'n', 'd', '_', 'G', 'P', 'R', 'T', 'C', 0, 601 /* 70 */ 'S', 'P', 0, 602 /* 73 */ 'G', 'P', 'R', 0, 603}; 604 605extern const MCRegisterClass RISCVMCRegisterClasses[] = { 606 { FPR32, FPR32Bits, 14, 32, sizeof(FPR32Bits), RISCV::FPR32RegClassID, 1, true }, 607 { GPR, GPRBits, 73, 32, sizeof(GPRBits), RISCV::GPRRegClassID, 1, true }, 608 { GPRNoX0, GPRNoX0Bits, 6, 31, sizeof(GPRNoX0Bits), RISCV::GPRNoX0RegClassID, 1, true }, 609 { GPRNoX0X2, GPRNoX0X2Bits, 20, 30, sizeof(GPRNoX0X2Bits), RISCV::GPRNoX0X2RegClassID, 1, true }, 610 { GPRTC, GPRTCBits, 64, 15, sizeof(GPRTCBits), RISCV::GPRTCRegClassID, 1, true }, 611 { FPR32C, FPR32CBits, 36, 8, sizeof(FPR32CBits), RISCV::FPR32CRegClassID, 1, true }, 612 { GPRC, GPRCBits, 50, 8, sizeof(GPRCBits), RISCV::GPRCRegClassID, 1, true }, 613 { GPRC_and_GPRTC, GPRC_and_GPRTCBits, 55, 6, sizeof(GPRC_and_GPRTCBits), RISCV::GPRC_and_GPRTCRegClassID, 1, true }, 614 { GPRX0, GPRX0Bits, 0, 1, sizeof(GPRX0Bits), RISCV::GPRX0RegClassID, 1, true }, 615 { SP, SPBits, 70, 1, sizeof(SPBits), RISCV::SPRegClassID, 1, true }, 616 { FPR64, FPR64Bits, 30, 32, sizeof(FPR64Bits), RISCV::FPR64RegClassID, 1, true }, 617 { FPR64C, FPR64CBits, 43, 8, sizeof(FPR64CBits), RISCV::FPR64CRegClassID, 1, true }, 618}; 619 620// RISCV Dwarf<->LLVM register mappings. 621extern const MCRegisterInfo::DwarfLLVMRegPair RISCVDwarfFlavour0Dwarf2L[] = { 622 { 0U, RISCV::X0 }, 623 { 1U, RISCV::X1 }, 624 { 2U, RISCV::X2 }, 625 { 3U, RISCV::X3 }, 626 { 4U, RISCV::X4 }, 627 { 5U, RISCV::X5 }, 628 { 6U, RISCV::X6 }, 629 { 7U, RISCV::X7 }, 630 { 8U, RISCV::X8 }, 631 { 9U, RISCV::X9 }, 632 { 10U, RISCV::X10 }, 633 { 11U, RISCV::X11 }, 634 { 12U, RISCV::X12 }, 635 { 13U, RISCV::X13 }, 636 { 14U, RISCV::X14 }, 637 { 15U, RISCV::X15 }, 638 { 16U, RISCV::X16 }, 639 { 17U, RISCV::X17 }, 640 { 18U, RISCV::X18 }, 641 { 19U, RISCV::X19 }, 642 { 20U, RISCV::X20 }, 643 { 21U, RISCV::X21 }, 644 { 22U, RISCV::X22 }, 645 { 23U, RISCV::X23 }, 646 { 24U, RISCV::X24 }, 647 { 25U, RISCV::X25 }, 648 { 26U, RISCV::X26 }, 649 { 27U, RISCV::X27 }, 650 { 28U, RISCV::X28 }, 651 { 29U, RISCV::X29 }, 652 { 30U, RISCV::X30 }, 653 { 31U, RISCV::X31 }, 654 { 32U, RISCV::F0_F }, 655 { 33U, RISCV::F1_F }, 656 { 34U, RISCV::F2_F }, 657 { 35U, RISCV::F3_F }, 658 { 36U, RISCV::F4_F }, 659 { 37U, RISCV::F5_F }, 660 { 38U, RISCV::F6_F }, 661 { 39U, RISCV::F7_F }, 662 { 40U, RISCV::F8_F }, 663 { 41U, RISCV::F9_F }, 664 { 42U, RISCV::F10_F }, 665 { 43U, RISCV::F11_F }, 666 { 44U, RISCV::F12_F }, 667 { 45U, RISCV::F13_F }, 668 { 46U, RISCV::F14_F }, 669 { 47U, RISCV::F15_F }, 670 { 48U, RISCV::F16_F }, 671 { 49U, RISCV::F17_F }, 672 { 50U, RISCV::F18_F }, 673 { 51U, RISCV::F19_F }, 674 { 52U, RISCV::F20_F }, 675 { 53U, RISCV::F21_F }, 676 { 54U, RISCV::F22_F }, 677 { 55U, RISCV::F23_F }, 678 { 56U, RISCV::F24_F }, 679 { 57U, RISCV::F25_F }, 680 { 58U, RISCV::F26_F }, 681 { 59U, RISCV::F27_F }, 682 { 60U, RISCV::F28_F }, 683 { 61U, RISCV::F29_F }, 684 { 62U, RISCV::F30_F }, 685 { 63U, RISCV::F31_F }, 686}; 687extern const unsigned RISCVDwarfFlavour0Dwarf2LSize = array_lengthof(RISCVDwarfFlavour0Dwarf2L); 688 689extern const MCRegisterInfo::DwarfLLVMRegPair RISCVEHFlavour0Dwarf2L[] = { 690 { 0U, RISCV::X0 }, 691 { 1U, RISCV::X1 }, 692 { 2U, RISCV::X2 }, 693 { 3U, RISCV::X3 }, 694 { 4U, RISCV::X4 }, 695 { 5U, RISCV::X5 }, 696 { 6U, RISCV::X6 }, 697 { 7U, RISCV::X7 }, 698 { 8U, RISCV::X8 }, 699 { 9U, RISCV::X9 }, 700 { 10U, RISCV::X10 }, 701 { 11U, RISCV::X11 }, 702 { 12U, RISCV::X12 }, 703 { 13U, RISCV::X13 }, 704 { 14U, RISCV::X14 }, 705 { 15U, RISCV::X15 }, 706 { 16U, RISCV::X16 }, 707 { 17U, RISCV::X17 }, 708 { 18U, RISCV::X18 }, 709 { 19U, RISCV::X19 }, 710 { 20U, RISCV::X20 }, 711 { 21U, RISCV::X21 }, 712 { 22U, RISCV::X22 }, 713 { 23U, RISCV::X23 }, 714 { 24U, RISCV::X24 }, 715 { 25U, RISCV::X25 }, 716 { 26U, RISCV::X26 }, 717 { 27U, RISCV::X27 }, 718 { 28U, RISCV::X28 }, 719 { 29U, RISCV::X29 }, 720 { 30U, RISCV::X30 }, 721 { 31U, RISCV::X31 }, 722 { 32U, RISCV::F0_F }, 723 { 33U, RISCV::F1_F }, 724 { 34U, RISCV::F2_F }, 725 { 35U, RISCV::F3_F }, 726 { 36U, RISCV::F4_F }, 727 { 37U, RISCV::F5_F }, 728 { 38U, RISCV::F6_F }, 729 { 39U, RISCV::F7_F }, 730 { 40U, RISCV::F8_F }, 731 { 41U, RISCV::F9_F }, 732 { 42U, RISCV::F10_F }, 733 { 43U, RISCV::F11_F }, 734 { 44U, RISCV::F12_F }, 735 { 45U, RISCV::F13_F }, 736 { 46U, RISCV::F14_F }, 737 { 47U, RISCV::F15_F }, 738 { 48U, RISCV::F16_F }, 739 { 49U, RISCV::F17_F }, 740 { 50U, RISCV::F18_F }, 741 { 51U, RISCV::F19_F }, 742 { 52U, RISCV::F20_F }, 743 { 53U, RISCV::F21_F }, 744 { 54U, RISCV::F22_F }, 745 { 55U, RISCV::F23_F }, 746 { 56U, RISCV::F24_F }, 747 { 57U, RISCV::F25_F }, 748 { 58U, RISCV::F26_F }, 749 { 59U, RISCV::F27_F }, 750 { 60U, RISCV::F28_F }, 751 { 61U, RISCV::F29_F }, 752 { 62U, RISCV::F30_F }, 753 { 63U, RISCV::F31_F }, 754}; 755extern const unsigned RISCVEHFlavour0Dwarf2LSize = array_lengthof(RISCVEHFlavour0Dwarf2L); 756 757extern const MCRegisterInfo::DwarfLLVMRegPair RISCVDwarfFlavour0L2Dwarf[] = { 758 { RISCV::X0, 0U }, 759 { RISCV::X1, 1U }, 760 { RISCV::X2, 2U }, 761 { RISCV::X3, 3U }, 762 { RISCV::X4, 4U }, 763 { RISCV::X5, 5U }, 764 { RISCV::X6, 6U }, 765 { RISCV::X7, 7U }, 766 { RISCV::X8, 8U }, 767 { RISCV::X9, 9U }, 768 { RISCV::X10, 10U }, 769 { RISCV::X11, 11U }, 770 { RISCV::X12, 12U }, 771 { RISCV::X13, 13U }, 772 { RISCV::X14, 14U }, 773 { RISCV::X15, 15U }, 774 { RISCV::X16, 16U }, 775 { RISCV::X17, 17U }, 776 { RISCV::X18, 18U }, 777 { RISCV::X19, 19U }, 778 { RISCV::X20, 20U }, 779 { RISCV::X21, 21U }, 780 { RISCV::X22, 22U }, 781 { RISCV::X23, 23U }, 782 { RISCV::X24, 24U }, 783 { RISCV::X25, 25U }, 784 { RISCV::X26, 26U }, 785 { RISCV::X27, 27U }, 786 { RISCV::X28, 28U }, 787 { RISCV::X29, 29U }, 788 { RISCV::X30, 30U }, 789 { RISCV::X31, 31U }, 790 { RISCV::F0_D, 32U }, 791 { RISCV::F1_D, 33U }, 792 { RISCV::F2_D, 34U }, 793 { RISCV::F3_D, 35U }, 794 { RISCV::F4_D, 36U }, 795 { RISCV::F5_D, 37U }, 796 { RISCV::F6_D, 38U }, 797 { RISCV::F7_D, 39U }, 798 { RISCV::F8_D, 40U }, 799 { RISCV::F9_D, 41U }, 800 { RISCV::F10_D, 42U }, 801 { RISCV::F11_D, 43U }, 802 { RISCV::F12_D, 44U }, 803 { RISCV::F13_D, 45U }, 804 { RISCV::F14_D, 46U }, 805 { RISCV::F15_D, 47U }, 806 { RISCV::F16_D, 48U }, 807 { RISCV::F17_D, 49U }, 808 { RISCV::F18_D, 50U }, 809 { RISCV::F19_D, 51U }, 810 { RISCV::F20_D, 52U }, 811 { RISCV::F21_D, 53U }, 812 { RISCV::F22_D, 54U }, 813 { RISCV::F23_D, 55U }, 814 { RISCV::F24_D, 56U }, 815 { RISCV::F25_D, 57U }, 816 { RISCV::F26_D, 58U }, 817 { RISCV::F27_D, 59U }, 818 { RISCV::F28_D, 60U }, 819 { RISCV::F29_D, 61U }, 820 { RISCV::F30_D, 62U }, 821 { RISCV::F31_D, 63U }, 822 { RISCV::F0_F, 32U }, 823 { RISCV::F1_F, 33U }, 824 { RISCV::F2_F, 34U }, 825 { RISCV::F3_F, 35U }, 826 { RISCV::F4_F, 36U }, 827 { RISCV::F5_F, 37U }, 828 { RISCV::F6_F, 38U }, 829 { RISCV::F7_F, 39U }, 830 { RISCV::F8_F, 40U }, 831 { RISCV::F9_F, 41U }, 832 { RISCV::F10_F, 42U }, 833 { RISCV::F11_F, 43U }, 834 { RISCV::F12_F, 44U }, 835 { RISCV::F13_F, 45U }, 836 { RISCV::F14_F, 46U }, 837 { RISCV::F15_F, 47U }, 838 { RISCV::F16_F, 48U }, 839 { RISCV::F17_F, 49U }, 840 { RISCV::F18_F, 50U }, 841 { RISCV::F19_F, 51U }, 842 { RISCV::F20_F, 52U }, 843 { RISCV::F21_F, 53U }, 844 { RISCV::F22_F, 54U }, 845 { RISCV::F23_F, 55U }, 846 { RISCV::F24_F, 56U }, 847 { RISCV::F25_F, 57U }, 848 { RISCV::F26_F, 58U }, 849 { RISCV::F27_F, 59U }, 850 { RISCV::F28_F, 60U }, 851 { RISCV::F29_F, 61U }, 852 { RISCV::F30_F, 62U }, 853 { RISCV::F31_F, 63U }, 854}; 855extern const unsigned RISCVDwarfFlavour0L2DwarfSize = array_lengthof(RISCVDwarfFlavour0L2Dwarf); 856 857extern const MCRegisterInfo::DwarfLLVMRegPair RISCVEHFlavour0L2Dwarf[] = { 858 { RISCV::X0, 0U }, 859 { RISCV::X1, 1U }, 860 { RISCV::X2, 2U }, 861 { RISCV::X3, 3U }, 862 { RISCV::X4, 4U }, 863 { RISCV::X5, 5U }, 864 { RISCV::X6, 6U }, 865 { RISCV::X7, 7U }, 866 { RISCV::X8, 8U }, 867 { RISCV::X9, 9U }, 868 { RISCV::X10, 10U }, 869 { RISCV::X11, 11U }, 870 { RISCV::X12, 12U }, 871 { RISCV::X13, 13U }, 872 { RISCV::X14, 14U }, 873 { RISCV::X15, 15U }, 874 { RISCV::X16, 16U }, 875 { RISCV::X17, 17U }, 876 { RISCV::X18, 18U }, 877 { RISCV::X19, 19U }, 878 { RISCV::X20, 20U }, 879 { RISCV::X21, 21U }, 880 { RISCV::X22, 22U }, 881 { RISCV::X23, 23U }, 882 { RISCV::X24, 24U }, 883 { RISCV::X25, 25U }, 884 { RISCV::X26, 26U }, 885 { RISCV::X27, 27U }, 886 { RISCV::X28, 28U }, 887 { RISCV::X29, 29U }, 888 { RISCV::X30, 30U }, 889 { RISCV::X31, 31U }, 890 { RISCV::F0_D, 32U }, 891 { RISCV::F1_D, 33U }, 892 { RISCV::F2_D, 34U }, 893 { RISCV::F3_D, 35U }, 894 { RISCV::F4_D, 36U }, 895 { RISCV::F5_D, 37U }, 896 { RISCV::F6_D, 38U }, 897 { RISCV::F7_D, 39U }, 898 { RISCV::F8_D, 40U }, 899 { RISCV::F9_D, 41U }, 900 { RISCV::F10_D, 42U }, 901 { RISCV::F11_D, 43U }, 902 { RISCV::F12_D, 44U }, 903 { RISCV::F13_D, 45U }, 904 { RISCV::F14_D, 46U }, 905 { RISCV::F15_D, 47U }, 906 { RISCV::F16_D, 48U }, 907 { RISCV::F17_D, 49U }, 908 { RISCV::F18_D, 50U }, 909 { RISCV::F19_D, 51U }, 910 { RISCV::F20_D, 52U }, 911 { RISCV::F21_D, 53U }, 912 { RISCV::F22_D, 54U }, 913 { RISCV::F23_D, 55U }, 914 { RISCV::F24_D, 56U }, 915 { RISCV::F25_D, 57U }, 916 { RISCV::F26_D, 58U }, 917 { RISCV::F27_D, 59U }, 918 { RISCV::F28_D, 60U }, 919 { RISCV::F29_D, 61U }, 920 { RISCV::F30_D, 62U }, 921 { RISCV::F31_D, 63U }, 922 { RISCV::F0_F, 32U }, 923 { RISCV::F1_F, 33U }, 924 { RISCV::F2_F, 34U }, 925 { RISCV::F3_F, 35U }, 926 { RISCV::F4_F, 36U }, 927 { RISCV::F5_F, 37U }, 928 { RISCV::F6_F, 38U }, 929 { RISCV::F7_F, 39U }, 930 { RISCV::F8_F, 40U }, 931 { RISCV::F9_F, 41U }, 932 { RISCV::F10_F, 42U }, 933 { RISCV::F11_F, 43U }, 934 { RISCV::F12_F, 44U }, 935 { RISCV::F13_F, 45U }, 936 { RISCV::F14_F, 46U }, 937 { RISCV::F15_F, 47U }, 938 { RISCV::F16_F, 48U }, 939 { RISCV::F17_F, 49U }, 940 { RISCV::F18_F, 50U }, 941 { RISCV::F19_F, 51U }, 942 { RISCV::F20_F, 52U }, 943 { RISCV::F21_F, 53U }, 944 { RISCV::F22_F, 54U }, 945 { RISCV::F23_F, 55U }, 946 { RISCV::F24_F, 56U }, 947 { RISCV::F25_F, 57U }, 948 { RISCV::F26_F, 58U }, 949 { RISCV::F27_F, 59U }, 950 { RISCV::F28_F, 60U }, 951 { RISCV::F29_F, 61U }, 952 { RISCV::F30_F, 62U }, 953 { RISCV::F31_F, 63U }, 954}; 955extern const unsigned RISCVEHFlavour0L2DwarfSize = array_lengthof(RISCVEHFlavour0L2Dwarf); 956 957extern const uint16_t RISCVRegEncodingTable[] = { 958 0, 959 0, 960 1, 961 2, 962 3, 963 4, 964 5, 965 6, 966 7, 967 8, 968 9, 969 10, 970 11, 971 12, 972 13, 973 14, 974 15, 975 16, 976 17, 977 18, 978 19, 979 20, 980 21, 981 22, 982 23, 983 24, 984 25, 985 26, 986 27, 987 28, 988 29, 989 30, 990 31, 991 0, 992 1, 993 2, 994 3, 995 4, 996 5, 997 6, 998 7, 999 8, 1000 9, 1001 10, 1002 11, 1003 12, 1004 13, 1005 14, 1006 15, 1007 16, 1008 17, 1009 18, 1010 19, 1011 20, 1012 21, 1013 22, 1014 23, 1015 24, 1016 25, 1017 26, 1018 27, 1019 28, 1020 29, 1021 30, 1022 31, 1023 0, 1024 1, 1025 2, 1026 3, 1027 4, 1028 5, 1029 6, 1030 7, 1031 8, 1032 9, 1033 10, 1034 11, 1035 12, 1036 13, 1037 14, 1038 15, 1039 16, 1040 17, 1041 18, 1042 19, 1043 20, 1044 21, 1045 22, 1046 23, 1047 24, 1048 25, 1049 26, 1050 27, 1051 28, 1052 29, 1053 30, 1054 31, 1055}; 1056static inline void InitRISCVMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) { 1057 RI->InitMCRegisterInfo(RISCVRegDesc, 97, RA, PC, RISCVMCRegisterClasses, 12, RISCVRegUnitRoots, 64, RISCVRegDiffLists, RISCVLaneMaskLists, RISCVRegStrings, RISCVRegClassStrings, RISCVSubRegIdxLists, 2, 1058RISCVSubRegIdxRanges, RISCVRegEncodingTable); 1059 1060 switch (DwarfFlavour) { 1061 default: 1062 llvm_unreachable("Unknown DWARF flavour"); 1063 case 0: 1064 RI->mapDwarfRegsToLLVMRegs(RISCVDwarfFlavour0Dwarf2L, RISCVDwarfFlavour0Dwarf2LSize, false); 1065 break; 1066 } 1067 switch (EHFlavour) { 1068 default: 1069 llvm_unreachable("Unknown DWARF flavour"); 1070 case 0: 1071 RI->mapDwarfRegsToLLVMRegs(RISCVEHFlavour0Dwarf2L, RISCVEHFlavour0Dwarf2LSize, true); 1072 break; 1073 } 1074 switch (DwarfFlavour) { 1075 default: 1076 llvm_unreachable("Unknown DWARF flavour"); 1077 case 0: 1078 RI->mapLLVMRegsToDwarfRegs(RISCVDwarfFlavour0L2Dwarf, RISCVDwarfFlavour0L2DwarfSize, false); 1079 break; 1080 } 1081 switch (EHFlavour) { 1082 default: 1083 llvm_unreachable("Unknown DWARF flavour"); 1084 case 0: 1085 RI->mapLLVMRegsToDwarfRegs(RISCVEHFlavour0L2Dwarf, RISCVEHFlavour0L2DwarfSize, true); 1086 break; 1087 } 1088} 1089 1090} // end namespace llvm 1091 1092#endif // GET_REGINFO_MC_DESC 1093 1094/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 1095|* *| 1096|* Register Information Header Fragment *| 1097|* *| 1098|* Automatically generated file, do not edit! *| 1099|* *| 1100\*===----------------------------------------------------------------------===*/ 1101 1102 1103#ifdef GET_REGINFO_HEADER 1104#undef GET_REGINFO_HEADER 1105 1106#include "llvm/CodeGen/TargetRegisterInfo.h" 1107 1108namespace llvm { 1109 1110class RISCVFrameLowering; 1111 1112struct RISCVGenRegisterInfo : public TargetRegisterInfo { 1113 explicit RISCVGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0, 1114 unsigned PC = 0, unsigned HwMode = 0); 1115 unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override; 1116 LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override; 1117 LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override; 1118 const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override; 1119 const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override; 1120 unsigned getRegUnitWeight(unsigned RegUnit) const override; 1121 unsigned getNumRegPressureSets() const override; 1122 const char *getRegPressureSetName(unsigned Idx) const override; 1123 unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override; 1124 const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override; 1125 const int *getRegUnitPressureSets(unsigned RegUnit) const override; 1126 ArrayRef<const char *> getRegMaskNames() const override; 1127 ArrayRef<const uint32_t *> getRegMasks() const override; 1128 /// Devirtualized TargetFrameLowering. 1129 static const RISCVFrameLowering *getFrameLowering( 1130 const MachineFunction &MF); 1131}; 1132 1133namespace RISCV { // Register classes 1134 extern const TargetRegisterClass FPR32RegClass; 1135 extern const TargetRegisterClass GPRRegClass; 1136 extern const TargetRegisterClass GPRNoX0RegClass; 1137 extern const TargetRegisterClass GPRNoX0X2RegClass; 1138 extern const TargetRegisterClass GPRTCRegClass; 1139 extern const TargetRegisterClass FPR32CRegClass; 1140 extern const TargetRegisterClass GPRCRegClass; 1141 extern const TargetRegisterClass GPRC_and_GPRTCRegClass; 1142 extern const TargetRegisterClass GPRX0RegClass; 1143 extern const TargetRegisterClass SPRegClass; 1144 extern const TargetRegisterClass FPR64RegClass; 1145 extern const TargetRegisterClass FPR64CRegClass; 1146} // end namespace RISCV 1147 1148} // end namespace llvm 1149 1150#endif // GET_REGINFO_HEADER 1151 1152/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 1153|* *| 1154|* Target Register and Register Classes Information *| 1155|* *| 1156|* Automatically generated file, do not edit! *| 1157|* *| 1158\*===----------------------------------------------------------------------===*/ 1159 1160 1161#ifdef GET_REGINFO_TARGET_DESC 1162#undef GET_REGINFO_TARGET_DESC 1163 1164namespace llvm { 1165 1166extern const MCRegisterClass RISCVMCRegisterClasses[]; 1167 1168static const MVT::SimpleValueType VTLists[] = { 1169 /* 0 */ MVT::i32, MVT::Other, 1170 /* 2 */ MVT::i64, MVT::Other, 1171 /* 4 */ MVT::f32, MVT::Other, 1172 /* 6 */ MVT::f64, MVT::Other, 1173}; 1174 1175static const char *const SubRegIndexNameTable[] = { "sub_32", "" }; 1176 1177 1178static const LaneBitmask SubRegIndexLaneMaskTable[] = { 1179 LaneBitmask::getAll(), 1180 LaneBitmask(0x00000001), // sub_32 1181 }; 1182 1183 1184 1185static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = { 1186 // Mode = 0 (Default) 1187 { 32, 32, 32, VTLists+4 }, // FPR32 1188 { 32, 32, 32, VTLists+0 }, // GPR 1189 { 32, 32, 32, VTLists+0 }, // GPRNoX0 1190 { 32, 32, 32, VTLists+0 }, // GPRNoX0X2 1191 { 32, 32, 32, VTLists+0 }, // GPRTC 1192 { 32, 32, 32, VTLists+4 }, // FPR32C 1193 { 32, 32, 32, VTLists+0 }, // GPRC 1194 { 32, 32, 32, VTLists+0 }, // GPRC_and_GPRTC 1195 { 32, 32, 32, VTLists+0 }, // GPRX0 1196 { 32, 32, 32, VTLists+0 }, // SP 1197 { 64, 64, 64, VTLists+6 }, // FPR64 1198 { 64, 64, 64, VTLists+6 }, // FPR64C 1199 // Mode = 1 (RV32) 1200 { 32, 32, 32, VTLists+4 }, // FPR32 1201 { 32, 32, 32, VTLists+0 }, // GPR 1202 { 32, 32, 32, VTLists+0 }, // GPRNoX0 1203 { 32, 32, 32, VTLists+0 }, // GPRNoX0X2 1204 { 32, 32, 32, VTLists+0 }, // GPRTC 1205 { 32, 32, 32, VTLists+4 }, // FPR32C 1206 { 32, 32, 32, VTLists+0 }, // GPRC 1207 { 32, 32, 32, VTLists+0 }, // GPRC_and_GPRTC 1208 { 32, 32, 32, VTLists+0 }, // GPRX0 1209 { 32, 32, 32, VTLists+0 }, // SP 1210 { 64, 64, 64, VTLists+6 }, // FPR64 1211 { 64, 64, 64, VTLists+6 }, // FPR64C 1212 // Mode = 2 (RV64) 1213 { 32, 32, 32, VTLists+4 }, // FPR32 1214 { 64, 64, 64, VTLists+2 }, // GPR 1215 { 64, 64, 64, VTLists+2 }, // GPRNoX0 1216 { 64, 64, 64, VTLists+2 }, // GPRNoX0X2 1217 { 64, 64, 64, VTLists+2 }, // GPRTC 1218 { 32, 32, 32, VTLists+4 }, // FPR32C 1219 { 64, 64, 64, VTLists+2 }, // GPRC 1220 { 64, 64, 64, VTLists+2 }, // GPRC_and_GPRTC 1221 { 64, 64, 64, VTLists+2 }, // GPRX0 1222 { 64, 64, 64, VTLists+2 }, // SP 1223 { 64, 64, 64, VTLists+6 }, // FPR64 1224 { 64, 64, 64, VTLists+6 }, // FPR64C 1225}; 1226 1227static const TargetRegisterClass *const NullRegClasses[] = { nullptr }; 1228 1229static const uint32_t FPR32SubClassMask[] = { 1230 0x00000021, 1231 0x00000c00, // sub_32 1232}; 1233 1234static const uint32_t GPRSubClassMask[] = { 1235 0x000003de, 1236}; 1237 1238static const uint32_t GPRNoX0SubClassMask[] = { 1239 0x000002dc, 1240}; 1241 1242static const uint32_t GPRNoX0X2SubClassMask[] = { 1243 0x000000d8, 1244}; 1245 1246static const uint32_t GPRTCSubClassMask[] = { 1247 0x00000090, 1248}; 1249 1250static const uint32_t FPR32CSubClassMask[] = { 1251 0x00000020, 1252 0x00000800, // sub_32 1253}; 1254 1255static const uint32_t GPRCSubClassMask[] = { 1256 0x000000c0, 1257}; 1258 1259static const uint32_t GPRC_and_GPRTCSubClassMask[] = { 1260 0x00000080, 1261}; 1262 1263static const uint32_t GPRX0SubClassMask[] = { 1264 0x00000100, 1265}; 1266 1267static const uint32_t SPSubClassMask[] = { 1268 0x00000200, 1269}; 1270 1271static const uint32_t FPR64SubClassMask[] = { 1272 0x00000c00, 1273}; 1274 1275static const uint32_t FPR64CSubClassMask[] = { 1276 0x00000800, 1277}; 1278 1279static const uint16_t SuperRegIdxSeqs[] = { 1280 /* 0 */ 1, 0, 1281}; 1282 1283static const TargetRegisterClass *const GPRNoX0Superclasses[] = { 1284 &RISCV::GPRRegClass, 1285 nullptr 1286}; 1287 1288static const TargetRegisterClass *const GPRNoX0X2Superclasses[] = { 1289 &RISCV::GPRRegClass, 1290 &RISCV::GPRNoX0RegClass, 1291 nullptr 1292}; 1293 1294static const TargetRegisterClass *const GPRTCSuperclasses[] = { 1295 &RISCV::GPRRegClass, 1296 &RISCV::GPRNoX0RegClass, 1297 &RISCV::GPRNoX0X2RegClass, 1298 nullptr 1299}; 1300 1301static const TargetRegisterClass *const FPR32CSuperclasses[] = { 1302 &RISCV::FPR32RegClass, 1303 nullptr 1304}; 1305 1306static const TargetRegisterClass *const GPRCSuperclasses[] = { 1307 &RISCV::GPRRegClass, 1308 &RISCV::GPRNoX0RegClass, 1309 &RISCV::GPRNoX0X2RegClass, 1310 nullptr 1311}; 1312 1313static const TargetRegisterClass *const GPRC_and_GPRTCSuperclasses[] = { 1314 &RISCV::GPRRegClass, 1315 &RISCV::GPRNoX0RegClass, 1316 &RISCV::GPRNoX0X2RegClass, 1317 &RISCV::GPRTCRegClass, 1318 &RISCV::GPRCRegClass, 1319 nullptr 1320}; 1321 1322static const TargetRegisterClass *const GPRX0Superclasses[] = { 1323 &RISCV::GPRRegClass, 1324 nullptr 1325}; 1326 1327static const TargetRegisterClass *const SPSuperclasses[] = { 1328 &RISCV::GPRRegClass, 1329 &RISCV::GPRNoX0RegClass, 1330 nullptr 1331}; 1332 1333static const TargetRegisterClass *const FPR64CSuperclasses[] = { 1334 &RISCV::FPR64RegClass, 1335 nullptr 1336}; 1337 1338 1339namespace RISCV { // Register class instances 1340 extern const TargetRegisterClass FPR32RegClass = { 1341 &RISCVMCRegisterClasses[FPR32RegClassID], 1342 FPR32SubClassMask, 1343 SuperRegIdxSeqs + 0, 1344 LaneBitmask(0x00000001), 1345 0, 1346 false, /* HasDisjunctSubRegs */ 1347 false, /* CoveredBySubRegs */ 1348 NullRegClasses, 1349 nullptr 1350 }; 1351 1352 extern const TargetRegisterClass GPRRegClass = { 1353 &RISCVMCRegisterClasses[GPRRegClassID], 1354 GPRSubClassMask, 1355 SuperRegIdxSeqs + 1, 1356 LaneBitmask(0x00000001), 1357 0, 1358 false, /* HasDisjunctSubRegs */ 1359 false, /* CoveredBySubRegs */ 1360 NullRegClasses, 1361 nullptr 1362 }; 1363 1364 extern const TargetRegisterClass GPRNoX0RegClass = { 1365 &RISCVMCRegisterClasses[GPRNoX0RegClassID], 1366 GPRNoX0SubClassMask, 1367 SuperRegIdxSeqs + 1, 1368 LaneBitmask(0x00000001), 1369 0, 1370 false, /* HasDisjunctSubRegs */ 1371 false, /* CoveredBySubRegs */ 1372 GPRNoX0Superclasses, 1373 nullptr 1374 }; 1375 1376 extern const TargetRegisterClass GPRNoX0X2RegClass = { 1377 &RISCVMCRegisterClasses[GPRNoX0X2RegClassID], 1378 GPRNoX0X2SubClassMask, 1379 SuperRegIdxSeqs + 1, 1380 LaneBitmask(0x00000001), 1381 0, 1382 false, /* HasDisjunctSubRegs */ 1383 false, /* CoveredBySubRegs */ 1384 GPRNoX0X2Superclasses, 1385 nullptr 1386 }; 1387 1388 extern const TargetRegisterClass GPRTCRegClass = { 1389 &RISCVMCRegisterClasses[GPRTCRegClassID], 1390 GPRTCSubClassMask, 1391 SuperRegIdxSeqs + 1, 1392 LaneBitmask(0x00000001), 1393 0, 1394 false, /* HasDisjunctSubRegs */ 1395 false, /* CoveredBySubRegs */ 1396 GPRTCSuperclasses, 1397 nullptr 1398 }; 1399 1400 extern const TargetRegisterClass FPR32CRegClass = { 1401 &RISCVMCRegisterClasses[FPR32CRegClassID], 1402 FPR32CSubClassMask, 1403 SuperRegIdxSeqs + 0, 1404 LaneBitmask(0x00000001), 1405 0, 1406 false, /* HasDisjunctSubRegs */ 1407 false, /* CoveredBySubRegs */ 1408 FPR32CSuperclasses, 1409 nullptr 1410 }; 1411 1412 extern const TargetRegisterClass GPRCRegClass = { 1413 &RISCVMCRegisterClasses[GPRCRegClassID], 1414 GPRCSubClassMask, 1415 SuperRegIdxSeqs + 1, 1416 LaneBitmask(0x00000001), 1417 0, 1418 false, /* HasDisjunctSubRegs */ 1419 false, /* CoveredBySubRegs */ 1420 GPRCSuperclasses, 1421 nullptr 1422 }; 1423 1424 extern const TargetRegisterClass GPRC_and_GPRTCRegClass = { 1425 &RISCVMCRegisterClasses[GPRC_and_GPRTCRegClassID], 1426 GPRC_and_GPRTCSubClassMask, 1427 SuperRegIdxSeqs + 1, 1428 LaneBitmask(0x00000001), 1429 0, 1430 false, /* HasDisjunctSubRegs */ 1431 false, /* CoveredBySubRegs */ 1432 GPRC_and_GPRTCSuperclasses, 1433 nullptr 1434 }; 1435 1436 extern const TargetRegisterClass GPRX0RegClass = { 1437 &RISCVMCRegisterClasses[GPRX0RegClassID], 1438 GPRX0SubClassMask, 1439 SuperRegIdxSeqs + 1, 1440 LaneBitmask(0x00000001), 1441 0, 1442 false, /* HasDisjunctSubRegs */ 1443 false, /* CoveredBySubRegs */ 1444 GPRX0Superclasses, 1445 nullptr 1446 }; 1447 1448 extern const TargetRegisterClass SPRegClass = { 1449 &RISCVMCRegisterClasses[SPRegClassID], 1450 SPSubClassMask, 1451 SuperRegIdxSeqs + 1, 1452 LaneBitmask(0x00000001), 1453 0, 1454 false, /* HasDisjunctSubRegs */ 1455 false, /* CoveredBySubRegs */ 1456 SPSuperclasses, 1457 nullptr 1458 }; 1459 1460 extern const TargetRegisterClass FPR64RegClass = { 1461 &RISCVMCRegisterClasses[FPR64RegClassID], 1462 FPR64SubClassMask, 1463 SuperRegIdxSeqs + 1, 1464 LaneBitmask(0x00000001), 1465 0, 1466 false, /* HasDisjunctSubRegs */ 1467 false, /* CoveredBySubRegs */ 1468 NullRegClasses, 1469 nullptr 1470 }; 1471 1472 extern const TargetRegisterClass FPR64CRegClass = { 1473 &RISCVMCRegisterClasses[FPR64CRegClassID], 1474 FPR64CSubClassMask, 1475 SuperRegIdxSeqs + 1, 1476 LaneBitmask(0x00000001), 1477 0, 1478 false, /* HasDisjunctSubRegs */ 1479 false, /* CoveredBySubRegs */ 1480 FPR64CSuperclasses, 1481 nullptr 1482 }; 1483 1484} // end namespace RISCV 1485 1486namespace { 1487 const TargetRegisterClass* const RegisterClasses[] = { 1488 &RISCV::FPR32RegClass, 1489 &RISCV::GPRRegClass, 1490 &RISCV::GPRNoX0RegClass, 1491 &RISCV::GPRNoX0X2RegClass, 1492 &RISCV::GPRTCRegClass, 1493 &RISCV::FPR32CRegClass, 1494 &RISCV::GPRCRegClass, 1495 &RISCV::GPRC_and_GPRTCRegClass, 1496 &RISCV::GPRX0RegClass, 1497 &RISCV::SPRegClass, 1498 &RISCV::FPR64RegClass, 1499 &RISCV::FPR64CRegClass, 1500 }; 1501} // end anonymous namespace 1502 1503static const TargetRegisterInfoDesc RISCVRegInfoDesc[] = { // Extra Descriptors 1504 { 0, false }, 1505 { 0, true }, 1506 { 1, true }, 1507 { 1, true }, 1508 { 1, true }, 1509 { 1, true }, 1510 { 1, true }, 1511 { 1, true }, 1512 { 1, true }, 1513 { 0, true }, 1514 { 0, true }, 1515 { 0, true }, 1516 { 0, true }, 1517 { 0, true }, 1518 { 0, true }, 1519 { 0, true }, 1520 { 0, true }, 1521 { 1, true }, 1522 { 1, true }, 1523 { 1, true }, 1524 { 1, true }, 1525 { 1, true }, 1526 { 1, true }, 1527 { 1, true }, 1528 { 1, true }, 1529 { 1, true }, 1530 { 1, true }, 1531 { 1, true }, 1532 { 1, true }, 1533 { 1, true }, 1534 { 1, true }, 1535 { 1, true }, 1536 { 1, true }, 1537 { 0, true }, 1538 { 0, true }, 1539 { 0, true }, 1540 { 0, true }, 1541 { 0, true }, 1542 { 0, true }, 1543 { 0, true }, 1544 { 0, true }, 1545 { 0, true }, 1546 { 0, true }, 1547 { 0, true }, 1548 { 0, true }, 1549 { 0, true }, 1550 { 0, true }, 1551 { 0, true }, 1552 { 0, true }, 1553 { 0, true }, 1554 { 0, true }, 1555 { 0, true }, 1556 { 0, true }, 1557 { 0, true }, 1558 { 0, true }, 1559 { 0, true }, 1560 { 0, true }, 1561 { 0, true }, 1562 { 0, true }, 1563 { 0, true }, 1564 { 0, true }, 1565 { 0, true }, 1566 { 0, true }, 1567 { 0, true }, 1568 { 0, true }, 1569 { 0, true }, 1570 { 0, true }, 1571 { 0, true }, 1572 { 0, true }, 1573 { 0, true }, 1574 { 0, true }, 1575 { 0, true }, 1576 { 0, true }, 1577 { 0, true }, 1578 { 0, true }, 1579 { 0, true }, 1580 { 0, true }, 1581 { 0, true }, 1582 { 0, true }, 1583 { 0, true }, 1584 { 0, true }, 1585 { 0, true }, 1586 { 0, true }, 1587 { 0, true }, 1588 { 0, true }, 1589 { 0, true }, 1590 { 0, true }, 1591 { 0, true }, 1592 { 0, true }, 1593 { 0, true }, 1594 { 0, true }, 1595 { 0, true }, 1596 { 0, true }, 1597 { 0, true }, 1598 { 0, true }, 1599 { 0, true }, 1600 { 0, true }, 1601}; 1602unsigned RISCVGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const { 1603 static const uint8_t Rows[1][1] = { 1604 { 0, }, 1605 }; 1606 1607 --IdxA; assert(IdxA < 1); 1608 --IdxB; assert(IdxB < 1); 1609 return Rows[0][IdxB]; 1610} 1611 1612 struct MaskRolOp { 1613 LaneBitmask Mask; 1614 uint8_t RotateLeft; 1615 }; 1616 static const MaskRolOp LaneMaskComposeSequences[] = { 1617 { LaneBitmask(0xFFFFFFFF), 0 }, { LaneBitmask::getNone(), 0 } // Sequence 0 1618 }; 1619 static const MaskRolOp *const CompositeSequences[] = { 1620 &LaneMaskComposeSequences[0] // to sub_32 1621 }; 1622 1623LaneBitmask RISCVGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const { 1624 --IdxA; assert(IdxA < 1 && "Subregister index out of bounds"); 1625 LaneBitmask Result; 1626 for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) { 1627 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger(); 1628 if (unsigned S = Ops->RotateLeft) 1629 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S))); 1630 else 1631 Result |= LaneBitmask(M); 1632 } 1633 return Result; 1634} 1635 1636LaneBitmask RISCVGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const { 1637 LaneMask &= getSubRegIndexLaneMask(IdxA); 1638 --IdxA; assert(IdxA < 1 && "Subregister index out of bounds"); 1639 LaneBitmask Result; 1640 for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) { 1641 LaneBitmask::Type M = LaneMask.getAsInteger(); 1642 if (unsigned S = Ops->RotateLeft) 1643 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S))); 1644 else 1645 Result |= LaneBitmask(M); 1646 } 1647 return Result; 1648} 1649 1650const TargetRegisterClass *RISCVGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const { 1651 static const uint8_t Table[12][1] = { 1652 { // FPR32 1653 0, // sub_32 1654 }, 1655 { // GPR 1656 0, // sub_32 1657 }, 1658 { // GPRNoX0 1659 0, // sub_32 1660 }, 1661 { // GPRNoX0X2 1662 0, // sub_32 1663 }, 1664 { // GPRTC 1665 0, // sub_32 1666 }, 1667 { // FPR32C 1668 0, // sub_32 1669 }, 1670 { // GPRC 1671 0, // sub_32 1672 }, 1673 { // GPRC_and_GPRTC 1674 0, // sub_32 1675 }, 1676 { // GPRX0 1677 0, // sub_32 1678 }, 1679 { // SP 1680 0, // sub_32 1681 }, 1682 { // FPR64 1683 11, // sub_32 -> FPR64 1684 }, 1685 { // FPR64C 1686 12, // sub_32 -> FPR64C 1687 }, 1688 }; 1689 assert(RC && "Missing regclass"); 1690 if (!Idx) return RC; 1691 --Idx; 1692 assert(Idx < 1 && "Bad subreg"); 1693 unsigned TV = Table[RC->getID()][Idx]; 1694 return TV ? getRegClass(TV - 1) : nullptr; 1695} 1696 1697/// Get the weight in units of pressure for this register class. 1698const RegClassWeight &RISCVGenRegisterInfo:: 1699getRegClassWeight(const TargetRegisterClass *RC) const { 1700 static const RegClassWeight RCWeightTable[] = { 1701 {1, 32}, // FPR32 1702 {1, 32}, // GPR 1703 {1, 31}, // GPRNoX0 1704 {1, 30}, // GPRNoX0X2 1705 {1, 15}, // GPRTC 1706 {1, 8}, // FPR32C 1707 {1, 8}, // GPRC 1708 {1, 6}, // GPRC_and_GPRTC 1709 {1, 1}, // GPRX0 1710 {1, 1}, // SP 1711 {1, 32}, // FPR64 1712 {1, 8}, // FPR64C 1713 }; 1714 return RCWeightTable[RC->getID()]; 1715} 1716 1717/// Get the weight in units of pressure for this register unit. 1718unsigned RISCVGenRegisterInfo:: 1719getRegUnitWeight(unsigned RegUnit) const { 1720 assert(RegUnit < 64 && "invalid register unit"); 1721 // All register units have unit weight. 1722 return 1; 1723} 1724 1725 1726// Get the number of dimensions of register pressure. 1727unsigned RISCVGenRegisterInfo::getNumRegPressureSets() const { 1728 return 7; 1729} 1730 1731// Get the name of this register unit pressure set. 1732const char *RISCVGenRegisterInfo:: 1733getRegPressureSetName(unsigned Idx) const { 1734 static const char *const PressureNameTable[] = { 1735 "GPRX0", 1736 "SP", 1737 "FPR32C", 1738 "GPRC", 1739 "GPRTC", 1740 "FPR32", 1741 "GPR", 1742 }; 1743 return PressureNameTable[Idx]; 1744} 1745 1746// Get the register unit pressure limit for this dimension. 1747// This limit must be adjusted dynamically for reserved registers. 1748unsigned RISCVGenRegisterInfo:: 1749getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const { 1750 static const uint8_t PressureLimitTable[] = { 1751 1, // 0: GPRX0 1752 1, // 1: SP 1753 8, // 2: FPR32C 1754 8, // 3: GPRC 1755 17, // 4: GPRTC 1756 32, // 5: FPR32 1757 32, // 6: GPR 1758 }; 1759 return PressureLimitTable[Idx]; 1760} 1761 1762/// Table of pressure sets per register class or unit. 1763static const int RCSetsTable[] = { 1764 /* 0 */ 2, 5, -1, 1765 /* 3 */ 0, 6, -1, 1766 /* 6 */ 1, 6, -1, 1767 /* 9 */ 3, 4, 6, -1, 1768}; 1769 1770/// Get the dimensions of register pressure impacted by this register class. 1771/// Returns a -1 terminated array of pressure set IDs 1772const int* RISCVGenRegisterInfo:: 1773getRegClassPressureSets(const TargetRegisterClass *RC) const { 1774 static const uint8_t RCSetStartTable[] = { 1775 1,4,4,4,10,0,9,9,3,6,1,0,}; 1776 return &RCSetsTable[RCSetStartTable[RC->getID()]]; 1777} 1778 1779/// Get the dimensions of register pressure impacted by this register unit. 1780/// Returns a -1 terminated array of pressure set IDs 1781const int* RISCVGenRegisterInfo:: 1782getRegUnitPressureSets(unsigned RegUnit) const { 1783 assert(RegUnit < 64 && "invalid register unit"); 1784 static const uint8_t RUSetStartTable[] = { 1785 3,4,6,4,4,10,10,10,9,9,9,9,9,9,9,9,10,10,4,4,4,4,4,4,4,4,4,4,10,10,10,10,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,}; 1786 return &RCSetsTable[RUSetStartTable[RegUnit]]; 1787} 1788 1789extern const MCRegisterDesc RISCVRegDesc[]; 1790extern const MCPhysReg RISCVRegDiffLists[]; 1791extern const LaneBitmask RISCVLaneMaskLists[]; 1792extern const char RISCVRegStrings[]; 1793extern const char RISCVRegClassStrings[]; 1794extern const MCPhysReg RISCVRegUnitRoots[][2]; 1795extern const uint16_t RISCVSubRegIdxLists[]; 1796extern const MCRegisterInfo::SubRegCoveredBits RISCVSubRegIdxRanges[]; 1797extern const uint16_t RISCVRegEncodingTable[]; 1798// RISCV Dwarf<->LLVM register mappings. 1799extern const MCRegisterInfo::DwarfLLVMRegPair RISCVDwarfFlavour0Dwarf2L[]; 1800extern const unsigned RISCVDwarfFlavour0Dwarf2LSize; 1801 1802extern const MCRegisterInfo::DwarfLLVMRegPair RISCVEHFlavour0Dwarf2L[]; 1803extern const unsigned RISCVEHFlavour0Dwarf2LSize; 1804 1805extern const MCRegisterInfo::DwarfLLVMRegPair RISCVDwarfFlavour0L2Dwarf[]; 1806extern const unsigned RISCVDwarfFlavour0L2DwarfSize; 1807 1808extern const MCRegisterInfo::DwarfLLVMRegPair RISCVEHFlavour0L2Dwarf[]; 1809extern const unsigned RISCVEHFlavour0L2DwarfSize; 1810 1811RISCVGenRegisterInfo:: 1812RISCVGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour, 1813 unsigned PC, unsigned HwMode) 1814 : TargetRegisterInfo(RISCVRegInfoDesc, RegisterClasses, RegisterClasses+12, 1815 SubRegIndexNameTable, SubRegIndexLaneMaskTable, 1816 LaneBitmask(0xFFFFFFFE), RegClassInfos, HwMode) { 1817 InitMCRegisterInfo(RISCVRegDesc, 97, RA, PC, 1818 RISCVMCRegisterClasses, 12, 1819 RISCVRegUnitRoots, 1820 64, 1821 RISCVRegDiffLists, 1822 RISCVLaneMaskLists, 1823 RISCVRegStrings, 1824 RISCVRegClassStrings, 1825 RISCVSubRegIdxLists, 1826 2, 1827 RISCVSubRegIdxRanges, 1828 RISCVRegEncodingTable); 1829 1830 switch (DwarfFlavour) { 1831 default: 1832 llvm_unreachable("Unknown DWARF flavour"); 1833 case 0: 1834 mapDwarfRegsToLLVMRegs(RISCVDwarfFlavour0Dwarf2L, RISCVDwarfFlavour0Dwarf2LSize, false); 1835 break; 1836 } 1837 switch (EHFlavour) { 1838 default: 1839 llvm_unreachable("Unknown DWARF flavour"); 1840 case 0: 1841 mapDwarfRegsToLLVMRegs(RISCVEHFlavour0Dwarf2L, RISCVEHFlavour0Dwarf2LSize, true); 1842 break; 1843 } 1844 switch (DwarfFlavour) { 1845 default: 1846 llvm_unreachable("Unknown DWARF flavour"); 1847 case 0: 1848 mapLLVMRegsToDwarfRegs(RISCVDwarfFlavour0L2Dwarf, RISCVDwarfFlavour0L2DwarfSize, false); 1849 break; 1850 } 1851 switch (EHFlavour) { 1852 default: 1853 llvm_unreachable("Unknown DWARF flavour"); 1854 case 0: 1855 mapLLVMRegsToDwarfRegs(RISCVEHFlavour0L2Dwarf, RISCVEHFlavour0L2DwarfSize, true); 1856 break; 1857 } 1858} 1859 1860static const MCPhysReg CSR_ILP32D_LP64D_SaveList[] = { RISCV::X1, RISCV::X3, RISCV::X4, RISCV::X8, RISCV::X9, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27, RISCV::F8_D, RISCV::F9_D, RISCV::F18_D, RISCV::F19_D, RISCV::F20_D, RISCV::F21_D, RISCV::F22_D, RISCV::F23_D, RISCV::F24_D, RISCV::F25_D, RISCV::F26_D, RISCV::F27_D, 0 }; 1861static const uint32_t CSR_ILP32D_LP64D_RegMask[] = { 0x1ff80634, 0x1ff80600, 0x1ff80600, 0x00000000, }; 1862static const MCPhysReg CSR_ILP32F_LP64F_SaveList[] = { RISCV::X1, RISCV::X3, RISCV::X4, RISCV::X8, RISCV::X9, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27, RISCV::F8_F, RISCV::F9_F, RISCV::F18_F, RISCV::F19_F, RISCV::F20_F, RISCV::F21_F, RISCV::F22_F, RISCV::F23_F, RISCV::F24_F, RISCV::F25_F, RISCV::F26_F, RISCV::F27_F, 0 }; 1863static const uint32_t CSR_ILP32F_LP64F_RegMask[] = { 0x1ff80634, 0x00000000, 0x1ff80600, 0x00000000, }; 1864static const MCPhysReg CSR_ILP32_LP64_SaveList[] = { RISCV::X1, RISCV::X3, RISCV::X4, RISCV::X8, RISCV::X9, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27, 0 }; 1865static const uint32_t CSR_ILP32_LP64_RegMask[] = { 0x1ff80634, 0x00000000, 0x00000000, 0x00000000, }; 1866static const MCPhysReg CSR_Interrupt_SaveList[] = { RISCV::X1, RISCV::X3, RISCV::X4, RISCV::X5, RISCV::X6, RISCV::X7, RISCV::X8, RISCV::X9, RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27, RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31, 0 }; 1867static const uint32_t CSR_Interrupt_RegMask[] = { 0xfffffff4, 0x00000001, 0x00000000, 0x00000000, }; 1868static const MCPhysReg CSR_NoRegs_SaveList[] = { 0 }; 1869static const uint32_t CSR_NoRegs_RegMask[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, }; 1870static const MCPhysReg CSR_XLEN_F32_Interrupt_SaveList[] = { RISCV::X1, RISCV::X3, RISCV::X4, RISCV::X5, RISCV::X6, RISCV::X7, RISCV::X8, RISCV::X9, RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27, RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31, RISCV::F0_F, RISCV::F1_F, RISCV::F2_F, RISCV::F3_F, RISCV::F4_F, RISCV::F5_F, RISCV::F6_F, RISCV::F7_F, RISCV::F10_F, RISCV::F11_F, RISCV::F12_F, RISCV::F13_F, RISCV::F14_F, RISCV::F15_F, RISCV::F16_F, RISCV::F17_F, RISCV::F28_F, RISCV::F29_F, RISCV::F30_F, RISCV::F31_F, RISCV::F8_F, RISCV::F9_F, RISCV::F18_F, RISCV::F19_F, RISCV::F20_F, RISCV::F21_F, RISCV::F22_F, RISCV::F23_F, RISCV::F24_F, RISCV::F25_F, RISCV::F26_F, RISCV::F27_F, 0 }; 1871static const uint32_t CSR_XLEN_F32_Interrupt_RegMask[] = { 0xfffffff4, 0x00000001, 0xfffffffe, 0x00000001, }; 1872static const MCPhysReg CSR_XLEN_F64_Interrupt_SaveList[] = { RISCV::X1, RISCV::X3, RISCV::X4, RISCV::X5, RISCV::X6, RISCV::X7, RISCV::X8, RISCV::X9, RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27, RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31, RISCV::F0_D, RISCV::F1_D, RISCV::F2_D, RISCV::F3_D, RISCV::F4_D, RISCV::F5_D, RISCV::F6_D, RISCV::F7_D, RISCV::F10_D, RISCV::F11_D, RISCV::F12_D, RISCV::F13_D, RISCV::F14_D, RISCV::F15_D, RISCV::F16_D, RISCV::F17_D, RISCV::F28_D, RISCV::F29_D, RISCV::F30_D, RISCV::F31_D, RISCV::F8_D, RISCV::F9_D, RISCV::F18_D, RISCV::F19_D, RISCV::F20_D, RISCV::F21_D, RISCV::F22_D, RISCV::F23_D, RISCV::F24_D, RISCV::F25_D, RISCV::F26_D, RISCV::F27_D, 0 }; 1873static const uint32_t CSR_XLEN_F64_Interrupt_RegMask[] = { 0xfffffff4, 0xffffffff, 0xffffffff, 0x00000001, }; 1874 1875 1876ArrayRef<const uint32_t *> RISCVGenRegisterInfo::getRegMasks() const { 1877 static const uint32_t *const Masks[] = { 1878 CSR_ILP32D_LP64D_RegMask, 1879 CSR_ILP32F_LP64F_RegMask, 1880 CSR_ILP32_LP64_RegMask, 1881 CSR_Interrupt_RegMask, 1882 CSR_NoRegs_RegMask, 1883 CSR_XLEN_F32_Interrupt_RegMask, 1884 CSR_XLEN_F64_Interrupt_RegMask, 1885 }; 1886 return makeArrayRef(Masks); 1887} 1888 1889ArrayRef<const char *> RISCVGenRegisterInfo::getRegMaskNames() const { 1890 static const char *const Names[] = { 1891 "CSR_ILP32D_LP64D", 1892 "CSR_ILP32F_LP64F", 1893 "CSR_ILP32_LP64", 1894 "CSR_Interrupt", 1895 "CSR_NoRegs", 1896 "CSR_XLEN_F32_Interrupt", 1897 "CSR_XLEN_F64_Interrupt", 1898 }; 1899 return makeArrayRef(Names); 1900} 1901 1902const RISCVFrameLowering * 1903RISCVGenRegisterInfo::getFrameLowering(const MachineFunction &MF) { 1904 return static_cast<const RISCVFrameLowering *>( 1905 MF.getSubtarget().getFrameLowering()); 1906} 1907 1908} // end namespace llvm 1909 1910#endif // GET_REGINFO_TARGET_DESC 1911 1912