1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2|* *| 3|* Register Bank Source Fragments *| 4|* *| 5|* Automatically generated file, do not edit! *| 6|* *| 7\*===----------------------------------------------------------------------===*/ 8 9#ifdef GET_REGBANK_DECLARATIONS 10#undef GET_REGBANK_DECLARATIONS 11namespace llvm { 12namespace AArch64 { 13enum : unsigned { 14 InvalidRegBankID = ~0u, 15 CCRegBankID = 0, 16 FPRRegBankID = 1, 17 GPRRegBankID = 2, 18 NumRegisterBanks, 19}; 20} // end namespace AArch64 21} // end namespace llvm 22#endif // GET_REGBANK_DECLARATIONS 23 24#ifdef GET_TARGET_REGBANK_CLASS 25#undef GET_TARGET_REGBANK_CLASS 26private: 27 static RegisterBank *RegBanks[]; 28 29protected: 30 AArch64GenRegisterBankInfo(); 31 32#endif // GET_TARGET_REGBANK_CLASS 33 34#ifdef GET_TARGET_REGBANK_IMPL 35#undef GET_TARGET_REGBANK_IMPL 36namespace llvm { 37namespace AArch64 { 38const uint32_t CCRegBankCoverageData[] = { 39 // 0-31 40 (1u << (AArch64::CCRRegClassID - 0)) | 41 0, 42 // 32-63 43 0, 44 // 64-95 45 0, 46 // 96-127 47 0, 48 // 128-159 49 0, 50 // 160-191 51 0, 52 // 192-223 53 0, 54 // 224-255 55 0, 56 // 256-287 57 0, 58}; 59const uint32_t FPRRegBankCoverageData[] = { 60 // 0-31 61 (1u << (AArch64::FPR8RegClassID - 0)) | 62 (1u << (AArch64::FPR16RegClassID - 0)) | 63 (1u << (AArch64::FPR32RegClassID - 0)) | 64 (1u << (AArch64::FPR16_loRegClassID - 0)) | 65 (1u << (AArch64::FPR32_with_hsub_in_FPR16_loRegClassID - 0)) | 66 0, 67 // 32-63 68 (1u << (AArch64::FPR64RegClassID - 32)) | 69 (1u << (AArch64::DDRegClassID - 32)) | 70 (1u << (AArch64::FPR64_loRegClassID - 32)) | 71 (1u << (AArch64::DD_with_dsub0_in_FPR64_loRegClassID - 32)) | 72 (1u << (AArch64::DD_with_dsub1_in_FPR64_loRegClassID - 32)) | 73 (1u << (AArch64::DD_with_dsub0_in_FPR64_lo_and_DD_with_dsub1_in_FPR64_loRegClassID - 32)) | 74 0, 75 // 64-95 76 (1u << (AArch64::FPR128RegClassID - 64)) | 77 (1u << (AArch64::DDDRegClassID - 64)) | 78 (1u << (AArch64::DDDDRegClassID - 64)) | 79 (1u << (AArch64::QQRegClassID - 64)) | 80 (1u << (AArch64::FPR128_loRegClassID - 64)) | 81 (1u << (AArch64::DDD_with_dsub0_in_FPR64_loRegClassID - 64)) | 82 (1u << (AArch64::DDDD_with_dsub0_in_FPR64_loRegClassID - 64)) | 83 (1u << (AArch64::QQ_with_dsub_in_FPR64_loRegClassID - 64)) | 84 (1u << (AArch64::DDD_with_dsub1_in_FPR64_loRegClassID - 64)) | 85 (1u << (AArch64::DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub1_in_FPR64_loRegClassID - 64)) | 86 (1u << (AArch64::DDDD_with_dsub1_in_FPR64_loRegClassID - 64)) | 87 (1u << (AArch64::DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_loRegClassID - 64)) | 88 (1u << (AArch64::DDD_with_dsub2_in_FPR64_loRegClassID - 64)) | 89 (1u << (AArch64::DDD_with_dsub1_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_loRegClassID - 64)) | 90 (1u << (AArch64::DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_loRegClassID - 64)) | 91 (1u << (AArch64::DDDD_with_dsub2_in_FPR64_loRegClassID - 64)) | 92 (1u << (AArch64::DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_loRegClassID - 64)) | 93 (1u << (AArch64::DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_loRegClassID - 64)) | 94 (1u << (AArch64::DDDD_with_dsub3_in_FPR64_loRegClassID - 64)) | 95 (1u << (AArch64::DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loRegClassID - 64)) | 96 (1u << (AArch64::DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loRegClassID - 64)) | 97 (1u << (AArch64::DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loRegClassID - 64)) | 98 0, 99 // 96-127 100 (1u << (AArch64::QQQRegClassID - 96)) | 101 (1u << (AArch64::QQQ_with_dsub_in_FPR64_loRegClassID - 96)) | 102 (1u << (AArch64::QQ_with_qsub1_in_FPR128_loRegClassID - 96)) | 103 (1u << (AArch64::QQ_with_dsub_in_FPR64_lo_and_QQ_with_qsub1_in_FPR128_loRegClassID - 96)) | 104 (1u << (AArch64::QQQ_with_qsub1_in_FPR128_loRegClassID - 96)) | 105 (1u << (AArch64::QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub1_in_FPR128_loRegClassID - 96)) | 106 (1u << (AArch64::QQQ_with_qsub2_in_FPR128_loRegClassID - 96)) | 107 (1u << (AArch64::QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID - 96)) | 108 (1u << (AArch64::QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID - 96)) | 109 0, 110 // 128-159 111 (1u << (AArch64::QQQQRegClassID - 128)) | 112 (1u << (AArch64::QQQQ_with_dsub_in_FPR64_loRegClassID - 128)) | 113 (1u << (AArch64::QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClassID - 128)) | 114 (1u << (AArch64::QQQQ_with_qsub1_in_FPR128_loRegClassID - 128)) | 115 (1u << (AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID - 128)) | 116 (1u << (AArch64::QQQQ_with_qsub2_in_FPR128_loRegClassID - 128)) | 117 (1u << (AArch64::QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID - 128)) | 118 (1u << (AArch64::QQQQ_with_qsub3_in_FPR128_loRegClassID - 128)) | 119 0, 120 // 160-191 121 (1u << (AArch64::QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID - 160)) | 122 (1u << (AArch64::QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID - 160)) | 123 (1u << (AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID - 160)) | 124 0, 125 // 192-223 126 0, 127 // 224-255 128 0, 129 // 256-287 130 0, 131}; 132const uint32_t GPRRegBankCoverageData[] = { 133 // 0-31 134 (1u << (AArch64::GPR32allRegClassID - 0)) | 135 (1u << (AArch64::GPR32RegClassID - 0)) | 136 (1u << (AArch64::GPR32spRegClassID - 0)) | 137 (1u << (AArch64::GPR32commonRegClassID - 0)) | 138 (1u << (AArch64::WSeqPairsClassRegClassID - 0)) | 139 (1u << (AArch64::WSeqPairsClass_with_subo32_in_GPR32commonRegClassID - 0)) | 140 (1u << (AArch64::GPR32argRegClassID - 0)) | 141 (1u << (AArch64::WSeqPairsClass_with_sube32_in_GPR32argRegClassID - 0)) | 142 (1u << (AArch64::MatrixIndexGPR32_12_15RegClassID - 0)) | 143 (1u << (AArch64::MatrixIndexGPR32_8_11RegClassID - 0)) | 144 0, 145 // 32-63 146 (1u << (AArch64::XSeqPairsClassRegClassID - 32)) | 147 (1u << (AArch64::GPR64allRegClassID - 32)) | 148 (1u << (AArch64::GPR64RegClassID - 32)) | 149 (1u << (AArch64::GPR64spRegClassID - 32)) | 150 (1u << (AArch64::GPR64commonRegClassID - 32)) | 151 (1u << (AArch64::XSeqPairsClass_with_subo64_in_GPR64commonRegClassID - 32)) | 152 (1u << (AArch64::XSeqPairsClass_with_sube64_in_GPR64noipRegClassID - 32)) | 153 (1u << (AArch64::GPR64noipRegClassID - 32)) | 154 (1u << (AArch64::GPR64common_and_GPR64noipRegClassID - 32)) | 155 (1u << (AArch64::XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64RegClassID - 32)) | 156 (1u << (AArch64::tcGPR64RegClassID - 32)) | 157 (1u << (AArch64::GPR64noip_and_tcGPR64RegClassID - 32)) | 158 (1u << (AArch64::XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64RegClassID - 32)) | 159 (1u << (AArch64::GPR64argRegClassID - 32)) | 160 (1u << (AArch64::WSeqPairsClass_with_sube32_in_MatrixIndexGPR32_12_15RegClassID - 32)) | 161 (1u << (AArch64::GPR64_with_sub_32_in_MatrixIndexGPR32_12_15RegClassID - 32)) | 162 (1u << (AArch64::WSeqPairsClass_with_sube32_in_MatrixIndexGPR32_8_11RegClassID - 32)) | 163 (1u << (AArch64::GPR64_with_sub_32_in_MatrixIndexGPR32_8_11RegClassID - 32)) | 164 (1u << (AArch64::FIXED_REGSRegClassID - 32)) | 165 (1u << (AArch64::FIXED_REGS_with_sub_32RegClassID - 32)) | 166 (1u << (AArch64::FIXED_REGS_and_GPR64RegClassID - 32)) | 167 (1u << (AArch64::XSeqPairsClass_with_sube64_in_tcGPR64RegClassID - 32)) | 168 (1u << (AArch64::XSeqPairsClass_with_subo64_in_tcGPR64RegClassID - 32)) | 169 (1u << (AArch64::rtcGPR64RegClassID - 32)) | 170 (1u << (AArch64::XSeqPairsClass_with_subo64_in_GPR64noipRegClassID - 32)) | 171 0, 172 // 64-95 173 (1u << (AArch64::XSeqPairsClass_with_sub_32_in_GPR32argRegClassID - 64)) | 174 (1u << (AArch64::XSeqPairsClass_with_sub_32_in_MatrixIndexGPR32_12_15RegClassID - 64)) | 175 (1u << (AArch64::XSeqPairsClass_with_sub_32_in_MatrixIndexGPR32_8_11RegClassID - 64)) | 176 (1u << (AArch64::XSeqPairsClass_with_subo64_in_FIXED_REGSRegClassID - 64)) | 177 (1u << (AArch64::XSeqPairsClass_with_sube64_in_rtcGPR64RegClassID - 64)) | 178 0, 179 // 96-127 180 0, 181 // 128-159 182 0, 183 // 160-191 184 0, 185 // 192-223 186 0, 187 // 224-255 188 0, 189 // 256-287 190 0, 191}; 192 193RegisterBank CCRegBank(/* ID */ AArch64::CCRegBankID, /* Name */ "CC", /* Size */ 32, /* CoveredRegClasses */ CCRegBankCoverageData, /* NumRegClasses */ 273); 194RegisterBank FPRRegBank(/* ID */ AArch64::FPRRegBankID, /* Name */ "FPR", /* Size */ 512, /* CoveredRegClasses */ FPRRegBankCoverageData, /* NumRegClasses */ 273); 195RegisterBank GPRRegBank(/* ID */ AArch64::GPRRegBankID, /* Name */ "GPR", /* Size */ 128, /* CoveredRegClasses */ GPRRegBankCoverageData, /* NumRegClasses */ 273); 196} // end namespace AArch64 197 198RegisterBank *AArch64GenRegisterBankInfo::RegBanks[] = { 199 &AArch64::CCRegBank, 200 &AArch64::FPRRegBank, 201 &AArch64::GPRRegBank, 202}; 203 204AArch64GenRegisterBankInfo::AArch64GenRegisterBankInfo() 205 : RegisterBankInfo(RegBanks, AArch64::NumRegisterBanks) { 206 // Assert that RegBank indices match their ID's 207#ifndef NDEBUG 208 for (auto RB : enumerate(RegBanks)) 209 assert(RB.index() == RB.value()->getID() && "Index != ID"); 210#endif // NDEBUG 211} 212} // end namespace llvm 213#endif // GET_TARGET_REGBANK_IMPL 214