1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2|* *| 3|* Assembly Matcher Source Fragment *| 4|* *| 5|* Automatically generated file, do not edit! *| 6|* *| 7\*===----------------------------------------------------------------------===*/ 8 9 10#ifdef GET_ASSEMBLER_HEADER 11#undef GET_ASSEMBLER_HEADER 12 // This should be included into the middle of the declaration of 13 // your subclasses implementation of MCTargetAsmParser. 14 FeatureBitset ComputeAvailableFeatures(const FeatureBitset &FB) const; 15 void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode, 16 const OperandVector &Operands); 17 void convertToMapAndConstraints(unsigned Kind, 18 const OperandVector &Operands) override; 19 unsigned MatchInstructionImpl(const OperandVector &Operands, 20 MCInst &Inst, 21 SmallVectorImpl<NearMissInfo> *NearMisses, 22 bool matchingInlineAsm, 23 unsigned VariantID = 0); 24 OperandMatchResultTy MatchOperandParserImpl( 25 OperandVector &Operands, 26 StringRef Mnemonic, 27 bool ParseForAllFeatures = false); 28 OperandMatchResultTy tryCustomParseOperand( 29 OperandVector &Operands, 30 unsigned MCK); 31 32#endif // GET_ASSEMBLER_HEADER_INFO 33 34 35#ifdef GET_OPERAND_DIAGNOSTIC_TYPES 36#undef GET_OPERAND_DIAGNOSTIC_TYPES 37 38 Match_AlignedMemory16, 39 Match_AlignedMemory32, 40 Match_AlignedMemory64, 41 Match_AlignedMemory64or128, 42 Match_AlignedMemory64or128or256, 43 Match_AlignedMemoryNone, 44 Match_ComplexRotationEven, 45 Match_ComplexRotationOdd, 46 Match_CondCodeRestrictedFP, 47 Match_CondCodeRestrictedI, 48 Match_CondCodeRestrictedS, 49 Match_CondCodeRestrictedU, 50 Match_DPR, 51 Match_DPR_8, 52 Match_DPR_RegList, 53 Match_DPR_VFP2, 54 Match_DupAlignedMemory16, 55 Match_DupAlignedMemory32, 56 Match_DupAlignedMemory64, 57 Match_DupAlignedMemory64or128, 58 Match_DupAlignedMemoryNone, 59 Match_GPR, 60 Match_GPRnoip, 61 Match_GPRnopc, 62 Match_GPRnosp, 63 Match_GPRsp, 64 Match_GPRwithAPSR, 65 Match_GPRwithAPSR_NZCVnosp, 66 Match_GPRwithZR, 67 Match_GPRwithZRnosp, 68 Match_Imm0_1, 69 Match_Imm0_15, 70 Match_Imm0_239, 71 Match_Imm0_255, 72 Match_Imm0_3, 73 Match_Imm0_31, 74 Match_Imm0_32, 75 Match_Imm0_4095, 76 Match_Imm0_63, 77 Match_Imm0_65535, 78 Match_Imm0_65535Expr, 79 Match_Imm0_7, 80 Match_Imm11b, 81 Match_Imm12b, 82 Match_Imm13b, 83 Match_Imm16, 84 Match_Imm1_15, 85 Match_Imm1_31, 86 Match_Imm1_7, 87 Match_Imm24bit, 88 Match_Imm256_65535Expr, 89 Match_Imm32, 90 Match_Imm3b, 91 Match_Imm4b, 92 Match_Imm6b, 93 Match_Imm7b, 94 Match_Imm8, 95 Match_Imm8_255, 96 Match_Imm9b, 97 Match_ImmRange1_16, 98 Match_ImmRange1_32, 99 Match_ImmThumbSR, 100 Match_LELabel, 101 Match_MVELongShift, 102 Match_MVEShiftImm1_15, 103 Match_MVEShiftImm1_7, 104 Match_MVEVcvtImm16, 105 Match_MVEVcvtImm32, 106 Match_MveSaturate, 107 Match_PKHLSLImm, 108 Match_QPR, 109 Match_QPR_8, 110 Match_QPR_VFP2, 111 Match_SPR, 112 Match_SPRRegList, 113 Match_SPR_8, 114 Match_SetEndImm, 115 Match_ShrImm16, 116 Match_ShrImm32, 117 Match_ShrImm64, 118 Match_ShrImm8, 119 Match_VIDUP_imm, 120 Match_VecListFourMQ, 121 Match_VecListTwoMQ, 122 Match_WLSLabel, 123 Match_hGPR, 124 Match_rGPR, 125 Match_tGPR, 126 Match_tGPREven, 127 Match_tGPROdd, 128 END_OPERAND_DIAGNOSTIC_TYPES 129#endif // GET_OPERAND_DIAGNOSTIC_TYPES 130 131 132#ifdef GET_REGISTER_MATCHER 133#undef GET_REGISTER_MATCHER 134 135// Bits for subtarget features that participate in instruction matching. 136enum SubtargetFeatureBits : uint8_t { 137 Feature_HasV4TBit = 35, 138 Feature_HasV5TBit = 36, 139 Feature_HasV5TEBit = 37, 140 Feature_HasV6Bit = 38, 141 Feature_HasV6MBit = 40, 142 Feature_HasV8MBaselineBit = 45, 143 Feature_HasV8MMainlineBit = 46, 144 Feature_HasV8_1MMainlineBit = 47, 145 Feature_HasMVEIntBit = 26, 146 Feature_HasMVEFloatBit = 25, 147 Feature_HasCDEBit = 4, 148 Feature_HasFPRegsBit = 18, 149 Feature_HasFPRegs16Bit = 19, 150 Feature_HasNoFPRegs16Bit = 29, 151 Feature_HasFPRegs64Bit = 20, 152 Feature_HasFPRegsV8_1MBit = 21, 153 Feature_HasV6T2Bit = 41, 154 Feature_HasV6KBit = 39, 155 Feature_HasV7Bit = 42, 156 Feature_HasV8Bit = 44, 157 Feature_PreV8Bit = 64, 158 Feature_HasV8_1aBit = 48, 159 Feature_HasV8_2aBit = 49, 160 Feature_HasV8_3aBit = 50, 161 Feature_HasV8_4aBit = 51, 162 Feature_HasV8_5aBit = 52, 163 Feature_HasV8_6aBit = 53, 164 Feature_HasV8_7aBit = 54, 165 Feature_HasVFP2Bit = 55, 166 Feature_HasVFP3Bit = 56, 167 Feature_HasVFP4Bit = 57, 168 Feature_HasDPVFPBit = 10, 169 Feature_HasFPARMv8Bit = 17, 170 Feature_HasNEONBit = 28, 171 Feature_HasSHA2Bit = 33, 172 Feature_HasAESBit = 1, 173 Feature_HasCryptoBit = 7, 174 Feature_HasDotProdBit = 14, 175 Feature_HasCRCBit = 6, 176 Feature_HasRASBit = 31, 177 Feature_HasLOBBit = 23, 178 Feature_HasPACBTIBit = 30, 179 Feature_HasFP16Bit = 15, 180 Feature_HasFullFP16Bit = 22, 181 Feature_HasFP16FMLBit = 16, 182 Feature_HasBF16Bit = 3, 183 Feature_HasMatMulInt8Bit = 27, 184 Feature_HasDivideInThumbBit = 13, 185 Feature_HasDivideInARMBit = 12, 186 Feature_HasDSPBit = 11, 187 Feature_HasDBBit = 8, 188 Feature_HasDFBBit = 9, 189 Feature_HasV7ClrexBit = 43, 190 Feature_HasAcquireReleaseBit = 2, 191 Feature_HasMPBit = 24, 192 Feature_HasVirtualizationBit = 58, 193 Feature_HasTrustZoneBit = 34, 194 Feature_Has8MSecExtBit = 0, 195 Feature_IsThumbBit = 62, 196 Feature_IsThumb2Bit = 63, 197 Feature_IsMClassBit = 60, 198 Feature_IsNotMClassBit = 61, 199 Feature_IsARMBit = 59, 200 Feature_UseNaClTrapBit = 65, 201 Feature_UseNegativeImmediatesBit = 66, 202 Feature_HasSBBit = 32, 203 Feature_HasCLRBHBBit = 5, 204}; 205 206static unsigned MatchRegisterName(StringRef Name) { 207 switch (Name.size()) { 208 default: break; 209 case 2: // 45 strings to match. 210 switch (Name[0]) { 211 default: break; 212 case 'd': // 10 strings to match. 213 switch (Name[1]) { 214 default: break; 215 case '0': // 1 string to match. 216 return 20; // "d0" 217 case '1': // 1 string to match. 218 return 21; // "d1" 219 case '2': // 1 string to match. 220 return 22; // "d2" 221 case '3': // 1 string to match. 222 return 23; // "d3" 223 case '4': // 1 string to match. 224 return 24; // "d4" 225 case '5': // 1 string to match. 226 return 25; // "d5" 227 case '6': // 1 string to match. 228 return 26; // "d6" 229 case '7': // 1 string to match. 230 return 27; // "d7" 231 case '8': // 1 string to match. 232 return 28; // "d8" 233 case '9': // 1 string to match. 234 return 29; // "d9" 235 } 236 break; 237 case 'l': // 1 string to match. 238 if (Name[1] != 'r') 239 break; 240 return 13; // "lr" 241 case 'p': // 2 strings to match. 242 switch (Name[1]) { 243 default: break; 244 case '0': // 1 string to match. 245 return 56; // "p0" 246 case 'c': // 1 string to match. 247 return 14; // "pc" 248 } 249 break; 250 case 'q': // 10 strings to match. 251 switch (Name[1]) { 252 default: break; 253 case '0': // 1 string to match. 254 return 57; // "q0" 255 case '1': // 1 string to match. 256 return 58; // "q1" 257 case '2': // 1 string to match. 258 return 59; // "q2" 259 case '3': // 1 string to match. 260 return 60; // "q3" 261 case '4': // 1 string to match. 262 return 61; // "q4" 263 case '5': // 1 string to match. 264 return 62; // "q5" 265 case '6': // 1 string to match. 266 return 63; // "q6" 267 case '7': // 1 string to match. 268 return 64; // "q7" 269 case '8': // 1 string to match. 270 return 65; // "q8" 271 case '9': // 1 string to match. 272 return 66; // "q9" 273 } 274 break; 275 case 'r': // 10 strings to match. 276 switch (Name[1]) { 277 default: break; 278 case '0': // 1 string to match. 279 return 73; // "r0" 280 case '1': // 1 string to match. 281 return 74; // "r1" 282 case '2': // 1 string to match. 283 return 75; // "r2" 284 case '3': // 1 string to match. 285 return 76; // "r3" 286 case '4': // 1 string to match. 287 return 77; // "r4" 288 case '5': // 1 string to match. 289 return 78; // "r5" 290 case '6': // 1 string to match. 291 return 79; // "r6" 292 case '7': // 1 string to match. 293 return 80; // "r7" 294 case '8': // 1 string to match. 295 return 81; // "r8" 296 case '9': // 1 string to match. 297 return 82; // "r9" 298 } 299 break; 300 case 's': // 11 strings to match. 301 switch (Name[1]) { 302 default: break; 303 case '0': // 1 string to match. 304 return 86; // "s0" 305 case '1': // 1 string to match. 306 return 87; // "s1" 307 case '2': // 1 string to match. 308 return 88; // "s2" 309 case '3': // 1 string to match. 310 return 89; // "s3" 311 case '4': // 1 string to match. 312 return 90; // "s4" 313 case '5': // 1 string to match. 314 return 91; // "s5" 315 case '6': // 1 string to match. 316 return 92; // "s6" 317 case '7': // 1 string to match. 318 return 93; // "s7" 319 case '8': // 1 string to match. 320 return 94; // "s8" 321 case '9': // 1 string to match. 322 return 95; // "s9" 323 case 'p': // 1 string to match. 324 return 16; // "sp" 325 } 326 break; 327 case 'z': // 1 string to match. 328 if (Name[1] != 'r') 329 break; 330 return 19; // "zr" 331 } 332 break; 333 case 3: // 54 strings to match. 334 switch (Name[0]) { 335 default: break; 336 case 'd': // 22 strings to match. 337 switch (Name[1]) { 338 default: break; 339 case '1': // 10 strings to match. 340 switch (Name[2]) { 341 default: break; 342 case '0': // 1 string to match. 343 return 30; // "d10" 344 case '1': // 1 string to match. 345 return 31; // "d11" 346 case '2': // 1 string to match. 347 return 32; // "d12" 348 case '3': // 1 string to match. 349 return 33; // "d13" 350 case '4': // 1 string to match. 351 return 34; // "d14" 352 case '5': // 1 string to match. 353 return 35; // "d15" 354 case '6': // 1 string to match. 355 return 36; // "d16" 356 case '7': // 1 string to match. 357 return 37; // "d17" 358 case '8': // 1 string to match. 359 return 38; // "d18" 360 case '9': // 1 string to match. 361 return 39; // "d19" 362 } 363 break; 364 case '2': // 10 strings to match. 365 switch (Name[2]) { 366 default: break; 367 case '0': // 1 string to match. 368 return 40; // "d20" 369 case '1': // 1 string to match. 370 return 41; // "d21" 371 case '2': // 1 string to match. 372 return 42; // "d22" 373 case '3': // 1 string to match. 374 return 43; // "d23" 375 case '4': // 1 string to match. 376 return 44; // "d24" 377 case '5': // 1 string to match. 378 return 45; // "d25" 379 case '6': // 1 string to match. 380 return 46; // "d26" 381 case '7': // 1 string to match. 382 return 47; // "d27" 383 case '8': // 1 string to match. 384 return 48; // "d28" 385 case '9': // 1 string to match. 386 return 49; // "d29" 387 } 388 break; 389 case '3': // 2 strings to match. 390 switch (Name[2]) { 391 default: break; 392 case '0': // 1 string to match. 393 return 50; // "d30" 394 case '1': // 1 string to match. 395 return 51; // "d31" 396 } 397 break; 398 } 399 break; 400 case 'q': // 6 strings to match. 401 if (Name[1] != '1') 402 break; 403 switch (Name[2]) { 404 default: break; 405 case '0': // 1 string to match. 406 return 67; // "q10" 407 case '1': // 1 string to match. 408 return 68; // "q11" 409 case '2': // 1 string to match. 410 return 69; // "q12" 411 case '3': // 1 string to match. 412 return 70; // "q13" 413 case '4': // 1 string to match. 414 return 71; // "q14" 415 case '5': // 1 string to match. 416 return 72; // "q15" 417 } 418 break; 419 case 'r': // 3 strings to match. 420 if (Name[1] != '1') 421 break; 422 switch (Name[2]) { 423 default: break; 424 case '0': // 1 string to match. 425 return 83; // "r10" 426 case '1': // 1 string to match. 427 return 84; // "r11" 428 case '2': // 1 string to match. 429 return 85; // "r12" 430 } 431 break; 432 case 's': // 22 strings to match. 433 switch (Name[1]) { 434 default: break; 435 case '1': // 10 strings to match. 436 switch (Name[2]) { 437 default: break; 438 case '0': // 1 string to match. 439 return 96; // "s10" 440 case '1': // 1 string to match. 441 return 97; // "s11" 442 case '2': // 1 string to match. 443 return 98; // "s12" 444 case '3': // 1 string to match. 445 return 99; // "s13" 446 case '4': // 1 string to match. 447 return 100; // "s14" 448 case '5': // 1 string to match. 449 return 101; // "s15" 450 case '6': // 1 string to match. 451 return 102; // "s16" 452 case '7': // 1 string to match. 453 return 103; // "s17" 454 case '8': // 1 string to match. 455 return 104; // "s18" 456 case '9': // 1 string to match. 457 return 105; // "s19" 458 } 459 break; 460 case '2': // 10 strings to match. 461 switch (Name[2]) { 462 default: break; 463 case '0': // 1 string to match. 464 return 106; // "s20" 465 case '1': // 1 string to match. 466 return 107; // "s21" 467 case '2': // 1 string to match. 468 return 108; // "s22" 469 case '3': // 1 string to match. 470 return 109; // "s23" 471 case '4': // 1 string to match. 472 return 110; // "s24" 473 case '5': // 1 string to match. 474 return 111; // "s25" 475 case '6': // 1 string to match. 476 return 112; // "s26" 477 case '7': // 1 string to match. 478 return 113; // "s27" 479 case '8': // 1 string to match. 480 return 114; // "s28" 481 case '9': // 1 string to match. 482 return 115; // "s29" 483 } 484 break; 485 case '3': // 2 strings to match. 486 switch (Name[2]) { 487 default: break; 488 case '0': // 1 string to match. 489 return 116; // "s30" 490 case '1': // 1 string to match. 491 return 117; // "s31" 492 } 493 break; 494 } 495 break; 496 case 'v': // 1 string to match. 497 if (memcmp(Name.data()+1, "pr", 2) != 0) 498 break; 499 return 18; // "vpr" 500 } 501 break; 502 case 4: // 3 strings to match. 503 switch (Name[0]) { 504 default: break; 505 case 'a': // 1 string to match. 506 if (memcmp(Name.data()+1, "psr", 3) != 0) 507 break; 508 return 1; // "apsr" 509 case 'c': // 1 string to match. 510 if (memcmp(Name.data()+1, "psr", 3) != 0) 511 break; 512 return 3; // "cpsr" 513 case 's': // 1 string to match. 514 if (memcmp(Name.data()+1, "psr", 3) != 0) 515 break; 516 return 17; // "spsr" 517 } 518 break; 519 case 5: // 6 strings to match. 520 switch (Name[0]) { 521 default: break; 522 case 'f': // 3 strings to match. 523 if (Name[1] != 'p') 524 break; 525 switch (Name[2]) { 526 default: break; 527 case 'e': // 1 string to match. 528 if (memcmp(Name.data()+3, "xc", 2) != 0) 529 break; 530 return 6; // "fpexc" 531 case 's': // 2 strings to match. 532 switch (Name[3]) { 533 default: break; 534 case 'c': // 1 string to match. 535 if (Name[4] != 'r') 536 break; 537 return 8; // "fpscr" 538 case 'i': // 1 string to match. 539 if (Name[4] != 'd') 540 break; 541 return 11; // "fpsid" 542 } 543 break; 544 } 545 break; 546 case 'm': // 3 strings to match. 547 if (memcmp(Name.data()+1, "vfr", 3) != 0) 548 break; 549 switch (Name[4]) { 550 default: break; 551 case '0': // 1 string to match. 552 return 53; // "mvfr0" 553 case '1': // 1 string to match. 554 return 54; // "mvfr1" 555 case '2': // 1 string to match. 556 return 55; // "mvfr2" 557 } 558 break; 559 } 560 break; 561 case 6: // 2 strings to match. 562 if (memcmp(Name.data()+0, "fp", 2) != 0) 563 break; 564 switch (Name[2]) { 565 default: break; 566 case 'c': // 1 string to match. 567 if (memcmp(Name.data()+3, "xts", 3) != 0) 568 break; 569 return 5; // "fpcxts" 570 case 'i': // 1 string to match. 571 if (memcmp(Name.data()+3, "nst", 3) != 0) 572 break; 573 return 7; // "fpinst" 574 } 575 break; 576 case 7: // 3 strings to match. 577 switch (Name[0]) { 578 default: break; 579 case 'f': // 2 strings to match. 580 if (Name[1] != 'p') 581 break; 582 switch (Name[2]) { 583 default: break; 584 case 'c': // 1 string to match. 585 if (memcmp(Name.data()+3, "xtns", 4) != 0) 586 break; 587 return 4; // "fpcxtns" 588 case 'i': // 1 string to match. 589 if (memcmp(Name.data()+3, "nst2", 4) != 0) 590 break; 591 return 52; // "fpinst2" 592 } 593 break; 594 case 'i': // 1 string to match. 595 if (memcmp(Name.data()+1, "tstate", 6) != 0) 596 break; 597 return 12; // "itstate" 598 } 599 break; 600 case 9: // 1 string to match. 601 if (memcmp(Name.data()+0, "apsr_nzcv", 9) != 0) 602 break; 603 return 2; // "apsr_nzcv" 604 case 10: // 1 string to match. 605 if (memcmp(Name.data()+0, "fpscr_nzcv", 10) != 0) 606 break; 607 return 9; // "fpscr_nzcv" 608 case 12: // 2 strings to match. 609 switch (Name[0]) { 610 default: break; 611 case 'f': // 1 string to match. 612 if (memcmp(Name.data()+1, "pscr_nzcvqc", 11) != 0) 613 break; 614 return 10; // "fpscr_nzcvqc" 615 case 'r': // 1 string to match. 616 if (memcmp(Name.data()+1, "a_auth_code", 11) != 0) 617 break; 618 return 15; // "ra_auth_code" 619 } 620 break; 621 } 622 return 0; 623} 624 625#endif // GET_REGISTER_MATCHER 626 627 628#ifdef GET_SUBTARGET_FEATURE_NAME 629#undef GET_SUBTARGET_FEATURE_NAME 630 631// User-level names for subtarget features that participate in 632// instruction matching. 633static const char *getSubtargetFeatureName(uint64_t Val) { 634 switch(Val) { 635 case Feature_HasV4TBit: return "armv4t"; 636 case Feature_HasV5TBit: return "armv5t"; 637 case Feature_HasV5TEBit: return "armv5te"; 638 case Feature_HasV6Bit: return "armv6"; 639 case Feature_HasV6MBit: return "armv6m or armv6t2"; 640 case Feature_HasV8MBaselineBit: return "armv8m.base"; 641 case Feature_HasV8MMainlineBit: return "armv8m.main"; 642 case Feature_HasV8_1MMainlineBit: return "armv8.1m.main"; 643 case Feature_HasMVEIntBit: return "mve"; 644 case Feature_HasMVEFloatBit: return "mve.fp"; 645 case Feature_HasCDEBit: return "cde"; 646 case Feature_HasFPRegsBit: return "fp registers"; 647 case Feature_HasFPRegs16Bit: return "16-bit fp registers"; 648 case Feature_HasNoFPRegs16Bit: return "16-bit fp registers"; 649 case Feature_HasFPRegs64Bit: return "64-bit fp registers"; 650 case Feature_HasFPRegsV8_1MBit: return "armv8.1m.main with FP or MVE"; 651 case Feature_HasV6T2Bit: return "armv6t2"; 652 case Feature_HasV6KBit: return "armv6k"; 653 case Feature_HasV7Bit: return "armv7"; 654 case Feature_HasV8Bit: return "armv8"; 655 case Feature_PreV8Bit: return "armv7 or earlier"; 656 case Feature_HasV8_1aBit: return "armv8.1a"; 657 case Feature_HasV8_2aBit: return "armv8.2a"; 658 case Feature_HasV8_3aBit: return "armv8.3a"; 659 case Feature_HasV8_4aBit: return "armv8.4a"; 660 case Feature_HasV8_5aBit: return "armv8.5a"; 661 case Feature_HasV8_6aBit: return "armv8.6a"; 662 case Feature_HasV8_7aBit: return "armv8.7a"; 663 case Feature_HasVFP2Bit: return "VFP2"; 664 case Feature_HasVFP3Bit: return "VFP3"; 665 case Feature_HasVFP4Bit: return "VFP4"; 666 case Feature_HasDPVFPBit: return "double precision VFP"; 667 case Feature_HasFPARMv8Bit: return "FPARMv8"; 668 case Feature_HasNEONBit: return "NEON"; 669 case Feature_HasSHA2Bit: return "sha2"; 670 case Feature_HasAESBit: return "aes"; 671 case Feature_HasCryptoBit: return "crypto"; 672 case Feature_HasDotProdBit: return "dotprod"; 673 case Feature_HasCRCBit: return "crc"; 674 case Feature_HasRASBit: return "ras"; 675 case Feature_HasLOBBit: return "lob"; 676 case Feature_HasPACBTIBit: return "pacbti"; 677 case Feature_HasFP16Bit: return "half-float conversions"; 678 case Feature_HasFullFP16Bit: return "full half-float"; 679 case Feature_HasFP16FMLBit: return "full half-float fml"; 680 case Feature_HasBF16Bit: return "BFloat16 floating point extension"; 681 case Feature_HasMatMulInt8Bit: return "8-bit integer matrix multiply"; 682 case Feature_HasDivideInThumbBit: return "divide in THUMB"; 683 case Feature_HasDivideInARMBit: return "divide in ARM"; 684 case Feature_HasDSPBit: return "dsp"; 685 case Feature_HasDBBit: return "data-barriers"; 686 case Feature_HasDFBBit: return "full-data-barrier"; 687 case Feature_HasV7ClrexBit: return "v7 clrex"; 688 case Feature_HasAcquireReleaseBit: return "acquire/release"; 689 case Feature_HasMPBit: return "mp-extensions"; 690 case Feature_HasVirtualizationBit: return "virtualization-extensions"; 691 case Feature_HasTrustZoneBit: return "TrustZone"; 692 case Feature_Has8MSecExtBit: return "ARMv8-M Security Extensions"; 693 case Feature_IsThumbBit: return "thumb"; 694 case Feature_IsThumb2Bit: return "thumb2"; 695 case Feature_IsMClassBit: return "armv*m"; 696 case Feature_IsNotMClassBit: return "!armv*m"; 697 case Feature_IsARMBit: return "arm-mode"; 698 case Feature_UseNaClTrapBit: return "NaCl"; 699 case Feature_UseNegativeImmediatesBit: return "NegativeImmediates"; 700 case Feature_HasSBBit: return "sb"; 701 case Feature_HasCLRBHBBit: return "clrbhb"; 702 default: return "(unknown)"; 703 } 704} 705 706#endif // GET_SUBTARGET_FEATURE_NAME 707 708 709#ifdef GET_MATCHER_IMPLEMENTATION 710#undef GET_MATCHER_IMPLEMENTATION 711 712static void applyMnemonicAliases(StringRef &Mnemonic, const FeatureBitset &Features, unsigned VariantID) { 713 switch (VariantID) { 714 case 0: 715 break; 716 } 717 switch (Mnemonic.size()) { 718 default: break; 719 case 3: // 4 strings to match. 720 switch (Mnemonic[0]) { 721 default: break; 722 case 'r': // 1 string to match. 723 if (memcmp(Mnemonic.data()+1, "fe", 2) != 0) 724 break; 725 Mnemonic = "rfeia"; // "rfe" 726 return; 727 case 's': // 3 strings to match. 728 switch (Mnemonic[1]) { 729 default: break; 730 case 'm': // 1 string to match. 731 if (Mnemonic[2] != 'i') 732 break; 733 Mnemonic = "smc"; // "smi" 734 return; 735 case 'r': // 1 string to match. 736 if (Mnemonic[2] != 's') 737 break; 738 Mnemonic = "srsia"; // "srs" 739 return; 740 case 'w': // 1 string to match. 741 if (Mnemonic[2] != 'i') 742 break; 743 Mnemonic = "svc"; // "swi" 744 return; 745 } 746 break; 747 } 748 break; 749 case 4: // 10 strings to match. 750 switch (Mnemonic[0]) { 751 default: break; 752 case 'f': // 8 strings to match. 753 switch (Mnemonic[1]) { 754 default: break; 755 case 'l': // 2 strings to match. 756 if (Mnemonic[2] != 'd') 757 break; 758 switch (Mnemonic[3]) { 759 default: break; 760 case 'd': // 1 string to match. 761 if (Features.test(Feature_HasVFP2Bit)) // "fldd" 762 Mnemonic = "vldr"; 763 return; 764 case 's': // 1 string to match. 765 if (Features.test(Feature_HasVFP2Bit)) // "flds" 766 Mnemonic = "vldr"; 767 return; 768 } 769 break; 770 case 'm': // 4 strings to match. 771 switch (Mnemonic[2]) { 772 default: break; 773 case 'r': // 2 strings to match. 774 switch (Mnemonic[3]) { 775 default: break; 776 case 's': // 1 string to match. 777 if (Features.test(Feature_HasVFP2Bit)) // "fmrs" 778 Mnemonic = "vmov"; 779 return; 780 case 'x': // 1 string to match. 781 if (Features.test(Feature_HasVFP2Bit)) // "fmrx" 782 Mnemonic = "vmrs"; 783 return; 784 } 785 break; 786 case 's': // 1 string to match. 787 if (Mnemonic[3] != 'r') 788 break; 789 if (Features.test(Feature_HasVFP2Bit)) // "fmsr" 790 Mnemonic = "vmov"; 791 return; 792 case 'x': // 1 string to match. 793 if (Mnemonic[3] != 'r') 794 break; 795 if (Features.test(Feature_HasVFP2Bit)) // "fmxr" 796 Mnemonic = "vmsr"; 797 return; 798 } 799 break; 800 case 's': // 2 strings to match. 801 if (Mnemonic[2] != 't') 802 break; 803 switch (Mnemonic[3]) { 804 default: break; 805 case 'd': // 1 string to match. 806 if (Features.test(Feature_HasVFP2Bit)) // "fstd" 807 Mnemonic = "vstr"; 808 return; 809 case 's': // 1 string to match. 810 if (Features.test(Feature_HasVFP2Bit)) // "fsts" 811 Mnemonic = "vstr"; 812 return; 813 } 814 break; 815 } 816 break; 817 case 'v': // 2 strings to match. 818 switch (Mnemonic[1]) { 819 default: break; 820 case 'l': // 1 string to match. 821 if (memcmp(Mnemonic.data()+2, "dm", 2) != 0) 822 break; 823 Mnemonic = "vldmia"; // "vldm" 824 return; 825 case 's': // 1 string to match. 826 if (memcmp(Mnemonic.data()+2, "tm", 2) != 0) 827 break; 828 Mnemonic = "vstmia"; // "vstm" 829 return; 830 } 831 break; 832 } 833 break; 834 case 5: // 51 strings to match. 835 switch (Mnemonic[0]) { 836 default: break; 837 case 'f': // 18 strings to match. 838 switch (Mnemonic[1]) { 839 default: break; 840 case 'a': // 2 strings to match. 841 if (memcmp(Mnemonic.data()+2, "dd", 2) != 0) 842 break; 843 switch (Mnemonic[4]) { 844 default: break; 845 case 'd': // 1 string to match. 846 if (Features.test(Feature_HasVFP2Bit)) // "faddd" 847 Mnemonic = "vadd.f64"; 848 return; 849 case 's': // 1 string to match. 850 if (Features.test(Feature_HasVFP2Bit)) // "fadds" 851 Mnemonic = "vadd.f32"; 852 return; 853 } 854 break; 855 case 'c': // 4 strings to match. 856 switch (Mnemonic[2]) { 857 default: break; 858 case 'm': // 2 strings to match. 859 if (Mnemonic[3] != 'p') 860 break; 861 switch (Mnemonic[4]) { 862 default: break; 863 case 'd': // 1 string to match. 864 if (Features.test(Feature_HasVFP2Bit)) // "fcmpd" 865 Mnemonic = "vcmp.f64"; 866 return; 867 case 's': // 1 string to match. 868 if (Features.test(Feature_HasVFP2Bit)) // "fcmps" 869 Mnemonic = "vcmp.f32"; 870 return; 871 } 872 break; 873 case 'p': // 2 strings to match. 874 if (Mnemonic[3] != 'y') 875 break; 876 switch (Mnemonic[4]) { 877 default: break; 878 case 'd': // 1 string to match. 879 if (Features.test(Feature_HasVFP2Bit)) // "fcpyd" 880 Mnemonic = "vmov.f64"; 881 return; 882 case 's': // 1 string to match. 883 if (Features.test(Feature_HasVFP2Bit)) // "fcpys" 884 Mnemonic = "vmov.f32"; 885 return; 886 } 887 break; 888 } 889 break; 890 case 'd': // 2 strings to match. 891 if (memcmp(Mnemonic.data()+2, "iv", 2) != 0) 892 break; 893 switch (Mnemonic[4]) { 894 default: break; 895 case 'd': // 1 string to match. 896 if (Features.test(Feature_HasVFP2Bit)) // "fdivd" 897 Mnemonic = "vdiv.f64"; 898 return; 899 case 's': // 1 string to match. 900 if (Features.test(Feature_HasVFP2Bit)) // "fdivs" 901 Mnemonic = "vdiv.f32"; 902 return; 903 } 904 break; 905 case 'm': // 8 strings to match. 906 switch (Mnemonic[2]) { 907 default: break; 908 case 'a': // 2 strings to match. 909 if (Mnemonic[3] != 'c') 910 break; 911 switch (Mnemonic[4]) { 912 default: break; 913 case 'd': // 1 string to match. 914 if (Features.test(Feature_HasVFP2Bit)) // "fmacd" 915 Mnemonic = "vmla.f64"; 916 return; 917 case 's': // 1 string to match. 918 if (Features.test(Feature_HasVFP2Bit)) // "fmacs" 919 Mnemonic = "vmla.f32"; 920 return; 921 } 922 break; 923 case 'd': // 1 string to match. 924 if (memcmp(Mnemonic.data()+3, "rr", 2) != 0) 925 break; 926 if (Features.test(Feature_HasVFP2Bit)) // "fmdrr" 927 Mnemonic = "vmov"; 928 return; 929 case 'r': // 3 strings to match. 930 switch (Mnemonic[3]) { 931 default: break; 932 case 'd': // 2 strings to match. 933 switch (Mnemonic[4]) { 934 default: break; 935 case 'd': // 1 string to match. 936 if (Features.test(Feature_HasVFP2Bit)) // "fmrdd" 937 Mnemonic = "vmov"; 938 return; 939 case 's': // 1 string to match. 940 if (Features.test(Feature_HasVFP2Bit)) // "fmrds" 941 Mnemonic = "vmov"; 942 return; 943 } 944 break; 945 case 'r': // 1 string to match. 946 if (Mnemonic[4] != 'd') 947 break; 948 if (Features.test(Feature_HasVFP2Bit)) // "fmrrd" 949 Mnemonic = "vmov"; 950 return; 951 } 952 break; 953 case 'u': // 2 strings to match. 954 if (Mnemonic[3] != 'l') 955 break; 956 switch (Mnemonic[4]) { 957 default: break; 958 case 'd': // 1 string to match. 959 if (Features.test(Feature_HasVFP2Bit)) // "fmuld" 960 Mnemonic = "vmul.f64"; 961 return; 962 case 's': // 1 string to match. 963 if (Features.test(Feature_HasVFP2Bit)) // "fmuls" 964 Mnemonic = "vmul.f32"; 965 return; 966 } 967 break; 968 } 969 break; 970 case 'n': // 2 strings to match. 971 if (memcmp(Mnemonic.data()+2, "eg", 2) != 0) 972 break; 973 switch (Mnemonic[4]) { 974 default: break; 975 case 'd': // 1 string to match. 976 if (Features.test(Feature_HasVFP2Bit)) // "fnegd" 977 Mnemonic = "vneg.f64"; 978 return; 979 case 's': // 1 string to match. 980 if (Features.test(Feature_HasVFP2Bit)) // "fnegs" 981 Mnemonic = "vneg.f32"; 982 return; 983 } 984 break; 985 } 986 break; 987 case 'l': // 3 strings to match. 988 if (memcmp(Mnemonic.data()+1, "dm", 2) != 0) 989 break; 990 switch (Mnemonic[3]) { 991 default: break; 992 case 'e': // 1 string to match. 993 if (Mnemonic[4] != 'a') 994 break; 995 Mnemonic = "ldmdb"; // "ldmea" 996 return; 997 case 'f': // 1 string to match. 998 if (Mnemonic[4] != 'd') 999 break; 1000 Mnemonic = "ldm"; // "ldmfd" 1001 return; 1002 case 'i': // 1 string to match. 1003 if (Mnemonic[4] != 'a') 1004 break; 1005 Mnemonic = "ldm"; // "ldmia" 1006 return; 1007 } 1008 break; 1009 case 'r': // 4 strings to match. 1010 if (memcmp(Mnemonic.data()+1, "fe", 2) != 0) 1011 break; 1012 switch (Mnemonic[3]) { 1013 default: break; 1014 case 'e': // 2 strings to match. 1015 switch (Mnemonic[4]) { 1016 default: break; 1017 case 'a': // 1 string to match. 1018 Mnemonic = "rfedb"; // "rfeea" 1019 return; 1020 case 'd': // 1 string to match. 1021 Mnemonic = "rfeib"; // "rfeed" 1022 return; 1023 } 1024 break; 1025 case 'f': // 2 strings to match. 1026 switch (Mnemonic[4]) { 1027 default: break; 1028 case 'a': // 1 string to match. 1029 Mnemonic = "rfeda"; // "rfefa" 1030 return; 1031 case 'd': // 1 string to match. 1032 Mnemonic = "rfeia"; // "rfefd" 1033 return; 1034 } 1035 break; 1036 } 1037 break; 1038 case 's': // 7 strings to match. 1039 switch (Mnemonic[1]) { 1040 default: break; 1041 case 'r': // 4 strings to match. 1042 if (Mnemonic[2] != 's') 1043 break; 1044 switch (Mnemonic[3]) { 1045 default: break; 1046 case 'e': // 2 strings to match. 1047 switch (Mnemonic[4]) { 1048 default: break; 1049 case 'a': // 1 string to match. 1050 Mnemonic = "srsia"; // "srsea" 1051 return; 1052 case 'd': // 1 string to match. 1053 Mnemonic = "srsda"; // "srsed" 1054 return; 1055 } 1056 break; 1057 case 'f': // 2 strings to match. 1058 switch (Mnemonic[4]) { 1059 default: break; 1060 case 'a': // 1 string to match. 1061 Mnemonic = "srsib"; // "srsfa" 1062 return; 1063 case 'd': // 1 string to match. 1064 Mnemonic = "srsdb"; // "srsfd" 1065 return; 1066 } 1067 break; 1068 } 1069 break; 1070 case 't': // 3 strings to match. 1071 if (Mnemonic[2] != 'm') 1072 break; 1073 switch (Mnemonic[3]) { 1074 default: break; 1075 case 'e': // 1 string to match. 1076 if (Mnemonic[4] != 'a') 1077 break; 1078 Mnemonic = "stm"; // "stmea" 1079 return; 1080 case 'f': // 1 string to match. 1081 if (Mnemonic[4] != 'd') 1082 break; 1083 Mnemonic = "stmdb"; // "stmfd" 1084 return; 1085 case 'i': // 1 string to match. 1086 if (Mnemonic[4] != 'a') 1087 break; 1088 Mnemonic = "stm"; // "stmia" 1089 return; 1090 } 1091 break; 1092 } 1093 break; 1094 case 'v': // 19 strings to match. 1095 switch (Mnemonic[1]) { 1096 default: break; 1097 case 'a': // 3 strings to match. 1098 switch (Mnemonic[2]) { 1099 default: break; 1100 case 'b': // 1 string to match. 1101 if (memcmp(Mnemonic.data()+3, "sq", 2) != 0) 1102 break; 1103 if (Features.test(Feature_HasNEONBit)) // "vabsq" 1104 Mnemonic = "vabs"; 1105 return; 1106 case 'd': // 1 string to match. 1107 if (memcmp(Mnemonic.data()+3, "dq", 2) != 0) 1108 break; 1109 if (Features.test(Feature_HasNEONBit)) // "vaddq" 1110 Mnemonic = "vadd"; 1111 return; 1112 case 'n': // 1 string to match. 1113 if (memcmp(Mnemonic.data()+3, "dq", 2) != 0) 1114 break; 1115 if (Features.test(Feature_HasNEONBit)) // "vandq" 1116 Mnemonic = "vand"; 1117 return; 1118 } 1119 break; 1120 case 'b': // 1 string to match. 1121 if (memcmp(Mnemonic.data()+2, "icq", 3) != 0) 1122 break; 1123 if (Features.test(Feature_HasNEONBit)) // "vbicq" 1124 Mnemonic = "vbic"; 1125 return; 1126 case 'c': // 3 strings to match. 1127 switch (Mnemonic[2]) { 1128 default: break; 1129 case 'e': // 1 string to match. 1130 if (memcmp(Mnemonic.data()+3, "qq", 2) != 0) 1131 break; 1132 if (Features.test(Feature_HasNEONBit)) // "vceqq" 1133 Mnemonic = "vceq"; 1134 return; 1135 case 'l': // 1 string to match. 1136 if (memcmp(Mnemonic.data()+3, "eq", 2) != 0) 1137 break; 1138 if (Features.test(Feature_HasNEONBit)) // "vcleq" 1139 Mnemonic = "vcle"; 1140 return; 1141 case 'v': // 1 string to match. 1142 if (memcmp(Mnemonic.data()+3, "tq", 2) != 0) 1143 break; 1144 if (Features.test(Feature_HasNEONBit)) // "vcvtq" 1145 Mnemonic = "vcvt"; 1146 return; 1147 } 1148 break; 1149 case 'e': // 1 string to match. 1150 if (memcmp(Mnemonic.data()+2, "orq", 3) != 0) 1151 break; 1152 if (Features.test(Feature_HasNEONBit)) // "veorq" 1153 Mnemonic = "veor"; 1154 return; 1155 case 'm': // 5 strings to match. 1156 switch (Mnemonic[2]) { 1157 default: break; 1158 case 'a': // 1 string to match. 1159 if (memcmp(Mnemonic.data()+3, "xq", 2) != 0) 1160 break; 1161 if (Features.test(Feature_HasNEONBit)) // "vmaxq" 1162 Mnemonic = "vmax"; 1163 return; 1164 case 'i': // 1 string to match. 1165 if (memcmp(Mnemonic.data()+3, "nq", 2) != 0) 1166 break; 1167 if (Features.test(Feature_HasNEONBit)) // "vminq" 1168 Mnemonic = "vmin"; 1169 return; 1170 case 'o': // 1 string to match. 1171 if (memcmp(Mnemonic.data()+3, "vq", 2) != 0) 1172 break; 1173 if (Features.test(Feature_HasNEONBit)) // "vmovq" 1174 Mnemonic = "vmov"; 1175 return; 1176 case 'u': // 1 string to match. 1177 if (memcmp(Mnemonic.data()+3, "lq", 2) != 0) 1178 break; 1179 if (Features.test(Feature_HasNEONBit)) // "vmulq" 1180 Mnemonic = "vmul"; 1181 return; 1182 case 'v': // 1 string to match. 1183 if (memcmp(Mnemonic.data()+3, "nq", 2) != 0) 1184 break; 1185 if (Features.test(Feature_HasNEONBit)) // "vmvnq" 1186 Mnemonic = "vmvn"; 1187 return; 1188 } 1189 break; 1190 case 'o': // 1 string to match. 1191 if (memcmp(Mnemonic.data()+2, "rrq", 3) != 0) 1192 break; 1193 if (Features.test(Feature_HasNEONBit)) // "vorrq" 1194 Mnemonic = "vorr"; 1195 return; 1196 case 's': // 4 strings to match. 1197 switch (Mnemonic[2]) { 1198 default: break; 1199 case 'h': // 2 strings to match. 1200 switch (Mnemonic[3]) { 1201 default: break; 1202 case 'l': // 1 string to match. 1203 if (Mnemonic[4] != 'q') 1204 break; 1205 if (Features.test(Feature_HasNEONBit)) // "vshlq" 1206 Mnemonic = "vshl"; 1207 return; 1208 case 'r': // 1 string to match. 1209 if (Mnemonic[4] != 'q') 1210 break; 1211 if (Features.test(Feature_HasNEONBit)) // "vshrq" 1212 Mnemonic = "vshr"; 1213 return; 1214 } 1215 break; 1216 case 'u': // 1 string to match. 1217 if (memcmp(Mnemonic.data()+3, "bq", 2) != 0) 1218 break; 1219 if (Features.test(Feature_HasNEONBit)) // "vsubq" 1220 Mnemonic = "vsub"; 1221 return; 1222 case 'w': // 1 string to match. 1223 if (memcmp(Mnemonic.data()+3, "pq", 2) != 0) 1224 break; 1225 if (Features.test(Feature_HasNEONBit)) // "vswpq" 1226 Mnemonic = "vswp"; 1227 return; 1228 } 1229 break; 1230 case 'z': // 1 string to match. 1231 if (memcmp(Mnemonic.data()+2, "ipq", 3) != 0) 1232 break; 1233 if (Features.test(Feature_HasNEONBit)) // "vzipq" 1234 Mnemonic = "vzip"; 1235 return; 1236 } 1237 break; 1238 } 1239 break; 1240 case 6: // 10 strings to match. 1241 if (Mnemonic[0] != 'f') 1242 break; 1243 switch (Mnemonic[1]) { 1244 default: break; 1245 case 's': // 4 strings to match. 1246 switch (Mnemonic[2]) { 1247 default: break; 1248 case 'i': // 2 strings to match. 1249 if (memcmp(Mnemonic.data()+3, "to", 2) != 0) 1250 break; 1251 switch (Mnemonic[5]) { 1252 default: break; 1253 case 'd': // 1 string to match. 1254 if (Features.test(Feature_HasVFP2Bit)) // "fsitod" 1255 Mnemonic = "vcvt.f64.s32"; 1256 return; 1257 case 's': // 1 string to match. 1258 if (Features.test(Feature_HasVFP2Bit)) // "fsitos" 1259 Mnemonic = "vcvt.f32.s32"; 1260 return; 1261 } 1262 break; 1263 case 'q': // 2 strings to match. 1264 if (memcmp(Mnemonic.data()+3, "rt", 2) != 0) 1265 break; 1266 switch (Mnemonic[5]) { 1267 default: break; 1268 case 'd': // 1 string to match. 1269 if (Features.test(Feature_HasVFP2Bit)) // "fsqrtd" 1270 Mnemonic = "vsqrt"; 1271 return; 1272 case 's': // 1 string to match. 1273 if (Features.test(Feature_HasVFP2Bit)) // "fsqrts" 1274 Mnemonic = "vsqrt"; 1275 return; 1276 } 1277 break; 1278 } 1279 break; 1280 case 't': // 4 strings to match. 1281 if (Mnemonic[2] != 'o') 1282 break; 1283 switch (Mnemonic[3]) { 1284 default: break; 1285 case 's': // 2 strings to match. 1286 if (Mnemonic[4] != 'i') 1287 break; 1288 switch (Mnemonic[5]) { 1289 default: break; 1290 case 'd': // 1 string to match. 1291 if (Features.test(Feature_HasVFP2Bit)) // "ftosid" 1292 Mnemonic = "vcvtr.s32.f64"; 1293 return; 1294 case 's': // 1 string to match. 1295 if (Features.test(Feature_HasVFP2Bit)) // "ftosis" 1296 Mnemonic = "vcvtr.s32.f32"; 1297 return; 1298 } 1299 break; 1300 case 'u': // 2 strings to match. 1301 if (Mnemonic[4] != 'i') 1302 break; 1303 switch (Mnemonic[5]) { 1304 default: break; 1305 case 'd': // 1 string to match. 1306 if (Features.test(Feature_HasVFP2Bit)) // "ftouid" 1307 Mnemonic = "vcvtr.u32.f64"; 1308 return; 1309 case 's': // 1 string to match. 1310 if (Features.test(Feature_HasVFP2Bit)) // "ftouis" 1311 Mnemonic = "vcvtr.u32.f32"; 1312 return; 1313 } 1314 break; 1315 } 1316 break; 1317 case 'u': // 2 strings to match. 1318 if (memcmp(Mnemonic.data()+2, "ito", 3) != 0) 1319 break; 1320 switch (Mnemonic[5]) { 1321 default: break; 1322 case 'd': // 1 string to match. 1323 if (Features.test(Feature_HasVFP2Bit)) // "fuitod" 1324 Mnemonic = "vcvt.f64.u32"; 1325 return; 1326 case 's': // 1 string to match. 1327 if (Features.test(Feature_HasVFP2Bit)) // "fuitos" 1328 Mnemonic = "vcvt.f32.u32"; 1329 return; 1330 } 1331 break; 1332 } 1333 break; 1334 case 7: // 9 strings to match. 1335 switch (Mnemonic[0]) { 1336 default: break; 1337 case 'f': // 8 strings to match. 1338 switch (Mnemonic[1]) { 1339 default: break; 1340 case 'l': // 2 strings to match. 1341 if (memcmp(Mnemonic.data()+2, "dm", 2) != 0) 1342 break; 1343 switch (Mnemonic[4]) { 1344 default: break; 1345 case 'e': // 1 string to match. 1346 if (memcmp(Mnemonic.data()+5, "ax", 2) != 0) 1347 break; 1348 if (Features.test(Feature_HasVFP2Bit)) // "fldmeax" 1349 Mnemonic = "fldmdbx"; 1350 return; 1351 case 'f': // 1 string to match. 1352 if (memcmp(Mnemonic.data()+5, "dx", 2) != 0) 1353 break; 1354 if (Features.test(Feature_HasVFP2Bit)) // "fldmfdx" 1355 Mnemonic = "fldmiax"; 1356 return; 1357 } 1358 break; 1359 case 's': // 2 strings to match. 1360 if (memcmp(Mnemonic.data()+2, "tm", 2) != 0) 1361 break; 1362 switch (Mnemonic[4]) { 1363 default: break; 1364 case 'e': // 1 string to match. 1365 if (memcmp(Mnemonic.data()+5, "ax", 2) != 0) 1366 break; 1367 if (Features.test(Feature_HasVFP2Bit)) // "fstmeax" 1368 Mnemonic = "fstmiax"; 1369 return; 1370 case 'f': // 1 string to match. 1371 if (memcmp(Mnemonic.data()+5, "dx", 2) != 0) 1372 break; 1373 if (Features.test(Feature_HasVFP2Bit)) // "fstmfdx" 1374 Mnemonic = "fstmdbx"; 1375 return; 1376 } 1377 break; 1378 case 't': // 4 strings to match. 1379 if (Mnemonic[2] != 'o') 1380 break; 1381 switch (Mnemonic[3]) { 1382 default: break; 1383 case 's': // 2 strings to match. 1384 if (memcmp(Mnemonic.data()+4, "iz", 2) != 0) 1385 break; 1386 switch (Mnemonic[6]) { 1387 default: break; 1388 case 'd': // 1 string to match. 1389 if (Features.test(Feature_HasVFP2Bit)) // "ftosizd" 1390 Mnemonic = "vcvt.s32.f64"; 1391 return; 1392 case 's': // 1 string to match. 1393 if (Features.test(Feature_HasVFP2Bit)) // "ftosizs" 1394 Mnemonic = "vcvt.s32.f32"; 1395 return; 1396 } 1397 break; 1398 case 'u': // 2 strings to match. 1399 if (memcmp(Mnemonic.data()+4, "iz", 2) != 0) 1400 break; 1401 switch (Mnemonic[6]) { 1402 default: break; 1403 case 'd': // 1 string to match. 1404 if (Features.test(Feature_HasVFP2Bit)) // "ftouizd" 1405 Mnemonic = "vcvt.u32.f64"; 1406 return; 1407 case 's': // 1 string to match. 1408 if (Features.test(Feature_HasVFP2Bit)) // "ftouizs" 1409 Mnemonic = "vcvt.u32.f32"; 1410 return; 1411 } 1412 break; 1413 } 1414 break; 1415 } 1416 break; 1417 case 'v': // 1 string to match. 1418 if (memcmp(Mnemonic.data()+1, "ldrb.8", 6) != 0) 1419 break; 1420 Mnemonic = "vldrb.u8"; // "vldrb.8" 1421 return; 1422 } 1423 break; 1424 case 8: // 13 strings to match. 1425 switch (Mnemonic[0]) { 1426 default: break; 1427 case 'q': // 1 string to match. 1428 if (memcmp(Mnemonic.data()+1, "subaddx", 7) != 0) 1429 break; 1430 Mnemonic = "qsax"; // "qsubaddx" 1431 return; 1432 case 's': // 2 strings to match. 1433 switch (Mnemonic[1]) { 1434 default: break; 1435 case 'a': // 1 string to match. 1436 if (memcmp(Mnemonic.data()+2, "ddsubx", 6) != 0) 1437 break; 1438 Mnemonic = "sasx"; // "saddsubx" 1439 return; 1440 case 's': // 1 string to match. 1441 if (memcmp(Mnemonic.data()+2, "ubaddx", 6) != 0) 1442 break; 1443 Mnemonic = "ssax"; // "ssubaddx" 1444 return; 1445 } 1446 break; 1447 case 'u': // 2 strings to match. 1448 switch (Mnemonic[1]) { 1449 default: break; 1450 case 'a': // 1 string to match. 1451 if (memcmp(Mnemonic.data()+2, "ddsubx", 6) != 0) 1452 break; 1453 Mnemonic = "uasx"; // "uaddsubx" 1454 return; 1455 case 's': // 1 string to match. 1456 if (memcmp(Mnemonic.data()+2, "ubaddx", 6) != 0) 1457 break; 1458 Mnemonic = "usax"; // "usubaddx" 1459 return; 1460 } 1461 break; 1462 case 'v': // 8 strings to match. 1463 switch (Mnemonic[1]) { 1464 default: break; 1465 case 'l': // 6 strings to match. 1466 if (memcmp(Mnemonic.data()+2, "dr", 2) != 0) 1467 break; 1468 switch (Mnemonic[4]) { 1469 default: break; 1470 case 'b': // 3 strings to match. 1471 switch (Mnemonic[5]) { 1472 default: break; 1473 case '.': // 1 string to match. 1474 if (memcmp(Mnemonic.data()+6, "s8", 2) != 0) 1475 break; 1476 Mnemonic = "vldrb.u8"; // "vldrb.s8" 1477 return; 1478 case 'e': // 1 string to match. 1479 if (memcmp(Mnemonic.data()+6, ".8", 2) != 0) 1480 break; 1481 Mnemonic = "vldrbe.u8"; // "vldrbe.8" 1482 return; 1483 case 't': // 1 string to match. 1484 if (memcmp(Mnemonic.data()+6, ".8", 2) != 0) 1485 break; 1486 Mnemonic = "vldrbt.u8"; // "vldrbt.8" 1487 return; 1488 } 1489 break; 1490 case 'd': // 1 string to match. 1491 if (memcmp(Mnemonic.data()+5, ".64", 3) != 0) 1492 break; 1493 Mnemonic = "vldrd.u64"; // "vldrd.64" 1494 return; 1495 case 'h': // 1 string to match. 1496 if (memcmp(Mnemonic.data()+5, ".16", 3) != 0) 1497 break; 1498 Mnemonic = "vldrh.u16"; // "vldrh.16" 1499 return; 1500 case 'w': // 1 string to match. 1501 if (memcmp(Mnemonic.data()+5, ".32", 3) != 0) 1502 break; 1503 Mnemonic = "vldrw.u32"; // "vldrw.32" 1504 return; 1505 } 1506 break; 1507 case 's': // 2 strings to match. 1508 if (memcmp(Mnemonic.data()+2, "trb.", 4) != 0) 1509 break; 1510 switch (Mnemonic[6]) { 1511 default: break; 1512 case 's': // 1 string to match. 1513 if (Mnemonic[7] != '8') 1514 break; 1515 Mnemonic = "vstrb.8"; // "vstrb.s8" 1516 return; 1517 case 'u': // 1 string to match. 1518 if (Mnemonic[7] != '8') 1519 break; 1520 Mnemonic = "vstrb.8"; // "vstrb.u8" 1521 return; 1522 } 1523 break; 1524 } 1525 break; 1526 } 1527 break; 1528 case 9: // 35 strings to match. 1529 switch (Mnemonic[0]) { 1530 default: break; 1531 case 's': // 2 strings to match. 1532 if (Mnemonic[1] != 'h') 1533 break; 1534 switch (Mnemonic[2]) { 1535 default: break; 1536 case 'a': // 1 string to match. 1537 if (memcmp(Mnemonic.data()+3, "ddsubx", 6) != 0) 1538 break; 1539 Mnemonic = "shasx"; // "shaddsubx" 1540 return; 1541 case 's': // 1 string to match. 1542 if (memcmp(Mnemonic.data()+3, "ubaddx", 6) != 0) 1543 break; 1544 Mnemonic = "shsax"; // "shsubaddx" 1545 return; 1546 } 1547 break; 1548 case 'u': // 4 strings to match. 1549 switch (Mnemonic[1]) { 1550 default: break; 1551 case 'h': // 2 strings to match. 1552 switch (Mnemonic[2]) { 1553 default: break; 1554 case 'a': // 1 string to match. 1555 if (memcmp(Mnemonic.data()+3, "ddsubx", 6) != 0) 1556 break; 1557 Mnemonic = "uhasx"; // "uhaddsubx" 1558 return; 1559 case 's': // 1 string to match. 1560 if (memcmp(Mnemonic.data()+3, "ubaddx", 6) != 0) 1561 break; 1562 Mnemonic = "uhsax"; // "uhsubaddx" 1563 return; 1564 } 1565 break; 1566 case 'q': // 2 strings to match. 1567 switch (Mnemonic[2]) { 1568 default: break; 1569 case 'a': // 1 string to match. 1570 if (memcmp(Mnemonic.data()+3, "ddsubx", 6) != 0) 1571 break; 1572 Mnemonic = "uqasx"; // "uqaddsubx" 1573 return; 1574 case 's': // 1 string to match. 1575 if (memcmp(Mnemonic.data()+3, "ubaddx", 6) != 0) 1576 break; 1577 Mnemonic = "uqsax"; // "uqsubaddx" 1578 return; 1579 } 1580 break; 1581 } 1582 break; 1583 case 'v': // 29 strings to match. 1584 switch (Mnemonic[1]) { 1585 default: break; 1586 case 'l': // 14 strings to match. 1587 if (memcmp(Mnemonic.data()+2, "dr", 2) != 0) 1588 break; 1589 switch (Mnemonic[4]) { 1590 default: break; 1591 case 'b': // 2 strings to match. 1592 switch (Mnemonic[5]) { 1593 default: break; 1594 case 'e': // 1 string to match. 1595 if (memcmp(Mnemonic.data()+6, ".s8", 3) != 0) 1596 break; 1597 Mnemonic = "vldrbe.u8"; // "vldrbe.s8" 1598 return; 1599 case 't': // 1 string to match. 1600 if (memcmp(Mnemonic.data()+6, ".s8", 3) != 0) 1601 break; 1602 Mnemonic = "vldrbt.u8"; // "vldrbt.s8" 1603 return; 1604 } 1605 break; 1606 case 'd': // 4 strings to match. 1607 switch (Mnemonic[5]) { 1608 default: break; 1609 case '.': // 2 strings to match. 1610 switch (Mnemonic[6]) { 1611 default: break; 1612 case 'f': // 1 string to match. 1613 if (memcmp(Mnemonic.data()+7, "64", 2) != 0) 1614 break; 1615 Mnemonic = "vldrd.u64"; // "vldrd.f64" 1616 return; 1617 case 's': // 1 string to match. 1618 if (memcmp(Mnemonic.data()+7, "64", 2) != 0) 1619 break; 1620 Mnemonic = "vldrd.u64"; // "vldrd.s64" 1621 return; 1622 } 1623 break; 1624 case 'e': // 1 string to match. 1625 if (memcmp(Mnemonic.data()+6, ".64", 3) != 0) 1626 break; 1627 Mnemonic = "vldrde.u64"; // "vldrde.64" 1628 return; 1629 case 't': // 1 string to match. 1630 if (memcmp(Mnemonic.data()+6, ".64", 3) != 0) 1631 break; 1632 Mnemonic = "vldrdt.u64"; // "vldrdt.64" 1633 return; 1634 } 1635 break; 1636 case 'h': // 4 strings to match. 1637 switch (Mnemonic[5]) { 1638 default: break; 1639 case '.': // 2 strings to match. 1640 switch (Mnemonic[6]) { 1641 default: break; 1642 case 'f': // 1 string to match. 1643 if (memcmp(Mnemonic.data()+7, "16", 2) != 0) 1644 break; 1645 Mnemonic = "vldrh.u16"; // "vldrh.f16" 1646 return; 1647 case 's': // 1 string to match. 1648 if (memcmp(Mnemonic.data()+7, "16", 2) != 0) 1649 break; 1650 Mnemonic = "vldrh.u16"; // "vldrh.s16" 1651 return; 1652 } 1653 break; 1654 case 'e': // 1 string to match. 1655 if (memcmp(Mnemonic.data()+6, ".16", 3) != 0) 1656 break; 1657 Mnemonic = "vldrhe.u16"; // "vldrhe.16" 1658 return; 1659 case 't': // 1 string to match. 1660 if (memcmp(Mnemonic.data()+6, ".16", 3) != 0) 1661 break; 1662 Mnemonic = "vldrht.u16"; // "vldrht.16" 1663 return; 1664 } 1665 break; 1666 case 'w': // 4 strings to match. 1667 switch (Mnemonic[5]) { 1668 default: break; 1669 case '.': // 2 strings to match. 1670 switch (Mnemonic[6]) { 1671 default: break; 1672 case 'f': // 1 string to match. 1673 if (memcmp(Mnemonic.data()+7, "32", 2) != 0) 1674 break; 1675 Mnemonic = "vldrw.u32"; // "vldrw.f32" 1676 return; 1677 case 's': // 1 string to match. 1678 if (memcmp(Mnemonic.data()+7, "32", 2) != 0) 1679 break; 1680 Mnemonic = "vldrw.u32"; // "vldrw.s32" 1681 return; 1682 } 1683 break; 1684 case 'e': // 1 string to match. 1685 if (memcmp(Mnemonic.data()+6, ".32", 3) != 0) 1686 break; 1687 Mnemonic = "vldrwe.u32"; // "vldrwe.32" 1688 return; 1689 case 't': // 1 string to match. 1690 if (memcmp(Mnemonic.data()+6, ".32", 3) != 0) 1691 break; 1692 Mnemonic = "vldrwt.u32"; // "vldrwt.32" 1693 return; 1694 } 1695 break; 1696 } 1697 break; 1698 case 'm': // 2 strings to match. 1699 if (memcmp(Mnemonic.data()+2, "ovq.f", 5) != 0) 1700 break; 1701 switch (Mnemonic[7]) { 1702 default: break; 1703 case '3': // 1 string to match. 1704 if (Mnemonic[8] != '2') 1705 break; 1706 if (Features.test(Feature_HasNEONBit)) // "vmovq.f32" 1707 Mnemonic = "vmov.f32"; 1708 return; 1709 case '6': // 1 string to match. 1710 if (Mnemonic[8] != '4') 1711 break; 1712 if (Features.test(Feature_HasNEONBit)) // "vmovq.f64" 1713 Mnemonic = "vmov.f64"; 1714 return; 1715 } 1716 break; 1717 case 's': // 13 strings to match. 1718 if (memcmp(Mnemonic.data()+2, "tr", 2) != 0) 1719 break; 1720 switch (Mnemonic[4]) { 1721 default: break; 1722 case 'b': // 4 strings to match. 1723 switch (Mnemonic[5]) { 1724 default: break; 1725 case 'e': // 2 strings to match. 1726 if (Mnemonic[6] != '.') 1727 break; 1728 switch (Mnemonic[7]) { 1729 default: break; 1730 case 's': // 1 string to match. 1731 if (Mnemonic[8] != '8') 1732 break; 1733 Mnemonic = "vstrbe.8"; // "vstrbe.s8" 1734 return; 1735 case 'u': // 1 string to match. 1736 if (Mnemonic[8] != '8') 1737 break; 1738 Mnemonic = "vstrbe.8"; // "vstrbe.u8" 1739 return; 1740 } 1741 break; 1742 case 't': // 2 strings to match. 1743 if (Mnemonic[6] != '.') 1744 break; 1745 switch (Mnemonic[7]) { 1746 default: break; 1747 case 's': // 1 string to match. 1748 if (Mnemonic[8] != '8') 1749 break; 1750 Mnemonic = "vstrbt.8"; // "vstrbt.s8" 1751 return; 1752 case 'u': // 1 string to match. 1753 if (Mnemonic[8] != '8') 1754 break; 1755 Mnemonic = "vstrbt.8"; // "vstrbt.u8" 1756 return; 1757 } 1758 break; 1759 } 1760 break; 1761 case 'd': // 3 strings to match. 1762 if (Mnemonic[5] != '.') 1763 break; 1764 switch (Mnemonic[6]) { 1765 default: break; 1766 case 'f': // 1 string to match. 1767 if (memcmp(Mnemonic.data()+7, "64", 2) != 0) 1768 break; 1769 Mnemonic = "vstrd.64"; // "vstrd.f64" 1770 return; 1771 case 's': // 1 string to match. 1772 if (memcmp(Mnemonic.data()+7, "64", 2) != 0) 1773 break; 1774 Mnemonic = "vstrd.64"; // "vstrd.s64" 1775 return; 1776 case 'u': // 1 string to match. 1777 if (memcmp(Mnemonic.data()+7, "64", 2) != 0) 1778 break; 1779 Mnemonic = "vstrd.64"; // "vstrd.u64" 1780 return; 1781 } 1782 break; 1783 case 'h': // 3 strings to match. 1784 if (Mnemonic[5] != '.') 1785 break; 1786 switch (Mnemonic[6]) { 1787 default: break; 1788 case 'f': // 1 string to match. 1789 if (memcmp(Mnemonic.data()+7, "16", 2) != 0) 1790 break; 1791 Mnemonic = "vstrh.16"; // "vstrh.f16" 1792 return; 1793 case 's': // 1 string to match. 1794 if (memcmp(Mnemonic.data()+7, "16", 2) != 0) 1795 break; 1796 Mnemonic = "vstrh.16"; // "vstrh.s16" 1797 return; 1798 case 'u': // 1 string to match. 1799 if (memcmp(Mnemonic.data()+7, "16", 2) != 0) 1800 break; 1801 Mnemonic = "vstrh.16"; // "vstrh.u16" 1802 return; 1803 } 1804 break; 1805 case 'w': // 3 strings to match. 1806 if (Mnemonic[5] != '.') 1807 break; 1808 switch (Mnemonic[6]) { 1809 default: break; 1810 case 'f': // 1 string to match. 1811 if (memcmp(Mnemonic.data()+7, "32", 2) != 0) 1812 break; 1813 Mnemonic = "vstrw.32"; // "vstrw.f32" 1814 return; 1815 case 's': // 1 string to match. 1816 if (memcmp(Mnemonic.data()+7, "32", 2) != 0) 1817 break; 1818 Mnemonic = "vstrw.32"; // "vstrw.s32" 1819 return; 1820 case 'u': // 1 string to match. 1821 if (memcmp(Mnemonic.data()+7, "32", 2) != 0) 1822 break; 1823 Mnemonic = "vstrw.32"; // "vstrw.u32" 1824 return; 1825 } 1826 break; 1827 } 1828 break; 1829 } 1830 break; 1831 } 1832 break; 1833 case 10: // 30 strings to match. 1834 if (Mnemonic[0] != 'v') 1835 break; 1836 switch (Mnemonic[1]) { 1837 default: break; 1838 case 'l': // 12 strings to match. 1839 if (memcmp(Mnemonic.data()+2, "dr", 2) != 0) 1840 break; 1841 switch (Mnemonic[4]) { 1842 default: break; 1843 case 'd': // 4 strings to match. 1844 switch (Mnemonic[5]) { 1845 default: break; 1846 case 'e': // 2 strings to match. 1847 if (Mnemonic[6] != '.') 1848 break; 1849 switch (Mnemonic[7]) { 1850 default: break; 1851 case 'f': // 1 string to match. 1852 if (memcmp(Mnemonic.data()+8, "64", 2) != 0) 1853 break; 1854 Mnemonic = "vldrde.u64"; // "vldrde.f64" 1855 return; 1856 case 's': // 1 string to match. 1857 if (memcmp(Mnemonic.data()+8, "64", 2) != 0) 1858 break; 1859 Mnemonic = "vldrde.u64"; // "vldrde.s64" 1860 return; 1861 } 1862 break; 1863 case 't': // 2 strings to match. 1864 if (Mnemonic[6] != '.') 1865 break; 1866 switch (Mnemonic[7]) { 1867 default: break; 1868 case 'f': // 1 string to match. 1869 if (memcmp(Mnemonic.data()+8, "64", 2) != 0) 1870 break; 1871 Mnemonic = "vldrdt.u64"; // "vldrdt.f64" 1872 return; 1873 case 's': // 1 string to match. 1874 if (memcmp(Mnemonic.data()+8, "64", 2) != 0) 1875 break; 1876 Mnemonic = "vldrdt.u64"; // "vldrdt.s64" 1877 return; 1878 } 1879 break; 1880 } 1881 break; 1882 case 'h': // 4 strings to match. 1883 switch (Mnemonic[5]) { 1884 default: break; 1885 case 'e': // 2 strings to match. 1886 if (Mnemonic[6] != '.') 1887 break; 1888 switch (Mnemonic[7]) { 1889 default: break; 1890 case 'f': // 1 string to match. 1891 if (memcmp(Mnemonic.data()+8, "16", 2) != 0) 1892 break; 1893 Mnemonic = "vldrhe.u16"; // "vldrhe.f16" 1894 return; 1895 case 's': // 1 string to match. 1896 if (memcmp(Mnemonic.data()+8, "16", 2) != 0) 1897 break; 1898 Mnemonic = "vldrhe.u16"; // "vldrhe.s16" 1899 return; 1900 } 1901 break; 1902 case 't': // 2 strings to match. 1903 if (Mnemonic[6] != '.') 1904 break; 1905 switch (Mnemonic[7]) { 1906 default: break; 1907 case 'f': // 1 string to match. 1908 if (memcmp(Mnemonic.data()+8, "16", 2) != 0) 1909 break; 1910 Mnemonic = "vldrht.u16"; // "vldrht.f16" 1911 return; 1912 case 's': // 1 string to match. 1913 if (memcmp(Mnemonic.data()+8, "16", 2) != 0) 1914 break; 1915 Mnemonic = "vldrht.u16"; // "vldrht.s16" 1916 return; 1917 } 1918 break; 1919 } 1920 break; 1921 case 'w': // 4 strings to match. 1922 switch (Mnemonic[5]) { 1923 default: break; 1924 case 'e': // 2 strings to match. 1925 if (Mnemonic[6] != '.') 1926 break; 1927 switch (Mnemonic[7]) { 1928 default: break; 1929 case 'f': // 1 string to match. 1930 if (memcmp(Mnemonic.data()+8, "32", 2) != 0) 1931 break; 1932 Mnemonic = "vldrwe.u32"; // "vldrwe.f32" 1933 return; 1934 case 's': // 1 string to match. 1935 if (memcmp(Mnemonic.data()+8, "32", 2) != 0) 1936 break; 1937 Mnemonic = "vldrwe.u32"; // "vldrwe.s32" 1938 return; 1939 } 1940 break; 1941 case 't': // 2 strings to match. 1942 if (Mnemonic[6] != '.') 1943 break; 1944 switch (Mnemonic[7]) { 1945 default: break; 1946 case 'f': // 1 string to match. 1947 if (memcmp(Mnemonic.data()+8, "32", 2) != 0) 1948 break; 1949 Mnemonic = "vldrwt.u32"; // "vldrwt.f32" 1950 return; 1951 case 's': // 1 string to match. 1952 if (memcmp(Mnemonic.data()+8, "32", 2) != 0) 1953 break; 1954 Mnemonic = "vldrwt.u32"; // "vldrwt.s32" 1955 return; 1956 } 1957 break; 1958 } 1959 break; 1960 } 1961 break; 1962 case 's': // 18 strings to match. 1963 if (memcmp(Mnemonic.data()+2, "tr", 2) != 0) 1964 break; 1965 switch (Mnemonic[4]) { 1966 default: break; 1967 case 'd': // 6 strings to match. 1968 switch (Mnemonic[5]) { 1969 default: break; 1970 case 'e': // 3 strings to match. 1971 if (Mnemonic[6] != '.') 1972 break; 1973 switch (Mnemonic[7]) { 1974 default: break; 1975 case 'f': // 1 string to match. 1976 if (memcmp(Mnemonic.data()+8, "64", 2) != 0) 1977 break; 1978 Mnemonic = "vstrde.64"; // "vstrde.f64" 1979 return; 1980 case 's': // 1 string to match. 1981 if (memcmp(Mnemonic.data()+8, "64", 2) != 0) 1982 break; 1983 Mnemonic = "vstrde.64"; // "vstrde.s64" 1984 return; 1985 case 'u': // 1 string to match. 1986 if (memcmp(Mnemonic.data()+8, "64", 2) != 0) 1987 break; 1988 Mnemonic = "vstrde.64"; // "vstrde.u64" 1989 return; 1990 } 1991 break; 1992 case 't': // 3 strings to match. 1993 if (Mnemonic[6] != '.') 1994 break; 1995 switch (Mnemonic[7]) { 1996 default: break; 1997 case 'f': // 1 string to match. 1998 if (memcmp(Mnemonic.data()+8, "64", 2) != 0) 1999 break; 2000 Mnemonic = "vstrdt.64"; // "vstrdt.f64" 2001 return; 2002 case 's': // 1 string to match. 2003 if (memcmp(Mnemonic.data()+8, "64", 2) != 0) 2004 break; 2005 Mnemonic = "vstrdt.64"; // "vstrdt.s64" 2006 return; 2007 case 'u': // 1 string to match. 2008 if (memcmp(Mnemonic.data()+8, "64", 2) != 0) 2009 break; 2010 Mnemonic = "vstrdt.64"; // "vstrdt.u64" 2011 return; 2012 } 2013 break; 2014 } 2015 break; 2016 case 'h': // 6 strings to match. 2017 switch (Mnemonic[5]) { 2018 default: break; 2019 case 'e': // 3 strings to match. 2020 if (Mnemonic[6] != '.') 2021 break; 2022 switch (Mnemonic[7]) { 2023 default: break; 2024 case 'f': // 1 string to match. 2025 if (memcmp(Mnemonic.data()+8, "16", 2) != 0) 2026 break; 2027 Mnemonic = "vstrhe.16"; // "vstrhe.f16" 2028 return; 2029 case 's': // 1 string to match. 2030 if (memcmp(Mnemonic.data()+8, "16", 2) != 0) 2031 break; 2032 Mnemonic = "vstrhe.16"; // "vstrhe.s16" 2033 return; 2034 case 'u': // 1 string to match. 2035 if (memcmp(Mnemonic.data()+8, "16", 2) != 0) 2036 break; 2037 Mnemonic = "vstrhe.16"; // "vstrhe.u16" 2038 return; 2039 } 2040 break; 2041 case 't': // 3 strings to match. 2042 if (Mnemonic[6] != '.') 2043 break; 2044 switch (Mnemonic[7]) { 2045 default: break; 2046 case 'f': // 1 string to match. 2047 if (memcmp(Mnemonic.data()+8, "16", 2) != 0) 2048 break; 2049 Mnemonic = "vstrht.16"; // "vstrht.f16" 2050 return; 2051 case 's': // 1 string to match. 2052 if (memcmp(Mnemonic.data()+8, "16", 2) != 0) 2053 break; 2054 Mnemonic = "vstrht.16"; // "vstrht.s16" 2055 return; 2056 case 'u': // 1 string to match. 2057 if (memcmp(Mnemonic.data()+8, "16", 2) != 0) 2058 break; 2059 Mnemonic = "vstrht.16"; // "vstrht.u16" 2060 return; 2061 } 2062 break; 2063 } 2064 break; 2065 case 'w': // 6 strings to match. 2066 switch (Mnemonic[5]) { 2067 default: break; 2068 case 'e': // 3 strings to match. 2069 if (Mnemonic[6] != '.') 2070 break; 2071 switch (Mnemonic[7]) { 2072 default: break; 2073 case 'f': // 1 string to match. 2074 if (memcmp(Mnemonic.data()+8, "32", 2) != 0) 2075 break; 2076 Mnemonic = "vstrwe.32"; // "vstrwe.f32" 2077 return; 2078 case 's': // 1 string to match. 2079 if (memcmp(Mnemonic.data()+8, "32", 2) != 0) 2080 break; 2081 Mnemonic = "vstrwe.32"; // "vstrwe.s32" 2082 return; 2083 case 'u': // 1 string to match. 2084 if (memcmp(Mnemonic.data()+8, "32", 2) != 0) 2085 break; 2086 Mnemonic = "vstrwe.32"; // "vstrwe.u32" 2087 return; 2088 } 2089 break; 2090 case 't': // 3 strings to match. 2091 if (Mnemonic[6] != '.') 2092 break; 2093 switch (Mnemonic[7]) { 2094 default: break; 2095 case 'f': // 1 string to match. 2096 if (memcmp(Mnemonic.data()+8, "32", 2) != 0) 2097 break; 2098 Mnemonic = "vstrwt.32"; // "vstrwt.f32" 2099 return; 2100 case 's': // 1 string to match. 2101 if (memcmp(Mnemonic.data()+8, "32", 2) != 0) 2102 break; 2103 Mnemonic = "vstrwt.32"; // "vstrwt.s32" 2104 return; 2105 case 'u': // 1 string to match. 2106 if (memcmp(Mnemonic.data()+8, "32", 2) != 0) 2107 break; 2108 Mnemonic = "vstrwt.32"; // "vstrwt.u32" 2109 return; 2110 } 2111 break; 2112 } 2113 break; 2114 } 2115 break; 2116 } 2117 break; 2118 case 11: // 2 strings to match. 2119 if (memcmp(Mnemonic.data()+0, "vrecpeq.", 8) != 0) 2120 break; 2121 switch (Mnemonic[8]) { 2122 default: break; 2123 case 'f': // 1 string to match. 2124 if (memcmp(Mnemonic.data()+9, "32", 2) != 0) 2125 break; 2126 if (Features.test(Feature_HasNEONBit)) // "vrecpeq.f32" 2127 Mnemonic = "vrecpe.f32"; 2128 return; 2129 case 'u': // 1 string to match. 2130 if (memcmp(Mnemonic.data()+9, "32", 2) != 0) 2131 break; 2132 if (Features.test(Feature_HasNEONBit)) // "vrecpeq.u32" 2133 Mnemonic = "vrecpe.u32"; 2134 return; 2135 } 2136 break; 2137 } 2138} 2139 2140enum { 2141 Tie0_1_1, 2142 Tie0_2_2, 2143 Tie0_2_4, 2144 Tie0_3_3, 2145 Tie0_4_4, 2146 Tie0_4_5, 2147 Tie1_1_1, 2148 Tie1_2_2, 2149 Tie1_3_3, 2150 Tie1_4_4, 2151 Tie2_4_4, 2152}; 2153 2154static const uint8_t TiedAsmOperandTable[][3] = { 2155 /* Tie0_1_1 */ { 0, 1, 1 }, 2156 /* Tie0_2_2 */ { 0, 2, 2 }, 2157 /* Tie0_2_4 */ { 0, 2, 4 }, 2158 /* Tie0_3_3 */ { 0, 3, 3 }, 2159 /* Tie0_4_4 */ { 0, 4, 4 }, 2160 /* Tie0_4_5 */ { 0, 4, 5 }, 2161 /* Tie1_1_1 */ { 1, 1, 1 }, 2162 /* Tie1_2_2 */ { 1, 2, 2 }, 2163 /* Tie1_3_3 */ { 1, 3, 3 }, 2164 /* Tie1_4_4 */ { 1, 4, 4 }, 2165 /* Tie2_4_4 */ { 2, 4, 4 }, 2166}; 2167 2168namespace { 2169enum OperatorConversionKind { 2170 CVT_Done, 2171 CVT_Reg, 2172 CVT_Tied, 2173 CVT_95_Reg, 2174 CVT_95_addCCOutOperands, 2175 CVT_95_addCondCodeOperands, 2176 CVT_95_addRegShiftedRegOperands, 2177 CVT_95_addModImmOperands, 2178 CVT_95_addModImmNotOperands, 2179 CVT_95_addRegShiftedImmOperands, 2180 CVT_95_addImmOperands, 2181 CVT_95_addT2SOImmNotOperands, 2182 CVT_95_addImm0_95_4095NegOperands, 2183 CVT_95_addImm0_95_508s4Operands, 2184 CVT_regSP, 2185 CVT_95_addImm0_95_508s4NegOperands, 2186 CVT_95_addT2SOImmNegOperands, 2187 CVT_95_addThumbModImmNeg8_95_255Operands, 2188 CVT_95_addModImmNegOperands, 2189 CVT_95_addImm0_95_1020s4Operands, 2190 CVT_95_addThumbModImmNeg1_95_7Operands, 2191 CVT_95_addUnsignedOffset_95_b8s2Operands, 2192 CVT_95_addAdrLabelOperands, 2193 CVT_imm_95_45, 2194 CVT_95_addARMBranchTargetOperands, 2195 CVT_cvtThumbBranches, 2196 CVT_95_addBitfieldOperands, 2197 CVT_95_addITCondCodeOperands, 2198 CVT_imm_95_0, 2199 CVT_95_addThumbBranchTargetOperands, 2200 CVT_imm_95_15, 2201 CVT_95_addCoprocNumOperands, 2202 CVT_95_addCoprocRegOperands, 2203 CVT_95_addITCondCodeInvOperands, 2204 CVT_imm_95_22, 2205 CVT_95_addRegListWithAPSROperands, 2206 CVT_95_addProcIFlagsOperands, 2207 CVT_imm_95_20, 2208 CVT_regZR, 2209 CVT_imm_95_12, 2210 CVT_95_addMemBarrierOptOperands, 2211 CVT_imm_95_16, 2212 CVT_95_addFPImmOperands, 2213 CVT_95_addDPRRegListOperands, 2214 CVT_imm_95_1, 2215 CVT_95_addInstSyncBarrierOptOperands, 2216 CVT_95_addITMaskOperands, 2217 CVT_95_addMemNoOffsetOperands, 2218 CVT_95_addAddrMode5Operands, 2219 CVT_95_addCoprocOptionOperands, 2220 CVT_95_addPostIdxImm8s4Operands, 2221 CVT_95_addRegListOperands, 2222 CVT_95_addThumbMemPCOperands, 2223 CVT_95_addConstPoolAsmImmOperands, 2224 CVT_95_addMemThumbRIs4Operands, 2225 CVT_95_addMemThumbRROperands, 2226 CVT_95_addMemThumbSPIOperands, 2227 CVT_95_addMemImm12OffsetOperands, 2228 CVT_95_addMemImmOffsetOperands, 2229 CVT_95_addMemRegOffsetOperands, 2230 CVT_95_addMemUImm12OffsetOperands, 2231 CVT_95_addT2MemRegOffsetOperands, 2232 CVT_95_addMemPCRelImm12Operands, 2233 CVT_95_addAM2OffsetImmOperands, 2234 CVT_95_addPostIdxRegShiftedOperands, 2235 CVT_95_addMemThumbRIs1Operands, 2236 CVT_95_addMemImm8s4OffsetOperands, 2237 CVT_95_addAddrMode3Operands, 2238 CVT_95_addAM3OffsetOperands, 2239 CVT_95_addMemImm0_95_1020s4OffsetOperands, 2240 CVT_95_addMemThumbRIs2Operands, 2241 CVT_95_addPostIdxRegOperands, 2242 CVT_95_addPostIdxImm8Operands, 2243 CVT_reg0, 2244 CVT_regCPSR, 2245 CVT_imm_95_14, 2246 CVT_95_addBankedRegOperands, 2247 CVT_95_addMSRMaskOperands, 2248 CVT_cvtThumbMultiply, 2249 CVT_regR8, 2250 CVT_regR0, 2251 CVT_imm_95_29, 2252 CVT_imm_95_13, 2253 CVT_95_addPKHASRImmOperands, 2254 CVT_imm_95_4, 2255 CVT_95_addImm1_95_32Operands, 2256 CVT_imm_95_5, 2257 CVT_95_addMveSaturateOperands, 2258 CVT_95_addShifterImmOperands, 2259 CVT_95_addImm1_95_16Operands, 2260 CVT_95_addRotImmOperands, 2261 CVT_95_addMemTBBOperands, 2262 CVT_95_addMemTBHOperands, 2263 CVT_95_addTraceSyncBarrierOptOperands, 2264 CVT_95_addVPTPredNOperands, 2265 CVT_95_addVPTPredROperands, 2266 CVT_95_addNEONi16splatNotOperands, 2267 CVT_95_addNEONi32splatNotOperands, 2268 CVT_95_addNEONi16splatOperands, 2269 CVT_95_addNEONi32splatOperands, 2270 CVT_95_addComplexRotationOddOperands, 2271 CVT_95_addComplexRotationEvenOperands, 2272 CVT_95_addVectorIndex64Operands, 2273 CVT_95_addVectorIndex32Operands, 2274 CVT_95_addFBits16Operands, 2275 CVT_95_addFBits32Operands, 2276 CVT_95_addPowerTwoOperands, 2277 CVT_95_addVectorIndex16Operands, 2278 CVT_95_addVectorIndex8Operands, 2279 CVT_95_addVecListOperands, 2280 CVT_95_addDupAlignedMemory16Operands, 2281 CVT_95_addAlignedMemory64or128Operands, 2282 CVT_95_addAlignedMemory64or128or256Operands, 2283 CVT_95_addAlignedMemory64Operands, 2284 CVT_95_addVecListIndexedOperands, 2285 CVT_95_addAlignedMemory16Operands, 2286 CVT_95_addDupAlignedMemory32Operands, 2287 CVT_95_addAlignedMemory32Operands, 2288 CVT_95_addDupAlignedMemoryNoneOperands, 2289 CVT_95_addAlignedMemoryNoneOperands, 2290 CVT_95_addAlignedMemoryOperands, 2291 CVT_95_addDupAlignedMemory64Operands, 2292 CVT_95_addMVEVecListOperands, 2293 CVT_95_addMemNoOffsetT2Operands, 2294 CVT_95_addMemNoOffsetT2NoSpOperands, 2295 CVT_95_addDupAlignedMemory64or128Operands, 2296 CVT_95_addSPRRegListOperands, 2297 CVT_95_addMemImm7s4OffsetOperands, 2298 CVT_95_addAddrMode5FP16Operands, 2299 CVT_95_addImm7s4Operands, 2300 CVT_95_addMemRegRQOffsetOperands, 2301 CVT_95_addMemNoOffsetTOperands, 2302 CVT_95_addImm7Shift0Operands, 2303 CVT_95_addImm7Shift1Operands, 2304 CVT_95_addImm7Shift2Operands, 2305 CVT_95_addNEONi32vmovOperands, 2306 CVT_95_addNEONvmovi8ReplicateOperands, 2307 CVT_95_addNEONvmovi16ReplicateOperands, 2308 CVT_95_addNEONi32vmovNegOperands, 2309 CVT_95_addNEONvmovi32ReplicateOperands, 2310 CVT_95_addNEONi64splatOperands, 2311 CVT_95_addNEONi8splatOperands, 2312 CVT_95_addMVEVectorIndexOperands, 2313 CVT_95_addMVEPairVectorIndexOperands, 2314 CVT_cvtMVEVMOVQtoDReg, 2315 CVT_95_addNEONinvi8ReplicateOperands, 2316 CVT_95_addFPDRegListWithVPROperands, 2317 CVT_95_addFPSRegListWithVPROperands, 2318 CVT_imm_95_2, 2319 CVT_imm_95_3, 2320 CVT_NUM_CONVERTERS 2321}; 2322 2323enum InstructionConversionKind { 2324 Convert_NoOperands, 2325 Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, 2326 Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, 2327 Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, 2328 Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, 2329 Convert__Reg1_2__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0, 2330 Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, 2331 Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, 2332 Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, 2333 Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, 2334 Convert__Reg1_2__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0, 2335 Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, 2336 Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, 2337 Convert__Reg1_2__Reg1_3__ModImmNot1_4__CondCode2_1__CCOut1_0, 2338 Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, 2339 Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, 2340 Convert__Reg1_1__Tie0_1_1__Reg1_2__CondCode2_0, 2341 Convert__Reg1_1__Reg1_1__Imm0_40951_2__CondCode2_0, 2342 Convert__Reg1_1__Reg1_1__Imm0_4095Neg1_2__CondCode2_0, 2343 Convert__Reg1_1__Tie0_1_1__Imm0_508s41_2__CondCode2_0, 2344 Convert__regSP__Tie0_1_1__Imm0_508s4Neg1_2__CondCode2_0, 2345 Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, 2346 Convert__Reg1_2__Reg1_2__T2SOImmNeg1_3__CondCode2_1__CCOut1_0, 2347 Convert__Reg1_2__CCOut1_0__Reg1_2__Reg1_3__CondCode2_1, 2348 Convert__Reg1_2__CCOut1_0__Tie0_1_1__Imm0_2551_3__CondCode2_1, 2349 Convert__Reg1_2__CCOut1_0__Tie0_3_3__ThumbModImmNeg8_2551_3__CondCode2_1, 2350 Convert__Reg1_2__Reg1_2__ModImmNeg1_3__CondCode2_1__CCOut1_0, 2351 Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0, 2352 Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0, 2353 Convert__regSP__Tie0_1_1__Imm0_508s41_3__CondCode2_0, 2354 Convert__regSP__Tie0_1_1__Imm0_508s4Neg1_3__CondCode2_0, 2355 Convert__Reg1_1__Reg1_2__Imm0_1020s41_3__CondCode2_0, 2356 Convert__Reg1_1__Imm0_40951_3__CondCode2_0, 2357 Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, 2358 Convert__Reg1_3__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, 2359 Convert__Reg1_3__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0, 2360 Convert__Reg1_2__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0, 2361 Convert__Reg1_2__CCOut1_0__Reg1_3__Reg1_4__CondCode2_1, 2362 Convert__Reg1_2__CCOut1_0__Reg1_3__Imm0_71_4__CondCode2_1, 2363 Convert__Reg1_2__CCOut1_0__Reg1_3__ThumbModImmNeg1_71_4__CondCode2_1, 2364 Convert__Reg1_2__Reg1_3__ModImmNeg1_4__CondCode2_1__CCOut1_0, 2365 Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, 2366 Convert__Reg1_3__Reg1_4__T2SOImmNeg1_5__CondCode2_1__CCOut1_0, 2367 Convert__Reg1_1__UnsignedOffset_b8s21_2__CondCode2_0, 2368 Convert__Reg1_1__Imm1_2__CondCode2_0, 2369 Convert__Reg1_1__AdrLabel1_2__CondCode2_0, 2370 Convert__Reg1_2__Imm1_3__CondCode2_0, 2371 Convert__Reg1_1__Tie0_1_1__Reg1_2, 2372 Convert__Reg1_1__Reg1_2, 2373 Convert__Reg1_2__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0, 2374 Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, 2375 Convert__Reg1_3__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, 2376 Convert__Reg1_3__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0, 2377 Convert__Reg1_3__Reg1_4__T2SOImmNot1_5__CondCode2_1__CCOut1_0, 2378 Convert__Reg1_2__CCOut1_0__Reg1_2__ImmThumbSR1_3__CondCode2_1, 2379 Convert__Reg1_2__Reg1_2__ImmThumbSR1_3__CondCode2_1__CCOut1_0, 2380 Convert__Reg1_2__Reg1_2__Imm0_321_3__CondCode2_1__CCOut1_0, 2381 Convert__Reg1_3__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0, 2382 Convert__Reg1_2__CCOut1_0__Reg1_3__ImmThumbSR1_4__CondCode2_1, 2383 Convert__Reg1_2__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0, 2384 Convert__Reg1_2__Reg1_3__Imm0_321_4__CondCode2_1__CCOut1_0, 2385 Convert__Reg1_3__Reg1_4__ImmThumbSR1_5__CondCode2_1__CCOut1_0, 2386 Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__Reg1_3__CondCode2_0, 2387 Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__MVELongShift1_3__CondCode2_0, 2388 Convert__imm_95_45__CondCode2_0, 2389 Convert__CondCode2_0__Reg1_1__Reg1_2__Reg1_3, 2390 Convert__ARMBranchTarget1_1__CondCode2_0, 2391 ConvertCustom_cvtThumbBranches, 2392 Convert__Imm1_1__Imm1_2__CondCode2_0, 2393 Convert__Reg1_1__Tie0_1_1__Bitfield1_2__CondCode2_0, 2394 Convert__Imm1_0__Imm1_1__Imm1_2__CondCodeNoAL1_3, 2395 Convert__Reg1_1__Tie0_1_1__Reg1_2__Bitfield1_3__CondCode2_0, 2396 Convert__Imm1_1__Reg1_2__CondCode2_0, 2397 Convert__imm_95_0, 2398 Convert__Imm0_2551_0, 2399 Convert__Imm0_655351_0, 2400 Convert__ARMBranchTarget1_0, 2401 Convert__CondCode2_0__ThumbBranchTarget1_1, 2402 Convert__CondCode2_0__ThumbBranchTarget1_2, 2403 Convert__Reg1_0, 2404 Convert__ThumbBranchTarget1_0, 2405 Convert__Reg1_1__CondCode2_0, 2406 Convert__CondCode2_0__Reg1_1, 2407 Convert__CondCode2_0__ARMBranchTarget1_1, 2408 Convert__imm_95_15__CondCode2_0, 2409 Convert__CondCode2_0, 2410 Convert__Reg1_0__ThumbBranchTarget1_1, 2411 Convert__CoprocNum1_1__Imm0_151_2__CoprocReg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, 2412 Convert__CoprocNum1_0__Imm0_151_1__CoprocReg1_2__CoprocReg1_3__CoprocReg1_4__Imm0_71_5, 2413 Convert__Reg1_0__Reg1_1__Reg1_1__CondCodeNoALInv1_2, 2414 Convert__imm_95_22__CondCode2_0, 2415 Convert__CondCode2_0__RegListWithAPSR1_1, 2416 Convert__Reg1_1__Reg1_2__CondCode2_0, 2417 Convert__Reg1_1__ModImmNeg1_2__CondCode2_0, 2418 Convert__Reg1_1__T2SOImmNeg1_2__CondCode2_0, 2419 Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, 2420 Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0, 2421 Convert__Reg1_1__T2SOImm1_2__CondCode2_0, 2422 Convert__Reg1_1__ModImm1_2__CondCode2_0, 2423 Convert__Reg1_2__Reg1_3__CondCode2_0, 2424 Convert__Reg1_2__RegShiftedImm2_3__CondCode2_0, 2425 Convert__Reg1_2__T2SOImm1_3__CondCode2_0, 2426 Convert__Reg1_1__Imm0_2551_2__CondCode2_0, 2427 Convert__Imm0_311_0, 2428 Convert__Imm0_311_1, 2429 Convert__Imm1_0__ProcIFlags1_1, 2430 Convert__Imm1_0__ProcIFlags1_2, 2431 Convert__Imm1_0__ProcIFlags1_1__Imm0_311_2, 2432 Convert__Imm1_0__ProcIFlags1_1__Imm1_2, 2433 Convert__Imm1_0__ProcIFlags1_2__Imm1_3, 2434 Convert__Reg1_0__Reg1_1__Reg1_2, 2435 Convert__imm_95_20__CondCode2_0, 2436 Convert__Reg1_0__Reg1_1__Reg1_2__CondCodeNoAL1_3, 2437 Convert__Reg1_0__regZR__regZR__CondCodeNoALInv1_1, 2438 Convert__Reg1_1__CoprocNum1_0__Imm13b1_2, 2439 Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Imm13b1_3__CondCode2_0, 2440 Convert__Reg1_1__CoprocNum1_0__Reg1_2__Imm9b1_3, 2441 Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Reg1_3__Imm9b1_4__CondCode2_0, 2442 Convert__Reg1_1__CoprocNum1_0__Reg1_2__Reg1_3__Imm6b1_4, 2443 Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Reg1_3__Reg1_4__Imm6b1_5__CondCode2_0, 2444 Convert__Imm0_151_1__CondCode2_0, 2445 Convert__Imm0_151_2__CondCode2_0, 2446 Convert__imm_95_12, 2447 Convert__imm_95_12__CondCode2_0, 2448 Convert__Reg1_0__Reg1_1, 2449 Convert__imm_95_15, 2450 Convert__MemBarrierOpt1_0, 2451 Convert__MemBarrierOpt1_1__CondCode2_0, 2452 Convert__MemBarrierOpt1_2__CondCode2_0, 2453 Convert__imm_95_0__CondCode2_0, 2454 Convert__imm_95_16__CondCode2_0, 2455 Convert__Reg1_1__FPImm1_2__CondCode2_0, 2456 Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3, 2457 Convert__Reg1_1__CondCode2_0__DPRRegList1_2, 2458 Convert__Reg1_1__Tie0_2_2__Reg1_2__imm_95_1__CondCode2_0, 2459 Convert__Reg1_1__Tie0_2_2__Reg1_2__imm_95_0__CondCode2_0, 2460 Convert__Imm0_2391_1__CondCode2_0, 2461 Convert__Imm0_2391_2__CondCode2_0, 2462 Convert__Imm0_631_0, 2463 Convert__Imm0_655351_1, 2464 Convert__InstSyncBarrierOpt1_0, 2465 Convert__InstSyncBarrierOpt1_1__CondCode2_0, 2466 Convert__ITCondCode1_1__ITMask1_0, 2467 Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, 2468 Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, 2469 Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, 2470 Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, 2471 Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, 2472 Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, 2473 Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__CoprocOption1_3, 2474 Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__PostIdxImm8s41_3, 2475 Convert__Reg1_1__CondCode2_0__RegList1_2, 2476 Convert__Reg1_2__CondCode2_0__RegList1_3, 2477 Convert__Reg1_1__CondCode2_0__RegList1_3, 2478 Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, 2479 Convert__Reg1_2__Tie0_3_3__CondCode2_0__RegList1_4, 2480 Convert__Reg1_1__ThumbMemPC1_2__CondCode2_0, 2481 Convert__Reg1_1__ConstPoolAsmImm1_2__CondCode2_0, 2482 Convert__Reg1_1__MemThumbRIs42_2__CondCode2_0, 2483 Convert__Reg1_1__MemThumbRR2_2__CondCode2_0, 2484 Convert__Reg1_1__MemThumbSPI2_2__CondCode2_0, 2485 Convert__Reg1_1__MemImm12Offset2_2__CondCode2_0, 2486 Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0, 2487 Convert__Reg1_1__MemRegOffset3_2__CondCode2_0, 2488 Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0, 2489 Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0, 2490 Convert__Reg1_1__MemPCRelImm121_2__CondCode2_0, 2491 Convert__Reg1_2__ConstPoolAsmImm1_3__CondCode2_0, 2492 Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0, 2493 Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0, 2494 Convert__Reg1_2__MemPCRelImm121_3__CondCode2_0, 2495 Convert__Reg1_1__imm_95_0__MemImm12Offset2_2__CondCode2_0, 2496 Convert__Reg1_1__imm_95_0__MemImm8Offset2_2__CondCode2_0, 2497 Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM2OffsetImm2_3__CondCode2_0, 2498 Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__Imm1_3__CondCode2_0, 2499 Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxRegShifted2_3__CondCode2_0, 2500 Convert__Reg1_1__imm_95_0__MemRegOffset3_2__CondCode2_0, 2501 Convert__Reg1_2__MemImm8Offset2_3__CondCode2_0, 2502 Convert__Reg1_2__MemNoOffset1_3__Imm1_4__CondCode2_0, 2503 Convert__Reg1_1__MemThumbRIs12_2__CondCode2_0, 2504 Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0, 2505 Convert__Reg1_1__Reg1_2__MemImm8s4Offset2_3__CondCode2_0, 2506 Convert__Reg1_1__Reg1_2__AddrMode33_3__CondCode2_0, 2507 Convert__Reg1_1__Reg1_2__imm_95_0__MemImm8s4Offset2_3__CondCode2_0, 2508 Convert__Reg1_1__Reg1_2__MemNoOffset1_3__Tie2_4_4__Imm1_4__CondCode2_0, 2509 Convert__Reg1_1__Reg1_2__imm_95_0__AddrMode33_3__CondCode2_0, 2510 Convert__Reg1_1__Reg1_2__MemNoOffset1_3__Tie2_4_4__AM3Offset2_4__CondCode2_0, 2511 Convert__Reg1_1__MemImm0_1020s4Offset2_2__CondCode2_0, 2512 Convert__Reg1_1__MemThumbRIs22_2__CondCode2_0, 2513 Convert__Reg1_1__AddrMode33_2__CondCode2_0, 2514 Convert__Reg1_1__imm_95_0__AddrMode33_2__CondCode2_0, 2515 Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM3Offset2_3__CondCode2_0, 2516 Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxReg2_3__CondCode2_0, 2517 Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxImm81_3__CondCode2_0, 2518 Convert__LELabel1_0, 2519 Convert__imm_95_0__Reg1_0__LELabel1_1, 2520 Convert__Reg1_2__CCOut1_0__Reg1_2__Imm0_311_3__CondCode2_1, 2521 Convert__Reg1_2__Reg1_2__Imm1_311_3__CondCode2_1__CCOut1_0, 2522 Convert__Reg1_2__Reg1_2__Imm0_311_3__CondCode2_1__CCOut1_0, 2523 Convert__Reg1_3__Reg1_3__Imm1_311_4__CondCode2_1__CCOut1_0, 2524 Convert__Reg1_2__CCOut1_0__Reg1_3__Imm0_311_4__CondCode2_1, 2525 Convert__Reg1_2__Reg1_3__Imm1_311_4__CondCode2_1__CCOut1_0, 2526 Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, 2527 Convert__Reg1_2__Reg1_3__Imm0_311_4__CondCode2_1__CCOut1_0, 2528 Convert__Reg1_3__Reg1_4__Imm1_311_5__CondCode2_1__CCOut1_0, 2529 Convert__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, 2530 Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0, 2531 Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, 2532 Convert__CoprocNum1_0__Imm0_71_1__Reg1_2__CoprocReg1_3__CoprocReg1_4__imm_95_0, 2533 Convert__CoprocNum1_0__Imm0_71_1__Reg1_2__CoprocReg1_3__CoprocReg1_4__Imm0_71_5, 2534 Convert__CoprocNum1_1__Imm0_151_2__Reg1_3__Reg1_4__CoprocReg1_5__CondCode2_0, 2535 Convert__CoprocNum1_0__Imm0_151_1__Reg1_2__Reg1_3__CoprocReg1_4, 2536 Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, 2537 Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, 2538 Convert__Reg1_1__Imm256_65535Expr1_2__CondCode2_0, 2539 Convert__Reg1_1__T2SOImm1_2__CondCode2_0__reg0, 2540 Convert__Reg1_1__T2SOImmNot1_2__CondCode2_0__reg0, 2541 Convert__Reg1_1__Imm0_65535Expr1_2__CondCode2_0, 2542 Convert__Reg1_2__CCOut1_0__Imm0_2551_3__CondCode2_1, 2543 Convert__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0, 2544 Convert__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, 2545 Convert__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, 2546 Convert__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, 2547 Convert__Reg1_2__RegShiftedReg3_3__CondCode2_0, 2548 Convert__Reg1_2__T2SOImm1_3__CondCode2_0__reg0, 2549 Convert__Reg1_2__Reg1_3__CondCode2_0__reg0, 2550 Convert__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, 2551 Convert__Reg1_0__regCPSR__Imm0_2551_1__imm_95_14__imm_95_0, 2552 Convert__Reg1_1__T2SOImm1_2__CondCode2_0__regCPSR, 2553 Convert__Reg1_1__Reg1_2__CondCode2_0__regCPSR, 2554 Convert__Reg1_2__T2SOImm1_3__CondCode2_0__regCPSR, 2555 Convert__Reg1_2__Reg1_3__CondCode2_0__regCPSR, 2556 Convert__Reg1_1__Tie0_1_1__Imm0_65535Expr1_2__CondCode2_0, 2557 Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0, 2558 Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, 2559 Convert__Reg1_2__CoprocNum1_0__Imm0_71_1__CoprocReg1_3__CoprocReg1_4__imm_95_0, 2560 Convert__Reg1_2__CoprocNum1_0__Imm0_71_1__CoprocReg1_3__CoprocReg1_4__Imm0_71_5, 2561 Convert__Reg1_3__Reg1_4__CoprocNum1_1__Imm0_151_2__CoprocReg1_5__CondCode2_0, 2562 Convert__Reg1_2__Reg1_3__CoprocNum1_0__Imm0_151_1__CoprocReg1_4, 2563 Convert__Reg1_1__BankedReg1_2__CondCode2_0, 2564 Convert__Reg1_1__MSRMask1_2__CondCode2_0, 2565 Convert__BankedReg1_1__Reg1_2__CondCode2_0, 2566 Convert__MSRMask1_1__Reg1_2__CondCode2_0, 2567 Convert__MSRMask1_1__ModImm1_2__CondCode2_0, 2568 Convert__Reg1_1__Reg1_2__Reg1_1__CondCode2_0, 2569 ConvertCustom_cvtThumbMultiply, 2570 Convert__Reg1_2__CCOut1_0__Reg1_3__CondCode2_1, 2571 Convert__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, 2572 Convert__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0, 2573 Convert__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, 2574 Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_1__CCOut1_0, 2575 Convert__regR8__regR8__imm_95_14__imm_95_0, 2576 Convert__regR0__regR0__CondCode2_0__reg0, 2577 Convert__imm_95_29__CondCode2_0, 2578 Convert__imm_95_13__CondCode2_0, 2579 Convert__Reg1_1__CondCode2_0__Reg1_2__Reg1_3, 2580 Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, 2581 Convert__Reg1_1__Reg1_2__Reg1_3__PKHLSLImm1_4__CondCode2_0, 2582 Convert__Reg1_1__Reg1_3__Reg1_2__imm_95_0__CondCode2_0, 2583 Convert__Reg1_1__Reg1_2__Reg1_3__PKHASRImm1_4__CondCode2_0, 2584 Convert__MemImm12Offset2_0, 2585 Convert__MemRegOffset3_0, 2586 Convert__Imm1_1__CondCode2_0, 2587 Convert__MemNegImm8Offset2_1__CondCode2_0, 2588 Convert__MemUImm12Offset2_1__CondCode2_0, 2589 Convert__T2MemRegOffset3_1__CondCode2_0, 2590 Convert__MemPCRelImm121_1__CondCode2_0, 2591 Convert__Imm1_2__CondCode2_0, 2592 Convert__MemNegImm8Offset2_2__CondCode2_0, 2593 Convert__MemUImm12Offset2_2__CondCode2_0, 2594 Convert__T2MemRegOffset3_2__CondCode2_0, 2595 Convert__MemPCRelImm121_2__CondCode2_0, 2596 Convert__CondCode2_0__RegList1_1, 2597 Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_1, 2598 Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_2, 2599 Convert__imm_95_4__imm_95_14__imm_95_0, 2600 Convert__imm_95_4, 2601 Convert__Reg1_1__Reg1_2__Imm0_311_3__Imm1_321_4__CondCode2_0, 2602 Convert__SetEndImm1_0, 2603 Convert__Imm0_11_0, 2604 Convert__imm_95_4__CondCode2_0, 2605 Convert__imm_95_5__CondCode2_0, 2606 Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3, 2607 Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, 2608 Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0_1_1__Tie1_1_1__CondCode2_1__CCOut1_0, 2609 Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0_3_3__Tie1_4_4__CondCode2_1__CCOut1_0, 2610 Convert__Reg1_1__Tie0_2_2__Reg1_2__CondCode2_0, 2611 Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__Reg1_4__MveSaturate1_3__CondCode2_0, 2612 Convert__Reg1_1__Tie0_2_2__MVELongShift1_2__CondCode2_0, 2613 Convert__Imm0_311_2, 2614 Convert__Imm0_311_1__CondCode2_0, 2615 Convert__Imm0_311_2__CondCode2_0, 2616 Convert__Imm0_311_3__CondCode2_0, 2617 Convert__Reg1_1__Imm1_321_2__Reg1_3__imm_95_0__CondCode2_0, 2618 Convert__Reg1_1__Imm1_321_2__Reg1_3__ShifterImm1_4__CondCode2_0, 2619 Convert__Reg1_1__Imm1_161_2__Reg1_3__CondCode2_0, 2620 Convert__imm_95_0__imm_95_14__imm_95_0, 2621 Convert__Reg1_1__Reg1_2__Reg1_3__MemNoOffset1_4__CondCode2_0, 2622 Convert__imm_95_0__Reg1_1__MemImm8Offset2_2__CondCode2_0, 2623 Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__Imm1_3__CondCode2_0, 2624 Convert__imm_95_0__Reg1_1__MemImm12Offset2_2__CondCode2_0, 2625 Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM2OffsetImm2_3__CondCode2_0, 2626 Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxRegShifted2_3__CondCode2_0, 2627 Convert__imm_95_0__Reg1_1__MemRegOffset3_2__CondCode2_0, 2628 Convert__imm_95_0__Reg1_1__Reg1_2__MemImm8s4Offset2_3__CondCode2_0, 2629 Convert__MemNoOffset1_3__Reg1_1__Reg1_2__Tie0_4_4__Imm1_4__CondCode2_0, 2630 Convert__imm_95_0__Reg1_1__Reg1_2__AddrMode33_3__CondCode2_0, 2631 Convert__MemNoOffset1_3__Reg1_1__Reg1_2__Tie0_4_4__AM3Offset2_4__CondCode2_0, 2632 Convert__Reg1_1__Reg1_2__MemImm0_1020s4Offset2_3__CondCode2_0, 2633 Convert__imm_95_0__Reg1_1__AddrMode33_2__CondCode2_0, 2634 Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM3Offset2_3__CondCode2_0, 2635 Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxImm81_3__CondCode2_0, 2636 Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxReg2_3__CondCode2_0, 2637 Convert__Imm0_2551_3__CondCode2_0, 2638 Convert__Imm0_2551_1__CondCode2_0, 2639 Convert__Imm24bit1_1__CondCode2_0, 2640 Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, 2641 Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, 2642 Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, 2643 Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, 2644 Convert__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, 2645 Convert__MemTBB2_1__CondCode2_0, 2646 Convert__MemTBH2_1__CondCode2_0, 2647 Convert__TraceSyncBarrierOpt1_0, 2648 Convert__TraceSyncBarrierOpt1_1__CondCode2_0, 2649 Convert__Reg1_1__Imm0_311_2__Reg1_3__imm_95_0__CondCode2_0, 2650 Convert__Reg1_1__Imm0_311_2__Reg1_3__ShifterImm1_4__CondCode2_0, 2651 Convert__Reg1_1__Imm0_151_2__Reg1_3__CondCode2_0, 2652 Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, 2653 Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, 2654 Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, 2655 Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, 2656 Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, 2657 Convert__Reg1_2__Reg1_3__VPTPredR4_0, 2658 Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0, 2659 Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, 2660 Convert__Reg1_2__imm_95_0__Reg1_3__Reg1_4__imm_95_0__VPTPredR4_0, 2661 Convert__Reg1_2__imm_95_0__Reg1_3__Reg1_4__VPTPredR4_0, 2662 Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, 2663 Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__VPTPredN3_0, 2664 Convert__Reg1_2__Reg1_3__VPTPredN3_0, 2665 Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, 2666 Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, 2667 Convert__Reg1_2__NEONi16splatNot1_3__Tie0_3_3__CondCode2_0, 2668 Convert__Reg1_2__NEONi32splatNot1_3__Tie0_3_3__CondCode2_0, 2669 Convert__Reg1_2__Tie0_3_3__NEONi16splatNot1_3__VPTPredN3_0, 2670 Convert__Reg1_2__Tie0_3_3__NEONi32splatNot1_3__VPTPredN3_0, 2671 Convert__Reg1_1__Reg1_2__Reg1_3__VPTPredR4_0, 2672 Convert__Reg1_2__NEONi16splat1_3__Tie0_1_1__CondCode2_0, 2673 Convert__Reg1_2__NEONi32splat1_3__Tie0_1_1__CondCode2_0, 2674 Convert__Reg1_2__Tie0_1_1__NEONi16splat1_3__VPTPredN3_0, 2675 Convert__Reg1_2__Tie0_1_1__NEONi32splat1_3__VPTPredN3_0, 2676 Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__CondCode2_0, 2677 Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, 2678 Convert__Reg1_1__Reg1_2__Reg1_3__ComplexRotationOdd1_4, 2679 Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationOdd1_5__VPTPredR4_0, 2680 Convert__Reg1_2__Reg1_2__CondCode2_0, 2681 Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__ComplexRotationEven1_4, 2682 Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__VectorIndex641_4__ComplexRotationEven1_5, 2683 Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__VectorIndex321_4__ComplexRotationEven1_5, 2684 Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__ComplexRotationEven1_5__VPTPredN3_0, 2685 Convert__Reg1_2__CondCode2_0, 2686 Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2__VPTPredN3_0, 2687 Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2__VPTPredN3_0, 2688 Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedFP1_2__VPTPredN3_0, 2689 Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2__VPTPredN3_0, 2690 Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationEven1_5__VPTPredR4_0, 2691 Convert__imm_95_0__Reg1_2__VPTPredN3_0, 2692 Convert__Reg1_3__Reg1_4__CondCode2_0, 2693 Convert__Reg1_3__Reg1_4__VPTPredR4_0, 2694 Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, 2695 Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, 2696 Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, 2697 Convert__Reg1_3__Reg1_4__MVEVcvtImm161_5__VPTPredR4_0, 2698 Convert__Reg1_3__Reg1_4__MVEVcvtImm321_5__VPTPredR4_0, 2699 Convert__Reg1_2__Reg1_3, 2700 Convert__Reg1_3__Tie0_1_1__Reg1_4__CondCode2_0, 2701 Convert__Reg1_3__Tie0_1_1__Reg1_4__VPTPredN3_0, 2702 Convert__Reg1_1__CoprocNum1_0__Imm11b1_2, 2703 Convert__Reg1_2__CoprocNum1_1__Imm12b1_3__VPTPredR4_0, 2704 Convert__Reg1_1__CoprocNum1_0__Tie0_1_1__Imm11b1_2, 2705 Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Imm12b1_3__VPTPredN3_0, 2706 Convert__Reg1_1__CoprocNum1_0__Reg1_2__Imm6b1_3, 2707 Convert__Reg1_2__CoprocNum1_1__Reg1_3__Imm7b1_4__VPTPredR4_0, 2708 Convert__Reg1_1__CoprocNum1_0__Tie0_1_1__Reg1_2__Imm6b1_3, 2709 Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Reg1_3__Imm7b1_4__VPTPredN3_0, 2710 Convert__Reg1_1__CoprocNum1_0__Reg1_2__Reg1_3__Imm3b1_4, 2711 Convert__Reg1_2__CoprocNum1_1__Reg1_3__Reg1_4__Imm4b1_5__VPTPredR4_0, 2712 Convert__Reg1_1__CoprocNum1_0__Tie0_1_1__Reg1_2__Reg1_3__Imm3b1_4, 2713 Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Reg1_3__Reg1_4__Imm4b1_5__VPTPredN3_0, 2714 Convert__Reg1_2__Reg1_3__Tie1_1_1__VIDUP_imm1_4__VPTPredR4_0, 2715 Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, 2716 Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4, 2717 Convert__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0, 2718 Convert__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0, 2719 Convert__Reg1_2__Reg1_3__VectorIndex81_4__CondCode2_0, 2720 Convert__Reg1_2__Reg1_3__Tie1_1_1__Reg1_4__VIDUP_imm1_5__VPTPredR4_0, 2721 Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_71_4__CondCode2_0, 2722 Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_31_4__CondCode2_0, 2723 Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_11_4__CondCode2_0, 2724 Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_151_4__CondCode2_0, 2725 Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_71_5__CondCode2_0, 2726 Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_31_5__CondCode2_0, 2727 Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_11_5__CondCode2_0, 2728 Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_151_5__CondCode2_0, 2729 Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex161_4, 2730 Convert__Reg1_1__Reg1_2__Reg1_3, 2731 Convert__Reg1_1__Reg1_2__Reg1_3__VectorIndex161_4, 2732 Convert__Reg1_1__Reg1_2__Reg1_3__VectorIndex321_4, 2733 Convert__VecListDPairAllLanes1_2__DupAlignedMemory162_3__CondCode2_0, 2734 Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0, 2735 Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, 2736 Convert__VecListOneDAllLanes1_2__DupAlignedMemory162_3__CondCode2_0, 2737 Convert__VecListOneD1_2__AlignedMemory642_3__CondCode2_0, 2738 Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__CondCode2_0, 2739 Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, 2740 Convert__VecListDPairAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, 2741 Convert__VecListOneDAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, 2742 Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__CondCode2_0, 2743 Convert__VecListDPairAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, 2744 Convert__VecListOneDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, 2745 Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, 2746 Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0, 2747 Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0, 2748 Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, 2749 Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, 2750 Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0, 2751 Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, 2752 Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0, 2753 Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0, 2754 Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, 2755 Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0, 2756 Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__Reg1_4__CondCode2_0, 2757 Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, 2758 Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0, 2759 Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0, 2760 Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0, 2761 Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0, 2762 Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0, 2763 Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0, 2764 Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__CondCode2_0, 2765 Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, 2766 Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__CondCode2_0, 2767 Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, 2768 Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, 2769 Convert__Reg1_3__AlignedMemory2_8__Tie0_1_1__Imm1_5__CondCode2_0, 2770 Convert__Reg1_3__imm_95_0__AlignedMemory2_8__Imm1_9__Tie0_1_1__Imm1_5__CondCode2_0, 2771 Convert__Reg1_3__Reg1_8__Imm1_9__Tie0_1_1__Imm1_5__CondCode2_0, 2772 Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, 2773 Convert__VecListDPairSpaced1_2__AlignedMemory64or1282_3__CondCode2_0, 2774 Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__CondCode2_0, 2775 Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__CondCode2_0, 2776 Convert__VecListDPairAllLanes1_2__DupAlignedMemory642_3__CondCode2_0, 2777 Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory642_3__CondCode2_0, 2778 Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__CondCode2_0, 2779 Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__CondCode2_0, 2780 Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory162_3__CondCode2_0, 2781 Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__CondCode2_0, 2782 Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0, 2783 Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0, 2784 Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, 2785 Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, 2786 Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0, 2787 Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0, 2788 Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory642_3__CondCode2_0, 2789 Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory642_3__Reg1_4__CondCode2_0, 2790 Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory642_3__CondCode2_0, 2791 Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory642_3__Reg1_4__CondCode2_0, 2792 Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0, 2793 Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0, 2794 Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0, 2795 Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0, 2796 Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__Reg1_4__CondCode2_0, 2797 Convert__VecListTwoMQ1_1__Tie0_1_1__MemNoOffsetT21_2, 2798 Convert__VecListTwoMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, 2799 Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, 2800 Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, 2801 Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, 2802 Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, 2803 Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, 2804 Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, 2805 Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, 2806 Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, 2807 Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, 2808 Convert__VecListThreeD1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, 2809 Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, 2810 Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, 2811 Convert__VecListThreeQ1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, 2812 Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, 2813 Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, 2814 Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, 2815 Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, 2816 Convert__Reg1_3__Reg1_4__Reg1_5__AlignedMemory2_7__CondCode2_0, 2817 Convert__Reg1_3__Reg1_4__Reg1_5__imm_95_0__AlignedMemory2_7__Imm1_8__CondCode2_0, 2818 Convert__Reg1_3__Reg1_6__Reg1_9__AlignedMemory2_13__CondCode2_0, 2819 Convert__Reg1_3__Reg1_6__Reg1_9__imm_95_0__DupAlignedMemory642_13__Imm1_14__CondCode2_0, 2820 Convert__VecListFourDAllLanes1_2__DupAlignedMemory642_3__CondCode2_0, 2821 Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__CondCode2_0, 2822 Convert__VecListFourQAllLanes1_2__DupAlignedMemory642_3__CondCode2_0, 2823 Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, 2824 Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__CondCode2_0, 2825 Convert__VecListFourDAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0, 2826 Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0, 2827 Convert__VecListFourQAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0, 2828 Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0, 2829 Convert__VecListFourDAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, 2830 Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__CondCode2_0, 2831 Convert__VecListFourQAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, 2832 Convert__VecListFourDAllLanes1_2__DupAlignedMemory642_3__Reg1_4__CondCode2_0, 2833 Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, 2834 Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0, 2835 Convert__VecListFourQAllLanes1_2__DupAlignedMemory642_3__Reg1_4__CondCode2_0, 2836 Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, 2837 Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0, 2838 Convert__VecListFourDAllLanes1_2__DupAlignedMemory64or1282_3__Reg1_4__CondCode2_0, 2839 Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, 2840 Convert__VecListFourQAllLanes1_2__DupAlignedMemory64or1282_3__Reg1_4__CondCode2_0, 2841 Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, 2842 Convert__VecListFourDAllLanes1_2__DupAlignedMemory322_3__Reg1_4__CondCode2_0, 2843 Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0, 2844 Convert__VecListFourQAllLanes1_2__DupAlignedMemory322_3__Reg1_4__CondCode2_0, 2845 Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__AlignedMemory2_8__CondCode2_0, 2846 Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__imm_95_0__AlignedMemory2_8__Imm1_9__CondCode2_0, 2847 Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__AlignedMemory2_16__CondCode2_0, 2848 Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__imm_95_0__AlignedMemory2_16__Imm1_17__CondCode2_0, 2849 Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2, 2850 Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, 2851 Convert__Reg1_1__Tie0_2_2__CondCode2_0__SPRRegList1_3, 2852 Convert__Reg1_1__CondCode2_0__SPRRegList1_2, 2853 Convert__MemImm7s4Offset2_2__CondCode2_0, 2854 Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, 2855 Convert__Reg1_1__AddrMode52_2__CondCode2_0, 2856 Convert__Reg1_2__AddrMode5FP162_3__CondCode2_0, 2857 Convert__Reg1_2__AddrMode52_3__CondCode2_0, 2858 Convert__MemNoOffsetT21_2__Tie0_3_3__Imm7s41_3__CondCode2_0, 2859 Convert__imm_95_0__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, 2860 Convert__imm_95_0__MemNoOffsetT21_2__Tie1_3_3__Imm7s41_3__CondCode2_0, 2861 Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, 2862 Convert__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN3_0, 2863 Convert__Reg1_2__MemImm7Shift0Offset2_3__VPTPredN3_0, 2864 Convert__MemNoOffsetT1_3__Reg1_2__Tie0_4_4__Imm7Shift01_4__VPTPredN3_0, 2865 Convert__imm_95_0__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN3_0, 2866 Convert__imm_95_0__Reg1_2__MemImm7Shift0OffsetWB2_3__VPTPredN3_0, 2867 Convert__MemNoOffsetT2NoSp1_3__Reg1_2__Tie0_4_4__Imm7Shift01_4__VPTPredN3_0, 2868 Convert__Reg1_2__MemRegQS3Offset2_3__VPTPredN3_0, 2869 Convert__Reg1_2__MemRegRQS3Offset2_3__VPTPredN3_0, 2870 Convert__imm_95_0__Reg1_2__MemRegQS3Offset2_3__VPTPredN3_0, 2871 Convert__Reg1_2__MemRegRQS1Offset2_3__VPTPredN3_0, 2872 Convert__Reg1_2__TMemImm7Shift1Offset2_3__VPTPredN3_0, 2873 Convert__Reg1_2__MemImm7Shift1Offset2_3__VPTPredN3_0, 2874 Convert__MemNoOffsetT1_3__Reg1_2__Tie0_4_4__Imm7Shift11_4__VPTPredN3_0, 2875 Convert__imm_95_0__Reg1_2__TMemImm7Shift1Offset2_3__VPTPredN3_0, 2876 Convert__imm_95_0__Reg1_2__MemImm7Shift1OffsetWB2_3__VPTPredN3_0, 2877 Convert__MemNoOffsetT2NoSp1_3__Reg1_2__Tie0_4_4__Imm7Shift11_4__VPTPredN3_0, 2878 Convert__Reg1_2__MemImm7Shift2Offset2_3__VPTPredN3_0, 2879 Convert__Reg1_2__MemRegQS2Offset2_3__VPTPredN3_0, 2880 Convert__Reg1_2__MemRegRQS2Offset2_3__VPTPredN3_0, 2881 Convert__imm_95_0__Reg1_2__MemImm7Shift2OffsetWB2_3__VPTPredN3_0, 2882 Convert__MemNoOffsetT2NoSp1_3__Reg1_2__Tie0_4_4__Imm7Shift21_4__VPTPredN3_0, 2883 Convert__imm_95_0__Reg1_2__MemRegQS2Offset2_3__VPTPredN3_0, 2884 Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, 2885 Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, 2886 Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, 2887 Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, 2888 Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN3_0, 2889 Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__Reg1_4__Reg1_5__VPTPredN3_0, 2890 Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__VPTPredN3_0, 2891 Convert__Reg1_1__Reg1_2__Reg1_2__CondCode2_0, 2892 Convert__Reg1_1__Reg1_2__Reg1_2__VPTPredR4_0, 2893 Convert__Reg1_2__FPImm1_3__CondCode2_0, 2894 Convert__Reg1_2__NEONi32vmov1_3__CondCode2_0, 2895 Convert__Reg1_2__NEONi16vmovi8Replicate1_3__CondCode2_0, 2896 Convert__Reg1_2__NEONi16splat1_3__CondCode2_0, 2897 Convert__Reg1_2__NEONi32vmovi8Replicate1_3__CondCode2_0, 2898 Convert__Reg1_2__NEONi32vmovi16Replicate1_3__CondCode2_0, 2899 Convert__Reg1_2__NEONi32vmovNeg1_3__CondCode2_0, 2900 Convert__Reg1_2__NEONi64vmovi8Replicate1_3__CondCode2_0, 2901 Convert__Reg1_2__NEONi64vmovi16Replicate1_3__CondCode2_0, 2902 Convert__Reg1_2__NEONi64vmovi32Replicate1_3__CondCode2_0, 2903 Convert__Reg1_2__NEONi64splat1_3__CondCode2_0, 2904 Convert__Reg1_2__NEONi8splat1_3__CondCode2_0, 2905 Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0, 2906 Convert__Reg1_2__FPImm1_3__VPTPredR4_0, 2907 Convert__Reg1_2__NEONi16splat1_3__VPTPredR4_0, 2908 Convert__Reg1_2__NEONi32vmov1_3__VPTPredR4_0, 2909 Convert__Reg1_2__NEONi64splat1_3__VPTPredR4_0, 2910 Convert__Reg1_2__NEONi8splat1_3__VPTPredR4_0, 2911 Convert__Reg1_2__Reg1_3__MVEVectorIndex81_4__CondCode2_0, 2912 Convert__Reg1_2__Reg1_3__MVEVectorIndex161_4__CondCode2_0, 2913 Convert__Reg1_2__Tie0_1_1__Reg1_4__MVEVectorIndex81_3__CondCode2_0, 2914 Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex161_3__CondCode2_0, 2915 Convert__Reg1_2__Tie0_1_1__Reg1_4__MVEVectorIndex41_3__CondCode2_0, 2916 Convert__Reg1_2__Reg1_3__MVEVectorIndex41_4__CondCode2_0, 2917 Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex321_3__CondCode2_0, 2918 Convert__Reg1_2__Tie0_1_1__Reg1_4__MVEVectorIndex161_3__CondCode2_0, 2919 Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex81_3__CondCode2_0, 2920 Convert__Reg1_1__Tie0_2_4__Reg1_5__Reg1_6__MVEPairVectorIndex21_2__MVEPairVectorIndex01_4__CondCode2_0, 2921 ConvertCustom_cvtMVEVMOVQtoDReg, 2922 Convert__Reg1_1__imm_95_0__CondCode2_0, 2923 Convert__imm_95_0__Reg1_2__CondCode2_0, 2924 Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0, 2925 Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0, 2926 Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, 2927 Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, 2928 Convert__Reg1_1__Reg1_2__VPTPredR4_0, 2929 Convert__Reg1_2__NEONi16invi8Replicate1_3__CondCode2_0, 2930 Convert__Reg1_2__NEONi32invi8Replicate1_3__CondCode2_0, 2931 Convert__Reg1_2__NEONi64invi8Replicate1_3__CondCode2_0, 2932 Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, 2933 Convert__imm_95_0__imm_95_0__VPTPredN3_0, 2934 Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_1, 2935 Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_1, 2936 Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2, 2937 Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2, 2938 Convert__Reg1_1__Reg1_2__Reg1_3__VPTPredN3_0, 2939 Convert__ITMask1_0, 2940 Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2, 2941 Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2, 2942 Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedFP1_2, 2943 Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2, 2944 Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, 2945 Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, 2946 Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, 2947 Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, 2948 Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, 2949 Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, 2950 Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, 2951 Convert__Reg1_2__Reg1_3__Imm0_151_4__VPTPredR4_0, 2952 Convert__Reg1_2__Reg1_3__Imm0_311_4__VPTPredR4_0, 2953 Convert__Reg1_2__Reg1_3__Imm0_71_4__VPTPredR4_0, 2954 Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0, 2955 Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0, 2956 Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0, 2957 Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0, 2958 Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0, 2959 Convert__Reg1_2__Reg1_3__ShrImm161_4__VPTPredR4_0, 2960 Convert__Reg1_2__Reg1_3__ShrImm321_4__VPTPredR4_0, 2961 Convert__Reg1_2__Reg1_3__ShrImm81_4__VPTPredR4_0, 2962 Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, 2963 Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, 2964 Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, 2965 Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, 2966 Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, 2967 Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, 2968 Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, 2969 Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, 2970 Convert__CondCode2_0__FPDRegListWithVPR1_1, 2971 Convert__CondCode2_0__FPSRegListWithVPR1_1, 2972 Convert__Reg1_2__Reg1_1__Tie1_2_2__Tie0_3_3__MVELongShift1_3__VPTPredN3_0, 2973 Convert__Reg1_2__Reg1_3__Imm1_151_4__CondCode2_0, 2974 Convert__Reg1_2__Reg1_3__Imm1_311_4__CondCode2_0, 2975 Convert__Reg1_2__Reg1_3__Imm1_71_4__CondCode2_0, 2976 Convert__Reg1_2__Reg1_3__Imm161_4__CondCode2_0, 2977 Convert__Reg1_2__Reg1_3__Imm321_4__CondCode2_0, 2978 Convert__Reg1_2__Reg1_3__Imm81_4__CondCode2_0, 2979 Convert__Reg1_2__Reg1_3__MVEShiftImm1_151_4__VPTPredR4_0, 2980 Convert__Reg1_2__Reg1_3__MVEShiftImm1_71_4__VPTPredR4_0, 2981 Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0, 2982 Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0, 2983 Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm0_151_4__VPTPredN3_0, 2984 Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm0_311_4__VPTPredN3_0, 2985 Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm0_71_4__VPTPredN3_0, 2986 Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__VPTPredN3_0, 2987 Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, 2988 Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, 2989 Convert__AlignedMemory642_3__VecListOneD1_2__CondCode2_0, 2990 Convert__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0, 2991 Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, 2992 Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0, 2993 Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, 2994 Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0, 2995 Convert__imm_95_0__AlignedMemory642_3__VecListOneD1_2__CondCode2_0, 2996 Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListOneD1_2__CondCode2_0, 2997 Convert__imm_95_0__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0, 2998 Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListThreeD1_2__CondCode2_0, 2999 Convert__AlignedMemory2_8__Reg1_3__Imm1_5__CondCode2_0, 3000 Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Imm1_5__CondCode2_0, 3001 Convert__Reg1_8__Imm1_9__Reg1_3__Imm1_5__CondCode2_0, 3002 Convert__imm_95_0__Reg1_8__Imm1_9__Imm1_10__Reg1_3__Imm1_5__CondCode2_0, 3003 Convert__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0, 3004 Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0, 3005 Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPairSpaced1_2__CondCode2_0, 3006 Convert__VecListTwoMQ1_1__MemNoOffsetT21_2, 3007 Convert__MemNoOffsetT2NoSp1_2__VecListTwoMQ1_1__Tie0_3_3, 3008 Convert__AlignedMemory2_7__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, 3009 Convert__imm_95_0__AlignedMemory2_7__Imm1_8__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, 3010 Convert__AlignedMemory2_8__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, 3011 Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, 3012 Convert__VecListFourMQ1_1__MemNoOffsetT21_2, 3013 Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, 3014 Convert__MemNoOffsetT21_2__imm_95_0__Tie0_3_3__Imm7s41_3__CondCode2_0, 3015 Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__CondCode2_0, 3016 Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, 3017 Convert__Reg1_2__VecListDPair1_3__Reg1_4__CondCode2_0, 3018 Convert__Reg1_2__VecListFourD1_3__Reg1_4__CondCode2_0, 3019 Convert__Reg1_2__VecListOneD1_3__Reg1_4__CondCode2_0, 3020 Convert__Reg1_2__VecListThreeD1_3__Reg1_4__CondCode2_0, 3021 Convert__Reg1_2__Tie0_1_1__VecListDPair1_3__Reg1_4__CondCode2_0, 3022 Convert__Reg1_2__Tie0_1_1__VecListFourD1_3__Reg1_4__CondCode2_0, 3023 Convert__Reg1_2__Tie0_1_1__VecListOneD1_3__Reg1_4__CondCode2_0, 3024 Convert__Reg1_2__Tie0_1_1__VecListThreeD1_3__Reg1_4__CondCode2_0, 3025 Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, 3026 Convert__imm_95_2__CondCode2_0, 3027 Convert__imm_95_3__CondCode2_0, 3028 Convert__Reg1_0__Reg1_1__WLSLabel1_2, 3029 Convert__Reg1_1__Reg1_2__WLSLabel1_3, 3030 Convert__imm_95_1__CondCode2_0, 3031 CVT_NUM_SIGNATURES 3032}; 3033 3034} // end anonymous namespace 3035 3036static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][17] = { 3037 // Convert_NoOperands 3038 { CVT_Done }, 3039 // Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1 3040 { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 2, CVT_Done }, 3041 // Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0 3042 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addRegShiftedRegOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3043 // Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0 3044 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3045 // Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0 3046 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addModImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3047 // Convert__Reg1_2__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0 3048 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addModImmNotOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3049 // Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0 3050 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addRegShiftedImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3051 // Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0 3052 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3053 // Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0 3054 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addRegShiftedImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3055 // Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0 3056 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3057 // Convert__Reg1_2__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0 3058 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addT2SOImmNotOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3059 // Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0 3060 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addRegShiftedRegOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3061 // Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0 3062 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addModImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3063 // Convert__Reg1_2__Reg1_3__ModImmNot1_4__CondCode2_1__CCOut1_0 3064 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addModImmNotOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3065 // Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0 3066 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3067 // Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0 3068 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addRegShiftedImmOperands, 6, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3069 // Convert__Reg1_1__Tie0_1_1__Reg1_2__CondCode2_0 3070 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3071 // Convert__Reg1_1__Reg1_1__Imm0_40951_2__CondCode2_0 3072 { CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3073 // Convert__Reg1_1__Reg1_1__Imm0_4095Neg1_2__CondCode2_0 3074 { CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_addImm0_95_4095NegOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3075 // Convert__Reg1_1__Tie0_1_1__Imm0_508s41_2__CondCode2_0 3076 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_addImm0_95_508s4Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3077 // Convert__regSP__Tie0_1_1__Imm0_508s4Neg1_2__CondCode2_0 3078 { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addImm0_95_508s4NegOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3079 // Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0 3080 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3081 // Convert__Reg1_2__Reg1_2__T2SOImmNeg1_3__CondCode2_1__CCOut1_0 3082 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addT2SOImmNegOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3083 // Convert__Reg1_2__CCOut1_0__Reg1_2__Reg1_3__CondCode2_1 3084 { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 2, CVT_Done }, 3085 // Convert__Reg1_2__CCOut1_0__Tie0_1_1__Imm0_2551_3__CondCode2_1 3086 { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_Done }, 3087 // Convert__Reg1_2__CCOut1_0__Tie0_3_3__ThumbModImmNeg8_2551_3__CondCode2_1 3088 { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_Tied, Tie0_3_3, CVT_95_addThumbModImmNeg8_95_255Operands, 4, CVT_95_addCondCodeOperands, 2, CVT_Done }, 3089 // Convert__Reg1_2__Reg1_2__ModImmNeg1_3__CondCode2_1__CCOut1_0 3090 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addModImmNegOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3091 // Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0 3092 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3093 // Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0 3094 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImm0_95_4095NegOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3095 // Convert__regSP__Tie0_1_1__Imm0_508s41_3__CondCode2_0 3096 { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addImm0_95_508s4Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3097 // Convert__regSP__Tie0_1_1__Imm0_508s4Neg1_3__CondCode2_0 3098 { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addImm0_95_508s4NegOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3099 // Convert__Reg1_1__Reg1_2__Imm0_1020s41_3__CondCode2_0 3100 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImm0_95_1020s4Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3101 // Convert__Reg1_1__Imm0_40951_3__CondCode2_0 3102 { CVT_95_Reg, 2, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3103 // Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0 3104 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3105 // Convert__Reg1_3__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0 3106 { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3107 // Convert__Reg1_3__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0 3108 { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addT2SOImmNegOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3109 // Convert__Reg1_2__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0 3110 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addT2SOImmNegOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3111 // Convert__Reg1_2__CCOut1_0__Reg1_3__Reg1_4__CondCode2_1 3112 { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 2, CVT_Done }, 3113 // Convert__Reg1_2__CCOut1_0__Reg1_3__Imm0_71_4__CondCode2_1 3114 { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_Done }, 3115 // Convert__Reg1_2__CCOut1_0__Reg1_3__ThumbModImmNeg1_71_4__CondCode2_1 3116 { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_Reg, 4, CVT_95_addThumbModImmNeg1_95_7Operands, 5, CVT_95_addCondCodeOperands, 2, CVT_Done }, 3117 // Convert__Reg1_2__Reg1_3__ModImmNeg1_4__CondCode2_1__CCOut1_0 3118 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addModImmNegOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3119 // Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0 3120 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3121 // Convert__Reg1_3__Reg1_4__T2SOImmNeg1_5__CondCode2_1__CCOut1_0 3122 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addT2SOImmNegOperands, 6, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3123 // Convert__Reg1_1__UnsignedOffset_b8s21_2__CondCode2_0 3124 { CVT_95_Reg, 2, CVT_95_addUnsignedOffset_95_b8s2Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3125 // Convert__Reg1_1__Imm1_2__CondCode2_0 3126 { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3127 // Convert__Reg1_1__AdrLabel1_2__CondCode2_0 3128 { CVT_95_Reg, 2, CVT_95_addAdrLabelOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3129 // Convert__Reg1_2__Imm1_3__CondCode2_0 3130 { CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3131 // Convert__Reg1_1__Tie0_1_1__Reg1_2 3132 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_Done }, 3133 // Convert__Reg1_1__Reg1_2 3134 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done }, 3135 // Convert__Reg1_2__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0 3136 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addT2SOImmNotOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3137 // Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0 3138 { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3139 // Convert__Reg1_3__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0 3140 { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addRegShiftedImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3141 // Convert__Reg1_3__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0 3142 { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addT2SOImmNotOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3143 // Convert__Reg1_3__Reg1_4__T2SOImmNot1_5__CondCode2_1__CCOut1_0 3144 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addT2SOImmNotOperands, 6, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3145 // Convert__Reg1_2__CCOut1_0__Reg1_2__ImmThumbSR1_3__CondCode2_1 3146 { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_Done }, 3147 // Convert__Reg1_2__Reg1_2__ImmThumbSR1_3__CondCode2_1__CCOut1_0 3148 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3149 // Convert__Reg1_2__Reg1_2__Imm0_321_3__CondCode2_1__CCOut1_0 3150 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3151 // Convert__Reg1_3__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0 3152 { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3153 // Convert__Reg1_2__CCOut1_0__Reg1_3__ImmThumbSR1_4__CondCode2_1 3154 { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_Done }, 3155 // Convert__Reg1_2__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0 3156 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3157 // Convert__Reg1_2__Reg1_3__Imm0_321_4__CondCode2_1__CCOut1_0 3158 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3159 // Convert__Reg1_3__Reg1_4__ImmThumbSR1_5__CondCode2_1__CCOut1_0 3160 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3161 // Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__Reg1_3__CondCode2_0 3162 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_1_1, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3163 // Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__MVELongShift1_3__CondCode2_0 3164 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_1_1, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3165 // Convert__imm_95_45__CondCode2_0 3166 { CVT_imm_95_45, 0, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3167 // Convert__CondCode2_0__Reg1_1__Reg1_2__Reg1_3 3168 { CVT_95_addCondCodeOperands, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done }, 3169 // Convert__ARMBranchTarget1_1__CondCode2_0 3170 { CVT_95_addARMBranchTargetOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3171 // ConvertCustom_cvtThumbBranches 3172 { CVT_cvtThumbBranches, 0, CVT_Done }, 3173 // Convert__Imm1_1__Imm1_2__CondCode2_0 3174 { CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3175 // Convert__Reg1_1__Tie0_1_1__Bitfield1_2__CondCode2_0 3176 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_addBitfieldOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3177 // Convert__Imm1_0__Imm1_1__Imm1_2__CondCodeNoAL1_3 3178 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addITCondCodeOperands, 4, CVT_Done }, 3179 // Convert__Reg1_1__Tie0_1_1__Reg1_2__Bitfield1_3__CondCode2_0 3180 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addBitfieldOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3181 // Convert__Imm1_1__Reg1_2__CondCode2_0 3182 { CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3183 // Convert__imm_95_0 3184 { CVT_imm_95_0, 0, CVT_Done }, 3185 // Convert__Imm0_2551_0 3186 { CVT_95_addImmOperands, 1, CVT_Done }, 3187 // Convert__Imm0_655351_0 3188 { CVT_95_addImmOperands, 1, CVT_Done }, 3189 // Convert__ARMBranchTarget1_0 3190 { CVT_95_addARMBranchTargetOperands, 1, CVT_Done }, 3191 // Convert__CondCode2_0__ThumbBranchTarget1_1 3192 { CVT_95_addCondCodeOperands, 1, CVT_95_addThumbBranchTargetOperands, 2, CVT_Done }, 3193 // Convert__CondCode2_0__ThumbBranchTarget1_2 3194 { CVT_95_addCondCodeOperands, 1, CVT_95_addThumbBranchTargetOperands, 3, CVT_Done }, 3195 // Convert__Reg1_0 3196 { CVT_95_Reg, 1, CVT_Done }, 3197 // Convert__ThumbBranchTarget1_0 3198 { CVT_95_addThumbBranchTargetOperands, 1, CVT_Done }, 3199 // Convert__Reg1_1__CondCode2_0 3200 { CVT_95_Reg, 2, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3201 // Convert__CondCode2_0__Reg1_1 3202 { CVT_95_addCondCodeOperands, 1, CVT_95_Reg, 2, CVT_Done }, 3203 // Convert__CondCode2_0__ARMBranchTarget1_1 3204 { CVT_95_addCondCodeOperands, 1, CVT_95_addARMBranchTargetOperands, 2, CVT_Done }, 3205 // Convert__imm_95_15__CondCode2_0 3206 { CVT_imm_95_15, 0, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3207 // Convert__CondCode2_0 3208 { CVT_95_addCondCodeOperands, 1, CVT_Done }, 3209 // Convert__Reg1_0__ThumbBranchTarget1_1 3210 { CVT_95_Reg, 1, CVT_95_addThumbBranchTargetOperands, 2, CVT_Done }, 3211 // Convert__CoprocNum1_1__Imm0_151_2__CoprocReg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0 3212 { CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addCoprocRegOperands, 4, CVT_95_addCoprocRegOperands, 5, CVT_95_addCoprocRegOperands, 6, CVT_95_addImmOperands, 7, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3213 // Convert__CoprocNum1_0__Imm0_151_1__CoprocReg1_2__CoprocReg1_3__CoprocReg1_4__Imm0_71_5 3214 { CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addCoprocRegOperands, 3, CVT_95_addCoprocRegOperands, 4, CVT_95_addCoprocRegOperands, 5, CVT_95_addImmOperands, 6, CVT_Done }, 3215 // Convert__Reg1_0__Reg1_1__Reg1_1__CondCodeNoALInv1_2 3216 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_addITCondCodeInvOperands, 3, CVT_Done }, 3217 // Convert__imm_95_22__CondCode2_0 3218 { CVT_imm_95_22, 0, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3219 // Convert__CondCode2_0__RegListWithAPSR1_1 3220 { CVT_95_addCondCodeOperands, 1, CVT_95_addRegListWithAPSROperands, 2, CVT_Done }, 3221 // Convert__Reg1_1__Reg1_2__CondCode2_0 3222 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3223 // Convert__Reg1_1__ModImmNeg1_2__CondCode2_0 3224 { CVT_95_Reg, 2, CVT_95_addModImmNegOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3225 // Convert__Reg1_1__T2SOImmNeg1_2__CondCode2_0 3226 { CVT_95_Reg, 2, CVT_95_addT2SOImmNegOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3227 // Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0 3228 { CVT_95_Reg, 2, CVT_95_addRegShiftedImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3229 // Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0 3230 { CVT_95_Reg, 2, CVT_95_addRegShiftedRegOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3231 // Convert__Reg1_1__T2SOImm1_2__CondCode2_0 3232 { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3233 // Convert__Reg1_1__ModImm1_2__CondCode2_0 3234 { CVT_95_Reg, 2, CVT_95_addModImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3235 // Convert__Reg1_2__Reg1_3__CondCode2_0 3236 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3237 // Convert__Reg1_2__RegShiftedImm2_3__CondCode2_0 3238 { CVT_95_Reg, 3, CVT_95_addRegShiftedImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3239 // Convert__Reg1_2__T2SOImm1_3__CondCode2_0 3240 { CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3241 // Convert__Reg1_1__Imm0_2551_2__CondCode2_0 3242 { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3243 // Convert__Imm0_311_0 3244 { CVT_95_addImmOperands, 1, CVT_Done }, 3245 // Convert__Imm0_311_1 3246 { CVT_95_addImmOperands, 2, CVT_Done }, 3247 // Convert__Imm1_0__ProcIFlags1_1 3248 { CVT_95_addImmOperands, 1, CVT_95_addProcIFlagsOperands, 2, CVT_Done }, 3249 // Convert__Imm1_0__ProcIFlags1_2 3250 { CVT_95_addImmOperands, 1, CVT_95_addProcIFlagsOperands, 3, CVT_Done }, 3251 // Convert__Imm1_0__ProcIFlags1_1__Imm0_311_2 3252 { CVT_95_addImmOperands, 1, CVT_95_addProcIFlagsOperands, 2, CVT_95_addImmOperands, 3, CVT_Done }, 3253 // Convert__Imm1_0__ProcIFlags1_1__Imm1_2 3254 { CVT_95_addImmOperands, 1, CVT_95_addProcIFlagsOperands, 2, CVT_95_addImmOperands, 3, CVT_Done }, 3255 // Convert__Imm1_0__ProcIFlags1_2__Imm1_3 3256 { CVT_95_addImmOperands, 1, CVT_95_addProcIFlagsOperands, 3, CVT_95_addImmOperands, 4, CVT_Done }, 3257 // Convert__Reg1_0__Reg1_1__Reg1_2 3258 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done }, 3259 // Convert__imm_95_20__CondCode2_0 3260 { CVT_imm_95_20, 0, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3261 // Convert__Reg1_0__Reg1_1__Reg1_2__CondCodeNoAL1_3 3262 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addITCondCodeOperands, 4, CVT_Done }, 3263 // Convert__Reg1_0__regZR__regZR__CondCodeNoALInv1_1 3264 { CVT_95_Reg, 1, CVT_regZR, 0, CVT_regZR, 0, CVT_95_addITCondCodeInvOperands, 2, CVT_Done }, 3265 // Convert__Reg1_1__CoprocNum1_0__Imm13b1_2 3266 { CVT_95_Reg, 2, CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 3, CVT_Done }, 3267 // Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Imm13b1_3__CondCode2_0 3268 { CVT_95_Reg, 3, CVT_95_addCoprocNumOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3269 // Convert__Reg1_1__CoprocNum1_0__Reg1_2__Imm9b1_3 3270 { CVT_95_Reg, 2, CVT_95_addCoprocNumOperands, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done }, 3271 // Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Reg1_3__Imm9b1_4__CondCode2_0 3272 { CVT_95_Reg, 3, CVT_95_addCoprocNumOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3273 // Convert__Reg1_1__CoprocNum1_0__Reg1_2__Reg1_3__Imm6b1_4 3274 { CVT_95_Reg, 2, CVT_95_addCoprocNumOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_Done }, 3275 // Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Reg1_3__Reg1_4__Imm6b1_5__CondCode2_0 3276 { CVT_95_Reg, 3, CVT_95_addCoprocNumOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3277 // Convert__Imm0_151_1__CondCode2_0 3278 { CVT_95_addImmOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3279 // Convert__Imm0_151_2__CondCode2_0 3280 { CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3281 // Convert__imm_95_12 3282 { CVT_imm_95_12, 0, CVT_Done }, 3283 // Convert__imm_95_12__CondCode2_0 3284 { CVT_imm_95_12, 0, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3285 // Convert__Reg1_0__Reg1_1 3286 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done }, 3287 // Convert__imm_95_15 3288 { CVT_imm_95_15, 0, CVT_Done }, 3289 // Convert__MemBarrierOpt1_0 3290 { CVT_95_addMemBarrierOptOperands, 1, CVT_Done }, 3291 // Convert__MemBarrierOpt1_1__CondCode2_0 3292 { CVT_95_addMemBarrierOptOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3293 // Convert__MemBarrierOpt1_2__CondCode2_0 3294 { CVT_95_addMemBarrierOptOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3295 // Convert__imm_95_0__CondCode2_0 3296 { CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3297 // Convert__imm_95_16__CondCode2_0 3298 { CVT_imm_95_16, 0, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3299 // Convert__Reg1_1__FPImm1_2__CondCode2_0 3300 { CVT_95_Reg, 2, CVT_95_addFPImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3301 // Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3 3302 { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_addCondCodeOperands, 1, CVT_95_addDPRRegListOperands, 4, CVT_Done }, 3303 // Convert__Reg1_1__CondCode2_0__DPRRegList1_2 3304 { CVT_95_Reg, 2, CVT_95_addCondCodeOperands, 1, CVT_95_addDPRRegListOperands, 3, CVT_Done }, 3305 // Convert__Reg1_1__Tie0_2_2__Reg1_2__imm_95_1__CondCode2_0 3306 { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_imm_95_1, 0, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3307 // Convert__Reg1_1__Tie0_2_2__Reg1_2__imm_95_0__CondCode2_0 3308 { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3309 // Convert__Imm0_2391_1__CondCode2_0 3310 { CVT_95_addImmOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3311 // Convert__Imm0_2391_2__CondCode2_0 3312 { CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3313 // Convert__Imm0_631_0 3314 { CVT_95_addImmOperands, 1, CVT_Done }, 3315 // Convert__Imm0_655351_1 3316 { CVT_95_addImmOperands, 2, CVT_Done }, 3317 // Convert__InstSyncBarrierOpt1_0 3318 { CVT_95_addInstSyncBarrierOptOperands, 1, CVT_Done }, 3319 // Convert__InstSyncBarrierOpt1_1__CondCode2_0 3320 { CVT_95_addInstSyncBarrierOptOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3321 // Convert__ITCondCode1_1__ITMask1_0 3322 { CVT_95_addITCondCodeOperands, 2, CVT_95_addITMaskOperands, 1, CVT_Done }, 3323 // Convert__Reg1_1__MemNoOffset1_2__CondCode2_0 3324 { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3325 // Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0 3326 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemNoOffsetOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3327 // Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0 3328 { CVT_95_addCoprocNumOperands, 2, CVT_95_addCoprocRegOperands, 3, CVT_95_addAddrMode5Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3329 // Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0 3330 { CVT_95_addCoprocNumOperands, 2, CVT_95_addCoprocRegOperands, 3, CVT_95_addMemNoOffsetOperands, 4, CVT_95_addCoprocOptionOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3331 // Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0 3332 { CVT_95_addCoprocNumOperands, 2, CVT_95_addCoprocRegOperands, 3, CVT_95_addMemNoOffsetOperands, 4, CVT_95_addPostIdxImm8s4Operands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3333 // Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2 3334 { CVT_95_addCoprocNumOperands, 1, CVT_95_addCoprocRegOperands, 2, CVT_95_addAddrMode5Operands, 3, CVT_Done }, 3335 // Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__CoprocOption1_3 3336 { CVT_95_addCoprocNumOperands, 1, CVT_95_addCoprocRegOperands, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_95_addCoprocOptionOperands, 4, CVT_Done }, 3337 // Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__PostIdxImm8s41_3 3338 { CVT_95_addCoprocNumOperands, 1, CVT_95_addCoprocRegOperands, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_95_addPostIdxImm8s4Operands, 4, CVT_Done }, 3339 // Convert__Reg1_1__CondCode2_0__RegList1_2 3340 { CVT_95_Reg, 2, CVT_95_addCondCodeOperands, 1, CVT_95_addRegListOperands, 3, CVT_Done }, 3341 // Convert__Reg1_2__CondCode2_0__RegList1_3 3342 { CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_95_addRegListOperands, 4, CVT_Done }, 3343 // Convert__Reg1_1__CondCode2_0__RegList1_3 3344 { CVT_95_Reg, 2, CVT_95_addCondCodeOperands, 1, CVT_95_addRegListOperands, 4, CVT_Done }, 3345 // Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3 3346 { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_addCondCodeOperands, 1, CVT_95_addRegListOperands, 4, CVT_Done }, 3347 // Convert__Reg1_2__Tie0_3_3__CondCode2_0__RegList1_4 3348 { CVT_95_Reg, 3, CVT_Tied, Tie0_3_3, CVT_95_addCondCodeOperands, 1, CVT_95_addRegListOperands, 5, CVT_Done }, 3349 // Convert__Reg1_1__ThumbMemPC1_2__CondCode2_0 3350 { CVT_95_Reg, 2, CVT_95_addThumbMemPCOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3351 // Convert__Reg1_1__ConstPoolAsmImm1_2__CondCode2_0 3352 { CVT_95_Reg, 2, CVT_95_addConstPoolAsmImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3353 // Convert__Reg1_1__MemThumbRIs42_2__CondCode2_0 3354 { CVT_95_Reg, 2, CVT_95_addMemThumbRIs4Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3355 // Convert__Reg1_1__MemThumbRR2_2__CondCode2_0 3356 { CVT_95_Reg, 2, CVT_95_addMemThumbRROperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3357 // Convert__Reg1_1__MemThumbSPI2_2__CondCode2_0 3358 { CVT_95_Reg, 2, CVT_95_addMemThumbSPIOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3359 // Convert__Reg1_1__MemImm12Offset2_2__CondCode2_0 3360 { CVT_95_Reg, 2, CVT_95_addMemImm12OffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3361 // Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0 3362 { CVT_95_Reg, 2, CVT_95_addMemImmOffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3363 // Convert__Reg1_1__MemRegOffset3_2__CondCode2_0 3364 { CVT_95_Reg, 2, CVT_95_addMemRegOffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3365 // Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0 3366 { CVT_95_Reg, 2, CVT_95_addMemUImm12OffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3367 // Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0 3368 { CVT_95_Reg, 2, CVT_95_addT2MemRegOffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3369 // Convert__Reg1_1__MemPCRelImm121_2__CondCode2_0 3370 { CVT_95_Reg, 2, CVT_95_addMemPCRelImm12Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3371 // Convert__Reg1_2__ConstPoolAsmImm1_3__CondCode2_0 3372 { CVT_95_Reg, 3, CVT_95_addConstPoolAsmImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3373 // Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0 3374 { CVT_95_Reg, 3, CVT_95_addMemUImm12OffsetOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3375 // Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0 3376 { CVT_95_Reg, 3, CVT_95_addT2MemRegOffsetOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3377 // Convert__Reg1_2__MemPCRelImm121_3__CondCode2_0 3378 { CVT_95_Reg, 3, CVT_95_addMemPCRelImm12Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3379 // Convert__Reg1_1__imm_95_0__MemImm12Offset2_2__CondCode2_0 3380 { CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_95_addMemImm12OffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3381 // Convert__Reg1_1__imm_95_0__MemImm8Offset2_2__CondCode2_0 3382 { CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_95_addMemImmOffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3383 // Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM2OffsetImm2_3__CondCode2_0 3384 { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_Tied, Tie1_3_3, CVT_95_addAM2OffsetImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3385 // Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__Imm1_3__CondCode2_0 3386 { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_Tied, Tie1_3_3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3387 // Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxRegShifted2_3__CondCode2_0 3388 { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_Tied, Tie1_3_3, CVT_95_addPostIdxRegShiftedOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3389 // Convert__Reg1_1__imm_95_0__MemRegOffset3_2__CondCode2_0 3390 { CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_95_addMemRegOffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3391 // Convert__Reg1_2__MemImm8Offset2_3__CondCode2_0 3392 { CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3393 // Convert__Reg1_2__MemNoOffset1_3__Imm1_4__CondCode2_0 3394 { CVT_95_Reg, 3, CVT_95_addMemNoOffsetOperands, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3395 // Convert__Reg1_1__MemThumbRIs12_2__CondCode2_0 3396 { CVT_95_Reg, 2, CVT_95_addMemThumbRIs1Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3397 // Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0 3398 { CVT_95_Reg, 2, CVT_95_addMemImmOffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3399 // Convert__Reg1_1__Reg1_2__MemImm8s4Offset2_3__CondCode2_0 3400 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemImm8s4OffsetOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3401 // Convert__Reg1_1__Reg1_2__AddrMode33_3__CondCode2_0 3402 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addAddrMode3Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3403 // Convert__Reg1_1__Reg1_2__imm_95_0__MemImm8s4Offset2_3__CondCode2_0 3404 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_addMemImm8s4OffsetOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3405 // Convert__Reg1_1__Reg1_2__MemNoOffset1_3__Tie2_4_4__Imm1_4__CondCode2_0 3406 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemNoOffsetOperands, 4, CVT_Tied, Tie2_4_4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3407 // Convert__Reg1_1__Reg1_2__imm_95_0__AddrMode33_3__CondCode2_0 3408 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_addAddrMode3Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3409 // Convert__Reg1_1__Reg1_2__MemNoOffset1_3__Tie2_4_4__AM3Offset2_4__CondCode2_0 3410 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemNoOffsetOperands, 4, CVT_Tied, Tie2_4_4, CVT_95_addAM3OffsetOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3411 // Convert__Reg1_1__MemImm0_1020s4Offset2_2__CondCode2_0 3412 { CVT_95_Reg, 2, CVT_95_addMemImm0_95_1020s4OffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3413 // Convert__Reg1_1__MemThumbRIs22_2__CondCode2_0 3414 { CVT_95_Reg, 2, CVT_95_addMemThumbRIs2Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3415 // Convert__Reg1_1__AddrMode33_2__CondCode2_0 3416 { CVT_95_Reg, 2, CVT_95_addAddrMode3Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3417 // Convert__Reg1_1__imm_95_0__AddrMode33_2__CondCode2_0 3418 { CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_95_addAddrMode3Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3419 // Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM3Offset2_3__CondCode2_0 3420 { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_Tied, Tie1_3_3, CVT_95_addAM3OffsetOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3421 // Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxReg2_3__CondCode2_0 3422 { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_Tied, Tie1_3_3, CVT_95_addPostIdxRegOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3423 // Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxImm81_3__CondCode2_0 3424 { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_Tied, Tie1_3_3, CVT_95_addPostIdxImm8Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3425 // Convert__LELabel1_0 3426 { CVT_95_addImmOperands, 1, CVT_Done }, 3427 // Convert__imm_95_0__Reg1_0__LELabel1_1 3428 { CVT_imm_95_0, 0, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done }, 3429 // Convert__Reg1_2__CCOut1_0__Reg1_2__Imm0_311_3__CondCode2_1 3430 { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_Done }, 3431 // Convert__Reg1_2__Reg1_2__Imm1_311_3__CondCode2_1__CCOut1_0 3432 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3433 // Convert__Reg1_2__Reg1_2__Imm0_311_3__CondCode2_1__CCOut1_0 3434 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3435 // Convert__Reg1_3__Reg1_3__Imm1_311_4__CondCode2_1__CCOut1_0 3436 { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3437 // Convert__Reg1_2__CCOut1_0__Reg1_3__Imm0_311_4__CondCode2_1 3438 { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_Done }, 3439 // Convert__Reg1_2__Reg1_3__Imm1_311_4__CondCode2_1__CCOut1_0 3440 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3441 // Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0 3442 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3443 // Convert__Reg1_2__Reg1_3__Imm0_311_4__CondCode2_1__CCOut1_0 3444 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3445 // Convert__Reg1_3__Reg1_4__Imm1_311_5__CondCode2_1__CCOut1_0 3446 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3447 // Convert__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0 3448 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3449 // Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0 3450 { CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_95_addCoprocRegOperands, 5, CVT_95_addCoprocRegOperands, 6, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3451 // Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0 3452 { CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_95_addCoprocRegOperands, 5, CVT_95_addCoprocRegOperands, 6, CVT_95_addImmOperands, 7, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3453 // Convert__CoprocNum1_0__Imm0_71_1__Reg1_2__CoprocReg1_3__CoprocReg1_4__imm_95_0 3454 { CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_95_addCoprocRegOperands, 4, CVT_95_addCoprocRegOperands, 5, CVT_imm_95_0, 0, CVT_Done }, 3455 // Convert__CoprocNum1_0__Imm0_71_1__Reg1_2__CoprocReg1_3__CoprocReg1_4__Imm0_71_5 3456 { CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_95_addCoprocRegOperands, 4, CVT_95_addCoprocRegOperands, 5, CVT_95_addImmOperands, 6, CVT_Done }, 3457 // Convert__CoprocNum1_1__Imm0_151_2__Reg1_3__Reg1_4__CoprocReg1_5__CondCode2_0 3458 { CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCoprocRegOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3459 // Convert__CoprocNum1_0__Imm0_151_1__Reg1_2__Reg1_3__CoprocReg1_4 3460 { CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCoprocRegOperands, 5, CVT_Done }, 3461 // Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0 3462 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3463 // Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0 3464 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3465 // Convert__Reg1_1__Imm256_65535Expr1_2__CondCode2_0 3466 { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3467 // Convert__Reg1_1__T2SOImm1_2__CondCode2_0__reg0 3468 { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_reg0, 0, CVT_Done }, 3469 // Convert__Reg1_1__T2SOImmNot1_2__CondCode2_0__reg0 3470 { CVT_95_Reg, 2, CVT_95_addT2SOImmNotOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_reg0, 0, CVT_Done }, 3471 // Convert__Reg1_1__Imm0_65535Expr1_2__CondCode2_0 3472 { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3473 // Convert__Reg1_2__CCOut1_0__Imm0_2551_3__CondCode2_1 3474 { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_Done }, 3475 // Convert__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0 3476 { CVT_95_Reg, 3, CVT_95_addModImmNotOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3477 // Convert__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0 3478 { CVT_95_Reg, 3, CVT_95_addRegShiftedRegOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3479 // Convert__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0 3480 { CVT_95_Reg, 3, CVT_95_addModImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3481 // Convert__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0 3482 { CVT_95_Reg, 3, CVT_95_addRegShiftedImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3483 // Convert__Reg1_2__RegShiftedReg3_3__CondCode2_0 3484 { CVT_95_Reg, 3, CVT_95_addRegShiftedRegOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3485 // Convert__Reg1_2__T2SOImm1_3__CondCode2_0__reg0 3486 { CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_reg0, 0, CVT_Done }, 3487 // Convert__Reg1_2__Reg1_3__CondCode2_0__reg0 3488 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_reg0, 0, CVT_Done }, 3489 // Convert__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0 3490 { CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3491 // Convert__Reg1_0__regCPSR__Imm0_2551_1__imm_95_14__imm_95_0 3492 { CVT_95_Reg, 1, CVT_regCPSR, 0, CVT_95_addImmOperands, 2, CVT_imm_95_14, 0, CVT_imm_95_0, 0, CVT_Done }, 3493 // Convert__Reg1_1__T2SOImm1_2__CondCode2_0__regCPSR 3494 { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_regCPSR, 0, CVT_Done }, 3495 // Convert__Reg1_1__Reg1_2__CondCode2_0__regCPSR 3496 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_regCPSR, 0, CVT_Done }, 3497 // Convert__Reg1_2__T2SOImm1_3__CondCode2_0__regCPSR 3498 { CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_regCPSR, 0, CVT_Done }, 3499 // Convert__Reg1_2__Reg1_3__CondCode2_0__regCPSR 3500 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_regCPSR, 0, CVT_Done }, 3501 // Convert__Reg1_1__Tie0_1_1__Imm0_65535Expr1_2__CondCode2_0 3502 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3503 // Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0 3504 { CVT_95_Reg, 4, CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addCoprocRegOperands, 5, CVT_95_addCoprocRegOperands, 6, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3505 // Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0 3506 { CVT_95_Reg, 4, CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addCoprocRegOperands, 5, CVT_95_addCoprocRegOperands, 6, CVT_95_addImmOperands, 7, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3507 // Convert__Reg1_2__CoprocNum1_0__Imm0_71_1__CoprocReg1_3__CoprocReg1_4__imm_95_0 3508 { CVT_95_Reg, 3, CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addCoprocRegOperands, 4, CVT_95_addCoprocRegOperands, 5, CVT_imm_95_0, 0, CVT_Done }, 3509 // Convert__Reg1_2__CoprocNum1_0__Imm0_71_1__CoprocReg1_3__CoprocReg1_4__Imm0_71_5 3510 { CVT_95_Reg, 3, CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addCoprocRegOperands, 4, CVT_95_addCoprocRegOperands, 5, CVT_95_addImmOperands, 6, CVT_Done }, 3511 // Convert__Reg1_3__Reg1_4__CoprocNum1_1__Imm0_151_2__CoprocReg1_5__CondCode2_0 3512 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addCoprocRegOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3513 // Convert__Reg1_2__Reg1_3__CoprocNum1_0__Imm0_151_1__CoprocReg1_4 3514 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addCoprocRegOperands, 5, CVT_Done }, 3515 // Convert__Reg1_1__BankedReg1_2__CondCode2_0 3516 { CVT_95_Reg, 2, CVT_95_addBankedRegOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3517 // Convert__Reg1_1__MSRMask1_2__CondCode2_0 3518 { CVT_95_Reg, 2, CVT_95_addMSRMaskOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3519 // Convert__BankedReg1_1__Reg1_2__CondCode2_0 3520 { CVT_95_addBankedRegOperands, 2, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3521 // Convert__MSRMask1_1__Reg1_2__CondCode2_0 3522 { CVT_95_addMSRMaskOperands, 2, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3523 // Convert__MSRMask1_1__ModImm1_2__CondCode2_0 3524 { CVT_95_addMSRMaskOperands, 2, CVT_95_addModImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3525 // Convert__Reg1_1__Reg1_2__Reg1_1__CondCode2_0 3526 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3527 // ConvertCustom_cvtThumbMultiply 3528 { CVT_cvtThumbMultiply, 0, CVT_Done }, 3529 // Convert__Reg1_2__CCOut1_0__Reg1_3__CondCode2_1 3530 { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 2, CVT_Done }, 3531 // Convert__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0 3532 { CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3533 // Convert__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0 3534 { CVT_95_Reg, 3, CVT_95_addT2SOImmNotOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3535 // Convert__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0 3536 { CVT_95_Reg, 4, CVT_95_addRegShiftedImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3537 // Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_1__CCOut1_0 3538 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3539 // Convert__regR8__regR8__imm_95_14__imm_95_0 3540 { CVT_regR8, 0, CVT_regR8, 0, CVT_imm_95_14, 0, CVT_imm_95_0, 0, CVT_Done }, 3541 // Convert__regR0__regR0__CondCode2_0__reg0 3542 { CVT_regR0, 0, CVT_regR0, 0, CVT_95_addCondCodeOperands, 1, CVT_reg0, 0, CVT_Done }, 3543 // Convert__imm_95_29__CondCode2_0 3544 { CVT_imm_95_29, 0, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3545 // Convert__imm_95_13__CondCode2_0 3546 { CVT_imm_95_13, 0, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3547 // Convert__Reg1_1__CondCode2_0__Reg1_2__Reg1_3 3548 { CVT_95_Reg, 2, CVT_95_addCondCodeOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done }, 3549 // Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0 3550 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3551 // Convert__Reg1_1__Reg1_2__Reg1_3__PKHLSLImm1_4__CondCode2_0 3552 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3553 // Convert__Reg1_1__Reg1_3__Reg1_2__imm_95_0__CondCode2_0 3554 { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3555 // Convert__Reg1_1__Reg1_2__Reg1_3__PKHASRImm1_4__CondCode2_0 3556 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addPKHASRImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3557 // Convert__MemImm12Offset2_0 3558 { CVT_95_addMemImm12OffsetOperands, 1, CVT_Done }, 3559 // Convert__MemRegOffset3_0 3560 { CVT_95_addMemRegOffsetOperands, 1, CVT_Done }, 3561 // Convert__Imm1_1__CondCode2_0 3562 { CVT_95_addImmOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3563 // Convert__MemNegImm8Offset2_1__CondCode2_0 3564 { CVT_95_addMemImmOffsetOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3565 // Convert__MemUImm12Offset2_1__CondCode2_0 3566 { CVT_95_addMemUImm12OffsetOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3567 // Convert__T2MemRegOffset3_1__CondCode2_0 3568 { CVT_95_addT2MemRegOffsetOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3569 // Convert__MemPCRelImm121_1__CondCode2_0 3570 { CVT_95_addMemPCRelImm12Operands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3571 // Convert__Imm1_2__CondCode2_0 3572 { CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3573 // Convert__MemNegImm8Offset2_2__CondCode2_0 3574 { CVT_95_addMemImmOffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3575 // Convert__MemUImm12Offset2_2__CondCode2_0 3576 { CVT_95_addMemUImm12OffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3577 // Convert__T2MemRegOffset3_2__CondCode2_0 3578 { CVT_95_addT2MemRegOffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3579 // Convert__MemPCRelImm121_2__CondCode2_0 3580 { CVT_95_addMemPCRelImm12Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3581 // Convert__CondCode2_0__RegList1_1 3582 { CVT_95_addCondCodeOperands, 1, CVT_95_addRegListOperands, 2, CVT_Done }, 3583 // Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_1 3584 { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands, 1, CVT_95_addRegListOperands, 2, CVT_Done }, 3585 // Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_2 3586 { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands, 1, CVT_95_addRegListOperands, 3, CVT_Done }, 3587 // Convert__imm_95_4__imm_95_14__imm_95_0 3588 { CVT_imm_95_4, 0, CVT_imm_95_14, 0, CVT_imm_95_0, 0, CVT_Done }, 3589 // Convert__imm_95_4 3590 { CVT_imm_95_4, 0, CVT_Done }, 3591 // Convert__Reg1_1__Reg1_2__Imm0_311_3__Imm1_321_4__CondCode2_0 3592 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addImm1_95_32Operands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3593 // Convert__SetEndImm1_0 3594 { CVT_95_addImmOperands, 1, CVT_Done }, 3595 // Convert__Imm0_11_0 3596 { CVT_95_addImmOperands, 1, CVT_Done }, 3597 // Convert__imm_95_4__CondCode2_0 3598 { CVT_imm_95_4, 0, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3599 // Convert__imm_95_5__CondCode2_0 3600 { CVT_imm_95_5, 0, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3601 // Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3 3602 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done }, 3603 // Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0 3604 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_1_1, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3605 // Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0_1_1__Tie1_1_1__CondCode2_1__CCOut1_0 3606 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_1_1, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3607 // Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0_3_3__Tie1_4_4__CondCode2_1__CCOut1_0 3608 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_Tied, Tie0_3_3, CVT_Tied, Tie1_4_4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 3609 // Convert__Reg1_1__Tie0_2_2__Reg1_2__CondCode2_0 3610 { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3611 // Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__Reg1_4__MveSaturate1_3__CondCode2_0 3612 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_1_1, CVT_95_Reg, 5, CVT_95_addMveSaturateOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3613 // Convert__Reg1_1__Tie0_2_2__MVELongShift1_2__CondCode2_0 3614 { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3615 // Convert__Imm0_311_2 3616 { CVT_95_addImmOperands, 3, CVT_Done }, 3617 // Convert__Imm0_311_1__CondCode2_0 3618 { CVT_95_addImmOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3619 // Convert__Imm0_311_2__CondCode2_0 3620 { CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3621 // Convert__Imm0_311_3__CondCode2_0 3622 { CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3623 // Convert__Reg1_1__Imm1_321_2__Reg1_3__imm_95_0__CondCode2_0 3624 { CVT_95_Reg, 2, CVT_95_addImm1_95_32Operands, 3, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3625 // Convert__Reg1_1__Imm1_321_2__Reg1_3__ShifterImm1_4__CondCode2_0 3626 { CVT_95_Reg, 2, CVT_95_addImm1_95_32Operands, 3, CVT_95_Reg, 4, CVT_95_addShifterImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3627 // Convert__Reg1_1__Imm1_161_2__Reg1_3__CondCode2_0 3628 { CVT_95_Reg, 2, CVT_95_addImm1_95_16Operands, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3629 // Convert__imm_95_0__imm_95_14__imm_95_0 3630 { CVT_imm_95_0, 0, CVT_imm_95_14, 0, CVT_imm_95_0, 0, CVT_Done }, 3631 // Convert__Reg1_1__Reg1_2__Reg1_3__MemNoOffset1_4__CondCode2_0 3632 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemNoOffsetOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3633 // Convert__imm_95_0__Reg1_1__MemImm8Offset2_2__CondCode2_0 3634 { CVT_imm_95_0, 0, CVT_95_Reg, 2, CVT_95_addMemImmOffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3635 // Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__Imm1_3__CondCode2_0 3636 { CVT_95_addMemNoOffsetOperands, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3637 // Convert__imm_95_0__Reg1_1__MemImm12Offset2_2__CondCode2_0 3638 { CVT_imm_95_0, 0, CVT_95_Reg, 2, CVT_95_addMemImm12OffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3639 // Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM2OffsetImm2_3__CondCode2_0 3640 { CVT_95_addMemNoOffsetOperands, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_95_addAM2OffsetImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3641 // Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxRegShifted2_3__CondCode2_0 3642 { CVT_95_addMemNoOffsetOperands, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_95_addPostIdxRegShiftedOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3643 // Convert__imm_95_0__Reg1_1__MemRegOffset3_2__CondCode2_0 3644 { CVT_imm_95_0, 0, CVT_95_Reg, 2, CVT_95_addMemRegOffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3645 // Convert__imm_95_0__Reg1_1__Reg1_2__MemImm8s4Offset2_3__CondCode2_0 3646 { CVT_imm_95_0, 0, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemImm8s4OffsetOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3647 // Convert__MemNoOffset1_3__Reg1_1__Reg1_2__Tie0_4_4__Imm1_4__CondCode2_0 3648 { CVT_95_addMemNoOffsetOperands, 4, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Tied, Tie0_4_4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3649 // Convert__imm_95_0__Reg1_1__Reg1_2__AddrMode33_3__CondCode2_0 3650 { CVT_imm_95_0, 0, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addAddrMode3Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3651 // Convert__MemNoOffset1_3__Reg1_1__Reg1_2__Tie0_4_4__AM3Offset2_4__CondCode2_0 3652 { CVT_95_addMemNoOffsetOperands, 4, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Tied, Tie0_4_4, CVT_95_addAM3OffsetOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3653 // Convert__Reg1_1__Reg1_2__MemImm0_1020s4Offset2_3__CondCode2_0 3654 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemImm0_95_1020s4OffsetOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3655 // Convert__imm_95_0__Reg1_1__AddrMode33_2__CondCode2_0 3656 { CVT_imm_95_0, 0, CVT_95_Reg, 2, CVT_95_addAddrMode3Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3657 // Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM3Offset2_3__CondCode2_0 3658 { CVT_95_addMemNoOffsetOperands, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_95_addAM3OffsetOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3659 // Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxImm81_3__CondCode2_0 3660 { CVT_95_addMemNoOffsetOperands, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_95_addPostIdxImm8Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3661 // Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxReg2_3__CondCode2_0 3662 { CVT_95_addMemNoOffsetOperands, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_95_addPostIdxRegOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3663 // Convert__Imm0_2551_3__CondCode2_0 3664 { CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3665 // Convert__Imm0_2551_1__CondCode2_0 3666 { CVT_95_addImmOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3667 // Convert__Imm24bit1_1__CondCode2_0 3668 { CVT_95_addImmOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3669 // Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0 3670 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addRotImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3671 // Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0 3672 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3673 // Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_0 3674 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3675 // Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0 3676 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addRotImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3677 // Convert__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0 3678 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addRotImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3679 // Convert__MemTBB2_1__CondCode2_0 3680 { CVT_95_addMemTBBOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3681 // Convert__MemTBH2_1__CondCode2_0 3682 { CVT_95_addMemTBHOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3683 // Convert__TraceSyncBarrierOpt1_0 3684 { CVT_95_addTraceSyncBarrierOptOperands, 1, CVT_Done }, 3685 // Convert__TraceSyncBarrierOpt1_1__CondCode2_0 3686 { CVT_95_addTraceSyncBarrierOptOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3687 // Convert__Reg1_1__Imm0_311_2__Reg1_3__imm_95_0__CondCode2_0 3688 { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3689 // Convert__Reg1_1__Imm0_311_2__Reg1_3__ShifterImm1_4__CondCode2_0 3690 { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_95_addShifterImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3691 // Convert__Reg1_1__Imm0_151_2__Reg1_3__CondCode2_0 3692 { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3693 // Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0 3694 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3695 // Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0 3696 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 3697 // Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0 3698 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3699 // Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0 3700 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3701 // Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0 3702 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVPTPredROperands, 1, CVT_Done }, 3703 // Convert__Reg1_2__Reg1_3__VPTPredR4_0 3704 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVPTPredROperands, 1, CVT_Done }, 3705 // Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0 3706 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3707 // Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0 3708 { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3709 // Convert__Reg1_2__imm_95_0__Reg1_3__Reg1_4__imm_95_0__VPTPredR4_0 3710 { CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_imm_95_0, 0, CVT_95_addVPTPredROperands, 1, CVT_Done }, 3711 // Convert__Reg1_2__imm_95_0__Reg1_3__Reg1_4__VPTPredR4_0 3712 { CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVPTPredROperands, 1, CVT_Done }, 3713 // Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0 3714 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 3715 // Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__VPTPredN3_0 3716 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_1_1, CVT_95_Reg, 5, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 3717 // Convert__Reg1_2__Reg1_3__VPTPredN3_0 3718 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 3719 // Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0 3720 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 3721 // Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0 3722 { CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3723 // Convert__Reg1_2__NEONi16splatNot1_3__Tie0_3_3__CondCode2_0 3724 { CVT_95_Reg, 3, CVT_95_addNEONi16splatNotOperands, 4, CVT_Tied, Tie0_3_3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3725 // Convert__Reg1_2__NEONi32splatNot1_3__Tie0_3_3__CondCode2_0 3726 { CVT_95_Reg, 3, CVT_95_addNEONi32splatNotOperands, 4, CVT_Tied, Tie0_3_3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3727 // Convert__Reg1_2__Tie0_3_3__NEONi16splatNot1_3__VPTPredN3_0 3728 { CVT_95_Reg, 3, CVT_Tied, Tie0_3_3, CVT_95_addNEONi16splatNotOperands, 4, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 3729 // Convert__Reg1_2__Tie0_3_3__NEONi32splatNot1_3__VPTPredN3_0 3730 { CVT_95_Reg, 3, CVT_Tied, Tie0_3_3, CVT_95_addNEONi32splatNotOperands, 4, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 3731 // Convert__Reg1_1__Reg1_2__Reg1_3__VPTPredR4_0 3732 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVPTPredROperands, 1, CVT_Done }, 3733 // Convert__Reg1_2__NEONi16splat1_3__Tie0_1_1__CondCode2_0 3734 { CVT_95_Reg, 3, CVT_95_addNEONi16splatOperands, 4, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3735 // Convert__Reg1_2__NEONi32splat1_3__Tie0_1_1__CondCode2_0 3736 { CVT_95_Reg, 3, CVT_95_addNEONi32splatOperands, 4, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3737 // Convert__Reg1_2__Tie0_1_1__NEONi16splat1_3__VPTPredN3_0 3738 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addNEONi16splatOperands, 4, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 3739 // Convert__Reg1_2__Tie0_1_1__NEONi32splat1_3__VPTPredN3_0 3740 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addNEONi32splatOperands, 4, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 3741 // Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__CondCode2_0 3742 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3743 // Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0 3744 { CVT_95_Reg, 3, CVT_Tied, Tie0_3_3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3745 // Convert__Reg1_1__Reg1_2__Reg1_3__ComplexRotationOdd1_4 3746 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addComplexRotationOddOperands, 5, CVT_Done }, 3747 // Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationOdd1_5__VPTPredR4_0 3748 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addComplexRotationOddOperands, 6, CVT_95_addVPTPredROperands, 1, CVT_Done }, 3749 // Convert__Reg1_2__Reg1_2__CondCode2_0 3750 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3751 // Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__ComplexRotationEven1_4 3752 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addComplexRotationEvenOperands, 5, CVT_Done }, 3753 // Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__VectorIndex641_4__ComplexRotationEven1_5 3754 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex64Operands, 5, CVT_95_addComplexRotationEvenOperands, 6, CVT_Done }, 3755 // Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__VectorIndex321_4__ComplexRotationEven1_5 3756 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex32Operands, 5, CVT_95_addComplexRotationEvenOperands, 6, CVT_Done }, 3757 // Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__ComplexRotationEven1_5__VPTPredN3_0 3758 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addComplexRotationEvenOperands, 6, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 3759 // Convert__Reg1_2__CondCode2_0 3760 { CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3761 // Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2__VPTPredN3_0 3762 { CVT_imm_95_0, 0, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addITCondCodeOperands, 3, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 3763 // Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2__VPTPredN3_0 3764 { CVT_imm_95_0, 0, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addITCondCodeOperands, 3, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 3765 // Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedFP1_2__VPTPredN3_0 3766 { CVT_imm_95_0, 0, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addITCondCodeOperands, 3, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 3767 // Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2__VPTPredN3_0 3768 { CVT_imm_95_0, 0, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addITCondCodeOperands, 3, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 3769 // Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationEven1_5__VPTPredR4_0 3770 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addComplexRotationEvenOperands, 6, CVT_95_addVPTPredROperands, 1, CVT_Done }, 3771 // Convert__imm_95_0__Reg1_2__VPTPredN3_0 3772 { CVT_imm_95_0, 0, CVT_95_Reg, 3, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 3773 // Convert__Reg1_3__Reg1_4__CondCode2_0 3774 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3775 // Convert__Reg1_3__Reg1_4__VPTPredR4_0 3776 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVPTPredROperands, 1, CVT_Done }, 3777 // Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0 3778 { CVT_95_Reg, 4, CVT_Tied, Tie0_4_5, CVT_95_addFBits16Operands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3779 // Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0 3780 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3781 // Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0 3782 { CVT_95_Reg, 4, CVT_Tied, Tie0_4_5, CVT_95_addFBits32Operands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3783 // Convert__Reg1_3__Reg1_4__MVEVcvtImm161_5__VPTPredR4_0 3784 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addVPTPredROperands, 1, CVT_Done }, 3785 // Convert__Reg1_3__Reg1_4__MVEVcvtImm321_5__VPTPredR4_0 3786 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addVPTPredROperands, 1, CVT_Done }, 3787 // Convert__Reg1_2__Reg1_3 3788 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done }, 3789 // Convert__Reg1_3__Tie0_1_1__Reg1_4__CondCode2_0 3790 { CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3791 // Convert__Reg1_3__Tie0_1_1__Reg1_4__VPTPredN3_0 3792 { CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 3793 // Convert__Reg1_1__CoprocNum1_0__Imm11b1_2 3794 { CVT_95_Reg, 2, CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 3, CVT_Done }, 3795 // Convert__Reg1_2__CoprocNum1_1__Imm12b1_3__VPTPredR4_0 3796 { CVT_95_Reg, 3, CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 4, CVT_95_addVPTPredROperands, 1, CVT_Done }, 3797 // Convert__Reg1_1__CoprocNum1_0__Tie0_1_1__Imm11b1_2 3798 { CVT_95_Reg, 2, CVT_95_addCoprocNumOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 3, CVT_Done }, 3799 // Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Imm12b1_3__VPTPredN3_0 3800 { CVT_95_Reg, 3, CVT_95_addCoprocNumOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 4, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 3801 // Convert__Reg1_1__CoprocNum1_0__Reg1_2__Imm6b1_3 3802 { CVT_95_Reg, 2, CVT_95_addCoprocNumOperands, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done }, 3803 // Convert__Reg1_2__CoprocNum1_1__Reg1_3__Imm7b1_4__VPTPredR4_0 3804 { CVT_95_Reg, 3, CVT_95_addCoprocNumOperands, 2, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredROperands, 1, CVT_Done }, 3805 // Convert__Reg1_1__CoprocNum1_0__Tie0_1_1__Reg1_2__Imm6b1_3 3806 { CVT_95_Reg, 2, CVT_95_addCoprocNumOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done }, 3807 // Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Reg1_3__Imm7b1_4__VPTPredN3_0 3808 { CVT_95_Reg, 3, CVT_95_addCoprocNumOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 3809 // Convert__Reg1_1__CoprocNum1_0__Reg1_2__Reg1_3__Imm3b1_4 3810 { CVT_95_Reg, 2, CVT_95_addCoprocNumOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_Done }, 3811 // Convert__Reg1_2__CoprocNum1_1__Reg1_3__Reg1_4__Imm4b1_5__VPTPredR4_0 3812 { CVT_95_Reg, 3, CVT_95_addCoprocNumOperands, 2, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addVPTPredROperands, 1, CVT_Done }, 3813 // Convert__Reg1_1__CoprocNum1_0__Tie0_1_1__Reg1_2__Reg1_3__Imm3b1_4 3814 { CVT_95_Reg, 2, CVT_95_addCoprocNumOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_Done }, 3815 // Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Reg1_3__Reg1_4__Imm4b1_5__VPTPredN3_0 3816 { CVT_95_Reg, 3, CVT_95_addCoprocNumOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 3817 // Convert__Reg1_2__Reg1_3__Tie1_1_1__VIDUP_imm1_4__VPTPredR4_0 3818 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Tied, Tie1_1_1, CVT_95_addPowerTwoOperands, 5, CVT_95_addVPTPredROperands, 1, CVT_Done }, 3819 // Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3 3820 { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done }, 3821 // Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4 3822 { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex32Operands, 5, CVT_Done }, 3823 // Convert__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0 3824 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex16Operands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3825 // Convert__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0 3826 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex32Operands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3827 // Convert__Reg1_2__Reg1_3__VectorIndex81_4__CondCode2_0 3828 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex8Operands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3829 // Convert__Reg1_2__Reg1_3__Tie1_1_1__Reg1_4__VIDUP_imm1_5__VPTPredR4_0 3830 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Tied, Tie1_1_1, CVT_95_Reg, 5, CVT_95_addPowerTwoOperands, 6, CVT_95_addVPTPredROperands, 1, CVT_Done }, 3831 // Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_71_4__CondCode2_0 3832 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3833 // Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_31_4__CondCode2_0 3834 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3835 // Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_11_4__CondCode2_0 3836 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3837 // Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_151_4__CondCode2_0 3838 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3839 // Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_71_5__CondCode2_0 3840 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3841 // Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_31_5__CondCode2_0 3842 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3843 // Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_11_5__CondCode2_0 3844 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3845 // Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_151_5__CondCode2_0 3846 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3847 // Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex161_4 3848 { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex16Operands, 5, CVT_Done }, 3849 // Convert__Reg1_1__Reg1_2__Reg1_3 3850 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done }, 3851 // Convert__Reg1_1__Reg1_2__Reg1_3__VectorIndex161_4 3852 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex16Operands, 5, CVT_Done }, 3853 // Convert__Reg1_1__Reg1_2__Reg1_3__VectorIndex321_4 3854 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex32Operands, 5, CVT_Done }, 3855 // Convert__VecListDPairAllLanes1_2__DupAlignedMemory162_3__CondCode2_0 3856 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3857 // Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0 3858 { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3859 // Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0 3860 { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3861 // Convert__VecListOneDAllLanes1_2__DupAlignedMemory162_3__CondCode2_0 3862 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3863 // Convert__VecListOneD1_2__AlignedMemory642_3__CondCode2_0 3864 { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3865 // Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__CondCode2_0 3866 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3867 // Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0 3868 { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3869 // Convert__VecListDPairAllLanes1_2__DupAlignedMemory322_3__CondCode2_0 3870 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3871 // Convert__VecListOneDAllLanes1_2__DupAlignedMemory322_3__CondCode2_0 3872 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3873 // Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__CondCode2_0 3874 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3875 // Convert__VecListDPairAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0 3876 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3877 // Convert__VecListOneDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0 3878 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3879 // Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0 3880 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3881 // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0 3882 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3883 // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0 3884 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3885 // Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0 3886 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3887 // Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0 3888 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3889 // Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0 3890 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3891 // Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0 3892 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3893 // Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0 3894 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3895 // Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0 3896 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3897 // Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0 3898 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3899 // Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0 3900 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3901 // Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__Reg1_4__CondCode2_0 3902 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory16Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3903 // Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0 3904 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3905 // Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0 3906 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3907 // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0 3908 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3909 // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0 3910 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3911 // Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0 3912 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3913 // Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0 3914 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3915 // Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0 3916 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3917 // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__CondCode2_0 3918 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3919 // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0 3920 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3921 // Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__CondCode2_0 3922 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3923 // Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0 3924 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3925 // Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0 3926 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3927 // Convert__Reg1_3__AlignedMemory2_8__Tie0_1_1__Imm1_5__CondCode2_0 3928 { CVT_95_Reg, 4, CVT_95_addAlignedMemoryOperands, 9, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3929 // Convert__Reg1_3__imm_95_0__AlignedMemory2_8__Imm1_9__Tie0_1_1__Imm1_5__CondCode2_0 3930 { CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 9, CVT_95_addImmOperands, 10, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3931 // Convert__Reg1_3__Reg1_8__Imm1_9__Tie0_1_1__Imm1_5__CondCode2_0 3932 { CVT_95_Reg, 4, CVT_95_Reg, 9, CVT_95_addImmOperands, 10, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3933 // Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory322_3__CondCode2_0 3934 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3935 // Convert__VecListDPairSpaced1_2__AlignedMemory64or1282_3__CondCode2_0 3936 { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3937 // Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__CondCode2_0 3938 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3939 // Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__CondCode2_0 3940 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3941 // Convert__VecListDPairAllLanes1_2__DupAlignedMemory642_3__CondCode2_0 3942 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3943 // Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory642_3__CondCode2_0 3944 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3945 // Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__CondCode2_0 3946 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3947 // Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__CondCode2_0 3948 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3949 // Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory162_3__CondCode2_0 3950 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3951 // Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__CondCode2_0 3952 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3953 // Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0 3954 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3955 // Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0 3956 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3957 // Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0 3958 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3959 // Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0 3960 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3961 // Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0 3962 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3963 // Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0 3964 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3965 // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory642_3__CondCode2_0 3966 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3967 // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory642_3__Reg1_4__CondCode2_0 3968 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3969 // Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory642_3__CondCode2_0 3970 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3971 // Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory642_3__Reg1_4__CondCode2_0 3972 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3973 // Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0 3974 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3975 // Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0 3976 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3977 // Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0 3978 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3979 // Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0 3980 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3981 // Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__Reg1_4__CondCode2_0 3982 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory16Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3983 // Convert__VecListTwoMQ1_1__Tie0_1_1__MemNoOffsetT21_2 3984 { CVT_95_addMVEVecListOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_addMemNoOffsetT2Operands, 3, CVT_Done }, 3985 // Convert__VecListTwoMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3 3986 { CVT_95_addMVEVecListOperands, 2, CVT_95_addMemNoOffsetT2NoSpOperands, 3, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_3_3, CVT_Done }, 3987 // Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0 3988 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3989 // Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0 3990 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3991 // Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0 3992 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3993 // Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0 3994 { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3995 // Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0 3996 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3997 // Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0 3998 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3999 // Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0 4000 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4001 // Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0 4002 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4003 // Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0 4004 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4005 // Convert__VecListThreeD1_2__AlignedMemory642_3__Reg1_4__CondCode2_0 4006 { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4007 // Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0 4008 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4009 // Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0 4010 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4011 // Convert__VecListThreeQ1_2__AlignedMemory642_3__Reg1_4__CondCode2_0 4012 { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4013 // Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0 4014 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4015 // Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0 4016 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4017 // Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0 4018 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4019 // Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0 4020 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4021 // Convert__Reg1_3__Reg1_4__Reg1_5__AlignedMemory2_7__CondCode2_0 4022 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addAlignedMemoryOperands, 8, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4023 // Convert__Reg1_3__Reg1_4__Reg1_5__imm_95_0__AlignedMemory2_7__Imm1_8__CondCode2_0 4024 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 8, CVT_95_addImmOperands, 9, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4025 // Convert__Reg1_3__Reg1_6__Reg1_9__AlignedMemory2_13__CondCode2_0 4026 { CVT_95_Reg, 4, CVT_95_Reg, 7, CVT_95_Reg, 10, CVT_95_addAlignedMemoryOperands, 14, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4027 // Convert__Reg1_3__Reg1_6__Reg1_9__imm_95_0__DupAlignedMemory642_13__Imm1_14__CondCode2_0 4028 { CVT_95_Reg, 4, CVT_95_Reg, 7, CVT_95_Reg, 10, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory64Operands, 14, CVT_95_addImmOperands, 15, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4029 // Convert__VecListFourDAllLanes1_2__DupAlignedMemory642_3__CondCode2_0 4030 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4031 // Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__CondCode2_0 4032 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4033 // Convert__VecListFourQAllLanes1_2__DupAlignedMemory642_3__CondCode2_0 4034 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4035 // Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0 4036 { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4037 // Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__CondCode2_0 4038 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4039 // Convert__VecListFourDAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0 4040 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4041 // Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0 4042 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4043 // Convert__VecListFourQAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0 4044 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4045 // Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0 4046 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4047 // Convert__VecListFourDAllLanes1_2__DupAlignedMemory322_3__CondCode2_0 4048 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4049 // Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__CondCode2_0 4050 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4051 // Convert__VecListFourQAllLanes1_2__DupAlignedMemory322_3__CondCode2_0 4052 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4053 // Convert__VecListFourDAllLanes1_2__DupAlignedMemory642_3__Reg1_4__CondCode2_0 4054 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4055 // Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0 4056 { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4057 // Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0 4058 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4059 // Convert__VecListFourQAllLanes1_2__DupAlignedMemory642_3__Reg1_4__CondCode2_0 4060 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4061 // Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0 4062 { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4063 // Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0 4064 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4065 // Convert__VecListFourDAllLanes1_2__DupAlignedMemory64or1282_3__Reg1_4__CondCode2_0 4066 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4067 // Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__Reg1_4__CondCode2_0 4068 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4069 // Convert__VecListFourQAllLanes1_2__DupAlignedMemory64or1282_3__Reg1_4__CondCode2_0 4070 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4071 // Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__Reg1_4__CondCode2_0 4072 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4073 // Convert__VecListFourDAllLanes1_2__DupAlignedMemory322_3__Reg1_4__CondCode2_0 4074 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4075 // Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0 4076 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4077 // Convert__VecListFourQAllLanes1_2__DupAlignedMemory322_3__Reg1_4__CondCode2_0 4078 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4079 // Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__AlignedMemory2_8__CondCode2_0 4080 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_95_addAlignedMemoryOperands, 9, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4081 // Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__imm_95_0__AlignedMemory2_8__Imm1_9__CondCode2_0 4082 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 9, CVT_95_addImmOperands, 10, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4083 // Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__AlignedMemory2_16__CondCode2_0 4084 { CVT_95_Reg, 4, CVT_95_Reg, 7, CVT_95_Reg, 10, CVT_95_Reg, 13, CVT_95_addAlignedMemoryOperands, 17, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4085 // Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__imm_95_0__AlignedMemory2_16__Imm1_17__CondCode2_0 4086 { CVT_95_Reg, 4, CVT_95_Reg, 7, CVT_95_Reg, 10, CVT_95_Reg, 13, CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 17, CVT_95_addImmOperands, 18, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4087 // Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2 4088 { CVT_95_addMVEVecListOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_addMemNoOffsetT2Operands, 3, CVT_Done }, 4089 // Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3 4090 { CVT_95_addMVEVecListOperands, 2, CVT_95_addMemNoOffsetT2NoSpOperands, 3, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_3_3, CVT_Done }, 4091 // Convert__Reg1_1__Tie0_2_2__CondCode2_0__SPRRegList1_3 4092 { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_addCondCodeOperands, 1, CVT_95_addSPRRegListOperands, 4, CVT_Done }, 4093 // Convert__Reg1_1__CondCode2_0__SPRRegList1_2 4094 { CVT_95_Reg, 2, CVT_95_addCondCodeOperands, 1, CVT_95_addSPRRegListOperands, 3, CVT_Done }, 4095 // Convert__MemImm7s4Offset2_2__CondCode2_0 4096 { CVT_95_addMemImm7s4OffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4097 // Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0 4098 { CVT_imm_95_0, 0, CVT_95_addMemImm7s4OffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4099 // Convert__Reg1_1__AddrMode52_2__CondCode2_0 4100 { CVT_95_Reg, 2, CVT_95_addAddrMode5Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4101 // Convert__Reg1_2__AddrMode5FP162_3__CondCode2_0 4102 { CVT_95_Reg, 3, CVT_95_addAddrMode5FP16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4103 // Convert__Reg1_2__AddrMode52_3__CondCode2_0 4104 { CVT_95_Reg, 3, CVT_95_addAddrMode5Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4105 // Convert__MemNoOffsetT21_2__Tie0_3_3__Imm7s41_3__CondCode2_0 4106 { CVT_95_addMemNoOffsetT2Operands, 3, CVT_Tied, Tie0_3_3, CVT_95_addImm7s4Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4107 // Convert__imm_95_0__imm_95_0__MemImm7s4Offset2_2__CondCode2_0 4108 { CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_95_addMemImm7s4OffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4109 // Convert__imm_95_0__MemNoOffsetT21_2__Tie1_3_3__Imm7s41_3__CondCode2_0 4110 { CVT_imm_95_0, 0, CVT_95_addMemNoOffsetT2Operands, 3, CVT_Tied, Tie1_3_3, CVT_95_addImm7s4Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4111 // Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0 4112 { CVT_95_Reg, 3, CVT_95_addMemRegRQOffsetOperands, 4, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4113 // Convert__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN3_0 4114 { CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4115 // Convert__Reg1_2__MemImm7Shift0Offset2_3__VPTPredN3_0 4116 { CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4117 // Convert__MemNoOffsetT1_3__Reg1_2__Tie0_4_4__Imm7Shift01_4__VPTPredN3_0 4118 { CVT_95_addMemNoOffsetTOperands, 4, CVT_95_Reg, 3, CVT_Tied, Tie0_4_4, CVT_95_addImm7Shift0Operands, 5, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4119 // Convert__imm_95_0__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN3_0 4120 { CVT_imm_95_0, 0, CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4121 // Convert__imm_95_0__Reg1_2__MemImm7Shift0OffsetWB2_3__VPTPredN3_0 4122 { CVT_imm_95_0, 0, CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4123 // Convert__MemNoOffsetT2NoSp1_3__Reg1_2__Tie0_4_4__Imm7Shift01_4__VPTPredN3_0 4124 { CVT_95_addMemNoOffsetT2NoSpOperands, 4, CVT_95_Reg, 3, CVT_Tied, Tie0_4_4, CVT_95_addImm7Shift0Operands, 5, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4125 // Convert__Reg1_2__MemRegQS3Offset2_3__VPTPredN3_0 4126 { CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4127 // Convert__Reg1_2__MemRegRQS3Offset2_3__VPTPredN3_0 4128 { CVT_95_Reg, 3, CVT_95_addMemRegRQOffsetOperands, 4, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4129 // Convert__imm_95_0__Reg1_2__MemRegQS3Offset2_3__VPTPredN3_0 4130 { CVT_imm_95_0, 0, CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4131 // Convert__Reg1_2__MemRegRQS1Offset2_3__VPTPredN3_0 4132 { CVT_95_Reg, 3, CVT_95_addMemRegRQOffsetOperands, 4, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4133 // Convert__Reg1_2__TMemImm7Shift1Offset2_3__VPTPredN3_0 4134 { CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4135 // Convert__Reg1_2__MemImm7Shift1Offset2_3__VPTPredN3_0 4136 { CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4137 // Convert__MemNoOffsetT1_3__Reg1_2__Tie0_4_4__Imm7Shift11_4__VPTPredN3_0 4138 { CVT_95_addMemNoOffsetTOperands, 4, CVT_95_Reg, 3, CVT_Tied, Tie0_4_4, CVT_95_addImm7Shift1Operands, 5, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4139 // Convert__imm_95_0__Reg1_2__TMemImm7Shift1Offset2_3__VPTPredN3_0 4140 { CVT_imm_95_0, 0, CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4141 // Convert__imm_95_0__Reg1_2__MemImm7Shift1OffsetWB2_3__VPTPredN3_0 4142 { CVT_imm_95_0, 0, CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4143 // Convert__MemNoOffsetT2NoSp1_3__Reg1_2__Tie0_4_4__Imm7Shift11_4__VPTPredN3_0 4144 { CVT_95_addMemNoOffsetT2NoSpOperands, 4, CVT_95_Reg, 3, CVT_Tied, Tie0_4_4, CVT_95_addImm7Shift1Operands, 5, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4145 // Convert__Reg1_2__MemImm7Shift2Offset2_3__VPTPredN3_0 4146 { CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4147 // Convert__Reg1_2__MemRegQS2Offset2_3__VPTPredN3_0 4148 { CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4149 // Convert__Reg1_2__MemRegRQS2Offset2_3__VPTPredN3_0 4150 { CVT_95_Reg, 3, CVT_95_addMemRegRQOffsetOperands, 4, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4151 // Convert__imm_95_0__Reg1_2__MemImm7Shift2OffsetWB2_3__VPTPredN3_0 4152 { CVT_imm_95_0, 0, CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4153 // Convert__MemNoOffsetT2NoSp1_3__Reg1_2__Tie0_4_4__Imm7Shift21_4__VPTPredN3_0 4154 { CVT_95_addMemNoOffsetT2NoSpOperands, 4, CVT_95_Reg, 3, CVT_Tied, Tie0_4_4, CVT_95_addImm7Shift2Operands, 5, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4155 // Convert__imm_95_0__Reg1_2__MemRegQS2Offset2_3__VPTPredN3_0 4156 { CVT_imm_95_0, 0, CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4157 // Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0 4158 { CVT_95_Reg, 3, CVT_Tied, Tie0_3_3, CVT_95_Reg, 4, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4159 // Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0 4160 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVectorIndex32Operands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4161 // Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0 4162 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVectorIndex16Operands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4163 // Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0 4164 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4165 // Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN3_0 4166 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_1_1, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4167 // Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__Reg1_4__Reg1_5__VPTPredN3_0 4168 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Tied, Tie0_3_3, CVT_Tied, Tie1_4_4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4169 // Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__VPTPredN3_0 4170 { CVT_95_Reg, 3, CVT_Tied, Tie0_3_3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4171 // Convert__Reg1_1__Reg1_2__Reg1_2__CondCode2_0 4172 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4173 // Convert__Reg1_1__Reg1_2__Reg1_2__VPTPredR4_0 4174 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addVPTPredROperands, 1, CVT_Done }, 4175 // Convert__Reg1_2__FPImm1_3__CondCode2_0 4176 { CVT_95_Reg, 3, CVT_95_addFPImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4177 // Convert__Reg1_2__NEONi32vmov1_3__CondCode2_0 4178 { CVT_95_Reg, 3, CVT_95_addNEONi32vmovOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4179 // Convert__Reg1_2__NEONi16vmovi8Replicate1_3__CondCode2_0 4180 { CVT_95_Reg, 3, CVT_95_addNEONvmovi8ReplicateOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4181 // Convert__Reg1_2__NEONi16splat1_3__CondCode2_0 4182 { CVT_95_Reg, 3, CVT_95_addNEONi16splatOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4183 // Convert__Reg1_2__NEONi32vmovi8Replicate1_3__CondCode2_0 4184 { CVT_95_Reg, 3, CVT_95_addNEONvmovi8ReplicateOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4185 // Convert__Reg1_2__NEONi32vmovi16Replicate1_3__CondCode2_0 4186 { CVT_95_Reg, 3, CVT_95_addNEONvmovi16ReplicateOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4187 // Convert__Reg1_2__NEONi32vmovNeg1_3__CondCode2_0 4188 { CVT_95_Reg, 3, CVT_95_addNEONi32vmovNegOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4189 // Convert__Reg1_2__NEONi64vmovi8Replicate1_3__CondCode2_0 4190 { CVT_95_Reg, 3, CVT_95_addNEONvmovi8ReplicateOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4191 // Convert__Reg1_2__NEONi64vmovi16Replicate1_3__CondCode2_0 4192 { CVT_95_Reg, 3, CVT_95_addNEONvmovi16ReplicateOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4193 // Convert__Reg1_2__NEONi64vmovi32Replicate1_3__CondCode2_0 4194 { CVT_95_Reg, 3, CVT_95_addNEONvmovi32ReplicateOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4195 // Convert__Reg1_2__NEONi64splat1_3__CondCode2_0 4196 { CVT_95_Reg, 3, CVT_95_addNEONi64splatOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4197 // Convert__Reg1_2__NEONi8splat1_3__CondCode2_0 4198 { CVT_95_Reg, 3, CVT_95_addNEONi8splatOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4199 // Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0 4200 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4201 // Convert__Reg1_2__FPImm1_3__VPTPredR4_0 4202 { CVT_95_Reg, 3, CVT_95_addFPImmOperands, 4, CVT_95_addVPTPredROperands, 1, CVT_Done }, 4203 // Convert__Reg1_2__NEONi16splat1_3__VPTPredR4_0 4204 { CVT_95_Reg, 3, CVT_95_addNEONi16splatOperands, 4, CVT_95_addVPTPredROperands, 1, CVT_Done }, 4205 // Convert__Reg1_2__NEONi32vmov1_3__VPTPredR4_0 4206 { CVT_95_Reg, 3, CVT_95_addNEONi32vmovOperands, 4, CVT_95_addVPTPredROperands, 1, CVT_Done }, 4207 // Convert__Reg1_2__NEONi64splat1_3__VPTPredR4_0 4208 { CVT_95_Reg, 3, CVT_95_addNEONi64splatOperands, 4, CVT_95_addVPTPredROperands, 1, CVT_Done }, 4209 // Convert__Reg1_2__NEONi8splat1_3__VPTPredR4_0 4210 { CVT_95_Reg, 3, CVT_95_addNEONi8splatOperands, 4, CVT_95_addVPTPredROperands, 1, CVT_Done }, 4211 // Convert__Reg1_2__Reg1_3__MVEVectorIndex81_4__CondCode2_0 4212 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMVEVectorIndexOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4213 // Convert__Reg1_2__Reg1_3__MVEVectorIndex161_4__CondCode2_0 4214 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMVEVectorIndexOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4215 // Convert__Reg1_2__Tie0_1_1__Reg1_4__MVEVectorIndex81_3__CondCode2_0 4216 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_addMVEVectorIndexOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4217 // Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex161_3__CondCode2_0 4218 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_addVectorIndex16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4219 // Convert__Reg1_2__Tie0_1_1__Reg1_4__MVEVectorIndex41_3__CondCode2_0 4220 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_addMVEVectorIndexOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4221 // Convert__Reg1_2__Reg1_3__MVEVectorIndex41_4__CondCode2_0 4222 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMVEVectorIndexOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4223 // Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex321_3__CondCode2_0 4224 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_addVectorIndex32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4225 // Convert__Reg1_2__Tie0_1_1__Reg1_4__MVEVectorIndex161_3__CondCode2_0 4226 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_addMVEVectorIndexOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4227 // Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex81_3__CondCode2_0 4228 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_addVectorIndex8Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4229 // Convert__Reg1_1__Tie0_2_4__Reg1_5__Reg1_6__MVEPairVectorIndex21_2__MVEPairVectorIndex01_4__CondCode2_0 4230 { CVT_95_Reg, 2, CVT_Tied, Tie0_2_4, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_95_addMVEPairVectorIndexOperands, 3, CVT_95_addMVEPairVectorIndexOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4231 // ConvertCustom_cvtMVEVMOVQtoDReg 4232 { CVT_cvtMVEVMOVQtoDReg, 0, CVT_Done }, 4233 // Convert__Reg1_1__imm_95_0__CondCode2_0 4234 { CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4235 // Convert__imm_95_0__Reg1_2__CondCode2_0 4236 { CVT_imm_95_0, 0, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4237 // Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0 4238 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex32Operands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4239 // Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0 4240 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex16Operands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4241 // Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0 4242 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVectorIndex32Operands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4243 // Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0 4244 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVectorIndex16Operands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4245 // Convert__Reg1_1__Reg1_2__VPTPredR4_0 4246 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addVPTPredROperands, 1, CVT_Done }, 4247 // Convert__Reg1_2__NEONi16invi8Replicate1_3__CondCode2_0 4248 { CVT_95_Reg, 3, CVT_95_addNEONinvi8ReplicateOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4249 // Convert__Reg1_2__NEONi32invi8Replicate1_3__CondCode2_0 4250 { CVT_95_Reg, 3, CVT_95_addNEONinvi8ReplicateOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4251 // Convert__Reg1_2__NEONi64invi8Replicate1_3__CondCode2_0 4252 { CVT_95_Reg, 3, CVT_95_addNEONinvi8ReplicateOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4253 // Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0 4254 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4255 // Convert__imm_95_0__imm_95_0__VPTPredN3_0 4256 { CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4257 // Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_1 4258 { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands, 1, CVT_95_addDPRRegListOperands, 2, CVT_Done }, 4259 // Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_1 4260 { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands, 1, CVT_95_addSPRRegListOperands, 2, CVT_Done }, 4261 // Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2 4262 { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands, 1, CVT_95_addDPRRegListOperands, 3, CVT_Done }, 4263 // Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2 4264 { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands, 1, CVT_95_addSPRRegListOperands, 3, CVT_Done }, 4265 // Convert__Reg1_1__Reg1_2__Reg1_3__VPTPredN3_0 4266 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4267 // Convert__ITMask1_0 4268 { CVT_95_addITMaskOperands, 1, CVT_Done }, 4269 // Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2 4270 { CVT_95_addITMaskOperands, 1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addITCondCodeOperands, 3, CVT_Done }, 4271 // Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2 4272 { CVT_95_addITMaskOperands, 1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addITCondCodeOperands, 3, CVT_Done }, 4273 // Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedFP1_2 4274 { CVT_95_addITMaskOperands, 1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addITCondCodeOperands, 3, CVT_Done }, 4275 // Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2 4276 { CVT_95_addITMaskOperands, 1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addITCondCodeOperands, 3, CVT_Done }, 4277 // Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0 4278 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4279 // Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0 4280 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4281 // Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0 4282 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4283 // Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0 4284 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4285 // Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0 4286 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4287 // Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0 4288 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4289 // Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0 4290 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4291 // Convert__Reg1_2__Reg1_3__Imm0_151_4__VPTPredR4_0 4292 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredROperands, 1, CVT_Done }, 4293 // Convert__Reg1_2__Reg1_3__Imm0_311_4__VPTPredR4_0 4294 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredROperands, 1, CVT_Done }, 4295 // Convert__Reg1_2__Reg1_3__Imm0_71_4__VPTPredR4_0 4296 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredROperands, 1, CVT_Done }, 4297 // Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0 4298 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4299 // Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0 4300 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4301 // Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0 4302 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4303 // Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0 4304 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4305 // Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0 4306 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4307 // Convert__Reg1_2__Reg1_3__ShrImm161_4__VPTPredR4_0 4308 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredROperands, 1, CVT_Done }, 4309 // Convert__Reg1_2__Reg1_3__ShrImm321_4__VPTPredR4_0 4310 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredROperands, 1, CVT_Done }, 4311 // Convert__Reg1_2__Reg1_3__ShrImm81_4__VPTPredR4_0 4312 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredROperands, 1, CVT_Done }, 4313 // Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0 4314 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4315 // Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0 4316 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4317 // Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0 4318 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4319 // Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0 4320 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4321 // Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0 4322 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4323 // Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0 4324 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4325 // Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0 4326 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4327 // Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0 4328 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4329 // Convert__CondCode2_0__FPDRegListWithVPR1_1 4330 { CVT_95_addCondCodeOperands, 1, CVT_95_addFPDRegListWithVPROperands, 2, CVT_Done }, 4331 // Convert__CondCode2_0__FPSRegListWithVPR1_1 4332 { CVT_95_addCondCodeOperands, 1, CVT_95_addFPSRegListWithVPROperands, 2, CVT_Done }, 4333 // Convert__Reg1_2__Reg1_1__Tie1_2_2__Tie0_3_3__MVELongShift1_3__VPTPredN3_0 4334 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Tied, Tie1_2_2, CVT_Tied, Tie0_3_3, CVT_95_addImmOperands, 4, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4335 // Convert__Reg1_2__Reg1_3__Imm1_151_4__CondCode2_0 4336 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4337 // Convert__Reg1_2__Reg1_3__Imm1_311_4__CondCode2_0 4338 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4339 // Convert__Reg1_2__Reg1_3__Imm1_71_4__CondCode2_0 4340 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4341 // Convert__Reg1_2__Reg1_3__Imm161_4__CondCode2_0 4342 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4343 // Convert__Reg1_2__Reg1_3__Imm321_4__CondCode2_0 4344 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4345 // Convert__Reg1_2__Reg1_3__Imm81_4__CondCode2_0 4346 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4347 // Convert__Reg1_2__Reg1_3__MVEShiftImm1_151_4__VPTPredR4_0 4348 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredROperands, 1, CVT_Done }, 4349 // Convert__Reg1_2__Reg1_3__MVEShiftImm1_71_4__VPTPredR4_0 4350 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredROperands, 1, CVT_Done }, 4351 // Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0 4352 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4353 // Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0 4354 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4355 // Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm0_151_4__VPTPredN3_0 4356 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4357 // Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm0_311_4__VPTPredN3_0 4358 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4359 // Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm0_71_4__VPTPredN3_0 4360 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4361 // Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__VPTPredN3_0 4362 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredNOperands, 1, CVT_Done }, 4363 // Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0 4364 { CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4365 // Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0 4366 { CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4367 // Convert__AlignedMemory642_3__VecListOneD1_2__CondCode2_0 4368 { CVT_95_addAlignedMemory64Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4369 // Convert__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0 4370 { CVT_95_addAlignedMemory64Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4371 // Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0 4372 { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4373 // Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0 4374 { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4375 // Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0 4376 { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4377 // Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0 4378 { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_Reg, 5, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4379 // Convert__imm_95_0__AlignedMemory642_3__VecListOneD1_2__CondCode2_0 4380 { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4381 // Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListOneD1_2__CondCode2_0 4382 { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4383 // Convert__imm_95_0__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0 4384 { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4385 // Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListThreeD1_2__CondCode2_0 4386 { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4387 // Convert__AlignedMemory2_8__Reg1_3__Imm1_5__CondCode2_0 4388 { CVT_95_addAlignedMemoryOperands, 9, CVT_95_Reg, 4, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4389 // Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Imm1_5__CondCode2_0 4390 { CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 9, CVT_95_addImmOperands, 10, CVT_95_Reg, 4, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4391 // Convert__Reg1_8__Imm1_9__Reg1_3__Imm1_5__CondCode2_0 4392 { CVT_95_Reg, 9, CVT_95_addImmOperands, 10, CVT_95_Reg, 4, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4393 // Convert__imm_95_0__Reg1_8__Imm1_9__Imm1_10__Reg1_3__Imm1_5__CondCode2_0 4394 { CVT_imm_95_0, 0, CVT_95_Reg, 9, CVT_95_addImmOperands, 10, CVT_95_addImmOperands, 11, CVT_95_Reg, 4, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4395 // Convert__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0 4396 { CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4397 // Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0 4398 { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4399 // Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPairSpaced1_2__CondCode2_0 4400 { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4401 // Convert__VecListTwoMQ1_1__MemNoOffsetT21_2 4402 { CVT_95_addMVEVecListOperands, 2, CVT_95_addMemNoOffsetT2Operands, 3, CVT_Done }, 4403 // Convert__MemNoOffsetT2NoSp1_2__VecListTwoMQ1_1__Tie0_3_3 4404 { CVT_95_addMemNoOffsetT2NoSpOperands, 3, CVT_95_addMVEVecListOperands, 2, CVT_Tied, Tie0_3_3, CVT_Done }, 4405 // Convert__AlignedMemory2_7__Reg1_3__Reg1_4__Reg1_5__CondCode2_0 4406 { CVT_95_addAlignedMemoryOperands, 8, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4407 // Convert__imm_95_0__AlignedMemory2_7__Imm1_8__Reg1_3__Reg1_4__Reg1_5__CondCode2_0 4408 { CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 8, CVT_95_addImmOperands, 9, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4409 // Convert__AlignedMemory2_8__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0 4410 { CVT_95_addAlignedMemoryOperands, 9, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4411 // Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0 4412 { CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 9, CVT_95_addImmOperands, 10, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4413 // Convert__VecListFourMQ1_1__MemNoOffsetT21_2 4414 { CVT_95_addMVEVecListOperands, 2, CVT_95_addMemNoOffsetT2Operands, 3, CVT_Done }, 4415 // Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3 4416 { CVT_95_addMemNoOffsetT2NoSpOperands, 3, CVT_95_addMVEVecListOperands, 2, CVT_Tied, Tie0_3_3, CVT_Done }, 4417 // Convert__MemNoOffsetT21_2__imm_95_0__Tie0_3_3__Imm7s41_3__CondCode2_0 4418 { CVT_95_addMemNoOffsetT2Operands, 3, CVT_imm_95_0, 0, CVT_Tied, Tie0_3_3, CVT_95_addImm7s4Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4419 // Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__CondCode2_0 4420 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_1_1, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4421 // Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0 4422 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Tied, Tie0_3_3, CVT_Tied, Tie1_4_4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4423 // Convert__Reg1_2__VecListDPair1_3__Reg1_4__CondCode2_0 4424 { CVT_95_Reg, 3, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4425 // Convert__Reg1_2__VecListFourD1_3__Reg1_4__CondCode2_0 4426 { CVT_95_Reg, 3, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4427 // Convert__Reg1_2__VecListOneD1_3__Reg1_4__CondCode2_0 4428 { CVT_95_Reg, 3, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4429 // Convert__Reg1_2__VecListThreeD1_3__Reg1_4__CondCode2_0 4430 { CVT_95_Reg, 3, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4431 // Convert__Reg1_2__Tie0_1_1__VecListDPair1_3__Reg1_4__CondCode2_0 4432 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4433 // Convert__Reg1_2__Tie0_1_1__VecListFourD1_3__Reg1_4__CondCode2_0 4434 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4435 // Convert__Reg1_2__Tie0_1_1__VecListOneD1_3__Reg1_4__CondCode2_0 4436 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4437 // Convert__Reg1_2__Tie0_1_1__VecListThreeD1_3__Reg1_4__CondCode2_0 4438 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4439 // Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0 4440 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_1_1, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4441 // Convert__imm_95_2__CondCode2_0 4442 { CVT_imm_95_2, 0, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4443 // Convert__imm_95_3__CondCode2_0 4444 { CVT_imm_95_3, 0, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4445 // Convert__Reg1_0__Reg1_1__WLSLabel1_2 4446 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done }, 4447 // Convert__Reg1_1__Reg1_2__WLSLabel1_3 4448 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done }, 4449 // Convert__imm_95_1__CondCode2_0 4450 { CVT_imm_95_1, 0, CVT_95_addCondCodeOperands, 1, CVT_Done }, 4451}; 4452 4453void ARMAsmParser:: 4454convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode, 4455 const OperandVector &Operands) { 4456 assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!"); 4457 const uint8_t *Converter = ConversionTable[Kind]; 4458 unsigned OpIdx; 4459 Inst.setOpcode(Opcode); 4460 for (const uint8_t *p = Converter; *p; p += 2) { 4461 OpIdx = *(p + 1); 4462 switch (*p) { 4463 default: llvm_unreachable("invalid conversion entry!"); 4464 case CVT_Reg: 4465 static_cast<ARMOperand &>(*Operands[OpIdx]).addRegOperands(Inst, 1); 4466 break; 4467 case CVT_Tied: { 4468 assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) - 4469 std::begin(TiedAsmOperandTable)) && 4470 "Tied operand not found"); 4471 unsigned TiedResOpnd = TiedAsmOperandTable[OpIdx][0]; 4472 if (TiedResOpnd != (uint8_t)-1) 4473 Inst.addOperand(Inst.getOperand(TiedResOpnd)); 4474 break; 4475 } 4476 case CVT_95_Reg: 4477 static_cast<ARMOperand &>(*Operands[OpIdx]).addRegOperands(Inst, 1); 4478 break; 4479 case CVT_95_addCCOutOperands: 4480 static_cast<ARMOperand &>(*Operands[OpIdx]).addCCOutOperands(Inst, 1); 4481 break; 4482 case CVT_95_addCondCodeOperands: 4483 static_cast<ARMOperand &>(*Operands[OpIdx]).addCondCodeOperands(Inst, 2); 4484 break; 4485 case CVT_95_addRegShiftedRegOperands: 4486 static_cast<ARMOperand &>(*Operands[OpIdx]).addRegShiftedRegOperands(Inst, 3); 4487 break; 4488 case CVT_95_addModImmOperands: 4489 static_cast<ARMOperand &>(*Operands[OpIdx]).addModImmOperands(Inst, 1); 4490 break; 4491 case CVT_95_addModImmNotOperands: 4492 static_cast<ARMOperand &>(*Operands[OpIdx]).addModImmNotOperands(Inst, 1); 4493 break; 4494 case CVT_95_addRegShiftedImmOperands: 4495 static_cast<ARMOperand &>(*Operands[OpIdx]).addRegShiftedImmOperands(Inst, 2); 4496 break; 4497 case CVT_95_addImmOperands: 4498 static_cast<ARMOperand &>(*Operands[OpIdx]).addImmOperands(Inst, 1); 4499 break; 4500 case CVT_95_addT2SOImmNotOperands: 4501 static_cast<ARMOperand &>(*Operands[OpIdx]).addT2SOImmNotOperands(Inst, 1); 4502 break; 4503 case CVT_95_addImm0_95_4095NegOperands: 4504 static_cast<ARMOperand &>(*Operands[OpIdx]).addImm0_4095NegOperands(Inst, 1); 4505 break; 4506 case CVT_95_addImm0_95_508s4Operands: 4507 static_cast<ARMOperand &>(*Operands[OpIdx]).addImm0_508s4Operands(Inst, 1); 4508 break; 4509 case CVT_regSP: 4510 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4511 break; 4512 case CVT_95_addImm0_95_508s4NegOperands: 4513 static_cast<ARMOperand &>(*Operands[OpIdx]).addImm0_508s4NegOperands(Inst, 1); 4514 break; 4515 case CVT_95_addT2SOImmNegOperands: 4516 static_cast<ARMOperand &>(*Operands[OpIdx]).addT2SOImmNegOperands(Inst, 1); 4517 break; 4518 case CVT_95_addThumbModImmNeg8_95_255Operands: 4519 static_cast<ARMOperand &>(*Operands[OpIdx]).addThumbModImmNeg8_255Operands(Inst, 1); 4520 break; 4521 case CVT_95_addModImmNegOperands: 4522 static_cast<ARMOperand &>(*Operands[OpIdx]).addModImmNegOperands(Inst, 1); 4523 break; 4524 case CVT_95_addImm0_95_1020s4Operands: 4525 static_cast<ARMOperand &>(*Operands[OpIdx]).addImm0_1020s4Operands(Inst, 1); 4526 break; 4527 case CVT_95_addThumbModImmNeg1_95_7Operands: 4528 static_cast<ARMOperand &>(*Operands[OpIdx]).addThumbModImmNeg1_7Operands(Inst, 1); 4529 break; 4530 case CVT_95_addUnsignedOffset_95_b8s2Operands: 4531 static_cast<ARMOperand &>(*Operands[OpIdx]).addUnsignedOffset_b8s2Operands(Inst, 1); 4532 break; 4533 case CVT_95_addAdrLabelOperands: 4534 static_cast<ARMOperand &>(*Operands[OpIdx]).addAdrLabelOperands(Inst, 1); 4535 break; 4536 case CVT_imm_95_45: 4537 Inst.addOperand(MCOperand::createImm(45)); 4538 break; 4539 case CVT_95_addARMBranchTargetOperands: 4540 static_cast<ARMOperand &>(*Operands[OpIdx]).addARMBranchTargetOperands(Inst, 1); 4541 break; 4542 case CVT_cvtThumbBranches: 4543 cvtThumbBranches(Inst, Operands); 4544 break; 4545 case CVT_95_addBitfieldOperands: 4546 static_cast<ARMOperand &>(*Operands[OpIdx]).addBitfieldOperands(Inst, 1); 4547 break; 4548 case CVT_95_addITCondCodeOperands: 4549 static_cast<ARMOperand &>(*Operands[OpIdx]).addITCondCodeOperands(Inst, 1); 4550 break; 4551 case CVT_imm_95_0: 4552 Inst.addOperand(MCOperand::createImm(0)); 4553 break; 4554 case CVT_95_addThumbBranchTargetOperands: 4555 static_cast<ARMOperand &>(*Operands[OpIdx]).addThumbBranchTargetOperands(Inst, 1); 4556 break; 4557 case CVT_imm_95_15: 4558 Inst.addOperand(MCOperand::createImm(15)); 4559 break; 4560 case CVT_95_addCoprocNumOperands: 4561 static_cast<ARMOperand &>(*Operands[OpIdx]).addCoprocNumOperands(Inst, 1); 4562 break; 4563 case CVT_95_addCoprocRegOperands: 4564 static_cast<ARMOperand &>(*Operands[OpIdx]).addCoprocRegOperands(Inst, 1); 4565 break; 4566 case CVT_95_addITCondCodeInvOperands: 4567 static_cast<ARMOperand &>(*Operands[OpIdx]).addITCondCodeInvOperands(Inst, 1); 4568 break; 4569 case CVT_imm_95_22: 4570 Inst.addOperand(MCOperand::createImm(22)); 4571 break; 4572 case CVT_95_addRegListWithAPSROperands: 4573 static_cast<ARMOperand &>(*Operands[OpIdx]).addRegListWithAPSROperands(Inst, 1); 4574 break; 4575 case CVT_95_addProcIFlagsOperands: 4576 static_cast<ARMOperand &>(*Operands[OpIdx]).addProcIFlagsOperands(Inst, 1); 4577 break; 4578 case CVT_imm_95_20: 4579 Inst.addOperand(MCOperand::createImm(20)); 4580 break; 4581 case CVT_regZR: 4582 Inst.addOperand(MCOperand::createReg(ARM::ZR)); 4583 break; 4584 case CVT_imm_95_12: 4585 Inst.addOperand(MCOperand::createImm(12)); 4586 break; 4587 case CVT_95_addMemBarrierOptOperands: 4588 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemBarrierOptOperands(Inst, 1); 4589 break; 4590 case CVT_imm_95_16: 4591 Inst.addOperand(MCOperand::createImm(16)); 4592 break; 4593 case CVT_95_addFPImmOperands: 4594 static_cast<ARMOperand &>(*Operands[OpIdx]).addFPImmOperands(Inst, 1); 4595 break; 4596 case CVT_95_addDPRRegListOperands: 4597 static_cast<ARMOperand &>(*Operands[OpIdx]).addDPRRegListOperands(Inst, 1); 4598 break; 4599 case CVT_imm_95_1: 4600 Inst.addOperand(MCOperand::createImm(1)); 4601 break; 4602 case CVT_95_addInstSyncBarrierOptOperands: 4603 static_cast<ARMOperand &>(*Operands[OpIdx]).addInstSyncBarrierOptOperands(Inst, 1); 4604 break; 4605 case CVT_95_addITMaskOperands: 4606 static_cast<ARMOperand &>(*Operands[OpIdx]).addITMaskOperands(Inst, 1); 4607 break; 4608 case CVT_95_addMemNoOffsetOperands: 4609 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemNoOffsetOperands(Inst, 1); 4610 break; 4611 case CVT_95_addAddrMode5Operands: 4612 static_cast<ARMOperand &>(*Operands[OpIdx]).addAddrMode5Operands(Inst, 2); 4613 break; 4614 case CVT_95_addCoprocOptionOperands: 4615 static_cast<ARMOperand &>(*Operands[OpIdx]).addCoprocOptionOperands(Inst, 1); 4616 break; 4617 case CVT_95_addPostIdxImm8s4Operands: 4618 static_cast<ARMOperand &>(*Operands[OpIdx]).addPostIdxImm8s4Operands(Inst, 1); 4619 break; 4620 case CVT_95_addRegListOperands: 4621 static_cast<ARMOperand &>(*Operands[OpIdx]).addRegListOperands(Inst, 1); 4622 break; 4623 case CVT_95_addThumbMemPCOperands: 4624 static_cast<ARMOperand &>(*Operands[OpIdx]).addThumbMemPCOperands(Inst, 1); 4625 break; 4626 case CVT_95_addConstPoolAsmImmOperands: 4627 static_cast<ARMOperand &>(*Operands[OpIdx]).addConstPoolAsmImmOperands(Inst, 1); 4628 break; 4629 case CVT_95_addMemThumbRIs4Operands: 4630 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemThumbRIs4Operands(Inst, 2); 4631 break; 4632 case CVT_95_addMemThumbRROperands: 4633 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemThumbRROperands(Inst, 2); 4634 break; 4635 case CVT_95_addMemThumbSPIOperands: 4636 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemThumbSPIOperands(Inst, 2); 4637 break; 4638 case CVT_95_addMemImm12OffsetOperands: 4639 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemImm12OffsetOperands(Inst, 2); 4640 break; 4641 case CVT_95_addMemImmOffsetOperands: 4642 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemImmOffsetOperands(Inst, 2); 4643 break; 4644 case CVT_95_addMemRegOffsetOperands: 4645 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemRegOffsetOperands(Inst, 3); 4646 break; 4647 case CVT_95_addMemUImm12OffsetOperands: 4648 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemUImm12OffsetOperands(Inst, 2); 4649 break; 4650 case CVT_95_addT2MemRegOffsetOperands: 4651 static_cast<ARMOperand &>(*Operands[OpIdx]).addT2MemRegOffsetOperands(Inst, 3); 4652 break; 4653 case CVT_95_addMemPCRelImm12Operands: 4654 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemPCRelImm12Operands(Inst, 1); 4655 break; 4656 case CVT_95_addAM2OffsetImmOperands: 4657 static_cast<ARMOperand &>(*Operands[OpIdx]).addAM2OffsetImmOperands(Inst, 2); 4658 break; 4659 case CVT_95_addPostIdxRegShiftedOperands: 4660 static_cast<ARMOperand &>(*Operands[OpIdx]).addPostIdxRegShiftedOperands(Inst, 2); 4661 break; 4662 case CVT_95_addMemThumbRIs1Operands: 4663 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemThumbRIs1Operands(Inst, 2); 4664 break; 4665 case CVT_95_addMemImm8s4OffsetOperands: 4666 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemImm8s4OffsetOperands(Inst, 2); 4667 break; 4668 case CVT_95_addAddrMode3Operands: 4669 static_cast<ARMOperand &>(*Operands[OpIdx]).addAddrMode3Operands(Inst, 3); 4670 break; 4671 case CVT_95_addAM3OffsetOperands: 4672 static_cast<ARMOperand &>(*Operands[OpIdx]).addAM3OffsetOperands(Inst, 2); 4673 break; 4674 case CVT_95_addMemImm0_95_1020s4OffsetOperands: 4675 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemImm0_1020s4OffsetOperands(Inst, 2); 4676 break; 4677 case CVT_95_addMemThumbRIs2Operands: 4678 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemThumbRIs2Operands(Inst, 2); 4679 break; 4680 case CVT_95_addPostIdxRegOperands: 4681 static_cast<ARMOperand &>(*Operands[OpIdx]).addPostIdxRegOperands(Inst, 2); 4682 break; 4683 case CVT_95_addPostIdxImm8Operands: 4684 static_cast<ARMOperand &>(*Operands[OpIdx]).addPostIdxImm8Operands(Inst, 1); 4685 break; 4686 case CVT_reg0: 4687 Inst.addOperand(MCOperand::createReg(0)); 4688 break; 4689 case CVT_regCPSR: 4690 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 4691 break; 4692 case CVT_imm_95_14: 4693 Inst.addOperand(MCOperand::createImm(14)); 4694 break; 4695 case CVT_95_addBankedRegOperands: 4696 static_cast<ARMOperand &>(*Operands[OpIdx]).addBankedRegOperands(Inst, 1); 4697 break; 4698 case CVT_95_addMSRMaskOperands: 4699 static_cast<ARMOperand &>(*Operands[OpIdx]).addMSRMaskOperands(Inst, 1); 4700 break; 4701 case CVT_cvtThumbMultiply: 4702 cvtThumbMultiply(Inst, Operands); 4703 break; 4704 case CVT_regR8: 4705 Inst.addOperand(MCOperand::createReg(ARM::R8)); 4706 break; 4707 case CVT_regR0: 4708 Inst.addOperand(MCOperand::createReg(ARM::R0)); 4709 break; 4710 case CVT_imm_95_29: 4711 Inst.addOperand(MCOperand::createImm(29)); 4712 break; 4713 case CVT_imm_95_13: 4714 Inst.addOperand(MCOperand::createImm(13)); 4715 break; 4716 case CVT_95_addPKHASRImmOperands: 4717 static_cast<ARMOperand &>(*Operands[OpIdx]).addPKHASRImmOperands(Inst, 1); 4718 break; 4719 case CVT_imm_95_4: 4720 Inst.addOperand(MCOperand::createImm(4)); 4721 break; 4722 case CVT_95_addImm1_95_32Operands: 4723 static_cast<ARMOperand &>(*Operands[OpIdx]).addImm1_32Operands(Inst, 1); 4724 break; 4725 case CVT_imm_95_5: 4726 Inst.addOperand(MCOperand::createImm(5)); 4727 break; 4728 case CVT_95_addMveSaturateOperands: 4729 static_cast<ARMOperand &>(*Operands[OpIdx]).addMveSaturateOperands(Inst, 1); 4730 break; 4731 case CVT_95_addShifterImmOperands: 4732 static_cast<ARMOperand &>(*Operands[OpIdx]).addShifterImmOperands(Inst, 1); 4733 break; 4734 case CVT_95_addImm1_95_16Operands: 4735 static_cast<ARMOperand &>(*Operands[OpIdx]).addImm1_16Operands(Inst, 1); 4736 break; 4737 case CVT_95_addRotImmOperands: 4738 static_cast<ARMOperand &>(*Operands[OpIdx]).addRotImmOperands(Inst, 1); 4739 break; 4740 case CVT_95_addMemTBBOperands: 4741 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemTBBOperands(Inst, 2); 4742 break; 4743 case CVT_95_addMemTBHOperands: 4744 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemTBHOperands(Inst, 2); 4745 break; 4746 case CVT_95_addTraceSyncBarrierOptOperands: 4747 static_cast<ARMOperand &>(*Operands[OpIdx]).addTraceSyncBarrierOptOperands(Inst, 1); 4748 break; 4749 case CVT_95_addVPTPredNOperands: 4750 static_cast<ARMOperand &>(*Operands[OpIdx]).addVPTPredNOperands(Inst, 3); 4751 break; 4752 case CVT_95_addVPTPredROperands: 4753 static_cast<ARMOperand &>(*Operands[OpIdx]).addVPTPredROperands(Inst, 4); 4754 break; 4755 case CVT_95_addNEONi16splatNotOperands: 4756 static_cast<ARMOperand &>(*Operands[OpIdx]).addNEONi16splatNotOperands(Inst, 1); 4757 break; 4758 case CVT_95_addNEONi32splatNotOperands: 4759 static_cast<ARMOperand &>(*Operands[OpIdx]).addNEONi32splatNotOperands(Inst, 1); 4760 break; 4761 case CVT_95_addNEONi16splatOperands: 4762 static_cast<ARMOperand &>(*Operands[OpIdx]).addNEONi16splatOperands(Inst, 1); 4763 break; 4764 case CVT_95_addNEONi32splatOperands: 4765 static_cast<ARMOperand &>(*Operands[OpIdx]).addNEONi32splatOperands(Inst, 1); 4766 break; 4767 case CVT_95_addComplexRotationOddOperands: 4768 static_cast<ARMOperand &>(*Operands[OpIdx]).addComplexRotationOddOperands(Inst, 1); 4769 break; 4770 case CVT_95_addComplexRotationEvenOperands: 4771 static_cast<ARMOperand &>(*Operands[OpIdx]).addComplexRotationEvenOperands(Inst, 1); 4772 break; 4773 case CVT_95_addVectorIndex64Operands: 4774 static_cast<ARMOperand &>(*Operands[OpIdx]).addVectorIndex64Operands(Inst, 1); 4775 break; 4776 case CVT_95_addVectorIndex32Operands: 4777 static_cast<ARMOperand &>(*Operands[OpIdx]).addVectorIndex32Operands(Inst, 1); 4778 break; 4779 case CVT_95_addFBits16Operands: 4780 static_cast<ARMOperand &>(*Operands[OpIdx]).addFBits16Operands(Inst, 1); 4781 break; 4782 case CVT_95_addFBits32Operands: 4783 static_cast<ARMOperand &>(*Operands[OpIdx]).addFBits32Operands(Inst, 1); 4784 break; 4785 case CVT_95_addPowerTwoOperands: 4786 static_cast<ARMOperand &>(*Operands[OpIdx]).addPowerTwoOperands(Inst, 1); 4787 break; 4788 case CVT_95_addVectorIndex16Operands: 4789 static_cast<ARMOperand &>(*Operands[OpIdx]).addVectorIndex16Operands(Inst, 1); 4790 break; 4791 case CVT_95_addVectorIndex8Operands: 4792 static_cast<ARMOperand &>(*Operands[OpIdx]).addVectorIndex8Operands(Inst, 1); 4793 break; 4794 case CVT_95_addVecListOperands: 4795 static_cast<ARMOperand &>(*Operands[OpIdx]).addVecListOperands(Inst, 1); 4796 break; 4797 case CVT_95_addDupAlignedMemory16Operands: 4798 static_cast<ARMOperand &>(*Operands[OpIdx]).addDupAlignedMemory16Operands(Inst, 2); 4799 break; 4800 case CVT_95_addAlignedMemory64or128Operands: 4801 static_cast<ARMOperand &>(*Operands[OpIdx]).addAlignedMemory64or128Operands(Inst, 2); 4802 break; 4803 case CVT_95_addAlignedMemory64or128or256Operands: 4804 static_cast<ARMOperand &>(*Operands[OpIdx]).addAlignedMemory64or128or256Operands(Inst, 2); 4805 break; 4806 case CVT_95_addAlignedMemory64Operands: 4807 static_cast<ARMOperand &>(*Operands[OpIdx]).addAlignedMemory64Operands(Inst, 2); 4808 break; 4809 case CVT_95_addVecListIndexedOperands: 4810 static_cast<ARMOperand &>(*Operands[OpIdx]).addVecListIndexedOperands(Inst, 2); 4811 break; 4812 case CVT_95_addAlignedMemory16Operands: 4813 static_cast<ARMOperand &>(*Operands[OpIdx]).addAlignedMemory16Operands(Inst, 2); 4814 break; 4815 case CVT_95_addDupAlignedMemory32Operands: 4816 static_cast<ARMOperand &>(*Operands[OpIdx]).addDupAlignedMemory32Operands(Inst, 2); 4817 break; 4818 case CVT_95_addAlignedMemory32Operands: 4819 static_cast<ARMOperand &>(*Operands[OpIdx]).addAlignedMemory32Operands(Inst, 2); 4820 break; 4821 case CVT_95_addDupAlignedMemoryNoneOperands: 4822 static_cast<ARMOperand &>(*Operands[OpIdx]).addDupAlignedMemoryNoneOperands(Inst, 2); 4823 break; 4824 case CVT_95_addAlignedMemoryNoneOperands: 4825 static_cast<ARMOperand &>(*Operands[OpIdx]).addAlignedMemoryNoneOperands(Inst, 2); 4826 break; 4827 case CVT_95_addAlignedMemoryOperands: 4828 static_cast<ARMOperand &>(*Operands[OpIdx]).addAlignedMemoryOperands(Inst, 2); 4829 break; 4830 case CVT_95_addDupAlignedMemory64Operands: 4831 static_cast<ARMOperand &>(*Operands[OpIdx]).addDupAlignedMemory64Operands(Inst, 2); 4832 break; 4833 case CVT_95_addMVEVecListOperands: 4834 static_cast<ARMOperand &>(*Operands[OpIdx]).addMVEVecListOperands(Inst, 1); 4835 break; 4836 case CVT_95_addMemNoOffsetT2Operands: 4837 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemNoOffsetT2Operands(Inst, 1); 4838 break; 4839 case CVT_95_addMemNoOffsetT2NoSpOperands: 4840 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemNoOffsetT2NoSpOperands(Inst, 1); 4841 break; 4842 case CVT_95_addDupAlignedMemory64or128Operands: 4843 static_cast<ARMOperand &>(*Operands[OpIdx]).addDupAlignedMemory64or128Operands(Inst, 2); 4844 break; 4845 case CVT_95_addSPRRegListOperands: 4846 static_cast<ARMOperand &>(*Operands[OpIdx]).addSPRRegListOperands(Inst, 1); 4847 break; 4848 case CVT_95_addMemImm7s4OffsetOperands: 4849 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemImm7s4OffsetOperands(Inst, 2); 4850 break; 4851 case CVT_95_addAddrMode5FP16Operands: 4852 static_cast<ARMOperand &>(*Operands[OpIdx]).addAddrMode5FP16Operands(Inst, 2); 4853 break; 4854 case CVT_95_addImm7s4Operands: 4855 static_cast<ARMOperand &>(*Operands[OpIdx]).addImm7s4Operands(Inst, 1); 4856 break; 4857 case CVT_95_addMemRegRQOffsetOperands: 4858 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemRegRQOffsetOperands(Inst, 2); 4859 break; 4860 case CVT_95_addMemNoOffsetTOperands: 4861 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemNoOffsetTOperands(Inst, 1); 4862 break; 4863 case CVT_95_addImm7Shift0Operands: 4864 static_cast<ARMOperand &>(*Operands[OpIdx]).addImm7Shift0Operands(Inst, 1); 4865 break; 4866 case CVT_95_addImm7Shift1Operands: 4867 static_cast<ARMOperand &>(*Operands[OpIdx]).addImm7Shift1Operands(Inst, 1); 4868 break; 4869 case CVT_95_addImm7Shift2Operands: 4870 static_cast<ARMOperand &>(*Operands[OpIdx]).addImm7Shift2Operands(Inst, 1); 4871 break; 4872 case CVT_95_addNEONi32vmovOperands: 4873 static_cast<ARMOperand &>(*Operands[OpIdx]).addNEONi32vmovOperands(Inst, 1); 4874 break; 4875 case CVT_95_addNEONvmovi8ReplicateOperands: 4876 static_cast<ARMOperand &>(*Operands[OpIdx]).addNEONvmovi8ReplicateOperands(Inst, 1); 4877 break; 4878 case CVT_95_addNEONvmovi16ReplicateOperands: 4879 static_cast<ARMOperand &>(*Operands[OpIdx]).addNEONvmovi16ReplicateOperands(Inst, 1); 4880 break; 4881 case CVT_95_addNEONi32vmovNegOperands: 4882 static_cast<ARMOperand &>(*Operands[OpIdx]).addNEONi32vmovNegOperands(Inst, 1); 4883 break; 4884 case CVT_95_addNEONvmovi32ReplicateOperands: 4885 static_cast<ARMOperand &>(*Operands[OpIdx]).addNEONvmovi32ReplicateOperands(Inst, 1); 4886 break; 4887 case CVT_95_addNEONi64splatOperands: 4888 static_cast<ARMOperand &>(*Operands[OpIdx]).addNEONi64splatOperands(Inst, 1); 4889 break; 4890 case CVT_95_addNEONi8splatOperands: 4891 static_cast<ARMOperand &>(*Operands[OpIdx]).addNEONi8splatOperands(Inst, 1); 4892 break; 4893 case CVT_95_addMVEVectorIndexOperands: 4894 static_cast<ARMOperand &>(*Operands[OpIdx]).addMVEVectorIndexOperands(Inst, 1); 4895 break; 4896 case CVT_95_addMVEPairVectorIndexOperands: 4897 static_cast<ARMOperand &>(*Operands[OpIdx]).addMVEPairVectorIndexOperands(Inst, 1); 4898 break; 4899 case CVT_cvtMVEVMOVQtoDReg: 4900 cvtMVEVMOVQtoDReg(Inst, Operands); 4901 break; 4902 case CVT_95_addNEONinvi8ReplicateOperands: 4903 static_cast<ARMOperand &>(*Operands[OpIdx]).addNEONinvi8ReplicateOperands(Inst, 1); 4904 break; 4905 case CVT_95_addFPDRegListWithVPROperands: 4906 static_cast<ARMOperand &>(*Operands[OpIdx]).addFPDRegListWithVPROperands(Inst, 1); 4907 break; 4908 case CVT_95_addFPSRegListWithVPROperands: 4909 static_cast<ARMOperand &>(*Operands[OpIdx]).addFPSRegListWithVPROperands(Inst, 1); 4910 break; 4911 case CVT_imm_95_2: 4912 Inst.addOperand(MCOperand::createImm(2)); 4913 break; 4914 case CVT_imm_95_3: 4915 Inst.addOperand(MCOperand::createImm(3)); 4916 break; 4917 } 4918 } 4919} 4920 4921void ARMAsmParser:: 4922convertToMapAndConstraints(unsigned Kind, 4923 const OperandVector &Operands) { 4924 assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!"); 4925 unsigned NumMCOperands = 0; 4926 const uint8_t *Converter = ConversionTable[Kind]; 4927 for (const uint8_t *p = Converter; *p; p += 2) { 4928 switch (*p) { 4929 default: llvm_unreachable("invalid conversion entry!"); 4930 case CVT_Reg: 4931 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4932 Operands[*(p + 1)]->setConstraint("r"); 4933 ++NumMCOperands; 4934 break; 4935 case CVT_Tied: 4936 ++NumMCOperands; 4937 break; 4938 case CVT_95_Reg: 4939 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4940 Operands[*(p + 1)]->setConstraint("r"); 4941 NumMCOperands += 1; 4942 break; 4943 case CVT_95_addCCOutOperands: 4944 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4945 Operands[*(p + 1)]->setConstraint("m"); 4946 NumMCOperands += 1; 4947 break; 4948 case CVT_95_addCondCodeOperands: 4949 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4950 Operands[*(p + 1)]->setConstraint("m"); 4951 NumMCOperands += 2; 4952 break; 4953 case CVT_95_addRegShiftedRegOperands: 4954 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4955 Operands[*(p + 1)]->setConstraint("m"); 4956 NumMCOperands += 3; 4957 break; 4958 case CVT_95_addModImmOperands: 4959 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4960 Operands[*(p + 1)]->setConstraint("m"); 4961 NumMCOperands += 1; 4962 break; 4963 case CVT_95_addModImmNotOperands: 4964 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4965 Operands[*(p + 1)]->setConstraint("m"); 4966 NumMCOperands += 1; 4967 break; 4968 case CVT_95_addRegShiftedImmOperands: 4969 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4970 Operands[*(p + 1)]->setConstraint("m"); 4971 NumMCOperands += 2; 4972 break; 4973 case CVT_95_addImmOperands: 4974 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4975 Operands[*(p + 1)]->setConstraint("m"); 4976 NumMCOperands += 1; 4977 break; 4978 case CVT_95_addT2SOImmNotOperands: 4979 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4980 Operands[*(p + 1)]->setConstraint("m"); 4981 NumMCOperands += 1; 4982 break; 4983 case CVT_95_addImm0_95_4095NegOperands: 4984 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4985 Operands[*(p + 1)]->setConstraint("m"); 4986 NumMCOperands += 1; 4987 break; 4988 case CVT_95_addImm0_95_508s4Operands: 4989 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4990 Operands[*(p + 1)]->setConstraint("m"); 4991 NumMCOperands += 1; 4992 break; 4993 case CVT_regSP: 4994 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4995 Operands[*(p + 1)]->setConstraint("m"); 4996 ++NumMCOperands; 4997 break; 4998 case CVT_95_addImm0_95_508s4NegOperands: 4999 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5000 Operands[*(p + 1)]->setConstraint("m"); 5001 NumMCOperands += 1; 5002 break; 5003 case CVT_95_addT2SOImmNegOperands: 5004 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5005 Operands[*(p + 1)]->setConstraint("m"); 5006 NumMCOperands += 1; 5007 break; 5008 case CVT_95_addThumbModImmNeg8_95_255Operands: 5009 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5010 Operands[*(p + 1)]->setConstraint("m"); 5011 NumMCOperands += 1; 5012 break; 5013 case CVT_95_addModImmNegOperands: 5014 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5015 Operands[*(p + 1)]->setConstraint("m"); 5016 NumMCOperands += 1; 5017 break; 5018 case CVT_95_addImm0_95_1020s4Operands: 5019 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5020 Operands[*(p + 1)]->setConstraint("m"); 5021 NumMCOperands += 1; 5022 break; 5023 case CVT_95_addThumbModImmNeg1_95_7Operands: 5024 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5025 Operands[*(p + 1)]->setConstraint("m"); 5026 NumMCOperands += 1; 5027 break; 5028 case CVT_95_addUnsignedOffset_95_b8s2Operands: 5029 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5030 Operands[*(p + 1)]->setConstraint("m"); 5031 NumMCOperands += 1; 5032 break; 5033 case CVT_95_addAdrLabelOperands: 5034 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5035 Operands[*(p + 1)]->setConstraint("m"); 5036 NumMCOperands += 1; 5037 break; 5038 case CVT_imm_95_45: 5039 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5040 Operands[*(p + 1)]->setConstraint(""); 5041 ++NumMCOperands; 5042 break; 5043 case CVT_95_addARMBranchTargetOperands: 5044 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5045 Operands[*(p + 1)]->setConstraint("m"); 5046 NumMCOperands += 1; 5047 break; 5048 case CVT_95_addBitfieldOperands: 5049 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5050 Operands[*(p + 1)]->setConstraint("m"); 5051 NumMCOperands += 1; 5052 break; 5053 case CVT_95_addITCondCodeOperands: 5054 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5055 Operands[*(p + 1)]->setConstraint("m"); 5056 NumMCOperands += 1; 5057 break; 5058 case CVT_imm_95_0: 5059 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5060 Operands[*(p + 1)]->setConstraint(""); 5061 ++NumMCOperands; 5062 break; 5063 case CVT_95_addThumbBranchTargetOperands: 5064 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5065 Operands[*(p + 1)]->setConstraint("m"); 5066 NumMCOperands += 1; 5067 break; 5068 case CVT_imm_95_15: 5069 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5070 Operands[*(p + 1)]->setConstraint(""); 5071 ++NumMCOperands; 5072 break; 5073 case CVT_95_addCoprocNumOperands: 5074 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5075 Operands[*(p + 1)]->setConstraint("m"); 5076 NumMCOperands += 1; 5077 break; 5078 case CVT_95_addCoprocRegOperands: 5079 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5080 Operands[*(p + 1)]->setConstraint("m"); 5081 NumMCOperands += 1; 5082 break; 5083 case CVT_95_addITCondCodeInvOperands: 5084 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5085 Operands[*(p + 1)]->setConstraint("m"); 5086 NumMCOperands += 1; 5087 break; 5088 case CVT_imm_95_22: 5089 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5090 Operands[*(p + 1)]->setConstraint(""); 5091 ++NumMCOperands; 5092 break; 5093 case CVT_95_addRegListWithAPSROperands: 5094 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5095 Operands[*(p + 1)]->setConstraint("m"); 5096 NumMCOperands += 1; 5097 break; 5098 case CVT_95_addProcIFlagsOperands: 5099 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5100 Operands[*(p + 1)]->setConstraint("m"); 5101 NumMCOperands += 1; 5102 break; 5103 case CVT_imm_95_20: 5104 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5105 Operands[*(p + 1)]->setConstraint(""); 5106 ++NumMCOperands; 5107 break; 5108 case CVT_regZR: 5109 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5110 Operands[*(p + 1)]->setConstraint("m"); 5111 ++NumMCOperands; 5112 break; 5113 case CVT_imm_95_12: 5114 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5115 Operands[*(p + 1)]->setConstraint(""); 5116 ++NumMCOperands; 5117 break; 5118 case CVT_95_addMemBarrierOptOperands: 5119 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5120 Operands[*(p + 1)]->setConstraint("m"); 5121 NumMCOperands += 1; 5122 break; 5123 case CVT_imm_95_16: 5124 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5125 Operands[*(p + 1)]->setConstraint(""); 5126 ++NumMCOperands; 5127 break; 5128 case CVT_95_addFPImmOperands: 5129 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5130 Operands[*(p + 1)]->setConstraint("m"); 5131 NumMCOperands += 1; 5132 break; 5133 case CVT_95_addDPRRegListOperands: 5134 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5135 Operands[*(p + 1)]->setConstraint("m"); 5136 NumMCOperands += 1; 5137 break; 5138 case CVT_imm_95_1: 5139 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5140 Operands[*(p + 1)]->setConstraint(""); 5141 ++NumMCOperands; 5142 break; 5143 case CVT_95_addInstSyncBarrierOptOperands: 5144 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5145 Operands[*(p + 1)]->setConstraint("m"); 5146 NumMCOperands += 1; 5147 break; 5148 case CVT_95_addITMaskOperands: 5149 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5150 Operands[*(p + 1)]->setConstraint("m"); 5151 NumMCOperands += 1; 5152 break; 5153 case CVT_95_addMemNoOffsetOperands: 5154 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5155 Operands[*(p + 1)]->setConstraint("m"); 5156 NumMCOperands += 1; 5157 break; 5158 case CVT_95_addAddrMode5Operands: 5159 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5160 Operands[*(p + 1)]->setConstraint("m"); 5161 NumMCOperands += 2; 5162 break; 5163 case CVT_95_addCoprocOptionOperands: 5164 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5165 Operands[*(p + 1)]->setConstraint("m"); 5166 NumMCOperands += 1; 5167 break; 5168 case CVT_95_addPostIdxImm8s4Operands: 5169 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5170 Operands[*(p + 1)]->setConstraint("m"); 5171 NumMCOperands += 1; 5172 break; 5173 case CVT_95_addRegListOperands: 5174 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5175 Operands[*(p + 1)]->setConstraint("m"); 5176 NumMCOperands += 1; 5177 break; 5178 case CVT_95_addThumbMemPCOperands: 5179 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5180 Operands[*(p + 1)]->setConstraint("m"); 5181 NumMCOperands += 1; 5182 break; 5183 case CVT_95_addConstPoolAsmImmOperands: 5184 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5185 Operands[*(p + 1)]->setConstraint("m"); 5186 NumMCOperands += 1; 5187 break; 5188 case CVT_95_addMemThumbRIs4Operands: 5189 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5190 Operands[*(p + 1)]->setConstraint("m"); 5191 NumMCOperands += 2; 5192 break; 5193 case CVT_95_addMemThumbRROperands: 5194 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5195 Operands[*(p + 1)]->setConstraint("m"); 5196 NumMCOperands += 2; 5197 break; 5198 case CVT_95_addMemThumbSPIOperands: 5199 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5200 Operands[*(p + 1)]->setConstraint("m"); 5201 NumMCOperands += 2; 5202 break; 5203 case CVT_95_addMemImm12OffsetOperands: 5204 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5205 Operands[*(p + 1)]->setConstraint("m"); 5206 NumMCOperands += 2; 5207 break; 5208 case CVT_95_addMemImmOffsetOperands: 5209 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5210 Operands[*(p + 1)]->setConstraint("m"); 5211 NumMCOperands += 2; 5212 break; 5213 case CVT_95_addMemRegOffsetOperands: 5214 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5215 Operands[*(p + 1)]->setConstraint("m"); 5216 NumMCOperands += 3; 5217 break; 5218 case CVT_95_addMemUImm12OffsetOperands: 5219 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5220 Operands[*(p + 1)]->setConstraint("m"); 5221 NumMCOperands += 2; 5222 break; 5223 case CVT_95_addT2MemRegOffsetOperands: 5224 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5225 Operands[*(p + 1)]->setConstraint("m"); 5226 NumMCOperands += 3; 5227 break; 5228 case CVT_95_addMemPCRelImm12Operands: 5229 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5230 Operands[*(p + 1)]->setConstraint("m"); 5231 NumMCOperands += 1; 5232 break; 5233 case CVT_95_addAM2OffsetImmOperands: 5234 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5235 Operands[*(p + 1)]->setConstraint("m"); 5236 NumMCOperands += 2; 5237 break; 5238 case CVT_95_addPostIdxRegShiftedOperands: 5239 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5240 Operands[*(p + 1)]->setConstraint("m"); 5241 NumMCOperands += 2; 5242 break; 5243 case CVT_95_addMemThumbRIs1Operands: 5244 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5245 Operands[*(p + 1)]->setConstraint("m"); 5246 NumMCOperands += 2; 5247 break; 5248 case CVT_95_addMemImm8s4OffsetOperands: 5249 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5250 Operands[*(p + 1)]->setConstraint("m"); 5251 NumMCOperands += 2; 5252 break; 5253 case CVT_95_addAddrMode3Operands: 5254 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5255 Operands[*(p + 1)]->setConstraint("m"); 5256 NumMCOperands += 3; 5257 break; 5258 case CVT_95_addAM3OffsetOperands: 5259 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5260 Operands[*(p + 1)]->setConstraint("m"); 5261 NumMCOperands += 2; 5262 break; 5263 case CVT_95_addMemImm0_95_1020s4OffsetOperands: 5264 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5265 Operands[*(p + 1)]->setConstraint("m"); 5266 NumMCOperands += 2; 5267 break; 5268 case CVT_95_addMemThumbRIs2Operands: 5269 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5270 Operands[*(p + 1)]->setConstraint("m"); 5271 NumMCOperands += 2; 5272 break; 5273 case CVT_95_addPostIdxRegOperands: 5274 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5275 Operands[*(p + 1)]->setConstraint("m"); 5276 NumMCOperands += 2; 5277 break; 5278 case CVT_95_addPostIdxImm8Operands: 5279 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5280 Operands[*(p + 1)]->setConstraint("m"); 5281 NumMCOperands += 1; 5282 break; 5283 case CVT_reg0: 5284 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5285 Operands[*(p + 1)]->setConstraint("m"); 5286 ++NumMCOperands; 5287 break; 5288 case CVT_regCPSR: 5289 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5290 Operands[*(p + 1)]->setConstraint("m"); 5291 ++NumMCOperands; 5292 break; 5293 case CVT_imm_95_14: 5294 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5295 Operands[*(p + 1)]->setConstraint(""); 5296 ++NumMCOperands; 5297 break; 5298 case CVT_95_addBankedRegOperands: 5299 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5300 Operands[*(p + 1)]->setConstraint("m"); 5301 NumMCOperands += 1; 5302 break; 5303 case CVT_95_addMSRMaskOperands: 5304 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5305 Operands[*(p + 1)]->setConstraint("m"); 5306 NumMCOperands += 1; 5307 break; 5308 case CVT_regR8: 5309 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5310 Operands[*(p + 1)]->setConstraint("m"); 5311 ++NumMCOperands; 5312 break; 5313 case CVT_regR0: 5314 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5315 Operands[*(p + 1)]->setConstraint("m"); 5316 ++NumMCOperands; 5317 break; 5318 case CVT_imm_95_29: 5319 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5320 Operands[*(p + 1)]->setConstraint(""); 5321 ++NumMCOperands; 5322 break; 5323 case CVT_imm_95_13: 5324 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5325 Operands[*(p + 1)]->setConstraint(""); 5326 ++NumMCOperands; 5327 break; 5328 case CVT_95_addPKHASRImmOperands: 5329 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5330 Operands[*(p + 1)]->setConstraint("m"); 5331 NumMCOperands += 1; 5332 break; 5333 case CVT_imm_95_4: 5334 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5335 Operands[*(p + 1)]->setConstraint(""); 5336 ++NumMCOperands; 5337 break; 5338 case CVT_95_addImm1_95_32Operands: 5339 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5340 Operands[*(p + 1)]->setConstraint("m"); 5341 NumMCOperands += 1; 5342 break; 5343 case CVT_imm_95_5: 5344 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5345 Operands[*(p + 1)]->setConstraint(""); 5346 ++NumMCOperands; 5347 break; 5348 case CVT_95_addMveSaturateOperands: 5349 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5350 Operands[*(p + 1)]->setConstraint("m"); 5351 NumMCOperands += 1; 5352 break; 5353 case CVT_95_addShifterImmOperands: 5354 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5355 Operands[*(p + 1)]->setConstraint("m"); 5356 NumMCOperands += 1; 5357 break; 5358 case CVT_95_addImm1_95_16Operands: 5359 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5360 Operands[*(p + 1)]->setConstraint("m"); 5361 NumMCOperands += 1; 5362 break; 5363 case CVT_95_addRotImmOperands: 5364 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5365 Operands[*(p + 1)]->setConstraint("m"); 5366 NumMCOperands += 1; 5367 break; 5368 case CVT_95_addMemTBBOperands: 5369 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5370 Operands[*(p + 1)]->setConstraint("m"); 5371 NumMCOperands += 2; 5372 break; 5373 case CVT_95_addMemTBHOperands: 5374 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5375 Operands[*(p + 1)]->setConstraint("m"); 5376 NumMCOperands += 2; 5377 break; 5378 case CVT_95_addTraceSyncBarrierOptOperands: 5379 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5380 Operands[*(p + 1)]->setConstraint("m"); 5381 NumMCOperands += 1; 5382 break; 5383 case CVT_95_addVPTPredNOperands: 5384 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5385 Operands[*(p + 1)]->setConstraint("m"); 5386 NumMCOperands += 3; 5387 break; 5388 case CVT_95_addVPTPredROperands: 5389 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5390 Operands[*(p + 1)]->setConstraint("m"); 5391 NumMCOperands += 4; 5392 break; 5393 case CVT_95_addNEONi16splatNotOperands: 5394 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5395 Operands[*(p + 1)]->setConstraint("m"); 5396 NumMCOperands += 1; 5397 break; 5398 case CVT_95_addNEONi32splatNotOperands: 5399 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5400 Operands[*(p + 1)]->setConstraint("m"); 5401 NumMCOperands += 1; 5402 break; 5403 case CVT_95_addNEONi16splatOperands: 5404 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5405 Operands[*(p + 1)]->setConstraint("m"); 5406 NumMCOperands += 1; 5407 break; 5408 case CVT_95_addNEONi32splatOperands: 5409 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5410 Operands[*(p + 1)]->setConstraint("m"); 5411 NumMCOperands += 1; 5412 break; 5413 case CVT_95_addComplexRotationOddOperands: 5414 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5415 Operands[*(p + 1)]->setConstraint("m"); 5416 NumMCOperands += 1; 5417 break; 5418 case CVT_95_addComplexRotationEvenOperands: 5419 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5420 Operands[*(p + 1)]->setConstraint("m"); 5421 NumMCOperands += 1; 5422 break; 5423 case CVT_95_addVectorIndex64Operands: 5424 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5425 Operands[*(p + 1)]->setConstraint("m"); 5426 NumMCOperands += 1; 5427 break; 5428 case CVT_95_addVectorIndex32Operands: 5429 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5430 Operands[*(p + 1)]->setConstraint("m"); 5431 NumMCOperands += 1; 5432 break; 5433 case CVT_95_addFBits16Operands: 5434 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5435 Operands[*(p + 1)]->setConstraint("m"); 5436 NumMCOperands += 1; 5437 break; 5438 case CVT_95_addFBits32Operands: 5439 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5440 Operands[*(p + 1)]->setConstraint("m"); 5441 NumMCOperands += 1; 5442 break; 5443 case CVT_95_addPowerTwoOperands: 5444 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5445 Operands[*(p + 1)]->setConstraint("m"); 5446 NumMCOperands += 1; 5447 break; 5448 case CVT_95_addVectorIndex16Operands: 5449 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5450 Operands[*(p + 1)]->setConstraint("m"); 5451 NumMCOperands += 1; 5452 break; 5453 case CVT_95_addVectorIndex8Operands: 5454 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5455 Operands[*(p + 1)]->setConstraint("m"); 5456 NumMCOperands += 1; 5457 break; 5458 case CVT_95_addVecListOperands: 5459 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5460 Operands[*(p + 1)]->setConstraint("m"); 5461 NumMCOperands += 1; 5462 break; 5463 case CVT_95_addDupAlignedMemory16Operands: 5464 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5465 Operands[*(p + 1)]->setConstraint("m"); 5466 NumMCOperands += 2; 5467 break; 5468 case CVT_95_addAlignedMemory64or128Operands: 5469 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5470 Operands[*(p + 1)]->setConstraint("m"); 5471 NumMCOperands += 2; 5472 break; 5473 case CVT_95_addAlignedMemory64or128or256Operands: 5474 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5475 Operands[*(p + 1)]->setConstraint("m"); 5476 NumMCOperands += 2; 5477 break; 5478 case CVT_95_addAlignedMemory64Operands: 5479 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5480 Operands[*(p + 1)]->setConstraint("m"); 5481 NumMCOperands += 2; 5482 break; 5483 case CVT_95_addVecListIndexedOperands: 5484 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5485 Operands[*(p + 1)]->setConstraint("m"); 5486 NumMCOperands += 2; 5487 break; 5488 case CVT_95_addAlignedMemory16Operands: 5489 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5490 Operands[*(p + 1)]->setConstraint("m"); 5491 NumMCOperands += 2; 5492 break; 5493 case CVT_95_addDupAlignedMemory32Operands: 5494 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5495 Operands[*(p + 1)]->setConstraint("m"); 5496 NumMCOperands += 2; 5497 break; 5498 case CVT_95_addAlignedMemory32Operands: 5499 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5500 Operands[*(p + 1)]->setConstraint("m"); 5501 NumMCOperands += 2; 5502 break; 5503 case CVT_95_addDupAlignedMemoryNoneOperands: 5504 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5505 Operands[*(p + 1)]->setConstraint("m"); 5506 NumMCOperands += 2; 5507 break; 5508 case CVT_95_addAlignedMemoryNoneOperands: 5509 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5510 Operands[*(p + 1)]->setConstraint("m"); 5511 NumMCOperands += 2; 5512 break; 5513 case CVT_95_addAlignedMemoryOperands: 5514 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5515 Operands[*(p + 1)]->setConstraint("m"); 5516 NumMCOperands += 2; 5517 break; 5518 case CVT_95_addDupAlignedMemory64Operands: 5519 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5520 Operands[*(p + 1)]->setConstraint("m"); 5521 NumMCOperands += 2; 5522 break; 5523 case CVT_95_addMVEVecListOperands: 5524 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5525 Operands[*(p + 1)]->setConstraint("m"); 5526 NumMCOperands += 1; 5527 break; 5528 case CVT_95_addMemNoOffsetT2Operands: 5529 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5530 Operands[*(p + 1)]->setConstraint("m"); 5531 NumMCOperands += 1; 5532 break; 5533 case CVT_95_addMemNoOffsetT2NoSpOperands: 5534 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5535 Operands[*(p + 1)]->setConstraint("m"); 5536 NumMCOperands += 1; 5537 break; 5538 case CVT_95_addDupAlignedMemory64or128Operands: 5539 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5540 Operands[*(p + 1)]->setConstraint("m"); 5541 NumMCOperands += 2; 5542 break; 5543 case CVT_95_addSPRRegListOperands: 5544 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5545 Operands[*(p + 1)]->setConstraint("m"); 5546 NumMCOperands += 1; 5547 break; 5548 case CVT_95_addMemImm7s4OffsetOperands: 5549 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5550 Operands[*(p + 1)]->setConstraint("m"); 5551 NumMCOperands += 2; 5552 break; 5553 case CVT_95_addAddrMode5FP16Operands: 5554 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5555 Operands[*(p + 1)]->setConstraint("m"); 5556 NumMCOperands += 2; 5557 break; 5558 case CVT_95_addImm7s4Operands: 5559 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5560 Operands[*(p + 1)]->setConstraint("m"); 5561 NumMCOperands += 1; 5562 break; 5563 case CVT_95_addMemRegRQOffsetOperands: 5564 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5565 Operands[*(p + 1)]->setConstraint("m"); 5566 NumMCOperands += 2; 5567 break; 5568 case CVT_95_addMemNoOffsetTOperands: 5569 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5570 Operands[*(p + 1)]->setConstraint("m"); 5571 NumMCOperands += 1; 5572 break; 5573 case CVT_95_addImm7Shift0Operands: 5574 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5575 Operands[*(p + 1)]->setConstraint("m"); 5576 NumMCOperands += 1; 5577 break; 5578 case CVT_95_addImm7Shift1Operands: 5579 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5580 Operands[*(p + 1)]->setConstraint("m"); 5581 NumMCOperands += 1; 5582 break; 5583 case CVT_95_addImm7Shift2Operands: 5584 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5585 Operands[*(p + 1)]->setConstraint("m"); 5586 NumMCOperands += 1; 5587 break; 5588 case CVT_95_addNEONi32vmovOperands: 5589 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5590 Operands[*(p + 1)]->setConstraint("m"); 5591 NumMCOperands += 1; 5592 break; 5593 case CVT_95_addNEONvmovi8ReplicateOperands: 5594 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5595 Operands[*(p + 1)]->setConstraint("m"); 5596 NumMCOperands += 1; 5597 break; 5598 case CVT_95_addNEONvmovi16ReplicateOperands: 5599 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5600 Operands[*(p + 1)]->setConstraint("m"); 5601 NumMCOperands += 1; 5602 break; 5603 case CVT_95_addNEONi32vmovNegOperands: 5604 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5605 Operands[*(p + 1)]->setConstraint("m"); 5606 NumMCOperands += 1; 5607 break; 5608 case CVT_95_addNEONvmovi32ReplicateOperands: 5609 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5610 Operands[*(p + 1)]->setConstraint("m"); 5611 NumMCOperands += 1; 5612 break; 5613 case CVT_95_addNEONi64splatOperands: 5614 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5615 Operands[*(p + 1)]->setConstraint("m"); 5616 NumMCOperands += 1; 5617 break; 5618 case CVT_95_addNEONi8splatOperands: 5619 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5620 Operands[*(p + 1)]->setConstraint("m"); 5621 NumMCOperands += 1; 5622 break; 5623 case CVT_95_addMVEVectorIndexOperands: 5624 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5625 Operands[*(p + 1)]->setConstraint("m"); 5626 NumMCOperands += 1; 5627 break; 5628 case CVT_95_addMVEPairVectorIndexOperands: 5629 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5630 Operands[*(p + 1)]->setConstraint("m"); 5631 NumMCOperands += 1; 5632 break; 5633 case CVT_95_addNEONinvi8ReplicateOperands: 5634 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5635 Operands[*(p + 1)]->setConstraint("m"); 5636 NumMCOperands += 1; 5637 break; 5638 case CVT_95_addFPDRegListWithVPROperands: 5639 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5640 Operands[*(p + 1)]->setConstraint("m"); 5641 NumMCOperands += 1; 5642 break; 5643 case CVT_95_addFPSRegListWithVPROperands: 5644 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5645 Operands[*(p + 1)]->setConstraint("m"); 5646 NumMCOperands += 1; 5647 break; 5648 case CVT_imm_95_2: 5649 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5650 Operands[*(p + 1)]->setConstraint(""); 5651 ++NumMCOperands; 5652 break; 5653 case CVT_imm_95_3: 5654 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 5655 Operands[*(p + 1)]->setConstraint(""); 5656 ++NumMCOperands; 5657 break; 5658 } 5659 } 5660} 5661 5662namespace { 5663 5664/// MatchClassKind - The kinds of classes which participate in 5665/// instruction matching. 5666enum MatchClassKind { 5667 InvalidMatchClass = 0, 5668 OptionalMatchClass = 1, 5669 MCK__DOT_d, // '.d' 5670 MCK__DOT_f, // '.f' 5671 MCK__DOT_s16, // '.s16' 5672 MCK__DOT_s32, // '.s32' 5673 MCK__DOT_s64, // '.s64' 5674 MCK__DOT_s8, // '.s8' 5675 MCK__DOT_u16, // '.u16' 5676 MCK__DOT_u32, // '.u32' 5677 MCK__DOT_u64, // '.u64' 5678 MCK__DOT_u8, // '.u8' 5679 MCK__DOT_f32, // '.f32' 5680 MCK__DOT_f64, // '.f64' 5681 MCK__DOT_i16, // '.i16' 5682 MCK__DOT_i32, // '.i32' 5683 MCK__DOT_i64, // '.i64' 5684 MCK__DOT_i8, // '.i8' 5685 MCK__DOT_p16, // '.p16' 5686 MCK__DOT_p8, // '.p8' 5687 MCK__EXCLAIM_, // '!' 5688 MCK__HASH_0, // '#0' 5689 MCK__HASH_16, // '#16' 5690 MCK__HASH_8, // '#8' 5691 MCK__DOT_16, // '.16' 5692 MCK__DOT_32, // '.32' 5693 MCK__DOT_64, // '.64' 5694 MCK__DOT_8, // '.8' 5695 MCK__DOT_bf16, // '.bf16' 5696 MCK__DOT_f16, // '.f16' 5697 MCK__DOT_p64, // '.p64' 5698 MCK__DOT_w, // '.w' 5699 MCK__91_, // '[' 5700 MCK__93_, // ']' 5701 MCK__94_, // '^' 5702 MCK__123_, // '{' 5703 MCK__125_, // '}' 5704 MCK_LAST_TOKEN = MCK__125_, 5705 MCK_Reg107, // derived register class 5706 MCK_Reg91, // derived register class 5707 MCK_APSR, // register class 'APSR' 5708 MCK_APSR_NZCV, // register class 'APSR_NZCV' 5709 MCK_CCR, // register class 'CCR,CPSR' 5710 MCK_FPCXTRegs, // register class 'FPCXTRegs,FPCXTNS' 5711 MCK_FPCXTS, // register class 'FPCXTS' 5712 MCK_FPEXC, // register class 'FPEXC' 5713 MCK_FPINST, // register class 'FPINST' 5714 MCK_FPINST2, // register class 'FPINST2' 5715 MCK_FPSCR, // register class 'FPSCR' 5716 MCK_FPSCR_NZCVQC, // register class 'FPSCR_NZCVQC' 5717 MCK_FPSID, // register class 'FPSID' 5718 MCK_GPRlr, // register class 'GPRlr,LR' 5719 MCK_GPRsp, // register class 'GPRsp,SP' 5720 MCK_MVFR0, // register class 'MVFR0' 5721 MCK_MVFR1, // register class 'MVFR1' 5722 MCK_MVFR2, // register class 'MVFR2' 5723 MCK_P0, // register class 'P0' 5724 MCK_PC, // register class 'PC' 5725 MCK_R12, // register class 'R12' 5726 MCK_SPSR, // register class 'SPSR' 5727 MCK_VCCR, // register class 'VCCR,VPR' 5728 MCK_cl_FPSCR_NZCV, // register class 'cl_FPSCR_NZCV' 5729 MCK_Reg132, // derived register class 5730 MCK_Reg105, // derived register class 5731 MCK_Reg100, // derived register class 5732 MCK_Reg92, // derived register class 5733 MCK_Reg35, // derived register class 5734 MCK_Reg33, // derived register class 5735 MCK_Reg22, // derived register class 5736 MCK_Reg17, // derived register class 5737 MCK_Reg133, // derived register class 5738 MCK_Reg120, // derived register class 5739 MCK_Reg115, // derived register class 5740 MCK_Reg106, // derived register class 5741 MCK_Reg104, // derived register class 5742 MCK_Reg93, // derived register class 5743 MCK_Reg77, // derived register class 5744 MCK_Reg21, // derived register class 5745 MCK_Reg134, // derived register class 5746 MCK_Reg125, // derived register class 5747 MCK_Reg121, // derived register class 5748 MCK_Reg116, // derived register class 5749 MCK_Reg101, // derived register class 5750 MCK_Reg94, // derived register class 5751 MCK_Reg78, // derived register class 5752 MCK_Reg34, // derived register class 5753 MCK_Reg25, // derived register class 5754 MCK_Reg23, // derived register class 5755 MCK_Reg18, // derived register class 5756 MCK_Reg0, // derived register class 5757 MCK_QPR_8, // register class 'QPR_8' 5758 MCK_Reg89, // derived register class 5759 MCK_Reg32, // derived register class 5760 MCK_Reg30, // derived register class 5761 MCK_MQQQQPR, // register class 'MQQQQPR' 5762 MCK_tcGPR, // register class 'tcGPR' 5763 MCK_Reg135, // derived register class 5764 MCK_Reg126, // derived register class 5765 MCK_Reg108, // derived register class 5766 MCK_Reg96, // derived register class 5767 MCK_Reg90, // derived register class 5768 MCK_Reg72, // derived register class 5769 MCK_Reg31, // derived register class 5770 MCK_Reg28, // derived register class 5771 MCK_Reg19, // derived register class 5772 MCK_GPRPairnosp, // register class 'GPRPairnosp' 5773 MCK_tGPROdd, // register class 'tGPROdd' 5774 MCK_Reg136, // derived register class 5775 MCK_Reg122, // derived register class 5776 MCK_Reg117, // derived register class 5777 MCK_Reg109, // derived register class 5778 MCK_Reg97, // derived register class 5779 MCK_Reg87, // derived register class 5780 MCK_Reg52, // derived register class 5781 MCK_Reg29, // derived register class 5782 MCK_Reg26, // derived register class 5783 MCK_GPRPair, // register class 'GPRPair' 5784 MCK_MQQPR, // register class 'MQQPR' 5785 MCK_Reg137, // derived register class 5786 MCK_Reg127, // derived register class 5787 MCK_Reg123, // derived register class 5788 MCK_Reg118, // derived register class 5789 MCK_Reg110, // derived register class 5790 MCK_Reg98, // derived register class 5791 MCK_Reg88, // derived register class 5792 MCK_Reg80, // derived register class 5793 MCK_Reg73, // derived register class 5794 MCK_Reg53, // derived register class 5795 MCK_DPR_8, // register class 'DPR_8' 5796 MCK_MQPR, // register class 'MQPR,QPR_VFP2' 5797 MCK_hGPR, // register class 'hGPR' 5798 MCK_tGPR, // register class 'tGPR' 5799 MCK_tGPREven, // register class 'tGPREven' 5800 MCK_tGPRwithpc, // register class 'tGPRwithpc' 5801 MCK_Reg128, // derived register class 5802 MCK_Reg2, // derived register class 5803 MCK_Reg85, // derived register class 5804 MCK_Reg14, // derived register class 5805 MCK_Reg12, // derived register class 5806 MCK_QQQQPR, // register class 'QQQQPR' 5807 MCK_Reg138, // derived register class 5808 MCK_Reg129, // derived register class 5809 MCK_Reg111, // derived register class 5810 MCK_Reg86, // derived register class 5811 MCK_Reg74, // derived register class 5812 MCK_GPRnoip, // register class 'GPRnoip' 5813 MCK_rGPR, // register class 'rGPR' 5814 MCK_Reg124, // derived register class 5815 MCK_Reg119, // derived register class 5816 MCK_Reg112, // derived register class 5817 MCK_Reg83, // derived register class 5818 MCK_Reg50, // derived register class 5819 MCK_GPRnopc, // register class 'GPRnopc' 5820 MCK_GPRnosp, // register class 'GPRnosp' 5821 MCK_GPRwithAPSR_NZCVnosp, // register class 'GPRwithAPSR_NZCVnosp' 5822 MCK_GPRwithAPSRnosp, // register class 'GPRwithAPSRnosp' 5823 MCK_GPRwithZRnosp, // register class 'GPRwithZRnosp' 5824 MCK_QQPR, // register class 'QQPR' 5825 MCK_Reg130, // derived register class 5826 MCK_Reg113, // derived register class 5827 MCK_Reg84, // derived register class 5828 MCK_Reg75, // derived register class 5829 MCK_Reg51, // derived register class 5830 MCK_DPR_VFP2, // register class 'DPR_VFP2' 5831 MCK_GPR, // register class 'GPR' 5832 MCK_GPRwithAPSR, // register class 'GPRwithAPSR' 5833 MCK_GPRwithZR, // register class 'GPRwithZR' 5834 MCK_QPR, // register class 'QPR' 5835 MCK_SPR_8, // register class 'SPR_8' 5836 MCK_DTripleSpc, // register class 'DTripleSpc,DQuadSpc' 5837 MCK_DQuad, // register class 'DQuad' 5838 MCK_DPairSpc, // register class 'DPairSpc' 5839 MCK_DTriple, // register class 'DTriple' 5840 MCK_DPair, // register class 'DPair' 5841 MCK_DPR, // register class 'DPR' 5842 MCK_HPR, // register class 'HPR,SPR' 5843 MCK_FPWithVPR, // register class 'FPWithVPR' 5844 MCK_LAST_REGISTER = MCK_FPWithVPR, 5845 MCK_AM2OffsetImm, // user defined class 'AM2OffsetImmAsmOperand' 5846 MCK_AM3Offset, // user defined class 'AM3OffsetAsmOperand' 5847 MCK_ARMBranchTarget, // user defined class 'ARMBranchTarget' 5848 MCK_AddrMode3, // user defined class 'AddrMode3AsmOperand' 5849 MCK_AddrMode5, // user defined class 'AddrMode5AsmOperand' 5850 MCK_AddrMode5FP16, // user defined class 'AddrMode5FP16AsmOperand' 5851 MCK_AlignedMemory16, // user defined class 'AddrMode6Align16AsmOperand' 5852 MCK_AlignedMemory32, // user defined class 'AddrMode6Align32AsmOperand' 5853 MCK_AlignedMemory64, // user defined class 'AddrMode6Align64AsmOperand' 5854 MCK_AlignedMemory64or128, // user defined class 'AddrMode6Align64or128AsmOperand' 5855 MCK_AlignedMemory64or128or256, // user defined class 'AddrMode6Align64or128or256AsmOperand' 5856 MCK_AlignedMemoryNone, // user defined class 'AddrMode6AlignNoneAsmOperand' 5857 MCK_AlignedMemory, // user defined class 'AddrMode6AsmOperand' 5858 MCK_DupAlignedMemory16, // user defined class 'AddrMode6dupAlign16AsmOperand' 5859 MCK_DupAlignedMemory32, // user defined class 'AddrMode6dupAlign32AsmOperand' 5860 MCK_DupAlignedMemory64, // user defined class 'AddrMode6dupAlign64AsmOperand' 5861 MCK_DupAlignedMemory64or128, // user defined class 'AddrMode6dupAlign64or128AsmOperand' 5862 MCK_DupAlignedMemoryNone, // user defined class 'AddrMode6dupAlignNoneAsmOperand' 5863 MCK_AdrLabel, // user defined class 'AdrLabelAsmOperand' 5864 MCK_BankedReg, // user defined class 'BankedRegOperand' 5865 MCK_Bitfield, // user defined class 'BitfieldAsmOperand' 5866 MCK_CCOut, // user defined class 'CCOutOperand' 5867 MCK_CondCode, // user defined class 'CondCodeOperand' 5868 MCK_CoprocNum, // user defined class 'CoprocNumAsmOperand' 5869 MCK_CoprocOption, // user defined class 'CoprocOptionAsmOperand' 5870 MCK_CoprocReg, // user defined class 'CoprocRegAsmOperand' 5871 MCK_DPRRegList, // user defined class 'DPRRegListAsmOperand' 5872 MCK_FPDRegListWithVPR, // user defined class 'FPDRegListWithVPRAsmOperand' 5873 MCK_FPImm, // user defined class 'FPImmOperand' 5874 MCK_FPSRegListWithVPR, // user defined class 'FPSRegListWithVPRAsmOperand' 5875 MCK_Imm0_15, // user defined class 'Imm0_15AsmOperand' 5876 MCK_Imm0_1, // user defined class 'Imm0_1AsmOperand' 5877 MCK_Imm0_239, // user defined class 'Imm0_239AsmOperand' 5878 MCK_Imm0_255, // user defined class 'Imm0_255AsmOperand' 5879 MCK_Imm0_31, // user defined class 'Imm0_31AsmOperand' 5880 MCK_Imm0_32, // user defined class 'Imm0_32AsmOperand' 5881 MCK_Imm0_3, // user defined class 'Imm0_3AsmOperand' 5882 MCK_Imm0_63, // user defined class 'Imm0_63AsmOperand' 5883 MCK_Imm0_65535, // user defined class 'Imm0_65535AsmOperand' 5884 MCK_Imm0_65535Expr, // user defined class 'Imm0_65535ExprAsmOperand' 5885 MCK_Imm0_7, // user defined class 'Imm0_7AsmOperand' 5886 MCK_Imm16, // user defined class 'Imm16AsmOperand' 5887 MCK_Imm1_15, // user defined class 'Imm1_15AsmOperand' 5888 MCK_Imm1_16, // user defined class 'Imm1_16AsmOperand' 5889 MCK_Imm1_31, // user defined class 'Imm1_31AsmOperand' 5890 MCK_Imm1_32, // user defined class 'Imm1_32AsmOperand' 5891 MCK_Imm1_7, // user defined class 'Imm1_7AsmOperand' 5892 MCK_Imm24bit, // user defined class 'Imm24bitAsmOperand' 5893 MCK_Imm256_65535Expr, // user defined class 'Imm256_65535ExprAsmOperand' 5894 MCK_Imm32, // user defined class 'Imm32AsmOperand' 5895 MCK_Imm8, // user defined class 'Imm8AsmOperand' 5896 MCK_Imm8_255, // user defined class 'Imm8_255AsmOperand' 5897 MCK_Imm, // user defined class 'ImmAsmOperand' 5898 MCK_InstSyncBarrierOpt, // user defined class 'InstSyncBarrierOptOperand' 5899 MCK_MSRMask, // user defined class 'MSRMaskOperand' 5900 MCK_MVEShiftImm1_15, // user defined class 'MVEShiftImm1_15AsmOperand' 5901 MCK_MVEShiftImm1_7, // user defined class 'MVEShiftImm1_7AsmOperand' 5902 MCK_VIDUP_imm, // user defined class 'MVE_VIDUP_imm_asmoperand' 5903 MCK_MemBarrierOpt, // user defined class 'MemBarrierOptOperand' 5904 MCK_MemImm0_1020s4Offset, // user defined class 'MemImm0_1020s4OffsetAsmOperand' 5905 MCK_MemImm12Offset, // user defined class 'MemImm12OffsetAsmOperand' 5906 MCK_MemImm7Shift0Offset, // user defined class 'MemImm7Shift0OffsetAsmOperand' 5907 MCK_MemImm7Shift0OffsetWB, // user defined class 'MemImm7Shift0OffsetWBAsmOperand' 5908 MCK_MemImm7Shift1Offset, // user defined class 'MemImm7Shift1OffsetAsmOperand' 5909 MCK_MemImm7Shift1OffsetWB, // user defined class 'MemImm7Shift1OffsetWBAsmOperand' 5910 MCK_MemImm7Shift2Offset, // user defined class 'MemImm7Shift2OffsetAsmOperand' 5911 MCK_MemImm7Shift2OffsetWB, // user defined class 'MemImm7Shift2OffsetWBAsmOperand' 5912 MCK_MemImm7s4Offset, // user defined class 'MemImm7s4OffsetAsmOperand' 5913 MCK_MemImm8Offset, // user defined class 'MemImm8OffsetAsmOperand' 5914 MCK_MemImm8s4Offset, // user defined class 'MemImm8s4OffsetAsmOperand' 5915 MCK_MemNegImm8Offset, // user defined class 'MemNegImm8OffsetAsmOperand' 5916 MCK_MemNoOffset, // user defined class 'MemNoOffsetAsmOperand' 5917 MCK_MemNoOffsetT2, // user defined class 'MemNoOffsetT2AsmOperand' 5918 MCK_MemNoOffsetT2NoSp, // user defined class 'MemNoOffsetT2NoSpAsmOperand' 5919 MCK_MemNoOffsetT, // user defined class 'MemNoOffsetTAsmOperand' 5920 MCK_MemPosImm8Offset, // user defined class 'MemPosImm8OffsetAsmOperand' 5921 MCK_MemRegOffset, // user defined class 'MemRegOffsetAsmOperand' 5922 MCK_MemRegQS2Offset, // user defined class 'MemRegQS2OffsetAsmOperand' 5923 MCK_MemRegQS3Offset, // user defined class 'MemRegQS3OffsetAsmOperand' 5924 MCK_MemRegRQS0Offset, // user defined class 'MemRegRQS0OffsetAsmOperand' 5925 MCK_MemRegRQS1Offset, // user defined class 'MemRegRQS1OffsetAsmOperand' 5926 MCK_MemRegRQS2Offset, // user defined class 'MemRegRQS2OffsetAsmOperand' 5927 MCK_MemRegRQS3Offset, // user defined class 'MemRegRQS3OffsetAsmOperand' 5928 MCK_ModImm, // user defined class 'ModImmAsmOperand' 5929 MCK_ModImmNeg, // user defined class 'ModImmNegAsmOperand' 5930 MCK_ModImmNot, // user defined class 'ModImmNotAsmOperand' 5931 MCK_MveSaturate, // user defined class 'MveSaturateOperand' 5932 MCK_PKHASRImm, // user defined class 'PKHASRAsmOperand' 5933 MCK_PKHLSLImm, // user defined class 'PKHLSLAsmOperand' 5934 MCK_PostIdxImm8, // user defined class 'PostIdxImm8AsmOperand' 5935 MCK_PostIdxImm8s4, // user defined class 'PostIdxImm8s4AsmOperand' 5936 MCK_PostIdxReg, // user defined class 'PostIdxRegAsmOperand' 5937 MCK_PostIdxRegShifted, // user defined class 'PostIdxRegShiftedAsmOperand' 5938 MCK_ProcIFlags, // user defined class 'ProcIFlagsOperand' 5939 MCK_RegList, // user defined class 'RegListAsmOperand' 5940 MCK_RegListWithAPSR, // user defined class 'RegListWithAPSRAsmOperand' 5941 MCK_RotImm, // user defined class 'RotImmAsmOperand' 5942 MCK_SPRRegList, // user defined class 'SPRRegListAsmOperand' 5943 MCK_SetEndImm, // user defined class 'SetEndAsmOperand' 5944 MCK_RegShiftedImm, // user defined class 'ShiftedImmAsmOperand' 5945 MCK_RegShiftedReg, // user defined class 'ShiftedRegAsmOperand' 5946 MCK_ShifterImm, // user defined class 'ShifterImmAsmOperand' 5947 MCK_ThumbBranchTarget, // user defined class 'ThumbBranchTarget' 5948 MCK_ThumbMemPC, // user defined class 'ThumbMemPC' 5949 MCK_ThumbModImmNeg1_7, // user defined class 'ThumbModImmNeg1_7AsmOperand' 5950 MCK_ThumbModImmNeg8_255, // user defined class 'ThumbModImmNeg8_255AsmOperand' 5951 MCK_ImmThumbSR, // user defined class 'ThumbSRImmAsmOperand' 5952 MCK_TraceSyncBarrierOpt, // user defined class 'TraceSyncBarrierOptOperand' 5953 MCK_UnsignedOffset_b8s2, // user defined class 'UnsignedOffset_b8s2' 5954 MCK_VPTPredN, // user defined class 'VPTPredNOperand' 5955 MCK_VPTPredR, // user defined class 'VPTPredROperand' 5956 MCK_VecListTwoMQ, // user defined class 'VecList2QAsmOperand' 5957 MCK_VecListFourMQ, // user defined class 'VecList4QAsmOperand' 5958 MCK_VecListDPairAllLanes, // user defined class 'VecListDPairAllLanesAsmOperand' 5959 MCK_VecListDPair, // user defined class 'VecListDPairAsmOperand' 5960 MCK_VecListDPairSpacedAllLanes, // user defined class 'VecListDPairSpacedAllLanesAsmOperand' 5961 MCK_VecListDPairSpaced, // user defined class 'VecListDPairSpacedAsmOperand' 5962 MCK_VecListFourDAllLanes, // user defined class 'VecListFourDAllLanesAsmOperand' 5963 MCK_VecListFourD, // user defined class 'VecListFourDAsmOperand' 5964 MCK_VecListFourDByteIndexed, // user defined class 'VecListFourDByteIndexAsmOperand' 5965 MCK_VecListFourDHWordIndexed, // user defined class 'VecListFourDHWordIndexAsmOperand' 5966 MCK_VecListFourDWordIndexed, // user defined class 'VecListFourDWordIndexAsmOperand' 5967 MCK_VecListFourQAllLanes, // user defined class 'VecListFourQAllLanesAsmOperand' 5968 MCK_VecListFourQ, // user defined class 'VecListFourQAsmOperand' 5969 MCK_VecListFourQHWordIndexed, // user defined class 'VecListFourQHWordIndexAsmOperand' 5970 MCK_VecListFourQWordIndexed, // user defined class 'VecListFourQWordIndexAsmOperand' 5971 MCK_VecListOneDAllLanes, // user defined class 'VecListOneDAllLanesAsmOperand' 5972 MCK_VecListOneD, // user defined class 'VecListOneDAsmOperand' 5973 MCK_VecListOneDByteIndexed, // user defined class 'VecListOneDByteIndexAsmOperand' 5974 MCK_VecListOneDHWordIndexed, // user defined class 'VecListOneDHWordIndexAsmOperand' 5975 MCK_VecListOneDWordIndexed, // user defined class 'VecListOneDWordIndexAsmOperand' 5976 MCK_VecListThreeDAllLanes, // user defined class 'VecListThreeDAllLanesAsmOperand' 5977 MCK_VecListThreeD, // user defined class 'VecListThreeDAsmOperand' 5978 MCK_VecListThreeDByteIndexed, // user defined class 'VecListThreeDByteIndexAsmOperand' 5979 MCK_VecListThreeDHWordIndexed, // user defined class 'VecListThreeDHWordIndexAsmOperand' 5980 MCK_VecListThreeDWordIndexed, // user defined class 'VecListThreeDWordIndexAsmOperand' 5981 MCK_VecListThreeQAllLanes, // user defined class 'VecListThreeQAllLanesAsmOperand' 5982 MCK_VecListThreeQ, // user defined class 'VecListThreeQAsmOperand' 5983 MCK_VecListThreeQHWordIndexed, // user defined class 'VecListThreeQHWordIndexAsmOperand' 5984 MCK_VecListThreeQWordIndexed, // user defined class 'VecListThreeQWordIndexAsmOperand' 5985 MCK_VecListTwoDByteIndexed, // user defined class 'VecListTwoDByteIndexAsmOperand' 5986 MCK_VecListTwoDHWordIndexed, // user defined class 'VecListTwoDHWordIndexAsmOperand' 5987 MCK_VecListTwoDWordIndexed, // user defined class 'VecListTwoDWordIndexAsmOperand' 5988 MCK_VecListTwoQHWordIndexed, // user defined class 'VecListTwoQHWordIndexAsmOperand' 5989 MCK_VecListTwoQWordIndexed, // user defined class 'VecListTwoQWordIndexAsmOperand' 5990 MCK_VectorIndex16, // user defined class 'VectorIndex16Operand' 5991 MCK_VectorIndex32, // user defined class 'VectorIndex32Operand' 5992 MCK_VectorIndex64, // user defined class 'VectorIndex64Operand' 5993 MCK_VectorIndex8, // user defined class 'VectorIndex8Operand' 5994 MCK_MemTBB, // user defined class 'addrmode_tbb_asmoperand' 5995 MCK_MemTBH, // user defined class 'addrmode_tbh_asmoperand' 5996 MCK_MVEPairVectorIndex0, // user defined class 'anonymous_4092' 5997 MCK_MVEPairVectorIndex2, // user defined class 'anonymous_4093' 5998 MCK_ComplexRotationEven, // user defined class 'anonymous_4102' 5999 MCK_ComplexRotationOdd, // user defined class 'anonymous_4103' 6000 MCK_NEONi16vmovi8Replicate, // user defined class 'anonymous_5427' 6001 MCK_NEONi16invi8Replicate, // user defined class 'anonymous_5429' 6002 MCK_NEONi32vmovi8Replicate, // user defined class 'anonymous_5432' 6003 MCK_NEONi32invi8Replicate, // user defined class 'anonymous_5434' 6004 MCK_NEONi64vmovi8Replicate, // user defined class 'anonymous_5441' 6005 MCK_NEONi64invi8Replicate, // user defined class 'anonymous_5443' 6006 MCK_NEONi32vmovi16Replicate, // user defined class 'anonymous_5454' 6007 MCK_NEONi64vmovi16Replicate, // user defined class 'anonymous_5457' 6008 MCK_NEONi64vmovi32Replicate, // user defined class 'anonymous_5464' 6009 MCK_MVEVectorIndex4, // user defined class 'anonymous_6739' 6010 MCK_MVEVectorIndex8, // user defined class 'anonymous_6741' 6011 MCK_MVEVectorIndex16, // user defined class 'anonymous_6743' 6012 MCK_MVEVcvtImm32, // user defined class 'anonymous_7477' 6013 MCK_MVEVcvtImm16, // user defined class 'anonymous_7479' 6014 MCK_TMemImm7Shift2Offset, // user defined class 'anonymous_7724' 6015 MCK_TMemImm7Shift0Offset, // user defined class 'anonymous_8471' 6016 MCK_TMemImm7Shift1Offset, // user defined class 'anonymous_8474' 6017 MCK_Imm3b, // user defined class 'anonymous_9006' 6018 MCK_Imm4b, // user defined class 'anonymous_9007' 6019 MCK_Imm6b, // user defined class 'anonymous_9008' 6020 MCK_Imm7b, // user defined class 'anonymous_9009' 6021 MCK_Imm9b, // user defined class 'anonymous_9010' 6022 MCK_Imm11b, // user defined class 'anonymous_9011' 6023 MCK_Imm12b, // user defined class 'anonymous_9012' 6024 MCK_Imm13b, // user defined class 'anonymous_9013' 6025 MCK_ConstPoolAsmImm, // user defined class 'const_pool_asm_operand' 6026 MCK_FBits16, // user defined class 'fbits16_asm_operand' 6027 MCK_FBits32, // user defined class 'fbits32_asm_operand' 6028 MCK_Imm0_4095, // user defined class 'imm0_4095_asmoperand' 6029 MCK_Imm0_4095Neg, // user defined class 'imm0_4095_neg_asmoperand' 6030 MCK_ITMask, // user defined class 'it_mask_asmoperand' 6031 MCK_ITCondCode, // user defined class 'it_pred_asmoperand' 6032 MCK_LELabel, // user defined class 'lelabel_u11_asmoperand' 6033 MCK_MVELongShift, // user defined class 'mve_shift_imm' 6034 MCK_NEONi16splat, // user defined class 'nImmSplatI16AsmOperand' 6035 MCK_NEONi32splat, // user defined class 'nImmSplatI32AsmOperand' 6036 MCK_NEONi64splat, // user defined class 'nImmSplatI64AsmOperand' 6037 MCK_NEONi8splat, // user defined class 'nImmSplatI8AsmOperand' 6038 MCK_NEONi16splatNot, // user defined class 'nImmSplatNotI16AsmOperand' 6039 MCK_NEONi32splatNot, // user defined class 'nImmSplatNotI32AsmOperand' 6040 MCK_NEONi32vmov, // user defined class 'nImmVMOVI32AsmOperand' 6041 MCK_NEONi32vmovNeg, // user defined class 'nImmVMOVI32NegAsmOperand' 6042 MCK_CondCodeNoAL, // user defined class 'pred_noal_asmoperand' 6043 MCK_CondCodeNoALInv, // user defined class 'pred_noal_inv_asmoperand' 6044 MCK_CondCodeRestrictedFP, // user defined class 'pred_restricted_fp_asmoperand' 6045 MCK_CondCodeRestrictedI, // user defined class 'pred_restricted_i_asmoperand' 6046 MCK_CondCodeRestrictedS, // user defined class 'pred_restricted_s_asmoperand' 6047 MCK_CondCodeRestrictedU, // user defined class 'pred_restricted_u_asmoperand' 6048 MCK_ShrImm16, // user defined class 'shr_imm16_asm_operand' 6049 MCK_ShrImm32, // user defined class 'shr_imm32_asm_operand' 6050 MCK_ShrImm64, // user defined class 'shr_imm64_asm_operand' 6051 MCK_ShrImm8, // user defined class 'shr_imm8_asm_operand' 6052 MCK_T2SOImm, // user defined class 't2_so_imm_asmoperand' 6053 MCK_T2SOImmNeg, // user defined class 't2_so_imm_neg_asmoperand' 6054 MCK_T2SOImmNot, // user defined class 't2_so_imm_not_asmoperand' 6055 MCK_MemUImm12Offset, // user defined class 't2addrmode_imm12_asmoperand' 6056 MCK_T2MemRegOffset, // user defined class 't2addrmode_so_reg_asmoperand' 6057 MCK_Imm7s4, // user defined class 't2am_imm7s4_offset_asmoperand' 6058 MCK_Imm7Shift0, // user defined class 't2am_imm7shift0OffsetAsmOperand' 6059 MCK_Imm7Shift1, // user defined class 't2am_imm7shift1OffsetAsmOperand' 6060 MCK_Imm7Shift2, // user defined class 't2am_imm7shift2OffsetAsmOperand' 6061 MCK_Imm8s4, // user defined class 't2am_imm8s4_offset_asmoperand' 6062 MCK_MemPCRelImm12, // user defined class 't2ldr_pcrel_imm12_asmoperand' 6063 MCK_MemThumbRIs1, // user defined class 't_addrmode_is1_asm_operand' 6064 MCK_MemThumbRIs2, // user defined class 't_addrmode_is2_asm_operand' 6065 MCK_MemThumbRIs4, // user defined class 't_addrmode_is4_asm_operand' 6066 MCK_MemThumbRR, // user defined class 't_addrmode_rr_asm_operand' 6067 MCK_MemThumbSPI, // user defined class 't_addrmode_sp_asm_operand' 6068 MCK_Imm0_1020s4, // user defined class 't_imm0_1020s4_asmoperand' 6069 MCK_Imm0_508s4, // user defined class 't_imm0_508s4_asmoperand' 6070 MCK_Imm0_508s4Neg, // user defined class 't_imm0_508s4_neg_asmoperand' 6071 MCK_WLSLabel, // user defined class 'wlslabel_u11_asmoperand' 6072 NumMatchClassKinds 6073}; 6074 6075} // end anonymous namespace 6076 6077static const char *getMatchKindDiag(ARMAsmParser::ARMMatchResultTy MatchResult) { 6078 switch (MatchResult) { 6079 case ARMAsmParser::Match_GPRsp: 6080 return "operand must be a register sp"; 6081 case ARMAsmParser::Match_QPR_8: 6082 return "operand must be a register in range [q0, q3]"; 6083 case ARMAsmParser::Match_tGPROdd: 6084 return "operand must be an odd-numbered register in range [r1,r11]"; 6085 case ARMAsmParser::Match_DPR_8: 6086 return "operand must be a register in range [d0, d7]"; 6087 case ARMAsmParser::Match_QPR_VFP2: 6088 return "operand must be a register in range [q0, q7]"; 6089 case ARMAsmParser::Match_hGPR: 6090 return "operand must be a register in range [r8, r15]"; 6091 case ARMAsmParser::Match_tGPR: 6092 return "operand must be a register in range [r0, r7]"; 6093 case ARMAsmParser::Match_tGPREven: 6094 return "operand must be an even-numbered register"; 6095 case ARMAsmParser::Match_GPRnoip: 6096 return "operand must be a register in range [r0, r14]"; 6097 case ARMAsmParser::Match_GPRnopc: 6098 return "operand must be a register in range [r0, r14]"; 6099 case ARMAsmParser::Match_GPRnosp: 6100 return "operand must be a register in range [r0, r12] or LR or PC"; 6101 case ARMAsmParser::Match_GPRwithAPSR_NZCVnosp: 6102 return "operand must be a register in the range [r0, r12], r14 or apsr_nzcv"; 6103 case ARMAsmParser::Match_GPRwithZRnosp: 6104 return "operand must be a register in range [r0, r12] or r14 or zr"; 6105 case ARMAsmParser::Match_DPR_VFP2: 6106 return "operand must be a register in range [d0, d15]"; 6107 case ARMAsmParser::Match_GPR: 6108 return "operand must be a register in range [r0, r15]"; 6109 case ARMAsmParser::Match_GPRwithAPSR: 6110 return "operand must be a register in range [r0, r14] or apsr_nzcv"; 6111 case ARMAsmParser::Match_GPRwithZR: 6112 return "operand must be a register in range [r0, r14] or zr"; 6113 case ARMAsmParser::Match_QPR: 6114 return "operand must be a register in range [q0, q15]"; 6115 case ARMAsmParser::Match_SPR_8: 6116 return "operand must be a register in range [s0, s15]"; 6117 case ARMAsmParser::Match_SPR: 6118 return "operand must be a register in range [s0, s31]"; 6119 case ARMAsmParser::Match_AlignedMemory16: 6120 return "alignment must be 16 or omitted"; 6121 case ARMAsmParser::Match_AlignedMemory32: 6122 return "alignment must be 32 or omitted"; 6123 case ARMAsmParser::Match_AlignedMemory64: 6124 return "alignment must be 64 or omitted"; 6125 case ARMAsmParser::Match_AlignedMemory64or128: 6126 return "alignment must be 64, 128 or omitted"; 6127 case ARMAsmParser::Match_AlignedMemory64or128or256: 6128 return "alignment must be 64, 128, 256 or omitted"; 6129 case ARMAsmParser::Match_AlignedMemoryNone: 6130 return "alignment must be omitted"; 6131 case ARMAsmParser::Match_DupAlignedMemory16: 6132 return "alignment must be 16 or omitted"; 6133 case ARMAsmParser::Match_DupAlignedMemory32: 6134 return "alignment must be 32 or omitted"; 6135 case ARMAsmParser::Match_DupAlignedMemory64: 6136 return "alignment must be 64 or omitted"; 6137 case ARMAsmParser::Match_DupAlignedMemory64or128: 6138 return "alignment must be 64, 128 or omitted"; 6139 case ARMAsmParser::Match_DupAlignedMemoryNone: 6140 return "alignment must be omitted"; 6141 case ARMAsmParser::Match_Imm0_15: 6142 return "operand must be an immediate in the range [0,15]"; 6143 case ARMAsmParser::Match_Imm0_1: 6144 return "operand must be an immediate in the range [0,1]"; 6145 case ARMAsmParser::Match_Imm0_239: 6146 return "operand must be an immediate in the range [0,239]"; 6147 case ARMAsmParser::Match_Imm0_255: 6148 return "operand must be an immediate in the range [0,255]"; 6149 case ARMAsmParser::Match_Imm0_31: 6150 return "operand must be an immediate in the range [0,31]"; 6151 case ARMAsmParser::Match_Imm0_32: 6152 return "operand must be an immediate in the range [0,32]"; 6153 case ARMAsmParser::Match_Imm0_3: 6154 return "operand must be an immediate in the range [0,3]"; 6155 case ARMAsmParser::Match_Imm0_63: 6156 return "operand must be an immediate in the range [0,63]"; 6157 case ARMAsmParser::Match_Imm0_65535: 6158 return "operand must be an immediate in the range [0,65535]"; 6159 case ARMAsmParser::Match_Imm0_65535Expr: 6160 return "operand must be an immediate in the range [0,0xffff] or a relocatable expression"; 6161 case ARMAsmParser::Match_Imm0_7: 6162 return "operand must be an immediate in the range [0,7]"; 6163 case ARMAsmParser::Match_Imm16: 6164 return "operand must be an immediate in the range [16,16]"; 6165 case ARMAsmParser::Match_Imm1_15: 6166 return "operand must be an immediate in the range [1,15]"; 6167 case ARMAsmParser::Match_ImmRange1_16: 6168 return "operand must be an immediate in the range [1,16]"; 6169 case ARMAsmParser::Match_Imm1_31: 6170 return "operand must be an immediate in the range [1,31]"; 6171 case ARMAsmParser::Match_ImmRange1_32: 6172 return "operand must be an immediate in the range [1,32]"; 6173 case ARMAsmParser::Match_Imm1_7: 6174 return "operand must be an immediate in the range [1,7]"; 6175 case ARMAsmParser::Match_Imm24bit: 6176 return "operand must be an immediate in the range [0,0xffffff]"; 6177 case ARMAsmParser::Match_Imm256_65535Expr: 6178 return "operand must be an immediate in the range [256,65535]"; 6179 case ARMAsmParser::Match_Imm32: 6180 return "operand must be an immediate in the range [32,32]"; 6181 case ARMAsmParser::Match_Imm8: 6182 return "operand must be an immediate in the range [8,8]"; 6183 case ARMAsmParser::Match_Imm8_255: 6184 return "operand must be an immediate in the range [8,255]"; 6185 case ARMAsmParser::Match_MVEShiftImm1_15: 6186 return "operand must be an immediate in the range [1,16]"; 6187 case ARMAsmParser::Match_MVEShiftImm1_7: 6188 return "operand must be an immediate in the range [1,8]"; 6189 case ARMAsmParser::Match_VIDUP_imm: 6190 return "vector increment immediate must be 1, 2, 4 or 8"; 6191 case ARMAsmParser::Match_MveSaturate: 6192 return "saturate operand must be 48 or 64"; 6193 case ARMAsmParser::Match_PKHLSLImm: 6194 return "operand must be an immediate in the range [0,31]"; 6195 case ARMAsmParser::Match_SPRRegList: 6196 return "operand must be a list of registers in range [s0, s31]"; 6197 case ARMAsmParser::Match_SetEndImm: 6198 return "operand must be an immediate in the range [0,1]"; 6199 case ARMAsmParser::Match_ImmThumbSR: 6200 return "operand must be an immediate in the range [1,32]"; 6201 case ARMAsmParser::Match_VecListTwoMQ: 6202 return "operand must be a list of two consecutive q-registers in range [q0,q7]"; 6203 case ARMAsmParser::Match_VecListFourMQ: 6204 return "operand must be a list of four consecutive q-registers in range [q0,q7]"; 6205 case ARMAsmParser::Match_ComplexRotationEven: 6206 return "complex rotation must be 0, 90, 180 or 270"; 6207 case ARMAsmParser::Match_ComplexRotationOdd: 6208 return "complex rotation must be 90 or 270"; 6209 case ARMAsmParser::Match_MVEVcvtImm32: 6210 return "MVE fixed-point immediate operand must be between 1 and 32"; 6211 case ARMAsmParser::Match_MVEVcvtImm16: 6212 return "MVE fixed-point immediate operand must be between 1 and 16"; 6213 case ARMAsmParser::Match_Imm3b: 6214 return "operand must be an immediate in the range [0,7]"; 6215 case ARMAsmParser::Match_Imm4b: 6216 return "operand must be an immediate in the range [0,15]"; 6217 case ARMAsmParser::Match_Imm6b: 6218 return "operand must be an immediate in the range [0,63]"; 6219 case ARMAsmParser::Match_Imm7b: 6220 return "operand must be an immediate in the range [0,127]"; 6221 case ARMAsmParser::Match_Imm9b: 6222 return "operand must be an immediate in the range [0,511]"; 6223 case ARMAsmParser::Match_Imm11b: 6224 return "operand must be an immediate in the range [0,2047]"; 6225 case ARMAsmParser::Match_Imm12b: 6226 return "operand must be an immediate in the range [0,4095]"; 6227 case ARMAsmParser::Match_Imm13b: 6228 return "operand must be an immediate in the range [0,8191]"; 6229 case ARMAsmParser::Match_Imm0_4095: 6230 return "operand must be an immediate in the range [0,4095]"; 6231 case ARMAsmParser::Match_LELabel: 6232 return "loop start is out of range or not a negative multiple of 2"; 6233 case ARMAsmParser::Match_MVELongShift: 6234 return "operand must be an immediate in the range [1,32]"; 6235 case ARMAsmParser::Match_CondCodeRestrictedFP: 6236 return "condition code for floating-point comparison must be EQ, NE, LT, GT, LE or GE"; 6237 case ARMAsmParser::Match_CondCodeRestrictedI: 6238 return "condition code for sign-independent integer comparison must be EQ or NE"; 6239 case ARMAsmParser::Match_CondCodeRestrictedS: 6240 return "condition code for signed integer comparison must be EQ, NE, LT, GT, LE or GE"; 6241 case ARMAsmParser::Match_CondCodeRestrictedU: 6242 return "condition code for unsigned integer comparison must be EQ, NE, HS or HI"; 6243 case ARMAsmParser::Match_ShrImm16: 6244 return "operand must be an immediate in the range [1,16]"; 6245 case ARMAsmParser::Match_ShrImm32: 6246 return "operand must be an immediate in the range [1,32]"; 6247 case ARMAsmParser::Match_ShrImm64: 6248 return "operand must be an immediate in the range [1,64]"; 6249 case ARMAsmParser::Match_ShrImm8: 6250 return "operand must be an immediate in the range [1,8]"; 6251 case ARMAsmParser::Match_WLSLabel: 6252 return "loop end is out of range or not a positive multiple of 2"; 6253 default: 6254 return nullptr; 6255 } 6256} 6257 6258static unsigned getDiagKindFromRegisterClass(MatchClassKind RegisterClass) { 6259 switch (RegisterClass) { 6260 case MCK_GPRsp: 6261 return ARMAsmParser::Match_GPRsp; 6262 case MCK_QPR_8: 6263 return ARMAsmParser::Match_QPR_8; 6264 case MCK_tGPROdd: 6265 return ARMAsmParser::Match_tGPROdd; 6266 case MCK_DPR_8: 6267 return ARMAsmParser::Match_DPR_8; 6268 case MCK_MQPR: 6269 return ARMAsmParser::Match_QPR_VFP2; 6270 case MCK_hGPR: 6271 return ARMAsmParser::Match_hGPR; 6272 case MCK_tGPR: 6273 return ARMAsmParser::Match_tGPR; 6274 case MCK_tGPREven: 6275 return ARMAsmParser::Match_tGPREven; 6276 case MCK_GPRnoip: 6277 return ARMAsmParser::Match_GPRnoip; 6278 case MCK_rGPR: 6279 return ARMAsmParser::Match_rGPR; 6280 case MCK_GPRnopc: 6281 return ARMAsmParser::Match_GPRnopc; 6282 case MCK_GPRnosp: 6283 return ARMAsmParser::Match_GPRnosp; 6284 case MCK_GPRwithAPSR_NZCVnosp: 6285 return ARMAsmParser::Match_GPRwithAPSR_NZCVnosp; 6286 case MCK_GPRwithZRnosp: 6287 return ARMAsmParser::Match_GPRwithZRnosp; 6288 case MCK_DPR_VFP2: 6289 return ARMAsmParser::Match_DPR_VFP2; 6290 case MCK_GPR: 6291 return ARMAsmParser::Match_GPR; 6292 case MCK_GPRwithAPSR: 6293 return ARMAsmParser::Match_GPRwithAPSR; 6294 case MCK_GPRwithZR: 6295 return ARMAsmParser::Match_GPRwithZR; 6296 case MCK_QPR: 6297 return ARMAsmParser::Match_QPR; 6298 case MCK_SPR_8: 6299 return ARMAsmParser::Match_SPR_8; 6300 case MCK_DPR: 6301 return ARMAsmParser::Match_DPR; 6302 case MCK_HPR: 6303 return ARMAsmParser::Match_SPR; 6304 default: 6305 return MCTargetAsmParser::Match_InvalidOperand; 6306 } 6307} 6308 6309static MatchClassKind matchTokenString(StringRef Name) { 6310 switch (Name.size()) { 6311 default: break; 6312 case 1: // 6 strings to match. 6313 switch (Name[0]) { 6314 default: break; 6315 case '!': // 1 string to match. 6316 return MCK__EXCLAIM_; // "!" 6317 case '[': // 1 string to match. 6318 return MCK__91_; // "[" 6319 case ']': // 1 string to match. 6320 return MCK__93_; // "]" 6321 case '^': // 1 string to match. 6322 return MCK__94_; // "^" 6323 case '{': // 1 string to match. 6324 return MCK__123_; // "{" 6325 case '}': // 1 string to match. 6326 return MCK__125_; // "}" 6327 } 6328 break; 6329 case 2: // 6 strings to match. 6330 switch (Name[0]) { 6331 default: break; 6332 case '#': // 2 strings to match. 6333 switch (Name[1]) { 6334 default: break; 6335 case '0': // 1 string to match. 6336 return MCK__HASH_0; // "#0" 6337 case '8': // 1 string to match. 6338 return MCK__HASH_8; // "#8" 6339 } 6340 break; 6341 case '.': // 4 strings to match. 6342 switch (Name[1]) { 6343 default: break; 6344 case '8': // 1 string to match. 6345 return MCK__DOT_8; // ".8" 6346 case 'd': // 1 string to match. 6347 return MCK__DOT_d; // ".d" 6348 case 'f': // 1 string to match. 6349 return MCK__DOT_f; // ".f" 6350 case 'w': // 1 string to match. 6351 return MCK__DOT_w; // ".w" 6352 } 6353 break; 6354 } 6355 break; 6356 case 3: // 8 strings to match. 6357 switch (Name[0]) { 6358 default: break; 6359 case '#': // 1 string to match. 6360 if (memcmp(Name.data()+1, "16", 2) != 0) 6361 break; 6362 return MCK__HASH_16; // "#16" 6363 case '.': // 7 strings to match. 6364 switch (Name[1]) { 6365 default: break; 6366 case '1': // 1 string to match. 6367 if (Name[2] != '6') 6368 break; 6369 return MCK__DOT_16; // ".16" 6370 case '3': // 1 string to match. 6371 if (Name[2] != '2') 6372 break; 6373 return MCK__DOT_32; // ".32" 6374 case '6': // 1 string to match. 6375 if (Name[2] != '4') 6376 break; 6377 return MCK__DOT_64; // ".64" 6378 case 'i': // 1 string to match. 6379 if (Name[2] != '8') 6380 break; 6381 return MCK__DOT_i8; // ".i8" 6382 case 'p': // 1 string to match. 6383 if (Name[2] != '8') 6384 break; 6385 return MCK__DOT_p8; // ".p8" 6386 case 's': // 1 string to match. 6387 if (Name[2] != '8') 6388 break; 6389 return MCK__DOT_s8; // ".s8" 6390 case 'u': // 1 string to match. 6391 if (Name[2] != '8') 6392 break; 6393 return MCK__DOT_u8; // ".u8" 6394 } 6395 break; 6396 } 6397 break; 6398 case 4: // 14 strings to match. 6399 if (Name[0] != '.') 6400 break; 6401 switch (Name[1]) { 6402 default: break; 6403 case 'f': // 3 strings to match. 6404 switch (Name[2]) { 6405 default: break; 6406 case '1': // 1 string to match. 6407 if (Name[3] != '6') 6408 break; 6409 return MCK__DOT_f16; // ".f16" 6410 case '3': // 1 string to match. 6411 if (Name[3] != '2') 6412 break; 6413 return MCK__DOT_f32; // ".f32" 6414 case '6': // 1 string to match. 6415 if (Name[3] != '4') 6416 break; 6417 return MCK__DOT_f64; // ".f64" 6418 } 6419 break; 6420 case 'i': // 3 strings to match. 6421 switch (Name[2]) { 6422 default: break; 6423 case '1': // 1 string to match. 6424 if (Name[3] != '6') 6425 break; 6426 return MCK__DOT_i16; // ".i16" 6427 case '3': // 1 string to match. 6428 if (Name[3] != '2') 6429 break; 6430 return MCK__DOT_i32; // ".i32" 6431 case '6': // 1 string to match. 6432 if (Name[3] != '4') 6433 break; 6434 return MCK__DOT_i64; // ".i64" 6435 } 6436 break; 6437 case 'p': // 2 strings to match. 6438 switch (Name[2]) { 6439 default: break; 6440 case '1': // 1 string to match. 6441 if (Name[3] != '6') 6442 break; 6443 return MCK__DOT_p16; // ".p16" 6444 case '6': // 1 string to match. 6445 if (Name[3] != '4') 6446 break; 6447 return MCK__DOT_p64; // ".p64" 6448 } 6449 break; 6450 case 's': // 3 strings to match. 6451 switch (Name[2]) { 6452 default: break; 6453 case '1': // 1 string to match. 6454 if (Name[3] != '6') 6455 break; 6456 return MCK__DOT_s16; // ".s16" 6457 case '3': // 1 string to match. 6458 if (Name[3] != '2') 6459 break; 6460 return MCK__DOT_s32; // ".s32" 6461 case '6': // 1 string to match. 6462 if (Name[3] != '4') 6463 break; 6464 return MCK__DOT_s64; // ".s64" 6465 } 6466 break; 6467 case 'u': // 3 strings to match. 6468 switch (Name[2]) { 6469 default: break; 6470 case '1': // 1 string to match. 6471 if (Name[3] != '6') 6472 break; 6473 return MCK__DOT_u16; // ".u16" 6474 case '3': // 1 string to match. 6475 if (Name[3] != '2') 6476 break; 6477 return MCK__DOT_u32; // ".u32" 6478 case '6': // 1 string to match. 6479 if (Name[3] != '4') 6480 break; 6481 return MCK__DOT_u64; // ".u64" 6482 } 6483 break; 6484 } 6485 break; 6486 case 5: // 1 string to match. 6487 if (memcmp(Name.data()+0, ".bf16", 5) != 0) 6488 break; 6489 return MCK__DOT_bf16; // ".bf16" 6490 } 6491 return InvalidMatchClass; 6492} 6493 6494/// isSubclass - Compute whether \p A is a subclass of \p B. 6495static bool isSubclass(MatchClassKind A, MatchClassKind B) { 6496 if (A == B) 6497 return true; 6498 6499 switch (A) { 6500 default: 6501 return false; 6502 6503 case MCK__DOT_d: 6504 switch (B) { 6505 default: return false; 6506 case MCK__DOT_f64: return true; 6507 case MCK__DOT_64: return true; 6508 } 6509 6510 case MCK__DOT_f: 6511 switch (B) { 6512 default: return false; 6513 case MCK__DOT_f32: return true; 6514 case MCK__DOT_32: return true; 6515 } 6516 6517 case MCK__DOT_s16: 6518 switch (B) { 6519 default: return false; 6520 case MCK__DOT_i16: return true; 6521 case MCK__DOT_16: return true; 6522 } 6523 6524 case MCK__DOT_s32: 6525 switch (B) { 6526 default: return false; 6527 case MCK__DOT_i32: return true; 6528 case MCK__DOT_32: return true; 6529 } 6530 6531 case MCK__DOT_s64: 6532 switch (B) { 6533 default: return false; 6534 case MCK__DOT_i64: return true; 6535 case MCK__DOT_64: return true; 6536 } 6537 6538 case MCK__DOT_s8: 6539 switch (B) { 6540 default: return false; 6541 case MCK__DOT_i8: return true; 6542 case MCK__DOT_8: return true; 6543 } 6544 6545 case MCK__DOT_u16: 6546 switch (B) { 6547 default: return false; 6548 case MCK__DOT_i16: return true; 6549 case MCK__DOT_16: return true; 6550 } 6551 6552 case MCK__DOT_u32: 6553 switch (B) { 6554 default: return false; 6555 case MCK__DOT_i32: return true; 6556 case MCK__DOT_32: return true; 6557 } 6558 6559 case MCK__DOT_u64: 6560 switch (B) { 6561 default: return false; 6562 case MCK__DOT_i64: return true; 6563 case MCK__DOT_64: return true; 6564 } 6565 6566 case MCK__DOT_u8: 6567 switch (B) { 6568 default: return false; 6569 case MCK__DOT_i8: return true; 6570 case MCK__DOT_8: return true; 6571 } 6572 6573 case MCK__DOT_f32: 6574 return B == MCK__DOT_32; 6575 6576 case MCK__DOT_f64: 6577 return B == MCK__DOT_64; 6578 6579 case MCK__DOT_i16: 6580 return B == MCK__DOT_16; 6581 6582 case MCK__DOT_i32: 6583 return B == MCK__DOT_32; 6584 6585 case MCK__DOT_i64: 6586 return B == MCK__DOT_64; 6587 6588 case MCK__DOT_i8: 6589 return B == MCK__DOT_8; 6590 6591 case MCK__DOT_p16: 6592 return B == MCK__DOT_16; 6593 6594 case MCK__DOT_p8: 6595 return B == MCK__DOT_8; 6596 6597 case MCK_Reg107: 6598 switch (B) { 6599 default: return false; 6600 case MCK_Reg106: return true; 6601 case MCK_Reg104: return true; 6602 case MCK_GPRPair: return true; 6603 } 6604 6605 case MCK_Reg91: 6606 switch (B) { 6607 default: return false; 6608 case MCK_Reg92: return true; 6609 case MCK_Reg93: return true; 6610 case MCK_Reg94: return true; 6611 case MCK_MQQQQPR: return true; 6612 case MCK_Reg96: return true; 6613 case MCK_Reg97: return true; 6614 case MCK_Reg98: return true; 6615 case MCK_QQQQPR: return true; 6616 } 6617 6618 case MCK_APSR: 6619 return B == MCK_GPRwithAPSRnosp; 6620 6621 case MCK_APSR_NZCV: 6622 switch (B) { 6623 default: return false; 6624 case MCK_GPRwithAPSR_NZCVnosp: return true; 6625 case MCK_GPRwithAPSR: return true; 6626 } 6627 6628 case MCK_GPRlr: 6629 switch (B) { 6630 default: return false; 6631 case MCK_Reg34: return true; 6632 case MCK_Reg28: return true; 6633 case MCK_Reg29: return true; 6634 case MCK_Reg26: return true; 6635 case MCK_hGPR: return true; 6636 case MCK_tGPREven: return true; 6637 case MCK_rGPR: return true; 6638 case MCK_GPRnopc: return true; 6639 case MCK_GPRnosp: return true; 6640 case MCK_GPRwithAPSR_NZCVnosp: return true; 6641 case MCK_GPRwithAPSRnosp: return true; 6642 case MCK_GPRwithZRnosp: return true; 6643 case MCK_GPR: return true; 6644 case MCK_GPRwithAPSR: return true; 6645 case MCK_GPRwithZR: return true; 6646 } 6647 6648 case MCK_GPRsp: 6649 switch (B) { 6650 default: return false; 6651 case MCK_Reg30: return true; 6652 case MCK_Reg31: return true; 6653 case MCK_Reg26: return true; 6654 case MCK_hGPR: return true; 6655 case MCK_Reg12: return true; 6656 case MCK_GPRnoip: return true; 6657 case MCK_GPRnopc: return true; 6658 case MCK_GPR: return true; 6659 case MCK_GPRwithAPSR: return true; 6660 case MCK_GPRwithZR: return true; 6661 } 6662 6663 case MCK_PC: 6664 switch (B) { 6665 default: return false; 6666 case MCK_Reg32: return true; 6667 case MCK_Reg31: return true; 6668 case MCK_Reg29: return true; 6669 case MCK_hGPR: return true; 6670 case MCK_tGPRwithpc: return true; 6671 case MCK_Reg14: return true; 6672 case MCK_GPRnoip: return true; 6673 case MCK_GPRnosp: return true; 6674 case MCK_GPR: return true; 6675 } 6676 6677 case MCK_R12: 6678 switch (B) { 6679 default: return false; 6680 case MCK_Reg21: return true; 6681 case MCK_Reg34: return true; 6682 case MCK_tcGPR: return true; 6683 case MCK_Reg28: return true; 6684 case MCK_Reg29: return true; 6685 case MCK_Reg26: return true; 6686 case MCK_hGPR: return true; 6687 case MCK_tGPREven: return true; 6688 case MCK_rGPR: return true; 6689 case MCK_GPRnopc: return true; 6690 case MCK_GPRnosp: return true; 6691 case MCK_GPRwithAPSR_NZCVnosp: return true; 6692 case MCK_GPRwithAPSRnosp: return true; 6693 case MCK_GPRwithZRnosp: return true; 6694 case MCK_GPR: return true; 6695 case MCK_GPRwithAPSR: return true; 6696 case MCK_GPRwithZR: return true; 6697 } 6698 6699 case MCK_VCCR: 6700 return B == MCK_FPWithVPR; 6701 6702 case MCK_Reg132: 6703 switch (B) { 6704 default: return false; 6705 case MCK_Reg133: return true; 6706 case MCK_Reg134: return true; 6707 case MCK_Reg89: return true; 6708 case MCK_Reg135: return true; 6709 case MCK_Reg90: return true; 6710 case MCK_Reg136: return true; 6711 case MCK_Reg87: return true; 6712 case MCK_Reg137: return true; 6713 case MCK_Reg88: return true; 6714 case MCK_Reg85: return true; 6715 case MCK_Reg138: return true; 6716 case MCK_Reg86: return true; 6717 case MCK_Reg83: return true; 6718 case MCK_Reg84: return true; 6719 case MCK_DQuad: return true; 6720 } 6721 6722 case MCK_Reg105: 6723 switch (B) { 6724 default: return false; 6725 case MCK_Reg106: return true; 6726 case MCK_GPRPairnosp: return true; 6727 case MCK_GPRPair: return true; 6728 } 6729 6730 case MCK_Reg100: 6731 switch (B) { 6732 default: return false; 6733 case MCK_Reg104: return true; 6734 case MCK_Reg101: return true; 6735 case MCK_GPRPairnosp: return true; 6736 case MCK_GPRPair: return true; 6737 } 6738 6739 case MCK_Reg92: 6740 switch (B) { 6741 default: return false; 6742 case MCK_Reg93: return true; 6743 case MCK_Reg94: return true; 6744 case MCK_MQQQQPR: return true; 6745 case MCK_Reg96: return true; 6746 case MCK_Reg97: return true; 6747 case MCK_Reg98: return true; 6748 case MCK_QQQQPR: return true; 6749 } 6750 6751 case MCK_Reg35: 6752 switch (B) { 6753 default: return false; 6754 case MCK_Reg25: return true; 6755 case MCK_Reg32: return true; 6756 case MCK_Reg30: return true; 6757 case MCK_Reg31: return true; 6758 case MCK_Reg28: return true; 6759 case MCK_tGPROdd: return true; 6760 case MCK_Reg29: return true; 6761 case MCK_Reg26: return true; 6762 case MCK_hGPR: return true; 6763 case MCK_Reg2: return true; 6764 case MCK_Reg14: return true; 6765 case MCK_Reg12: return true; 6766 case MCK_GPRnoip: return true; 6767 case MCK_rGPR: return true; 6768 case MCK_GPRnopc: return true; 6769 case MCK_GPRnosp: return true; 6770 case MCK_GPRwithAPSR_NZCVnosp: return true; 6771 case MCK_GPRwithAPSRnosp: return true; 6772 case MCK_GPRwithZRnosp: return true; 6773 case MCK_GPR: return true; 6774 case MCK_GPRwithAPSR: return true; 6775 case MCK_GPRwithZR: return true; 6776 } 6777 6778 case MCK_Reg33: 6779 switch (B) { 6780 default: return false; 6781 case MCK_Reg34: return true; 6782 case MCK_Reg25: return true; 6783 case MCK_Reg32: return true; 6784 case MCK_Reg30: return true; 6785 case MCK_Reg31: return true; 6786 case MCK_Reg28: return true; 6787 case MCK_Reg19: return true; 6788 case MCK_Reg29: return true; 6789 case MCK_Reg26: return true; 6790 case MCK_hGPR: return true; 6791 case MCK_tGPREven: return true; 6792 case MCK_Reg2: return true; 6793 case MCK_Reg14: return true; 6794 case MCK_Reg12: return true; 6795 case MCK_GPRnoip: return true; 6796 case MCK_rGPR: return true; 6797 case MCK_GPRnopc: return true; 6798 case MCK_GPRnosp: return true; 6799 case MCK_GPRwithAPSR_NZCVnosp: return true; 6800 case MCK_GPRwithAPSRnosp: return true; 6801 case MCK_GPRwithZRnosp: return true; 6802 case MCK_GPR: return true; 6803 case MCK_GPRwithAPSR: return true; 6804 case MCK_GPRwithZR: return true; 6805 } 6806 6807 case MCK_Reg22: 6808 switch (B) { 6809 default: return false; 6810 case MCK_Reg23: return true; 6811 case MCK_Reg0: return true; 6812 case MCK_tcGPR: return true; 6813 case MCK_tGPROdd: return true; 6814 case MCK_tGPR: return true; 6815 case MCK_tGPRwithpc: return true; 6816 case MCK_Reg2: return true; 6817 case MCK_Reg14: return true; 6818 case MCK_Reg12: return true; 6819 case MCK_GPRnoip: return true; 6820 case MCK_rGPR: return true; 6821 case MCK_GPRnopc: return true; 6822 case MCK_GPRnosp: return true; 6823 case MCK_GPRwithAPSR_NZCVnosp: return true; 6824 case MCK_GPRwithAPSRnosp: return true; 6825 case MCK_GPRwithZRnosp: return true; 6826 case MCK_GPR: return true; 6827 case MCK_GPRwithAPSR: return true; 6828 case MCK_GPRwithZR: return true; 6829 } 6830 6831 case MCK_Reg17: 6832 switch (B) { 6833 default: return false; 6834 case MCK_Reg21: return true; 6835 case MCK_Reg18: return true; 6836 case MCK_Reg0: return true; 6837 case MCK_tcGPR: return true; 6838 case MCK_Reg19: return true; 6839 case MCK_tGPR: return true; 6840 case MCK_tGPREven: return true; 6841 case MCK_tGPRwithpc: return true; 6842 case MCK_Reg2: return true; 6843 case MCK_Reg14: return true; 6844 case MCK_Reg12: return true; 6845 case MCK_GPRnoip: return true; 6846 case MCK_rGPR: return true; 6847 case MCK_GPRnopc: return true; 6848 case MCK_GPRnosp: return true; 6849 case MCK_GPRwithAPSR_NZCVnosp: return true; 6850 case MCK_GPRwithAPSRnosp: return true; 6851 case MCK_GPRwithZRnosp: return true; 6852 case MCK_GPR: return true; 6853 case MCK_GPRwithAPSR: return true; 6854 case MCK_GPRwithZR: return true; 6855 } 6856 6857 case MCK_Reg133: 6858 switch (B) { 6859 default: return false; 6860 case MCK_Reg134: return true; 6861 case MCK_Reg135: return true; 6862 case MCK_Reg90: return true; 6863 case MCK_Reg136: return true; 6864 case MCK_Reg87: return true; 6865 case MCK_Reg137: return true; 6866 case MCK_Reg88: return true; 6867 case MCK_Reg85: return true; 6868 case MCK_Reg138: return true; 6869 case MCK_Reg86: return true; 6870 case MCK_Reg83: return true; 6871 case MCK_Reg84: return true; 6872 case MCK_DQuad: return true; 6873 } 6874 6875 case MCK_Reg120: 6876 switch (B) { 6877 default: return false; 6878 case MCK_Reg121: return true; 6879 case MCK_Reg108: return true; 6880 case MCK_Reg122: return true; 6881 case MCK_Reg109: return true; 6882 case MCK_Reg123: return true; 6883 case MCK_Reg110: return true; 6884 case MCK_Reg111: return true; 6885 case MCK_Reg124: return true; 6886 case MCK_Reg112: return true; 6887 case MCK_Reg113: return true; 6888 case MCK_DTriple: return true; 6889 } 6890 6891 case MCK_Reg115: 6892 switch (B) { 6893 default: return false; 6894 case MCK_Reg116: return true; 6895 case MCK_Reg108: return true; 6896 case MCK_Reg117: return true; 6897 case MCK_Reg109: return true; 6898 case MCK_Reg118: return true; 6899 case MCK_Reg110: return true; 6900 case MCK_Reg111: return true; 6901 case MCK_Reg119: return true; 6902 case MCK_Reg112: return true; 6903 case MCK_Reg113: return true; 6904 case MCK_DTriple: return true; 6905 } 6906 6907 case MCK_Reg106: 6908 return B == MCK_GPRPair; 6909 6910 case MCK_Reg104: 6911 return B == MCK_GPRPair; 6912 6913 case MCK_Reg93: 6914 switch (B) { 6915 default: return false; 6916 case MCK_Reg94: return true; 6917 case MCK_MQQQQPR: return true; 6918 case MCK_Reg96: return true; 6919 case MCK_Reg97: return true; 6920 case MCK_Reg98: return true; 6921 case MCK_QQQQPR: return true; 6922 } 6923 6924 case MCK_Reg77: 6925 switch (B) { 6926 default: return false; 6927 case MCK_Reg78: return true; 6928 case MCK_Reg89: return true; 6929 case MCK_Reg90: return true; 6930 case MCK_Reg87: return true; 6931 case MCK_MQQPR: return true; 6932 case MCK_Reg88: return true; 6933 case MCK_Reg80: return true; 6934 case MCK_Reg85: return true; 6935 case MCK_Reg86: return true; 6936 case MCK_Reg83: return true; 6937 case MCK_QQPR: return true; 6938 case MCK_Reg84: return true; 6939 case MCK_DQuad: return true; 6940 } 6941 6942 case MCK_Reg21: 6943 switch (B) { 6944 default: return false; 6945 case MCK_tcGPR: return true; 6946 case MCK_tGPREven: return true; 6947 case MCK_rGPR: return true; 6948 case MCK_GPRnopc: return true; 6949 case MCK_GPRnosp: return true; 6950 case MCK_GPRwithAPSR_NZCVnosp: return true; 6951 case MCK_GPRwithAPSRnosp: return true; 6952 case MCK_GPRwithZRnosp: return true; 6953 case MCK_GPR: return true; 6954 case MCK_GPRwithAPSR: return true; 6955 case MCK_GPRwithZR: return true; 6956 } 6957 6958 case MCK_Reg134: 6959 switch (B) { 6960 default: return false; 6961 case MCK_Reg135: return true; 6962 case MCK_Reg136: return true; 6963 case MCK_Reg137: return true; 6964 case MCK_Reg88: return true; 6965 case MCK_Reg85: return true; 6966 case MCK_Reg138: return true; 6967 case MCK_Reg86: return true; 6968 case MCK_Reg83: return true; 6969 case MCK_Reg84: return true; 6970 case MCK_DQuad: return true; 6971 } 6972 6973 case MCK_Reg125: 6974 switch (B) { 6975 default: return false; 6976 case MCK_Reg126: return true; 6977 case MCK_Reg127: return true; 6978 case MCK_Reg128: return true; 6979 case MCK_Reg129: return true; 6980 case MCK_Reg130: return true; 6981 case MCK_DTripleSpc: return true; 6982 } 6983 6984 case MCK_Reg121: 6985 switch (B) { 6986 default: return false; 6987 case MCK_Reg122: return true; 6988 case MCK_Reg123: return true; 6989 case MCK_Reg110: return true; 6990 case MCK_Reg111: return true; 6991 case MCK_Reg124: return true; 6992 case MCK_Reg112: return true; 6993 case MCK_Reg113: return true; 6994 case MCK_DTriple: return true; 6995 } 6996 6997 case MCK_Reg116: 6998 switch (B) { 6999 default: return false; 7000 case MCK_Reg117: return true; 7001 case MCK_Reg109: return true; 7002 case MCK_Reg118: return true; 7003 case MCK_Reg110: return true; 7004 case MCK_Reg111: return true; 7005 case MCK_Reg119: return true; 7006 case MCK_Reg112: return true; 7007 case MCK_Reg113: return true; 7008 case MCK_DTriple: return true; 7009 } 7010 7011 case MCK_Reg101: 7012 switch (B) { 7013 default: return false; 7014 case MCK_GPRPairnosp: return true; 7015 case MCK_GPRPair: return true; 7016 } 7017 7018 case MCK_Reg94: 7019 switch (B) { 7020 default: return false; 7021 case MCK_MQQQQPR: return true; 7022 case MCK_Reg96: return true; 7023 case MCK_Reg97: return true; 7024 case MCK_Reg98: return true; 7025 case MCK_QQQQPR: return true; 7026 } 7027 7028 case MCK_Reg78: 7029 switch (B) { 7030 default: return false; 7031 case MCK_Reg87: return true; 7032 case MCK_MQQPR: return true; 7033 case MCK_Reg88: return true; 7034 case MCK_Reg80: return true; 7035 case MCK_Reg85: return true; 7036 case MCK_Reg86: return true; 7037 case MCK_Reg83: return true; 7038 case MCK_QQPR: return true; 7039 case MCK_Reg84: return true; 7040 case MCK_DQuad: return true; 7041 } 7042 7043 case MCK_Reg34: 7044 switch (B) { 7045 default: return false; 7046 case MCK_Reg28: return true; 7047 case MCK_Reg29: return true; 7048 case MCK_Reg26: return true; 7049 case MCK_hGPR: return true; 7050 case MCK_tGPREven: return true; 7051 case MCK_rGPR: return true; 7052 case MCK_GPRnopc: return true; 7053 case MCK_GPRnosp: return true; 7054 case MCK_GPRwithAPSR_NZCVnosp: return true; 7055 case MCK_GPRwithAPSRnosp: return true; 7056 case MCK_GPRwithZRnosp: return true; 7057 case MCK_GPR: return true; 7058 case MCK_GPRwithAPSR: return true; 7059 case MCK_GPRwithZR: return true; 7060 } 7061 7062 case MCK_Reg25: 7063 switch (B) { 7064 default: return false; 7065 case MCK_Reg32: return true; 7066 case MCK_Reg30: return true; 7067 case MCK_Reg31: return true; 7068 case MCK_Reg28: return true; 7069 case MCK_Reg29: return true; 7070 case MCK_Reg26: return true; 7071 case MCK_hGPR: return true; 7072 case MCK_Reg2: return true; 7073 case MCK_Reg14: return true; 7074 case MCK_Reg12: return true; 7075 case MCK_GPRnoip: return true; 7076 case MCK_rGPR: return true; 7077 case MCK_GPRnopc: return true; 7078 case MCK_GPRnosp: return true; 7079 case MCK_GPRwithAPSR_NZCVnosp: return true; 7080 case MCK_GPRwithAPSRnosp: return true; 7081 case MCK_GPRwithZRnosp: return true; 7082 case MCK_GPR: return true; 7083 case MCK_GPRwithAPSR: return true; 7084 case MCK_GPRwithZR: return true; 7085 } 7086 7087 case MCK_Reg23: 7088 switch (B) { 7089 default: return false; 7090 case MCK_tGPROdd: return true; 7091 case MCK_tGPR: return true; 7092 case MCK_tGPRwithpc: return true; 7093 case MCK_Reg2: return true; 7094 case MCK_Reg14: return true; 7095 case MCK_Reg12: return true; 7096 case MCK_GPRnoip: return true; 7097 case MCK_rGPR: return true; 7098 case MCK_GPRnopc: return true; 7099 case MCK_GPRnosp: return true; 7100 case MCK_GPRwithAPSR_NZCVnosp: return true; 7101 case MCK_GPRwithAPSRnosp: return true; 7102 case MCK_GPRwithZRnosp: return true; 7103 case MCK_GPR: return true; 7104 case MCK_GPRwithAPSR: return true; 7105 case MCK_GPRwithZR: return true; 7106 } 7107 7108 case MCK_Reg18: 7109 switch (B) { 7110 default: return false; 7111 case MCK_Reg19: return true; 7112 case MCK_tGPR: return true; 7113 case MCK_tGPREven: return true; 7114 case MCK_tGPRwithpc: return true; 7115 case MCK_Reg2: return true; 7116 case MCK_Reg14: return true; 7117 case MCK_Reg12: return true; 7118 case MCK_GPRnoip: return true; 7119 case MCK_rGPR: return true; 7120 case MCK_GPRnopc: return true; 7121 case MCK_GPRnosp: return true; 7122 case MCK_GPRwithAPSR_NZCVnosp: return true; 7123 case MCK_GPRwithAPSRnosp: return true; 7124 case MCK_GPRwithZRnosp: return true; 7125 case MCK_GPR: return true; 7126 case MCK_GPRwithAPSR: return true; 7127 case MCK_GPRwithZR: return true; 7128 } 7129 7130 case MCK_Reg0: 7131 switch (B) { 7132 default: return false; 7133 case MCK_tcGPR: return true; 7134 case MCK_tGPR: return true; 7135 case MCK_tGPRwithpc: return true; 7136 case MCK_Reg2: return true; 7137 case MCK_Reg14: return true; 7138 case MCK_Reg12: return true; 7139 case MCK_GPRnoip: return true; 7140 case MCK_rGPR: return true; 7141 case MCK_GPRnopc: return true; 7142 case MCK_GPRnosp: return true; 7143 case MCK_GPRwithAPSR_NZCVnosp: return true; 7144 case MCK_GPRwithAPSRnosp: return true; 7145 case MCK_GPRwithZRnosp: return true; 7146 case MCK_GPR: return true; 7147 case MCK_GPRwithAPSR: return true; 7148 case MCK_GPRwithZR: return true; 7149 } 7150 7151 case MCK_QPR_8: 7152 switch (B) { 7153 default: return false; 7154 case MCK_Reg52: return true; 7155 case MCK_Reg53: return true; 7156 case MCK_MQPR: return true; 7157 case MCK_Reg50: return true; 7158 case MCK_Reg51: return true; 7159 case MCK_QPR: return true; 7160 case MCK_DPair: return true; 7161 } 7162 7163 case MCK_Reg89: 7164 switch (B) { 7165 default: return false; 7166 case MCK_Reg90: return true; 7167 case MCK_Reg87: return true; 7168 case MCK_Reg88: return true; 7169 case MCK_Reg85: return true; 7170 case MCK_Reg86: return true; 7171 case MCK_Reg83: return true; 7172 case MCK_Reg84: return true; 7173 case MCK_DQuad: return true; 7174 } 7175 7176 case MCK_Reg32: 7177 switch (B) { 7178 default: return false; 7179 case MCK_Reg31: return true; 7180 case MCK_Reg29: return true; 7181 case MCK_hGPR: return true; 7182 case MCK_Reg14: return true; 7183 case MCK_GPRnoip: return true; 7184 case MCK_GPRnosp: return true; 7185 case MCK_GPR: return true; 7186 } 7187 7188 case MCK_Reg30: 7189 switch (B) { 7190 default: return false; 7191 case MCK_Reg31: return true; 7192 case MCK_Reg26: return true; 7193 case MCK_hGPR: return true; 7194 case MCK_Reg12: return true; 7195 case MCK_GPRnoip: return true; 7196 case MCK_GPRnopc: return true; 7197 case MCK_GPR: return true; 7198 case MCK_GPRwithAPSR: return true; 7199 case MCK_GPRwithZR: return true; 7200 } 7201 7202 case MCK_MQQQQPR: 7203 switch (B) { 7204 default: return false; 7205 case MCK_Reg96: return true; 7206 case MCK_Reg97: return true; 7207 case MCK_Reg98: return true; 7208 case MCK_QQQQPR: return true; 7209 } 7210 7211 case MCK_tcGPR: 7212 switch (B) { 7213 default: return false; 7214 case MCK_rGPR: return true; 7215 case MCK_GPRnopc: return true; 7216 case MCK_GPRnosp: return true; 7217 case MCK_GPRwithAPSR_NZCVnosp: return true; 7218 case MCK_GPRwithAPSRnosp: return true; 7219 case MCK_GPRwithZRnosp: return true; 7220 case MCK_GPR: return true; 7221 case MCK_GPRwithAPSR: return true; 7222 case MCK_GPRwithZR: return true; 7223 } 7224 7225 case MCK_Reg135: 7226 switch (B) { 7227 default: return false; 7228 case MCK_Reg136: return true; 7229 case MCK_Reg137: return true; 7230 case MCK_Reg85: return true; 7231 case MCK_Reg138: return true; 7232 case MCK_Reg86: return true; 7233 case MCK_Reg83: return true; 7234 case MCK_Reg84: return true; 7235 case MCK_DQuad: return true; 7236 } 7237 7238 case MCK_Reg126: 7239 switch (B) { 7240 default: return false; 7241 case MCK_Reg127: return true; 7242 case MCK_Reg128: return true; 7243 case MCK_Reg129: return true; 7244 case MCK_Reg130: return true; 7245 case MCK_DTripleSpc: return true; 7246 } 7247 7248 case MCK_Reg108: 7249 switch (B) { 7250 default: return false; 7251 case MCK_Reg109: return true; 7252 case MCK_Reg110: return true; 7253 case MCK_Reg111: return true; 7254 case MCK_Reg112: return true; 7255 case MCK_Reg113: return true; 7256 case MCK_DTriple: return true; 7257 } 7258 7259 case MCK_Reg96: 7260 switch (B) { 7261 default: return false; 7262 case MCK_Reg97: return true; 7263 case MCK_Reg98: return true; 7264 case MCK_QQQQPR: return true; 7265 } 7266 7267 case MCK_Reg90: 7268 switch (B) { 7269 default: return false; 7270 case MCK_Reg87: return true; 7271 case MCK_Reg88: return true; 7272 case MCK_Reg85: return true; 7273 case MCK_Reg86: return true; 7274 case MCK_Reg83: return true; 7275 case MCK_Reg84: return true; 7276 case MCK_DQuad: return true; 7277 } 7278 7279 case MCK_Reg72: 7280 switch (B) { 7281 default: return false; 7282 case MCK_Reg73: return true; 7283 case MCK_Reg74: return true; 7284 case MCK_Reg75: return true; 7285 case MCK_DPairSpc: return true; 7286 } 7287 7288 case MCK_Reg31: 7289 switch (B) { 7290 default: return false; 7291 case MCK_hGPR: return true; 7292 case MCK_GPRnoip: return true; 7293 case MCK_GPR: return true; 7294 } 7295 7296 case MCK_Reg28: 7297 switch (B) { 7298 default: return false; 7299 case MCK_Reg29: return true; 7300 case MCK_Reg26: return true; 7301 case MCK_hGPR: return true; 7302 case MCK_rGPR: return true; 7303 case MCK_GPRnopc: return true; 7304 case MCK_GPRnosp: return true; 7305 case MCK_GPRwithAPSR_NZCVnosp: return true; 7306 case MCK_GPRwithAPSRnosp: return true; 7307 case MCK_GPRwithZRnosp: return true; 7308 case MCK_GPR: return true; 7309 case MCK_GPRwithAPSR: return true; 7310 case MCK_GPRwithZR: return true; 7311 } 7312 7313 case MCK_Reg19: 7314 switch (B) { 7315 default: return false; 7316 case MCK_tGPREven: return true; 7317 case MCK_Reg2: return true; 7318 case MCK_Reg14: return true; 7319 case MCK_Reg12: return true; 7320 case MCK_GPRnoip: return true; 7321 case MCK_rGPR: return true; 7322 case MCK_GPRnopc: return true; 7323 case MCK_GPRnosp: return true; 7324 case MCK_GPRwithAPSR_NZCVnosp: return true; 7325 case MCK_GPRwithAPSRnosp: return true; 7326 case MCK_GPRwithZRnosp: return true; 7327 case MCK_GPR: return true; 7328 case MCK_GPRwithAPSR: return true; 7329 case MCK_GPRwithZR: return true; 7330 } 7331 7332 case MCK_GPRPairnosp: 7333 return B == MCK_GPRPair; 7334 7335 case MCK_tGPROdd: 7336 switch (B) { 7337 default: return false; 7338 case MCK_Reg2: return true; 7339 case MCK_Reg14: return true; 7340 case MCK_Reg12: return true; 7341 case MCK_GPRnoip: return true; 7342 case MCK_rGPR: return true; 7343 case MCK_GPRnopc: return true; 7344 case MCK_GPRnosp: return true; 7345 case MCK_GPRwithAPSR_NZCVnosp: return true; 7346 case MCK_GPRwithAPSRnosp: return true; 7347 case MCK_GPRwithZRnosp: return true; 7348 case MCK_GPR: return true; 7349 case MCK_GPRwithAPSR: return true; 7350 case MCK_GPRwithZR: return true; 7351 } 7352 7353 case MCK_Reg136: 7354 switch (B) { 7355 default: return false; 7356 case MCK_Reg137: return true; 7357 case MCK_Reg138: return true; 7358 case MCK_Reg86: return true; 7359 case MCK_Reg83: return true; 7360 case MCK_Reg84: return true; 7361 case MCK_DQuad: return true; 7362 } 7363 7364 case MCK_Reg122: 7365 switch (B) { 7366 default: return false; 7367 case MCK_Reg123: return true; 7368 case MCK_Reg111: return true; 7369 case MCK_Reg124: return true; 7370 case MCK_Reg112: return true; 7371 case MCK_Reg113: return true; 7372 case MCK_DTriple: return true; 7373 } 7374 7375 case MCK_Reg117: 7376 switch (B) { 7377 default: return false; 7378 case MCK_Reg118: return true; 7379 case MCK_Reg111: return true; 7380 case MCK_Reg119: return true; 7381 case MCK_Reg112: return true; 7382 case MCK_Reg113: return true; 7383 case MCK_DTriple: return true; 7384 } 7385 7386 case MCK_Reg109: 7387 switch (B) { 7388 default: return false; 7389 case MCK_Reg110: return true; 7390 case MCK_Reg111: return true; 7391 case MCK_Reg112: return true; 7392 case MCK_Reg113: return true; 7393 case MCK_DTriple: return true; 7394 } 7395 7396 case MCK_Reg97: 7397 switch (B) { 7398 default: return false; 7399 case MCK_Reg98: return true; 7400 case MCK_QQQQPR: return true; 7401 } 7402 7403 case MCK_Reg87: 7404 switch (B) { 7405 default: return false; 7406 case MCK_Reg88: return true; 7407 case MCK_Reg85: return true; 7408 case MCK_Reg86: return true; 7409 case MCK_Reg83: return true; 7410 case MCK_Reg84: return true; 7411 case MCK_DQuad: return true; 7412 } 7413 7414 case MCK_Reg52: 7415 switch (B) { 7416 default: return false; 7417 case MCK_Reg53: return true; 7418 case MCK_Reg50: return true; 7419 case MCK_Reg51: return true; 7420 case MCK_DPair: return true; 7421 } 7422 7423 case MCK_Reg29: 7424 switch (B) { 7425 default: return false; 7426 case MCK_hGPR: return true; 7427 case MCK_GPRnosp: return true; 7428 case MCK_GPR: return true; 7429 } 7430 7431 case MCK_Reg26: 7432 switch (B) { 7433 default: return false; 7434 case MCK_hGPR: return true; 7435 case MCK_GPRnopc: return true; 7436 case MCK_GPR: return true; 7437 case MCK_GPRwithAPSR: return true; 7438 case MCK_GPRwithZR: return true; 7439 } 7440 7441 case MCK_MQQPR: 7442 switch (B) { 7443 default: return false; 7444 case MCK_Reg80: return true; 7445 case MCK_Reg85: return true; 7446 case MCK_Reg86: return true; 7447 case MCK_Reg83: return true; 7448 case MCK_QQPR: return true; 7449 case MCK_Reg84: return true; 7450 case MCK_DQuad: return true; 7451 } 7452 7453 case MCK_Reg137: 7454 switch (B) { 7455 default: return false; 7456 case MCK_Reg138: return true; 7457 case MCK_Reg84: return true; 7458 case MCK_DQuad: return true; 7459 } 7460 7461 case MCK_Reg127: 7462 switch (B) { 7463 default: return false; 7464 case MCK_Reg128: return true; 7465 case MCK_Reg129: return true; 7466 case MCK_Reg130: return true; 7467 case MCK_DTripleSpc: return true; 7468 } 7469 7470 case MCK_Reg123: 7471 switch (B) { 7472 default: return false; 7473 case MCK_Reg124: return true; 7474 case MCK_Reg113: return true; 7475 case MCK_DTriple: return true; 7476 } 7477 7478 case MCK_Reg118: 7479 switch (B) { 7480 default: return false; 7481 case MCK_Reg119: return true; 7482 case MCK_Reg112: return true; 7483 case MCK_Reg113: return true; 7484 case MCK_DTriple: return true; 7485 } 7486 7487 case MCK_Reg110: 7488 switch (B) { 7489 default: return false; 7490 case MCK_Reg111: return true; 7491 case MCK_Reg112: return true; 7492 case MCK_Reg113: return true; 7493 case MCK_DTriple: return true; 7494 } 7495 7496 case MCK_Reg98: 7497 return B == MCK_QQQQPR; 7498 7499 case MCK_Reg88: 7500 switch (B) { 7501 default: return false; 7502 case MCK_Reg85: return true; 7503 case MCK_Reg86: return true; 7504 case MCK_Reg83: return true; 7505 case MCK_Reg84: return true; 7506 case MCK_DQuad: return true; 7507 } 7508 7509 case MCK_Reg80: 7510 switch (B) { 7511 default: return false; 7512 case MCK_Reg83: return true; 7513 case MCK_QQPR: return true; 7514 case MCK_Reg84: return true; 7515 case MCK_DQuad: return true; 7516 } 7517 7518 case MCK_Reg73: 7519 switch (B) { 7520 default: return false; 7521 case MCK_Reg74: return true; 7522 case MCK_Reg75: return true; 7523 case MCK_DPairSpc: return true; 7524 } 7525 7526 case MCK_Reg53: 7527 switch (B) { 7528 default: return false; 7529 case MCK_Reg50: return true; 7530 case MCK_Reg51: return true; 7531 case MCK_DPair: return true; 7532 } 7533 7534 case MCK_DPR_8: 7535 switch (B) { 7536 default: return false; 7537 case MCK_DPR_VFP2: return true; 7538 case MCK_DPR: return true; 7539 case MCK_FPWithVPR: return true; 7540 } 7541 7542 case MCK_MQPR: 7543 switch (B) { 7544 default: return false; 7545 case MCK_Reg50: return true; 7546 case MCK_Reg51: return true; 7547 case MCK_QPR: return true; 7548 case MCK_DPair: return true; 7549 } 7550 7551 case MCK_hGPR: 7552 return B == MCK_GPR; 7553 7554 case MCK_tGPR: 7555 switch (B) { 7556 default: return false; 7557 case MCK_tGPRwithpc: return true; 7558 case MCK_Reg2: return true; 7559 case MCK_Reg14: return true; 7560 case MCK_Reg12: return true; 7561 case MCK_GPRnoip: return true; 7562 case MCK_rGPR: return true; 7563 case MCK_GPRnopc: return true; 7564 case MCK_GPRnosp: return true; 7565 case MCK_GPRwithAPSR_NZCVnosp: return true; 7566 case MCK_GPRwithAPSRnosp: return true; 7567 case MCK_GPRwithZRnosp: return true; 7568 case MCK_GPR: return true; 7569 case MCK_GPRwithAPSR: return true; 7570 case MCK_GPRwithZR: return true; 7571 } 7572 7573 case MCK_tGPREven: 7574 switch (B) { 7575 default: return false; 7576 case MCK_rGPR: return true; 7577 case MCK_GPRnopc: return true; 7578 case MCK_GPRnosp: return true; 7579 case MCK_GPRwithAPSR_NZCVnosp: return true; 7580 case MCK_GPRwithAPSRnosp: return true; 7581 case MCK_GPRwithZRnosp: return true; 7582 case MCK_GPR: return true; 7583 case MCK_GPRwithAPSR: return true; 7584 case MCK_GPRwithZR: return true; 7585 } 7586 7587 case MCK_tGPRwithpc: 7588 switch (B) { 7589 default: return false; 7590 case MCK_Reg14: return true; 7591 case MCK_GPRnoip: return true; 7592 case MCK_GPRnosp: return true; 7593 case MCK_GPR: return true; 7594 } 7595 7596 case MCK_Reg128: 7597 switch (B) { 7598 default: return false; 7599 case MCK_Reg129: return true; 7600 case MCK_Reg130: return true; 7601 case MCK_DTripleSpc: return true; 7602 } 7603 7604 case MCK_Reg2: 7605 switch (B) { 7606 default: return false; 7607 case MCK_Reg14: return true; 7608 case MCK_Reg12: return true; 7609 case MCK_GPRnoip: return true; 7610 case MCK_rGPR: return true; 7611 case MCK_GPRnopc: return true; 7612 case MCK_GPRnosp: return true; 7613 case MCK_GPRwithAPSR_NZCVnosp: return true; 7614 case MCK_GPRwithAPSRnosp: return true; 7615 case MCK_GPRwithZRnosp: return true; 7616 case MCK_GPR: return true; 7617 case MCK_GPRwithAPSR: return true; 7618 case MCK_GPRwithZR: return true; 7619 } 7620 7621 case MCK_Reg85: 7622 switch (B) { 7623 default: return false; 7624 case MCK_Reg86: return true; 7625 case MCK_Reg83: return true; 7626 case MCK_Reg84: return true; 7627 case MCK_DQuad: return true; 7628 } 7629 7630 case MCK_Reg14: 7631 switch (B) { 7632 default: return false; 7633 case MCK_GPRnoip: return true; 7634 case MCK_GPRnosp: return true; 7635 case MCK_GPR: return true; 7636 } 7637 7638 case MCK_Reg12: 7639 switch (B) { 7640 default: return false; 7641 case MCK_GPRnoip: return true; 7642 case MCK_GPRnopc: return true; 7643 case MCK_GPR: return true; 7644 case MCK_GPRwithAPSR: return true; 7645 case MCK_GPRwithZR: return true; 7646 } 7647 7648 case MCK_Reg138: 7649 return B == MCK_DQuad; 7650 7651 case MCK_Reg129: 7652 switch (B) { 7653 default: return false; 7654 case MCK_Reg130: return true; 7655 case MCK_DTripleSpc: return true; 7656 } 7657 7658 case MCK_Reg111: 7659 switch (B) { 7660 default: return false; 7661 case MCK_Reg112: return true; 7662 case MCK_Reg113: return true; 7663 case MCK_DTriple: return true; 7664 } 7665 7666 case MCK_Reg86: 7667 switch (B) { 7668 default: return false; 7669 case MCK_Reg83: return true; 7670 case MCK_Reg84: return true; 7671 case MCK_DQuad: return true; 7672 } 7673 7674 case MCK_Reg74: 7675 switch (B) { 7676 default: return false; 7677 case MCK_Reg75: return true; 7678 case MCK_DPairSpc: return true; 7679 } 7680 7681 case MCK_GPRnoip: 7682 return B == MCK_GPR; 7683 7684 case MCK_rGPR: 7685 switch (B) { 7686 default: return false; 7687 case MCK_GPRnopc: return true; 7688 case MCK_GPRnosp: return true; 7689 case MCK_GPRwithAPSR_NZCVnosp: return true; 7690 case MCK_GPRwithAPSRnosp: return true; 7691 case MCK_GPRwithZRnosp: return true; 7692 case MCK_GPR: return true; 7693 case MCK_GPRwithAPSR: return true; 7694 case MCK_GPRwithZR: return true; 7695 } 7696 7697 case MCK_Reg124: 7698 return B == MCK_DTriple; 7699 7700 case MCK_Reg119: 7701 return B == MCK_DTriple; 7702 7703 case MCK_Reg112: 7704 switch (B) { 7705 default: return false; 7706 case MCK_Reg113: return true; 7707 case MCK_DTriple: return true; 7708 } 7709 7710 case MCK_Reg83: 7711 switch (B) { 7712 default: return false; 7713 case MCK_Reg84: return true; 7714 case MCK_DQuad: return true; 7715 } 7716 7717 case MCK_Reg50: 7718 switch (B) { 7719 default: return false; 7720 case MCK_Reg51: return true; 7721 case MCK_DPair: return true; 7722 } 7723 7724 case MCK_GPRnopc: 7725 switch (B) { 7726 default: return false; 7727 case MCK_GPR: return true; 7728 case MCK_GPRwithAPSR: return true; 7729 case MCK_GPRwithZR: return true; 7730 } 7731 7732 case MCK_GPRnosp: 7733 return B == MCK_GPR; 7734 7735 case MCK_GPRwithAPSR_NZCVnosp: 7736 return B == MCK_GPRwithAPSR; 7737 7738 case MCK_GPRwithZRnosp: 7739 return B == MCK_GPRwithZR; 7740 7741 case MCK_QQPR: 7742 return B == MCK_DQuad; 7743 7744 case MCK_Reg130: 7745 return B == MCK_DTripleSpc; 7746 7747 case MCK_Reg113: 7748 return B == MCK_DTriple; 7749 7750 case MCK_Reg84: 7751 return B == MCK_DQuad; 7752 7753 case MCK_Reg75: 7754 return B == MCK_DPairSpc; 7755 7756 case MCK_Reg51: 7757 return B == MCK_DPair; 7758 7759 case MCK_DPR_VFP2: 7760 switch (B) { 7761 default: return false; 7762 case MCK_DPR: return true; 7763 case MCK_FPWithVPR: return true; 7764 } 7765 7766 case MCK_QPR: 7767 return B == MCK_DPair; 7768 7769 case MCK_SPR_8: 7770 switch (B) { 7771 default: return false; 7772 case MCK_HPR: return true; 7773 case MCK_FPWithVPR: return true; 7774 } 7775 7776 case MCK_DPR: 7777 return B == MCK_FPWithVPR; 7778 7779 case MCK_HPR: 7780 return B == MCK_FPWithVPR; 7781 } 7782} 7783 7784static unsigned validateOperandClass(MCParsedAsmOperand &GOp, MatchClassKind Kind) { 7785 ARMOperand &Operand = (ARMOperand &)GOp; 7786 if (Kind == InvalidMatchClass) 7787 return MCTargetAsmParser::Match_InvalidOperand; 7788 7789 if (Operand.isToken() && Kind <= MCK_LAST_TOKEN) 7790 return isSubclass(matchTokenString(Operand.getToken()), Kind) ? 7791 MCTargetAsmParser::Match_Success : 7792 MCTargetAsmParser::Match_InvalidOperand; 7793 7794 switch (Kind) { 7795 default: break; 7796 // 'AM2OffsetImm' class 7797 case MCK_AM2OffsetImm: { 7798 DiagnosticPredicate DP(Operand.isAM2OffsetImm()); 7799 if (DP.isMatch()) 7800 return MCTargetAsmParser::Match_Success; 7801 break; 7802 } 7803 // 'AM3Offset' class 7804 case MCK_AM3Offset: { 7805 DiagnosticPredicate DP(Operand.isAM3Offset()); 7806 if (DP.isMatch()) 7807 return MCTargetAsmParser::Match_Success; 7808 break; 7809 } 7810 // 'ARMBranchTarget' class 7811 case MCK_ARMBranchTarget: { 7812 DiagnosticPredicate DP(Operand.isARMBranchTarget()); 7813 if (DP.isMatch()) 7814 return MCTargetAsmParser::Match_Success; 7815 break; 7816 } 7817 // 'AddrMode3' class 7818 case MCK_AddrMode3: { 7819 DiagnosticPredicate DP(Operand.isAddrMode3()); 7820 if (DP.isMatch()) 7821 return MCTargetAsmParser::Match_Success; 7822 break; 7823 } 7824 // 'AddrMode5' class 7825 case MCK_AddrMode5: { 7826 DiagnosticPredicate DP(Operand.isAddrMode5()); 7827 if (DP.isMatch()) 7828 return MCTargetAsmParser::Match_Success; 7829 break; 7830 } 7831 // 'AddrMode5FP16' class 7832 case MCK_AddrMode5FP16: { 7833 DiagnosticPredicate DP(Operand.isAddrMode5FP16()); 7834 if (DP.isMatch()) 7835 return MCTargetAsmParser::Match_Success; 7836 break; 7837 } 7838 // 'AlignedMemory16' class 7839 case MCK_AlignedMemory16: { 7840 DiagnosticPredicate DP(Operand.isAlignedMemory16()); 7841 if (DP.isMatch()) 7842 return MCTargetAsmParser::Match_Success; 7843 if (DP.isNearMatch()) 7844 return ARMAsmParser::Match_AlignedMemory16; 7845 break; 7846 } 7847 // 'AlignedMemory32' class 7848 case MCK_AlignedMemory32: { 7849 DiagnosticPredicate DP(Operand.isAlignedMemory32()); 7850 if (DP.isMatch()) 7851 return MCTargetAsmParser::Match_Success; 7852 if (DP.isNearMatch()) 7853 return ARMAsmParser::Match_AlignedMemory32; 7854 break; 7855 } 7856 // 'AlignedMemory64' class 7857 case MCK_AlignedMemory64: { 7858 DiagnosticPredicate DP(Operand.isAlignedMemory64()); 7859 if (DP.isMatch()) 7860 return MCTargetAsmParser::Match_Success; 7861 if (DP.isNearMatch()) 7862 return ARMAsmParser::Match_AlignedMemory64; 7863 break; 7864 } 7865 // 'AlignedMemory64or128' class 7866 case MCK_AlignedMemory64or128: { 7867 DiagnosticPredicate DP(Operand.isAlignedMemory64or128()); 7868 if (DP.isMatch()) 7869 return MCTargetAsmParser::Match_Success; 7870 if (DP.isNearMatch()) 7871 return ARMAsmParser::Match_AlignedMemory64or128; 7872 break; 7873 } 7874 // 'AlignedMemory64or128or256' class 7875 case MCK_AlignedMemory64or128or256: { 7876 DiagnosticPredicate DP(Operand.isAlignedMemory64or128or256()); 7877 if (DP.isMatch()) 7878 return MCTargetAsmParser::Match_Success; 7879 if (DP.isNearMatch()) 7880 return ARMAsmParser::Match_AlignedMemory64or128or256; 7881 break; 7882 } 7883 // 'AlignedMemoryNone' class 7884 case MCK_AlignedMemoryNone: { 7885 DiagnosticPredicate DP(Operand.isAlignedMemoryNone()); 7886 if (DP.isMatch()) 7887 return MCTargetAsmParser::Match_Success; 7888 if (DP.isNearMatch()) 7889 return ARMAsmParser::Match_AlignedMemoryNone; 7890 break; 7891 } 7892 // 'AlignedMemory' class 7893 case MCK_AlignedMemory: { 7894 DiagnosticPredicate DP(Operand.isAlignedMemory()); 7895 if (DP.isMatch()) 7896 return MCTargetAsmParser::Match_Success; 7897 break; 7898 } 7899 // 'DupAlignedMemory16' class 7900 case MCK_DupAlignedMemory16: { 7901 DiagnosticPredicate DP(Operand.isDupAlignedMemory16()); 7902 if (DP.isMatch()) 7903 return MCTargetAsmParser::Match_Success; 7904 if (DP.isNearMatch()) 7905 return ARMAsmParser::Match_DupAlignedMemory16; 7906 break; 7907 } 7908 // 'DupAlignedMemory32' class 7909 case MCK_DupAlignedMemory32: { 7910 DiagnosticPredicate DP(Operand.isDupAlignedMemory32()); 7911 if (DP.isMatch()) 7912 return MCTargetAsmParser::Match_Success; 7913 if (DP.isNearMatch()) 7914 return ARMAsmParser::Match_DupAlignedMemory32; 7915 break; 7916 } 7917 // 'DupAlignedMemory64' class 7918 case MCK_DupAlignedMemory64: { 7919 DiagnosticPredicate DP(Operand.isDupAlignedMemory64()); 7920 if (DP.isMatch()) 7921 return MCTargetAsmParser::Match_Success; 7922 if (DP.isNearMatch()) 7923 return ARMAsmParser::Match_DupAlignedMemory64; 7924 break; 7925 } 7926 // 'DupAlignedMemory64or128' class 7927 case MCK_DupAlignedMemory64or128: { 7928 DiagnosticPredicate DP(Operand.isDupAlignedMemory64or128()); 7929 if (DP.isMatch()) 7930 return MCTargetAsmParser::Match_Success; 7931 if (DP.isNearMatch()) 7932 return ARMAsmParser::Match_DupAlignedMemory64or128; 7933 break; 7934 } 7935 // 'DupAlignedMemoryNone' class 7936 case MCK_DupAlignedMemoryNone: { 7937 DiagnosticPredicate DP(Operand.isDupAlignedMemoryNone()); 7938 if (DP.isMatch()) 7939 return MCTargetAsmParser::Match_Success; 7940 if (DP.isNearMatch()) 7941 return ARMAsmParser::Match_DupAlignedMemoryNone; 7942 break; 7943 } 7944 // 'AdrLabel' class 7945 case MCK_AdrLabel: { 7946 DiagnosticPredicate DP(Operand.isAdrLabel()); 7947 if (DP.isMatch()) 7948 return MCTargetAsmParser::Match_Success; 7949 break; 7950 } 7951 // 'BankedReg' class 7952 case MCK_BankedReg: { 7953 DiagnosticPredicate DP(Operand.isBankedReg()); 7954 if (DP.isMatch()) 7955 return MCTargetAsmParser::Match_Success; 7956 break; 7957 } 7958 // 'Bitfield' class 7959 case MCK_Bitfield: { 7960 DiagnosticPredicate DP(Operand.isBitfield()); 7961 if (DP.isMatch()) 7962 return MCTargetAsmParser::Match_Success; 7963 break; 7964 } 7965 // 'CCOut' class 7966 case MCK_CCOut: { 7967 DiagnosticPredicate DP(Operand.isCCOut()); 7968 if (DP.isMatch()) 7969 return MCTargetAsmParser::Match_Success; 7970 break; 7971 } 7972 // 'CondCode' class 7973 case MCK_CondCode: { 7974 DiagnosticPredicate DP(Operand.isCondCode()); 7975 if (DP.isMatch()) 7976 return MCTargetAsmParser::Match_Success; 7977 break; 7978 } 7979 // 'CoprocNum' class 7980 case MCK_CoprocNum: { 7981 DiagnosticPredicate DP(Operand.isCoprocNum()); 7982 if (DP.isMatch()) 7983 return MCTargetAsmParser::Match_Success; 7984 break; 7985 } 7986 // 'CoprocOption' class 7987 case MCK_CoprocOption: { 7988 DiagnosticPredicate DP(Operand.isCoprocOption()); 7989 if (DP.isMatch()) 7990 return MCTargetAsmParser::Match_Success; 7991 break; 7992 } 7993 // 'CoprocReg' class 7994 case MCK_CoprocReg: { 7995 DiagnosticPredicate DP(Operand.isCoprocReg()); 7996 if (DP.isMatch()) 7997 return MCTargetAsmParser::Match_Success; 7998 break; 7999 } 8000 // 'DPRRegList' class 8001 case MCK_DPRRegList: { 8002 DiagnosticPredicate DP(Operand.isDPRRegList()); 8003 if (DP.isMatch()) 8004 return MCTargetAsmParser::Match_Success; 8005 if (DP.isNearMatch()) 8006 return ARMAsmParser::Match_DPR_RegList; 8007 break; 8008 } 8009 // 'FPDRegListWithVPR' class 8010 case MCK_FPDRegListWithVPR: { 8011 DiagnosticPredicate DP(Operand.isFPDRegListWithVPR()); 8012 if (DP.isMatch()) 8013 return MCTargetAsmParser::Match_Success; 8014 break; 8015 } 8016 // 'FPImm' class 8017 case MCK_FPImm: { 8018 DiagnosticPredicate DP(Operand.isFPImm()); 8019 if (DP.isMatch()) 8020 return MCTargetAsmParser::Match_Success; 8021 break; 8022 } 8023 // 'FPSRegListWithVPR' class 8024 case MCK_FPSRegListWithVPR: { 8025 DiagnosticPredicate DP(Operand.isFPSRegListWithVPR()); 8026 if (DP.isMatch()) 8027 return MCTargetAsmParser::Match_Success; 8028 break; 8029 } 8030 // 'Imm0_15' class 8031 case MCK_Imm0_15: { 8032 DiagnosticPredicate DP(Operand.isImmediate<0,15>()); 8033 if (DP.isMatch()) 8034 return MCTargetAsmParser::Match_Success; 8035 if (DP.isNearMatch()) 8036 return ARMAsmParser::Match_Imm0_15; 8037 break; 8038 } 8039 // 'Imm0_1' class 8040 case MCK_Imm0_1: { 8041 DiagnosticPredicate DP(Operand.isImmediate<0,1>()); 8042 if (DP.isMatch()) 8043 return MCTargetAsmParser::Match_Success; 8044 if (DP.isNearMatch()) 8045 return ARMAsmParser::Match_Imm0_1; 8046 break; 8047 } 8048 // 'Imm0_239' class 8049 case MCK_Imm0_239: { 8050 DiagnosticPredicate DP(Operand.isImmediate<0,239>()); 8051 if (DP.isMatch()) 8052 return MCTargetAsmParser::Match_Success; 8053 if (DP.isNearMatch()) 8054 return ARMAsmParser::Match_Imm0_239; 8055 break; 8056 } 8057 // 'Imm0_255' class 8058 case MCK_Imm0_255: { 8059 DiagnosticPredicate DP(Operand.isImmediate<0,255>()); 8060 if (DP.isMatch()) 8061 return MCTargetAsmParser::Match_Success; 8062 if (DP.isNearMatch()) 8063 return ARMAsmParser::Match_Imm0_255; 8064 break; 8065 } 8066 // 'Imm0_31' class 8067 case MCK_Imm0_31: { 8068 DiagnosticPredicate DP(Operand.isImmediate<0,31>()); 8069 if (DP.isMatch()) 8070 return MCTargetAsmParser::Match_Success; 8071 if (DP.isNearMatch()) 8072 return ARMAsmParser::Match_Imm0_31; 8073 break; 8074 } 8075 // 'Imm0_32' class 8076 case MCK_Imm0_32: { 8077 DiagnosticPredicate DP(Operand.isImmediate<0,32>()); 8078 if (DP.isMatch()) 8079 return MCTargetAsmParser::Match_Success; 8080 if (DP.isNearMatch()) 8081 return ARMAsmParser::Match_Imm0_32; 8082 break; 8083 } 8084 // 'Imm0_3' class 8085 case MCK_Imm0_3: { 8086 DiagnosticPredicate DP(Operand.isImmediate<0,3>()); 8087 if (DP.isMatch()) 8088 return MCTargetAsmParser::Match_Success; 8089 if (DP.isNearMatch()) 8090 return ARMAsmParser::Match_Imm0_3; 8091 break; 8092 } 8093 // 'Imm0_63' class 8094 case MCK_Imm0_63: { 8095 DiagnosticPredicate DP(Operand.isImmediate<0,63>()); 8096 if (DP.isMatch()) 8097 return MCTargetAsmParser::Match_Success; 8098 if (DP.isNearMatch()) 8099 return ARMAsmParser::Match_Imm0_63; 8100 break; 8101 } 8102 // 'Imm0_65535' class 8103 case MCK_Imm0_65535: { 8104 DiagnosticPredicate DP(Operand.isImmediate<0,65535>()); 8105 if (DP.isMatch()) 8106 return MCTargetAsmParser::Match_Success; 8107 if (DP.isNearMatch()) 8108 return ARMAsmParser::Match_Imm0_65535; 8109 break; 8110 } 8111 // 'Imm0_65535Expr' class 8112 case MCK_Imm0_65535Expr: { 8113 DiagnosticPredicate DP(Operand.isImm0_65535Expr()); 8114 if (DP.isMatch()) 8115 return MCTargetAsmParser::Match_Success; 8116 if (DP.isNearMatch()) 8117 return ARMAsmParser::Match_Imm0_65535Expr; 8118 break; 8119 } 8120 // 'Imm0_7' class 8121 case MCK_Imm0_7: { 8122 DiagnosticPredicate DP(Operand.isImmediate<0,7>()); 8123 if (DP.isMatch()) 8124 return MCTargetAsmParser::Match_Success; 8125 if (DP.isNearMatch()) 8126 return ARMAsmParser::Match_Imm0_7; 8127 break; 8128 } 8129 // 'Imm16' class 8130 case MCK_Imm16: { 8131 DiagnosticPredicate DP(Operand.isImmediate<16,16>()); 8132 if (DP.isMatch()) 8133 return MCTargetAsmParser::Match_Success; 8134 if (DP.isNearMatch()) 8135 return ARMAsmParser::Match_Imm16; 8136 break; 8137 } 8138 // 'Imm1_15' class 8139 case MCK_Imm1_15: { 8140 DiagnosticPredicate DP(Operand.isImmediate<1,15>()); 8141 if (DP.isMatch()) 8142 return MCTargetAsmParser::Match_Success; 8143 if (DP.isNearMatch()) 8144 return ARMAsmParser::Match_Imm1_15; 8145 break; 8146 } 8147 // 'Imm1_16' class 8148 case MCK_Imm1_16: { 8149 DiagnosticPredicate DP(Operand.isImmediate<1,16>()); 8150 if (DP.isMatch()) 8151 return MCTargetAsmParser::Match_Success; 8152 if (DP.isNearMatch()) 8153 return ARMAsmParser::Match_ImmRange1_16; 8154 break; 8155 } 8156 // 'Imm1_31' class 8157 case MCK_Imm1_31: { 8158 DiagnosticPredicate DP(Operand.isImmediate<1,31>()); 8159 if (DP.isMatch()) 8160 return MCTargetAsmParser::Match_Success; 8161 if (DP.isNearMatch()) 8162 return ARMAsmParser::Match_Imm1_31; 8163 break; 8164 } 8165 // 'Imm1_32' class 8166 case MCK_Imm1_32: { 8167 DiagnosticPredicate DP(Operand.isImmediate<1,32>()); 8168 if (DP.isMatch()) 8169 return MCTargetAsmParser::Match_Success; 8170 if (DP.isNearMatch()) 8171 return ARMAsmParser::Match_ImmRange1_32; 8172 break; 8173 } 8174 // 'Imm1_7' class 8175 case MCK_Imm1_7: { 8176 DiagnosticPredicate DP(Operand.isImmediate<1,7>()); 8177 if (DP.isMatch()) 8178 return MCTargetAsmParser::Match_Success; 8179 if (DP.isNearMatch()) 8180 return ARMAsmParser::Match_Imm1_7; 8181 break; 8182 } 8183 // 'Imm24bit' class 8184 case MCK_Imm24bit: { 8185 DiagnosticPredicate DP(Operand.isImmediate<0,16777215>()); 8186 if (DP.isMatch()) 8187 return MCTargetAsmParser::Match_Success; 8188 if (DP.isNearMatch()) 8189 return ARMAsmParser::Match_Imm24bit; 8190 break; 8191 } 8192 // 'Imm256_65535Expr' class 8193 case MCK_Imm256_65535Expr: { 8194 DiagnosticPredicate DP(Operand.isImmediate<256,65535>()); 8195 if (DP.isMatch()) 8196 return MCTargetAsmParser::Match_Success; 8197 if (DP.isNearMatch()) 8198 return ARMAsmParser::Match_Imm256_65535Expr; 8199 break; 8200 } 8201 // 'Imm32' class 8202 case MCK_Imm32: { 8203 DiagnosticPredicate DP(Operand.isImmediate<32,32>()); 8204 if (DP.isMatch()) 8205 return MCTargetAsmParser::Match_Success; 8206 if (DP.isNearMatch()) 8207 return ARMAsmParser::Match_Imm32; 8208 break; 8209 } 8210 // 'Imm8' class 8211 case MCK_Imm8: { 8212 DiagnosticPredicate DP(Operand.isImmediate<8,8>()); 8213 if (DP.isMatch()) 8214 return MCTargetAsmParser::Match_Success; 8215 if (DP.isNearMatch()) 8216 return ARMAsmParser::Match_Imm8; 8217 break; 8218 } 8219 // 'Imm8_255' class 8220 case MCK_Imm8_255: { 8221 DiagnosticPredicate DP(Operand.isImmediate<8,255>()); 8222 if (DP.isMatch()) 8223 return MCTargetAsmParser::Match_Success; 8224 if (DP.isNearMatch()) 8225 return ARMAsmParser::Match_Imm8_255; 8226 break; 8227 } 8228 // 'Imm' class 8229 case MCK_Imm: { 8230 DiagnosticPredicate DP(Operand.isImm()); 8231 if (DP.isMatch()) 8232 return MCTargetAsmParser::Match_Success; 8233 break; 8234 } 8235 // 'InstSyncBarrierOpt' class 8236 case MCK_InstSyncBarrierOpt: { 8237 DiagnosticPredicate DP(Operand.isInstSyncBarrierOpt()); 8238 if (DP.isMatch()) 8239 return MCTargetAsmParser::Match_Success; 8240 break; 8241 } 8242 // 'MSRMask' class 8243 case MCK_MSRMask: { 8244 DiagnosticPredicate DP(Operand.isMSRMask()); 8245 if (DP.isMatch()) 8246 return MCTargetAsmParser::Match_Success; 8247 break; 8248 } 8249 // 'MVEShiftImm1_15' class 8250 case MCK_MVEShiftImm1_15: { 8251 DiagnosticPredicate DP(Operand.isImmediate<1,15>()); 8252 if (DP.isMatch()) 8253 return MCTargetAsmParser::Match_Success; 8254 if (DP.isNearMatch()) 8255 return ARMAsmParser::Match_MVEShiftImm1_15; 8256 break; 8257 } 8258 // 'MVEShiftImm1_7' class 8259 case MCK_MVEShiftImm1_7: { 8260 DiagnosticPredicate DP(Operand.isImmediate<1,7>()); 8261 if (DP.isMatch()) 8262 return MCTargetAsmParser::Match_Success; 8263 if (DP.isNearMatch()) 8264 return ARMAsmParser::Match_MVEShiftImm1_7; 8265 break; 8266 } 8267 // 'VIDUP_imm' class 8268 case MCK_VIDUP_imm: { 8269 DiagnosticPredicate DP(Operand.isPowerTwoInRange<1,8>()); 8270 if (DP.isMatch()) 8271 return MCTargetAsmParser::Match_Success; 8272 if (DP.isNearMatch()) 8273 return ARMAsmParser::Match_VIDUP_imm; 8274 break; 8275 } 8276 // 'MemBarrierOpt' class 8277 case MCK_MemBarrierOpt: { 8278 DiagnosticPredicate DP(Operand.isMemBarrierOpt()); 8279 if (DP.isMatch()) 8280 return MCTargetAsmParser::Match_Success; 8281 break; 8282 } 8283 // 'MemImm0_1020s4Offset' class 8284 case MCK_MemImm0_1020s4Offset: { 8285 DiagnosticPredicate DP(Operand.isMemImm0_1020s4Offset()); 8286 if (DP.isMatch()) 8287 return MCTargetAsmParser::Match_Success; 8288 break; 8289 } 8290 // 'MemImm12Offset' class 8291 case MCK_MemImm12Offset: { 8292 DiagnosticPredicate DP(Operand.isMemImm12Offset()); 8293 if (DP.isMatch()) 8294 return MCTargetAsmParser::Match_Success; 8295 break; 8296 } 8297 // 'MemImm7Shift0Offset' class 8298 case MCK_MemImm7Shift0Offset: { 8299 DiagnosticPredicate DP(Operand.isMemImm7ShiftedOffset<0,ARM::GPRnopcRegClassID>()); 8300 if (DP.isMatch()) 8301 return MCTargetAsmParser::Match_Success; 8302 break; 8303 } 8304 // 'MemImm7Shift0OffsetWB' class 8305 case MCK_MemImm7Shift0OffsetWB: { 8306 DiagnosticPredicate DP(Operand.isMemImm7ShiftedOffset<0,ARM::rGPRRegClassID>()); 8307 if (DP.isMatch()) 8308 return MCTargetAsmParser::Match_Success; 8309 break; 8310 } 8311 // 'MemImm7Shift1Offset' class 8312 case MCK_MemImm7Shift1Offset: { 8313 DiagnosticPredicate DP(Operand.isMemImm7ShiftedOffset<1,ARM::GPRnopcRegClassID>()); 8314 if (DP.isMatch()) 8315 return MCTargetAsmParser::Match_Success; 8316 break; 8317 } 8318 // 'MemImm7Shift1OffsetWB' class 8319 case MCK_MemImm7Shift1OffsetWB: { 8320 DiagnosticPredicate DP(Operand.isMemImm7ShiftedOffset<1,ARM::rGPRRegClassID>()); 8321 if (DP.isMatch()) 8322 return MCTargetAsmParser::Match_Success; 8323 break; 8324 } 8325 // 'MemImm7Shift2Offset' class 8326 case MCK_MemImm7Shift2Offset: { 8327 DiagnosticPredicate DP(Operand.isMemImm7ShiftedOffset<2,ARM::GPRnopcRegClassID>()); 8328 if (DP.isMatch()) 8329 return MCTargetAsmParser::Match_Success; 8330 break; 8331 } 8332 // 'MemImm7Shift2OffsetWB' class 8333 case MCK_MemImm7Shift2OffsetWB: { 8334 DiagnosticPredicate DP(Operand.isMemImm7ShiftedOffset<2,ARM::rGPRRegClassID>()); 8335 if (DP.isMatch()) 8336 return MCTargetAsmParser::Match_Success; 8337 break; 8338 } 8339 // 'MemImm7s4Offset' class 8340 case MCK_MemImm7s4Offset: { 8341 DiagnosticPredicate DP(Operand.isMemImm7s4Offset()); 8342 if (DP.isMatch()) 8343 return MCTargetAsmParser::Match_Success; 8344 break; 8345 } 8346 // 'MemImm8Offset' class 8347 case MCK_MemImm8Offset: { 8348 DiagnosticPredicate DP(Operand.isMemImm8Offset()); 8349 if (DP.isMatch()) 8350 return MCTargetAsmParser::Match_Success; 8351 break; 8352 } 8353 // 'MemImm8s4Offset' class 8354 case MCK_MemImm8s4Offset: { 8355 DiagnosticPredicate DP(Operand.isMemImm8s4Offset()); 8356 if (DP.isMatch()) 8357 return MCTargetAsmParser::Match_Success; 8358 break; 8359 } 8360 // 'MemNegImm8Offset' class 8361 case MCK_MemNegImm8Offset: { 8362 DiagnosticPredicate DP(Operand.isMemNegImm8Offset()); 8363 if (DP.isMatch()) 8364 return MCTargetAsmParser::Match_Success; 8365 break; 8366 } 8367 // 'MemNoOffset' class 8368 case MCK_MemNoOffset: { 8369 DiagnosticPredicate DP(Operand.isMemNoOffset()); 8370 if (DP.isMatch()) 8371 return MCTargetAsmParser::Match_Success; 8372 break; 8373 } 8374 // 'MemNoOffsetT2' class 8375 case MCK_MemNoOffsetT2: { 8376 DiagnosticPredicate DP(Operand.isMemNoOffsetT2()); 8377 if (DP.isMatch()) 8378 return MCTargetAsmParser::Match_Success; 8379 break; 8380 } 8381 // 'MemNoOffsetT2NoSp' class 8382 case MCK_MemNoOffsetT2NoSp: { 8383 DiagnosticPredicate DP(Operand.isMemNoOffsetT2NoSp()); 8384 if (DP.isMatch()) 8385 return MCTargetAsmParser::Match_Success; 8386 break; 8387 } 8388 // 'MemNoOffsetT' class 8389 case MCK_MemNoOffsetT: { 8390 DiagnosticPredicate DP(Operand.isMemNoOffsetT()); 8391 if (DP.isMatch()) 8392 return MCTargetAsmParser::Match_Success; 8393 break; 8394 } 8395 // 'MemPosImm8Offset' class 8396 case MCK_MemPosImm8Offset: { 8397 DiagnosticPredicate DP(Operand.isMemPosImm8Offset()); 8398 if (DP.isMatch()) 8399 return MCTargetAsmParser::Match_Success; 8400 break; 8401 } 8402 // 'MemRegOffset' class 8403 case MCK_MemRegOffset: { 8404 DiagnosticPredicate DP(Operand.isMemRegOffset()); 8405 if (DP.isMatch()) 8406 return MCTargetAsmParser::Match_Success; 8407 break; 8408 } 8409 // 'MemRegQS2Offset' class 8410 case MCK_MemRegQS2Offset: { 8411 DiagnosticPredicate DP(Operand.isMemRegQOffset<2>()); 8412 if (DP.isMatch()) 8413 return MCTargetAsmParser::Match_Success; 8414 break; 8415 } 8416 // 'MemRegQS3Offset' class 8417 case MCK_MemRegQS3Offset: { 8418 DiagnosticPredicate DP(Operand.isMemRegQOffset<3>()); 8419 if (DP.isMatch()) 8420 return MCTargetAsmParser::Match_Success; 8421 break; 8422 } 8423 // 'MemRegRQS0Offset' class 8424 case MCK_MemRegRQS0Offset: { 8425 DiagnosticPredicate DP(Operand.isMemRegRQOffset<0>()); 8426 if (DP.isMatch()) 8427 return MCTargetAsmParser::Match_Success; 8428 break; 8429 } 8430 // 'MemRegRQS1Offset' class 8431 case MCK_MemRegRQS1Offset: { 8432 DiagnosticPredicate DP(Operand.isMemRegRQOffset<1>()); 8433 if (DP.isMatch()) 8434 return MCTargetAsmParser::Match_Success; 8435 break; 8436 } 8437 // 'MemRegRQS2Offset' class 8438 case MCK_MemRegRQS2Offset: { 8439 DiagnosticPredicate DP(Operand.isMemRegRQOffset<2>()); 8440 if (DP.isMatch()) 8441 return MCTargetAsmParser::Match_Success; 8442 break; 8443 } 8444 // 'MemRegRQS3Offset' class 8445 case MCK_MemRegRQS3Offset: { 8446 DiagnosticPredicate DP(Operand.isMemRegRQOffset<3>()); 8447 if (DP.isMatch()) 8448 return MCTargetAsmParser::Match_Success; 8449 break; 8450 } 8451 // 'ModImm' class 8452 case MCK_ModImm: { 8453 DiagnosticPredicate DP(Operand.isModImm()); 8454 if (DP.isMatch()) 8455 return MCTargetAsmParser::Match_Success; 8456 break; 8457 } 8458 // 'ModImmNeg' class 8459 case MCK_ModImmNeg: { 8460 DiagnosticPredicate DP(Operand.isModImmNeg()); 8461 if (DP.isMatch()) 8462 return MCTargetAsmParser::Match_Success; 8463 break; 8464 } 8465 // 'ModImmNot' class 8466 case MCK_ModImmNot: { 8467 DiagnosticPredicate DP(Operand.isModImmNot()); 8468 if (DP.isMatch()) 8469 return MCTargetAsmParser::Match_Success; 8470 break; 8471 } 8472 // 'MveSaturate' class 8473 case MCK_MveSaturate: { 8474 DiagnosticPredicate DP(Operand.isMveSaturateOp()); 8475 if (DP.isMatch()) 8476 return MCTargetAsmParser::Match_Success; 8477 if (DP.isNearMatch()) 8478 return ARMAsmParser::Match_MveSaturate; 8479 break; 8480 } 8481 // 'PKHASRImm' class 8482 case MCK_PKHASRImm: { 8483 DiagnosticPredicate DP(Operand.isPKHASRImm()); 8484 if (DP.isMatch()) 8485 return MCTargetAsmParser::Match_Success; 8486 break; 8487 } 8488 // 'PKHLSLImm' class 8489 case MCK_PKHLSLImm: { 8490 DiagnosticPredicate DP(Operand.isImmediate<0,31>()); 8491 if (DP.isMatch()) 8492 return MCTargetAsmParser::Match_Success; 8493 if (DP.isNearMatch()) 8494 return ARMAsmParser::Match_PKHLSLImm; 8495 break; 8496 } 8497 // 'PostIdxImm8' class 8498 case MCK_PostIdxImm8: { 8499 DiagnosticPredicate DP(Operand.isPostIdxImm8()); 8500 if (DP.isMatch()) 8501 return MCTargetAsmParser::Match_Success; 8502 break; 8503 } 8504 // 'PostIdxImm8s4' class 8505 case MCK_PostIdxImm8s4: { 8506 DiagnosticPredicate DP(Operand.isPostIdxImm8s4()); 8507 if (DP.isMatch()) 8508 return MCTargetAsmParser::Match_Success; 8509 break; 8510 } 8511 // 'PostIdxReg' class 8512 case MCK_PostIdxReg: { 8513 DiagnosticPredicate DP(Operand.isPostIdxReg()); 8514 if (DP.isMatch()) 8515 return MCTargetAsmParser::Match_Success; 8516 break; 8517 } 8518 // 'PostIdxRegShifted' class 8519 case MCK_PostIdxRegShifted: { 8520 DiagnosticPredicate DP(Operand.isPostIdxRegShifted()); 8521 if (DP.isMatch()) 8522 return MCTargetAsmParser::Match_Success; 8523 break; 8524 } 8525 // 'ProcIFlags' class 8526 case MCK_ProcIFlags: { 8527 DiagnosticPredicate DP(Operand.isProcIFlags()); 8528 if (DP.isMatch()) 8529 return MCTargetAsmParser::Match_Success; 8530 break; 8531 } 8532 // 'RegList' class 8533 case MCK_RegList: { 8534 DiagnosticPredicate DP(Operand.isRegList()); 8535 if (DP.isMatch()) 8536 return MCTargetAsmParser::Match_Success; 8537 break; 8538 } 8539 // 'RegListWithAPSR' class 8540 case MCK_RegListWithAPSR: { 8541 DiagnosticPredicate DP(Operand.isRegListWithAPSR()); 8542 if (DP.isMatch()) 8543 return MCTargetAsmParser::Match_Success; 8544 break; 8545 } 8546 // 'RotImm' class 8547 case MCK_RotImm: { 8548 DiagnosticPredicate DP(Operand.isRotImm()); 8549 if (DP.isMatch()) 8550 return MCTargetAsmParser::Match_Success; 8551 break; 8552 } 8553 // 'SPRRegList' class 8554 case MCK_SPRRegList: { 8555 DiagnosticPredicate DP(Operand.isSPRRegList()); 8556 if (DP.isMatch()) 8557 return MCTargetAsmParser::Match_Success; 8558 if (DP.isNearMatch()) 8559 return ARMAsmParser::Match_SPRRegList; 8560 break; 8561 } 8562 // 'SetEndImm' class 8563 case MCK_SetEndImm: { 8564 DiagnosticPredicate DP(Operand.isImmediate<0,1>()); 8565 if (DP.isMatch()) 8566 return MCTargetAsmParser::Match_Success; 8567 if (DP.isNearMatch()) 8568 return ARMAsmParser::Match_SetEndImm; 8569 break; 8570 } 8571 // 'RegShiftedImm' class 8572 case MCK_RegShiftedImm: { 8573 DiagnosticPredicate DP(Operand.isRegShiftedImm()); 8574 if (DP.isMatch()) 8575 return MCTargetAsmParser::Match_Success; 8576 break; 8577 } 8578 // 'RegShiftedReg' class 8579 case MCK_RegShiftedReg: { 8580 DiagnosticPredicate DP(Operand.isRegShiftedReg()); 8581 if (DP.isMatch()) 8582 return MCTargetAsmParser::Match_Success; 8583 break; 8584 } 8585 // 'ShifterImm' class 8586 case MCK_ShifterImm: { 8587 DiagnosticPredicate DP(Operand.isShifterImm()); 8588 if (DP.isMatch()) 8589 return MCTargetAsmParser::Match_Success; 8590 break; 8591 } 8592 // 'ThumbBranchTarget' class 8593 case MCK_ThumbBranchTarget: { 8594 DiagnosticPredicate DP(Operand.isThumbBranchTarget()); 8595 if (DP.isMatch()) 8596 return MCTargetAsmParser::Match_Success; 8597 break; 8598 } 8599 // 'ThumbMemPC' class 8600 case MCK_ThumbMemPC: { 8601 DiagnosticPredicate DP(Operand.isThumbMemPC()); 8602 if (DP.isMatch()) 8603 return MCTargetAsmParser::Match_Success; 8604 break; 8605 } 8606 // 'ThumbModImmNeg1_7' class 8607 case MCK_ThumbModImmNeg1_7: { 8608 DiagnosticPredicate DP(Operand.isThumbModImmNeg1_7()); 8609 if (DP.isMatch()) 8610 return MCTargetAsmParser::Match_Success; 8611 break; 8612 } 8613 // 'ThumbModImmNeg8_255' class 8614 case MCK_ThumbModImmNeg8_255: { 8615 DiagnosticPredicate DP(Operand.isThumbModImmNeg8_255()); 8616 if (DP.isMatch()) 8617 return MCTargetAsmParser::Match_Success; 8618 break; 8619 } 8620 // 'ImmThumbSR' class 8621 case MCK_ImmThumbSR: { 8622 DiagnosticPredicate DP(Operand.isImmediate<1,32>()); 8623 if (DP.isMatch()) 8624 return MCTargetAsmParser::Match_Success; 8625 if (DP.isNearMatch()) 8626 return ARMAsmParser::Match_ImmThumbSR; 8627 break; 8628 } 8629 // 'TraceSyncBarrierOpt' class 8630 case MCK_TraceSyncBarrierOpt: { 8631 DiagnosticPredicate DP(Operand.isTraceSyncBarrierOpt()); 8632 if (DP.isMatch()) 8633 return MCTargetAsmParser::Match_Success; 8634 break; 8635 } 8636 // 'UnsignedOffset_b8s2' class 8637 case MCK_UnsignedOffset_b8s2: { 8638 DiagnosticPredicate DP(Operand.isUnsignedOffset<8, 2>()); 8639 if (DP.isMatch()) 8640 return MCTargetAsmParser::Match_Success; 8641 break; 8642 } 8643 // 'VPTPredN' class 8644 case MCK_VPTPredN: { 8645 DiagnosticPredicate DP(Operand.isVPTPred()); 8646 if (DP.isMatch()) 8647 return MCTargetAsmParser::Match_Success; 8648 break; 8649 } 8650 // 'VPTPredR' class 8651 case MCK_VPTPredR: { 8652 DiagnosticPredicate DP(Operand.isVPTPred()); 8653 if (DP.isMatch()) 8654 return MCTargetAsmParser::Match_Success; 8655 break; 8656 } 8657 // 'VecListTwoMQ' class 8658 case MCK_VecListTwoMQ: { 8659 DiagnosticPredicate DP(Operand.isVecListTwoMQ()); 8660 if (DP.isMatch()) 8661 return MCTargetAsmParser::Match_Success; 8662 if (DP.isNearMatch()) 8663 return ARMAsmParser::Match_VecListTwoMQ; 8664 break; 8665 } 8666 // 'VecListFourMQ' class 8667 case MCK_VecListFourMQ: { 8668 DiagnosticPredicate DP(Operand.isVecListFourMQ()); 8669 if (DP.isMatch()) 8670 return MCTargetAsmParser::Match_Success; 8671 if (DP.isNearMatch()) 8672 return ARMAsmParser::Match_VecListFourMQ; 8673 break; 8674 } 8675 // 'VecListDPairAllLanes' class 8676 case MCK_VecListDPairAllLanes: { 8677 DiagnosticPredicate DP(Operand.isVecListDPairAllLanes()); 8678 if (DP.isMatch()) 8679 return MCTargetAsmParser::Match_Success; 8680 break; 8681 } 8682 // 'VecListDPair' class 8683 case MCK_VecListDPair: { 8684 DiagnosticPredicate DP(Operand.isVecListDPair()); 8685 if (DP.isMatch()) 8686 return MCTargetAsmParser::Match_Success; 8687 break; 8688 } 8689 // 'VecListDPairSpacedAllLanes' class 8690 case MCK_VecListDPairSpacedAllLanes: { 8691 DiagnosticPredicate DP(Operand.isVecListDPairSpacedAllLanes()); 8692 if (DP.isMatch()) 8693 return MCTargetAsmParser::Match_Success; 8694 break; 8695 } 8696 // 'VecListDPairSpaced' class 8697 case MCK_VecListDPairSpaced: { 8698 DiagnosticPredicate DP(Operand.isVecListDPairSpaced()); 8699 if (DP.isMatch()) 8700 return MCTargetAsmParser::Match_Success; 8701 break; 8702 } 8703 // 'VecListFourDAllLanes' class 8704 case MCK_VecListFourDAllLanes: { 8705 DiagnosticPredicate DP(Operand.isVecListFourDAllLanes()); 8706 if (DP.isMatch()) 8707 return MCTargetAsmParser::Match_Success; 8708 break; 8709 } 8710 // 'VecListFourD' class 8711 case MCK_VecListFourD: { 8712 DiagnosticPredicate DP(Operand.isVecListFourD()); 8713 if (DP.isMatch()) 8714 return MCTargetAsmParser::Match_Success; 8715 break; 8716 } 8717 // 'VecListFourDByteIndexed' class 8718 case MCK_VecListFourDByteIndexed: { 8719 DiagnosticPredicate DP(Operand.isVecListFourDByteIndexed()); 8720 if (DP.isMatch()) 8721 return MCTargetAsmParser::Match_Success; 8722 break; 8723 } 8724 // 'VecListFourDHWordIndexed' class 8725 case MCK_VecListFourDHWordIndexed: { 8726 DiagnosticPredicate DP(Operand.isVecListFourDHWordIndexed()); 8727 if (DP.isMatch()) 8728 return MCTargetAsmParser::Match_Success; 8729 break; 8730 } 8731 // 'VecListFourDWordIndexed' class 8732 case MCK_VecListFourDWordIndexed: { 8733 DiagnosticPredicate DP(Operand.isVecListFourDWordIndexed()); 8734 if (DP.isMatch()) 8735 return MCTargetAsmParser::Match_Success; 8736 break; 8737 } 8738 // 'VecListFourQAllLanes' class 8739 case MCK_VecListFourQAllLanes: { 8740 DiagnosticPredicate DP(Operand.isVecListFourQAllLanes()); 8741 if (DP.isMatch()) 8742 return MCTargetAsmParser::Match_Success; 8743 break; 8744 } 8745 // 'VecListFourQ' class 8746 case MCK_VecListFourQ: { 8747 DiagnosticPredicate DP(Operand.isVecListFourQ()); 8748 if (DP.isMatch()) 8749 return MCTargetAsmParser::Match_Success; 8750 break; 8751 } 8752 // 'VecListFourQHWordIndexed' class 8753 case MCK_VecListFourQHWordIndexed: { 8754 DiagnosticPredicate DP(Operand.isVecListFourQHWordIndexed()); 8755 if (DP.isMatch()) 8756 return MCTargetAsmParser::Match_Success; 8757 break; 8758 } 8759 // 'VecListFourQWordIndexed' class 8760 case MCK_VecListFourQWordIndexed: { 8761 DiagnosticPredicate DP(Operand.isVecListFourQWordIndexed()); 8762 if (DP.isMatch()) 8763 return MCTargetAsmParser::Match_Success; 8764 break; 8765 } 8766 // 'VecListOneDAllLanes' class 8767 case MCK_VecListOneDAllLanes: { 8768 DiagnosticPredicate DP(Operand.isVecListOneDAllLanes()); 8769 if (DP.isMatch()) 8770 return MCTargetAsmParser::Match_Success; 8771 break; 8772 } 8773 // 'VecListOneD' class 8774 case MCK_VecListOneD: { 8775 DiagnosticPredicate DP(Operand.isVecListOneD()); 8776 if (DP.isMatch()) 8777 return MCTargetAsmParser::Match_Success; 8778 break; 8779 } 8780 // 'VecListOneDByteIndexed' class 8781 case MCK_VecListOneDByteIndexed: { 8782 DiagnosticPredicate DP(Operand.isVecListOneDByteIndexed()); 8783 if (DP.isMatch()) 8784 return MCTargetAsmParser::Match_Success; 8785 break; 8786 } 8787 // 'VecListOneDHWordIndexed' class 8788 case MCK_VecListOneDHWordIndexed: { 8789 DiagnosticPredicate DP(Operand.isVecListOneDHWordIndexed()); 8790 if (DP.isMatch()) 8791 return MCTargetAsmParser::Match_Success; 8792 break; 8793 } 8794 // 'VecListOneDWordIndexed' class 8795 case MCK_VecListOneDWordIndexed: { 8796 DiagnosticPredicate DP(Operand.isVecListOneDWordIndexed()); 8797 if (DP.isMatch()) 8798 return MCTargetAsmParser::Match_Success; 8799 break; 8800 } 8801 // 'VecListThreeDAllLanes' class 8802 case MCK_VecListThreeDAllLanes: { 8803 DiagnosticPredicate DP(Operand.isVecListThreeDAllLanes()); 8804 if (DP.isMatch()) 8805 return MCTargetAsmParser::Match_Success; 8806 break; 8807 } 8808 // 'VecListThreeD' class 8809 case MCK_VecListThreeD: { 8810 DiagnosticPredicate DP(Operand.isVecListThreeD()); 8811 if (DP.isMatch()) 8812 return MCTargetAsmParser::Match_Success; 8813 break; 8814 } 8815 // 'VecListThreeDByteIndexed' class 8816 case MCK_VecListThreeDByteIndexed: { 8817 DiagnosticPredicate DP(Operand.isVecListThreeDByteIndexed()); 8818 if (DP.isMatch()) 8819 return MCTargetAsmParser::Match_Success; 8820 break; 8821 } 8822 // 'VecListThreeDHWordIndexed' class 8823 case MCK_VecListThreeDHWordIndexed: { 8824 DiagnosticPredicate DP(Operand.isVecListThreeDHWordIndexed()); 8825 if (DP.isMatch()) 8826 return MCTargetAsmParser::Match_Success; 8827 break; 8828 } 8829 // 'VecListThreeDWordIndexed' class 8830 case MCK_VecListThreeDWordIndexed: { 8831 DiagnosticPredicate DP(Operand.isVecListThreeDWordIndexed()); 8832 if (DP.isMatch()) 8833 return MCTargetAsmParser::Match_Success; 8834 break; 8835 } 8836 // 'VecListThreeQAllLanes' class 8837 case MCK_VecListThreeQAllLanes: { 8838 DiagnosticPredicate DP(Operand.isVecListThreeQAllLanes()); 8839 if (DP.isMatch()) 8840 return MCTargetAsmParser::Match_Success; 8841 break; 8842 } 8843 // 'VecListThreeQ' class 8844 case MCK_VecListThreeQ: { 8845 DiagnosticPredicate DP(Operand.isVecListThreeQ()); 8846 if (DP.isMatch()) 8847 return MCTargetAsmParser::Match_Success; 8848 break; 8849 } 8850 // 'VecListThreeQHWordIndexed' class 8851 case MCK_VecListThreeQHWordIndexed: { 8852 DiagnosticPredicate DP(Operand.isVecListThreeQHWordIndexed()); 8853 if (DP.isMatch()) 8854 return MCTargetAsmParser::Match_Success; 8855 break; 8856 } 8857 // 'VecListThreeQWordIndexed' class 8858 case MCK_VecListThreeQWordIndexed: { 8859 DiagnosticPredicate DP(Operand.isVecListThreeQWordIndexed()); 8860 if (DP.isMatch()) 8861 return MCTargetAsmParser::Match_Success; 8862 break; 8863 } 8864 // 'VecListTwoDByteIndexed' class 8865 case MCK_VecListTwoDByteIndexed: { 8866 DiagnosticPredicate DP(Operand.isVecListTwoDByteIndexed()); 8867 if (DP.isMatch()) 8868 return MCTargetAsmParser::Match_Success; 8869 break; 8870 } 8871 // 'VecListTwoDHWordIndexed' class 8872 case MCK_VecListTwoDHWordIndexed: { 8873 DiagnosticPredicate DP(Operand.isVecListTwoDHWordIndexed()); 8874 if (DP.isMatch()) 8875 return MCTargetAsmParser::Match_Success; 8876 break; 8877 } 8878 // 'VecListTwoDWordIndexed' class 8879 case MCK_VecListTwoDWordIndexed: { 8880 DiagnosticPredicate DP(Operand.isVecListTwoDWordIndexed()); 8881 if (DP.isMatch()) 8882 return MCTargetAsmParser::Match_Success; 8883 break; 8884 } 8885 // 'VecListTwoQHWordIndexed' class 8886 case MCK_VecListTwoQHWordIndexed: { 8887 DiagnosticPredicate DP(Operand.isVecListTwoQHWordIndexed()); 8888 if (DP.isMatch()) 8889 return MCTargetAsmParser::Match_Success; 8890 break; 8891 } 8892 // 'VecListTwoQWordIndexed' class 8893 case MCK_VecListTwoQWordIndexed: { 8894 DiagnosticPredicate DP(Operand.isVecListTwoQWordIndexed()); 8895 if (DP.isMatch()) 8896 return MCTargetAsmParser::Match_Success; 8897 break; 8898 } 8899 // 'VectorIndex16' class 8900 case MCK_VectorIndex16: { 8901 DiagnosticPredicate DP(Operand.isVectorIndex16()); 8902 if (DP.isMatch()) 8903 return MCTargetAsmParser::Match_Success; 8904 break; 8905 } 8906 // 'VectorIndex32' class 8907 case MCK_VectorIndex32: { 8908 DiagnosticPredicate DP(Operand.isVectorIndex32()); 8909 if (DP.isMatch()) 8910 return MCTargetAsmParser::Match_Success; 8911 break; 8912 } 8913 // 'VectorIndex64' class 8914 case MCK_VectorIndex64: { 8915 DiagnosticPredicate DP(Operand.isVectorIndex64()); 8916 if (DP.isMatch()) 8917 return MCTargetAsmParser::Match_Success; 8918 break; 8919 } 8920 // 'VectorIndex8' class 8921 case MCK_VectorIndex8: { 8922 DiagnosticPredicate DP(Operand.isVectorIndex8()); 8923 if (DP.isMatch()) 8924 return MCTargetAsmParser::Match_Success; 8925 break; 8926 } 8927 // 'MemTBB' class 8928 case MCK_MemTBB: { 8929 DiagnosticPredicate DP(Operand.isMemTBB()); 8930 if (DP.isMatch()) 8931 return MCTargetAsmParser::Match_Success; 8932 break; 8933 } 8934 // 'MemTBH' class 8935 case MCK_MemTBH: { 8936 DiagnosticPredicate DP(Operand.isMemTBH()); 8937 if (DP.isMatch()) 8938 return MCTargetAsmParser::Match_Success; 8939 break; 8940 } 8941 // 'MVEPairVectorIndex0' class 8942 case MCK_MVEPairVectorIndex0: { 8943 DiagnosticPredicate DP(Operand.isMVEPairVectorIndex<0, 1>()); 8944 if (DP.isMatch()) 8945 return MCTargetAsmParser::Match_Success; 8946 break; 8947 } 8948 // 'MVEPairVectorIndex2' class 8949 case MCK_MVEPairVectorIndex2: { 8950 DiagnosticPredicate DP(Operand.isMVEPairVectorIndex<2, 3>()); 8951 if (DP.isMatch()) 8952 return MCTargetAsmParser::Match_Success; 8953 break; 8954 } 8955 // 'ComplexRotationEven' class 8956 case MCK_ComplexRotationEven: { 8957 DiagnosticPredicate DP(Operand.isComplexRotation<90, 0>()); 8958 if (DP.isMatch()) 8959 return MCTargetAsmParser::Match_Success; 8960 if (DP.isNearMatch()) 8961 return ARMAsmParser::Match_ComplexRotationEven; 8962 break; 8963 } 8964 // 'ComplexRotationOdd' class 8965 case MCK_ComplexRotationOdd: { 8966 DiagnosticPredicate DP(Operand.isComplexRotation<180, 90>()); 8967 if (DP.isMatch()) 8968 return MCTargetAsmParser::Match_Success; 8969 if (DP.isNearMatch()) 8970 return ARMAsmParser::Match_ComplexRotationOdd; 8971 break; 8972 } 8973 // 'NEONi16vmovi8Replicate' class 8974 case MCK_NEONi16vmovi8Replicate: { 8975 DiagnosticPredicate DP(Operand.isNEONmovReplicate<8, 16>()); 8976 if (DP.isMatch()) 8977 return MCTargetAsmParser::Match_Success; 8978 break; 8979 } 8980 // 'NEONi16invi8Replicate' class 8981 case MCK_NEONi16invi8Replicate: { 8982 DiagnosticPredicate DP(Operand.isNEONinvReplicate<8, 16>()); 8983 if (DP.isMatch()) 8984 return MCTargetAsmParser::Match_Success; 8985 break; 8986 } 8987 // 'NEONi32vmovi8Replicate' class 8988 case MCK_NEONi32vmovi8Replicate: { 8989 DiagnosticPredicate DP(Operand.isNEONmovReplicate<8, 32>()); 8990 if (DP.isMatch()) 8991 return MCTargetAsmParser::Match_Success; 8992 break; 8993 } 8994 // 'NEONi32invi8Replicate' class 8995 case MCK_NEONi32invi8Replicate: { 8996 DiagnosticPredicate DP(Operand.isNEONinvReplicate<8, 32>()); 8997 if (DP.isMatch()) 8998 return MCTargetAsmParser::Match_Success; 8999 break; 9000 } 9001 // 'NEONi64vmovi8Replicate' class 9002 case MCK_NEONi64vmovi8Replicate: { 9003 DiagnosticPredicate DP(Operand.isNEONmovReplicate<8, 64>()); 9004 if (DP.isMatch()) 9005 return MCTargetAsmParser::Match_Success; 9006 break; 9007 } 9008 // 'NEONi64invi8Replicate' class 9009 case MCK_NEONi64invi8Replicate: { 9010 DiagnosticPredicate DP(Operand.isNEONinvReplicate<8, 64>()); 9011 if (DP.isMatch()) 9012 return MCTargetAsmParser::Match_Success; 9013 break; 9014 } 9015 // 'NEONi32vmovi16Replicate' class 9016 case MCK_NEONi32vmovi16Replicate: { 9017 DiagnosticPredicate DP(Operand.isNEONmovReplicate<16, 32>()); 9018 if (DP.isMatch()) 9019 return MCTargetAsmParser::Match_Success; 9020 break; 9021 } 9022 // 'NEONi64vmovi16Replicate' class 9023 case MCK_NEONi64vmovi16Replicate: { 9024 DiagnosticPredicate DP(Operand.isNEONmovReplicate<16, 64>()); 9025 if (DP.isMatch()) 9026 return MCTargetAsmParser::Match_Success; 9027 break; 9028 } 9029 // 'NEONi64vmovi32Replicate' class 9030 case MCK_NEONi64vmovi32Replicate: { 9031 DiagnosticPredicate DP(Operand.isNEONmovReplicate<32, 64>()); 9032 if (DP.isMatch()) 9033 return MCTargetAsmParser::Match_Success; 9034 break; 9035 } 9036 // 'MVEVectorIndex4' class 9037 case MCK_MVEVectorIndex4: { 9038 DiagnosticPredicate DP(Operand.isVectorIndexInRange<4>()); 9039 if (DP.isMatch()) 9040 return MCTargetAsmParser::Match_Success; 9041 break; 9042 } 9043 // 'MVEVectorIndex8' class 9044 case MCK_MVEVectorIndex8: { 9045 DiagnosticPredicate DP(Operand.isVectorIndexInRange<8>()); 9046 if (DP.isMatch()) 9047 return MCTargetAsmParser::Match_Success; 9048 break; 9049 } 9050 // 'MVEVectorIndex16' class 9051 case MCK_MVEVectorIndex16: { 9052 DiagnosticPredicate DP(Operand.isVectorIndexInRange<16>()); 9053 if (DP.isMatch()) 9054 return MCTargetAsmParser::Match_Success; 9055 break; 9056 } 9057 // 'MVEVcvtImm32' class 9058 case MCK_MVEVcvtImm32: { 9059 DiagnosticPredicate DP(Operand.isImmediate<1,32>()); 9060 if (DP.isMatch()) 9061 return MCTargetAsmParser::Match_Success; 9062 if (DP.isNearMatch()) 9063 return ARMAsmParser::Match_MVEVcvtImm32; 9064 break; 9065 } 9066 // 'MVEVcvtImm16' class 9067 case MCK_MVEVcvtImm16: { 9068 DiagnosticPredicate DP(Operand.isImmediate<1,16>()); 9069 if (DP.isMatch()) 9070 return MCTargetAsmParser::Match_Success; 9071 if (DP.isNearMatch()) 9072 return ARMAsmParser::Match_MVEVcvtImm16; 9073 break; 9074 } 9075 // 'TMemImm7Shift2Offset' class 9076 case MCK_TMemImm7Shift2Offset: { 9077 DiagnosticPredicate DP(Operand.isMemImm7ShiftedOffset<2,ARM::tGPRRegClassID>()); 9078 if (DP.isMatch()) 9079 return MCTargetAsmParser::Match_Success; 9080 break; 9081 } 9082 // 'TMemImm7Shift0Offset' class 9083 case MCK_TMemImm7Shift0Offset: { 9084 DiagnosticPredicate DP(Operand.isMemImm7ShiftedOffset<0,ARM::tGPRRegClassID>()); 9085 if (DP.isMatch()) 9086 return MCTargetAsmParser::Match_Success; 9087 break; 9088 } 9089 // 'TMemImm7Shift1Offset' class 9090 case MCK_TMemImm7Shift1Offset: { 9091 DiagnosticPredicate DP(Operand.isMemImm7ShiftedOffset<1,ARM::tGPRRegClassID>()); 9092 if (DP.isMatch()) 9093 return MCTargetAsmParser::Match_Success; 9094 break; 9095 } 9096 // 'Imm3b' class 9097 case MCK_Imm3b: { 9098 DiagnosticPredicate DP(Operand.isImmediate<0,7>()); 9099 if (DP.isMatch()) 9100 return MCTargetAsmParser::Match_Success; 9101 if (DP.isNearMatch()) 9102 return ARMAsmParser::Match_Imm3b; 9103 break; 9104 } 9105 // 'Imm4b' class 9106 case MCK_Imm4b: { 9107 DiagnosticPredicate DP(Operand.isImmediate<0,15>()); 9108 if (DP.isMatch()) 9109 return MCTargetAsmParser::Match_Success; 9110 if (DP.isNearMatch()) 9111 return ARMAsmParser::Match_Imm4b; 9112 break; 9113 } 9114 // 'Imm6b' class 9115 case MCK_Imm6b: { 9116 DiagnosticPredicate DP(Operand.isImmediate<0,63>()); 9117 if (DP.isMatch()) 9118 return MCTargetAsmParser::Match_Success; 9119 if (DP.isNearMatch()) 9120 return ARMAsmParser::Match_Imm6b; 9121 break; 9122 } 9123 // 'Imm7b' class 9124 case MCK_Imm7b: { 9125 DiagnosticPredicate DP(Operand.isImmediate<0,127>()); 9126 if (DP.isMatch()) 9127 return MCTargetAsmParser::Match_Success; 9128 if (DP.isNearMatch()) 9129 return ARMAsmParser::Match_Imm7b; 9130 break; 9131 } 9132 // 'Imm9b' class 9133 case MCK_Imm9b: { 9134 DiagnosticPredicate DP(Operand.isImmediate<0,511>()); 9135 if (DP.isMatch()) 9136 return MCTargetAsmParser::Match_Success; 9137 if (DP.isNearMatch()) 9138 return ARMAsmParser::Match_Imm9b; 9139 break; 9140 } 9141 // 'Imm11b' class 9142 case MCK_Imm11b: { 9143 DiagnosticPredicate DP(Operand.isImmediate<0,2047>()); 9144 if (DP.isMatch()) 9145 return MCTargetAsmParser::Match_Success; 9146 if (DP.isNearMatch()) 9147 return ARMAsmParser::Match_Imm11b; 9148 break; 9149 } 9150 // 'Imm12b' class 9151 case MCK_Imm12b: { 9152 DiagnosticPredicate DP(Operand.isImmediate<0,4095>()); 9153 if (DP.isMatch()) 9154 return MCTargetAsmParser::Match_Success; 9155 if (DP.isNearMatch()) 9156 return ARMAsmParser::Match_Imm12b; 9157 break; 9158 } 9159 // 'Imm13b' class 9160 case MCK_Imm13b: { 9161 DiagnosticPredicate DP(Operand.isImmediate<0,8191>()); 9162 if (DP.isMatch()) 9163 return MCTargetAsmParser::Match_Success; 9164 if (DP.isNearMatch()) 9165 return ARMAsmParser::Match_Imm13b; 9166 break; 9167 } 9168 // 'ConstPoolAsmImm' class 9169 case MCK_ConstPoolAsmImm: { 9170 DiagnosticPredicate DP(Operand.isConstPoolAsmImm()); 9171 if (DP.isMatch()) 9172 return MCTargetAsmParser::Match_Success; 9173 break; 9174 } 9175 // 'FBits16' class 9176 case MCK_FBits16: { 9177 DiagnosticPredicate DP(Operand.isFBits16()); 9178 if (DP.isMatch()) 9179 return MCTargetAsmParser::Match_Success; 9180 break; 9181 } 9182 // 'FBits32' class 9183 case MCK_FBits32: { 9184 DiagnosticPredicate DP(Operand.isFBits32()); 9185 if (DP.isMatch()) 9186 return MCTargetAsmParser::Match_Success; 9187 break; 9188 } 9189 // 'Imm0_4095' class 9190 case MCK_Imm0_4095: { 9191 DiagnosticPredicate DP(Operand.isImmediate<0,4095>()); 9192 if (DP.isMatch()) 9193 return MCTargetAsmParser::Match_Success; 9194 if (DP.isNearMatch()) 9195 return ARMAsmParser::Match_Imm0_4095; 9196 break; 9197 } 9198 // 'Imm0_4095Neg' class 9199 case MCK_Imm0_4095Neg: { 9200 DiagnosticPredicate DP(Operand.isImm0_4095Neg()); 9201 if (DP.isMatch()) 9202 return MCTargetAsmParser::Match_Success; 9203 break; 9204 } 9205 // 'ITMask' class 9206 case MCK_ITMask: { 9207 DiagnosticPredicate DP(Operand.isITMask()); 9208 if (DP.isMatch()) 9209 return MCTargetAsmParser::Match_Success; 9210 break; 9211 } 9212 // 'ITCondCode' class 9213 case MCK_ITCondCode: { 9214 DiagnosticPredicate DP(Operand.isITCondCode()); 9215 if (DP.isMatch()) 9216 return MCTargetAsmParser::Match_Success; 9217 break; 9218 } 9219 // 'LELabel' class 9220 case MCK_LELabel: { 9221 DiagnosticPredicate DP(Operand.isLEOffset()); 9222 if (DP.isMatch()) 9223 return MCTargetAsmParser::Match_Success; 9224 if (DP.isNearMatch()) 9225 return ARMAsmParser::Match_LELabel; 9226 break; 9227 } 9228 // 'MVELongShift' class 9229 case MCK_MVELongShift: { 9230 DiagnosticPredicate DP(Operand.isMVELongShift()); 9231 if (DP.isMatch()) 9232 return MCTargetAsmParser::Match_Success; 9233 if (DP.isNearMatch()) 9234 return ARMAsmParser::Match_MVELongShift; 9235 break; 9236 } 9237 // 'NEONi16splat' class 9238 case MCK_NEONi16splat: { 9239 DiagnosticPredicate DP(Operand.isNEONi16splat()); 9240 if (DP.isMatch()) 9241 return MCTargetAsmParser::Match_Success; 9242 break; 9243 } 9244 // 'NEONi32splat' class 9245 case MCK_NEONi32splat: { 9246 DiagnosticPredicate DP(Operand.isNEONi32splat()); 9247 if (DP.isMatch()) 9248 return MCTargetAsmParser::Match_Success; 9249 break; 9250 } 9251 // 'NEONi64splat' class 9252 case MCK_NEONi64splat: { 9253 DiagnosticPredicate DP(Operand.isNEONi64splat()); 9254 if (DP.isMatch()) 9255 return MCTargetAsmParser::Match_Success; 9256 break; 9257 } 9258 // 'NEONi8splat' class 9259 case MCK_NEONi8splat: { 9260 DiagnosticPredicate DP(Operand.isNEONi8splat()); 9261 if (DP.isMatch()) 9262 return MCTargetAsmParser::Match_Success; 9263 break; 9264 } 9265 // 'NEONi16splatNot' class 9266 case MCK_NEONi16splatNot: { 9267 DiagnosticPredicate DP(Operand.isNEONi16splatNot()); 9268 if (DP.isMatch()) 9269 return MCTargetAsmParser::Match_Success; 9270 break; 9271 } 9272 // 'NEONi32splatNot' class 9273 case MCK_NEONi32splatNot: { 9274 DiagnosticPredicate DP(Operand.isNEONi32splatNot()); 9275 if (DP.isMatch()) 9276 return MCTargetAsmParser::Match_Success; 9277 break; 9278 } 9279 // 'NEONi32vmov' class 9280 case MCK_NEONi32vmov: { 9281 DiagnosticPredicate DP(Operand.isNEONi32vmov()); 9282 if (DP.isMatch()) 9283 return MCTargetAsmParser::Match_Success; 9284 break; 9285 } 9286 // 'NEONi32vmovNeg' class 9287 case MCK_NEONi32vmovNeg: { 9288 DiagnosticPredicate DP(Operand.isNEONi32vmovNeg()); 9289 if (DP.isMatch()) 9290 return MCTargetAsmParser::Match_Success; 9291 break; 9292 } 9293 // 'CondCodeNoAL' class 9294 case MCK_CondCodeNoAL: { 9295 DiagnosticPredicate DP(Operand.isITCondCodeNoAL()); 9296 if (DP.isMatch()) 9297 return MCTargetAsmParser::Match_Success; 9298 break; 9299 } 9300 // 'CondCodeNoALInv' class 9301 case MCK_CondCodeNoALInv: { 9302 DiagnosticPredicate DP(Operand.isITCondCodeNoAL()); 9303 if (DP.isMatch()) 9304 return MCTargetAsmParser::Match_Success; 9305 break; 9306 } 9307 // 'CondCodeRestrictedFP' class 9308 case MCK_CondCodeRestrictedFP: { 9309 DiagnosticPredicate DP(Operand.isITCondCodeRestrictedFP()); 9310 if (DP.isMatch()) 9311 return MCTargetAsmParser::Match_Success; 9312 if (DP.isNearMatch()) 9313 return ARMAsmParser::Match_CondCodeRestrictedFP; 9314 break; 9315 } 9316 // 'CondCodeRestrictedI' class 9317 case MCK_CondCodeRestrictedI: { 9318 DiagnosticPredicate DP(Operand.isITCondCodeRestrictedI()); 9319 if (DP.isMatch()) 9320 return MCTargetAsmParser::Match_Success; 9321 if (DP.isNearMatch()) 9322 return ARMAsmParser::Match_CondCodeRestrictedI; 9323 break; 9324 } 9325 // 'CondCodeRestrictedS' class 9326 case MCK_CondCodeRestrictedS: { 9327 DiagnosticPredicate DP(Operand.isITCondCodeRestrictedS()); 9328 if (DP.isMatch()) 9329 return MCTargetAsmParser::Match_Success; 9330 if (DP.isNearMatch()) 9331 return ARMAsmParser::Match_CondCodeRestrictedS; 9332 break; 9333 } 9334 // 'CondCodeRestrictedU' class 9335 case MCK_CondCodeRestrictedU: { 9336 DiagnosticPredicate DP(Operand.isITCondCodeRestrictedU()); 9337 if (DP.isMatch()) 9338 return MCTargetAsmParser::Match_Success; 9339 if (DP.isNearMatch()) 9340 return ARMAsmParser::Match_CondCodeRestrictedU; 9341 break; 9342 } 9343 // 'ShrImm16' class 9344 case MCK_ShrImm16: { 9345 DiagnosticPredicate DP(Operand.isImmediate<1,16>()); 9346 if (DP.isMatch()) 9347 return MCTargetAsmParser::Match_Success; 9348 if (DP.isNearMatch()) 9349 return ARMAsmParser::Match_ShrImm16; 9350 break; 9351 } 9352 // 'ShrImm32' class 9353 case MCK_ShrImm32: { 9354 DiagnosticPredicate DP(Operand.isImmediate<1,32>()); 9355 if (DP.isMatch()) 9356 return MCTargetAsmParser::Match_Success; 9357 if (DP.isNearMatch()) 9358 return ARMAsmParser::Match_ShrImm32; 9359 break; 9360 } 9361 // 'ShrImm64' class 9362 case MCK_ShrImm64: { 9363 DiagnosticPredicate DP(Operand.isImmediate<1,64>()); 9364 if (DP.isMatch()) 9365 return MCTargetAsmParser::Match_Success; 9366 if (DP.isNearMatch()) 9367 return ARMAsmParser::Match_ShrImm64; 9368 break; 9369 } 9370 // 'ShrImm8' class 9371 case MCK_ShrImm8: { 9372 DiagnosticPredicate DP(Operand.isImmediate<1,8>()); 9373 if (DP.isMatch()) 9374 return MCTargetAsmParser::Match_Success; 9375 if (DP.isNearMatch()) 9376 return ARMAsmParser::Match_ShrImm8; 9377 break; 9378 } 9379 // 'T2SOImm' class 9380 case MCK_T2SOImm: { 9381 DiagnosticPredicate DP(Operand.isT2SOImm()); 9382 if (DP.isMatch()) 9383 return MCTargetAsmParser::Match_Success; 9384 break; 9385 } 9386 // 'T2SOImmNeg' class 9387 case MCK_T2SOImmNeg: { 9388 DiagnosticPredicate DP(Operand.isT2SOImmNeg()); 9389 if (DP.isMatch()) 9390 return MCTargetAsmParser::Match_Success; 9391 break; 9392 } 9393 // 'T2SOImmNot' class 9394 case MCK_T2SOImmNot: { 9395 DiagnosticPredicate DP(Operand.isT2SOImmNot()); 9396 if (DP.isMatch()) 9397 return MCTargetAsmParser::Match_Success; 9398 break; 9399 } 9400 // 'MemUImm12Offset' class 9401 case MCK_MemUImm12Offset: { 9402 DiagnosticPredicate DP(Operand.isMemUImm12Offset()); 9403 if (DP.isMatch()) 9404 return MCTargetAsmParser::Match_Success; 9405 break; 9406 } 9407 // 'T2MemRegOffset' class 9408 case MCK_T2MemRegOffset: { 9409 DiagnosticPredicate DP(Operand.isT2MemRegOffset()); 9410 if (DP.isMatch()) 9411 return MCTargetAsmParser::Match_Success; 9412 break; 9413 } 9414 // 'Imm7s4' class 9415 case MCK_Imm7s4: { 9416 DiagnosticPredicate DP(Operand.isImm7s4()); 9417 if (DP.isMatch()) 9418 return MCTargetAsmParser::Match_Success; 9419 break; 9420 } 9421 // 'Imm7Shift0' class 9422 case MCK_Imm7Shift0: { 9423 DiagnosticPredicate DP(Operand.isImm7Shift0()); 9424 if (DP.isMatch()) 9425 return MCTargetAsmParser::Match_Success; 9426 break; 9427 } 9428 // 'Imm7Shift1' class 9429 case MCK_Imm7Shift1: { 9430 DiagnosticPredicate DP(Operand.isImm7Shift1()); 9431 if (DP.isMatch()) 9432 return MCTargetAsmParser::Match_Success; 9433 break; 9434 } 9435 // 'Imm7Shift2' class 9436 case MCK_Imm7Shift2: { 9437 DiagnosticPredicate DP(Operand.isImm7Shift2()); 9438 if (DP.isMatch()) 9439 return MCTargetAsmParser::Match_Success; 9440 break; 9441 } 9442 // 'Imm8s4' class 9443 case MCK_Imm8s4: { 9444 DiagnosticPredicate DP(Operand.isImm8s4()); 9445 if (DP.isMatch()) 9446 return MCTargetAsmParser::Match_Success; 9447 break; 9448 } 9449 // 'MemPCRelImm12' class 9450 case MCK_MemPCRelImm12: { 9451 DiagnosticPredicate DP(Operand.isMemPCRelImm12()); 9452 if (DP.isMatch()) 9453 return MCTargetAsmParser::Match_Success; 9454 break; 9455 } 9456 // 'MemThumbRIs1' class 9457 case MCK_MemThumbRIs1: { 9458 DiagnosticPredicate DP(Operand.isMemThumbRIs1()); 9459 if (DP.isMatch()) 9460 return MCTargetAsmParser::Match_Success; 9461 break; 9462 } 9463 // 'MemThumbRIs2' class 9464 case MCK_MemThumbRIs2: { 9465 DiagnosticPredicate DP(Operand.isMemThumbRIs2()); 9466 if (DP.isMatch()) 9467 return MCTargetAsmParser::Match_Success; 9468 break; 9469 } 9470 // 'MemThumbRIs4' class 9471 case MCK_MemThumbRIs4: { 9472 DiagnosticPredicate DP(Operand.isMemThumbRIs4()); 9473 if (DP.isMatch()) 9474 return MCTargetAsmParser::Match_Success; 9475 break; 9476 } 9477 // 'MemThumbRR' class 9478 case MCK_MemThumbRR: { 9479 DiagnosticPredicate DP(Operand.isMemThumbRR()); 9480 if (DP.isMatch()) 9481 return MCTargetAsmParser::Match_Success; 9482 break; 9483 } 9484 // 'MemThumbSPI' class 9485 case MCK_MemThumbSPI: { 9486 DiagnosticPredicate DP(Operand.isMemThumbSPI()); 9487 if (DP.isMatch()) 9488 return MCTargetAsmParser::Match_Success; 9489 break; 9490 } 9491 // 'Imm0_1020s4' class 9492 case MCK_Imm0_1020s4: { 9493 DiagnosticPredicate DP(Operand.isImm0_1020s4()); 9494 if (DP.isMatch()) 9495 return MCTargetAsmParser::Match_Success; 9496 break; 9497 } 9498 // 'Imm0_508s4' class 9499 case MCK_Imm0_508s4: { 9500 DiagnosticPredicate DP(Operand.isImm0_508s4()); 9501 if (DP.isMatch()) 9502 return MCTargetAsmParser::Match_Success; 9503 break; 9504 } 9505 // 'Imm0_508s4Neg' class 9506 case MCK_Imm0_508s4Neg: { 9507 DiagnosticPredicate DP(Operand.isImm0_508s4Neg()); 9508 if (DP.isMatch()) 9509 return MCTargetAsmParser::Match_Success; 9510 break; 9511 } 9512 // 'WLSLabel' class 9513 case MCK_WLSLabel: { 9514 DiagnosticPredicate DP(Operand.isUnsignedOffset<11, 1>()); 9515 if (DP.isMatch()) 9516 return MCTargetAsmParser::Match_Success; 9517 if (DP.isNearMatch()) 9518 return ARMAsmParser::Match_WLSLabel; 9519 break; 9520 } 9521 } // end switch (Kind) 9522 9523 if (Operand.isReg()) { 9524 MatchClassKind OpKind; 9525 switch (Operand.getReg()) { 9526 default: OpKind = InvalidMatchClass; break; 9527 case ARM::R0: OpKind = MCK_Reg17; break; 9528 case ARM::R1: OpKind = MCK_Reg22; break; 9529 case ARM::R2: OpKind = MCK_Reg17; break; 9530 case ARM::R3: OpKind = MCK_Reg22; break; 9531 case ARM::R4: OpKind = MCK_Reg18; break; 9532 case ARM::R5: OpKind = MCK_Reg23; break; 9533 case ARM::R6: OpKind = MCK_Reg18; break; 9534 case ARM::R7: OpKind = MCK_Reg23; break; 9535 case ARM::R8: OpKind = MCK_Reg33; break; 9536 case ARM::R9: OpKind = MCK_Reg35; break; 9537 case ARM::R10: OpKind = MCK_Reg33; break; 9538 case ARM::R11: OpKind = MCK_Reg35; break; 9539 case ARM::R12: OpKind = MCK_R12; break; 9540 case ARM::SP: OpKind = MCK_GPRsp; break; 9541 case ARM::LR: OpKind = MCK_GPRlr; break; 9542 case ARM::PC: OpKind = MCK_PC; break; 9543 case ARM::S0: OpKind = MCK_SPR_8; break; 9544 case ARM::S1: OpKind = MCK_SPR_8; break; 9545 case ARM::S2: OpKind = MCK_SPR_8; break; 9546 case ARM::S3: OpKind = MCK_SPR_8; break; 9547 case ARM::S4: OpKind = MCK_SPR_8; break; 9548 case ARM::S5: OpKind = MCK_SPR_8; break; 9549 case ARM::S6: OpKind = MCK_SPR_8; break; 9550 case ARM::S7: OpKind = MCK_SPR_8; break; 9551 case ARM::S8: OpKind = MCK_SPR_8; break; 9552 case ARM::S9: OpKind = MCK_SPR_8; break; 9553 case ARM::S10: OpKind = MCK_SPR_8; break; 9554 case ARM::S11: OpKind = MCK_SPR_8; break; 9555 case ARM::S12: OpKind = MCK_SPR_8; break; 9556 case ARM::S13: OpKind = MCK_SPR_8; break; 9557 case ARM::S14: OpKind = MCK_SPR_8; break; 9558 case ARM::S15: OpKind = MCK_SPR_8; break; 9559 case ARM::S16: OpKind = MCK_HPR; break; 9560 case ARM::S17: OpKind = MCK_HPR; break; 9561 case ARM::S18: OpKind = MCK_HPR; break; 9562 case ARM::S19: OpKind = MCK_HPR; break; 9563 case ARM::S20: OpKind = MCK_HPR; break; 9564 case ARM::S21: OpKind = MCK_HPR; break; 9565 case ARM::S22: OpKind = MCK_HPR; break; 9566 case ARM::S23: OpKind = MCK_HPR; break; 9567 case ARM::S24: OpKind = MCK_HPR; break; 9568 case ARM::S25: OpKind = MCK_HPR; break; 9569 case ARM::S26: OpKind = MCK_HPR; break; 9570 case ARM::S27: OpKind = MCK_HPR; break; 9571 case ARM::S28: OpKind = MCK_HPR; break; 9572 case ARM::S29: OpKind = MCK_HPR; break; 9573 case ARM::S30: OpKind = MCK_HPR; break; 9574 case ARM::S31: OpKind = MCK_HPR; break; 9575 case ARM::D0: OpKind = MCK_DPR_8; break; 9576 case ARM::D1: OpKind = MCK_DPR_8; break; 9577 case ARM::D2: OpKind = MCK_DPR_8; break; 9578 case ARM::D3: OpKind = MCK_DPR_8; break; 9579 case ARM::D4: OpKind = MCK_DPR_8; break; 9580 case ARM::D5: OpKind = MCK_DPR_8; break; 9581 case ARM::D6: OpKind = MCK_DPR_8; break; 9582 case ARM::D7: OpKind = MCK_DPR_8; break; 9583 case ARM::D8: OpKind = MCK_DPR_VFP2; break; 9584 case ARM::D9: OpKind = MCK_DPR_VFP2; break; 9585 case ARM::D10: OpKind = MCK_DPR_VFP2; break; 9586 case ARM::D11: OpKind = MCK_DPR_VFP2; break; 9587 case ARM::D12: OpKind = MCK_DPR_VFP2; break; 9588 case ARM::D13: OpKind = MCK_DPR_VFP2; break; 9589 case ARM::D14: OpKind = MCK_DPR_VFP2; break; 9590 case ARM::D15: OpKind = MCK_DPR_VFP2; break; 9591 case ARM::D16: OpKind = MCK_DPR; break; 9592 case ARM::D17: OpKind = MCK_DPR; break; 9593 case ARM::D18: OpKind = MCK_DPR; break; 9594 case ARM::D19: OpKind = MCK_DPR; break; 9595 case ARM::D20: OpKind = MCK_DPR; break; 9596 case ARM::D21: OpKind = MCK_DPR; break; 9597 case ARM::D22: OpKind = MCK_DPR; break; 9598 case ARM::D23: OpKind = MCK_DPR; break; 9599 case ARM::D24: OpKind = MCK_DPR; break; 9600 case ARM::D25: OpKind = MCK_DPR; break; 9601 case ARM::D26: OpKind = MCK_DPR; break; 9602 case ARM::D27: OpKind = MCK_DPR; break; 9603 case ARM::D28: OpKind = MCK_DPR; break; 9604 case ARM::D29: OpKind = MCK_DPR; break; 9605 case ARM::D30: OpKind = MCK_DPR; break; 9606 case ARM::D31: OpKind = MCK_DPR; break; 9607 case ARM::Q0: OpKind = MCK_QPR_8; break; 9608 case ARM::Q1: OpKind = MCK_QPR_8; break; 9609 case ARM::Q2: OpKind = MCK_QPR_8; break; 9610 case ARM::Q3: OpKind = MCK_QPR_8; break; 9611 case ARM::Q4: OpKind = MCK_MQPR; break; 9612 case ARM::Q5: OpKind = MCK_MQPR; break; 9613 case ARM::Q6: OpKind = MCK_MQPR; break; 9614 case ARM::Q7: OpKind = MCK_MQPR; break; 9615 case ARM::Q8: OpKind = MCK_QPR; break; 9616 case ARM::Q9: OpKind = MCK_QPR; break; 9617 case ARM::Q10: OpKind = MCK_QPR; break; 9618 case ARM::Q11: OpKind = MCK_QPR; break; 9619 case ARM::Q12: OpKind = MCK_QPR; break; 9620 case ARM::Q13: OpKind = MCK_QPR; break; 9621 case ARM::Q14: OpKind = MCK_QPR; break; 9622 case ARM::Q15: OpKind = MCK_QPR; break; 9623 case ARM::CPSR: OpKind = MCK_CCR; break; 9624 case ARM::APSR: OpKind = MCK_APSR; break; 9625 case ARM::APSR_NZCV: OpKind = MCK_APSR_NZCV; break; 9626 case ARM::SPSR: OpKind = MCK_SPSR; break; 9627 case ARM::FPSCR: OpKind = MCK_FPSCR; break; 9628 case ARM::FPSCR_NZCV: OpKind = MCK_cl_FPSCR_NZCV; break; 9629 case ARM::FPSID: OpKind = MCK_FPSID; break; 9630 case ARM::MVFR2: OpKind = MCK_MVFR2; break; 9631 case ARM::MVFR1: OpKind = MCK_MVFR1; break; 9632 case ARM::MVFR0: OpKind = MCK_MVFR0; break; 9633 case ARM::FPEXC: OpKind = MCK_FPEXC; break; 9634 case ARM::FPINST: OpKind = MCK_FPINST; break; 9635 case ARM::FPINST2: OpKind = MCK_FPINST2; break; 9636 case ARM::VPR: OpKind = MCK_VCCR; break; 9637 case ARM::FPSCR_NZCVQC: OpKind = MCK_FPSCR_NZCVQC; break; 9638 case ARM::P0: OpKind = MCK_P0; break; 9639 case ARM::FPCXTNS: OpKind = MCK_FPCXTRegs; break; 9640 case ARM::FPCXTS: OpKind = MCK_FPCXTS; break; 9641 case ARM::ZR: OpKind = MCK_GPRwithZRnosp; break; 9642 case ARM::D0_D2: OpKind = MCK_Reg72; break; 9643 case ARM::D1_D3: OpKind = MCK_Reg72; break; 9644 case ARM::D2_D4: OpKind = MCK_Reg72; break; 9645 case ARM::D3_D5: OpKind = MCK_Reg72; break; 9646 case ARM::D4_D6: OpKind = MCK_Reg72; break; 9647 case ARM::D5_D7: OpKind = MCK_Reg72; break; 9648 case ARM::D6_D8: OpKind = MCK_Reg73; break; 9649 case ARM::D7_D9: OpKind = MCK_Reg73; break; 9650 case ARM::D8_D10: OpKind = MCK_Reg74; break; 9651 case ARM::D9_D11: OpKind = MCK_Reg74; break; 9652 case ARM::D10_D12: OpKind = MCK_Reg74; break; 9653 case ARM::D11_D13: OpKind = MCK_Reg74; break; 9654 case ARM::D12_D14: OpKind = MCK_Reg74; break; 9655 case ARM::D13_D15: OpKind = MCK_Reg74; break; 9656 case ARM::D14_D16: OpKind = MCK_Reg75; break; 9657 case ARM::D15_D17: OpKind = MCK_Reg75; break; 9658 case ARM::D16_D18: OpKind = MCK_DPairSpc; break; 9659 case ARM::D17_D19: OpKind = MCK_DPairSpc; break; 9660 case ARM::D18_D20: OpKind = MCK_DPairSpc; break; 9661 case ARM::D19_D21: OpKind = MCK_DPairSpc; break; 9662 case ARM::D20_D22: OpKind = MCK_DPairSpc; break; 9663 case ARM::D21_D23: OpKind = MCK_DPairSpc; break; 9664 case ARM::D22_D24: OpKind = MCK_DPairSpc; break; 9665 case ARM::D23_D25: OpKind = MCK_DPairSpc; break; 9666 case ARM::D24_D26: OpKind = MCK_DPairSpc; break; 9667 case ARM::D25_D27: OpKind = MCK_DPairSpc; break; 9668 case ARM::D26_D28: OpKind = MCK_DPairSpc; break; 9669 case ARM::D27_D29: OpKind = MCK_DPairSpc; break; 9670 case ARM::D28_D30: OpKind = MCK_DPairSpc; break; 9671 case ARM::D29_D31: OpKind = MCK_DPairSpc; break; 9672 case ARM::Q0_Q1: OpKind = MCK_Reg77; break; 9673 case ARM::Q1_Q2: OpKind = MCK_Reg77; break; 9674 case ARM::Q2_Q3: OpKind = MCK_Reg77; break; 9675 case ARM::Q3_Q4: OpKind = MCK_Reg78; break; 9676 case ARM::Q4_Q5: OpKind = MCK_MQQPR; break; 9677 case ARM::Q5_Q6: OpKind = MCK_MQQPR; break; 9678 case ARM::Q6_Q7: OpKind = MCK_MQQPR; break; 9679 case ARM::Q7_Q8: OpKind = MCK_Reg80; break; 9680 case ARM::Q8_Q9: OpKind = MCK_QQPR; break; 9681 case ARM::Q9_Q10: OpKind = MCK_QQPR; break; 9682 case ARM::Q10_Q11: OpKind = MCK_QQPR; break; 9683 case ARM::Q11_Q12: OpKind = MCK_QQPR; break; 9684 case ARM::Q12_Q13: OpKind = MCK_QQPR; break; 9685 case ARM::Q13_Q14: OpKind = MCK_QQPR; break; 9686 case ARM::Q14_Q15: OpKind = MCK_QQPR; break; 9687 case ARM::Q0_Q1_Q2_Q3: OpKind = MCK_Reg91; break; 9688 case ARM::Q1_Q2_Q3_Q4: OpKind = MCK_Reg92; break; 9689 case ARM::Q2_Q3_Q4_Q5: OpKind = MCK_Reg93; break; 9690 case ARM::Q3_Q4_Q5_Q6: OpKind = MCK_Reg94; break; 9691 case ARM::Q4_Q5_Q6_Q7: OpKind = MCK_MQQQQPR; break; 9692 case ARM::Q5_Q6_Q7_Q8: OpKind = MCK_Reg96; break; 9693 case ARM::Q6_Q7_Q8_Q9: OpKind = MCK_Reg97; break; 9694 case ARM::Q7_Q8_Q9_Q10: OpKind = MCK_Reg98; break; 9695 case ARM::Q8_Q9_Q10_Q11: OpKind = MCK_QQQQPR; break; 9696 case ARM::Q9_Q10_Q11_Q12: OpKind = MCK_QQQQPR; break; 9697 case ARM::Q10_Q11_Q12_Q13: OpKind = MCK_QQQQPR; break; 9698 case ARM::Q11_Q12_Q13_Q14: OpKind = MCK_QQQQPR; break; 9699 case ARM::Q12_Q13_Q14_Q15: OpKind = MCK_QQQQPR; break; 9700 case ARM::R0_R1: OpKind = MCK_Reg100; break; 9701 case ARM::R2_R3: OpKind = MCK_Reg100; break; 9702 case ARM::R4_R5: OpKind = MCK_Reg101; break; 9703 case ARM::R6_R7: OpKind = MCK_Reg101; break; 9704 case ARM::R8_R9: OpKind = MCK_Reg105; break; 9705 case ARM::R10_R11: OpKind = MCK_Reg105; break; 9706 case ARM::R12_SP: OpKind = MCK_Reg107; break; 9707 case ARM::D0_D1_D2: OpKind = MCK_Reg115; break; 9708 case ARM::D1_D2_D3: OpKind = MCK_Reg120; break; 9709 case ARM::D2_D3_D4: OpKind = MCK_Reg115; break; 9710 case ARM::D3_D4_D5: OpKind = MCK_Reg120; break; 9711 case ARM::D4_D5_D6: OpKind = MCK_Reg115; break; 9712 case ARM::D5_D6_D7: OpKind = MCK_Reg120; break; 9713 case ARM::D6_D7_D8: OpKind = MCK_Reg116; break; 9714 case ARM::D7_D8_D9: OpKind = MCK_Reg121; break; 9715 case ARM::D8_D9_D10: OpKind = MCK_Reg117; break; 9716 case ARM::D9_D10_D11: OpKind = MCK_Reg122; break; 9717 case ARM::D10_D11_D12: OpKind = MCK_Reg117; break; 9718 case ARM::D11_D12_D13: OpKind = MCK_Reg122; break; 9719 case ARM::D12_D13_D14: OpKind = MCK_Reg117; break; 9720 case ARM::D13_D14_D15: OpKind = MCK_Reg122; break; 9721 case ARM::D14_D15_D16: OpKind = MCK_Reg118; break; 9722 case ARM::D15_D16_D17: OpKind = MCK_Reg123; break; 9723 case ARM::D16_D17_D18: OpKind = MCK_Reg119; break; 9724 case ARM::D17_D18_D19: OpKind = MCK_Reg124; break; 9725 case ARM::D18_D19_D20: OpKind = MCK_Reg119; break; 9726 case ARM::D19_D20_D21: OpKind = MCK_Reg124; break; 9727 case ARM::D20_D21_D22: OpKind = MCK_Reg119; break; 9728 case ARM::D21_D22_D23: OpKind = MCK_Reg124; break; 9729 case ARM::D22_D23_D24: OpKind = MCK_Reg119; break; 9730 case ARM::D23_D24_D25: OpKind = MCK_Reg124; break; 9731 case ARM::D24_D25_D26: OpKind = MCK_Reg119; break; 9732 case ARM::D25_D26_D27: OpKind = MCK_Reg124; break; 9733 case ARM::D26_D27_D28: OpKind = MCK_Reg119; break; 9734 case ARM::D27_D28_D29: OpKind = MCK_Reg124; break; 9735 case ARM::D28_D29_D30: OpKind = MCK_Reg119; break; 9736 case ARM::D29_D30_D31: OpKind = MCK_Reg124; break; 9737 case ARM::D0_D2_D4: OpKind = MCK_Reg125; break; 9738 case ARM::D1_D3_D5: OpKind = MCK_Reg125; break; 9739 case ARM::D2_D4_D6: OpKind = MCK_Reg125; break; 9740 case ARM::D3_D5_D7: OpKind = MCK_Reg125; break; 9741 case ARM::D4_D6_D8: OpKind = MCK_Reg126; break; 9742 case ARM::D5_D7_D9: OpKind = MCK_Reg126; break; 9743 case ARM::D6_D8_D10: OpKind = MCK_Reg127; break; 9744 case ARM::D7_D9_D11: OpKind = MCK_Reg127; break; 9745 case ARM::D8_D10_D12: OpKind = MCK_Reg128; break; 9746 case ARM::D9_D11_D13: OpKind = MCK_Reg128; break; 9747 case ARM::D10_D12_D14: OpKind = MCK_Reg128; break; 9748 case ARM::D11_D13_D15: OpKind = MCK_Reg128; break; 9749 case ARM::D12_D14_D16: OpKind = MCK_Reg129; break; 9750 case ARM::D13_D15_D17: OpKind = MCK_Reg129; break; 9751 case ARM::D14_D16_D18: OpKind = MCK_Reg130; break; 9752 case ARM::D15_D17_D19: OpKind = MCK_Reg130; break; 9753 case ARM::D16_D18_D20: OpKind = MCK_DTripleSpc; break; 9754 case ARM::D17_D19_D21: OpKind = MCK_DTripleSpc; break; 9755 case ARM::D18_D20_D22: OpKind = MCK_DTripleSpc; break; 9756 case ARM::D19_D21_D23: OpKind = MCK_DTripleSpc; break; 9757 case ARM::D20_D22_D24: OpKind = MCK_DTripleSpc; break; 9758 case ARM::D21_D23_D25: OpKind = MCK_DTripleSpc; break; 9759 case ARM::D22_D24_D26: OpKind = MCK_DTripleSpc; break; 9760 case ARM::D23_D25_D27: OpKind = MCK_DTripleSpc; break; 9761 case ARM::D24_D26_D28: OpKind = MCK_DTripleSpc; break; 9762 case ARM::D25_D27_D29: OpKind = MCK_DTripleSpc; break; 9763 case ARM::D26_D28_D30: OpKind = MCK_DTripleSpc; break; 9764 case ARM::D27_D29_D31: OpKind = MCK_DTripleSpc; break; 9765 case ARM::D1_D2: OpKind = MCK_Reg52; break; 9766 case ARM::D3_D4: OpKind = MCK_Reg52; break; 9767 case ARM::D5_D6: OpKind = MCK_Reg52; break; 9768 case ARM::D7_D8: OpKind = MCK_Reg53; break; 9769 case ARM::D9_D10: OpKind = MCK_Reg50; break; 9770 case ARM::D11_D12: OpKind = MCK_Reg50; break; 9771 case ARM::D13_D14: OpKind = MCK_Reg50; break; 9772 case ARM::D15_D16: OpKind = MCK_Reg51; break; 9773 case ARM::D17_D18: OpKind = MCK_DPair; break; 9774 case ARM::D19_D20: OpKind = MCK_DPair; break; 9775 case ARM::D21_D22: OpKind = MCK_DPair; break; 9776 case ARM::D23_D24: OpKind = MCK_DPair; break; 9777 case ARM::D25_D26: OpKind = MCK_DPair; break; 9778 case ARM::D27_D28: OpKind = MCK_DPair; break; 9779 case ARM::D29_D30: OpKind = MCK_DPair; break; 9780 case ARM::D1_D2_D3_D4: OpKind = MCK_Reg132; break; 9781 case ARM::D3_D4_D5_D6: OpKind = MCK_Reg132; break; 9782 case ARM::D5_D6_D7_D8: OpKind = MCK_Reg133; break; 9783 case ARM::D7_D8_D9_D10: OpKind = MCK_Reg134; break; 9784 case ARM::D9_D10_D11_D12: OpKind = MCK_Reg135; break; 9785 case ARM::D11_D12_D13_D14: OpKind = MCK_Reg135; break; 9786 case ARM::D13_D14_D15_D16: OpKind = MCK_Reg136; break; 9787 case ARM::D15_D16_D17_D18: OpKind = MCK_Reg137; break; 9788 case ARM::D17_D18_D19_D20: OpKind = MCK_Reg138; break; 9789 case ARM::D19_D20_D21_D22: OpKind = MCK_Reg138; break; 9790 case ARM::D21_D22_D23_D24: OpKind = MCK_Reg138; break; 9791 case ARM::D23_D24_D25_D26: OpKind = MCK_Reg138; break; 9792 case ARM::D25_D26_D27_D28: OpKind = MCK_Reg138; break; 9793 case ARM::D27_D28_D29_D30: OpKind = MCK_Reg138; break; 9794 } 9795 return isSubclass(OpKind, Kind) ? (unsigned)MCTargetAsmParser::Match_Success : 9796 getDiagKindFromRegisterClass(Kind); 9797 } 9798 9799 if (Kind > MCK_LAST_TOKEN && Kind <= MCK_LAST_REGISTER) 9800 return getDiagKindFromRegisterClass(Kind); 9801 9802 return MCTargetAsmParser::Match_InvalidOperand; 9803} 9804 9805#ifndef NDEBUG 9806const char *getMatchClassName(MatchClassKind Kind) { 9807 switch (Kind) { 9808 case InvalidMatchClass: return "InvalidMatchClass"; 9809 case OptionalMatchClass: return "OptionalMatchClass"; 9810 case MCK__DOT_d: return "MCK__DOT_d"; 9811 case MCK__DOT_f: return "MCK__DOT_f"; 9812 case MCK__DOT_s16: return "MCK__DOT_s16"; 9813 case MCK__DOT_s32: return "MCK__DOT_s32"; 9814 case MCK__DOT_s64: return "MCK__DOT_s64"; 9815 case MCK__DOT_s8: return "MCK__DOT_s8"; 9816 case MCK__DOT_u16: return "MCK__DOT_u16"; 9817 case MCK__DOT_u32: return "MCK__DOT_u32"; 9818 case MCK__DOT_u64: return "MCK__DOT_u64"; 9819 case MCK__DOT_u8: return "MCK__DOT_u8"; 9820 case MCK__DOT_f32: return "MCK__DOT_f32"; 9821 case MCK__DOT_f64: return "MCK__DOT_f64"; 9822 case MCK__DOT_i16: return "MCK__DOT_i16"; 9823 case MCK__DOT_i32: return "MCK__DOT_i32"; 9824 case MCK__DOT_i64: return "MCK__DOT_i64"; 9825 case MCK__DOT_i8: return "MCK__DOT_i8"; 9826 case MCK__DOT_p16: return "MCK__DOT_p16"; 9827 case MCK__DOT_p8: return "MCK__DOT_p8"; 9828 case MCK__EXCLAIM_: return "MCK__EXCLAIM_"; 9829 case MCK__HASH_0: return "MCK__HASH_0"; 9830 case MCK__HASH_16: return "MCK__HASH_16"; 9831 case MCK__HASH_8: return "MCK__HASH_8"; 9832 case MCK__DOT_16: return "MCK__DOT_16"; 9833 case MCK__DOT_32: return "MCK__DOT_32"; 9834 case MCK__DOT_64: return "MCK__DOT_64"; 9835 case MCK__DOT_8: return "MCK__DOT_8"; 9836 case MCK__DOT_bf16: return "MCK__DOT_bf16"; 9837 case MCK__DOT_f16: return "MCK__DOT_f16"; 9838 case MCK__DOT_p64: return "MCK__DOT_p64"; 9839 case MCK__DOT_w: return "MCK__DOT_w"; 9840 case MCK__91_: return "MCK__91_"; 9841 case MCK__93_: return "MCK__93_"; 9842 case MCK__94_: return "MCK__94_"; 9843 case MCK__123_: return "MCK__123_"; 9844 case MCK__125_: return "MCK__125_"; 9845 case MCK_Reg107: return "MCK_Reg107"; 9846 case MCK_Reg91: return "MCK_Reg91"; 9847 case MCK_APSR: return "MCK_APSR"; 9848 case MCK_APSR_NZCV: return "MCK_APSR_NZCV"; 9849 case MCK_CCR: return "MCK_CCR"; 9850 case MCK_FPCXTRegs: return "MCK_FPCXTRegs"; 9851 case MCK_FPCXTS: return "MCK_FPCXTS"; 9852 case MCK_FPEXC: return "MCK_FPEXC"; 9853 case MCK_FPINST: return "MCK_FPINST"; 9854 case MCK_FPINST2: return "MCK_FPINST2"; 9855 case MCK_FPSCR: return "MCK_FPSCR"; 9856 case MCK_FPSCR_NZCVQC: return "MCK_FPSCR_NZCVQC"; 9857 case MCK_FPSID: return "MCK_FPSID"; 9858 case MCK_GPRlr: return "MCK_GPRlr"; 9859 case MCK_GPRsp: return "MCK_GPRsp"; 9860 case MCK_MVFR0: return "MCK_MVFR0"; 9861 case MCK_MVFR1: return "MCK_MVFR1"; 9862 case MCK_MVFR2: return "MCK_MVFR2"; 9863 case MCK_P0: return "MCK_P0"; 9864 case MCK_PC: return "MCK_PC"; 9865 case MCK_R12: return "MCK_R12"; 9866 case MCK_SPSR: return "MCK_SPSR"; 9867 case MCK_VCCR: return "MCK_VCCR"; 9868 case MCK_cl_FPSCR_NZCV: return "MCK_cl_FPSCR_NZCV"; 9869 case MCK_Reg132: return "MCK_Reg132"; 9870 case MCK_Reg105: return "MCK_Reg105"; 9871 case MCK_Reg100: return "MCK_Reg100"; 9872 case MCK_Reg92: return "MCK_Reg92"; 9873 case MCK_Reg35: return "MCK_Reg35"; 9874 case MCK_Reg33: return "MCK_Reg33"; 9875 case MCK_Reg22: return "MCK_Reg22"; 9876 case MCK_Reg17: return "MCK_Reg17"; 9877 case MCK_Reg133: return "MCK_Reg133"; 9878 case MCK_Reg120: return "MCK_Reg120"; 9879 case MCK_Reg115: return "MCK_Reg115"; 9880 case MCK_Reg106: return "MCK_Reg106"; 9881 case MCK_Reg104: return "MCK_Reg104"; 9882 case MCK_Reg93: return "MCK_Reg93"; 9883 case MCK_Reg77: return "MCK_Reg77"; 9884 case MCK_Reg21: return "MCK_Reg21"; 9885 case MCK_Reg134: return "MCK_Reg134"; 9886 case MCK_Reg125: return "MCK_Reg125"; 9887 case MCK_Reg121: return "MCK_Reg121"; 9888 case MCK_Reg116: return "MCK_Reg116"; 9889 case MCK_Reg101: return "MCK_Reg101"; 9890 case MCK_Reg94: return "MCK_Reg94"; 9891 case MCK_Reg78: return "MCK_Reg78"; 9892 case MCK_Reg34: return "MCK_Reg34"; 9893 case MCK_Reg25: return "MCK_Reg25"; 9894 case MCK_Reg23: return "MCK_Reg23"; 9895 case MCK_Reg18: return "MCK_Reg18"; 9896 case MCK_Reg0: return "MCK_Reg0"; 9897 case MCK_QPR_8: return "MCK_QPR_8"; 9898 case MCK_Reg89: return "MCK_Reg89"; 9899 case MCK_Reg32: return "MCK_Reg32"; 9900 case MCK_Reg30: return "MCK_Reg30"; 9901 case MCK_MQQQQPR: return "MCK_MQQQQPR"; 9902 case MCK_tcGPR: return "MCK_tcGPR"; 9903 case MCK_Reg135: return "MCK_Reg135"; 9904 case MCK_Reg126: return "MCK_Reg126"; 9905 case MCK_Reg108: return "MCK_Reg108"; 9906 case MCK_Reg96: return "MCK_Reg96"; 9907 case MCK_Reg90: return "MCK_Reg90"; 9908 case MCK_Reg72: return "MCK_Reg72"; 9909 case MCK_Reg31: return "MCK_Reg31"; 9910 case MCK_Reg28: return "MCK_Reg28"; 9911 case MCK_Reg19: return "MCK_Reg19"; 9912 case MCK_GPRPairnosp: return "MCK_GPRPairnosp"; 9913 case MCK_tGPROdd: return "MCK_tGPROdd"; 9914 case MCK_Reg136: return "MCK_Reg136"; 9915 case MCK_Reg122: return "MCK_Reg122"; 9916 case MCK_Reg117: return "MCK_Reg117"; 9917 case MCK_Reg109: return "MCK_Reg109"; 9918 case MCK_Reg97: return "MCK_Reg97"; 9919 case MCK_Reg87: return "MCK_Reg87"; 9920 case MCK_Reg52: return "MCK_Reg52"; 9921 case MCK_Reg29: return "MCK_Reg29"; 9922 case MCK_Reg26: return "MCK_Reg26"; 9923 case MCK_GPRPair: return "MCK_GPRPair"; 9924 case MCK_MQQPR: return "MCK_MQQPR"; 9925 case MCK_Reg137: return "MCK_Reg137"; 9926 case MCK_Reg127: return "MCK_Reg127"; 9927 case MCK_Reg123: return "MCK_Reg123"; 9928 case MCK_Reg118: return "MCK_Reg118"; 9929 case MCK_Reg110: return "MCK_Reg110"; 9930 case MCK_Reg98: return "MCK_Reg98"; 9931 case MCK_Reg88: return "MCK_Reg88"; 9932 case MCK_Reg80: return "MCK_Reg80"; 9933 case MCK_Reg73: return "MCK_Reg73"; 9934 case MCK_Reg53: return "MCK_Reg53"; 9935 case MCK_DPR_8: return "MCK_DPR_8"; 9936 case MCK_MQPR: return "MCK_MQPR"; 9937 case MCK_hGPR: return "MCK_hGPR"; 9938 case MCK_tGPR: return "MCK_tGPR"; 9939 case MCK_tGPREven: return "MCK_tGPREven"; 9940 case MCK_tGPRwithpc: return "MCK_tGPRwithpc"; 9941 case MCK_Reg128: return "MCK_Reg128"; 9942 case MCK_Reg2: return "MCK_Reg2"; 9943 case MCK_Reg85: return "MCK_Reg85"; 9944 case MCK_Reg14: return "MCK_Reg14"; 9945 case MCK_Reg12: return "MCK_Reg12"; 9946 case MCK_QQQQPR: return "MCK_QQQQPR"; 9947 case MCK_Reg138: return "MCK_Reg138"; 9948 case MCK_Reg129: return "MCK_Reg129"; 9949 case MCK_Reg111: return "MCK_Reg111"; 9950 case MCK_Reg86: return "MCK_Reg86"; 9951 case MCK_Reg74: return "MCK_Reg74"; 9952 case MCK_GPRnoip: return "MCK_GPRnoip"; 9953 case MCK_rGPR: return "MCK_rGPR"; 9954 case MCK_Reg124: return "MCK_Reg124"; 9955 case MCK_Reg119: return "MCK_Reg119"; 9956 case MCK_Reg112: return "MCK_Reg112"; 9957 case MCK_Reg83: return "MCK_Reg83"; 9958 case MCK_Reg50: return "MCK_Reg50"; 9959 case MCK_GPRnopc: return "MCK_GPRnopc"; 9960 case MCK_GPRnosp: return "MCK_GPRnosp"; 9961 case MCK_GPRwithAPSR_NZCVnosp: return "MCK_GPRwithAPSR_NZCVnosp"; 9962 case MCK_GPRwithAPSRnosp: return "MCK_GPRwithAPSRnosp"; 9963 case MCK_GPRwithZRnosp: return "MCK_GPRwithZRnosp"; 9964 case MCK_QQPR: return "MCK_QQPR"; 9965 case MCK_Reg130: return "MCK_Reg130"; 9966 case MCK_Reg113: return "MCK_Reg113"; 9967 case MCK_Reg84: return "MCK_Reg84"; 9968 case MCK_Reg75: return "MCK_Reg75"; 9969 case MCK_Reg51: return "MCK_Reg51"; 9970 case MCK_DPR_VFP2: return "MCK_DPR_VFP2"; 9971 case MCK_GPR: return "MCK_GPR"; 9972 case MCK_GPRwithAPSR: return "MCK_GPRwithAPSR"; 9973 case MCK_GPRwithZR: return "MCK_GPRwithZR"; 9974 case MCK_QPR: return "MCK_QPR"; 9975 case MCK_SPR_8: return "MCK_SPR_8"; 9976 case MCK_DTripleSpc: return "MCK_DTripleSpc"; 9977 case MCK_DQuad: return "MCK_DQuad"; 9978 case MCK_DPairSpc: return "MCK_DPairSpc"; 9979 case MCK_DTriple: return "MCK_DTriple"; 9980 case MCK_DPair: return "MCK_DPair"; 9981 case MCK_DPR: return "MCK_DPR"; 9982 case MCK_HPR: return "MCK_HPR"; 9983 case MCK_FPWithVPR: return "MCK_FPWithVPR"; 9984 case MCK_AM2OffsetImm: return "MCK_AM2OffsetImm"; 9985 case MCK_AM3Offset: return "MCK_AM3Offset"; 9986 case MCK_ARMBranchTarget: return "MCK_ARMBranchTarget"; 9987 case MCK_AddrMode3: return "MCK_AddrMode3"; 9988 case MCK_AddrMode5: return "MCK_AddrMode5"; 9989 case MCK_AddrMode5FP16: return "MCK_AddrMode5FP16"; 9990 case MCK_AlignedMemory16: return "MCK_AlignedMemory16"; 9991 case MCK_AlignedMemory32: return "MCK_AlignedMemory32"; 9992 case MCK_AlignedMemory64: return "MCK_AlignedMemory64"; 9993 case MCK_AlignedMemory64or128: return "MCK_AlignedMemory64or128"; 9994 case MCK_AlignedMemory64or128or256: return "MCK_AlignedMemory64or128or256"; 9995 case MCK_AlignedMemoryNone: return "MCK_AlignedMemoryNone"; 9996 case MCK_AlignedMemory: return "MCK_AlignedMemory"; 9997 case MCK_DupAlignedMemory16: return "MCK_DupAlignedMemory16"; 9998 case MCK_DupAlignedMemory32: return "MCK_DupAlignedMemory32"; 9999 case MCK_DupAlignedMemory64: return "MCK_DupAlignedMemory64"; 10000 case MCK_DupAlignedMemory64or128: return "MCK_DupAlignedMemory64or128"; 10001 case MCK_DupAlignedMemoryNone: return "MCK_DupAlignedMemoryNone"; 10002 case MCK_AdrLabel: return "MCK_AdrLabel"; 10003 case MCK_BankedReg: return "MCK_BankedReg"; 10004 case MCK_Bitfield: return "MCK_Bitfield"; 10005 case MCK_CCOut: return "MCK_CCOut"; 10006 case MCK_CondCode: return "MCK_CondCode"; 10007 case MCK_CoprocNum: return "MCK_CoprocNum"; 10008 case MCK_CoprocOption: return "MCK_CoprocOption"; 10009 case MCK_CoprocReg: return "MCK_CoprocReg"; 10010 case MCK_DPRRegList: return "MCK_DPRRegList"; 10011 case MCK_FPDRegListWithVPR: return "MCK_FPDRegListWithVPR"; 10012 case MCK_FPImm: return "MCK_FPImm"; 10013 case MCK_FPSRegListWithVPR: return "MCK_FPSRegListWithVPR"; 10014 case MCK_Imm0_15: return "MCK_Imm0_15"; 10015 case MCK_Imm0_1: return "MCK_Imm0_1"; 10016 case MCK_Imm0_239: return "MCK_Imm0_239"; 10017 case MCK_Imm0_255: return "MCK_Imm0_255"; 10018 case MCK_Imm0_31: return "MCK_Imm0_31"; 10019 case MCK_Imm0_32: return "MCK_Imm0_32"; 10020 case MCK_Imm0_3: return "MCK_Imm0_3"; 10021 case MCK_Imm0_63: return "MCK_Imm0_63"; 10022 case MCK_Imm0_65535: return "MCK_Imm0_65535"; 10023 case MCK_Imm0_65535Expr: return "MCK_Imm0_65535Expr"; 10024 case MCK_Imm0_7: return "MCK_Imm0_7"; 10025 case MCK_Imm16: return "MCK_Imm16"; 10026 case MCK_Imm1_15: return "MCK_Imm1_15"; 10027 case MCK_Imm1_16: return "MCK_Imm1_16"; 10028 case MCK_Imm1_31: return "MCK_Imm1_31"; 10029 case MCK_Imm1_32: return "MCK_Imm1_32"; 10030 case MCK_Imm1_7: return "MCK_Imm1_7"; 10031 case MCK_Imm24bit: return "MCK_Imm24bit"; 10032 case MCK_Imm256_65535Expr: return "MCK_Imm256_65535Expr"; 10033 case MCK_Imm32: return "MCK_Imm32"; 10034 case MCK_Imm8: return "MCK_Imm8"; 10035 case MCK_Imm8_255: return "MCK_Imm8_255"; 10036 case MCK_Imm: return "MCK_Imm"; 10037 case MCK_InstSyncBarrierOpt: return "MCK_InstSyncBarrierOpt"; 10038 case MCK_MSRMask: return "MCK_MSRMask"; 10039 case MCK_MVEShiftImm1_15: return "MCK_MVEShiftImm1_15"; 10040 case MCK_MVEShiftImm1_7: return "MCK_MVEShiftImm1_7"; 10041 case MCK_VIDUP_imm: return "MCK_VIDUP_imm"; 10042 case MCK_MemBarrierOpt: return "MCK_MemBarrierOpt"; 10043 case MCK_MemImm0_1020s4Offset: return "MCK_MemImm0_1020s4Offset"; 10044 case MCK_MemImm12Offset: return "MCK_MemImm12Offset"; 10045 case MCK_MemImm7Shift0Offset: return "MCK_MemImm7Shift0Offset"; 10046 case MCK_MemImm7Shift0OffsetWB: return "MCK_MemImm7Shift0OffsetWB"; 10047 case MCK_MemImm7Shift1Offset: return "MCK_MemImm7Shift1Offset"; 10048 case MCK_MemImm7Shift1OffsetWB: return "MCK_MemImm7Shift1OffsetWB"; 10049 case MCK_MemImm7Shift2Offset: return "MCK_MemImm7Shift2Offset"; 10050 case MCK_MemImm7Shift2OffsetWB: return "MCK_MemImm7Shift2OffsetWB"; 10051 case MCK_MemImm7s4Offset: return "MCK_MemImm7s4Offset"; 10052 case MCK_MemImm8Offset: return "MCK_MemImm8Offset"; 10053 case MCK_MemImm8s4Offset: return "MCK_MemImm8s4Offset"; 10054 case MCK_MemNegImm8Offset: return "MCK_MemNegImm8Offset"; 10055 case MCK_MemNoOffset: return "MCK_MemNoOffset"; 10056 case MCK_MemNoOffsetT2: return "MCK_MemNoOffsetT2"; 10057 case MCK_MemNoOffsetT2NoSp: return "MCK_MemNoOffsetT2NoSp"; 10058 case MCK_MemNoOffsetT: return "MCK_MemNoOffsetT"; 10059 case MCK_MemPosImm8Offset: return "MCK_MemPosImm8Offset"; 10060 case MCK_MemRegOffset: return "MCK_MemRegOffset"; 10061 case MCK_MemRegQS2Offset: return "MCK_MemRegQS2Offset"; 10062 case MCK_MemRegQS3Offset: return "MCK_MemRegQS3Offset"; 10063 case MCK_MemRegRQS0Offset: return "MCK_MemRegRQS0Offset"; 10064 case MCK_MemRegRQS1Offset: return "MCK_MemRegRQS1Offset"; 10065 case MCK_MemRegRQS2Offset: return "MCK_MemRegRQS2Offset"; 10066 case MCK_MemRegRQS3Offset: return "MCK_MemRegRQS3Offset"; 10067 case MCK_ModImm: return "MCK_ModImm"; 10068 case MCK_ModImmNeg: return "MCK_ModImmNeg"; 10069 case MCK_ModImmNot: return "MCK_ModImmNot"; 10070 case MCK_MveSaturate: return "MCK_MveSaturate"; 10071 case MCK_PKHASRImm: return "MCK_PKHASRImm"; 10072 case MCK_PKHLSLImm: return "MCK_PKHLSLImm"; 10073 case MCK_PostIdxImm8: return "MCK_PostIdxImm8"; 10074 case MCK_PostIdxImm8s4: return "MCK_PostIdxImm8s4"; 10075 case MCK_PostIdxReg: return "MCK_PostIdxReg"; 10076 case MCK_PostIdxRegShifted: return "MCK_PostIdxRegShifted"; 10077 case MCK_ProcIFlags: return "MCK_ProcIFlags"; 10078 case MCK_RegList: return "MCK_RegList"; 10079 case MCK_RegListWithAPSR: return "MCK_RegListWithAPSR"; 10080 case MCK_RotImm: return "MCK_RotImm"; 10081 case MCK_SPRRegList: return "MCK_SPRRegList"; 10082 case MCK_SetEndImm: return "MCK_SetEndImm"; 10083 case MCK_RegShiftedImm: return "MCK_RegShiftedImm"; 10084 case MCK_RegShiftedReg: return "MCK_RegShiftedReg"; 10085 case MCK_ShifterImm: return "MCK_ShifterImm"; 10086 case MCK_ThumbBranchTarget: return "MCK_ThumbBranchTarget"; 10087 case MCK_ThumbMemPC: return "MCK_ThumbMemPC"; 10088 case MCK_ThumbModImmNeg1_7: return "MCK_ThumbModImmNeg1_7"; 10089 case MCK_ThumbModImmNeg8_255: return "MCK_ThumbModImmNeg8_255"; 10090 case MCK_ImmThumbSR: return "MCK_ImmThumbSR"; 10091 case MCK_TraceSyncBarrierOpt: return "MCK_TraceSyncBarrierOpt"; 10092 case MCK_UnsignedOffset_b8s2: return "MCK_UnsignedOffset_b8s2"; 10093 case MCK_VPTPredN: return "MCK_VPTPredN"; 10094 case MCK_VPTPredR: return "MCK_VPTPredR"; 10095 case MCK_VecListTwoMQ: return "MCK_VecListTwoMQ"; 10096 case MCK_VecListFourMQ: return "MCK_VecListFourMQ"; 10097 case MCK_VecListDPairAllLanes: return "MCK_VecListDPairAllLanes"; 10098 case MCK_VecListDPair: return "MCK_VecListDPair"; 10099 case MCK_VecListDPairSpacedAllLanes: return "MCK_VecListDPairSpacedAllLanes"; 10100 case MCK_VecListDPairSpaced: return "MCK_VecListDPairSpaced"; 10101 case MCK_VecListFourDAllLanes: return "MCK_VecListFourDAllLanes"; 10102 case MCK_VecListFourD: return "MCK_VecListFourD"; 10103 case MCK_VecListFourDByteIndexed: return "MCK_VecListFourDByteIndexed"; 10104 case MCK_VecListFourDHWordIndexed: return "MCK_VecListFourDHWordIndexed"; 10105 case MCK_VecListFourDWordIndexed: return "MCK_VecListFourDWordIndexed"; 10106 case MCK_VecListFourQAllLanes: return "MCK_VecListFourQAllLanes"; 10107 case MCK_VecListFourQ: return "MCK_VecListFourQ"; 10108 case MCK_VecListFourQHWordIndexed: return "MCK_VecListFourQHWordIndexed"; 10109 case MCK_VecListFourQWordIndexed: return "MCK_VecListFourQWordIndexed"; 10110 case MCK_VecListOneDAllLanes: return "MCK_VecListOneDAllLanes"; 10111 case MCK_VecListOneD: return "MCK_VecListOneD"; 10112 case MCK_VecListOneDByteIndexed: return "MCK_VecListOneDByteIndexed"; 10113 case MCK_VecListOneDHWordIndexed: return "MCK_VecListOneDHWordIndexed"; 10114 case MCK_VecListOneDWordIndexed: return "MCK_VecListOneDWordIndexed"; 10115 case MCK_VecListThreeDAllLanes: return "MCK_VecListThreeDAllLanes"; 10116 case MCK_VecListThreeD: return "MCK_VecListThreeD"; 10117 case MCK_VecListThreeDByteIndexed: return "MCK_VecListThreeDByteIndexed"; 10118 case MCK_VecListThreeDHWordIndexed: return "MCK_VecListThreeDHWordIndexed"; 10119 case MCK_VecListThreeDWordIndexed: return "MCK_VecListThreeDWordIndexed"; 10120 case MCK_VecListThreeQAllLanes: return "MCK_VecListThreeQAllLanes"; 10121 case MCK_VecListThreeQ: return "MCK_VecListThreeQ"; 10122 case MCK_VecListThreeQHWordIndexed: return "MCK_VecListThreeQHWordIndexed"; 10123 case MCK_VecListThreeQWordIndexed: return "MCK_VecListThreeQWordIndexed"; 10124 case MCK_VecListTwoDByteIndexed: return "MCK_VecListTwoDByteIndexed"; 10125 case MCK_VecListTwoDHWordIndexed: return "MCK_VecListTwoDHWordIndexed"; 10126 case MCK_VecListTwoDWordIndexed: return "MCK_VecListTwoDWordIndexed"; 10127 case MCK_VecListTwoQHWordIndexed: return "MCK_VecListTwoQHWordIndexed"; 10128 case MCK_VecListTwoQWordIndexed: return "MCK_VecListTwoQWordIndexed"; 10129 case MCK_VectorIndex16: return "MCK_VectorIndex16"; 10130 case MCK_VectorIndex32: return "MCK_VectorIndex32"; 10131 case MCK_VectorIndex64: return "MCK_VectorIndex64"; 10132 case MCK_VectorIndex8: return "MCK_VectorIndex8"; 10133 case MCK_MemTBB: return "MCK_MemTBB"; 10134 case MCK_MemTBH: return "MCK_MemTBH"; 10135 case MCK_MVEPairVectorIndex0: return "MCK_MVEPairVectorIndex0"; 10136 case MCK_MVEPairVectorIndex2: return "MCK_MVEPairVectorIndex2"; 10137 case MCK_ComplexRotationEven: return "MCK_ComplexRotationEven"; 10138 case MCK_ComplexRotationOdd: return "MCK_ComplexRotationOdd"; 10139 case MCK_NEONi16vmovi8Replicate: return "MCK_NEONi16vmovi8Replicate"; 10140 case MCK_NEONi16invi8Replicate: return "MCK_NEONi16invi8Replicate"; 10141 case MCK_NEONi32vmovi8Replicate: return "MCK_NEONi32vmovi8Replicate"; 10142 case MCK_NEONi32invi8Replicate: return "MCK_NEONi32invi8Replicate"; 10143 case MCK_NEONi64vmovi8Replicate: return "MCK_NEONi64vmovi8Replicate"; 10144 case MCK_NEONi64invi8Replicate: return "MCK_NEONi64invi8Replicate"; 10145 case MCK_NEONi32vmovi16Replicate: return "MCK_NEONi32vmovi16Replicate"; 10146 case MCK_NEONi64vmovi16Replicate: return "MCK_NEONi64vmovi16Replicate"; 10147 case MCK_NEONi64vmovi32Replicate: return "MCK_NEONi64vmovi32Replicate"; 10148 case MCK_MVEVectorIndex4: return "MCK_MVEVectorIndex4"; 10149 case MCK_MVEVectorIndex8: return "MCK_MVEVectorIndex8"; 10150 case MCK_MVEVectorIndex16: return "MCK_MVEVectorIndex16"; 10151 case MCK_MVEVcvtImm32: return "MCK_MVEVcvtImm32"; 10152 case MCK_MVEVcvtImm16: return "MCK_MVEVcvtImm16"; 10153 case MCK_TMemImm7Shift2Offset: return "MCK_TMemImm7Shift2Offset"; 10154 case MCK_TMemImm7Shift0Offset: return "MCK_TMemImm7Shift0Offset"; 10155 case MCK_TMemImm7Shift1Offset: return "MCK_TMemImm7Shift1Offset"; 10156 case MCK_Imm3b: return "MCK_Imm3b"; 10157 case MCK_Imm4b: return "MCK_Imm4b"; 10158 case MCK_Imm6b: return "MCK_Imm6b"; 10159 case MCK_Imm7b: return "MCK_Imm7b"; 10160 case MCK_Imm9b: return "MCK_Imm9b"; 10161 case MCK_Imm11b: return "MCK_Imm11b"; 10162 case MCK_Imm12b: return "MCK_Imm12b"; 10163 case MCK_Imm13b: return "MCK_Imm13b"; 10164 case MCK_ConstPoolAsmImm: return "MCK_ConstPoolAsmImm"; 10165 case MCK_FBits16: return "MCK_FBits16"; 10166 case MCK_FBits32: return "MCK_FBits32"; 10167 case MCK_Imm0_4095: return "MCK_Imm0_4095"; 10168 case MCK_Imm0_4095Neg: return "MCK_Imm0_4095Neg"; 10169 case MCK_ITMask: return "MCK_ITMask"; 10170 case MCK_ITCondCode: return "MCK_ITCondCode"; 10171 case MCK_LELabel: return "MCK_LELabel"; 10172 case MCK_MVELongShift: return "MCK_MVELongShift"; 10173 case MCK_NEONi16splat: return "MCK_NEONi16splat"; 10174 case MCK_NEONi32splat: return "MCK_NEONi32splat"; 10175 case MCK_NEONi64splat: return "MCK_NEONi64splat"; 10176 case MCK_NEONi8splat: return "MCK_NEONi8splat"; 10177 case MCK_NEONi16splatNot: return "MCK_NEONi16splatNot"; 10178 case MCK_NEONi32splatNot: return "MCK_NEONi32splatNot"; 10179 case MCK_NEONi32vmov: return "MCK_NEONi32vmov"; 10180 case MCK_NEONi32vmovNeg: return "MCK_NEONi32vmovNeg"; 10181 case MCK_CondCodeNoAL: return "MCK_CondCodeNoAL"; 10182 case MCK_CondCodeNoALInv: return "MCK_CondCodeNoALInv"; 10183 case MCK_CondCodeRestrictedFP: return "MCK_CondCodeRestrictedFP"; 10184 case MCK_CondCodeRestrictedI: return "MCK_CondCodeRestrictedI"; 10185 case MCK_CondCodeRestrictedS: return "MCK_CondCodeRestrictedS"; 10186 case MCK_CondCodeRestrictedU: return "MCK_CondCodeRestrictedU"; 10187 case MCK_ShrImm16: return "MCK_ShrImm16"; 10188 case MCK_ShrImm32: return "MCK_ShrImm32"; 10189 case MCK_ShrImm64: return "MCK_ShrImm64"; 10190 case MCK_ShrImm8: return "MCK_ShrImm8"; 10191 case MCK_T2SOImm: return "MCK_T2SOImm"; 10192 case MCK_T2SOImmNeg: return "MCK_T2SOImmNeg"; 10193 case MCK_T2SOImmNot: return "MCK_T2SOImmNot"; 10194 case MCK_MemUImm12Offset: return "MCK_MemUImm12Offset"; 10195 case MCK_T2MemRegOffset: return "MCK_T2MemRegOffset"; 10196 case MCK_Imm7s4: return "MCK_Imm7s4"; 10197 case MCK_Imm7Shift0: return "MCK_Imm7Shift0"; 10198 case MCK_Imm7Shift1: return "MCK_Imm7Shift1"; 10199 case MCK_Imm7Shift2: return "MCK_Imm7Shift2"; 10200 case MCK_Imm8s4: return "MCK_Imm8s4"; 10201 case MCK_MemPCRelImm12: return "MCK_MemPCRelImm12"; 10202 case MCK_MemThumbRIs1: return "MCK_MemThumbRIs1"; 10203 case MCK_MemThumbRIs2: return "MCK_MemThumbRIs2"; 10204 case MCK_MemThumbRIs4: return "MCK_MemThumbRIs4"; 10205 case MCK_MemThumbRR: return "MCK_MemThumbRR"; 10206 case MCK_MemThumbSPI: return "MCK_MemThumbSPI"; 10207 case MCK_Imm0_1020s4: return "MCK_Imm0_1020s4"; 10208 case MCK_Imm0_508s4: return "MCK_Imm0_508s4"; 10209 case MCK_Imm0_508s4Neg: return "MCK_Imm0_508s4Neg"; 10210 case MCK_WLSLabel: return "MCK_WLSLabel"; 10211 case NumMatchClassKinds: return "NumMatchClassKinds"; 10212 } 10213 llvm_unreachable("unhandled MatchClassKind!"); 10214} 10215 10216#endif // NDEBUG 10217FeatureBitset ARMAsmParser:: 10218ComputeAvailableFeatures(const FeatureBitset &FB) const { 10219 FeatureBitset Features; 10220 if (FB[ARM::HasV4TOps]) 10221 Features.set(Feature_HasV4TBit); 10222 if (FB[ARM::HasV5TOps]) 10223 Features.set(Feature_HasV5TBit); 10224 if (FB[ARM::HasV5TEOps]) 10225 Features.set(Feature_HasV5TEBit); 10226 if (FB[ARM::HasV6Ops]) 10227 Features.set(Feature_HasV6Bit); 10228 if (FB[ARM::HasV6MOps]) 10229 Features.set(Feature_HasV6MBit); 10230 if (FB[ARM::HasV8MBaselineOps]) 10231 Features.set(Feature_HasV8MBaselineBit); 10232 if (FB[ARM::HasV8MMainlineOps]) 10233 Features.set(Feature_HasV8MMainlineBit); 10234 if (FB[ARM::HasV8_1MMainlineOps]) 10235 Features.set(Feature_HasV8_1MMainlineBit); 10236 if (FB[ARM::HasMVEIntegerOps]) 10237 Features.set(Feature_HasMVEIntBit); 10238 if (FB[ARM::HasMVEFloatOps]) 10239 Features.set(Feature_HasMVEFloatBit); 10240 if (FB[ARM::HasCDEOps]) 10241 Features.set(Feature_HasCDEBit); 10242 if (FB[ARM::FeatureFPRegs]) 10243 Features.set(Feature_HasFPRegsBit); 10244 if (FB[ARM::FeatureFPRegs16]) 10245 Features.set(Feature_HasFPRegs16Bit); 10246 if (!FB[ARM::FeatureFPRegs16]) 10247 Features.set(Feature_HasNoFPRegs16Bit); 10248 if (FB[ARM::FeatureFPRegs64]) 10249 Features.set(Feature_HasFPRegs64Bit); 10250 if (FB[ARM::FeatureFPRegs] && FB[ARM::HasV8_1MMainlineOps]) 10251 Features.set(Feature_HasFPRegsV8_1MBit); 10252 if (FB[ARM::HasV6T2Ops]) 10253 Features.set(Feature_HasV6T2Bit); 10254 if (FB[ARM::HasV6KOps]) 10255 Features.set(Feature_HasV6KBit); 10256 if (FB[ARM::HasV7Ops]) 10257 Features.set(Feature_HasV7Bit); 10258 if (FB[ARM::HasV8Ops]) 10259 Features.set(Feature_HasV8Bit); 10260 if (!FB[ARM::HasV8Ops]) 10261 Features.set(Feature_PreV8Bit); 10262 if (FB[ARM::HasV8_1aOps]) 10263 Features.set(Feature_HasV8_1aBit); 10264 if (FB[ARM::HasV8_2aOps]) 10265 Features.set(Feature_HasV8_2aBit); 10266 if (FB[ARM::HasV8_3aOps]) 10267 Features.set(Feature_HasV8_3aBit); 10268 if (FB[ARM::HasV8_4aOps]) 10269 Features.set(Feature_HasV8_4aBit); 10270 if (FB[ARM::HasV8_5aOps]) 10271 Features.set(Feature_HasV8_5aBit); 10272 if (FB[ARM::HasV8_6aOps]) 10273 Features.set(Feature_HasV8_6aBit); 10274 if (FB[ARM::HasV8_7aOps]) 10275 Features.set(Feature_HasV8_7aBit); 10276 if (FB[ARM::FeatureVFP2_SP]) 10277 Features.set(Feature_HasVFP2Bit); 10278 if (FB[ARM::FeatureVFP3_D16_SP]) 10279 Features.set(Feature_HasVFP3Bit); 10280 if (FB[ARM::FeatureVFP4_D16_SP]) 10281 Features.set(Feature_HasVFP4Bit); 10282 if (FB[ARM::FeatureFP64]) 10283 Features.set(Feature_HasDPVFPBit); 10284 if (FB[ARM::FeatureFPARMv8_D16_SP]) 10285 Features.set(Feature_HasFPARMv8Bit); 10286 if (FB[ARM::FeatureNEON]) 10287 Features.set(Feature_HasNEONBit); 10288 if (FB[ARM::FeatureSHA2]) 10289 Features.set(Feature_HasSHA2Bit); 10290 if (FB[ARM::FeatureAES]) 10291 Features.set(Feature_HasAESBit); 10292 if (FB[ARM::FeatureCrypto]) 10293 Features.set(Feature_HasCryptoBit); 10294 if (FB[ARM::FeatureDotProd]) 10295 Features.set(Feature_HasDotProdBit); 10296 if (FB[ARM::FeatureCRC]) 10297 Features.set(Feature_HasCRCBit); 10298 if (FB[ARM::FeatureRAS]) 10299 Features.set(Feature_HasRASBit); 10300 if (FB[ARM::FeatureLOB]) 10301 Features.set(Feature_HasLOBBit); 10302 if (FB[ARM::FeaturePACBTI]) 10303 Features.set(Feature_HasPACBTIBit); 10304 if (FB[ARM::FeatureFP16]) 10305 Features.set(Feature_HasFP16Bit); 10306 if (FB[ARM::FeatureFullFP16]) 10307 Features.set(Feature_HasFullFP16Bit); 10308 if (FB[ARM::FeatureFP16FML]) 10309 Features.set(Feature_HasFP16FMLBit); 10310 if (FB[ARM::FeatureBF16]) 10311 Features.set(Feature_HasBF16Bit); 10312 if (FB[ARM::FeatureMatMulInt8]) 10313 Features.set(Feature_HasMatMulInt8Bit); 10314 if (FB[ARM::FeatureHWDivThumb]) 10315 Features.set(Feature_HasDivideInThumbBit); 10316 if (FB[ARM::FeatureHWDivARM]) 10317 Features.set(Feature_HasDivideInARMBit); 10318 if (FB[ARM::FeatureDSP]) 10319 Features.set(Feature_HasDSPBit); 10320 if (FB[ARM::FeatureDB]) 10321 Features.set(Feature_HasDBBit); 10322 if (FB[ARM::FeatureDFB]) 10323 Features.set(Feature_HasDFBBit); 10324 if (FB[ARM::FeatureV7Clrex]) 10325 Features.set(Feature_HasV7ClrexBit); 10326 if (FB[ARM::FeatureAcquireRelease]) 10327 Features.set(Feature_HasAcquireReleaseBit); 10328 if (FB[ARM::FeatureMP]) 10329 Features.set(Feature_HasMPBit); 10330 if (FB[ARM::FeatureVirtualization]) 10331 Features.set(Feature_HasVirtualizationBit); 10332 if (FB[ARM::FeatureTrustZone]) 10333 Features.set(Feature_HasTrustZoneBit); 10334 if (FB[ARM::Feature8MSecExt]) 10335 Features.set(Feature_Has8MSecExtBit); 10336 if (FB[ARM::ModeThumb]) 10337 Features.set(Feature_IsThumbBit); 10338 if (FB[ARM::ModeThumb] && FB[ARM::FeatureThumb2]) 10339 Features.set(Feature_IsThumb2Bit); 10340 if (FB[ARM::FeatureMClass]) 10341 Features.set(Feature_IsMClassBit); 10342 if (!FB[ARM::FeatureMClass]) 10343 Features.set(Feature_IsNotMClassBit); 10344 if (!FB[ARM::ModeThumb]) 10345 Features.set(Feature_IsARMBit); 10346 if (FB[ARM::FeatureNaClTrap]) 10347 Features.set(Feature_UseNaClTrapBit); 10348 if (!FB[ARM::FeatureNoNegativeImmediates]) 10349 Features.set(Feature_UseNegativeImmediatesBit); 10350 if (FB[ARM::FeatureSB]) 10351 Features.set(Feature_HasSBBit); 10352 if (FB[ARM::FeatureCLRBHB]) 10353 Features.set(Feature_HasCLRBHBBit); 10354 return Features; 10355} 10356 10357static const char MnemonicTable[] = 10358 "\t__brkdiv0\003adc\003add\004addw\003adr\004aesd\004aese\006aesimc\005a" 10359 "esmc\003and\003asr\004asrl\003aut\004autg\001b\002bf\003bfc\006bfcsel\003" 10360 "bfi\003bfl\004bflx\003bfx\003bic\004bkpt\002bl\003blx\005blxns\003bti\002" 10361 "bx\005bxaut\003bxj\004bxns\004cbnz\003cbz\003cdp\004cdp2\004cinc\004cin" 10362 "v\006clrbhb\005clrex\004clrm\003clz\003cmn\003cmp\004cneg\003cps\006crc" 10363 "32b\007crc32cb\007crc32ch\007crc32cw\006crc32h\006crc32w\004csdb\004cse" 10364 "l\004cset\005csetm\005csinc\005csinv\005csneg\003cx1\004cx1a\004cx1d\005" 10365 "cx1da\003cx2\004cx2a\004cx2d\005cx2da\003cx3\004cx3a\004cx3d\005cx3da\003" 10366 "dbg\005dcps1\005dcps2\005dcps3\003dfb\003dls\005dlstp\003dmb\003dsb\003" 10367 "eor\004eret\003esb\005faddd\005fadds\006fcmpzd\006fcmpzs\007fconstd\007" 10368 "fconsts\007fldmdbx\007fldmiax\005fmdhr\005fmdlr\006fmstat\007fstmdbx\007" 10369 "fstmiax\005fsubd\005fsubs\004hint\003hlt\003hvc\003isb\002it\004lctp\003" 10370 "lda\004ldab\005ldaex\006ldaexb\006ldaexd\006ldaexh\004ldah\003ldc\004ld" 10371 "c2\005ldc2l\004ldcl\003ldm\005ldmda\005ldmdb\005ldmib\003ldr\004ldrb\005" 10372 "ldrbt\004ldrd\005ldrex\006ldrexb\006ldrexd\006ldrexh\004ldrh\005ldrht\005" 10373 "ldrsb\006ldrsbt\005ldrsh\006ldrsht\004ldrt\002le\004letp\003lsl\004lsll" 10374 "\003lsr\004lsrl\003mcr\004mcr2\004mcrr\005mcrr2\003mla\003mls\003mov\004" 10375 "movs\004movt\004movw\003mrc\004mrc2\004mrrc\005mrrc2\003mrs\003msr\003m" 10376 "ul\003mvn\003neg\003nop\003orn\003orr\003pac\006pacbti\004pacg\005pkhbt" 10377 "\005pkhtb\003pld\004pldw\003pli\003pop\005pssbb\004push\004qadd\006qadd" 10378 "16\005qadd8\004qasx\005qdadd\005qdsub\004qsax\004qsub\006qsub16\005qsub" 10379 "8\004rbit\003rev\005rev16\005revsh\005rfeda\005rfedb\005rfeia\005rfeib\003" 10380 "ror\003rrx\003rsb\003rsc\006sadd16\005sadd8\004sasx\002sb\003sbc\004sbf" 10381 "x\004sdiv\003sel\006setend\006setpan\003sev\004sevl\002sg\005sha1c\005s" 10382 "ha1h\005sha1m\005sha1p\007sha1su0\007sha1su1\007sha256h\010sha256h2\tsh" 10383 "a256su0\tsha256su1\007shadd16\006shadd8\005shasx\005shsax\007shsub16\006" 10384 "shsub8\003smc\006smlabb\006smlabt\005smlad\006smladx\005smlal\007smlalb" 10385 "b\007smlalbt\006smlald\007smlaldx\007smlaltb\007smlaltt\006smlatb\006sm" 10386 "latt\006smlawb\006smlawt\005smlsd\006smlsdx\006smlsld\007smlsldx\005smm" 10387 "la\006smmlar\005smmls\006smmlsr\005smmul\006smmulr\005smuad\006smuadx\006" 10388 "smulbb\006smulbt\005smull\006smultb\006smultt\006smulwb\006smulwt\005sm" 10389 "usd\006smusdx\006sqrshr\007sqrshrl\005sqshl\006sqshll\005srsda\005srsdb" 10390 "\005srshr\006srshrl\005srsia\005srsib\004ssat\006ssat16\004ssax\004ssbb" 10391 "\006ssub16\005ssub8\003stc\004stc2\005stc2l\004stcl\003stl\004stlb\005s" 10392 "tlex\006stlexb\006stlexd\006stlexh\004stlh\003stm\005stmda\005stmdb\005" 10393 "stmib\003str\004strb\005strbt\004strd\005strex\006strexb\006strexd\006s" 10394 "trexh\004strh\005strht\004strt\003sub\004subs\004subw\003svc\003swp\004" 10395 "swpb\005sxtab\007sxtab16\005sxtah\004sxtb\006sxtb16\004sxth\003tbb\003t" 10396 "bh\003teq\004trap\003tsb\003tst\002tt\003tta\004ttat\003ttt\006uadd16\005" 10397 "uadd8\004uasx\004ubfx\003udf\004udiv\007uhadd16\006uhadd8\005uhasx\005u" 10398 "hsax\007uhsub16\006uhsub8\005umaal\005umlal\005umull\007uqadd16\006uqad" 10399 "d8\005uqasx\006uqrshl\007uqrshll\005uqsax\005uqshl\006uqshll\007uqsub16" 10400 "\006uqsub8\005urshr\006urshrl\005usad8\006usada8\004usat\006usat16\004u" 10401 "sax\006usub16\005usub8\005uxtab\007uxtab16\005uxtah\004uxtb\006uxtb16\004" 10402 "uxth\004vaba\005vabal\005vabav\004vabd\005vabdl\004vabs\005vacge\005vac" 10403 "gt\005vacle\005vaclt\004vadc\005vadci\004vadd\006vaddhn\005vaddl\006vad" 10404 "dlv\007vaddlva\005vaddv\006vaddva\005vaddw\004vand\004vbic\004vbif\004v" 10405 "bit\005vbrsr\004vbsl\005vcadd\004vceq\004vcge\004vcgt\004vcle\004vcls\004" 10406 "vclt\004vclz\005vcmla\004vcmp\005vcmpe\005vcmul\004vcnt\004vctp\004vcvt" 10407 "\005vcvta\005vcvtb\005vcvtm\005vcvtn\005vcvtp\005vcvtr\005vcvtt\004vcx1" 10408 "\005vcx1a\004vcx2\005vcx2a\004vcx3\005vcx3a\005vddup\004vdiv\004vdot\004" 10409 "vdup\006vdwdup\004veor\004vext\004vfma\005vfmab\005vfmal\005vfmas\005vf" 10410 "mat\004vfms\005vfmsl\005vfnma\005vfnms\005vhadd\006vhcadd\005vhsub\005v" 10411 "idup\004vins\006viwdup\005vjcvt\004vld1\004vld2\005vld20\005vld21\004vl" 10412 "d3\004vld4\005vld40\005vld41\005vld42\005vld43\006vldmdb\006vldmia\004v" 10413 "ldr\005vldrb\005vldrd\005vldrh\005vldrw\005vlldm\005vlstm\004vmax\005vm" 10414 "axa\006vmaxav\006vmaxnm\007vmaxnma\010vmaxnmav\007vmaxnmv\005vmaxv\004v" 10415 "min\005vmina\006vminav\006vminnm\007vminnma\010vminnmav\007vminnmv\005v" 10416 "minv\004vmla\007vmladav\010vmladava\tvmladavax\010vmladavx\005vmlal\010" 10417 "vmlaldav\tvmlaldava\nvmlaldavax\tvmlaldavx\006vmlalv\007vmlalva\005vmla" 10418 "s\005vmlav\006vmlava\004vmls\007vmlsdav\010vmlsdava\tvmlsdavax\010vmlsd" 10419 "avx\005vmlsl\010vmlsldav\tvmlsldava\nvmlsldavax\tvmlsldavx\005vmmla\004" 10420 "vmov\005vmovl\006vmovlb\006vmovlt\005vmovn\006vmovnb\006vmovnt\005vmovx" 10421 "\004vmrs\004vmsr\004vmul\005vmulh\005vmull\006vmullb\006vmullt\004vmvn\004" 10422 "vneg\005vnmla\005vnmls\005vnmul\004vorn\004vorr\006vpadal\005vpadd\006v" 10423 "paddl\005vpmax\005vpmin\005vpnot\004vpop\005vpsel\004vpst\003vpt\005vpu" 10424 "sh\005vqabs\005vqadd\010vqdmladh\tvqdmladhx\007vqdmlah\007vqdmlal\010vq" 10425 "dmlash\010vqdmlsdh\tvqdmlsdhx\007vqdmlsl\007vqdmulh\007vqdmull\010vqdmu" 10426 "llb\010vqdmullt\006vqmovn\007vqmovnb\007vqmovnt\007vqmovun\010vqmovunb\010" 10427 "vqmovunt\005vqneg\tvqrdmladh\nvqrdmladhx\010vqrdmlah\tvqrdmlash\tvqrdml" 10428 "sdh\nvqrdmlsdhx\010vqrdmlsh\010vqrdmulh\006vqrshl\007vqrshrn\010vqrshrn" 10429 "b\010vqrshrnt\010vqrshrun\tvqrshrunb\tvqrshrunt\005vqshl\006vqshlu\006v" 10430 "qshrn\007vqshrnb\007vqshrnt\007vqshrun\010vqshrunb\010vqshrunt\005vqsub" 10431 "\007vraddhn\006vrecpe\006vrecps\006vrev16\006vrev32\006vrev64\006vrhadd" 10432 "\006vrinta\006vrintm\006vrintn\006vrintp\006vrintr\006vrintx\006vrintz\n" 10433 "vrmlaldavh\013vrmlaldavha\014vrmlaldavhax\013vrmlaldavhx\010vrmlalvh\tv" 10434 "rmlalvha\nvrmlsldavh\013vrmlsldavha\014vrmlsldavhax\013vrmlsldavhx\006v" 10435 "rmulh\005vrshl\005vrshr\006vrshrn\007vrshrnb\007vrshrnt\007vrsqrte\007v" 10436 "rsqrts\005vrsra\007vrsubhn\004vsbc\005vsbci\007vscclrm\005vsdot\006vsel" 10437 "eq\006vselge\006vselgt\006vselvs\004vshl\005vshlc\005vshll\006vshllb\006" 10438 "vshllt\004vshr\005vshrn\006vshrnb\006vshrnt\004vsli\006vsmmla\005vsqrt\004" 10439 "vsra\004vsri\004vst1\004vst2\005vst20\005vst21\004vst3\004vst4\005vst40" 10440 "\005vst41\005vst42\005vst43\006vstmdb\006vstmia\004vstr\005vstrb\005vst" 10441 "rd\005vstrh\005vstrw\004vsub\006vsubhn\005vsubl\005vsubw\006vsudot\004v" 10442 "swp\004vtbl\004vtbx\004vtrn\004vtst\005vudot\006vummla\006vusdot\007vus" 10443 "mmla\004vuzp\004vzip\003wfe\003wfi\003wls\005wlstp\005yield"; 10444 10445// Feature bitsets. 10446enum : uint8_t { 10447 AMFBS_None, 10448 AMFBS_Has8MSecExt, 10449 AMFBS_HasBF16, 10450 AMFBS_HasCDE, 10451 AMFBS_HasDB, 10452 AMFBS_HasDFB, 10453 AMFBS_HasDotProd, 10454 AMFBS_HasFP16, 10455 AMFBS_HasFPARMv8, 10456 AMFBS_HasFPRegs, 10457 AMFBS_HasFPRegs16, 10458 AMFBS_HasFPRegs64, 10459 AMFBS_HasFPRegsV8_1M, 10460 AMFBS_HasFullFP16, 10461 AMFBS_HasMVEFloat, 10462 AMFBS_HasMVEInt, 10463 AMFBS_HasMatMulInt8, 10464 AMFBS_HasNEON, 10465 AMFBS_HasV8_1MMainline, 10466 AMFBS_HasVFP2, 10467 AMFBS_HasVFP3, 10468 AMFBS_HasVFP4, 10469 AMFBS_IsARM, 10470 AMFBS_IsThumb, 10471 AMFBS_IsThumb2, 10472 AMFBS_HasBF16_HasNEON, 10473 AMFBS_HasCDE_HasFPRegs, 10474 AMFBS_HasCDE_HasMVEInt, 10475 AMFBS_HasDB_IsThumb2, 10476 AMFBS_HasDSP_IsThumb2, 10477 AMFBS_HasFPARMv8_HasDPVFP, 10478 AMFBS_HasFPARMv8_HasV8_3a, 10479 AMFBS_HasFPRegs_HasV8_1MMainline, 10480 AMFBS_HasMVEInt_IsThumb, 10481 AMFBS_HasNEON_HasFP16, 10482 AMFBS_HasNEON_HasFP16FML, 10483 AMFBS_HasNEON_HasFullFP16, 10484 AMFBS_HasNEON_HasV8_1a, 10485 AMFBS_HasNEON_HasV8_3a, 10486 AMFBS_HasNEON_HasVFP4, 10487 AMFBS_HasV7_IsMClass, 10488 AMFBS_HasV8_HasAES, 10489 AMFBS_HasV8_HasNEON, 10490 AMFBS_HasV8_HasSHA2, 10491 AMFBS_HasV8MMainline_Has8MSecExt, 10492 AMFBS_HasV8_1MMainline_Has8MSecExt, 10493 AMFBS_HasV8_1MMainline_HasFPRegs, 10494 AMFBS_HasV8_1MMainline_HasMVEInt, 10495 AMFBS_HasVFP2_HasDPVFP, 10496 AMFBS_HasVFP3_HasDPVFP, 10497 AMFBS_HasVFP4_HasDPVFP, 10498 AMFBS_IsARM_HasAcquireRelease, 10499 AMFBS_IsARM_HasDB, 10500 AMFBS_IsARM_HasDFB, 10501 AMFBS_IsARM_HasDivideInARM, 10502 AMFBS_IsARM_HasRAS, 10503 AMFBS_IsARM_HasSB, 10504 AMFBS_IsARM_HasTrustZone, 10505 AMFBS_IsARM_HasV4T, 10506 AMFBS_IsARM_HasV5T, 10507 AMFBS_IsARM_HasV5TE, 10508 AMFBS_IsARM_HasV6, 10509 AMFBS_IsARM_HasV6K, 10510 AMFBS_IsARM_HasV6T2, 10511 AMFBS_IsARM_HasV7, 10512 AMFBS_IsARM_HasV8, 10513 AMFBS_IsARM_HasV8_4a, 10514 AMFBS_IsARM_HasVirtualization, 10515 AMFBS_IsARM_PreV8, 10516 AMFBS_IsARM_UseNaClTrap, 10517 AMFBS_IsARM_UseNegativeImmediates, 10518 AMFBS_IsThumb_Has8MSecExt, 10519 AMFBS_IsThumb_HasAcquireRelease, 10520 AMFBS_IsThumb_HasDB, 10521 AMFBS_IsThumb_HasV5T, 10522 AMFBS_IsThumb_HasV6, 10523 AMFBS_IsThumb_HasV6M, 10524 AMFBS_IsThumb_HasV7Clrex, 10525 AMFBS_IsThumb_HasV8, 10526 AMFBS_IsThumb_HasV8MBaseline, 10527 AMFBS_IsThumb_HasV8_4a, 10528 AMFBS_IsThumb_HasVirtualization, 10529 AMFBS_IsThumb_IsMClass, 10530 AMFBS_IsThumb_IsNotMClass, 10531 AMFBS_IsThumb_UseNegativeImmediates, 10532 AMFBS_IsThumb2_HasDSP, 10533 AMFBS_IsThumb2_HasRAS, 10534 AMFBS_IsThumb2_HasSB, 10535 AMFBS_IsThumb2_HasTrustZone, 10536 AMFBS_IsThumb2_HasV7, 10537 AMFBS_IsThumb2_HasV8, 10538 AMFBS_IsThumb2_HasVirtualization, 10539 AMFBS_IsThumb2_IsNotMClass, 10540 AMFBS_IsThumb2_PreV8, 10541 AMFBS_IsThumb2_UseNegativeImmediates, 10542 AMFBS_PreV8_IsThumb2, 10543 AMFBS_HasDivideInThumb_IsThumb_HasV8MBaseline, 10544 AMFBS_HasNEON_HasV8_3a_HasFullFP16, 10545 AMFBS_HasV8_HasNEON_HasFullFP16, 10546 AMFBS_IsARM_HasAcquireRelease_HasV7Clrex, 10547 AMFBS_IsARM_HasV7_HasMP, 10548 AMFBS_IsARM_HasV8_HasCLRBHB, 10549 AMFBS_IsARM_HasV8_HasCRC, 10550 AMFBS_IsARM_HasV8_HasV8_1a, 10551 AMFBS_IsThumb_HasAcquireRelease_HasV7Clrex, 10552 AMFBS_IsThumb_HasV5T_IsNotMClass, 10553 AMFBS_IsThumb2_HasV7_HasMP, 10554 AMFBS_IsThumb2_HasV8_HasCLRBHB, 10555 AMFBS_IsThumb2_HasV8_HasCRC, 10556 AMFBS_IsThumb2_HasV8_HasV8_1a, 10557 AMFBS_IsThumb2_HasV8_1MMainline_HasLOB, 10558 AMFBS_IsThumb2_HasV8_1MMainline_HasPACBTI, 10559 AMFBS_IsThumb_HasAcquireRelease_HasV7Clrex_IsNotMClass, 10560}; 10561 10562static constexpr FeatureBitset FeatureBitsets[] = { 10563 {}, // AMFBS_None 10564 {Feature_Has8MSecExtBit, }, 10565 {Feature_HasBF16Bit, }, 10566 {Feature_HasCDEBit, }, 10567 {Feature_HasDBBit, }, 10568 {Feature_HasDFBBit, }, 10569 {Feature_HasDotProdBit, }, 10570 {Feature_HasFP16Bit, }, 10571 {Feature_HasFPARMv8Bit, }, 10572 {Feature_HasFPRegsBit, }, 10573 {Feature_HasFPRegs16Bit, }, 10574 {Feature_HasFPRegs64Bit, }, 10575 {Feature_HasFPRegsV8_1MBit, }, 10576 {Feature_HasFullFP16Bit, }, 10577 {Feature_HasMVEFloatBit, }, 10578 {Feature_HasMVEIntBit, }, 10579 {Feature_HasMatMulInt8Bit, }, 10580 {Feature_HasNEONBit, }, 10581 {Feature_HasV8_1MMainlineBit, }, 10582 {Feature_HasVFP2Bit, }, 10583 {Feature_HasVFP3Bit, }, 10584 {Feature_HasVFP4Bit, }, 10585 {Feature_IsARMBit, }, 10586 {Feature_IsThumbBit, }, 10587 {Feature_IsThumb2Bit, }, 10588 {Feature_HasBF16Bit, Feature_HasNEONBit, }, 10589 {Feature_HasCDEBit, Feature_HasFPRegsBit, }, 10590 {Feature_HasCDEBit, Feature_HasMVEIntBit, }, 10591 {Feature_HasDBBit, Feature_IsThumb2Bit, }, 10592 {Feature_HasDSPBit, Feature_IsThumb2Bit, }, 10593 {Feature_HasFPARMv8Bit, Feature_HasDPVFPBit, }, 10594 {Feature_HasFPARMv8Bit, Feature_HasV8_3aBit, }, 10595 {Feature_HasFPRegsBit, Feature_HasV8_1MMainlineBit, }, 10596 {Feature_HasMVEIntBit, Feature_IsThumbBit, }, 10597 {Feature_HasNEONBit, Feature_HasFP16Bit, }, 10598 {Feature_HasNEONBit, Feature_HasFP16FMLBit, }, 10599 {Feature_HasNEONBit, Feature_HasFullFP16Bit, }, 10600 {Feature_HasNEONBit, Feature_HasV8_1aBit, }, 10601 {Feature_HasNEONBit, Feature_HasV8_3aBit, }, 10602 {Feature_HasNEONBit, Feature_HasVFP4Bit, }, 10603 {Feature_HasV7Bit, Feature_IsMClassBit, }, 10604 {Feature_HasV8Bit, Feature_HasAESBit, }, 10605 {Feature_HasV8Bit, Feature_HasNEONBit, }, 10606 {Feature_HasV8Bit, Feature_HasSHA2Bit, }, 10607 {Feature_HasV8MMainlineBit, Feature_Has8MSecExtBit, }, 10608 {Feature_HasV8_1MMainlineBit, Feature_Has8MSecExtBit, }, 10609 {Feature_HasV8_1MMainlineBit, Feature_HasFPRegsBit, }, 10610 {Feature_HasV8_1MMainlineBit, Feature_HasMVEIntBit, }, 10611 {Feature_HasVFP2Bit, Feature_HasDPVFPBit, }, 10612 {Feature_HasVFP3Bit, Feature_HasDPVFPBit, }, 10613 {Feature_HasVFP4Bit, Feature_HasDPVFPBit, }, 10614 {Feature_IsARMBit, Feature_HasAcquireReleaseBit, }, 10615 {Feature_IsARMBit, Feature_HasDBBit, }, 10616 {Feature_IsARMBit, Feature_HasDFBBit, }, 10617 {Feature_IsARMBit, Feature_HasDivideInARMBit, }, 10618 {Feature_IsARMBit, Feature_HasRASBit, }, 10619 {Feature_IsARMBit, Feature_HasSBBit, }, 10620 {Feature_IsARMBit, Feature_HasTrustZoneBit, }, 10621 {Feature_IsARMBit, Feature_HasV4TBit, }, 10622 {Feature_IsARMBit, Feature_HasV5TBit, }, 10623 {Feature_IsARMBit, Feature_HasV5TEBit, }, 10624 {Feature_IsARMBit, Feature_HasV6Bit, }, 10625 {Feature_IsARMBit, Feature_HasV6KBit, }, 10626 {Feature_IsARMBit, Feature_HasV6T2Bit, }, 10627 {Feature_IsARMBit, Feature_HasV7Bit, }, 10628 {Feature_IsARMBit, Feature_HasV8Bit, }, 10629 {Feature_IsARMBit, Feature_HasV8_4aBit, }, 10630 {Feature_IsARMBit, Feature_HasVirtualizationBit, }, 10631 {Feature_IsARMBit, Feature_PreV8Bit, }, 10632 {Feature_IsARMBit, Feature_UseNaClTrapBit, }, 10633 {Feature_IsARMBit, Feature_UseNegativeImmediatesBit, }, 10634 {Feature_IsThumbBit, Feature_Has8MSecExtBit, }, 10635 {Feature_IsThumbBit, Feature_HasAcquireReleaseBit, }, 10636 {Feature_IsThumbBit, Feature_HasDBBit, }, 10637 {Feature_IsThumbBit, Feature_HasV5TBit, }, 10638 {Feature_IsThumbBit, Feature_HasV6Bit, }, 10639 {Feature_IsThumbBit, Feature_HasV6MBit, }, 10640 {Feature_IsThumbBit, Feature_HasV7ClrexBit, }, 10641 {Feature_IsThumbBit, Feature_HasV8Bit, }, 10642 {Feature_IsThumbBit, Feature_HasV8MBaselineBit, }, 10643 {Feature_IsThumbBit, Feature_HasV8_4aBit, }, 10644 {Feature_IsThumbBit, Feature_HasVirtualizationBit, }, 10645 {Feature_IsThumbBit, Feature_IsMClassBit, }, 10646 {Feature_IsThumbBit, Feature_IsNotMClassBit, }, 10647 {Feature_IsThumbBit, Feature_UseNegativeImmediatesBit, }, 10648 {Feature_IsThumb2Bit, Feature_HasDSPBit, }, 10649 {Feature_IsThumb2Bit, Feature_HasRASBit, }, 10650 {Feature_IsThumb2Bit, Feature_HasSBBit, }, 10651 {Feature_IsThumb2Bit, Feature_HasTrustZoneBit, }, 10652 {Feature_IsThumb2Bit, Feature_HasV7Bit, }, 10653 {Feature_IsThumb2Bit, Feature_HasV8Bit, }, 10654 {Feature_IsThumb2Bit, Feature_HasVirtualizationBit, }, 10655 {Feature_IsThumb2Bit, Feature_IsNotMClassBit, }, 10656 {Feature_IsThumb2Bit, Feature_PreV8Bit, }, 10657 {Feature_IsThumb2Bit, Feature_UseNegativeImmediatesBit, }, 10658 {Feature_PreV8Bit, Feature_IsThumb2Bit, }, 10659 {Feature_HasDivideInThumbBit, Feature_IsThumbBit, Feature_HasV8MBaselineBit, }, 10660 {Feature_HasNEONBit, Feature_HasV8_3aBit, Feature_HasFullFP16Bit, }, 10661 {Feature_HasV8Bit, Feature_HasNEONBit, Feature_HasFullFP16Bit, }, 10662 {Feature_IsARMBit, Feature_HasAcquireReleaseBit, Feature_HasV7ClrexBit, }, 10663 {Feature_IsARMBit, Feature_HasV7Bit, Feature_HasMPBit, }, 10664 {Feature_IsARMBit, Feature_HasV8Bit, Feature_HasCLRBHBBit, }, 10665 {Feature_IsARMBit, Feature_HasV8Bit, Feature_HasCRCBit, }, 10666 {Feature_IsARMBit, Feature_HasV8Bit, Feature_HasV8_1aBit, }, 10667 {Feature_IsThumbBit, Feature_HasAcquireReleaseBit, Feature_HasV7ClrexBit, }, 10668 {Feature_IsThumbBit, Feature_HasV5TBit, Feature_IsNotMClassBit, }, 10669 {Feature_IsThumb2Bit, Feature_HasV7Bit, Feature_HasMPBit, }, 10670 {Feature_IsThumb2Bit, Feature_HasV8Bit, Feature_HasCLRBHBBit, }, 10671 {Feature_IsThumb2Bit, Feature_HasV8Bit, Feature_HasCRCBit, }, 10672 {Feature_IsThumb2Bit, Feature_HasV8Bit, Feature_HasV8_1aBit, }, 10673 {Feature_IsThumb2Bit, Feature_HasV8_1MMainlineBit, Feature_HasLOBBit, }, 10674 {Feature_IsThumb2Bit, Feature_HasV8_1MMainlineBit, Feature_HasPACBTIBit, }, 10675 {Feature_IsThumbBit, Feature_HasAcquireReleaseBit, Feature_HasV7ClrexBit, Feature_IsNotMClassBit, }, 10676}; 10677 10678namespace { 10679 struct MatchEntry { 10680 uint16_t Mnemonic; 10681 uint16_t Opcode; 10682 uint16_t ConvertFn; 10683 uint8_t RequiredFeaturesIdx; 10684 uint16_t Classes[18]; 10685 StringRef getMnemonic() const { 10686 return StringRef(MnemonicTable + Mnemonic + 1, 10687 MnemonicTable[Mnemonic]); 10688 } 10689 }; 10690 10691 // Predicate for searching for an opcode. 10692 struct LessOpcode { 10693 bool operator()(const MatchEntry &LHS, StringRef RHS) { 10694 return LHS.getMnemonic() < RHS; 10695 } 10696 bool operator()(StringRef LHS, const MatchEntry &RHS) { 10697 return LHS < RHS.getMnemonic(); 10698 } 10699 bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) { 10700 return LHS.getMnemonic() < RHS.getMnemonic(); 10701 } 10702 }; 10703} // end anonymous namespace 10704 10705static const MatchEntry MatchTable0[] = { 10706 { 0 /* __brkdiv0 */, ARM::t__brkdiv0, Convert_NoOperands, AMFBS_IsThumb, { }, }, 10707 { 10 /* adc */, ARM::tADC, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 10708 { 10 /* adc */, ARM::ADCrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, }, 10709 { 10 /* adc */, ARM::ADCrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, }, 10710 { 10 /* adc */, ARM::ADCri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, }, 10711 { 10 /* adc */, ARM::SBCri, Convert__Reg1_2__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImmNot }, }, 10712 { 10 /* adc */, ARM::ADCrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, }, 10713 { 10 /* adc */, ARM::t2ADCrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 10714 { 10 /* adc */, ARM::t2ADCrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, }, 10715 { 10 /* adc */, ARM::t2ADCri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, }, 10716 { 10 /* adc */, ARM::t2SBCri, Convert__Reg1_2__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImmNot }, }, 10717 { 10 /* adc */, ARM::ADCrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RegShiftedReg }, }, 10718 { 10 /* adc */, ARM::ADCrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 10719 { 10 /* adc */, ARM::ADCri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, }, 10720 { 10 /* adc */, ARM::SBCri, Convert__Reg1_2__Reg1_3__ModImmNot1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImmNot }, }, 10721 { 10 /* adc */, ARM::ADCrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, }, 10722 { 10 /* adc */, ARM::t2ADCrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 10723 { 10 /* adc */, ARM::t2ADCrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, }, 10724 { 14 /* add */, ARM::tADDspr, Convert__Reg1_1__Tie0_1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_GPRsp, MCK_GPR }, }, 10725 { 14 /* add */, ARM::t2ADDspImm12, Convert__Reg1_1__Reg1_1__Imm0_40951_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_4095 }, }, 10726 { 14 /* add */, ARM::t2SUBspImm12, Convert__Reg1_1__Reg1_1__Imm0_4095Neg1_2__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_4095Neg }, }, 10727 { 14 /* add */, ARM::tADDspi, Convert__Reg1_1__Tie0_1_1__Imm0_508s41_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_508s4 }, }, 10728 { 14 /* add */, ARM::tSUBspi, Convert__regSP__Tie0_1_1__Imm0_508s4Neg1_2__CondCode2_0, AMFBS_IsThumb_UseNegativeImmediates, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_508s4Neg }, }, 10729 { 14 /* add */, ARM::t2ADDri12, Convert__Reg1_1__Reg1_1__Imm0_40951_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm0_4095 }, }, 10730 { 14 /* add */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_1__Imm0_4095Neg1_2__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_Imm0_4095Neg }, }, 10731 { 14 /* add */, ARM::tADDhirr, Convert__Reg1_1__Tie0_1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_GPR, MCK_GPR }, }, 10732 { 14 /* add */, ARM::t2ADDspImm, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRsp, MCK_T2SOImm }, }, 10733 { 14 /* add */, ARM::t2SUBspImm, Convert__Reg1_2__Reg1_2__T2SOImmNeg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPRsp, MCK_T2SOImmNeg }, }, 10734 { 14 /* add */, ARM::t2SUBspImm, Convert__Reg1_2__Reg1_2__T2SOImmNeg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPRsp, MCK_T2SOImmNeg }, }, 10735 { 14 /* add */, ARM::tADDrr, Convert__Reg1_2__CCOut1_0__Reg1_2__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 10736 { 14 /* add */, ARM::tADDi8, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Imm0_2551_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_Imm0_255 }, }, 10737 { 14 /* add */, ARM::tSUBi8, Convert__Reg1_2__CCOut1_0__Tie0_3_3__ThumbModImmNeg8_2551_3__CondCode2_1, AMFBS_IsThumb_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_ThumbModImmNeg8_255 }, }, 10738 { 14 /* add */, ARM::t2ADDri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, }, 10739 { 14 /* add */, ARM::t2SUBri, Convert__Reg1_2__Reg1_2__T2SOImmNeg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImmNeg }, }, 10740 { 14 /* add */, ARM::t2SUBri, Convert__Reg1_2__Reg1_2__T2SOImmNeg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImmNeg }, }, 10741 { 14 /* add */, ARM::t2ADDrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_rGPR }, }, 10742 { 14 /* add */, ARM::t2ADDrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedImm }, }, 10743 { 14 /* add */, ARM::ADDrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, }, 10744 { 14 /* add */, ARM::ADDri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, }, 10745 { 14 /* add */, ARM::SUBri, Convert__Reg1_2__Reg1_2__ModImmNeg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImmNeg }, }, 10746 { 14 /* add */, ARM::ADDrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, }, 10747 { 14 /* add */, ARM::ADDrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, }, 10748 { 14 /* add */, ARM::t2ADDspImm12, Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_Imm0_4095 }, }, 10749 { 14 /* add */, ARM::t2SUBspImm12, Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_Imm0_4095Neg }, }, 10750 { 14 /* add */, ARM::tADDspi, Convert__regSP__Tie0_1_1__Imm0_508s41_3__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_Imm0_508s4 }, }, 10751 { 14 /* add */, ARM::tSUBspi, Convert__regSP__Tie0_1_1__Imm0_508s4Neg1_3__CondCode2_0, AMFBS_IsThumb_UseNegativeImmediates, { MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_Imm0_508s4Neg }, }, 10752 { 14 /* add */, ARM::tADDrSPi, Convert__Reg1_1__Reg1_2__Imm0_1020s41_3__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_GPRsp, MCK_Imm0_1020s4 }, }, 10753 { 14 /* add */, ARM::t2ADR, Convert__Reg1_1__Imm0_40951_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_PC, MCK_Imm0_4095 }, }, 10754 { 14 /* add */, ARM::t2ADDri12, Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_GPR, MCK_Imm0_4095 }, }, 10755 { 14 /* add */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_GPR, MCK_Imm0_4095Neg }, }, 10756 { 14 /* add */, ARM::tADDrSP, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_GPR, MCK_GPRsp, MCK_GPR }, }, 10757 { 14 /* add */, ARM::t2ADDspImm, Convert__Reg1_3__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRsp, MCK_T2SOImm }, }, 10758 { 14 /* add */, ARM::t2SUBspImm, Convert__Reg1_3__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRsp, MCK_T2SOImmNeg }, }, 10759 { 14 /* add */, ARM::t2SUBri, Convert__Reg1_3__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImmNeg }, }, 10760 { 14 /* add */, ARM::t2ADDspImm, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_T2SOImm }, }, 10761 { 14 /* add */, ARM::t2SUBspImm, Convert__Reg1_2__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_T2SOImmNeg }, }, 10762 { 14 /* add */, ARM::t2SUBspImm, Convert__Reg1_2__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_T2SOImmNeg }, }, 10763 { 14 /* add */, ARM::tADDrr, Convert__Reg1_2__CCOut1_0__Reg1_3__Reg1_4__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_tGPR }, }, 10764 { 14 /* add */, ARM::tADDi3, Convert__Reg1_2__CCOut1_0__Reg1_3__Imm0_71_4__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_Imm0_7 }, }, 10765 { 14 /* add */, ARM::tSUBi3, Convert__Reg1_2__CCOut1_0__Reg1_3__ThumbModImmNeg1_71_4__CondCode2_1, AMFBS_IsThumb_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_ThumbModImmNeg1_7 }, }, 10766 { 14 /* add */, ARM::t2ADDri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_GPRnopc, MCK_T2SOImm }, }, 10767 { 14 /* add */, ARM::t2SUBri, Convert__Reg1_2__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_GPRnopc, MCK_T2SOImmNeg }, }, 10768 { 14 /* add */, ARM::t2SUBri, Convert__Reg1_2__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_GPRnopc, MCK_T2SOImmNeg }, }, 10769 { 14 /* add */, ARM::t2ADDrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_rGPR }, }, 10770 { 14 /* add */, ARM::t2ADDrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RegShiftedImm }, }, 10771 { 14 /* add */, ARM::ADDrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 10772 { 14 /* add */, ARM::ADDri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, }, 10773 { 14 /* add */, ARM::SUBri, Convert__Reg1_2__Reg1_3__ModImmNeg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImmNeg }, }, 10774 { 14 /* add */, ARM::ADDrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, }, 10775 { 14 /* add */, ARM::ADDrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, }, 10776 { 14 /* add */, ARM::t2ADDspImm, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRsp, MCK_GPRsp, MCK_T2SOImm }, }, 10777 { 14 /* add */, ARM::t2SUBspImm, Convert__Reg1_3__Reg1_4__T2SOImmNeg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRsp, MCK_GPRsp, MCK_T2SOImmNeg }, }, 10778 { 14 /* add */, ARM::t2SUBspImm, Convert__Reg1_3__Reg1_4__T2SOImmNeg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRsp, MCK_GPRsp, MCK_T2SOImmNeg }, }, 10779 { 14 /* add */, ARM::t2ADDri, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_GPRnopc, MCK_T2SOImm }, }, 10780 { 14 /* add */, ARM::t2SUBri, Convert__Reg1_3__Reg1_4__T2SOImmNeg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_GPRnopc, MCK_T2SOImmNeg }, }, 10781 { 14 /* add */, ARM::t2SUBri, Convert__Reg1_3__Reg1_4__T2SOImmNeg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_GPRnopc, MCK_T2SOImmNeg }, }, 10782 { 14 /* add */, ARM::t2ADDrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc, MCK_rGPR }, }, 10783 { 14 /* add */, ARM::t2ADDrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc, MCK_RegShiftedImm }, }, 10784 { 18 /* addw */, ARM::t2ADDspImm12, Convert__Reg1_1__Reg1_1__Imm0_40951_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_4095 }, }, 10785 { 18 /* addw */, ARM::t2SUBspImm12, Convert__Reg1_1__Reg1_1__Imm0_4095Neg1_2__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_4095Neg }, }, 10786 { 18 /* addw */, ARM::t2ADDri12, Convert__Reg1_1__Reg1_1__Imm0_40951_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm0_4095 }, }, 10787 { 18 /* addw */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_1__Imm0_4095Neg1_2__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_Imm0_4095Neg }, }, 10788 { 18 /* addw */, ARM::t2ADDspImm12, Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_Imm0_4095 }, }, 10789 { 18 /* addw */, ARM::t2SUBspImm12, Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_Imm0_4095Neg }, }, 10790 { 18 /* addw */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_Imm0_4095Neg }, }, 10791 { 18 /* addw */, ARM::t2ADDri12, Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_GPR, MCK_Imm0_4095 }, }, 10792 { 23 /* adr */, ARM::tADR, Convert__Reg1_1__UnsignedOffset_b8s21_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_UnsignedOffset_b8s2 }, }, 10793 { 23 /* adr */, ARM::t2ADR, Convert__Reg1_1__Imm1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm }, }, 10794 { 23 /* adr */, ARM::ADR, Convert__Reg1_1__AdrLabel1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_AdrLabel }, }, 10795 { 23 /* adr */, ARM::t2ADR, Convert__Reg1_2__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_Imm }, }, 10796 { 27 /* aesd */, ARM::AESD, Convert__Reg1_1__Tie0_1_1__Reg1_2, AMFBS_HasV8_HasAES, { MCK__DOT_8, MCK_QPR, MCK_QPR }, }, 10797 { 32 /* aese */, ARM::AESE, Convert__Reg1_1__Tie0_1_1__Reg1_2, AMFBS_HasV8_HasAES, { MCK__DOT_8, MCK_QPR, MCK_QPR }, }, 10798 { 37 /* aesimc */, ARM::AESIMC, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasAES, { MCK__DOT_8, MCK_QPR, MCK_QPR }, }, 10799 { 44 /* aesmc */, ARM::AESMC, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasAES, { MCK__DOT_8, MCK_QPR, MCK_QPR }, }, 10800 { 50 /* and */, ARM::tAND, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 10801 { 50 /* and */, ARM::t2ANDrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 10802 { 50 /* and */, ARM::t2ANDrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, }, 10803 { 50 /* and */, ARM::t2ANDri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, }, 10804 { 50 /* and */, ARM::t2BICri, Convert__Reg1_2__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImmNot }, }, 10805 { 50 /* and */, ARM::ANDrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, }, 10806 { 50 /* and */, ARM::ANDri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, }, 10807 { 50 /* and */, ARM::BICri, Convert__Reg1_2__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImmNot }, }, 10808 { 50 /* and */, ARM::ANDrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, }, 10809 { 50 /* and */, ARM::ANDrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, }, 10810 { 50 /* and */, ARM::t2ANDrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, }, 10811 { 50 /* and */, ARM::t2ANDrs, Convert__Reg1_3__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, }, 10812 { 50 /* and */, ARM::t2ANDri, Convert__Reg1_3__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, }, 10813 { 50 /* and */, ARM::t2BICri, Convert__Reg1_3__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImmNot }, }, 10814 { 50 /* and */, ARM::t2ANDrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 10815 { 50 /* and */, ARM::t2ANDrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, }, 10816 { 50 /* and */, ARM::t2ANDri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, }, 10817 { 50 /* and */, ARM::t2BICri, Convert__Reg1_2__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImmNot }, }, 10818 { 50 /* and */, ARM::ANDrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 10819 { 50 /* and */, ARM::ANDri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, }, 10820 { 50 /* and */, ARM::BICri, Convert__Reg1_2__Reg1_3__ModImmNot1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImmNot }, }, 10821 { 50 /* and */, ARM::ANDrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, }, 10822 { 50 /* and */, ARM::ANDrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, }, 10823 { 50 /* and */, ARM::t2ANDrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 10824 { 50 /* and */, ARM::t2ANDrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, }, 10825 { 50 /* and */, ARM::t2ANDri, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, }, 10826 { 50 /* and */, ARM::t2BICri, Convert__Reg1_3__Reg1_4__T2SOImmNot1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_T2SOImmNot }, }, 10827 { 54 /* asr */, ARM::tASRrr, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 10828 { 54 /* asr */, ARM::tASRri, Convert__Reg1_2__CCOut1_0__Reg1_2__ImmThumbSR1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_ImmThumbSR }, }, 10829 { 54 /* asr */, ARM::t2ASRrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 10830 { 54 /* asr */, ARM::t2ASRri, Convert__Reg1_2__Reg1_2__ImmThumbSR1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_ImmThumbSR }, }, 10831 { 54 /* asr */, ARM::ASRr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, }, 10832 { 54 /* asr */, ARM::ASRi, Convert__Reg1_2__Reg1_2__Imm0_321_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_Imm0_32 }, }, 10833 { 54 /* asr */, ARM::t2ASRrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, }, 10834 { 54 /* asr */, ARM::t2ASRri, Convert__Reg1_3__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_ImmThumbSR }, }, 10835 { 54 /* asr */, ARM::tASRri, Convert__Reg1_2__CCOut1_0__Reg1_3__ImmThumbSR1_4__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_ImmThumbSR }, }, 10836 { 54 /* asr */, ARM::t2ASRrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 10837 { 54 /* asr */, ARM::t2ASRri, Convert__Reg1_2__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_ImmThumbSR }, }, 10838 { 54 /* asr */, ARM::ASRr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 10839 { 54 /* asr */, ARM::ASRi, Convert__Reg1_2__Reg1_3__Imm0_321_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_Imm0_32 }, }, 10840 { 54 /* asr */, ARM::t2ASRrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 10841 { 54 /* asr */, ARM::t2ASRri, Convert__Reg1_3__Reg1_4__ImmThumbSR1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_ImmThumbSR }, }, 10842 { 58 /* asrl */, ARM::MVE_ASRLr, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__Reg1_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_tGPREven, MCK_tGPROdd, MCK_rGPR }, }, 10843 { 58 /* asrl */, ARM::MVE_ASRLi, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__MVELongShift1_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_tGPREven, MCK_tGPROdd, MCK_MVELongShift }, }, 10844 { 63 /* aut */, ARM::t2AUT, Convert_NoOperands, AMFBS_HasV7_IsMClass, { MCK_R12, MCK_GPRlr, MCK_GPRsp }, }, 10845 { 63 /* aut */, ARM::t2HINT, Convert__imm_95_45__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_R12, MCK_GPRlr, MCK_GPRsp }, }, 10846 { 67 /* autg */, ARM::t2AUTG, Convert__CondCode2_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_IsThumb2_HasV8_1MMainline_HasPACBTI, { MCK_CondCode, MCK_GPRnosp, MCK_GPRnopc, MCK_GPRnopc }, }, 10847 { 72 /* b */, ARM::Bcc, Convert__ARMBranchTarget1_1__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_ARMBranchTarget }, }, 10848 { 72 /* b */, ARM::tB, ConvertCustom_cvtThumbBranches, AMFBS_IsThumb, { MCK_CondCode, MCK_Imm }, }, 10849 { 72 /* b */, ARM::tBcc, ConvertCustom_cvtThumbBranches, AMFBS_IsThumb, { MCK_CondCode, MCK_ThumbBranchTarget }, }, 10850 { 72 /* b */, ARM::t2Bcc, ConvertCustom_cvtThumbBranches, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_Imm }, }, 10851 { 72 /* b */, ARM::t2B, ConvertCustom_cvtThumbBranches, AMFBS_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK__DOT_w, MCK_ThumbBranchTarget }, }, 10852 { 74 /* bf */, ARM::t2BFi, Convert__Imm1_1__Imm1_2__CondCode2_0, AMFBS_IsThumb2_HasV8_1MMainline_HasLOB, { MCK_CondCode, MCK_Imm, MCK_Imm }, }, 10853 { 77 /* bfc */, ARM::t2BFC, Convert__Reg1_1__Tie0_1_1__Bitfield1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Bitfield }, }, 10854 { 77 /* bfc */, ARM::BFC, Convert__Reg1_1__Tie0_1_1__Bitfield1_2__CondCode2_0, AMFBS_IsARM_HasV6T2, { MCK_CondCode, MCK_GPR, MCK_Bitfield }, }, 10855 { 81 /* bfcsel */, ARM::t2BFic, Convert__Imm1_0__Imm1_1__Imm1_2__CondCodeNoAL1_3, AMFBS_IsThumb2_HasV8_1MMainline_HasLOB, { MCK_Imm, MCK_Imm, MCK_Imm, MCK_CondCodeNoAL }, }, 10856 { 88 /* bfi */, ARM::t2BFI, Convert__Reg1_1__Tie0_1_1__Reg1_2__Bitfield1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_Bitfield }, }, 10857 { 88 /* bfi */, ARM::BFI, Convert__Reg1_1__Tie0_1_1__Reg1_2__Bitfield1_3__CondCode2_0, AMFBS_IsARM_HasV6T2, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_Bitfield }, }, 10858 { 92 /* bfl */, ARM::t2BFLi, Convert__Imm1_1__Imm1_2__CondCode2_0, AMFBS_IsThumb2_HasV8_1MMainline_HasLOB, { MCK_CondCode, MCK_Imm, MCK_Imm }, }, 10859 { 96 /* bflx */, ARM::t2BFLr, Convert__Imm1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb2_HasV8_1MMainline_HasLOB, { MCK_CondCode, MCK_Imm, MCK_rGPR }, }, 10860 { 101 /* bfx */, ARM::t2BFr, Convert__Imm1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb2_HasV8_1MMainline_HasLOB, { MCK_CondCode, MCK_Imm, MCK_rGPR }, }, 10861 { 105 /* bic */, ARM::tBIC, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 10862 { 105 /* bic */, ARM::t2BICrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 10863 { 105 /* bic */, ARM::t2BICrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, }, 10864 { 105 /* bic */, ARM::t2BICri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, }, 10865 { 105 /* bic */, ARM::t2ANDri, Convert__Reg1_2__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImmNot }, }, 10866 { 105 /* bic */, ARM::BICrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, }, 10867 { 105 /* bic */, ARM::BICri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, }, 10868 { 105 /* bic */, ARM::ANDri, Convert__Reg1_2__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImmNot }, }, 10869 { 105 /* bic */, ARM::BICrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, }, 10870 { 105 /* bic */, ARM::BICrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, }, 10871 { 105 /* bic */, ARM::t2BICrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, }, 10872 { 105 /* bic */, ARM::t2BICrs, Convert__Reg1_3__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, }, 10873 { 105 /* bic */, ARM::t2BICri, Convert__Reg1_3__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, }, 10874 { 105 /* bic */, ARM::t2ANDri, Convert__Reg1_3__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImmNot }, }, 10875 { 105 /* bic */, ARM::t2BICrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 10876 { 105 /* bic */, ARM::t2BICrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, }, 10877 { 105 /* bic */, ARM::t2BICri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, }, 10878 { 105 /* bic */, ARM::t2ANDri, Convert__Reg1_2__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImmNot }, }, 10879 { 105 /* bic */, ARM::BICrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 10880 { 105 /* bic */, ARM::BICri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, }, 10881 { 105 /* bic */, ARM::ANDri, Convert__Reg1_2__Reg1_3__ModImmNot1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImmNot }, }, 10882 { 105 /* bic */, ARM::BICrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, }, 10883 { 105 /* bic */, ARM::BICrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, }, 10884 { 105 /* bic */, ARM::t2BICrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 10885 { 105 /* bic */, ARM::t2BICrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, }, 10886 { 105 /* bic */, ARM::t2BICri, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, }, 10887 { 105 /* bic */, ARM::t2ANDri, Convert__Reg1_3__Reg1_4__T2SOImmNot1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_T2SOImmNot }, }, 10888 { 109 /* bkpt */, ARM::BKPT, Convert__imm_95_0, AMFBS_IsARM, { }, }, 10889 { 109 /* bkpt */, ARM::tBKPT, Convert__imm_95_0, AMFBS_IsThumb, { }, }, 10890 { 109 /* bkpt */, ARM::tBKPT, Convert__Imm0_2551_0, AMFBS_IsThumb, { MCK_Imm0_255 }, }, 10891 { 109 /* bkpt */, ARM::BKPT, Convert__Imm0_655351_0, AMFBS_IsARM, { MCK_Imm0_65535 }, }, 10892 { 114 /* bl */, ARM::BL, Convert__ARMBranchTarget1_0, AMFBS_IsARM, { MCK_ARMBranchTarget }, }, 10893 { 114 /* bl */, ARM::BL_pred, Convert__ARMBranchTarget1_1__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_ARMBranchTarget }, }, 10894 { 114 /* bl */, ARM::tBL, Convert__CondCode2_0__ThumbBranchTarget1_1, AMFBS_IsThumb, { MCK_CondCode, MCK_ThumbBranchTarget }, }, 10895 { 114 /* bl */, ARM::tBL, Convert__CondCode2_0__ThumbBranchTarget1_2, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_ThumbBranchTarget }, }, 10896 { 117 /* blx */, ARM::BLX, Convert__Reg1_0, AMFBS_IsARM_HasV5T, { MCK_GPR }, }, 10897 { 117 /* blx */, ARM::BLXi, Convert__ThumbBranchTarget1_0, AMFBS_IsARM_HasV5T, { MCK_ThumbBranchTarget }, }, 10898 { 117 /* blx */, ARM::BLX_pred, Convert__Reg1_1__CondCode2_0, AMFBS_IsARM_HasV5T, { MCK_CondCode, MCK_GPR }, }, 10899 { 117 /* blx */, ARM::tBLXr, Convert__CondCode2_0__Reg1_1, AMFBS_IsThumb_HasV5T, { MCK_CondCode, MCK_GPR }, }, 10900 { 117 /* blx */, ARM::tBLXi, Convert__CondCode2_0__ARMBranchTarget1_1, AMFBS_IsThumb_HasV5T_IsNotMClass, { MCK_CondCode, MCK_ARMBranchTarget }, }, 10901 { 121 /* blxns */, ARM::tBLXNSr, Convert__CondCode2_0__Reg1_1, AMFBS_IsThumb_Has8MSecExt, { MCK_CondCode, MCK_GPRnopc }, }, 10902 { 127 /* bti */, ARM::t2BTI, Convert_NoOperands, AMFBS_HasV7_IsMClass, { }, }, 10903 { 127 /* bti */, ARM::t2HINT, Convert__imm_95_15__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode }, }, 10904 { 131 /* bx */, ARM::BX, Convert__Reg1_0, AMFBS_IsARM_HasV4T, { MCK_GPR }, }, 10905 { 131 /* bx */, ARM::BX_RET, Convert__CondCode2_0, AMFBS_IsARM_HasV4T, { MCK_CondCode, MCK_GPRlr }, }, 10906 { 131 /* bx */, ARM::BX_pred, Convert__Reg1_1__CondCode2_0, AMFBS_IsARM_HasV4T, { MCK_CondCode, MCK_GPR }, }, 10907 { 131 /* bx */, ARM::tBX, Convert__Reg1_1__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_GPR }, }, 10908 { 134 /* bxaut */, ARM::t2BXAUT, Convert__CondCode2_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_IsThumb2_HasV8_1MMainline_HasPACBTI, { MCK_CondCode, MCK_GPRnosp, MCK_rGPR, MCK_GPRnopc }, }, 10909 { 140 /* bxj */, ARM::t2BXJ, Convert__Reg1_1__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPRnopc }, }, 10910 { 140 /* bxj */, ARM::BXJ, Convert__Reg1_1__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR }, }, 10911 { 144 /* bxns */, ARM::tBXNS, Convert__Reg1_1__CondCode2_0, AMFBS_IsThumb_Has8MSecExt, { MCK_CondCode, MCK_GPR }, }, 10912 { 149 /* cbnz */, ARM::tCBNZ, Convert__Reg1_0__ThumbBranchTarget1_1, AMFBS_IsThumb_HasV8MBaseline, { MCK_tGPR, MCK_ThumbBranchTarget }, }, 10913 { 154 /* cbz */, ARM::tCBZ, Convert__Reg1_0__ThumbBranchTarget1_1, AMFBS_IsThumb_HasV8MBaseline, { MCK_tGPR, MCK_ThumbBranchTarget }, }, 10914 { 158 /* cdp */, ARM::CDP, Convert__CoprocNum1_1__Imm0_151_2__CoprocReg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, AMFBS_IsARM_PreV8, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_CoprocReg, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, }, 10915 { 158 /* cdp */, ARM::t2CDP, Convert__CoprocNum1_1__Imm0_151_2__CoprocReg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, AMFBS_IsThumb2_PreV8, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_CoprocReg, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, }, 10916 { 162 /* cdp2 */, ARM::CDP2, Convert__CoprocNum1_0__Imm0_151_1__CoprocReg1_2__CoprocReg1_3__CoprocReg1_4__Imm0_71_5, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_Imm0_15, MCK_CoprocReg, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, }, 10917 { 162 /* cdp2 */, ARM::t2CDP2, Convert__CoprocNum1_1__Imm0_151_2__CoprocReg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, AMFBS_IsThumb2_PreV8, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_CoprocReg, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, }, 10918 { 167 /* cinc */, ARM::t2CSINC, Convert__Reg1_0__Reg1_1__Reg1_1__CondCodeNoALInv1_2, AMFBS_HasV8_1MMainline, { MCK_rGPR, MCK_GPRwithZRnosp, MCK_CondCodeNoALInv }, }, 10919 { 172 /* cinv */, ARM::t2CSINV, Convert__Reg1_0__Reg1_1__Reg1_1__CondCodeNoALInv1_2, AMFBS_HasV8_1MMainline, { MCK_rGPR, MCK_GPRwithZRnosp, MCK_CondCodeNoALInv }, }, 10920 { 177 /* clrbhb */, ARM::HINT, Convert__imm_95_22__CondCode2_0, AMFBS_IsARM_HasV8_HasCLRBHB, { MCK_CondCode }, }, 10921 { 177 /* clrbhb */, ARM::t2HINT, Convert__imm_95_22__CondCode2_0, AMFBS_IsThumb2_HasV8_HasCLRBHB, { MCK_CondCode }, }, 10922 { 177 /* clrbhb */, ARM::HINT, Convert__imm_95_22__CondCode2_0, AMFBS_IsARM_HasV8, { MCK_CondCode }, }, 10923 { 177 /* clrbhb */, ARM::t2HINT, Convert__imm_95_22__CondCode2_0, AMFBS_IsThumb2_HasV8, { MCK_CondCode }, }, 10924 { 184 /* clrex */, ARM::CLREX, Convert_NoOperands, AMFBS_IsARM_HasV6K, { }, }, 10925 { 184 /* clrex */, ARM::t2CLREX, Convert__CondCode2_0, AMFBS_IsThumb_HasV7Clrex, { MCK_CondCode }, }, 10926 { 190 /* clrm */, ARM::t2CLRM, Convert__CondCode2_0__RegListWithAPSR1_1, AMFBS_HasV8_1MMainline, { MCK_CondCode, MCK_RegListWithAPSR }, }, 10927 { 195 /* clz */, ARM::t2CLZ, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 10928 { 195 /* clz */, ARM::CLZ, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsARM_HasV5T, { MCK_CondCode, MCK_GPR, MCK_GPR }, }, 10929 { 199 /* cmn */, ARM::tCMNz, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 10930 { 199 /* cmn */, ARM::CMPri, Convert__Reg1_1__ModImmNeg1_2__CondCode2_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_ModImmNeg }, }, 10931 { 199 /* cmn */, ARM::t2CMPri, Convert__Reg1_1__T2SOImmNeg1_2__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_T2SOImmNeg }, }, 10932 { 199 /* cmn */, ARM::t2CMNzrr, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_rGPR }, }, 10933 { 199 /* cmn */, ARM::t2CMNzrs, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedImm }, }, 10934 { 199 /* cmn */, ARM::CMNzrsr, Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, }, 10935 { 199 /* cmn */, ARM::t2CMNri, Convert__Reg1_1__T2SOImm1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_T2SOImm }, }, 10936 { 199 /* cmn */, ARM::CMNzrr, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR }, }, 10937 { 199 /* cmn */, ARM::CMNri, Convert__Reg1_1__ModImm1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_ModImm }, }, 10938 { 199 /* cmn */, ARM::CMNzrsi, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, }, 10939 { 199 /* cmn */, ARM::t2CMNzrr, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_rGPR }, }, 10940 { 199 /* cmn */, ARM::t2CMNzrs, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_RegShiftedImm }, }, 10941 { 199 /* cmn */, ARM::t2CMNri, Convert__Reg1_2__T2SOImm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_T2SOImm }, }, 10942 { 203 /* cmp */, ARM::tCMPr, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 10943 { 203 /* cmp */, ARM::tCMPi8, Convert__Reg1_1__Imm0_2551_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_Imm0_255 }, }, 10944 { 203 /* cmp */, ARM::CMNri, Convert__Reg1_1__ModImmNeg1_2__CondCode2_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_ModImmNeg }, }, 10945 { 203 /* cmp */, ARM::t2CMNri, Convert__Reg1_1__T2SOImmNeg1_2__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_T2SOImmNeg }, }, 10946 { 203 /* cmp */, ARM::t2CMPrs, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedImm }, }, 10947 { 203 /* cmp */, ARM::CMPrsr, Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, }, 10948 { 203 /* cmp */, ARM::t2CMPri, Convert__Reg1_1__T2SOImm1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_T2SOImm }, }, 10949 { 203 /* cmp */, ARM::CMPrr, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR }, }, 10950 { 203 /* cmp */, ARM::tCMPhir, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_GPR, MCK_GPR }, }, 10951 { 203 /* cmp */, ARM::CMPri, Convert__Reg1_1__ModImm1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_ModImm }, }, 10952 { 203 /* cmp */, ARM::CMPrsi, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, }, 10953 { 203 /* cmp */, ARM::t2CMPrr, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_rGPR }, }, 10954 { 203 /* cmp */, ARM::t2CMPrs, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_RegShiftedImm }, }, 10955 { 203 /* cmp */, ARM::t2CMPri, Convert__Reg1_2__T2SOImm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_T2SOImm }, }, 10956 { 207 /* cneg */, ARM::t2CSNEG, Convert__Reg1_0__Reg1_1__Reg1_1__CondCodeNoALInv1_2, AMFBS_HasV8_1MMainline, { MCK_rGPR, MCK_GPRwithZRnosp, MCK_CondCodeNoALInv }, }, 10957 { 212 /* cps */, ARM::t2CPS1p, Convert__Imm0_311_0, AMFBS_IsThumb2_IsNotMClass, { MCK_Imm0_31 }, }, 10958 { 212 /* cps */, ARM::CPS1p, Convert__Imm0_311_0, AMFBS_IsARM, { MCK_Imm0_31 }, }, 10959 { 212 /* cps */, ARM::t2CPS1p, Convert__Imm0_311_1, AMFBS_IsThumb2, { MCK__DOT_w, MCK_Imm0_31 }, }, 10960 { 212 /* cps */, ARM::CPS2p, Convert__Imm1_0__ProcIFlags1_1, AMFBS_IsARM, { MCK_Imm, MCK_ProcIFlags }, }, 10961 { 212 /* cps */, ARM::tCPS, Convert__Imm1_0__ProcIFlags1_1, AMFBS_IsThumb, { MCK_Imm, MCK_ProcIFlags }, }, 10962 { 212 /* cps */, ARM::t2CPS2p, Convert__Imm1_0__ProcIFlags1_2, AMFBS_IsThumb2_IsNotMClass, { MCK_Imm, MCK__DOT_w, MCK_ProcIFlags }, }, 10963 { 212 /* cps */, ARM::CPS3p, Convert__Imm1_0__ProcIFlags1_1__Imm0_311_2, AMFBS_IsARM, { MCK_Imm, MCK_ProcIFlags, MCK_Imm0_31 }, }, 10964 { 212 /* cps */, ARM::t2CPS3p, Convert__Imm1_0__ProcIFlags1_1__Imm1_2, AMFBS_IsThumb2_IsNotMClass, { MCK_Imm, MCK_ProcIFlags, MCK_Imm }, }, 10965 { 212 /* cps */, ARM::t2CPS3p, Convert__Imm1_0__ProcIFlags1_2__Imm1_3, AMFBS_IsThumb2, { MCK_Imm, MCK__DOT_w, MCK_ProcIFlags, MCK_Imm }, }, 10966 { 216 /* crc32b */, ARM::t2CRC32B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsThumb2_HasV8_HasCRC, { MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 10967 { 216 /* crc32b */, ARM::CRC32B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsARM_HasV8_HasCRC, { MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 10968 { 223 /* crc32cb */, ARM::t2CRC32CB, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsThumb2_HasV8_HasCRC, { MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 10969 { 223 /* crc32cb */, ARM::CRC32CB, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsARM_HasV8_HasCRC, { MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 10970 { 231 /* crc32ch */, ARM::t2CRC32CH, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsThumb2_HasV8_HasCRC, { MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 10971 { 231 /* crc32ch */, ARM::CRC32CH, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsARM_HasV8_HasCRC, { MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 10972 { 239 /* crc32cw */, ARM::t2CRC32CW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsThumb2_HasV8_HasCRC, { MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 10973 { 239 /* crc32cw */, ARM::CRC32CW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsARM_HasV8_HasCRC, { MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 10974 { 247 /* crc32h */, ARM::t2CRC32H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsThumb2_HasV8_HasCRC, { MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 10975 { 247 /* crc32h */, ARM::CRC32H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsARM_HasV8_HasCRC, { MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 10976 { 254 /* crc32w */, ARM::t2CRC32W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsThumb2_HasV8_HasCRC, { MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 10977 { 254 /* crc32w */, ARM::CRC32W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsARM_HasV8_HasCRC, { MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 10978 { 261 /* csdb */, ARM::HINT, Convert__imm_95_20__CondCode2_0, AMFBS_IsARM_HasV6K, { MCK_CondCode }, }, 10979 { 261 /* csdb */, ARM::t2HINT, Convert__imm_95_20__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode }, }, 10980 { 261 /* csdb */, ARM::t2HINT, Convert__imm_95_20__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w }, }, 10981 { 266 /* csel */, ARM::t2CSEL, Convert__Reg1_0__Reg1_1__Reg1_2__CondCodeNoAL1_3, AMFBS_HasV8_1MMainline, { MCK_rGPR, MCK_GPRwithZRnosp, MCK_GPRwithZRnosp, MCK_CondCodeNoAL }, }, 10982 { 271 /* cset */, ARM::t2CSINC, Convert__Reg1_0__regZR__regZR__CondCodeNoALInv1_1, AMFBS_HasV8_1MMainline, { MCK_rGPR, MCK_CondCodeNoALInv }, }, 10983 { 276 /* csetm */, ARM::t2CSINV, Convert__Reg1_0__regZR__regZR__CondCodeNoALInv1_1, AMFBS_HasV8_1MMainline, { MCK_rGPR, MCK_CondCodeNoALInv }, }, 10984 { 282 /* csinc */, ARM::t2CSINC, Convert__Reg1_0__Reg1_1__Reg1_2__CondCodeNoAL1_3, AMFBS_HasV8_1MMainline, { MCK_rGPR, MCK_GPRwithZRnosp, MCK_GPRwithZRnosp, MCK_CondCodeNoAL }, }, 10985 { 288 /* csinv */, ARM::t2CSINV, Convert__Reg1_0__Reg1_1__Reg1_2__CondCodeNoAL1_3, AMFBS_HasV8_1MMainline, { MCK_rGPR, MCK_GPRwithZRnosp, MCK_GPRwithZRnosp, MCK_CondCodeNoAL }, }, 10986 { 294 /* csneg */, ARM::t2CSNEG, Convert__Reg1_0__Reg1_1__Reg1_2__CondCodeNoAL1_3, AMFBS_HasV8_1MMainline, { MCK_rGPR, MCK_GPRwithZRnosp, MCK_GPRwithZRnosp, MCK_CondCodeNoAL }, }, 10987 { 300 /* cx1 */, ARM::CDE_CX1, Convert__Reg1_1__CoprocNum1_0__Imm13b1_2, AMFBS_HasCDE, { MCK_CoprocNum, MCK_GPRwithAPSR_NZCVnosp, MCK_Imm13b }, }, 10988 { 304 /* cx1a */, ARM::CDE_CX1A, Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Imm13b1_3__CondCode2_0, AMFBS_HasCDE, { MCK_CondCode, MCK_CoprocNum, MCK_GPRwithAPSR_NZCVnosp, MCK_Imm13b }, }, 10989 { 309 /* cx1d */, ARM::CDE_CX1D, Convert__Reg1_1__CoprocNum1_0__Imm13b1_2, AMFBS_HasCDE, { MCK_CoprocNum, MCK_GPRPairnosp, MCK_Imm13b }, }, 10990 { 314 /* cx1da */, ARM::CDE_CX1DA, Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Imm13b1_3__CondCode2_0, AMFBS_HasCDE, { MCK_CondCode, MCK_CoprocNum, MCK_GPRPairnosp, MCK_Imm13b }, }, 10991 { 320 /* cx2 */, ARM::CDE_CX2, Convert__Reg1_1__CoprocNum1_0__Reg1_2__Imm9b1_3, AMFBS_HasCDE, { MCK_CoprocNum, MCK_GPRwithAPSR_NZCVnosp, MCK_GPRwithAPSR_NZCVnosp, MCK_Imm9b }, }, 10992 { 324 /* cx2a */, ARM::CDE_CX2A, Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Reg1_3__Imm9b1_4__CondCode2_0, AMFBS_HasCDE, { MCK_CondCode, MCK_CoprocNum, MCK_GPRwithAPSR_NZCVnosp, MCK_GPRwithAPSR_NZCVnosp, MCK_Imm9b }, }, 10993 { 329 /* cx2d */, ARM::CDE_CX2D, Convert__Reg1_1__CoprocNum1_0__Reg1_2__Imm9b1_3, AMFBS_HasCDE, { MCK_CoprocNum, MCK_GPRPairnosp, MCK_GPRwithAPSR_NZCVnosp, MCK_Imm9b }, }, 10994 { 334 /* cx2da */, ARM::CDE_CX2DA, Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Reg1_3__Imm9b1_4__CondCode2_0, AMFBS_HasCDE, { MCK_CondCode, MCK_CoprocNum, MCK_GPRPairnosp, MCK_GPRwithAPSR_NZCVnosp, MCK_Imm9b }, }, 10995 { 340 /* cx3 */, ARM::CDE_CX3, Convert__Reg1_1__CoprocNum1_0__Reg1_2__Reg1_3__Imm6b1_4, AMFBS_HasCDE, { MCK_CoprocNum, MCK_GPRwithAPSR_NZCVnosp, MCK_GPRwithAPSR_NZCVnosp, MCK_GPRwithAPSR_NZCVnosp, MCK_Imm6b }, }, 10996 { 344 /* cx3a */, ARM::CDE_CX3A, Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Reg1_3__Reg1_4__Imm6b1_5__CondCode2_0, AMFBS_HasCDE, { MCK_CondCode, MCK_CoprocNum, MCK_GPRwithAPSR_NZCVnosp, MCK_GPRwithAPSR_NZCVnosp, MCK_GPRwithAPSR_NZCVnosp, MCK_Imm6b }, }, 10997 { 349 /* cx3d */, ARM::CDE_CX3D, Convert__Reg1_1__CoprocNum1_0__Reg1_2__Reg1_3__Imm6b1_4, AMFBS_HasCDE, { MCK_CoprocNum, MCK_GPRPairnosp, MCK_GPRwithAPSR_NZCVnosp, MCK_GPRwithAPSR_NZCVnosp, MCK_Imm6b }, }, 10998 { 354 /* cx3da */, ARM::CDE_CX3DA, Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Reg1_3__Reg1_4__Imm6b1_5__CondCode2_0, AMFBS_HasCDE, { MCK_CondCode, MCK_CoprocNum, MCK_GPRPairnosp, MCK_GPRwithAPSR_NZCVnosp, MCK_GPRwithAPSR_NZCVnosp, MCK_Imm6b }, }, 10999 { 360 /* dbg */, ARM::DBG, Convert__Imm0_151_1__CondCode2_0, AMFBS_IsARM_HasV7, { MCK_CondCode, MCK_Imm0_15 }, }, 11000 { 360 /* dbg */, ARM::t2DBG, Convert__Imm0_151_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_Imm0_15 }, }, 11001 { 360 /* dbg */, ARM::t2DBG, Convert__Imm0_151_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_Imm0_15 }, }, 11002 { 364 /* dcps1 */, ARM::t2DCPS1, Convert__CondCode2_0, AMFBS_IsThumb2_HasV8, { MCK_CondCode }, }, 11003 { 370 /* dcps2 */, ARM::t2DCPS2, Convert__CondCode2_0, AMFBS_IsThumb2_HasV8, { MCK_CondCode }, }, 11004 { 376 /* dcps3 */, ARM::t2DCPS3, Convert__CondCode2_0, AMFBS_IsThumb2_HasV8, { MCK_CondCode }, }, 11005 { 382 /* dfb */, ARM::DSB, Convert__imm_95_12, AMFBS_IsARM_HasDFB, { }, }, 11006 { 382 /* dfb */, ARM::t2DSB, Convert__imm_95_12__CondCode2_0, AMFBS_HasDFB, { MCK_CondCode }, }, 11007 { 386 /* dls */, ARM::t2DLS, Convert__Reg1_0__Reg1_1, AMFBS_IsThumb2_HasV8_1MMainline_HasLOB, { MCK_GPRlr, MCK_rGPR }, }, 11008 { 390 /* dlstp */, ARM::MVE_DLSTP_16, Convert__Reg1_1__Reg1_2, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_GPRlr, MCK_rGPR }, }, 11009 { 390 /* dlstp */, ARM::MVE_DLSTP_32, Convert__Reg1_1__Reg1_2, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_GPRlr, MCK_rGPR }, }, 11010 { 390 /* dlstp */, ARM::MVE_DLSTP_64, Convert__Reg1_1__Reg1_2, AMFBS_HasMVEInt, { MCK__DOT_64, MCK_GPRlr, MCK_rGPR }, }, 11011 { 390 /* dlstp */, ARM::MVE_DLSTP_8, Convert__Reg1_1__Reg1_2, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_GPRlr, MCK_rGPR }, }, 11012 { 396 /* dmb */, ARM::DMB, Convert__imm_95_15, AMFBS_IsARM_HasDB, { }, }, 11013 { 396 /* dmb */, ARM::t2DMB, Convert__imm_95_15__CondCode2_0, AMFBS_HasDB, { MCK_CondCode }, }, 11014 { 396 /* dmb */, ARM::DMB, Convert__MemBarrierOpt1_0, AMFBS_IsARM_HasDB, { MCK_MemBarrierOpt }, }, 11015 { 396 /* dmb */, ARM::t2DMB, Convert__imm_95_15__CondCode2_0, AMFBS_HasDB, { MCK_CondCode, MCK__DOT_w }, }, 11016 { 396 /* dmb */, ARM::t2DMB, Convert__MemBarrierOpt1_1__CondCode2_0, AMFBS_IsThumb_HasDB, { MCK_CondCode, MCK_MemBarrierOpt }, }, 11017 { 396 /* dmb */, ARM::t2DMB, Convert__MemBarrierOpt1_2__CondCode2_0, AMFBS_HasDB, { MCK_CondCode, MCK__DOT_w, MCK_MemBarrierOpt }, }, 11018 { 400 /* dsb */, ARM::DSB, Convert__imm_95_15, AMFBS_IsARM_HasDB, { }, }, 11019 { 400 /* dsb */, ARM::t2DSB, Convert__imm_95_15__CondCode2_0, AMFBS_HasDB, { MCK_CondCode }, }, 11020 { 400 /* dsb */, ARM::DSB, Convert__MemBarrierOpt1_0, AMFBS_IsARM_HasDB, { MCK_MemBarrierOpt }, }, 11021 { 400 /* dsb */, ARM::t2DSB, Convert__imm_95_15__CondCode2_0, AMFBS_HasDB, { MCK_CondCode, MCK__DOT_w }, }, 11022 { 400 /* dsb */, ARM::t2DSB, Convert__MemBarrierOpt1_1__CondCode2_0, AMFBS_IsThumb_HasDB, { MCK_CondCode, MCK_MemBarrierOpt }, }, 11023 { 400 /* dsb */, ARM::t2DSB, Convert__MemBarrierOpt1_2__CondCode2_0, AMFBS_HasDB, { MCK_CondCode, MCK__DOT_w, MCK_MemBarrierOpt }, }, 11024 { 404 /* eor */, ARM::tEOR, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 11025 { 404 /* eor */, ARM::t2EORrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 11026 { 404 /* eor */, ARM::t2EORrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, }, 11027 { 404 /* eor */, ARM::t2EORri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, }, 11028 { 404 /* eor */, ARM::EORrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, }, 11029 { 404 /* eor */, ARM::EORri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, }, 11030 { 404 /* eor */, ARM::EORrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, }, 11031 { 404 /* eor */, ARM::EORrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, }, 11032 { 404 /* eor */, ARM::t2EORrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, }, 11033 { 404 /* eor */, ARM::t2EORrs, Convert__Reg1_3__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, }, 11034 { 404 /* eor */, ARM::t2EORri, Convert__Reg1_3__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, }, 11035 { 404 /* eor */, ARM::t2EORrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11036 { 404 /* eor */, ARM::t2EORrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, }, 11037 { 404 /* eor */, ARM::t2EORri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, }, 11038 { 404 /* eor */, ARM::EORrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 11039 { 404 /* eor */, ARM::EORri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, }, 11040 { 404 /* eor */, ARM::EORrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, }, 11041 { 404 /* eor */, ARM::EORrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, }, 11042 { 404 /* eor */, ARM::t2EORrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11043 { 404 /* eor */, ARM::t2EORrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, }, 11044 { 404 /* eor */, ARM::t2EORri, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, }, 11045 { 408 /* eret */, ARM::ERET, Convert__CondCode2_0, AMFBS_IsARM_HasVirtualization, { MCK_CondCode }, }, 11046 { 408 /* eret */, ARM::t2SUBS_PC_LR, Convert__imm_95_0__CondCode2_0, AMFBS_IsThumb2_HasVirtualization, { MCK_CondCode }, }, 11047 { 413 /* esb */, ARM::HINT, Convert__imm_95_16__CondCode2_0, AMFBS_IsARM_HasRAS, { MCK_CondCode }, }, 11048 { 413 /* esb */, ARM::t2HINT, Convert__imm_95_16__CondCode2_0, AMFBS_IsThumb2_HasRAS, { MCK_CondCode }, }, 11049 { 413 /* esb */, ARM::t2HINT, Convert__imm_95_16__CondCode2_0, AMFBS_IsThumb2_HasRAS, { MCK_CondCode, MCK__DOT_w }, }, 11050 { 417 /* faddd */, ARM::VADDD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11051 { 423 /* fadds */, ARM::VADDS, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_HPR, MCK_HPR, MCK_HPR }, }, 11052 { 429 /* fcmpzd */, ARM::VCMPZD, Convert__Reg1_1__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK_DPR }, }, 11053 { 436 /* fcmpzs */, ARM::VCMPZS, Convert__Reg1_1__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_HPR }, }, 11054 { 443 /* fconstd */, ARM::FCONSTD, Convert__Reg1_1__FPImm1_2__CondCode2_0, AMFBS_HasVFP3, { MCK_CondCode, MCK_DPR, MCK_FPImm }, }, 11055 { 451 /* fconsts */, ARM::FCONSTS, Convert__Reg1_1__FPImm1_2__CondCode2_0, AMFBS_HasVFP3, { MCK_CondCode, MCK_HPR, MCK_FPImm }, }, 11056 { 459 /* fldmdbx */, ARM::FLDMXDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_DPRRegList }, }, 11057 { 467 /* fldmiax */, ARM::FLDMXIA, Convert__Reg1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK_DPRRegList }, }, 11058 { 467 /* fldmiax */, ARM::FLDMXIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_DPRRegList }, }, 11059 { 475 /* fmdhr */, ARM::VSETLNi32, Convert__Reg1_1__Tie0_2_2__Reg1_2__imm_95_1__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_DPR, MCK_GPR }, }, 11060 { 481 /* fmdlr */, ARM::VSETLNi32, Convert__Reg1_1__Tie0_2_2__Reg1_2__imm_95_0__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_DPR, MCK_GPR }, }, 11061 { 487 /* fmstat */, ARM::FMSTAT, Convert__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode }, }, 11062 { 494 /* fstmdbx */, ARM::FSTMXDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_DPRRegList }, }, 11063 { 502 /* fstmiax */, ARM::FSTMXIA, Convert__Reg1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK_DPRRegList }, }, 11064 { 502 /* fstmiax */, ARM::FSTMXIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_DPRRegList }, }, 11065 { 510 /* fsubd */, ARM::VSUBD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11066 { 516 /* fsubs */, ARM::VSUBS, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_HPR, MCK_HPR, MCK_HPR }, }, 11067 { 522 /* hint */, ARM::tHINT, Convert__Imm0_151_1__CondCode2_0, AMFBS_IsThumb_HasV6M, { MCK_CondCode, MCK_Imm0_15 }, }, 11068 { 522 /* hint */, ARM::HINT, Convert__Imm0_2391_1__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_Imm0_239 }, }, 11069 { 522 /* hint */, ARM::t2HINT, Convert__Imm0_2391_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_Imm0_239 }, }, 11070 { 522 /* hint */, ARM::t2HINT, Convert__Imm0_2391_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_Imm0_239 }, }, 11071 { 527 /* hlt */, ARM::tHLT, Convert__Imm0_631_0, AMFBS_IsThumb_HasV8, { MCK_Imm0_63 }, }, 11072 { 527 /* hlt */, ARM::HLT, Convert__Imm0_655351_0, AMFBS_IsARM_HasV8, { MCK_Imm0_65535 }, }, 11073 { 531 /* hvc */, ARM::HVC, Convert__Imm0_655351_0, AMFBS_IsARM_HasVirtualization, { MCK_Imm0_65535 }, }, 11074 { 531 /* hvc */, ARM::t2HVC, Convert__Imm0_655351_0, AMFBS_IsThumb2, { MCK_Imm0_65535 }, }, 11075 { 531 /* hvc */, ARM::t2HVC, Convert__Imm0_655351_1, AMFBS_IsThumb2_HasVirtualization, { MCK__DOT_w, MCK_Imm0_65535 }, }, 11076 { 535 /* isb */, ARM::ISB, Convert__imm_95_15, AMFBS_IsARM_HasDB, { }, }, 11077 { 535 /* isb */, ARM::t2ISB, Convert__imm_95_15__CondCode2_0, AMFBS_HasDB, { MCK_CondCode }, }, 11078 { 535 /* isb */, ARM::ISB, Convert__InstSyncBarrierOpt1_0, AMFBS_IsARM_HasDB, { MCK_InstSyncBarrierOpt }, }, 11079 { 535 /* isb */, ARM::t2ISB, Convert__imm_95_15__CondCode2_0, AMFBS_HasDB, { MCK_CondCode, MCK__DOT_w }, }, 11080 { 535 /* isb */, ARM::t2ISB, Convert__InstSyncBarrierOpt1_1__CondCode2_0, AMFBS_IsThumb_HasDB, { MCK_CondCode, MCK_InstSyncBarrierOpt }, }, 11081 { 535 /* isb */, ARM::t2ISB, Convert__MemBarrierOpt1_2__CondCode2_0, AMFBS_HasDB, { MCK_CondCode, MCK__DOT_w, MCK_MemBarrierOpt }, }, 11082 { 539 /* it */, ARM::ITasm, Convert__ITCondCode1_1__ITMask1_0, AMFBS_IsARM, { MCK_ITMask, MCK_ITCondCode }, }, 11083 { 539 /* it */, ARM::t2IT, Convert__ITCondCode1_1__ITMask1_0, AMFBS_IsThumb2, { MCK_ITMask, MCK_ITCondCode }, }, 11084 { 542 /* lctp */, ARM::MVE_LCTP, Convert__CondCode2_0, AMFBS_HasMVEInt, { MCK_CondCode }, }, 11085 { 547 /* lda */, ARM::t2LDA, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, }, 11086 { 547 /* lda */, ARM::LDA, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM_HasAcquireRelease, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, }, 11087 { 551 /* ldab */, ARM::t2LDAB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, }, 11088 { 551 /* ldab */, ARM::LDAB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM_HasAcquireRelease, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, }, 11089 { 556 /* ldaex */, ARM::t2LDAEX, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, }, 11090 { 556 /* ldaex */, ARM::LDAEX, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, }, 11091 { 562 /* ldaexb */, ARM::t2LDAEXB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, }, 11092 { 562 /* ldaexb */, ARM::LDAEXB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, }, 11093 { 569 /* ldaexd */, ARM::LDAEXD, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_GPRPair, MCK_MemNoOffset }, }, 11094 { 569 /* ldaexd */, ARM::t2LDAEXD, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease_HasV7Clrex_IsNotMClass, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, }, 11095 { 576 /* ldaexh */, ARM::t2LDAEXH, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, }, 11096 { 576 /* ldaexh */, ARM::LDAEXH, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, }, 11097 { 583 /* ldah */, ARM::t2LDAH, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, }, 11098 { 583 /* ldah */, ARM::LDAH, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM_HasAcquireRelease, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, }, 11099 { 588 /* ldc */, ARM::LDC_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, }, 11100 { 588 /* ldc */, ARM::t2LDC_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, }, 11101 { 588 /* ldc */, ARM::LDC_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, }, 11102 { 588 /* ldc */, ARM::t2LDC_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, }, 11103 { 588 /* ldc */, ARM::LDC_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, }, 11104 { 588 /* ldc */, ARM::t2LDC_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, }, 11105 { 588 /* ldc */, ARM::LDC_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, }, 11106 { 588 /* ldc */, ARM::t2LDC_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, }, 11107 { 592 /* ldc2 */, ARM::LDC2_OFFSET, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, }, 11108 { 592 /* ldc2 */, ARM::t2LDC2_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, }, 11109 { 592 /* ldc2 */, ARM::LDC2_PRE, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, }, 11110 { 592 /* ldc2 */, ARM::LDC2_OPTION, Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__CoprocOption1_3, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, }, 11111 { 592 /* ldc2 */, ARM::LDC2_POST, Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__PostIdxImm8s41_3, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, }, 11112 { 592 /* ldc2 */, ARM::t2LDC2_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, }, 11113 { 592 /* ldc2 */, ARM::t2LDC2_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, }, 11114 { 592 /* ldc2 */, ARM::t2LDC2_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, }, 11115 { 597 /* ldc2l */, ARM::LDC2L_OFFSET, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, }, 11116 { 597 /* ldc2l */, ARM::t2LDC2L_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, }, 11117 { 597 /* ldc2l */, ARM::LDC2L_PRE, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, }, 11118 { 597 /* ldc2l */, ARM::LDC2L_OPTION, Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__CoprocOption1_3, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, }, 11119 { 597 /* ldc2l */, ARM::LDC2L_POST, Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__PostIdxImm8s41_3, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, }, 11120 { 597 /* ldc2l */, ARM::t2LDC2L_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, }, 11121 { 597 /* ldc2l */, ARM::t2LDC2L_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, }, 11122 { 597 /* ldc2l */, ARM::t2LDC2L_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, }, 11123 { 603 /* ldcl */, ARM::LDCL_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, }, 11124 { 603 /* ldcl */, ARM::t2LDCL_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, }, 11125 { 603 /* ldcl */, ARM::LDCL_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, }, 11126 { 603 /* ldcl */, ARM::t2LDCL_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, }, 11127 { 603 /* ldcl */, ARM::LDCL_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, }, 11128 { 603 /* ldcl */, ARM::t2LDCL_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, }, 11129 { 603 /* ldcl */, ARM::LDCL_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, }, 11130 { 603 /* ldcl */, ARM::t2LDCL_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, }, 11131 { 608 /* ldm */, ARM::tLDMIA, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_RegList }, }, 11132 { 608 /* ldm */, ARM::LDMIA, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, }, 11133 { 608 /* ldm */, ARM::t2LDMIA, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_RegList }, }, 11134 { 608 /* ldm */, ARM::t2LDMIA, Convert__Reg1_2__CondCode2_0__RegList1_3, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_RegList }, }, 11135 { 608 /* ldm */, ARM::tLDMIA, Convert__Reg1_1__CondCode2_0__RegList1_3, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK__EXCLAIM_, MCK_RegList }, }, 11136 { 608 /* ldm */, ARM::LDMIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, }, 11137 { 608 /* ldm */, ARM::t2LDMIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, }, 11138 { 608 /* ldm */, ARM::sysLDMIA, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, }, 11139 { 608 /* ldm */, ARM::t2LDMIA_UPD, Convert__Reg1_2__Tie0_3_3__CondCode2_0__RegList1_4, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, }, 11140 { 608 /* ldm */, ARM::sysLDMIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, }, 11141 { 612 /* ldmda */, ARM::LDMDA, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, }, 11142 { 612 /* ldmda */, ARM::LDMDA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, }, 11143 { 612 /* ldmda */, ARM::sysLDMDA, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, }, 11144 { 612 /* ldmda */, ARM::sysLDMDA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, }, 11145 { 618 /* ldmdb */, ARM::LDMDB, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, }, 11146 { 618 /* ldmdb */, ARM::t2LDMDB, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_RegList }, }, 11147 { 618 /* ldmdb */, ARM::t2LDMDB, Convert__Reg1_2__CondCode2_0__RegList1_3, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_RegList }, }, 11148 { 618 /* ldmdb */, ARM::LDMDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, }, 11149 { 618 /* ldmdb */, ARM::t2LDMDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, }, 11150 { 618 /* ldmdb */, ARM::sysLDMDB, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, }, 11151 { 618 /* ldmdb */, ARM::t2LDMDB_UPD, Convert__Reg1_2__Tie0_3_3__CondCode2_0__RegList1_4, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, }, 11152 { 618 /* ldmdb */, ARM::sysLDMDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, }, 11153 { 624 /* ldmib */, ARM::LDMIB, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, }, 11154 { 624 /* ldmib */, ARM::LDMIB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, }, 11155 { 624 /* ldmib */, ARM::sysLDMIB, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, }, 11156 { 624 /* ldmib */, ARM::sysLDMIB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, }, 11157 { 630 /* ldr */, ARM::tLDRpci, Convert__Reg1_1__ThumbMemPC1_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_ThumbMemPC }, }, 11158 { 630 /* ldr */, ARM::tLDRConstPool, Convert__Reg1_1__ConstPoolAsmImm1_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_ConstPoolAsmImm }, }, 11159 { 630 /* ldr */, ARM::tLDRi, Convert__Reg1_1__MemThumbRIs42_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRIs4 }, }, 11160 { 630 /* ldr */, ARM::tLDRr, Convert__Reg1_1__MemThumbRR2_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRR }, }, 11161 { 630 /* ldr */, ARM::tLDRspi, Convert__Reg1_1__MemThumbSPI2_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbSPI }, }, 11162 { 630 /* ldr */, ARM::t2LDRpci, Convert__Reg1_1__Imm1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_Imm }, }, 11163 { 630 /* ldr */, ARM::LDRi12, Convert__Reg1_1__MemImm12Offset2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemImm12Offset }, }, 11164 { 630 /* ldr */, ARM::t2LDRi8, Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemNegImm8Offset }, }, 11165 { 630 /* ldr */, ARM::LDRrs, Convert__Reg1_1__MemRegOffset3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemRegOffset }, }, 11166 { 630 /* ldr */, ARM::LDRConstPool, Convert__Reg1_1__ConstPoolAsmImm1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_ConstPoolAsmImm }, }, 11167 { 630 /* ldr */, ARM::t2LDRConstPool, Convert__Reg1_1__ConstPoolAsmImm1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_ConstPoolAsmImm }, }, 11168 { 630 /* ldr */, ARM::t2LDRi12, Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemUImm12Offset }, }, 11169 { 630 /* ldr */, ARM::t2LDRs, Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_T2MemRegOffset }, }, 11170 { 630 /* ldr */, ARM::t2LDRpcrel, Convert__Reg1_1__MemPCRelImm121_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemPCRelImm12 }, }, 11171 { 630 /* ldr */, ARM::t2LDRConstPool, Convert__Reg1_2__ConstPoolAsmImm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_ConstPoolAsmImm }, }, 11172 { 630 /* ldr */, ARM::t2LDRpci, Convert__Reg1_2__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_Imm }, }, 11173 { 630 /* ldr */, ARM::t2LDRi12, Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemUImm12Offset }, }, 11174 { 630 /* ldr */, ARM::t2LDRs, Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_T2MemRegOffset }, }, 11175 { 630 /* ldr */, ARM::t2LDRpcrel, Convert__Reg1_2__MemPCRelImm121_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemPCRelImm12 }, }, 11176 { 630 /* ldr */, ARM::LDR_PRE_IMM, Convert__Reg1_1__imm_95_0__MemImm12Offset2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemImm12Offset, MCK__EXCLAIM_ }, }, 11177 { 630 /* ldr */, ARM::t2LDR_PRE, Convert__Reg1_1__imm_95_0__MemImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, }, 11178 { 630 /* ldr */, ARM::LDR_POST_IMM, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM2OffsetImm2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, }, 11179 { 630 /* ldr */, ARM::t2LDR_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_Imm }, }, 11180 { 630 /* ldr */, ARM::LDR_POST_REG, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxRegShifted2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, }, 11181 { 630 /* ldr */, ARM::LDR_PRE_REG, Convert__Reg1_1__imm_95_0__MemRegOffset3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemRegOffset, MCK__EXCLAIM_ }, }, 11182 { 630 /* ldr */, ARM::t2LDR_PRE_imm, Convert__Reg1_2__MemImm8Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, }, 11183 { 630 /* ldr */, ARM::t2LDR_POST_imm, Convert__Reg1_2__MemNoOffset1_3__Imm1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemNoOffset, MCK_Imm }, }, 11184 { 634 /* ldrb */, ARM::tLDRBi, Convert__Reg1_1__MemThumbRIs12_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRIs1 }, }, 11185 { 634 /* ldrb */, ARM::tLDRBr, Convert__Reg1_1__MemThumbRR2_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRR }, }, 11186 { 634 /* ldrb */, ARM::t2LDRBpci, Convert__Reg1_1__Imm1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm }, }, 11187 { 634 /* ldrb */, ARM::t2LDRBi12, Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemUImm12Offset }, }, 11188 { 634 /* ldrb */, ARM::t2LDRBs, Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2MemRegOffset }, }, 11189 { 634 /* ldrb */, ARM::LDRBi12, Convert__Reg1_1__MemImm12Offset2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_MemImm12Offset }, }, 11190 { 634 /* ldrb */, ARM::t2LDRBi8, Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemNegImm8Offset }, }, 11191 { 634 /* ldrb */, ARM::LDRBrs, Convert__Reg1_1__MemRegOffset3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_MemRegOffset }, }, 11192 { 634 /* ldrb */, ARM::t2LDRBpcrel, Convert__Reg1_1__MemPCRelImm121_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemPCRelImm12 }, }, 11193 { 634 /* ldrb */, ARM::t2LDRBpci, Convert__Reg1_2__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_Imm }, }, 11194 { 634 /* ldrb */, ARM::t2LDRBi12, Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_MemUImm12Offset }, }, 11195 { 634 /* ldrb */, ARM::t2LDRBs, Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_T2MemRegOffset }, }, 11196 { 634 /* ldrb */, ARM::t2LDRBpcrel, Convert__Reg1_2__MemPCRelImm121_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_MemPCRelImm12 }, }, 11197 { 634 /* ldrb */, ARM::LDRB_PRE_IMM, Convert__Reg1_1__imm_95_0__MemImm12Offset2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemImm12Offset, MCK__EXCLAIM_ }, }, 11198 { 634 /* ldrb */, ARM::t2LDRB_PRE, Convert__Reg1_1__imm_95_0__MemImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, }, 11199 { 634 /* ldrb */, ARM::LDRB_POST_IMM, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM2OffsetImm2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, }, 11200 { 634 /* ldrb */, ARM::t2LDRB_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_Imm }, }, 11201 { 634 /* ldrb */, ARM::LDRB_POST_REG, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxRegShifted2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, }, 11202 { 634 /* ldrb */, ARM::LDRB_PRE_REG, Convert__Reg1_1__imm_95_0__MemRegOffset3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemRegOffset, MCK__EXCLAIM_ }, }, 11203 { 639 /* ldrbt */, ARM::t2LDRBT, Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemPosImm8Offset }, }, 11204 { 639 /* ldrbt */, ARM::LDRBT_POST, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, }, 11205 { 639 /* ldrbt */, ARM::LDRBT_POST_IMM, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM2OffsetImm2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, }, 11206 { 639 /* ldrbt */, ARM::LDRBT_POST_REG, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxRegShifted2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, }, 11207 { 645 /* ldrd */, ARM::t2LDRDi8, Convert__Reg1_1__Reg1_2__MemImm8s4Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemImm8s4Offset }, }, 11208 { 645 /* ldrd */, ARM::LDRD, Convert__Reg1_1__Reg1_2__AddrMode33_3__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_AddrMode3 }, }, 11209 { 645 /* ldrd */, ARM::t2LDRD_PRE, Convert__Reg1_1__Reg1_2__imm_95_0__MemImm8s4Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemImm8s4Offset, MCK__EXCLAIM_ }, }, 11210 { 645 /* ldrd */, ARM::t2LDRD_POST, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__Tie2_4_4__Imm1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset, MCK_Imm }, }, 11211 { 645 /* ldrd */, ARM::LDRD_PRE, Convert__Reg1_1__Reg1_2__imm_95_0__AddrMode33_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_AddrMode3, MCK__EXCLAIM_ }, }, 11212 { 645 /* ldrd */, ARM::LDRD_POST, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__Tie2_4_4__AM3Offset2_4__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset, MCK_AM3Offset }, }, 11213 { 650 /* ldrex */, ARM::t2LDREX, Convert__Reg1_1__MemImm0_1020s4Offset2_2__CondCode2_0, AMFBS_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_MemImm0_1020s4Offset }, }, 11214 { 650 /* ldrex */, ARM::LDREX, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, }, 11215 { 656 /* ldrexb */, ARM::t2LDREXB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, }, 11216 { 656 /* ldrexb */, ARM::LDREXB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, }, 11217 { 663 /* ldrexd */, ARM::LDREXD, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRPair, MCK_MemNoOffset }, }, 11218 { 663 /* ldrexd */, ARM::t2LDREXD, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, }, 11219 { 670 /* ldrexh */, ARM::t2LDREXH, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, }, 11220 { 670 /* ldrexh */, ARM::LDREXH, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, }, 11221 { 677 /* ldrh */, ARM::tLDRHi, Convert__Reg1_1__MemThumbRIs22_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRIs2 }, }, 11222 { 677 /* ldrh */, ARM::tLDRHr, Convert__Reg1_1__MemThumbRR2_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRR }, }, 11223 { 677 /* ldrh */, ARM::t2LDRHpci, Convert__Reg1_1__Imm1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm }, }, 11224 { 677 /* ldrh */, ARM::t2LDRHi12, Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemUImm12Offset }, }, 11225 { 677 /* ldrh */, ARM::t2LDRHs, Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2MemRegOffset }, }, 11226 { 677 /* ldrh */, ARM::t2LDRHi8, Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemNegImm8Offset }, }, 11227 { 677 /* ldrh */, ARM::t2LDRHpcrel, Convert__Reg1_1__MemPCRelImm121_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemPCRelImm12 }, }, 11228 { 677 /* ldrh */, ARM::LDRH, Convert__Reg1_1__AddrMode33_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3 }, }, 11229 { 677 /* ldrh */, ARM::t2LDRHpci, Convert__Reg1_2__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_Imm }, }, 11230 { 677 /* ldrh */, ARM::t2LDRHi12, Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_MemUImm12Offset }, }, 11231 { 677 /* ldrh */, ARM::t2LDRHs, Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_T2MemRegOffset }, }, 11232 { 677 /* ldrh */, ARM::t2LDRHpcrel, Convert__Reg1_2__MemPCRelImm121_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_MemPCRelImm12 }, }, 11233 { 677 /* ldrh */, ARM::LDRH_PRE, Convert__Reg1_1__imm_95_0__AddrMode33_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3, MCK__EXCLAIM_ }, }, 11234 { 677 /* ldrh */, ARM::t2LDRH_PRE, Convert__Reg1_1__imm_95_0__MemImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, }, 11235 { 677 /* ldrh */, ARM::LDRH_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM3Offset2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM3Offset }, }, 11236 { 677 /* ldrh */, ARM::t2LDRH_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_Imm }, }, 11237 { 682 /* ldrht */, ARM::t2LDRHT, Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemPosImm8Offset }, }, 11238 { 682 /* ldrht */, ARM::LDRHTii, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, }, 11239 { 682 /* ldrht */, ARM::LDRHTr, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxReg2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_MemNoOffset, MCK_PostIdxReg }, }, 11240 { 682 /* ldrht */, ARM::LDRHTi, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxImm81_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxImm8 }, }, 11241 { 688 /* ldrsb */, ARM::tLDRSB, Convert__Reg1_1__MemThumbRR2_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRR }, }, 11242 { 688 /* ldrsb */, ARM::t2LDRSBpci, Convert__Reg1_1__Imm1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm }, }, 11243 { 688 /* ldrsb */, ARM::t2LDRSBi12, Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemUImm12Offset }, }, 11244 { 688 /* ldrsb */, ARM::t2LDRSBs, Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2MemRegOffset }, }, 11245 { 688 /* ldrsb */, ARM::t2LDRSBi8, Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemNegImm8Offset }, }, 11246 { 688 /* ldrsb */, ARM::t2LDRSBpcrel, Convert__Reg1_1__MemPCRelImm121_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemPCRelImm12 }, }, 11247 { 688 /* ldrsb */, ARM::LDRSB, Convert__Reg1_1__AddrMode33_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3 }, }, 11248 { 688 /* ldrsb */, ARM::t2LDRSBpci, Convert__Reg1_2__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_Imm }, }, 11249 { 688 /* ldrsb */, ARM::t2LDRSBi12, Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_MemUImm12Offset }, }, 11250 { 688 /* ldrsb */, ARM::t2LDRSBs, Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_T2MemRegOffset }, }, 11251 { 688 /* ldrsb */, ARM::t2LDRSBpcrel, Convert__Reg1_2__MemPCRelImm121_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_MemPCRelImm12 }, }, 11252 { 688 /* ldrsb */, ARM::LDRSB_PRE, Convert__Reg1_1__imm_95_0__AddrMode33_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3, MCK__EXCLAIM_ }, }, 11253 { 688 /* ldrsb */, ARM::t2LDRSB_PRE, Convert__Reg1_1__imm_95_0__MemImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, }, 11254 { 688 /* ldrsb */, ARM::LDRSB_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM3Offset2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM3Offset }, }, 11255 { 688 /* ldrsb */, ARM::t2LDRSB_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_Imm }, }, 11256 { 694 /* ldrsbt */, ARM::t2LDRSBT, Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemPosImm8Offset }, }, 11257 { 694 /* ldrsbt */, ARM::LDRSBTii, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, }, 11258 { 694 /* ldrsbt */, ARM::LDRSBTr, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxReg2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_MemNoOffset, MCK_PostIdxReg }, }, 11259 { 694 /* ldrsbt */, ARM::LDRSBTi, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxImm81_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxImm8 }, }, 11260 { 701 /* ldrsh */, ARM::tLDRSH, Convert__Reg1_1__MemThumbRR2_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRR }, }, 11261 { 701 /* ldrsh */, ARM::t2LDRSHpci, Convert__Reg1_1__Imm1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm }, }, 11262 { 701 /* ldrsh */, ARM::t2LDRSHi12, Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemUImm12Offset }, }, 11263 { 701 /* ldrsh */, ARM::t2LDRSHs, Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2MemRegOffset }, }, 11264 { 701 /* ldrsh */, ARM::t2LDRSHi8, Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemNegImm8Offset }, }, 11265 { 701 /* ldrsh */, ARM::t2LDRSHpcrel, Convert__Reg1_1__MemPCRelImm121_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemPCRelImm12 }, }, 11266 { 701 /* ldrsh */, ARM::LDRSH, Convert__Reg1_1__AddrMode33_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3 }, }, 11267 { 701 /* ldrsh */, ARM::t2LDRSHpci, Convert__Reg1_2__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_Imm }, }, 11268 { 701 /* ldrsh */, ARM::t2LDRSHi12, Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_MemUImm12Offset }, }, 11269 { 701 /* ldrsh */, ARM::t2LDRSHs, Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_T2MemRegOffset }, }, 11270 { 701 /* ldrsh */, ARM::t2LDRSHpcrel, Convert__Reg1_2__MemPCRelImm121_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_MemPCRelImm12 }, }, 11271 { 701 /* ldrsh */, ARM::LDRSH_PRE, Convert__Reg1_1__imm_95_0__AddrMode33_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3, MCK__EXCLAIM_ }, }, 11272 { 701 /* ldrsh */, ARM::t2LDRSH_PRE, Convert__Reg1_1__imm_95_0__MemImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, }, 11273 { 701 /* ldrsh */, ARM::LDRSH_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM3Offset2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM3Offset }, }, 11274 { 701 /* ldrsh */, ARM::t2LDRSH_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_Imm }, }, 11275 { 707 /* ldrsht */, ARM::t2LDRSHT, Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemPosImm8Offset }, }, 11276 { 707 /* ldrsht */, ARM::LDRSHTii, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, }, 11277 { 707 /* ldrsht */, ARM::LDRSHTr, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxReg2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_MemNoOffset, MCK_PostIdxReg }, }, 11278 { 707 /* ldrsht */, ARM::LDRSHTi, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxImm81_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxImm8 }, }, 11279 { 714 /* ldrt */, ARM::t2LDRT, Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemPosImm8Offset }, }, 11280 { 714 /* ldrt */, ARM::LDRT_POST, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, }, 11281 { 714 /* ldrt */, ARM::LDRT_POST_IMM, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM2OffsetImm2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, }, 11282 { 714 /* ldrt */, ARM::LDRT_POST_REG, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxRegShifted2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, }, 11283 { 719 /* le */, ARM::t2LE, Convert__LELabel1_0, AMFBS_IsThumb2_HasV8_1MMainline_HasLOB, { MCK_LELabel }, }, 11284 { 719 /* le */, ARM::t2LEUpdate, Convert__imm_95_0__Reg1_0__LELabel1_1, AMFBS_IsThumb2_HasV8_1MMainline_HasLOB, { MCK_GPRlr, MCK_LELabel }, }, 11285 { 722 /* letp */, ARM::MVE_LETP, Convert__imm_95_0__Reg1_0__LELabel1_1, AMFBS_HasMVEInt, { MCK_GPRlr, MCK_LELabel }, }, 11286 { 727 /* lsl */, ARM::tLSLrr, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 11287 { 727 /* lsl */, ARM::tLSLri, Convert__Reg1_2__CCOut1_0__Reg1_2__Imm0_311_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_Imm0_31 }, }, 11288 { 727 /* lsl */, ARM::t2LSLrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 11289 { 727 /* lsl */, ARM::t2LSLri, Convert__Reg1_2__Reg1_2__Imm1_311_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_Imm1_31 }, }, 11290 { 727 /* lsl */, ARM::LSLr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, }, 11291 { 727 /* lsl */, ARM::LSLi, Convert__Reg1_2__Reg1_2__Imm0_311_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_Imm0_31 }, }, 11292 { 727 /* lsl */, ARM::t2LSLrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, }, 11293 { 727 /* lsl */, ARM::t2LSLri, Convert__Reg1_3__Reg1_3__Imm1_311_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_Imm1_31 }, }, 11294 { 727 /* lsl */, ARM::tLSLri, Convert__Reg1_2__CCOut1_0__Reg1_3__Imm0_311_4__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_Imm0_31 }, }, 11295 { 727 /* lsl */, ARM::t2LSLrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11296 { 727 /* lsl */, ARM::t2LSLri, Convert__Reg1_2__Reg1_3__Imm1_311_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_Imm1_31 }, }, 11297 { 727 /* lsl */, ARM::t2MOVr, Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK__HASH_0 }, }, 11298 { 727 /* lsl */, ARM::LSLr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11299 { 727 /* lsl */, ARM::LSLi, Convert__Reg1_2__Reg1_3__Imm0_311_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_Imm0_31 }, }, 11300 { 727 /* lsl */, ARM::t2LSLrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11301 { 727 /* lsl */, ARM::t2LSLri, Convert__Reg1_3__Reg1_4__Imm1_311_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_Imm1_31 }, }, 11302 { 727 /* lsl */, ARM::t2MOVr, Convert__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc, MCK__HASH_0 }, }, 11303 { 731 /* lsll */, ARM::MVE_LSLLr, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__Reg1_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_tGPREven, MCK_tGPROdd, MCK_rGPR }, }, 11304 { 731 /* lsll */, ARM::MVE_LSLLi, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__MVELongShift1_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_tGPREven, MCK_tGPROdd, MCK_MVELongShift }, }, 11305 { 736 /* lsr */, ARM::tLSRrr, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 11306 { 736 /* lsr */, ARM::tLSRri, Convert__Reg1_2__CCOut1_0__Reg1_2__ImmThumbSR1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_ImmThumbSR }, }, 11307 { 736 /* lsr */, ARM::t2LSRrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 11308 { 736 /* lsr */, ARM::t2LSRri, Convert__Reg1_2__Reg1_2__ImmThumbSR1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_ImmThumbSR }, }, 11309 { 736 /* lsr */, ARM::LSRr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, }, 11310 { 736 /* lsr */, ARM::LSRi, Convert__Reg1_2__Reg1_2__Imm0_321_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_Imm0_32 }, }, 11311 { 736 /* lsr */, ARM::t2LSRrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, }, 11312 { 736 /* lsr */, ARM::t2LSRri, Convert__Reg1_3__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_ImmThumbSR }, }, 11313 { 736 /* lsr */, ARM::tLSRri, Convert__Reg1_2__CCOut1_0__Reg1_3__ImmThumbSR1_4__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_ImmThumbSR }, }, 11314 { 736 /* lsr */, ARM::t2LSRrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11315 { 736 /* lsr */, ARM::t2LSRri, Convert__Reg1_2__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_ImmThumbSR }, }, 11316 { 736 /* lsr */, ARM::LSRr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11317 { 736 /* lsr */, ARM::LSRi, Convert__Reg1_2__Reg1_3__Imm0_321_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_Imm0_32 }, }, 11318 { 736 /* lsr */, ARM::t2LSRrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11319 { 736 /* lsr */, ARM::t2LSRri, Convert__Reg1_3__Reg1_4__ImmThumbSR1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_ImmThumbSR }, }, 11320 { 740 /* lsrl */, ARM::MVE_LSRL, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__MVELongShift1_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_tGPREven, MCK_tGPROdd, MCK_MVELongShift }, }, 11321 { 745 /* mcr */, ARM::MCR, Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPR, MCK_CoprocReg, MCK_CoprocReg }, }, 11322 { 745 /* mcr */, ARM::t2MCR, Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPR, MCK_CoprocReg, MCK_CoprocReg }, }, 11323 { 745 /* mcr */, ARM::MCR, Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPR, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, }, 11324 { 745 /* mcr */, ARM::t2MCR, Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPR, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, }, 11325 { 749 /* mcr2 */, ARM::MCR2, Convert__CoprocNum1_0__Imm0_71_1__Reg1_2__CoprocReg1_3__CoprocReg1_4__imm_95_0, AMFBS_IsARM, { MCK_CoprocNum, MCK_Imm0_7, MCK_GPR, MCK_CoprocReg, MCK_CoprocReg }, }, 11326 { 749 /* mcr2 */, ARM::t2MCR2, Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPR, MCK_CoprocReg, MCK_CoprocReg }, }, 11327 { 749 /* mcr2 */, ARM::MCR2, Convert__CoprocNum1_0__Imm0_71_1__Reg1_2__CoprocReg1_3__CoprocReg1_4__Imm0_71_5, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_Imm0_7, MCK_GPR, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, }, 11328 { 749 /* mcr2 */, ARM::t2MCR2, Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, AMFBS_IsThumb2_PreV8, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPR, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, }, 11329 { 754 /* mcrr */, ARM::MCRR, Convert__CoprocNum1_1__Imm0_151_2__Reg1_3__Reg1_4__CoprocReg1_5__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_GPRnopc, MCK_GPRnopc, MCK_CoprocReg }, }, 11330 { 754 /* mcrr */, ARM::t2MCRR, Convert__CoprocNum1_1__Imm0_151_2__Reg1_3__Reg1_4__CoprocReg1_5__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_GPR, MCK_GPR, MCK_CoprocReg }, }, 11331 { 759 /* mcrr2 */, ARM::MCRR2, Convert__CoprocNum1_0__Imm0_151_1__Reg1_2__Reg1_3__CoprocReg1_4, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_Imm0_15, MCK_GPRnopc, MCK_GPRnopc, MCK_CoprocReg }, }, 11332 { 759 /* mcrr2 */, ARM::t2MCRR2, Convert__CoprocNum1_1__Imm0_151_2__Reg1_3__Reg1_4__CoprocReg1_5__CondCode2_0, AMFBS_IsThumb2_PreV8, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_GPR, MCK_GPR, MCK_CoprocReg }, }, 11333 { 765 /* mla */, ARM::t2MLA, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11334 { 765 /* mla */, ARM::MLA, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsARM_HasV6, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11335 { 765 /* mla */, ARM::MLA, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11336 { 769 /* mls */, ARM::t2MLS, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11337 { 769 /* mls */, ARM::MLS, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV6T2, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, }, 11338 { 773 /* mov */, ARM::MOVPCLR, Convert__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_PC, MCK_GPRlr }, }, 11339 { 773 /* mov */, ARM::t2MOVi16, Convert__Reg1_1__Imm256_65535Expr1_2__CondCode2_0, AMFBS_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_Imm256_65535Expr }, }, 11340 { 773 /* mov */, ARM::t2MOVsi, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, }, 11341 { 773 /* mov */, ARM::t2MOVsr, Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_RegShiftedReg }, }, 11342 { 773 /* mov */, ARM::t2MOVi, Convert__Reg1_1__T2SOImm1_2__CondCode2_0__reg0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, }, 11343 { 773 /* mov */, ARM::t2MVNi, Convert__Reg1_1__T2SOImmNot1_2__CondCode2_0__reg0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_T2SOImmNot }, }, 11344 { 773 /* mov */, ARM::tMOVr, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_GPR, MCK_GPR }, }, 11345 { 773 /* mov */, ARM::MOVi16, Convert__Reg1_1__Imm0_65535Expr1_2__CondCode2_0, AMFBS_IsARM_HasV6T2, { MCK_CondCode, MCK_GPR, MCK_Imm0_65535Expr }, }, 11346 { 773 /* mov */, ARM::MOVr_TC, Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_tcGPR, MCK_tcGPR }, }, 11347 { 773 /* mov */, ARM::tMOVi8, Convert__Reg1_2__CCOut1_0__Imm0_2551_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_Imm0_255 }, }, 11348 { 773 /* mov */, ARM::MVNi, Convert__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_ModImmNot }, }, 11349 { 773 /* mov */, ARM::MOVsr, Convert__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, }, 11350 { 773 /* mov */, ARM::MOVr, Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, }, 11351 { 773 /* mov */, ARM::MOVi, Convert__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, }, 11352 { 773 /* mov */, ARM::MOVsi, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, }, 11353 { 773 /* mov */, ARM::t2MOVsi, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, }, 11354 { 773 /* mov */, ARM::t2MOVsr, Convert__Reg1_2__RegShiftedReg3_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedReg }, }, 11355 { 773 /* mov */, ARM::t2MOVi, Convert__Reg1_2__T2SOImm1_3__CondCode2_0__reg0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, }, 11356 { 773 /* mov */, ARM::t2MOVr, Convert__Reg1_2__Reg1_3__CondCode2_0__reg0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc }, }, 11357 { 773 /* mov */, ARM::t2MOVi, Convert__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, }, 11358 { 773 /* mov */, ARM::t2MOVr, Convert__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc }, }, 11359 { 777 /* movs */, ARM::tMOVSr, Convert__Reg1_0__Reg1_1, AMFBS_IsThumb, { MCK_tGPR, MCK_tGPR }, }, 11360 { 777 /* movs */, ARM::tMOVi8, Convert__Reg1_0__regCPSR__Imm0_2551_1__imm_95_14__imm_95_0, AMFBS_IsThumb, { MCK_tGPR, MCK_Imm0_255 }, }, 11361 { 777 /* movs */, ARM::t2SUBS_PC_LR, Convert__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_PC, MCK_GPRlr }, }, 11362 { 777 /* movs */, ARM::t2MOVSsi, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, }, 11363 { 777 /* movs */, ARM::t2MOVSsr, Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_RegShiftedReg }, }, 11364 { 777 /* movs */, ARM::t2MOVi, Convert__Reg1_1__T2SOImm1_2__CondCode2_0__regCPSR, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, }, 11365 { 777 /* movs */, ARM::t2MOVr, Convert__Reg1_1__Reg1_2__CondCode2_0__regCPSR, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, }, 11366 { 777 /* movs */, ARM::t2SUBS_PC_LR, Convert__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_PC, MCK_GPRlr }, }, 11367 { 777 /* movs */, ARM::t2MOVSsi, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, }, 11368 { 777 /* movs */, ARM::t2MOVSsr, Convert__Reg1_2__RegShiftedReg3_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedReg }, }, 11369 { 777 /* movs */, ARM::t2MOVi, Convert__Reg1_2__T2SOImm1_3__CondCode2_0__regCPSR, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, }, 11370 { 777 /* movs */, ARM::t2MOVr, Convert__Reg1_2__Reg1_3__CondCode2_0__regCPSR, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc }, }, 11371 { 782 /* movt */, ARM::t2MOVTi16, Convert__Reg1_1__Tie0_1_1__Imm0_65535Expr1_2__CondCode2_0, AMFBS_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_Imm0_65535Expr }, }, 11372 { 782 /* movt */, ARM::MOVTi16, Convert__Reg1_1__Tie0_1_1__Imm0_65535Expr1_2__CondCode2_0, AMFBS_IsARM_HasV6T2, { MCK_CondCode, MCK_GPRnopc, MCK_Imm0_65535Expr }, }, 11373 { 787 /* movw */, ARM::t2MOVi16, Convert__Reg1_1__Imm0_65535Expr1_2__CondCode2_0, AMFBS_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_Imm0_65535Expr }, }, 11374 { 787 /* movw */, ARM::MOVi16, Convert__Reg1_1__Imm0_65535Expr1_2__CondCode2_0, AMFBS_IsARM_HasV6T2, { MCK_CondCode, MCK_GPR, MCK_Imm0_65535Expr }, }, 11375 { 792 /* mrc */, ARM::MRC, Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPRwithAPSR, MCK_CoprocReg, MCK_CoprocReg }, }, 11376 { 792 /* mrc */, ARM::t2MRC, Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPRwithAPSR, MCK_CoprocReg, MCK_CoprocReg }, }, 11377 { 792 /* mrc */, ARM::MRC, Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPRwithAPSR, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, }, 11378 { 792 /* mrc */, ARM::t2MRC, Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPRwithAPSR, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, }, 11379 { 796 /* mrc2 */, ARM::MRC2, Convert__Reg1_2__CoprocNum1_0__Imm0_71_1__CoprocReg1_3__CoprocReg1_4__imm_95_0, AMFBS_IsARM, { MCK_CoprocNum, MCK_Imm0_7, MCK_GPRwithAPSR, MCK_CoprocReg, MCK_CoprocReg }, }, 11380 { 796 /* mrc2 */, ARM::t2MRC2, Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPRwithAPSR, MCK_CoprocReg, MCK_CoprocReg }, }, 11381 { 796 /* mrc2 */, ARM::MRC2, Convert__Reg1_2__CoprocNum1_0__Imm0_71_1__CoprocReg1_3__CoprocReg1_4__Imm0_71_5, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_Imm0_7, MCK_GPRwithAPSR, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, }, 11382 { 796 /* mrc2 */, ARM::t2MRC2, Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, AMFBS_IsThumb2_PreV8, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPRwithAPSR, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, }, 11383 { 801 /* mrrc */, ARM::MRRC, Convert__Reg1_3__Reg1_4__CoprocNum1_1__Imm0_151_2__CoprocReg1_5__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_GPRnopc, MCK_GPRnopc, MCK_CoprocReg }, }, 11384 { 801 /* mrrc */, ARM::t2MRRC, Convert__Reg1_3__Reg1_4__CoprocNum1_1__Imm0_151_2__CoprocReg1_5__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_GPR, MCK_GPR, MCK_CoprocReg }, }, 11385 { 806 /* mrrc2 */, ARM::MRRC2, Convert__Reg1_2__Reg1_3__CoprocNum1_0__Imm0_151_1__CoprocReg1_4, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_Imm0_15, MCK_GPRnopc, MCK_GPRnopc, MCK_CoprocReg }, }, 11386 { 806 /* mrrc2 */, ARM::t2MRRC2, Convert__Reg1_3__Reg1_4__CoprocNum1_1__Imm0_151_2__CoprocReg1_5__CondCode2_0, AMFBS_IsThumb2_PreV8, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_GPR, MCK_GPR, MCK_CoprocReg }, }, 11387 { 812 /* mrs */, ARM::t2MRSbanked, Convert__Reg1_1__BankedReg1_2__CondCode2_0, AMFBS_IsThumb_HasVirtualization, { MCK_CondCode, MCK_rGPR, MCK_BankedReg }, }, 11388 { 812 /* mrs */, ARM::t2MRS_M, Convert__Reg1_1__MSRMask1_2__CondCode2_0, AMFBS_IsThumb_IsMClass, { MCK_CondCode, MCK_rGPR, MCK_MSRMask }, }, 11389 { 812 /* mrs */, ARM::MRS, Convert__Reg1_1__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_APSR }, }, 11390 { 812 /* mrs */, ARM::MRS, Convert__Reg1_1__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_CCR }, }, 11391 { 812 /* mrs */, ARM::MRSsys, Convert__Reg1_1__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_SPSR }, }, 11392 { 812 /* mrs */, ARM::MRSbanked, Convert__Reg1_1__BankedReg1_2__CondCode2_0, AMFBS_IsARM_HasVirtualization, { MCK_CondCode, MCK_GPRnopc, MCK_BankedReg }, }, 11393 { 812 /* mrs */, ARM::t2MRS_AR, Convert__Reg1_1__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPR, MCK_APSR }, }, 11394 { 812 /* mrs */, ARM::t2MRS_AR, Convert__Reg1_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_CCR }, }, 11395 { 812 /* mrs */, ARM::t2MRSsys_AR, Convert__Reg1_1__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPR, MCK_SPSR }, }, 11396 { 816 /* msr */, ARM::t2MSRbanked, Convert__BankedReg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb_HasVirtualization, { MCK_CondCode, MCK_BankedReg, MCK_rGPR }, }, 11397 { 816 /* msr */, ARM::MSRbanked, Convert__BankedReg1_1__Reg1_2__CondCode2_0, AMFBS_IsARM_HasVirtualization, { MCK_CondCode, MCK_BankedReg, MCK_GPRnopc }, }, 11398 { 816 /* msr */, ARM::t2MSR_AR, Convert__MSRMask1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_MSRMask, MCK_rGPR }, }, 11399 { 816 /* msr */, ARM::t2MSR_M, Convert__MSRMask1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb_IsMClass, { MCK_CondCode, MCK_MSRMask, MCK_rGPR }, }, 11400 { 816 /* msr */, ARM::MSR, Convert__MSRMask1_1__Reg1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_MSRMask, MCK_GPR }, }, 11401 { 816 /* msr */, ARM::MSRi, Convert__MSRMask1_1__ModImm1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_MSRMask, MCK_ModImm }, }, 11402 { 820 /* mul */, ARM::t2MUL, Convert__Reg1_1__Reg1_2__Reg1_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 11403 { 820 /* mul */, ARM::tMUL, ConvertCustom_cvtThumbMultiply, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 11404 { 820 /* mul */, ARM::MUL, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM_HasV6, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, }, 11405 { 820 /* mul */, ARM::t2MUL, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11406 { 820 /* mul */, ARM::tMUL, ConvertCustom_cvtThumbMultiply, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_tGPR }, }, 11407 { 820 /* mul */, ARM::MUL, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM_HasV6, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11408 { 820 /* mul */, ARM::MUL, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11409 { 824 /* mvn */, ARM::tMVN, Convert__Reg1_2__CCOut1_0__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 11410 { 824 /* mvn */, ARM::t2MVNr, Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 11411 { 824 /* mvn */, ARM::MOVi, Convert__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_ModImmNot }, }, 11412 { 824 /* mvn */, ARM::t2MVNs, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, }, 11413 { 824 /* mvn */, ARM::t2MVNi, Convert__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, }, 11414 { 824 /* mvn */, ARM::t2MOVi, Convert__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImmNot }, }, 11415 { 824 /* mvn */, ARM::MVNsr, Convert__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, }, 11416 { 824 /* mvn */, ARM::MVNr, Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, }, 11417 { 824 /* mvn */, ARM::MVNi, Convert__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, }, 11418 { 824 /* mvn */, ARM::MVNsi, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, }, 11419 { 824 /* mvn */, ARM::t2MVNr, Convert__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, }, 11420 { 824 /* mvn */, ARM::t2MVNs, Convert__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, }, 11421 { 824 /* mvn */, ARM::t2MVNi, Convert__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, }, 11422 { 828 /* neg */, ARM::tRSB, Convert__Reg1_2__CCOut1_0__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 11423 { 828 /* neg */, ARM::t2RSBri, Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 11424 { 828 /* neg */, ARM::RSBri, Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, }, 11425 { 832 /* nop */, ARM::tMOVr, Convert__regR8__regR8__imm_95_14__imm_95_0, AMFBS_IsThumb, { }, }, 11426 { 832 /* nop */, ARM::HINT, Convert__imm_95_0__CondCode2_0, AMFBS_IsARM_HasV6K, { MCK_CondCode }, }, 11427 { 832 /* nop */, ARM::tHINT, Convert__imm_95_0__CondCode2_0, AMFBS_IsThumb_HasV6M, { MCK_CondCode }, }, 11428 { 832 /* nop */, ARM::MOVr, Convert__regR0__regR0__CondCode2_0__reg0, AMFBS_IsARM, { MCK_CondCode }, }, 11429 { 832 /* nop */, ARM::t2HINT, Convert__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w }, }, 11430 { 836 /* orn */, ARM::t2ORNrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 11431 { 836 /* orn */, ARM::t2ORNrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, }, 11432 { 836 /* orn */, ARM::t2ORNri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, }, 11433 { 836 /* orn */, ARM::t2ORRri, Convert__Reg1_2__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImmNot }, }, 11434 { 836 /* orn */, ARM::t2ORNrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11435 { 836 /* orn */, ARM::t2ORNrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, }, 11436 { 836 /* orn */, ARM::t2ORNri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, }, 11437 { 836 /* orn */, ARM::t2ORRri, Convert__Reg1_2__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImmNot }, }, 11438 { 836 /* orn */, ARM::t2ORNrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11439 { 836 /* orn */, ARM::t2ORNrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, }, 11440 { 836 /* orn */, ARM::t2ORNri, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, }, 11441 { 840 /* orr */, ARM::tORR, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 11442 { 840 /* orr */, ARM::t2ORRrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 11443 { 840 /* orr */, ARM::t2ORRrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, }, 11444 { 840 /* orr */, ARM::t2ORRri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, }, 11445 { 840 /* orr */, ARM::t2ORNri, Convert__Reg1_2__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImmNot }, }, 11446 { 840 /* orr */, ARM::ORRrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, }, 11447 { 840 /* orr */, ARM::ORRri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, }, 11448 { 840 /* orr */, ARM::ORRrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, }, 11449 { 840 /* orr */, ARM::ORRrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, }, 11450 { 840 /* orr */, ARM::t2ORRrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, }, 11451 { 840 /* orr */, ARM::t2ORRrs, Convert__Reg1_3__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, }, 11452 { 840 /* orr */, ARM::t2ORRri, Convert__Reg1_3__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, }, 11453 { 840 /* orr */, ARM::t2ORRrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11454 { 840 /* orr */, ARM::t2ORRrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, }, 11455 { 840 /* orr */, ARM::t2ORRri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, }, 11456 { 840 /* orr */, ARM::t2ORNri, Convert__Reg1_2__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImmNot }, }, 11457 { 840 /* orr */, ARM::ORRrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 11458 { 840 /* orr */, ARM::ORRri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, }, 11459 { 840 /* orr */, ARM::ORRrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, }, 11460 { 840 /* orr */, ARM::ORRrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, }, 11461 { 840 /* orr */, ARM::t2ORRrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11462 { 840 /* orr */, ARM::t2ORRrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, }, 11463 { 840 /* orr */, ARM::t2ORRri, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, }, 11464 { 844 /* pac */, ARM::t2PAC, Convert_NoOperands, AMFBS_HasV7_IsMClass, { MCK_R12, MCK_GPRlr, MCK_GPRsp }, }, 11465 { 844 /* pac */, ARM::t2HINT, Convert__imm_95_29__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_R12, MCK_GPRlr, MCK_GPRsp }, }, 11466 { 848 /* pacbti */, ARM::t2PACBTI, Convert_NoOperands, AMFBS_HasV7_IsMClass, { MCK_R12, MCK_GPRlr, MCK_GPRsp }, }, 11467 { 848 /* pacbti */, ARM::t2HINT, Convert__imm_95_13__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_R12, MCK_GPRlr, MCK_GPRsp }, }, 11468 { 855 /* pacg */, ARM::t2PACG, Convert__Reg1_1__CondCode2_0__Reg1_2__Reg1_3, AMFBS_IsThumb2_HasV8_1MMainline_HasPACBTI, { MCK_CondCode, MCK_rGPR, MCK_GPRnopc, MCK_GPRnopc }, }, 11469 { 860 /* pkhbt */, ARM::t2PKHBT, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11470 { 860 /* pkhbt */, ARM::PKHBT, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11471 { 860 /* pkhbt */, ARM::t2PKHBT, Convert__Reg1_1__Reg1_2__Reg1_3__PKHLSLImm1_4__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_PKHLSLImm }, }, 11472 { 860 /* pkhbt */, ARM::PKHBT, Convert__Reg1_1__Reg1_2__Reg1_3__PKHLSLImm1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_PKHLSLImm }, }, 11473 { 866 /* pkhtb */, ARM::t2PKHBT, Convert__Reg1_1__Reg1_3__Reg1_2__imm_95_0__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11474 { 866 /* pkhtb */, ARM::PKHBT, Convert__Reg1_1__Reg1_3__Reg1_2__imm_95_0__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11475 { 866 /* pkhtb */, ARM::t2PKHTB, Convert__Reg1_1__Reg1_2__Reg1_3__PKHASRImm1_4__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_PKHASRImm }, }, 11476 { 866 /* pkhtb */, ARM::PKHTB, Convert__Reg1_1__Reg1_2__Reg1_3__PKHASRImm1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_PKHASRImm }, }, 11477 { 872 /* pld */, ARM::PLDi12, Convert__MemImm12Offset2_0, AMFBS_IsARM, { MCK_MemImm12Offset }, }, 11478 { 872 /* pld */, ARM::PLDrs, Convert__MemRegOffset3_0, AMFBS_IsARM, { MCK_MemRegOffset }, }, 11479 { 872 /* pld */, ARM::t2PLDpci, Convert__Imm1_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_Imm }, }, 11480 { 872 /* pld */, ARM::t2PLDi8, Convert__MemNegImm8Offset2_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_MemNegImm8Offset }, }, 11481 { 872 /* pld */, ARM::t2PLDi12, Convert__MemUImm12Offset2_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_MemUImm12Offset }, }, 11482 { 872 /* pld */, ARM::t2PLDs, Convert__T2MemRegOffset3_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_T2MemRegOffset }, }, 11483 { 872 /* pld */, ARM::t2PLDpci, Convert__MemPCRelImm121_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_MemPCRelImm12 }, }, 11484 { 872 /* pld */, ARM::t2PLDpci, Convert__Imm1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_Imm }, }, 11485 { 872 /* pld */, ARM::t2PLDi8, Convert__MemNegImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_MemNegImm8Offset }, }, 11486 { 872 /* pld */, ARM::t2PLDi12, Convert__MemUImm12Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_MemUImm12Offset }, }, 11487 { 872 /* pld */, ARM::t2PLDs, Convert__T2MemRegOffset3_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_T2MemRegOffset }, }, 11488 { 872 /* pld */, ARM::t2PLDpci, Convert__MemPCRelImm121_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_MemPCRelImm12 }, }, 11489 { 876 /* pldw */, ARM::PLDWi12, Convert__MemImm12Offset2_0, AMFBS_IsARM_HasV7_HasMP, { MCK_MemImm12Offset }, }, 11490 { 876 /* pldw */, ARM::PLDWrs, Convert__MemRegOffset3_0, AMFBS_IsARM_HasV7_HasMP, { MCK_MemRegOffset }, }, 11491 { 876 /* pldw */, ARM::t2PLDWi8, Convert__MemNegImm8Offset2_1__CondCode2_0, AMFBS_IsThumb2_HasV7_HasMP, { MCK_CondCode, MCK_MemNegImm8Offset }, }, 11492 { 876 /* pldw */, ARM::t2PLDWi12, Convert__MemUImm12Offset2_1__CondCode2_0, AMFBS_IsThumb2_HasV7_HasMP, { MCK_CondCode, MCK_MemUImm12Offset }, }, 11493 { 876 /* pldw */, ARM::t2PLDWs, Convert__T2MemRegOffset3_1__CondCode2_0, AMFBS_IsThumb2_HasV7_HasMP, { MCK_CondCode, MCK_T2MemRegOffset }, }, 11494 { 876 /* pldw */, ARM::t2PLDWi8, Convert__MemNegImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2_HasV7_HasMP, { MCK_CondCode, MCK__DOT_w, MCK_MemNegImm8Offset }, }, 11495 { 876 /* pldw */, ARM::t2PLDWi12, Convert__MemUImm12Offset2_2__CondCode2_0, AMFBS_IsThumb2_HasV7_HasMP, { MCK_CondCode, MCK__DOT_w, MCK_MemUImm12Offset }, }, 11496 { 876 /* pldw */, ARM::t2PLDWs, Convert__T2MemRegOffset3_2__CondCode2_0, AMFBS_IsThumb2_HasV7_HasMP, { MCK_CondCode, MCK__DOT_w, MCK_T2MemRegOffset }, }, 11497 { 881 /* pli */, ARM::PLIi12, Convert__MemImm12Offset2_0, AMFBS_IsARM_HasV7, { MCK_MemImm12Offset }, }, 11498 { 881 /* pli */, ARM::PLIrs, Convert__MemRegOffset3_0, AMFBS_IsARM_HasV7, { MCK_MemRegOffset }, }, 11499 { 881 /* pli */, ARM::t2PLIpci, Convert__Imm1_1__CondCode2_0, AMFBS_IsThumb2_HasV7, { MCK_CondCode, MCK_Imm }, }, 11500 { 881 /* pli */, ARM::t2PLIi8, Convert__MemNegImm8Offset2_1__CondCode2_0, AMFBS_IsThumb2_HasV7, { MCK_CondCode, MCK_MemNegImm8Offset }, }, 11501 { 881 /* pli */, ARM::t2PLIi12, Convert__MemUImm12Offset2_1__CondCode2_0, AMFBS_IsThumb2_HasV7, { MCK_CondCode, MCK_MemUImm12Offset }, }, 11502 { 881 /* pli */, ARM::t2PLIs, Convert__T2MemRegOffset3_1__CondCode2_0, AMFBS_IsThumb2_HasV7, { MCK_CondCode, MCK_T2MemRegOffset }, }, 11503 { 881 /* pli */, ARM::t2PLIpci, Convert__MemPCRelImm121_1__CondCode2_0, AMFBS_IsThumb2_HasV7, { MCK_CondCode, MCK_MemPCRelImm12 }, }, 11504 { 881 /* pli */, ARM::t2PLIpci, Convert__Imm1_2__CondCode2_0, AMFBS_IsThumb2_HasV7, { MCK_CondCode, MCK__DOT_w, MCK_Imm }, }, 11505 { 881 /* pli */, ARM::t2PLIi8, Convert__MemNegImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2_HasV7, { MCK_CondCode, MCK__DOT_w, MCK_MemNegImm8Offset }, }, 11506 { 881 /* pli */, ARM::t2PLIi12, Convert__MemUImm12Offset2_2__CondCode2_0, AMFBS_IsThumb2_HasV7, { MCK_CondCode, MCK__DOT_w, MCK_MemUImm12Offset }, }, 11507 { 881 /* pli */, ARM::t2PLIs, Convert__T2MemRegOffset3_2__CondCode2_0, AMFBS_IsThumb2_HasV7, { MCK_CondCode, MCK__DOT_w, MCK_T2MemRegOffset }, }, 11508 { 881 /* pli */, ARM::t2PLIpci, Convert__MemPCRelImm121_2__CondCode2_0, AMFBS_IsThumb2_HasV7, { MCK_CondCode, MCK__DOT_w, MCK_MemPCRelImm12 }, }, 11509 { 885 /* pop */, ARM::tPOP, Convert__CondCode2_0__RegList1_1, AMFBS_IsThumb, { MCK_CondCode, MCK_RegList }, }, 11510 { 885 /* pop */, ARM::t2LDMIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_1, AMFBS_IsThumb2, { MCK_CondCode, MCK_RegList }, }, 11511 { 885 /* pop */, ARM::LDMIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_1, AMFBS_IsARM, { MCK_CondCode, MCK_RegList }, }, 11512 { 885 /* pop */, ARM::t2LDMIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_2, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_RegList }, }, 11513 { 889 /* pssbb */, ARM::t2DSB, Convert__imm_95_4__imm_95_14__imm_95_0, AMFBS_HasDB_IsThumb2, { }, }, 11514 { 889 /* pssbb */, ARM::DSB, Convert__imm_95_4, AMFBS_IsARM_HasDB, { }, }, 11515 { 895 /* push */, ARM::tPUSH, Convert__CondCode2_0__RegList1_1, AMFBS_IsThumb, { MCK_CondCode, MCK_RegList }, }, 11516 { 895 /* push */, ARM::t2STMDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_1, AMFBS_IsThumb2, { MCK_CondCode, MCK_RegList }, }, 11517 { 895 /* push */, ARM::STMDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_1, AMFBS_IsARM, { MCK_CondCode, MCK_RegList }, }, 11518 { 895 /* push */, ARM::t2STMDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_2, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_RegList }, }, 11519 { 900 /* qadd */, ARM::t2QADD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11520 { 900 /* qadd */, ARM::QADD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11521 { 905 /* qadd16 */, ARM::t2QADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11522 { 905 /* qadd16 */, ARM::QADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11523 { 912 /* qadd8 */, ARM::t2QADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11524 { 912 /* qadd8 */, ARM::QADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11525 { 918 /* qasx */, ARM::t2QASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11526 { 918 /* qasx */, ARM::QASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11527 { 923 /* qdadd */, ARM::t2QDADD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11528 { 923 /* qdadd */, ARM::QDADD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11529 { 929 /* qdsub */, ARM::t2QDSUB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11530 { 929 /* qdsub */, ARM::QDSUB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11531 { 935 /* qsax */, ARM::t2QSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11532 { 935 /* qsax */, ARM::QSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11533 { 940 /* qsub */, ARM::t2QSUB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11534 { 940 /* qsub */, ARM::QSUB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11535 { 945 /* qsub16 */, ARM::t2QSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11536 { 945 /* qsub16 */, ARM::QSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11537 { 952 /* qsub8 */, ARM::t2QSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11538 { 952 /* qsub8 */, ARM::QSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11539 { 958 /* rbit */, ARM::t2RBIT, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 11540 { 958 /* rbit */, ARM::RBIT, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsARM_HasV6T2, { MCK_CondCode, MCK_GPR, MCK_GPR }, }, 11541 { 963 /* rev */, ARM::tREV, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb_HasV6, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 11542 { 963 /* rev */, ARM::t2REV, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 11543 { 963 /* rev */, ARM::REV, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR }, }, 11544 { 963 /* rev */, ARM::t2REV, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, }, 11545 { 967 /* rev16 */, ARM::tREV16, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb_HasV6, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 11546 { 967 /* rev16 */, ARM::t2REV16, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 11547 { 967 /* rev16 */, ARM::REV16, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR }, }, 11548 { 967 /* rev16 */, ARM::t2REV16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, }, 11549 { 973 /* revsh */, ARM::tREVSH, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb_HasV6, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 11550 { 973 /* revsh */, ARM::t2REVSH, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 11551 { 973 /* revsh */, ARM::REVSH, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR }, }, 11552 { 973 /* revsh */, ARM::t2REVSH, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, }, 11553 { 979 /* rfeda */, ARM::RFEDA, Convert__Reg1_0, AMFBS_IsARM, { MCK_GPR }, }, 11554 { 979 /* rfeda */, ARM::RFEDA_UPD, Convert__Reg1_0, AMFBS_IsARM, { MCK_GPR, MCK__EXCLAIM_ }, }, 11555 { 985 /* rfedb */, ARM::RFEDB, Convert__Reg1_0, AMFBS_IsARM, { MCK_GPR }, }, 11556 { 985 /* rfedb */, ARM::RFEDB_UPD, Convert__Reg1_0, AMFBS_IsARM, { MCK_GPR, MCK__EXCLAIM_ }, }, 11557 { 985 /* rfedb */, ARM::t2RFEDB, Convert__Reg1_1__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPR }, }, 11558 { 985 /* rfedb */, ARM::t2RFEDBW, Convert__Reg1_1__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_ }, }, 11559 { 991 /* rfeia */, ARM::RFEIA, Convert__Reg1_0, AMFBS_IsARM, { MCK_GPR }, }, 11560 { 991 /* rfeia */, ARM::RFEIA_UPD, Convert__Reg1_0, AMFBS_IsARM, { MCK_GPR, MCK__EXCLAIM_ }, }, 11561 { 991 /* rfeia */, ARM::t2RFEIA, Convert__Reg1_1__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPR }, }, 11562 { 991 /* rfeia */, ARM::t2RFEIAW, Convert__Reg1_1__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_ }, }, 11563 { 997 /* rfeib */, ARM::RFEIB, Convert__Reg1_0, AMFBS_IsARM, { MCK_GPR }, }, 11564 { 997 /* rfeib */, ARM::RFEIB_UPD, Convert__Reg1_0, AMFBS_IsARM, { MCK_GPR, MCK__EXCLAIM_ }, }, 11565 { 1003 /* ror */, ARM::tROR, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 11566 { 1003 /* ror */, ARM::t2RORrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 11567 { 1003 /* ror */, ARM::t2RORri, Convert__Reg1_2__Reg1_2__Imm1_311_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_Imm1_31 }, }, 11568 { 1003 /* ror */, ARM::RORr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, }, 11569 { 1003 /* ror */, ARM::RORi, Convert__Reg1_2__Reg1_2__Imm0_311_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_Imm0_31 }, }, 11570 { 1003 /* ror */, ARM::t2RORrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, }, 11571 { 1003 /* ror */, ARM::t2RORri, Convert__Reg1_3__Reg1_3__Imm1_311_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_Imm1_31 }, }, 11572 { 1003 /* ror */, ARM::t2RORrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11573 { 1003 /* ror */, ARM::t2RORri, Convert__Reg1_2__Reg1_3__Imm1_311_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_Imm1_31 }, }, 11574 { 1003 /* ror */, ARM::RORr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11575 { 1003 /* ror */, ARM::RORi, Convert__Reg1_2__Reg1_3__Imm0_311_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_Imm0_31 }, }, 11576 { 1003 /* ror */, ARM::t2RORrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11577 { 1003 /* ror */, ARM::t2RORri, Convert__Reg1_3__Reg1_4__Imm1_311_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_Imm1_31 }, }, 11578 { 1007 /* rrx */, ARM::t2RRX, Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 11579 { 1007 /* rrx */, ARM::RRXi, Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, }, 11580 { 1011 /* rsb */, ARM::t2RSBrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 11581 { 1011 /* rsb */, ARM::t2RSBrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, }, 11582 { 1011 /* rsb */, ARM::t2RSBri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, }, 11583 { 1011 /* rsb */, ARM::RSBrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, }, 11584 { 1011 /* rsb */, ARM::RSBri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, }, 11585 { 1011 /* rsb */, ARM::RSBrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, }, 11586 { 1011 /* rsb */, ARM::RSBrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, }, 11587 { 1011 /* rsb */, ARM::t2RSBrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, }, 11588 { 1011 /* rsb */, ARM::tRSB, Convert__Reg1_2__CCOut1_0__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK__HASH_0 }, }, 11589 { 1011 /* rsb */, ARM::t2RSBrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11590 { 1011 /* rsb */, ARM::t2RSBrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, }, 11591 { 1011 /* rsb */, ARM::t2RSBri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, }, 11592 { 1011 /* rsb */, ARM::RSBrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 11593 { 1011 /* rsb */, ARM::RSBri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, }, 11594 { 1011 /* rsb */, ARM::RSBrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, }, 11595 { 1011 /* rsb */, ARM::RSBrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, }, 11596 { 1011 /* rsb */, ARM::t2RSBrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11597 { 1011 /* rsb */, ARM::t2RSBrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, }, 11598 { 1011 /* rsb */, ARM::t2RSBri, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, }, 11599 { 1015 /* rsc */, ARM::RSCrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, }, 11600 { 1015 /* rsc */, ARM::RSCri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, }, 11601 { 1015 /* rsc */, ARM::RSCrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, }, 11602 { 1015 /* rsc */, ARM::RSCrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, }, 11603 { 1015 /* rsc */, ARM::RSCrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 11604 { 1015 /* rsc */, ARM::RSCri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, }, 11605 { 1015 /* rsc */, ARM::RSCrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, }, 11606 { 1015 /* rsc */, ARM::RSCrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, }, 11607 { 1019 /* sadd16 */, ARM::t2SADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11608 { 1019 /* sadd16 */, ARM::SADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11609 { 1026 /* sadd8 */, ARM::t2SADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11610 { 1026 /* sadd8 */, ARM::SADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11611 { 1032 /* sasx */, ARM::t2SASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11612 { 1032 /* sasx */, ARM::SASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11613 { 1037 /* sb */, ARM::SB, Convert_NoOperands, AMFBS_IsARM_HasSB, { }, }, 11614 { 1037 /* sb */, ARM::t2SB, Convert_NoOperands, AMFBS_IsThumb2_HasSB, { }, }, 11615 { 1040 /* sbc */, ARM::tSBC, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 11616 { 1040 /* sbc */, ARM::SBCrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, }, 11617 { 1040 /* sbc */, ARM::SBCrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, }, 11618 { 1040 /* sbc */, ARM::SBCri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, }, 11619 { 1040 /* sbc */, ARM::ADCri, Convert__Reg1_2__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImmNot }, }, 11620 { 1040 /* sbc */, ARM::SBCrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, }, 11621 { 1040 /* sbc */, ARM::t2SBCrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11622 { 1040 /* sbc */, ARM::t2SBCrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, }, 11623 { 1040 /* sbc */, ARM::t2SBCri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, }, 11624 { 1040 /* sbc */, ARM::t2ADCri, Convert__Reg1_2__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImmNot }, }, 11625 { 1040 /* sbc */, ARM::SBCrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RegShiftedReg }, }, 11626 { 1040 /* sbc */, ARM::SBCrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 11627 { 1040 /* sbc */, ARM::SBCri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, }, 11628 { 1040 /* sbc */, ARM::ADCri, Convert__Reg1_2__Reg1_3__ModImmNot1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImmNot }, }, 11629 { 1040 /* sbc */, ARM::SBCrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, }, 11630 { 1040 /* sbc */, ARM::t2SBCrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11631 { 1040 /* sbc */, ARM::t2SBCrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, }, 11632 { 1044 /* sbfx */, ARM::t2SBFX, Convert__Reg1_1__Reg1_2__Imm0_311_3__Imm1_321_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_Imm0_31, MCK_Imm1_32 }, }, 11633 { 1044 /* sbfx */, ARM::SBFX, Convert__Reg1_1__Reg1_2__Imm0_311_3__Imm1_321_4__CondCode2_0, AMFBS_IsARM_HasV6T2, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_Imm0_31, MCK_Imm1_32 }, }, 11634 { 1049 /* sdiv */, ARM::t2SDIV, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasDivideInThumb_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11635 { 1049 /* sdiv */, ARM::SDIV, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasDivideInARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 11636 { 1054 /* sel */, ARM::SEL, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 11637 { 1054 /* sel */, ARM::t2SEL, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 11638 { 1058 /* setend */, ARM::tSETEND, Convert__SetEndImm1_0, AMFBS_IsThumb_IsNotMClass, { MCK_SetEndImm }, }, 11639 { 1058 /* setend */, ARM::SETEND, Convert__SetEndImm1_0, AMFBS_IsARM, { MCK_SetEndImm }, }, 11640 { 1065 /* setpan */, ARM::SETPAN, Convert__Imm0_11_0, AMFBS_IsARM_HasV8_HasV8_1a, { MCK_Imm0_1 }, }, 11641 { 1065 /* setpan */, ARM::t2SETPAN, Convert__Imm0_11_0, AMFBS_IsThumb2_HasV8_HasV8_1a, { MCK_Imm0_1 }, }, 11642 { 1072 /* sev */, ARM::HINT, Convert__imm_95_4__CondCode2_0, AMFBS_IsARM_HasV6K, { MCK_CondCode }, }, 11643 { 1072 /* sev */, ARM::tHINT, Convert__imm_95_4__CondCode2_0, AMFBS_IsThumb_HasV6M, { MCK_CondCode }, }, 11644 { 1072 /* sev */, ARM::t2HINT, Convert__imm_95_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w }, }, 11645 { 1076 /* sevl */, ARM::HINT, Convert__imm_95_5__CondCode2_0, AMFBS_IsARM_HasV8, { MCK_CondCode }, }, 11646 { 1076 /* sevl */, ARM::tHINT, Convert__imm_95_5__CondCode2_0, AMFBS_IsThumb2_HasV8, { MCK_CondCode }, }, 11647 { 1076 /* sevl */, ARM::t2HINT, Convert__imm_95_5__CondCode2_0, AMFBS_IsThumb2_HasV8, { MCK_CondCode, MCK__DOT_w }, }, 11648 { 1081 /* sg */, ARM::t2SG, Convert__CondCode2_0, AMFBS_Has8MSecExt, { MCK_CondCode }, }, 11649 { 1084 /* sha1c */, ARM::SHA1C, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3, AMFBS_HasV8_HasSHA2, { MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11650 { 1090 /* sha1h */, ARM::SHA1H, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasSHA2, { MCK__DOT_32, MCK_QPR, MCK_QPR }, }, 11651 { 1096 /* sha1m */, ARM::SHA1M, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3, AMFBS_HasV8_HasSHA2, { MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11652 { 1102 /* sha1p */, ARM::SHA1P, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3, AMFBS_HasV8_HasSHA2, { MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11653 { 1108 /* sha1su0 */, ARM::SHA1SU0, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3, AMFBS_HasV8_HasSHA2, { MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11654 { 1116 /* sha1su1 */, ARM::SHA1SU1, Convert__Reg1_1__Tie0_1_1__Reg1_2, AMFBS_HasV8_HasSHA2, { MCK__DOT_32, MCK_QPR, MCK_QPR }, }, 11655 { 1124 /* sha256h */, ARM::SHA256H, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3, AMFBS_HasV8_HasSHA2, { MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11656 { 1132 /* sha256h2 */, ARM::SHA256H2, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3, AMFBS_HasV8_HasSHA2, { MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11657 { 1141 /* sha256su0 */, ARM::SHA256SU0, Convert__Reg1_1__Tie0_1_1__Reg1_2, AMFBS_HasV8_HasSHA2, { MCK__DOT_32, MCK_QPR, MCK_QPR }, }, 11658 { 1151 /* sha256su1 */, ARM::SHA256SU1, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3, AMFBS_HasV8_HasSHA2, { MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11659 { 1161 /* shadd16 */, ARM::t2SHADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11660 { 1161 /* shadd16 */, ARM::SHADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11661 { 1169 /* shadd8 */, ARM::t2SHADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11662 { 1169 /* shadd8 */, ARM::SHADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11663 { 1176 /* shasx */, ARM::t2SHASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11664 { 1176 /* shasx */, ARM::SHASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11665 { 1182 /* shsax */, ARM::t2SHSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11666 { 1182 /* shsax */, ARM::SHSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11667 { 1188 /* shsub16 */, ARM::t2SHSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11668 { 1188 /* shsub16 */, ARM::SHSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11669 { 1196 /* shsub8 */, ARM::t2SHSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11670 { 1196 /* shsub8 */, ARM::SHSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11671 { 1203 /* smc */, ARM::SMC, Convert__Imm0_151_1__CondCode2_0, AMFBS_IsARM_HasTrustZone, { MCK_CondCode, MCK_Imm0_15 }, }, 11672 { 1203 /* smc */, ARM::t2SMC, Convert__Imm0_151_1__CondCode2_0, AMFBS_IsThumb2_HasTrustZone, { MCK_CondCode, MCK_Imm0_15 }, }, 11673 { 1207 /* smlabb */, ARM::t2SMLABB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11674 { 1207 /* smlabb */, ARM::SMLABB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, }, 11675 { 1214 /* smlabt */, ARM::t2SMLABT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11676 { 1214 /* smlabt */, ARM::SMLABT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, }, 11677 { 1221 /* smlad */, ARM::t2SMLAD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11678 { 1221 /* smlad */, ARM::SMLAD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, }, 11679 { 1227 /* smladx */, ARM::t2SMLADX, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11680 { 1227 /* smladx */, ARM::SMLADX, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, }, 11681 { 1234 /* smlal */, ARM::t2SMLAL, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11682 { 1234 /* smlal */, ARM::SMLAL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0_1_1__Tie1_1_1__CondCode2_1__CCOut1_0, AMFBS_IsARM_HasV6, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, }, 11683 { 1234 /* smlal */, ARM::SMLAL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0_3_3__Tie1_4_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, }, 11684 { 1240 /* smlalbb */, ARM::t2SMLALBB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11685 { 1240 /* smlalbb */, ARM::SMLALBB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11686 { 1248 /* smlalbt */, ARM::t2SMLALBT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11687 { 1248 /* smlalbt */, ARM::SMLALBT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11688 { 1256 /* smlald */, ARM::t2SMLALD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11689 { 1256 /* smlald */, ARM::SMLALD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11690 { 1263 /* smlaldx */, ARM::t2SMLALDX, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11691 { 1263 /* smlaldx */, ARM::SMLALDX, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11692 { 1271 /* smlaltb */, ARM::t2SMLALTB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11693 { 1271 /* smlaltb */, ARM::SMLALTB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11694 { 1279 /* smlaltt */, ARM::t2SMLALTT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11695 { 1279 /* smlaltt */, ARM::SMLALTT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11696 { 1287 /* smlatb */, ARM::t2SMLATB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11697 { 1287 /* smlatb */, ARM::SMLATB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, }, 11698 { 1294 /* smlatt */, ARM::t2SMLATT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11699 { 1294 /* smlatt */, ARM::SMLATT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, }, 11700 { 1301 /* smlawb */, ARM::t2SMLAWB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11701 { 1301 /* smlawb */, ARM::SMLAWB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, }, 11702 { 1308 /* smlawt */, ARM::t2SMLAWT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11703 { 1308 /* smlawt */, ARM::SMLAWT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, }, 11704 { 1315 /* smlsd */, ARM::t2SMLSD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11705 { 1315 /* smlsd */, ARM::SMLSD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, }, 11706 { 1321 /* smlsdx */, ARM::t2SMLSDX, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11707 { 1321 /* smlsdx */, ARM::SMLSDX, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, }, 11708 { 1328 /* smlsld */, ARM::t2SMLSLD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11709 { 1328 /* smlsld */, ARM::SMLSLD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11710 { 1335 /* smlsldx */, ARM::t2SMLSLDX, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11711 { 1335 /* smlsldx */, ARM::SMLSLDX, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11712 { 1343 /* smmla */, ARM::t2SMMLA, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11713 { 1343 /* smmla */, ARM::SMMLA, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, }, 11714 { 1349 /* smmlar */, ARM::t2SMMLAR, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11715 { 1349 /* smmlar */, ARM::SMMLAR, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, }, 11716 { 1356 /* smmls */, ARM::t2SMMLS, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11717 { 1356 /* smmls */, ARM::SMMLS, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, }, 11718 { 1362 /* smmlsr */, ARM::t2SMMLSR, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11719 { 1362 /* smmlsr */, ARM::SMMLSR, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, }, 11720 { 1369 /* smmul */, ARM::t2SMMUL, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11721 { 1369 /* smmul */, ARM::SMMUL, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 11722 { 1375 /* smmulr */, ARM::t2SMMULR, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11723 { 1375 /* smmulr */, ARM::SMMULR, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 11724 { 1382 /* smuad */, ARM::t2SMUAD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11725 { 1382 /* smuad */, ARM::SMUAD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11726 { 1388 /* smuadx */, ARM::t2SMUADX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11727 { 1388 /* smuadx */, ARM::SMUADX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11728 { 1395 /* smulbb */, ARM::t2SMULBB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11729 { 1395 /* smulbb */, ARM::SMULBB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 11730 { 1402 /* smulbt */, ARM::t2SMULBT, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11731 { 1402 /* smulbt */, ARM::SMULBT, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 11732 { 1409 /* smull */, ARM::t2SMULL, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11733 { 1409 /* smull */, ARM::SMULL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsARM_HasV6, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, }, 11734 { 1409 /* smull */, ARM::SMULL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, }, 11735 { 1415 /* smultb */, ARM::t2SMULTB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11736 { 1415 /* smultb */, ARM::SMULTB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 11737 { 1422 /* smultt */, ARM::t2SMULTT, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11738 { 1422 /* smultt */, ARM::SMULTT, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 11739 { 1429 /* smulwb */, ARM::t2SMULWB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11740 { 1429 /* smulwb */, ARM::SMULWB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 11741 { 1436 /* smulwt */, ARM::t2SMULWT, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11742 { 1436 /* smulwt */, ARM::SMULWT, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 11743 { 1443 /* smusd */, ARM::t2SMUSD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11744 { 1443 /* smusd */, ARM::SMUSD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11745 { 1449 /* smusdx */, ARM::t2SMUSDX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11746 { 1449 /* smusdx */, ARM::SMUSDX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11747 { 1456 /* sqrshr */, ARM::MVE_SQRSHR, Convert__Reg1_1__Tie0_2_2__Reg1_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 11748 { 1463 /* sqrshrl */, ARM::MVE_SQRSHRL, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__Reg1_4__MveSaturate1_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_tGPREven, MCK_tGPROdd, MCK_MveSaturate, MCK_rGPR }, }, 11749 { 1471 /* sqshl */, ARM::MVE_SQSHL, Convert__Reg1_1__Tie0_2_2__MVELongShift1_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_rGPR, MCK_MVELongShift }, }, 11750 { 1477 /* sqshll */, ARM::MVE_SQSHLL, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__MVELongShift1_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_tGPREven, MCK_tGPROdd, MCK_MVELongShift }, }, 11751 { 1484 /* srsda */, ARM::SRSDA, Convert__Imm0_311_0, AMFBS_IsARM, { MCK_Imm0_31 }, }, 11752 { 1484 /* srsda */, ARM::SRSDA, Convert__Imm0_311_1, AMFBS_IsARM, { MCK_GPRsp, MCK_Imm0_31 }, }, 11753 { 1484 /* srsda */, ARM::SRSDA_UPD, Convert__Imm0_311_0, AMFBS_IsARM, { MCK_Imm0_31, MCK__EXCLAIM_ }, }, 11754 { 1484 /* srsda */, ARM::SRSDA_UPD, Convert__Imm0_311_2, AMFBS_IsARM, { MCK_GPRsp, MCK__EXCLAIM_, MCK_Imm0_31 }, }, 11755 { 1490 /* srsdb */, ARM::SRSDB, Convert__Imm0_311_0, AMFBS_IsARM, { MCK_Imm0_31 }, }, 11756 { 1490 /* srsdb */, ARM::SRSDB, Convert__Imm0_311_1, AMFBS_IsARM, { MCK_GPRsp, MCK_Imm0_31 }, }, 11757 { 1490 /* srsdb */, ARM::t2SRSDB, Convert__Imm0_311_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_Imm0_31 }, }, 11758 { 1490 /* srsdb */, ARM::SRSDB_UPD, Convert__Imm0_311_0, AMFBS_IsARM, { MCK_Imm0_31, MCK__EXCLAIM_ }, }, 11759 { 1490 /* srsdb */, ARM::SRSDB_UPD, Convert__Imm0_311_2, AMFBS_IsARM, { MCK_GPRsp, MCK__EXCLAIM_, MCK_Imm0_31 }, }, 11760 { 1490 /* srsdb */, ARM::t2SRSDB, Convert__Imm0_311_2__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_31 }, }, 11761 { 1490 /* srsdb */, ARM::t2SRSDB_UPD, Convert__Imm0_311_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_Imm0_31, MCK__EXCLAIM_ }, }, 11762 { 1490 /* srsdb */, ARM::t2SRSDB_UPD, Convert__Imm0_311_3__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPRsp, MCK__EXCLAIM_, MCK_Imm0_31 }, }, 11763 { 1496 /* srshr */, ARM::MVE_SRSHR, Convert__Reg1_1__Tie0_2_2__MVELongShift1_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_rGPR, MCK_MVELongShift }, }, 11764 { 1502 /* srshrl */, ARM::MVE_SRSHRL, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__MVELongShift1_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_tGPREven, MCK_tGPROdd, MCK_MVELongShift }, }, 11765 { 1509 /* srsia */, ARM::SRSIA, Convert__Imm0_311_0, AMFBS_IsARM, { MCK_Imm0_31 }, }, 11766 { 1509 /* srsia */, ARM::SRSIA, Convert__Imm0_311_1, AMFBS_IsARM, { MCK_GPRsp, MCK_Imm0_31 }, }, 11767 { 1509 /* srsia */, ARM::t2SRSIA, Convert__Imm0_311_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_Imm0_31 }, }, 11768 { 1509 /* srsia */, ARM::SRSIA_UPD, Convert__Imm0_311_0, AMFBS_IsARM, { MCK_Imm0_31, MCK__EXCLAIM_ }, }, 11769 { 1509 /* srsia */, ARM::SRSIA_UPD, Convert__Imm0_311_2, AMFBS_IsARM, { MCK_GPRsp, MCK__EXCLAIM_, MCK_Imm0_31 }, }, 11770 { 1509 /* srsia */, ARM::t2SRSIA, Convert__Imm0_311_2__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_31 }, }, 11771 { 1509 /* srsia */, ARM::t2SRSIA_UPD, Convert__Imm0_311_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_Imm0_31, MCK__EXCLAIM_ }, }, 11772 { 1509 /* srsia */, ARM::t2SRSIA_UPD, Convert__Imm0_311_3__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPRsp, MCK__EXCLAIM_, MCK_Imm0_31 }, }, 11773 { 1515 /* srsib */, ARM::SRSIB, Convert__Imm0_311_0, AMFBS_IsARM, { MCK_Imm0_31 }, }, 11774 { 1515 /* srsib */, ARM::SRSIB, Convert__Imm0_311_1, AMFBS_IsARM, { MCK_GPRsp, MCK_Imm0_31 }, }, 11775 { 1515 /* srsib */, ARM::SRSIB_UPD, Convert__Imm0_311_0, AMFBS_IsARM, { MCK_Imm0_31, MCK__EXCLAIM_ }, }, 11776 { 1515 /* srsib */, ARM::SRSIB_UPD, Convert__Imm0_311_2, AMFBS_IsARM, { MCK_GPRsp, MCK__EXCLAIM_, MCK_Imm0_31 }, }, 11777 { 1521 /* ssat */, ARM::t2SSAT, Convert__Reg1_1__Imm1_321_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm1_32, MCK_rGPR }, }, 11778 { 1521 /* ssat */, ARM::SSAT, Convert__Reg1_1__Imm1_321_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_Imm1_32, MCK_GPRnopc }, }, 11779 { 1521 /* ssat */, ARM::t2SSAT, Convert__Reg1_1__Imm1_321_2__Reg1_3__ShifterImm1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm1_32, MCK_rGPR, MCK_ShifterImm }, }, 11780 { 1521 /* ssat */, ARM::SSAT, Convert__Reg1_1__Imm1_321_2__Reg1_3__ShifterImm1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_Imm1_32, MCK_GPRnopc, MCK_ShifterImm }, }, 11781 { 1526 /* ssat16 */, ARM::t2SSAT16, Convert__Reg1_1__Imm1_161_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_Imm1_16, MCK_rGPR }, }, 11782 { 1526 /* ssat16 */, ARM::SSAT16, Convert__Reg1_1__Imm1_161_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_Imm1_16, MCK_GPRnopc }, }, 11783 { 1533 /* ssax */, ARM::t2SSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11784 { 1533 /* ssax */, ARM::SSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11785 { 1538 /* ssbb */, ARM::t2DSB, Convert__imm_95_0__imm_95_14__imm_95_0, AMFBS_HasDB_IsThumb2, { }, }, 11786 { 1538 /* ssbb */, ARM::DSB, Convert__imm_95_0, AMFBS_IsARM_HasDB, { }, }, 11787 { 1543 /* ssub16 */, ARM::t2SSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11788 { 1543 /* ssub16 */, ARM::SSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11789 { 1550 /* ssub8 */, ARM::t2SSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11790 { 1550 /* ssub8 */, ARM::SSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 11791 { 1556 /* stc */, ARM::STC_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, }, 11792 { 1556 /* stc */, ARM::t2STC_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, }, 11793 { 1556 /* stc */, ARM::STC_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, }, 11794 { 1556 /* stc */, ARM::t2STC_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, }, 11795 { 1556 /* stc */, ARM::STC_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, }, 11796 { 1556 /* stc */, ARM::t2STC_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, }, 11797 { 1556 /* stc */, ARM::STC_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, }, 11798 { 1556 /* stc */, ARM::t2STC_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, }, 11799 { 1560 /* stc2 */, ARM::STC2_OFFSET, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, }, 11800 { 1560 /* stc2 */, ARM::t2STC2_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, }, 11801 { 1560 /* stc2 */, ARM::STC2_PRE, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, }, 11802 { 1560 /* stc2 */, ARM::STC2_OPTION, Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__CoprocOption1_3, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, }, 11803 { 1560 /* stc2 */, ARM::STC2_POST, Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__PostIdxImm8s41_3, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, }, 11804 { 1560 /* stc2 */, ARM::t2STC2_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, }, 11805 { 1560 /* stc2 */, ARM::t2STC2_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, }, 11806 { 1560 /* stc2 */, ARM::t2STC2_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, }, 11807 { 1565 /* stc2l */, ARM::STC2L_OFFSET, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, }, 11808 { 1565 /* stc2l */, ARM::t2STC2L_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, }, 11809 { 1565 /* stc2l */, ARM::STC2L_PRE, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, }, 11810 { 1565 /* stc2l */, ARM::STC2L_OPTION, Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__CoprocOption1_3, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, }, 11811 { 1565 /* stc2l */, ARM::STC2L_POST, Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__PostIdxImm8s41_3, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, }, 11812 { 1565 /* stc2l */, ARM::t2STC2L_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, }, 11813 { 1565 /* stc2l */, ARM::t2STC2L_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, }, 11814 { 1565 /* stc2l */, ARM::t2STC2L_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, }, 11815 { 1571 /* stcl */, ARM::STCL_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, }, 11816 { 1571 /* stcl */, ARM::t2STCL_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, }, 11817 { 1571 /* stcl */, ARM::STCL_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, }, 11818 { 1571 /* stcl */, ARM::t2STCL_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, }, 11819 { 1571 /* stcl */, ARM::STCL_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, }, 11820 { 1571 /* stcl */, ARM::t2STCL_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, }, 11821 { 1571 /* stcl */, ARM::STCL_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, }, 11822 { 1571 /* stcl */, ARM::t2STCL_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, }, 11823 { 1576 /* stl */, ARM::t2STL, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, }, 11824 { 1576 /* stl */, ARM::STL, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM_HasAcquireRelease, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, }, 11825 { 1580 /* stlb */, ARM::t2STLB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, }, 11826 { 1580 /* stlb */, ARM::STLB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM_HasAcquireRelease, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, }, 11827 { 1585 /* stlex */, ARM::t2STLEX, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, }, 11828 { 1585 /* stlex */, ARM::STLEX, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsARM_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset }, }, 11829 { 1591 /* stlexb */, ARM::t2STLEXB, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, }, 11830 { 1591 /* stlexb */, ARM::STLEXB, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsARM_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset }, }, 11831 { 1598 /* stlexd */, ARM::STLEXD, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsARM_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_GPR, MCK_GPRPair, MCK_MemNoOffset }, }, 11832 { 1598 /* stlexd */, ARM::t2STLEXD, Convert__Reg1_1__Reg1_2__Reg1_3__MemNoOffset1_4__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease_HasV7Clrex_IsNotMClass, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, }, 11833 { 1605 /* stlexh */, ARM::t2STLEXH, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, }, 11834 { 1605 /* stlexh */, ARM::STLEXH, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsARM_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset }, }, 11835 { 1612 /* stlh */, ARM::t2STLH, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, }, 11836 { 1612 /* stlh */, ARM::STLH, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM_HasAcquireRelease, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, }, 11837 { 1617 /* stm */, ARM::STMIA, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, }, 11838 { 1617 /* stm */, ARM::t2STMIA, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_RegList }, }, 11839 { 1617 /* stm */, ARM::t2STMIA, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_RegList }, }, 11840 { 1617 /* stm */, ARM::t2STMIA, Convert__Reg1_2__CondCode2_0__RegList1_3, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_RegList }, }, 11841 { 1617 /* stm */, ARM::tSTMIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK__EXCLAIM_, MCK_RegList }, }, 11842 { 1617 /* stm */, ARM::STMIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, }, 11843 { 1617 /* stm */, ARM::t2STMIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, }, 11844 { 1617 /* stm */, ARM::sysSTMIA, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, }, 11845 { 1617 /* stm */, ARM::t2STMIA_UPD, Convert__Reg1_2__Tie0_3_3__CondCode2_0__RegList1_4, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, }, 11846 { 1617 /* stm */, ARM::sysSTMIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, }, 11847 { 1621 /* stmda */, ARM::STMDA, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, }, 11848 { 1621 /* stmda */, ARM::STMDA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, }, 11849 { 1621 /* stmda */, ARM::sysSTMDA, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, }, 11850 { 1621 /* stmda */, ARM::sysSTMDA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, }, 11851 { 1627 /* stmdb */, ARM::STMDB, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, }, 11852 { 1627 /* stmdb */, ARM::t2STMDB, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_RegList }, }, 11853 { 1627 /* stmdb */, ARM::t2STMDB, Convert__Reg1_2__CondCode2_0__RegList1_3, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_RegList }, }, 11854 { 1627 /* stmdb */, ARM::STMDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, }, 11855 { 1627 /* stmdb */, ARM::t2STMDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, }, 11856 { 1627 /* stmdb */, ARM::sysSTMDB, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, }, 11857 { 1627 /* stmdb */, ARM::t2STMDB_UPD, Convert__Reg1_2__Tie0_3_3__CondCode2_0__RegList1_4, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, }, 11858 { 1627 /* stmdb */, ARM::sysSTMDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, }, 11859 { 1633 /* stmib */, ARM::STMIB, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, }, 11860 { 1633 /* stmib */, ARM::STMIB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, }, 11861 { 1633 /* stmib */, ARM::sysSTMIB, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, }, 11862 { 1633 /* stmib */, ARM::sysSTMIB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, }, 11863 { 1639 /* str */, ARM::tSTRi, Convert__Reg1_1__MemThumbRIs42_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRIs4 }, }, 11864 { 1639 /* str */, ARM::tSTRr, Convert__Reg1_1__MemThumbRR2_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRR }, }, 11865 { 1639 /* str */, ARM::tSTRspi, Convert__Reg1_1__MemThumbSPI2_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbSPI }, }, 11866 { 1639 /* str */, ARM::STRi12, Convert__Reg1_1__MemImm12Offset2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemImm12Offset }, }, 11867 { 1639 /* str */, ARM::t2STRi8, Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemNegImm8Offset }, }, 11868 { 1639 /* str */, ARM::STRrs, Convert__Reg1_1__MemRegOffset3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemRegOffset }, }, 11869 { 1639 /* str */, ARM::t2STRi12, Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemUImm12Offset }, }, 11870 { 1639 /* str */, ARM::t2STRs, Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_T2MemRegOffset }, }, 11871 { 1639 /* str */, ARM::t2STRi12, Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemUImm12Offset }, }, 11872 { 1639 /* str */, ARM::t2STRs, Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_T2MemRegOffset }, }, 11873 { 1639 /* str */, ARM::t2STR_PRE, Convert__imm_95_0__Reg1_1__MemImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemImm8Offset, MCK__EXCLAIM_ }, }, 11874 { 1639 /* str */, ARM::t2STR_POST, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemNoOffset, MCK_Imm }, }, 11875 { 1639 /* str */, ARM::STR_PRE_IMM, Convert__imm_95_0__Reg1_1__MemImm12Offset2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemImm12Offset, MCK__EXCLAIM_ }, }, 11876 { 1639 /* str */, ARM::STR_POST_IMM, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM2OffsetImm2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, }, 11877 { 1639 /* str */, ARM::STR_POST_REG, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxRegShifted2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, }, 11878 { 1639 /* str */, ARM::STR_PRE_REG, Convert__imm_95_0__Reg1_1__MemRegOffset3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemRegOffset, MCK__EXCLAIM_ }, }, 11879 { 1639 /* str */, ARM::t2STR_PRE_imm, Convert__Reg1_2__MemImm8Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, }, 11880 { 1639 /* str */, ARM::t2STR_POST_imm, Convert__Reg1_2__MemNoOffset1_3__Imm1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemNoOffset, MCK_Imm }, }, 11881 { 1643 /* strb */, ARM::tSTRBi, Convert__Reg1_1__MemThumbRIs12_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRIs1 }, }, 11882 { 1643 /* strb */, ARM::tSTRBr, Convert__Reg1_1__MemThumbRR2_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRR }, }, 11883 { 1643 /* strb */, ARM::t2STRBi8, Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemNegImm8Offset }, }, 11884 { 1643 /* strb */, ARM::t2STRBi12, Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemUImm12Offset }, }, 11885 { 1643 /* strb */, ARM::t2STRBs, Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2MemRegOffset }, }, 11886 { 1643 /* strb */, ARM::STRBi12, Convert__Reg1_1__MemImm12Offset2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_MemImm12Offset }, }, 11887 { 1643 /* strb */, ARM::STRBrs, Convert__Reg1_1__MemRegOffset3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_MemRegOffset }, }, 11888 { 1643 /* strb */, ARM::t2STRBi12, Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_MemUImm12Offset }, }, 11889 { 1643 /* strb */, ARM::t2STRBs, Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2MemRegOffset }, }, 11890 { 1643 /* strb */, ARM::t2STRB_PRE, Convert__imm_95_0__Reg1_1__MemImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, }, 11891 { 1643 /* strb */, ARM::t2STRB_POST, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset, MCK_Imm }, }, 11892 { 1643 /* strb */, ARM::STRB_PRE_IMM, Convert__imm_95_0__Reg1_1__MemImm12Offset2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemImm12Offset, MCK__EXCLAIM_ }, }, 11893 { 1643 /* strb */, ARM::STRB_POST_IMM, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM2OffsetImm2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, }, 11894 { 1643 /* strb */, ARM::STRB_POST_REG, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxRegShifted2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, }, 11895 { 1643 /* strb */, ARM::STRB_PRE_REG, Convert__imm_95_0__Reg1_1__MemRegOffset3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemRegOffset, MCK__EXCLAIM_ }, }, 11896 { 1648 /* strbt */, ARM::t2STRBT, Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemPosImm8Offset }, }, 11897 { 1648 /* strbt */, ARM::STRBT_POST, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, }, 11898 { 1648 /* strbt */, ARM::STRBT_POST_IMM, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM2OffsetImm2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, }, 11899 { 1648 /* strbt */, ARM::STRBT_POST_REG, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxRegShifted2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, }, 11900 { 1654 /* strd */, ARM::t2STRDi8, Convert__Reg1_1__Reg1_2__MemImm8s4Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemImm8s4Offset }, }, 11901 { 1654 /* strd */, ARM::STRD, Convert__Reg1_1__Reg1_2__AddrMode33_3__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_AddrMode3 }, }, 11902 { 1654 /* strd */, ARM::t2STRD_PRE, Convert__imm_95_0__Reg1_1__Reg1_2__MemImm8s4Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemImm8s4Offset, MCK__EXCLAIM_ }, }, 11903 { 1654 /* strd */, ARM::t2STRD_POST, Convert__MemNoOffset1_3__Reg1_1__Reg1_2__Tie0_4_4__Imm1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset, MCK_Imm }, }, 11904 { 1654 /* strd */, ARM::STRD_PRE, Convert__imm_95_0__Reg1_1__Reg1_2__AddrMode33_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_AddrMode3, MCK__EXCLAIM_ }, }, 11905 { 1654 /* strd */, ARM::STRD_POST, Convert__MemNoOffset1_3__Reg1_1__Reg1_2__Tie0_4_4__AM3Offset2_4__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset, MCK_AM3Offset }, }, 11906 { 1659 /* strex */, ARM::t2STREX, Convert__Reg1_1__Reg1_2__MemImm0_1020s4Offset2_3__CondCode2_0, AMFBS_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemImm0_1020s4Offset }, }, 11907 { 1659 /* strex */, ARM::STREX, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset }, }, 11908 { 1665 /* strexb */, ARM::t2STREXB, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, }, 11909 { 1665 /* strexb */, ARM::STREXB, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset }, }, 11910 { 1672 /* strexd */, ARM::STREXD, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPRPair, MCK_MemNoOffset }, }, 11911 { 1672 /* strexd */, ARM::t2STREXD, Convert__Reg1_1__Reg1_2__Reg1_3__MemNoOffset1_4__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, }, 11912 { 1679 /* strexh */, ARM::t2STREXH, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, }, 11913 { 1679 /* strexh */, ARM::STREXH, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset }, }, 11914 { 1686 /* strh */, ARM::tSTRHi, Convert__Reg1_1__MemThumbRIs22_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRIs2 }, }, 11915 { 1686 /* strh */, ARM::tSTRHr, Convert__Reg1_1__MemThumbRR2_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRR }, }, 11916 { 1686 /* strh */, ARM::t2STRHi8, Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemNegImm8Offset }, }, 11917 { 1686 /* strh */, ARM::t2STRHi12, Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemUImm12Offset }, }, 11918 { 1686 /* strh */, ARM::t2STRHs, Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2MemRegOffset }, }, 11919 { 1686 /* strh */, ARM::STRH, Convert__Reg1_1__AddrMode33_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3 }, }, 11920 { 1686 /* strh */, ARM::t2STRHi12, Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_MemUImm12Offset }, }, 11921 { 1686 /* strh */, ARM::t2STRHs, Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2MemRegOffset }, }, 11922 { 1686 /* strh */, ARM::t2STRH_PRE, Convert__imm_95_0__Reg1_1__MemImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, }, 11923 { 1686 /* strh */, ARM::t2STRH_POST, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset, MCK_Imm }, }, 11924 { 1686 /* strh */, ARM::STRH_PRE, Convert__imm_95_0__Reg1_1__AddrMode33_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3, MCK__EXCLAIM_ }, }, 11925 { 1686 /* strh */, ARM::STRH_POST, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM3Offset2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM3Offset }, }, 11926 { 1691 /* strht */, ARM::t2STRHT, Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemPosImm8Offset }, }, 11927 { 1691 /* strht */, ARM::STRHTi, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxImm81_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxImm8 }, }, 11928 { 1691 /* strht */, ARM::STRHTr, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxReg2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxReg }, }, 11929 { 1697 /* strt */, ARM::t2STRT, Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemPosImm8Offset }, }, 11930 { 1697 /* strt */, ARM::STRT_POST, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, }, 11931 { 1697 /* strt */, ARM::STRT_POST_IMM, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM2OffsetImm2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, }, 11932 { 1697 /* strt */, ARM::STRT_POST_REG, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxRegShifted2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, }, 11933 { 1702 /* sub */, ARM::t2SUBspImm12, Convert__Reg1_1__Reg1_1__Imm0_40951_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_4095 }, }, 11934 { 1702 /* sub */, ARM::tSUBspi, Convert__Reg1_1__Tie0_1_1__Imm0_508s41_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_508s4 }, }, 11935 { 1702 /* sub */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_1__Imm0_40951_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm0_4095 }, }, 11936 { 1702 /* sub */, ARM::t2SUBspImm, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRsp, MCK_T2SOImm }, }, 11937 { 1702 /* sub */, ARM::tSUBrr, Convert__Reg1_2__CCOut1_0__Reg1_2__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 11938 { 1702 /* sub */, ARM::tSUBi8, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Imm0_2551_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_Imm0_255 }, }, 11939 { 1702 /* sub */, ARM::tADDi8, Convert__Reg1_2__CCOut1_0__Tie0_3_3__ThumbModImmNeg8_2551_3__CondCode2_1, AMFBS_IsThumb_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_ThumbModImmNeg8_255 }, }, 11940 { 1702 /* sub */, ARM::t2SUBri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, }, 11941 { 1702 /* sub */, ARM::t2SUBrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_rGPR }, }, 11942 { 1702 /* sub */, ARM::t2SUBrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedImm }, }, 11943 { 1702 /* sub */, ARM::SUBrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, }, 11944 { 1702 /* sub */, ARM::SUBri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, }, 11945 { 1702 /* sub */, ARM::ADDri, Convert__Reg1_2__Reg1_2__ModImmNeg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImmNeg }, }, 11946 { 1702 /* sub */, ARM::SUBrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, }, 11947 { 1702 /* sub */, ARM::SUBrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, }, 11948 { 1702 /* sub */, ARM::t2SUBspImm12, Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_Imm0_4095 }, }, 11949 { 1702 /* sub */, ARM::t2ADDspImm12, Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_Imm0_4095Neg }, }, 11950 { 1702 /* sub */, ARM::tSUBspi, Convert__regSP__Tie0_1_1__Imm0_508s41_3__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_Imm0_508s4 }, }, 11951 { 1702 /* sub */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_GPR, MCK_Imm0_4095 }, }, 11952 { 1702 /* sub */, ARM::t2ADDri12, Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_GPR, MCK_Imm0_4095Neg }, }, 11953 { 1702 /* sub */, ARM::t2SUBspImm, Convert__Reg1_3__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRsp, MCK_T2SOImm }, }, 11954 { 1702 /* sub */, ARM::t2SUBrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_rGPR }, }, 11955 { 1702 /* sub */, ARM::t2SUBspImm, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_T2SOImm }, }, 11956 { 1702 /* sub */, ARM::t2ADDspImm, Convert__Reg1_2__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_T2SOImmNeg }, }, 11957 { 1702 /* sub */, ARM::tSUBrr, Convert__Reg1_2__CCOut1_0__Reg1_3__Reg1_4__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_tGPR }, }, 11958 { 1702 /* sub */, ARM::tSUBi3, Convert__Reg1_2__CCOut1_0__Reg1_3__Imm0_71_4__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_Imm0_7 }, }, 11959 { 1702 /* sub */, ARM::tADDi3, Convert__Reg1_2__CCOut1_0__Reg1_3__ThumbModImmNeg1_71_4__CondCode2_1, AMFBS_IsThumb_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_ThumbModImmNeg1_7 }, }, 11960 { 1702 /* sub */, ARM::t2SUBri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_GPRnopc, MCK_T2SOImm }, }, 11961 { 1702 /* sub */, ARM::t2ADDri, Convert__Reg1_2__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_GPRnopc, MCK_T2SOImmNeg }, }, 11962 { 1702 /* sub */, ARM::t2SUBrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_rGPR }, }, 11963 { 1702 /* sub */, ARM::t2SUBrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RegShiftedImm }, }, 11964 { 1702 /* sub */, ARM::SUBrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 11965 { 1702 /* sub */, ARM::SUBri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, }, 11966 { 1702 /* sub */, ARM::ADDri, Convert__Reg1_2__Reg1_3__ModImmNeg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImmNeg }, }, 11967 { 1702 /* sub */, ARM::SUBrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, }, 11968 { 1702 /* sub */, ARM::SUBrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, }, 11969 { 1702 /* sub */, ARM::t2SUBspImm, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRsp, MCK_GPRsp, MCK_T2SOImm }, }, 11970 { 1702 /* sub */, ARM::t2ADDspImm, Convert__Reg1_3__Reg1_4__T2SOImmNeg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRsp, MCK_GPRsp, MCK_T2SOImmNeg }, }, 11971 { 1702 /* sub */, ARM::t2SUBri, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_GPRnopc, MCK_T2SOImm }, }, 11972 { 1702 /* sub */, ARM::t2ADDri, Convert__Reg1_3__Reg1_4__T2SOImmNeg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_GPRnopc, MCK_T2SOImmNeg }, }, 11973 { 1702 /* sub */, ARM::t2SUBrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc, MCK_rGPR }, }, 11974 { 1702 /* sub */, ARM::t2SUBrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc, MCK_RegShiftedImm }, }, 11975 { 1706 /* subs */, ARM::t2SUBS_PC_LR, Convert__Imm0_2551_3__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_PC, MCK_GPRlr, MCK_Imm0_255 }, }, 11976 { 1711 /* subw */, ARM::t2SUBspImm12, Convert__Reg1_1__Reg1_1__Imm0_40951_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_4095 }, }, 11977 { 1711 /* subw */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_1__Imm0_40951_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm0_4095 }, }, 11978 { 1711 /* subw */, ARM::t2SUBspImm12, Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_Imm0_4095 }, }, 11979 { 1711 /* subw */, ARM::t2ADDspImm12, Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_Imm0_4095Neg }, }, 11980 { 1711 /* subw */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_GPR, MCK_Imm0_4095 }, }, 11981 { 1711 /* subw */, ARM::t2ADDri12, Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_GPR, MCK_Imm0_4095Neg }, }, 11982 { 1716 /* svc */, ARM::tSVC, Convert__Imm0_2551_1__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_Imm0_255 }, }, 11983 { 1716 /* svc */, ARM::SVC, Convert__Imm24bit1_1__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_Imm24bit }, }, 11984 { 1720 /* swp */, ARM::SWP, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsARM_PreV8, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_MemNoOffset }, }, 11985 { 1724 /* swpb */, ARM::SWPB, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsARM_PreV8, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_MemNoOffset }, }, 11986 { 1729 /* sxtab */, ARM::t2SXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11987 { 1729 /* sxtab */, ARM::SXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc }, }, 11988 { 1729 /* sxtab */, ARM::t2SXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_RotImm }, }, 11989 { 1729 /* sxtab */, ARM::SXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc, MCK_RotImm }, }, 11990 { 1735 /* sxtab16 */, ARM::t2SXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11991 { 1735 /* sxtab16 */, ARM::SXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc }, }, 11992 { 1735 /* sxtab16 */, ARM::t2SXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_RotImm }, }, 11993 { 1735 /* sxtab16 */, ARM::SXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc, MCK_RotImm }, }, 11994 { 1743 /* sxtah */, ARM::t2SXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 11995 { 1743 /* sxtah */, ARM::SXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc }, }, 11996 { 1743 /* sxtah */, ARM::t2SXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_RotImm }, }, 11997 { 1743 /* sxtah */, ARM::SXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc, MCK_RotImm }, }, 11998 { 1749 /* sxtb */, ARM::tSXTB, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb_HasV6, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 11999 { 1749 /* sxtb */, ARM::t2SXTB, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 12000 { 1749 /* sxtb */, ARM::SXTB, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, }, 12001 { 1749 /* sxtb */, ARM::t2SXTB, Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, }, 12002 { 1749 /* sxtb */, ARM::t2SXTB, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, }, 12003 { 1749 /* sxtb */, ARM::SXTB, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RotImm }, }, 12004 { 1749 /* sxtb */, ARM::t2SXTB, Convert__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RotImm }, }, 12005 { 1754 /* sxtb16 */, ARM::t2SXTB16, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 12006 { 1754 /* sxtb16 */, ARM::SXTB16, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, }, 12007 { 1754 /* sxtb16 */, ARM::t2SXTB16, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, }, 12008 { 1754 /* sxtb16 */, ARM::t2SXTB16, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, }, 12009 { 1754 /* sxtb16 */, ARM::SXTB16, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RotImm }, }, 12010 { 1761 /* sxth */, ARM::tSXTH, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb_HasV6, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 12011 { 1761 /* sxth */, ARM::t2SXTH, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 12012 { 1761 /* sxth */, ARM::SXTH, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, }, 12013 { 1761 /* sxth */, ARM::t2SXTH, Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, }, 12014 { 1761 /* sxth */, ARM::t2SXTH, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, }, 12015 { 1761 /* sxth */, ARM::SXTH, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RotImm }, }, 12016 { 1761 /* sxth */, ARM::t2SXTH, Convert__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RotImm }, }, 12017 { 1766 /* tbb */, ARM::t2TBB, Convert__MemTBB2_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_MemTBB }, }, 12018 { 1770 /* tbh */, ARM::t2TBH, Convert__MemTBH2_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_MemTBH }, }, 12019 { 1774 /* teq */, ARM::t2TEQrr, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 12020 { 1774 /* teq */, ARM::t2TEQrs, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, }, 12021 { 1774 /* teq */, ARM::t2TEQri, Convert__Reg1_1__T2SOImm1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, }, 12022 { 1774 /* teq */, ARM::TEQrsr, Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, }, 12023 { 1774 /* teq */, ARM::TEQrr, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR }, }, 12024 { 1774 /* teq */, ARM::TEQri, Convert__Reg1_1__ModImm1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_ModImm }, }, 12025 { 1774 /* teq */, ARM::TEQrsi, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, }, 12026 { 1774 /* teq */, ARM::t2TEQrr, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, }, 12027 { 1774 /* teq */, ARM::t2TEQrs, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, }, 12028 { 1774 /* teq */, ARM::t2TEQri, Convert__Reg1_2__T2SOImm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, }, 12029 { 1778 /* trap */, ARM::TRAPNaCl, Convert_NoOperands, AMFBS_IsARM_UseNaClTrap, { }, }, 12030 { 1778 /* trap */, ARM::TRAP, Convert_NoOperands, AMFBS_IsARM, { }, }, 12031 { 1778 /* trap */, ARM::tTRAP, Convert_NoOperands, AMFBS_IsThumb, { }, }, 12032 { 1783 /* tsb */, ARM::TSB, Convert__TraceSyncBarrierOpt1_0, AMFBS_IsARM_HasV8_4a, { MCK_TraceSyncBarrierOpt }, }, 12033 { 1783 /* tsb */, ARM::t2TSB, Convert__TraceSyncBarrierOpt1_1__CondCode2_0, AMFBS_IsThumb_HasV8_4a, { MCK_CondCode, MCK_TraceSyncBarrierOpt }, }, 12034 { 1787 /* tst */, ARM::tTST, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 12035 { 1787 /* tst */, ARM::t2TSTrr, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 12036 { 1787 /* tst */, ARM::t2TSTrs, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, }, 12037 { 1787 /* tst */, ARM::t2TSTri, Convert__Reg1_1__T2SOImm1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, }, 12038 { 1787 /* tst */, ARM::TSTrsr, Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, }, 12039 { 1787 /* tst */, ARM::TSTrr, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR }, }, 12040 { 1787 /* tst */, ARM::TSTri, Convert__Reg1_1__ModImm1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_ModImm }, }, 12041 { 1787 /* tst */, ARM::TSTrsi, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, }, 12042 { 1787 /* tst */, ARM::t2TSTrr, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, }, 12043 { 1787 /* tst */, ARM::t2TSTrs, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, }, 12044 { 1787 /* tst */, ARM::t2TSTri, Convert__Reg1_2__T2SOImm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, }, 12045 { 1791 /* tt */, ARM::t2TT, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb_Has8MSecExt, { MCK_CondCode, MCK_rGPR, MCK_GPRnopc }, }, 12046 { 1794 /* tta */, ARM::t2TTA, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb_Has8MSecExt, { MCK_CondCode, MCK_rGPR, MCK_GPRnopc }, }, 12047 { 1798 /* ttat */, ARM::t2TTAT, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb_Has8MSecExt, { MCK_CondCode, MCK_rGPR, MCK_GPRnopc }, }, 12048 { 1803 /* ttt */, ARM::t2TTT, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb_Has8MSecExt, { MCK_CondCode, MCK_rGPR, MCK_GPRnopc }, }, 12049 { 1807 /* uadd16 */, ARM::t2UADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 12050 { 1807 /* uadd16 */, ARM::UADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 12051 { 1814 /* uadd8 */, ARM::t2UADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 12052 { 1814 /* uadd8 */, ARM::UADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 12053 { 1820 /* uasx */, ARM::t2UASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 12054 { 1820 /* uasx */, ARM::UASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 12055 { 1825 /* ubfx */, ARM::t2UBFX, Convert__Reg1_1__Reg1_2__Imm0_311_3__Imm1_321_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_Imm0_31, MCK_Imm1_32 }, }, 12056 { 1825 /* ubfx */, ARM::UBFX, Convert__Reg1_1__Reg1_2__Imm0_311_3__Imm1_321_4__CondCode2_0, AMFBS_IsARM_HasV6T2, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_Imm0_31, MCK_Imm1_32 }, }, 12057 { 1830 /* udf */, ARM::tUDF, Convert__Imm0_2551_0, AMFBS_IsThumb, { MCK_Imm0_255 }, }, 12058 { 1830 /* udf */, ARM::UDF, Convert__Imm0_655351_0, AMFBS_IsARM, { MCK_Imm0_65535 }, }, 12059 { 1830 /* udf */, ARM::t2UDF, Convert__Imm0_655351_1, AMFBS_IsThumb2, { MCK__DOT_w, MCK_Imm0_65535 }, }, 12060 { 1834 /* udiv */, ARM::t2UDIV, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasDivideInThumb_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 12061 { 1834 /* udiv */, ARM::UDIV, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasDivideInARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 12062 { 1839 /* uhadd16 */, ARM::t2UHADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 12063 { 1839 /* uhadd16 */, ARM::UHADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 12064 { 1847 /* uhadd8 */, ARM::t2UHADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 12065 { 1847 /* uhadd8 */, ARM::UHADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 12066 { 1854 /* uhasx */, ARM::t2UHASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 12067 { 1854 /* uhasx */, ARM::UHASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 12068 { 1860 /* uhsax */, ARM::t2UHSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 12069 { 1860 /* uhsax */, ARM::UHSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 12070 { 1866 /* uhsub16 */, ARM::t2UHSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 12071 { 1866 /* uhsub16 */, ARM::UHSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 12072 { 1874 /* uhsub8 */, ARM::t2UHSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 12073 { 1874 /* uhsub8 */, ARM::UHSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 12074 { 1881 /* umaal */, ARM::t2UMAAL, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 12075 { 1881 /* umaal */, ARM::UMAAL, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, }, 12076 { 1887 /* umlal */, ARM::t2UMLAL, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 12077 { 1887 /* umlal */, ARM::UMLAL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0_1_1__Tie1_1_1__CondCode2_1__CCOut1_0, AMFBS_IsARM_HasV6, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, }, 12078 { 1887 /* umlal */, ARM::UMLAL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0_3_3__Tie1_4_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, }, 12079 { 1893 /* umull */, ARM::t2UMULL, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 12080 { 1893 /* umull */, ARM::UMULL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsARM_HasV6, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, }, 12081 { 1893 /* umull */, ARM::UMULL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, }, 12082 { 1899 /* uqadd16 */, ARM::t2UQADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 12083 { 1899 /* uqadd16 */, ARM::UQADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 12084 { 1907 /* uqadd8 */, ARM::t2UQADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 12085 { 1907 /* uqadd8 */, ARM::UQADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 12086 { 1914 /* uqasx */, ARM::t2UQASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 12087 { 1914 /* uqasx */, ARM::UQASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 12088 { 1920 /* uqrshl */, ARM::MVE_UQRSHL, Convert__Reg1_1__Tie0_2_2__Reg1_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 12089 { 1927 /* uqrshll */, ARM::MVE_UQRSHLL, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__Reg1_4__MveSaturate1_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_tGPREven, MCK_tGPROdd, MCK_MveSaturate, MCK_rGPR }, }, 12090 { 1935 /* uqsax */, ARM::t2UQSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 12091 { 1935 /* uqsax */, ARM::UQSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 12092 { 1941 /* uqshl */, ARM::MVE_UQSHL, Convert__Reg1_1__Tie0_2_2__MVELongShift1_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_rGPR, MCK_MVELongShift }, }, 12093 { 1947 /* uqshll */, ARM::MVE_UQSHLL, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__MVELongShift1_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_tGPREven, MCK_tGPROdd, MCK_MVELongShift }, }, 12094 { 1954 /* uqsub16 */, ARM::t2UQSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 12095 { 1954 /* uqsub16 */, ARM::UQSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 12096 { 1962 /* uqsub8 */, ARM::t2UQSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 12097 { 1962 /* uqsub8 */, ARM::UQSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 12098 { 1969 /* urshr */, ARM::MVE_URSHR, Convert__Reg1_1__Tie0_2_2__MVELongShift1_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_rGPR, MCK_MVELongShift }, }, 12099 { 1975 /* urshrl */, ARM::MVE_URSHRL, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__MVELongShift1_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_tGPREven, MCK_tGPROdd, MCK_MVELongShift }, }, 12100 { 1982 /* usad8 */, ARM::t2USAD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 12101 { 1982 /* usad8 */, ARM::USAD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 12102 { 1988 /* usada8 */, ARM::t2USADA8, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 12103 { 1988 /* usada8 */, ARM::USADA8, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, }, 12104 { 1995 /* usat */, ARM::t2USAT, Convert__Reg1_1__Imm0_311_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm0_31, MCK_rGPR }, }, 12105 { 1995 /* usat */, ARM::USAT, Convert__Reg1_1__Imm0_311_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_Imm0_31, MCK_GPRnopc }, }, 12106 { 1995 /* usat */, ARM::t2USAT, Convert__Reg1_1__Imm0_311_2__Reg1_3__ShifterImm1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm0_31, MCK_rGPR, MCK_ShifterImm }, }, 12107 { 1995 /* usat */, ARM::USAT, Convert__Reg1_1__Imm0_311_2__Reg1_3__ShifterImm1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_Imm0_31, MCK_GPRnopc, MCK_ShifterImm }, }, 12108 { 2000 /* usat16 */, ARM::t2USAT16, Convert__Reg1_1__Imm0_151_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_Imm0_15, MCK_rGPR }, }, 12109 { 2000 /* usat16 */, ARM::USAT16, Convert__Reg1_1__Imm0_151_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_Imm0_15, MCK_GPRnopc }, }, 12110 { 2007 /* usax */, ARM::t2USAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 12111 { 2007 /* usax */, ARM::USAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 12112 { 2012 /* usub16 */, ARM::t2USUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 12113 { 2012 /* usub16 */, ARM::USUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 12114 { 2019 /* usub8 */, ARM::t2USUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 12115 { 2019 /* usub8 */, ARM::USUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 12116 { 2025 /* uxtab */, ARM::t2UXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 12117 { 2025 /* uxtab */, ARM::UXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc }, }, 12118 { 2025 /* uxtab */, ARM::t2UXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_RotImm }, }, 12119 { 2025 /* uxtab */, ARM::UXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc, MCK_RotImm }, }, 12120 { 2031 /* uxtab16 */, ARM::t2UXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 12121 { 2031 /* uxtab16 */, ARM::UXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc }, }, 12122 { 2031 /* uxtab16 */, ARM::t2UXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_RotImm }, }, 12123 { 2031 /* uxtab16 */, ARM::UXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc, MCK_RotImm }, }, 12124 { 2039 /* uxtah */, ARM::t2UXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 12125 { 2039 /* uxtah */, ARM::UXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc }, }, 12126 { 2039 /* uxtah */, ARM::t2UXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_RotImm }, }, 12127 { 2039 /* uxtah */, ARM::UXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc, MCK_RotImm }, }, 12128 { 2045 /* uxtb */, ARM::tUXTB, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb_HasV6, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 12129 { 2045 /* uxtb */, ARM::t2UXTB, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 12130 { 2045 /* uxtb */, ARM::UXTB, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, }, 12131 { 2045 /* uxtb */, ARM::t2UXTB, Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, }, 12132 { 2045 /* uxtb */, ARM::t2UXTB, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, }, 12133 { 2045 /* uxtb */, ARM::UXTB, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RotImm }, }, 12134 { 2045 /* uxtb */, ARM::t2UXTB, Convert__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RotImm }, }, 12135 { 2050 /* uxtb16 */, ARM::t2UXTB16, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 12136 { 2050 /* uxtb16 */, ARM::UXTB16, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, }, 12137 { 2050 /* uxtb16 */, ARM::t2UXTB16, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, }, 12138 { 2050 /* uxtb16 */, ARM::t2UXTB16, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, }, 12139 { 2050 /* uxtb16 */, ARM::UXTB16, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RotImm }, }, 12140 { 2057 /* uxth */, ARM::tUXTH, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb_HasV6, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 12141 { 2057 /* uxth */, ARM::t2UXTH, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 12142 { 2057 /* uxth */, ARM::UXTH, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, }, 12143 { 2057 /* uxth */, ARM::t2UXTH, Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, }, 12144 { 2057 /* uxth */, ARM::t2UXTH, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, }, 12145 { 2057 /* uxth */, ARM::UXTH, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RotImm }, }, 12146 { 2057 /* uxth */, ARM::t2UXTH, Convert__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RotImm }, }, 12147 { 2062 /* vaba */, ARM::VABAsv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12148 { 2062 /* vaba */, ARM::VABAsv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12149 { 2062 /* vaba */, ARM::VABAsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12150 { 2062 /* vaba */, ARM::VABAsv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12151 { 2062 /* vaba */, ARM::VABAsv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12152 { 2062 /* vaba */, ARM::VABAsv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12153 { 2062 /* vaba */, ARM::VABAuv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12154 { 2062 /* vaba */, ARM::VABAuv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12155 { 2062 /* vaba */, ARM::VABAuv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12156 { 2062 /* vaba */, ARM::VABAuv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12157 { 2062 /* vaba */, ARM::VABAuv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12158 { 2062 /* vaba */, ARM::VABAuv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12159 { 2067 /* vabal */, ARM::VABALsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, }, 12160 { 2067 /* vabal */, ARM::VABALsv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, }, 12161 { 2067 /* vabal */, ARM::VABALsv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR, MCK_DPR }, }, 12162 { 2067 /* vabal */, ARM::VABALuv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR }, }, 12163 { 2067 /* vabal */, ARM::VABALuv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR }, }, 12164 { 2067 /* vabal */, ARM::VABALuv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR, MCK_DPR }, }, 12165 { 2073 /* vabav */, ARM::MVE_VABAVs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_rGPR, MCK_MQPR, MCK_MQPR }, }, 12166 { 2073 /* vabav */, ARM::MVE_VABAVs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_rGPR, MCK_MQPR, MCK_MQPR }, }, 12167 { 2073 /* vabav */, ARM::MVE_VABAVs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_rGPR, MCK_MQPR, MCK_MQPR }, }, 12168 { 2073 /* vabav */, ARM::MVE_VABAVu16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_rGPR, MCK_MQPR, MCK_MQPR }, }, 12169 { 2073 /* vabav */, ARM::MVE_VABAVu32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_rGPR, MCK_MQPR, MCK_MQPR }, }, 12170 { 2073 /* vabav */, ARM::MVE_VABAVu8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_rGPR, MCK_MQPR, MCK_MQPR }, }, 12171 { 2079 /* vabd */, ARM::VABDsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 12172 { 2079 /* vabd */, ARM::VABDsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 12173 { 2079 /* vabd */, ARM::VABDsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 12174 { 2079 /* vabd */, ARM::VABDsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 12175 { 2079 /* vabd */, ARM::VABDsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, }, 12176 { 2079 /* vabd */, ARM::VABDsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 12177 { 2079 /* vabd */, ARM::VABDuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, }, 12178 { 2079 /* vabd */, ARM::VABDuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, }, 12179 { 2079 /* vabd */, ARM::VABDuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, }, 12180 { 2079 /* vabd */, ARM::VABDuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, }, 12181 { 2079 /* vabd */, ARM::VABDuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, }, 12182 { 2079 /* vabd */, ARM::VABDuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, }, 12183 { 2079 /* vabd */, ARM::VABDfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 12184 { 2079 /* vabd */, ARM::VABDfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 12185 { 2079 /* vabd */, ARM::VABDhq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 12186 { 2079 /* vabd */, ARM::VABDhd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 12187 { 2079 /* vabd */, ARM::VABDsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12188 { 2079 /* vabd */, ARM::VABDsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12189 { 2079 /* vabd */, ARM::VABDsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12190 { 2079 /* vabd */, ARM::VABDsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12191 { 2079 /* vabd */, ARM::VABDsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12192 { 2079 /* vabd */, ARM::VABDsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12193 { 2079 /* vabd */, ARM::VABDuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12194 { 2079 /* vabd */, ARM::VABDuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12195 { 2079 /* vabd */, ARM::VABDuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12196 { 2079 /* vabd */, ARM::VABDuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12197 { 2079 /* vabd */, ARM::VABDuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12198 { 2079 /* vabd */, ARM::VABDuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12199 { 2079 /* vabd */, ARM::VABDfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12200 { 2079 /* vabd */, ARM::VABDfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12201 { 2079 /* vabd */, ARM::VABDhq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12202 { 2079 /* vabd */, ARM::VABDhd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12203 { 2079 /* vabd */, ARM::MVE_VABDs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 12204 { 2079 /* vabd */, ARM::MVE_VABDs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 12205 { 2079 /* vabd */, ARM::MVE_VABDs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 12206 { 2079 /* vabd */, ARM::MVE_VABDu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 12207 { 2079 /* vabd */, ARM::MVE_VABDu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 12208 { 2079 /* vabd */, ARM::MVE_VABDu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 12209 { 2079 /* vabd */, ARM::MVE_VABDf32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 12210 { 2079 /* vabd */, ARM::MVE_VABDf16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 12211 { 2084 /* vabdl */, ARM::VABDLsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, }, 12212 { 2084 /* vabdl */, ARM::VABDLsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, }, 12213 { 2084 /* vabdl */, ARM::VABDLsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR, MCK_DPR }, }, 12214 { 2084 /* vabdl */, ARM::VABDLuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR }, }, 12215 { 2084 /* vabdl */, ARM::VABDLuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR }, }, 12216 { 2084 /* vabdl */, ARM::VABDLuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR, MCK_DPR }, }, 12217 { 2090 /* vabs */, ARM::VABSv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 12218 { 2090 /* vabs */, ARM::VABSv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 12219 { 2090 /* vabs */, ARM::VABSv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 12220 { 2090 /* vabs */, ARM::VABSv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 12221 { 2090 /* vabs */, ARM::VABSv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, }, 12222 { 2090 /* vabs */, ARM::VABSv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 12223 { 2090 /* vabs */, ARM::VABSfq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 12224 { 2090 /* vabs */, ARM::VABSfd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 12225 { 2090 /* vabs */, ARM::VABSS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 12226 { 2090 /* vabs */, ARM::VABSD, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 12227 { 2090 /* vabs */, ARM::VABShq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 12228 { 2090 /* vabs */, ARM::VABShd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 12229 { 2090 /* vabs */, ARM::VABSH, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 12230 { 2090 /* vabs */, ARM::MVE_VABSs16, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, }, 12231 { 2090 /* vabs */, ARM::MVE_VABSs32, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, }, 12232 { 2090 /* vabs */, ARM::MVE_VABSs8, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR }, }, 12233 { 2090 /* vabs */, ARM::MVE_VABSf32, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, }, 12234 { 2090 /* vabs */, ARM::MVE_VABSf16, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, }, 12235 { 2095 /* vacge */, ARM::VACGEfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 12236 { 2095 /* vacge */, ARM::VACGEfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 12237 { 2095 /* vacge */, ARM::VACGEhq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 12238 { 2095 /* vacge */, ARM::VACGEhd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 12239 { 2095 /* vacge */, ARM::VACGEfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12240 { 2095 /* vacge */, ARM::VACGEfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12241 { 2095 /* vacge */, ARM::VACGEhq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12242 { 2095 /* vacge */, ARM::VACGEhd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12243 { 2101 /* vacgt */, ARM::VACGTfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 12244 { 2101 /* vacgt */, ARM::VACGTfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 12245 { 2101 /* vacgt */, ARM::VACGThq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 12246 { 2101 /* vacgt */, ARM::VACGThd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 12247 { 2101 /* vacgt */, ARM::VACGTfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12248 { 2101 /* vacgt */, ARM::VACGTfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12249 { 2101 /* vacgt */, ARM::VACGThq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12250 { 2101 /* vacgt */, ARM::VACGThd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12251 { 2107 /* vacle */, ARM::VACGEfq, Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 12252 { 2107 /* vacle */, ARM::VACGEfd, Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 12253 { 2107 /* vacle */, ARM::VACGEhq, Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 12254 { 2107 /* vacle */, ARM::VACGEhd, Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 12255 { 2107 /* vacle */, ARM::VACGEfq, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12256 { 2107 /* vacle */, ARM::VACGEfd, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12257 { 2107 /* vacle */, ARM::VACGEhq, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12258 { 2107 /* vacle */, ARM::VACGEhd, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12259 { 2113 /* vaclt */, ARM::VACGTfq, Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 12260 { 2113 /* vaclt */, ARM::VACGTfd, Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 12261 { 2113 /* vaclt */, ARM::VACGThq, Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 12262 { 2113 /* vaclt */, ARM::VACGThd, Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 12263 { 2113 /* vaclt */, ARM::VACGTfq, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12264 { 2113 /* vaclt */, ARM::VACGTfd, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12265 { 2113 /* vaclt */, ARM::VACGThq, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12266 { 2113 /* vaclt */, ARM::VACGThd, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12267 { 2119 /* vadc */, ARM::MVE_VADC, Convert__Reg1_2__imm_95_0__Reg1_3__Reg1_4__imm_95_0__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 12268 { 2124 /* vadci */, ARM::MVE_VADCI, Convert__Reg1_2__imm_95_0__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 12269 { 2130 /* vadd */, ARM::VADDfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 12270 { 2130 /* vadd */, ARM::VADDfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 12271 { 2130 /* vadd */, ARM::VADDS, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 12272 { 2130 /* vadd */, ARM::VADDD, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 12273 { 2130 /* vadd */, ARM::VADDv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR }, }, 12274 { 2130 /* vadd */, ARM::VADDv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR }, }, 12275 { 2130 /* vadd */, ARM::VADDv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR }, }, 12276 { 2130 /* vadd */, ARM::VADDv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR }, }, 12277 { 2130 /* vadd */, ARM::VADDv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_QPR }, }, 12278 { 2130 /* vadd */, ARM::VADDv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_DPR }, }, 12279 { 2130 /* vadd */, ARM::VADDv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR }, }, 12280 { 2130 /* vadd */, ARM::VADDv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR }, }, 12281 { 2130 /* vadd */, ARM::VADDhq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 12282 { 2130 /* vadd */, ARM::VADDhd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 12283 { 2130 /* vadd */, ARM::VADDH, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 12284 { 2130 /* vadd */, ARM::VADDfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12285 { 2130 /* vadd */, ARM::VADDfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12286 { 2130 /* vadd */, ARM::VADDS, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, }, 12287 { 2130 /* vadd */, ARM::VADDD, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12288 { 2130 /* vadd */, ARM::VADDv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12289 { 2130 /* vadd */, ARM::VADDv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12290 { 2130 /* vadd */, ARM::VADDv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12291 { 2130 /* vadd */, ARM::VADDv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12292 { 2130 /* vadd */, ARM::VADDv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12293 { 2130 /* vadd */, ARM::VADDv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12294 { 2130 /* vadd */, ARM::VADDv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12295 { 2130 /* vadd */, ARM::VADDv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12296 { 2130 /* vadd */, ARM::VADDhq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12297 { 2130 /* vadd */, ARM::VADDhd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12298 { 2130 /* vadd */, ARM::VADDH, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, }, 12299 { 2130 /* vadd */, ARM::MVE_VADDf32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 12300 { 2130 /* vadd */, ARM::MVE_VADD_qr_f32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 12301 { 2130 /* vadd */, ARM::MVE_VADDi16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 12302 { 2130 /* vadd */, ARM::MVE_VADD_qr_i16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 12303 { 2130 /* vadd */, ARM::MVE_VADDi32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 12304 { 2130 /* vadd */, ARM::MVE_VADD_qr_i32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 12305 { 2130 /* vadd */, ARM::MVE_VADDi8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 12306 { 2130 /* vadd */, ARM::MVE_VADD_qr_i8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 12307 { 2130 /* vadd */, ARM::MVE_VADDf16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 12308 { 2130 /* vadd */, ARM::MVE_VADD_qr_f16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 12309 { 2135 /* vaddhn */, ARM::VADDHNv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_QPR, MCK_QPR }, }, 12310 { 2135 /* vaddhn */, ARM::VADDHNv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_QPR, MCK_QPR }, }, 12311 { 2135 /* vaddhn */, ARM::VADDHNv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_QPR, MCK_QPR }, }, 12312 { 2142 /* vaddl */, ARM::VADDLsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, }, 12313 { 2142 /* vaddl */, ARM::VADDLsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, }, 12314 { 2142 /* vaddl */, ARM::VADDLsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR, MCK_DPR }, }, 12315 { 2142 /* vaddl */, ARM::VADDLuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR }, }, 12316 { 2142 /* vaddl */, ARM::VADDLuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR }, }, 12317 { 2142 /* vaddl */, ARM::VADDLuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR, MCK_DPR }, }, 12318 { 2148 /* vaddlv */, ARM::MVE_VADDLVs32no_acc, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR }, }, 12319 { 2148 /* vaddlv */, ARM::MVE_VADDLVu32no_acc, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR }, }, 12320 { 2155 /* vaddlva */, ARM::MVE_VADDLVs32acc, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR }, }, 12321 { 2155 /* vaddlva */, ARM::MVE_VADDLVu32acc, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR }, }, 12322 { 2163 /* vaddv */, ARM::MVE_VADDVs16no_acc, Convert__Reg1_2__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_MQPR }, }, 12323 { 2163 /* vaddv */, ARM::MVE_VADDVs32no_acc, Convert__Reg1_2__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR }, }, 12324 { 2163 /* vaddv */, ARM::MVE_VADDVs8no_acc, Convert__Reg1_2__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_tGPREven, MCK_MQPR }, }, 12325 { 2163 /* vaddv */, ARM::MVE_VADDVu16no_acc, Convert__Reg1_2__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_tGPREven, MCK_MQPR }, }, 12326 { 2163 /* vaddv */, ARM::MVE_VADDVu32no_acc, Convert__Reg1_2__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_MQPR }, }, 12327 { 2163 /* vaddv */, ARM::MVE_VADDVu8no_acc, Convert__Reg1_2__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_tGPREven, MCK_MQPR }, }, 12328 { 2169 /* vaddva */, ARM::MVE_VADDVs16acc, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_MQPR }, }, 12329 { 2169 /* vaddva */, ARM::MVE_VADDVs32acc, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR }, }, 12330 { 2169 /* vaddva */, ARM::MVE_VADDVs8acc, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_tGPREven, MCK_MQPR }, }, 12331 { 2169 /* vaddva */, ARM::MVE_VADDVu16acc, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_tGPREven, MCK_MQPR }, }, 12332 { 2169 /* vaddva */, ARM::MVE_VADDVu32acc, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_MQPR }, }, 12333 { 2169 /* vaddva */, ARM::MVE_VADDVu8acc, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_tGPREven, MCK_MQPR }, }, 12334 { 2176 /* vaddw */, ARM::VADDWsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR }, }, 12335 { 2176 /* vaddw */, ARM::VADDWsv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR }, }, 12336 { 2176 /* vaddw */, ARM::VADDWsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR }, }, 12337 { 2176 /* vaddw */, ARM::VADDWuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR }, }, 12338 { 2176 /* vaddw */, ARM::VADDWuv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR }, }, 12339 { 2176 /* vaddw */, ARM::VADDWuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR }, }, 12340 { 2176 /* vaddw */, ARM::VADDWsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_DPR }, }, 12341 { 2176 /* vaddw */, ARM::VADDWsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_DPR }, }, 12342 { 2176 /* vaddw */, ARM::VADDWsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_DPR }, }, 12343 { 2176 /* vaddw */, ARM::VADDWuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_DPR }, }, 12344 { 2176 /* vaddw */, ARM::VADDWuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_DPR }, }, 12345 { 2176 /* vaddw */, ARM::VADDWuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_DPR }, }, 12346 { 2182 /* vand */, ARM::VANDq, Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR }, }, 12347 { 2182 /* vand */, ARM::VANDd, Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR }, }, 12348 { 2182 /* vand */, ARM::VBICiv8i16, Convert__Reg1_2__NEONi16splatNot1_3__Tie0_3_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_NEONi16splatNot }, }, 12349 { 2182 /* vand */, ARM::VBICiv4i16, Convert__Reg1_2__NEONi16splatNot1_3__Tie0_3_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_NEONi16splatNot }, }, 12350 { 2182 /* vand */, ARM::VBICiv4i32, Convert__Reg1_2__NEONi32splatNot1_3__Tie0_3_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32splatNot }, }, 12351 { 2182 /* vand */, ARM::VBICiv2i32, Convert__Reg1_2__NEONi32splatNot1_3__Tie0_3_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32splatNot }, }, 12352 { 2182 /* vand */, ARM::VANDq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, }, 12353 { 2182 /* vand */, ARM::VANDd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, }, 12354 { 2182 /* vand */, ARM::VANDq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, }, 12355 { 2182 /* vand */, ARM::VANDd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, }, 12356 { 2182 /* vand */, ARM::VANDq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR }, }, 12357 { 2182 /* vand */, ARM::VANDd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR }, }, 12358 { 2182 /* vand */, ARM::VANDq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, }, 12359 { 2182 /* vand */, ARM::VANDd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, }, 12360 { 2182 /* vand */, ARM::VANDq, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12361 { 2182 /* vand */, ARM::VANDd, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12362 { 2182 /* vand */, ARM::MVE_VBICimmi16, Convert__Reg1_2__Tie0_3_3__NEONi16splatNot1_3__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_i16, MCK_MQPR, MCK_NEONi16splatNot }, }, 12363 { 2182 /* vand */, ARM::MVE_VBICimmi32, Convert__Reg1_2__Tie0_3_3__NEONi32splatNot1_3__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_NEONi32splatNot }, }, 12364 { 2182 /* vand */, ARM::MVE_VAND, Convert__Reg1_1__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 12365 { 2182 /* vand */, ARM::VANDq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12366 { 2182 /* vand */, ARM::VANDd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12367 { 2182 /* vand */, ARM::VANDq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12368 { 2182 /* vand */, ARM::VANDd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12369 { 2182 /* vand */, ARM::VANDq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12370 { 2182 /* vand */, ARM::VANDd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12371 { 2182 /* vand */, ARM::VANDq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12372 { 2182 /* vand */, ARM::VANDd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12373 { 2182 /* vand */, ARM::MVE_VAND, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 12374 { 2182 /* vand */, ARM::MVE_VAND, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 12375 { 2182 /* vand */, ARM::MVE_VAND, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 12376 { 2182 /* vand */, ARM::MVE_VAND, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 12377 { 2182 /* vand */, ARM::MVE_VAND, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 12378 { 2182 /* vand */, ARM::MVE_VAND, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 12379 { 2182 /* vand */, ARM::MVE_VAND, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 12380 { 2182 /* vand */, ARM::MVE_VAND, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 12381 { 2182 /* vand */, ARM::MVE_VAND, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 12382 { 2182 /* vand */, ARM::MVE_VAND, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 12383 { 2182 /* vand */, ARM::MVE_VAND, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 12384 { 2187 /* vbic */, ARM::VBICq, Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR }, }, 12385 { 2187 /* vbic */, ARM::VBICd, Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR }, }, 12386 { 2187 /* vbic */, ARM::VBICiv8i16, Convert__Reg1_2__NEONi16splat1_3__Tie0_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_NEONi16splat }, }, 12387 { 2187 /* vbic */, ARM::VBICiv4i16, Convert__Reg1_2__NEONi16splat1_3__Tie0_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_NEONi16splat }, }, 12388 { 2187 /* vbic */, ARM::VBICiv4i32, Convert__Reg1_2__NEONi32splat1_3__Tie0_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32splat }, }, 12389 { 2187 /* vbic */, ARM::VBICiv2i32, Convert__Reg1_2__NEONi32splat1_3__Tie0_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32splat }, }, 12390 { 2187 /* vbic */, ARM::VBICq, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12391 { 2187 /* vbic */, ARM::VBICd, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12392 { 2187 /* vbic */, ARM::MVE_VBICimmi16, Convert__Reg1_2__Tie0_1_1__NEONi16splat1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i16, MCK_MQPR, MCK_NEONi16splat }, }, 12393 { 2187 /* vbic */, ARM::MVE_VBICimmi32, Convert__Reg1_2__Tie0_1_1__NEONi32splat1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_NEONi32splat }, }, 12394 { 2187 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_1__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 12395 { 2187 /* vbic */, ARM::VBICq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12396 { 2187 /* vbic */, ARM::VBICd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12397 { 2187 /* vbic */, ARM::VBICq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12398 { 2187 /* vbic */, ARM::VBICd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12399 { 2187 /* vbic */, ARM::VBICq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12400 { 2187 /* vbic */, ARM::VBICd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12401 { 2187 /* vbic */, ARM::VBICq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12402 { 2187 /* vbic */, ARM::VBICd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12403 { 2187 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 12404 { 2187 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 12405 { 2187 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 12406 { 2187 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 12407 { 2187 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 12408 { 2187 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 12409 { 2187 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 12410 { 2187 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 12411 { 2187 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 12412 { 2187 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 12413 { 2187 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 12414 { 2192 /* vbif */, ARM::VBIFq, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12415 { 2192 /* vbif */, ARM::VBIFd, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12416 { 2192 /* vbif */, ARM::VBIFq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12417 { 2192 /* vbif */, ARM::VBIFd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12418 { 2192 /* vbif */, ARM::VBIFq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12419 { 2192 /* vbif */, ARM::VBIFd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12420 { 2192 /* vbif */, ARM::VBIFq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12421 { 2192 /* vbif */, ARM::VBIFd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12422 { 2192 /* vbif */, ARM::VBIFq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12423 { 2192 /* vbif */, ARM::VBIFd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12424 { 2197 /* vbit */, ARM::VBITq, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12425 { 2197 /* vbit */, ARM::VBITd, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12426 { 2197 /* vbit */, ARM::VBITq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12427 { 2197 /* vbit */, ARM::VBITd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12428 { 2197 /* vbit */, ARM::VBITq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12429 { 2197 /* vbit */, ARM::VBITd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12430 { 2197 /* vbit */, ARM::VBITq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12431 { 2197 /* vbit */, ARM::VBITd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12432 { 2197 /* vbit */, ARM::VBITq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12433 { 2197 /* vbit */, ARM::VBITd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12434 { 2202 /* vbrsr */, ARM::MVE_VBRSR16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 12435 { 2202 /* vbrsr */, ARM::MVE_VBRSR32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 12436 { 2202 /* vbrsr */, ARM::MVE_VBRSR8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 12437 { 2208 /* vbsl */, ARM::VBSLq, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12438 { 2208 /* vbsl */, ARM::VBSLd, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12439 { 2208 /* vbsl */, ARM::VBSLq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12440 { 2208 /* vbsl */, ARM::VBSLd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12441 { 2208 /* vbsl */, ARM::VBSLq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12442 { 2208 /* vbsl */, ARM::VBSLd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12443 { 2208 /* vbsl */, ARM::VBSLq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12444 { 2208 /* vbsl */, ARM::VBSLd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12445 { 2208 /* vbsl */, ARM::VBSLq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12446 { 2208 /* vbsl */, ARM::VBSLd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12447 { 2213 /* vcadd */, ARM::VCADDv4f32, Convert__Reg1_1__Reg1_2__Reg1_3__ComplexRotationOdd1_4, AMFBS_HasNEON_HasV8_3a, { MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR, MCK_ComplexRotationOdd }, }, 12448 { 2213 /* vcadd */, ARM::VCADDv2f32, Convert__Reg1_1__Reg1_2__Reg1_3__ComplexRotationOdd1_4, AMFBS_HasNEON_HasV8_3a, { MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR, MCK_ComplexRotationOdd }, }, 12449 { 2213 /* vcadd */, ARM::VCADDv8f16, Convert__Reg1_1__Reg1_2__Reg1_3__ComplexRotationOdd1_4, AMFBS_HasNEON_HasV8_3a_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR, MCK_ComplexRotationOdd }, }, 12450 { 2213 /* vcadd */, ARM::VCADDv4f16, Convert__Reg1_1__Reg1_2__Reg1_3__ComplexRotationOdd1_4, AMFBS_HasNEON_HasV8_3a_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR, MCK_ComplexRotationOdd }, }, 12451 { 2213 /* vcadd */, ARM::MVE_VCADDf32, Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationOdd1_5__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationOdd }, }, 12452 { 2213 /* vcadd */, ARM::MVE_VCADDi16, Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationOdd1_5__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationOdd }, }, 12453 { 2213 /* vcadd */, ARM::MVE_VCADDi32, Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationOdd1_5__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationOdd }, }, 12454 { 2213 /* vcadd */, ARM::MVE_VCADDi8, Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationOdd1_5__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationOdd }, }, 12455 { 2213 /* vcadd */, ARM::MVE_VCADDf16, Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationOdd1_5__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationOdd }, }, 12456 { 2219 /* vceq */, ARM::VCEQzv4f32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK__HASH_0 }, }, 12457 { 2219 /* vceq */, ARM::VCEQfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 12458 { 2219 /* vceq */, ARM::VCEQzv2f32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK__HASH_0 }, }, 12459 { 2219 /* vceq */, ARM::VCEQfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 12460 { 2219 /* vceq */, ARM::VCEQzv8i16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK__HASH_0 }, }, 12461 { 2219 /* vceq */, ARM::VCEQv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR }, }, 12462 { 2219 /* vceq */, ARM::VCEQzv4i16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK__HASH_0 }, }, 12463 { 2219 /* vceq */, ARM::VCEQv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR }, }, 12464 { 2219 /* vceq */, ARM::VCEQzv4i32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK__HASH_0 }, }, 12465 { 2219 /* vceq */, ARM::VCEQv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR }, }, 12466 { 2219 /* vceq */, ARM::VCEQzv2i32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK__HASH_0 }, }, 12467 { 2219 /* vceq */, ARM::VCEQv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR }, }, 12468 { 2219 /* vceq */, ARM::VCEQzv16i8, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK__HASH_0 }, }, 12469 { 2219 /* vceq */, ARM::VCEQv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR }, }, 12470 { 2219 /* vceq */, ARM::VCEQzv8i8, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK__HASH_0 }, }, 12471 { 2219 /* vceq */, ARM::VCEQv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR }, }, 12472 { 2219 /* vceq */, ARM::VCEQzv8f16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK__HASH_0 }, }, 12473 { 2219 /* vceq */, ARM::VCEQhq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 12474 { 2219 /* vceq */, ARM::VCEQzv4f16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK__HASH_0 }, }, 12475 { 2219 /* vceq */, ARM::VCEQhd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 12476 { 2219 /* vceq */, ARM::VCEQzv4f32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, }, 12477 { 2219 /* vceq */, ARM::VCEQfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12478 { 2219 /* vceq */, ARM::VCEQzv2f32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, }, 12479 { 2219 /* vceq */, ARM::VCEQfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12480 { 2219 /* vceq */, ARM::VCEQzv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, }, 12481 { 2219 /* vceq */, ARM::VCEQv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12482 { 2219 /* vceq */, ARM::VCEQzv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, }, 12483 { 2219 /* vceq */, ARM::VCEQv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12484 { 2219 /* vceq */, ARM::VCEQzv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, }, 12485 { 2219 /* vceq */, ARM::VCEQv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12486 { 2219 /* vceq */, ARM::VCEQzv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, }, 12487 { 2219 /* vceq */, ARM::VCEQv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12488 { 2219 /* vceq */, ARM::VCEQzv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR, MCK__HASH_0 }, }, 12489 { 2219 /* vceq */, ARM::VCEQv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12490 { 2219 /* vceq */, ARM::VCEQzv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR, MCK__HASH_0 }, }, 12491 { 2219 /* vceq */, ARM::VCEQv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12492 { 2219 /* vceq */, ARM::VCEQzv8f16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, }, 12493 { 2219 /* vceq */, ARM::VCEQhq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12494 { 2219 /* vceq */, ARM::VCEQzv4f16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, }, 12495 { 2219 /* vceq */, ARM::VCEQhd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12496 { 2224 /* vcge */, ARM::VCGEzv8i16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK__HASH_0 }, }, 12497 { 2224 /* vcge */, ARM::VCGEsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 12498 { 2224 /* vcge */, ARM::VCGEzv4i16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK__HASH_0 }, }, 12499 { 2224 /* vcge */, ARM::VCGEsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 12500 { 2224 /* vcge */, ARM::VCGEzv4i32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK__HASH_0 }, }, 12501 { 2224 /* vcge */, ARM::VCGEsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 12502 { 2224 /* vcge */, ARM::VCGEzv2i32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK__HASH_0 }, }, 12503 { 2224 /* vcge */, ARM::VCGEsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 12504 { 2224 /* vcge */, ARM::VCGEzv16i8, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK__HASH_0 }, }, 12505 { 2224 /* vcge */, ARM::VCGEsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, }, 12506 { 2224 /* vcge */, ARM::VCGEzv8i8, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK__HASH_0 }, }, 12507 { 2224 /* vcge */, ARM::VCGEsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 12508 { 2224 /* vcge */, ARM::VCGEuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, }, 12509 { 2224 /* vcge */, ARM::VCGEuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, }, 12510 { 2224 /* vcge */, ARM::VCGEuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, }, 12511 { 2224 /* vcge */, ARM::VCGEuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, }, 12512 { 2224 /* vcge */, ARM::VCGEuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, }, 12513 { 2224 /* vcge */, ARM::VCGEuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, }, 12514 { 2224 /* vcge */, ARM::VCGEzv4f32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK__HASH_0 }, }, 12515 { 2224 /* vcge */, ARM::VCGEfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 12516 { 2224 /* vcge */, ARM::VCGEzv2f32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK__HASH_0 }, }, 12517 { 2224 /* vcge */, ARM::VCGEfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 12518 { 2224 /* vcge */, ARM::VCGEzv8f16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK__HASH_0 }, }, 12519 { 2224 /* vcge */, ARM::VCGEhq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 12520 { 2224 /* vcge */, ARM::VCGEzv4f16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK__HASH_0 }, }, 12521 { 2224 /* vcge */, ARM::VCGEhd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 12522 { 2224 /* vcge */, ARM::VCGEzv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, }, 12523 { 2224 /* vcge */, ARM::VCGEsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12524 { 2224 /* vcge */, ARM::VCGEzv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, }, 12525 { 2224 /* vcge */, ARM::VCGEsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12526 { 2224 /* vcge */, ARM::VCGEzv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, }, 12527 { 2224 /* vcge */, ARM::VCGEsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12528 { 2224 /* vcge */, ARM::VCGEzv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, }, 12529 { 2224 /* vcge */, ARM::VCGEsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12530 { 2224 /* vcge */, ARM::VCGEzv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK__HASH_0 }, }, 12531 { 2224 /* vcge */, ARM::VCGEsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12532 { 2224 /* vcge */, ARM::VCGEzv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK__HASH_0 }, }, 12533 { 2224 /* vcge */, ARM::VCGEsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12534 { 2224 /* vcge */, ARM::VCGEuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12535 { 2224 /* vcge */, ARM::VCGEuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12536 { 2224 /* vcge */, ARM::VCGEuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12537 { 2224 /* vcge */, ARM::VCGEuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12538 { 2224 /* vcge */, ARM::VCGEuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12539 { 2224 /* vcge */, ARM::VCGEuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12540 { 2224 /* vcge */, ARM::VCGEzv4f32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, }, 12541 { 2224 /* vcge */, ARM::VCGEfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12542 { 2224 /* vcge */, ARM::VCGEzv2f32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, }, 12543 { 2224 /* vcge */, ARM::VCGEfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12544 { 2224 /* vcge */, ARM::VCGEzv8f16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, }, 12545 { 2224 /* vcge */, ARM::VCGEhq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12546 { 2224 /* vcge */, ARM::VCGEzv4f16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, }, 12547 { 2224 /* vcge */, ARM::VCGEhd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12548 { 2229 /* vcgt */, ARM::VCGTzv8i16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK__HASH_0 }, }, 12549 { 2229 /* vcgt */, ARM::VCGTsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 12550 { 2229 /* vcgt */, ARM::VCGTzv4i16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK__HASH_0 }, }, 12551 { 2229 /* vcgt */, ARM::VCGTsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 12552 { 2229 /* vcgt */, ARM::VCGTzv4i32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK__HASH_0 }, }, 12553 { 2229 /* vcgt */, ARM::VCGTsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 12554 { 2229 /* vcgt */, ARM::VCGTzv2i32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK__HASH_0 }, }, 12555 { 2229 /* vcgt */, ARM::VCGTsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 12556 { 2229 /* vcgt */, ARM::VCGTzv16i8, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK__HASH_0 }, }, 12557 { 2229 /* vcgt */, ARM::VCGTsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, }, 12558 { 2229 /* vcgt */, ARM::VCGTzv8i8, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK__HASH_0 }, }, 12559 { 2229 /* vcgt */, ARM::VCGTsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 12560 { 2229 /* vcgt */, ARM::VCGTuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, }, 12561 { 2229 /* vcgt */, ARM::VCGTuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, }, 12562 { 2229 /* vcgt */, ARM::VCGTuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, }, 12563 { 2229 /* vcgt */, ARM::VCGTuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, }, 12564 { 2229 /* vcgt */, ARM::VCGTuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, }, 12565 { 2229 /* vcgt */, ARM::VCGTuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, }, 12566 { 2229 /* vcgt */, ARM::VCGTzv4f32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK__HASH_0 }, }, 12567 { 2229 /* vcgt */, ARM::VCGTfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 12568 { 2229 /* vcgt */, ARM::VCGTzv2f32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK__HASH_0 }, }, 12569 { 2229 /* vcgt */, ARM::VCGTfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 12570 { 2229 /* vcgt */, ARM::VCGTzv8f16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK__HASH_0 }, }, 12571 { 2229 /* vcgt */, ARM::VCGThq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 12572 { 2229 /* vcgt */, ARM::VCGTzv4f16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK__HASH_0 }, }, 12573 { 2229 /* vcgt */, ARM::VCGThd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 12574 { 2229 /* vcgt */, ARM::VCGTzv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, }, 12575 { 2229 /* vcgt */, ARM::VCGTsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12576 { 2229 /* vcgt */, ARM::VCGTzv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, }, 12577 { 2229 /* vcgt */, ARM::VCGTsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12578 { 2229 /* vcgt */, ARM::VCGTzv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, }, 12579 { 2229 /* vcgt */, ARM::VCGTsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12580 { 2229 /* vcgt */, ARM::VCGTzv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, }, 12581 { 2229 /* vcgt */, ARM::VCGTsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12582 { 2229 /* vcgt */, ARM::VCGTzv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK__HASH_0 }, }, 12583 { 2229 /* vcgt */, ARM::VCGTsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12584 { 2229 /* vcgt */, ARM::VCGTzv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK__HASH_0 }, }, 12585 { 2229 /* vcgt */, ARM::VCGTsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12586 { 2229 /* vcgt */, ARM::VCGTuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12587 { 2229 /* vcgt */, ARM::VCGTuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12588 { 2229 /* vcgt */, ARM::VCGTuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12589 { 2229 /* vcgt */, ARM::VCGTuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12590 { 2229 /* vcgt */, ARM::VCGTuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12591 { 2229 /* vcgt */, ARM::VCGTuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12592 { 2229 /* vcgt */, ARM::VCGTzv4f32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, }, 12593 { 2229 /* vcgt */, ARM::VCGTfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12594 { 2229 /* vcgt */, ARM::VCGTzv2f32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, }, 12595 { 2229 /* vcgt */, ARM::VCGTfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12596 { 2229 /* vcgt */, ARM::VCGTzv8f16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, }, 12597 { 2229 /* vcgt */, ARM::VCGThq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12598 { 2229 /* vcgt */, ARM::VCGTzv4f16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, }, 12599 { 2229 /* vcgt */, ARM::VCGThd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12600 { 2234 /* vcle */, ARM::VCLEzv8i16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK__HASH_0 }, }, 12601 { 2234 /* vcle */, ARM::VCLEzv4i16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK__HASH_0 }, }, 12602 { 2234 /* vcle */, ARM::VCLEzv4i32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK__HASH_0 }, }, 12603 { 2234 /* vcle */, ARM::VCLEzv2i32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK__HASH_0 }, }, 12604 { 2234 /* vcle */, ARM::VCLEzv16i8, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK__HASH_0 }, }, 12605 { 2234 /* vcle */, ARM::VCLEzv8i8, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK__HASH_0 }, }, 12606 { 2234 /* vcle */, ARM::VCLEzv4f32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK__HASH_0 }, }, 12607 { 2234 /* vcle */, ARM::VCLEzv2f32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK__HASH_0 }, }, 12608 { 2234 /* vcle */, ARM::VCLEzv8f16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK__HASH_0 }, }, 12609 { 2234 /* vcle */, ARM::VCLEzv4f16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK__HASH_0 }, }, 12610 { 2234 /* vcle */, ARM::VCLEzv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, }, 12611 { 2234 /* vcle */, ARM::VCGEsv8i16, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12612 { 2234 /* vcle */, ARM::VCLEzv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, }, 12613 { 2234 /* vcle */, ARM::VCGEsv4i16, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12614 { 2234 /* vcle */, ARM::VCLEzv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, }, 12615 { 2234 /* vcle */, ARM::VCGEsv4i32, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12616 { 2234 /* vcle */, ARM::VCLEzv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, }, 12617 { 2234 /* vcle */, ARM::VCGEsv2i32, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12618 { 2234 /* vcle */, ARM::VCLEzv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK__HASH_0 }, }, 12619 { 2234 /* vcle */, ARM::VCGEsv16i8, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12620 { 2234 /* vcle */, ARM::VCLEzv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK__HASH_0 }, }, 12621 { 2234 /* vcle */, ARM::VCGEsv8i8, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12622 { 2234 /* vcle */, ARM::VCGEuv8i16, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12623 { 2234 /* vcle */, ARM::VCGEuv4i16, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12624 { 2234 /* vcle */, ARM::VCGEuv4i32, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12625 { 2234 /* vcle */, ARM::VCGEuv2i32, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12626 { 2234 /* vcle */, ARM::VCGEuv16i8, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12627 { 2234 /* vcle */, ARM::VCGEuv8i8, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12628 { 2234 /* vcle */, ARM::VCLEzv4f32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, }, 12629 { 2234 /* vcle */, ARM::VCGEfq, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12630 { 2234 /* vcle */, ARM::VCLEzv2f32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, }, 12631 { 2234 /* vcle */, ARM::VCGEfd, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12632 { 2234 /* vcle */, ARM::VCLEzv8f16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, }, 12633 { 2234 /* vcle */, ARM::VCGEhq, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12634 { 2234 /* vcle */, ARM::VCLEzv4f16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, }, 12635 { 2234 /* vcle */, ARM::VCGEhd, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12636 { 2239 /* vcls */, ARM::VCLSv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 12637 { 2239 /* vcls */, ARM::VCLSv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 12638 { 2239 /* vcls */, ARM::VCLSv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 12639 { 2239 /* vcls */, ARM::VCLSv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 12640 { 2239 /* vcls */, ARM::VCLSv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, }, 12641 { 2239 /* vcls */, ARM::VCLSv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 12642 { 2239 /* vcls */, ARM::MVE_VCLSs16, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, }, 12643 { 2239 /* vcls */, ARM::MVE_VCLSs32, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, }, 12644 { 2239 /* vcls */, ARM::MVE_VCLSs8, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR }, }, 12645 { 2244 /* vclt */, ARM::VCLTzv8i16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK__HASH_0 }, }, 12646 { 2244 /* vclt */, ARM::VCLTzv4i16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK__HASH_0 }, }, 12647 { 2244 /* vclt */, ARM::VCLTzv4i32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK__HASH_0 }, }, 12648 { 2244 /* vclt */, ARM::VCLTzv2i32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK__HASH_0 }, }, 12649 { 2244 /* vclt */, ARM::VCLTzv16i8, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK__HASH_0 }, }, 12650 { 2244 /* vclt */, ARM::VCLTzv8i8, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK__HASH_0 }, }, 12651 { 2244 /* vclt */, ARM::VCLTzv4f32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK__HASH_0 }, }, 12652 { 2244 /* vclt */, ARM::VCLTzv2f32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK__HASH_0 }, }, 12653 { 2244 /* vclt */, ARM::VCLTzv8f16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK__HASH_0 }, }, 12654 { 2244 /* vclt */, ARM::VCLTzv4f16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK__HASH_0 }, }, 12655 { 2244 /* vclt */, ARM::VCLTzv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, }, 12656 { 2244 /* vclt */, ARM::VCGTsv8i16, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12657 { 2244 /* vclt */, ARM::VCLTzv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, }, 12658 { 2244 /* vclt */, ARM::VCGTsv4i16, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12659 { 2244 /* vclt */, ARM::VCLTzv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, }, 12660 { 2244 /* vclt */, ARM::VCGTsv4i32, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12661 { 2244 /* vclt */, ARM::VCLTzv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, }, 12662 { 2244 /* vclt */, ARM::VCGTsv2i32, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12663 { 2244 /* vclt */, ARM::VCLTzv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK__HASH_0 }, }, 12664 { 2244 /* vclt */, ARM::VCGTsv16i8, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12665 { 2244 /* vclt */, ARM::VCLTzv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK__HASH_0 }, }, 12666 { 2244 /* vclt */, ARM::VCGTsv8i8, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12667 { 2244 /* vclt */, ARM::VCGTuv8i16, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12668 { 2244 /* vclt */, ARM::VCGTuv4i16, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12669 { 2244 /* vclt */, ARM::VCGTuv4i32, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12670 { 2244 /* vclt */, ARM::VCGTuv2i32, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12671 { 2244 /* vclt */, ARM::VCGTuv16i8, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12672 { 2244 /* vclt */, ARM::VCGTuv8i8, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12673 { 2244 /* vclt */, ARM::VCLTzv4f32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, }, 12674 { 2244 /* vclt */, ARM::VCGTfq, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12675 { 2244 /* vclt */, ARM::VCLTzv2f32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, }, 12676 { 2244 /* vclt */, ARM::VCGTfd, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12677 { 2244 /* vclt */, ARM::VCLTzv8f16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, }, 12678 { 2244 /* vclt */, ARM::VCGThq, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12679 { 2244 /* vclt */, ARM::VCLTzv4f16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, }, 12680 { 2244 /* vclt */, ARM::VCGThd, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12681 { 2249 /* vclz */, ARM::VCLZv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR }, }, 12682 { 2249 /* vclz */, ARM::VCLZv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR }, }, 12683 { 2249 /* vclz */, ARM::VCLZv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR }, }, 12684 { 2249 /* vclz */, ARM::VCLZv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR }, }, 12685 { 2249 /* vclz */, ARM::VCLZv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR }, }, 12686 { 2249 /* vclz */, ARM::VCLZv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR }, }, 12687 { 2249 /* vclz */, ARM::MVE_VCLZs16, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR }, }, 12688 { 2249 /* vclz */, ARM::MVE_VCLZs32, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR }, }, 12689 { 2249 /* vclz */, ARM::MVE_VCLZs8, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR }, }, 12690 { 2254 /* vcmla */, ARM::VCMLAv4f32, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__ComplexRotationEven1_4, AMFBS_HasNEON_HasV8_3a, { MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR, MCK_ComplexRotationEven }, }, 12691 { 2254 /* vcmla */, ARM::VCMLAv2f32, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__ComplexRotationEven1_4, AMFBS_HasNEON_HasV8_3a, { MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR, MCK_ComplexRotationEven }, }, 12692 { 2254 /* vcmla */, ARM::VCMLAv8f16, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__ComplexRotationEven1_4, AMFBS_HasNEON_HasV8_3a_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR, MCK_ComplexRotationEven }, }, 12693 { 2254 /* vcmla */, ARM::VCMLAv4f16, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__ComplexRotationEven1_4, AMFBS_HasNEON_HasV8_3a_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR, MCK_ComplexRotationEven }, }, 12694 { 2254 /* vcmla */, ARM::VCMLAv4f32_indexed, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__VectorIndex641_4__ComplexRotationEven1_5, AMFBS_HasNEON_HasV8_3a, { MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_DPR, MCK_VectorIndex64, MCK_ComplexRotationEven }, }, 12695 { 2254 /* vcmla */, ARM::VCMLAv2f32_indexed, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__VectorIndex641_4__ComplexRotationEven1_5, AMFBS_HasNEON_HasV8_3a, { MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR, MCK_VectorIndex64, MCK_ComplexRotationEven }, }, 12696 { 2254 /* vcmla */, ARM::VCMLAv8f16_indexed, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__VectorIndex321_4__ComplexRotationEven1_5, AMFBS_HasNEON_HasV8_3a_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32, MCK_ComplexRotationEven }, }, 12697 { 2254 /* vcmla */, ARM::VCMLAv4f16_indexed, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__VectorIndex321_4__ComplexRotationEven1_5, AMFBS_HasNEON_HasV8_3a_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32, MCK_ComplexRotationEven }, }, 12698 { 2254 /* vcmla */, ARM::MVE_VCMLAf32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__ComplexRotationEven1_5__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationEven }, }, 12699 { 2254 /* vcmla */, ARM::MVE_VCMLAf16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__ComplexRotationEven1_5__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationEven }, }, 12700 { 2260 /* vcmp */, ARM::VCMPZS, Convert__Reg1_2__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK__HASH_0 }, }, 12701 { 2260 /* vcmp */, ARM::VCMPS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 12702 { 2260 /* vcmp */, ARM::VCMPZD, Convert__Reg1_2__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK__HASH_0 }, }, 12703 { 2260 /* vcmp */, ARM::VCMPD, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 12704 { 2260 /* vcmp */, ARM::VCMPZH, Convert__Reg1_2__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK__HASH_0 }, }, 12705 { 2260 /* vcmp */, ARM::VCMPH, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 12706 { 2260 /* vcmp */, ARM::MVE_VCMPs16, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_MQPR }, }, 12707 { 2260 /* vcmp */, ARM::MVE_VCMPs16r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_GPRwithZR }, }, 12708 { 2260 /* vcmp */, ARM::MVE_VCMPs32, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_MQPR }, }, 12709 { 2260 /* vcmp */, ARM::MVE_VCMPs32r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_GPRwithZR }, }, 12710 { 2260 /* vcmp */, ARM::MVE_VCMPs8, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_MQPR }, }, 12711 { 2260 /* vcmp */, ARM::MVE_VCMPs8r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_GPRwithZR }, }, 12712 { 2260 /* vcmp */, ARM::MVE_VCMPu16, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_CondCodeRestrictedU, MCK_MQPR, MCK_MQPR }, }, 12713 { 2260 /* vcmp */, ARM::MVE_VCMPu16r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_CondCodeRestrictedU, MCK_MQPR, MCK_GPRwithZR }, }, 12714 { 2260 /* vcmp */, ARM::MVE_VCMPu32, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_CondCodeRestrictedU, MCK_MQPR, MCK_MQPR }, }, 12715 { 2260 /* vcmp */, ARM::MVE_VCMPu32r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_CondCodeRestrictedU, MCK_MQPR, MCK_GPRwithZR }, }, 12716 { 2260 /* vcmp */, ARM::MVE_VCMPu8, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_CondCodeRestrictedU, MCK_MQPR, MCK_MQPR }, }, 12717 { 2260 /* vcmp */, ARM::MVE_VCMPu8r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_CondCodeRestrictedU, MCK_MQPR, MCK_GPRwithZR }, }, 12718 { 2260 /* vcmp */, ARM::MVE_VCMPf32, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedFP1_2__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f32, MCK_CondCodeRestrictedFP, MCK_MQPR, MCK_MQPR }, }, 12719 { 2260 /* vcmp */, ARM::MVE_VCMPf32r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedFP1_2__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f32, MCK_CondCodeRestrictedFP, MCK_MQPR, MCK_GPRwithZR }, }, 12720 { 2260 /* vcmp */, ARM::MVE_VCMPi16, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i16, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_MQPR }, }, 12721 { 2260 /* vcmp */, ARM::MVE_VCMPi16r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i16, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_GPRwithZR }, }, 12722 { 2260 /* vcmp */, ARM::MVE_VCMPi32, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_MQPR }, }, 12723 { 2260 /* vcmp */, ARM::MVE_VCMPi32r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_GPRwithZR }, }, 12724 { 2260 /* vcmp */, ARM::MVE_VCMPi8, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i8, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_MQPR }, }, 12725 { 2260 /* vcmp */, ARM::MVE_VCMPi8r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i8, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_GPRwithZR }, }, 12726 { 2260 /* vcmp */, ARM::MVE_VCMPf16, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedFP1_2__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK_CondCodeRestrictedFP, MCK_MQPR, MCK_MQPR }, }, 12727 { 2260 /* vcmp */, ARM::MVE_VCMPf16r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedFP1_2__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK_CondCodeRestrictedFP, MCK_MQPR, MCK_GPRwithZR }, }, 12728 { 2265 /* vcmpe */, ARM::VCMPEZS, Convert__Reg1_2__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK__HASH_0 }, }, 12729 { 2265 /* vcmpe */, ARM::VCMPES, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 12730 { 2265 /* vcmpe */, ARM::VCMPEZD, Convert__Reg1_2__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK__HASH_0 }, }, 12731 { 2265 /* vcmpe */, ARM::VCMPED, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 12732 { 2265 /* vcmpe */, ARM::VCMPEZH, Convert__Reg1_2__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK__HASH_0 }, }, 12733 { 2265 /* vcmpe */, ARM::VCMPEH, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 12734 { 2271 /* vcmul */, ARM::MVE_VCMULf32, Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationEven1_5__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationEven }, }, 12735 { 2271 /* vcmul */, ARM::MVE_VCMULf16, Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationEven1_5__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationEven }, }, 12736 { 2277 /* vcnt */, ARM::VCNTq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, }, 12737 { 2277 /* vcnt */, ARM::VCNTd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, }, 12738 { 2282 /* vctp */, ARM::MVE_VCTP16, Convert__imm_95_0__Reg1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_16, MCK_rGPR }, }, 12739 { 2282 /* vctp */, ARM::MVE_VCTP32, Convert__imm_95_0__Reg1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_rGPR }, }, 12740 { 2282 /* vctp */, ARM::MVE_VCTP64, Convert__imm_95_0__Reg1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_64, MCK_rGPR }, }, 12741 { 2282 /* vctp */, ARM::MVE_VCTP8, Convert__imm_95_0__Reg1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_8, MCK_rGPR }, }, 12742 { 2287 /* vcvt */, ARM::VCVTh2sq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 12743 { 2287 /* vcvt */, ARM::VCVTh2sd, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 12744 { 2287 /* vcvt */, ARM::VCVTf2sq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 12745 { 2287 /* vcvt */, ARM::VCVTf2sd, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 12746 { 2287 /* vcvt */, ARM::VTOSIZS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 12747 { 2287 /* vcvt */, ARM::VTOSIZD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, }, 12748 { 2287 /* vcvt */, ARM::VTOSIZH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 12749 { 2287 /* vcvt */, ARM::VCVTh2uq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 12750 { 2287 /* vcvt */, ARM::VCVTh2ud, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 12751 { 2287 /* vcvt */, ARM::VCVTf2uq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 12752 { 2287 /* vcvt */, ARM::VCVTf2ud, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 12753 { 2287 /* vcvt */, ARM::VTOUIZS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 12754 { 2287 /* vcvt */, ARM::VTOUIZD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, }, 12755 { 2287 /* vcvt */, ARM::VTOUIZH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 12756 { 2287 /* vcvt */, ARM::VCVTs2fq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 12757 { 2287 /* vcvt */, ARM::VCVTs2fd, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 12758 { 2287 /* vcvt */, ARM::VSITOS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_HPR, MCK_HPR }, }, 12759 { 2287 /* vcvt */, ARM::VCVTu2fq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u32, MCK_QPR, MCK_QPR }, }, 12760 { 2287 /* vcvt */, ARM::VCVTu2fd, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u32, MCK_DPR, MCK_DPR }, }, 12761 { 2287 /* vcvt */, ARM::VUITOS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u32, MCK_HPR, MCK_HPR }, }, 12762 { 2287 /* vcvt */, ARM::VCVTSD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, }, 12763 { 2287 /* vcvt */, ARM::VCVTh2f, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFP16, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_f16, MCK_QPR, MCK_DPR }, }, 12764 { 2287 /* vcvt */, ARM::VSITOD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_s32, MCK_DPR, MCK_HPR }, }, 12765 { 2287 /* vcvt */, ARM::VUITOD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_u32, MCK_DPR, MCK_HPR }, }, 12766 { 2287 /* vcvt */, ARM::VCVTDS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_f32, MCK_DPR, MCK_HPR }, }, 12767 { 2287 /* vcvt */, ARM::BF16_VCVT, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasBF16_HasNEON, { MCK_CondCode, MCK__DOT_bf16, MCK__DOT_f32, MCK_DPR, MCK_QPR }, }, 12768 { 2287 /* vcvt */, ARM::VCVTs2hq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 12769 { 2287 /* vcvt */, ARM::VCVTs2hd, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 12770 { 2287 /* vcvt */, ARM::VSITOH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s32, MCK_HPR, MCK_HPR }, }, 12771 { 2287 /* vcvt */, ARM::VCVTu2hq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u16, MCK_QPR, MCK_QPR }, }, 12772 { 2287 /* vcvt */, ARM::VCVTu2hd, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u16, MCK_DPR, MCK_DPR }, }, 12773 { 2287 /* vcvt */, ARM::VUITOH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u32, MCK_HPR, MCK_HPR }, }, 12774 { 2287 /* vcvt */, ARM::VCVTf2h, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_f32, MCK_DPR, MCK_QPR }, }, 12775 { 2287 /* vcvt */, ARM::MVE_VCVTs16f16z, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, }, 12776 { 2287 /* vcvt */, ARM::MVE_VCVTs32f32z, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, }, 12777 { 2287 /* vcvt */, ARM::MVE_VCVTu16f16z, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, }, 12778 { 2287 /* vcvt */, ARM::MVE_VCVTu32f32z, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, }, 12779 { 2287 /* vcvt */, ARM::MVE_VCVTf32s32n, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, }, 12780 { 2287 /* vcvt */, ARM::MVE_VCVTf32u32n, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK__DOT_u32, MCK_MQPR, MCK_MQPR }, }, 12781 { 2287 /* vcvt */, ARM::MVE_VCVTf16s16n, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, }, 12782 { 2287 /* vcvt */, ARM::MVE_VCVTf16u16n, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK__DOT_u16, MCK_MQPR, MCK_MQPR }, }, 12783 { 2287 /* vcvt */, ARM::VTOSHS, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_FBits16 }, }, 12784 { 2287 /* vcvt */, ARM::VTOSHD, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_FBits16 }, }, 12785 { 2287 /* vcvt */, ARM::VCVTh2sq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, }, 12786 { 2287 /* vcvt */, ARM::VCVTh2xsq, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_Imm }, }, 12787 { 2287 /* vcvt */, ARM::VCVTh2sd, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, }, 12788 { 2287 /* vcvt */, ARM::VCVTh2xsd, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_Imm }, }, 12789 { 2287 /* vcvt */, ARM::VTOSHH, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_FBits16 }, }, 12790 { 2287 /* vcvt */, ARM::VCVTf2sq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, }, 12791 { 2287 /* vcvt */, ARM::VCVTf2xsq, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_Imm }, }, 12792 { 2287 /* vcvt */, ARM::VCVTf2sd, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, }, 12793 { 2287 /* vcvt */, ARM::VCVTf2xsd, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_Imm }, }, 12794 { 2287 /* vcvt */, ARM::VTOSLS, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_FBits32 }, }, 12795 { 2287 /* vcvt */, ARM::VTOSLD, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_FBits32 }, }, 12796 { 2287 /* vcvt */, ARM::VTOSLH, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_FBits32 }, }, 12797 { 2287 /* vcvt */, ARM::VTOUHS, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_FBits16 }, }, 12798 { 2287 /* vcvt */, ARM::VTOUHD, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_FBits16 }, }, 12799 { 2287 /* vcvt */, ARM::VCVTh2uq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, }, 12800 { 2287 /* vcvt */, ARM::VCVTh2xuq, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_Imm }, }, 12801 { 2287 /* vcvt */, ARM::VCVTh2ud, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, }, 12802 { 2287 /* vcvt */, ARM::VCVTh2xud, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_Imm }, }, 12803 { 2287 /* vcvt */, ARM::VTOUHH, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_FBits16 }, }, 12804 { 2287 /* vcvt */, ARM::VCVTf2uq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, }, 12805 { 2287 /* vcvt */, ARM::VCVTf2xuq, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_Imm }, }, 12806 { 2287 /* vcvt */, ARM::VCVTf2ud, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, }, 12807 { 2287 /* vcvt */, ARM::VCVTf2xud, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_Imm }, }, 12808 { 2287 /* vcvt */, ARM::VTOULS, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_FBits32 }, }, 12809 { 2287 /* vcvt */, ARM::VTOULD, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_FBits32 }, }, 12810 { 2287 /* vcvt */, ARM::VTOULH, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_FBits32 }, }, 12811 { 2287 /* vcvt */, ARM::VSHTOS, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s16, MCK_HPR, MCK_HPR, MCK_FBits16 }, }, 12812 { 2287 /* vcvt */, ARM::VCVTs2fq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, }, 12813 { 2287 /* vcvt */, ARM::VCVTxs2fq, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_Imm }, }, 12814 { 2287 /* vcvt */, ARM::VCVTs2fd, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, }, 12815 { 2287 /* vcvt */, ARM::VCVTxs2fd, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_Imm }, }, 12816 { 2287 /* vcvt */, ARM::VSLTOS, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_HPR, MCK_HPR, MCK_FBits32 }, }, 12817 { 2287 /* vcvt */, ARM::VUHTOS, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u16, MCK_HPR, MCK_HPR, MCK_FBits16 }, }, 12818 { 2287 /* vcvt */, ARM::VCVTu2fq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, }, 12819 { 2287 /* vcvt */, ARM::VCVTxu2fq, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_Imm }, }, 12820 { 2287 /* vcvt */, ARM::VCVTu2fd, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, }, 12821 { 2287 /* vcvt */, ARM::VCVTxu2fd, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_Imm }, }, 12822 { 2287 /* vcvt */, ARM::VULTOS, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u32, MCK_HPR, MCK_HPR, MCK_FBits32 }, }, 12823 { 2287 /* vcvt */, ARM::VSHTOD, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_FBits16 }, }, 12824 { 2287 /* vcvt */, ARM::VSLTOD, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_FBits32 }, }, 12825 { 2287 /* vcvt */, ARM::VUHTOD, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_FBits16 }, }, 12826 { 2287 /* vcvt */, ARM::VULTOD, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_FBits32 }, }, 12827 { 2287 /* vcvt */, ARM::VCVTs2hq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, }, 12828 { 2287 /* vcvt */, ARM::VCVTxs2hq, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_Imm }, }, 12829 { 2287 /* vcvt */, ARM::VCVTs2hd, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, }, 12830 { 2287 /* vcvt */, ARM::VCVTxs2hd, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_Imm }, }, 12831 { 2287 /* vcvt */, ARM::VSHTOH, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s16, MCK_HPR, MCK_HPR, MCK_FBits16 }, }, 12832 { 2287 /* vcvt */, ARM::VSLTOH, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s32, MCK_HPR, MCK_HPR, MCK_FBits32 }, }, 12833 { 2287 /* vcvt */, ARM::VCVTu2hq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, }, 12834 { 2287 /* vcvt */, ARM::VCVTxu2hq, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_Imm }, }, 12835 { 2287 /* vcvt */, ARM::VCVTu2hd, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, }, 12836 { 2287 /* vcvt */, ARM::VCVTxu2hd, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_Imm }, }, 12837 { 2287 /* vcvt */, ARM::VUHTOH, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u16, MCK_HPR, MCK_HPR, MCK_FBits16 }, }, 12838 { 2287 /* vcvt */, ARM::VULTOH, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u32, MCK_HPR, MCK_HPR, MCK_FBits32 }, }, 12839 { 2287 /* vcvt */, ARM::MVE_VCVTs16f16_fix, Convert__Reg1_3__Reg1_4__MVEVcvtImm161_5__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MVEVcvtImm16 }, }, 12840 { 2287 /* vcvt */, ARM::MVE_VCVTs32f32_fix, Convert__Reg1_3__Reg1_4__MVEVcvtImm321_5__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MVEVcvtImm32 }, }, 12841 { 2287 /* vcvt */, ARM::MVE_VCVTu16f16_fix, Convert__Reg1_3__Reg1_4__MVEVcvtImm161_5__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MVEVcvtImm16 }, }, 12842 { 2287 /* vcvt */, ARM::MVE_VCVTu32f32_fix, Convert__Reg1_3__Reg1_4__MVEVcvtImm321_5__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MVEVcvtImm32 }, }, 12843 { 2287 /* vcvt */, ARM::MVE_VCVTf32s32_fix, Convert__Reg1_3__Reg1_4__MVEVcvtImm321_5__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MVEVcvtImm32 }, }, 12844 { 2287 /* vcvt */, ARM::MVE_VCVTf32u32_fix, Convert__Reg1_3__Reg1_4__MVEVcvtImm321_5__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MVEVcvtImm32 }, }, 12845 { 2287 /* vcvt */, ARM::MVE_VCVTf16s16_fix, Convert__Reg1_3__Reg1_4__MVEVcvtImm161_5__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MVEVcvtImm16 }, }, 12846 { 2287 /* vcvt */, ARM::MVE_VCVTf16u16_fix, Convert__Reg1_3__Reg1_4__MVEVcvtImm161_5__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MVEVcvtImm16 }, }, 12847 { 2292 /* vcvta */, ARM::VCVTANSQh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_s16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 12848 { 2292 /* vcvta */, ARM::VCVTANSDh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_s16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 12849 { 2292 /* vcvta */, ARM::VCVTANSQf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_s32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 12850 { 2292 /* vcvta */, ARM::VCVTANSDf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_s32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 12851 { 2292 /* vcvta */, ARM::VCVTASS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 12852 { 2292 /* vcvta */, ARM::VCVTASD, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_s32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, }, 12853 { 2292 /* vcvta */, ARM::VCVTASH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 12854 { 2292 /* vcvta */, ARM::VCVTANUQh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_u16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 12855 { 2292 /* vcvta */, ARM::VCVTANUDh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_u16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 12856 { 2292 /* vcvta */, ARM::VCVTANUQf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_u32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 12857 { 2292 /* vcvta */, ARM::VCVTANUDf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_u32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 12858 { 2292 /* vcvta */, ARM::VCVTAUS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_u32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 12859 { 2292 /* vcvta */, ARM::VCVTAUD, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_u32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, }, 12860 { 2292 /* vcvta */, ARM::VCVTAUH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_u32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 12861 { 2292 /* vcvta */, ARM::MVE_VCVTs16f16a, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, }, 12862 { 2292 /* vcvta */, ARM::MVE_VCVTs32f32a, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, }, 12863 { 2292 /* vcvta */, ARM::MVE_VCVTu16f16a, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, }, 12864 { 2292 /* vcvta */, ARM::MVE_VCVTu32f32a, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, }, 12865 { 2298 /* vcvtb */, ARM::VCVTBHS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFP16, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 12866 { 2298 /* vcvtb */, ARM::VCVTBHD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPARMv8_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_f16, MCK_DPR, MCK_HPR }, }, 12867 { 2298 /* vcvtb */, ARM::BF16_VCVTB, Convert__Reg1_3__Tie0_1_1__Reg1_4__CondCode2_0, AMFBS_HasBF16, { MCK_CondCode, MCK__DOT_bf16, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 12868 { 2298 /* vcvtb */, ARM::VCVTBSH, Convert__Reg1_3__Tie0_1_1__Reg1_4__CondCode2_0, AMFBS_HasFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 12869 { 2298 /* vcvtb */, ARM::VCVTBDH, Convert__Reg1_3__Tie0_1_1__Reg1_4__CondCode2_0, AMFBS_HasFPARMv8_HasDPVFP, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_f64, MCK_HPR, MCK_DPR }, }, 12870 { 2298 /* vcvtb */, ARM::MVE_VCVTf16f32bh, Convert__Reg1_3__Tie0_1_1__Reg1_4__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, }, 12871 { 2298 /* vcvtb */, ARM::MVE_VCVTf32f16bh, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, }, 12872 { 2304 /* vcvtm */, ARM::VCVTMNSQh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_s16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 12873 { 2304 /* vcvtm */, ARM::VCVTMNSDh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_s16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 12874 { 2304 /* vcvtm */, ARM::VCVTMNSQf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_s32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 12875 { 2304 /* vcvtm */, ARM::VCVTMNSDf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_s32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 12876 { 2304 /* vcvtm */, ARM::VCVTMSS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 12877 { 2304 /* vcvtm */, ARM::VCVTMSD, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_s32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, }, 12878 { 2304 /* vcvtm */, ARM::VCVTMSH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 12879 { 2304 /* vcvtm */, ARM::VCVTMNUQh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_u16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 12880 { 2304 /* vcvtm */, ARM::VCVTMNUDh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_u16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 12881 { 2304 /* vcvtm */, ARM::VCVTMNUQf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_u32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 12882 { 2304 /* vcvtm */, ARM::VCVTMNUDf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_u32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 12883 { 2304 /* vcvtm */, ARM::VCVTMUS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_u32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 12884 { 2304 /* vcvtm */, ARM::VCVTMUD, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_u32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, }, 12885 { 2304 /* vcvtm */, ARM::VCVTMUH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_u32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 12886 { 2304 /* vcvtm */, ARM::MVE_VCVTs16f16m, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, }, 12887 { 2304 /* vcvtm */, ARM::MVE_VCVTs32f32m, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, }, 12888 { 2304 /* vcvtm */, ARM::MVE_VCVTu16f16m, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, }, 12889 { 2304 /* vcvtm */, ARM::MVE_VCVTu32f32m, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, }, 12890 { 2310 /* vcvtn */, ARM::VCVTNNSQh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_s16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 12891 { 2310 /* vcvtn */, ARM::VCVTNNSDh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_s16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 12892 { 2310 /* vcvtn */, ARM::VCVTNNSQf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_s32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 12893 { 2310 /* vcvtn */, ARM::VCVTNNSDf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_s32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 12894 { 2310 /* vcvtn */, ARM::VCVTNSS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 12895 { 2310 /* vcvtn */, ARM::VCVTNSD, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_s32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, }, 12896 { 2310 /* vcvtn */, ARM::VCVTNSH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 12897 { 2310 /* vcvtn */, ARM::VCVTNNUQh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_u16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 12898 { 2310 /* vcvtn */, ARM::VCVTNNUDh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_u16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 12899 { 2310 /* vcvtn */, ARM::VCVTNNUQf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_u32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 12900 { 2310 /* vcvtn */, ARM::VCVTNNUDf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_u32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 12901 { 2310 /* vcvtn */, ARM::VCVTNUS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_u32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 12902 { 2310 /* vcvtn */, ARM::VCVTNUD, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_u32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, }, 12903 { 2310 /* vcvtn */, ARM::VCVTNUH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_u32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 12904 { 2310 /* vcvtn */, ARM::MVE_VCVTs16f16n, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, }, 12905 { 2310 /* vcvtn */, ARM::MVE_VCVTs32f32n, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, }, 12906 { 2310 /* vcvtn */, ARM::MVE_VCVTu16f16n, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, }, 12907 { 2310 /* vcvtn */, ARM::MVE_VCVTu32f32n, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, }, 12908 { 2316 /* vcvtp */, ARM::VCVTPNSQh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_s16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 12909 { 2316 /* vcvtp */, ARM::VCVTPNSDh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_s16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 12910 { 2316 /* vcvtp */, ARM::VCVTPNSQf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_s32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 12911 { 2316 /* vcvtp */, ARM::VCVTPNSDf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_s32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 12912 { 2316 /* vcvtp */, ARM::VCVTPSS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 12913 { 2316 /* vcvtp */, ARM::VCVTPSD, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_s32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, }, 12914 { 2316 /* vcvtp */, ARM::VCVTPSH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 12915 { 2316 /* vcvtp */, ARM::VCVTPNUQh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_u16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 12916 { 2316 /* vcvtp */, ARM::VCVTPNUDh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_u16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 12917 { 2316 /* vcvtp */, ARM::VCVTPNUQf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_u32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 12918 { 2316 /* vcvtp */, ARM::VCVTPNUDf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_u32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 12919 { 2316 /* vcvtp */, ARM::VCVTPUS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_u32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 12920 { 2316 /* vcvtp */, ARM::VCVTPUD, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_u32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, }, 12921 { 2316 /* vcvtp */, ARM::VCVTPUH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_u32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 12922 { 2316 /* vcvtp */, ARM::MVE_VCVTs16f16p, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, }, 12923 { 2316 /* vcvtp */, ARM::MVE_VCVTs32f32p, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, }, 12924 { 2316 /* vcvtp */, ARM::MVE_VCVTu16f16p, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, }, 12925 { 2316 /* vcvtp */, ARM::MVE_VCVTu32f32p, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, }, 12926 { 2322 /* vcvtr */, ARM::VTOSIRS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 12927 { 2322 /* vcvtr */, ARM::VTOSIRD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, }, 12928 { 2322 /* vcvtr */, ARM::VTOSIRH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 12929 { 2322 /* vcvtr */, ARM::VTOUIRS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 12930 { 2322 /* vcvtr */, ARM::VTOUIRD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, }, 12931 { 2322 /* vcvtr */, ARM::VTOUIRH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 12932 { 2328 /* vcvtt */, ARM::VCVTTHS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFP16, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 12933 { 2328 /* vcvtt */, ARM::VCVTTHD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPARMv8_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_f16, MCK_DPR, MCK_HPR }, }, 12934 { 2328 /* vcvtt */, ARM::BF16_VCVTT, Convert__Reg1_3__Tie0_1_1__Reg1_4__CondCode2_0, AMFBS_HasBF16, { MCK_CondCode, MCK__DOT_bf16, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 12935 { 2328 /* vcvtt */, ARM::VCVTTSH, Convert__Reg1_3__Tie0_1_1__Reg1_4__CondCode2_0, AMFBS_HasFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 12936 { 2328 /* vcvtt */, ARM::VCVTTDH, Convert__Reg1_3__Tie0_1_1__Reg1_4__CondCode2_0, AMFBS_HasFPARMv8_HasDPVFP, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_f64, MCK_HPR, MCK_DPR }, }, 12937 { 2328 /* vcvtt */, ARM::MVE_VCVTf16f32th, Convert__Reg1_3__Tie0_1_1__Reg1_4__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, }, 12938 { 2328 /* vcvtt */, ARM::MVE_VCVTf32f16th, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, }, 12939 { 2334 /* vcx1 */, ARM::CDE_VCX1_fpdp, Convert__Reg1_1__CoprocNum1_0__Imm11b1_2, AMFBS_HasCDE_HasFPRegs, { MCK_CoprocNum, MCK_DPR_VFP2, MCK_Imm11b }, }, 12940 { 2334 /* vcx1 */, ARM::CDE_VCX1_fpsp, Convert__Reg1_1__CoprocNum1_0__Imm11b1_2, AMFBS_HasCDE_HasFPRegs, { MCK_CoprocNum, MCK_HPR, MCK_Imm11b }, }, 12941 { 2334 /* vcx1 */, ARM::CDE_VCX1_vec, Convert__Reg1_2__CoprocNum1_1__Imm12b1_3__VPTPredR4_0, AMFBS_HasCDE_HasMVEInt, { MCK_VPTPredR, MCK_CoprocNum, MCK_MQPR, MCK_Imm12b }, }, 12942 { 2339 /* vcx1a */, ARM::CDE_VCX1A_fpdp, Convert__Reg1_1__CoprocNum1_0__Tie0_1_1__Imm11b1_2, AMFBS_HasCDE_HasFPRegs, { MCK_CoprocNum, MCK_DPR_VFP2, MCK_Imm11b }, }, 12943 { 2339 /* vcx1a */, ARM::CDE_VCX1A_fpsp, Convert__Reg1_1__CoprocNum1_0__Tie0_1_1__Imm11b1_2, AMFBS_HasCDE_HasFPRegs, { MCK_CoprocNum, MCK_HPR, MCK_Imm11b }, }, 12944 { 2339 /* vcx1a */, ARM::CDE_VCX1A_vec, Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Imm12b1_3__VPTPredN3_0, AMFBS_HasCDE_HasMVEInt, { MCK_VPTPredN, MCK_CoprocNum, MCK_MQPR, MCK_Imm12b }, }, 12945 { 2345 /* vcx2 */, ARM::CDE_VCX2_fpdp, Convert__Reg1_1__CoprocNum1_0__Reg1_2__Imm6b1_3, AMFBS_HasCDE_HasFPRegs, { MCK_CoprocNum, MCK_DPR_VFP2, MCK_DPR_VFP2, MCK_Imm6b }, }, 12946 { 2345 /* vcx2 */, ARM::CDE_VCX2_fpsp, Convert__Reg1_1__CoprocNum1_0__Reg1_2__Imm6b1_3, AMFBS_HasCDE_HasFPRegs, { MCK_CoprocNum, MCK_HPR, MCK_HPR, MCK_Imm6b }, }, 12947 { 2345 /* vcx2 */, ARM::CDE_VCX2_vec, Convert__Reg1_2__CoprocNum1_1__Reg1_3__Imm7b1_4__VPTPredR4_0, AMFBS_HasCDE_HasMVEInt, { MCK_VPTPredR, MCK_CoprocNum, MCK_MQPR, MCK_MQPR, MCK_Imm7b }, }, 12948 { 2350 /* vcx2a */, ARM::CDE_VCX2A_fpdp, Convert__Reg1_1__CoprocNum1_0__Tie0_1_1__Reg1_2__Imm6b1_3, AMFBS_HasCDE_HasFPRegs, { MCK_CoprocNum, MCK_DPR_VFP2, MCK_DPR_VFP2, MCK_Imm6b }, }, 12949 { 2350 /* vcx2a */, ARM::CDE_VCX2A_fpsp, Convert__Reg1_1__CoprocNum1_0__Tie0_1_1__Reg1_2__Imm6b1_3, AMFBS_HasCDE_HasFPRegs, { MCK_CoprocNum, MCK_HPR, MCK_HPR, MCK_Imm6b }, }, 12950 { 2350 /* vcx2a */, ARM::CDE_VCX2A_vec, Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Reg1_3__Imm7b1_4__VPTPredN3_0, AMFBS_HasCDE_HasMVEInt, { MCK_VPTPredN, MCK_CoprocNum, MCK_MQPR, MCK_MQPR, MCK_Imm7b }, }, 12951 { 2356 /* vcx3 */, ARM::CDE_VCX3_fpdp, Convert__Reg1_1__CoprocNum1_0__Reg1_2__Reg1_3__Imm3b1_4, AMFBS_HasCDE_HasFPRegs, { MCK_CoprocNum, MCK_DPR_VFP2, MCK_DPR_VFP2, MCK_DPR_VFP2, MCK_Imm3b }, }, 12952 { 2356 /* vcx3 */, ARM::CDE_VCX3_fpsp, Convert__Reg1_1__CoprocNum1_0__Reg1_2__Reg1_3__Imm3b1_4, AMFBS_HasCDE_HasFPRegs, { MCK_CoprocNum, MCK_HPR, MCK_HPR, MCK_HPR, MCK_Imm3b }, }, 12953 { 2356 /* vcx3 */, ARM::CDE_VCX3_vec, Convert__Reg1_2__CoprocNum1_1__Reg1_3__Reg1_4__Imm4b1_5__VPTPredR4_0, AMFBS_HasCDE_HasMVEInt, { MCK_VPTPredR, MCK_CoprocNum, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_Imm4b }, }, 12954 { 2361 /* vcx3a */, ARM::CDE_VCX3A_fpdp, Convert__Reg1_1__CoprocNum1_0__Tie0_1_1__Reg1_2__Reg1_3__Imm3b1_4, AMFBS_HasCDE_HasFPRegs, { MCK_CoprocNum, MCK_DPR_VFP2, MCK_DPR_VFP2, MCK_DPR_VFP2, MCK_Imm3b }, }, 12955 { 2361 /* vcx3a */, ARM::CDE_VCX3A_fpsp, Convert__Reg1_1__CoprocNum1_0__Tie0_1_1__Reg1_2__Reg1_3__Imm3b1_4, AMFBS_HasCDE_HasFPRegs, { MCK_CoprocNum, MCK_HPR, MCK_HPR, MCK_HPR, MCK_Imm3b }, }, 12956 { 2361 /* vcx3a */, ARM::CDE_VCX3A_vec, Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Reg1_3__Reg1_4__Imm4b1_5__VPTPredN3_0, AMFBS_HasCDE_HasMVEInt, { MCK_VPTPredN, MCK_CoprocNum, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_Imm4b }, }, 12957 { 2367 /* vddup */, ARM::MVE_VDDUPu16, Convert__Reg1_2__Reg1_3__Tie1_1_1__VIDUP_imm1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_tGPREven, MCK_VIDUP_imm }, }, 12958 { 2367 /* vddup */, ARM::MVE_VDDUPu32, Convert__Reg1_2__Reg1_3__Tie1_1_1__VIDUP_imm1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_tGPREven, MCK_VIDUP_imm }, }, 12959 { 2367 /* vddup */, ARM::MVE_VDDUPu8, Convert__Reg1_2__Reg1_3__Tie1_1_1__VIDUP_imm1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_tGPREven, MCK_VIDUP_imm }, }, 12960 { 2373 /* vdiv */, ARM::VDIVS, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 12961 { 2373 /* vdiv */, ARM::VDIVD, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 12962 { 2373 /* vdiv */, ARM::VDIVH, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 12963 { 2373 /* vdiv */, ARM::VDIVS, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, }, 12964 { 2373 /* vdiv */, ARM::VDIVD, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12965 { 2373 /* vdiv */, ARM::VDIVH, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, }, 12966 { 2378 /* vdot */, ARM::BF16VDOTS_VDOTQ, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasBF16_HasNEON, { MCK__DOT_bf16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12967 { 2378 /* vdot */, ARM::BF16VDOTS_VDOTD, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasBF16_HasNEON, { MCK__DOT_bf16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 12968 { 2378 /* vdot */, ARM::BF16VDOTI_VDOTQ, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4, AMFBS_HasBF16_HasNEON, { MCK__DOT_bf16, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 12969 { 2378 /* vdot */, ARM::BF16VDOTI_VDOTD, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4, AMFBS_HasBF16_HasNEON, { MCK__DOT_bf16, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 12970 { 2383 /* vdup */, ARM::VDUP16q, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_GPR }, }, 12971 { 2383 /* vdup */, ARM::VDUP16d, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_GPR }, }, 12972 { 2383 /* vdup */, ARM::VDUP32q, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_GPR }, }, 12973 { 2383 /* vdup */, ARM::VDUP32d, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_GPR }, }, 12974 { 2383 /* vdup */, ARM::VDUP8q, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_GPR }, }, 12975 { 2383 /* vdup */, ARM::VDUP8d, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_GPR }, }, 12976 { 2383 /* vdup */, ARM::MVE_VDUP16, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_16, MCK_MQPR, MCK_rGPR }, }, 12977 { 2383 /* vdup */, ARM::MVE_VDUP32, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_32, MCK_MQPR, MCK_rGPR }, }, 12978 { 2383 /* vdup */, ARM::MVE_VDUP8, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_8, MCK_MQPR, MCK_rGPR }, }, 12979 { 2383 /* vdup */, ARM::VDUPLN16q, Convert__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_DPR, MCK_VectorIndex16 }, }, 12980 { 2383 /* vdup */, ARM::VDUPLN16d, Convert__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_VectorIndex16 }, }, 12981 { 2383 /* vdup */, ARM::VDUPLN32q, Convert__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_DPR, MCK_VectorIndex32 }, }, 12982 { 2383 /* vdup */, ARM::VDUPLN32d, Convert__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_VectorIndex32 }, }, 12983 { 2383 /* vdup */, ARM::VDUPLN8q, Convert__Reg1_2__Reg1_3__VectorIndex81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_DPR, MCK_VectorIndex8 }, }, 12984 { 2383 /* vdup */, ARM::VDUPLN8d, Convert__Reg1_2__Reg1_3__VectorIndex81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_VectorIndex8 }, }, 12985 { 2388 /* vdwdup */, ARM::MVE_VDWDUPu16, Convert__Reg1_2__Reg1_3__Tie1_1_1__Reg1_4__VIDUP_imm1_5__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_tGPREven, MCK_tGPROdd, MCK_VIDUP_imm }, }, 12986 { 2388 /* vdwdup */, ARM::MVE_VDWDUPu32, Convert__Reg1_2__Reg1_3__Tie1_1_1__Reg1_4__VIDUP_imm1_5__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_tGPREven, MCK_tGPROdd, MCK_VIDUP_imm }, }, 12987 { 2388 /* vdwdup */, ARM::MVE_VDWDUPu8, Convert__Reg1_2__Reg1_3__Tie1_1_1__Reg1_4__VIDUP_imm1_5__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_tGPREven, MCK_tGPROdd, MCK_VIDUP_imm }, }, 12988 { 2395 /* veor */, ARM::VEORq, Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR }, }, 12989 { 2395 /* veor */, ARM::VEORd, Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR }, }, 12990 { 2395 /* veor */, ARM::VEORq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, }, 12991 { 2395 /* veor */, ARM::VEORd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, }, 12992 { 2395 /* veor */, ARM::VEORq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, }, 12993 { 2395 /* veor */, ARM::VEORd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, }, 12994 { 2395 /* veor */, ARM::VEORq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR }, }, 12995 { 2395 /* veor */, ARM::VEORd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR }, }, 12996 { 2395 /* veor */, ARM::VEORq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, }, 12997 { 2395 /* veor */, ARM::VEORd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, }, 12998 { 2395 /* veor */, ARM::VEORq, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR, MCK_QPR }, }, 12999 { 2395 /* veor */, ARM::VEORd, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13000 { 2395 /* veor */, ARM::MVE_VEOR, Convert__Reg1_1__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13001 { 2395 /* veor */, ARM::VEORq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13002 { 2395 /* veor */, ARM::VEORd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13003 { 2395 /* veor */, ARM::VEORq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13004 { 2395 /* veor */, ARM::VEORd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13005 { 2395 /* veor */, ARM::VEORq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13006 { 2395 /* veor */, ARM::VEORd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13007 { 2395 /* veor */, ARM::VEORq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13008 { 2395 /* veor */, ARM::VEORd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13009 { 2395 /* veor */, ARM::MVE_VEOR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13010 { 2395 /* veor */, ARM::MVE_VEOR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13011 { 2395 /* veor */, ARM::MVE_VEOR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13012 { 2395 /* veor */, ARM::MVE_VEOR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13013 { 2395 /* veor */, ARM::MVE_VEOR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13014 { 2395 /* veor */, ARM::MVE_VEOR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13015 { 2395 /* veor */, ARM::MVE_VEOR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13016 { 2395 /* veor */, ARM::MVE_VEOR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13017 { 2395 /* veor */, ARM::MVE_VEOR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13018 { 2395 /* veor */, ARM::MVE_VEOR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13019 { 2395 /* veor */, ARM::MVE_VEOR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13020 { 2400 /* vext */, ARM::VEXTq16, Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_71_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_Imm0_7 }, }, 13021 { 2400 /* vext */, ARM::VEXTd16, Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_31_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_Imm0_3 }, }, 13022 { 2400 /* vext */, ARM::VEXTq32, Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_31_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_Imm0_3 }, }, 13023 { 2400 /* vext */, ARM::VEXTd32, Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_11_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_Imm0_1 }, }, 13024 { 2400 /* vext */, ARM::VEXTq64, Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_11_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_Imm0_1 }, }, 13025 { 2400 /* vext */, ARM::VEXTq8, Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_151_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_Imm0_15 }, }, 13026 { 2400 /* vext */, ARM::VEXTd8, Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_71_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_Imm0_7 }, }, 13027 { 2400 /* vext */, ARM::VEXTq16, Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_71_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_QPR, MCK_Imm0_7 }, }, 13028 { 2400 /* vext */, ARM::VEXTd16, Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_31_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_DPR, MCK_Imm0_3 }, }, 13029 { 2400 /* vext */, ARM::VEXTq32, Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_31_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR, MCK_Imm0_3 }, }, 13030 { 2400 /* vext */, ARM::VEXTd32, Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_11_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_DPR, MCK_Imm0_1 }, }, 13031 { 2400 /* vext */, ARM::VEXTq64, Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_11_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_QPR, MCK_Imm0_1 }, }, 13032 { 2400 /* vext */, ARM::VEXTq8, Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_151_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_QPR, MCK_Imm0_15 }, }, 13033 { 2400 /* vext */, ARM::VEXTd8, Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_71_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_DPR, MCK_Imm0_7 }, }, 13034 { 2405 /* vfma */, ARM::VFMAfq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasVFP4, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13035 { 2405 /* vfma */, ARM::VFMAfd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasVFP4, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13036 { 2405 /* vfma */, ARM::VFMAS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP4, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, }, 13037 { 2405 /* vfma */, ARM::VFMAD, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP4_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13038 { 2405 /* vfma */, ARM::VFMAhq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13039 { 2405 /* vfma */, ARM::VFMAhd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13040 { 2405 /* vfma */, ARM::VFMAH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, }, 13041 { 2405 /* vfma */, ARM::MVE_VFMAf32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13042 { 2405 /* vfma */, ARM::MVE_VFMA_qr_f32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 13043 { 2405 /* vfma */, ARM::MVE_VFMAf16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13044 { 2405 /* vfma */, ARM::MVE_VFMA_qr_f16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 13045 { 2410 /* vfmab */, ARM::VBF16MALBQ, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasBF16_HasNEON, { MCK__DOT_bf16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13046 { 2410 /* vfmab */, ARM::VBF16MALBQI, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex161_4, AMFBS_HasBF16_HasNEON, { MCK__DOT_bf16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 13047 { 2416 /* vfmal */, ARM::VFMALQ, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFP16FML, { MCK__DOT_f16, MCK_QPR, MCK_DPR, MCK_DPR }, }, 13048 { 2416 /* vfmal */, ARM::VFMALD, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFP16FML, { MCK__DOT_f16, MCK_DPR, MCK_HPR, MCK_HPR }, }, 13049 { 2416 /* vfmal */, ARM::VFMALQI, Convert__Reg1_1__Reg1_2__Reg1_3__VectorIndex161_4, AMFBS_HasNEON_HasFP16FML, { MCK__DOT_f16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 13050 { 2416 /* vfmal */, ARM::VFMALDI, Convert__Reg1_1__Reg1_2__Reg1_3__VectorIndex321_4, AMFBS_HasNEON_HasFP16FML, { MCK__DOT_f16, MCK_DPR, MCK_HPR, MCK_SPR_8, MCK_VectorIndex32 }, }, 13051 { 2422 /* vfmas */, ARM::MVE_VFMA_qr_Sf32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 13052 { 2422 /* vfmas */, ARM::MVE_VFMA_qr_Sf16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 13053 { 2428 /* vfmat */, ARM::VBF16MALTQ, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasBF16_HasNEON, { MCK__DOT_bf16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13054 { 2428 /* vfmat */, ARM::VBF16MALTQI, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex161_4, AMFBS_HasBF16_HasNEON, { MCK__DOT_bf16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 13055 { 2434 /* vfms */, ARM::VFMSfq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasVFP4, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13056 { 2434 /* vfms */, ARM::VFMSfd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasVFP4, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13057 { 2434 /* vfms */, ARM::VFMSS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP4, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, }, 13058 { 2434 /* vfms */, ARM::VFMSD, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP4_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13059 { 2434 /* vfms */, ARM::VFMShq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13060 { 2434 /* vfms */, ARM::VFMShd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13061 { 2434 /* vfms */, ARM::VFMSH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, }, 13062 { 2434 /* vfms */, ARM::MVE_VFMSf32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13063 { 2434 /* vfms */, ARM::MVE_VFMSf16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13064 { 2439 /* vfmsl */, ARM::VFMSLQ, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFP16FML, { MCK__DOT_f16, MCK_QPR, MCK_DPR, MCK_DPR }, }, 13065 { 2439 /* vfmsl */, ARM::VFMSLD, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFP16FML, { MCK__DOT_f16, MCK_DPR, MCK_HPR, MCK_HPR }, }, 13066 { 2439 /* vfmsl */, ARM::VFMSLQI, Convert__Reg1_1__Reg1_2__Reg1_3__VectorIndex161_4, AMFBS_HasNEON_HasFP16FML, { MCK__DOT_f16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 13067 { 2439 /* vfmsl */, ARM::VFMSLDI, Convert__Reg1_1__Reg1_2__Reg1_3__VectorIndex321_4, AMFBS_HasNEON_HasFP16FML, { MCK__DOT_f16, MCK_DPR, MCK_HPR, MCK_SPR_8, MCK_VectorIndex32 }, }, 13068 { 2445 /* vfnma */, ARM::VFNMAS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP4, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, }, 13069 { 2445 /* vfnma */, ARM::VFNMAD, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP4_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13070 { 2445 /* vfnma */, ARM::VFNMAH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, }, 13071 { 2451 /* vfnms */, ARM::VFNMSS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP4, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, }, 13072 { 2451 /* vfnms */, ARM::VFNMSD, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP4_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13073 { 2451 /* vfnms */, ARM::VFNMSH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, }, 13074 { 2457 /* vhadd */, ARM::VHADDsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 13075 { 2457 /* vhadd */, ARM::VHADDsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 13076 { 2457 /* vhadd */, ARM::VHADDsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 13077 { 2457 /* vhadd */, ARM::VHADDsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 13078 { 2457 /* vhadd */, ARM::VHADDsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, }, 13079 { 2457 /* vhadd */, ARM::VHADDsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 13080 { 2457 /* vhadd */, ARM::VHADDuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, }, 13081 { 2457 /* vhadd */, ARM::VHADDuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, }, 13082 { 2457 /* vhadd */, ARM::VHADDuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, }, 13083 { 2457 /* vhadd */, ARM::VHADDuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, }, 13084 { 2457 /* vhadd */, ARM::VHADDuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, }, 13085 { 2457 /* vhadd */, ARM::VHADDuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, }, 13086 { 2457 /* vhadd */, ARM::VHADDsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13087 { 2457 /* vhadd */, ARM::VHADDsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13088 { 2457 /* vhadd */, ARM::VHADDsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13089 { 2457 /* vhadd */, ARM::VHADDsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13090 { 2457 /* vhadd */, ARM::VHADDsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13091 { 2457 /* vhadd */, ARM::VHADDsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13092 { 2457 /* vhadd */, ARM::VHADDuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13093 { 2457 /* vhadd */, ARM::VHADDuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13094 { 2457 /* vhadd */, ARM::VHADDuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13095 { 2457 /* vhadd */, ARM::VHADDuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13096 { 2457 /* vhadd */, ARM::VHADDuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13097 { 2457 /* vhadd */, ARM::VHADDuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13098 { 2457 /* vhadd */, ARM::MVE_VHADDs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13099 { 2457 /* vhadd */, ARM::MVE_VHADD_qr_s16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 13100 { 2457 /* vhadd */, ARM::MVE_VHADDs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13101 { 2457 /* vhadd */, ARM::MVE_VHADD_qr_s32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 13102 { 2457 /* vhadd */, ARM::MVE_VHADDs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13103 { 2457 /* vhadd */, ARM::MVE_VHADD_qr_s8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 13104 { 2457 /* vhadd */, ARM::MVE_VHADDu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13105 { 2457 /* vhadd */, ARM::MVE_VHADD_qr_u16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 13106 { 2457 /* vhadd */, ARM::MVE_VHADDu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13107 { 2457 /* vhadd */, ARM::MVE_VHADD_qr_u32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 13108 { 2457 /* vhadd */, ARM::MVE_VHADDu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13109 { 2457 /* vhadd */, ARM::MVE_VHADD_qr_u8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 13110 { 2463 /* vhcadd */, ARM::MVE_VHCADDs16, Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationOdd1_5__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationOdd }, }, 13111 { 2463 /* vhcadd */, ARM::MVE_VHCADDs32, Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationOdd1_5__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationOdd }, }, 13112 { 2463 /* vhcadd */, ARM::MVE_VHCADDs8, Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationOdd1_5__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationOdd }, }, 13113 { 2470 /* vhsub */, ARM::VHSUBsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 13114 { 2470 /* vhsub */, ARM::VHSUBsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 13115 { 2470 /* vhsub */, ARM::VHSUBsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 13116 { 2470 /* vhsub */, ARM::VHSUBsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 13117 { 2470 /* vhsub */, ARM::VHSUBsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, }, 13118 { 2470 /* vhsub */, ARM::VHSUBsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 13119 { 2470 /* vhsub */, ARM::VHSUBuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, }, 13120 { 2470 /* vhsub */, ARM::VHSUBuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, }, 13121 { 2470 /* vhsub */, ARM::VHSUBuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, }, 13122 { 2470 /* vhsub */, ARM::VHSUBuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, }, 13123 { 2470 /* vhsub */, ARM::VHSUBuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, }, 13124 { 2470 /* vhsub */, ARM::VHSUBuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, }, 13125 { 2470 /* vhsub */, ARM::VHSUBsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13126 { 2470 /* vhsub */, ARM::VHSUBsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13127 { 2470 /* vhsub */, ARM::VHSUBsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13128 { 2470 /* vhsub */, ARM::VHSUBsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13129 { 2470 /* vhsub */, ARM::VHSUBsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13130 { 2470 /* vhsub */, ARM::VHSUBsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13131 { 2470 /* vhsub */, ARM::VHSUBuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13132 { 2470 /* vhsub */, ARM::VHSUBuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13133 { 2470 /* vhsub */, ARM::VHSUBuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13134 { 2470 /* vhsub */, ARM::VHSUBuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13135 { 2470 /* vhsub */, ARM::VHSUBuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13136 { 2470 /* vhsub */, ARM::VHSUBuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13137 { 2470 /* vhsub */, ARM::MVE_VHSUBs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13138 { 2470 /* vhsub */, ARM::MVE_VHSUB_qr_s16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 13139 { 2470 /* vhsub */, ARM::MVE_VHSUBs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13140 { 2470 /* vhsub */, ARM::MVE_VHSUB_qr_s32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 13141 { 2470 /* vhsub */, ARM::MVE_VHSUBs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13142 { 2470 /* vhsub */, ARM::MVE_VHSUB_qr_s8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 13143 { 2470 /* vhsub */, ARM::MVE_VHSUBu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13144 { 2470 /* vhsub */, ARM::MVE_VHSUB_qr_u16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 13145 { 2470 /* vhsub */, ARM::MVE_VHSUBu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13146 { 2470 /* vhsub */, ARM::MVE_VHSUB_qr_u32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 13147 { 2470 /* vhsub */, ARM::MVE_VHSUBu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13148 { 2470 /* vhsub */, ARM::MVE_VHSUB_qr_u8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 13149 { 2476 /* vidup */, ARM::MVE_VIDUPu16, Convert__Reg1_2__Reg1_3__Tie1_1_1__VIDUP_imm1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_tGPREven, MCK_VIDUP_imm }, }, 13150 { 2476 /* vidup */, ARM::MVE_VIDUPu32, Convert__Reg1_2__Reg1_3__Tie1_1_1__VIDUP_imm1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_tGPREven, MCK_VIDUP_imm }, }, 13151 { 2476 /* vidup */, ARM::MVE_VIDUPu8, Convert__Reg1_2__Reg1_3__Tie1_1_1__VIDUP_imm1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_tGPREven, MCK_VIDUP_imm }, }, 13152 { 2482 /* vins */, ARM::VINSH, Convert__Reg1_1__Tie0_1_1__Reg1_2, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 13153 { 2487 /* viwdup */, ARM::MVE_VIWDUPu16, Convert__Reg1_2__Reg1_3__Tie1_1_1__Reg1_4__VIDUP_imm1_5__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_tGPREven, MCK_tGPROdd, MCK_VIDUP_imm }, }, 13154 { 2487 /* viwdup */, ARM::MVE_VIWDUPu32, Convert__Reg1_2__Reg1_3__Tie1_1_1__Reg1_4__VIDUP_imm1_5__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_tGPREven, MCK_tGPROdd, MCK_VIDUP_imm }, }, 13155 { 2487 /* viwdup */, ARM::MVE_VIWDUPu8, Convert__Reg1_2__Reg1_3__Tie1_1_1__Reg1_4__VIDUP_imm1_5__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_tGPREven, MCK_tGPROdd, MCK_VIDUP_imm }, }, 13156 { 2494 /* vjcvt */, ARM::VJCVT, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPARMv8_HasV8_3a, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, }, 13157 { 2500 /* vld1 */, ARM::VLD1DUPq16, Convert__VecListDPairAllLanes1_2__DupAlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory16 }, }, 13158 { 2500 /* vld1 */, ARM::VLD1q16, Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128 }, }, 13159 { 2500 /* vld1 */, ARM::VLD1d16Q, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, }, 13160 { 2500 /* vld1 */, ARM::VLD1DUPd16, Convert__VecListOneDAllLanes1_2__DupAlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneDAllLanes, MCK_DupAlignedMemory16 }, }, 13161 { 2500 /* vld1 */, ARM::VLD1d16, Convert__VecListOneD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneD, MCK_AlignedMemory64 }, }, 13162 { 2500 /* vld1 */, ARM::VLD1LNdAsm_16, Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneDHWordIndexed, MCK_AlignedMemory16 }, }, 13163 { 2500 /* vld1 */, ARM::VLD1d16T, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64 }, }, 13164 { 2500 /* vld1 */, ARM::VLD1DUPq32, Convert__VecListDPairAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory32 }, }, 13165 { 2500 /* vld1 */, ARM::VLD1q32, Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128 }, }, 13166 { 2500 /* vld1 */, ARM::VLD1d32Q, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, }, 13167 { 2500 /* vld1 */, ARM::VLD1DUPd32, Convert__VecListOneDAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneDAllLanes, MCK_DupAlignedMemory32 }, }, 13168 { 2500 /* vld1 */, ARM::VLD1d32, Convert__VecListOneD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneD, MCK_AlignedMemory64 }, }, 13169 { 2500 /* vld1 */, ARM::VLD1LNdAsm_32, Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneDWordIndexed, MCK_AlignedMemory32 }, }, 13170 { 2500 /* vld1 */, ARM::VLD1d32T, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64 }, }, 13171 { 2500 /* vld1 */, ARM::VLD1q64, Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListDPair, MCK_AlignedMemory64or128 }, }, 13172 { 2500 /* vld1 */, ARM::VLD1d64Q, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, }, 13173 { 2500 /* vld1 */, ARM::VLD1d64, Convert__VecListOneD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListOneD, MCK_AlignedMemory64 }, }, 13174 { 2500 /* vld1 */, ARM::VLD1d64T, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListThreeD, MCK_AlignedMemory64 }, }, 13175 { 2500 /* vld1 */, ARM::VLD1DUPq8, Convert__VecListDPairAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairAllLanes, MCK_DupAlignedMemoryNone }, }, 13176 { 2500 /* vld1 */, ARM::VLD1q8, Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128 }, }, 13177 { 2500 /* vld1 */, ARM::VLD1d8Q, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, }, 13178 { 2500 /* vld1 */, ARM::VLD1DUPd8, Convert__VecListOneDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneDAllLanes, MCK_DupAlignedMemoryNone }, }, 13179 { 2500 /* vld1 */, ARM::VLD1d8, Convert__VecListOneD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneD, MCK_AlignedMemory64 }, }, 13180 { 2500 /* vld1 */, ARM::VLD1LNdAsm_8, Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneDByteIndexed, MCK_AlignedMemoryNone }, }, 13181 { 2500 /* vld1 */, ARM::VLD1d8T, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64 }, }, 13182 { 2500 /* vld1 */, ARM::VLD1DUPq16wb_fixed, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory16, MCK__EXCLAIM_ }, }, 13183 { 2500 /* vld1 */, ARM::VLD1DUPq16wb_register, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory16, MCK_rGPR }, }, 13184 { 2500 /* vld1 */, ARM::VLD1q16wb_fixed, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 13185 { 2500 /* vld1 */, ARM::VLD1q16wb_register, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, }, 13186 { 2500 /* vld1 */, ARM::VLD1d16Qwb_fixed, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 13187 { 2500 /* vld1 */, ARM::VLD1d16Qwb_register, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 13188 { 2500 /* vld1 */, ARM::VLD1DUPd16wb_fixed, Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneDAllLanes, MCK_DupAlignedMemory16, MCK__EXCLAIM_ }, }, 13189 { 2500 /* vld1 */, ARM::VLD1DUPd16wb_register, Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneDAllLanes, MCK_DupAlignedMemory16, MCK_rGPR }, }, 13190 { 2500 /* vld1 */, ARM::VLD1d16wb_fixed, Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 13191 { 2500 /* vld1 */, ARM::VLD1d16wb_register, Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneD, MCK_AlignedMemory64, MCK_rGPR }, }, 13192 { 2500 /* vld1 */, ARM::VLD1LNdWB_fixed_Asm_16, Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneDHWordIndexed, MCK_AlignedMemory16, MCK__EXCLAIM_ }, }, 13193 { 2500 /* vld1 */, ARM::VLD1LNdWB_register_Asm_16, Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneDHWordIndexed, MCK_AlignedMemory16, MCK_rGPR }, }, 13194 { 2500 /* vld1 */, ARM::VLD1d16Twb_fixed, Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 13195 { 2500 /* vld1 */, ARM::VLD1d16Twb_register, Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, }, 13196 { 2500 /* vld1 */, ARM::VLD1DUPq32wb_fixed, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory32, MCK__EXCLAIM_ }, }, 13197 { 2500 /* vld1 */, ARM::VLD1DUPq32wb_register, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory32, MCK_rGPR }, }, 13198 { 2500 /* vld1 */, ARM::VLD1q32wb_fixed, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 13199 { 2500 /* vld1 */, ARM::VLD1q32wb_register, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, }, 13200 { 2500 /* vld1 */, ARM::VLD1d32Qwb_fixed, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 13201 { 2500 /* vld1 */, ARM::VLD1d32Qwb_register, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 13202 { 2500 /* vld1 */, ARM::VLD1DUPd32wb_fixed, Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneDAllLanes, MCK_DupAlignedMemory32, MCK__EXCLAIM_ }, }, 13203 { 2500 /* vld1 */, ARM::VLD1DUPd32wb_register, Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneDAllLanes, MCK_DupAlignedMemory32, MCK_rGPR }, }, 13204 { 2500 /* vld1 */, ARM::VLD1d32wb_fixed, Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 13205 { 2500 /* vld1 */, ARM::VLD1d32wb_register, Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneD, MCK_AlignedMemory64, MCK_rGPR }, }, 13206 { 2500 /* vld1 */, ARM::VLD1LNdWB_fixed_Asm_32, Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneDWordIndexed, MCK_AlignedMemory32, MCK__EXCLAIM_ }, }, 13207 { 2500 /* vld1 */, ARM::VLD1LNdWB_register_Asm_32, Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneDWordIndexed, MCK_AlignedMemory32, MCK_rGPR }, }, 13208 { 2500 /* vld1 */, ARM::VLD1d32Twb_fixed, Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 13209 { 2500 /* vld1 */, ARM::VLD1d32Twb_register, Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, }, 13210 { 2500 /* vld1 */, ARM::VLD1q64wb_fixed, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 13211 { 2500 /* vld1 */, ARM::VLD1q64wb_register, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, }, 13212 { 2500 /* vld1 */, ARM::VLD1d64Qwb_fixed, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 13213 { 2500 /* vld1 */, ARM::VLD1d64Qwb_register, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 13214 { 2500 /* vld1 */, ARM::VLD1d64wb_fixed, Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListOneD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 13215 { 2500 /* vld1 */, ARM::VLD1d64wb_register, Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListOneD, MCK_AlignedMemory64, MCK_rGPR }, }, 13216 { 2500 /* vld1 */, ARM::VLD1d64Twb_fixed, Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 13217 { 2500 /* vld1 */, ARM::VLD1d64Twb_register, Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, }, 13218 { 2500 /* vld1 */, ARM::VLD1DUPq8wb_fixed, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairAllLanes, MCK_DupAlignedMemoryNone, MCK__EXCLAIM_ }, }, 13219 { 2500 /* vld1 */, ARM::VLD1DUPq8wb_register, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairAllLanes, MCK_DupAlignedMemoryNone, MCK_rGPR }, }, 13220 { 2500 /* vld1 */, ARM::VLD1q8wb_fixed, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 13221 { 2500 /* vld1 */, ARM::VLD1q8wb_register, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, }, 13222 { 2500 /* vld1 */, ARM::VLD1d8Qwb_fixed, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 13223 { 2500 /* vld1 */, ARM::VLD1d8Qwb_register, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 13224 { 2500 /* vld1 */, ARM::VLD1DUPd8wb_fixed, Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneDAllLanes, MCK_DupAlignedMemoryNone, MCK__EXCLAIM_ }, }, 13225 { 2500 /* vld1 */, ARM::VLD1DUPd8wb_register, Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneDAllLanes, MCK_DupAlignedMemoryNone, MCK_rGPR }, }, 13226 { 2500 /* vld1 */, ARM::VLD1d8wb_fixed, Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 13227 { 2500 /* vld1 */, ARM::VLD1d8wb_register, Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneD, MCK_AlignedMemory64, MCK_rGPR }, }, 13228 { 2500 /* vld1 */, ARM::VLD1LNdWB_fixed_Asm_8, Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneDByteIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, }, 13229 { 2500 /* vld1 */, ARM::VLD1LNdWB_register_Asm_8, Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneDByteIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, }, 13230 { 2500 /* vld1 */, ARM::VLD1d8Twb_fixed, Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 13231 { 2500 /* vld1 */, ARM::VLD1d8Twb_register, Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, }, 13232 { 2500 /* vld1 */, ARM::VLD1LNd16, Convert__Reg1_3__AlignedMemory2_8__Tie0_1_1__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_AlignedMemory }, }, 13233 { 2500 /* vld1 */, ARM::VLD1LNd8, Convert__Reg1_3__AlignedMemory2_8__Tie0_1_1__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_AlignedMemory }, }, 13234 { 2500 /* vld1 */, ARM::VLD1LNd16_UPD, Convert__Reg1_3__imm_95_0__AlignedMemory2_8__Imm1_9__Tie0_1_1__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 13235 { 2500 /* vld1 */, ARM::VLD1LNd32, Convert__Reg1_3__Reg1_8__Imm1_9__Tie0_1_1__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_GPR, MCK_Imm }, }, 13236 { 2500 /* vld1 */, ARM::VLD1LNd32_UPD, Convert__Reg1_3__imm_95_0__AlignedMemory2_8__Imm1_9__Tie0_1_1__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 13237 { 2500 /* vld1 */, ARM::VLD1LNd8_UPD, Convert__Reg1_3__imm_95_0__AlignedMemory2_8__Imm1_9__Tie0_1_1__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 13238 { 2505 /* vld2 */, ARM::VLD2DUPd16, Convert__VecListDPairAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory32 }, }, 13239 { 2505 /* vld2 */, ARM::VLD2d16, Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128 }, }, 13240 { 2505 /* vld2 */, ARM::VLD2DUPd16x2, Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairSpacedAllLanes, MCK_DupAlignedMemory32 }, }, 13241 { 2505 /* vld2 */, ARM::VLD2b16, Convert__VecListDPairSpaced1_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128 }, }, 13242 { 2505 /* vld2 */, ARM::VLD2q16, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, }, 13243 { 2505 /* vld2 */, ARM::VLD2LNdAsm_16, Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoDHWordIndexed, MCK_AlignedMemory32 }, }, 13244 { 2505 /* vld2 */, ARM::VLD2LNqAsm_16, Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoQHWordIndexed, MCK_AlignedMemory32 }, }, 13245 { 2505 /* vld2 */, ARM::VLD2DUPd32, Convert__VecListDPairAllLanes1_2__DupAlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory64 }, }, 13246 { 2505 /* vld2 */, ARM::VLD2d32, Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128 }, }, 13247 { 2505 /* vld2 */, ARM::VLD2DUPd32x2, Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairSpacedAllLanes, MCK_DupAlignedMemory64 }, }, 13248 { 2505 /* vld2 */, ARM::VLD2b32, Convert__VecListDPairSpaced1_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128 }, }, 13249 { 2505 /* vld2 */, ARM::VLD2q32, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, }, 13250 { 2505 /* vld2 */, ARM::VLD2LNdAsm_32, Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoDWordIndexed, MCK_AlignedMemory64 }, }, 13251 { 2505 /* vld2 */, ARM::VLD2LNqAsm_32, Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoQWordIndexed, MCK_AlignedMemory64 }, }, 13252 { 2505 /* vld2 */, ARM::VLD2DUPd8, Convert__VecListDPairAllLanes1_2__DupAlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory16 }, }, 13253 { 2505 /* vld2 */, ARM::VLD2d8, Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128 }, }, 13254 { 2505 /* vld2 */, ARM::VLD2DUPd8x2, Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairSpacedAllLanes, MCK_DupAlignedMemory16 }, }, 13255 { 2505 /* vld2 */, ARM::VLD2b8, Convert__VecListDPairSpaced1_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128 }, }, 13256 { 2505 /* vld2 */, ARM::VLD2q8, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, }, 13257 { 2505 /* vld2 */, ARM::VLD2LNdAsm_8, Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListTwoDByteIndexed, MCK_AlignedMemory16 }, }, 13258 { 2505 /* vld2 */, ARM::VLD2DUPd16wb_fixed, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory32, MCK__EXCLAIM_ }, }, 13259 { 2505 /* vld2 */, ARM::VLD2DUPd16wb_register, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory32, MCK_rGPR }, }, 13260 { 2505 /* vld2 */, ARM::VLD2d16wb_fixed, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 13261 { 2505 /* vld2 */, ARM::VLD2d16wb_register, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, }, 13262 { 2505 /* vld2 */, ARM::VLD2DUPd16x2wb_fixed, Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairSpacedAllLanes, MCK_DupAlignedMemory32, MCK__EXCLAIM_ }, }, 13263 { 2505 /* vld2 */, ARM::VLD2DUPd16x2wb_register, Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairSpacedAllLanes, MCK_DupAlignedMemory32, MCK_rGPR }, }, 13264 { 2505 /* vld2 */, ARM::VLD2b16wb_fixed, Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 13265 { 2505 /* vld2 */, ARM::VLD2b16wb_register, Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK_rGPR }, }, 13266 { 2505 /* vld2 */, ARM::VLD2q16wb_fixed, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 13267 { 2505 /* vld2 */, ARM::VLD2q16wb_register, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 13268 { 2505 /* vld2 */, ARM::VLD2LNdWB_fixed_Asm_16, Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoDHWordIndexed, MCK_AlignedMemory32, MCK__EXCLAIM_ }, }, 13269 { 2505 /* vld2 */, ARM::VLD2LNdWB_register_Asm_16, Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoDHWordIndexed, MCK_AlignedMemory32, MCK_rGPR }, }, 13270 { 2505 /* vld2 */, ARM::VLD2LNqWB_fixed_Asm_16, Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoQHWordIndexed, MCK_AlignedMemory32, MCK__EXCLAIM_ }, }, 13271 { 2505 /* vld2 */, ARM::VLD2LNqWB_register_Asm_16, Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoQHWordIndexed, MCK_AlignedMemory32, MCK_rGPR }, }, 13272 { 2505 /* vld2 */, ARM::VLD2DUPd32wb_fixed, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory64, MCK__EXCLAIM_ }, }, 13273 { 2505 /* vld2 */, ARM::VLD2DUPd32wb_register, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory64, MCK_rGPR }, }, 13274 { 2505 /* vld2 */, ARM::VLD2d32wb_fixed, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 13275 { 2505 /* vld2 */, ARM::VLD2d32wb_register, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, }, 13276 { 2505 /* vld2 */, ARM::VLD2DUPd32x2wb_fixed, Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairSpacedAllLanes, MCK_DupAlignedMemory64, MCK__EXCLAIM_ }, }, 13277 { 2505 /* vld2 */, ARM::VLD2DUPd32x2wb_register, Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairSpacedAllLanes, MCK_DupAlignedMemory64, MCK_rGPR }, }, 13278 { 2505 /* vld2 */, ARM::VLD2b32wb_fixed, Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 13279 { 2505 /* vld2 */, ARM::VLD2b32wb_register, Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK_rGPR }, }, 13280 { 2505 /* vld2 */, ARM::VLD2q32wb_fixed, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 13281 { 2505 /* vld2 */, ARM::VLD2q32wb_register, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 13282 { 2505 /* vld2 */, ARM::VLD2LNdWB_fixed_Asm_32, Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoDWordIndexed, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 13283 { 2505 /* vld2 */, ARM::VLD2LNdWB_register_Asm_32, Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoDWordIndexed, MCK_AlignedMemory64, MCK_rGPR }, }, 13284 { 2505 /* vld2 */, ARM::VLD2LNqWB_fixed_Asm_32, Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoQWordIndexed, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 13285 { 2505 /* vld2 */, ARM::VLD2LNqWB_register_Asm_32, Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoQWordIndexed, MCK_AlignedMemory64, MCK_rGPR }, }, 13286 { 2505 /* vld2 */, ARM::VLD2DUPd8wb_fixed, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory16, MCK__EXCLAIM_ }, }, 13287 { 2505 /* vld2 */, ARM::VLD2DUPd8wb_register, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory16, MCK_rGPR }, }, 13288 { 2505 /* vld2 */, ARM::VLD2d8wb_fixed, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 13289 { 2505 /* vld2 */, ARM::VLD2d8wb_register, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, }, 13290 { 2505 /* vld2 */, ARM::VLD2DUPd8x2wb_fixed, Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairSpacedAllLanes, MCK_DupAlignedMemory16, MCK__EXCLAIM_ }, }, 13291 { 2505 /* vld2 */, ARM::VLD2DUPd8x2wb_register, Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairSpacedAllLanes, MCK_DupAlignedMemory16, MCK_rGPR }, }, 13292 { 2505 /* vld2 */, ARM::VLD2b8wb_fixed, Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 13293 { 2505 /* vld2 */, ARM::VLD2b8wb_register, Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK_rGPR }, }, 13294 { 2505 /* vld2 */, ARM::VLD2q8wb_fixed, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 13295 { 2505 /* vld2 */, ARM::VLD2q8wb_register, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 13296 { 2505 /* vld2 */, ARM::VLD2LNdWB_fixed_Asm_8, Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListTwoDByteIndexed, MCK_AlignedMemory16, MCK__EXCLAIM_ }, }, 13297 { 2505 /* vld2 */, ARM::VLD2LNdWB_register_Asm_8, Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListTwoDByteIndexed, MCK_AlignedMemory16, MCK_rGPR }, }, 13298 { 2510 /* vld20 */, ARM::MVE_VLD20_16, Convert__VecListTwoMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListTwoMQ, MCK_MemNoOffsetT2 }, }, 13299 { 2510 /* vld20 */, ARM::MVE_VLD20_32, Convert__VecListTwoMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListTwoMQ, MCK_MemNoOffsetT2 }, }, 13300 { 2510 /* vld20 */, ARM::MVE_VLD20_8, Convert__VecListTwoMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListTwoMQ, MCK_MemNoOffsetT2 }, }, 13301 { 2510 /* vld20 */, ARM::MVE_VLD20_16_wb, Convert__VecListTwoMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 13302 { 2510 /* vld20 */, ARM::MVE_VLD20_32_wb, Convert__VecListTwoMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 13303 { 2510 /* vld20 */, ARM::MVE_VLD20_8_wb, Convert__VecListTwoMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 13304 { 2516 /* vld21 */, ARM::MVE_VLD21_16, Convert__VecListTwoMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListTwoMQ, MCK_MemNoOffsetT2 }, }, 13305 { 2516 /* vld21 */, ARM::MVE_VLD21_32, Convert__VecListTwoMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListTwoMQ, MCK_MemNoOffsetT2 }, }, 13306 { 2516 /* vld21 */, ARM::MVE_VLD21_8, Convert__VecListTwoMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListTwoMQ, MCK_MemNoOffsetT2 }, }, 13307 { 2516 /* vld21 */, ARM::MVE_VLD21_16_wb, Convert__VecListTwoMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 13308 { 2516 /* vld21 */, ARM::MVE_VLD21_32_wb, Convert__VecListTwoMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 13309 { 2516 /* vld21 */, ARM::MVE_VLD21_8_wb, Convert__VecListTwoMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 13310 { 2522 /* vld3 */, ARM::VLD3DUPdAsm_16, Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeDAllLanes, MCK_DupAlignedMemoryNone }, }, 13311 { 2522 /* vld3 */, ARM::VLD3dAsm_16, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64 }, }, 13312 { 2522 /* vld3 */, ARM::VLD3LNdAsm_16, Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeDHWordIndexed, MCK_AlignedMemoryNone }, }, 13313 { 2522 /* vld3 */, ARM::VLD3DUPqAsm_16, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone }, }, 13314 { 2522 /* vld3 */, ARM::VLD3qAsm_16, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQ, MCK_AlignedMemory64 }, }, 13315 { 2522 /* vld3 */, ARM::VLD3LNqAsm_16, Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQHWordIndexed, MCK_AlignedMemoryNone }, }, 13316 { 2522 /* vld3 */, ARM::VLD3DUPdAsm_32, Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeDAllLanes, MCK_DupAlignedMemoryNone }, }, 13317 { 2522 /* vld3 */, ARM::VLD3dAsm_32, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64 }, }, 13318 { 2522 /* vld3 */, ARM::VLD3LNdAsm_32, Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeDWordIndexed, MCK_AlignedMemoryNone }, }, 13319 { 2522 /* vld3 */, ARM::VLD3DUPqAsm_32, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone }, }, 13320 { 2522 /* vld3 */, ARM::VLD3qAsm_32, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQ, MCK_AlignedMemory64 }, }, 13321 { 2522 /* vld3 */, ARM::VLD3LNqAsm_32, Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQWordIndexed, MCK_AlignedMemoryNone }, }, 13322 { 2522 /* vld3 */, ARM::VLD3DUPdAsm_8, Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeDAllLanes, MCK_DupAlignedMemoryNone }, }, 13323 { 2522 /* vld3 */, ARM::VLD3dAsm_8, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64 }, }, 13324 { 2522 /* vld3 */, ARM::VLD3LNdAsm_8, Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeDByteIndexed, MCK_AlignedMemoryNone }, }, 13325 { 2522 /* vld3 */, ARM::VLD3DUPqAsm_8, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone }, }, 13326 { 2522 /* vld3 */, ARM::VLD3qAsm_8, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQ, MCK_AlignedMemory64 }, }, 13327 { 2522 /* vld3 */, ARM::VLD3DUPdWB_fixed_Asm_16, Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeDAllLanes, MCK_DupAlignedMemoryNone, MCK__EXCLAIM_ }, }, 13328 { 2522 /* vld3 */, ARM::VLD3DUPdWB_register_Asm_16, Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeDAllLanes, MCK_DupAlignedMemoryNone, MCK_rGPR }, }, 13329 { 2522 /* vld3 */, ARM::VLD3dWB_fixed_Asm_16, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 13330 { 2522 /* vld3 */, ARM::VLD3dWB_register_Asm_16, Convert__VecListThreeD1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, }, 13331 { 2522 /* vld3 */, ARM::VLD3LNdWB_fixed_Asm_16, Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeDHWordIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, }, 13332 { 2522 /* vld3 */, ARM::VLD3LNdWB_register_Asm_16, Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeDHWordIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, }, 13333 { 2522 /* vld3 */, ARM::VLD3DUPqWB_fixed_Asm_16, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone, MCK__EXCLAIM_ }, }, 13334 { 2522 /* vld3 */, ARM::VLD3DUPqWB_register_Asm_16, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone, MCK_rGPR }, }, 13335 { 2522 /* vld3 */, ARM::VLD3qWB_fixed_Asm_16, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 13336 { 2522 /* vld3 */, ARM::VLD3qWB_register_Asm_16, Convert__VecListThreeQ1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK_rGPR }, }, 13337 { 2522 /* vld3 */, ARM::VLD3LNqWB_fixed_Asm_16, Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQHWordIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, }, 13338 { 2522 /* vld3 */, ARM::VLD3LNqWB_register_Asm_16, Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQHWordIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, }, 13339 { 2522 /* vld3 */, ARM::VLD3DUPdWB_fixed_Asm_32, Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeDAllLanes, MCK_DupAlignedMemoryNone, MCK__EXCLAIM_ }, }, 13340 { 2522 /* vld3 */, ARM::VLD3DUPdWB_register_Asm_32, Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeDAllLanes, MCK_DupAlignedMemoryNone, MCK_rGPR }, }, 13341 { 2522 /* vld3 */, ARM::VLD3dWB_fixed_Asm_32, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 13342 { 2522 /* vld3 */, ARM::VLD3dWB_register_Asm_32, Convert__VecListThreeD1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, }, 13343 { 2522 /* vld3 */, ARM::VLD3LNdWB_fixed_Asm_32, Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeDWordIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, }, 13344 { 2522 /* vld3 */, ARM::VLD3LNdWB_register_Asm_32, Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeDWordIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, }, 13345 { 2522 /* vld3 */, ARM::VLD3DUPqWB_fixed_Asm_32, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone, MCK__EXCLAIM_ }, }, 13346 { 2522 /* vld3 */, ARM::VLD3DUPqWB_register_Asm_32, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone, MCK_rGPR }, }, 13347 { 2522 /* vld3 */, ARM::VLD3qWB_fixed_Asm_32, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 13348 { 2522 /* vld3 */, ARM::VLD3qWB_register_Asm_32, Convert__VecListThreeQ1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK_rGPR }, }, 13349 { 2522 /* vld3 */, ARM::VLD3LNqWB_fixed_Asm_32, Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQWordIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, }, 13350 { 2522 /* vld3 */, ARM::VLD3LNqWB_register_Asm_32, Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQWordIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, }, 13351 { 2522 /* vld3 */, ARM::VLD3DUPdWB_fixed_Asm_8, Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeDAllLanes, MCK_DupAlignedMemoryNone, MCK__EXCLAIM_ }, }, 13352 { 2522 /* vld3 */, ARM::VLD3DUPdWB_register_Asm_8, Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeDAllLanes, MCK_DupAlignedMemoryNone, MCK_rGPR }, }, 13353 { 2522 /* vld3 */, ARM::VLD3dWB_fixed_Asm_8, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 13354 { 2522 /* vld3 */, ARM::VLD3dWB_register_Asm_8, Convert__VecListThreeD1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, }, 13355 { 2522 /* vld3 */, ARM::VLD3LNdWB_fixed_Asm_8, Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeDByteIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, }, 13356 { 2522 /* vld3 */, ARM::VLD3LNdWB_register_Asm_8, Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeDByteIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, }, 13357 { 2522 /* vld3 */, ARM::VLD3DUPqWB_fixed_Asm_8, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone, MCK__EXCLAIM_ }, }, 13358 { 2522 /* vld3 */, ARM::VLD3DUPqWB_register_Asm_8, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone, MCK_rGPR }, }, 13359 { 2522 /* vld3 */, ARM::VLD3qWB_fixed_Asm_8, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 13360 { 2522 /* vld3 */, ARM::VLD3qWB_register_Asm_8, Convert__VecListThreeQ1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK_rGPR }, }, 13361 { 2522 /* vld3 */, ARM::VLD3d16, Convert__Reg1_3__Reg1_4__Reg1_5__AlignedMemory2_7__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 13362 { 2522 /* vld3 */, ARM::VLD3q16, Convert__Reg1_3__Reg1_4__Reg1_5__AlignedMemory2_7__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 13363 { 2522 /* vld3 */, ARM::VLD3d32, Convert__Reg1_3__Reg1_4__Reg1_5__AlignedMemory2_7__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 13364 { 2522 /* vld3 */, ARM::VLD3q32, Convert__Reg1_3__Reg1_4__Reg1_5__AlignedMemory2_7__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 13365 { 2522 /* vld3 */, ARM::VLD3d8, Convert__Reg1_3__Reg1_4__Reg1_5__AlignedMemory2_7__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 13366 { 2522 /* vld3 */, ARM::VLD3q8, Convert__Reg1_3__Reg1_4__Reg1_5__AlignedMemory2_7__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 13367 { 2522 /* vld3 */, ARM::VLD3d16_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__imm_95_0__AlignedMemory2_7__Imm1_8__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 13368 { 2522 /* vld3 */, ARM::VLD3q16_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__imm_95_0__AlignedMemory2_7__Imm1_8__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 13369 { 2522 /* vld3 */, ARM::VLD3d32_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__imm_95_0__AlignedMemory2_7__Imm1_8__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 13370 { 2522 /* vld3 */, ARM::VLD3q32_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__imm_95_0__AlignedMemory2_7__Imm1_8__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 13371 { 2522 /* vld3 */, ARM::VLD3d8_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__imm_95_0__AlignedMemory2_7__Imm1_8__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 13372 { 2522 /* vld3 */, ARM::VLD3q8_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__imm_95_0__AlignedMemory2_7__Imm1_8__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 13373 { 2522 /* vld3 */, ARM::VLD3DUPd16, Convert__Reg1_3__Reg1_6__Reg1_9__AlignedMemory2_13__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, }, 13374 { 2522 /* vld3 */, ARM::VLD3DUPq16, Convert__Reg1_3__Reg1_6__Reg1_9__AlignedMemory2_13__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, }, 13375 { 2522 /* vld3 */, ARM::VLD3DUPd32, Convert__Reg1_3__Reg1_6__Reg1_9__AlignedMemory2_13__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, }, 13376 { 2522 /* vld3 */, ARM::VLD3DUPq32, Convert__Reg1_3__Reg1_6__Reg1_9__AlignedMemory2_13__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, }, 13377 { 2522 /* vld3 */, ARM::VLD3DUPd8, Convert__Reg1_3__Reg1_6__Reg1_9__AlignedMemory2_13__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, }, 13378 { 2522 /* vld3 */, ARM::VLD3DUPq8, Convert__Reg1_3__Reg1_6__Reg1_9__AlignedMemory2_13__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, }, 13379 { 2522 /* vld3 */, ARM::VLD3DUPd16_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__imm_95_0__DupAlignedMemory642_13__Imm1_14__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_DupAlignedMemory64, MCK_Imm }, }, 13380 { 2522 /* vld3 */, ARM::VLD3DUPq16_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__imm_95_0__DupAlignedMemory642_13__Imm1_14__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_DupAlignedMemory64, MCK_Imm }, }, 13381 { 2522 /* vld3 */, ARM::VLD3DUPd32_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__imm_95_0__DupAlignedMemory642_13__Imm1_14__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_DupAlignedMemory64, MCK_Imm }, }, 13382 { 2522 /* vld3 */, ARM::VLD3DUPq32_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__imm_95_0__DupAlignedMemory642_13__Imm1_14__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_DupAlignedMemory64, MCK_Imm }, }, 13383 { 2522 /* vld3 */, ARM::VLD3DUPd8_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__imm_95_0__DupAlignedMemory642_13__Imm1_14__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_DupAlignedMemory64, MCK_Imm }, }, 13384 { 2522 /* vld3 */, ARM::VLD3DUPq8_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__imm_95_0__DupAlignedMemory642_13__Imm1_14__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_DupAlignedMemory64, MCK_Imm }, }, 13385 { 2527 /* vld4 */, ARM::VLD4DUPdAsm_16, Convert__VecListFourDAllLanes1_2__DupAlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory64 }, }, 13386 { 2527 /* vld4 */, ARM::VLD4dAsm_16, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, }, 13387 { 2527 /* vld4 */, ARM::VLD4LNdAsm_16, Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDHWordIndexed, MCK_AlignedMemory64 }, }, 13388 { 2527 /* vld4 */, ARM::VLD4DUPqAsm_16, Convert__VecListFourQAllLanes1_2__DupAlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory64 }, }, 13389 { 2527 /* vld4 */, ARM::VLD4qAsm_16, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQ, MCK_AlignedMemory64or128or256 }, }, 13390 { 2527 /* vld4 */, ARM::VLD4LNqAsm_16, Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQHWordIndexed, MCK_AlignedMemory64 }, }, 13391 { 2527 /* vld4 */, ARM::VLD4DUPdAsm_32, Convert__VecListFourDAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory64or128 }, }, 13392 { 2527 /* vld4 */, ARM::VLD4dAsm_32, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, }, 13393 { 2527 /* vld4 */, ARM::VLD4LNdAsm_32, Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDWordIndexed, MCK_AlignedMemory64or128 }, }, 13394 { 2527 /* vld4 */, ARM::VLD4DUPqAsm_32, Convert__VecListFourQAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory64or128 }, }, 13395 { 2527 /* vld4 */, ARM::VLD4qAsm_32, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQ, MCK_AlignedMemory64or128or256 }, }, 13396 { 2527 /* vld4 */, ARM::VLD4LNqAsm_32, Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQWordIndexed, MCK_AlignedMemory64or128 }, }, 13397 { 2527 /* vld4 */, ARM::VLD4DUPdAsm_8, Convert__VecListFourDAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory32 }, }, 13398 { 2527 /* vld4 */, ARM::VLD4dAsm_8, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, }, 13399 { 2527 /* vld4 */, ARM::VLD4LNdAsm_8, Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDByteIndexed, MCK_AlignedMemory32 }, }, 13400 { 2527 /* vld4 */, ARM::VLD4DUPqAsm_8, Convert__VecListFourQAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory32 }, }, 13401 { 2527 /* vld4 */, ARM::VLD4qAsm_8, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQ, MCK_AlignedMemory64or128or256 }, }, 13402 { 2527 /* vld4 */, ARM::VLD4DUPdWB_fixed_Asm_16, Convert__VecListFourDAllLanes1_2__DupAlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory64, MCK__EXCLAIM_ }, }, 13403 { 2527 /* vld4 */, ARM::VLD4DUPdWB_register_Asm_16, Convert__VecListFourDAllLanes1_2__DupAlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory64, MCK_rGPR }, }, 13404 { 2527 /* vld4 */, ARM::VLD4dWB_fixed_Asm_16, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 13405 { 2527 /* vld4 */, ARM::VLD4dWB_register_Asm_16, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 13406 { 2527 /* vld4 */, ARM::VLD4LNdWB_fixed_Asm_16, Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDHWordIndexed, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 13407 { 2527 /* vld4 */, ARM::VLD4LNdWB_register_Asm_16, Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDHWordIndexed, MCK_AlignedMemory64, MCK_rGPR }, }, 13408 { 2527 /* vld4 */, ARM::VLD4DUPqWB_fixed_Asm_16, Convert__VecListFourQAllLanes1_2__DupAlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory64, MCK__EXCLAIM_ }, }, 13409 { 2527 /* vld4 */, ARM::VLD4DUPqWB_register_Asm_16, Convert__VecListFourQAllLanes1_2__DupAlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory64, MCK_rGPR }, }, 13410 { 2527 /* vld4 */, ARM::VLD4qWB_fixed_Asm_16, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 13411 { 2527 /* vld4 */, ARM::VLD4qWB_register_Asm_16, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 13412 { 2527 /* vld4 */, ARM::VLD4LNqWB_fixed_Asm_16, Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQHWordIndexed, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 13413 { 2527 /* vld4 */, ARM::VLD4LNqWB_register_Asm_16, Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQHWordIndexed, MCK_AlignedMemory64, MCK_rGPR }, }, 13414 { 2527 /* vld4 */, ARM::VLD4DUPdWB_fixed_Asm_32, Convert__VecListFourDAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory64or128, MCK__EXCLAIM_ }, }, 13415 { 2527 /* vld4 */, ARM::VLD4DUPdWB_register_Asm_32, Convert__VecListFourDAllLanes1_2__DupAlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory64or128, MCK_rGPR }, }, 13416 { 2527 /* vld4 */, ARM::VLD4dWB_fixed_Asm_32, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 13417 { 2527 /* vld4 */, ARM::VLD4dWB_register_Asm_32, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 13418 { 2527 /* vld4 */, ARM::VLD4LNdWB_fixed_Asm_32, Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDWordIndexed, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 13419 { 2527 /* vld4 */, ARM::VLD4LNdWB_register_Asm_32, Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDWordIndexed, MCK_AlignedMemory64or128, MCK_rGPR }, }, 13420 { 2527 /* vld4 */, ARM::VLD4DUPqWB_fixed_Asm_32, Convert__VecListFourQAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory64or128, MCK__EXCLAIM_ }, }, 13421 { 2527 /* vld4 */, ARM::VLD4DUPqWB_register_Asm_32, Convert__VecListFourQAllLanes1_2__DupAlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory64or128, MCK_rGPR }, }, 13422 { 2527 /* vld4 */, ARM::VLD4qWB_fixed_Asm_32, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 13423 { 2527 /* vld4 */, ARM::VLD4qWB_register_Asm_32, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 13424 { 2527 /* vld4 */, ARM::VLD4LNqWB_fixed_Asm_32, Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQWordIndexed, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 13425 { 2527 /* vld4 */, ARM::VLD4LNqWB_register_Asm_32, Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQWordIndexed, MCK_AlignedMemory64or128, MCK_rGPR }, }, 13426 { 2527 /* vld4 */, ARM::VLD4DUPdWB_fixed_Asm_8, Convert__VecListFourDAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory32, MCK__EXCLAIM_ }, }, 13427 { 2527 /* vld4 */, ARM::VLD4DUPdWB_register_Asm_8, Convert__VecListFourDAllLanes1_2__DupAlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory32, MCK_rGPR }, }, 13428 { 2527 /* vld4 */, ARM::VLD4dWB_fixed_Asm_8, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 13429 { 2527 /* vld4 */, ARM::VLD4dWB_register_Asm_8, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 13430 { 2527 /* vld4 */, ARM::VLD4LNdWB_fixed_Asm_8, Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDByteIndexed, MCK_AlignedMemory32, MCK__EXCLAIM_ }, }, 13431 { 2527 /* vld4 */, ARM::VLD4LNdWB_register_Asm_8, Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDByteIndexed, MCK_AlignedMemory32, MCK_rGPR }, }, 13432 { 2527 /* vld4 */, ARM::VLD4DUPqWB_fixed_Asm_8, Convert__VecListFourQAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory32, MCK__EXCLAIM_ }, }, 13433 { 2527 /* vld4 */, ARM::VLD4DUPqWB_register_Asm_8, Convert__VecListFourQAllLanes1_2__DupAlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory32, MCK_rGPR }, }, 13434 { 2527 /* vld4 */, ARM::VLD4qWB_fixed_Asm_8, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 13435 { 2527 /* vld4 */, ARM::VLD4qWB_register_Asm_8, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 13436 { 2527 /* vld4 */, ARM::VLD4d16, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__AlignedMemory2_8__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 13437 { 2527 /* vld4 */, ARM::VLD4q16, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__AlignedMemory2_8__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 13438 { 2527 /* vld4 */, ARM::VLD4d32, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__AlignedMemory2_8__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 13439 { 2527 /* vld4 */, ARM::VLD4q32, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__AlignedMemory2_8__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 13440 { 2527 /* vld4 */, ARM::VLD4d8, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__AlignedMemory2_8__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 13441 { 2527 /* vld4 */, ARM::VLD4q8, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__AlignedMemory2_8__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 13442 { 2527 /* vld4 */, ARM::VLD4d16_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__imm_95_0__AlignedMemory2_8__Imm1_9__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 13443 { 2527 /* vld4 */, ARM::VLD4q16_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__imm_95_0__AlignedMemory2_8__Imm1_9__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 13444 { 2527 /* vld4 */, ARM::VLD4d32_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__imm_95_0__AlignedMemory2_8__Imm1_9__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 13445 { 2527 /* vld4 */, ARM::VLD4q32_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__imm_95_0__AlignedMemory2_8__Imm1_9__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 13446 { 2527 /* vld4 */, ARM::VLD4d8_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__imm_95_0__AlignedMemory2_8__Imm1_9__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 13447 { 2527 /* vld4 */, ARM::VLD4q8_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__imm_95_0__AlignedMemory2_8__Imm1_9__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 13448 { 2527 /* vld4 */, ARM::VLD4DUPd16, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__AlignedMemory2_16__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, }, 13449 { 2527 /* vld4 */, ARM::VLD4DUPq16, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__AlignedMemory2_16__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, }, 13450 { 2527 /* vld4 */, ARM::VLD4DUPd32, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__AlignedMemory2_16__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, }, 13451 { 2527 /* vld4 */, ARM::VLD4DUPq32, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__AlignedMemory2_16__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, }, 13452 { 2527 /* vld4 */, ARM::VLD4DUPd8, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__AlignedMemory2_16__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, }, 13453 { 2527 /* vld4 */, ARM::VLD4DUPq8, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__AlignedMemory2_16__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, }, 13454 { 2527 /* vld4 */, ARM::VLD4DUPd16_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__imm_95_0__AlignedMemory2_16__Imm1_17__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 13455 { 2527 /* vld4 */, ARM::VLD4DUPq16_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__imm_95_0__AlignedMemory2_16__Imm1_17__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 13456 { 2527 /* vld4 */, ARM::VLD4DUPd32_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__imm_95_0__AlignedMemory2_16__Imm1_17__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 13457 { 2527 /* vld4 */, ARM::VLD4DUPq32_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__imm_95_0__AlignedMemory2_16__Imm1_17__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 13458 { 2527 /* vld4 */, ARM::VLD4DUPd8_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__imm_95_0__AlignedMemory2_16__Imm1_17__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 13459 { 2527 /* vld4 */, ARM::VLD4DUPq8_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__imm_95_0__AlignedMemory2_16__Imm1_17__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 13460 { 2532 /* vld40 */, ARM::MVE_VLD40_16, Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, }, 13461 { 2532 /* vld40 */, ARM::MVE_VLD40_32, Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, }, 13462 { 2532 /* vld40 */, ARM::MVE_VLD40_8, Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, }, 13463 { 2532 /* vld40 */, ARM::MVE_VLD40_16_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 13464 { 2532 /* vld40 */, ARM::MVE_VLD40_32_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 13465 { 2532 /* vld40 */, ARM::MVE_VLD40_8_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 13466 { 2538 /* vld41 */, ARM::MVE_VLD41_16, Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, }, 13467 { 2538 /* vld41 */, ARM::MVE_VLD41_32, Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, }, 13468 { 2538 /* vld41 */, ARM::MVE_VLD41_8, Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, }, 13469 { 2538 /* vld41 */, ARM::MVE_VLD41_16_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 13470 { 2538 /* vld41 */, ARM::MVE_VLD41_32_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 13471 { 2538 /* vld41 */, ARM::MVE_VLD41_8_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 13472 { 2544 /* vld42 */, ARM::MVE_VLD42_16, Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, }, 13473 { 2544 /* vld42 */, ARM::MVE_VLD42_32, Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, }, 13474 { 2544 /* vld42 */, ARM::MVE_VLD42_8, Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, }, 13475 { 2544 /* vld42 */, ARM::MVE_VLD42_16_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 13476 { 2544 /* vld42 */, ARM::MVE_VLD42_32_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 13477 { 2544 /* vld42 */, ARM::MVE_VLD42_8_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 13478 { 2550 /* vld43 */, ARM::MVE_VLD43_16, Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, }, 13479 { 2550 /* vld43 */, ARM::MVE_VLD43_32, Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, }, 13480 { 2550 /* vld43 */, ARM::MVE_VLD43_8, Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, }, 13481 { 2550 /* vld43 */, ARM::MVE_VLD43_16_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 13482 { 2550 /* vld43 */, ARM::MVE_VLD43_32_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 13483 { 2550 /* vld43 */, ARM::MVE_VLD43_8_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 13484 { 2556 /* vldmdb */, ARM::VLDMDDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_DPRRegList }, }, 13485 { 2556 /* vldmdb */, ARM::VLDMSDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__SPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_SPRRegList }, }, 13486 { 2563 /* vldmia */, ARM::VLDMDIA, Convert__Reg1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK_DPRRegList }, }, 13487 { 2563 /* vldmia */, ARM::VLDMSIA, Convert__Reg1_1__CondCode2_0__SPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK_SPRRegList }, }, 13488 { 2563 /* vldmia */, ARM::VLDMDIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_DPRRegList }, }, 13489 { 2563 /* vldmia */, ARM::VLDMSIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__SPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_SPRRegList }, }, 13490 { 2570 /* vldr */, ARM::VLDR_FPCXTNS_off, Convert__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTRegs, MCK_MemImm7s4Offset }, }, 13491 { 2570 /* vldr */, ARM::VLDR_FPCXTS_off, Convert__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTS, MCK_MemImm7s4Offset }, }, 13492 { 2570 /* vldr */, ARM::VLDR_FPSCR_off, Convert__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasFPRegs_HasV8_1MMainline, { MCK_CondCode, MCK_FPSCR, MCK_MemImm7s4Offset }, }, 13493 { 2570 /* vldr */, ARM::VLDR_FPSCR_NZCVQC_off, Convert__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasFPRegs_HasV8_1MMainline, { MCK_CondCode, MCK_FPSCR_NZCVQC, MCK_MemImm7s4Offset }, }, 13494 { 2570 /* vldr */, ARM::VLDR_P0_off, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_P0, MCK_MemImm7s4Offset }, }, 13495 { 2570 /* vldr */, ARM::VLDR_VPR_off, Convert__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_VCCR, MCK_MemImm7s4Offset }, }, 13496 { 2570 /* vldr */, ARM::VLDRD, Convert__Reg1_1__AddrMode52_2__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_DPR, MCK_AddrMode5 }, }, 13497 { 2570 /* vldr */, ARM::VLDRS, Convert__Reg1_1__AddrMode52_2__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_HPR, MCK_AddrMode5 }, }, 13498 { 2570 /* vldr */, ARM::VLDRH, Convert__Reg1_2__AddrMode5FP162_3__CondCode2_0, AMFBS_HasFPRegs16, { MCK_CondCode, MCK__DOT_16, MCK_HPR, MCK_AddrMode5FP16 }, }, 13499 { 2570 /* vldr */, ARM::VLDRS, Convert__Reg1_2__AddrMode52_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_32, MCK_HPR, MCK_AddrMode5 }, }, 13500 { 2570 /* vldr */, ARM::VLDRD, Convert__Reg1_2__AddrMode52_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_AddrMode5 }, }, 13501 { 2570 /* vldr */, ARM::VLDR_FPCXTNS_pre, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTRegs, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, }, 13502 { 2570 /* vldr */, ARM::VLDR_FPCXTNS_post, Convert__MemNoOffsetT21_2__Tie0_3_3__Imm7s41_3__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTRegs, MCK_MemNoOffsetT2, MCK_Imm7s4 }, }, 13503 { 2570 /* vldr */, ARM::VLDR_FPCXTS_pre, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTS, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, }, 13504 { 2570 /* vldr */, ARM::VLDR_FPCXTS_post, Convert__MemNoOffsetT21_2__Tie0_3_3__Imm7s41_3__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTS, MCK_MemNoOffsetT2, MCK_Imm7s4 }, }, 13505 { 2570 /* vldr */, ARM::VLDR_FPSCR_pre, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasFPRegs_HasV8_1MMainline, { MCK_CondCode, MCK_FPSCR, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, }, 13506 { 2570 /* vldr */, ARM::VLDR_FPSCR_post, Convert__MemNoOffsetT21_2__Tie0_3_3__Imm7s41_3__CondCode2_0, AMFBS_HasFPRegs_HasV8_1MMainline, { MCK_CondCode, MCK_FPSCR, MCK_MemNoOffsetT2, MCK_Imm7s4 }, }, 13507 { 2570 /* vldr */, ARM::VLDR_FPSCR_NZCVQC_pre, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasFPRegs_HasV8_1MMainline, { MCK_CondCode, MCK_FPSCR_NZCVQC, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, }, 13508 { 2570 /* vldr */, ARM::VLDR_FPSCR_NZCVQC_post, Convert__MemNoOffsetT21_2__Tie0_3_3__Imm7s41_3__CondCode2_0, AMFBS_HasFPRegs_HasV8_1MMainline, { MCK_CondCode, MCK_FPSCR_NZCVQC, MCK_MemNoOffsetT2, MCK_Imm7s4 }, }, 13509 { 2570 /* vldr */, ARM::VLDR_P0_pre, Convert__imm_95_0__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_P0, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, }, 13510 { 2570 /* vldr */, ARM::VLDR_P0_post, Convert__imm_95_0__MemNoOffsetT21_2__Tie1_3_3__Imm7s41_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_P0, MCK_MemNoOffsetT2, MCK_Imm7s4 }, }, 13511 { 2570 /* vldr */, ARM::VLDR_VPR_pre, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_VCCR, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, }, 13512 { 2570 /* vldr */, ARM::VLDR_VPR_post, Convert__MemNoOffsetT21_2__Tie0_3_3__Imm7s41_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_VCCR, MCK_MemNoOffsetT2, MCK_Imm7s4 }, }, 13513 { 2575 /* vldrb */, ARM::MVE_VLDRBS16_rq, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MemRegRQS0Offset }, }, 13514 { 2575 /* vldrb */, ARM::MVE_VLDRBS16, Convert__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_TMemImm7Shift0Offset }, }, 13515 { 2575 /* vldrb */, ARM::MVE_VLDRBS32_rq, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MemRegRQS0Offset }, }, 13516 { 2575 /* vldrb */, ARM::MVE_VLDRBS32, Convert__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_TMemImm7Shift0Offset }, }, 13517 { 2575 /* vldrb */, ARM::MVE_VLDRBU16_rq, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MemRegRQS0Offset }, }, 13518 { 2575 /* vldrb */, ARM::MVE_VLDRBU16, Convert__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_TMemImm7Shift0Offset }, }, 13519 { 2575 /* vldrb */, ARM::MVE_VLDRBU32_rq, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MemRegRQS0Offset }, }, 13520 { 2575 /* vldrb */, ARM::MVE_VLDRBU32, Convert__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_TMemImm7Shift0Offset }, }, 13521 { 2575 /* vldrb */, ARM::MVE_VLDRBU8, Convert__Reg1_2__MemImm7Shift0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_MQPR, MCK_MemImm7Shift0Offset }, }, 13522 { 2575 /* vldrb */, ARM::MVE_VLDRBU8_rq, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_MQPR, MCK_MemRegRQS0Offset }, }, 13523 { 2575 /* vldrb */, ARM::MVE_VLDRBS16_post, Convert__MemNoOffsetT1_3__Reg1_2__Tie0_4_4__Imm7Shift01_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MemNoOffsetT, MCK_Imm7Shift0 }, }, 13524 { 2575 /* vldrb */, ARM::MVE_VLDRBS16_pre, Convert__imm_95_0__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_TMemImm7Shift0Offset, MCK__EXCLAIM_ }, }, 13525 { 2575 /* vldrb */, ARM::MVE_VLDRBS32_post, Convert__MemNoOffsetT1_3__Reg1_2__Tie0_4_4__Imm7Shift01_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MemNoOffsetT, MCK_Imm7Shift0 }, }, 13526 { 2575 /* vldrb */, ARM::MVE_VLDRBS32_pre, Convert__imm_95_0__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_TMemImm7Shift0Offset, MCK__EXCLAIM_ }, }, 13527 { 2575 /* vldrb */, ARM::MVE_VLDRBU16_post, Convert__MemNoOffsetT1_3__Reg1_2__Tie0_4_4__Imm7Shift01_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MemNoOffsetT, MCK_Imm7Shift0 }, }, 13528 { 2575 /* vldrb */, ARM::MVE_VLDRBU16_pre, Convert__imm_95_0__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_TMemImm7Shift0Offset, MCK__EXCLAIM_ }, }, 13529 { 2575 /* vldrb */, ARM::MVE_VLDRBU32_post, Convert__MemNoOffsetT1_3__Reg1_2__Tie0_4_4__Imm7Shift01_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MemNoOffsetT, MCK_Imm7Shift0 }, }, 13530 { 2575 /* vldrb */, ARM::MVE_VLDRBU32_pre, Convert__imm_95_0__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_TMemImm7Shift0Offset, MCK__EXCLAIM_ }, }, 13531 { 2575 /* vldrb */, ARM::MVE_VLDRBU8_pre, Convert__imm_95_0__Reg1_2__MemImm7Shift0OffsetWB2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_MQPR, MCK_MemImm7Shift0OffsetWB, MCK__EXCLAIM_ }, }, 13532 { 2575 /* vldrb */, ARM::MVE_VLDRBU8_post, Convert__MemNoOffsetT2NoSp1_3__Reg1_2__Tie0_4_4__Imm7Shift01_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_MQPR, MCK_MemNoOffsetT2NoSp, MCK_Imm7Shift0 }, }, 13533 { 2581 /* vldrd */, ARM::MVE_VLDRDU64_qi, Convert__Reg1_2__MemRegQS3Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u64, MCK_MQPR, MCK_MemRegQS3Offset }, }, 13534 { 2581 /* vldrd */, ARM::MVE_VLDRDU64_rq_u, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u64, MCK_MQPR, MCK_MemRegRQS0Offset }, }, 13535 { 2581 /* vldrd */, ARM::MVE_VLDRDU64_rq, Convert__Reg1_2__MemRegRQS3Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u64, MCK_MQPR, MCK_MemRegRQS3Offset }, }, 13536 { 2581 /* vldrd */, ARM::MVE_VLDRDU64_qi_pre, Convert__imm_95_0__Reg1_2__MemRegQS3Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u64, MCK_MQPR, MCK_MemRegQS3Offset, MCK__EXCLAIM_ }, }, 13537 { 2587 /* vldrh */, ARM::MVE_VLDRHS32_rq_u, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MemRegRQS0Offset }, }, 13538 { 2587 /* vldrh */, ARM::MVE_VLDRHS32_rq, Convert__Reg1_2__MemRegRQS1Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MemRegRQS1Offset }, }, 13539 { 2587 /* vldrh */, ARM::MVE_VLDRHS32, Convert__Reg1_2__TMemImm7Shift1Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_TMemImm7Shift1Offset }, }, 13540 { 2587 /* vldrh */, ARM::MVE_VLDRHU16, Convert__Reg1_2__MemImm7Shift1Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MemImm7Shift1Offset }, }, 13541 { 2587 /* vldrh */, ARM::MVE_VLDRHU16_rq_u, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MemRegRQS0Offset }, }, 13542 { 2587 /* vldrh */, ARM::MVE_VLDRHU16_rq, Convert__Reg1_2__MemRegRQS1Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MemRegRQS1Offset }, }, 13543 { 2587 /* vldrh */, ARM::MVE_VLDRHU32_rq_u, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MemRegRQS0Offset }, }, 13544 { 2587 /* vldrh */, ARM::MVE_VLDRHU32_rq, Convert__Reg1_2__MemRegRQS1Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MemRegRQS1Offset }, }, 13545 { 2587 /* vldrh */, ARM::MVE_VLDRHU32, Convert__Reg1_2__TMemImm7Shift1Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_TMemImm7Shift1Offset }, }, 13546 { 2587 /* vldrh */, ARM::MVE_VLDRHS32_post, Convert__MemNoOffsetT1_3__Reg1_2__Tie0_4_4__Imm7Shift11_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MemNoOffsetT, MCK_Imm7Shift1 }, }, 13547 { 2587 /* vldrh */, ARM::MVE_VLDRHS32_pre, Convert__imm_95_0__Reg1_2__TMemImm7Shift1Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_TMemImm7Shift1Offset, MCK__EXCLAIM_ }, }, 13548 { 2587 /* vldrh */, ARM::MVE_VLDRHU16_pre, Convert__imm_95_0__Reg1_2__MemImm7Shift1OffsetWB2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MemImm7Shift1OffsetWB, MCK__EXCLAIM_ }, }, 13549 { 2587 /* vldrh */, ARM::MVE_VLDRHU16_post, Convert__MemNoOffsetT2NoSp1_3__Reg1_2__Tie0_4_4__Imm7Shift11_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MemNoOffsetT2NoSp, MCK_Imm7Shift1 }, }, 13550 { 2587 /* vldrh */, ARM::MVE_VLDRHU32_post, Convert__MemNoOffsetT1_3__Reg1_2__Tie0_4_4__Imm7Shift11_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MemNoOffsetT, MCK_Imm7Shift1 }, }, 13551 { 2587 /* vldrh */, ARM::MVE_VLDRHU32_pre, Convert__imm_95_0__Reg1_2__TMemImm7Shift1Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_TMemImm7Shift1Offset, MCK__EXCLAIM_ }, }, 13552 { 2593 /* vldrw */, ARM::MVE_VLDRWU32, Convert__Reg1_2__MemImm7Shift2Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MemImm7Shift2Offset }, }, 13553 { 2593 /* vldrw */, ARM::MVE_VLDRWU32_qi, Convert__Reg1_2__MemRegQS2Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MemRegQS2Offset }, }, 13554 { 2593 /* vldrw */, ARM::MVE_VLDRWU32_rq_u, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MemRegRQS0Offset }, }, 13555 { 2593 /* vldrw */, ARM::MVE_VLDRWU32_rq, Convert__Reg1_2__MemRegRQS2Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MemRegRQS2Offset }, }, 13556 { 2593 /* vldrw */, ARM::MVE_VLDRWU32_pre, Convert__imm_95_0__Reg1_2__MemImm7Shift2OffsetWB2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MemImm7Shift2OffsetWB, MCK__EXCLAIM_ }, }, 13557 { 2593 /* vldrw */, ARM::MVE_VLDRWU32_post, Convert__MemNoOffsetT2NoSp1_3__Reg1_2__Tie0_4_4__Imm7Shift21_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MemNoOffsetT2NoSp, MCK_Imm7Shift2 }, }, 13558 { 2593 /* vldrw */, ARM::MVE_VLDRWU32_qi_pre, Convert__imm_95_0__Reg1_2__MemRegQS2Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MemRegQS2Offset, MCK__EXCLAIM_ }, }, 13559 { 2599 /* vlldm */, ARM::VLLDM, Convert__Reg1_1__CondCode2_0, AMFBS_HasV8MMainline_Has8MSecExt, { MCK_CondCode, MCK_GPRnopc }, }, 13560 { 2605 /* vlstm */, ARM::VLSTM, Convert__Reg1_1__CondCode2_0, AMFBS_HasV8MMainline_Has8MSecExt, { MCK_CondCode, MCK_GPRnopc }, }, 13561 { 2611 /* vmax */, ARM::VMAXsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 13562 { 2611 /* vmax */, ARM::VMAXsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 13563 { 2611 /* vmax */, ARM::VMAXsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 13564 { 2611 /* vmax */, ARM::VMAXsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 13565 { 2611 /* vmax */, ARM::VMAXsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, }, 13566 { 2611 /* vmax */, ARM::VMAXsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 13567 { 2611 /* vmax */, ARM::VMAXuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, }, 13568 { 2611 /* vmax */, ARM::VMAXuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, }, 13569 { 2611 /* vmax */, ARM::VMAXuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, }, 13570 { 2611 /* vmax */, ARM::VMAXuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, }, 13571 { 2611 /* vmax */, ARM::VMAXuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, }, 13572 { 2611 /* vmax */, ARM::VMAXuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, }, 13573 { 2611 /* vmax */, ARM::VMAXfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 13574 { 2611 /* vmax */, ARM::VMAXfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 13575 { 2611 /* vmax */, ARM::VMAXhq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 13576 { 2611 /* vmax */, ARM::VMAXhd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 13577 { 2611 /* vmax */, ARM::VMAXsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13578 { 2611 /* vmax */, ARM::VMAXsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13579 { 2611 /* vmax */, ARM::VMAXsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13580 { 2611 /* vmax */, ARM::VMAXsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13581 { 2611 /* vmax */, ARM::VMAXsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13582 { 2611 /* vmax */, ARM::VMAXsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13583 { 2611 /* vmax */, ARM::VMAXuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13584 { 2611 /* vmax */, ARM::VMAXuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13585 { 2611 /* vmax */, ARM::VMAXuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13586 { 2611 /* vmax */, ARM::VMAXuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13587 { 2611 /* vmax */, ARM::VMAXuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13588 { 2611 /* vmax */, ARM::VMAXuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13589 { 2611 /* vmax */, ARM::VMAXfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13590 { 2611 /* vmax */, ARM::VMAXfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13591 { 2611 /* vmax */, ARM::VMAXhq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13592 { 2611 /* vmax */, ARM::VMAXhd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13593 { 2611 /* vmax */, ARM::MVE_VMAXs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13594 { 2611 /* vmax */, ARM::MVE_VMAXs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13595 { 2611 /* vmax */, ARM::MVE_VMAXs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13596 { 2611 /* vmax */, ARM::MVE_VMAXu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13597 { 2611 /* vmax */, ARM::MVE_VMAXu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13598 { 2611 /* vmax */, ARM::MVE_VMAXu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13599 { 2616 /* vmaxa */, ARM::MVE_VMAXAs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, }, 13600 { 2616 /* vmaxa */, ARM::MVE_VMAXAs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, }, 13601 { 2616 /* vmaxa */, ARM::MVE_VMAXAs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR }, }, 13602 { 2622 /* vmaxav */, ARM::MVE_VMAXAVs16, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_rGPR, MCK_MQPR }, }, 13603 { 2622 /* vmaxav */, ARM::MVE_VMAXAVs32, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_rGPR, MCK_MQPR }, }, 13604 { 2622 /* vmaxav */, ARM::MVE_VMAXAVs8, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_rGPR, MCK_MQPR }, }, 13605 { 2629 /* vmaxnm */, ARM::NEON_VMAXNMNQf, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13606 { 2629 /* vmaxnm */, ARM::NEON_VMAXNMNDf, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13607 { 2629 /* vmaxnm */, ARM::VFP_VMAXNMS, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, }, 13608 { 2629 /* vmaxnm */, ARM::VFP_VMAXNMD, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13609 { 2629 /* vmaxnm */, ARM::NEON_VMAXNMNQh, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13610 { 2629 /* vmaxnm */, ARM::NEON_VMAXNMNDh, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13611 { 2629 /* vmaxnm */, ARM::VFP_VMAXNMH, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, }, 13612 { 2629 /* vmaxnm */, ARM::MVE_VMAXNMf32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13613 { 2629 /* vmaxnm */, ARM::MVE_VMAXNMf16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13614 { 2636 /* vmaxnma */, ARM::MVE_VMAXNMAf32, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, }, 13615 { 2636 /* vmaxnma */, ARM::MVE_VMAXNMAf16, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, }, 13616 { 2644 /* vmaxnmav */, ARM::MVE_VMAXNMAVf32, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f32, MCK_rGPR, MCK_MQPR }, }, 13617 { 2644 /* vmaxnmav */, ARM::MVE_VMAXNMAVf16, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK_rGPR, MCK_MQPR }, }, 13618 { 2653 /* vmaxnmv */, ARM::MVE_VMAXNMVf32, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f32, MCK_rGPR, MCK_MQPR }, }, 13619 { 2653 /* vmaxnmv */, ARM::MVE_VMAXNMVf16, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK_rGPR, MCK_MQPR }, }, 13620 { 2661 /* vmaxv */, ARM::MVE_VMAXVs16, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_rGPR, MCK_MQPR }, }, 13621 { 2661 /* vmaxv */, ARM::MVE_VMAXVs32, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_rGPR, MCK_MQPR }, }, 13622 { 2661 /* vmaxv */, ARM::MVE_VMAXVs8, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_rGPR, MCK_MQPR }, }, 13623 { 2661 /* vmaxv */, ARM::MVE_VMAXVu16, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_rGPR, MCK_MQPR }, }, 13624 { 2661 /* vmaxv */, ARM::MVE_VMAXVu32, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_rGPR, MCK_MQPR }, }, 13625 { 2661 /* vmaxv */, ARM::MVE_VMAXVu8, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_rGPR, MCK_MQPR }, }, 13626 { 2667 /* vmin */, ARM::VMINsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 13627 { 2667 /* vmin */, ARM::VMINsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 13628 { 2667 /* vmin */, ARM::VMINsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 13629 { 2667 /* vmin */, ARM::VMINsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 13630 { 2667 /* vmin */, ARM::VMINsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, }, 13631 { 2667 /* vmin */, ARM::VMINsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 13632 { 2667 /* vmin */, ARM::VMINuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, }, 13633 { 2667 /* vmin */, ARM::VMINuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, }, 13634 { 2667 /* vmin */, ARM::VMINuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, }, 13635 { 2667 /* vmin */, ARM::VMINuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, }, 13636 { 2667 /* vmin */, ARM::VMINuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, }, 13637 { 2667 /* vmin */, ARM::VMINuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, }, 13638 { 2667 /* vmin */, ARM::VMINfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 13639 { 2667 /* vmin */, ARM::VMINfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 13640 { 2667 /* vmin */, ARM::VMINhq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 13641 { 2667 /* vmin */, ARM::VMINhd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 13642 { 2667 /* vmin */, ARM::VMINsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13643 { 2667 /* vmin */, ARM::VMINsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13644 { 2667 /* vmin */, ARM::VMINsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13645 { 2667 /* vmin */, ARM::VMINsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13646 { 2667 /* vmin */, ARM::VMINsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13647 { 2667 /* vmin */, ARM::VMINsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13648 { 2667 /* vmin */, ARM::VMINuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13649 { 2667 /* vmin */, ARM::VMINuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13650 { 2667 /* vmin */, ARM::VMINuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13651 { 2667 /* vmin */, ARM::VMINuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13652 { 2667 /* vmin */, ARM::VMINuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13653 { 2667 /* vmin */, ARM::VMINuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13654 { 2667 /* vmin */, ARM::VMINfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13655 { 2667 /* vmin */, ARM::VMINfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13656 { 2667 /* vmin */, ARM::VMINhq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13657 { 2667 /* vmin */, ARM::VMINhd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13658 { 2667 /* vmin */, ARM::MVE_VMINs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13659 { 2667 /* vmin */, ARM::MVE_VMINs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13660 { 2667 /* vmin */, ARM::MVE_VMINs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13661 { 2667 /* vmin */, ARM::MVE_VMINu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13662 { 2667 /* vmin */, ARM::MVE_VMINu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13663 { 2667 /* vmin */, ARM::MVE_VMINu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13664 { 2672 /* vmina */, ARM::MVE_VMINAs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, }, 13665 { 2672 /* vmina */, ARM::MVE_VMINAs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, }, 13666 { 2672 /* vmina */, ARM::MVE_VMINAs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR }, }, 13667 { 2678 /* vminav */, ARM::MVE_VMINAVs16, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_rGPR, MCK_MQPR }, }, 13668 { 2678 /* vminav */, ARM::MVE_VMINAVs32, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_rGPR, MCK_MQPR }, }, 13669 { 2678 /* vminav */, ARM::MVE_VMINAVs8, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_rGPR, MCK_MQPR }, }, 13670 { 2685 /* vminnm */, ARM::NEON_VMINNMNQf, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13671 { 2685 /* vminnm */, ARM::NEON_VMINNMNDf, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13672 { 2685 /* vminnm */, ARM::VFP_VMINNMS, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, }, 13673 { 2685 /* vminnm */, ARM::VFP_VMINNMD, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13674 { 2685 /* vminnm */, ARM::NEON_VMINNMNQh, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13675 { 2685 /* vminnm */, ARM::NEON_VMINNMNDh, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13676 { 2685 /* vminnm */, ARM::VFP_VMINNMH, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, }, 13677 { 2685 /* vminnm */, ARM::MVE_VMINNMf32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13678 { 2685 /* vminnm */, ARM::MVE_VMINNMf16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13679 { 2692 /* vminnma */, ARM::MVE_VMINNMAf32, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, }, 13680 { 2692 /* vminnma */, ARM::MVE_VMINNMAf16, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, }, 13681 { 2700 /* vminnmav */, ARM::MVE_VMINNMAVf32, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f32, MCK_rGPR, MCK_MQPR }, }, 13682 { 2700 /* vminnmav */, ARM::MVE_VMINNMAVf16, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK_rGPR, MCK_MQPR }, }, 13683 { 2709 /* vminnmv */, ARM::MVE_VMINNMVf32, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f32, MCK_rGPR, MCK_MQPR }, }, 13684 { 2709 /* vminnmv */, ARM::MVE_VMINNMVf16, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK_rGPR, MCK_MQPR }, }, 13685 { 2717 /* vminv */, ARM::MVE_VMINVs16, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_rGPR, MCK_MQPR }, }, 13686 { 2717 /* vminv */, ARM::MVE_VMINVs32, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_rGPR, MCK_MQPR }, }, 13687 { 2717 /* vminv */, ARM::MVE_VMINVs8, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_rGPR, MCK_MQPR }, }, 13688 { 2717 /* vminv */, ARM::MVE_VMINVu16, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_rGPR, MCK_MQPR }, }, 13689 { 2717 /* vminv */, ARM::MVE_VMINVu32, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_rGPR, MCK_MQPR }, }, 13690 { 2717 /* vminv */, ARM::MVE_VMINVu8, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_rGPR, MCK_MQPR }, }, 13691 { 2723 /* vmla */, ARM::VMLAfq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13692 { 2723 /* vmla */, ARM::VMLAfd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13693 { 2723 /* vmla */, ARM::VMLAS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, }, 13694 { 2723 /* vmla */, ARM::VMLAD, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13695 { 2723 /* vmla */, ARM::VMLAv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13696 { 2723 /* vmla */, ARM::VMLAv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13697 { 2723 /* vmla */, ARM::VMLAv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13698 { 2723 /* vmla */, ARM::VMLAv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13699 { 2723 /* vmla */, ARM::VMLAv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13700 { 2723 /* vmla */, ARM::VMLAv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13701 { 2723 /* vmla */, ARM::VMLAhq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13702 { 2723 /* vmla */, ARM::VMLAhd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13703 { 2723 /* vmla */, ARM::VMLAH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, }, 13704 { 2723 /* vmla */, ARM::MVE_VMLA_qr_i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 13705 { 2723 /* vmla */, ARM::MVE_VMLA_qr_i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 13706 { 2723 /* vmla */, ARM::MVE_VMLA_qr_i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 13707 { 2723 /* vmla */, ARM::VMLAslfq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 13708 { 2723 /* vmla */, ARM::VMLAslfd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 13709 { 2723 /* vmla */, ARM::VMLAslv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 13710 { 2723 /* vmla */, ARM::VMLAslv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 13711 { 2723 /* vmla */, ARM::VMLAslv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 13712 { 2723 /* vmla */, ARM::VMLAslv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 13713 { 2723 /* vmla */, ARM::VMLAslhq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 13714 { 2723 /* vmla */, ARM::VMLAslhd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 13715 { 2728 /* vmladav */, ARM::MVE_VMLADAVs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13716 { 2728 /* vmladav */, ARM::MVE_VMLADAVs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13717 { 2728 /* vmladav */, ARM::MVE_VMLADAVs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13718 { 2728 /* vmladav */, ARM::MVE_VMLADAVu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13719 { 2728 /* vmladav */, ARM::MVE_VMLADAVu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13720 { 2728 /* vmladav */, ARM::MVE_VMLADAVu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13721 { 2736 /* vmladava */, ARM::MVE_VMLADAVas16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13722 { 2736 /* vmladava */, ARM::MVE_VMLADAVas32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13723 { 2736 /* vmladava */, ARM::MVE_VMLADAVas8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13724 { 2736 /* vmladava */, ARM::MVE_VMLADAVau16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13725 { 2736 /* vmladava */, ARM::MVE_VMLADAVau32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13726 { 2736 /* vmladava */, ARM::MVE_VMLADAVau8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13727 { 2745 /* vmladavax */, ARM::MVE_VMLADAVaxs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13728 { 2745 /* vmladavax */, ARM::MVE_VMLADAVaxs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13729 { 2745 /* vmladavax */, ARM::MVE_VMLADAVaxs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13730 { 2755 /* vmladavx */, ARM::MVE_VMLADAVxs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13731 { 2755 /* vmladavx */, ARM::MVE_VMLADAVxs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13732 { 2755 /* vmladavx */, ARM::MVE_VMLADAVxs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13733 { 2764 /* vmlal */, ARM::VMLALsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, }, 13734 { 2764 /* vmlal */, ARM::VMLALsv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, }, 13735 { 2764 /* vmlal */, ARM::VMLALsv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR, MCK_DPR }, }, 13736 { 2764 /* vmlal */, ARM::VMLALuv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR }, }, 13737 { 2764 /* vmlal */, ARM::VMLALuv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR }, }, 13738 { 2764 /* vmlal */, ARM::VMLALuv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR, MCK_DPR }, }, 13739 { 2764 /* vmlal */, ARM::VMLALslsv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 13740 { 2764 /* vmlal */, ARM::VMLALslsv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 13741 { 2764 /* vmlal */, ARM::VMLALsluv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 13742 { 2764 /* vmlal */, ARM::VMLALsluv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 13743 { 2770 /* vmlaldav */, ARM::MVE_VMLALDAVs16, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 13744 { 2770 /* vmlaldav */, ARM::MVE_VMLALDAVs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 13745 { 2770 /* vmlaldav */, ARM::MVE_VMLALDAVu16, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 13746 { 2770 /* vmlaldav */, ARM::MVE_VMLALDAVu32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 13747 { 2779 /* vmlaldava */, ARM::MVE_VMLALDAVas16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 13748 { 2779 /* vmlaldava */, ARM::MVE_VMLALDAVas32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 13749 { 2779 /* vmlaldava */, ARM::MVE_VMLALDAVau16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 13750 { 2779 /* vmlaldava */, ARM::MVE_VMLALDAVau32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 13751 { 2789 /* vmlaldavax */, ARM::MVE_VMLALDAVaxs16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 13752 { 2789 /* vmlaldavax */, ARM::MVE_VMLALDAVaxs32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 13753 { 2800 /* vmlaldavx */, ARM::MVE_VMLALDAVxs16, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 13754 { 2800 /* vmlaldavx */, ARM::MVE_VMLALDAVxs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 13755 { 2810 /* vmlalv */, ARM::MVE_VMLALDAVs16, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 13756 { 2810 /* vmlalv */, ARM::MVE_VMLALDAVs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 13757 { 2810 /* vmlalv */, ARM::MVE_VMLALDAVu16, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 13758 { 2810 /* vmlalv */, ARM::MVE_VMLALDAVu32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 13759 { 2817 /* vmlalva */, ARM::MVE_VMLALDAVas16, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 13760 { 2817 /* vmlalva */, ARM::MVE_VMLALDAVas32, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 13761 { 2817 /* vmlalva */, ARM::MVE_VMLALDAVau16, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 13762 { 2817 /* vmlalva */, ARM::MVE_VMLALDAVau32, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 13763 { 2825 /* vmlas */, ARM::MVE_VMLAS_qr_i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 13764 { 2825 /* vmlas */, ARM::MVE_VMLAS_qr_i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 13765 { 2825 /* vmlas */, ARM::MVE_VMLAS_qr_i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 13766 { 2831 /* vmlav */, ARM::MVE_VMLADAVs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13767 { 2831 /* vmlav */, ARM::MVE_VMLADAVs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13768 { 2831 /* vmlav */, ARM::MVE_VMLADAVs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13769 { 2831 /* vmlav */, ARM::MVE_VMLADAVu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13770 { 2831 /* vmlav */, ARM::MVE_VMLADAVu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13771 { 2831 /* vmlav */, ARM::MVE_VMLADAVu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13772 { 2837 /* vmlava */, ARM::MVE_VMLADAVas16, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13773 { 2837 /* vmlava */, ARM::MVE_VMLADAVas32, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13774 { 2837 /* vmlava */, ARM::MVE_VMLADAVas8, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13775 { 2837 /* vmlava */, ARM::MVE_VMLADAVau16, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13776 { 2837 /* vmlava */, ARM::MVE_VMLADAVau32, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13777 { 2837 /* vmlava */, ARM::MVE_VMLADAVau8, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13778 { 2844 /* vmls */, ARM::VMLSfq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13779 { 2844 /* vmls */, ARM::VMLSfd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13780 { 2844 /* vmls */, ARM::VMLSS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, }, 13781 { 2844 /* vmls */, ARM::VMLSD, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13782 { 2844 /* vmls */, ARM::VMLSv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13783 { 2844 /* vmls */, ARM::VMLSv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13784 { 2844 /* vmls */, ARM::VMLSv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13785 { 2844 /* vmls */, ARM::VMLSv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13786 { 2844 /* vmls */, ARM::VMLSv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13787 { 2844 /* vmls */, ARM::VMLSv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13788 { 2844 /* vmls */, ARM::VMLShq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13789 { 2844 /* vmls */, ARM::VMLShd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13790 { 2844 /* vmls */, ARM::VMLSH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, }, 13791 { 2844 /* vmls */, ARM::VMLSslfq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 13792 { 2844 /* vmls */, ARM::VMLSslfd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 13793 { 2844 /* vmls */, ARM::VMLSslv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 13794 { 2844 /* vmls */, ARM::VMLSslv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 13795 { 2844 /* vmls */, ARM::VMLSslv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 13796 { 2844 /* vmls */, ARM::VMLSslv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 13797 { 2844 /* vmls */, ARM::VMLSslhq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 13798 { 2844 /* vmls */, ARM::VMLSslhd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 13799 { 2849 /* vmlsdav */, ARM::MVE_VMLSDAVs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13800 { 2849 /* vmlsdav */, ARM::MVE_VMLSDAVs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13801 { 2849 /* vmlsdav */, ARM::MVE_VMLSDAVs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13802 { 2857 /* vmlsdava */, ARM::MVE_VMLSDAVas16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13803 { 2857 /* vmlsdava */, ARM::MVE_VMLSDAVas32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13804 { 2857 /* vmlsdava */, ARM::MVE_VMLSDAVas8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13805 { 2866 /* vmlsdavax */, ARM::MVE_VMLSDAVaxs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13806 { 2866 /* vmlsdavax */, ARM::MVE_VMLSDAVaxs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13807 { 2866 /* vmlsdavax */, ARM::MVE_VMLSDAVaxs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13808 { 2876 /* vmlsdavx */, ARM::MVE_VMLSDAVxs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13809 { 2876 /* vmlsdavx */, ARM::MVE_VMLSDAVxs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13810 { 2876 /* vmlsdavx */, ARM::MVE_VMLSDAVxs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, }, 13811 { 2885 /* vmlsl */, ARM::VMLSLsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, }, 13812 { 2885 /* vmlsl */, ARM::VMLSLsv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, }, 13813 { 2885 /* vmlsl */, ARM::VMLSLsv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR, MCK_DPR }, }, 13814 { 2885 /* vmlsl */, ARM::VMLSLuv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR }, }, 13815 { 2885 /* vmlsl */, ARM::VMLSLuv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR }, }, 13816 { 2885 /* vmlsl */, ARM::VMLSLuv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR, MCK_DPR }, }, 13817 { 2885 /* vmlsl */, ARM::VMLSLslsv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 13818 { 2885 /* vmlsl */, ARM::VMLSLslsv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 13819 { 2885 /* vmlsl */, ARM::VMLSLsluv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 13820 { 2885 /* vmlsl */, ARM::VMLSLsluv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 13821 { 2891 /* vmlsldav */, ARM::MVE_VMLSLDAVs16, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 13822 { 2891 /* vmlsldav */, ARM::MVE_VMLSLDAVs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 13823 { 2900 /* vmlsldava */, ARM::MVE_VMLSLDAVas16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 13824 { 2900 /* vmlsldava */, ARM::MVE_VMLSLDAVas32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 13825 { 2910 /* vmlsldavax */, ARM::MVE_VMLSLDAVaxs16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 13826 { 2910 /* vmlsldavax */, ARM::MVE_VMLSLDAVaxs32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 13827 { 2921 /* vmlsldavx */, ARM::MVE_VMLSLDAVxs16, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 13828 { 2921 /* vmlsldavx */, ARM::MVE_VMLSLDAVxs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 13829 { 2931 /* vmmla */, ARM::VMMLA, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasBF16_HasNEON, { MCK__DOT_bf16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13830 { 2937 /* vmov */, ARM::VMOVRS, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK_HPR }, }, 13831 { 2937 /* vmov */, ARM::VORRq, Convert__Reg1_1__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR }, }, 13832 { 2937 /* vmov */, ARM::VORRd, Convert__Reg1_1__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR }, }, 13833 { 2937 /* vmov */, ARM::VMOVSR, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_HPR, MCK_GPR }, }, 13834 { 2937 /* vmov */, ARM::VMOVS, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_HPR, MCK_HPR }, }, 13835 { 2937 /* vmov */, ARM::MVE_VORR, Convert__Reg1_1__Reg1_2__Reg1_2__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK_MQPR, MCK_MQPR }, }, 13836 { 2937 /* vmov */, ARM::VMOVv4f32, Convert__Reg1_2__FPImm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_FPImm }, }, 13837 { 2937 /* vmov */, ARM::VMOVv4i32, Convert__Reg1_2__NEONi32vmov1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_NEONi32vmov }, }, 13838 { 2937 /* vmov */, ARM::VMOVv2f32, Convert__Reg1_2__FPImm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_FPImm }, }, 13839 { 2937 /* vmov */, ARM::VMOVv2i32, Convert__Reg1_2__NEONi32vmov1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_NEONi32vmov }, }, 13840 { 2937 /* vmov */, ARM::VMOVS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 13841 { 2937 /* vmov */, ARM::FCONSTS, Convert__Reg1_2__FPImm1_3__CondCode2_0, AMFBS_HasVFP3, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_FPImm }, }, 13842 { 2937 /* vmov */, ARM::VMOVD, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPRegs64, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 13843 { 2937 /* vmov */, ARM::FCONSTD, Convert__Reg1_2__FPImm1_3__CondCode2_0, AMFBS_HasVFP3_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_FPImm }, }, 13844 { 2937 /* vmov */, ARM::VMOVv16i8, Convert__Reg1_2__NEONi16vmovi8Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_NEONi16vmovi8Replicate }, }, 13845 { 2937 /* vmov */, ARM::VMOVv8i16, Convert__Reg1_2__NEONi16splat1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_NEONi16splat }, }, 13846 { 2937 /* vmov */, ARM::VMOVv8i8, Convert__Reg1_2__NEONi16vmovi8Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_NEONi16vmovi8Replicate }, }, 13847 { 2937 /* vmov */, ARM::VMOVv4i16, Convert__Reg1_2__NEONi16splat1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_NEONi16splat }, }, 13848 { 2937 /* vmov */, ARM::VMOVv16i8, Convert__Reg1_2__NEONi32vmovi8Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32vmovi8Replicate }, }, 13849 { 2937 /* vmov */, ARM::VMOVv8i16, Convert__Reg1_2__NEONi32vmovi16Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32vmovi16Replicate }, }, 13850 { 2937 /* vmov */, ARM::VMOVv4i32, Convert__Reg1_2__NEONi32vmov1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32vmov }, }, 13851 { 2937 /* vmov */, ARM::VMVNv4i32, Convert__Reg1_2__NEONi32vmovNeg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32vmovNeg }, }, 13852 { 2937 /* vmov */, ARM::VMOVv8i8, Convert__Reg1_2__NEONi32vmovi8Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32vmovi8Replicate }, }, 13853 { 2937 /* vmov */, ARM::VMOVv4i16, Convert__Reg1_2__NEONi32vmovi16Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32vmovi16Replicate }, }, 13854 { 2937 /* vmov */, ARM::VMOVv2i32, Convert__Reg1_2__NEONi32vmov1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32vmov }, }, 13855 { 2937 /* vmov */, ARM::VMVNv2i32, Convert__Reg1_2__NEONi32vmovNeg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32vmovNeg }, }, 13856 { 2937 /* vmov */, ARM::VMOVv16i8, Convert__Reg1_2__NEONi64vmovi8Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_NEONi64vmovi8Replicate }, }, 13857 { 2937 /* vmov */, ARM::VMOVv8i16, Convert__Reg1_2__NEONi64vmovi16Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_NEONi64vmovi16Replicate }, }, 13858 { 2937 /* vmov */, ARM::VMOVv4i32, Convert__Reg1_2__NEONi64vmovi32Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_NEONi64vmovi32Replicate }, }, 13859 { 2937 /* vmov */, ARM::VMOVv2i64, Convert__Reg1_2__NEONi64splat1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_NEONi64splat }, }, 13860 { 2937 /* vmov */, ARM::VMOVv8i8, Convert__Reg1_2__NEONi64vmovi8Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_NEONi64vmovi8Replicate }, }, 13861 { 2937 /* vmov */, ARM::VMOVv4i16, Convert__Reg1_2__NEONi64vmovi16Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_NEONi64vmovi16Replicate }, }, 13862 { 2937 /* vmov */, ARM::VMOVv2i32, Convert__Reg1_2__NEONi64vmovi32Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_NEONi64vmovi32Replicate }, }, 13863 { 2937 /* vmov */, ARM::VMOVv1i64, Convert__Reg1_2__NEONi64splat1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_NEONi64splat }, }, 13864 { 2937 /* vmov */, ARM::VMOVv16i8, Convert__Reg1_2__NEONi8splat1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_NEONi8splat }, }, 13865 { 2937 /* vmov */, ARM::VMOVv8i8, Convert__Reg1_2__NEONi8splat1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_NEONi8splat }, }, 13866 { 2937 /* vmov */, ARM::VMOVRS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_16, MCK_GPR, MCK_HPR }, }, 13867 { 2937 /* vmov */, ARM::VORRq, Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, }, 13868 { 2937 /* vmov */, ARM::VORRd, Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, }, 13869 { 2937 /* vmov */, ARM::VMOVSR, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_16, MCK_HPR, MCK_GPR }, }, 13870 { 2937 /* vmov */, ARM::VMOVRS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_32, MCK_GPR, MCK_HPR }, }, 13871 { 2937 /* vmov */, ARM::VORRq, Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, }, 13872 { 2937 /* vmov */, ARM::VORRd, Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, }, 13873 { 2937 /* vmov */, ARM::VMOVSR, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_32, MCK_HPR, MCK_GPR }, }, 13874 { 2937 /* vmov */, ARM::VORRq, Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR }, }, 13875 { 2937 /* vmov */, ARM::VORRd, Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR }, }, 13876 { 2937 /* vmov */, ARM::VMOVRS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_8, MCK_GPR, MCK_HPR }, }, 13877 { 2937 /* vmov */, ARM::VORRq, Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, }, 13878 { 2937 /* vmov */, ARM::VORRd, Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, }, 13879 { 2937 /* vmov */, ARM::VMOVSR, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_8, MCK_HPR, MCK_GPR }, }, 13880 { 2937 /* vmov */, ARM::VMOVRH, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPRegs16, { MCK_CondCode, MCK__DOT_f16, MCK_rGPR, MCK_HPR }, }, 13881 { 2937 /* vmov */, ARM::VMOVHR, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPRegs16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_rGPR }, }, 13882 { 2937 /* vmov */, ARM::FCONSTH, Convert__Reg1_2__FPImm1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_FPImm }, }, 13883 { 2937 /* vmov */, ARM::VMOVRRD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_DPR }, }, 13884 { 2937 /* vmov */, ARM::VMOVDRR, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_DPR, MCK_GPR, MCK_GPR }, }, 13885 { 2937 /* vmov */, ARM::MVE_VMOVimmf32, Convert__Reg1_2__FPImm1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_FPImm }, }, 13886 { 2937 /* vmov */, ARM::MVE_VMOVimmi16, Convert__Reg1_2__NEONi16splat1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_NEONi16splat }, }, 13887 { 2937 /* vmov */, ARM::MVE_VMOVimmi32, Convert__Reg1_2__NEONi32vmov1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_NEONi32vmov }, }, 13888 { 2937 /* vmov */, ARM::MVE_VMOVimmi64, Convert__Reg1_2__NEONi64splat1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i64, MCK_MQPR, MCK_NEONi64splat }, }, 13889 { 2937 /* vmov */, ARM::MVE_VMOVimmi8, Convert__Reg1_2__NEONi8splat1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_NEONi8splat }, }, 13890 { 2937 /* vmov */, ARM::MVE_VMOV_from_lane_s16, Convert__Reg1_2__Reg1_3__MVEVectorIndex81_4__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK__DOT_s16, MCK_rGPR, MCK_MQPR, MCK_MVEVectorIndex8 }, }, 13891 { 2937 /* vmov */, ARM::VGETLNs16, Convert__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_GPR, MCK_DPR, MCK_VectorIndex16 }, }, 13892 { 2937 /* vmov */, ARM::MVE_VMOV_from_lane_s8, Convert__Reg1_2__Reg1_3__MVEVectorIndex161_4__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK__DOT_s8, MCK_rGPR, MCK_MQPR, MCK_MVEVectorIndex16 }, }, 13893 { 2937 /* vmov */, ARM::VGETLNs8, Convert__Reg1_2__Reg1_3__VectorIndex81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_GPR, MCK_DPR, MCK_VectorIndex8 }, }, 13894 { 2937 /* vmov */, ARM::MVE_VMOV_from_lane_u16, Convert__Reg1_2__Reg1_3__MVEVectorIndex81_4__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK__DOT_u16, MCK_rGPR, MCK_MQPR, MCK_MVEVectorIndex8 }, }, 13895 { 2937 /* vmov */, ARM::VGETLNu16, Convert__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_GPR, MCK_DPR, MCK_VectorIndex16 }, }, 13896 { 2937 /* vmov */, ARM::MVE_VMOV_from_lane_u8, Convert__Reg1_2__Reg1_3__MVEVectorIndex161_4__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK__DOT_u8, MCK_rGPR, MCK_MQPR, MCK_MVEVectorIndex16 }, }, 13897 { 2937 /* vmov */, ARM::VGETLNu8, Convert__Reg1_2__Reg1_3__VectorIndex81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_GPR, MCK_DPR, MCK_VectorIndex8 }, }, 13898 { 2937 /* vmov */, ARM::VMOVRRD, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f64, MCK_GPR, MCK_GPR, MCK_DPR }, }, 13899 { 2937 /* vmov */, ARM::VMOVDRR, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_GPR, MCK_GPR }, }, 13900 { 2937 /* vmov */, ARM::MVE_VMOV_to_lane_16, Convert__Reg1_2__Tie0_1_1__Reg1_4__MVEVectorIndex81_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK__DOT_16, MCK_MQPR, MCK_MVEVectorIndex8, MCK_rGPR }, }, 13901 { 2937 /* vmov */, ARM::VSETLNi16, Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_VectorIndex16, MCK_GPR }, }, 13902 { 2937 /* vmov */, ARM::MVE_VMOV_to_lane_32, Convert__Reg1_2__Tie0_1_1__Reg1_4__MVEVectorIndex41_3__CondCode2_0, AMFBS_HasFPRegsV8_1M, { MCK_CondCode, MCK__DOT_32, MCK_MQPR, MCK_MVEVectorIndex4, MCK_rGPR }, }, 13903 { 2937 /* vmov */, ARM::MVE_VMOV_from_lane_32, Convert__Reg1_2__Reg1_3__MVEVectorIndex41_4__CondCode2_0, AMFBS_HasFPRegsV8_1M, { MCK_CondCode, MCK__DOT_32, MCK_rGPR, MCK_MQPR, MCK_MVEVectorIndex4 }, }, 13904 { 2937 /* vmov */, ARM::VGETLNi32, Convert__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_32, MCK_GPR, MCK_DPR, MCK_VectorIndex32 }, }, 13905 { 2937 /* vmov */, ARM::VSETLNi32, Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex321_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_VectorIndex32, MCK_GPR }, }, 13906 { 2937 /* vmov */, ARM::MVE_VMOV_to_lane_8, Convert__Reg1_2__Tie0_1_1__Reg1_4__MVEVectorIndex161_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK__DOT_8, MCK_MQPR, MCK_MVEVectorIndex16, MCK_rGPR }, }, 13907 { 2937 /* vmov */, ARM::VSETLNi8, Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_VectorIndex8, MCK_GPR }, }, 13908 { 2937 /* vmov */, ARM::VMOVRRS, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_HPR, MCK_HPR }, }, 13909 { 2937 /* vmov */, ARM::VMOVSRR, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_HPR, MCK_HPR, MCK_GPR, MCK_GPR }, }, 13910 { 2937 /* vmov */, ARM::MVE_VMOV_q_rr, Convert__Reg1_1__Tie0_2_4__Reg1_5__Reg1_6__MVEPairVectorIndex21_2__MVEPairVectorIndex01_4__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_MQPR, MCK_MVEPairVectorIndex2, MCK_MQPR, MCK_MVEPairVectorIndex0, MCK_rGPR, MCK_rGPR }, }, 13911 { 2937 /* vmov */, ARM::MVE_VMOV_rr_q, ConvertCustom_cvtMVEVMOVQtoDReg, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MQPR, MCK_MVEPairVectorIndex2, MCK_MQPR, MCK_MVEPairVectorIndex0 }, }, 13912 { 2942 /* vmovl */, ARM::VMOVLsv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR }, }, 13913 { 2942 /* vmovl */, ARM::VMOVLsv2i64, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR }, }, 13914 { 2942 /* vmovl */, ARM::VMOVLsv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR }, }, 13915 { 2942 /* vmovl */, ARM::VMOVLuv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR }, }, 13916 { 2942 /* vmovl */, ARM::VMOVLuv2i64, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR }, }, 13917 { 2942 /* vmovl */, ARM::VMOVLuv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR }, }, 13918 { 2948 /* vmovlb */, ARM::MVE_VMOVLs16bh, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, }, 13919 { 2948 /* vmovlb */, ARM::MVE_VMOVLs8bh, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR }, }, 13920 { 2948 /* vmovlb */, ARM::MVE_VMOVLu16bh, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR }, }, 13921 { 2948 /* vmovlb */, ARM::MVE_VMOVLu8bh, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR }, }, 13922 { 2955 /* vmovlt */, ARM::MVE_VMOVLs16th, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, }, 13923 { 2955 /* vmovlt */, ARM::MVE_VMOVLs8th, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR }, }, 13924 { 2955 /* vmovlt */, ARM::MVE_VMOVLu16th, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR }, }, 13925 { 2955 /* vmovlt */, ARM::MVE_VMOVLu8th, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR }, }, 13926 { 2962 /* vmovn */, ARM::VMOVNv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_QPR }, }, 13927 { 2962 /* vmovn */, ARM::VMOVNv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_QPR }, }, 13928 { 2962 /* vmovn */, ARM::VMOVNv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_QPR }, }, 13929 { 2968 /* vmovnb */, ARM::MVE_VMOVNi16bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i16, MCK_MQPR, MCK_MQPR }, }, 13930 { 2968 /* vmovnb */, ARM::MVE_VMOVNi32bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_MQPR }, }, 13931 { 2975 /* vmovnt */, ARM::MVE_VMOVNi16th, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i16, MCK_MQPR, MCK_MQPR }, }, 13932 { 2975 /* vmovnt */, ARM::MVE_VMOVNi32th, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_MQPR }, }, 13933 { 2982 /* vmovx */, ARM::VMOVH, Convert__Reg1_1__Reg1_2, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 13934 { 2988 /* vmrs */, ARM::FMSTAT, Convert__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_APSR_NZCV, MCK_FPSCR }, }, 13935 { 2988 /* vmrs */, ARM::VMRS_FPEXC, Convert__Reg1_1__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_GPRnopc, MCK_FPEXC }, }, 13936 { 2988 /* vmrs */, ARM::VMRS_FPINST, Convert__Reg1_1__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_GPRnopc, MCK_FPINST }, }, 13937 { 2988 /* vmrs */, ARM::VMRS_FPINST2, Convert__Reg1_1__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_GPRnopc, MCK_FPINST2 }, }, 13938 { 2988 /* vmrs */, ARM::VMRS, Convert__Reg1_1__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPRnopc, MCK_FPSCR }, }, 13939 { 2988 /* vmrs */, ARM::VMRS_FPSID, Convert__Reg1_1__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_GPRnopc, MCK_FPSID }, }, 13940 { 2988 /* vmrs */, ARM::VMRS_MVFR0, Convert__Reg1_1__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_GPRnopc, MCK_MVFR0 }, }, 13941 { 2988 /* vmrs */, ARM::VMRS_MVFR1, Convert__Reg1_1__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_GPRnopc, MCK_MVFR1 }, }, 13942 { 2988 /* vmrs */, ARM::VMRS_MVFR2, Convert__Reg1_1__CondCode2_0, AMFBS_HasFPARMv8, { MCK_CondCode, MCK_GPRnopc, MCK_MVFR2 }, }, 13943 { 2988 /* vmrs */, ARM::VMRS_FPCXTNS, Convert__Reg1_1__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_GPR, MCK_FPCXTRegs }, }, 13944 { 2988 /* vmrs */, ARM::VMRS_FPCXTS, Convert__Reg1_1__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_GPR, MCK_FPCXTS }, }, 13945 { 2988 /* vmrs */, ARM::VMRS_FPSCR_NZCVQC, Convert__Reg1_1__imm_95_0__CondCode2_0, AMFBS_HasV8_1MMainline_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK_FPSCR_NZCVQC }, }, 13946 { 2988 /* vmrs */, ARM::VMRS_P0, Convert__Reg1_1__imm_95_0__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_GPR, MCK_P0 }, }, 13947 { 2988 /* vmrs */, ARM::VMRS_VPR, Convert__Reg1_1__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_GPR, MCK_VCCR }, }, 13948 { 2993 /* vmsr */, ARM::VMSR_FPCXTNS, Convert__Reg1_2__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTRegs, MCK_GPR }, }, 13949 { 2993 /* vmsr */, ARM::VMSR_FPCXTS, Convert__Reg1_2__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTS, MCK_GPR }, }, 13950 { 2993 /* vmsr */, ARM::VMSR_FPEXC, Convert__Reg1_2__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_FPEXC, MCK_GPRnopc }, }, 13951 { 2993 /* vmsr */, ARM::VMSR_FPINST, Convert__Reg1_2__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_FPINST, MCK_GPRnopc }, }, 13952 { 2993 /* vmsr */, ARM::VMSR_FPINST2, Convert__Reg1_2__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_FPINST2, MCK_GPRnopc }, }, 13953 { 2993 /* vmsr */, ARM::VMSR, Convert__Reg1_2__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_FPSCR, MCK_GPRnopc }, }, 13954 { 2993 /* vmsr */, ARM::VMSR_FPSCR_NZCVQC, Convert__imm_95_0__Reg1_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasFPRegs, { MCK_CondCode, MCK_FPSCR_NZCVQC, MCK_GPR }, }, 13955 { 2993 /* vmsr */, ARM::VMSR_FPSID, Convert__Reg1_2__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_FPSID, MCK_GPRnopc }, }, 13956 { 2993 /* vmsr */, ARM::VMSR_P0, Convert__imm_95_0__Reg1_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_P0, MCK_GPR }, }, 13957 { 2993 /* vmsr */, ARM::VMSR_VPR, Convert__Reg1_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_VCCR, MCK_GPR }, }, 13958 { 2998 /* vmul */, ARM::VMULfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 13959 { 2998 /* vmul */, ARM::VMULfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 13960 { 2998 /* vmul */, ARM::VMULS, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 13961 { 2998 /* vmul */, ARM::VMULD, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 13962 { 2998 /* vmul */, ARM::VMULv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR }, }, 13963 { 2998 /* vmul */, ARM::VMULv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR }, }, 13964 { 2998 /* vmul */, ARM::VMULv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR }, }, 13965 { 2998 /* vmul */, ARM::VMULv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR }, }, 13966 { 2998 /* vmul */, ARM::VMULv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR }, }, 13967 { 2998 /* vmul */, ARM::VMULv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR }, }, 13968 { 2998 /* vmul */, ARM::VMULpq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_p8, MCK_QPR, MCK_QPR }, }, 13969 { 2998 /* vmul */, ARM::VMULpd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_p8, MCK_DPR, MCK_DPR }, }, 13970 { 2998 /* vmul */, ARM::VMULhq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 13971 { 2998 /* vmul */, ARM::VMULhd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 13972 { 2998 /* vmul */, ARM::VMULH, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 13973 { 2998 /* vmul */, ARM::VMULslfq, Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 13974 { 2998 /* vmul */, ARM::VMULfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13975 { 2998 /* vmul */, ARM::VMULslfd, Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 13976 { 2998 /* vmul */, ARM::VMULfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13977 { 2998 /* vmul */, ARM::VMULS, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, }, 13978 { 2998 /* vmul */, ARM::VMULD, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13979 { 2998 /* vmul */, ARM::VMULslv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 13980 { 2998 /* vmul */, ARM::VMULv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13981 { 2998 /* vmul */, ARM::VMULslv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 13982 { 2998 /* vmul */, ARM::VMULv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13983 { 2998 /* vmul */, ARM::VMULslv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 13984 { 2998 /* vmul */, ARM::VMULv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13985 { 2998 /* vmul */, ARM::VMULslv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 13986 { 2998 /* vmul */, ARM::VMULv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13987 { 2998 /* vmul */, ARM::VMULv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13988 { 2998 /* vmul */, ARM::VMULv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13989 { 2998 /* vmul */, ARM::VMULpq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_p8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13990 { 2998 /* vmul */, ARM::VMULpd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_p8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13991 { 2998 /* vmul */, ARM::VMULslhq, Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 13992 { 2998 /* vmul */, ARM::VMULhq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 13993 { 2998 /* vmul */, ARM::VMULslhd, Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 13994 { 2998 /* vmul */, ARM::VMULhd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 13995 { 2998 /* vmul */, ARM::VMULH, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, }, 13996 { 2998 /* vmul */, ARM::MVE_VMULf32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13997 { 2998 /* vmul */, ARM::MVE_VMUL_qr_f32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 13998 { 2998 /* vmul */, ARM::MVE_VMULi16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 13999 { 2998 /* vmul */, ARM::MVE_VMUL_qr_i16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 14000 { 2998 /* vmul */, ARM::MVE_VMULi32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14001 { 2998 /* vmul */, ARM::MVE_VMUL_qr_i32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 14002 { 2998 /* vmul */, ARM::MVE_VMULi8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14003 { 2998 /* vmul */, ARM::MVE_VMUL_qr_i8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 14004 { 2998 /* vmul */, ARM::MVE_VMULf16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14005 { 2998 /* vmul */, ARM::MVE_VMUL_qr_f16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 14006 { 2998 /* vmul */, ARM::VMULslfq, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 14007 { 2998 /* vmul */, ARM::VMULslfd, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 14008 { 2998 /* vmul */, ARM::VMULslv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 14009 { 2998 /* vmul */, ARM::VMULslv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 14010 { 2998 /* vmul */, ARM::VMULslv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 14011 { 2998 /* vmul */, ARM::VMULslv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 14012 { 2998 /* vmul */, ARM::VMULslhq, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 14013 { 2998 /* vmul */, ARM::VMULslhd, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 14014 { 3003 /* vmulh */, ARM::MVE_VMULHs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14015 { 3003 /* vmulh */, ARM::MVE_VMULHs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14016 { 3003 /* vmulh */, ARM::MVE_VMULHs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14017 { 3003 /* vmulh */, ARM::MVE_VMULHu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14018 { 3003 /* vmulh */, ARM::MVE_VMULHu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14019 { 3003 /* vmulh */, ARM::MVE_VMULHu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14020 { 3009 /* vmull */, ARM::VMULLp64, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasV8_HasAES, { MCK__DOT_p64, MCK_QPR, MCK_DPR, MCK_DPR }, }, 14021 { 3009 /* vmull */, ARM::VMULLsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, }, 14022 { 3009 /* vmull */, ARM::VMULLsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, }, 14023 { 3009 /* vmull */, ARM::VMULLsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR, MCK_DPR }, }, 14024 { 3009 /* vmull */, ARM::VMULLuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR }, }, 14025 { 3009 /* vmull */, ARM::VMULLuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR }, }, 14026 { 3009 /* vmull */, ARM::VMULLuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR, MCK_DPR }, }, 14027 { 3009 /* vmull */, ARM::VMULLp8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_p8, MCK_QPR, MCK_DPR, MCK_DPR }, }, 14028 { 3009 /* vmull */, ARM::VMULLslsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 14029 { 3009 /* vmull */, ARM::VMULLslsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 14030 { 3009 /* vmull */, ARM::VMULLsluv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 14031 { 3009 /* vmull */, ARM::VMULLsluv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 14032 { 3015 /* vmullb */, ARM::MVE_VMULLBs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14033 { 3015 /* vmullb */, ARM::MVE_VMULLBs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14034 { 3015 /* vmullb */, ARM::MVE_VMULLBs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14035 { 3015 /* vmullb */, ARM::MVE_VMULLBu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14036 { 3015 /* vmullb */, ARM::MVE_VMULLBu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14037 { 3015 /* vmullb */, ARM::MVE_VMULLBu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14038 { 3015 /* vmullb */, ARM::MVE_VMULLBp16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_p16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14039 { 3015 /* vmullb */, ARM::MVE_VMULLBp8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_p8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14040 { 3022 /* vmullt */, ARM::MVE_VMULLTs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14041 { 3022 /* vmullt */, ARM::MVE_VMULLTs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14042 { 3022 /* vmullt */, ARM::MVE_VMULLTs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14043 { 3022 /* vmullt */, ARM::MVE_VMULLTu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14044 { 3022 /* vmullt */, ARM::MVE_VMULLTu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14045 { 3022 /* vmullt */, ARM::MVE_VMULLTu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14046 { 3022 /* vmullt */, ARM::MVE_VMULLTp16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_p16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14047 { 3022 /* vmullt */, ARM::MVE_VMULLTp8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_p8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14048 { 3029 /* vmvn */, ARM::VMVNq, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR }, }, 14049 { 3029 /* vmvn */, ARM::VMVNd, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR }, }, 14050 { 3029 /* vmvn */, ARM::MVE_VMVN, Convert__Reg1_1__Reg1_2__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK_MQPR, MCK_MQPR }, }, 14051 { 3029 /* vmvn */, ARM::VMOVv16i8, Convert__Reg1_2__NEONi16invi8Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_NEONi16invi8Replicate }, }, 14052 { 3029 /* vmvn */, ARM::VMVNv8i16, Convert__Reg1_2__NEONi16splat1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_NEONi16splat }, }, 14053 { 3029 /* vmvn */, ARM::VMOVv8i8, Convert__Reg1_2__NEONi16invi8Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_NEONi16invi8Replicate }, }, 14054 { 3029 /* vmvn */, ARM::VMVNv4i16, Convert__Reg1_2__NEONi16splat1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_NEONi16splat }, }, 14055 { 3029 /* vmvn */, ARM::VMOVv16i8, Convert__Reg1_2__NEONi32invi8Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32invi8Replicate }, }, 14056 { 3029 /* vmvn */, ARM::VMVNv8i16, Convert__Reg1_2__NEONi32vmovi16Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32vmovi16Replicate }, }, 14057 { 3029 /* vmvn */, ARM::VMVNv4i32, Convert__Reg1_2__NEONi32vmov1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32vmov }, }, 14058 { 3029 /* vmvn */, ARM::VMOVv4i32, Convert__Reg1_2__NEONi32vmovNeg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32vmovNeg }, }, 14059 { 3029 /* vmvn */, ARM::VMOVv8i8, Convert__Reg1_2__NEONi32invi8Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32invi8Replicate }, }, 14060 { 3029 /* vmvn */, ARM::VMVNv4i16, Convert__Reg1_2__NEONi32vmovi16Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32vmovi16Replicate }, }, 14061 { 3029 /* vmvn */, ARM::VMVNv2i32, Convert__Reg1_2__NEONi32vmov1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32vmov }, }, 14062 { 3029 /* vmvn */, ARM::VMOVv2i32, Convert__Reg1_2__NEONi32vmovNeg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32vmovNeg }, }, 14063 { 3029 /* vmvn */, ARM::VMOVv16i8, Convert__Reg1_2__NEONi64invi8Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_NEONi64invi8Replicate }, }, 14064 { 3029 /* vmvn */, ARM::VMVNv8i16, Convert__Reg1_2__NEONi64vmovi16Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_NEONi64vmovi16Replicate }, }, 14065 { 3029 /* vmvn */, ARM::VMVNv4i32, Convert__Reg1_2__NEONi64vmovi32Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_NEONi64vmovi32Replicate }, }, 14066 { 3029 /* vmvn */, ARM::VMOVv8i8, Convert__Reg1_2__NEONi64invi8Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_NEONi64invi8Replicate }, }, 14067 { 3029 /* vmvn */, ARM::VMVNv4i16, Convert__Reg1_2__NEONi64vmovi16Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_NEONi64vmovi16Replicate }, }, 14068 { 3029 /* vmvn */, ARM::VMVNv2i32, Convert__Reg1_2__NEONi64vmovi32Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_NEONi64vmovi32Replicate }, }, 14069 { 3029 /* vmvn */, ARM::VMVNq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, }, 14070 { 3029 /* vmvn */, ARM::VMVNd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, }, 14071 { 3029 /* vmvn */, ARM::VMVNq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, }, 14072 { 3029 /* vmvn */, ARM::VMVNd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, }, 14073 { 3029 /* vmvn */, ARM::VMVNq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR }, }, 14074 { 3029 /* vmvn */, ARM::VMVNd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR }, }, 14075 { 3029 /* vmvn */, ARM::VMVNq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, }, 14076 { 3029 /* vmvn */, ARM::VMVNd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, }, 14077 { 3029 /* vmvn */, ARM::MVE_VMVNimmi16, Convert__Reg1_2__NEONi16splat1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_NEONi16splat }, }, 14078 { 3029 /* vmvn */, ARM::MVE_VMVNimmi32, Convert__Reg1_2__NEONi32vmov1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_NEONi32vmov }, }, 14079 { 3034 /* vneg */, ARM::VNEGs16q, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 14080 { 3034 /* vneg */, ARM::VNEGs16d, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 14081 { 3034 /* vneg */, ARM::VNEGs32q, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 14082 { 3034 /* vneg */, ARM::VNEGs32d, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 14083 { 3034 /* vneg */, ARM::VNEGs8q, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, }, 14084 { 3034 /* vneg */, ARM::VNEGs8d, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 14085 { 3034 /* vneg */, ARM::VNEGf32q, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 14086 { 3034 /* vneg */, ARM::VNEGfd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 14087 { 3034 /* vneg */, ARM::VNEGS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 14088 { 3034 /* vneg */, ARM::VNEGD, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 14089 { 3034 /* vneg */, ARM::VNEGhq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 14090 { 3034 /* vneg */, ARM::VNEGhd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 14091 { 3034 /* vneg */, ARM::VNEGH, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 14092 { 3034 /* vneg */, ARM::MVE_VNEGs16, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, }, 14093 { 3034 /* vneg */, ARM::MVE_VNEGs32, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, }, 14094 { 3034 /* vneg */, ARM::MVE_VNEGs8, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR }, }, 14095 { 3034 /* vneg */, ARM::MVE_VNEGf32, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, }, 14096 { 3034 /* vneg */, ARM::MVE_VNEGf16, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, }, 14097 { 3039 /* vnmla */, ARM::VNMLAS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, }, 14098 { 3039 /* vnmla */, ARM::VNMLAD, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14099 { 3039 /* vnmla */, ARM::VNMLAH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, }, 14100 { 3045 /* vnmls */, ARM::VNMLSS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, }, 14101 { 3045 /* vnmls */, ARM::VNMLSD, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14102 { 3045 /* vnmls */, ARM::VNMLSH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, }, 14103 { 3051 /* vnmul */, ARM::VNMULS, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 14104 { 3051 /* vnmul */, ARM::VNMULD, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 14105 { 3051 /* vnmul */, ARM::VNMULH, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 14106 { 3051 /* vnmul */, ARM::VNMULS, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, }, 14107 { 3051 /* vnmul */, ARM::VNMULD, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14108 { 3051 /* vnmul */, ARM::VNMULH, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, }, 14109 { 3057 /* vorn */, ARM::VORNq, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14110 { 3057 /* vorn */, ARM::VORNd, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14111 { 3057 /* vorn */, ARM::MVE_VORRimmi16, Convert__Reg1_2__Tie0_3_3__NEONi16splatNot1_3__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_i16, MCK_MQPR, MCK_NEONi16splatNot }, }, 14112 { 3057 /* vorn */, ARM::MVE_VORRimmi32, Convert__Reg1_2__Tie0_3_3__NEONi32splatNot1_3__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_NEONi32splatNot }, }, 14113 { 3057 /* vorn */, ARM::MVE_VORN, Convert__Reg1_1__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14114 { 3057 /* vorn */, ARM::MVE_VORN, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14115 { 3057 /* vorn */, ARM::MVE_VORN, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14116 { 3057 /* vorn */, ARM::MVE_VORN, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14117 { 3057 /* vorn */, ARM::MVE_VORN, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14118 { 3057 /* vorn */, ARM::MVE_VORN, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14119 { 3057 /* vorn */, ARM::MVE_VORN, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14120 { 3057 /* vorn */, ARM::MVE_VORN, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14121 { 3057 /* vorn */, ARM::MVE_VORN, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14122 { 3057 /* vorn */, ARM::MVE_VORN, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14123 { 3057 /* vorn */, ARM::MVE_VORN, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14124 { 3057 /* vorn */, ARM::MVE_VORN, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14125 { 3062 /* vorr */, ARM::VORRq, Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR }, }, 14126 { 3062 /* vorr */, ARM::VORRd, Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR }, }, 14127 { 3062 /* vorr */, ARM::VORRiv8i16, Convert__Reg1_2__NEONi16splat1_3__Tie0_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_NEONi16splat }, }, 14128 { 3062 /* vorr */, ARM::VORRiv4i16, Convert__Reg1_2__NEONi16splat1_3__Tie0_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_NEONi16splat }, }, 14129 { 3062 /* vorr */, ARM::VORRiv4i32, Convert__Reg1_2__NEONi32splat1_3__Tie0_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32splat }, }, 14130 { 3062 /* vorr */, ARM::VORRiv2i32, Convert__Reg1_2__NEONi32splat1_3__Tie0_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32splat }, }, 14131 { 3062 /* vorr */, ARM::VORRq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, }, 14132 { 3062 /* vorr */, ARM::VORRd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, }, 14133 { 3062 /* vorr */, ARM::VORRq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, }, 14134 { 3062 /* vorr */, ARM::VORRd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, }, 14135 { 3062 /* vorr */, ARM::VORRq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR }, }, 14136 { 3062 /* vorr */, ARM::VORRd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR }, }, 14137 { 3062 /* vorr */, ARM::VORRq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, }, 14138 { 3062 /* vorr */, ARM::VORRd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, }, 14139 { 3062 /* vorr */, ARM::VORRq, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14140 { 3062 /* vorr */, ARM::VORRd, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14141 { 3062 /* vorr */, ARM::MVE_VORRimmi16, Convert__Reg1_2__Tie0_1_1__NEONi16splat1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i16, MCK_MQPR, MCK_NEONi16splat }, }, 14142 { 3062 /* vorr */, ARM::MVE_VORRimmi32, Convert__Reg1_2__Tie0_1_1__NEONi32splat1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_NEONi32splat }, }, 14143 { 3062 /* vorr */, ARM::MVE_VORR, Convert__Reg1_1__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14144 { 3062 /* vorr */, ARM::VORRq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14145 { 3062 /* vorr */, ARM::VORRd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14146 { 3062 /* vorr */, ARM::VORRq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14147 { 3062 /* vorr */, ARM::VORRd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14148 { 3062 /* vorr */, ARM::VORRq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14149 { 3062 /* vorr */, ARM::VORRd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14150 { 3062 /* vorr */, ARM::VORRq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14151 { 3062 /* vorr */, ARM::VORRd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14152 { 3062 /* vorr */, ARM::MVE_VORR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14153 { 3062 /* vorr */, ARM::MVE_VORR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14154 { 3062 /* vorr */, ARM::MVE_VORR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14155 { 3062 /* vorr */, ARM::MVE_VORR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14156 { 3062 /* vorr */, ARM::MVE_VORR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14157 { 3062 /* vorr */, ARM::MVE_VORR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14158 { 3062 /* vorr */, ARM::MVE_VORR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14159 { 3062 /* vorr */, ARM::MVE_VORR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14160 { 3062 /* vorr */, ARM::MVE_VORR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14161 { 3062 /* vorr */, ARM::MVE_VORR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14162 { 3062 /* vorr */, ARM::MVE_VORR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14163 { 3067 /* vpadal */, ARM::VPADALsv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 14164 { 3067 /* vpadal */, ARM::VPADALsv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 14165 { 3067 /* vpadal */, ARM::VPADALsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 14166 { 3067 /* vpadal */, ARM::VPADALsv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 14167 { 3067 /* vpadal */, ARM::VPADALsv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, }, 14168 { 3067 /* vpadal */, ARM::VPADALsv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 14169 { 3067 /* vpadal */, ARM::VPADALuv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, }, 14170 { 3067 /* vpadal */, ARM::VPADALuv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, }, 14171 { 3067 /* vpadal */, ARM::VPADALuv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, }, 14172 { 3067 /* vpadal */, ARM::VPADALuv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, }, 14173 { 3067 /* vpadal */, ARM::VPADALuv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, }, 14174 { 3067 /* vpadal */, ARM::VPADALuv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, }, 14175 { 3074 /* vpadd */, ARM::VPADDf, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 14176 { 3074 /* vpadd */, ARM::VPADDi16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR }, }, 14177 { 3074 /* vpadd */, ARM::VPADDi32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR }, }, 14178 { 3074 /* vpadd */, ARM::VPADDi8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR }, }, 14179 { 3074 /* vpadd */, ARM::VPADDh, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 14180 { 3074 /* vpadd */, ARM::VPADDf, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14181 { 3074 /* vpadd */, ARM::VPADDi16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14182 { 3074 /* vpadd */, ARM::VPADDi32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14183 { 3074 /* vpadd */, ARM::VPADDi8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14184 { 3074 /* vpadd */, ARM::VPADDh, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14185 { 3080 /* vpaddl */, ARM::VPADDLsv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 14186 { 3080 /* vpaddl */, ARM::VPADDLsv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 14187 { 3080 /* vpaddl */, ARM::VPADDLsv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 14188 { 3080 /* vpaddl */, ARM::VPADDLsv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 14189 { 3080 /* vpaddl */, ARM::VPADDLsv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, }, 14190 { 3080 /* vpaddl */, ARM::VPADDLsv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 14191 { 3080 /* vpaddl */, ARM::VPADDLuv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, }, 14192 { 3080 /* vpaddl */, ARM::VPADDLuv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, }, 14193 { 3080 /* vpaddl */, ARM::VPADDLuv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, }, 14194 { 3080 /* vpaddl */, ARM::VPADDLuv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, }, 14195 { 3080 /* vpaddl */, ARM::VPADDLuv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, }, 14196 { 3080 /* vpaddl */, ARM::VPADDLuv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, }, 14197 { 3087 /* vpmax */, ARM::VPMAXs16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 14198 { 3087 /* vpmax */, ARM::VPMAXs32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 14199 { 3087 /* vpmax */, ARM::VPMAXs8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 14200 { 3087 /* vpmax */, ARM::VPMAXu16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, }, 14201 { 3087 /* vpmax */, ARM::VPMAXu32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, }, 14202 { 3087 /* vpmax */, ARM::VPMAXu8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, }, 14203 { 3087 /* vpmax */, ARM::VPMAXf, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 14204 { 3087 /* vpmax */, ARM::VPMAXh, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 14205 { 3087 /* vpmax */, ARM::VPMAXs16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14206 { 3087 /* vpmax */, ARM::VPMAXs32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14207 { 3087 /* vpmax */, ARM::VPMAXs8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14208 { 3087 /* vpmax */, ARM::VPMAXu16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14209 { 3087 /* vpmax */, ARM::VPMAXu32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14210 { 3087 /* vpmax */, ARM::VPMAXu8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14211 { 3087 /* vpmax */, ARM::VPMAXf, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14212 { 3087 /* vpmax */, ARM::VPMAXh, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14213 { 3093 /* vpmin */, ARM::VPMINs16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 14214 { 3093 /* vpmin */, ARM::VPMINs32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 14215 { 3093 /* vpmin */, ARM::VPMINs8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 14216 { 3093 /* vpmin */, ARM::VPMINu16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, }, 14217 { 3093 /* vpmin */, ARM::VPMINu32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, }, 14218 { 3093 /* vpmin */, ARM::VPMINu8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, }, 14219 { 3093 /* vpmin */, ARM::VPMINf, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 14220 { 3093 /* vpmin */, ARM::VPMINh, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 14221 { 3093 /* vpmin */, ARM::VPMINs16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14222 { 3093 /* vpmin */, ARM::VPMINs32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14223 { 3093 /* vpmin */, ARM::VPMINs8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14224 { 3093 /* vpmin */, ARM::VPMINu16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14225 { 3093 /* vpmin */, ARM::VPMINu32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14226 { 3093 /* vpmin */, ARM::VPMINu8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14227 { 3093 /* vpmin */, ARM::VPMINf, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14228 { 3093 /* vpmin */, ARM::VPMINh, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14229 { 3099 /* vpnot */, ARM::MVE_VPNOT, Convert__imm_95_0__imm_95_0__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN }, }, 14230 { 3105 /* vpop */, ARM::VLDMDIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_1, AMFBS_HasFPRegs, { MCK_CondCode, MCK_DPRRegList }, }, 14231 { 3105 /* vpop */, ARM::VLDMSIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_1, AMFBS_HasFPRegs, { MCK_CondCode, MCK_SPRRegList }, }, 14232 { 3105 /* vpop */, ARM::VLDMDIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_16, MCK_DPRRegList }, }, 14233 { 3105 /* vpop */, ARM::VLDMSIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_16, MCK_SPRRegList }, }, 14234 { 3105 /* vpop */, ARM::VLDMDIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_32, MCK_DPRRegList }, }, 14235 { 3105 /* vpop */, ARM::VLDMSIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_32, MCK_SPRRegList }, }, 14236 { 3105 /* vpop */, ARM::VLDMDIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_64, MCK_DPRRegList }, }, 14237 { 3105 /* vpop */, ARM::VLDMSIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_64, MCK_SPRRegList }, }, 14238 { 3105 /* vpop */, ARM::VLDMDIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_8, MCK_DPRRegList }, }, 14239 { 3105 /* vpop */, ARM::VLDMSIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_8, MCK_SPRRegList }, }, 14240 { 3110 /* vpsel */, ARM::MVE_VPSEL, Convert__Reg1_1__Reg1_2__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14241 { 3110 /* vpsel */, ARM::MVE_VPSEL, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14242 { 3110 /* vpsel */, ARM::MVE_VPSEL, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14243 { 3110 /* vpsel */, ARM::MVE_VPSEL, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14244 { 3110 /* vpsel */, ARM::MVE_VPSEL, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14245 { 3110 /* vpsel */, ARM::MVE_VPSEL, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14246 { 3110 /* vpsel */, ARM::MVE_VPSEL, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14247 { 3110 /* vpsel */, ARM::MVE_VPSEL, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14248 { 3110 /* vpsel */, ARM::MVE_VPSEL, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14249 { 3110 /* vpsel */, ARM::MVE_VPSEL, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14250 { 3110 /* vpsel */, ARM::MVE_VPSEL, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14251 { 3110 /* vpsel */, ARM::MVE_VPSEL, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14252 { 3116 /* vpst */, ARM::MVE_VPST, Convert__ITMask1_0, AMFBS_HasMVEInt, { MCK_ITMask }, }, 14253 { 3121 /* vpt */, ARM::MVE_VPTv8s16, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_s16, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_MQPR }, }, 14254 { 3121 /* vpt */, ARM::MVE_VPTv8s16r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_s16, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_GPRwithZR }, }, 14255 { 3121 /* vpt */, ARM::MVE_VPTv4s32, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_s32, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_MQPR }, }, 14256 { 3121 /* vpt */, ARM::MVE_VPTv4s32r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_s32, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_GPRwithZR }, }, 14257 { 3121 /* vpt */, ARM::MVE_VPTv16s8, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_s8, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_MQPR }, }, 14258 { 3121 /* vpt */, ARM::MVE_VPTv16s8r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_s8, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_GPRwithZR }, }, 14259 { 3121 /* vpt */, ARM::MVE_VPTv8u16, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_u16, MCK_CondCodeRestrictedU, MCK_MQPR, MCK_MQPR }, }, 14260 { 3121 /* vpt */, ARM::MVE_VPTv8u16r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_u16, MCK_CondCodeRestrictedU, MCK_MQPR, MCK_GPRwithZR }, }, 14261 { 3121 /* vpt */, ARM::MVE_VPTv4u32, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_u32, MCK_CondCodeRestrictedU, MCK_MQPR, MCK_MQPR }, }, 14262 { 3121 /* vpt */, ARM::MVE_VPTv4u32r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_u32, MCK_CondCodeRestrictedU, MCK_MQPR, MCK_GPRwithZR }, }, 14263 { 3121 /* vpt */, ARM::MVE_VPTv16u8, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_u8, MCK_CondCodeRestrictedU, MCK_MQPR, MCK_MQPR }, }, 14264 { 3121 /* vpt */, ARM::MVE_VPTv16u8r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_u8, MCK_CondCodeRestrictedU, MCK_MQPR, MCK_GPRwithZR }, }, 14265 { 3121 /* vpt */, ARM::MVE_VPTv4f32, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedFP1_2, AMFBS_HasMVEFloat, { MCK_ITMask, MCK__DOT_f32, MCK_CondCodeRestrictedFP, MCK_MQPR, MCK_MQPR }, }, 14266 { 3121 /* vpt */, ARM::MVE_VPTv4f32r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedFP1_2, AMFBS_HasMVEFloat, { MCK_ITMask, MCK__DOT_f32, MCK_CondCodeRestrictedFP, MCK_MQPR, MCK_GPRwithZR }, }, 14267 { 3121 /* vpt */, ARM::MVE_VPTv8i16, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_i16, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_MQPR }, }, 14268 { 3121 /* vpt */, ARM::MVE_VPTv8i16r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_i16, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_GPRwithZR }, }, 14269 { 3121 /* vpt */, ARM::MVE_VPTv4i32, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_i32, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_MQPR }, }, 14270 { 3121 /* vpt */, ARM::MVE_VPTv4i32r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_i32, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_GPRwithZR }, }, 14271 { 3121 /* vpt */, ARM::MVE_VPTv16i8, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_i8, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_MQPR }, }, 14272 { 3121 /* vpt */, ARM::MVE_VPTv16i8r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_i8, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_GPRwithZR }, }, 14273 { 3121 /* vpt */, ARM::MVE_VPTv8f16, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedFP1_2, AMFBS_HasMVEFloat, { MCK_ITMask, MCK__DOT_f16, MCK_CondCodeRestrictedFP, MCK_MQPR, MCK_MQPR }, }, 14274 { 3121 /* vpt */, ARM::MVE_VPTv8f16r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedFP1_2, AMFBS_HasMVEFloat, { MCK_ITMask, MCK__DOT_f16, MCK_CondCodeRestrictedFP, MCK_MQPR, MCK_GPRwithZR }, }, 14275 { 3125 /* vpush */, ARM::VSTMDDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_1, AMFBS_HasFPRegs, { MCK_CondCode, MCK_DPRRegList }, }, 14276 { 3125 /* vpush */, ARM::VSTMSDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_1, AMFBS_HasFPRegs, { MCK_CondCode, MCK_SPRRegList }, }, 14277 { 3125 /* vpush */, ARM::VSTMDDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_16, MCK_DPRRegList }, }, 14278 { 3125 /* vpush */, ARM::VSTMSDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_16, MCK_SPRRegList }, }, 14279 { 3125 /* vpush */, ARM::VSTMDDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_32, MCK_DPRRegList }, }, 14280 { 3125 /* vpush */, ARM::VSTMSDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_32, MCK_SPRRegList }, }, 14281 { 3125 /* vpush */, ARM::VSTMDDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_64, MCK_DPRRegList }, }, 14282 { 3125 /* vpush */, ARM::VSTMSDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_64, MCK_SPRRegList }, }, 14283 { 3125 /* vpush */, ARM::VSTMDDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_8, MCK_DPRRegList }, }, 14284 { 3125 /* vpush */, ARM::VSTMSDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_8, MCK_SPRRegList }, }, 14285 { 3131 /* vqabs */, ARM::VQABSv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 14286 { 3131 /* vqabs */, ARM::VQABSv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 14287 { 3131 /* vqabs */, ARM::VQABSv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 14288 { 3131 /* vqabs */, ARM::VQABSv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 14289 { 3131 /* vqabs */, ARM::VQABSv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, }, 14290 { 3131 /* vqabs */, ARM::VQABSv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 14291 { 3131 /* vqabs */, ARM::MVE_VQABSs16, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, }, 14292 { 3131 /* vqabs */, ARM::MVE_VQABSs32, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, }, 14293 { 3131 /* vqabs */, ARM::MVE_VQABSs8, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR }, }, 14294 { 3137 /* vqadd */, ARM::VQADDsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 14295 { 3137 /* vqadd */, ARM::VQADDsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 14296 { 3137 /* vqadd */, ARM::VQADDsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 14297 { 3137 /* vqadd */, ARM::VQADDsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 14298 { 3137 /* vqadd */, ARM::VQADDsv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR }, }, 14299 { 3137 /* vqadd */, ARM::VQADDsv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR }, }, 14300 { 3137 /* vqadd */, ARM::VQADDsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, }, 14301 { 3137 /* vqadd */, ARM::VQADDsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 14302 { 3137 /* vqadd */, ARM::VQADDuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, }, 14303 { 3137 /* vqadd */, ARM::VQADDuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, }, 14304 { 3137 /* vqadd */, ARM::VQADDuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, }, 14305 { 3137 /* vqadd */, ARM::VQADDuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, }, 14306 { 3137 /* vqadd */, ARM::VQADDuv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR }, }, 14307 { 3137 /* vqadd */, ARM::VQADDuv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR }, }, 14308 { 3137 /* vqadd */, ARM::VQADDuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, }, 14309 { 3137 /* vqadd */, ARM::VQADDuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, }, 14310 { 3137 /* vqadd */, ARM::VQADDsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14311 { 3137 /* vqadd */, ARM::VQADDsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14312 { 3137 /* vqadd */, ARM::VQADDsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14313 { 3137 /* vqadd */, ARM::VQADDsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14314 { 3137 /* vqadd */, ARM::VQADDsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14315 { 3137 /* vqadd */, ARM::VQADDsv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14316 { 3137 /* vqadd */, ARM::VQADDsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14317 { 3137 /* vqadd */, ARM::VQADDsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14318 { 3137 /* vqadd */, ARM::VQADDuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14319 { 3137 /* vqadd */, ARM::VQADDuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14320 { 3137 /* vqadd */, ARM::VQADDuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14321 { 3137 /* vqadd */, ARM::VQADDuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14322 { 3137 /* vqadd */, ARM::VQADDuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14323 { 3137 /* vqadd */, ARM::VQADDuv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14324 { 3137 /* vqadd */, ARM::VQADDuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14325 { 3137 /* vqadd */, ARM::VQADDuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14326 { 3137 /* vqadd */, ARM::MVE_VQADDs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14327 { 3137 /* vqadd */, ARM::MVE_VQADD_qr_s16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 14328 { 3137 /* vqadd */, ARM::MVE_VQADDs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14329 { 3137 /* vqadd */, ARM::MVE_VQADD_qr_s32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 14330 { 3137 /* vqadd */, ARM::MVE_VQADDs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14331 { 3137 /* vqadd */, ARM::MVE_VQADD_qr_s8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 14332 { 3137 /* vqadd */, ARM::MVE_VQADDu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14333 { 3137 /* vqadd */, ARM::MVE_VQADD_qr_u16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 14334 { 3137 /* vqadd */, ARM::MVE_VQADDu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14335 { 3137 /* vqadd */, ARM::MVE_VQADD_qr_u32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 14336 { 3137 /* vqadd */, ARM::MVE_VQADDu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14337 { 3137 /* vqadd */, ARM::MVE_VQADD_qr_u8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 14338 { 3143 /* vqdmladh */, ARM::MVE_VQDMLADHs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14339 { 3143 /* vqdmladh */, ARM::MVE_VQDMLADHs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14340 { 3143 /* vqdmladh */, ARM::MVE_VQDMLADHs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14341 { 3152 /* vqdmladhx */, ARM::MVE_VQDMLADHXs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14342 { 3152 /* vqdmladhx */, ARM::MVE_VQDMLADHXs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14343 { 3152 /* vqdmladhx */, ARM::MVE_VQDMLADHXs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14344 { 3162 /* vqdmlah */, ARM::MVE_VQDMLAH_qrs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 14345 { 3162 /* vqdmlah */, ARM::MVE_VQDMLAH_qrs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 14346 { 3162 /* vqdmlah */, ARM::MVE_VQDMLAH_qrs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 14347 { 3170 /* vqdmlal */, ARM::VQDMLALv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, }, 14348 { 3170 /* vqdmlal */, ARM::VQDMLALv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, }, 14349 { 3170 /* vqdmlal */, ARM::VQDMLALslv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 14350 { 3170 /* vqdmlal */, ARM::VQDMLALslv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 14351 { 3178 /* vqdmlash */, ARM::MVE_VQDMLASH_qrs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 14352 { 3178 /* vqdmlash */, ARM::MVE_VQDMLASH_qrs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 14353 { 3178 /* vqdmlash */, ARM::MVE_VQDMLASH_qrs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 14354 { 3187 /* vqdmlsdh */, ARM::MVE_VQDMLSDHs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14355 { 3187 /* vqdmlsdh */, ARM::MVE_VQDMLSDHs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14356 { 3187 /* vqdmlsdh */, ARM::MVE_VQDMLSDHs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14357 { 3196 /* vqdmlsdhx */, ARM::MVE_VQDMLSDHXs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14358 { 3196 /* vqdmlsdhx */, ARM::MVE_VQDMLSDHXs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14359 { 3196 /* vqdmlsdhx */, ARM::MVE_VQDMLSDHXs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14360 { 3206 /* vqdmlsl */, ARM::VQDMLSLv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, }, 14361 { 3206 /* vqdmlsl */, ARM::VQDMLSLv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, }, 14362 { 3206 /* vqdmlsl */, ARM::VQDMLSLslv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 14363 { 3206 /* vqdmlsl */, ARM::VQDMLSLslv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 14364 { 3214 /* vqdmulh */, ARM::VQDMULHv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 14365 { 3214 /* vqdmulh */, ARM::VQDMULHv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 14366 { 3214 /* vqdmulh */, ARM::VQDMULHv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 14367 { 3214 /* vqdmulh */, ARM::VQDMULHv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 14368 { 3214 /* vqdmulh */, ARM::VQDMULHv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14369 { 3214 /* vqdmulh */, ARM::VQDMULHv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14370 { 3214 /* vqdmulh */, ARM::VQDMULHv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14371 { 3214 /* vqdmulh */, ARM::VQDMULHv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14372 { 3214 /* vqdmulh */, ARM::MVE_VQDMULHi16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14373 { 3214 /* vqdmulh */, ARM::MVE_VQDMULH_qr_s16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 14374 { 3214 /* vqdmulh */, ARM::MVE_VQDMULHi32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14375 { 3214 /* vqdmulh */, ARM::MVE_VQDMULH_qr_s32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 14376 { 3214 /* vqdmulh */, ARM::MVE_VQDMULHi8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14377 { 3214 /* vqdmulh */, ARM::MVE_VQDMULH_qr_s8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 14378 { 3214 /* vqdmulh */, ARM::VQDMULHslv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 14379 { 3214 /* vqdmulh */, ARM::VQDMULHslv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 14380 { 3214 /* vqdmulh */, ARM::VQDMULHslv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 14381 { 3214 /* vqdmulh */, ARM::VQDMULHslv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 14382 { 3222 /* vqdmull */, ARM::VQDMULLv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, }, 14383 { 3222 /* vqdmull */, ARM::VQDMULLv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, }, 14384 { 3222 /* vqdmull */, ARM::VQDMULLslv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 14385 { 3222 /* vqdmull */, ARM::VQDMULLslv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 14386 { 3230 /* vqdmullb */, ARM::MVE_VQDMULLs16bh, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14387 { 3230 /* vqdmullb */, ARM::MVE_VQDMULL_qr_s16bh, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 14388 { 3230 /* vqdmullb */, ARM::MVE_VQDMULLs32bh, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14389 { 3230 /* vqdmullb */, ARM::MVE_VQDMULL_qr_s32bh, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 14390 { 3239 /* vqdmullt */, ARM::MVE_VQDMULLs16th, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14391 { 3239 /* vqdmullt */, ARM::MVE_VQDMULL_qr_s16th, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 14392 { 3239 /* vqdmullt */, ARM::MVE_VQDMULLs32th, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14393 { 3239 /* vqdmullt */, ARM::MVE_VQDMULL_qr_s32th, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 14394 { 3248 /* vqmovn */, ARM::VQMOVNsv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_QPR }, }, 14395 { 3248 /* vqmovn */, ARM::VQMOVNsv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_QPR }, }, 14396 { 3248 /* vqmovn */, ARM::VQMOVNsv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_QPR }, }, 14397 { 3248 /* vqmovn */, ARM::VQMOVNuv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_QPR }, }, 14398 { 3248 /* vqmovn */, ARM::VQMOVNuv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_QPR }, }, 14399 { 3248 /* vqmovn */, ARM::VQMOVNuv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_QPR }, }, 14400 { 3255 /* vqmovnb */, ARM::MVE_VQMOVNs16bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, }, 14401 { 3255 /* vqmovnb */, ARM::MVE_VQMOVNs32bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, }, 14402 { 3255 /* vqmovnb */, ARM::MVE_VQMOVNu16bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MQPR }, }, 14403 { 3255 /* vqmovnb */, ARM::MVE_VQMOVNu32bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MQPR }, }, 14404 { 3263 /* vqmovnt */, ARM::MVE_VQMOVNs16th, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, }, 14405 { 3263 /* vqmovnt */, ARM::MVE_VQMOVNs32th, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, }, 14406 { 3263 /* vqmovnt */, ARM::MVE_VQMOVNu16th, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MQPR }, }, 14407 { 3263 /* vqmovnt */, ARM::MVE_VQMOVNu32th, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MQPR }, }, 14408 { 3271 /* vqmovun */, ARM::VQMOVNsuv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_QPR }, }, 14409 { 3271 /* vqmovun */, ARM::VQMOVNsuv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_QPR }, }, 14410 { 3271 /* vqmovun */, ARM::VQMOVNsuv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_QPR }, }, 14411 { 3279 /* vqmovunb */, ARM::MVE_VQMOVUNs16bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, }, 14412 { 3279 /* vqmovunb */, ARM::MVE_VQMOVUNs32bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, }, 14413 { 3288 /* vqmovunt */, ARM::MVE_VQMOVUNs16th, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, }, 14414 { 3288 /* vqmovunt */, ARM::MVE_VQMOVUNs32th, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, }, 14415 { 3297 /* vqneg */, ARM::VQNEGv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 14416 { 3297 /* vqneg */, ARM::VQNEGv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 14417 { 3297 /* vqneg */, ARM::VQNEGv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 14418 { 3297 /* vqneg */, ARM::VQNEGv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 14419 { 3297 /* vqneg */, ARM::VQNEGv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, }, 14420 { 3297 /* vqneg */, ARM::VQNEGv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 14421 { 3297 /* vqneg */, ARM::MVE_VQNEGs16, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, }, 14422 { 3297 /* vqneg */, ARM::MVE_VQNEGs32, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, }, 14423 { 3297 /* vqneg */, ARM::MVE_VQNEGs8, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR }, }, 14424 { 3303 /* vqrdmladh */, ARM::MVE_VQRDMLADHs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14425 { 3303 /* vqrdmladh */, ARM::MVE_VQRDMLADHs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14426 { 3303 /* vqrdmladh */, ARM::MVE_VQRDMLADHs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14427 { 3313 /* vqrdmladhx */, ARM::MVE_VQRDMLADHXs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14428 { 3313 /* vqrdmladhx */, ARM::MVE_VQRDMLADHXs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14429 { 3313 /* vqrdmladhx */, ARM::MVE_VQRDMLADHXs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14430 { 3324 /* vqrdmlah */, ARM::VQRDMLAHv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14431 { 3324 /* vqrdmlah */, ARM::VQRDMLAHv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14432 { 3324 /* vqrdmlah */, ARM::VQRDMLAHv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14433 { 3324 /* vqrdmlah */, ARM::VQRDMLAHv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14434 { 3324 /* vqrdmlah */, ARM::MVE_VQRDMLAH_qrs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 14435 { 3324 /* vqrdmlah */, ARM::MVE_VQRDMLAH_qrs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 14436 { 3324 /* vqrdmlah */, ARM::MVE_VQRDMLAH_qrs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 14437 { 3324 /* vqrdmlah */, ARM::VQRDMLAHslv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 14438 { 3324 /* vqrdmlah */, ARM::VQRDMLAHslv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 14439 { 3324 /* vqrdmlah */, ARM::VQRDMLAHslv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 14440 { 3324 /* vqrdmlah */, ARM::VQRDMLAHslv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 14441 { 3333 /* vqrdmlash */, ARM::MVE_VQRDMLASH_qrs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 14442 { 3333 /* vqrdmlash */, ARM::MVE_VQRDMLASH_qrs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 14443 { 3333 /* vqrdmlash */, ARM::MVE_VQRDMLASH_qrs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 14444 { 3343 /* vqrdmlsdh */, ARM::MVE_VQRDMLSDHs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14445 { 3343 /* vqrdmlsdh */, ARM::MVE_VQRDMLSDHs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14446 { 3343 /* vqrdmlsdh */, ARM::MVE_VQRDMLSDHs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14447 { 3353 /* vqrdmlsdhx */, ARM::MVE_VQRDMLSDHXs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14448 { 3353 /* vqrdmlsdhx */, ARM::MVE_VQRDMLSDHXs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14449 { 3353 /* vqrdmlsdhx */, ARM::MVE_VQRDMLSDHXs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14450 { 3364 /* vqrdmlsh */, ARM::VQRDMLSHv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14451 { 3364 /* vqrdmlsh */, ARM::VQRDMLSHv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14452 { 3364 /* vqrdmlsh */, ARM::VQRDMLSHv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14453 { 3364 /* vqrdmlsh */, ARM::VQRDMLSHv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14454 { 3364 /* vqrdmlsh */, ARM::VQRDMLSHslv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 14455 { 3364 /* vqrdmlsh */, ARM::VQRDMLSHslv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 14456 { 3364 /* vqrdmlsh */, ARM::VQRDMLSHslv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 14457 { 3364 /* vqrdmlsh */, ARM::VQRDMLSHslv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 14458 { 3373 /* vqrdmulh */, ARM::VQRDMULHv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 14459 { 3373 /* vqrdmulh */, ARM::VQRDMULHv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 14460 { 3373 /* vqrdmulh */, ARM::VQRDMULHv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 14461 { 3373 /* vqrdmulh */, ARM::VQRDMULHv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 14462 { 3373 /* vqrdmulh */, ARM::VQRDMULHv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14463 { 3373 /* vqrdmulh */, ARM::VQRDMULHv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14464 { 3373 /* vqrdmulh */, ARM::VQRDMULHv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14465 { 3373 /* vqrdmulh */, ARM::VQRDMULHv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14466 { 3373 /* vqrdmulh */, ARM::MVE_VQRDMULHi16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14467 { 3373 /* vqrdmulh */, ARM::MVE_VQRDMULH_qr_s16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 14468 { 3373 /* vqrdmulh */, ARM::MVE_VQRDMULHi32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14469 { 3373 /* vqrdmulh */, ARM::MVE_VQRDMULH_qr_s32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 14470 { 3373 /* vqrdmulh */, ARM::MVE_VQRDMULHi8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14471 { 3373 /* vqrdmulh */, ARM::MVE_VQRDMULH_qr_s8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 14472 { 3373 /* vqrdmulh */, ARM::VQRDMULHslv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 14473 { 3373 /* vqrdmulh */, ARM::VQRDMULHslv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 14474 { 3373 /* vqrdmulh */, ARM::VQRDMULHslv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 14475 { 3373 /* vqrdmulh */, ARM::VQRDMULHslv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 14476 { 3382 /* vqrshl */, ARM::VQRSHLsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 14477 { 3382 /* vqrshl */, ARM::VQRSHLsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 14478 { 3382 /* vqrshl */, ARM::VQRSHLsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 14479 { 3382 /* vqrshl */, ARM::VQRSHLsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 14480 { 3382 /* vqrshl */, ARM::VQRSHLsv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR }, }, 14481 { 3382 /* vqrshl */, ARM::VQRSHLsv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR }, }, 14482 { 3382 /* vqrshl */, ARM::VQRSHLsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, }, 14483 { 3382 /* vqrshl */, ARM::VQRSHLsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 14484 { 3382 /* vqrshl */, ARM::VQRSHLuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, }, 14485 { 3382 /* vqrshl */, ARM::VQRSHLuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, }, 14486 { 3382 /* vqrshl */, ARM::VQRSHLuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, }, 14487 { 3382 /* vqrshl */, ARM::VQRSHLuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, }, 14488 { 3382 /* vqrshl */, ARM::VQRSHLuv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR }, }, 14489 { 3382 /* vqrshl */, ARM::VQRSHLuv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR }, }, 14490 { 3382 /* vqrshl */, ARM::VQRSHLuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, }, 14491 { 3382 /* vqrshl */, ARM::VQRSHLuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, }, 14492 { 3382 /* vqrshl */, ARM::MVE_VQRSHL_qrs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_rGPR }, }, 14493 { 3382 /* vqrshl */, ARM::MVE_VQRSHL_qrs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_rGPR }, }, 14494 { 3382 /* vqrshl */, ARM::MVE_VQRSHL_qrs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_rGPR }, }, 14495 { 3382 /* vqrshl */, ARM::MVE_VQRSHL_qru16, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_rGPR }, }, 14496 { 3382 /* vqrshl */, ARM::MVE_VQRSHL_qru32, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_rGPR }, }, 14497 { 3382 /* vqrshl */, ARM::MVE_VQRSHL_qru8, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_MQPR, MCK_rGPR }, }, 14498 { 3382 /* vqrshl */, ARM::VQRSHLsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14499 { 3382 /* vqrshl */, ARM::VQRSHLsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14500 { 3382 /* vqrshl */, ARM::VQRSHLsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14501 { 3382 /* vqrshl */, ARM::VQRSHLsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14502 { 3382 /* vqrshl */, ARM::VQRSHLsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14503 { 3382 /* vqrshl */, ARM::VQRSHLsv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14504 { 3382 /* vqrshl */, ARM::VQRSHLsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14505 { 3382 /* vqrshl */, ARM::VQRSHLsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14506 { 3382 /* vqrshl */, ARM::VQRSHLuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14507 { 3382 /* vqrshl */, ARM::VQRSHLuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14508 { 3382 /* vqrshl */, ARM::VQRSHLuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14509 { 3382 /* vqrshl */, ARM::VQRSHLuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14510 { 3382 /* vqrshl */, ARM::VQRSHLuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14511 { 3382 /* vqrshl */, ARM::VQRSHLuv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14512 { 3382 /* vqrshl */, ARM::VQRSHLuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14513 { 3382 /* vqrshl */, ARM::VQRSHLuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14514 { 3382 /* vqrshl */, ARM::MVE_VQRSHL_by_vecs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14515 { 3382 /* vqrshl */, ARM::MVE_VQRSHL_by_vecs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14516 { 3382 /* vqrshl */, ARM::MVE_VQRSHL_by_vecs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14517 { 3382 /* vqrshl */, ARM::MVE_VQRSHL_by_vecu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14518 { 3382 /* vqrshl */, ARM::MVE_VQRSHL_by_vecu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14519 { 3382 /* vqrshl */, ARM::MVE_VQRSHL_by_vecu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14520 { 3389 /* vqrshrn */, ARM::VQRSHRNsv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_QPR, MCK_ShrImm8 }, }, 14521 { 3389 /* vqrshrn */, ARM::VQRSHRNsv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_QPR, MCK_ShrImm16 }, }, 14522 { 3389 /* vqrshrn */, ARM::VQRSHRNsv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_QPR, MCK_ShrImm32 }, }, 14523 { 3389 /* vqrshrn */, ARM::VQRSHRNuv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_QPR, MCK_ShrImm8 }, }, 14524 { 3389 /* vqrshrn */, ARM::VQRSHRNuv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_QPR, MCK_ShrImm16 }, }, 14525 { 3389 /* vqrshrn */, ARM::VQRSHRNuv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_QPR, MCK_ShrImm32 }, }, 14526 { 3397 /* vqrshrnb */, ARM::MVE_VQRSHRNbhs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, }, 14527 { 3397 /* vqrshrnb */, ARM::MVE_VQRSHRNbhs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, }, 14528 { 3397 /* vqrshrnb */, ARM::MVE_VQRSHRNbhu16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, }, 14529 { 3397 /* vqrshrnb */, ARM::MVE_VQRSHRNbhu32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, }, 14530 { 3406 /* vqrshrnt */, ARM::MVE_VQRSHRNths16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, }, 14531 { 3406 /* vqrshrnt */, ARM::MVE_VQRSHRNths32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, }, 14532 { 3406 /* vqrshrnt */, ARM::MVE_VQRSHRNthu16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, }, 14533 { 3406 /* vqrshrnt */, ARM::MVE_VQRSHRNthu32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, }, 14534 { 3415 /* vqrshrun */, ARM::VQRSHRUNv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_QPR, MCK_ShrImm8 }, }, 14535 { 3415 /* vqrshrun */, ARM::VQRSHRUNv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_QPR, MCK_ShrImm16 }, }, 14536 { 3415 /* vqrshrun */, ARM::VQRSHRUNv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_QPR, MCK_ShrImm32 }, }, 14537 { 3424 /* vqrshrunb */, ARM::MVE_VQRSHRUNs16bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, }, 14538 { 3424 /* vqrshrunb */, ARM::MVE_VQRSHRUNs32bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, }, 14539 { 3434 /* vqrshrunt */, ARM::MVE_VQRSHRUNs16th, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, }, 14540 { 3434 /* vqrshrunt */, ARM::MVE_VQRSHRUNs32th, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, }, 14541 { 3444 /* vqshl */, ARM::VQSHLsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 14542 { 3444 /* vqshl */, ARM::VQSHLsiv8i16, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_Imm }, }, 14543 { 3444 /* vqshl */, ARM::VQSHLsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 14544 { 3444 /* vqshl */, ARM::VQSHLsiv4i16, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_Imm }, }, 14545 { 3444 /* vqshl */, ARM::VQSHLsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 14546 { 3444 /* vqshl */, ARM::VQSHLsiv4i32, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_Imm }, }, 14547 { 3444 /* vqshl */, ARM::VQSHLsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 14548 { 3444 /* vqshl */, ARM::VQSHLsiv2i32, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_Imm }, }, 14549 { 3444 /* vqshl */, ARM::VQSHLsv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR }, }, 14550 { 3444 /* vqshl */, ARM::VQSHLsiv2i64, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_Imm }, }, 14551 { 3444 /* vqshl */, ARM::VQSHLsv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR }, }, 14552 { 3444 /* vqshl */, ARM::VQSHLsiv1i64, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_Imm }, }, 14553 { 3444 /* vqshl */, ARM::VQSHLsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, }, 14554 { 3444 /* vqshl */, ARM::VQSHLsiv16i8, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_Imm }, }, 14555 { 3444 /* vqshl */, ARM::VQSHLsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 14556 { 3444 /* vqshl */, ARM::VQSHLsiv8i8, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_Imm }, }, 14557 { 3444 /* vqshl */, ARM::VQSHLuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, }, 14558 { 3444 /* vqshl */, ARM::VQSHLuiv8i16, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_Imm }, }, 14559 { 3444 /* vqshl */, ARM::VQSHLuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, }, 14560 { 3444 /* vqshl */, ARM::VQSHLuiv4i16, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_Imm }, }, 14561 { 3444 /* vqshl */, ARM::VQSHLuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, }, 14562 { 3444 /* vqshl */, ARM::VQSHLuiv4i32, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_Imm }, }, 14563 { 3444 /* vqshl */, ARM::VQSHLuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, }, 14564 { 3444 /* vqshl */, ARM::VQSHLuiv2i32, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_Imm }, }, 14565 { 3444 /* vqshl */, ARM::VQSHLuv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR }, }, 14566 { 3444 /* vqshl */, ARM::VQSHLuiv2i64, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_Imm }, }, 14567 { 3444 /* vqshl */, ARM::VQSHLuv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR }, }, 14568 { 3444 /* vqshl */, ARM::VQSHLuiv1i64, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_Imm }, }, 14569 { 3444 /* vqshl */, ARM::VQSHLuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, }, 14570 { 3444 /* vqshl */, ARM::VQSHLuiv16i8, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_Imm }, }, 14571 { 3444 /* vqshl */, ARM::VQSHLuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, }, 14572 { 3444 /* vqshl */, ARM::VQSHLuiv8i8, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_Imm }, }, 14573 { 3444 /* vqshl */, ARM::MVE_VQSHL_qrs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_rGPR }, }, 14574 { 3444 /* vqshl */, ARM::MVE_VQSHL_qrs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_rGPR }, }, 14575 { 3444 /* vqshl */, ARM::MVE_VQSHL_qrs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_rGPR }, }, 14576 { 3444 /* vqshl */, ARM::MVE_VQSHL_qru16, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_rGPR }, }, 14577 { 3444 /* vqshl */, ARM::MVE_VQSHL_qru32, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_rGPR }, }, 14578 { 3444 /* vqshl */, ARM::MVE_VQSHL_qru8, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_MQPR, MCK_rGPR }, }, 14579 { 3444 /* vqshl */, ARM::VQSHLsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14580 { 3444 /* vqshl */, ARM::VQSHLsiv8i16, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_Imm }, }, 14581 { 3444 /* vqshl */, ARM::VQSHLsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14582 { 3444 /* vqshl */, ARM::VQSHLsiv4i16, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_Imm }, }, 14583 { 3444 /* vqshl */, ARM::VQSHLsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14584 { 3444 /* vqshl */, ARM::VQSHLsiv4i32, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_Imm }, }, 14585 { 3444 /* vqshl */, ARM::VQSHLsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14586 { 3444 /* vqshl */, ARM::VQSHLsiv2i32, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_Imm }, }, 14587 { 3444 /* vqshl */, ARM::VQSHLsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14588 { 3444 /* vqshl */, ARM::VQSHLsiv2i64, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_Imm }, }, 14589 { 3444 /* vqshl */, ARM::VQSHLsv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14590 { 3444 /* vqshl */, ARM::VQSHLsiv1i64, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_Imm }, }, 14591 { 3444 /* vqshl */, ARM::VQSHLsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14592 { 3444 /* vqshl */, ARM::VQSHLsiv16i8, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_Imm }, }, 14593 { 3444 /* vqshl */, ARM::VQSHLsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14594 { 3444 /* vqshl */, ARM::VQSHLsiv8i8, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_Imm }, }, 14595 { 3444 /* vqshl */, ARM::VQSHLuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14596 { 3444 /* vqshl */, ARM::VQSHLuiv8i16, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_Imm }, }, 14597 { 3444 /* vqshl */, ARM::VQSHLuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14598 { 3444 /* vqshl */, ARM::VQSHLuiv4i16, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_Imm }, }, 14599 { 3444 /* vqshl */, ARM::VQSHLuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14600 { 3444 /* vqshl */, ARM::VQSHLuiv4i32, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_Imm }, }, 14601 { 3444 /* vqshl */, ARM::VQSHLuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14602 { 3444 /* vqshl */, ARM::VQSHLuiv2i32, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_Imm }, }, 14603 { 3444 /* vqshl */, ARM::VQSHLuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14604 { 3444 /* vqshl */, ARM::VQSHLuiv2i64, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_Imm }, }, 14605 { 3444 /* vqshl */, ARM::VQSHLuv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14606 { 3444 /* vqshl */, ARM::VQSHLuiv1i64, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_Imm }, }, 14607 { 3444 /* vqshl */, ARM::VQSHLuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14608 { 3444 /* vqshl */, ARM::VQSHLuiv16i8, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_Imm }, }, 14609 { 3444 /* vqshl */, ARM::VQSHLuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14610 { 3444 /* vqshl */, ARM::VQSHLuiv8i8, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_Imm }, }, 14611 { 3444 /* vqshl */, ARM::MVE_VQSHL_by_vecs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14612 { 3444 /* vqshl */, ARM::MVE_VQSHLimms16, Convert__Reg1_2__Reg1_3__Imm0_151_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_Imm0_15 }, }, 14613 { 3444 /* vqshl */, ARM::MVE_VQSHL_by_vecs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14614 { 3444 /* vqshl */, ARM::MVE_VQSHLimms32, Convert__Reg1_2__Reg1_3__Imm0_311_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_Imm0_31 }, }, 14615 { 3444 /* vqshl */, ARM::MVE_VQSHL_by_vecs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14616 { 3444 /* vqshl */, ARM::MVE_VQSHLimms8, Convert__Reg1_2__Reg1_3__Imm0_71_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_Imm0_7 }, }, 14617 { 3444 /* vqshl */, ARM::MVE_VQSHL_by_vecu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14618 { 3444 /* vqshl */, ARM::MVE_VQSHLimmu16, Convert__Reg1_2__Reg1_3__Imm0_151_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_Imm0_15 }, }, 14619 { 3444 /* vqshl */, ARM::MVE_VQSHL_by_vecu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14620 { 3444 /* vqshl */, ARM::MVE_VQSHLimmu32, Convert__Reg1_2__Reg1_3__Imm0_311_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_Imm0_31 }, }, 14621 { 3444 /* vqshl */, ARM::MVE_VQSHL_by_vecu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14622 { 3444 /* vqshl */, ARM::MVE_VQSHLimmu8, Convert__Reg1_2__Reg1_3__Imm0_71_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_Imm0_7 }, }, 14623 { 3450 /* vqshlu */, ARM::VQSHLsuv8i16, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_Imm }, }, 14624 { 3450 /* vqshlu */, ARM::VQSHLsuv4i16, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_Imm }, }, 14625 { 3450 /* vqshlu */, ARM::VQSHLsuv4i32, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_Imm }, }, 14626 { 3450 /* vqshlu */, ARM::VQSHLsuv2i32, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_Imm }, }, 14627 { 3450 /* vqshlu */, ARM::VQSHLsuv2i64, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_Imm }, }, 14628 { 3450 /* vqshlu */, ARM::VQSHLsuv1i64, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_Imm }, }, 14629 { 3450 /* vqshlu */, ARM::VQSHLsuv16i8, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_Imm }, }, 14630 { 3450 /* vqshlu */, ARM::VQSHLsuv8i8, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_Imm }, }, 14631 { 3450 /* vqshlu */, ARM::VQSHLsuv8i16, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_Imm }, }, 14632 { 3450 /* vqshlu */, ARM::VQSHLsuv4i16, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_Imm }, }, 14633 { 3450 /* vqshlu */, ARM::VQSHLsuv4i32, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_Imm }, }, 14634 { 3450 /* vqshlu */, ARM::VQSHLsuv2i32, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_Imm }, }, 14635 { 3450 /* vqshlu */, ARM::VQSHLsuv2i64, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_Imm }, }, 14636 { 3450 /* vqshlu */, ARM::VQSHLsuv1i64, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_Imm }, }, 14637 { 3450 /* vqshlu */, ARM::VQSHLsuv16i8, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_Imm }, }, 14638 { 3450 /* vqshlu */, ARM::VQSHLsuv8i8, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_Imm }, }, 14639 { 3450 /* vqshlu */, ARM::MVE_VQSHLU_imms16, Convert__Reg1_2__Reg1_3__Imm0_151_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_Imm0_15 }, }, 14640 { 3450 /* vqshlu */, ARM::MVE_VQSHLU_imms32, Convert__Reg1_2__Reg1_3__Imm0_311_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_Imm0_31 }, }, 14641 { 3450 /* vqshlu */, ARM::MVE_VQSHLU_imms8, Convert__Reg1_2__Reg1_3__Imm0_71_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_Imm0_7 }, }, 14642 { 3457 /* vqshrn */, ARM::VQSHRNsv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_QPR, MCK_ShrImm8 }, }, 14643 { 3457 /* vqshrn */, ARM::VQSHRNsv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_QPR, MCK_ShrImm16 }, }, 14644 { 3457 /* vqshrn */, ARM::VQSHRNsv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_QPR, MCK_ShrImm32 }, }, 14645 { 3457 /* vqshrn */, ARM::VQSHRNuv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_QPR, MCK_ShrImm8 }, }, 14646 { 3457 /* vqshrn */, ARM::VQSHRNuv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_QPR, MCK_ShrImm16 }, }, 14647 { 3457 /* vqshrn */, ARM::VQSHRNuv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_QPR, MCK_ShrImm32 }, }, 14648 { 3464 /* vqshrnb */, ARM::MVE_VQSHRNbhs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, }, 14649 { 3464 /* vqshrnb */, ARM::MVE_VQSHRNbhs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, }, 14650 { 3464 /* vqshrnb */, ARM::MVE_VQSHRNbhu16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, }, 14651 { 3464 /* vqshrnb */, ARM::MVE_VQSHRNbhu32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, }, 14652 { 3472 /* vqshrnt */, ARM::MVE_VQSHRNths16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, }, 14653 { 3472 /* vqshrnt */, ARM::MVE_VQSHRNths32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, }, 14654 { 3472 /* vqshrnt */, ARM::MVE_VQSHRNthu16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, }, 14655 { 3472 /* vqshrnt */, ARM::MVE_VQSHRNthu32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, }, 14656 { 3480 /* vqshrun */, ARM::VQSHRUNv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_QPR, MCK_ShrImm8 }, }, 14657 { 3480 /* vqshrun */, ARM::VQSHRUNv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_QPR, MCK_ShrImm16 }, }, 14658 { 3480 /* vqshrun */, ARM::VQSHRUNv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_QPR, MCK_ShrImm32 }, }, 14659 { 3488 /* vqshrunb */, ARM::MVE_VQSHRUNs16bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, }, 14660 { 3488 /* vqshrunb */, ARM::MVE_VQSHRUNs32bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, }, 14661 { 3497 /* vqshrunt */, ARM::MVE_VQSHRUNs16th, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, }, 14662 { 3497 /* vqshrunt */, ARM::MVE_VQSHRUNs32th, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, }, 14663 { 3506 /* vqsub */, ARM::VQSUBsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 14664 { 3506 /* vqsub */, ARM::VQSUBsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 14665 { 3506 /* vqsub */, ARM::VQSUBsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 14666 { 3506 /* vqsub */, ARM::VQSUBsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 14667 { 3506 /* vqsub */, ARM::VQSUBsv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR }, }, 14668 { 3506 /* vqsub */, ARM::VQSUBsv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR }, }, 14669 { 3506 /* vqsub */, ARM::VQSUBsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, }, 14670 { 3506 /* vqsub */, ARM::VQSUBsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 14671 { 3506 /* vqsub */, ARM::VQSUBuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, }, 14672 { 3506 /* vqsub */, ARM::VQSUBuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, }, 14673 { 3506 /* vqsub */, ARM::VQSUBuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, }, 14674 { 3506 /* vqsub */, ARM::VQSUBuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, }, 14675 { 3506 /* vqsub */, ARM::VQSUBuv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR }, }, 14676 { 3506 /* vqsub */, ARM::VQSUBuv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR }, }, 14677 { 3506 /* vqsub */, ARM::VQSUBuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, }, 14678 { 3506 /* vqsub */, ARM::VQSUBuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, }, 14679 { 3506 /* vqsub */, ARM::VQSUBsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14680 { 3506 /* vqsub */, ARM::VQSUBsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14681 { 3506 /* vqsub */, ARM::VQSUBsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14682 { 3506 /* vqsub */, ARM::VQSUBsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14683 { 3506 /* vqsub */, ARM::VQSUBsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14684 { 3506 /* vqsub */, ARM::VQSUBsv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14685 { 3506 /* vqsub */, ARM::VQSUBsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14686 { 3506 /* vqsub */, ARM::VQSUBsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14687 { 3506 /* vqsub */, ARM::VQSUBuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14688 { 3506 /* vqsub */, ARM::VQSUBuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14689 { 3506 /* vqsub */, ARM::VQSUBuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14690 { 3506 /* vqsub */, ARM::VQSUBuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14691 { 3506 /* vqsub */, ARM::VQSUBuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14692 { 3506 /* vqsub */, ARM::VQSUBuv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14693 { 3506 /* vqsub */, ARM::VQSUBuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14694 { 3506 /* vqsub */, ARM::VQSUBuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14695 { 3506 /* vqsub */, ARM::MVE_VQSUBs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14696 { 3506 /* vqsub */, ARM::MVE_VQSUB_qr_s16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 14697 { 3506 /* vqsub */, ARM::MVE_VQSUBs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14698 { 3506 /* vqsub */, ARM::MVE_VQSUB_qr_s32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 14699 { 3506 /* vqsub */, ARM::MVE_VQSUBs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14700 { 3506 /* vqsub */, ARM::MVE_VQSUB_qr_s8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 14701 { 3506 /* vqsub */, ARM::MVE_VQSUBu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14702 { 3506 /* vqsub */, ARM::MVE_VQSUB_qr_u16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 14703 { 3506 /* vqsub */, ARM::MVE_VQSUBu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14704 { 3506 /* vqsub */, ARM::MVE_VQSUB_qr_u32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 14705 { 3506 /* vqsub */, ARM::MVE_VQSUBu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14706 { 3506 /* vqsub */, ARM::MVE_VQSUB_qr_u8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 14707 { 3512 /* vraddhn */, ARM::VRADDHNv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_QPR, MCK_QPR }, }, 14708 { 3512 /* vraddhn */, ARM::VRADDHNv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_QPR, MCK_QPR }, }, 14709 { 3512 /* vraddhn */, ARM::VRADDHNv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_QPR, MCK_QPR }, }, 14710 { 3520 /* vrecpe */, ARM::VRECPEq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, }, 14711 { 3520 /* vrecpe */, ARM::VRECPEd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, }, 14712 { 3520 /* vrecpe */, ARM::VRECPEfq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 14713 { 3520 /* vrecpe */, ARM::VRECPEfd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 14714 { 3520 /* vrecpe */, ARM::VRECPEhq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 14715 { 3520 /* vrecpe */, ARM::VRECPEhd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 14716 { 3527 /* vrecps */, ARM::VRECPSfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 14717 { 3527 /* vrecps */, ARM::VRECPSfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 14718 { 3527 /* vrecps */, ARM::VRECPShq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 14719 { 3527 /* vrecps */, ARM::VRECPShd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 14720 { 3527 /* vrecps */, ARM::VRECPSfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14721 { 3527 /* vrecps */, ARM::VRECPSfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14722 { 3527 /* vrecps */, ARM::VRECPShq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14723 { 3527 /* vrecps */, ARM::VRECPShd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14724 { 3534 /* vrev16 */, ARM::VREV16q8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, }, 14725 { 3534 /* vrev16 */, ARM::VREV16d8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, }, 14726 { 3534 /* vrev16 */, ARM::MVE_VREV16_8, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_8, MCK_MQPR, MCK_MQPR }, }, 14727 { 3541 /* vrev32 */, ARM::VREV32q16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, }, 14728 { 3541 /* vrev32 */, ARM::VREV32d16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, }, 14729 { 3541 /* vrev32 */, ARM::VREV32q8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, }, 14730 { 3541 /* vrev32 */, ARM::VREV32d8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, }, 14731 { 3541 /* vrev32 */, ARM::MVE_VREV32_16, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_16, MCK_MQPR, MCK_MQPR }, }, 14732 { 3541 /* vrev32 */, ARM::MVE_VREV32_8, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_8, MCK_MQPR, MCK_MQPR }, }, 14733 { 3548 /* vrev64 */, ARM::VREV64q16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, }, 14734 { 3548 /* vrev64 */, ARM::VREV64d16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, }, 14735 { 3548 /* vrev64 */, ARM::VREV64q32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, }, 14736 { 3548 /* vrev64 */, ARM::VREV64d32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, }, 14737 { 3548 /* vrev64 */, ARM::VREV64q8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, }, 14738 { 3548 /* vrev64 */, ARM::VREV64d8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, }, 14739 { 3548 /* vrev64 */, ARM::MVE_VREV64_16, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_16, MCK_MQPR, MCK_MQPR }, }, 14740 { 3548 /* vrev64 */, ARM::MVE_VREV64_32, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_32, MCK_MQPR, MCK_MQPR }, }, 14741 { 3548 /* vrev64 */, ARM::MVE_VREV64_8, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_8, MCK_MQPR, MCK_MQPR }, }, 14742 { 3555 /* vrhadd */, ARM::VRHADDsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 14743 { 3555 /* vrhadd */, ARM::VRHADDsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 14744 { 3555 /* vrhadd */, ARM::VRHADDsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 14745 { 3555 /* vrhadd */, ARM::VRHADDsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 14746 { 3555 /* vrhadd */, ARM::VRHADDsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, }, 14747 { 3555 /* vrhadd */, ARM::VRHADDsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 14748 { 3555 /* vrhadd */, ARM::VRHADDuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, }, 14749 { 3555 /* vrhadd */, ARM::VRHADDuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, }, 14750 { 3555 /* vrhadd */, ARM::VRHADDuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, }, 14751 { 3555 /* vrhadd */, ARM::VRHADDuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, }, 14752 { 3555 /* vrhadd */, ARM::VRHADDuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, }, 14753 { 3555 /* vrhadd */, ARM::VRHADDuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, }, 14754 { 3555 /* vrhadd */, ARM::VRHADDsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14755 { 3555 /* vrhadd */, ARM::VRHADDsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14756 { 3555 /* vrhadd */, ARM::VRHADDsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14757 { 3555 /* vrhadd */, ARM::VRHADDsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14758 { 3555 /* vrhadd */, ARM::VRHADDsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14759 { 3555 /* vrhadd */, ARM::VRHADDsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14760 { 3555 /* vrhadd */, ARM::VRHADDuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14761 { 3555 /* vrhadd */, ARM::VRHADDuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14762 { 3555 /* vrhadd */, ARM::VRHADDuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14763 { 3555 /* vrhadd */, ARM::VRHADDuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14764 { 3555 /* vrhadd */, ARM::VRHADDuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14765 { 3555 /* vrhadd */, ARM::VRHADDuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14766 { 3555 /* vrhadd */, ARM::MVE_VRHADDs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14767 { 3555 /* vrhadd */, ARM::MVE_VRHADDs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14768 { 3555 /* vrhadd */, ARM::MVE_VRHADDs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14769 { 3555 /* vrhadd */, ARM::MVE_VRHADDu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14770 { 3555 /* vrhadd */, ARM::MVE_VRHADDu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14771 { 3555 /* vrhadd */, ARM::MVE_VRHADDu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14772 { 3562 /* vrinta */, ARM::VRINTANQf, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON, { MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 14773 { 3562 /* vrinta */, ARM::VRINTANDf, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON, { MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 14774 { 3562 /* vrinta */, ARM::VRINTAS, Convert__Reg1_1__Reg1_2, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 14775 { 3562 /* vrinta */, ARM::VRINTAD, Convert__Reg1_1__Reg1_2, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 14776 { 3562 /* vrinta */, ARM::VRINTANQh, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 14777 { 3562 /* vrinta */, ARM::VRINTANDh, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 14778 { 3562 /* vrinta */, ARM::VRINTAH, Convert__Reg1_1__Reg1_2, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 14779 { 3562 /* vrinta */, ARM::VRINTANQf, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 14780 { 3562 /* vrinta */, ARM::VRINTANDf, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 14781 { 3562 /* vrinta */, ARM::VRINTAS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 14782 { 3562 /* vrinta */, ARM::VRINTAD, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 14783 { 3562 /* vrinta */, ARM::VRINTANQh, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 14784 { 3562 /* vrinta */, ARM::VRINTANDh, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 14785 { 3562 /* vrinta */, ARM::VRINTAH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 14786 { 3562 /* vrinta */, ARM::MVE_VRINTf32A, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, }, 14787 { 3562 /* vrinta */, ARM::MVE_VRINTf16A, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, }, 14788 { 3569 /* vrintm */, ARM::VRINTMNQf, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON, { MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 14789 { 3569 /* vrintm */, ARM::VRINTMNDf, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON, { MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 14790 { 3569 /* vrintm */, ARM::VRINTMS, Convert__Reg1_1__Reg1_2, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 14791 { 3569 /* vrintm */, ARM::VRINTMD, Convert__Reg1_1__Reg1_2, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 14792 { 3569 /* vrintm */, ARM::VRINTMNQh, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 14793 { 3569 /* vrintm */, ARM::VRINTMNDh, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 14794 { 3569 /* vrintm */, ARM::VRINTMH, Convert__Reg1_1__Reg1_2, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 14795 { 3569 /* vrintm */, ARM::VRINTMNQf, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 14796 { 3569 /* vrintm */, ARM::VRINTMNDf, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 14797 { 3569 /* vrintm */, ARM::VRINTMS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 14798 { 3569 /* vrintm */, ARM::VRINTMD, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 14799 { 3569 /* vrintm */, ARM::VRINTMNQh, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 14800 { 3569 /* vrintm */, ARM::VRINTMNDh, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 14801 { 3569 /* vrintm */, ARM::VRINTMH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 14802 { 3569 /* vrintm */, ARM::MVE_VRINTf32M, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, }, 14803 { 3569 /* vrintm */, ARM::MVE_VRINTf16M, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, }, 14804 { 3576 /* vrintn */, ARM::VRINTNNQf, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON, { MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 14805 { 3576 /* vrintn */, ARM::VRINTNNDf, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON, { MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 14806 { 3576 /* vrintn */, ARM::VRINTNS, Convert__Reg1_1__Reg1_2, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 14807 { 3576 /* vrintn */, ARM::VRINTND, Convert__Reg1_1__Reg1_2, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 14808 { 3576 /* vrintn */, ARM::VRINTNNQh, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 14809 { 3576 /* vrintn */, ARM::VRINTNNDh, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 14810 { 3576 /* vrintn */, ARM::VRINTNH, Convert__Reg1_1__Reg1_2, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 14811 { 3576 /* vrintn */, ARM::VRINTNNQf, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 14812 { 3576 /* vrintn */, ARM::VRINTNNDf, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 14813 { 3576 /* vrintn */, ARM::VRINTNS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 14814 { 3576 /* vrintn */, ARM::VRINTND, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 14815 { 3576 /* vrintn */, ARM::VRINTNNQh, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 14816 { 3576 /* vrintn */, ARM::VRINTNNDh, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 14817 { 3576 /* vrintn */, ARM::VRINTNH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 14818 { 3576 /* vrintn */, ARM::MVE_VRINTf32N, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, }, 14819 { 3576 /* vrintn */, ARM::MVE_VRINTf16N, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, }, 14820 { 3583 /* vrintp */, ARM::VRINTPNQf, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON, { MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 14821 { 3583 /* vrintp */, ARM::VRINTPNDf, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON, { MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 14822 { 3583 /* vrintp */, ARM::VRINTPS, Convert__Reg1_1__Reg1_2, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 14823 { 3583 /* vrintp */, ARM::VRINTPD, Convert__Reg1_1__Reg1_2, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 14824 { 3583 /* vrintp */, ARM::VRINTPNQh, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 14825 { 3583 /* vrintp */, ARM::VRINTPNDh, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 14826 { 3583 /* vrintp */, ARM::VRINTPH, Convert__Reg1_1__Reg1_2, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 14827 { 3583 /* vrintp */, ARM::VRINTPNQf, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 14828 { 3583 /* vrintp */, ARM::VRINTPNDf, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 14829 { 3583 /* vrintp */, ARM::VRINTPS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 14830 { 3583 /* vrintp */, ARM::VRINTPD, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 14831 { 3583 /* vrintp */, ARM::VRINTPNQh, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 14832 { 3583 /* vrintp */, ARM::VRINTPNDh, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 14833 { 3583 /* vrintp */, ARM::VRINTPH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 14834 { 3583 /* vrintp */, ARM::MVE_VRINTf32P, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, }, 14835 { 3583 /* vrintp */, ARM::MVE_VRINTf16P, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, }, 14836 { 3590 /* vrintr */, ARM::VRINTRS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPARMv8, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 14837 { 3590 /* vrintr */, ARM::VRINTRD, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPARMv8_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 14838 { 3590 /* vrintr */, ARM::VRINTRH, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 14839 { 3590 /* vrintr */, ARM::VRINTRS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPARMv8, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 14840 { 3590 /* vrintr */, ARM::VRINTRD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPARMv8_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 14841 { 3590 /* vrintr */, ARM::VRINTRH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 14842 { 3597 /* vrintx */, ARM::VRINTXNQf, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON, { MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 14843 { 3597 /* vrintx */, ARM::VRINTXNDf, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON, { MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 14844 { 3597 /* vrintx */, ARM::VRINTXNQh, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 14845 { 3597 /* vrintx */, ARM::VRINTXNDh, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 14846 { 3597 /* vrintx */, ARM::VRINTXNQf, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 14847 { 3597 /* vrintx */, ARM::VRINTXNDf, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 14848 { 3597 /* vrintx */, ARM::VRINTXNQh, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 14849 { 3597 /* vrintx */, ARM::VRINTXNDh, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 14850 { 3597 /* vrintx */, ARM::VRINTXS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPARMv8, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 14851 { 3597 /* vrintx */, ARM::VRINTXD, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPARMv8_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 14852 { 3597 /* vrintx */, ARM::VRINTXH, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 14853 { 3597 /* vrintx */, ARM::MVE_VRINTf32X, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, }, 14854 { 3597 /* vrintx */, ARM::MVE_VRINTf16X, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, }, 14855 { 3597 /* vrintx */, ARM::VRINTXS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPARMv8, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 14856 { 3597 /* vrintx */, ARM::VRINTXD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPARMv8_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 14857 { 3597 /* vrintx */, ARM::VRINTXH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 14858 { 3604 /* vrintz */, ARM::VRINTZNQf, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON, { MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 14859 { 3604 /* vrintz */, ARM::VRINTZNDf, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON, { MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 14860 { 3604 /* vrintz */, ARM::VRINTZNQh, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 14861 { 3604 /* vrintz */, ARM::VRINTZNDh, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 14862 { 3604 /* vrintz */, ARM::VRINTZNQf, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 14863 { 3604 /* vrintz */, ARM::VRINTZNDf, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 14864 { 3604 /* vrintz */, ARM::VRINTZNQh, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 14865 { 3604 /* vrintz */, ARM::VRINTZNDh, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 14866 { 3604 /* vrintz */, ARM::VRINTZS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPARMv8, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 14867 { 3604 /* vrintz */, ARM::VRINTZD, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPARMv8_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 14868 { 3604 /* vrintz */, ARM::VRINTZH, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 14869 { 3604 /* vrintz */, ARM::MVE_VRINTf32Z, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, }, 14870 { 3604 /* vrintz */, ARM::MVE_VRINTf16Z, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, }, 14871 { 3604 /* vrintz */, ARM::VRINTZS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPARMv8, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 14872 { 3604 /* vrintz */, ARM::VRINTZD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPARMv8_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 14873 { 3604 /* vrintz */, ARM::VRINTZH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 14874 { 3611 /* vrmlaldavh */, ARM::MVE_VRMLALDAVHs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 14875 { 3611 /* vrmlaldavh */, ARM::MVE_VRMLALDAVHu32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 14876 { 3622 /* vrmlaldavha */, ARM::MVE_VRMLALDAVHas32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 14877 { 3622 /* vrmlaldavha */, ARM::MVE_VRMLALDAVHau32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 14878 { 3634 /* vrmlaldavhax */, ARM::MVE_VRMLALDAVHaxs32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 14879 { 3647 /* vrmlaldavhx */, ARM::MVE_VRMLALDAVHxs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 14880 { 3659 /* vrmlalvh */, ARM::MVE_VRMLALDAVHs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 14881 { 3659 /* vrmlalvh */, ARM::MVE_VRMLALDAVHu32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 14882 { 3668 /* vrmlalvha */, ARM::MVE_VRMLALDAVHas32, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 14883 { 3668 /* vrmlalvha */, ARM::MVE_VRMLALDAVHau32, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 14884 { 3678 /* vrmlsldavh */, ARM::MVE_VRMLSLDAVHs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 14885 { 3689 /* vrmlsldavha */, ARM::MVE_VRMLSLDAVHas32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 14886 { 3701 /* vrmlsldavhax */, ARM::MVE_VRMLSLDAVHaxs32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 14887 { 3714 /* vrmlsldavhx */, ARM::MVE_VRMLSLDAVHxs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, }, 14888 { 3726 /* vrmulh */, ARM::MVE_VRMULHs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14889 { 3726 /* vrmulh */, ARM::MVE_VRMULHs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14890 { 3726 /* vrmulh */, ARM::MVE_VRMULHs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14891 { 3726 /* vrmulh */, ARM::MVE_VRMULHu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14892 { 3726 /* vrmulh */, ARM::MVE_VRMULHu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14893 { 3726 /* vrmulh */, ARM::MVE_VRMULHu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14894 { 3733 /* vrshl */, ARM::VRSHLsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 14895 { 3733 /* vrshl */, ARM::VRSHLsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 14896 { 3733 /* vrshl */, ARM::VRSHLsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 14897 { 3733 /* vrshl */, ARM::VRSHLsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 14898 { 3733 /* vrshl */, ARM::VRSHLsv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR }, }, 14899 { 3733 /* vrshl */, ARM::VRSHLsv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR }, }, 14900 { 3733 /* vrshl */, ARM::VRSHLsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, }, 14901 { 3733 /* vrshl */, ARM::VRSHLsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 14902 { 3733 /* vrshl */, ARM::VRSHLuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, }, 14903 { 3733 /* vrshl */, ARM::VRSHLuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, }, 14904 { 3733 /* vrshl */, ARM::VRSHLuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, }, 14905 { 3733 /* vrshl */, ARM::VRSHLuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, }, 14906 { 3733 /* vrshl */, ARM::VRSHLuv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR }, }, 14907 { 3733 /* vrshl */, ARM::VRSHLuv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR }, }, 14908 { 3733 /* vrshl */, ARM::VRSHLuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, }, 14909 { 3733 /* vrshl */, ARM::VRSHLuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, }, 14910 { 3733 /* vrshl */, ARM::MVE_VRSHL_qrs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_rGPR }, }, 14911 { 3733 /* vrshl */, ARM::MVE_VRSHL_qrs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_rGPR }, }, 14912 { 3733 /* vrshl */, ARM::MVE_VRSHL_qrs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_rGPR }, }, 14913 { 3733 /* vrshl */, ARM::MVE_VRSHL_qru16, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_rGPR }, }, 14914 { 3733 /* vrshl */, ARM::MVE_VRSHL_qru32, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_rGPR }, }, 14915 { 3733 /* vrshl */, ARM::MVE_VRSHL_qru8, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_MQPR, MCK_rGPR }, }, 14916 { 3733 /* vrshl */, ARM::VRSHLsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14917 { 3733 /* vrshl */, ARM::VRSHLsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14918 { 3733 /* vrshl */, ARM::VRSHLsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14919 { 3733 /* vrshl */, ARM::VRSHLsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14920 { 3733 /* vrshl */, ARM::VRSHLsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14921 { 3733 /* vrshl */, ARM::VRSHLsv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14922 { 3733 /* vrshl */, ARM::VRSHLsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14923 { 3733 /* vrshl */, ARM::VRSHLsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14924 { 3733 /* vrshl */, ARM::VRSHLuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14925 { 3733 /* vrshl */, ARM::VRSHLuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14926 { 3733 /* vrshl */, ARM::VRSHLuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14927 { 3733 /* vrshl */, ARM::VRSHLuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14928 { 3733 /* vrshl */, ARM::VRSHLuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14929 { 3733 /* vrshl */, ARM::VRSHLuv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14930 { 3733 /* vrshl */, ARM::VRSHLuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14931 { 3733 /* vrshl */, ARM::VRSHLuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14932 { 3733 /* vrshl */, ARM::MVE_VRSHL_by_vecs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14933 { 3733 /* vrshl */, ARM::MVE_VRSHL_by_vecs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14934 { 3733 /* vrshl */, ARM::MVE_VRSHL_by_vecs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14935 { 3733 /* vrshl */, ARM::MVE_VRSHL_by_vecu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14936 { 3733 /* vrshl */, ARM::MVE_VRSHL_by_vecu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14937 { 3733 /* vrshl */, ARM::MVE_VRSHL_by_vecu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 14938 { 3739 /* vrshr */, ARM::VRSHRsv8i16, Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_ShrImm16 }, }, 14939 { 3739 /* vrshr */, ARM::VRSHRsv4i16, Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_ShrImm16 }, }, 14940 { 3739 /* vrshr */, ARM::VRSHRsv4i32, Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_ShrImm32 }, }, 14941 { 3739 /* vrshr */, ARM::VRSHRsv2i32, Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_ShrImm32 }, }, 14942 { 3739 /* vrshr */, ARM::VRSHRsv2i64, Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_ShrImm64 }, }, 14943 { 3739 /* vrshr */, ARM::VRSHRsv1i64, Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_ShrImm64 }, }, 14944 { 3739 /* vrshr */, ARM::VRSHRsv16i8, Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_ShrImm8 }, }, 14945 { 3739 /* vrshr */, ARM::VRSHRsv8i8, Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_ShrImm8 }, }, 14946 { 3739 /* vrshr */, ARM::VRSHRuv8i16, Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_ShrImm16 }, }, 14947 { 3739 /* vrshr */, ARM::VRSHRuv4i16, Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_ShrImm16 }, }, 14948 { 3739 /* vrshr */, ARM::VRSHRuv4i32, Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_ShrImm32 }, }, 14949 { 3739 /* vrshr */, ARM::VRSHRuv2i32, Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_ShrImm32 }, }, 14950 { 3739 /* vrshr */, ARM::VRSHRuv2i64, Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_ShrImm64 }, }, 14951 { 3739 /* vrshr */, ARM::VRSHRuv1i64, Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_ShrImm64 }, }, 14952 { 3739 /* vrshr */, ARM::VRSHRuv16i8, Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_ShrImm8 }, }, 14953 { 3739 /* vrshr */, ARM::VRSHRuv8i8, Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_ShrImm8 }, }, 14954 { 3739 /* vrshr */, ARM::VRSHRsv8i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_ShrImm16 }, }, 14955 { 3739 /* vrshr */, ARM::VRSHRsv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_ShrImm16 }, }, 14956 { 3739 /* vrshr */, ARM::VRSHRsv4i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_ShrImm32 }, }, 14957 { 3739 /* vrshr */, ARM::VRSHRsv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_ShrImm32 }, }, 14958 { 3739 /* vrshr */, ARM::VRSHRsv2i64, Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_ShrImm64 }, }, 14959 { 3739 /* vrshr */, ARM::VRSHRsv1i64, Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_ShrImm64 }, }, 14960 { 3739 /* vrshr */, ARM::VRSHRsv16i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_ShrImm8 }, }, 14961 { 3739 /* vrshr */, ARM::VRSHRsv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_ShrImm8 }, }, 14962 { 3739 /* vrshr */, ARM::VRSHRuv8i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_ShrImm16 }, }, 14963 { 3739 /* vrshr */, ARM::VRSHRuv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_ShrImm16 }, }, 14964 { 3739 /* vrshr */, ARM::VRSHRuv4i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_ShrImm32 }, }, 14965 { 3739 /* vrshr */, ARM::VRSHRuv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_ShrImm32 }, }, 14966 { 3739 /* vrshr */, ARM::VRSHRuv2i64, Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_ShrImm64 }, }, 14967 { 3739 /* vrshr */, ARM::VRSHRuv1i64, Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_ShrImm64 }, }, 14968 { 3739 /* vrshr */, ARM::VRSHRuv16i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_ShrImm8 }, }, 14969 { 3739 /* vrshr */, ARM::VRSHRuv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_ShrImm8 }, }, 14970 { 3739 /* vrshr */, ARM::MVE_VRSHR_imms16, Convert__Reg1_2__Reg1_3__ShrImm161_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, }, 14971 { 3739 /* vrshr */, ARM::MVE_VRSHR_imms32, Convert__Reg1_2__Reg1_3__ShrImm321_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm32 }, }, 14972 { 3739 /* vrshr */, ARM::MVE_VRSHR_imms8, Convert__Reg1_2__Reg1_3__ShrImm81_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, }, 14973 { 3739 /* vrshr */, ARM::MVE_VRSHR_immu16, Convert__Reg1_2__Reg1_3__ShrImm161_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, }, 14974 { 3739 /* vrshr */, ARM::MVE_VRSHR_immu32, Convert__Reg1_2__Reg1_3__ShrImm321_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_ShrImm32 }, }, 14975 { 3739 /* vrshr */, ARM::MVE_VRSHR_immu8, Convert__Reg1_2__Reg1_3__ShrImm81_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, }, 14976 { 3745 /* vrshrn */, ARM::VRSHRNv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_QPR, MCK_ShrImm8 }, }, 14977 { 3745 /* vrshrn */, ARM::VRSHRNv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_QPR, MCK_ShrImm16 }, }, 14978 { 3745 /* vrshrn */, ARM::VRSHRNv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_QPR, MCK_ShrImm32 }, }, 14979 { 3752 /* vrshrnb */, ARM::MVE_VRSHRNi16bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, }, 14980 { 3752 /* vrshrnb */, ARM::MVE_VRSHRNi32bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, }, 14981 { 3760 /* vrshrnt */, ARM::MVE_VRSHRNi16th, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, }, 14982 { 3760 /* vrshrnt */, ARM::MVE_VRSHRNi32th, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, }, 14983 { 3768 /* vrsqrte */, ARM::VRSQRTEq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, }, 14984 { 3768 /* vrsqrte */, ARM::VRSQRTEd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, }, 14985 { 3768 /* vrsqrte */, ARM::VRSQRTEfq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 14986 { 3768 /* vrsqrte */, ARM::VRSQRTEfd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 14987 { 3768 /* vrsqrte */, ARM::VRSQRTEhq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 14988 { 3768 /* vrsqrte */, ARM::VRSQRTEhd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 14989 { 3776 /* vrsqrts */, ARM::VRSQRTSfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 14990 { 3776 /* vrsqrts */, ARM::VRSQRTSfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 14991 { 3776 /* vrsqrts */, ARM::VRSQRTShq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 14992 { 3776 /* vrsqrts */, ARM::VRSQRTShd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 14993 { 3776 /* vrsqrts */, ARM::VRSQRTSfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14994 { 3776 /* vrsqrts */, ARM::VRSQRTSfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14995 { 3776 /* vrsqrts */, ARM::VRSQRTShq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 14996 { 3776 /* vrsqrts */, ARM::VRSQRTShd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 14997 { 3784 /* vrsra */, ARM::VRSRAsv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_ShrImm16 }, }, 14998 { 3784 /* vrsra */, ARM::VRSRAsv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_ShrImm16 }, }, 14999 { 3784 /* vrsra */, ARM::VRSRAsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_ShrImm32 }, }, 15000 { 3784 /* vrsra */, ARM::VRSRAsv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_ShrImm32 }, }, 15001 { 3784 /* vrsra */, ARM::VRSRAsv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_ShrImm64 }, }, 15002 { 3784 /* vrsra */, ARM::VRSRAsv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_ShrImm64 }, }, 15003 { 3784 /* vrsra */, ARM::VRSRAsv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_ShrImm8 }, }, 15004 { 3784 /* vrsra */, ARM::VRSRAsv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_ShrImm8 }, }, 15005 { 3784 /* vrsra */, ARM::VRSRAuv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_ShrImm16 }, }, 15006 { 3784 /* vrsra */, ARM::VRSRAuv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_ShrImm16 }, }, 15007 { 3784 /* vrsra */, ARM::VRSRAuv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_ShrImm32 }, }, 15008 { 3784 /* vrsra */, ARM::VRSRAuv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_ShrImm32 }, }, 15009 { 3784 /* vrsra */, ARM::VRSRAuv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_ShrImm64 }, }, 15010 { 3784 /* vrsra */, ARM::VRSRAuv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_ShrImm64 }, }, 15011 { 3784 /* vrsra */, ARM::VRSRAuv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_ShrImm8 }, }, 15012 { 3784 /* vrsra */, ARM::VRSRAuv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_ShrImm8 }, }, 15013 { 3784 /* vrsra */, ARM::VRSRAsv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_ShrImm16 }, }, 15014 { 3784 /* vrsra */, ARM::VRSRAsv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_ShrImm16 }, }, 15015 { 3784 /* vrsra */, ARM::VRSRAsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_ShrImm32 }, }, 15016 { 3784 /* vrsra */, ARM::VRSRAsv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_ShrImm32 }, }, 15017 { 3784 /* vrsra */, ARM::VRSRAsv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_ShrImm64 }, }, 15018 { 3784 /* vrsra */, ARM::VRSRAsv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_ShrImm64 }, }, 15019 { 3784 /* vrsra */, ARM::VRSRAsv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_ShrImm8 }, }, 15020 { 3784 /* vrsra */, ARM::VRSRAsv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_ShrImm8 }, }, 15021 { 3784 /* vrsra */, ARM::VRSRAuv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_ShrImm16 }, }, 15022 { 3784 /* vrsra */, ARM::VRSRAuv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_ShrImm16 }, }, 15023 { 3784 /* vrsra */, ARM::VRSRAuv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_ShrImm32 }, }, 15024 { 3784 /* vrsra */, ARM::VRSRAuv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_ShrImm32 }, }, 15025 { 3784 /* vrsra */, ARM::VRSRAuv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_ShrImm64 }, }, 15026 { 3784 /* vrsra */, ARM::VRSRAuv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_ShrImm64 }, }, 15027 { 3784 /* vrsra */, ARM::VRSRAuv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_ShrImm8 }, }, 15028 { 3784 /* vrsra */, ARM::VRSRAuv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_ShrImm8 }, }, 15029 { 3790 /* vrsubhn */, ARM::VRSUBHNv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_QPR, MCK_QPR }, }, 15030 { 3790 /* vrsubhn */, ARM::VRSUBHNv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_QPR, MCK_QPR }, }, 15031 { 3790 /* vrsubhn */, ARM::VRSUBHNv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_QPR, MCK_QPR }, }, 15032 { 3798 /* vsbc */, ARM::MVE_VSBC, Convert__Reg1_2__imm_95_0__Reg1_3__Reg1_4__imm_95_0__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 15033 { 3803 /* vsbci */, ARM::MVE_VSBCI, Convert__Reg1_2__imm_95_0__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 15034 { 3809 /* vscclrm */, ARM::VSCCLRMD, Convert__CondCode2_0__FPDRegListWithVPR1_1, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPDRegListWithVPR }, }, 15035 { 3809 /* vscclrm */, ARM::VSCCLRMS, Convert__CondCode2_0__FPSRegListWithVPR1_1, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPSRegListWithVPR }, }, 15036 { 3817 /* vsdot */, ARM::VSDOTQ, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasDotProd, { MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 15037 { 3817 /* vsdot */, ARM::VSDOTD, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasDotProd, { MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 15038 { 3817 /* vsdot */, ARM::VSDOTQI, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4, AMFBS_HasDotProd, { MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 15039 { 3817 /* vsdot */, ARM::VSDOTDI, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4, AMFBS_HasDotProd, { MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 15040 { 3823 /* vseleq */, ARM::VSELEQS, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, }, 15041 { 3823 /* vseleq */, ARM::VSELEQD, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 15042 { 3823 /* vseleq */, ARM::VSELEQH, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, }, 15043 { 3830 /* vselge */, ARM::VSELGES, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, }, 15044 { 3830 /* vselge */, ARM::VSELGED, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 15045 { 3830 /* vselge */, ARM::VSELGEH, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, }, 15046 { 3837 /* vselgt */, ARM::VSELGTS, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, }, 15047 { 3837 /* vselgt */, ARM::VSELGTD, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 15048 { 3837 /* vselgt */, ARM::VSELGTH, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, }, 15049 { 3844 /* vselvs */, ARM::VSELVSS, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, }, 15050 { 3844 /* vselvs */, ARM::VSELVSD, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 15051 { 3844 /* vselvs */, ARM::VSELVSH, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, }, 15052 { 3851 /* vshl */, ARM::VSHLsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 15053 { 3851 /* vshl */, ARM::VSHLsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 15054 { 3851 /* vshl */, ARM::VSHLsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 15055 { 3851 /* vshl */, ARM::VSHLsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 15056 { 3851 /* vshl */, ARM::VSHLsv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR }, }, 15057 { 3851 /* vshl */, ARM::VSHLsv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR }, }, 15058 { 3851 /* vshl */, ARM::VSHLsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, }, 15059 { 3851 /* vshl */, ARM::VSHLsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 15060 { 3851 /* vshl */, ARM::VSHLuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, }, 15061 { 3851 /* vshl */, ARM::VSHLuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, }, 15062 { 3851 /* vshl */, ARM::VSHLuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, }, 15063 { 3851 /* vshl */, ARM::VSHLuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, }, 15064 { 3851 /* vshl */, ARM::VSHLuv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR }, }, 15065 { 3851 /* vshl */, ARM::VSHLuv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR }, }, 15066 { 3851 /* vshl */, ARM::VSHLuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, }, 15067 { 3851 /* vshl */, ARM::VSHLuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, }, 15068 { 3851 /* vshl */, ARM::VSHLiv8i16, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_Imm }, }, 15069 { 3851 /* vshl */, ARM::VSHLiv4i16, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_Imm }, }, 15070 { 3851 /* vshl */, ARM::VSHLiv4i32, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_Imm }, }, 15071 { 3851 /* vshl */, ARM::VSHLiv2i32, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_Imm }, }, 15072 { 3851 /* vshl */, ARM::VSHLiv2i64, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_Imm }, }, 15073 { 3851 /* vshl */, ARM::VSHLiv1i64, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_Imm }, }, 15074 { 3851 /* vshl */, ARM::VSHLiv16i8, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_Imm }, }, 15075 { 3851 /* vshl */, ARM::VSHLiv8i8, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_Imm }, }, 15076 { 3851 /* vshl */, ARM::MVE_VSHL_qrs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_rGPR }, }, 15077 { 3851 /* vshl */, ARM::MVE_VSHL_qrs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_rGPR }, }, 15078 { 3851 /* vshl */, ARM::MVE_VSHL_qrs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_rGPR }, }, 15079 { 3851 /* vshl */, ARM::MVE_VSHL_qru16, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_rGPR }, }, 15080 { 3851 /* vshl */, ARM::MVE_VSHL_qru32, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_rGPR }, }, 15081 { 3851 /* vshl */, ARM::MVE_VSHL_qru8, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_MQPR, MCK_rGPR }, }, 15082 { 3851 /* vshl */, ARM::VSHLsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 15083 { 3851 /* vshl */, ARM::VSHLsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 15084 { 3851 /* vshl */, ARM::VSHLsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 15085 { 3851 /* vshl */, ARM::VSHLsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 15086 { 3851 /* vshl */, ARM::VSHLsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_QPR }, }, 15087 { 3851 /* vshl */, ARM::VSHLsv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 15088 { 3851 /* vshl */, ARM::VSHLsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 15089 { 3851 /* vshl */, ARM::VSHLsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 15090 { 3851 /* vshl */, ARM::VSHLuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 15091 { 3851 /* vshl */, ARM::VSHLuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 15092 { 3851 /* vshl */, ARM::VSHLuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 15093 { 3851 /* vshl */, ARM::VSHLuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 15094 { 3851 /* vshl */, ARM::VSHLuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_QPR }, }, 15095 { 3851 /* vshl */, ARM::VSHLuv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 15096 { 3851 /* vshl */, ARM::VSHLuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 15097 { 3851 /* vshl */, ARM::VSHLuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 15098 { 3851 /* vshl */, ARM::VSHLiv8i16, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_Imm }, }, 15099 { 3851 /* vshl */, ARM::VSHLiv4i16, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_Imm }, }, 15100 { 3851 /* vshl */, ARM::VSHLiv4i32, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_Imm }, }, 15101 { 3851 /* vshl */, ARM::VSHLiv2i32, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_Imm }, }, 15102 { 3851 /* vshl */, ARM::VSHLiv2i64, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_QPR, MCK_Imm }, }, 15103 { 3851 /* vshl */, ARM::VSHLiv1i64, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_DPR, MCK_Imm }, }, 15104 { 3851 /* vshl */, ARM::VSHLiv16i8, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR, MCK_Imm }, }, 15105 { 3851 /* vshl */, ARM::VSHLiv8i8, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR, MCK_Imm }, }, 15106 { 3851 /* vshl */, ARM::MVE_VSHL_by_vecs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 15107 { 3851 /* vshl */, ARM::MVE_VSHL_by_vecs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 15108 { 3851 /* vshl */, ARM::MVE_VSHL_by_vecs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 15109 { 3851 /* vshl */, ARM::MVE_VSHL_by_vecu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 15110 { 3851 /* vshl */, ARM::MVE_VSHL_by_vecu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 15111 { 3851 /* vshl */, ARM::MVE_VSHL_by_vecu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 15112 { 3851 /* vshl */, ARM::MVE_VSHL_immi16, Convert__Reg1_2__Reg1_3__Imm0_151_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_Imm0_15 }, }, 15113 { 3851 /* vshl */, ARM::MVE_VSHL_immi32, Convert__Reg1_2__Reg1_3__Imm0_311_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_Imm0_31 }, }, 15114 { 3851 /* vshl */, ARM::MVE_VSHL_immi8, Convert__Reg1_2__Reg1_3__Imm0_71_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_Imm0_7 }, }, 15115 { 3856 /* vshlc */, ARM::MVE_VSHLC, Convert__Reg1_2__Reg1_1__Tie1_2_2__Tie0_3_3__MVELongShift1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK_MQPR, MCK_rGPR, MCK_MVELongShift }, }, 15116 { 3862 /* vshll */, ARM::VSHLLsv4i32, Convert__Reg1_2__Reg1_3__Imm1_151_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_Imm1_15 }, }, 15117 { 3862 /* vshll */, ARM::VSHLLsv2i64, Convert__Reg1_2__Reg1_3__Imm1_311_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_Imm1_31 }, }, 15118 { 3862 /* vshll */, ARM::VSHLLsv8i16, Convert__Reg1_2__Reg1_3__Imm1_71_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR, MCK_Imm1_7 }, }, 15119 { 3862 /* vshll */, ARM::VSHLLuv4i32, Convert__Reg1_2__Reg1_3__Imm1_151_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_Imm1_15 }, }, 15120 { 3862 /* vshll */, ARM::VSHLLuv2i64, Convert__Reg1_2__Reg1_3__Imm1_311_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_Imm1_31 }, }, 15121 { 3862 /* vshll */, ARM::VSHLLuv8i16, Convert__Reg1_2__Reg1_3__Imm1_71_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR, MCK_Imm1_7 }, }, 15122 { 3862 /* vshll */, ARM::VSHLLi16, Convert__Reg1_2__Reg1_3__Imm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_DPR, MCK_Imm16 }, }, 15123 { 3862 /* vshll */, ARM::VSHLLi32, Convert__Reg1_2__Reg1_3__Imm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_DPR, MCK_Imm32 }, }, 15124 { 3862 /* vshll */, ARM::VSHLLi8, Convert__Reg1_2__Reg1_3__Imm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_DPR, MCK_Imm8 }, }, 15125 { 3868 /* vshllb */, ARM::MVE_VSHLL_lws16bh, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK__HASH_16 }, }, 15126 { 3868 /* vshllb */, ARM::MVE_VSHLL_imms16bh, Convert__Reg1_2__Reg1_3__MVEShiftImm1_151_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MVEShiftImm1_15 }, }, 15127 { 3868 /* vshllb */, ARM::MVE_VSHLL_lws8bh, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK__HASH_8 }, }, 15128 { 3868 /* vshllb */, ARM::MVE_VSHLL_imms8bh, Convert__Reg1_2__Reg1_3__MVEShiftImm1_71_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MVEShiftImm1_7 }, }, 15129 { 3868 /* vshllb */, ARM::MVE_VSHLL_lwu16bh, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK__HASH_16 }, }, 15130 { 3868 /* vshllb */, ARM::MVE_VSHLL_immu16bh, Convert__Reg1_2__Reg1_3__MVEShiftImm1_151_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MVEShiftImm1_15 }, }, 15131 { 3868 /* vshllb */, ARM::MVE_VSHLL_lwu8bh, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK__HASH_8 }, }, 15132 { 3868 /* vshllb */, ARM::MVE_VSHLL_immu8bh, Convert__Reg1_2__Reg1_3__MVEShiftImm1_71_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MVEShiftImm1_7 }, }, 15133 { 3875 /* vshllt */, ARM::MVE_VSHLL_lws16th, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK__HASH_16 }, }, 15134 { 3875 /* vshllt */, ARM::MVE_VSHLL_imms16th, Convert__Reg1_2__Reg1_3__MVEShiftImm1_151_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MVEShiftImm1_15 }, }, 15135 { 3875 /* vshllt */, ARM::MVE_VSHLL_lws8th, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK__HASH_8 }, }, 15136 { 3875 /* vshllt */, ARM::MVE_VSHLL_imms8th, Convert__Reg1_2__Reg1_3__MVEShiftImm1_71_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MVEShiftImm1_7 }, }, 15137 { 3875 /* vshllt */, ARM::MVE_VSHLL_lwu16th, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK__HASH_16 }, }, 15138 { 3875 /* vshllt */, ARM::MVE_VSHLL_immu16th, Convert__Reg1_2__Reg1_3__MVEShiftImm1_151_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MVEShiftImm1_15 }, }, 15139 { 3875 /* vshllt */, ARM::MVE_VSHLL_lwu8th, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK__HASH_8 }, }, 15140 { 3875 /* vshllt */, ARM::MVE_VSHLL_immu8th, Convert__Reg1_2__Reg1_3__MVEShiftImm1_71_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MVEShiftImm1_7 }, }, 15141 { 3882 /* vshr */, ARM::VSHRsv8i16, Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_ShrImm16 }, }, 15142 { 3882 /* vshr */, ARM::VSHRsv4i16, Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_ShrImm16 }, }, 15143 { 3882 /* vshr */, ARM::VSHRsv4i32, Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_ShrImm32 }, }, 15144 { 3882 /* vshr */, ARM::VSHRsv2i32, Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_ShrImm32 }, }, 15145 { 3882 /* vshr */, ARM::VSHRsv2i64, Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_ShrImm64 }, }, 15146 { 3882 /* vshr */, ARM::VSHRsv1i64, Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_ShrImm64 }, }, 15147 { 3882 /* vshr */, ARM::VSHRsv16i8, Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_ShrImm8 }, }, 15148 { 3882 /* vshr */, ARM::VSHRsv8i8, Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_ShrImm8 }, }, 15149 { 3882 /* vshr */, ARM::VSHRuv8i16, Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_ShrImm16 }, }, 15150 { 3882 /* vshr */, ARM::VSHRuv4i16, Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_ShrImm16 }, }, 15151 { 3882 /* vshr */, ARM::VSHRuv4i32, Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_ShrImm32 }, }, 15152 { 3882 /* vshr */, ARM::VSHRuv2i32, Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_ShrImm32 }, }, 15153 { 3882 /* vshr */, ARM::VSHRuv2i64, Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_ShrImm64 }, }, 15154 { 3882 /* vshr */, ARM::VSHRuv1i64, Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_ShrImm64 }, }, 15155 { 3882 /* vshr */, ARM::VSHRuv16i8, Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_ShrImm8 }, }, 15156 { 3882 /* vshr */, ARM::VSHRuv8i8, Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_ShrImm8 }, }, 15157 { 3882 /* vshr */, ARM::VSHRsv8i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_ShrImm16 }, }, 15158 { 3882 /* vshr */, ARM::VSHRsv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_ShrImm16 }, }, 15159 { 3882 /* vshr */, ARM::VSHRsv4i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_ShrImm32 }, }, 15160 { 3882 /* vshr */, ARM::VSHRsv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_ShrImm32 }, }, 15161 { 3882 /* vshr */, ARM::VSHRsv2i64, Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_ShrImm64 }, }, 15162 { 3882 /* vshr */, ARM::VSHRsv1i64, Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_ShrImm64 }, }, 15163 { 3882 /* vshr */, ARM::VSHRsv16i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_ShrImm8 }, }, 15164 { 3882 /* vshr */, ARM::VSHRsv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_ShrImm8 }, }, 15165 { 3882 /* vshr */, ARM::VSHRuv8i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_ShrImm16 }, }, 15166 { 3882 /* vshr */, ARM::VSHRuv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_ShrImm16 }, }, 15167 { 3882 /* vshr */, ARM::VSHRuv4i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_ShrImm32 }, }, 15168 { 3882 /* vshr */, ARM::VSHRuv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_ShrImm32 }, }, 15169 { 3882 /* vshr */, ARM::VSHRuv2i64, Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_ShrImm64 }, }, 15170 { 3882 /* vshr */, ARM::VSHRuv1i64, Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_ShrImm64 }, }, 15171 { 3882 /* vshr */, ARM::VSHRuv16i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_ShrImm8 }, }, 15172 { 3882 /* vshr */, ARM::VSHRuv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_ShrImm8 }, }, 15173 { 3882 /* vshr */, ARM::MVE_VSHR_imms16, Convert__Reg1_2__Reg1_3__ShrImm161_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, }, 15174 { 3882 /* vshr */, ARM::MVE_VSHR_imms32, Convert__Reg1_2__Reg1_3__ShrImm321_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm32 }, }, 15175 { 3882 /* vshr */, ARM::MVE_VSHR_imms8, Convert__Reg1_2__Reg1_3__ShrImm81_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, }, 15176 { 3882 /* vshr */, ARM::MVE_VSHR_immu16, Convert__Reg1_2__Reg1_3__ShrImm161_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, }, 15177 { 3882 /* vshr */, ARM::MVE_VSHR_immu32, Convert__Reg1_2__Reg1_3__ShrImm321_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_ShrImm32 }, }, 15178 { 3882 /* vshr */, ARM::MVE_VSHR_immu8, Convert__Reg1_2__Reg1_3__ShrImm81_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, }, 15179 { 3887 /* vshrn */, ARM::VSHRNv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_QPR, MCK_ShrImm8 }, }, 15180 { 3887 /* vshrn */, ARM::VSHRNv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_QPR, MCK_ShrImm16 }, }, 15181 { 3887 /* vshrn */, ARM::VSHRNv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_QPR, MCK_ShrImm32 }, }, 15182 { 3893 /* vshrnb */, ARM::MVE_VSHRNi16bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, }, 15183 { 3893 /* vshrnb */, ARM::MVE_VSHRNi32bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, }, 15184 { 3900 /* vshrnt */, ARM::MVE_VSHRNi16th, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, }, 15185 { 3900 /* vshrnt */, ARM::MVE_VSHRNi32th, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, }, 15186 { 3907 /* vsli */, ARM::VSLIv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_Imm }, }, 15187 { 3907 /* vsli */, ARM::VSLIv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_Imm }, }, 15188 { 3907 /* vsli */, ARM::VSLIv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_Imm }, }, 15189 { 3907 /* vsli */, ARM::VSLIv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_Imm }, }, 15190 { 3907 /* vsli */, ARM::VSLIv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_Imm }, }, 15191 { 3907 /* vsli */, ARM::VSLIv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_Imm }, }, 15192 { 3907 /* vsli */, ARM::VSLIv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_Imm }, }, 15193 { 3907 /* vsli */, ARM::VSLIv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_Imm }, }, 15194 { 3907 /* vsli */, ARM::VSLIv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_Imm }, }, 15195 { 3907 /* vsli */, ARM::VSLIv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_Imm }, }, 15196 { 3907 /* vsli */, ARM::VSLIv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_Imm }, }, 15197 { 3907 /* vsli */, ARM::VSLIv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_Imm }, }, 15198 { 3907 /* vsli */, ARM::VSLIv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_Imm }, }, 15199 { 3907 /* vsli */, ARM::VSLIv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR, MCK_Imm }, }, 15200 { 3907 /* vsli */, ARM::VSLIv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_Imm }, }, 15201 { 3907 /* vsli */, ARM::VSLIv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_Imm }, }, 15202 { 3907 /* vsli */, ARM::MVE_VSLIimm16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm0_151_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_16, MCK_MQPR, MCK_MQPR, MCK_Imm0_15 }, }, 15203 { 3907 /* vsli */, ARM::MVE_VSLIimm32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm0_311_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MQPR, MCK_Imm0_31 }, }, 15204 { 3907 /* vsli */, ARM::MVE_VSLIimm8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm0_71_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_8, MCK_MQPR, MCK_MQPR, MCK_Imm0_7 }, }, 15205 { 3912 /* vsmmla */, ARM::VSMMLA, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasMatMulInt8, { MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 15206 { 3919 /* vsqrt */, ARM::VSQRTD, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK_DPR, MCK_DPR }, }, 15207 { 3919 /* vsqrt */, ARM::VSQRTS, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_HPR, MCK_HPR }, }, 15208 { 3919 /* vsqrt */, ARM::VSQRTS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 15209 { 3919 /* vsqrt */, ARM::VSQRTD, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 15210 { 3919 /* vsqrt */, ARM::VSQRTH, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 15211 { 3925 /* vsra */, ARM::VSRAsv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_ShrImm16 }, }, 15212 { 3925 /* vsra */, ARM::VSRAsv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_ShrImm16 }, }, 15213 { 3925 /* vsra */, ARM::VSRAsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_ShrImm32 }, }, 15214 { 3925 /* vsra */, ARM::VSRAsv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_ShrImm32 }, }, 15215 { 3925 /* vsra */, ARM::VSRAsv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_ShrImm64 }, }, 15216 { 3925 /* vsra */, ARM::VSRAsv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_ShrImm64 }, }, 15217 { 3925 /* vsra */, ARM::VSRAsv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_ShrImm8 }, }, 15218 { 3925 /* vsra */, ARM::VSRAsv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_ShrImm8 }, }, 15219 { 3925 /* vsra */, ARM::VSRAuv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_ShrImm16 }, }, 15220 { 3925 /* vsra */, ARM::VSRAuv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_ShrImm16 }, }, 15221 { 3925 /* vsra */, ARM::VSRAuv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_ShrImm32 }, }, 15222 { 3925 /* vsra */, ARM::VSRAuv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_ShrImm32 }, }, 15223 { 3925 /* vsra */, ARM::VSRAuv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_ShrImm64 }, }, 15224 { 3925 /* vsra */, ARM::VSRAuv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_ShrImm64 }, }, 15225 { 3925 /* vsra */, ARM::VSRAuv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_ShrImm8 }, }, 15226 { 3925 /* vsra */, ARM::VSRAuv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_ShrImm8 }, }, 15227 { 3925 /* vsra */, ARM::VSRAsv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_ShrImm16 }, }, 15228 { 3925 /* vsra */, ARM::VSRAsv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_ShrImm16 }, }, 15229 { 3925 /* vsra */, ARM::VSRAsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_ShrImm32 }, }, 15230 { 3925 /* vsra */, ARM::VSRAsv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_ShrImm32 }, }, 15231 { 3925 /* vsra */, ARM::VSRAsv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_ShrImm64 }, }, 15232 { 3925 /* vsra */, ARM::VSRAsv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_ShrImm64 }, }, 15233 { 3925 /* vsra */, ARM::VSRAsv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_ShrImm8 }, }, 15234 { 3925 /* vsra */, ARM::VSRAsv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_ShrImm8 }, }, 15235 { 3925 /* vsra */, ARM::VSRAuv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_ShrImm16 }, }, 15236 { 3925 /* vsra */, ARM::VSRAuv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_ShrImm16 }, }, 15237 { 3925 /* vsra */, ARM::VSRAuv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_ShrImm32 }, }, 15238 { 3925 /* vsra */, ARM::VSRAuv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_ShrImm32 }, }, 15239 { 3925 /* vsra */, ARM::VSRAuv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_ShrImm64 }, }, 15240 { 3925 /* vsra */, ARM::VSRAuv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_ShrImm64 }, }, 15241 { 3925 /* vsra */, ARM::VSRAuv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_ShrImm8 }, }, 15242 { 3925 /* vsra */, ARM::VSRAuv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_ShrImm8 }, }, 15243 { 3930 /* vsri */, ARM::VSRIv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_ShrImm16 }, }, 15244 { 3930 /* vsri */, ARM::VSRIv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_ShrImm16 }, }, 15245 { 3930 /* vsri */, ARM::VSRIv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_ShrImm32 }, }, 15246 { 3930 /* vsri */, ARM::VSRIv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_ShrImm32 }, }, 15247 { 3930 /* vsri */, ARM::VSRIv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_ShrImm64 }, }, 15248 { 3930 /* vsri */, ARM::VSRIv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_ShrImm64 }, }, 15249 { 3930 /* vsri */, ARM::VSRIv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_ShrImm8 }, }, 15250 { 3930 /* vsri */, ARM::VSRIv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_ShrImm8 }, }, 15251 { 3930 /* vsri */, ARM::VSRIv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_ShrImm16 }, }, 15252 { 3930 /* vsri */, ARM::VSRIv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_ShrImm16 }, }, 15253 { 3930 /* vsri */, ARM::VSRIv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_ShrImm32 }, }, 15254 { 3930 /* vsri */, ARM::VSRIv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_ShrImm32 }, }, 15255 { 3930 /* vsri */, ARM::VSRIv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_ShrImm64 }, }, 15256 { 3930 /* vsri */, ARM::VSRIv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR, MCK_ShrImm64 }, }, 15257 { 3930 /* vsri */, ARM::VSRIv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_ShrImm8 }, }, 15258 { 3930 /* vsri */, ARM::VSRIv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_ShrImm8 }, }, 15259 { 3930 /* vsri */, ARM::MVE_VSRIimm16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_16, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, }, 15260 { 3930 /* vsri */, ARM::MVE_VSRIimm32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MQPR, MCK_ShrImm32 }, }, 15261 { 3930 /* vsri */, ARM::MVE_VSRIimm8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_8, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, }, 15262 { 3935 /* vst1 */, ARM::VST1q16, Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128 }, }, 15263 { 3935 /* vst1 */, ARM::VST1d16Q, Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, }, 15264 { 3935 /* vst1 */, ARM::VST1d16, Convert__AlignedMemory642_3__VecListOneD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneD, MCK_AlignedMemory64 }, }, 15265 { 3935 /* vst1 */, ARM::VST1LNdAsm_16, Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneDHWordIndexed, MCK_AlignedMemory16 }, }, 15266 { 3935 /* vst1 */, ARM::VST1d16T, Convert__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64 }, }, 15267 { 3935 /* vst1 */, ARM::VST1q32, Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128 }, }, 15268 { 3935 /* vst1 */, ARM::VST1d32Q, Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, }, 15269 { 3935 /* vst1 */, ARM::VST1d32, Convert__AlignedMemory642_3__VecListOneD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneD, MCK_AlignedMemory64 }, }, 15270 { 3935 /* vst1 */, ARM::VST1LNdAsm_32, Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneDWordIndexed, MCK_AlignedMemory32 }, }, 15271 { 3935 /* vst1 */, ARM::VST1d32T, Convert__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64 }, }, 15272 { 3935 /* vst1 */, ARM::VST1q64, Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListDPair, MCK_AlignedMemory64or128 }, }, 15273 { 3935 /* vst1 */, ARM::VST1d64Q, Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, }, 15274 { 3935 /* vst1 */, ARM::VST1d64, Convert__AlignedMemory642_3__VecListOneD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListOneD, MCK_AlignedMemory64 }, }, 15275 { 3935 /* vst1 */, ARM::VST1d64T, Convert__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListThreeD, MCK_AlignedMemory64 }, }, 15276 { 3935 /* vst1 */, ARM::VST1q8, Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128 }, }, 15277 { 3935 /* vst1 */, ARM::VST1d8Q, Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, }, 15278 { 3935 /* vst1 */, ARM::VST1d8, Convert__AlignedMemory642_3__VecListOneD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneD, MCK_AlignedMemory64 }, }, 15279 { 3935 /* vst1 */, ARM::VST1LNdAsm_8, Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneDByteIndexed, MCK_AlignedMemoryNone }, }, 15280 { 3935 /* vst1 */, ARM::VST1d8T, Convert__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64 }, }, 15281 { 3935 /* vst1 */, ARM::VST1q16wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 15282 { 3935 /* vst1 */, ARM::VST1q16wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, }, 15283 { 3935 /* vst1 */, ARM::VST1d16Qwb_fixed, Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 15284 { 3935 /* vst1 */, ARM::VST1d16Qwb_register, Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 15285 { 3935 /* vst1 */, ARM::VST1d16wb_fixed, Convert__imm_95_0__AlignedMemory642_3__VecListOneD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 15286 { 3935 /* vst1 */, ARM::VST1d16wb_register, Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListOneD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneD, MCK_AlignedMemory64, MCK_rGPR }, }, 15287 { 3935 /* vst1 */, ARM::VST1LNdWB_fixed_Asm_16, Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneDHWordIndexed, MCK_AlignedMemory16, MCK__EXCLAIM_ }, }, 15288 { 3935 /* vst1 */, ARM::VST1LNdWB_register_Asm_16, Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneDHWordIndexed, MCK_AlignedMemory16, MCK_rGPR }, }, 15289 { 3935 /* vst1 */, ARM::VST1d16Twb_fixed, Convert__imm_95_0__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 15290 { 3935 /* vst1 */, ARM::VST1d16Twb_register, Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListThreeD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, }, 15291 { 3935 /* vst1 */, ARM::VST1q32wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 15292 { 3935 /* vst1 */, ARM::VST1q32wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, }, 15293 { 3935 /* vst1 */, ARM::VST1d32Qwb_fixed, Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 15294 { 3935 /* vst1 */, ARM::VST1d32Qwb_register, Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 15295 { 3935 /* vst1 */, ARM::VST1d32wb_fixed, Convert__imm_95_0__AlignedMemory642_3__VecListOneD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 15296 { 3935 /* vst1 */, ARM::VST1d32wb_register, Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListOneD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneD, MCK_AlignedMemory64, MCK_rGPR }, }, 15297 { 3935 /* vst1 */, ARM::VST1LNdWB_fixed_Asm_32, Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneDWordIndexed, MCK_AlignedMemory32, MCK__EXCLAIM_ }, }, 15298 { 3935 /* vst1 */, ARM::VST1LNdWB_register_Asm_32, Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneDWordIndexed, MCK_AlignedMemory32, MCK_rGPR }, }, 15299 { 3935 /* vst1 */, ARM::VST1d32Twb_fixed, Convert__imm_95_0__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 15300 { 3935 /* vst1 */, ARM::VST1d32Twb_register, Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListThreeD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, }, 15301 { 3935 /* vst1 */, ARM::VST1q64wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 15302 { 3935 /* vst1 */, ARM::VST1q64wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, }, 15303 { 3935 /* vst1 */, ARM::VST1d64Qwb_fixed, Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 15304 { 3935 /* vst1 */, ARM::VST1d64Qwb_register, Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 15305 { 3935 /* vst1 */, ARM::VST1d64wb_fixed, Convert__imm_95_0__AlignedMemory642_3__VecListOneD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListOneD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 15306 { 3935 /* vst1 */, ARM::VST1d64wb_register, Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListOneD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListOneD, MCK_AlignedMemory64, MCK_rGPR }, }, 15307 { 3935 /* vst1 */, ARM::VST1d64Twb_fixed, Convert__imm_95_0__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 15308 { 3935 /* vst1 */, ARM::VST1d64Twb_register, Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListThreeD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, }, 15309 { 3935 /* vst1 */, ARM::VST1q8wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 15310 { 3935 /* vst1 */, ARM::VST1q8wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, }, 15311 { 3935 /* vst1 */, ARM::VST1d8Qwb_fixed, Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 15312 { 3935 /* vst1 */, ARM::VST1d8Qwb_register, Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 15313 { 3935 /* vst1 */, ARM::VST1d8wb_fixed, Convert__imm_95_0__AlignedMemory642_3__VecListOneD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 15314 { 3935 /* vst1 */, ARM::VST1d8wb_register, Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListOneD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneD, MCK_AlignedMemory64, MCK_rGPR }, }, 15315 { 3935 /* vst1 */, ARM::VST1LNdWB_fixed_Asm_8, Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneDByteIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, }, 15316 { 3935 /* vst1 */, ARM::VST1LNdWB_register_Asm_8, Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneDByteIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, }, 15317 { 3935 /* vst1 */, ARM::VST1d8Twb_fixed, Convert__imm_95_0__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 15318 { 3935 /* vst1 */, ARM::VST1d8Twb_register, Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListThreeD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, }, 15319 { 3935 /* vst1 */, ARM::VST1LNd16, Convert__AlignedMemory2_8__Reg1_3__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_AlignedMemory }, }, 15320 { 3935 /* vst1 */, ARM::VST1LNd8, Convert__AlignedMemory2_8__Reg1_3__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_AlignedMemory }, }, 15321 { 3935 /* vst1 */, ARM::VST1LNd16_UPD, Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 15322 { 3935 /* vst1 */, ARM::VST1LNd32, Convert__Reg1_8__Imm1_9__Reg1_3__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_GPR, MCK_Imm }, }, 15323 { 3935 /* vst1 */, ARM::VST1LNd8_UPD, Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 15324 { 3935 /* vst1 */, ARM::VST1LNd32_UPD, Convert__imm_95_0__Reg1_8__Imm1_9__Imm1_10__Reg1_3__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_GPR, MCK_Imm, MCK_Imm }, }, 15325 { 3940 /* vst2 */, ARM::VST2d16, Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128 }, }, 15326 { 3940 /* vst2 */, ARM::VST2b16, Convert__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128 }, }, 15327 { 3940 /* vst2 */, ARM::VST2q16, Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, }, 15328 { 3940 /* vst2 */, ARM::VST2LNdAsm_16, Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoDHWordIndexed, MCK_AlignedMemory32 }, }, 15329 { 3940 /* vst2 */, ARM::VST2LNqAsm_16, Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoQHWordIndexed, MCK_AlignedMemory32 }, }, 15330 { 3940 /* vst2 */, ARM::VST2d32, Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128 }, }, 15331 { 3940 /* vst2 */, ARM::VST2b32, Convert__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128 }, }, 15332 { 3940 /* vst2 */, ARM::VST2q32, Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, }, 15333 { 3940 /* vst2 */, ARM::VST2LNdAsm_32, Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoDWordIndexed, MCK_AlignedMemory64 }, }, 15334 { 3940 /* vst2 */, ARM::VST2LNqAsm_32, Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoQWordIndexed, MCK_AlignedMemory64 }, }, 15335 { 3940 /* vst2 */, ARM::VST2d8, Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128 }, }, 15336 { 3940 /* vst2 */, ARM::VST2b8, Convert__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128 }, }, 15337 { 3940 /* vst2 */, ARM::VST2q8, Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, }, 15338 { 3940 /* vst2 */, ARM::VST2LNdAsm_8, Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListTwoDByteIndexed, MCK_AlignedMemory16 }, }, 15339 { 3940 /* vst2 */, ARM::VST2d16wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 15340 { 3940 /* vst2 */, ARM::VST2d16wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, }, 15341 { 3940 /* vst2 */, ARM::VST2b16wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 15342 { 3940 /* vst2 */, ARM::VST2b16wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPairSpaced1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK_rGPR }, }, 15343 { 3940 /* vst2 */, ARM::VST2q16wb_fixed, Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 15344 { 3940 /* vst2 */, ARM::VST2q16wb_register, Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 15345 { 3940 /* vst2 */, ARM::VST2LNdWB_fixed_Asm_16, Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoDHWordIndexed, MCK_AlignedMemory32, MCK__EXCLAIM_ }, }, 15346 { 3940 /* vst2 */, ARM::VST2LNdWB_register_Asm_16, Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoDHWordIndexed, MCK_AlignedMemory32, MCK_rGPR }, }, 15347 { 3940 /* vst2 */, ARM::VST2LNqWB_fixed_Asm_16, Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoQHWordIndexed, MCK_AlignedMemory32, MCK__EXCLAIM_ }, }, 15348 { 3940 /* vst2 */, ARM::VST2LNqWB_register_Asm_16, Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoQHWordIndexed, MCK_AlignedMemory32, MCK_rGPR }, }, 15349 { 3940 /* vst2 */, ARM::VST2d32wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 15350 { 3940 /* vst2 */, ARM::VST2d32wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, }, 15351 { 3940 /* vst2 */, ARM::VST2b32wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 15352 { 3940 /* vst2 */, ARM::VST2b32wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPairSpaced1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK_rGPR }, }, 15353 { 3940 /* vst2 */, ARM::VST2q32wb_fixed, Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 15354 { 3940 /* vst2 */, ARM::VST2q32wb_register, Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 15355 { 3940 /* vst2 */, ARM::VST2LNdWB_fixed_Asm_32, Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoDWordIndexed, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 15356 { 3940 /* vst2 */, ARM::VST2LNdWB_register_Asm_32, Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoDWordIndexed, MCK_AlignedMemory64, MCK_rGPR }, }, 15357 { 3940 /* vst2 */, ARM::VST2LNqWB_fixed_Asm_32, Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoQWordIndexed, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 15358 { 3940 /* vst2 */, ARM::VST2LNqWB_register_Asm_32, Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoQWordIndexed, MCK_AlignedMemory64, MCK_rGPR }, }, 15359 { 3940 /* vst2 */, ARM::VST2d8wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 15360 { 3940 /* vst2 */, ARM::VST2d8wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, }, 15361 { 3940 /* vst2 */, ARM::VST2b8wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 15362 { 3940 /* vst2 */, ARM::VST2b8wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPairSpaced1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK_rGPR }, }, 15363 { 3940 /* vst2 */, ARM::VST2q8wb_fixed, Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 15364 { 3940 /* vst2 */, ARM::VST2q8wb_register, Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 15365 { 3940 /* vst2 */, ARM::VST2LNdWB_fixed_Asm_8, Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListTwoDByteIndexed, MCK_AlignedMemory16, MCK__EXCLAIM_ }, }, 15366 { 3940 /* vst2 */, ARM::VST2LNdWB_register_Asm_8, Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListTwoDByteIndexed, MCK_AlignedMemory16, MCK_rGPR }, }, 15367 { 3945 /* vst20 */, ARM::MVE_VST20_16, Convert__VecListTwoMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListTwoMQ, MCK_MemNoOffsetT2 }, }, 15368 { 3945 /* vst20 */, ARM::MVE_VST20_32, Convert__VecListTwoMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListTwoMQ, MCK_MemNoOffsetT2 }, }, 15369 { 3945 /* vst20 */, ARM::MVE_VST20_8, Convert__VecListTwoMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListTwoMQ, MCK_MemNoOffsetT2 }, }, 15370 { 3945 /* vst20 */, ARM::MVE_VST20_16_wb, Convert__MemNoOffsetT2NoSp1_2__VecListTwoMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 15371 { 3945 /* vst20 */, ARM::MVE_VST20_32_wb, Convert__MemNoOffsetT2NoSp1_2__VecListTwoMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 15372 { 3945 /* vst20 */, ARM::MVE_VST20_8_wb, Convert__MemNoOffsetT2NoSp1_2__VecListTwoMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 15373 { 3951 /* vst21 */, ARM::MVE_VST21_16, Convert__VecListTwoMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListTwoMQ, MCK_MemNoOffsetT2 }, }, 15374 { 3951 /* vst21 */, ARM::MVE_VST21_32, Convert__VecListTwoMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListTwoMQ, MCK_MemNoOffsetT2 }, }, 15375 { 3951 /* vst21 */, ARM::MVE_VST21_8, Convert__VecListTwoMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListTwoMQ, MCK_MemNoOffsetT2 }, }, 15376 { 3951 /* vst21 */, ARM::MVE_VST21_16_wb, Convert__MemNoOffsetT2NoSp1_2__VecListTwoMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 15377 { 3951 /* vst21 */, ARM::MVE_VST21_32_wb, Convert__MemNoOffsetT2NoSp1_2__VecListTwoMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 15378 { 3951 /* vst21 */, ARM::MVE_VST21_8_wb, Convert__MemNoOffsetT2NoSp1_2__VecListTwoMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 15379 { 3957 /* vst3 */, ARM::VST3dAsm_16, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64 }, }, 15380 { 3957 /* vst3 */, ARM::VST3LNdAsm_16, Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeDHWordIndexed, MCK_AlignedMemoryNone }, }, 15381 { 3957 /* vst3 */, ARM::VST3qAsm_16, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQ, MCK_AlignedMemory64 }, }, 15382 { 3957 /* vst3 */, ARM::VST3LNqAsm_16, Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQHWordIndexed, MCK_AlignedMemoryNone }, }, 15383 { 3957 /* vst3 */, ARM::VST3dAsm_32, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64 }, }, 15384 { 3957 /* vst3 */, ARM::VST3LNdAsm_32, Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeDWordIndexed, MCK_AlignedMemoryNone }, }, 15385 { 3957 /* vst3 */, ARM::VST3qAsm_32, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQ, MCK_AlignedMemory64 }, }, 15386 { 3957 /* vst3 */, ARM::VST3LNqAsm_32, Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQWordIndexed, MCK_AlignedMemoryNone }, }, 15387 { 3957 /* vst3 */, ARM::VST3dAsm_8, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64 }, }, 15388 { 3957 /* vst3 */, ARM::VST3LNdAsm_8, Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeDByteIndexed, MCK_AlignedMemoryNone }, }, 15389 { 3957 /* vst3 */, ARM::VST3qAsm_8, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQ, MCK_AlignedMemory64 }, }, 15390 { 3957 /* vst3 */, ARM::VST3dWB_fixed_Asm_16, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 15391 { 3957 /* vst3 */, ARM::VST3dWB_register_Asm_16, Convert__VecListThreeD1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, }, 15392 { 3957 /* vst3 */, ARM::VST3LNdWB_fixed_Asm_16, Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeDHWordIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, }, 15393 { 3957 /* vst3 */, ARM::VST3LNdWB_register_Asm_16, Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeDHWordIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, }, 15394 { 3957 /* vst3 */, ARM::VST3qWB_fixed_Asm_16, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 15395 { 3957 /* vst3 */, ARM::VST3qWB_register_Asm_16, Convert__VecListThreeQ1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK_rGPR }, }, 15396 { 3957 /* vst3 */, ARM::VST3LNqWB_fixed_Asm_16, Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQHWordIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, }, 15397 { 3957 /* vst3 */, ARM::VST3LNqWB_register_Asm_16, Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQHWordIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, }, 15398 { 3957 /* vst3 */, ARM::VST3dWB_fixed_Asm_32, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 15399 { 3957 /* vst3 */, ARM::VST3dWB_register_Asm_32, Convert__VecListThreeD1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, }, 15400 { 3957 /* vst3 */, ARM::VST3LNdWB_fixed_Asm_32, Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeDWordIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, }, 15401 { 3957 /* vst3 */, ARM::VST3LNdWB_register_Asm_32, Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeDWordIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, }, 15402 { 3957 /* vst3 */, ARM::VST3qWB_fixed_Asm_32, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 15403 { 3957 /* vst3 */, ARM::VST3qWB_register_Asm_32, Convert__VecListThreeQ1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK_rGPR }, }, 15404 { 3957 /* vst3 */, ARM::VST3LNqWB_fixed_Asm_32, Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQWordIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, }, 15405 { 3957 /* vst3 */, ARM::VST3LNqWB_register_Asm_32, Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQWordIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, }, 15406 { 3957 /* vst3 */, ARM::VST3dWB_fixed_Asm_8, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 15407 { 3957 /* vst3 */, ARM::VST3dWB_register_Asm_8, Convert__VecListThreeD1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, }, 15408 { 3957 /* vst3 */, ARM::VST3LNdWB_fixed_Asm_8, Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeDByteIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, }, 15409 { 3957 /* vst3 */, ARM::VST3LNdWB_register_Asm_8, Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeDByteIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, }, 15410 { 3957 /* vst3 */, ARM::VST3qWB_fixed_Asm_8, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 15411 { 3957 /* vst3 */, ARM::VST3qWB_register_Asm_8, Convert__VecListThreeQ1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK_rGPR }, }, 15412 { 3957 /* vst3 */, ARM::VST3d16, Convert__AlignedMemory2_7__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 15413 { 3957 /* vst3 */, ARM::VST3q16, Convert__AlignedMemory2_7__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 15414 { 3957 /* vst3 */, ARM::VST3d32, Convert__AlignedMemory2_7__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 15415 { 3957 /* vst3 */, ARM::VST3q32, Convert__AlignedMemory2_7__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 15416 { 3957 /* vst3 */, ARM::VST3d8, Convert__AlignedMemory2_7__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 15417 { 3957 /* vst3 */, ARM::VST3q8, Convert__AlignedMemory2_7__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 15418 { 3957 /* vst3 */, ARM::VST3d16_UPD, Convert__imm_95_0__AlignedMemory2_7__Imm1_8__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 15419 { 3957 /* vst3 */, ARM::VST3q16_UPD, Convert__imm_95_0__AlignedMemory2_7__Imm1_8__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 15420 { 3957 /* vst3 */, ARM::VST3d32_UPD, Convert__imm_95_0__AlignedMemory2_7__Imm1_8__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 15421 { 3957 /* vst3 */, ARM::VST3q32_UPD, Convert__imm_95_0__AlignedMemory2_7__Imm1_8__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 15422 { 3957 /* vst3 */, ARM::VST3d8_UPD, Convert__imm_95_0__AlignedMemory2_7__Imm1_8__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 15423 { 3957 /* vst3 */, ARM::VST3q8_UPD, Convert__imm_95_0__AlignedMemory2_7__Imm1_8__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 15424 { 3962 /* vst4 */, ARM::VST4dAsm_16, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, }, 15425 { 3962 /* vst4 */, ARM::VST4LNdAsm_16, Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDHWordIndexed, MCK_AlignedMemory64 }, }, 15426 { 3962 /* vst4 */, ARM::VST4qAsm_16, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQ, MCK_AlignedMemory64or128or256 }, }, 15427 { 3962 /* vst4 */, ARM::VST4LNqAsm_16, Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQHWordIndexed, MCK_AlignedMemory64 }, }, 15428 { 3962 /* vst4 */, ARM::VST4dAsm_32, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, }, 15429 { 3962 /* vst4 */, ARM::VST4LNdAsm_32, Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDWordIndexed, MCK_AlignedMemory64or128 }, }, 15430 { 3962 /* vst4 */, ARM::VST4qAsm_32, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQ, MCK_AlignedMemory64or128or256 }, }, 15431 { 3962 /* vst4 */, ARM::VST4LNqAsm_32, Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQWordIndexed, MCK_AlignedMemory64or128 }, }, 15432 { 3962 /* vst4 */, ARM::VST4dAsm_8, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, }, 15433 { 3962 /* vst4 */, ARM::VST4LNdAsm_8, Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDByteIndexed, MCK_AlignedMemory32 }, }, 15434 { 3962 /* vst4 */, ARM::VST4qAsm_8, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQ, MCK_AlignedMemory64or128or256 }, }, 15435 { 3962 /* vst4 */, ARM::VST4dWB_fixed_Asm_16, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 15436 { 3962 /* vst4 */, ARM::VST4dWB_register_Asm_16, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 15437 { 3962 /* vst4 */, ARM::VST4LNdWB_fixed_Asm_16, Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDHWordIndexed, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 15438 { 3962 /* vst4 */, ARM::VST4LNdWB_register_Asm_16, Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDHWordIndexed, MCK_AlignedMemory64, MCK_rGPR }, }, 15439 { 3962 /* vst4 */, ARM::VST4qWB_fixed_Asm_16, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 15440 { 3962 /* vst4 */, ARM::VST4qWB_register_Asm_16, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 15441 { 3962 /* vst4 */, ARM::VST4LNqWB_fixed_Asm_16, Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQHWordIndexed, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 15442 { 3962 /* vst4 */, ARM::VST4LNqWB_register_Asm_16, Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQHWordIndexed, MCK_AlignedMemory64, MCK_rGPR }, }, 15443 { 3962 /* vst4 */, ARM::VST4dWB_fixed_Asm_32, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 15444 { 3962 /* vst4 */, ARM::VST4dWB_register_Asm_32, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 15445 { 3962 /* vst4 */, ARM::VST4LNdWB_fixed_Asm_32, Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDWordIndexed, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 15446 { 3962 /* vst4 */, ARM::VST4LNdWB_register_Asm_32, Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDWordIndexed, MCK_AlignedMemory64or128, MCK_rGPR }, }, 15447 { 3962 /* vst4 */, ARM::VST4qWB_fixed_Asm_32, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 15448 { 3962 /* vst4 */, ARM::VST4qWB_register_Asm_32, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 15449 { 3962 /* vst4 */, ARM::VST4LNqWB_fixed_Asm_32, Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQWordIndexed, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 15450 { 3962 /* vst4 */, ARM::VST4LNqWB_register_Asm_32, Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQWordIndexed, MCK_AlignedMemory64or128, MCK_rGPR }, }, 15451 { 3962 /* vst4 */, ARM::VST4dWB_fixed_Asm_8, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 15452 { 3962 /* vst4 */, ARM::VST4dWB_register_Asm_8, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 15453 { 3962 /* vst4 */, ARM::VST4LNdWB_fixed_Asm_8, Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDByteIndexed, MCK_AlignedMemory32, MCK__EXCLAIM_ }, }, 15454 { 3962 /* vst4 */, ARM::VST4LNdWB_register_Asm_8, Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDByteIndexed, MCK_AlignedMemory32, MCK_rGPR }, }, 15455 { 3962 /* vst4 */, ARM::VST4qWB_fixed_Asm_8, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 15456 { 3962 /* vst4 */, ARM::VST4qWB_register_Asm_8, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 15457 { 3962 /* vst4 */, ARM::VST4d16, Convert__AlignedMemory2_8__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 15458 { 3962 /* vst4 */, ARM::VST4q16, Convert__AlignedMemory2_8__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 15459 { 3962 /* vst4 */, ARM::VST4d32, Convert__AlignedMemory2_8__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 15460 { 3962 /* vst4 */, ARM::VST4q32, Convert__AlignedMemory2_8__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 15461 { 3962 /* vst4 */, ARM::VST4d8, Convert__AlignedMemory2_8__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 15462 { 3962 /* vst4 */, ARM::VST4q8, Convert__AlignedMemory2_8__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 15463 { 3962 /* vst4 */, ARM::VST4d16_UPD, Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 15464 { 3962 /* vst4 */, ARM::VST4q16_UPD, Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 15465 { 3962 /* vst4 */, ARM::VST4d32_UPD, Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 15466 { 3962 /* vst4 */, ARM::VST4q32_UPD, Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 15467 { 3962 /* vst4 */, ARM::VST4d8_UPD, Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 15468 { 3962 /* vst4 */, ARM::VST4q8_UPD, Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 15469 { 3967 /* vst40 */, ARM::MVE_VST40_16, Convert__VecListFourMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, }, 15470 { 3967 /* vst40 */, ARM::MVE_VST40_32, Convert__VecListFourMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, }, 15471 { 3967 /* vst40 */, ARM::MVE_VST40_8, Convert__VecListFourMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, }, 15472 { 3967 /* vst40 */, ARM::MVE_VST40_16_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 15473 { 3967 /* vst40 */, ARM::MVE_VST40_32_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 15474 { 3967 /* vst40 */, ARM::MVE_VST40_8_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 15475 { 3973 /* vst41 */, ARM::MVE_VST41_16, Convert__VecListFourMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, }, 15476 { 3973 /* vst41 */, ARM::MVE_VST41_32, Convert__VecListFourMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, }, 15477 { 3973 /* vst41 */, ARM::MVE_VST41_8, Convert__VecListFourMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, }, 15478 { 3973 /* vst41 */, ARM::MVE_VST41_16_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 15479 { 3973 /* vst41 */, ARM::MVE_VST41_32_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 15480 { 3973 /* vst41 */, ARM::MVE_VST41_8_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 15481 { 3979 /* vst42 */, ARM::MVE_VST42_16, Convert__VecListFourMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, }, 15482 { 3979 /* vst42 */, ARM::MVE_VST42_32, Convert__VecListFourMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, }, 15483 { 3979 /* vst42 */, ARM::MVE_VST42_8, Convert__VecListFourMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, }, 15484 { 3979 /* vst42 */, ARM::MVE_VST42_16_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 15485 { 3979 /* vst42 */, ARM::MVE_VST42_32_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 15486 { 3979 /* vst42 */, ARM::MVE_VST42_8_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 15487 { 3985 /* vst43 */, ARM::MVE_VST43_16, Convert__VecListFourMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, }, 15488 { 3985 /* vst43 */, ARM::MVE_VST43_32, Convert__VecListFourMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, }, 15489 { 3985 /* vst43 */, ARM::MVE_VST43_8, Convert__VecListFourMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, }, 15490 { 3985 /* vst43 */, ARM::MVE_VST43_16_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 15491 { 3985 /* vst43 */, ARM::MVE_VST43_32_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 15492 { 3985 /* vst43 */, ARM::MVE_VST43_8_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, }, 15493 { 3991 /* vstmdb */, ARM::VSTMDDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_DPRRegList }, }, 15494 { 3991 /* vstmdb */, ARM::VSTMSDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__SPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_SPRRegList }, }, 15495 { 3998 /* vstmia */, ARM::VSTMDIA, Convert__Reg1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK_DPRRegList }, }, 15496 { 3998 /* vstmia */, ARM::VSTMSIA, Convert__Reg1_1__CondCode2_0__SPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK_SPRRegList }, }, 15497 { 3998 /* vstmia */, ARM::VSTMDIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_DPRRegList }, }, 15498 { 3998 /* vstmia */, ARM::VSTMSIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__SPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_SPRRegList }, }, 15499 { 4005 /* vstr */, ARM::VSTR_FPCXTNS_off, Convert__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTRegs, MCK_MemImm7s4Offset }, }, 15500 { 4005 /* vstr */, ARM::VSTR_FPCXTS_off, Convert__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTS, MCK_MemImm7s4Offset }, }, 15501 { 4005 /* vstr */, ARM::VSTR_FPSCR_off, Convert__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasFPRegs_HasV8_1MMainline, { MCK_CondCode, MCK_FPSCR, MCK_MemImm7s4Offset }, }, 15502 { 4005 /* vstr */, ARM::VSTR_FPSCR_NZCVQC_off, Convert__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasFPRegs_HasV8_1MMainline, { MCK_CondCode, MCK_FPSCR_NZCVQC, MCK_MemImm7s4Offset }, }, 15503 { 4005 /* vstr */, ARM::VSTR_P0_off, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_P0, MCK_MemImm7s4Offset }, }, 15504 { 4005 /* vstr */, ARM::VSTR_VPR_off, Convert__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_VCCR, MCK_MemImm7s4Offset }, }, 15505 { 4005 /* vstr */, ARM::VSTRD, Convert__Reg1_1__AddrMode52_2__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_DPR, MCK_AddrMode5 }, }, 15506 { 4005 /* vstr */, ARM::VSTRS, Convert__Reg1_1__AddrMode52_2__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_HPR, MCK_AddrMode5 }, }, 15507 { 4005 /* vstr */, ARM::VSTRH, Convert__Reg1_2__AddrMode5FP162_3__CondCode2_0, AMFBS_HasFPRegs16, { MCK_CondCode, MCK__DOT_16, MCK_HPR, MCK_AddrMode5FP16 }, }, 15508 { 4005 /* vstr */, ARM::VSTRS, Convert__Reg1_2__AddrMode52_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_32, MCK_HPR, MCK_AddrMode5 }, }, 15509 { 4005 /* vstr */, ARM::VSTRD, Convert__Reg1_2__AddrMode52_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_AddrMode5 }, }, 15510 { 4005 /* vstr */, ARM::VSTR_FPCXTNS_pre, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTRegs, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, }, 15511 { 4005 /* vstr */, ARM::VSTR_FPCXTNS_post, Convert__MemNoOffsetT21_2__Tie0_3_3__Imm7s41_3__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTRegs, MCK_MemNoOffsetT2, MCK_Imm7s4 }, }, 15512 { 4005 /* vstr */, ARM::VSTR_FPCXTS_pre, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTS, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, }, 15513 { 4005 /* vstr */, ARM::VSTR_FPCXTS_post, Convert__MemNoOffsetT21_2__Tie0_3_3__Imm7s41_3__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTS, MCK_MemNoOffsetT2, MCK_Imm7s4 }, }, 15514 { 4005 /* vstr */, ARM::VSTR_FPSCR_pre, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasFPRegs_HasV8_1MMainline, { MCK_CondCode, MCK_FPSCR, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, }, 15515 { 4005 /* vstr */, ARM::VSTR_FPSCR_post, Convert__MemNoOffsetT21_2__Tie0_3_3__Imm7s41_3__CondCode2_0, AMFBS_HasFPRegs_HasV8_1MMainline, { MCK_CondCode, MCK_FPSCR, MCK_MemNoOffsetT2, MCK_Imm7s4 }, }, 15516 { 4005 /* vstr */, ARM::VSTR_FPSCR_NZCVQC_pre, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasFPRegs_HasV8_1MMainline, { MCK_CondCode, MCK_FPSCR_NZCVQC, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, }, 15517 { 4005 /* vstr */, ARM::VSTR_FPSCR_NZCVQC_post, Convert__MemNoOffsetT21_2__Tie0_3_3__Imm7s41_3__CondCode2_0, AMFBS_HasFPRegs_HasV8_1MMainline, { MCK_CondCode, MCK_FPSCR_NZCVQC, MCK_MemNoOffsetT2, MCK_Imm7s4 }, }, 15518 { 4005 /* vstr */, ARM::VSTR_P0_pre, Convert__imm_95_0__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_P0, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, }, 15519 { 4005 /* vstr */, ARM::VSTR_P0_post, Convert__MemNoOffsetT21_2__imm_95_0__Tie0_3_3__Imm7s41_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_P0, MCK_MemNoOffsetT2, MCK_Imm7s4 }, }, 15520 { 4005 /* vstr */, ARM::VSTR_VPR_pre, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_VCCR, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, }, 15521 { 4005 /* vstr */, ARM::VSTR_VPR_post, Convert__MemNoOffsetT21_2__Tie0_3_3__Imm7s41_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_VCCR, MCK_MemNoOffsetT2, MCK_Imm7s4 }, }, 15522 { 4010 /* vstrb */, ARM::MVE_VSTRB16_rq, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_16, MCK_MQPR, MCK_MemRegRQS0Offset }, }, 15523 { 4010 /* vstrb */, ARM::MVE_VSTRB16, Convert__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_16, MCK_MQPR, MCK_TMemImm7Shift0Offset }, }, 15524 { 4010 /* vstrb */, ARM::MVE_VSTRB32_rq, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MemRegRQS0Offset }, }, 15525 { 4010 /* vstrb */, ARM::MVE_VSTRB32, Convert__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_TMemImm7Shift0Offset }, }, 15526 { 4010 /* vstrb */, ARM::MVE_VSTRBU8, Convert__Reg1_2__MemImm7Shift0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_8, MCK_MQPR, MCK_MemImm7Shift0Offset }, }, 15527 { 4010 /* vstrb */, ARM::MVE_VSTRB8_rq, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_8, MCK_MQPR, MCK_MemRegRQS0Offset }, }, 15528 { 4010 /* vstrb */, ARM::MVE_VSTRB16_post, Convert__MemNoOffsetT1_3__Reg1_2__Tie0_4_4__Imm7Shift01_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_16, MCK_MQPR, MCK_MemNoOffsetT, MCK_Imm7Shift0 }, }, 15529 { 4010 /* vstrb */, ARM::MVE_VSTRB16_pre, Convert__imm_95_0__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_16, MCK_MQPR, MCK_TMemImm7Shift0Offset, MCK__EXCLAIM_ }, }, 15530 { 4010 /* vstrb */, ARM::MVE_VSTRB32_post, Convert__MemNoOffsetT1_3__Reg1_2__Tie0_4_4__Imm7Shift01_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MemNoOffsetT, MCK_Imm7Shift0 }, }, 15531 { 4010 /* vstrb */, ARM::MVE_VSTRB32_pre, Convert__imm_95_0__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_TMemImm7Shift0Offset, MCK__EXCLAIM_ }, }, 15532 { 4010 /* vstrb */, ARM::MVE_VSTRBU8_pre, Convert__imm_95_0__Reg1_2__MemImm7Shift0OffsetWB2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_8, MCK_MQPR, MCK_MemImm7Shift0OffsetWB, MCK__EXCLAIM_ }, }, 15533 { 4010 /* vstrb */, ARM::MVE_VSTRBU8_post, Convert__MemNoOffsetT2NoSp1_3__Reg1_2__Tie0_4_4__Imm7Shift01_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_8, MCK_MQPR, MCK_MemNoOffsetT2NoSp, MCK_Imm7Shift0 }, }, 15534 { 4016 /* vstrd */, ARM::MVE_VSTRD64_qi, Convert__Reg1_2__MemRegQS3Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_64, MCK_MQPR, MCK_MemRegQS3Offset }, }, 15535 { 4016 /* vstrd */, ARM::MVE_VSTRD64_rq_u, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_64, MCK_MQPR, MCK_MemRegRQS0Offset }, }, 15536 { 4016 /* vstrd */, ARM::MVE_VSTRD64_rq, Convert__Reg1_2__MemRegRQS3Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_64, MCK_MQPR, MCK_MemRegRQS3Offset }, }, 15537 { 4016 /* vstrd */, ARM::MVE_VSTRD64_qi_pre, Convert__imm_95_0__Reg1_2__MemRegQS3Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_64, MCK_MQPR, MCK_MemRegQS3Offset, MCK__EXCLAIM_ }, }, 15538 { 4022 /* vstrh */, ARM::MVE_VSTRHU16, Convert__Reg1_2__MemImm7Shift1Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_16, MCK_MQPR, MCK_MemImm7Shift1Offset }, }, 15539 { 4022 /* vstrh */, ARM::MVE_VSTRH16_rq_u, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_16, MCK_MQPR, MCK_MemRegRQS0Offset }, }, 15540 { 4022 /* vstrh */, ARM::MVE_VSTRH16_rq, Convert__Reg1_2__MemRegRQS1Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_16, MCK_MQPR, MCK_MemRegRQS1Offset }, }, 15541 { 4022 /* vstrh */, ARM::MVE_VSTRH32_rq_u, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MemRegRQS0Offset }, }, 15542 { 4022 /* vstrh */, ARM::MVE_VSTRH32_rq, Convert__Reg1_2__MemRegRQS1Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MemRegRQS1Offset }, }, 15543 { 4022 /* vstrh */, ARM::MVE_VSTRH32, Convert__Reg1_2__TMemImm7Shift1Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_TMemImm7Shift1Offset }, }, 15544 { 4022 /* vstrh */, ARM::MVE_VSTRHU16_pre, Convert__imm_95_0__Reg1_2__MemImm7Shift1OffsetWB2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_16, MCK_MQPR, MCK_MemImm7Shift1OffsetWB, MCK__EXCLAIM_ }, }, 15545 { 4022 /* vstrh */, ARM::MVE_VSTRHU16_post, Convert__MemNoOffsetT2NoSp1_3__Reg1_2__Tie0_4_4__Imm7Shift11_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_16, MCK_MQPR, MCK_MemNoOffsetT2NoSp, MCK_Imm7Shift1 }, }, 15546 { 4022 /* vstrh */, ARM::MVE_VSTRH32_post, Convert__MemNoOffsetT1_3__Reg1_2__Tie0_4_4__Imm7Shift11_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MemNoOffsetT, MCK_Imm7Shift1 }, }, 15547 { 4022 /* vstrh */, ARM::MVE_VSTRH32_pre, Convert__imm_95_0__Reg1_2__TMemImm7Shift1Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_TMemImm7Shift1Offset, MCK__EXCLAIM_ }, }, 15548 { 4028 /* vstrw */, ARM::MVE_VSTRWU32, Convert__Reg1_2__MemImm7Shift2Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MemImm7Shift2Offset }, }, 15549 { 4028 /* vstrw */, ARM::MVE_VSTRW32_qi, Convert__Reg1_2__MemRegQS2Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MemRegQS2Offset }, }, 15550 { 4028 /* vstrw */, ARM::MVE_VSTRW32_rq_u, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MemRegRQS0Offset }, }, 15551 { 4028 /* vstrw */, ARM::MVE_VSTRW32_rq, Convert__Reg1_2__MemRegRQS2Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MemRegRQS2Offset }, }, 15552 { 4028 /* vstrw */, ARM::MVE_VSTRWU32_pre, Convert__imm_95_0__Reg1_2__MemImm7Shift2OffsetWB2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MemImm7Shift2OffsetWB, MCK__EXCLAIM_ }, }, 15553 { 4028 /* vstrw */, ARM::MVE_VSTRWU32_post, Convert__MemNoOffsetT2NoSp1_3__Reg1_2__Tie0_4_4__Imm7Shift21_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MemNoOffsetT2NoSp, MCK_Imm7Shift2 }, }, 15554 { 4028 /* vstrw */, ARM::MVE_VSTRW32_qi_pre, Convert__imm_95_0__Reg1_2__MemRegQS2Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MemRegQS2Offset, MCK__EXCLAIM_ }, }, 15555 { 4034 /* vsub */, ARM::VSUBfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 15556 { 4034 /* vsub */, ARM::VSUBfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 15557 { 4034 /* vsub */, ARM::VSUBS, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 15558 { 4034 /* vsub */, ARM::VSUBD, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 15559 { 4034 /* vsub */, ARM::VSUBv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR }, }, 15560 { 4034 /* vsub */, ARM::VSUBv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR }, }, 15561 { 4034 /* vsub */, ARM::VSUBv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR }, }, 15562 { 4034 /* vsub */, ARM::VSUBv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR }, }, 15563 { 4034 /* vsub */, ARM::VSUBv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_QPR }, }, 15564 { 4034 /* vsub */, ARM::VSUBv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_DPR }, }, 15565 { 4034 /* vsub */, ARM::VSUBv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR }, }, 15566 { 4034 /* vsub */, ARM::VSUBv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR }, }, 15567 { 4034 /* vsub */, ARM::VSUBhq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 15568 { 4034 /* vsub */, ARM::VSUBhd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 15569 { 4034 /* vsub */, ARM::VSUBH, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 15570 { 4034 /* vsub */, ARM::VSUBfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 15571 { 4034 /* vsub */, ARM::VSUBfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 15572 { 4034 /* vsub */, ARM::VSUBS, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, }, 15573 { 4034 /* vsub */, ARM::VSUBD, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 15574 { 4034 /* vsub */, ARM::VSUBv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 15575 { 4034 /* vsub */, ARM::VSUBv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 15576 { 4034 /* vsub */, ARM::VSUBv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 15577 { 4034 /* vsub */, ARM::VSUBv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 15578 { 4034 /* vsub */, ARM::VSUBv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_QPR, MCK_QPR }, }, 15579 { 4034 /* vsub */, ARM::VSUBv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 15580 { 4034 /* vsub */, ARM::VSUBv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 15581 { 4034 /* vsub */, ARM::VSUBv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 15582 { 4034 /* vsub */, ARM::VSUBhq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 15583 { 4034 /* vsub */, ARM::VSUBhd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 15584 { 4034 /* vsub */, ARM::VSUBH, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, }, 15585 { 4034 /* vsub */, ARM::MVE_VSUBf32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 15586 { 4034 /* vsub */, ARM::MVE_VSUB_qr_f32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 15587 { 4034 /* vsub */, ARM::MVE_VSUBi16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 15588 { 4034 /* vsub */, ARM::MVE_VSUB_qr_i16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 15589 { 4034 /* vsub */, ARM::MVE_VSUBi32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 15590 { 4034 /* vsub */, ARM::MVE_VSUB_qr_i32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 15591 { 4034 /* vsub */, ARM::MVE_VSUBi8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 15592 { 4034 /* vsub */, ARM::MVE_VSUB_qr_i8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 15593 { 4034 /* vsub */, ARM::MVE_VSUBf16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, }, 15594 { 4034 /* vsub */, ARM::MVE_VSUB_qr_f16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, }, 15595 { 4039 /* vsubhn */, ARM::VSUBHNv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_QPR, MCK_QPR }, }, 15596 { 4039 /* vsubhn */, ARM::VSUBHNv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_QPR, MCK_QPR }, }, 15597 { 4039 /* vsubhn */, ARM::VSUBHNv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_QPR, MCK_QPR }, }, 15598 { 4046 /* vsubl */, ARM::VSUBLsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, }, 15599 { 4046 /* vsubl */, ARM::VSUBLsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, }, 15600 { 4046 /* vsubl */, ARM::VSUBLsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR, MCK_DPR }, }, 15601 { 4046 /* vsubl */, ARM::VSUBLuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR }, }, 15602 { 4046 /* vsubl */, ARM::VSUBLuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR }, }, 15603 { 4046 /* vsubl */, ARM::VSUBLuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR, MCK_DPR }, }, 15604 { 4052 /* vsubw */, ARM::VSUBWsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR }, }, 15605 { 4052 /* vsubw */, ARM::VSUBWsv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR }, }, 15606 { 4052 /* vsubw */, ARM::VSUBWsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR }, }, 15607 { 4052 /* vsubw */, ARM::VSUBWuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR }, }, 15608 { 4052 /* vsubw */, ARM::VSUBWuv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR }, }, 15609 { 4052 /* vsubw */, ARM::VSUBWuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR }, }, 15610 { 4052 /* vsubw */, ARM::VSUBWsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_DPR }, }, 15611 { 4052 /* vsubw */, ARM::VSUBWsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_DPR }, }, 15612 { 4052 /* vsubw */, ARM::VSUBWsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_DPR }, }, 15613 { 4052 /* vsubw */, ARM::VSUBWuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_DPR }, }, 15614 { 4052 /* vsubw */, ARM::VSUBWuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_DPR }, }, 15615 { 4052 /* vsubw */, ARM::VSUBWuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_DPR }, }, 15616 { 4058 /* vsudot */, ARM::VSUDOTQI, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4, AMFBS_HasMatMulInt8, { MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 15617 { 4058 /* vsudot */, ARM::VSUDOTDI, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4, AMFBS_HasMatMulInt8, { MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 15618 { 4065 /* vswp */, ARM::VSWPq, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR }, }, 15619 { 4065 /* vswp */, ARM::VSWPd, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR }, }, 15620 { 4065 /* vswp */, ARM::VSWPq, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, }, 15621 { 4065 /* vswp */, ARM::VSWPd, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, }, 15622 { 4065 /* vswp */, ARM::VSWPq, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, }, 15623 { 4065 /* vswp */, ARM::VSWPd, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, }, 15624 { 4065 /* vswp */, ARM::VSWPq, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR }, }, 15625 { 4065 /* vswp */, ARM::VSWPd, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR }, }, 15626 { 4065 /* vswp */, ARM::VSWPq, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, }, 15627 { 4065 /* vswp */, ARM::VSWPd, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, }, 15628 { 4070 /* vtbl */, ARM::VTBL2, Convert__Reg1_2__VecListDPair1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_VecListDPair, MCK_DPR }, }, 15629 { 4070 /* vtbl */, ARM::VTBL4, Convert__Reg1_2__VecListFourD1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_VecListFourD, MCK_DPR }, }, 15630 { 4070 /* vtbl */, ARM::VTBL1, Convert__Reg1_2__VecListOneD1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_VecListOneD, MCK_DPR }, }, 15631 { 4070 /* vtbl */, ARM::VTBL3, Convert__Reg1_2__VecListThreeD1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_VecListThreeD, MCK_DPR }, }, 15632 { 4075 /* vtbx */, ARM::VTBX2, Convert__Reg1_2__Tie0_1_1__VecListDPair1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_VecListDPair, MCK_DPR }, }, 15633 { 4075 /* vtbx */, ARM::VTBX4, Convert__Reg1_2__Tie0_1_1__VecListFourD1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_VecListFourD, MCK_DPR }, }, 15634 { 4075 /* vtbx */, ARM::VTBX1, Convert__Reg1_2__Tie0_1_1__VecListOneD1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_VecListOneD, MCK_DPR }, }, 15635 { 4075 /* vtbx */, ARM::VTBX3, Convert__Reg1_2__Tie0_1_1__VecListThreeD1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_VecListThreeD, MCK_DPR }, }, 15636 { 4080 /* vtrn */, ARM::VTRNq16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, }, 15637 { 4080 /* vtrn */, ARM::VTRNd16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, }, 15638 { 4080 /* vtrn */, ARM::VTRNq32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, }, 15639 { 4080 /* vtrn */, ARM::VTRNd32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, }, 15640 { 4080 /* vtrn */, ARM::VTRNq8, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, }, 15641 { 4080 /* vtrn */, ARM::VTRNd8, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, }, 15642 { 4085 /* vtst */, ARM::VTSTv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, }, 15643 { 4085 /* vtst */, ARM::VTSTv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, }, 15644 { 4085 /* vtst */, ARM::VTSTv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, }, 15645 { 4085 /* vtst */, ARM::VTSTv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, }, 15646 { 4085 /* vtst */, ARM::VTSTv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, }, 15647 { 4085 /* vtst */, ARM::VTSTv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, }, 15648 { 4085 /* vtst */, ARM::VTSTv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 15649 { 4085 /* vtst */, ARM::VTSTv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 15650 { 4085 /* vtst */, ARM::VTSTv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 15651 { 4085 /* vtst */, ARM::VTSTv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 15652 { 4085 /* vtst */, ARM::VTSTv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 15653 { 4085 /* vtst */, ARM::VTSTv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 15654 { 4090 /* vudot */, ARM::VUDOTQ, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasDotProd, { MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 15655 { 4090 /* vudot */, ARM::VUDOTD, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasDotProd, { MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 15656 { 4090 /* vudot */, ARM::VUDOTQI, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4, AMFBS_HasDotProd, { MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 15657 { 4090 /* vudot */, ARM::VUDOTDI, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4, AMFBS_HasDotProd, { MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 15658 { 4096 /* vummla */, ARM::VUMMLA, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasMatMulInt8, { MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 15659 { 4103 /* vusdot */, ARM::VUSDOTQ, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasMatMulInt8, { MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 15660 { 4103 /* vusdot */, ARM::VUSDOTD, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasMatMulInt8, { MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 15661 { 4103 /* vusdot */, ARM::VUSDOTQI, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4, AMFBS_HasMatMulInt8, { MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 15662 { 4103 /* vusdot */, ARM::VUSDOTDI, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4, AMFBS_HasMatMulInt8, { MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 15663 { 4110 /* vusmmla */, ARM::VUSMMLA, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasMatMulInt8, { MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 15664 { 4118 /* vuzp */, ARM::VUZPq16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, }, 15665 { 4118 /* vuzp */, ARM::VUZPd16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, }, 15666 { 4118 /* vuzp */, ARM::VUZPq32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, }, 15667 { 4118 /* vuzp */, ARM::VTRNd32, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, }, 15668 { 4118 /* vuzp */, ARM::VUZPq8, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, }, 15669 { 4118 /* vuzp */, ARM::VUZPd8, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, }, 15670 { 4123 /* vzip */, ARM::VZIPq16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, }, 15671 { 4123 /* vzip */, ARM::VZIPd16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, }, 15672 { 4123 /* vzip */, ARM::VZIPq32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, }, 15673 { 4123 /* vzip */, ARM::VTRNd32, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, }, 15674 { 4123 /* vzip */, ARM::VZIPq8, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, }, 15675 { 4123 /* vzip */, ARM::VZIPd8, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, }, 15676 { 4128 /* wfe */, ARM::HINT, Convert__imm_95_2__CondCode2_0, AMFBS_IsARM_HasV6K, { MCK_CondCode }, }, 15677 { 4128 /* wfe */, ARM::tHINT, Convert__imm_95_2__CondCode2_0, AMFBS_IsThumb_HasV6M, { MCK_CondCode }, }, 15678 { 4128 /* wfe */, ARM::t2HINT, Convert__imm_95_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w }, }, 15679 { 4132 /* wfi */, ARM::HINT, Convert__imm_95_3__CondCode2_0, AMFBS_IsARM_HasV6K, { MCK_CondCode }, }, 15680 { 4132 /* wfi */, ARM::tHINT, Convert__imm_95_3__CondCode2_0, AMFBS_IsThumb_HasV6M, { MCK_CondCode }, }, 15681 { 4132 /* wfi */, ARM::t2HINT, Convert__imm_95_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w }, }, 15682 { 4136 /* wls */, ARM::t2WLS, Convert__Reg1_0__Reg1_1__WLSLabel1_2, AMFBS_IsThumb2_HasV8_1MMainline_HasLOB, { MCK_GPRlr, MCK_rGPR, MCK_WLSLabel }, }, 15683 { 4140 /* wlstp */, ARM::MVE_WLSTP_16, Convert__Reg1_1__Reg1_2__WLSLabel1_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_GPRlr, MCK_rGPR, MCK_WLSLabel }, }, 15684 { 4140 /* wlstp */, ARM::MVE_WLSTP_32, Convert__Reg1_1__Reg1_2__WLSLabel1_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_GPRlr, MCK_rGPR, MCK_WLSLabel }, }, 15685 { 4140 /* wlstp */, ARM::MVE_WLSTP_64, Convert__Reg1_1__Reg1_2__WLSLabel1_3, AMFBS_HasMVEInt, { MCK__DOT_64, MCK_GPRlr, MCK_rGPR, MCK_WLSLabel }, }, 15686 { 4140 /* wlstp */, ARM::MVE_WLSTP_8, Convert__Reg1_1__Reg1_2__WLSLabel1_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_GPRlr, MCK_rGPR, MCK_WLSLabel }, }, 15687 { 4146 /* yield */, ARM::HINT, Convert__imm_95_1__CondCode2_0, AMFBS_IsARM_HasV6K, { MCK_CondCode }, }, 15688 { 4146 /* yield */, ARM::tHINT, Convert__imm_95_1__CondCode2_0, AMFBS_IsThumb_HasV6M, { MCK_CondCode }, }, 15689 { 4146 /* yield */, ARM::t2HINT, Convert__imm_95_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w }, }, 15690}; 15691 15692#include "llvm/Support/Debug.h" 15693#include "llvm/Support/Format.h" 15694 15695unsigned ARMAsmParser:: 15696MatchInstructionImpl(const OperandVector &Operands, 15697 MCInst &Inst, 15698 SmallVectorImpl<NearMissInfo> *NearMisses, 15699 bool matchingInlineAsm, unsigned VariantID) { 15700 // Get the current feature set. 15701 const FeatureBitset &AvailableFeatures = getAvailableFeatures(); 15702 15703 // Get the instruction mnemonic, which is the first token. 15704 StringRef Mnemonic = ((ARMOperand &)*Operands[0]).getToken(); 15705 15706 // Process all MnemonicAliases to remap the mnemonic. 15707 applyMnemonicAliases(Mnemonic, AvailableFeatures, VariantID); 15708 15709 // Find the appropriate table for this asm variant. 15710 const MatchEntry *Start, *End; 15711 switch (VariantID) { 15712 default: llvm_unreachable("invalid variant!"); 15713 case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break; 15714 } 15715 // Search the table. 15716 auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode()); 15717 15718 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "AsmMatcher: found " << 15719 std::distance(MnemonicRange.first, MnemonicRange.second) << 15720 " encodings with mnemonic '" << Mnemonic << "'\n"); 15721 15722 // Return a more specific error code if no mnemonics match. 15723 if (MnemonicRange.first == MnemonicRange.second) 15724 return Match_MnemonicFail; 15725 15726 for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second; 15727 it != ie; ++it) { 15728 const FeatureBitset &RequiredFeatures = FeatureBitsets[it->RequiredFeaturesIdx]; 15729 bool HasRequiredFeatures = 15730 (AvailableFeatures & RequiredFeatures) == RequiredFeatures; 15731 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Trying to match opcode " 15732 << MII.getName(it->Opcode) << "\n"); 15733 // Some state to record ways in which this instruction did not match. 15734 NearMissInfo OperandNearMiss = NearMissInfo::getSuccess(); 15735 NearMissInfo FeaturesNearMiss = NearMissInfo::getSuccess(); 15736 NearMissInfo EarlyPredicateNearMiss = NearMissInfo::getSuccess(); 15737 NearMissInfo LatePredicateNearMiss = NearMissInfo::getSuccess(); 15738 bool MultipleInvalidOperands = false; 15739 // equal_range guarantees that instruction mnemonic matches. 15740 assert(Mnemonic == it->getMnemonic()); 15741 for (unsigned FormalIdx = 0, ActualIdx = 1; FormalIdx != 18; ++FormalIdx) { 15742 auto Formal = static_cast<MatchClassKind>(it->Classes[FormalIdx]); 15743 DEBUG_WITH_TYPE("asm-matcher", 15744 dbgs() << " Matching formal operand class " << getMatchClassName(Formal) 15745 << " against actual operand at index " << ActualIdx); 15746 if (ActualIdx < Operands.size()) 15747 DEBUG_WITH_TYPE("asm-matcher", dbgs() << " ("; 15748 Operands[ActualIdx]->print(dbgs()); dbgs() << "): "); 15749 else 15750 DEBUG_WITH_TYPE("asm-matcher", dbgs() << ": "); 15751 if (ActualIdx >= Operands.size()) { 15752 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "actual operand index out of range\n"); 15753 bool ThisOperandValid = (Formal == InvalidMatchClass) || isSubclass(Formal, OptionalMatchClass); 15754 if (!ThisOperandValid) { 15755 if (!OperandNearMiss) { 15756 // Record info about match failure for later use. 15757 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "recording too-few-operands near miss\n"); 15758 OperandNearMiss = 15759 NearMissInfo::getTooFewOperands(Formal, it->Opcode); 15760 } else if (OperandNearMiss.getKind() != NearMissInfo::NearMissTooFewOperands) { 15761 // If more than one operand is invalid, give up on this match entry. 15762 DEBUG_WITH_TYPE( 15763 "asm-matcher", 15764 dbgs() << "second invalid operand, giving up on this opcode\n"); 15765 MultipleInvalidOperands = true; 15766 break; 15767 } 15768 } else { 15769 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "but formal operand not required\n"); 15770 } 15771 continue; 15772 } 15773 MCParsedAsmOperand &Actual = *Operands[ActualIdx]; 15774 unsigned Diag = validateOperandClass(Actual, Formal); 15775 if (Diag == Match_Success) { 15776 DEBUG_WITH_TYPE("asm-matcher", 15777 dbgs() << "match success using generic matcher\n"); 15778 ++ActualIdx; 15779 continue; 15780 } 15781 // If the generic handler indicates an invalid operand 15782 // failure, check for a special case. 15783 if (Diag != Match_Success) { 15784 unsigned TargetDiag = validateTargetOperandClass(Actual, Formal); 15785 if (TargetDiag == Match_Success) { 15786 DEBUG_WITH_TYPE("asm-matcher", 15787 dbgs() << "match success using target matcher\n"); 15788 ++ActualIdx; 15789 continue; 15790 } 15791 // If the target matcher returned a specific error code use 15792 // that, else use the one from the generic matcher. 15793 if (TargetDiag != Match_InvalidOperand && HasRequiredFeatures) 15794 Diag = TargetDiag; 15795 } 15796 // If current formal operand wasn't matched and it is optional 15797 // then try to match next formal operand 15798 if (Diag == Match_InvalidOperand && isSubclass(Formal, OptionalMatchClass)) { 15799 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "ignoring optional operand\n"); 15800 continue; 15801 } 15802 if (!OperandNearMiss) { 15803 // If this is the first invalid operand we have seen, record some 15804 // information about it. 15805 DEBUG_WITH_TYPE( 15806 "asm-matcher", 15807 dbgs() 15808 << "operand match failed, recording near-miss with diag code " 15809 << Diag << "\n"); 15810 OperandNearMiss = 15811 NearMissInfo::getMissedOperand(Diag, Formal, it->Opcode, ActualIdx); 15812 ++ActualIdx; 15813 } else { 15814 // If more than one operand is invalid, give up on this match entry. 15815 DEBUG_WITH_TYPE( 15816 "asm-matcher", 15817 dbgs() << "second operand mismatch, skipping this opcode\n"); 15818 MultipleInvalidOperands = true; 15819 break; 15820 } 15821 } 15822 15823 if (MultipleInvalidOperands) { 15824 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Opcode result: multiple " 15825 "operand mismatches, ignoring " 15826 "this opcode\n"); 15827 continue; 15828 } 15829 if (!HasRequiredFeatures) { 15830 FeatureBitset NewMissingFeatures = RequiredFeatures & ~AvailableFeatures; 15831 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Missing target features:"; 15832 for (unsigned I = 0, E = NewMissingFeatures.size(); I != E; ++I) 15833 if (NewMissingFeatures[I]) 15834 dbgs() << ' ' << I; 15835 dbgs() << "\n"); 15836 FeaturesNearMiss = NearMissInfo::getMissedFeature(NewMissingFeatures); 15837 } 15838 15839 Inst.clear(); 15840 15841 Inst.setOpcode(it->Opcode); 15842 // We have a potential match but have not rendered the operands. 15843 // Check the target predicate to handle any context sensitive 15844 // constraints. 15845 // For example, Ties that are referenced multiple times must be 15846 // checked here to ensure the input is the same for each match 15847 // constraints. If we leave it any later the ties will have been 15848 // canonicalized 15849 unsigned MatchResult; 15850 if ((MatchResult = checkEarlyTargetMatchPredicate(Inst, Operands)) != Match_Success) { 15851 Inst.clear(); 15852 DEBUG_WITH_TYPE( 15853 "asm-matcher", 15854 dbgs() << "Early target match predicate failed with diag code " 15855 << MatchResult << "\n"); 15856 EarlyPredicateNearMiss = NearMissInfo::getMissedPredicate(MatchResult); 15857 } 15858 15859 // If we did not successfully match the operands, then we can't convert to 15860 // an MCInst, so bail out on this instruction variant now. 15861 if (OperandNearMiss) { 15862 // If the operand mismatch was the only problem, reprrt it as a near-miss. 15863 if (NearMisses && !FeaturesNearMiss && !EarlyPredicateNearMiss) { 15864 DEBUG_WITH_TYPE( 15865 "asm-matcher", 15866 dbgs() 15867 << "Opcode result: one mismatched operand, adding near-miss\n"); 15868 NearMisses->push_back(OperandNearMiss); 15869 } else { 15870 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Opcode result: multiple " 15871 "types of mismatch, so not " 15872 "reporting near-miss\n"); 15873 } 15874 continue; 15875 } 15876 15877 if (matchingInlineAsm) { 15878 convertToMapAndConstraints(it->ConvertFn, Operands); 15879 return Match_Success; 15880 } 15881 15882 // We have selected a definite instruction, convert the parsed 15883 // operands into the appropriate MCInst. 15884 convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands); 15885 15886 // We have a potential match. Check the target predicate to 15887 // handle any context sensitive constraints. 15888 if ((MatchResult = checkTargetMatchPredicate(Inst)) != Match_Success) { 15889 DEBUG_WITH_TYPE("asm-matcher", 15890 dbgs() << "Target match predicate failed with diag code " 15891 << MatchResult << "\n"); 15892 Inst.clear(); 15893 LatePredicateNearMiss = NearMissInfo::getMissedPredicate(MatchResult); 15894 } 15895 15896 int NumNearMisses = ((int)(bool)OperandNearMiss + 15897 (int)(bool)FeaturesNearMiss + 15898 (int)(bool)EarlyPredicateNearMiss + 15899 (int)(bool)LatePredicateNearMiss); 15900 if (NumNearMisses == 1) { 15901 // We had exactly one type of near-miss, so add that to the list. 15902 assert(!OperandNearMiss && "OperandNearMiss was handled earlier"); 15903 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Opcode result: found one type of " 15904 "mismatch, so reporting a " 15905 "near-miss\n"); 15906 if (NearMisses && FeaturesNearMiss) 15907 NearMisses->push_back(FeaturesNearMiss); 15908 else if (NearMisses && EarlyPredicateNearMiss) 15909 NearMisses->push_back(EarlyPredicateNearMiss); 15910 else if (NearMisses && LatePredicateNearMiss) 15911 NearMisses->push_back(LatePredicateNearMiss); 15912 15913 continue; 15914 } else if (NumNearMisses > 1) { 15915 // This instruction missed in more than one way, so ignore it. 15916 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Opcode result: multiple " 15917 "types of mismatch, so not " 15918 "reporting near-miss\n"); 15919 continue; 15920 } 15921 std::string Info; 15922 if (!getParser().getTargetParser().getTargetOptions().MCNoDeprecatedWarn && 15923 MII.getDeprecatedInfo(Inst, getSTI(), Info)) { 15924 SMLoc Loc = ((ARMOperand &)*Operands[0]).getStartLoc(); 15925 getParser().Warning(Loc, Info, std::nullopt); 15926 } 15927 DEBUG_WITH_TYPE( 15928 "asm-matcher", 15929 dbgs() << "Opcode result: complete match, selecting this opcode\n"); 15930 return Match_Success; 15931 } 15932 15933 // No instruction variants matched exactly. 15934 return Match_NearMisses; 15935} 15936 15937namespace { 15938 struct OperandMatchEntry { 15939 uint16_t Mnemonic; 15940 uint8_t OperandMask; 15941 uint16_t Class; 15942 uint8_t RequiredFeaturesIdx; 15943 15944 StringRef getMnemonic() const { 15945 return StringRef(MnemonicTable + Mnemonic + 1, 15946 MnemonicTable[Mnemonic]); 15947 } 15948 }; 15949 15950 // Predicate for searching for an opcode. 15951 struct LessOpcodeOperand { 15952 bool operator()(const OperandMatchEntry &LHS, StringRef RHS) { 15953 return LHS.getMnemonic() < RHS; 15954 } 15955 bool operator()(StringRef LHS, const OperandMatchEntry &RHS) { 15956 return LHS < RHS.getMnemonic(); 15957 } 15958 bool operator()(const OperandMatchEntry &LHS, const OperandMatchEntry &RHS) { 15959 return LHS.getMnemonic() < RHS.getMnemonic(); 15960 } 15961 }; 15962} // end anonymous namespace 15963 15964static const OperandMatchEntry OperandMatchTable[891] = { 15965 /* Operand List Mnemonic, Mask, Operand Class, Features */ 15966 { 10 /* adc */, 8 /* 3 */, MCK_ModImm, AMFBS_IsARM }, 15967 { 10 /* adc */, 16 /* 4 */, MCK_ModImm, AMFBS_IsARM }, 15968 { 14 /* add */, 8 /* 3 */, MCK_ModImm, AMFBS_IsARM }, 15969 { 14 /* add */, 16 /* 4 */, MCK_ModImm, AMFBS_IsARM }, 15970 { 50 /* and */, 8 /* 3 */, MCK_ModImm, AMFBS_IsARM }, 15971 { 50 /* and */, 16 /* 4 */, MCK_ModImm, AMFBS_IsARM }, 15972 { 77 /* bfc */, 4 /* 2 */, MCK_Bitfield, AMFBS_IsThumb2 }, 15973 { 77 /* bfc */, 4 /* 2 */, MCK_Bitfield, AMFBS_IsARM_HasV6T2 }, 15974 { 81 /* bfcsel */, 8 /* 3 */, MCK_CondCodeNoAL, AMFBS_IsThumb2_HasV8_1MMainline_HasLOB }, 15975 { 88 /* bfi */, 8 /* 3 */, MCK_Bitfield, AMFBS_IsThumb2 }, 15976 { 88 /* bfi */, 8 /* 3 */, MCK_Bitfield, AMFBS_IsARM_HasV6T2 }, 15977 { 105 /* bic */, 8 /* 3 */, MCK_ModImm, AMFBS_IsARM }, 15978 { 105 /* bic */, 16 /* 4 */, MCK_ModImm, AMFBS_IsARM }, 15979 { 158 /* cdp */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 }, 15980 { 158 /* cdp */, 56 /* 3, 4, 5 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 }, 15981 { 158 /* cdp */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsThumb2_PreV8 }, 15982 { 158 /* cdp */, 56 /* 3, 4, 5 */, MCK_CoprocReg, AMFBS_IsThumb2_PreV8 }, 15983 { 162 /* cdp2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 }, 15984 { 162 /* cdp2 */, 28 /* 2, 3, 4 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 }, 15985 { 162 /* cdp2 */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsThumb2_PreV8 }, 15986 { 162 /* cdp2 */, 56 /* 3, 4, 5 */, MCK_CoprocReg, AMFBS_IsThumb2_PreV8 }, 15987 { 167 /* cinc */, 4 /* 2 */, MCK_CondCodeNoALInv, AMFBS_HasV8_1MMainline }, 15988 { 172 /* cinv */, 4 /* 2 */, MCK_CondCodeNoALInv, AMFBS_HasV8_1MMainline }, 15989 { 199 /* cmn */, 4 /* 2 */, MCK_ModImm, AMFBS_IsARM }, 15990 { 203 /* cmp */, 4 /* 2 */, MCK_ModImm, AMFBS_IsARM }, 15991 { 207 /* cneg */, 4 /* 2 */, MCK_CondCodeNoALInv, AMFBS_HasV8_1MMainline }, 15992 { 212 /* cps */, 2 /* 1 */, MCK_ProcIFlags, AMFBS_IsARM }, 15993 { 212 /* cps */, 2 /* 1 */, MCK_ProcIFlags, AMFBS_IsThumb }, 15994 { 212 /* cps */, 4 /* 2 */, MCK_ProcIFlags, AMFBS_IsThumb2_IsNotMClass }, 15995 { 212 /* cps */, 2 /* 1 */, MCK_ProcIFlags, AMFBS_IsARM }, 15996 { 212 /* cps */, 2 /* 1 */, MCK_ProcIFlags, AMFBS_IsThumb2_IsNotMClass }, 15997 { 212 /* cps */, 4 /* 2 */, MCK_ProcIFlags, AMFBS_IsThumb2 }, 15998 { 266 /* csel */, 8 /* 3 */, MCK_CondCodeNoAL, AMFBS_HasV8_1MMainline }, 15999 { 271 /* cset */, 2 /* 1 */, MCK_CondCodeNoALInv, AMFBS_HasV8_1MMainline }, 16000 { 276 /* csetm */, 2 /* 1 */, MCK_CondCodeNoALInv, AMFBS_HasV8_1MMainline }, 16001 { 282 /* csinc */, 8 /* 3 */, MCK_CondCodeNoAL, AMFBS_HasV8_1MMainline }, 16002 { 288 /* csinv */, 8 /* 3 */, MCK_CondCodeNoAL, AMFBS_HasV8_1MMainline }, 16003 { 294 /* csneg */, 8 /* 3 */, MCK_CondCodeNoAL, AMFBS_HasV8_1MMainline }, 16004 { 300 /* cx1 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE }, 16005 { 304 /* cx1a */, 2 /* 1 */, MCK_CoprocNum, AMFBS_HasCDE }, 16006 { 309 /* cx1d */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE }, 16007 { 314 /* cx1da */, 2 /* 1 */, MCK_CoprocNum, AMFBS_HasCDE }, 16008 { 320 /* cx2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE }, 16009 { 324 /* cx2a */, 2 /* 1 */, MCK_CoprocNum, AMFBS_HasCDE }, 16010 { 329 /* cx2d */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE }, 16011 { 334 /* cx2da */, 2 /* 1 */, MCK_CoprocNum, AMFBS_HasCDE }, 16012 { 340 /* cx3 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE }, 16013 { 344 /* cx3a */, 2 /* 1 */, MCK_CoprocNum, AMFBS_HasCDE }, 16014 { 349 /* cx3d */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE }, 16015 { 354 /* cx3da */, 2 /* 1 */, MCK_CoprocNum, AMFBS_HasCDE }, 16016 { 396 /* dmb */, 1 /* 0 */, MCK_MemBarrierOpt, AMFBS_IsARM_HasDB }, 16017 { 396 /* dmb */, 2 /* 1 */, MCK_MemBarrierOpt, AMFBS_IsThumb_HasDB }, 16018 { 396 /* dmb */, 4 /* 2 */, MCK_MemBarrierOpt, AMFBS_HasDB }, 16019 { 400 /* dsb */, 1 /* 0 */, MCK_MemBarrierOpt, AMFBS_IsARM_HasDB }, 16020 { 400 /* dsb */, 2 /* 1 */, MCK_MemBarrierOpt, AMFBS_IsThumb_HasDB }, 16021 { 400 /* dsb */, 4 /* 2 */, MCK_MemBarrierOpt, AMFBS_HasDB }, 16022 { 404 /* eor */, 8 /* 3 */, MCK_ModImm, AMFBS_IsARM }, 16023 { 404 /* eor */, 16 /* 4 */, MCK_ModImm, AMFBS_IsARM }, 16024 { 443 /* fconstd */, 4 /* 2 */, MCK_FPImm, AMFBS_HasVFP3 }, 16025 { 451 /* fconsts */, 4 /* 2 */, MCK_FPImm, AMFBS_HasVFP3 }, 16026 { 535 /* isb */, 1 /* 0 */, MCK_InstSyncBarrierOpt, AMFBS_IsARM_HasDB }, 16027 { 535 /* isb */, 2 /* 1 */, MCK_InstSyncBarrierOpt, AMFBS_IsThumb_HasDB }, 16028 { 535 /* isb */, 4 /* 2 */, MCK_MemBarrierOpt, AMFBS_HasDB }, 16029 { 539 /* it */, 2 /* 1 */, MCK_ITCondCode, AMFBS_IsARM }, 16030 { 539 /* it */, 2 /* 1 */, MCK_ITCondCode, AMFBS_IsThumb2 }, 16031 { 588 /* ldc */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM }, 16032 { 588 /* ldc */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsARM }, 16033 { 588 /* ldc */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsThumb2 }, 16034 { 588 /* ldc */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsThumb2 }, 16035 { 588 /* ldc */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM }, 16036 { 588 /* ldc */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsARM }, 16037 { 588 /* ldc */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsThumb2 }, 16038 { 588 /* ldc */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsThumb2 }, 16039 { 588 /* ldc */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM }, 16040 { 588 /* ldc */, 16 /* 4 */, MCK_CoprocOption, AMFBS_IsARM }, 16041 { 588 /* ldc */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsARM }, 16042 { 588 /* ldc */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsThumb2 }, 16043 { 588 /* ldc */, 16 /* 4 */, MCK_CoprocOption, AMFBS_IsThumb2 }, 16044 { 588 /* ldc */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsThumb2 }, 16045 { 588 /* ldc */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM }, 16046 { 588 /* ldc */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsARM }, 16047 { 588 /* ldc */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsThumb2 }, 16048 { 588 /* ldc */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsThumb2 }, 16049 { 592 /* ldc2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 }, 16050 { 592 /* ldc2 */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 }, 16051 { 592 /* ldc2 */, 2 /* 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 }, 16052 { 592 /* ldc2 */, 4 /* 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 }, 16053 { 592 /* ldc2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 }, 16054 { 592 /* ldc2 */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 }, 16055 { 592 /* ldc2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 }, 16056 { 592 /* ldc2 */, 8 /* 3 */, MCK_CoprocOption, AMFBS_IsARM_PreV8 }, 16057 { 592 /* ldc2 */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 }, 16058 { 592 /* ldc2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 }, 16059 { 592 /* ldc2 */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 }, 16060 { 592 /* ldc2 */, 2 /* 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 }, 16061 { 592 /* ldc2 */, 4 /* 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 }, 16062 { 592 /* ldc2 */, 2 /* 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 }, 16063 { 592 /* ldc2 */, 16 /* 4 */, MCK_CoprocOption, AMFBS_PreV8_IsThumb2 }, 16064 { 592 /* ldc2 */, 4 /* 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 }, 16065 { 592 /* ldc2 */, 2 /* 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 }, 16066 { 592 /* ldc2 */, 4 /* 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 }, 16067 { 597 /* ldc2l */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 }, 16068 { 597 /* ldc2l */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 }, 16069 { 597 /* ldc2l */, 2 /* 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 }, 16070 { 597 /* ldc2l */, 4 /* 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 }, 16071 { 597 /* ldc2l */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 }, 16072 { 597 /* ldc2l */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 }, 16073 { 597 /* ldc2l */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 }, 16074 { 597 /* ldc2l */, 8 /* 3 */, MCK_CoprocOption, AMFBS_IsARM_PreV8 }, 16075 { 597 /* ldc2l */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 }, 16076 { 597 /* ldc2l */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 }, 16077 { 597 /* ldc2l */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 }, 16078 { 597 /* ldc2l */, 2 /* 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 }, 16079 { 597 /* ldc2l */, 4 /* 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 }, 16080 { 597 /* ldc2l */, 2 /* 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 }, 16081 { 597 /* ldc2l */, 16 /* 4 */, MCK_CoprocOption, AMFBS_PreV8_IsThumb2 }, 16082 { 597 /* ldc2l */, 4 /* 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 }, 16083 { 597 /* ldc2l */, 2 /* 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 }, 16084 { 597 /* ldc2l */, 4 /* 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 }, 16085 { 603 /* ldcl */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM }, 16086 { 603 /* ldcl */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsARM }, 16087 { 603 /* ldcl */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsThumb2 }, 16088 { 603 /* ldcl */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsThumb2 }, 16089 { 603 /* ldcl */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM }, 16090 { 603 /* ldcl */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsARM }, 16091 { 603 /* ldcl */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsThumb2 }, 16092 { 603 /* ldcl */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsThumb2 }, 16093 { 603 /* ldcl */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM }, 16094 { 603 /* ldcl */, 16 /* 4 */, MCK_CoprocOption, AMFBS_IsARM }, 16095 { 603 /* ldcl */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsARM }, 16096 { 603 /* ldcl */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsThumb2 }, 16097 { 603 /* ldcl */, 16 /* 4 */, MCK_CoprocOption, AMFBS_IsThumb2 }, 16098 { 603 /* ldcl */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsThumb2 }, 16099 { 603 /* ldcl */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM }, 16100 { 603 /* ldcl */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsARM }, 16101 { 603 /* ldcl */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsThumb2 }, 16102 { 603 /* ldcl */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsThumb2 }, 16103 { 630 /* ldr */, 8 /* 3 */, MCK_PostIdxRegShifted, AMFBS_IsARM }, 16104 { 634 /* ldrb */, 8 /* 3 */, MCK_PostIdxRegShifted, AMFBS_IsARM }, 16105 { 639 /* ldrbt */, 8 /* 3 */, MCK_PostIdxRegShifted, AMFBS_IsARM }, 16106 { 645 /* ldrd */, 16 /* 4 */, MCK_AM3Offset, AMFBS_IsARM }, 16107 { 677 /* ldrh */, 8 /* 3 */, MCK_AM3Offset, AMFBS_IsARM }, 16108 { 682 /* ldrht */, 8 /* 3 */, MCK_PostIdxReg, AMFBS_IsARM }, 16109 { 688 /* ldrsb */, 8 /* 3 */, MCK_AM3Offset, AMFBS_IsARM }, 16110 { 694 /* ldrsbt */, 8 /* 3 */, MCK_PostIdxReg, AMFBS_IsARM }, 16111 { 701 /* ldrsh */, 8 /* 3 */, MCK_AM3Offset, AMFBS_IsARM }, 16112 { 707 /* ldrsht */, 8 /* 3 */, MCK_PostIdxReg, AMFBS_IsARM }, 16113 { 714 /* ldrt */, 8 /* 3 */, MCK_PostIdxRegShifted, AMFBS_IsARM }, 16114 { 745 /* mcr */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM }, 16115 { 745 /* mcr */, 48 /* 4, 5 */, MCK_CoprocReg, AMFBS_IsARM }, 16116 { 745 /* mcr */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsThumb2 }, 16117 { 745 /* mcr */, 48 /* 4, 5 */, MCK_CoprocReg, AMFBS_IsThumb2 }, 16118 { 745 /* mcr */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM }, 16119 { 745 /* mcr */, 48 /* 4, 5 */, MCK_CoprocReg, AMFBS_IsARM }, 16120 { 745 /* mcr */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsThumb2 }, 16121 { 745 /* mcr */, 48 /* 4, 5 */, MCK_CoprocReg, AMFBS_IsThumb2 }, 16122 { 749 /* mcr2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM }, 16123 { 749 /* mcr2 */, 24 /* 3, 4 */, MCK_CoprocReg, AMFBS_IsARM }, 16124 { 749 /* mcr2 */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsThumb2 }, 16125 { 749 /* mcr2 */, 48 /* 4, 5 */, MCK_CoprocReg, AMFBS_IsThumb2 }, 16126 { 749 /* mcr2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 }, 16127 { 749 /* mcr2 */, 24 /* 3, 4 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 }, 16128 { 749 /* mcr2 */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsThumb2_PreV8 }, 16129 { 749 /* mcr2 */, 48 /* 4, 5 */, MCK_CoprocReg, AMFBS_IsThumb2_PreV8 }, 16130 { 754 /* mcrr */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM }, 16131 { 754 /* mcrr */, 32 /* 5 */, MCK_CoprocReg, AMFBS_IsARM }, 16132 { 754 /* mcrr */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsThumb2 }, 16133 { 754 /* mcrr */, 32 /* 5 */, MCK_CoprocReg, AMFBS_IsThumb2 }, 16134 { 759 /* mcrr2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 }, 16135 { 759 /* mcrr2 */, 16 /* 4 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 }, 16136 { 759 /* mcrr2 */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsThumb2_PreV8 }, 16137 { 759 /* mcrr2 */, 32 /* 5 */, MCK_CoprocReg, AMFBS_IsThumb2_PreV8 }, 16138 { 773 /* mov */, 8 /* 3 */, MCK_ModImm, AMFBS_IsARM }, 16139 { 792 /* mrc */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM }, 16140 { 792 /* mrc */, 48 /* 4, 5 */, MCK_CoprocReg, AMFBS_IsARM }, 16141 { 792 /* mrc */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsThumb2 }, 16142 { 792 /* mrc */, 48 /* 4, 5 */, MCK_CoprocReg, AMFBS_IsThumb2 }, 16143 { 792 /* mrc */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM }, 16144 { 792 /* mrc */, 48 /* 4, 5 */, MCK_CoprocReg, AMFBS_IsARM }, 16145 { 792 /* mrc */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsThumb2 }, 16146 { 792 /* mrc */, 48 /* 4, 5 */, MCK_CoprocReg, AMFBS_IsThumb2 }, 16147 { 796 /* mrc2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM }, 16148 { 796 /* mrc2 */, 24 /* 3, 4 */, MCK_CoprocReg, AMFBS_IsARM }, 16149 { 796 /* mrc2 */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsThumb2 }, 16150 { 796 /* mrc2 */, 48 /* 4, 5 */, MCK_CoprocReg, AMFBS_IsThumb2 }, 16151 { 796 /* mrc2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 }, 16152 { 796 /* mrc2 */, 24 /* 3, 4 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 }, 16153 { 796 /* mrc2 */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsThumb2_PreV8 }, 16154 { 796 /* mrc2 */, 48 /* 4, 5 */, MCK_CoprocReg, AMFBS_IsThumb2_PreV8 }, 16155 { 801 /* mrrc */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM }, 16156 { 801 /* mrrc */, 32 /* 5 */, MCK_CoprocReg, AMFBS_IsARM }, 16157 { 801 /* mrrc */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsThumb2 }, 16158 { 801 /* mrrc */, 32 /* 5 */, MCK_CoprocReg, AMFBS_IsThumb2 }, 16159 { 806 /* mrrc2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 }, 16160 { 806 /* mrrc2 */, 16 /* 4 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 }, 16161 { 806 /* mrrc2 */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsThumb2_PreV8 }, 16162 { 806 /* mrrc2 */, 32 /* 5 */, MCK_CoprocReg, AMFBS_IsThumb2_PreV8 }, 16163 { 812 /* mrs */, 4 /* 2 */, MCK_BankedReg, AMFBS_IsThumb_HasVirtualization }, 16164 { 812 /* mrs */, 4 /* 2 */, MCK_MSRMask, AMFBS_IsThumb_IsMClass }, 16165 { 812 /* mrs */, 4 /* 2 */, MCK_BankedReg, AMFBS_IsARM_HasVirtualization }, 16166 { 816 /* msr */, 2 /* 1 */, MCK_BankedReg, AMFBS_IsThumb_HasVirtualization }, 16167 { 816 /* msr */, 2 /* 1 */, MCK_BankedReg, AMFBS_IsARM_HasVirtualization }, 16168 { 816 /* msr */, 2 /* 1 */, MCK_MSRMask, AMFBS_IsThumb2_IsNotMClass }, 16169 { 816 /* msr */, 2 /* 1 */, MCK_MSRMask, AMFBS_IsThumb_IsMClass }, 16170 { 816 /* msr */, 2 /* 1 */, MCK_MSRMask, AMFBS_IsARM }, 16171 { 816 /* msr */, 2 /* 1 */, MCK_MSRMask, AMFBS_IsARM }, 16172 { 816 /* msr */, 4 /* 2 */, MCK_ModImm, AMFBS_IsARM }, 16173 { 824 /* mvn */, 8 /* 3 */, MCK_ModImm, AMFBS_IsARM }, 16174 { 840 /* orr */, 8 /* 3 */, MCK_ModImm, AMFBS_IsARM }, 16175 { 840 /* orr */, 16 /* 4 */, MCK_ModImm, AMFBS_IsARM }, 16176 { 860 /* pkhbt */, 16 /* 4 */, MCK_PKHLSLImm, AMFBS_HasDSP_IsThumb2 }, 16177 { 860 /* pkhbt */, 16 /* 4 */, MCK_PKHLSLImm, AMFBS_IsARM_HasV6 }, 16178 { 866 /* pkhtb */, 16 /* 4 */, MCK_PKHASRImm, AMFBS_HasDSP_IsThumb2 }, 16179 { 866 /* pkhtb */, 16 /* 4 */, MCK_PKHASRImm, AMFBS_IsARM_HasV6 }, 16180 { 1011 /* rsb */, 8 /* 3 */, MCK_ModImm, AMFBS_IsARM }, 16181 { 1011 /* rsb */, 16 /* 4 */, MCK_ModImm, AMFBS_IsARM }, 16182 { 1015 /* rsc */, 8 /* 3 */, MCK_ModImm, AMFBS_IsARM }, 16183 { 1015 /* rsc */, 16 /* 4 */, MCK_ModImm, AMFBS_IsARM }, 16184 { 1040 /* sbc */, 8 /* 3 */, MCK_ModImm, AMFBS_IsARM }, 16185 { 1040 /* sbc */, 16 /* 4 */, MCK_ModImm, AMFBS_IsARM }, 16186 { 1058 /* setend */, 1 /* 0 */, MCK_SetEndImm, AMFBS_IsThumb_IsNotMClass }, 16187 { 1058 /* setend */, 1 /* 0 */, MCK_SetEndImm, AMFBS_IsARM }, 16188 { 1521 /* ssat */, 16 /* 4 */, MCK_ShifterImm, AMFBS_IsThumb2 }, 16189 { 1521 /* ssat */, 16 /* 4 */, MCK_ShifterImm, AMFBS_IsARM_HasV6 }, 16190 { 1556 /* stc */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM }, 16191 { 1556 /* stc */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsARM }, 16192 { 1556 /* stc */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsThumb2 }, 16193 { 1556 /* stc */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsThumb2 }, 16194 { 1556 /* stc */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM }, 16195 { 1556 /* stc */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsARM }, 16196 { 1556 /* stc */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsThumb2 }, 16197 { 1556 /* stc */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsThumb2 }, 16198 { 1556 /* stc */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM }, 16199 { 1556 /* stc */, 16 /* 4 */, MCK_CoprocOption, AMFBS_IsARM }, 16200 { 1556 /* stc */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsARM }, 16201 { 1556 /* stc */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsThumb2 }, 16202 { 1556 /* stc */, 16 /* 4 */, MCK_CoprocOption, AMFBS_IsThumb2 }, 16203 { 1556 /* stc */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsThumb2 }, 16204 { 1556 /* stc */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM }, 16205 { 1556 /* stc */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsARM }, 16206 { 1556 /* stc */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsThumb2 }, 16207 { 1556 /* stc */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsThumb2 }, 16208 { 1560 /* stc2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 }, 16209 { 1560 /* stc2 */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 }, 16210 { 1560 /* stc2 */, 2 /* 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 }, 16211 { 1560 /* stc2 */, 4 /* 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 }, 16212 { 1560 /* stc2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 }, 16213 { 1560 /* stc2 */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 }, 16214 { 1560 /* stc2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 }, 16215 { 1560 /* stc2 */, 8 /* 3 */, MCK_CoprocOption, AMFBS_IsARM_PreV8 }, 16216 { 1560 /* stc2 */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 }, 16217 { 1560 /* stc2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 }, 16218 { 1560 /* stc2 */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 }, 16219 { 1560 /* stc2 */, 2 /* 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 }, 16220 { 1560 /* stc2 */, 4 /* 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 }, 16221 { 1560 /* stc2 */, 2 /* 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 }, 16222 { 1560 /* stc2 */, 16 /* 4 */, MCK_CoprocOption, AMFBS_PreV8_IsThumb2 }, 16223 { 1560 /* stc2 */, 4 /* 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 }, 16224 { 1560 /* stc2 */, 2 /* 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 }, 16225 { 1560 /* stc2 */, 4 /* 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 }, 16226 { 1565 /* stc2l */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 }, 16227 { 1565 /* stc2l */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 }, 16228 { 1565 /* stc2l */, 2 /* 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 }, 16229 { 1565 /* stc2l */, 4 /* 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 }, 16230 { 1565 /* stc2l */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 }, 16231 { 1565 /* stc2l */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 }, 16232 { 1565 /* stc2l */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 }, 16233 { 1565 /* stc2l */, 8 /* 3 */, MCK_CoprocOption, AMFBS_IsARM_PreV8 }, 16234 { 1565 /* stc2l */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 }, 16235 { 1565 /* stc2l */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 }, 16236 { 1565 /* stc2l */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 }, 16237 { 1565 /* stc2l */, 2 /* 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 }, 16238 { 1565 /* stc2l */, 4 /* 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 }, 16239 { 1565 /* stc2l */, 2 /* 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 }, 16240 { 1565 /* stc2l */, 16 /* 4 */, MCK_CoprocOption, AMFBS_PreV8_IsThumb2 }, 16241 { 1565 /* stc2l */, 4 /* 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 }, 16242 { 1565 /* stc2l */, 2 /* 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 }, 16243 { 1565 /* stc2l */, 4 /* 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 }, 16244 { 1571 /* stcl */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM }, 16245 { 1571 /* stcl */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsARM }, 16246 { 1571 /* stcl */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsThumb2 }, 16247 { 1571 /* stcl */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsThumb2 }, 16248 { 1571 /* stcl */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM }, 16249 { 1571 /* stcl */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsARM }, 16250 { 1571 /* stcl */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsThumb2 }, 16251 { 1571 /* stcl */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsThumb2 }, 16252 { 1571 /* stcl */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM }, 16253 { 1571 /* stcl */, 16 /* 4 */, MCK_CoprocOption, AMFBS_IsARM }, 16254 { 1571 /* stcl */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsARM }, 16255 { 1571 /* stcl */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsThumb2 }, 16256 { 1571 /* stcl */, 16 /* 4 */, MCK_CoprocOption, AMFBS_IsThumb2 }, 16257 { 1571 /* stcl */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsThumb2 }, 16258 { 1571 /* stcl */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM }, 16259 { 1571 /* stcl */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsARM }, 16260 { 1571 /* stcl */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsThumb2 }, 16261 { 1571 /* stcl */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsThumb2 }, 16262 { 1639 /* str */, 8 /* 3 */, MCK_PostIdxRegShifted, AMFBS_IsARM }, 16263 { 1643 /* strb */, 8 /* 3 */, MCK_PostIdxRegShifted, AMFBS_IsARM }, 16264 { 1648 /* strbt */, 8 /* 3 */, MCK_PostIdxRegShifted, AMFBS_IsARM }, 16265 { 1654 /* strd */, 16 /* 4 */, MCK_AM3Offset, AMFBS_IsARM }, 16266 { 1686 /* strh */, 8 /* 3 */, MCK_AM3Offset, AMFBS_IsARM }, 16267 { 1691 /* strht */, 8 /* 3 */, MCK_PostIdxReg, AMFBS_IsARM }, 16268 { 1697 /* strt */, 8 /* 3 */, MCK_PostIdxRegShifted, AMFBS_IsARM }, 16269 { 1702 /* sub */, 8 /* 3 */, MCK_ModImm, AMFBS_IsARM }, 16270 { 1702 /* sub */, 16 /* 4 */, MCK_ModImm, AMFBS_IsARM }, 16271 { 1729 /* sxtab */, 16 /* 4 */, MCK_RotImm, AMFBS_HasDSP_IsThumb2 }, 16272 { 1729 /* sxtab */, 16 /* 4 */, MCK_RotImm, AMFBS_IsARM_HasV6 }, 16273 { 1735 /* sxtab16 */, 16 /* 4 */, MCK_RotImm, AMFBS_HasDSP_IsThumb2 }, 16274 { 1735 /* sxtab16 */, 16 /* 4 */, MCK_RotImm, AMFBS_IsARM_HasV6 }, 16275 { 1743 /* sxtah */, 16 /* 4 */, MCK_RotImm, AMFBS_HasDSP_IsThumb2 }, 16276 { 1743 /* sxtah */, 16 /* 4 */, MCK_RotImm, AMFBS_IsARM_HasV6 }, 16277 { 1749 /* sxtb */, 8 /* 3 */, MCK_RotImm, AMFBS_IsThumb2 }, 16278 { 1749 /* sxtb */, 8 /* 3 */, MCK_RotImm, AMFBS_IsARM_HasV6 }, 16279 { 1749 /* sxtb */, 16 /* 4 */, MCK_RotImm, AMFBS_IsThumb2 }, 16280 { 1754 /* sxtb16 */, 8 /* 3 */, MCK_RotImm, AMFBS_HasDSP_IsThumb2 }, 16281 { 1754 /* sxtb16 */, 8 /* 3 */, MCK_RotImm, AMFBS_HasDSP_IsThumb2 }, 16282 { 1754 /* sxtb16 */, 8 /* 3 */, MCK_RotImm, AMFBS_IsARM_HasV6 }, 16283 { 1761 /* sxth */, 8 /* 3 */, MCK_RotImm, AMFBS_IsThumb2 }, 16284 { 1761 /* sxth */, 8 /* 3 */, MCK_RotImm, AMFBS_IsARM_HasV6 }, 16285 { 1761 /* sxth */, 16 /* 4 */, MCK_RotImm, AMFBS_IsThumb2 }, 16286 { 1774 /* teq */, 4 /* 2 */, MCK_ModImm, AMFBS_IsARM }, 16287 { 1783 /* tsb */, 1 /* 0 */, MCK_TraceSyncBarrierOpt, AMFBS_IsARM_HasV8_4a }, 16288 { 1783 /* tsb */, 2 /* 1 */, MCK_TraceSyncBarrierOpt, AMFBS_IsThumb_HasV8_4a }, 16289 { 1787 /* tst */, 4 /* 2 */, MCK_ModImm, AMFBS_IsARM }, 16290 { 1995 /* usat */, 16 /* 4 */, MCK_ShifterImm, AMFBS_IsThumb2 }, 16291 { 1995 /* usat */, 16 /* 4 */, MCK_ShifterImm, AMFBS_IsARM_HasV6 }, 16292 { 2025 /* uxtab */, 16 /* 4 */, MCK_RotImm, AMFBS_HasDSP_IsThumb2 }, 16293 { 2025 /* uxtab */, 16 /* 4 */, MCK_RotImm, AMFBS_IsARM_HasV6 }, 16294 { 2031 /* uxtab16 */, 16 /* 4 */, MCK_RotImm, AMFBS_HasDSP_IsThumb2 }, 16295 { 2031 /* uxtab16 */, 16 /* 4 */, MCK_RotImm, AMFBS_IsARM_HasV6 }, 16296 { 2039 /* uxtah */, 16 /* 4 */, MCK_RotImm, AMFBS_HasDSP_IsThumb2 }, 16297 { 2039 /* uxtah */, 16 /* 4 */, MCK_RotImm, AMFBS_IsARM_HasV6 }, 16298 { 2045 /* uxtb */, 8 /* 3 */, MCK_RotImm, AMFBS_IsThumb2 }, 16299 { 2045 /* uxtb */, 8 /* 3 */, MCK_RotImm, AMFBS_IsARM_HasV6 }, 16300 { 2045 /* uxtb */, 16 /* 4 */, MCK_RotImm, AMFBS_IsThumb2 }, 16301 { 2050 /* uxtb16 */, 8 /* 3 */, MCK_RotImm, AMFBS_HasDSP_IsThumb2 }, 16302 { 2050 /* uxtb16 */, 8 /* 3 */, MCK_RotImm, AMFBS_HasDSP_IsThumb2 }, 16303 { 2050 /* uxtb16 */, 8 /* 3 */, MCK_RotImm, AMFBS_IsARM_HasV6 }, 16304 { 2057 /* uxth */, 8 /* 3 */, MCK_RotImm, AMFBS_IsThumb2 }, 16305 { 2057 /* uxth */, 8 /* 3 */, MCK_RotImm, AMFBS_IsARM_HasV6 }, 16306 { 2057 /* uxth */, 16 /* 4 */, MCK_RotImm, AMFBS_IsThumb2 }, 16307 { 2260 /* vcmp */, 4 /* 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt }, 16308 { 2260 /* vcmp */, 4 /* 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt }, 16309 { 2260 /* vcmp */, 4 /* 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt }, 16310 { 2260 /* vcmp */, 4 /* 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt }, 16311 { 2260 /* vcmp */, 4 /* 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt }, 16312 { 2260 /* vcmp */, 4 /* 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt }, 16313 { 2260 /* vcmp */, 4 /* 2 */, MCK_CondCodeRestrictedU, AMFBS_HasMVEInt }, 16314 { 2260 /* vcmp */, 4 /* 2 */, MCK_CondCodeRestrictedU, AMFBS_HasMVEInt }, 16315 { 2260 /* vcmp */, 4 /* 2 */, MCK_CondCodeRestrictedU, AMFBS_HasMVEInt }, 16316 { 2260 /* vcmp */, 4 /* 2 */, MCK_CondCodeRestrictedU, AMFBS_HasMVEInt }, 16317 { 2260 /* vcmp */, 4 /* 2 */, MCK_CondCodeRestrictedU, AMFBS_HasMVEInt }, 16318 { 2260 /* vcmp */, 4 /* 2 */, MCK_CondCodeRestrictedU, AMFBS_HasMVEInt }, 16319 { 2260 /* vcmp */, 4 /* 2 */, MCK_CondCodeRestrictedFP, AMFBS_HasMVEFloat }, 16320 { 2260 /* vcmp */, 4 /* 2 */, MCK_CondCodeRestrictedFP, AMFBS_HasMVEFloat }, 16321 { 2260 /* vcmp */, 4 /* 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt }, 16322 { 2260 /* vcmp */, 4 /* 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt }, 16323 { 2260 /* vcmp */, 4 /* 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt }, 16324 { 2260 /* vcmp */, 4 /* 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt }, 16325 { 2260 /* vcmp */, 4 /* 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt }, 16326 { 2260 /* vcmp */, 4 /* 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt }, 16327 { 2260 /* vcmp */, 4 /* 2 */, MCK_CondCodeRestrictedFP, AMFBS_HasMVEFloat }, 16328 { 2260 /* vcmp */, 4 /* 2 */, MCK_CondCodeRestrictedFP, AMFBS_HasMVEFloat }, 16329 { 2334 /* vcx1 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE_HasFPRegs }, 16330 { 2334 /* vcx1 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE_HasFPRegs }, 16331 { 2334 /* vcx1 */, 2 /* 1 */, MCK_CoprocNum, AMFBS_HasCDE_HasMVEInt }, 16332 { 2339 /* vcx1a */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE_HasFPRegs }, 16333 { 2339 /* vcx1a */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE_HasFPRegs }, 16334 { 2339 /* vcx1a */, 2 /* 1 */, MCK_CoprocNum, AMFBS_HasCDE_HasMVEInt }, 16335 { 2345 /* vcx2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE_HasFPRegs }, 16336 { 2345 /* vcx2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE_HasFPRegs }, 16337 { 2345 /* vcx2 */, 2 /* 1 */, MCK_CoprocNum, AMFBS_HasCDE_HasMVEInt }, 16338 { 2350 /* vcx2a */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE_HasFPRegs }, 16339 { 2350 /* vcx2a */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE_HasFPRegs }, 16340 { 2350 /* vcx2a */, 2 /* 1 */, MCK_CoprocNum, AMFBS_HasCDE_HasMVEInt }, 16341 { 2356 /* vcx3 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE_HasFPRegs }, 16342 { 2356 /* vcx3 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE_HasFPRegs }, 16343 { 2356 /* vcx3 */, 2 /* 1 */, MCK_CoprocNum, AMFBS_HasCDE_HasMVEInt }, 16344 { 2361 /* vcx3a */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE_HasFPRegs }, 16345 { 2361 /* vcx3a */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE_HasFPRegs }, 16346 { 2361 /* vcx3a */, 2 /* 1 */, MCK_CoprocNum, AMFBS_HasCDE_HasMVEInt }, 16347 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON }, 16348 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 16349 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16350 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListOneDAllLanes, AMFBS_HasNEON }, 16351 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListOneD, AMFBS_HasNEON }, 16352 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListOneDHWordIndexed, AMFBS_HasNEON }, 16353 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 16354 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON }, 16355 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 16356 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16357 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListOneDAllLanes, AMFBS_HasNEON }, 16358 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListOneD, AMFBS_HasNEON }, 16359 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListOneDWordIndexed, AMFBS_HasNEON }, 16360 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 16361 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 16362 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16363 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListOneD, AMFBS_HasNEON }, 16364 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 16365 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON }, 16366 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 16367 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16368 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListOneDAllLanes, AMFBS_HasNEON }, 16369 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListOneD, AMFBS_HasNEON }, 16370 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListOneDByteIndexed, AMFBS_HasNEON }, 16371 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 16372 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON }, 16373 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON }, 16374 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 16375 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 16376 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16377 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16378 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListOneDAllLanes, AMFBS_HasNEON }, 16379 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListOneDAllLanes, AMFBS_HasNEON }, 16380 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListOneD, AMFBS_HasNEON }, 16381 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListOneD, AMFBS_HasNEON }, 16382 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListOneDHWordIndexed, AMFBS_HasNEON }, 16383 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListOneDHWordIndexed, AMFBS_HasNEON }, 16384 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 16385 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 16386 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON }, 16387 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON }, 16388 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 16389 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 16390 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16391 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16392 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListOneDAllLanes, AMFBS_HasNEON }, 16393 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListOneDAllLanes, AMFBS_HasNEON }, 16394 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListOneD, AMFBS_HasNEON }, 16395 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListOneD, AMFBS_HasNEON }, 16396 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListOneDWordIndexed, AMFBS_HasNEON }, 16397 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListOneDWordIndexed, AMFBS_HasNEON }, 16398 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 16399 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 16400 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 16401 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 16402 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16403 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16404 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListOneD, AMFBS_HasNEON }, 16405 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListOneD, AMFBS_HasNEON }, 16406 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 16407 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 16408 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON }, 16409 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON }, 16410 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 16411 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 16412 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16413 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16414 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListOneDAllLanes, AMFBS_HasNEON }, 16415 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListOneDAllLanes, AMFBS_HasNEON }, 16416 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListOneD, AMFBS_HasNEON }, 16417 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListOneD, AMFBS_HasNEON }, 16418 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListOneDByteIndexed, AMFBS_HasNEON }, 16419 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListOneDByteIndexed, AMFBS_HasNEON }, 16420 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 16421 { 2500 /* vld1 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 16422 { 2505 /* vld2 */, 4 /* 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON }, 16423 { 2505 /* vld2 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 16424 { 2505 /* vld2 */, 4 /* 2 */, MCK_VecListDPairSpacedAllLanes, AMFBS_HasNEON }, 16425 { 2505 /* vld2 */, 4 /* 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON }, 16426 { 2505 /* vld2 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16427 { 2505 /* vld2 */, 4 /* 2 */, MCK_VecListTwoDHWordIndexed, AMFBS_HasNEON }, 16428 { 2505 /* vld2 */, 4 /* 2 */, MCK_VecListTwoQHWordIndexed, AMFBS_HasNEON }, 16429 { 2505 /* vld2 */, 4 /* 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON }, 16430 { 2505 /* vld2 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 16431 { 2505 /* vld2 */, 4 /* 2 */, MCK_VecListDPairSpacedAllLanes, AMFBS_HasNEON }, 16432 { 2505 /* vld2 */, 4 /* 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON }, 16433 { 2505 /* vld2 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16434 { 2505 /* vld2 */, 4 /* 2 */, MCK_VecListTwoDWordIndexed, AMFBS_HasNEON }, 16435 { 2505 /* vld2 */, 4 /* 2 */, MCK_VecListTwoQWordIndexed, AMFBS_HasNEON }, 16436 { 2505 /* vld2 */, 4 /* 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON }, 16437 { 2505 /* vld2 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 16438 { 2505 /* vld2 */, 4 /* 2 */, MCK_VecListDPairSpacedAllLanes, AMFBS_HasNEON }, 16439 { 2505 /* vld2 */, 4 /* 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON }, 16440 { 2505 /* vld2 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16441 { 2505 /* vld2 */, 4 /* 2 */, MCK_VecListTwoDByteIndexed, AMFBS_HasNEON }, 16442 { 2505 /* vld2 */, 4 /* 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON }, 16443 { 2505 /* vld2 */, 4 /* 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON }, 16444 { 2505 /* vld2 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 16445 { 2505 /* vld2 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 16446 { 2505 /* vld2 */, 4 /* 2 */, MCK_VecListDPairSpacedAllLanes, AMFBS_HasNEON }, 16447 { 2505 /* vld2 */, 4 /* 2 */, MCK_VecListDPairSpacedAllLanes, AMFBS_HasNEON }, 16448 { 2505 /* vld2 */, 4 /* 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON }, 16449 { 2505 /* vld2 */, 4 /* 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON }, 16450 { 2505 /* vld2 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16451 { 2505 /* vld2 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16452 { 2505 /* vld2 */, 4 /* 2 */, MCK_VecListTwoDHWordIndexed, AMFBS_HasNEON }, 16453 { 2505 /* vld2 */, 4 /* 2 */, MCK_VecListTwoDHWordIndexed, AMFBS_HasNEON }, 16454 { 2505 /* vld2 */, 4 /* 2 */, MCK_VecListTwoQHWordIndexed, AMFBS_HasNEON }, 16455 { 2505 /* vld2 */, 4 /* 2 */, MCK_VecListTwoQHWordIndexed, AMFBS_HasNEON }, 16456 { 2505 /* vld2 */, 4 /* 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON }, 16457 { 2505 /* vld2 */, 4 /* 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON }, 16458 { 2505 /* vld2 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 16459 { 2505 /* vld2 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 16460 { 2505 /* vld2 */, 4 /* 2 */, MCK_VecListDPairSpacedAllLanes, AMFBS_HasNEON }, 16461 { 2505 /* vld2 */, 4 /* 2 */, MCK_VecListDPairSpacedAllLanes, AMFBS_HasNEON }, 16462 { 2505 /* vld2 */, 4 /* 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON }, 16463 { 2505 /* vld2 */, 4 /* 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON }, 16464 { 2505 /* vld2 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16465 { 2505 /* vld2 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16466 { 2505 /* vld2 */, 4 /* 2 */, MCK_VecListTwoDWordIndexed, AMFBS_HasNEON }, 16467 { 2505 /* vld2 */, 4 /* 2 */, MCK_VecListTwoDWordIndexed, AMFBS_HasNEON }, 16468 { 2505 /* vld2 */, 4 /* 2 */, MCK_VecListTwoQWordIndexed, AMFBS_HasNEON }, 16469 { 2505 /* vld2 */, 4 /* 2 */, MCK_VecListTwoQWordIndexed, AMFBS_HasNEON }, 16470 { 2505 /* vld2 */, 4 /* 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON }, 16471 { 2505 /* vld2 */, 4 /* 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON }, 16472 { 2505 /* vld2 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 16473 { 2505 /* vld2 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 16474 { 2505 /* vld2 */, 4 /* 2 */, MCK_VecListDPairSpacedAllLanes, AMFBS_HasNEON }, 16475 { 2505 /* vld2 */, 4 /* 2 */, MCK_VecListDPairSpacedAllLanes, AMFBS_HasNEON }, 16476 { 2505 /* vld2 */, 4 /* 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON }, 16477 { 2505 /* vld2 */, 4 /* 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON }, 16478 { 2505 /* vld2 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16479 { 2505 /* vld2 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16480 { 2505 /* vld2 */, 4 /* 2 */, MCK_VecListTwoDByteIndexed, AMFBS_HasNEON }, 16481 { 2505 /* vld2 */, 4 /* 2 */, MCK_VecListTwoDByteIndexed, AMFBS_HasNEON }, 16482 { 2510 /* vld20 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt }, 16483 { 2510 /* vld20 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt }, 16484 { 2510 /* vld20 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt }, 16485 { 2510 /* vld20 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt }, 16486 { 2510 /* vld20 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt }, 16487 { 2510 /* vld20 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt }, 16488 { 2516 /* vld21 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt }, 16489 { 2516 /* vld21 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt }, 16490 { 2516 /* vld21 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt }, 16491 { 2516 /* vld21 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt }, 16492 { 2516 /* vld21 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt }, 16493 { 2516 /* vld21 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt }, 16494 { 2522 /* vld3 */, 4 /* 2 */, MCK_VecListThreeDAllLanes, AMFBS_HasNEON }, 16495 { 2522 /* vld3 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 16496 { 2522 /* vld3 */, 4 /* 2 */, MCK_VecListThreeDHWordIndexed, AMFBS_HasNEON }, 16497 { 2522 /* vld3 */, 4 /* 2 */, MCK_VecListThreeQAllLanes, AMFBS_HasNEON }, 16498 { 2522 /* vld3 */, 4 /* 2 */, MCK_VecListThreeQ, AMFBS_HasNEON }, 16499 { 2522 /* vld3 */, 4 /* 2 */, MCK_VecListThreeQHWordIndexed, AMFBS_HasNEON }, 16500 { 2522 /* vld3 */, 4 /* 2 */, MCK_VecListThreeDAllLanes, AMFBS_HasNEON }, 16501 { 2522 /* vld3 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 16502 { 2522 /* vld3 */, 4 /* 2 */, MCK_VecListThreeDWordIndexed, AMFBS_HasNEON }, 16503 { 2522 /* vld3 */, 4 /* 2 */, MCK_VecListThreeQAllLanes, AMFBS_HasNEON }, 16504 { 2522 /* vld3 */, 4 /* 2 */, MCK_VecListThreeQ, AMFBS_HasNEON }, 16505 { 2522 /* vld3 */, 4 /* 2 */, MCK_VecListThreeQWordIndexed, AMFBS_HasNEON }, 16506 { 2522 /* vld3 */, 4 /* 2 */, MCK_VecListThreeDAllLanes, AMFBS_HasNEON }, 16507 { 2522 /* vld3 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 16508 { 2522 /* vld3 */, 4 /* 2 */, MCK_VecListThreeDByteIndexed, AMFBS_HasNEON }, 16509 { 2522 /* vld3 */, 4 /* 2 */, MCK_VecListThreeQAllLanes, AMFBS_HasNEON }, 16510 { 2522 /* vld3 */, 4 /* 2 */, MCK_VecListThreeQ, AMFBS_HasNEON }, 16511 { 2522 /* vld3 */, 4 /* 2 */, MCK_VecListThreeDAllLanes, AMFBS_HasNEON }, 16512 { 2522 /* vld3 */, 4 /* 2 */, MCK_VecListThreeDAllLanes, AMFBS_HasNEON }, 16513 { 2522 /* vld3 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 16514 { 2522 /* vld3 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 16515 { 2522 /* vld3 */, 4 /* 2 */, MCK_VecListThreeDHWordIndexed, AMFBS_HasNEON }, 16516 { 2522 /* vld3 */, 4 /* 2 */, MCK_VecListThreeDHWordIndexed, AMFBS_HasNEON }, 16517 { 2522 /* vld3 */, 4 /* 2 */, MCK_VecListThreeQAllLanes, AMFBS_HasNEON }, 16518 { 2522 /* vld3 */, 4 /* 2 */, MCK_VecListThreeQAllLanes, AMFBS_HasNEON }, 16519 { 2522 /* vld3 */, 4 /* 2 */, MCK_VecListThreeQ, AMFBS_HasNEON }, 16520 { 2522 /* vld3 */, 4 /* 2 */, MCK_VecListThreeQ, AMFBS_HasNEON }, 16521 { 2522 /* vld3 */, 4 /* 2 */, MCK_VecListThreeQHWordIndexed, AMFBS_HasNEON }, 16522 { 2522 /* vld3 */, 4 /* 2 */, MCK_VecListThreeQHWordIndexed, AMFBS_HasNEON }, 16523 { 2522 /* vld3 */, 4 /* 2 */, MCK_VecListThreeDAllLanes, AMFBS_HasNEON }, 16524 { 2522 /* vld3 */, 4 /* 2 */, MCK_VecListThreeDAllLanes, AMFBS_HasNEON }, 16525 { 2522 /* vld3 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 16526 { 2522 /* vld3 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 16527 { 2522 /* vld3 */, 4 /* 2 */, MCK_VecListThreeDWordIndexed, AMFBS_HasNEON }, 16528 { 2522 /* vld3 */, 4 /* 2 */, MCK_VecListThreeDWordIndexed, AMFBS_HasNEON }, 16529 { 2522 /* vld3 */, 4 /* 2 */, MCK_VecListThreeQAllLanes, AMFBS_HasNEON }, 16530 { 2522 /* vld3 */, 4 /* 2 */, MCK_VecListThreeQAllLanes, AMFBS_HasNEON }, 16531 { 2522 /* vld3 */, 4 /* 2 */, MCK_VecListThreeQ, AMFBS_HasNEON }, 16532 { 2522 /* vld3 */, 4 /* 2 */, MCK_VecListThreeQ, AMFBS_HasNEON }, 16533 { 2522 /* vld3 */, 4 /* 2 */, MCK_VecListThreeQWordIndexed, AMFBS_HasNEON }, 16534 { 2522 /* vld3 */, 4 /* 2 */, MCK_VecListThreeQWordIndexed, AMFBS_HasNEON }, 16535 { 2522 /* vld3 */, 4 /* 2 */, MCK_VecListThreeDAllLanes, AMFBS_HasNEON }, 16536 { 2522 /* vld3 */, 4 /* 2 */, MCK_VecListThreeDAllLanes, AMFBS_HasNEON }, 16537 { 2522 /* vld3 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 16538 { 2522 /* vld3 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 16539 { 2522 /* vld3 */, 4 /* 2 */, MCK_VecListThreeDByteIndexed, AMFBS_HasNEON }, 16540 { 2522 /* vld3 */, 4 /* 2 */, MCK_VecListThreeDByteIndexed, AMFBS_HasNEON }, 16541 { 2522 /* vld3 */, 4 /* 2 */, MCK_VecListThreeQAllLanes, AMFBS_HasNEON }, 16542 { 2522 /* vld3 */, 4 /* 2 */, MCK_VecListThreeQAllLanes, AMFBS_HasNEON }, 16543 { 2522 /* vld3 */, 4 /* 2 */, MCK_VecListThreeQ, AMFBS_HasNEON }, 16544 { 2522 /* vld3 */, 4 /* 2 */, MCK_VecListThreeQ, AMFBS_HasNEON }, 16545 { 2527 /* vld4 */, 4 /* 2 */, MCK_VecListFourDAllLanes, AMFBS_HasNEON }, 16546 { 2527 /* vld4 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16547 { 2527 /* vld4 */, 4 /* 2 */, MCK_VecListFourDHWordIndexed, AMFBS_HasNEON }, 16548 { 2527 /* vld4 */, 4 /* 2 */, MCK_VecListFourQAllLanes, AMFBS_HasNEON }, 16549 { 2527 /* vld4 */, 4 /* 2 */, MCK_VecListFourQ, AMFBS_HasNEON }, 16550 { 2527 /* vld4 */, 4 /* 2 */, MCK_VecListFourQHWordIndexed, AMFBS_HasNEON }, 16551 { 2527 /* vld4 */, 4 /* 2 */, MCK_VecListFourDAllLanes, AMFBS_HasNEON }, 16552 { 2527 /* vld4 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16553 { 2527 /* vld4 */, 4 /* 2 */, MCK_VecListFourDWordIndexed, AMFBS_HasNEON }, 16554 { 2527 /* vld4 */, 4 /* 2 */, MCK_VecListFourQAllLanes, AMFBS_HasNEON }, 16555 { 2527 /* vld4 */, 4 /* 2 */, MCK_VecListFourQ, AMFBS_HasNEON }, 16556 { 2527 /* vld4 */, 4 /* 2 */, MCK_VecListFourQWordIndexed, AMFBS_HasNEON }, 16557 { 2527 /* vld4 */, 4 /* 2 */, MCK_VecListFourDAllLanes, AMFBS_HasNEON }, 16558 { 2527 /* vld4 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16559 { 2527 /* vld4 */, 4 /* 2 */, MCK_VecListFourDByteIndexed, AMFBS_HasNEON }, 16560 { 2527 /* vld4 */, 4 /* 2 */, MCK_VecListFourQAllLanes, AMFBS_HasNEON }, 16561 { 2527 /* vld4 */, 4 /* 2 */, MCK_VecListFourQ, AMFBS_HasNEON }, 16562 { 2527 /* vld4 */, 4 /* 2 */, MCK_VecListFourDAllLanes, AMFBS_HasNEON }, 16563 { 2527 /* vld4 */, 4 /* 2 */, MCK_VecListFourDAllLanes, AMFBS_HasNEON }, 16564 { 2527 /* vld4 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16565 { 2527 /* vld4 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16566 { 2527 /* vld4 */, 4 /* 2 */, MCK_VecListFourDHWordIndexed, AMFBS_HasNEON }, 16567 { 2527 /* vld4 */, 4 /* 2 */, MCK_VecListFourDHWordIndexed, AMFBS_HasNEON }, 16568 { 2527 /* vld4 */, 4 /* 2 */, MCK_VecListFourQAllLanes, AMFBS_HasNEON }, 16569 { 2527 /* vld4 */, 4 /* 2 */, MCK_VecListFourQAllLanes, AMFBS_HasNEON }, 16570 { 2527 /* vld4 */, 4 /* 2 */, MCK_VecListFourQ, AMFBS_HasNEON }, 16571 { 2527 /* vld4 */, 4 /* 2 */, MCK_VecListFourQ, AMFBS_HasNEON }, 16572 { 2527 /* vld4 */, 4 /* 2 */, MCK_VecListFourQHWordIndexed, AMFBS_HasNEON }, 16573 { 2527 /* vld4 */, 4 /* 2 */, MCK_VecListFourQHWordIndexed, AMFBS_HasNEON }, 16574 { 2527 /* vld4 */, 4 /* 2 */, MCK_VecListFourDAllLanes, AMFBS_HasNEON }, 16575 { 2527 /* vld4 */, 4 /* 2 */, MCK_VecListFourDAllLanes, AMFBS_HasNEON }, 16576 { 2527 /* vld4 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16577 { 2527 /* vld4 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16578 { 2527 /* vld4 */, 4 /* 2 */, MCK_VecListFourDWordIndexed, AMFBS_HasNEON }, 16579 { 2527 /* vld4 */, 4 /* 2 */, MCK_VecListFourDWordIndexed, AMFBS_HasNEON }, 16580 { 2527 /* vld4 */, 4 /* 2 */, MCK_VecListFourQAllLanes, AMFBS_HasNEON }, 16581 { 2527 /* vld4 */, 4 /* 2 */, MCK_VecListFourQAllLanes, AMFBS_HasNEON }, 16582 { 2527 /* vld4 */, 4 /* 2 */, MCK_VecListFourQ, AMFBS_HasNEON }, 16583 { 2527 /* vld4 */, 4 /* 2 */, MCK_VecListFourQ, AMFBS_HasNEON }, 16584 { 2527 /* vld4 */, 4 /* 2 */, MCK_VecListFourQWordIndexed, AMFBS_HasNEON }, 16585 { 2527 /* vld4 */, 4 /* 2 */, MCK_VecListFourQWordIndexed, AMFBS_HasNEON }, 16586 { 2527 /* vld4 */, 4 /* 2 */, MCK_VecListFourDAllLanes, AMFBS_HasNEON }, 16587 { 2527 /* vld4 */, 4 /* 2 */, MCK_VecListFourDAllLanes, AMFBS_HasNEON }, 16588 { 2527 /* vld4 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16589 { 2527 /* vld4 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16590 { 2527 /* vld4 */, 4 /* 2 */, MCK_VecListFourDByteIndexed, AMFBS_HasNEON }, 16591 { 2527 /* vld4 */, 4 /* 2 */, MCK_VecListFourDByteIndexed, AMFBS_HasNEON }, 16592 { 2527 /* vld4 */, 4 /* 2 */, MCK_VecListFourQAllLanes, AMFBS_HasNEON }, 16593 { 2527 /* vld4 */, 4 /* 2 */, MCK_VecListFourQAllLanes, AMFBS_HasNEON }, 16594 { 2527 /* vld4 */, 4 /* 2 */, MCK_VecListFourQ, AMFBS_HasNEON }, 16595 { 2527 /* vld4 */, 4 /* 2 */, MCK_VecListFourQ, AMFBS_HasNEON }, 16596 { 2532 /* vld40 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16597 { 2532 /* vld40 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16598 { 2532 /* vld40 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16599 { 2532 /* vld40 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16600 { 2532 /* vld40 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16601 { 2532 /* vld40 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16602 { 2538 /* vld41 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16603 { 2538 /* vld41 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16604 { 2538 /* vld41 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16605 { 2538 /* vld41 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16606 { 2538 /* vld41 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16607 { 2538 /* vld41 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16608 { 2544 /* vld42 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16609 { 2544 /* vld42 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16610 { 2544 /* vld42 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16611 { 2544 /* vld42 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16612 { 2544 /* vld42 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16613 { 2544 /* vld42 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16614 { 2550 /* vld43 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16615 { 2550 /* vld43 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16616 { 2550 /* vld43 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16617 { 2550 /* vld43 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16618 { 2550 /* vld43 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16619 { 2550 /* vld43 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16620 { 2937 /* vmov */, 8 /* 3 */, MCK_FPImm, AMFBS_HasNEON }, 16621 { 2937 /* vmov */, 8 /* 3 */, MCK_FPImm, AMFBS_HasNEON }, 16622 { 2937 /* vmov */, 8 /* 3 */, MCK_FPImm, AMFBS_HasVFP3 }, 16623 { 2937 /* vmov */, 8 /* 3 */, MCK_FPImm, AMFBS_HasVFP3_HasDPVFP }, 16624 { 2937 /* vmov */, 8 /* 3 */, MCK_FPImm, AMFBS_HasFullFP16 }, 16625 { 2937 /* vmov */, 8 /* 3 */, MCK_FPImm, AMFBS_HasMVEInt }, 16626 { 3121 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt }, 16627 { 3121 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt }, 16628 { 3121 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt }, 16629 { 3121 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt }, 16630 { 3121 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt }, 16631 { 3121 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt }, 16632 { 3121 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedU, AMFBS_HasMVEInt }, 16633 { 3121 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedU, AMFBS_HasMVEInt }, 16634 { 3121 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedU, AMFBS_HasMVEInt }, 16635 { 3121 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedU, AMFBS_HasMVEInt }, 16636 { 3121 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedU, AMFBS_HasMVEInt }, 16637 { 3121 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedU, AMFBS_HasMVEInt }, 16638 { 3121 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedFP, AMFBS_HasMVEFloat }, 16639 { 3121 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedFP, AMFBS_HasMVEFloat }, 16640 { 3121 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt }, 16641 { 3121 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt }, 16642 { 3121 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt }, 16643 { 3121 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt }, 16644 { 3121 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt }, 16645 { 3121 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt }, 16646 { 3121 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedFP, AMFBS_HasMVEFloat }, 16647 { 3121 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedFP, AMFBS_HasMVEFloat }, 16648 { 3935 /* vst1 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 16649 { 3935 /* vst1 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16650 { 3935 /* vst1 */, 4 /* 2 */, MCK_VecListOneD, AMFBS_HasNEON }, 16651 { 3935 /* vst1 */, 4 /* 2 */, MCK_VecListOneDHWordIndexed, AMFBS_HasNEON }, 16652 { 3935 /* vst1 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 16653 { 3935 /* vst1 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 16654 { 3935 /* vst1 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16655 { 3935 /* vst1 */, 4 /* 2 */, MCK_VecListOneD, AMFBS_HasNEON }, 16656 { 3935 /* vst1 */, 4 /* 2 */, MCK_VecListOneDWordIndexed, AMFBS_HasNEON }, 16657 { 3935 /* vst1 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 16658 { 3935 /* vst1 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 16659 { 3935 /* vst1 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16660 { 3935 /* vst1 */, 4 /* 2 */, MCK_VecListOneD, AMFBS_HasNEON }, 16661 { 3935 /* vst1 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 16662 { 3935 /* vst1 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 16663 { 3935 /* vst1 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16664 { 3935 /* vst1 */, 4 /* 2 */, MCK_VecListOneD, AMFBS_HasNEON }, 16665 { 3935 /* vst1 */, 4 /* 2 */, MCK_VecListOneDByteIndexed, AMFBS_HasNEON }, 16666 { 3935 /* vst1 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 16667 { 3935 /* vst1 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 16668 { 3935 /* vst1 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 16669 { 3935 /* vst1 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16670 { 3935 /* vst1 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16671 { 3935 /* vst1 */, 4 /* 2 */, MCK_VecListOneD, AMFBS_HasNEON }, 16672 { 3935 /* vst1 */, 4 /* 2 */, MCK_VecListOneD, AMFBS_HasNEON }, 16673 { 3935 /* vst1 */, 4 /* 2 */, MCK_VecListOneDHWordIndexed, AMFBS_HasNEON }, 16674 { 3935 /* vst1 */, 4 /* 2 */, MCK_VecListOneDHWordIndexed, AMFBS_HasNEON }, 16675 { 3935 /* vst1 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 16676 { 3935 /* vst1 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 16677 { 3935 /* vst1 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 16678 { 3935 /* vst1 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 16679 { 3935 /* vst1 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16680 { 3935 /* vst1 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16681 { 3935 /* vst1 */, 4 /* 2 */, MCK_VecListOneD, AMFBS_HasNEON }, 16682 { 3935 /* vst1 */, 4 /* 2 */, MCK_VecListOneD, AMFBS_HasNEON }, 16683 { 3935 /* vst1 */, 4 /* 2 */, MCK_VecListOneDWordIndexed, AMFBS_HasNEON }, 16684 { 3935 /* vst1 */, 4 /* 2 */, MCK_VecListOneDWordIndexed, AMFBS_HasNEON }, 16685 { 3935 /* vst1 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 16686 { 3935 /* vst1 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 16687 { 3935 /* vst1 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 16688 { 3935 /* vst1 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 16689 { 3935 /* vst1 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16690 { 3935 /* vst1 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16691 { 3935 /* vst1 */, 4 /* 2 */, MCK_VecListOneD, AMFBS_HasNEON }, 16692 { 3935 /* vst1 */, 4 /* 2 */, MCK_VecListOneD, AMFBS_HasNEON }, 16693 { 3935 /* vst1 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 16694 { 3935 /* vst1 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 16695 { 3935 /* vst1 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 16696 { 3935 /* vst1 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 16697 { 3935 /* vst1 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16698 { 3935 /* vst1 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16699 { 3935 /* vst1 */, 4 /* 2 */, MCK_VecListOneD, AMFBS_HasNEON }, 16700 { 3935 /* vst1 */, 4 /* 2 */, MCK_VecListOneD, AMFBS_HasNEON }, 16701 { 3935 /* vst1 */, 4 /* 2 */, MCK_VecListOneDByteIndexed, AMFBS_HasNEON }, 16702 { 3935 /* vst1 */, 4 /* 2 */, MCK_VecListOneDByteIndexed, AMFBS_HasNEON }, 16703 { 3935 /* vst1 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 16704 { 3935 /* vst1 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 16705 { 3940 /* vst2 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 16706 { 3940 /* vst2 */, 4 /* 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON }, 16707 { 3940 /* vst2 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16708 { 3940 /* vst2 */, 4 /* 2 */, MCK_VecListTwoDHWordIndexed, AMFBS_HasNEON }, 16709 { 3940 /* vst2 */, 4 /* 2 */, MCK_VecListTwoQHWordIndexed, AMFBS_HasNEON }, 16710 { 3940 /* vst2 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 16711 { 3940 /* vst2 */, 4 /* 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON }, 16712 { 3940 /* vst2 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16713 { 3940 /* vst2 */, 4 /* 2 */, MCK_VecListTwoDWordIndexed, AMFBS_HasNEON }, 16714 { 3940 /* vst2 */, 4 /* 2 */, MCK_VecListTwoQWordIndexed, AMFBS_HasNEON }, 16715 { 3940 /* vst2 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 16716 { 3940 /* vst2 */, 4 /* 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON }, 16717 { 3940 /* vst2 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16718 { 3940 /* vst2 */, 4 /* 2 */, MCK_VecListTwoDByteIndexed, AMFBS_HasNEON }, 16719 { 3940 /* vst2 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 16720 { 3940 /* vst2 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 16721 { 3940 /* vst2 */, 4 /* 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON }, 16722 { 3940 /* vst2 */, 4 /* 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON }, 16723 { 3940 /* vst2 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16724 { 3940 /* vst2 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16725 { 3940 /* vst2 */, 4 /* 2 */, MCK_VecListTwoDHWordIndexed, AMFBS_HasNEON }, 16726 { 3940 /* vst2 */, 4 /* 2 */, MCK_VecListTwoDHWordIndexed, AMFBS_HasNEON }, 16727 { 3940 /* vst2 */, 4 /* 2 */, MCK_VecListTwoQHWordIndexed, AMFBS_HasNEON }, 16728 { 3940 /* vst2 */, 4 /* 2 */, MCK_VecListTwoQHWordIndexed, AMFBS_HasNEON }, 16729 { 3940 /* vst2 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 16730 { 3940 /* vst2 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 16731 { 3940 /* vst2 */, 4 /* 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON }, 16732 { 3940 /* vst2 */, 4 /* 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON }, 16733 { 3940 /* vst2 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16734 { 3940 /* vst2 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16735 { 3940 /* vst2 */, 4 /* 2 */, MCK_VecListTwoDWordIndexed, AMFBS_HasNEON }, 16736 { 3940 /* vst2 */, 4 /* 2 */, MCK_VecListTwoDWordIndexed, AMFBS_HasNEON }, 16737 { 3940 /* vst2 */, 4 /* 2 */, MCK_VecListTwoQWordIndexed, AMFBS_HasNEON }, 16738 { 3940 /* vst2 */, 4 /* 2 */, MCK_VecListTwoQWordIndexed, AMFBS_HasNEON }, 16739 { 3940 /* vst2 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 16740 { 3940 /* vst2 */, 4 /* 2 */, MCK_VecListDPair, AMFBS_HasNEON }, 16741 { 3940 /* vst2 */, 4 /* 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON }, 16742 { 3940 /* vst2 */, 4 /* 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON }, 16743 { 3940 /* vst2 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16744 { 3940 /* vst2 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16745 { 3940 /* vst2 */, 4 /* 2 */, MCK_VecListTwoDByteIndexed, AMFBS_HasNEON }, 16746 { 3940 /* vst2 */, 4 /* 2 */, MCK_VecListTwoDByteIndexed, AMFBS_HasNEON }, 16747 { 3945 /* vst20 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt }, 16748 { 3945 /* vst20 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt }, 16749 { 3945 /* vst20 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt }, 16750 { 3945 /* vst20 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt }, 16751 { 3945 /* vst20 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt }, 16752 { 3945 /* vst20 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt }, 16753 { 3951 /* vst21 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt }, 16754 { 3951 /* vst21 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt }, 16755 { 3951 /* vst21 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt }, 16756 { 3951 /* vst21 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt }, 16757 { 3951 /* vst21 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt }, 16758 { 3951 /* vst21 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt }, 16759 { 3957 /* vst3 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 16760 { 3957 /* vst3 */, 4 /* 2 */, MCK_VecListThreeDHWordIndexed, AMFBS_HasNEON }, 16761 { 3957 /* vst3 */, 4 /* 2 */, MCK_VecListThreeQ, AMFBS_HasNEON }, 16762 { 3957 /* vst3 */, 4 /* 2 */, MCK_VecListThreeQHWordIndexed, AMFBS_HasNEON }, 16763 { 3957 /* vst3 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 16764 { 3957 /* vst3 */, 4 /* 2 */, MCK_VecListThreeDWordIndexed, AMFBS_HasNEON }, 16765 { 3957 /* vst3 */, 4 /* 2 */, MCK_VecListThreeQ, AMFBS_HasNEON }, 16766 { 3957 /* vst3 */, 4 /* 2 */, MCK_VecListThreeQWordIndexed, AMFBS_HasNEON }, 16767 { 3957 /* vst3 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 16768 { 3957 /* vst3 */, 4 /* 2 */, MCK_VecListThreeDByteIndexed, AMFBS_HasNEON }, 16769 { 3957 /* vst3 */, 4 /* 2 */, MCK_VecListThreeQ, AMFBS_HasNEON }, 16770 { 3957 /* vst3 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 16771 { 3957 /* vst3 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 16772 { 3957 /* vst3 */, 4 /* 2 */, MCK_VecListThreeDHWordIndexed, AMFBS_HasNEON }, 16773 { 3957 /* vst3 */, 4 /* 2 */, MCK_VecListThreeDHWordIndexed, AMFBS_HasNEON }, 16774 { 3957 /* vst3 */, 4 /* 2 */, MCK_VecListThreeQ, AMFBS_HasNEON }, 16775 { 3957 /* vst3 */, 4 /* 2 */, MCK_VecListThreeQ, AMFBS_HasNEON }, 16776 { 3957 /* vst3 */, 4 /* 2 */, MCK_VecListThreeQHWordIndexed, AMFBS_HasNEON }, 16777 { 3957 /* vst3 */, 4 /* 2 */, MCK_VecListThreeQHWordIndexed, AMFBS_HasNEON }, 16778 { 3957 /* vst3 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 16779 { 3957 /* vst3 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 16780 { 3957 /* vst3 */, 4 /* 2 */, MCK_VecListThreeDWordIndexed, AMFBS_HasNEON }, 16781 { 3957 /* vst3 */, 4 /* 2 */, MCK_VecListThreeDWordIndexed, AMFBS_HasNEON }, 16782 { 3957 /* vst3 */, 4 /* 2 */, MCK_VecListThreeQ, AMFBS_HasNEON }, 16783 { 3957 /* vst3 */, 4 /* 2 */, MCK_VecListThreeQ, AMFBS_HasNEON }, 16784 { 3957 /* vst3 */, 4 /* 2 */, MCK_VecListThreeQWordIndexed, AMFBS_HasNEON }, 16785 { 3957 /* vst3 */, 4 /* 2 */, MCK_VecListThreeQWordIndexed, AMFBS_HasNEON }, 16786 { 3957 /* vst3 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 16787 { 3957 /* vst3 */, 4 /* 2 */, MCK_VecListThreeD, AMFBS_HasNEON }, 16788 { 3957 /* vst3 */, 4 /* 2 */, MCK_VecListThreeDByteIndexed, AMFBS_HasNEON }, 16789 { 3957 /* vst3 */, 4 /* 2 */, MCK_VecListThreeDByteIndexed, AMFBS_HasNEON }, 16790 { 3957 /* vst3 */, 4 /* 2 */, MCK_VecListThreeQ, AMFBS_HasNEON }, 16791 { 3957 /* vst3 */, 4 /* 2 */, MCK_VecListThreeQ, AMFBS_HasNEON }, 16792 { 3962 /* vst4 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16793 { 3962 /* vst4 */, 4 /* 2 */, MCK_VecListFourDHWordIndexed, AMFBS_HasNEON }, 16794 { 3962 /* vst4 */, 4 /* 2 */, MCK_VecListFourQ, AMFBS_HasNEON }, 16795 { 3962 /* vst4 */, 4 /* 2 */, MCK_VecListFourQHWordIndexed, AMFBS_HasNEON }, 16796 { 3962 /* vst4 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16797 { 3962 /* vst4 */, 4 /* 2 */, MCK_VecListFourDWordIndexed, AMFBS_HasNEON }, 16798 { 3962 /* vst4 */, 4 /* 2 */, MCK_VecListFourQ, AMFBS_HasNEON }, 16799 { 3962 /* vst4 */, 4 /* 2 */, MCK_VecListFourQWordIndexed, AMFBS_HasNEON }, 16800 { 3962 /* vst4 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16801 { 3962 /* vst4 */, 4 /* 2 */, MCK_VecListFourDByteIndexed, AMFBS_HasNEON }, 16802 { 3962 /* vst4 */, 4 /* 2 */, MCK_VecListFourQ, AMFBS_HasNEON }, 16803 { 3962 /* vst4 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16804 { 3962 /* vst4 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16805 { 3962 /* vst4 */, 4 /* 2 */, MCK_VecListFourDHWordIndexed, AMFBS_HasNEON }, 16806 { 3962 /* vst4 */, 4 /* 2 */, MCK_VecListFourDHWordIndexed, AMFBS_HasNEON }, 16807 { 3962 /* vst4 */, 4 /* 2 */, MCK_VecListFourQ, AMFBS_HasNEON }, 16808 { 3962 /* vst4 */, 4 /* 2 */, MCK_VecListFourQ, AMFBS_HasNEON }, 16809 { 3962 /* vst4 */, 4 /* 2 */, MCK_VecListFourQHWordIndexed, AMFBS_HasNEON }, 16810 { 3962 /* vst4 */, 4 /* 2 */, MCK_VecListFourQHWordIndexed, AMFBS_HasNEON }, 16811 { 3962 /* vst4 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16812 { 3962 /* vst4 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16813 { 3962 /* vst4 */, 4 /* 2 */, MCK_VecListFourDWordIndexed, AMFBS_HasNEON }, 16814 { 3962 /* vst4 */, 4 /* 2 */, MCK_VecListFourDWordIndexed, AMFBS_HasNEON }, 16815 { 3962 /* vst4 */, 4 /* 2 */, MCK_VecListFourQ, AMFBS_HasNEON }, 16816 { 3962 /* vst4 */, 4 /* 2 */, MCK_VecListFourQ, AMFBS_HasNEON }, 16817 { 3962 /* vst4 */, 4 /* 2 */, MCK_VecListFourQWordIndexed, AMFBS_HasNEON }, 16818 { 3962 /* vst4 */, 4 /* 2 */, MCK_VecListFourQWordIndexed, AMFBS_HasNEON }, 16819 { 3962 /* vst4 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16820 { 3962 /* vst4 */, 4 /* 2 */, MCK_VecListFourD, AMFBS_HasNEON }, 16821 { 3962 /* vst4 */, 4 /* 2 */, MCK_VecListFourDByteIndexed, AMFBS_HasNEON }, 16822 { 3962 /* vst4 */, 4 /* 2 */, MCK_VecListFourDByteIndexed, AMFBS_HasNEON }, 16823 { 3962 /* vst4 */, 4 /* 2 */, MCK_VecListFourQ, AMFBS_HasNEON }, 16824 { 3962 /* vst4 */, 4 /* 2 */, MCK_VecListFourQ, AMFBS_HasNEON }, 16825 { 3967 /* vst40 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16826 { 3967 /* vst40 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16827 { 3967 /* vst40 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16828 { 3967 /* vst40 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16829 { 3967 /* vst40 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16830 { 3967 /* vst40 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16831 { 3973 /* vst41 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16832 { 3973 /* vst41 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16833 { 3973 /* vst41 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16834 { 3973 /* vst41 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16835 { 3973 /* vst41 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16836 { 3973 /* vst41 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16837 { 3979 /* vst42 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16838 { 3979 /* vst42 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16839 { 3979 /* vst42 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16840 { 3979 /* vst42 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16841 { 3979 /* vst42 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16842 { 3979 /* vst42 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16843 { 3985 /* vst43 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16844 { 3985 /* vst43 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16845 { 3985 /* vst43 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16846 { 3985 /* vst43 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16847 { 3985 /* vst43 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16848 { 3985 /* vst43 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt }, 16849 { 4070 /* vtbl */, 8 /* 3 */, MCK_VecListDPair, AMFBS_HasNEON }, 16850 { 4070 /* vtbl */, 8 /* 3 */, MCK_VecListFourD, AMFBS_HasNEON }, 16851 { 4070 /* vtbl */, 8 /* 3 */, MCK_VecListOneD, AMFBS_HasNEON }, 16852 { 4070 /* vtbl */, 8 /* 3 */, MCK_VecListThreeD, AMFBS_HasNEON }, 16853 { 4075 /* vtbx */, 8 /* 3 */, MCK_VecListDPair, AMFBS_HasNEON }, 16854 { 4075 /* vtbx */, 8 /* 3 */, MCK_VecListFourD, AMFBS_HasNEON }, 16855 { 4075 /* vtbx */, 8 /* 3 */, MCK_VecListOneD, AMFBS_HasNEON }, 16856 { 4075 /* vtbx */, 8 /* 3 */, MCK_VecListThreeD, AMFBS_HasNEON }, 16857}; 16858 16859OperandMatchResultTy ARMAsmParser:: 16860tryCustomParseOperand(OperandVector &Operands, 16861 unsigned MCK) { 16862 16863 switch(MCK) { 16864 case MCK_AM3Offset: 16865 return parseAM3Offset(Operands); 16866 case MCK_BankedReg: 16867 return parseBankedRegOperand(Operands); 16868 case MCK_Bitfield: 16869 return parseBitfield(Operands); 16870 case MCK_CoprocNum: 16871 return parseCoprocNumOperand(Operands); 16872 case MCK_CoprocOption: 16873 return parseCoprocOptionOperand(Operands); 16874 case MCK_CoprocReg: 16875 return parseCoprocRegOperand(Operands); 16876 case MCK_FPImm: 16877 return parseFPImm(Operands); 16878 case MCK_InstSyncBarrierOpt: 16879 return parseInstSyncBarrierOptOperand(Operands); 16880 case MCK_MSRMask: 16881 return parseMSRMaskOperand(Operands); 16882 case MCK_MemBarrierOpt: 16883 return parseMemBarrierOptOperand(Operands); 16884 case MCK_ModImm: 16885 return parseModImm(Operands); 16886 case MCK_PKHASRImm: 16887 return parsePKHASRImm(Operands); 16888 case MCK_PKHLSLImm: 16889 return parsePKHLSLImm(Operands); 16890 case MCK_PostIdxReg: 16891 return parsePostIdxReg(Operands); 16892 case MCK_PostIdxRegShifted: 16893 return parsePostIdxReg(Operands); 16894 case MCK_ProcIFlags: 16895 return parseProcIFlagsOperand(Operands); 16896 case MCK_RotImm: 16897 return parseRotImm(Operands); 16898 case MCK_SetEndImm: 16899 return parseSetEndImm(Operands); 16900 case MCK_ShifterImm: 16901 return parseShifterImm(Operands); 16902 case MCK_TraceSyncBarrierOpt: 16903 return parseTraceSyncBarrierOptOperand(Operands); 16904 case MCK_VecListTwoMQ: 16905 return parseVectorList(Operands); 16906 case MCK_VecListFourMQ: 16907 return parseVectorList(Operands); 16908 case MCK_VecListDPairAllLanes: 16909 return parseVectorList(Operands); 16910 case MCK_VecListDPair: 16911 return parseVectorList(Operands); 16912 case MCK_VecListDPairSpacedAllLanes: 16913 return parseVectorList(Operands); 16914 case MCK_VecListDPairSpaced: 16915 return parseVectorList(Operands); 16916 case MCK_VecListFourDAllLanes: 16917 return parseVectorList(Operands); 16918 case MCK_VecListFourD: 16919 return parseVectorList(Operands); 16920 case MCK_VecListFourDByteIndexed: 16921 return parseVectorList(Operands); 16922 case MCK_VecListFourDHWordIndexed: 16923 return parseVectorList(Operands); 16924 case MCK_VecListFourDWordIndexed: 16925 return parseVectorList(Operands); 16926 case MCK_VecListFourQAllLanes: 16927 return parseVectorList(Operands); 16928 case MCK_VecListFourQ: 16929 return parseVectorList(Operands); 16930 case MCK_VecListFourQHWordIndexed: 16931 return parseVectorList(Operands); 16932 case MCK_VecListFourQWordIndexed: 16933 return parseVectorList(Operands); 16934 case MCK_VecListOneDAllLanes: 16935 return parseVectorList(Operands); 16936 case MCK_VecListOneD: 16937 return parseVectorList(Operands); 16938 case MCK_VecListOneDByteIndexed: 16939 return parseVectorList(Operands); 16940 case MCK_VecListOneDHWordIndexed: 16941 return parseVectorList(Operands); 16942 case MCK_VecListOneDWordIndexed: 16943 return parseVectorList(Operands); 16944 case MCK_VecListThreeDAllLanes: 16945 return parseVectorList(Operands); 16946 case MCK_VecListThreeD: 16947 return parseVectorList(Operands); 16948 case MCK_VecListThreeDByteIndexed: 16949 return parseVectorList(Operands); 16950 case MCK_VecListThreeDHWordIndexed: 16951 return parseVectorList(Operands); 16952 case MCK_VecListThreeDWordIndexed: 16953 return parseVectorList(Operands); 16954 case MCK_VecListThreeQAllLanes: 16955 return parseVectorList(Operands); 16956 case MCK_VecListThreeQ: 16957 return parseVectorList(Operands); 16958 case MCK_VecListThreeQHWordIndexed: 16959 return parseVectorList(Operands); 16960 case MCK_VecListThreeQWordIndexed: 16961 return parseVectorList(Operands); 16962 case MCK_VecListTwoDByteIndexed: 16963 return parseVectorList(Operands); 16964 case MCK_VecListTwoDHWordIndexed: 16965 return parseVectorList(Operands); 16966 case MCK_VecListTwoDWordIndexed: 16967 return parseVectorList(Operands); 16968 case MCK_VecListTwoQHWordIndexed: 16969 return parseVectorList(Operands); 16970 case MCK_VecListTwoQWordIndexed: 16971 return parseVectorList(Operands); 16972 case MCK_ITCondCode: 16973 return parseITCondCode(Operands); 16974 case MCK_CondCodeNoAL: 16975 return parseITCondCode(Operands); 16976 case MCK_CondCodeNoALInv: 16977 return parseITCondCode(Operands); 16978 case MCK_CondCodeRestrictedFP: 16979 return parseITCondCode(Operands); 16980 case MCK_CondCodeRestrictedI: 16981 return parseITCondCode(Operands); 16982 case MCK_CondCodeRestrictedS: 16983 return parseITCondCode(Operands); 16984 case MCK_CondCodeRestrictedU: 16985 return parseITCondCode(Operands); 16986 default: 16987 return MatchOperand_NoMatch; 16988 } 16989 return MatchOperand_NoMatch; 16990} 16991 16992OperandMatchResultTy ARMAsmParser:: 16993MatchOperandParserImpl(OperandVector &Operands, 16994 StringRef Mnemonic, 16995 bool ParseForAllFeatures) { 16996 // Get the current feature set. 16997 const FeatureBitset &AvailableFeatures = getAvailableFeatures(); 16998 16999 // Get the next operand index. 17000 unsigned NextOpNum = Operands.size() - 1; 17001 // Search the table. 17002 auto MnemonicRange = 17003 std::equal_range(std::begin(OperandMatchTable), std::end(OperandMatchTable), 17004 Mnemonic, LessOpcodeOperand()); 17005 17006 if (MnemonicRange.first == MnemonicRange.second) 17007 return MatchOperand_NoMatch; 17008 17009 for (const OperandMatchEntry *it = MnemonicRange.first, 17010 *ie = MnemonicRange.second; it != ie; ++it) { 17011 // equal_range guarantees that instruction mnemonic matches. 17012 assert(Mnemonic == it->getMnemonic()); 17013 17014 // check if the available features match 17015 const FeatureBitset &RequiredFeatures = FeatureBitsets[it->RequiredFeaturesIdx]; 17016 if (!ParseForAllFeatures && (AvailableFeatures & RequiredFeatures) != RequiredFeatures) 17017 continue; 17018 17019 // check if the operand in question has a custom parser. 17020 if (!(it->OperandMask & (1 << NextOpNum))) 17021 continue; 17022 17023 // call custom parse method to handle the operand 17024 OperandMatchResultTy Result = tryCustomParseOperand(Operands, it->Class); 17025 if (Result != MatchOperand_NoMatch) 17026 return Result; 17027 } 17028 17029 // Okay, we had no match. 17030 return MatchOperand_NoMatch; 17031} 17032 17033#endif // GET_MATCHER_IMPLEMENTATION 17034 17035 17036#ifdef GET_MNEMONIC_SPELL_CHECKER 17037#undef GET_MNEMONIC_SPELL_CHECKER 17038 17039static std::string ARMMnemonicSpellCheck(StringRef S, const FeatureBitset &FBS, unsigned VariantID) { 17040 const unsigned MaxEditDist = 2; 17041 std::vector<StringRef> Candidates; 17042 StringRef Prev = ""; 17043 17044 // Find the appropriate table for this asm variant. 17045 const MatchEntry *Start, *End; 17046 switch (VariantID) { 17047 default: llvm_unreachable("invalid variant!"); 17048 case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break; 17049 } 17050 17051 for (auto I = Start; I < End; I++) { 17052 // Ignore unsupported instructions. 17053 const FeatureBitset &RequiredFeatures = FeatureBitsets[I->RequiredFeaturesIdx]; 17054 if ((FBS & RequiredFeatures) != RequiredFeatures) 17055 continue; 17056 17057 StringRef T = I->getMnemonic(); 17058 // Avoid recomputing the edit distance for the same string. 17059 if (T.equals(Prev)) 17060 continue; 17061 17062 Prev = T; 17063 unsigned Dist = S.edit_distance(T, false, MaxEditDist); 17064 if (Dist <= MaxEditDist) 17065 Candidates.push_back(T); 17066 } 17067 17068 if (Candidates.empty()) 17069 return ""; 17070 17071 std::string Res = ", did you mean: "; 17072 unsigned i = 0; 17073 for (; i < Candidates.size() - 1; i++) 17074 Res += Candidates[i].str() + ", "; 17075 return Res + Candidates[i].str() + "?"; 17076} 17077 17078#endif // GET_MNEMONIC_SPELL_CHECKER 17079 17080 17081#ifdef GET_MNEMONIC_CHECKER 17082#undef GET_MNEMONIC_CHECKER 17083 17084static bool ARMCheckMnemonic(StringRef Mnemonic, 17085 const FeatureBitset &AvailableFeatures, 17086 unsigned VariantID) { 17087 // Process all MnemonicAliases to remap the mnemonic. 17088 applyMnemonicAliases(Mnemonic, AvailableFeatures, VariantID); 17089 17090 // Find the appropriate table for this asm variant. 17091 const MatchEntry *Start, *End; 17092 switch (VariantID) { 17093 default: llvm_unreachable("invalid variant!"); 17094 case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break; 17095 } 17096 17097 // Search the table. 17098 auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode()); 17099 17100 if (MnemonicRange.first == MnemonicRange.second) 17101 return false; 17102 17103 for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second; 17104 it != ie; ++it) { 17105 const FeatureBitset &RequiredFeatures = 17106 FeatureBitsets[it->RequiredFeaturesIdx]; 17107 if ((AvailableFeatures & RequiredFeatures) == RequiredFeatures) 17108 return true; 17109 } 17110 return false; 17111} 17112 17113#endif // GET_MNEMONIC_CHECKER 17114 17115