1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2|* *| 3|* Pseudo-instruction MC lowering Source Fragment *| 4|* *| 5|* Automatically generated file, do not edit! *| 6|* *| 7\*===----------------------------------------------------------------------===*/ 8 9bool ARMAsmPrinter:: 10emitPseudoExpansionLowering(MCStreamer &OutStreamer, 11 const MachineInstr *MI) { 12 switch (MI->getOpcode()) { 13 default: return false; 14 case ARM::B: { 15 MCInst TmpInst; 16 MCOperand MCOp; 17 TmpInst.setOpcode(ARM::Bcc); 18 // Operand: target 19 lowerOperand(MI->getOperand(0), MCOp); 20 TmpInst.addOperand(MCOp); 21 // Operand: p 22 TmpInst.addOperand(MCOperand::createImm(14)); 23 TmpInst.addOperand(MCOperand::createReg(0)); 24 EmitToStreamer(OutStreamer, TmpInst); 25 break; 26 } 27 case ARM::BLX_noip: { 28 MCInst TmpInst; 29 MCOperand MCOp; 30 TmpInst.setOpcode(ARM::BLX); 31 // Operand: func 32 lowerOperand(MI->getOperand(0), MCOp); 33 TmpInst.addOperand(MCOp); 34 EmitToStreamer(OutStreamer, TmpInst); 35 break; 36 } 37 case ARM::BLX_pred_noip: { 38 MCInst TmpInst; 39 MCOperand MCOp; 40 TmpInst.setOpcode(ARM::BLX_pred); 41 // Operand: func 42 lowerOperand(MI->getOperand(0), MCOp); 43 TmpInst.addOperand(MCOp); 44 // Operand: p 45 TmpInst.addOperand(MCOperand::createImm(14)); 46 TmpInst.addOperand(MCOperand::createReg(0)); 47 EmitToStreamer(OutStreamer, TmpInst); 48 break; 49 } 50 case ARM::LDMIA_RET: { 51 MCInst TmpInst; 52 MCOperand MCOp; 53 TmpInst.setOpcode(ARM::LDMIA_UPD); 54 // Operand: wb 55 lowerOperand(MI->getOperand(0), MCOp); 56 TmpInst.addOperand(MCOp); 57 // Operand: Rn 58 lowerOperand(MI->getOperand(1), MCOp); 59 TmpInst.addOperand(MCOp); 60 // Operand: p 61 lowerOperand(MI->getOperand(2), MCOp); 62 TmpInst.addOperand(MCOp); 63 lowerOperand(MI->getOperand(3), MCOp); 64 TmpInst.addOperand(MCOp); 65 // Operand: regs 66 lowerOperand(MI->getOperand(4), MCOp); 67 TmpInst.addOperand(MCOp); 68 // variable_ops 69 for (unsigned i = 5, e = MI->getNumOperands(); i != e; ++i) 70 if (lowerOperand(MI->getOperand(i), MCOp)) 71 TmpInst.addOperand(MCOp); 72 EmitToStreamer(OutStreamer, TmpInst); 73 break; 74 } 75 case ARM::MLAv5: { 76 MCInst TmpInst; 77 MCOperand MCOp; 78 TmpInst.setOpcode(ARM::MLA); 79 // Operand: Rd 80 lowerOperand(MI->getOperand(0), MCOp); 81 TmpInst.addOperand(MCOp); 82 // Operand: Rn 83 lowerOperand(MI->getOperand(1), MCOp); 84 TmpInst.addOperand(MCOp); 85 // Operand: Rm 86 lowerOperand(MI->getOperand(2), MCOp); 87 TmpInst.addOperand(MCOp); 88 // Operand: Ra 89 lowerOperand(MI->getOperand(3), MCOp); 90 TmpInst.addOperand(MCOp); 91 // Operand: p 92 lowerOperand(MI->getOperand(4), MCOp); 93 TmpInst.addOperand(MCOp); 94 lowerOperand(MI->getOperand(5), MCOp); 95 TmpInst.addOperand(MCOp); 96 // Operand: s 97 lowerOperand(MI->getOperand(6), MCOp); 98 TmpInst.addOperand(MCOp); 99 EmitToStreamer(OutStreamer, TmpInst); 100 break; 101 } 102 case ARM::MOVPCRX: { 103 MCInst TmpInst; 104 MCOperand MCOp; 105 TmpInst.setOpcode(ARM::MOVr); 106 // Operand: Rd 107 TmpInst.addOperand(MCOperand::createReg(ARM::PC)); 108 // Operand: Rm 109 lowerOperand(MI->getOperand(0), MCOp); 110 TmpInst.addOperand(MCOp); 111 // Operand: p 112 TmpInst.addOperand(MCOperand::createImm(14)); 113 TmpInst.addOperand(MCOperand::createReg(0)); 114 // Operand: s 115 TmpInst.addOperand(MCOperand::createReg(0)); 116 EmitToStreamer(OutStreamer, TmpInst); 117 break; 118 } 119 case ARM::MULv5: { 120 MCInst TmpInst; 121 MCOperand MCOp; 122 TmpInst.setOpcode(ARM::MUL); 123 // Operand: Rd 124 lowerOperand(MI->getOperand(0), MCOp); 125 TmpInst.addOperand(MCOp); 126 // Operand: Rn 127 lowerOperand(MI->getOperand(1), MCOp); 128 TmpInst.addOperand(MCOp); 129 // Operand: Rm 130 lowerOperand(MI->getOperand(2), MCOp); 131 TmpInst.addOperand(MCOp); 132 // Operand: p 133 lowerOperand(MI->getOperand(3), MCOp); 134 TmpInst.addOperand(MCOp); 135 lowerOperand(MI->getOperand(4), MCOp); 136 TmpInst.addOperand(MCOp); 137 // Operand: s 138 lowerOperand(MI->getOperand(5), MCOp); 139 TmpInst.addOperand(MCOp); 140 EmitToStreamer(OutStreamer, TmpInst); 141 break; 142 } 143 case ARM::SMLALv5: { 144 MCInst TmpInst; 145 MCOperand MCOp; 146 TmpInst.setOpcode(ARM::SMLAL); 147 // Operand: RdLo 148 lowerOperand(MI->getOperand(0), MCOp); 149 TmpInst.addOperand(MCOp); 150 // Operand: RdHi 151 lowerOperand(MI->getOperand(1), MCOp); 152 TmpInst.addOperand(MCOp); 153 // Operand: Rn 154 lowerOperand(MI->getOperand(2), MCOp); 155 TmpInst.addOperand(MCOp); 156 // Operand: Rm 157 lowerOperand(MI->getOperand(3), MCOp); 158 TmpInst.addOperand(MCOp); 159 // Operand: RLo 160 lowerOperand(MI->getOperand(4), MCOp); 161 TmpInst.addOperand(MCOp); 162 // Operand: RHi 163 lowerOperand(MI->getOperand(5), MCOp); 164 TmpInst.addOperand(MCOp); 165 // Operand: p 166 lowerOperand(MI->getOperand(6), MCOp); 167 TmpInst.addOperand(MCOp); 168 lowerOperand(MI->getOperand(7), MCOp); 169 TmpInst.addOperand(MCOp); 170 // Operand: s 171 lowerOperand(MI->getOperand(8), MCOp); 172 TmpInst.addOperand(MCOp); 173 EmitToStreamer(OutStreamer, TmpInst); 174 break; 175 } 176 case ARM::SMULLv5: { 177 MCInst TmpInst; 178 MCOperand MCOp; 179 TmpInst.setOpcode(ARM::SMULL); 180 // Operand: RdLo 181 lowerOperand(MI->getOperand(0), MCOp); 182 TmpInst.addOperand(MCOp); 183 // Operand: RdHi 184 lowerOperand(MI->getOperand(1), MCOp); 185 TmpInst.addOperand(MCOp); 186 // Operand: Rn 187 lowerOperand(MI->getOperand(2), MCOp); 188 TmpInst.addOperand(MCOp); 189 // Operand: Rm 190 lowerOperand(MI->getOperand(3), MCOp); 191 TmpInst.addOperand(MCOp); 192 // Operand: p 193 lowerOperand(MI->getOperand(4), MCOp); 194 TmpInst.addOperand(MCOp); 195 lowerOperand(MI->getOperand(5), MCOp); 196 TmpInst.addOperand(MCOp); 197 // Operand: s 198 lowerOperand(MI->getOperand(6), MCOp); 199 TmpInst.addOperand(MCOp); 200 EmitToStreamer(OutStreamer, TmpInst); 201 break; 202 } 203 case ARM::TAILJMPd: { 204 MCInst TmpInst; 205 MCOperand MCOp; 206 TmpInst.setOpcode(ARM::Bcc); 207 // Operand: target 208 lowerOperand(MI->getOperand(0), MCOp); 209 TmpInst.addOperand(MCOp); 210 // Operand: p 211 TmpInst.addOperand(MCOperand::createImm(14)); 212 TmpInst.addOperand(MCOperand::createReg(0)); 213 EmitToStreamer(OutStreamer, TmpInst); 214 break; 215 } 216 case ARM::TAILJMPr: { 217 MCInst TmpInst; 218 MCOperand MCOp; 219 TmpInst.setOpcode(ARM::BX); 220 // Operand: dst 221 lowerOperand(MI->getOperand(0), MCOp); 222 TmpInst.addOperand(MCOp); 223 EmitToStreamer(OutStreamer, TmpInst); 224 break; 225 } 226 case ARM::TAILJMPr4: { 227 MCInst TmpInst; 228 MCOperand MCOp; 229 TmpInst.setOpcode(ARM::MOVr); 230 // Operand: Rd 231 TmpInst.addOperand(MCOperand::createReg(ARM::PC)); 232 // Operand: Rm 233 lowerOperand(MI->getOperand(0), MCOp); 234 TmpInst.addOperand(MCOp); 235 // Operand: p 236 TmpInst.addOperand(MCOperand::createImm(14)); 237 TmpInst.addOperand(MCOperand::createReg(0)); 238 // Operand: s 239 TmpInst.addOperand(MCOperand::createReg(0)); 240 EmitToStreamer(OutStreamer, TmpInst); 241 break; 242 } 243 case ARM::UMLALv5: { 244 MCInst TmpInst; 245 MCOperand MCOp; 246 TmpInst.setOpcode(ARM::UMLAL); 247 // Operand: RdLo 248 lowerOperand(MI->getOperand(0), MCOp); 249 TmpInst.addOperand(MCOp); 250 // Operand: RdHi 251 lowerOperand(MI->getOperand(1), MCOp); 252 TmpInst.addOperand(MCOp); 253 // Operand: Rn 254 lowerOperand(MI->getOperand(2), MCOp); 255 TmpInst.addOperand(MCOp); 256 // Operand: Rm 257 lowerOperand(MI->getOperand(3), MCOp); 258 TmpInst.addOperand(MCOp); 259 // Operand: RLo 260 lowerOperand(MI->getOperand(4), MCOp); 261 TmpInst.addOperand(MCOp); 262 // Operand: RHi 263 lowerOperand(MI->getOperand(5), MCOp); 264 TmpInst.addOperand(MCOp); 265 // Operand: p 266 lowerOperand(MI->getOperand(6), MCOp); 267 TmpInst.addOperand(MCOp); 268 lowerOperand(MI->getOperand(7), MCOp); 269 TmpInst.addOperand(MCOp); 270 // Operand: s 271 lowerOperand(MI->getOperand(8), MCOp); 272 TmpInst.addOperand(MCOp); 273 EmitToStreamer(OutStreamer, TmpInst); 274 break; 275 } 276 case ARM::UMULLv5: { 277 MCInst TmpInst; 278 MCOperand MCOp; 279 TmpInst.setOpcode(ARM::UMULL); 280 // Operand: RdLo 281 lowerOperand(MI->getOperand(0), MCOp); 282 TmpInst.addOperand(MCOp); 283 // Operand: RdHi 284 lowerOperand(MI->getOperand(1), MCOp); 285 TmpInst.addOperand(MCOp); 286 // Operand: Rn 287 lowerOperand(MI->getOperand(2), MCOp); 288 TmpInst.addOperand(MCOp); 289 // Operand: Rm 290 lowerOperand(MI->getOperand(3), MCOp); 291 TmpInst.addOperand(MCOp); 292 // Operand: p 293 lowerOperand(MI->getOperand(4), MCOp); 294 TmpInst.addOperand(MCOp); 295 lowerOperand(MI->getOperand(5), MCOp); 296 TmpInst.addOperand(MCOp); 297 // Operand: s 298 lowerOperand(MI->getOperand(6), MCOp); 299 TmpInst.addOperand(MCOp); 300 EmitToStreamer(OutStreamer, TmpInst); 301 break; 302 } 303 case ARM::VMOVD0: { 304 MCInst TmpInst; 305 MCOperand MCOp; 306 TmpInst.setOpcode(ARM::VMOVv2i32); 307 // Operand: Vd 308 lowerOperand(MI->getOperand(0), MCOp); 309 TmpInst.addOperand(MCOp); 310 // Operand: SIMM 311 TmpInst.addOperand(MCOperand::createImm(0)); 312 // Operand: p 313 TmpInst.addOperand(MCOperand::createImm(14)); 314 TmpInst.addOperand(MCOperand::createReg(0)); 315 EmitToStreamer(OutStreamer, TmpInst); 316 break; 317 } 318 case ARM::VMOVQ0: { 319 MCInst TmpInst; 320 MCOperand MCOp; 321 TmpInst.setOpcode(ARM::VMOVv4i32); 322 // Operand: Vd 323 lowerOperand(MI->getOperand(0), MCOp); 324 TmpInst.addOperand(MCOp); 325 // Operand: SIMM 326 TmpInst.addOperand(MCOperand::createImm(0)); 327 // Operand: p 328 TmpInst.addOperand(MCOperand::createImm(14)); 329 TmpInst.addOperand(MCOperand::createReg(0)); 330 EmitToStreamer(OutStreamer, TmpInst); 331 break; 332 } 333 case ARM::t2LDMIA_RET: { 334 MCInst TmpInst; 335 MCOperand MCOp; 336 TmpInst.setOpcode(ARM::t2LDMIA_UPD); 337 // Operand: wb 338 lowerOperand(MI->getOperand(0), MCOp); 339 TmpInst.addOperand(MCOp); 340 // Operand: Rn 341 lowerOperand(MI->getOperand(1), MCOp); 342 TmpInst.addOperand(MCOp); 343 // Operand: p 344 lowerOperand(MI->getOperand(2), MCOp); 345 TmpInst.addOperand(MCOp); 346 lowerOperand(MI->getOperand(3), MCOp); 347 TmpInst.addOperand(MCOp); 348 // Operand: regs 349 lowerOperand(MI->getOperand(4), MCOp); 350 TmpInst.addOperand(MCOp); 351 // variable_ops 352 for (unsigned i = 5, e = MI->getNumOperands(); i != e; ++i) 353 if (lowerOperand(MI->getOperand(i), MCOp)) 354 TmpInst.addOperand(MCOp); 355 EmitToStreamer(OutStreamer, TmpInst); 356 break; 357 } 358 case ARM::tBLXr_noip: { 359 MCInst TmpInst; 360 MCOperand MCOp; 361 TmpInst.setOpcode(ARM::tBLXr); 362 // Operand: p 363 lowerOperand(MI->getOperand(0), MCOp); 364 TmpInst.addOperand(MCOp); 365 lowerOperand(MI->getOperand(1), MCOp); 366 TmpInst.addOperand(MCOp); 367 // Operand: func 368 lowerOperand(MI->getOperand(2), MCOp); 369 TmpInst.addOperand(MCOp); 370 EmitToStreamer(OutStreamer, TmpInst); 371 break; 372 } 373 case ARM::tBRIND: { 374 MCInst TmpInst; 375 MCOperand MCOp; 376 TmpInst.setOpcode(ARM::tMOVr); 377 // Operand: Rd 378 TmpInst.addOperand(MCOperand::createReg(ARM::PC)); 379 // Operand: Rm 380 lowerOperand(MI->getOperand(0), MCOp); 381 TmpInst.addOperand(MCOp); 382 // Operand: p 383 lowerOperand(MI->getOperand(1), MCOp); 384 TmpInst.addOperand(MCOp); 385 lowerOperand(MI->getOperand(2), MCOp); 386 TmpInst.addOperand(MCOp); 387 EmitToStreamer(OutStreamer, TmpInst); 388 break; 389 } 390 case ARM::tBX_RET: { 391 MCInst TmpInst; 392 MCOperand MCOp; 393 TmpInst.setOpcode(ARM::tBX); 394 // Operand: Rm 395 TmpInst.addOperand(MCOperand::createReg(ARM::LR)); 396 // Operand: p 397 lowerOperand(MI->getOperand(0), MCOp); 398 TmpInst.addOperand(MCOp); 399 lowerOperand(MI->getOperand(1), MCOp); 400 TmpInst.addOperand(MCOp); 401 EmitToStreamer(OutStreamer, TmpInst); 402 break; 403 } 404 case ARM::tBX_RET_vararg: { 405 MCInst TmpInst; 406 MCOperand MCOp; 407 TmpInst.setOpcode(ARM::tBX); 408 // Operand: Rm 409 lowerOperand(MI->getOperand(0), MCOp); 410 TmpInst.addOperand(MCOp); 411 // Operand: p 412 lowerOperand(MI->getOperand(1), MCOp); 413 TmpInst.addOperand(MCOp); 414 lowerOperand(MI->getOperand(2), MCOp); 415 TmpInst.addOperand(MCOp); 416 EmitToStreamer(OutStreamer, TmpInst); 417 break; 418 } 419 case ARM::tBfar: { 420 MCInst TmpInst; 421 MCOperand MCOp; 422 TmpInst.setOpcode(ARM::tBL); 423 // Operand: p 424 lowerOperand(MI->getOperand(1), MCOp); 425 TmpInst.addOperand(MCOp); 426 lowerOperand(MI->getOperand(2), MCOp); 427 TmpInst.addOperand(MCOp); 428 // Operand: func 429 lowerOperand(MI->getOperand(0), MCOp); 430 TmpInst.addOperand(MCOp); 431 EmitToStreamer(OutStreamer, TmpInst); 432 break; 433 } 434 case ARM::tLDMIA_UPD: { 435 MCInst TmpInst; 436 MCOperand MCOp; 437 TmpInst.setOpcode(ARM::tLDMIA); 438 // Operand: Rn 439 lowerOperand(MI->getOperand(1), MCOp); 440 TmpInst.addOperand(MCOp); 441 // Operand: p 442 lowerOperand(MI->getOperand(2), MCOp); 443 TmpInst.addOperand(MCOp); 444 lowerOperand(MI->getOperand(3), MCOp); 445 TmpInst.addOperand(MCOp); 446 // Operand: regs 447 lowerOperand(MI->getOperand(4), MCOp); 448 TmpInst.addOperand(MCOp); 449 // variable_ops 450 for (unsigned i = 5, e = MI->getNumOperands(); i != e; ++i) 451 if (lowerOperand(MI->getOperand(i), MCOp)) 452 TmpInst.addOperand(MCOp); 453 EmitToStreamer(OutStreamer, TmpInst); 454 break; 455 } 456 case ARM::tPOP_RET: { 457 MCInst TmpInst; 458 MCOperand MCOp; 459 TmpInst.setOpcode(ARM::tPOP); 460 // Operand: p 461 lowerOperand(MI->getOperand(0), MCOp); 462 TmpInst.addOperand(MCOp); 463 lowerOperand(MI->getOperand(1), MCOp); 464 TmpInst.addOperand(MCOp); 465 // Operand: regs 466 lowerOperand(MI->getOperand(2), MCOp); 467 TmpInst.addOperand(MCOp); 468 // variable_ops 469 for (unsigned i = 3, e = MI->getNumOperands(); i != e; ++i) 470 if (lowerOperand(MI->getOperand(i), MCOp)) 471 TmpInst.addOperand(MCOp); 472 EmitToStreamer(OutStreamer, TmpInst); 473 break; 474 } 475 case ARM::tTAILJMPd: { 476 MCInst TmpInst; 477 MCOperand MCOp; 478 TmpInst.setOpcode(ARM::t2B); 479 // Operand: target 480 lowerOperand(MI->getOperand(0), MCOp); 481 TmpInst.addOperand(MCOp); 482 // Operand: p 483 lowerOperand(MI->getOperand(1), MCOp); 484 TmpInst.addOperand(MCOp); 485 lowerOperand(MI->getOperand(2), MCOp); 486 TmpInst.addOperand(MCOp); 487 EmitToStreamer(OutStreamer, TmpInst); 488 break; 489 } 490 case ARM::tTAILJMPdND: { 491 MCInst TmpInst; 492 MCOperand MCOp; 493 TmpInst.setOpcode(ARM::tB); 494 // Operand: target 495 lowerOperand(MI->getOperand(0), MCOp); 496 TmpInst.addOperand(MCOp); 497 // Operand: p 498 lowerOperand(MI->getOperand(1), MCOp); 499 TmpInst.addOperand(MCOp); 500 lowerOperand(MI->getOperand(2), MCOp); 501 TmpInst.addOperand(MCOp); 502 EmitToStreamer(OutStreamer, TmpInst); 503 break; 504 } 505 case ARM::tTAILJMPr: { 506 MCInst TmpInst; 507 MCOperand MCOp; 508 TmpInst.setOpcode(ARM::tBX); 509 // Operand: Rm 510 lowerOperand(MI->getOperand(0), MCOp); 511 TmpInst.addOperand(MCOp); 512 // Operand: p 513 TmpInst.addOperand(MCOperand::createImm(14)); 514 TmpInst.addOperand(MCOperand::createReg(0)); 515 EmitToStreamer(OutStreamer, TmpInst); 516 break; 517 } 518 } 519 return true; 520} 521 522