1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2|* *| 3|* Target Instruction Enum Values and Descriptors *| 4|* *| 5|* Automatically generated file, do not edit! *| 6|* *| 7\*===----------------------------------------------------------------------===*/ 8 9#ifdef GET_INSTRINFO_ENUM 10#undef GET_INSTRINFO_ENUM 11namespace llvm { 12 13namespace LoongArch { 14 enum { 15 PHI = 0, 16 INLINEASM = 1, 17 INLINEASM_BR = 2, 18 CFI_INSTRUCTION = 3, 19 EH_LABEL = 4, 20 GC_LABEL = 5, 21 ANNOTATION_LABEL = 6, 22 KILL = 7, 23 EXTRACT_SUBREG = 8, 24 INSERT_SUBREG = 9, 25 IMPLICIT_DEF = 10, 26 SUBREG_TO_REG = 11, 27 COPY_TO_REGCLASS = 12, 28 DBG_VALUE = 13, 29 DBG_VALUE_LIST = 14, 30 DBG_INSTR_REF = 15, 31 DBG_PHI = 16, 32 DBG_LABEL = 17, 33 REG_SEQUENCE = 18, 34 COPY = 19, 35 BUNDLE = 20, 36 LIFETIME_START = 21, 37 LIFETIME_END = 22, 38 PSEUDO_PROBE = 23, 39 ARITH_FENCE = 24, 40 STACKMAP = 25, 41 FENTRY_CALL = 26, 42 PATCHPOINT = 27, 43 LOAD_STACK_GUARD = 28, 44 PREALLOCATED_SETUP = 29, 45 PREALLOCATED_ARG = 30, 46 STATEPOINT = 31, 47 LOCAL_ESCAPE = 32, 48 FAULTING_OP = 33, 49 PATCHABLE_OP = 34, 50 PATCHABLE_FUNCTION_ENTER = 35, 51 PATCHABLE_RET = 36, 52 PATCHABLE_FUNCTION_EXIT = 37, 53 PATCHABLE_TAIL_CALL = 38, 54 PATCHABLE_EVENT_CALL = 39, 55 PATCHABLE_TYPED_EVENT_CALL = 40, 56 ICALL_BRANCH_FUNNEL = 41, 57 MEMBARRIER = 42, 58 G_ASSERT_SEXT = 43, 59 G_ASSERT_ZEXT = 44, 60 G_ASSERT_ALIGN = 45, 61 G_ADD = 46, 62 G_SUB = 47, 63 G_MUL = 48, 64 G_SDIV = 49, 65 G_UDIV = 50, 66 G_SREM = 51, 67 G_UREM = 52, 68 G_SDIVREM = 53, 69 G_UDIVREM = 54, 70 G_AND = 55, 71 G_OR = 56, 72 G_XOR = 57, 73 G_IMPLICIT_DEF = 58, 74 G_PHI = 59, 75 G_FRAME_INDEX = 60, 76 G_GLOBAL_VALUE = 61, 77 G_EXTRACT = 62, 78 G_UNMERGE_VALUES = 63, 79 G_INSERT = 64, 80 G_MERGE_VALUES = 65, 81 G_BUILD_VECTOR = 66, 82 G_BUILD_VECTOR_TRUNC = 67, 83 G_CONCAT_VECTORS = 68, 84 G_PTRTOINT = 69, 85 G_INTTOPTR = 70, 86 G_BITCAST = 71, 87 G_FREEZE = 72, 88 G_INTRINSIC_FPTRUNC_ROUND = 73, 89 G_INTRINSIC_TRUNC = 74, 90 G_INTRINSIC_ROUND = 75, 91 G_INTRINSIC_LRINT = 76, 92 G_INTRINSIC_ROUNDEVEN = 77, 93 G_READCYCLECOUNTER = 78, 94 G_LOAD = 79, 95 G_SEXTLOAD = 80, 96 G_ZEXTLOAD = 81, 97 G_INDEXED_LOAD = 82, 98 G_INDEXED_SEXTLOAD = 83, 99 G_INDEXED_ZEXTLOAD = 84, 100 G_STORE = 85, 101 G_INDEXED_STORE = 86, 102 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 87, 103 G_ATOMIC_CMPXCHG = 88, 104 G_ATOMICRMW_XCHG = 89, 105 G_ATOMICRMW_ADD = 90, 106 G_ATOMICRMW_SUB = 91, 107 G_ATOMICRMW_AND = 92, 108 G_ATOMICRMW_NAND = 93, 109 G_ATOMICRMW_OR = 94, 110 G_ATOMICRMW_XOR = 95, 111 G_ATOMICRMW_MAX = 96, 112 G_ATOMICRMW_MIN = 97, 113 G_ATOMICRMW_UMAX = 98, 114 G_ATOMICRMW_UMIN = 99, 115 G_ATOMICRMW_FADD = 100, 116 G_ATOMICRMW_FSUB = 101, 117 G_ATOMICRMW_FMAX = 102, 118 G_ATOMICRMW_FMIN = 103, 119 G_ATOMICRMW_UINC_WRAP = 104, 120 G_ATOMICRMW_UDEC_WRAP = 105, 121 G_FENCE = 106, 122 G_BRCOND = 107, 123 G_BRINDIRECT = 108, 124 G_INVOKE_REGION_START = 109, 125 G_INTRINSIC = 110, 126 G_INTRINSIC_W_SIDE_EFFECTS = 111, 127 G_ANYEXT = 112, 128 G_TRUNC = 113, 129 G_CONSTANT = 114, 130 G_FCONSTANT = 115, 131 G_VASTART = 116, 132 G_VAARG = 117, 133 G_SEXT = 118, 134 G_SEXT_INREG = 119, 135 G_ZEXT = 120, 136 G_SHL = 121, 137 G_LSHR = 122, 138 G_ASHR = 123, 139 G_FSHL = 124, 140 G_FSHR = 125, 141 G_ROTR = 126, 142 G_ROTL = 127, 143 G_ICMP = 128, 144 G_FCMP = 129, 145 G_SELECT = 130, 146 G_UADDO = 131, 147 G_UADDE = 132, 148 G_USUBO = 133, 149 G_USUBE = 134, 150 G_SADDO = 135, 151 G_SADDE = 136, 152 G_SSUBO = 137, 153 G_SSUBE = 138, 154 G_UMULO = 139, 155 G_SMULO = 140, 156 G_UMULH = 141, 157 G_SMULH = 142, 158 G_UADDSAT = 143, 159 G_SADDSAT = 144, 160 G_USUBSAT = 145, 161 G_SSUBSAT = 146, 162 G_USHLSAT = 147, 163 G_SSHLSAT = 148, 164 G_SMULFIX = 149, 165 G_UMULFIX = 150, 166 G_SMULFIXSAT = 151, 167 G_UMULFIXSAT = 152, 168 G_SDIVFIX = 153, 169 G_UDIVFIX = 154, 170 G_SDIVFIXSAT = 155, 171 G_UDIVFIXSAT = 156, 172 G_FADD = 157, 173 G_FSUB = 158, 174 G_FMUL = 159, 175 G_FMA = 160, 176 G_FMAD = 161, 177 G_FDIV = 162, 178 G_FREM = 163, 179 G_FPOW = 164, 180 G_FPOWI = 165, 181 G_FEXP = 166, 182 G_FEXP2 = 167, 183 G_FLOG = 168, 184 G_FLOG2 = 169, 185 G_FLOG10 = 170, 186 G_FNEG = 171, 187 G_FPEXT = 172, 188 G_FPTRUNC = 173, 189 G_FPTOSI = 174, 190 G_FPTOUI = 175, 191 G_SITOFP = 176, 192 G_UITOFP = 177, 193 G_FABS = 178, 194 G_FCOPYSIGN = 179, 195 G_IS_FPCLASS = 180, 196 G_FCANONICALIZE = 181, 197 G_FMINNUM = 182, 198 G_FMAXNUM = 183, 199 G_FMINNUM_IEEE = 184, 200 G_FMAXNUM_IEEE = 185, 201 G_FMINIMUM = 186, 202 G_FMAXIMUM = 187, 203 G_PTR_ADD = 188, 204 G_PTRMASK = 189, 205 G_SMIN = 190, 206 G_SMAX = 191, 207 G_UMIN = 192, 208 G_UMAX = 193, 209 G_ABS = 194, 210 G_LROUND = 195, 211 G_LLROUND = 196, 212 G_BR = 197, 213 G_BRJT = 198, 214 G_INSERT_VECTOR_ELT = 199, 215 G_EXTRACT_VECTOR_ELT = 200, 216 G_SHUFFLE_VECTOR = 201, 217 G_CTTZ = 202, 218 G_CTTZ_ZERO_UNDEF = 203, 219 G_CTLZ = 204, 220 G_CTLZ_ZERO_UNDEF = 205, 221 G_CTPOP = 206, 222 G_BSWAP = 207, 223 G_BITREVERSE = 208, 224 G_FCEIL = 209, 225 G_FCOS = 210, 226 G_FSIN = 211, 227 G_FSQRT = 212, 228 G_FFLOOR = 213, 229 G_FRINT = 214, 230 G_FNEARBYINT = 215, 231 G_ADDRSPACE_CAST = 216, 232 G_BLOCK_ADDR = 217, 233 G_JUMP_TABLE = 218, 234 G_DYN_STACKALLOC = 219, 235 G_STRICT_FADD = 220, 236 G_STRICT_FSUB = 221, 237 G_STRICT_FMUL = 222, 238 G_STRICT_FDIV = 223, 239 G_STRICT_FREM = 224, 240 G_STRICT_FMA = 225, 241 G_STRICT_FSQRT = 226, 242 G_READ_REGISTER = 227, 243 G_WRITE_REGISTER = 228, 244 G_MEMCPY = 229, 245 G_MEMCPY_INLINE = 230, 246 G_MEMMOVE = 231, 247 G_MEMSET = 232, 248 G_BZERO = 233, 249 G_VECREDUCE_SEQ_FADD = 234, 250 G_VECREDUCE_SEQ_FMUL = 235, 251 G_VECREDUCE_FADD = 236, 252 G_VECREDUCE_FMUL = 237, 253 G_VECREDUCE_FMAX = 238, 254 G_VECREDUCE_FMIN = 239, 255 G_VECREDUCE_ADD = 240, 256 G_VECREDUCE_MUL = 241, 257 G_VECREDUCE_AND = 242, 258 G_VECREDUCE_OR = 243, 259 G_VECREDUCE_XOR = 244, 260 G_VECREDUCE_SMAX = 245, 261 G_VECREDUCE_SMIN = 246, 262 G_VECREDUCE_UMAX = 247, 263 G_VECREDUCE_UMIN = 248, 264 G_SBFX = 249, 265 G_UBFX = 250, 266 ADJCALLSTACKDOWN = 251, 267 ADJCALLSTACKUP = 252, 268 PseudoAtomicLoadAdd32 = 253, 269 PseudoAtomicLoadAnd32 = 254, 270 PseudoAtomicLoadNand32 = 255, 271 PseudoAtomicLoadNand64 = 256, 272 PseudoAtomicLoadOr32 = 257, 273 PseudoAtomicLoadSub32 = 258, 274 PseudoAtomicLoadXor32 = 259, 275 PseudoAtomicStoreD = 260, 276 PseudoAtomicStoreW = 261, 277 PseudoAtomicSwap32 = 262, 278 PseudoBR = 263, 279 PseudoBRIND = 264, 280 PseudoB_TAIL = 265, 281 PseudoCALL = 266, 282 PseudoCALLIndirect = 267, 283 PseudoCmpXchg32 = 268, 284 PseudoCmpXchg64 = 269, 285 PseudoJIRL_CALL = 270, 286 PseudoJIRL_TAIL = 271, 287 PseudoLA_ABS = 272, 288 PseudoLA_ABS_LARGE = 273, 289 PseudoLA_GOT = 274, 290 PseudoLA_GOT_LARGE = 275, 291 PseudoLA_PCREL = 276, 292 PseudoLA_PCREL_LARGE = 277, 293 PseudoLA_TLS_GD = 278, 294 PseudoLA_TLS_GD_LARGE = 279, 295 PseudoLA_TLS_IE = 280, 296 PseudoLA_TLS_IE_LARGE = 281, 297 PseudoLA_TLS_LD = 282, 298 PseudoLA_TLS_LD_LARGE = 283, 299 PseudoLA_TLS_LE = 284, 300 PseudoLD_CFR = 285, 301 PseudoLI_D = 286, 302 PseudoLI_W = 287, 303 PseudoMaskedAtomicLoadAdd32 = 288, 304 PseudoMaskedAtomicLoadMax32 = 289, 305 PseudoMaskedAtomicLoadMin32 = 290, 306 PseudoMaskedAtomicLoadNand32 = 291, 307 PseudoMaskedAtomicLoadSub32 = 292, 308 PseudoMaskedAtomicLoadUMax32 = 293, 309 PseudoMaskedAtomicLoadUMin32 = 294, 310 PseudoMaskedAtomicSwap32 = 295, 311 PseudoMaskedCmpXchg32 = 296, 312 PseudoRET = 297, 313 PseudoST_CFR = 298, 314 PseudoTAIL = 299, 315 PseudoTAILIndirect = 300, 316 PseudoUNIMP = 301, 317 RDFCSR = 302, 318 WRFCSR = 303, 319 ADDI_D = 304, 320 ADDI_W = 305, 321 ADDU16I_D = 306, 322 ADD_D = 307, 323 ADD_W = 308, 324 ALSL_D = 309, 325 ALSL_W = 310, 326 ALSL_WU = 311, 327 AMADD_D = 312, 328 AMADD_DB_D = 313, 329 AMADD_DB_W = 314, 330 AMADD_W = 315, 331 AMAND_D = 316, 332 AMAND_DB_D = 317, 333 AMAND_DB_W = 318, 334 AMAND_W = 319, 335 AMMAX_D = 320, 336 AMMAX_DB_D = 321, 337 AMMAX_DB_DU = 322, 338 AMMAX_DB_W = 323, 339 AMMAX_DB_WU = 324, 340 AMMAX_DU = 325, 341 AMMAX_W = 326, 342 AMMAX_WU = 327, 343 AMMIN_D = 328, 344 AMMIN_DB_D = 329, 345 AMMIN_DB_DU = 330, 346 AMMIN_DB_W = 331, 347 AMMIN_DB_WU = 332, 348 AMMIN_DU = 333, 349 AMMIN_W = 334, 350 AMMIN_WU = 335, 351 AMOR_D = 336, 352 AMOR_DB_D = 337, 353 AMOR_DB_W = 338, 354 AMOR_W = 339, 355 AMSWAP_D = 340, 356 AMSWAP_DB_D = 341, 357 AMSWAP_DB_W = 342, 358 AMSWAP_W = 343, 359 AMXOR_D = 344, 360 AMXOR_DB_D = 345, 361 AMXOR_DB_W = 346, 362 AMXOR_W = 347, 363 AND = 348, 364 ANDI = 349, 365 ANDN = 350, 366 ASRTGT_D = 351, 367 ASRTLE_D = 352, 368 B = 353, 369 BCEQZ = 354, 370 BCNEZ = 355, 371 BEQ = 356, 372 BEQZ = 357, 373 BGE = 358, 374 BGEU = 359, 375 BITREV_4B = 360, 376 BITREV_8B = 361, 377 BITREV_D = 362, 378 BITREV_W = 363, 379 BL = 364, 380 BLT = 365, 381 BLTU = 366, 382 BNE = 367, 383 BNEZ = 368, 384 BREAK = 369, 385 BSTRINS_D = 370, 386 BSTRINS_W = 371, 387 BSTRPICK_D = 372, 388 BSTRPICK_W = 373, 389 BYTEPICK_D = 374, 390 BYTEPICK_W = 375, 391 CACOP = 376, 392 CLO_D = 377, 393 CLO_W = 378, 394 CLZ_D = 379, 395 CLZ_W = 380, 396 CPUCFG = 381, 397 CRCC_W_B_W = 382, 398 CRCC_W_D_W = 383, 399 CRCC_W_H_W = 384, 400 CRCC_W_W_W = 385, 401 CRC_W_B_W = 386, 402 CRC_W_D_W = 387, 403 CRC_W_H_W = 388, 404 CRC_W_W_W = 389, 405 CSRRD = 390, 406 CSRWR = 391, 407 CSRXCHG = 392, 408 CTO_D = 393, 409 CTO_W = 394, 410 CTZ_D = 395, 411 CTZ_W = 396, 412 DBAR = 397, 413 DBCL = 398, 414 DIV_D = 399, 415 DIV_DU = 400, 416 DIV_W = 401, 417 DIV_WU = 402, 418 ERTN = 403, 419 EXT_W_B = 404, 420 EXT_W_H = 405, 421 FABS_D = 406, 422 FABS_S = 407, 423 FADD_D = 408, 424 FADD_S = 409, 425 FCLASS_D = 410, 426 FCLASS_S = 411, 427 FCMP_CAF_D = 412, 428 FCMP_CAF_S = 413, 429 FCMP_CEQ_D = 414, 430 FCMP_CEQ_S = 415, 431 FCMP_CLE_D = 416, 432 FCMP_CLE_S = 417, 433 FCMP_CLT_D = 418, 434 FCMP_CLT_S = 419, 435 FCMP_CNE_D = 420, 436 FCMP_CNE_S = 421, 437 FCMP_COR_D = 422, 438 FCMP_COR_S = 423, 439 FCMP_CUEQ_D = 424, 440 FCMP_CUEQ_S = 425, 441 FCMP_CULE_D = 426, 442 FCMP_CULE_S = 427, 443 FCMP_CULT_D = 428, 444 FCMP_CULT_S = 429, 445 FCMP_CUNE_D = 430, 446 FCMP_CUNE_S = 431, 447 FCMP_CUN_D = 432, 448 FCMP_CUN_S = 433, 449 FCMP_SAF_D = 434, 450 FCMP_SAF_S = 435, 451 FCMP_SEQ_D = 436, 452 FCMP_SEQ_S = 437, 453 FCMP_SLE_D = 438, 454 FCMP_SLE_S = 439, 455 FCMP_SLT_D = 440, 456 FCMP_SLT_S = 441, 457 FCMP_SNE_D = 442, 458 FCMP_SNE_S = 443, 459 FCMP_SOR_D = 444, 460 FCMP_SOR_S = 445, 461 FCMP_SUEQ_D = 446, 462 FCMP_SUEQ_S = 447, 463 FCMP_SULE_D = 448, 464 FCMP_SULE_S = 449, 465 FCMP_SULT_D = 450, 466 FCMP_SULT_S = 451, 467 FCMP_SUNE_D = 452, 468 FCMP_SUNE_S = 453, 469 FCMP_SUN_D = 454, 470 FCMP_SUN_S = 455, 471 FCOPYSIGN_D = 456, 472 FCOPYSIGN_S = 457, 473 FCVT_D_S = 458, 474 FCVT_S_D = 459, 475 FDIV_D = 460, 476 FDIV_S = 461, 477 FFINT_D_L = 462, 478 FFINT_D_W = 463, 479 FFINT_S_L = 464, 480 FFINT_S_W = 465, 481 FLDGT_D = 466, 482 FLDGT_S = 467, 483 FLDLE_D = 468, 484 FLDLE_S = 469, 485 FLDX_D = 470, 486 FLDX_S = 471, 487 FLD_D = 472, 488 FLD_S = 473, 489 FLOGB_D = 474, 490 FLOGB_S = 475, 491 FMADD_D = 476, 492 FMADD_S = 477, 493 FMAXA_D = 478, 494 FMAXA_S = 479, 495 FMAX_D = 480, 496 FMAX_S = 481, 497 FMINA_D = 482, 498 FMINA_S = 483, 499 FMIN_D = 484, 500 FMIN_S = 485, 501 FMOV_D = 486, 502 FMOV_S = 487, 503 FMSUB_D = 488, 504 FMSUB_S = 489, 505 FMUL_D = 490, 506 FMUL_S = 491, 507 FNEG_D = 492, 508 FNEG_S = 493, 509 FNMADD_D = 494, 510 FNMADD_S = 495, 511 FNMSUB_D = 496, 512 FNMSUB_S = 497, 513 FRECIP_D = 498, 514 FRECIP_S = 499, 515 FRINT_D = 500, 516 FRINT_S = 501, 517 FRSQRT_D = 502, 518 FRSQRT_S = 503, 519 FSCALEB_D = 504, 520 FSCALEB_S = 505, 521 FSEL_D = 506, 522 FSEL_S = 507, 523 FSQRT_D = 508, 524 FSQRT_S = 509, 525 FSTGT_D = 510, 526 FSTGT_S = 511, 527 FSTLE_D = 512, 528 FSTLE_S = 513, 529 FSTX_D = 514, 530 FSTX_S = 515, 531 FST_D = 516, 532 FST_S = 517, 533 FSUB_D = 518, 534 FSUB_S = 519, 535 FTINTRM_L_D = 520, 536 FTINTRM_L_S = 521, 537 FTINTRM_W_D = 522, 538 FTINTRM_W_S = 523, 539 FTINTRNE_L_D = 524, 540 FTINTRNE_L_S = 525, 541 FTINTRNE_W_D = 526, 542 FTINTRNE_W_S = 527, 543 FTINTRP_L_D = 528, 544 FTINTRP_L_S = 529, 545 FTINTRP_W_D = 530, 546 FTINTRP_W_S = 531, 547 FTINTRZ_L_D = 532, 548 FTINTRZ_L_S = 533, 549 FTINTRZ_W_D = 534, 550 FTINTRZ_W_S = 535, 551 FTINT_L_D = 536, 552 FTINT_L_S = 537, 553 FTINT_W_D = 538, 554 FTINT_W_S = 539, 555 IBAR = 540, 556 IDLE = 541, 557 INVTLB = 542, 558 IOCSRRD_B = 543, 559 IOCSRRD_D = 544, 560 IOCSRRD_H = 545, 561 IOCSRRD_W = 546, 562 IOCSRWR_B = 547, 563 IOCSRWR_D = 548, 564 IOCSRWR_H = 549, 565 IOCSRWR_W = 550, 566 JIRL = 551, 567 LDDIR = 552, 568 LDGT_B = 553, 569 LDGT_D = 554, 570 LDGT_H = 555, 571 LDGT_W = 556, 572 LDLE_B = 557, 573 LDLE_D = 558, 574 LDLE_H = 559, 575 LDLE_W = 560, 576 LDPTE = 561, 577 LDPTR_D = 562, 578 LDPTR_W = 563, 579 LDX_B = 564, 580 LDX_BU = 565, 581 LDX_D = 566, 582 LDX_H = 567, 583 LDX_HU = 568, 584 LDX_W = 569, 585 LDX_WU = 570, 586 LD_B = 571, 587 LD_BU = 572, 588 LD_D = 573, 589 LD_H = 574, 590 LD_HU = 575, 591 LD_W = 576, 592 LD_WU = 577, 593 LL_D = 578, 594 LL_W = 579, 595 LU12I_W = 580, 596 LU32I_D = 581, 597 LU52I_D = 582, 598 MASKEQZ = 583, 599 MASKNEZ = 584, 600 MOD_D = 585, 601 MOD_DU = 586, 602 MOD_W = 587, 603 MOD_WU = 588, 604 MOVCF2FR_S = 589, 605 MOVCF2GR = 590, 606 MOVFCSR2GR = 591, 607 MOVFR2CF_S = 592, 608 MOVFR2GR_D = 593, 609 MOVFR2GR_S = 594, 610 MOVFR2GR_S_64 = 595, 611 MOVFRH2GR_S = 596, 612 MOVGR2CF = 597, 613 MOVGR2FCSR = 598, 614 MOVGR2FRH_W = 599, 615 MOVGR2FR_D = 600, 616 MOVGR2FR_W = 601, 617 MOVGR2FR_W_64 = 602, 618 MULH_D = 603, 619 MULH_DU = 604, 620 MULH_W = 605, 621 MULH_WU = 606, 622 MULW_D_W = 607, 623 MULW_D_WU = 608, 624 MUL_D = 609, 625 MUL_W = 610, 626 NOR = 611, 627 OR = 612, 628 ORI = 613, 629 ORN = 614, 630 PCADDI = 615, 631 PCADDU12I = 616, 632 PCADDU18I = 617, 633 PCALAU12I = 618, 634 PRELD = 619, 635 PRELDX = 620, 636 RDTIMEH_W = 621, 637 RDTIMEL_W = 622, 638 RDTIME_D = 623, 639 REVB_2H = 624, 640 REVB_2W = 625, 641 REVB_4H = 626, 642 REVB_D = 627, 643 REVH_2W = 628, 644 REVH_D = 629, 645 ROTRI_D = 630, 646 ROTRI_W = 631, 647 ROTR_D = 632, 648 ROTR_W = 633, 649 SC_D = 634, 650 SC_W = 635, 651 SLLI_D = 636, 652 SLLI_W = 637, 653 SLL_D = 638, 654 SLL_W = 639, 655 SLT = 640, 656 SLTI = 641, 657 SLTU = 642, 658 SLTUI = 643, 659 SRAI_D = 644, 660 SRAI_W = 645, 661 SRA_D = 646, 662 SRA_W = 647, 663 SRLI_D = 648, 664 SRLI_W = 649, 665 SRL_D = 650, 666 SRL_W = 651, 667 STGT_B = 652, 668 STGT_D = 653, 669 STGT_H = 654, 670 STGT_W = 655, 671 STLE_B = 656, 672 STLE_D = 657, 673 STLE_H = 658, 674 STLE_W = 659, 675 STPTR_D = 660, 676 STPTR_W = 661, 677 STX_B = 662, 678 STX_D = 663, 679 STX_H = 664, 680 STX_W = 665, 681 ST_B = 666, 682 ST_D = 667, 683 ST_H = 668, 684 ST_W = 669, 685 SUB_D = 670, 686 SUB_W = 671, 687 SYSCALL = 672, 688 TLBCLR = 673, 689 TLBFILL = 674, 690 TLBFLUSH = 675, 691 TLBRD = 676, 692 TLBSRCH = 677, 693 TLBWR = 678, 694 XOR = 679, 695 XORI = 680, 696 INSTRUCTION_LIST_END = 681 697 }; 698 699} // end namespace LoongArch 700} // end namespace llvm 701#endif // GET_INSTRINFO_ENUM 702 703#ifdef GET_INSTRINFO_SCHED_ENUM 704#undef GET_INSTRINFO_SCHED_ENUM 705namespace llvm { 706 707namespace LoongArch { 708namespace Sched { 709 enum { 710 NoInstrModel = 0, 711 SCHED_LIST_END = 1 712 }; 713} // end namespace Sched 714} // end namespace LoongArch 715} // end namespace llvm 716#endif // GET_INSTRINFO_SCHED_ENUM 717 718#ifdef GET_INSTRINFO_MC_DESC 719#undef GET_INSTRINFO_MC_DESC 720namespace llvm { 721 722static const MCPhysReg ImplicitList1[] = { LoongArch::R3, LoongArch::R3 }; 723static const MCPhysReg ImplicitList2[] = { LoongArch::R3 }; 724static const MCPhysReg ImplicitList3[] = { LoongArch::R1 }; 725 726static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 727static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; 728static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; 729static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; 730static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; 731static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 732static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; 733static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, }; 734static const MCOperandInfo OperandInfo10[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; 735static const MCOperandInfo OperandInfo11[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; 736static const MCOperandInfo OperandInfo12[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; 737static const MCOperandInfo OperandInfo13[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; 738static const MCOperandInfo OperandInfo14[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; 739static const MCOperandInfo OperandInfo15[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 740static const MCOperandInfo OperandInfo16[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 741static const MCOperandInfo OperandInfo17[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, }; 742static const MCOperandInfo OperandInfo18[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; 743static const MCOperandInfo OperandInfo19[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; 744static const MCOperandInfo OperandInfo20[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; 745static const MCOperandInfo OperandInfo21[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 746static const MCOperandInfo OperandInfo22[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, }; 747static const MCOperandInfo OperandInfo23[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, }; 748static const MCOperandInfo OperandInfo24[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, }; 749static const MCOperandInfo OperandInfo25[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; 750static const MCOperandInfo OperandInfo26[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; 751static const MCOperandInfo OperandInfo27[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 752static const MCOperandInfo OperandInfo28[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 753static const MCOperandInfo OperandInfo29[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; 754static const MCOperandInfo OperandInfo30[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; 755static const MCOperandInfo OperandInfo31[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; 756static const MCOperandInfo OperandInfo32[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 757static const MCOperandInfo OperandInfo33[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, }; 758static const MCOperandInfo OperandInfo34[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, }; 759static const MCOperandInfo OperandInfo35[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, }; 760static const MCOperandInfo OperandInfo36[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, }; 761static const MCOperandInfo OperandInfo37[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, }; 762static const MCOperandInfo OperandInfo38[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, }; 763static const MCOperandInfo OperandInfo39[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, }; 764static const MCOperandInfo OperandInfo40[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, }; 765static const MCOperandInfo OperandInfo41[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 766static const MCOperandInfo OperandInfo42[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; 767static const MCOperandInfo OperandInfo43[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, }; 768static const MCOperandInfo OperandInfo44[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, }; 769static const MCOperandInfo OperandInfo45[] = { { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 770static const MCOperandInfo OperandInfo46[] = { { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 771static const MCOperandInfo OperandInfo47[] = { { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 772static const MCOperandInfo OperandInfo48[] = { { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 773static const MCOperandInfo OperandInfo49[] = { { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 774static const MCOperandInfo OperandInfo50[] = { { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 775static const MCOperandInfo OperandInfo51[] = { { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 776static const MCOperandInfo OperandInfo52[] = { { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 777static const MCOperandInfo OperandInfo53[] = { { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 778static const MCOperandInfo OperandInfo54[] = { { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 779static const MCOperandInfo OperandInfo55[] = { { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 780static const MCOperandInfo OperandInfo56[] = { { LoongArch::GPRTRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 781static const MCOperandInfo OperandInfo57[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 782static const MCOperandInfo OperandInfo58[] = { { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 783static const MCOperandInfo OperandInfo59[] = { { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 784static const MCOperandInfo OperandInfo60[] = { { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 785static const MCOperandInfo OperandInfo61[] = { { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 786static const MCOperandInfo OperandInfo62[] = { { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 787static const MCOperandInfo OperandInfo63[] = { { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 788static const MCOperandInfo OperandInfo64[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 789static const MCOperandInfo OperandInfo65[] = { { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 790static const MCOperandInfo OperandInfo66[] = { { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 791static const MCOperandInfo OperandInfo67[] = { { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 792static const MCOperandInfo OperandInfo68[] = { { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 793static const MCOperandInfo OperandInfo69[] = { { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 794static const MCOperandInfo OperandInfo70[] = { { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 795static const MCOperandInfo OperandInfo71[] = { { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 796static const MCOperandInfo OperandInfo72[] = { { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 797static const MCOperandInfo OperandInfo73[] = { { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 798static const MCOperandInfo OperandInfo74[] = { { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 799static const MCOperandInfo OperandInfo75[] = { { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 800static const MCOperandInfo OperandInfo76[] = { { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 801static const MCOperandInfo OperandInfo77[] = { { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 802static const MCOperandInfo OperandInfo78[] = { { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 803static const MCOperandInfo OperandInfo79[] = { { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 804static const MCOperandInfo OperandInfo80[] = { { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 805static const MCOperandInfo OperandInfo81[] = { { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 806static const MCOperandInfo OperandInfo82[] = { { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 807static const MCOperandInfo OperandInfo83[] = { { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 808static const MCOperandInfo OperandInfo84[] = { { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 809static const MCOperandInfo OperandInfo85[] = { { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FCSRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 810static const MCOperandInfo OperandInfo86[] = { { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 811static const MCOperandInfo OperandInfo87[] = { { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 812static const MCOperandInfo OperandInfo88[] = { { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 813static const MCOperandInfo OperandInfo89[] = { { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 814static const MCOperandInfo OperandInfo90[] = { { LoongArch::FCSRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 815static const MCOperandInfo OperandInfo91[] = { { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 816static const MCOperandInfo OperandInfo92[] = { { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 817static const MCOperandInfo OperandInfo93[] = { { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 818static const MCOperandInfo OperandInfo94[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 819 820extern const MCInstrDesc LoongArchInsts[] = { 821 { 680, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo50 }, // Inst #680 = XORI 822 { 679, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #679 = XOR 823 { 678, 0, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #678 = TLBWR 824 { 677, 0, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #677 = TLBSRCH 825 { 676, 0, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #676 = TLBRD 826 { 675, 0, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #675 = TLBFLUSH 827 { 674, 0, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #674 = TLBFILL 828 { 673, 0, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #673 = TLBCLR 829 { 672, 1, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo2 }, // Inst #672 = SYSCALL 830 { 671, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #671 = SUB_W 831 { 670, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #670 = SUB_D 832 { 669, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo50 }, // Inst #669 = ST_W 833 { 668, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo50 }, // Inst #668 = ST_H 834 { 667, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo50 }, // Inst #667 = ST_D 835 { 666, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo50 }, // Inst #666 = ST_B 836 { 665, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo46 }, // Inst #665 = STX_W 837 { 664, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo46 }, // Inst #664 = STX_H 838 { 663, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo46 }, // Inst #663 = STX_D 839 { 662, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo46 }, // Inst #662 = STX_B 840 { 661, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo50 }, // Inst #661 = STPTR_W 841 { 660, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo50 }, // Inst #660 = STPTR_D 842 { 659, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo46 }, // Inst #659 = STLE_W 843 { 658, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo46 }, // Inst #658 = STLE_H 844 { 657, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo46 }, // Inst #657 = STLE_D 845 { 656, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo46 }, // Inst #656 = STLE_B 846 { 655, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo46 }, // Inst #655 = STGT_W 847 { 654, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo46 }, // Inst #654 = STGT_H 848 { 653, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo46 }, // Inst #653 = STGT_D 849 { 652, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo46 }, // Inst #652 = STGT_B 850 { 651, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #651 = SRL_W 851 { 650, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #650 = SRL_D 852 { 649, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo50 }, // Inst #649 = SRLI_W 853 { 648, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo50 }, // Inst #648 = SRLI_D 854 { 647, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #647 = SRA_W 855 { 646, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #646 = SRA_D 856 { 645, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo50 }, // Inst #645 = SRAI_W 857 { 644, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo50 }, // Inst #644 = SRAI_D 858 { 643, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo50 }, // Inst #643 = SLTUI 859 { 642, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #642 = SLTU 860 { 641, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo50 }, // Inst #641 = SLTI 861 { 640, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #640 = SLT 862 { 639, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #639 = SLL_W 863 { 638, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #638 = SLL_D 864 { 637, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo50 }, // Inst #637 = SLLI_W 865 { 636, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo50 }, // Inst #636 = SLLI_D 866 { 635, 4, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo66 }, // Inst #635 = SC_W 867 { 634, 4, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo66 }, // Inst #634 = SC_D 868 { 633, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #633 = ROTR_W 869 { 632, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #632 = ROTR_D 870 { 631, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo50 }, // Inst #631 = ROTRI_W 871 { 630, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo50 }, // Inst #630 = ROTRI_D 872 { 629, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo60 }, // Inst #629 = REVH_D 873 { 628, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo60 }, // Inst #628 = REVH_2W 874 { 627, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo60 }, // Inst #627 = REVB_D 875 { 626, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo60 }, // Inst #626 = REVB_4H 876 { 625, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo60 }, // Inst #625 = REVB_2W 877 { 624, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo60 }, // Inst #624 = REVB_2H 878 { 623, 2, 2, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo60 }, // Inst #623 = RDTIME_D 879 { 622, 2, 2, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo60 }, // Inst #622 = RDTIMEL_W 880 { 621, 2, 2, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo60 }, // Inst #621 = RDTIMEH_W 881 { 620, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo94 }, // Inst #620 = PRELDX 882 { 619, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo64 }, // Inst #619 = PRELD 883 { 618, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo47 }, // Inst #618 = PCALAU12I 884 { 617, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo47 }, // Inst #617 = PCADDU18I 885 { 616, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo47 }, // Inst #616 = PCADDU12I 886 { 615, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo47 }, // Inst #615 = PCADDI 887 { 614, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #614 = ORN 888 { 613, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo50 }, // Inst #613 = ORI 889 { 612, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #612 = OR 890 { 611, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #611 = NOR 891 { 610, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #610 = MUL_W 892 { 609, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #609 = MUL_D 893 { 608, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #608 = MULW_D_WU 894 { 607, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #607 = MULW_D_W 895 { 606, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #606 = MULH_WU 896 { 605, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #605 = MULH_W 897 { 604, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #604 = MULH_DU 898 { 603, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #603 = MULH_D 899 { 602, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo92 }, // Inst #602 = MOVGR2FR_W_64 900 { 601, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo93 }, // Inst #601 = MOVGR2FR_W 901 { 600, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo92 }, // Inst #600 = MOVGR2FR_D 902 { 599, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo91 }, // Inst #599 = MOVGR2FRH_W 903 { 598, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo90 }, // Inst #598 = MOVGR2FCSR 904 { 597, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo89 }, // Inst #597 = MOVGR2CF 905 { 596, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo87 }, // Inst #596 = MOVFRH2GR_S 906 { 595, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo87 }, // Inst #595 = MOVFR2GR_S_64 907 { 594, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo88 }, // Inst #594 = MOVFR2GR_S 908 { 593, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo87 }, // Inst #593 = MOVFR2GR_D 909 { 592, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo86 }, // Inst #592 = MOVFR2CF_S 910 { 591, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo85 }, // Inst #591 = MOVFCSR2GR 911 { 590, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo84 }, // Inst #590 = MOVCF2GR 912 { 589, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo83 }, // Inst #589 = MOVCF2FR_S 913 { 588, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo46 }, // Inst #588 = MOD_WU 914 { 587, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo46 }, // Inst #587 = MOD_W 915 { 586, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo46 }, // Inst #586 = MOD_DU 916 { 585, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo46 }, // Inst #585 = MOD_D 917 { 584, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo46 }, // Inst #584 = MASKNEZ 918 { 583, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo46 }, // Inst #583 = MASKEQZ 919 { 582, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo50 }, // Inst #582 = LU52I_D 920 { 581, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo65 }, // Inst #581 = LU32I_D 921 { 580, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo47 }, // Inst #580 = LU12I_W 922 { 579, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo50 }, // Inst #579 = LL_W 923 { 578, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo50 }, // Inst #578 = LL_D 924 { 577, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo50 }, // Inst #577 = LD_WU 925 { 576, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo50 }, // Inst #576 = LD_W 926 { 575, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo50 }, // Inst #575 = LD_HU 927 { 574, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo50 }, // Inst #574 = LD_H 928 { 573, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo50 }, // Inst #573 = LD_D 929 { 572, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo50 }, // Inst #572 = LD_BU 930 { 571, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo50 }, // Inst #571 = LD_B 931 { 570, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo46 }, // Inst #570 = LDX_WU 932 { 569, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo46 }, // Inst #569 = LDX_W 933 { 568, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo46 }, // Inst #568 = LDX_HU 934 { 567, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo46 }, // Inst #567 = LDX_H 935 { 566, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo46 }, // Inst #566 = LDX_D 936 { 565, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo46 }, // Inst #565 = LDX_BU 937 { 564, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo46 }, // Inst #564 = LDX_B 938 { 563, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo50 }, // Inst #563 = LDPTR_W 939 { 562, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo50 }, // Inst #562 = LDPTR_D 940 { 561, 2, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo47 }, // Inst #561 = LDPTE 941 { 560, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo46 }, // Inst #560 = LDLE_W 942 { 559, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo46 }, // Inst #559 = LDLE_H 943 { 558, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo46 }, // Inst #558 = LDLE_D 944 { 557, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo46 }, // Inst #557 = LDLE_B 945 { 556, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo46 }, // Inst #556 = LDGT_W 946 { 555, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo46 }, // Inst #555 = LDGT_H 947 { 554, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo46 }, // Inst #554 = LDGT_D 948 { 553, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo46 }, // Inst #553 = LDGT_B 949 { 552, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo50 }, // Inst #552 = LDDIR 950 { 551, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo50 }, // Inst #551 = JIRL 951 { 550, 2, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo60 }, // Inst #550 = IOCSRWR_W 952 { 549, 2, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo60 }, // Inst #549 = IOCSRWR_H 953 { 548, 2, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo60 }, // Inst #548 = IOCSRWR_D 954 { 547, 2, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo60 }, // Inst #547 = IOCSRWR_B 955 { 546, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo60 }, // Inst #546 = IOCSRRD_W 956 { 545, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo60 }, // Inst #545 = IOCSRRD_H 957 { 544, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo60 }, // Inst #544 = IOCSRRD_D 958 { 543, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo60 }, // Inst #543 = IOCSRRD_B 959 { 542, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo50 }, // Inst #542 = INVTLB 960 { 541, 1, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo2 }, // Inst #541 = IDLE 961 { 540, 1, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo2 }, // Inst #540 = IBAR 962 { 539, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo68 }, // Inst #539 = FTINT_W_S 963 { 538, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo74 }, // Inst #538 = FTINT_W_D 964 { 537, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo73 }, // Inst #537 = FTINT_L_S 965 { 536, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo67 }, // Inst #536 = FTINT_L_D 966 { 535, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo68 }, // Inst #535 = FTINTRZ_W_S 967 { 534, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo74 }, // Inst #534 = FTINTRZ_W_D 968 { 533, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo73 }, // Inst #533 = FTINTRZ_L_S 969 { 532, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo67 }, // Inst #532 = FTINTRZ_L_D 970 { 531, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo68 }, // Inst #531 = FTINTRP_W_S 971 { 530, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo74 }, // Inst #530 = FTINTRP_W_D 972 { 529, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo73 }, // Inst #529 = FTINTRP_L_S 973 { 528, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo67 }, // Inst #528 = FTINTRP_L_D 974 { 527, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo68 }, // Inst #527 = FTINTRNE_W_S 975 { 526, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo74 }, // Inst #526 = FTINTRNE_W_D 976 { 525, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo73 }, // Inst #525 = FTINTRNE_L_S 977 { 524, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo67 }, // Inst #524 = FTINTRNE_L_D 978 { 523, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo68 }, // Inst #523 = FTINTRM_W_S 979 { 522, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo74 }, // Inst #522 = FTINTRM_W_D 980 { 521, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo73 }, // Inst #521 = FTINTRM_L_S 981 { 520, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo67 }, // Inst #520 = FTINTRM_L_D 982 { 519, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo70 }, // Inst #519 = FSUB_S 983 { 518, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo69 }, // Inst #518 = FSUB_D 984 { 517, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo78 }, // Inst #517 = FST_S 985 { 516, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo77 }, // Inst #516 = FST_D 986 { 515, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo76 }, // Inst #515 = FSTX_S 987 { 514, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo75 }, // Inst #514 = FSTX_D 988 { 513, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo76 }, // Inst #513 = FSTLE_S 989 { 512, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo75 }, // Inst #512 = FSTLE_D 990 { 511, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo76 }, // Inst #511 = FSTGT_S 991 { 510, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo75 }, // Inst #510 = FSTGT_D 992 { 509, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo68 }, // Inst #509 = FSQRT_S 993 { 508, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo67 }, // Inst #508 = FSQRT_D 994 { 507, 4, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo82 }, // Inst #507 = FSEL_S 995 { 506, 4, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo81 }, // Inst #506 = FSEL_D 996 { 505, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo70 }, // Inst #505 = FSCALEB_S 997 { 504, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo69 }, // Inst #504 = FSCALEB_D 998 { 503, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo68 }, // Inst #503 = FRSQRT_S 999 { 502, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo67 }, // Inst #502 = FRSQRT_D 1000 { 501, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo68 }, // Inst #501 = FRINT_S 1001 { 500, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo67 }, // Inst #500 = FRINT_D 1002 { 499, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo68 }, // Inst #499 = FRECIP_S 1003 { 498, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo67 }, // Inst #498 = FRECIP_D 1004 { 497, 4, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo80 }, // Inst #497 = FNMSUB_S 1005 { 496, 4, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo79 }, // Inst #496 = FNMSUB_D 1006 { 495, 4, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo80 }, // Inst #495 = FNMADD_S 1007 { 494, 4, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo79 }, // Inst #494 = FNMADD_D 1008 { 493, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo68 }, // Inst #493 = FNEG_S 1009 { 492, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo67 }, // Inst #492 = FNEG_D 1010 { 491, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo70 }, // Inst #491 = FMUL_S 1011 { 490, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo69 }, // Inst #490 = FMUL_D 1012 { 489, 4, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo80 }, // Inst #489 = FMSUB_S 1013 { 488, 4, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo79 }, // Inst #488 = FMSUB_D 1014 { 487, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo68 }, // Inst #487 = FMOV_S 1015 { 486, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo67 }, // Inst #486 = FMOV_D 1016 { 485, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo70 }, // Inst #485 = FMIN_S 1017 { 484, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo69 }, // Inst #484 = FMIN_D 1018 { 483, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo70 }, // Inst #483 = FMINA_S 1019 { 482, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo69 }, // Inst #482 = FMINA_D 1020 { 481, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo70 }, // Inst #481 = FMAX_S 1021 { 480, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo69 }, // Inst #480 = FMAX_D 1022 { 479, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo70 }, // Inst #479 = FMAXA_S 1023 { 478, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo69 }, // Inst #478 = FMAXA_D 1024 { 477, 4, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo80 }, // Inst #477 = FMADD_S 1025 { 476, 4, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo79 }, // Inst #476 = FMADD_D 1026 { 475, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo68 }, // Inst #475 = FLOGB_S 1027 { 474, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo67 }, // Inst #474 = FLOGB_D 1028 { 473, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo78 }, // Inst #473 = FLD_S 1029 { 472, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo77 }, // Inst #472 = FLD_D 1030 { 471, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo76 }, // Inst #471 = FLDX_S 1031 { 470, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo75 }, // Inst #470 = FLDX_D 1032 { 469, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo76 }, // Inst #469 = FLDLE_S 1033 { 468, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo75 }, // Inst #468 = FLDLE_D 1034 { 467, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo76 }, // Inst #467 = FLDGT_S 1035 { 466, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo75 }, // Inst #466 = FLDGT_D 1036 { 465, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo68 }, // Inst #465 = FFINT_S_W 1037 { 464, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo74 }, // Inst #464 = FFINT_S_L 1038 { 463, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo73 }, // Inst #463 = FFINT_D_W 1039 { 462, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo67 }, // Inst #462 = FFINT_D_L 1040 { 461, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo70 }, // Inst #461 = FDIV_S 1041 { 460, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo69 }, // Inst #460 = FDIV_D 1042 { 459, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo74 }, // Inst #459 = FCVT_S_D 1043 { 458, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo73 }, // Inst #458 = FCVT_D_S 1044 { 457, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo70 }, // Inst #457 = FCOPYSIGN_S 1045 { 456, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo69 }, // Inst #456 = FCOPYSIGN_D 1046 { 455, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo72 }, // Inst #455 = FCMP_SUN_S 1047 { 454, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo71 }, // Inst #454 = FCMP_SUN_D 1048 { 453, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo72 }, // Inst #453 = FCMP_SUNE_S 1049 { 452, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo71 }, // Inst #452 = FCMP_SUNE_D 1050 { 451, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo72 }, // Inst #451 = FCMP_SULT_S 1051 { 450, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo71 }, // Inst #450 = FCMP_SULT_D 1052 { 449, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo72 }, // Inst #449 = FCMP_SULE_S 1053 { 448, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo71 }, // Inst #448 = FCMP_SULE_D 1054 { 447, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo72 }, // Inst #447 = FCMP_SUEQ_S 1055 { 446, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo71 }, // Inst #446 = FCMP_SUEQ_D 1056 { 445, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo72 }, // Inst #445 = FCMP_SOR_S 1057 { 444, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo71 }, // Inst #444 = FCMP_SOR_D 1058 { 443, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo72 }, // Inst #443 = FCMP_SNE_S 1059 { 442, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo71 }, // Inst #442 = FCMP_SNE_D 1060 { 441, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo72 }, // Inst #441 = FCMP_SLT_S 1061 { 440, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo71 }, // Inst #440 = FCMP_SLT_D 1062 { 439, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo72 }, // Inst #439 = FCMP_SLE_S 1063 { 438, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo71 }, // Inst #438 = FCMP_SLE_D 1064 { 437, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo72 }, // Inst #437 = FCMP_SEQ_S 1065 { 436, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo71 }, // Inst #436 = FCMP_SEQ_D 1066 { 435, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo72 }, // Inst #435 = FCMP_SAF_S 1067 { 434, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo71 }, // Inst #434 = FCMP_SAF_D 1068 { 433, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo72 }, // Inst #433 = FCMP_CUN_S 1069 { 432, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo71 }, // Inst #432 = FCMP_CUN_D 1070 { 431, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo72 }, // Inst #431 = FCMP_CUNE_S 1071 { 430, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo71 }, // Inst #430 = FCMP_CUNE_D 1072 { 429, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo72 }, // Inst #429 = FCMP_CULT_S 1073 { 428, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo71 }, // Inst #428 = FCMP_CULT_D 1074 { 427, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo72 }, // Inst #427 = FCMP_CULE_S 1075 { 426, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo71 }, // Inst #426 = FCMP_CULE_D 1076 { 425, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo72 }, // Inst #425 = FCMP_CUEQ_S 1077 { 424, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo71 }, // Inst #424 = FCMP_CUEQ_D 1078 { 423, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo72 }, // Inst #423 = FCMP_COR_S 1079 { 422, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo71 }, // Inst #422 = FCMP_COR_D 1080 { 421, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo72 }, // Inst #421 = FCMP_CNE_S 1081 { 420, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo71 }, // Inst #420 = FCMP_CNE_D 1082 { 419, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo72 }, // Inst #419 = FCMP_CLT_S 1083 { 418, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo71 }, // Inst #418 = FCMP_CLT_D 1084 { 417, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo72 }, // Inst #417 = FCMP_CLE_S 1085 { 416, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo71 }, // Inst #416 = FCMP_CLE_D 1086 { 415, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo72 }, // Inst #415 = FCMP_CEQ_S 1087 { 414, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo71 }, // Inst #414 = FCMP_CEQ_D 1088 { 413, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo72 }, // Inst #413 = FCMP_CAF_S 1089 { 412, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo71 }, // Inst #412 = FCMP_CAF_D 1090 { 411, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo68 }, // Inst #411 = FCLASS_S 1091 { 410, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo67 }, // Inst #410 = FCLASS_D 1092 { 409, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo70 }, // Inst #409 = FADD_S 1093 { 408, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo69 }, // Inst #408 = FADD_D 1094 { 407, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo68 }, // Inst #407 = FABS_S 1095 { 406, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo67 }, // Inst #406 = FABS_D 1096 { 405, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo60 }, // Inst #405 = EXT_W_H 1097 { 404, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo60 }, // Inst #404 = EXT_W_B 1098 { 403, 0, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #403 = ERTN 1099 { 402, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo46 }, // Inst #402 = DIV_WU 1100 { 401, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo46 }, // Inst #401 = DIV_W 1101 { 400, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo46 }, // Inst #400 = DIV_DU 1102 { 399, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo46 }, // Inst #399 = DIV_D 1103 { 398, 1, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo2 }, // Inst #398 = DBCL 1104 { 397, 1, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo2 }, // Inst #397 = DBAR 1105 { 396, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo60 }, // Inst #396 = CTZ_W 1106 { 395, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo60 }, // Inst #395 = CTZ_D 1107 { 394, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo60 }, // Inst #394 = CTO_W 1108 { 393, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo60 }, // Inst #393 = CTO_D 1109 { 392, 4, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo66 }, // Inst #392 = CSRXCHG 1110 { 391, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo65 }, // Inst #391 = CSRWR 1111 { 390, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo47 }, // Inst #390 = CSRRD 1112 { 389, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #389 = CRC_W_W_W 1113 { 388, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #388 = CRC_W_H_W 1114 { 387, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #387 = CRC_W_D_W 1115 { 386, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #386 = CRC_W_B_W 1116 { 385, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #385 = CRCC_W_W_W 1117 { 384, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #384 = CRCC_W_H_W 1118 { 383, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #383 = CRCC_W_D_W 1119 { 382, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #382 = CRCC_W_B_W 1120 { 381, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo60 }, // Inst #381 = CPUCFG 1121 { 380, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo60 }, // Inst #380 = CLZ_W 1122 { 379, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo60 }, // Inst #379 = CLZ_D 1123 { 378, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo60 }, // Inst #378 = CLO_W 1124 { 377, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo60 }, // Inst #377 = CLO_D 1125 { 376, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo64 }, // Inst #376 = CACOP 1126 { 375, 4, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo58 }, // Inst #375 = BYTEPICK_W 1127 { 374, 4, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo58 }, // Inst #374 = BYTEPICK_D 1128 { 373, 4, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo63 }, // Inst #373 = BSTRPICK_W 1129 { 372, 4, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo63 }, // Inst #372 = BSTRPICK_D 1130 { 371, 5, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo62 }, // Inst #371 = BSTRINS_W 1131 { 370, 5, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo62 }, // Inst #370 = BSTRINS_D 1132 { 369, 1, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo2 }, // Inst #369 = BREAK 1133 { 368, 2, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, OperandInfo47 }, // Inst #368 = BNEZ 1134 { 367, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, OperandInfo50 }, // Inst #367 = BNE 1135 { 366, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, OperandInfo50 }, // Inst #366 = BLTU 1136 { 365, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, OperandInfo50 }, // Inst #365 = BLT 1137 { 364, 1, 0, 4, 0, 0, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList3, OperandInfo2 }, // Inst #364 = BL 1138 { 363, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo60 }, // Inst #363 = BITREV_W 1139 { 362, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo60 }, // Inst #362 = BITREV_D 1140 { 361, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo60 }, // Inst #361 = BITREV_8B 1141 { 360, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo60 }, // Inst #360 = BITREV_4B 1142 { 359, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, OperandInfo50 }, // Inst #359 = BGEU 1143 { 358, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, OperandInfo50 }, // Inst #358 = BGE 1144 { 357, 2, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, OperandInfo47 }, // Inst #357 = BEQZ 1145 { 356, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, OperandInfo50 }, // Inst #356 = BEQ 1146 { 355, 2, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo61 }, // Inst #355 = BCNEZ 1147 { 354, 2, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo61 }, // Inst #354 = BCEQZ 1148 { 353, 1, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo2 }, // Inst #353 = B 1149 { 352, 2, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo60 }, // Inst #352 = ASRTLE_D 1150 { 351, 2, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo60 }, // Inst #351 = ASRTGT_D 1151 { 350, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #350 = ANDN 1152 { 349, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo50 }, // Inst #349 = ANDI 1153 { 348, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #348 = AND 1154 { 347, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo59 }, // Inst #347 = AMXOR_W 1155 { 346, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo59 }, // Inst #346 = AMXOR_DB_W 1156 { 345, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo59 }, // Inst #345 = AMXOR_DB_D 1157 { 344, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo59 }, // Inst #344 = AMXOR_D 1158 { 343, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo59 }, // Inst #343 = AMSWAP_W 1159 { 342, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo59 }, // Inst #342 = AMSWAP_DB_W 1160 { 341, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo59 }, // Inst #341 = AMSWAP_DB_D 1161 { 340, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo59 }, // Inst #340 = AMSWAP_D 1162 { 339, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo59 }, // Inst #339 = AMOR_W 1163 { 338, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo59 }, // Inst #338 = AMOR_DB_W 1164 { 337, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo59 }, // Inst #337 = AMOR_DB_D 1165 { 336, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo59 }, // Inst #336 = AMOR_D 1166 { 335, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo59 }, // Inst #335 = AMMIN_WU 1167 { 334, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo59 }, // Inst #334 = AMMIN_W 1168 { 333, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo59 }, // Inst #333 = AMMIN_DU 1169 { 332, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo59 }, // Inst #332 = AMMIN_DB_WU 1170 { 331, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo59 }, // Inst #331 = AMMIN_DB_W 1171 { 330, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo59 }, // Inst #330 = AMMIN_DB_DU 1172 { 329, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo59 }, // Inst #329 = AMMIN_DB_D 1173 { 328, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo59 }, // Inst #328 = AMMIN_D 1174 { 327, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo59 }, // Inst #327 = AMMAX_WU 1175 { 326, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo59 }, // Inst #326 = AMMAX_W 1176 { 325, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo59 }, // Inst #325 = AMMAX_DU 1177 { 324, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo59 }, // Inst #324 = AMMAX_DB_WU 1178 { 323, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo59 }, // Inst #323 = AMMAX_DB_W 1179 { 322, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo59 }, // Inst #322 = AMMAX_DB_DU 1180 { 321, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo59 }, // Inst #321 = AMMAX_DB_D 1181 { 320, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo59 }, // Inst #320 = AMMAX_D 1182 { 319, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo59 }, // Inst #319 = AMAND_W 1183 { 318, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo59 }, // Inst #318 = AMAND_DB_W 1184 { 317, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo59 }, // Inst #317 = AMAND_DB_D 1185 { 316, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo59 }, // Inst #316 = AMAND_D 1186 { 315, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo59 }, // Inst #315 = AMADD_W 1187 { 314, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo59 }, // Inst #314 = AMADD_DB_W 1188 { 313, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo59 }, // Inst #313 = AMADD_DB_D 1189 { 312, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo59 }, // Inst #312 = AMADD_D 1190 { 311, 4, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo58 }, // Inst #311 = ALSL_WU 1191 { 310, 4, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo58 }, // Inst #310 = ALSL_W 1192 { 309, 4, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo58 }, // Inst #309 = ALSL_D 1193 { 308, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #308 = ADD_W 1194 { 307, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #307 = ADD_D 1195 { 306, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo50 }, // Inst #306 = ADDU16I_D 1196 { 305, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo50 }, // Inst #305 = ADDI_W 1197 { 304, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo50 }, // Inst #304 = ADDI_D 1198 { 303, 2, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo57 }, // Inst #303 = WRFCSR 1199 { 302, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo47 }, // Inst #302 = RDFCSR 1200 { 301, 0, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #301 = PseudoUNIMP 1201 { 300, 1, 0, 4, 0, 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, OperandInfo56 }, // Inst #300 = PseudoTAILIndirect 1202 { 299, 1, 0, 4, 0, 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, OperandInfo2 }, // Inst #299 = PseudoTAIL 1203 { 298, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo51 }, // Inst #298 = PseudoST_CFR 1204 { 297, 0, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr }, // Inst #297 = PseudoRET 1205 { 296, 7, 2, 44, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo55 }, // Inst #296 = PseudoMaskedCmpXchg32 1206 { 295, 6, 2, 36, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo52 }, // Inst #295 = PseudoMaskedAtomicSwap32 1207 { 294, 7, 3, 48, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo54 }, // Inst #294 = PseudoMaskedAtomicLoadUMin32 1208 { 293, 7, 3, 48, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo54 }, // Inst #293 = PseudoMaskedAtomicLoadUMax32 1209 { 292, 6, 2, 36, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo52 }, // Inst #292 = PseudoMaskedAtomicLoadSub32 1210 { 291, 6, 2, 36, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo52 }, // Inst #291 = PseudoMaskedAtomicLoadNand32 1211 { 290, 8, 3, 56, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo53 }, // Inst #290 = PseudoMaskedAtomicLoadMin32 1212 { 289, 8, 3, 56, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo53 }, // Inst #289 = PseudoMaskedAtomicLoadMax32 1213 { 288, 6, 2, 36, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo52 }, // Inst #288 = PseudoMaskedAtomicLoadAdd32 1214 { 287, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo47 }, // Inst #287 = PseudoLI_W 1215 { 286, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo47 }, // Inst #286 = PseudoLI_D 1216 { 285, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo51 }, // Inst #285 = PseudoLD_CFR 1217 { 284, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo47 }, // Inst #284 = PseudoLA_TLS_LE 1218 { 283, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo50 }, // Inst #283 = PseudoLA_TLS_LD_LARGE 1219 { 282, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo47 }, // Inst #282 = PseudoLA_TLS_LD 1220 { 281, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo50 }, // Inst #281 = PseudoLA_TLS_IE_LARGE 1221 { 280, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo47 }, // Inst #280 = PseudoLA_TLS_IE 1222 { 279, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo50 }, // Inst #279 = PseudoLA_TLS_GD_LARGE 1223 { 278, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo47 }, // Inst #278 = PseudoLA_TLS_GD 1224 { 277, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo50 }, // Inst #277 = PseudoLA_PCREL_LARGE 1225 { 276, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo47 }, // Inst #276 = PseudoLA_PCREL 1226 { 275, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo50 }, // Inst #275 = PseudoLA_GOT_LARGE 1227 { 274, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo47 }, // Inst #274 = PseudoLA_GOT 1228 { 273, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo50 }, // Inst #273 = PseudoLA_ABS_LARGE 1229 { 272, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo47 }, // Inst #272 = PseudoLA_ABS 1230 { 271, 2, 0, 4, 0, 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, OperandInfo47 }, // Inst #271 = PseudoJIRL_TAIL 1231 { 270, 2, 0, 4, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList3, OperandInfo47 }, // Inst #270 = PseudoJIRL_CALL 1232 { 269, 5, 2, 36, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo49 }, // Inst #269 = PseudoCmpXchg64 1233 { 268, 5, 2, 36, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo49 }, // Inst #268 = PseudoCmpXchg32 1234 { 267, 1, 0, 4, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL, ImplicitList3, OperandInfo48 }, // Inst #267 = PseudoCALLIndirect 1235 { 266, 1, 0, 4, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL, ImplicitList3, OperandInfo2 }, // Inst #266 = PseudoCALL 1236 { 265, 1, 0, 4, 0, 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, OperandInfo2 }, // Inst #265 = PseudoB_TAIL 1237 { 264, 2, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, OperandInfo47 }, // Inst #264 = PseudoBRIND 1238 { 263, 1, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, OperandInfo2 }, // Inst #263 = PseudoBR 1239 { 262, 5, 2, 24, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo45 }, // Inst #262 = PseudoAtomicSwap32 1240 { 261, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo46 }, // Inst #261 = PseudoAtomicStoreW 1241 { 260, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo46 }, // Inst #260 = PseudoAtomicStoreD 1242 { 259, 5, 2, 24, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo45 }, // Inst #259 = PseudoAtomicLoadXor32 1243 { 258, 5, 2, 24, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo45 }, // Inst #258 = PseudoAtomicLoadSub32 1244 { 257, 5, 2, 24, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo45 }, // Inst #257 = PseudoAtomicLoadOr32 1245 { 256, 5, 2, 24, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo45 }, // Inst #256 = PseudoAtomicLoadNand64 1246 { 255, 5, 2, 24, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo45 }, // Inst #255 = PseudoAtomicLoadNand32 1247 { 254, 5, 2, 24, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo45 }, // Inst #254 = PseudoAtomicLoadAnd32 1248 { 253, 5, 2, 24, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo45 }, // Inst #253 = PseudoAtomicLoadAdd32 1249 { 252, 2, 0, 4, 0, 1, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, ImplicitList1, OperandInfo10 }, // Inst #252 = ADJCALLSTACKUP 1250 { 251, 2, 0, 4, 0, 1, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, ImplicitList1, OperandInfo10 }, // Inst #251 = ADJCALLSTACKDOWN 1251 { 250, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo44 }, // Inst #250 = G_UBFX 1252 { 249, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo44 }, // Inst #249 = G_SBFX 1253 { 248, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #248 = G_VECREDUCE_UMIN 1254 { 247, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #247 = G_VECREDUCE_UMAX 1255 { 246, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #246 = G_VECREDUCE_SMIN 1256 { 245, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #245 = G_VECREDUCE_SMAX 1257 { 244, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #244 = G_VECREDUCE_XOR 1258 { 243, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #243 = G_VECREDUCE_OR 1259 { 242, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #242 = G_VECREDUCE_AND 1260 { 241, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #241 = G_VECREDUCE_MUL 1261 { 240, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #240 = G_VECREDUCE_ADD 1262 { 239, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #239 = G_VECREDUCE_FMIN 1263 { 238, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #238 = G_VECREDUCE_FMAX 1264 { 237, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #237 = G_VECREDUCE_FMUL 1265 { 236, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #236 = G_VECREDUCE_FADD 1266 { 235, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo40 }, // Inst #235 = G_VECREDUCE_SEQ_FMUL 1267 { 234, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo40 }, // Inst #234 = G_VECREDUCE_SEQ_FADD 1268 { 233, 3, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo22 }, // Inst #233 = G_BZERO 1269 { 232, 4, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo43 }, // Inst #232 = G_MEMSET 1270 { 231, 4, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo43 }, // Inst #231 = G_MEMMOVE 1271 { 230, 3, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo40 }, // Inst #230 = G_MEMCPY_INLINE 1272 { 229, 4, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo43 }, // Inst #229 = G_MEMCPY 1273 { 228, 2, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, OperandInfo42 }, // Inst #228 = G_WRITE_REGISTER 1274 { 227, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, OperandInfo21 }, // Inst #227 = G_READ_REGISTER 1275 { 226, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo25 }, // Inst #226 = G_STRICT_FSQRT 1276 { 225, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo19 }, // Inst #225 = G_STRICT_FMA 1277 { 224, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo18 }, // Inst #224 = G_STRICT_FREM 1278 { 223, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo18 }, // Inst #223 = G_STRICT_FDIV 1279 { 222, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo18 }, // Inst #222 = G_STRICT_FMUL 1280 { 221, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo18 }, // Inst #221 = G_STRICT_FSUB 1281 { 220, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo18 }, // Inst #220 = G_STRICT_FADD 1282 { 219, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo26 }, // Inst #219 = G_DYN_STACKALLOC 1283 { 218, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo21 }, // Inst #218 = G_JUMP_TABLE 1284 { 217, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo21 }, // Inst #217 = G_BLOCK_ADDR 1285 { 216, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #216 = G_ADDRSPACE_CAST 1286 { 215, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #215 = G_FNEARBYINT 1287 { 214, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #214 = G_FRINT 1288 { 213, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #213 = G_FFLOOR 1289 { 212, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #212 = G_FSQRT 1290 { 211, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #211 = G_FSIN 1291 { 210, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #210 = G_FCOS 1292 { 209, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #209 = G_FCEIL 1293 { 208, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #208 = G_BITREVERSE 1294 { 207, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #207 = G_BSWAP 1295 { 206, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #206 = G_CTPOP 1296 { 205, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #205 = G_CTLZ_ZERO_UNDEF 1297 { 204, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #204 = G_CTLZ 1298 { 203, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #203 = G_CTTZ_ZERO_UNDEF 1299 { 202, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #202 = G_CTTZ 1300 { 201, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo41 }, // Inst #201 = G_SHUFFLE_VECTOR 1301 { 200, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo40 }, // Inst #200 = G_EXTRACT_VECTOR_ELT 1302 { 199, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo39 }, // Inst #199 = G_INSERT_VECTOR_ELT 1303 { 198, 3, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, OperandInfo38 }, // Inst #198 = G_BRJT 1304 { 197, 1, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, OperandInfo2 }, // Inst #197 = G_BR 1305 { 196, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #196 = G_LLROUND 1306 { 195, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #195 = G_LROUND 1307 { 194, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #194 = G_ABS 1308 { 193, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #193 = G_UMAX 1309 { 192, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #192 = G_UMIN 1310 { 191, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #191 = G_SMAX 1311 { 190, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #190 = G_SMIN 1312 { 189, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo33 }, // Inst #189 = G_PTRMASK 1313 { 188, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo33 }, // Inst #188 = G_PTR_ADD 1314 { 187, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #187 = G_FMAXIMUM 1315 { 186, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #186 = G_FMINIMUM 1316 { 185, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #185 = G_FMAXNUM_IEEE 1317 { 184, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #184 = G_FMINNUM_IEEE 1318 { 183, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #183 = G_FMAXNUM 1319 { 182, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #182 = G_FMINNUM 1320 { 181, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #181 = G_FCANONICALIZE 1321 { 180, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo32 }, // Inst #180 = G_IS_FPCLASS 1322 { 179, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo33 }, // Inst #179 = G_FCOPYSIGN 1323 { 178, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #178 = G_FABS 1324 { 177, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #177 = G_UITOFP 1325 { 176, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #176 = G_SITOFP 1326 { 175, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #175 = G_FPTOUI 1327 { 174, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #174 = G_FPTOSI 1328 { 173, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #173 = G_FPTRUNC 1329 { 172, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #172 = G_FPEXT 1330 { 171, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #171 = G_FNEG 1331 { 170, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #170 = G_FLOG10 1332 { 169, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #169 = G_FLOG2 1333 { 168, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #168 = G_FLOG 1334 { 167, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #167 = G_FEXP2 1335 { 166, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #166 = G_FEXP 1336 { 165, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo33 }, // Inst #165 = G_FPOWI 1337 { 164, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo18 }, // Inst #164 = G_FPOW 1338 { 163, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo18 }, // Inst #163 = G_FREM 1339 { 162, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo18 }, // Inst #162 = G_FDIV 1340 { 161, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo19 }, // Inst #161 = G_FMAD 1341 { 160, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo19 }, // Inst #160 = G_FMA 1342 { 159, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #159 = G_FMUL 1343 { 158, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo18 }, // Inst #158 = G_FSUB 1344 { 157, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #157 = G_FADD 1345 { 156, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo37 }, // Inst #156 = G_UDIVFIXSAT 1346 { 155, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo37 }, // Inst #155 = G_SDIVFIXSAT 1347 { 154, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo37 }, // Inst #154 = G_UDIVFIX 1348 { 153, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo37 }, // Inst #153 = G_SDIVFIX 1349 { 152, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo37 }, // Inst #152 = G_UMULFIXSAT 1350 { 151, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo37 }, // Inst #151 = G_SMULFIXSAT 1351 { 150, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo37 }, // Inst #150 = G_UMULFIX 1352 { 149, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo37 }, // Inst #149 = G_SMULFIX 1353 { 148, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo33 }, // Inst #148 = G_SSHLSAT 1354 { 147, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo33 }, // Inst #147 = G_USHLSAT 1355 { 146, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo18 }, // Inst #146 = G_SSUBSAT 1356 { 145, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo18 }, // Inst #145 = G_USUBSAT 1357 { 144, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #144 = G_SADDSAT 1358 { 143, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #143 = G_UADDSAT 1359 { 142, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #142 = G_SMULH 1360 { 141, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #141 = G_UMULH 1361 { 140, 4, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo30 }, // Inst #140 = G_SMULO 1362 { 139, 4, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo30 }, // Inst #139 = G_UMULO 1363 { 138, 5, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo36 }, // Inst #138 = G_SSUBE 1364 { 137, 4, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo30 }, // Inst #137 = G_SSUBO 1365 { 136, 5, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo36 }, // Inst #136 = G_SADDE 1366 { 135, 4, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo30 }, // Inst #135 = G_SADDO 1367 { 134, 5, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo36 }, // Inst #134 = G_USUBE 1368 { 133, 4, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo30 }, // Inst #133 = G_USUBO 1369 { 132, 5, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo36 }, // Inst #132 = G_UADDE 1370 { 131, 4, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo30 }, // Inst #131 = G_UADDO 1371 { 130, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo30 }, // Inst #130 = G_SELECT 1372 { 129, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo35 }, // Inst #129 = G_FCMP 1373 { 128, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo35 }, // Inst #128 = G_ICMP 1374 { 127, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo33 }, // Inst #127 = G_ROTL 1375 { 126, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo33 }, // Inst #126 = G_ROTR 1376 { 125, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo34 }, // Inst #125 = G_FSHR 1377 { 124, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo34 }, // Inst #124 = G_FSHL 1378 { 123, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo33 }, // Inst #123 = G_ASHR 1379 { 122, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo33 }, // Inst #122 = G_LSHR 1380 { 121, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo33 }, // Inst #121 = G_SHL 1381 { 120, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #120 = G_ZEXT 1382 { 119, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo17 }, // Inst #119 = G_SEXT_INREG 1383 { 118, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #118 = G_SEXT 1384 { 117, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo32 }, // Inst #117 = G_VAARG 1385 { 116, 1, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo20 }, // Inst #116 = G_VASTART 1386 { 115, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo21 }, // Inst #115 = G_FCONSTANT 1387 { 114, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo21 }, // Inst #114 = G_CONSTANT 1388 { 113, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #113 = G_TRUNC 1389 { 112, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #112 = G_ANYEXT 1390 { 111, 1, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, OperandInfo2 }, // Inst #111 = G_INTRINSIC_W_SIDE_EFFECTS 1391 { 110, 1, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, OperandInfo2 }, // Inst #110 = G_INTRINSIC 1392 { 109, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr }, // Inst #109 = G_INVOKE_REGION_START 1393 { 108, 1, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, OperandInfo20 }, // Inst #108 = G_BRINDIRECT 1394 { 107, 2, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, OperandInfo21 }, // Inst #107 = G_BRCOND 1395 { 106, 2, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo10 }, // Inst #106 = G_FENCE 1396 { 105, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #105 = G_ATOMICRMW_UDEC_WRAP 1397 { 104, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #104 = G_ATOMICRMW_UINC_WRAP 1398 { 103, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #103 = G_ATOMICRMW_FMIN 1399 { 102, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #102 = G_ATOMICRMW_FMAX 1400 { 101, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #101 = G_ATOMICRMW_FSUB 1401 { 100, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #100 = G_ATOMICRMW_FADD 1402 { 99, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #99 = G_ATOMICRMW_UMIN 1403 { 98, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #98 = G_ATOMICRMW_UMAX 1404 { 97, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #97 = G_ATOMICRMW_MIN 1405 { 96, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #96 = G_ATOMICRMW_MAX 1406 { 95, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #95 = G_ATOMICRMW_XOR 1407 { 94, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #94 = G_ATOMICRMW_OR 1408 { 93, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #93 = G_ATOMICRMW_NAND 1409 { 92, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #92 = G_ATOMICRMW_AND 1410 { 91, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #91 = G_ATOMICRMW_SUB 1411 { 90, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #90 = G_ATOMICRMW_ADD 1412 { 89, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #89 = G_ATOMICRMW_XCHG 1413 { 88, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo30 }, // Inst #88 = G_ATOMIC_CMPXCHG 1414 { 87, 5, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo29 }, // Inst #87 = G_ATOMIC_CMPXCHG_WITH_SUCCESS 1415 { 86, 5, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo28 }, // Inst #86 = G_INDEXED_STORE 1416 { 85, 2, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo23 }, // Inst #85 = G_STORE 1417 { 84, 5, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo27 }, // Inst #84 = G_INDEXED_ZEXTLOAD 1418 { 83, 5, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo27 }, // Inst #83 = G_INDEXED_SEXTLOAD 1419 { 82, 5, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo27 }, // Inst #82 = G_INDEXED_LOAD 1420 { 81, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo23 }, // Inst #81 = G_ZEXTLOAD 1421 { 80, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo23 }, // Inst #80 = G_SEXTLOAD 1422 { 79, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo23 }, // Inst #79 = G_LOAD 1423 { 78, 1, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo20 }, // Inst #78 = G_READCYCLECOUNTER 1424 { 77, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #77 = G_INTRINSIC_ROUNDEVEN 1425 { 76, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #76 = G_INTRINSIC_LRINT 1426 { 75, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #75 = G_INTRINSIC_ROUND 1427 { 74, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #74 = G_INTRINSIC_TRUNC 1428 { 73, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo26 }, // Inst #73 = G_INTRINSIC_FPTRUNC_ROUND 1429 { 72, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #72 = G_FREEZE 1430 { 71, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #71 = G_BITCAST 1431 { 70, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #70 = G_INTTOPTR 1432 { 69, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #69 = G_PTRTOINT 1433 { 68, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, OperandInfo23 }, // Inst #68 = G_CONCAT_VECTORS 1434 { 67, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, OperandInfo23 }, // Inst #67 = G_BUILD_VECTOR_TRUNC 1435 { 66, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, OperandInfo23 }, // Inst #66 = G_BUILD_VECTOR 1436 { 65, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, OperandInfo23 }, // Inst #65 = G_MERGE_VALUES 1437 { 64, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo24 }, // Inst #64 = G_INSERT 1438 { 63, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, OperandInfo23 }, // Inst #63 = G_UNMERGE_VALUES 1439 { 62, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo22 }, // Inst #62 = G_EXTRACT 1440 { 61, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo21 }, // Inst #61 = G_GLOBAL_VALUE 1441 { 60, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo21 }, // Inst #60 = G_FRAME_INDEX 1442 { 59, 1, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, OperandInfo20 }, // Inst #59 = G_PHI 1443 { 58, 1, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo20 }, // Inst #58 = G_IMPLICIT_DEF 1444 { 57, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #57 = G_XOR 1445 { 56, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #56 = G_OR 1446 { 55, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #55 = G_AND 1447 { 54, 4, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo19 }, // Inst #54 = G_UDIVREM 1448 { 53, 4, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo19 }, // Inst #53 = G_SDIVREM 1449 { 52, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo18 }, // Inst #52 = G_UREM 1450 { 51, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo18 }, // Inst #51 = G_SREM 1451 { 50, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo18 }, // Inst #50 = G_UDIV 1452 { 49, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo18 }, // Inst #49 = G_SDIV 1453 { 48, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #48 = G_MUL 1454 { 47, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo18 }, // Inst #47 = G_SUB 1455 { 46, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #46 = G_ADD 1456 { 45, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo17 }, // Inst #45 = G_ASSERT_ALIGN 1457 { 44, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo17 }, // Inst #44 = G_ASSERT_ZEXT 1458 { 43, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo17 }, // Inst #43 = G_ASSERT_SEXT 1459 { 42, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #42 = MEMBARRIER 1460 { 41, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #41 = ICALL_BRANCH_FUNNEL 1461 { 40, 3, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo16 }, // Inst #40 = PATCHABLE_TYPED_EVENT_CALL 1462 { 39, 2, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo15 }, // Inst #39 = PATCHABLE_EVENT_CALL 1463 { 38, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #38 = PATCHABLE_TAIL_CALL 1464 { 37, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #37 = PATCHABLE_FUNCTION_EXIT 1465 { 36, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #36 = PATCHABLE_RET 1466 { 35, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #35 = PATCHABLE_FUNCTION_ENTER 1467 { 34, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #34 = PATCHABLE_OP 1468 { 33, 1, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo2 }, // Inst #33 = FAULTING_OP 1469 { 32, 2, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo14 }, // Inst #32 = LOCAL_ESCAPE 1470 { 31, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #31 = STATEPOINT 1471 { 30, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo13 }, // Inst #30 = PREALLOCATED_ARG 1472 { 29, 1, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo3 }, // Inst #29 = PREALLOCATED_SETUP 1473 { 28, 1, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, OperandInfo12 }, // Inst #28 = LOAD_STACK_GUARD 1474 { 27, 6, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo11 }, // Inst #27 = PATCHPOINT 1475 { 26, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #26 = FENTRY_CALL 1476 { 25, 2, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo10 }, // Inst #25 = STACKMAP 1477 { 24, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL, nullptr, OperandInfo9 }, // Inst #24 = ARITH_FENCE 1478 { 23, 4, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo8 }, // Inst #23 = PSEUDO_PROBE 1479 { 22, 1, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL, nullptr, OperandInfo3 }, // Inst #22 = LIFETIME_END 1480 { 21, 1, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL, nullptr, OperandInfo3 }, // Inst #21 = LIFETIME_START 1481 { 20, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr }, // Inst #20 = BUNDLE 1482 { 19, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, OperandInfo7 }, // Inst #19 = COPY 1483 { 18, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, OperandInfo7 }, // Inst #18 = REG_SEQUENCE 1484 { 17, 1, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL, nullptr, OperandInfo2 }, // Inst #17 = DBG_LABEL 1485 { 16, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr }, // Inst #16 = DBG_PHI 1486 { 15, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr }, // Inst #15 = DBG_INSTR_REF 1487 { 14, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr }, // Inst #14 = DBG_VALUE_LIST 1488 { 13, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr }, // Inst #13 = DBG_VALUE 1489 { 12, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, OperandInfo4 }, // Inst #12 = COPY_TO_REGCLASS 1490 { 11, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo6 }, // Inst #11 = SUBREG_TO_REG 1491 { 10, 1, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, OperandInfo2 }, // Inst #10 = IMPLICIT_DEF 1492 { 9, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo5 }, // Inst #9 = INSERT_SUBREG 1493 { 8, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo4 }, // Inst #8 = EXTRACT_SUBREG 1494 { 7, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr }, // Inst #7 = KILL 1495 { 6, 1, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, OperandInfo3 }, // Inst #6 = ANNOTATION_LABEL 1496 { 5, 1, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, OperandInfo3 }, // Inst #5 = GC_LABEL 1497 { 4, 1, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, OperandInfo3 }, // Inst #4 = EH_LABEL 1498 { 3, 1, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, OperandInfo3 }, // Inst #3 = CFI_INSTRUCTION 1499 { 2, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #2 = INLINEASM_BR 1500 { 1, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr }, // Inst #1 = INLINEASM 1501 { 0, 1, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, OperandInfo2 }, // Inst #0 = PHI 1502}; 1503 1504 1505#ifdef __GNUC__ 1506#pragma GCC diagnostic push 1507#pragma GCC diagnostic ignored "-Woverlength-strings" 1508#endif 1509extern const char LoongArchInstrNameData[] = { 1510 /* 0 */ "G_FLOG10\0" 1511 /* 9 */ "PseudoMaskedAtomicLoadSub32\0" 1512 /* 37 */ "PseudoAtomicLoadSub32\0" 1513 /* 59 */ "PseudoMaskedAtomicLoadAdd32\0" 1514 /* 87 */ "PseudoAtomicLoadAdd32\0" 1515 /* 109 */ "PseudoAtomicLoadAnd32\0" 1516 /* 131 */ "PseudoMaskedAtomicLoadNand32\0" 1517 /* 160 */ "PseudoAtomicLoadNand32\0" 1518 /* 183 */ "PseudoMaskedCmpXchg32\0" 1519 /* 205 */ "PseudoCmpXchg32\0" 1520 /* 221 */ "PseudoMaskedAtomicLoadUMin32\0" 1521 /* 250 */ "PseudoMaskedAtomicLoadMin32\0" 1522 /* 278 */ "PseudoMaskedAtomicSwap32\0" 1523 /* 303 */ "PseudoAtomicSwap32\0" 1524 /* 322 */ "PseudoAtomicLoadOr32\0" 1525 /* 343 */ "PseudoAtomicLoadXor32\0" 1526 /* 365 */ "PseudoMaskedAtomicLoadUMax32\0" 1527 /* 394 */ "PseudoMaskedAtomicLoadMax32\0" 1528 /* 422 */ "G_FLOG2\0" 1529 /* 430 */ "G_FEXP2\0" 1530 /* 438 */ "MOVFR2GR_S_64\0" 1531 /* 452 */ "MOVGR2FR_W_64\0" 1532 /* 466 */ "PseudoAtomicLoadNand64\0" 1533 /* 489 */ "PseudoCmpXchg64\0" 1534 /* 505 */ "G_FMA\0" 1535 /* 511 */ "G_STRICT_FMA\0" 1536 /* 524 */ "BITREV_4B\0" 1537 /* 534 */ "BITREV_8B\0" 1538 /* 544 */ "INVTLB\0" 1539 /* 551 */ "G_FSUB\0" 1540 /* 558 */ "G_STRICT_FSUB\0" 1541 /* 572 */ "G_ATOMICRMW_FSUB\0" 1542 /* 589 */ "G_SUB\0" 1543 /* 595 */ "G_ATOMICRMW_SUB\0" 1544 /* 611 */ "LD_B\0" 1545 /* 616 */ "IOCSRRD_B\0" 1546 /* 626 */ "LDLE_B\0" 1547 /* 633 */ "STLE_B\0" 1548 /* 640 */ "IOCSRWR_B\0" 1549 /* 650 */ "LDGT_B\0" 1550 /* 657 */ "STGT_B\0" 1551 /* 664 */ "ST_B\0" 1552 /* 669 */ "EXT_W_B\0" 1553 /* 677 */ "LDX_B\0" 1554 /* 683 */ "STX_B\0" 1555 /* 689 */ "G_INTRINSIC\0" 1556 /* 701 */ "G_FPTRUNC\0" 1557 /* 711 */ "G_INTRINSIC_TRUNC\0" 1558 /* 729 */ "G_TRUNC\0" 1559 /* 737 */ "G_BUILD_VECTOR_TRUNC\0" 1560 /* 758 */ "G_DYN_STACKALLOC\0" 1561 /* 775 */ "G_FMAD\0" 1562 /* 782 */ "G_INDEXED_SEXTLOAD\0" 1563 /* 801 */ "G_SEXTLOAD\0" 1564 /* 812 */ "G_INDEXED_ZEXTLOAD\0" 1565 /* 831 */ "G_ZEXTLOAD\0" 1566 /* 842 */ "G_INDEXED_LOAD\0" 1567 /* 857 */ "G_LOAD\0" 1568 /* 864 */ "G_VECREDUCE_FADD\0" 1569 /* 881 */ "G_FADD\0" 1570 /* 888 */ "G_VECREDUCE_SEQ_FADD\0" 1571 /* 909 */ "G_STRICT_FADD\0" 1572 /* 923 */ "G_ATOMICRMW_FADD\0" 1573 /* 940 */ "G_VECREDUCE_ADD\0" 1574 /* 956 */ "G_ADD\0" 1575 /* 962 */ "G_PTR_ADD\0" 1576 /* 972 */ "G_ATOMICRMW_ADD\0" 1577 /* 988 */ "PseudoLA_TLS_GD\0" 1578 /* 1004 */ "PRELD\0" 1579 /* 1010 */ "PseudoLA_TLS_LD\0" 1580 /* 1026 */ "G_ATOMICRMW_NAND\0" 1581 /* 1043 */ "G_VECREDUCE_AND\0" 1582 /* 1059 */ "G_AND\0" 1583 /* 1065 */ "G_ATOMICRMW_AND\0" 1584 /* 1081 */ "LIFETIME_END\0" 1585 /* 1094 */ "PseudoBRIND\0" 1586 /* 1106 */ "G_BRCOND\0" 1587 /* 1115 */ "G_LLROUND\0" 1588 /* 1125 */ "G_LROUND\0" 1589 /* 1134 */ "G_INTRINSIC_ROUND\0" 1590 /* 1152 */ "G_INTRINSIC_FPTRUNC_ROUND\0" 1591 /* 1178 */ "LOAD_STACK_GUARD\0" 1592 /* 1195 */ "TLBRD\0" 1593 /* 1201 */ "CSRRD\0" 1594 /* 1207 */ "FMINA_D\0" 1595 /* 1215 */ "SRA_D\0" 1596 /* 1221 */ "FMAXA_D\0" 1597 /* 1229 */ "AMADD_DB_D\0" 1598 /* 1240 */ "AMAND_DB_D\0" 1599 /* 1251 */ "AMMIN_DB_D\0" 1600 /* 1262 */ "AMSWAP_DB_D\0" 1601 /* 1274 */ "AMOR_DB_D\0" 1602 /* 1284 */ "AMXOR_DB_D\0" 1603 /* 1295 */ "AMMAX_DB_D\0" 1604 /* 1306 */ "FSCALEB_D\0" 1605 /* 1316 */ "FLOGB_D\0" 1606 /* 1324 */ "FSUB_D\0" 1607 /* 1331 */ "FMSUB_D\0" 1608 /* 1339 */ "FNMSUB_D\0" 1609 /* 1348 */ "REVB_D\0" 1610 /* 1355 */ "SC_D\0" 1611 /* 1360 */ "FADD_D\0" 1612 /* 1367 */ "AMADD_D\0" 1613 /* 1375 */ "FMADD_D\0" 1614 /* 1383 */ "FNMADD_D\0" 1615 /* 1392 */ "FLD_D\0" 1616 /* 1398 */ "AMAND_D\0" 1617 /* 1406 */ "MOD_D\0" 1618 /* 1412 */ "IOCSRRD_D\0" 1619 /* 1422 */ "FCMP_CLE_D\0" 1620 /* 1433 */ "FLDLE_D\0" 1621 /* 1441 */ "FCMP_SLE_D\0" 1622 /* 1452 */ "ASRTLE_D\0" 1623 /* 1461 */ "FSTLE_D\0" 1624 /* 1469 */ "FCMP_CULE_D\0" 1625 /* 1481 */ "FCMP_SULE_D\0" 1626 /* 1493 */ "RDTIME_D\0" 1627 /* 1502 */ "FCMP_CNE_D\0" 1628 /* 1513 */ "FCMP_SNE_D\0" 1629 /* 1524 */ "FCMP_CUNE_D\0" 1630 /* 1536 */ "FCMP_SUNE_D\0" 1631 /* 1548 */ "FCMP_CAF_D\0" 1632 /* 1559 */ "FCMP_SAF_D\0" 1633 /* 1570 */ "FNEG_D\0" 1634 /* 1577 */ "MULH_D\0" 1635 /* 1584 */ "REVH_D\0" 1636 /* 1591 */ "LU32I_D\0" 1637 /* 1599 */ "LU52I_D\0" 1638 /* 1607 */ "ADDU16I_D\0" 1639 /* 1617 */ "SRAI_D\0" 1640 /* 1624 */ "ADDI_D\0" 1641 /* 1631 */ "SLLI_D\0" 1642 /* 1638 */ "SRLI_D\0" 1643 /* 1645 */ "PseudoLI_D\0" 1644 /* 1656 */ "ROTRI_D\0" 1645 /* 1664 */ "BYTEPICK_D\0" 1646 /* 1675 */ "BSTRPICK_D\0" 1647 /* 1686 */ "FSEL_D\0" 1648 /* 1693 */ "SLL_D\0" 1649 /* 1699 */ "SRL_D\0" 1650 /* 1705 */ "ALSL_D\0" 1651 /* 1712 */ "FMUL_D\0" 1652 /* 1719 */ "FTINTRNE_L_D\0" 1653 /* 1732 */ "FTINTRM_L_D\0" 1654 /* 1744 */ "FTINTRP_L_D\0" 1655 /* 1756 */ "FTINT_L_D\0" 1656 /* 1766 */ "FTINTRZ_L_D\0" 1657 /* 1778 */ "FCOPYSIGN_D\0" 1658 /* 1790 */ "FMIN_D\0" 1659 /* 1797 */ "AMMIN_D\0" 1660 /* 1805 */ "FCMP_CUN_D\0" 1661 /* 1816 */ "FCMP_SUN_D\0" 1662 /* 1827 */ "CLO_D\0" 1663 /* 1833 */ "CTO_D\0" 1664 /* 1839 */ "AMSWAP_D\0" 1665 /* 1848 */ "FRECIP_D\0" 1666 /* 1857 */ "FCMP_CEQ_D\0" 1667 /* 1868 */ "FCMP_SEQ_D\0" 1668 /* 1879 */ "FCMP_CUEQ_D\0" 1669 /* 1891 */ "FCMP_SUEQ_D\0" 1670 /* 1903 */ "MOVGR2FR_D\0" 1671 /* 1914 */ "MOVFR2GR_D\0" 1672 /* 1925 */ "FCMP_COR_D\0" 1673 /* 1936 */ "AMOR_D\0" 1674 /* 1943 */ "FCMP_SOR_D\0" 1675 /* 1954 */ "AMXOR_D\0" 1676 /* 1962 */ "ROTR_D\0" 1677 /* 1969 */ "LDPTR_D\0" 1678 /* 1977 */ "STPTR_D\0" 1679 /* 1985 */ "IOCSRWR_D\0" 1680 /* 1995 */ "FABS_D\0" 1681 /* 2002 */ "BSTRINS_D\0" 1682 /* 2012 */ "FCLASS_D\0" 1683 /* 2021 */ "FCVT_S_D\0" 1684 /* 2030 */ "FLDGT_D\0" 1685 /* 2038 */ "ASRTGT_D\0" 1686 /* 2047 */ "FSTGT_D\0" 1687 /* 2055 */ "FCMP_CLT_D\0" 1688 /* 2066 */ "FCMP_SLT_D\0" 1689 /* 2077 */ "FCMP_CULT_D\0" 1690 /* 2089 */ "FCMP_SULT_D\0" 1691 /* 2101 */ "FRINT_D\0" 1692 /* 2109 */ "FSQRT_D\0" 1693 /* 2117 */ "FRSQRT_D\0" 1694 /* 2126 */ "FST_D\0" 1695 /* 2132 */ "BITREV_D\0" 1696 /* 2141 */ "FDIV_D\0" 1697 /* 2148 */ "FMOV_D\0" 1698 /* 2155 */ "FTINTRNE_W_D\0" 1699 /* 2168 */ "FTINTRM_W_D\0" 1700 /* 2180 */ "FTINTRP_W_D\0" 1701 /* 2192 */ "FTINT_W_D\0" 1702 /* 2202 */ "FTINTRZ_W_D\0" 1703 /* 2214 */ "FMAX_D\0" 1704 /* 2221 */ "AMMAX_D\0" 1705 /* 2229 */ "FLDX_D\0" 1706 /* 2236 */ "FSTX_D\0" 1707 /* 2243 */ "CLZ_D\0" 1708 /* 2249 */ "CTZ_D\0" 1709 /* 2255 */ "PseudoAtomicStoreD\0" 1710 /* 2274 */ "PSEUDO_PROBE\0" 1711 /* 2287 */ "G_SSUBE\0" 1712 /* 2295 */ "G_USUBE\0" 1713 /* 2303 */ "G_FENCE\0" 1714 /* 2311 */ "ARITH_FENCE\0" 1715 /* 2323 */ "REG_SEQUENCE\0" 1716 /* 2336 */ "G_SADDE\0" 1717 /* 2344 */ "G_UADDE\0" 1718 /* 2352 */ "G_FMINNUM_IEEE\0" 1719 /* 2367 */ "G_FMAXNUM_IEEE\0" 1720 /* 2382 */ "BGE\0" 1721 /* 2386 */ "PseudoLA_TLS_GD_LARGE\0" 1722 /* 2408 */ "PseudoLA_TLS_LD_LARGE\0" 1723 /* 2430 */ "PseudoLA_TLS_IE_LARGE\0" 1724 /* 2452 */ "PseudoLA_PCREL_LARGE\0" 1725 /* 2473 */ "PseudoLA_ABS_LARGE\0" 1726 /* 2492 */ "PseudoLA_GOT_LARGE\0" 1727 /* 2511 */ "PseudoLA_TLS_IE\0" 1728 /* 2527 */ "G_JUMP_TABLE\0" 1729 /* 2540 */ "IDLE\0" 1730 /* 2545 */ "BUNDLE\0" 1731 /* 2552 */ "PseudoLA_TLS_LE\0" 1732 /* 2568 */ "BNE\0" 1733 /* 2572 */ "G_MEMCPY_INLINE\0" 1734 /* 2588 */ "LOCAL_ESCAPE\0" 1735 /* 2601 */ "G_INDEXED_STORE\0" 1736 /* 2617 */ "G_STORE\0" 1737 /* 2625 */ "G_BITREVERSE\0" 1738 /* 2638 */ "LDPTE\0" 1739 /* 2644 */ "DBG_VALUE\0" 1740 /* 2654 */ "G_GLOBAL_VALUE\0" 1741 /* 2669 */ "G_MEMMOVE\0" 1742 /* 2679 */ "G_FREEZE\0" 1743 /* 2688 */ "G_FCANONICALIZE\0" 1744 /* 2704 */ "MOVGR2CF\0" 1745 /* 2713 */ "G_CTLZ_ZERO_UNDEF\0" 1746 /* 2731 */ "G_CTTZ_ZERO_UNDEF\0" 1747 /* 2749 */ "G_IMPLICIT_DEF\0" 1748 /* 2764 */ "DBG_INSTR_REF\0" 1749 /* 2778 */ "G_FNEG\0" 1750 /* 2785 */ "EXTRACT_SUBREG\0" 1751 /* 2800 */ "INSERT_SUBREG\0" 1752 /* 2814 */ "G_SEXT_INREG\0" 1753 /* 2827 */ "SUBREG_TO_REG\0" 1754 /* 2841 */ "CPUCFG\0" 1755 /* 2848 */ "G_ATOMIC_CMPXCHG\0" 1756 /* 2865 */ "CSRXCHG\0" 1757 /* 2873 */ "G_ATOMICRMW_XCHG\0" 1758 /* 2890 */ "G_FLOG\0" 1759 /* 2897 */ "G_VAARG\0" 1760 /* 2905 */ "PREALLOCATED_ARG\0" 1761 /* 2922 */ "REVB_2H\0" 1762 /* 2930 */ "REVB_4H\0" 1763 /* 2938 */ "TLBSRCH\0" 1764 /* 2946 */ "G_SMULH\0" 1765 /* 2954 */ "G_UMULH\0" 1766 /* 2962 */ "TLBFLUSH\0" 1767 /* 2971 */ "LD_H\0" 1768 /* 2976 */ "IOCSRRD_H\0" 1769 /* 2986 */ "LDLE_H\0" 1770 /* 2993 */ "STLE_H\0" 1771 /* 3000 */ "IOCSRWR_H\0" 1772 /* 3010 */ "LDGT_H\0" 1773 /* 3017 */ "STGT_H\0" 1774 /* 3024 */ "ST_H\0" 1775 /* 3029 */ "EXT_W_H\0" 1776 /* 3037 */ "LDX_H\0" 1777 /* 3043 */ "STX_H\0" 1778 /* 3049 */ "PCALAU12I\0" 1779 /* 3059 */ "PCADDU12I\0" 1780 /* 3069 */ "PCADDU18I\0" 1781 /* 3079 */ "PCADDI\0" 1782 /* 3086 */ "ANDI\0" 1783 /* 3091 */ "DBG_PHI\0" 1784 /* 3099 */ "XORI\0" 1785 /* 3104 */ "G_FPTOSI\0" 1786 /* 3113 */ "SLTI\0" 1787 /* 3118 */ "G_FPTOUI\0" 1788 /* 3127 */ "SLTUI\0" 1789 /* 3133 */ "G_FPOWI\0" 1790 /* 3141 */ "BREAK\0" 1791 /* 3147 */ "G_PTRMASK\0" 1792 /* 3157 */ "BL\0" 1793 /* 3160 */ "DBCL\0" 1794 /* 3165 */ "GC_LABEL\0" 1795 /* 3174 */ "DBG_LABEL\0" 1796 /* 3184 */ "EH_LABEL\0" 1797 /* 3193 */ "ANNOTATION_LABEL\0" 1798 /* 3210 */ "ICALL_BRANCH_FUNNEL\0" 1799 /* 3230 */ "PseudoLA_PCREL\0" 1800 /* 3245 */ "G_FSHL\0" 1801 /* 3252 */ "G_SHL\0" 1802 /* 3258 */ "PseudoB_TAIL\0" 1803 /* 3271 */ "PseudoJIRL_TAIL\0" 1804 /* 3287 */ "PseudoTAIL\0" 1805 /* 3298 */ "G_FCEIL\0" 1806 /* 3306 */ "SYSCALL\0" 1807 /* 3314 */ "PATCHABLE_TAIL_CALL\0" 1808 /* 3334 */ "PseudoJIRL_CALL\0" 1809 /* 3350 */ "PATCHABLE_TYPED_EVENT_CALL\0" 1810 /* 3377 */ "PATCHABLE_EVENT_CALL\0" 1811 /* 3398 */ "FENTRY_CALL\0" 1812 /* 3410 */ "PseudoCALL\0" 1813 /* 3421 */ "TLBFILL\0" 1814 /* 3429 */ "KILL\0" 1815 /* 3434 */ "JIRL\0" 1816 /* 3439 */ "G_ROTL\0" 1817 /* 3446 */ "G_VECREDUCE_FMUL\0" 1818 /* 3463 */ "G_FMUL\0" 1819 /* 3470 */ "G_VECREDUCE_SEQ_FMUL\0" 1820 /* 3491 */ "G_STRICT_FMUL\0" 1821 /* 3505 */ "G_VECREDUCE_MUL\0" 1822 /* 3521 */ "G_MUL\0" 1823 /* 3527 */ "FFINT_D_L\0" 1824 /* 3537 */ "FFINT_S_L\0" 1825 /* 3547 */ "G_FREM\0" 1826 /* 3554 */ "G_STRICT_FREM\0" 1827 /* 3568 */ "G_SREM\0" 1828 /* 3575 */ "G_UREM\0" 1829 /* 3582 */ "G_SDIVREM\0" 1830 /* 3592 */ "G_UDIVREM\0" 1831 /* 3602 */ "INLINEASM\0" 1832 /* 3612 */ "G_FMINIMUM\0" 1833 /* 3623 */ "G_FMAXIMUM\0" 1834 /* 3634 */ "G_FMINNUM\0" 1835 /* 3644 */ "G_FMAXNUM\0" 1836 /* 3654 */ "ANDN\0" 1837 /* 3659 */ "G_INTRINSIC_ROUNDEVEN\0" 1838 /* 3681 */ "G_ASSERT_ALIGN\0" 1839 /* 3696 */ "G_FCOPYSIGN\0" 1840 /* 3708 */ "G_VECREDUCE_FMIN\0" 1841 /* 3725 */ "G_ATOMICRMW_FMIN\0" 1842 /* 3742 */ "G_VECREDUCE_SMIN\0" 1843 /* 3759 */ "G_SMIN\0" 1844 /* 3766 */ "G_VECREDUCE_UMIN\0" 1845 /* 3783 */ "G_UMIN\0" 1846 /* 3790 */ "G_ATOMICRMW_UMIN\0" 1847 /* 3807 */ "G_ATOMICRMW_MIN\0" 1848 /* 3823 */ "G_FSIN\0" 1849 /* 3830 */ "CFI_INSTRUCTION\0" 1850 /* 3846 */ "ORN\0" 1851 /* 3850 */ "ERTN\0" 1852 /* 3855 */ "ADJCALLSTACKDOWN\0" 1853 /* 3872 */ "G_SSUBO\0" 1854 /* 3880 */ "G_USUBO\0" 1855 /* 3888 */ "G_SADDO\0" 1856 /* 3896 */ "G_UADDO\0" 1857 /* 3904 */ "G_SMULO\0" 1858 /* 3912 */ "G_UMULO\0" 1859 /* 3920 */ "G_BZERO\0" 1860 /* 3928 */ "STACKMAP\0" 1861 /* 3937 */ "G_ATOMICRMW_UDEC_WRAP\0" 1862 /* 3959 */ "G_ATOMICRMW_UINC_WRAP\0" 1863 /* 3981 */ "G_BSWAP\0" 1864 /* 3989 */ "G_SITOFP\0" 1865 /* 3998 */ "G_UITOFP\0" 1866 /* 4007 */ "G_FCMP\0" 1867 /* 4014 */ "G_ICMP\0" 1868 /* 4021 */ "PseudoUNIMP\0" 1869 /* 4033 */ "CACOP\0" 1870 /* 4039 */ "G_CTPOP\0" 1871 /* 4047 */ "PATCHABLE_OP\0" 1872 /* 4060 */ "FAULTING_OP\0" 1873 /* 4072 */ "ADJCALLSTACKUP\0" 1874 /* 4087 */ "PREALLOCATED_SETUP\0" 1875 /* 4106 */ "G_FEXP\0" 1876 /* 4113 */ "BEQ\0" 1877 /* 4117 */ "DBAR\0" 1878 /* 4122 */ "IBAR\0" 1879 /* 4127 */ "G_BR\0" 1880 /* 4132 */ "INLINEASM_BR\0" 1881 /* 4145 */ "PseudoBR\0" 1882 /* 4154 */ "G_BLOCK_ADDR\0" 1883 /* 4167 */ "MEMBARRIER\0" 1884 /* 4178 */ "PATCHABLE_FUNCTION_ENTER\0" 1885 /* 4203 */ "G_READCYCLECOUNTER\0" 1886 /* 4222 */ "G_READ_REGISTER\0" 1887 /* 4238 */ "G_WRITE_REGISTER\0" 1888 /* 4255 */ "PseudoLD_CFR\0" 1889 /* 4268 */ "PseudoST_CFR\0" 1890 /* 4281 */ "MOVCF2GR\0" 1891 /* 4290 */ "MOVFCSR2GR\0" 1892 /* 4301 */ "G_ASHR\0" 1893 /* 4308 */ "G_FSHR\0" 1894 /* 4315 */ "G_LSHR\0" 1895 /* 4322 */ "LDDIR\0" 1896 /* 4328 */ "TLBCLR\0" 1897 /* 4335 */ "NOR\0" 1898 /* 4339 */ "G_FFLOOR\0" 1899 /* 4348 */ "G_BUILD_VECTOR\0" 1900 /* 4363 */ "G_SHUFFLE_VECTOR\0" 1901 /* 4380 */ "G_VECREDUCE_XOR\0" 1902 /* 4396 */ "G_XOR\0" 1903 /* 4402 */ "G_ATOMICRMW_XOR\0" 1904 /* 4418 */ "G_VECREDUCE_OR\0" 1905 /* 4433 */ "G_OR\0" 1906 /* 4438 */ "G_ATOMICRMW_OR\0" 1907 /* 4453 */ "MOVGR2FCSR\0" 1908 /* 4464 */ "RDFCSR\0" 1909 /* 4471 */ "WRFCSR\0" 1910 /* 4478 */ "G_ROTR\0" 1911 /* 4485 */ "G_INTTOPTR\0" 1912 /* 4496 */ "TLBWR\0" 1913 /* 4502 */ "CSRWR\0" 1914 /* 4508 */ "G_FABS\0" 1915 /* 4515 */ "PseudoLA_ABS\0" 1916 /* 4528 */ "G_ABS\0" 1917 /* 4534 */ "G_UNMERGE_VALUES\0" 1918 /* 4551 */ "G_MERGE_VALUES\0" 1919 /* 4566 */ "G_FCOS\0" 1920 /* 4573 */ "G_CONCAT_VECTORS\0" 1921 /* 4590 */ "COPY_TO_REGCLASS\0" 1922 /* 4607 */ "G_IS_FPCLASS\0" 1923 /* 4620 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\0" 1924 /* 4650 */ "G_INTRINSIC_W_SIDE_EFFECTS\0" 1925 /* 4677 */ "FMINA_S\0" 1926 /* 4685 */ "FMAXA_S\0" 1927 /* 4693 */ "FSCALEB_S\0" 1928 /* 4703 */ "FLOGB_S\0" 1929 /* 4711 */ "FSUB_S\0" 1930 /* 4718 */ "FMSUB_S\0" 1931 /* 4726 */ "FNMSUB_S\0" 1932 /* 4735 */ "FADD_S\0" 1933 /* 4742 */ "FMADD_S\0" 1934 /* 4750 */ "FNMADD_S\0" 1935 /* 4759 */ "FLD_S\0" 1936 /* 4765 */ "FCVT_D_S\0" 1937 /* 4774 */ "FCMP_CLE_S\0" 1938 /* 4785 */ "FLDLE_S\0" 1939 /* 4793 */ "FCMP_SLE_S\0" 1940 /* 4804 */ "FSTLE_S\0" 1941 /* 4812 */ "FCMP_CULE_S\0" 1942 /* 4824 */ "FCMP_SULE_S\0" 1943 /* 4836 */ "FCMP_CNE_S\0" 1944 /* 4847 */ "FCMP_SNE_S\0" 1945 /* 4858 */ "FCMP_CUNE_S\0" 1946 /* 4870 */ "FCMP_SUNE_S\0" 1947 /* 4882 */ "FCMP_CAF_S\0" 1948 /* 4893 */ "FCMP_SAF_S\0" 1949 /* 4904 */ "MOVFR2CF_S\0" 1950 /* 4915 */ "FNEG_S\0" 1951 /* 4922 */ "FSEL_S\0" 1952 /* 4929 */ "FMUL_S\0" 1953 /* 4936 */ "FTINTRNE_L_S\0" 1954 /* 4949 */ "FTINTRM_L_S\0" 1955 /* 4961 */ "FTINTRP_L_S\0" 1956 /* 4973 */ "FTINT_L_S\0" 1957 /* 4983 */ "FTINTRZ_L_S\0" 1958 /* 4995 */ "FCOPYSIGN_S\0" 1959 /* 5007 */ "FMIN_S\0" 1960 /* 5014 */ "FCMP_CUN_S\0" 1961 /* 5025 */ "FCMP_SUN_S\0" 1962 /* 5036 */ "FRECIP_S\0" 1963 /* 5045 */ "FCMP_CEQ_S\0" 1964 /* 5056 */ "FCMP_SEQ_S\0" 1965 /* 5067 */ "FCMP_CUEQ_S\0" 1966 /* 5079 */ "FCMP_SUEQ_S\0" 1967 /* 5091 */ "MOVCF2FR_S\0" 1968 /* 5102 */ "MOVFRH2GR_S\0" 1969 /* 5114 */ "MOVFR2GR_S\0" 1970 /* 5125 */ "FCMP_COR_S\0" 1971 /* 5136 */ "FCMP_SOR_S\0" 1972 /* 5147 */ "FABS_S\0" 1973 /* 5154 */ "FCLASS_S\0" 1974 /* 5163 */ "FLDGT_S\0" 1975 /* 5171 */ "FSTGT_S\0" 1976 /* 5179 */ "FCMP_CLT_S\0" 1977 /* 5190 */ "FCMP_SLT_S\0" 1978 /* 5201 */ "FCMP_CULT_S\0" 1979 /* 5213 */ "FCMP_SULT_S\0" 1980 /* 5225 */ "FRINT_S\0" 1981 /* 5233 */ "FSQRT_S\0" 1982 /* 5241 */ "FRSQRT_S\0" 1983 /* 5250 */ "FST_S\0" 1984 /* 5256 */ "FDIV_S\0" 1985 /* 5263 */ "FMOV_S\0" 1986 /* 5270 */ "FTINTRNE_W_S\0" 1987 /* 5283 */ "FTINTRM_W_S\0" 1988 /* 5295 */ "FTINTRP_W_S\0" 1989 /* 5307 */ "FTINT_W_S\0" 1990 /* 5317 */ "FTINTRZ_W_S\0" 1991 /* 5329 */ "FMAX_S\0" 1992 /* 5336 */ "FLDX_S\0" 1993 /* 5343 */ "FSTX_S\0" 1994 /* 5350 */ "G_SSUBSAT\0" 1995 /* 5360 */ "G_USUBSAT\0" 1996 /* 5370 */ "G_SADDSAT\0" 1997 /* 5380 */ "G_UADDSAT\0" 1998 /* 5390 */ "G_SSHLSAT\0" 1999 /* 5400 */ "G_USHLSAT\0" 2000 /* 5410 */ "G_SMULFIXSAT\0" 2001 /* 5423 */ "G_UMULFIXSAT\0" 2002 /* 5436 */ "G_SDIVFIXSAT\0" 2003 /* 5449 */ "G_UDIVFIXSAT\0" 2004 /* 5462 */ "G_EXTRACT\0" 2005 /* 5472 */ "G_SELECT\0" 2006 /* 5481 */ "G_BRINDIRECT\0" 2007 /* 5494 */ "PATCHABLE_RET\0" 2008 /* 5508 */ "PseudoRET\0" 2009 /* 5518 */ "G_MEMSET\0" 2010 /* 5527 */ "PATCHABLE_FUNCTION_EXIT\0" 2011 /* 5551 */ "G_BRJT\0" 2012 /* 5558 */ "BLT\0" 2013 /* 5562 */ "G_EXTRACT_VECTOR_ELT\0" 2014 /* 5583 */ "G_INSERT_VECTOR_ELT\0" 2015 /* 5603 */ "SLT\0" 2016 /* 5607 */ "G_FCONSTANT\0" 2017 /* 5619 */ "G_CONSTANT\0" 2018 /* 5630 */ "STATEPOINT\0" 2019 /* 5641 */ "PATCHPOINT\0" 2020 /* 5652 */ "G_PTRTOINT\0" 2021 /* 5663 */ "G_FRINT\0" 2022 /* 5671 */ "G_INTRINSIC_LRINT\0" 2023 /* 5689 */ "G_FNEARBYINT\0" 2024 /* 5702 */ "PseudoLA_GOT\0" 2025 /* 5715 */ "G_VASTART\0" 2026 /* 5725 */ "LIFETIME_START\0" 2027 /* 5740 */ "G_INVOKE_REGION_START\0" 2028 /* 5762 */ "G_INSERT\0" 2029 /* 5771 */ "G_FSQRT\0" 2030 /* 5779 */ "G_STRICT_FSQRT\0" 2031 /* 5794 */ "G_BITCAST\0" 2032 /* 5804 */ "G_ADDRSPACE_CAST\0" 2033 /* 5821 */ "DBG_VALUE_LIST\0" 2034 /* 5836 */ "G_FPEXT\0" 2035 /* 5844 */ "G_SEXT\0" 2036 /* 5851 */ "G_ASSERT_SEXT\0" 2037 /* 5865 */ "G_ANYEXT\0" 2038 /* 5874 */ "G_ZEXT\0" 2039 /* 5881 */ "G_ASSERT_ZEXT\0" 2040 /* 5895 */ "LD_BU\0" 2041 /* 5901 */ "LDX_BU\0" 2042 /* 5908 */ "AMMIN_DB_DU\0" 2043 /* 5920 */ "AMMAX_DB_DU\0" 2044 /* 5932 */ "MOD_DU\0" 2045 /* 5939 */ "MULH_DU\0" 2046 /* 5947 */ "AMMIN_DU\0" 2047 /* 5956 */ "DIV_DU\0" 2048 /* 5963 */ "AMMAX_DU\0" 2049 /* 5972 */ "BGEU\0" 2050 /* 5977 */ "LD_HU\0" 2051 /* 5983 */ "LDX_HU\0" 2052 /* 5990 */ "BLTU\0" 2053 /* 5995 */ "SLTU\0" 2054 /* 6000 */ "AMMIN_DB_WU\0" 2055 /* 6012 */ "AMMAX_DB_WU\0" 2056 /* 6024 */ "LD_WU\0" 2057 /* 6030 */ "MOD_WU\0" 2058 /* 6037 */ "MULW_D_WU\0" 2059 /* 6047 */ "MULH_WU\0" 2060 /* 6055 */ "ALSL_WU\0" 2061 /* 6063 */ "AMMIN_WU\0" 2062 /* 6072 */ "DIV_WU\0" 2063 /* 6079 */ "AMMAX_WU\0" 2064 /* 6088 */ "LDX_WU\0" 2065 /* 6095 */ "G_FDIV\0" 2066 /* 6102 */ "G_STRICT_FDIV\0" 2067 /* 6116 */ "G_SDIV\0" 2068 /* 6123 */ "G_UDIV\0" 2069 /* 6130 */ "REVB_2W\0" 2070 /* 6138 */ "REVH_2W\0" 2071 /* 6146 */ "G_FPOW\0" 2072 /* 6153 */ "SRA_W\0" 2073 /* 6159 */ "AMADD_DB_W\0" 2074 /* 6170 */ "AMAND_DB_W\0" 2075 /* 6181 */ "AMMIN_DB_W\0" 2076 /* 6192 */ "AMSWAP_DB_W\0" 2077 /* 6204 */ "AMOR_DB_W\0" 2078 /* 6214 */ "AMXOR_DB_W\0" 2079 /* 6225 */ "AMMAX_DB_W\0" 2080 /* 6236 */ "SUB_W\0" 2081 /* 6242 */ "CRCC_W_B_W\0" 2082 /* 6253 */ "CRC_W_B_W\0" 2083 /* 6263 */ "SC_W\0" 2084 /* 6268 */ "AMADD_W\0" 2085 /* 6276 */ "LD_W\0" 2086 /* 6281 */ "AMAND_W\0" 2087 /* 6289 */ "MOD_W\0" 2088 /* 6295 */ "IOCSRRD_W\0" 2089 /* 6305 */ "FFINT_D_W\0" 2090 /* 6315 */ "MULW_D_W\0" 2091 /* 6324 */ "CRCC_W_D_W\0" 2092 /* 6335 */ "CRC_W_D_W\0" 2093 /* 6345 */ "LDLE_W\0" 2094 /* 6352 */ "STLE_W\0" 2095 /* 6359 */ "RDTIMEH_W\0" 2096 /* 6369 */ "MULH_W\0" 2097 /* 6376 */ "MOVGR2FRH_W\0" 2098 /* 6388 */ "CRCC_W_H_W\0" 2099 /* 6399 */ "CRC_W_H_W\0" 2100 /* 6409 */ "LU12I_W\0" 2101 /* 6417 */ "SRAI_W\0" 2102 /* 6424 */ "ADDI_W\0" 2103 /* 6431 */ "SLLI_W\0" 2104 /* 6438 */ "SRLI_W\0" 2105 /* 6445 */ "PseudoLI_W\0" 2106 /* 6456 */ "ROTRI_W\0" 2107 /* 6464 */ "BYTEPICK_W\0" 2108 /* 6475 */ "BSTRPICK_W\0" 2109 /* 6486 */ "RDTIMEL_W\0" 2110 /* 6496 */ "SLL_W\0" 2111 /* 6502 */ "SRL_W\0" 2112 /* 6508 */ "ALSL_W\0" 2113 /* 6515 */ "MUL_W\0" 2114 /* 6521 */ "AMMIN_W\0" 2115 /* 6529 */ "CLO_W\0" 2116 /* 6535 */ "CTO_W\0" 2117 /* 6541 */ "AMSWAP_W\0" 2118 /* 6550 */ "MOVGR2FR_W\0" 2119 /* 6561 */ "AMOR_W\0" 2120 /* 6568 */ "AMXOR_W\0" 2121 /* 6576 */ "ROTR_W\0" 2122 /* 6583 */ "LDPTR_W\0" 2123 /* 6591 */ "STPTR_W\0" 2124 /* 6599 */ "IOCSRWR_W\0" 2125 /* 6609 */ "BSTRINS_W\0" 2126 /* 6619 */ "FFINT_S_W\0" 2127 /* 6629 */ "LDGT_W\0" 2128 /* 6636 */ "STGT_W\0" 2129 /* 6643 */ "ST_W\0" 2130 /* 6648 */ "BITREV_W\0" 2131 /* 6657 */ "DIV_W\0" 2132 /* 6663 */ "CRCC_W_W_W\0" 2133 /* 6674 */ "CRC_W_W_W\0" 2134 /* 6684 */ "AMMAX_W\0" 2135 /* 6692 */ "LDX_W\0" 2136 /* 6698 */ "STX_W\0" 2137 /* 6704 */ "CLZ_W\0" 2138 /* 6710 */ "CTZ_W\0" 2139 /* 6716 */ "PseudoAtomicStoreW\0" 2140 /* 6735 */ "G_VECREDUCE_FMAX\0" 2141 /* 6752 */ "G_ATOMICRMW_FMAX\0" 2142 /* 6769 */ "G_VECREDUCE_SMAX\0" 2143 /* 6786 */ "G_SMAX\0" 2144 /* 6793 */ "G_VECREDUCE_UMAX\0" 2145 /* 6810 */ "G_UMAX\0" 2146 /* 6817 */ "G_ATOMICRMW_UMAX\0" 2147 /* 6834 */ "G_ATOMICRMW_MAX\0" 2148 /* 6850 */ "PRELDX\0" 2149 /* 6857 */ "G_FRAME_INDEX\0" 2150 /* 6871 */ "G_SBFX\0" 2151 /* 6878 */ "G_UBFX\0" 2152 /* 6885 */ "G_SMULFIX\0" 2153 /* 6895 */ "G_UMULFIX\0" 2154 /* 6905 */ "G_SDIVFIX\0" 2155 /* 6915 */ "G_UDIVFIX\0" 2156 /* 6925 */ "G_MEMCPY\0" 2157 /* 6934 */ "COPY\0" 2158 /* 6939 */ "BNEZ\0" 2159 /* 6944 */ "BCNEZ\0" 2160 /* 6950 */ "MASKNEZ\0" 2161 /* 6958 */ "G_CTLZ\0" 2162 /* 6965 */ "BEQZ\0" 2163 /* 6970 */ "BCEQZ\0" 2164 /* 6976 */ "MASKEQZ\0" 2165 /* 6984 */ "G_CTTZ\0" 2166 /* 6991 */ "PseudoTAILIndirect\0" 2167 /* 7010 */ "PseudoCALLIndirect\0" 2168}; 2169#ifdef __GNUC__ 2170#pragma GCC diagnostic pop 2171#endif 2172 2173extern const unsigned LoongArchInstrNameIndices[] = { 2174 3095U, 3602U, 4132U, 3830U, 3184U, 3165U, 3193U, 3429U, 2175 2785U, 2800U, 2751U, 2827U, 4590U, 2644U, 5821U, 2764U, 2176 3091U, 3174U, 2323U, 6934U, 2545U, 5725U, 1081U, 2274U, 2177 2311U, 3928U, 3398U, 5641U, 1178U, 4087U, 2905U, 5630U, 2178 2588U, 4060U, 4047U, 4178U, 5494U, 5527U, 3314U, 3377U, 2179 3350U, 3210U, 4167U, 5851U, 5881U, 3681U, 956U, 589U, 2180 3521U, 6116U, 6123U, 3568U, 3575U, 3582U, 3592U, 1059U, 2181 4433U, 4396U, 2749U, 3093U, 6857U, 2654U, 5462U, 4534U, 2182 5762U, 4551U, 4348U, 737U, 4573U, 5652U, 4485U, 5794U, 2183 2679U, 1152U, 711U, 1134U, 5671U, 3659U, 4203U, 857U, 2184 801U, 831U, 842U, 782U, 812U, 2617U, 2601U, 4620U, 2185 2848U, 2873U, 972U, 595U, 1065U, 1026U, 4438U, 4402U, 2186 6834U, 3807U, 6817U, 3790U, 923U, 572U, 6752U, 3725U, 2187 3959U, 3937U, 2303U, 1106U, 5481U, 5740U, 689U, 4650U, 2188 5865U, 729U, 5619U, 5607U, 5715U, 2897U, 5844U, 2814U, 2189 5874U, 3252U, 4315U, 4301U, 3245U, 4308U, 4478U, 3439U, 2190 4014U, 4007U, 5472U, 3896U, 2344U, 3880U, 2295U, 3888U, 2191 2336U, 3872U, 2287U, 3912U, 3904U, 2954U, 2946U, 5380U, 2192 5370U, 5360U, 5350U, 5400U, 5390U, 6885U, 6895U, 5410U, 2193 5423U, 6905U, 6915U, 5436U, 5449U, 881U, 551U, 3463U, 2194 505U, 775U, 6095U, 3547U, 6146U, 3133U, 4106U, 430U, 2195 2890U, 422U, 0U, 2778U, 5836U, 701U, 3104U, 3118U, 2196 3989U, 3998U, 4508U, 3696U, 4607U, 2688U, 3634U, 3644U, 2197 2352U, 2367U, 3612U, 3623U, 962U, 3147U, 3759U, 6786U, 2198 3783U, 6810U, 4528U, 1125U, 1115U, 4127U, 5551U, 5583U, 2199 5562U, 4363U, 6984U, 2731U, 6958U, 2713U, 4039U, 3981U, 2200 2625U, 3298U, 4566U, 3823U, 5771U, 4339U, 5663U, 5689U, 2201 5804U, 4154U, 2527U, 758U, 909U, 558U, 3491U, 6102U, 2202 3554U, 511U, 5779U, 4222U, 4238U, 6925U, 2572U, 2669U, 2203 5518U, 3920U, 888U, 3470U, 864U, 3446U, 6735U, 3708U, 2204 940U, 3505U, 1043U, 4418U, 4380U, 6769U, 3742U, 6793U, 2205 3766U, 6871U, 6878U, 3855U, 4072U, 87U, 109U, 160U, 2206 466U, 322U, 37U, 343U, 2255U, 6716U, 303U, 4145U, 2207 1094U, 3258U, 3410U, 7010U, 205U, 489U, 3334U, 3271U, 2208 4515U, 2473U, 5702U, 2492U, 3230U, 2452U, 988U, 2386U, 2209 2511U, 2430U, 1010U, 2408U, 2552U, 4255U, 1645U, 6445U, 2210 59U, 394U, 250U, 131U, 9U, 365U, 221U, 278U, 2211 183U, 5508U, 4268U, 3287U, 6991U, 4021U, 4464U, 4471U, 2212 1624U, 6424U, 1607U, 1361U, 6270U, 1705U, 6508U, 6055U, 2213 1367U, 1229U, 6159U, 6268U, 1398U, 1240U, 6170U, 6281U, 2214 2221U, 1295U, 5920U, 6225U, 6012U, 5963U, 6684U, 6079U, 2215 1797U, 1251U, 5908U, 6181U, 6000U, 5947U, 6521U, 6063U, 2216 1936U, 1274U, 6204U, 6561U, 1839U, 1262U, 6192U, 6541U, 2217 1954U, 1284U, 6214U, 6568U, 1039U, 3086U, 3654U, 2038U, 2218 1452U, 532U, 6970U, 6944U, 4113U, 6965U, 2382U, 5972U, 2219 524U, 534U, 2132U, 6648U, 3157U, 5558U, 5990U, 2568U, 2220 6939U, 3141U, 2002U, 6609U, 1675U, 6475U, 1664U, 6464U, 2221 4033U, 1827U, 6529U, 2243U, 6704U, 2841U, 6242U, 6324U, 2222 6388U, 6663U, 6253U, 6335U, 6399U, 6674U, 1201U, 4502U, 2223 2865U, 1833U, 6535U, 2249U, 6710U, 4117U, 3160U, 2142U, 2224 5956U, 6657U, 6072U, 3850U, 669U, 3029U, 1995U, 5147U, 2225 1360U, 4735U, 2012U, 5154U, 1548U, 4882U, 1857U, 5045U, 2226 1422U, 4774U, 2055U, 5179U, 1502U, 4836U, 1925U, 5125U, 2227 1879U, 5067U, 1469U, 4812U, 2077U, 5201U, 1524U, 4858U, 2228 1805U, 5014U, 1559U, 4893U, 1868U, 5056U, 1441U, 4793U, 2229 2066U, 5190U, 1513U, 4847U, 1943U, 5136U, 1891U, 5079U, 2230 1481U, 4824U, 2089U, 5213U, 1536U, 4870U, 1816U, 5025U, 2231 1778U, 4995U, 4765U, 2021U, 2141U, 5256U, 3527U, 6305U, 2232 3537U, 6619U, 2030U, 5163U, 1433U, 4785U, 2229U, 5336U, 2233 1392U, 4759U, 1316U, 4703U, 1375U, 4742U, 1221U, 4685U, 2234 2214U, 5329U, 1207U, 4677U, 1790U, 5007U, 2148U, 5263U, 2235 1331U, 4718U, 1712U, 4929U, 1570U, 4915U, 1383U, 4750U, 2236 1339U, 4726U, 1848U, 5036U, 2101U, 5225U, 2117U, 5241U, 2237 1306U, 4693U, 1686U, 4922U, 2109U, 5233U, 2047U, 5171U, 2238 1461U, 4804U, 2236U, 5343U, 2126U, 5250U, 1324U, 4711U, 2239 1732U, 4949U, 2168U, 5283U, 1719U, 4936U, 2155U, 5270U, 2240 1744U, 4961U, 2180U, 5295U, 1766U, 4983U, 2202U, 5317U, 2241 1756U, 4973U, 2192U, 5307U, 4122U, 2540U, 544U, 616U, 2242 1412U, 2976U, 6295U, 640U, 1985U, 3000U, 6599U, 3434U, 2243 4322U, 650U, 2031U, 3010U, 6629U, 626U, 1434U, 2986U, 2244 6345U, 2638U, 1969U, 6583U, 677U, 5901U, 2230U, 3037U, 2245 5983U, 6692U, 6088U, 611U, 5895U, 1393U, 2971U, 5977U, 2246 6276U, 6024U, 1694U, 6497U, 6409U, 1591U, 1599U, 6976U, 2247 6950U, 1406U, 5932U, 6289U, 6030U, 5091U, 4281U, 4290U, 2248 4904U, 1914U, 5114U, 438U, 5102U, 2704U, 4453U, 6376U, 2249 1903U, 6550U, 452U, 1577U, 5939U, 6369U, 6047U, 6315U, 2250 6037U, 1713U, 6515U, 4335U, 4336U, 3100U, 3846U, 3079U, 2251 3059U, 3069U, 3049U, 1004U, 6850U, 6359U, 6486U, 1493U, 2252 2922U, 6130U, 2930U, 1348U, 6138U, 1584U, 1656U, 6456U, 2253 1962U, 6576U, 1355U, 6263U, 1631U, 6431U, 1693U, 6496U, 2254 5603U, 3113U, 5995U, 3127U, 1617U, 6417U, 1215U, 6153U, 2255 1638U, 6438U, 1699U, 6502U, 657U, 2048U, 3017U, 6636U, 2256 633U, 1462U, 2993U, 6352U, 1977U, 6591U, 683U, 2237U, 2257 3043U, 6698U, 664U, 2127U, 3024U, 6643U, 1325U, 6236U, 2258 3306U, 4328U, 3421U, 2962U, 1195U, 2938U, 4496U, 4392U, 2259 3099U, 2260}; 2261 2262static inline void InitLoongArchMCInstrInfo(MCInstrInfo *II) { 2263 II->InitMCInstrInfo(LoongArchInsts, LoongArchInstrNameIndices, LoongArchInstrNameData, nullptr, nullptr, 681); 2264} 2265 2266} // end namespace llvm 2267#endif // GET_INSTRINFO_MC_DESC 2268 2269#ifdef GET_INSTRINFO_HEADER 2270#undef GET_INSTRINFO_HEADER 2271namespace llvm { 2272struct LoongArchGenInstrInfo : public TargetInstrInfo { 2273 explicit LoongArchGenInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u); 2274 ~LoongArchGenInstrInfo() override = default; 2275 2276}; 2277} // end namespace llvm 2278#endif // GET_INSTRINFO_HEADER 2279 2280#ifdef GET_INSTRINFO_HELPER_DECLS 2281#undef GET_INSTRINFO_HELPER_DECLS 2282 2283 2284#endif // GET_INSTRINFO_HELPER_DECLS 2285 2286#ifdef GET_INSTRINFO_HELPERS 2287#undef GET_INSTRINFO_HELPERS 2288 2289#endif // GET_INSTRINFO_HELPERS 2290 2291#ifdef GET_INSTRINFO_CTOR_DTOR 2292#undef GET_INSTRINFO_CTOR_DTOR 2293namespace llvm { 2294extern const MCInstrDesc LoongArchInsts[]; 2295extern const unsigned LoongArchInstrNameIndices[]; 2296extern const char LoongArchInstrNameData[]; 2297LoongArchGenInstrInfo::LoongArchGenInstrInfo(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode) 2298 : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) { 2299 InitMCInstrInfo(LoongArchInsts, LoongArchInstrNameIndices, LoongArchInstrNameData, nullptr, nullptr, 681); 2300} 2301} // end namespace llvm 2302#endif // GET_INSTRINFO_CTOR_DTOR 2303 2304#ifdef GET_INSTRINFO_OPERAND_ENUM 2305#undef GET_INSTRINFO_OPERAND_ENUM 2306namespace llvm { 2307namespace LoongArch { 2308namespace OpName { 2309enum { 2310 OPERAND_LAST 2311}; 2312} // end namespace OpName 2313} // end namespace LoongArch 2314} // end namespace llvm 2315#endif //GET_INSTRINFO_OPERAND_ENUM 2316 2317#ifdef GET_INSTRINFO_NAMED_OPS 2318#undef GET_INSTRINFO_NAMED_OPS 2319namespace llvm { 2320namespace LoongArch { 2321LLVM_READONLY 2322int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) { 2323 return -1; 2324} 2325} // end namespace LoongArch 2326} // end namespace llvm 2327#endif //GET_INSTRINFO_NAMED_OPS 2328 2329#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM 2330#undef GET_INSTRINFO_OPERAND_TYPES_ENUM 2331namespace llvm { 2332namespace LoongArch { 2333namespace OpTypes { 2334enum OperandType { 2335 bare_symbol = 0, 2336 f32imm = 1, 2337 f64imm = 2, 2338 grlenimm = 3, 2339 i16imm = 4, 2340 i1imm = 5, 2341 i32imm = 6, 2342 i64imm = 7, 2343 i8imm = 8, 2344 imm32 = 9, 2345 ptype0 = 10, 2346 ptype1 = 11, 2347 ptype2 = 12, 2348 ptype3 = 13, 2349 ptype4 = 14, 2350 ptype5 = 15, 2351 simm12 = 16, 2352 simm12_addlike = 17, 2353 simm12_lu52id = 18, 2354 simm14_lsl2 = 19, 2355 simm16 = 20, 2356 simm16_lsl2 = 21, 2357 simm16_lsl2_br = 22, 2358 simm20 = 23, 2359 simm20_lu12iw = 24, 2360 simm20_lu32id = 25, 2361 simm20_pcalau12i = 26, 2362 simm21_lsl2 = 27, 2363 simm26_b = 28, 2364 simm26_symbol = 29, 2365 type0 = 30, 2366 type1 = 31, 2367 type2 = 32, 2368 type3 = 33, 2369 type4 = 34, 2370 type5 = 35, 2371 uimm12 = 36, 2372 uimm12_ori = 37, 2373 uimm14 = 38, 2374 uimm15 = 39, 2375 uimm2 = 40, 2376 uimm2_plus1 = 41, 2377 uimm3 = 42, 2378 uimm5 = 43, 2379 uimm6 = 44, 2380 uimm8 = 45, 2381 untyped_imm_0 = 46, 2382 GPRMemAtomic = 47, 2383 CFR = 48, 2384 FCSR = 49, 2385 FPR32 = 50, 2386 FPR64 = 51, 2387 GPR = 52, 2388 GPRT = 53, 2389 OPERAND_TYPE_LIST_END 2390}; 2391} // end namespace OpTypes 2392} // end namespace LoongArch 2393} // end namespace llvm 2394#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM 2395 2396#ifdef GET_INSTRINFO_OPERAND_TYPE 2397#undef GET_INSTRINFO_OPERAND_TYPE 2398namespace llvm { 2399namespace LoongArch { 2400LLVM_READONLY 2401static int getOperandType(uint16_t Opcode, uint16_t OpIdx) { 2402 const uint16_t Offsets[] = { 2403 /* PHI */ 2404 0, 2405 /* INLINEASM */ 2406 1, 2407 /* INLINEASM_BR */ 2408 1, 2409 /* CFI_INSTRUCTION */ 2410 1, 2411 /* EH_LABEL */ 2412 2, 2413 /* GC_LABEL */ 2414 3, 2415 /* ANNOTATION_LABEL */ 2416 4, 2417 /* KILL */ 2418 5, 2419 /* EXTRACT_SUBREG */ 2420 5, 2421 /* INSERT_SUBREG */ 2422 8, 2423 /* IMPLICIT_DEF */ 2424 12, 2425 /* SUBREG_TO_REG */ 2426 13, 2427 /* COPY_TO_REGCLASS */ 2428 17, 2429 /* DBG_VALUE */ 2430 20, 2431 /* DBG_VALUE_LIST */ 2432 20, 2433 /* DBG_INSTR_REF */ 2434 20, 2435 /* DBG_PHI */ 2436 20, 2437 /* DBG_LABEL */ 2438 20, 2439 /* REG_SEQUENCE */ 2440 21, 2441 /* COPY */ 2442 23, 2443 /* BUNDLE */ 2444 25, 2445 /* LIFETIME_START */ 2446 25, 2447 /* LIFETIME_END */ 2448 26, 2449 /* PSEUDO_PROBE */ 2450 27, 2451 /* ARITH_FENCE */ 2452 31, 2453 /* STACKMAP */ 2454 33, 2455 /* FENTRY_CALL */ 2456 35, 2457 /* PATCHPOINT */ 2458 35, 2459 /* LOAD_STACK_GUARD */ 2460 41, 2461 /* PREALLOCATED_SETUP */ 2462 42, 2463 /* PREALLOCATED_ARG */ 2464 43, 2465 /* STATEPOINT */ 2466 46, 2467 /* LOCAL_ESCAPE */ 2468 46, 2469 /* FAULTING_OP */ 2470 48, 2471 /* PATCHABLE_OP */ 2472 49, 2473 /* PATCHABLE_FUNCTION_ENTER */ 2474 49, 2475 /* PATCHABLE_RET */ 2476 49, 2477 /* PATCHABLE_FUNCTION_EXIT */ 2478 49, 2479 /* PATCHABLE_TAIL_CALL */ 2480 49, 2481 /* PATCHABLE_EVENT_CALL */ 2482 49, 2483 /* PATCHABLE_TYPED_EVENT_CALL */ 2484 51, 2485 /* ICALL_BRANCH_FUNNEL */ 2486 54, 2487 /* MEMBARRIER */ 2488 54, 2489 /* G_ASSERT_SEXT */ 2490 54, 2491 /* G_ASSERT_ZEXT */ 2492 57, 2493 /* G_ASSERT_ALIGN */ 2494 60, 2495 /* G_ADD */ 2496 63, 2497 /* G_SUB */ 2498 66, 2499 /* G_MUL */ 2500 69, 2501 /* G_SDIV */ 2502 72, 2503 /* G_UDIV */ 2504 75, 2505 /* G_SREM */ 2506 78, 2507 /* G_UREM */ 2508 81, 2509 /* G_SDIVREM */ 2510 84, 2511 /* G_UDIVREM */ 2512 88, 2513 /* G_AND */ 2514 92, 2515 /* G_OR */ 2516 95, 2517 /* G_XOR */ 2518 98, 2519 /* G_IMPLICIT_DEF */ 2520 101, 2521 /* G_PHI */ 2522 102, 2523 /* G_FRAME_INDEX */ 2524 103, 2525 /* G_GLOBAL_VALUE */ 2526 105, 2527 /* G_EXTRACT */ 2528 107, 2529 /* G_UNMERGE_VALUES */ 2530 110, 2531 /* G_INSERT */ 2532 112, 2533 /* G_MERGE_VALUES */ 2534 116, 2535 /* G_BUILD_VECTOR */ 2536 118, 2537 /* G_BUILD_VECTOR_TRUNC */ 2538 120, 2539 /* G_CONCAT_VECTORS */ 2540 122, 2541 /* G_PTRTOINT */ 2542 124, 2543 /* G_INTTOPTR */ 2544 126, 2545 /* G_BITCAST */ 2546 128, 2547 /* G_FREEZE */ 2548 130, 2549 /* G_INTRINSIC_FPTRUNC_ROUND */ 2550 132, 2551 /* G_INTRINSIC_TRUNC */ 2552 135, 2553 /* G_INTRINSIC_ROUND */ 2554 137, 2555 /* G_INTRINSIC_LRINT */ 2556 139, 2557 /* G_INTRINSIC_ROUNDEVEN */ 2558 141, 2559 /* G_READCYCLECOUNTER */ 2560 143, 2561 /* G_LOAD */ 2562 144, 2563 /* G_SEXTLOAD */ 2564 146, 2565 /* G_ZEXTLOAD */ 2566 148, 2567 /* G_INDEXED_LOAD */ 2568 150, 2569 /* G_INDEXED_SEXTLOAD */ 2570 155, 2571 /* G_INDEXED_ZEXTLOAD */ 2572 160, 2573 /* G_STORE */ 2574 165, 2575 /* G_INDEXED_STORE */ 2576 167, 2577 /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */ 2578 172, 2579 /* G_ATOMIC_CMPXCHG */ 2580 177, 2581 /* G_ATOMICRMW_XCHG */ 2582 181, 2583 /* G_ATOMICRMW_ADD */ 2584 184, 2585 /* G_ATOMICRMW_SUB */ 2586 187, 2587 /* G_ATOMICRMW_AND */ 2588 190, 2589 /* G_ATOMICRMW_NAND */ 2590 193, 2591 /* G_ATOMICRMW_OR */ 2592 196, 2593 /* G_ATOMICRMW_XOR */ 2594 199, 2595 /* G_ATOMICRMW_MAX */ 2596 202, 2597 /* G_ATOMICRMW_MIN */ 2598 205, 2599 /* G_ATOMICRMW_UMAX */ 2600 208, 2601 /* G_ATOMICRMW_UMIN */ 2602 211, 2603 /* G_ATOMICRMW_FADD */ 2604 214, 2605 /* G_ATOMICRMW_FSUB */ 2606 217, 2607 /* G_ATOMICRMW_FMAX */ 2608 220, 2609 /* G_ATOMICRMW_FMIN */ 2610 223, 2611 /* G_ATOMICRMW_UINC_WRAP */ 2612 226, 2613 /* G_ATOMICRMW_UDEC_WRAP */ 2614 229, 2615 /* G_FENCE */ 2616 232, 2617 /* G_BRCOND */ 2618 234, 2619 /* G_BRINDIRECT */ 2620 236, 2621 /* G_INVOKE_REGION_START */ 2622 237, 2623 /* G_INTRINSIC */ 2624 237, 2625 /* G_INTRINSIC_W_SIDE_EFFECTS */ 2626 238, 2627 /* G_ANYEXT */ 2628 239, 2629 /* G_TRUNC */ 2630 241, 2631 /* G_CONSTANT */ 2632 243, 2633 /* G_FCONSTANT */ 2634 245, 2635 /* G_VASTART */ 2636 247, 2637 /* G_VAARG */ 2638 248, 2639 /* G_SEXT */ 2640 251, 2641 /* G_SEXT_INREG */ 2642 253, 2643 /* G_ZEXT */ 2644 256, 2645 /* G_SHL */ 2646 258, 2647 /* G_LSHR */ 2648 261, 2649 /* G_ASHR */ 2650 264, 2651 /* G_FSHL */ 2652 267, 2653 /* G_FSHR */ 2654 271, 2655 /* G_ROTR */ 2656 275, 2657 /* G_ROTL */ 2658 278, 2659 /* G_ICMP */ 2660 281, 2661 /* G_FCMP */ 2662 285, 2663 /* G_SELECT */ 2664 289, 2665 /* G_UADDO */ 2666 293, 2667 /* G_UADDE */ 2668 297, 2669 /* G_USUBO */ 2670 302, 2671 /* G_USUBE */ 2672 306, 2673 /* G_SADDO */ 2674 311, 2675 /* G_SADDE */ 2676 315, 2677 /* G_SSUBO */ 2678 320, 2679 /* G_SSUBE */ 2680 324, 2681 /* G_UMULO */ 2682 329, 2683 /* G_SMULO */ 2684 333, 2685 /* G_UMULH */ 2686 337, 2687 /* G_SMULH */ 2688 340, 2689 /* G_UADDSAT */ 2690 343, 2691 /* G_SADDSAT */ 2692 346, 2693 /* G_USUBSAT */ 2694 349, 2695 /* G_SSUBSAT */ 2696 352, 2697 /* G_USHLSAT */ 2698 355, 2699 /* G_SSHLSAT */ 2700 358, 2701 /* G_SMULFIX */ 2702 361, 2703 /* G_UMULFIX */ 2704 365, 2705 /* G_SMULFIXSAT */ 2706 369, 2707 /* G_UMULFIXSAT */ 2708 373, 2709 /* G_SDIVFIX */ 2710 377, 2711 /* G_UDIVFIX */ 2712 381, 2713 /* G_SDIVFIXSAT */ 2714 385, 2715 /* G_UDIVFIXSAT */ 2716 389, 2717 /* G_FADD */ 2718 393, 2719 /* G_FSUB */ 2720 396, 2721 /* G_FMUL */ 2722 399, 2723 /* G_FMA */ 2724 402, 2725 /* G_FMAD */ 2726 406, 2727 /* G_FDIV */ 2728 410, 2729 /* G_FREM */ 2730 413, 2731 /* G_FPOW */ 2732 416, 2733 /* G_FPOWI */ 2734 419, 2735 /* G_FEXP */ 2736 422, 2737 /* G_FEXP2 */ 2738 424, 2739 /* G_FLOG */ 2740 426, 2741 /* G_FLOG2 */ 2742 428, 2743 /* G_FLOG10 */ 2744 430, 2745 /* G_FNEG */ 2746 432, 2747 /* G_FPEXT */ 2748 434, 2749 /* G_FPTRUNC */ 2750 436, 2751 /* G_FPTOSI */ 2752 438, 2753 /* G_FPTOUI */ 2754 440, 2755 /* G_SITOFP */ 2756 442, 2757 /* G_UITOFP */ 2758 444, 2759 /* G_FABS */ 2760 446, 2761 /* G_FCOPYSIGN */ 2762 448, 2763 /* G_IS_FPCLASS */ 2764 451, 2765 /* G_FCANONICALIZE */ 2766 454, 2767 /* G_FMINNUM */ 2768 456, 2769 /* G_FMAXNUM */ 2770 459, 2771 /* G_FMINNUM_IEEE */ 2772 462, 2773 /* G_FMAXNUM_IEEE */ 2774 465, 2775 /* G_FMINIMUM */ 2776 468, 2777 /* G_FMAXIMUM */ 2778 471, 2779 /* G_PTR_ADD */ 2780 474, 2781 /* G_PTRMASK */ 2782 477, 2783 /* G_SMIN */ 2784 480, 2785 /* G_SMAX */ 2786 483, 2787 /* G_UMIN */ 2788 486, 2789 /* G_UMAX */ 2790 489, 2791 /* G_ABS */ 2792 492, 2793 /* G_LROUND */ 2794 494, 2795 /* G_LLROUND */ 2796 496, 2797 /* G_BR */ 2798 498, 2799 /* G_BRJT */ 2800 499, 2801 /* G_INSERT_VECTOR_ELT */ 2802 502, 2803 /* G_EXTRACT_VECTOR_ELT */ 2804 506, 2805 /* G_SHUFFLE_VECTOR */ 2806 509, 2807 /* G_CTTZ */ 2808 513, 2809 /* G_CTTZ_ZERO_UNDEF */ 2810 515, 2811 /* G_CTLZ */ 2812 517, 2813 /* G_CTLZ_ZERO_UNDEF */ 2814 519, 2815 /* G_CTPOP */ 2816 521, 2817 /* G_BSWAP */ 2818 523, 2819 /* G_BITREVERSE */ 2820 525, 2821 /* G_FCEIL */ 2822 527, 2823 /* G_FCOS */ 2824 529, 2825 /* G_FSIN */ 2826 531, 2827 /* G_FSQRT */ 2828 533, 2829 /* G_FFLOOR */ 2830 535, 2831 /* G_FRINT */ 2832 537, 2833 /* G_FNEARBYINT */ 2834 539, 2835 /* G_ADDRSPACE_CAST */ 2836 541, 2837 /* G_BLOCK_ADDR */ 2838 543, 2839 /* G_JUMP_TABLE */ 2840 545, 2841 /* G_DYN_STACKALLOC */ 2842 547, 2843 /* G_STRICT_FADD */ 2844 550, 2845 /* G_STRICT_FSUB */ 2846 553, 2847 /* G_STRICT_FMUL */ 2848 556, 2849 /* G_STRICT_FDIV */ 2850 559, 2851 /* G_STRICT_FREM */ 2852 562, 2853 /* G_STRICT_FMA */ 2854 565, 2855 /* G_STRICT_FSQRT */ 2856 569, 2857 /* G_READ_REGISTER */ 2858 571, 2859 /* G_WRITE_REGISTER */ 2860 573, 2861 /* G_MEMCPY */ 2862 575, 2863 /* G_MEMCPY_INLINE */ 2864 579, 2865 /* G_MEMMOVE */ 2866 582, 2867 /* G_MEMSET */ 2868 586, 2869 /* G_BZERO */ 2870 590, 2871 /* G_VECREDUCE_SEQ_FADD */ 2872 593, 2873 /* G_VECREDUCE_SEQ_FMUL */ 2874 596, 2875 /* G_VECREDUCE_FADD */ 2876 599, 2877 /* G_VECREDUCE_FMUL */ 2878 601, 2879 /* G_VECREDUCE_FMAX */ 2880 603, 2881 /* G_VECREDUCE_FMIN */ 2882 605, 2883 /* G_VECREDUCE_ADD */ 2884 607, 2885 /* G_VECREDUCE_MUL */ 2886 609, 2887 /* G_VECREDUCE_AND */ 2888 611, 2889 /* G_VECREDUCE_OR */ 2890 613, 2891 /* G_VECREDUCE_XOR */ 2892 615, 2893 /* G_VECREDUCE_SMAX */ 2894 617, 2895 /* G_VECREDUCE_SMIN */ 2896 619, 2897 /* G_VECREDUCE_UMAX */ 2898 621, 2899 /* G_VECREDUCE_UMIN */ 2900 623, 2901 /* G_SBFX */ 2902 625, 2903 /* G_UBFX */ 2904 629, 2905 /* ADJCALLSTACKDOWN */ 2906 633, 2907 /* ADJCALLSTACKUP */ 2908 635, 2909 /* PseudoAtomicLoadAdd32 */ 2910 637, 2911 /* PseudoAtomicLoadAnd32 */ 2912 642, 2913 /* PseudoAtomicLoadNand32 */ 2914 647, 2915 /* PseudoAtomicLoadNand64 */ 2916 652, 2917 /* PseudoAtomicLoadOr32 */ 2918 657, 2919 /* PseudoAtomicLoadSub32 */ 2920 662, 2921 /* PseudoAtomicLoadXor32 */ 2922 667, 2923 /* PseudoAtomicStoreD */ 2924 672, 2925 /* PseudoAtomicStoreW */ 2926 675, 2927 /* PseudoAtomicSwap32 */ 2928 678, 2929 /* PseudoBR */ 2930 683, 2931 /* PseudoBRIND */ 2932 684, 2933 /* PseudoB_TAIL */ 2934 686, 2935 /* PseudoCALL */ 2936 687, 2937 /* PseudoCALLIndirect */ 2938 688, 2939 /* PseudoCmpXchg32 */ 2940 689, 2941 /* PseudoCmpXchg64 */ 2942 694, 2943 /* PseudoJIRL_CALL */ 2944 699, 2945 /* PseudoJIRL_TAIL */ 2946 701, 2947 /* PseudoLA_ABS */ 2948 703, 2949 /* PseudoLA_ABS_LARGE */ 2950 705, 2951 /* PseudoLA_GOT */ 2952 708, 2953 /* PseudoLA_GOT_LARGE */ 2954 710, 2955 /* PseudoLA_PCREL */ 2956 713, 2957 /* PseudoLA_PCREL_LARGE */ 2958 715, 2959 /* PseudoLA_TLS_GD */ 2960 718, 2961 /* PseudoLA_TLS_GD_LARGE */ 2962 720, 2963 /* PseudoLA_TLS_IE */ 2964 723, 2965 /* PseudoLA_TLS_IE_LARGE */ 2966 725, 2967 /* PseudoLA_TLS_LD */ 2968 728, 2969 /* PseudoLA_TLS_LD_LARGE */ 2970 730, 2971 /* PseudoLA_TLS_LE */ 2972 733, 2973 /* PseudoLD_CFR */ 2974 735, 2975 /* PseudoLI_D */ 2976 738, 2977 /* PseudoLI_W */ 2978 740, 2979 /* PseudoMaskedAtomicLoadAdd32 */ 2980 742, 2981 /* PseudoMaskedAtomicLoadMax32 */ 2982 748, 2983 /* PseudoMaskedAtomicLoadMin32 */ 2984 756, 2985 /* PseudoMaskedAtomicLoadNand32 */ 2986 764, 2987 /* PseudoMaskedAtomicLoadSub32 */ 2988 770, 2989 /* PseudoMaskedAtomicLoadUMax32 */ 2990 776, 2991 /* PseudoMaskedAtomicLoadUMin32 */ 2992 783, 2993 /* PseudoMaskedAtomicSwap32 */ 2994 790, 2995 /* PseudoMaskedCmpXchg32 */ 2996 796, 2997 /* PseudoRET */ 2998 803, 2999 /* PseudoST_CFR */ 3000 803, 3001 /* PseudoTAIL */ 3002 806, 3003 /* PseudoTAILIndirect */ 3004 807, 3005 /* PseudoUNIMP */ 3006 808, 3007 /* RDFCSR */ 3008 808, 3009 /* WRFCSR */ 3010 810, 3011 /* ADDI_D */ 3012 812, 3013 /* ADDI_W */ 3014 815, 3015 /* ADDU16I_D */ 3016 818, 3017 /* ADD_D */ 3018 821, 3019 /* ADD_W */ 3020 824, 3021 /* ALSL_D */ 3022 827, 3023 /* ALSL_W */ 3024 831, 3025 /* ALSL_WU */ 3026 835, 3027 /* AMADD_D */ 3028 839, 3029 /* AMADD_DB_D */ 3030 842, 3031 /* AMADD_DB_W */ 3032 845, 3033 /* AMADD_W */ 3034 848, 3035 /* AMAND_D */ 3036 851, 3037 /* AMAND_DB_D */ 3038 854, 3039 /* AMAND_DB_W */ 3040 857, 3041 /* AMAND_W */ 3042 860, 3043 /* AMMAX_D */ 3044 863, 3045 /* AMMAX_DB_D */ 3046 866, 3047 /* AMMAX_DB_DU */ 3048 869, 3049 /* AMMAX_DB_W */ 3050 872, 3051 /* AMMAX_DB_WU */ 3052 875, 3053 /* AMMAX_DU */ 3054 878, 3055 /* AMMAX_W */ 3056 881, 3057 /* AMMAX_WU */ 3058 884, 3059 /* AMMIN_D */ 3060 887, 3061 /* AMMIN_DB_D */ 3062 890, 3063 /* AMMIN_DB_DU */ 3064 893, 3065 /* AMMIN_DB_W */ 3066 896, 3067 /* AMMIN_DB_WU */ 3068 899, 3069 /* AMMIN_DU */ 3070 902, 3071 /* AMMIN_W */ 3072 905, 3073 /* AMMIN_WU */ 3074 908, 3075 /* AMOR_D */ 3076 911, 3077 /* AMOR_DB_D */ 3078 914, 3079 /* AMOR_DB_W */ 3080 917, 3081 /* AMOR_W */ 3082 920, 3083 /* AMSWAP_D */ 3084 923, 3085 /* AMSWAP_DB_D */ 3086 926, 3087 /* AMSWAP_DB_W */ 3088 929, 3089 /* AMSWAP_W */ 3090 932, 3091 /* AMXOR_D */ 3092 935, 3093 /* AMXOR_DB_D */ 3094 938, 3095 /* AMXOR_DB_W */ 3096 941, 3097 /* AMXOR_W */ 3098 944, 3099 /* AND */ 3100 947, 3101 /* ANDI */ 3102 950, 3103 /* ANDN */ 3104 953, 3105 /* ASRTGT_D */ 3106 956, 3107 /* ASRTLE_D */ 3108 958, 3109 /* B */ 3110 960, 3111 /* BCEQZ */ 3112 961, 3113 /* BCNEZ */ 3114 963, 3115 /* BEQ */ 3116 965, 3117 /* BEQZ */ 3118 968, 3119 /* BGE */ 3120 970, 3121 /* BGEU */ 3122 973, 3123 /* BITREV_4B */ 3124 976, 3125 /* BITREV_8B */ 3126 978, 3127 /* BITREV_D */ 3128 980, 3129 /* BITREV_W */ 3130 982, 3131 /* BL */ 3132 984, 3133 /* BLT */ 3134 985, 3135 /* BLTU */ 3136 988, 3137 /* BNE */ 3138 991, 3139 /* BNEZ */ 3140 994, 3141 /* BREAK */ 3142 996, 3143 /* BSTRINS_D */ 3144 997, 3145 /* BSTRINS_W */ 3146 1002, 3147 /* BSTRPICK_D */ 3148 1007, 3149 /* BSTRPICK_W */ 3150 1011, 3151 /* BYTEPICK_D */ 3152 1015, 3153 /* BYTEPICK_W */ 3154 1019, 3155 /* CACOP */ 3156 1023, 3157 /* CLO_D */ 3158 1026, 3159 /* CLO_W */ 3160 1028, 3161 /* CLZ_D */ 3162 1030, 3163 /* CLZ_W */ 3164 1032, 3165 /* CPUCFG */ 3166 1034, 3167 /* CRCC_W_B_W */ 3168 1036, 3169 /* CRCC_W_D_W */ 3170 1039, 3171 /* CRCC_W_H_W */ 3172 1042, 3173 /* CRCC_W_W_W */ 3174 1045, 3175 /* CRC_W_B_W */ 3176 1048, 3177 /* CRC_W_D_W */ 3178 1051, 3179 /* CRC_W_H_W */ 3180 1054, 3181 /* CRC_W_W_W */ 3182 1057, 3183 /* CSRRD */ 3184 1060, 3185 /* CSRWR */ 3186 1062, 3187 /* CSRXCHG */ 3188 1065, 3189 /* CTO_D */ 3190 1069, 3191 /* CTO_W */ 3192 1071, 3193 /* CTZ_D */ 3194 1073, 3195 /* CTZ_W */ 3196 1075, 3197 /* DBAR */ 3198 1077, 3199 /* DBCL */ 3200 1078, 3201 /* DIV_D */ 3202 1079, 3203 /* DIV_DU */ 3204 1082, 3205 /* DIV_W */ 3206 1085, 3207 /* DIV_WU */ 3208 1088, 3209 /* ERTN */ 3210 1091, 3211 /* EXT_W_B */ 3212 1091, 3213 /* EXT_W_H */ 3214 1093, 3215 /* FABS_D */ 3216 1095, 3217 /* FABS_S */ 3218 1097, 3219 /* FADD_D */ 3220 1099, 3221 /* FADD_S */ 3222 1102, 3223 /* FCLASS_D */ 3224 1105, 3225 /* FCLASS_S */ 3226 1107, 3227 /* FCMP_CAF_D */ 3228 1109, 3229 /* FCMP_CAF_S */ 3230 1112, 3231 /* FCMP_CEQ_D */ 3232 1115, 3233 /* FCMP_CEQ_S */ 3234 1118, 3235 /* FCMP_CLE_D */ 3236 1121, 3237 /* FCMP_CLE_S */ 3238 1124, 3239 /* FCMP_CLT_D */ 3240 1127, 3241 /* FCMP_CLT_S */ 3242 1130, 3243 /* FCMP_CNE_D */ 3244 1133, 3245 /* FCMP_CNE_S */ 3246 1136, 3247 /* FCMP_COR_D */ 3248 1139, 3249 /* FCMP_COR_S */ 3250 1142, 3251 /* FCMP_CUEQ_D */ 3252 1145, 3253 /* FCMP_CUEQ_S */ 3254 1148, 3255 /* FCMP_CULE_D */ 3256 1151, 3257 /* FCMP_CULE_S */ 3258 1154, 3259 /* FCMP_CULT_D */ 3260 1157, 3261 /* FCMP_CULT_S */ 3262 1160, 3263 /* FCMP_CUNE_D */ 3264 1163, 3265 /* FCMP_CUNE_S */ 3266 1166, 3267 /* FCMP_CUN_D */ 3268 1169, 3269 /* FCMP_CUN_S */ 3270 1172, 3271 /* FCMP_SAF_D */ 3272 1175, 3273 /* FCMP_SAF_S */ 3274 1178, 3275 /* FCMP_SEQ_D */ 3276 1181, 3277 /* FCMP_SEQ_S */ 3278 1184, 3279 /* FCMP_SLE_D */ 3280 1187, 3281 /* FCMP_SLE_S */ 3282 1190, 3283 /* FCMP_SLT_D */ 3284 1193, 3285 /* FCMP_SLT_S */ 3286 1196, 3287 /* FCMP_SNE_D */ 3288 1199, 3289 /* FCMP_SNE_S */ 3290 1202, 3291 /* FCMP_SOR_D */ 3292 1205, 3293 /* FCMP_SOR_S */ 3294 1208, 3295 /* FCMP_SUEQ_D */ 3296 1211, 3297 /* FCMP_SUEQ_S */ 3298 1214, 3299 /* FCMP_SULE_D */ 3300 1217, 3301 /* FCMP_SULE_S */ 3302 1220, 3303 /* FCMP_SULT_D */ 3304 1223, 3305 /* FCMP_SULT_S */ 3306 1226, 3307 /* FCMP_SUNE_D */ 3308 1229, 3309 /* FCMP_SUNE_S */ 3310 1232, 3311 /* FCMP_SUN_D */ 3312 1235, 3313 /* FCMP_SUN_S */ 3314 1238, 3315 /* FCOPYSIGN_D */ 3316 1241, 3317 /* FCOPYSIGN_S */ 3318 1244, 3319 /* FCVT_D_S */ 3320 1247, 3321 /* FCVT_S_D */ 3322 1249, 3323 /* FDIV_D */ 3324 1251, 3325 /* FDIV_S */ 3326 1254, 3327 /* FFINT_D_L */ 3328 1257, 3329 /* FFINT_D_W */ 3330 1259, 3331 /* FFINT_S_L */ 3332 1261, 3333 /* FFINT_S_W */ 3334 1263, 3335 /* FLDGT_D */ 3336 1265, 3337 /* FLDGT_S */ 3338 1268, 3339 /* FLDLE_D */ 3340 1271, 3341 /* FLDLE_S */ 3342 1274, 3343 /* FLDX_D */ 3344 1277, 3345 /* FLDX_S */ 3346 1280, 3347 /* FLD_D */ 3348 1283, 3349 /* FLD_S */ 3350 1286, 3351 /* FLOGB_D */ 3352 1289, 3353 /* FLOGB_S */ 3354 1291, 3355 /* FMADD_D */ 3356 1293, 3357 /* FMADD_S */ 3358 1297, 3359 /* FMAXA_D */ 3360 1301, 3361 /* FMAXA_S */ 3362 1304, 3363 /* FMAX_D */ 3364 1307, 3365 /* FMAX_S */ 3366 1310, 3367 /* FMINA_D */ 3368 1313, 3369 /* FMINA_S */ 3370 1316, 3371 /* FMIN_D */ 3372 1319, 3373 /* FMIN_S */ 3374 1322, 3375 /* FMOV_D */ 3376 1325, 3377 /* FMOV_S */ 3378 1327, 3379 /* FMSUB_D */ 3380 1329, 3381 /* FMSUB_S */ 3382 1333, 3383 /* FMUL_D */ 3384 1337, 3385 /* FMUL_S */ 3386 1340, 3387 /* FNEG_D */ 3388 1343, 3389 /* FNEG_S */ 3390 1345, 3391 /* FNMADD_D */ 3392 1347, 3393 /* FNMADD_S */ 3394 1351, 3395 /* FNMSUB_D */ 3396 1355, 3397 /* FNMSUB_S */ 3398 1359, 3399 /* FRECIP_D */ 3400 1363, 3401 /* FRECIP_S */ 3402 1365, 3403 /* FRINT_D */ 3404 1367, 3405 /* FRINT_S */ 3406 1369, 3407 /* FRSQRT_D */ 3408 1371, 3409 /* FRSQRT_S */ 3410 1373, 3411 /* FSCALEB_D */ 3412 1375, 3413 /* FSCALEB_S */ 3414 1378, 3415 /* FSEL_D */ 3416 1381, 3417 /* FSEL_S */ 3418 1385, 3419 /* FSQRT_D */ 3420 1389, 3421 /* FSQRT_S */ 3422 1391, 3423 /* FSTGT_D */ 3424 1393, 3425 /* FSTGT_S */ 3426 1396, 3427 /* FSTLE_D */ 3428 1399, 3429 /* FSTLE_S */ 3430 1402, 3431 /* FSTX_D */ 3432 1405, 3433 /* FSTX_S */ 3434 1408, 3435 /* FST_D */ 3436 1411, 3437 /* FST_S */ 3438 1414, 3439 /* FSUB_D */ 3440 1417, 3441 /* FSUB_S */ 3442 1420, 3443 /* FTINTRM_L_D */ 3444 1423, 3445 /* FTINTRM_L_S */ 3446 1425, 3447 /* FTINTRM_W_D */ 3448 1427, 3449 /* FTINTRM_W_S */ 3450 1429, 3451 /* FTINTRNE_L_D */ 3452 1431, 3453 /* FTINTRNE_L_S */ 3454 1433, 3455 /* FTINTRNE_W_D */ 3456 1435, 3457 /* FTINTRNE_W_S */ 3458 1437, 3459 /* FTINTRP_L_D */ 3460 1439, 3461 /* FTINTRP_L_S */ 3462 1441, 3463 /* FTINTRP_W_D */ 3464 1443, 3465 /* FTINTRP_W_S */ 3466 1445, 3467 /* FTINTRZ_L_D */ 3468 1447, 3469 /* FTINTRZ_L_S */ 3470 1449, 3471 /* FTINTRZ_W_D */ 3472 1451, 3473 /* FTINTRZ_W_S */ 3474 1453, 3475 /* FTINT_L_D */ 3476 1455, 3477 /* FTINT_L_S */ 3478 1457, 3479 /* FTINT_W_D */ 3480 1459, 3481 /* FTINT_W_S */ 3482 1461, 3483 /* IBAR */ 3484 1463, 3485 /* IDLE */ 3486 1464, 3487 /* INVTLB */ 3488 1465, 3489 /* IOCSRRD_B */ 3490 1468, 3491 /* IOCSRRD_D */ 3492 1470, 3493 /* IOCSRRD_H */ 3494 1472, 3495 /* IOCSRRD_W */ 3496 1474, 3497 /* IOCSRWR_B */ 3498 1476, 3499 /* IOCSRWR_D */ 3500 1478, 3501 /* IOCSRWR_H */ 3502 1480, 3503 /* IOCSRWR_W */ 3504 1482, 3505 /* JIRL */ 3506 1484, 3507 /* LDDIR */ 3508 1487, 3509 /* LDGT_B */ 3510 1490, 3511 /* LDGT_D */ 3512 1493, 3513 /* LDGT_H */ 3514 1496, 3515 /* LDGT_W */ 3516 1499, 3517 /* LDLE_B */ 3518 1502, 3519 /* LDLE_D */ 3520 1505, 3521 /* LDLE_H */ 3522 1508, 3523 /* LDLE_W */ 3524 1511, 3525 /* LDPTE */ 3526 1514, 3527 /* LDPTR_D */ 3528 1516, 3529 /* LDPTR_W */ 3530 1519, 3531 /* LDX_B */ 3532 1522, 3533 /* LDX_BU */ 3534 1525, 3535 /* LDX_D */ 3536 1528, 3537 /* LDX_H */ 3538 1531, 3539 /* LDX_HU */ 3540 1534, 3541 /* LDX_W */ 3542 1537, 3543 /* LDX_WU */ 3544 1540, 3545 /* LD_B */ 3546 1543, 3547 /* LD_BU */ 3548 1546, 3549 /* LD_D */ 3550 1549, 3551 /* LD_H */ 3552 1552, 3553 /* LD_HU */ 3554 1555, 3555 /* LD_W */ 3556 1558, 3557 /* LD_WU */ 3558 1561, 3559 /* LL_D */ 3560 1564, 3561 /* LL_W */ 3562 1567, 3563 /* LU12I_W */ 3564 1570, 3565 /* LU32I_D */ 3566 1572, 3567 /* LU52I_D */ 3568 1575, 3569 /* MASKEQZ */ 3570 1578, 3571 /* MASKNEZ */ 3572 1581, 3573 /* MOD_D */ 3574 1584, 3575 /* MOD_DU */ 3576 1587, 3577 /* MOD_W */ 3578 1590, 3579 /* MOD_WU */ 3580 1593, 3581 /* MOVCF2FR_S */ 3582 1596, 3583 /* MOVCF2GR */ 3584 1598, 3585 /* MOVFCSR2GR */ 3586 1600, 3587 /* MOVFR2CF_S */ 3588 1602, 3589 /* MOVFR2GR_D */ 3590 1604, 3591 /* MOVFR2GR_S */ 3592 1606, 3593 /* MOVFR2GR_S_64 */ 3594 1608, 3595 /* MOVFRH2GR_S */ 3596 1610, 3597 /* MOVGR2CF */ 3598 1612, 3599 /* MOVGR2FCSR */ 3600 1614, 3601 /* MOVGR2FRH_W */ 3602 1616, 3603 /* MOVGR2FR_D */ 3604 1619, 3605 /* MOVGR2FR_W */ 3606 1621, 3607 /* MOVGR2FR_W_64 */ 3608 1623, 3609 /* MULH_D */ 3610 1625, 3611 /* MULH_DU */ 3612 1628, 3613 /* MULH_W */ 3614 1631, 3615 /* MULH_WU */ 3616 1634, 3617 /* MULW_D_W */ 3618 1637, 3619 /* MULW_D_WU */ 3620 1640, 3621 /* MUL_D */ 3622 1643, 3623 /* MUL_W */ 3624 1646, 3625 /* NOR */ 3626 1649, 3627 /* OR */ 3628 1652, 3629 /* ORI */ 3630 1655, 3631 /* ORN */ 3632 1658, 3633 /* PCADDI */ 3634 1661, 3635 /* PCADDU12I */ 3636 1663, 3637 /* PCADDU18I */ 3638 1665, 3639 /* PCALAU12I */ 3640 1667, 3641 /* PRELD */ 3642 1669, 3643 /* PRELDX */ 3644 1672, 3645 /* RDTIMEH_W */ 3646 1675, 3647 /* RDTIMEL_W */ 3648 1677, 3649 /* RDTIME_D */ 3650 1679, 3651 /* REVB_2H */ 3652 1681, 3653 /* REVB_2W */ 3654 1683, 3655 /* REVB_4H */ 3656 1685, 3657 /* REVB_D */ 3658 1687, 3659 /* REVH_2W */ 3660 1689, 3661 /* REVH_D */ 3662 1691, 3663 /* ROTRI_D */ 3664 1693, 3665 /* ROTRI_W */ 3666 1696, 3667 /* ROTR_D */ 3668 1699, 3669 /* ROTR_W */ 3670 1702, 3671 /* SC_D */ 3672 1705, 3673 /* SC_W */ 3674 1709, 3675 /* SLLI_D */ 3676 1713, 3677 /* SLLI_W */ 3678 1716, 3679 /* SLL_D */ 3680 1719, 3681 /* SLL_W */ 3682 1722, 3683 /* SLT */ 3684 1725, 3685 /* SLTI */ 3686 1728, 3687 /* SLTU */ 3688 1731, 3689 /* SLTUI */ 3690 1734, 3691 /* SRAI_D */ 3692 1737, 3693 /* SRAI_W */ 3694 1740, 3695 /* SRA_D */ 3696 1743, 3697 /* SRA_W */ 3698 1746, 3699 /* SRLI_D */ 3700 1749, 3701 /* SRLI_W */ 3702 1752, 3703 /* SRL_D */ 3704 1755, 3705 /* SRL_W */ 3706 1758, 3707 /* STGT_B */ 3708 1761, 3709 /* STGT_D */ 3710 1764, 3711 /* STGT_H */ 3712 1767, 3713 /* STGT_W */ 3714 1770, 3715 /* STLE_B */ 3716 1773, 3717 /* STLE_D */ 3718 1776, 3719 /* STLE_H */ 3720 1779, 3721 /* STLE_W */ 3722 1782, 3723 /* STPTR_D */ 3724 1785, 3725 /* STPTR_W */ 3726 1788, 3727 /* STX_B */ 3728 1791, 3729 /* STX_D */ 3730 1794, 3731 /* STX_H */ 3732 1797, 3733 /* STX_W */ 3734 1800, 3735 /* ST_B */ 3736 1803, 3737 /* ST_D */ 3738 1806, 3739 /* ST_H */ 3740 1809, 3741 /* ST_W */ 3742 1812, 3743 /* SUB_D */ 3744 1815, 3745 /* SUB_W */ 3746 1818, 3747 /* SYSCALL */ 3748 1821, 3749 /* TLBCLR */ 3750 1822, 3751 /* TLBFILL */ 3752 1822, 3753 /* TLBFLUSH */ 3754 1822, 3755 /* TLBRD */ 3756 1822, 3757 /* TLBSRCH */ 3758 1822, 3759 /* TLBWR */ 3760 1822, 3761 /* XOR */ 3762 1822, 3763 /* XORI */ 3764 1825, 3765 }; 3766 3767 using namespace OpTypes; 3768 const int8_t OpcodeOperandTypes[] = { 3769 3770 /* PHI */ 3771 -1, 3772 /* INLINEASM */ 3773 /* INLINEASM_BR */ 3774 /* CFI_INSTRUCTION */ 3775 i32imm, 3776 /* EH_LABEL */ 3777 i32imm, 3778 /* GC_LABEL */ 3779 i32imm, 3780 /* ANNOTATION_LABEL */ 3781 i32imm, 3782 /* KILL */ 3783 /* EXTRACT_SUBREG */ 3784 -1, -1, i32imm, 3785 /* INSERT_SUBREG */ 3786 -1, -1, -1, i32imm, 3787 /* IMPLICIT_DEF */ 3788 -1, 3789 /* SUBREG_TO_REG */ 3790 -1, -1, -1, i32imm, 3791 /* COPY_TO_REGCLASS */ 3792 -1, -1, i32imm, 3793 /* DBG_VALUE */ 3794 /* DBG_VALUE_LIST */ 3795 /* DBG_INSTR_REF */ 3796 /* DBG_PHI */ 3797 /* DBG_LABEL */ 3798 -1, 3799 /* REG_SEQUENCE */ 3800 -1, -1, 3801 /* COPY */ 3802 -1, -1, 3803 /* BUNDLE */ 3804 /* LIFETIME_START */ 3805 i32imm, 3806 /* LIFETIME_END */ 3807 i32imm, 3808 /* PSEUDO_PROBE */ 3809 i64imm, i64imm, i8imm, i32imm, 3810 /* ARITH_FENCE */ 3811 -1, -1, 3812 /* STACKMAP */ 3813 i64imm, i32imm, 3814 /* FENTRY_CALL */ 3815 /* PATCHPOINT */ 3816 -1, i64imm, i32imm, -1, i32imm, i32imm, 3817 /* LOAD_STACK_GUARD */ 3818 -1, 3819 /* PREALLOCATED_SETUP */ 3820 i32imm, 3821 /* PREALLOCATED_ARG */ 3822 -1, i32imm, i32imm, 3823 /* STATEPOINT */ 3824 /* LOCAL_ESCAPE */ 3825 -1, i32imm, 3826 /* FAULTING_OP */ 3827 -1, 3828 /* PATCHABLE_OP */ 3829 /* PATCHABLE_FUNCTION_ENTER */ 3830 /* PATCHABLE_RET */ 3831 /* PATCHABLE_FUNCTION_EXIT */ 3832 /* PATCHABLE_TAIL_CALL */ 3833 /* PATCHABLE_EVENT_CALL */ 3834 -1, -1, 3835 /* PATCHABLE_TYPED_EVENT_CALL */ 3836 -1, -1, -1, 3837 /* ICALL_BRANCH_FUNNEL */ 3838 /* MEMBARRIER */ 3839 /* G_ASSERT_SEXT */ 3840 type0, type0, untyped_imm_0, 3841 /* G_ASSERT_ZEXT */ 3842 type0, type0, untyped_imm_0, 3843 /* G_ASSERT_ALIGN */ 3844 type0, type0, untyped_imm_0, 3845 /* G_ADD */ 3846 type0, type0, type0, 3847 /* G_SUB */ 3848 type0, type0, type0, 3849 /* G_MUL */ 3850 type0, type0, type0, 3851 /* G_SDIV */ 3852 type0, type0, type0, 3853 /* G_UDIV */ 3854 type0, type0, type0, 3855 /* G_SREM */ 3856 type0, type0, type0, 3857 /* G_UREM */ 3858 type0, type0, type0, 3859 /* G_SDIVREM */ 3860 type0, type0, type0, type0, 3861 /* G_UDIVREM */ 3862 type0, type0, type0, type0, 3863 /* G_AND */ 3864 type0, type0, type0, 3865 /* G_OR */ 3866 type0, type0, type0, 3867 /* G_XOR */ 3868 type0, type0, type0, 3869 /* G_IMPLICIT_DEF */ 3870 type0, 3871 /* G_PHI */ 3872 type0, 3873 /* G_FRAME_INDEX */ 3874 type0, -1, 3875 /* G_GLOBAL_VALUE */ 3876 type0, -1, 3877 /* G_EXTRACT */ 3878 type0, type1, untyped_imm_0, 3879 /* G_UNMERGE_VALUES */ 3880 type0, type1, 3881 /* G_INSERT */ 3882 type0, type0, type1, untyped_imm_0, 3883 /* G_MERGE_VALUES */ 3884 type0, type1, 3885 /* G_BUILD_VECTOR */ 3886 type0, type1, 3887 /* G_BUILD_VECTOR_TRUNC */ 3888 type0, type1, 3889 /* G_CONCAT_VECTORS */ 3890 type0, type1, 3891 /* G_PTRTOINT */ 3892 type0, type1, 3893 /* G_INTTOPTR */ 3894 type0, type1, 3895 /* G_BITCAST */ 3896 type0, type1, 3897 /* G_FREEZE */ 3898 type0, type0, 3899 /* G_INTRINSIC_FPTRUNC_ROUND */ 3900 type0, type1, i32imm, 3901 /* G_INTRINSIC_TRUNC */ 3902 type0, type0, 3903 /* G_INTRINSIC_ROUND */ 3904 type0, type0, 3905 /* G_INTRINSIC_LRINT */ 3906 type0, type1, 3907 /* G_INTRINSIC_ROUNDEVEN */ 3908 type0, type0, 3909 /* G_READCYCLECOUNTER */ 3910 type0, 3911 /* G_LOAD */ 3912 type0, ptype1, 3913 /* G_SEXTLOAD */ 3914 type0, ptype1, 3915 /* G_ZEXTLOAD */ 3916 type0, ptype1, 3917 /* G_INDEXED_LOAD */ 3918 type0, ptype1, ptype1, type2, -1, 3919 /* G_INDEXED_SEXTLOAD */ 3920 type0, ptype1, ptype1, type2, -1, 3921 /* G_INDEXED_ZEXTLOAD */ 3922 type0, ptype1, ptype1, type2, -1, 3923 /* G_STORE */ 3924 type0, ptype1, 3925 /* G_INDEXED_STORE */ 3926 ptype0, type1, ptype0, ptype2, -1, 3927 /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */ 3928 type0, type1, type2, type0, type0, 3929 /* G_ATOMIC_CMPXCHG */ 3930 type0, ptype1, type0, type0, 3931 /* G_ATOMICRMW_XCHG */ 3932 type0, ptype1, type0, 3933 /* G_ATOMICRMW_ADD */ 3934 type0, ptype1, type0, 3935 /* G_ATOMICRMW_SUB */ 3936 type0, ptype1, type0, 3937 /* G_ATOMICRMW_AND */ 3938 type0, ptype1, type0, 3939 /* G_ATOMICRMW_NAND */ 3940 type0, ptype1, type0, 3941 /* G_ATOMICRMW_OR */ 3942 type0, ptype1, type0, 3943 /* G_ATOMICRMW_XOR */ 3944 type0, ptype1, type0, 3945 /* G_ATOMICRMW_MAX */ 3946 type0, ptype1, type0, 3947 /* G_ATOMICRMW_MIN */ 3948 type0, ptype1, type0, 3949 /* G_ATOMICRMW_UMAX */ 3950 type0, ptype1, type0, 3951 /* G_ATOMICRMW_UMIN */ 3952 type0, ptype1, type0, 3953 /* G_ATOMICRMW_FADD */ 3954 type0, ptype1, type0, 3955 /* G_ATOMICRMW_FSUB */ 3956 type0, ptype1, type0, 3957 /* G_ATOMICRMW_FMAX */ 3958 type0, ptype1, type0, 3959 /* G_ATOMICRMW_FMIN */ 3960 type0, ptype1, type0, 3961 /* G_ATOMICRMW_UINC_WRAP */ 3962 type0, ptype1, type0, 3963 /* G_ATOMICRMW_UDEC_WRAP */ 3964 type0, ptype1, type0, 3965 /* G_FENCE */ 3966 i32imm, i32imm, 3967 /* G_BRCOND */ 3968 type0, -1, 3969 /* G_BRINDIRECT */ 3970 type0, 3971 /* G_INVOKE_REGION_START */ 3972 /* G_INTRINSIC */ 3973 -1, 3974 /* G_INTRINSIC_W_SIDE_EFFECTS */ 3975 -1, 3976 /* G_ANYEXT */ 3977 type0, type1, 3978 /* G_TRUNC */ 3979 type0, type1, 3980 /* G_CONSTANT */ 3981 type0, -1, 3982 /* G_FCONSTANT */ 3983 type0, -1, 3984 /* G_VASTART */ 3985 type0, 3986 /* G_VAARG */ 3987 type0, type1, -1, 3988 /* G_SEXT */ 3989 type0, type1, 3990 /* G_SEXT_INREG */ 3991 type0, type0, untyped_imm_0, 3992 /* G_ZEXT */ 3993 type0, type1, 3994 /* G_SHL */ 3995 type0, type0, type1, 3996 /* G_LSHR */ 3997 type0, type0, type1, 3998 /* G_ASHR */ 3999 type0, type0, type1, 4000 /* G_FSHL */ 4001 type0, type0, type0, type1, 4002 /* G_FSHR */ 4003 type0, type0, type0, type1, 4004 /* G_ROTR */ 4005 type0, type0, type1, 4006 /* G_ROTL */ 4007 type0, type0, type1, 4008 /* G_ICMP */ 4009 type0, -1, type1, type1, 4010 /* G_FCMP */ 4011 type0, -1, type1, type1, 4012 /* G_SELECT */ 4013 type0, type1, type0, type0, 4014 /* G_UADDO */ 4015 type0, type1, type0, type0, 4016 /* G_UADDE */ 4017 type0, type1, type0, type0, type1, 4018 /* G_USUBO */ 4019 type0, type1, type0, type0, 4020 /* G_USUBE */ 4021 type0, type1, type0, type0, type1, 4022 /* G_SADDO */ 4023 type0, type1, type0, type0, 4024 /* G_SADDE */ 4025 type0, type1, type0, type0, type1, 4026 /* G_SSUBO */ 4027 type0, type1, type0, type0, 4028 /* G_SSUBE */ 4029 type0, type1, type0, type0, type1, 4030 /* G_UMULO */ 4031 type0, type1, type0, type0, 4032 /* G_SMULO */ 4033 type0, type1, type0, type0, 4034 /* G_UMULH */ 4035 type0, type0, type0, 4036 /* G_SMULH */ 4037 type0, type0, type0, 4038 /* G_UADDSAT */ 4039 type0, type0, type0, 4040 /* G_SADDSAT */ 4041 type0, type0, type0, 4042 /* G_USUBSAT */ 4043 type0, type0, type0, 4044 /* G_SSUBSAT */ 4045 type0, type0, type0, 4046 /* G_USHLSAT */ 4047 type0, type0, type1, 4048 /* G_SSHLSAT */ 4049 type0, type0, type1, 4050 /* G_SMULFIX */ 4051 type0, type0, type0, untyped_imm_0, 4052 /* G_UMULFIX */ 4053 type0, type0, type0, untyped_imm_0, 4054 /* G_SMULFIXSAT */ 4055 type0, type0, type0, untyped_imm_0, 4056 /* G_UMULFIXSAT */ 4057 type0, type0, type0, untyped_imm_0, 4058 /* G_SDIVFIX */ 4059 type0, type0, type0, untyped_imm_0, 4060 /* G_UDIVFIX */ 4061 type0, type0, type0, untyped_imm_0, 4062 /* G_SDIVFIXSAT */ 4063 type0, type0, type0, untyped_imm_0, 4064 /* G_UDIVFIXSAT */ 4065 type0, type0, type0, untyped_imm_0, 4066 /* G_FADD */ 4067 type0, type0, type0, 4068 /* G_FSUB */ 4069 type0, type0, type0, 4070 /* G_FMUL */ 4071 type0, type0, type0, 4072 /* G_FMA */ 4073 type0, type0, type0, type0, 4074 /* G_FMAD */ 4075 type0, type0, type0, type0, 4076 /* G_FDIV */ 4077 type0, type0, type0, 4078 /* G_FREM */ 4079 type0, type0, type0, 4080 /* G_FPOW */ 4081 type0, type0, type0, 4082 /* G_FPOWI */ 4083 type0, type0, type1, 4084 /* G_FEXP */ 4085 type0, type0, 4086 /* G_FEXP2 */ 4087 type0, type0, 4088 /* G_FLOG */ 4089 type0, type0, 4090 /* G_FLOG2 */ 4091 type0, type0, 4092 /* G_FLOG10 */ 4093 type0, type0, 4094 /* G_FNEG */ 4095 type0, type0, 4096 /* G_FPEXT */ 4097 type0, type1, 4098 /* G_FPTRUNC */ 4099 type0, type1, 4100 /* G_FPTOSI */ 4101 type0, type1, 4102 /* G_FPTOUI */ 4103 type0, type1, 4104 /* G_SITOFP */ 4105 type0, type1, 4106 /* G_UITOFP */ 4107 type0, type1, 4108 /* G_FABS */ 4109 type0, type0, 4110 /* G_FCOPYSIGN */ 4111 type0, type0, type1, 4112 /* G_IS_FPCLASS */ 4113 type0, type1, -1, 4114 /* G_FCANONICALIZE */ 4115 type0, type0, 4116 /* G_FMINNUM */ 4117 type0, type0, type0, 4118 /* G_FMAXNUM */ 4119 type0, type0, type0, 4120 /* G_FMINNUM_IEEE */ 4121 type0, type0, type0, 4122 /* G_FMAXNUM_IEEE */ 4123 type0, type0, type0, 4124 /* G_FMINIMUM */ 4125 type0, type0, type0, 4126 /* G_FMAXIMUM */ 4127 type0, type0, type0, 4128 /* G_PTR_ADD */ 4129 ptype0, ptype0, type1, 4130 /* G_PTRMASK */ 4131 ptype0, ptype0, type1, 4132 /* G_SMIN */ 4133 type0, type0, type0, 4134 /* G_SMAX */ 4135 type0, type0, type0, 4136 /* G_UMIN */ 4137 type0, type0, type0, 4138 /* G_UMAX */ 4139 type0, type0, type0, 4140 /* G_ABS */ 4141 type0, type0, 4142 /* G_LROUND */ 4143 type0, type1, 4144 /* G_LLROUND */ 4145 type0, type1, 4146 /* G_BR */ 4147 -1, 4148 /* G_BRJT */ 4149 ptype0, -1, type1, 4150 /* G_INSERT_VECTOR_ELT */ 4151 type0, type0, type1, type2, 4152 /* G_EXTRACT_VECTOR_ELT */ 4153 type0, type1, type2, 4154 /* G_SHUFFLE_VECTOR */ 4155 type0, type1, type1, -1, 4156 /* G_CTTZ */ 4157 type0, type1, 4158 /* G_CTTZ_ZERO_UNDEF */ 4159 type0, type1, 4160 /* G_CTLZ */ 4161 type0, type1, 4162 /* G_CTLZ_ZERO_UNDEF */ 4163 type0, type1, 4164 /* G_CTPOP */ 4165 type0, type1, 4166 /* G_BSWAP */ 4167 type0, type0, 4168 /* G_BITREVERSE */ 4169 type0, type0, 4170 /* G_FCEIL */ 4171 type0, type0, 4172 /* G_FCOS */ 4173 type0, type0, 4174 /* G_FSIN */ 4175 type0, type0, 4176 /* G_FSQRT */ 4177 type0, type0, 4178 /* G_FFLOOR */ 4179 type0, type0, 4180 /* G_FRINT */ 4181 type0, type0, 4182 /* G_FNEARBYINT */ 4183 type0, type0, 4184 /* G_ADDRSPACE_CAST */ 4185 type0, type1, 4186 /* G_BLOCK_ADDR */ 4187 type0, -1, 4188 /* G_JUMP_TABLE */ 4189 type0, -1, 4190 /* G_DYN_STACKALLOC */ 4191 ptype0, type1, i32imm, 4192 /* G_STRICT_FADD */ 4193 type0, type0, type0, 4194 /* G_STRICT_FSUB */ 4195 type0, type0, type0, 4196 /* G_STRICT_FMUL */ 4197 type0, type0, type0, 4198 /* G_STRICT_FDIV */ 4199 type0, type0, type0, 4200 /* G_STRICT_FREM */ 4201 type0, type0, type0, 4202 /* G_STRICT_FMA */ 4203 type0, type0, type0, type0, 4204 /* G_STRICT_FSQRT */ 4205 type0, type0, 4206 /* G_READ_REGISTER */ 4207 type0, -1, 4208 /* G_WRITE_REGISTER */ 4209 -1, type0, 4210 /* G_MEMCPY */ 4211 ptype0, ptype1, type2, untyped_imm_0, 4212 /* G_MEMCPY_INLINE */ 4213 ptype0, ptype1, type2, 4214 /* G_MEMMOVE */ 4215 ptype0, ptype1, type2, untyped_imm_0, 4216 /* G_MEMSET */ 4217 ptype0, type1, type2, untyped_imm_0, 4218 /* G_BZERO */ 4219 ptype0, type1, untyped_imm_0, 4220 /* G_VECREDUCE_SEQ_FADD */ 4221 type0, type1, type2, 4222 /* G_VECREDUCE_SEQ_FMUL */ 4223 type0, type1, type2, 4224 /* G_VECREDUCE_FADD */ 4225 type0, type1, 4226 /* G_VECREDUCE_FMUL */ 4227 type0, type1, 4228 /* G_VECREDUCE_FMAX */ 4229 type0, type1, 4230 /* G_VECREDUCE_FMIN */ 4231 type0, type1, 4232 /* G_VECREDUCE_ADD */ 4233 type0, type1, 4234 /* G_VECREDUCE_MUL */ 4235 type0, type1, 4236 /* G_VECREDUCE_AND */ 4237 type0, type1, 4238 /* G_VECREDUCE_OR */ 4239 type0, type1, 4240 /* G_VECREDUCE_XOR */ 4241 type0, type1, 4242 /* G_VECREDUCE_SMAX */ 4243 type0, type1, 4244 /* G_VECREDUCE_SMIN */ 4245 type0, type1, 4246 /* G_VECREDUCE_UMAX */ 4247 type0, type1, 4248 /* G_VECREDUCE_UMIN */ 4249 type0, type1, 4250 /* G_SBFX */ 4251 type0, type0, type1, type1, 4252 /* G_UBFX */ 4253 type0, type0, type1, type1, 4254 /* ADJCALLSTACKDOWN */ 4255 i32imm, i32imm, 4256 /* ADJCALLSTACKUP */ 4257 i32imm, i32imm, 4258 /* PseudoAtomicLoadAdd32 */ 4259 GPR, GPR, GPR, GPR, grlenimm, 4260 /* PseudoAtomicLoadAnd32 */ 4261 GPR, GPR, GPR, GPR, grlenimm, 4262 /* PseudoAtomicLoadNand32 */ 4263 GPR, GPR, GPR, GPR, grlenimm, 4264 /* PseudoAtomicLoadNand64 */ 4265 GPR, GPR, GPR, GPR, grlenimm, 4266 /* PseudoAtomicLoadOr32 */ 4267 GPR, GPR, GPR, GPR, grlenimm, 4268 /* PseudoAtomicLoadSub32 */ 4269 GPR, GPR, GPR, GPR, grlenimm, 4270 /* PseudoAtomicLoadXor32 */ 4271 GPR, GPR, GPR, GPR, grlenimm, 4272 /* PseudoAtomicStoreD */ 4273 GPR, GPR, GPR, 4274 /* PseudoAtomicStoreW */ 4275 GPR, GPR, GPR, 4276 /* PseudoAtomicSwap32 */ 4277 GPR, GPR, GPR, GPR, grlenimm, 4278 /* PseudoBR */ 4279 simm26_b, 4280 /* PseudoBRIND */ 4281 GPR, simm16_lsl2, 4282 /* PseudoB_TAIL */ 4283 simm26_b, 4284 /* PseudoCALL */ 4285 simm26_symbol, 4286 /* PseudoCALLIndirect */ 4287 GPR, 4288 /* PseudoCmpXchg32 */ 4289 GPR, GPR, GPR, GPR, GPR, 4290 /* PseudoCmpXchg64 */ 4291 GPR, GPR, GPR, GPR, GPR, 4292 /* PseudoJIRL_CALL */ 4293 GPR, simm16_lsl2, 4294 /* PseudoJIRL_TAIL */ 4295 GPR, simm16_lsl2, 4296 /* PseudoLA_ABS */ 4297 GPR, bare_symbol, 4298 /* PseudoLA_ABS_LARGE */ 4299 GPR, GPR, bare_symbol, 4300 /* PseudoLA_GOT */ 4301 GPR, bare_symbol, 4302 /* PseudoLA_GOT_LARGE */ 4303 GPR, GPR, bare_symbol, 4304 /* PseudoLA_PCREL */ 4305 GPR, bare_symbol, 4306 /* PseudoLA_PCREL_LARGE */ 4307 GPR, GPR, bare_symbol, 4308 /* PseudoLA_TLS_GD */ 4309 GPR, bare_symbol, 4310 /* PseudoLA_TLS_GD_LARGE */ 4311 GPR, GPR, bare_symbol, 4312 /* PseudoLA_TLS_IE */ 4313 GPR, bare_symbol, 4314 /* PseudoLA_TLS_IE_LARGE */ 4315 GPR, GPR, bare_symbol, 4316 /* PseudoLA_TLS_LD */ 4317 GPR, bare_symbol, 4318 /* PseudoLA_TLS_LD_LARGE */ 4319 GPR, GPR, bare_symbol, 4320 /* PseudoLA_TLS_LE */ 4321 GPR, bare_symbol, 4322 /* PseudoLD_CFR */ 4323 CFR, GPR, grlenimm, 4324 /* PseudoLI_D */ 4325 GPR, grlenimm, 4326 /* PseudoLI_W */ 4327 GPR, imm32, 4328 /* PseudoMaskedAtomicLoadAdd32 */ 4329 GPR, GPR, GPR, GPR, GPR, grlenimm, 4330 /* PseudoMaskedAtomicLoadMax32 */ 4331 GPR, GPR, GPR, GPR, GPR, GPR, grlenimm, grlenimm, 4332 /* PseudoMaskedAtomicLoadMin32 */ 4333 GPR, GPR, GPR, GPR, GPR, GPR, grlenimm, grlenimm, 4334 /* PseudoMaskedAtomicLoadNand32 */ 4335 GPR, GPR, GPR, GPR, GPR, grlenimm, 4336 /* PseudoMaskedAtomicLoadSub32 */ 4337 GPR, GPR, GPR, GPR, GPR, grlenimm, 4338 /* PseudoMaskedAtomicLoadUMax32 */ 4339 GPR, GPR, GPR, GPR, GPR, GPR, grlenimm, 4340 /* PseudoMaskedAtomicLoadUMin32 */ 4341 GPR, GPR, GPR, GPR, GPR, GPR, grlenimm, 4342 /* PseudoMaskedAtomicSwap32 */ 4343 GPR, GPR, GPR, GPR, GPR, grlenimm, 4344 /* PseudoMaskedCmpXchg32 */ 4345 GPR, GPR, GPR, GPR, GPR, GPR, grlenimm, 4346 /* PseudoRET */ 4347 /* PseudoST_CFR */ 4348 CFR, GPR, grlenimm, 4349 /* PseudoTAIL */ 4350 simm26_symbol, 4351 /* PseudoTAILIndirect */ 4352 GPRT, 4353 /* PseudoUNIMP */ 4354 /* RDFCSR */ 4355 GPR, uimm2, 4356 /* WRFCSR */ 4357 uimm2, GPR, 4358 /* ADDI_D */ 4359 GPR, GPR, simm12_addlike, 4360 /* ADDI_W */ 4361 GPR, GPR, simm12_addlike, 4362 /* ADDU16I_D */ 4363 GPR, GPR, simm16, 4364 /* ADD_D */ 4365 GPR, GPR, GPR, 4366 /* ADD_W */ 4367 GPR, GPR, GPR, 4368 /* ALSL_D */ 4369 GPR, GPR, GPR, uimm2_plus1, 4370 /* ALSL_W */ 4371 GPR, GPR, GPR, uimm2_plus1, 4372 /* ALSL_WU */ 4373 GPR, GPR, GPR, uimm2_plus1, 4374 /* AMADD_D */ 4375 GPR, GPR, GPRMemAtomic, 4376 /* AMADD_DB_D */ 4377 GPR, GPR, GPRMemAtomic, 4378 /* AMADD_DB_W */ 4379 GPR, GPR, GPRMemAtomic, 4380 /* AMADD_W */ 4381 GPR, GPR, GPRMemAtomic, 4382 /* AMAND_D */ 4383 GPR, GPR, GPRMemAtomic, 4384 /* AMAND_DB_D */ 4385 GPR, GPR, GPRMemAtomic, 4386 /* AMAND_DB_W */ 4387 GPR, GPR, GPRMemAtomic, 4388 /* AMAND_W */ 4389 GPR, GPR, GPRMemAtomic, 4390 /* AMMAX_D */ 4391 GPR, GPR, GPRMemAtomic, 4392 /* AMMAX_DB_D */ 4393 GPR, GPR, GPRMemAtomic, 4394 /* AMMAX_DB_DU */ 4395 GPR, GPR, GPRMemAtomic, 4396 /* AMMAX_DB_W */ 4397 GPR, GPR, GPRMemAtomic, 4398 /* AMMAX_DB_WU */ 4399 GPR, GPR, GPRMemAtomic, 4400 /* AMMAX_DU */ 4401 GPR, GPR, GPRMemAtomic, 4402 /* AMMAX_W */ 4403 GPR, GPR, GPRMemAtomic, 4404 /* AMMAX_WU */ 4405 GPR, GPR, GPRMemAtomic, 4406 /* AMMIN_D */ 4407 GPR, GPR, GPRMemAtomic, 4408 /* AMMIN_DB_D */ 4409 GPR, GPR, GPRMemAtomic, 4410 /* AMMIN_DB_DU */ 4411 GPR, GPR, GPRMemAtomic, 4412 /* AMMIN_DB_W */ 4413 GPR, GPR, GPRMemAtomic, 4414 /* AMMIN_DB_WU */ 4415 GPR, GPR, GPRMemAtomic, 4416 /* AMMIN_DU */ 4417 GPR, GPR, GPRMemAtomic, 4418 /* AMMIN_W */ 4419 GPR, GPR, GPRMemAtomic, 4420 /* AMMIN_WU */ 4421 GPR, GPR, GPRMemAtomic, 4422 /* AMOR_D */ 4423 GPR, GPR, GPRMemAtomic, 4424 /* AMOR_DB_D */ 4425 GPR, GPR, GPRMemAtomic, 4426 /* AMOR_DB_W */ 4427 GPR, GPR, GPRMemAtomic, 4428 /* AMOR_W */ 4429 GPR, GPR, GPRMemAtomic, 4430 /* AMSWAP_D */ 4431 GPR, GPR, GPRMemAtomic, 4432 /* AMSWAP_DB_D */ 4433 GPR, GPR, GPRMemAtomic, 4434 /* AMSWAP_DB_W */ 4435 GPR, GPR, GPRMemAtomic, 4436 /* AMSWAP_W */ 4437 GPR, GPR, GPRMemAtomic, 4438 /* AMXOR_D */ 4439 GPR, GPR, GPRMemAtomic, 4440 /* AMXOR_DB_D */ 4441 GPR, GPR, GPRMemAtomic, 4442 /* AMXOR_DB_W */ 4443 GPR, GPR, GPRMemAtomic, 4444 /* AMXOR_W */ 4445 GPR, GPR, GPRMemAtomic, 4446 /* AND */ 4447 GPR, GPR, GPR, 4448 /* ANDI */ 4449 GPR, GPR, uimm12, 4450 /* ANDN */ 4451 GPR, GPR, GPR, 4452 /* ASRTGT_D */ 4453 GPR, GPR, 4454 /* ASRTLE_D */ 4455 GPR, GPR, 4456 /* B */ 4457 simm26_b, 4458 /* BCEQZ */ 4459 CFR, simm21_lsl2, 4460 /* BCNEZ */ 4461 CFR, simm21_lsl2, 4462 /* BEQ */ 4463 GPR, GPR, simm16_lsl2_br, 4464 /* BEQZ */ 4465 GPR, simm21_lsl2, 4466 /* BGE */ 4467 GPR, GPR, simm16_lsl2_br, 4468 /* BGEU */ 4469 GPR, GPR, simm16_lsl2_br, 4470 /* BITREV_4B */ 4471 GPR, GPR, 4472 /* BITREV_8B */ 4473 GPR, GPR, 4474 /* BITREV_D */ 4475 GPR, GPR, 4476 /* BITREV_W */ 4477 GPR, GPR, 4478 /* BL */ 4479 simm26_symbol, 4480 /* BLT */ 4481 GPR, GPR, simm16_lsl2_br, 4482 /* BLTU */ 4483 GPR, GPR, simm16_lsl2_br, 4484 /* BNE */ 4485 GPR, GPR, simm16_lsl2_br, 4486 /* BNEZ */ 4487 GPR, simm21_lsl2, 4488 /* BREAK */ 4489 uimm15, 4490 /* BSTRINS_D */ 4491 GPR, GPR, GPR, uimm6, uimm6, 4492 /* BSTRINS_W */ 4493 GPR, GPR, GPR, uimm5, uimm5, 4494 /* BSTRPICK_D */ 4495 GPR, GPR, uimm6, uimm6, 4496 /* BSTRPICK_W */ 4497 GPR, GPR, uimm5, uimm5, 4498 /* BYTEPICK_D */ 4499 GPR, GPR, GPR, uimm3, 4500 /* BYTEPICK_W */ 4501 GPR, GPR, GPR, uimm2, 4502 /* CACOP */ 4503 uimm5, GPR, simm12, 4504 /* CLO_D */ 4505 GPR, GPR, 4506 /* CLO_W */ 4507 GPR, GPR, 4508 /* CLZ_D */ 4509 GPR, GPR, 4510 /* CLZ_W */ 4511 GPR, GPR, 4512 /* CPUCFG */ 4513 GPR, GPR, 4514 /* CRCC_W_B_W */ 4515 GPR, GPR, GPR, 4516 /* CRCC_W_D_W */ 4517 GPR, GPR, GPR, 4518 /* CRCC_W_H_W */ 4519 GPR, GPR, GPR, 4520 /* CRCC_W_W_W */ 4521 GPR, GPR, GPR, 4522 /* CRC_W_B_W */ 4523 GPR, GPR, GPR, 4524 /* CRC_W_D_W */ 4525 GPR, GPR, GPR, 4526 /* CRC_W_H_W */ 4527 GPR, GPR, GPR, 4528 /* CRC_W_W_W */ 4529 GPR, GPR, GPR, 4530 /* CSRRD */ 4531 GPR, uimm14, 4532 /* CSRWR */ 4533 GPR, GPR, uimm14, 4534 /* CSRXCHG */ 4535 GPR, GPR, GPR, uimm14, 4536 /* CTO_D */ 4537 GPR, GPR, 4538 /* CTO_W */ 4539 GPR, GPR, 4540 /* CTZ_D */ 4541 GPR, GPR, 4542 /* CTZ_W */ 4543 GPR, GPR, 4544 /* DBAR */ 4545 uimm15, 4546 /* DBCL */ 4547 uimm15, 4548 /* DIV_D */ 4549 GPR, GPR, GPR, 4550 /* DIV_DU */ 4551 GPR, GPR, GPR, 4552 /* DIV_W */ 4553 GPR, GPR, GPR, 4554 /* DIV_WU */ 4555 GPR, GPR, GPR, 4556 /* ERTN */ 4557 /* EXT_W_B */ 4558 GPR, GPR, 4559 /* EXT_W_H */ 4560 GPR, GPR, 4561 /* FABS_D */ 4562 FPR64, FPR64, 4563 /* FABS_S */ 4564 FPR32, FPR32, 4565 /* FADD_D */ 4566 FPR64, FPR64, FPR64, 4567 /* FADD_S */ 4568 FPR32, FPR32, FPR32, 4569 /* FCLASS_D */ 4570 FPR64, FPR64, 4571 /* FCLASS_S */ 4572 FPR32, FPR32, 4573 /* FCMP_CAF_D */ 4574 CFR, FPR64, FPR64, 4575 /* FCMP_CAF_S */ 4576 CFR, FPR32, FPR32, 4577 /* FCMP_CEQ_D */ 4578 CFR, FPR64, FPR64, 4579 /* FCMP_CEQ_S */ 4580 CFR, FPR32, FPR32, 4581 /* FCMP_CLE_D */ 4582 CFR, FPR64, FPR64, 4583 /* FCMP_CLE_S */ 4584 CFR, FPR32, FPR32, 4585 /* FCMP_CLT_D */ 4586 CFR, FPR64, FPR64, 4587 /* FCMP_CLT_S */ 4588 CFR, FPR32, FPR32, 4589 /* FCMP_CNE_D */ 4590 CFR, FPR64, FPR64, 4591 /* FCMP_CNE_S */ 4592 CFR, FPR32, FPR32, 4593 /* FCMP_COR_D */ 4594 CFR, FPR64, FPR64, 4595 /* FCMP_COR_S */ 4596 CFR, FPR32, FPR32, 4597 /* FCMP_CUEQ_D */ 4598 CFR, FPR64, FPR64, 4599 /* FCMP_CUEQ_S */ 4600 CFR, FPR32, FPR32, 4601 /* FCMP_CULE_D */ 4602 CFR, FPR64, FPR64, 4603 /* FCMP_CULE_S */ 4604 CFR, FPR32, FPR32, 4605 /* FCMP_CULT_D */ 4606 CFR, FPR64, FPR64, 4607 /* FCMP_CULT_S */ 4608 CFR, FPR32, FPR32, 4609 /* FCMP_CUNE_D */ 4610 CFR, FPR64, FPR64, 4611 /* FCMP_CUNE_S */ 4612 CFR, FPR32, FPR32, 4613 /* FCMP_CUN_D */ 4614 CFR, FPR64, FPR64, 4615 /* FCMP_CUN_S */ 4616 CFR, FPR32, FPR32, 4617 /* FCMP_SAF_D */ 4618 CFR, FPR64, FPR64, 4619 /* FCMP_SAF_S */ 4620 CFR, FPR32, FPR32, 4621 /* FCMP_SEQ_D */ 4622 CFR, FPR64, FPR64, 4623 /* FCMP_SEQ_S */ 4624 CFR, FPR32, FPR32, 4625 /* FCMP_SLE_D */ 4626 CFR, FPR64, FPR64, 4627 /* FCMP_SLE_S */ 4628 CFR, FPR32, FPR32, 4629 /* FCMP_SLT_D */ 4630 CFR, FPR64, FPR64, 4631 /* FCMP_SLT_S */ 4632 CFR, FPR32, FPR32, 4633 /* FCMP_SNE_D */ 4634 CFR, FPR64, FPR64, 4635 /* FCMP_SNE_S */ 4636 CFR, FPR32, FPR32, 4637 /* FCMP_SOR_D */ 4638 CFR, FPR64, FPR64, 4639 /* FCMP_SOR_S */ 4640 CFR, FPR32, FPR32, 4641 /* FCMP_SUEQ_D */ 4642 CFR, FPR64, FPR64, 4643 /* FCMP_SUEQ_S */ 4644 CFR, FPR32, FPR32, 4645 /* FCMP_SULE_D */ 4646 CFR, FPR64, FPR64, 4647 /* FCMP_SULE_S */ 4648 CFR, FPR32, FPR32, 4649 /* FCMP_SULT_D */ 4650 CFR, FPR64, FPR64, 4651 /* FCMP_SULT_S */ 4652 CFR, FPR32, FPR32, 4653 /* FCMP_SUNE_D */ 4654 CFR, FPR64, FPR64, 4655 /* FCMP_SUNE_S */ 4656 CFR, FPR32, FPR32, 4657 /* FCMP_SUN_D */ 4658 CFR, FPR64, FPR64, 4659 /* FCMP_SUN_S */ 4660 CFR, FPR32, FPR32, 4661 /* FCOPYSIGN_D */ 4662 FPR64, FPR64, FPR64, 4663 /* FCOPYSIGN_S */ 4664 FPR32, FPR32, FPR32, 4665 /* FCVT_D_S */ 4666 FPR64, FPR32, 4667 /* FCVT_S_D */ 4668 FPR32, FPR64, 4669 /* FDIV_D */ 4670 FPR64, FPR64, FPR64, 4671 /* FDIV_S */ 4672 FPR32, FPR32, FPR32, 4673 /* FFINT_D_L */ 4674 FPR64, FPR64, 4675 /* FFINT_D_W */ 4676 FPR64, FPR32, 4677 /* FFINT_S_L */ 4678 FPR32, FPR64, 4679 /* FFINT_S_W */ 4680 FPR32, FPR32, 4681 /* FLDGT_D */ 4682 FPR64, GPR, GPR, 4683 /* FLDGT_S */ 4684 FPR32, GPR, GPR, 4685 /* FLDLE_D */ 4686 FPR64, GPR, GPR, 4687 /* FLDLE_S */ 4688 FPR32, GPR, GPR, 4689 /* FLDX_D */ 4690 FPR64, GPR, GPR, 4691 /* FLDX_S */ 4692 FPR32, GPR, GPR, 4693 /* FLD_D */ 4694 FPR64, GPR, simm12, 4695 /* FLD_S */ 4696 FPR32, GPR, simm12, 4697 /* FLOGB_D */ 4698 FPR64, FPR64, 4699 /* FLOGB_S */ 4700 FPR32, FPR32, 4701 /* FMADD_D */ 4702 FPR64, FPR64, FPR64, FPR64, 4703 /* FMADD_S */ 4704 FPR32, FPR32, FPR32, FPR32, 4705 /* FMAXA_D */ 4706 FPR64, FPR64, FPR64, 4707 /* FMAXA_S */ 4708 FPR32, FPR32, FPR32, 4709 /* FMAX_D */ 4710 FPR64, FPR64, FPR64, 4711 /* FMAX_S */ 4712 FPR32, FPR32, FPR32, 4713 /* FMINA_D */ 4714 FPR64, FPR64, FPR64, 4715 /* FMINA_S */ 4716 FPR32, FPR32, FPR32, 4717 /* FMIN_D */ 4718 FPR64, FPR64, FPR64, 4719 /* FMIN_S */ 4720 FPR32, FPR32, FPR32, 4721 /* FMOV_D */ 4722 FPR64, FPR64, 4723 /* FMOV_S */ 4724 FPR32, FPR32, 4725 /* FMSUB_D */ 4726 FPR64, FPR64, FPR64, FPR64, 4727 /* FMSUB_S */ 4728 FPR32, FPR32, FPR32, FPR32, 4729 /* FMUL_D */ 4730 FPR64, FPR64, FPR64, 4731 /* FMUL_S */ 4732 FPR32, FPR32, FPR32, 4733 /* FNEG_D */ 4734 FPR64, FPR64, 4735 /* FNEG_S */ 4736 FPR32, FPR32, 4737 /* FNMADD_D */ 4738 FPR64, FPR64, FPR64, FPR64, 4739 /* FNMADD_S */ 4740 FPR32, FPR32, FPR32, FPR32, 4741 /* FNMSUB_D */ 4742 FPR64, FPR64, FPR64, FPR64, 4743 /* FNMSUB_S */ 4744 FPR32, FPR32, FPR32, FPR32, 4745 /* FRECIP_D */ 4746 FPR64, FPR64, 4747 /* FRECIP_S */ 4748 FPR32, FPR32, 4749 /* FRINT_D */ 4750 FPR64, FPR64, 4751 /* FRINT_S */ 4752 FPR32, FPR32, 4753 /* FRSQRT_D */ 4754 FPR64, FPR64, 4755 /* FRSQRT_S */ 4756 FPR32, FPR32, 4757 /* FSCALEB_D */ 4758 FPR64, FPR64, FPR64, 4759 /* FSCALEB_S */ 4760 FPR32, FPR32, FPR32, 4761 /* FSEL_D */ 4762 FPR64, FPR64, FPR64, CFR, 4763 /* FSEL_S */ 4764 FPR32, FPR32, FPR32, CFR, 4765 /* FSQRT_D */ 4766 FPR64, FPR64, 4767 /* FSQRT_S */ 4768 FPR32, FPR32, 4769 /* FSTGT_D */ 4770 FPR64, GPR, GPR, 4771 /* FSTGT_S */ 4772 FPR32, GPR, GPR, 4773 /* FSTLE_D */ 4774 FPR64, GPR, GPR, 4775 /* FSTLE_S */ 4776 FPR32, GPR, GPR, 4777 /* FSTX_D */ 4778 FPR64, GPR, GPR, 4779 /* FSTX_S */ 4780 FPR32, GPR, GPR, 4781 /* FST_D */ 4782 FPR64, GPR, simm12, 4783 /* FST_S */ 4784 FPR32, GPR, simm12, 4785 /* FSUB_D */ 4786 FPR64, FPR64, FPR64, 4787 /* FSUB_S */ 4788 FPR32, FPR32, FPR32, 4789 /* FTINTRM_L_D */ 4790 FPR64, FPR64, 4791 /* FTINTRM_L_S */ 4792 FPR64, FPR32, 4793 /* FTINTRM_W_D */ 4794 FPR32, FPR64, 4795 /* FTINTRM_W_S */ 4796 FPR32, FPR32, 4797 /* FTINTRNE_L_D */ 4798 FPR64, FPR64, 4799 /* FTINTRNE_L_S */ 4800 FPR64, FPR32, 4801 /* FTINTRNE_W_D */ 4802 FPR32, FPR64, 4803 /* FTINTRNE_W_S */ 4804 FPR32, FPR32, 4805 /* FTINTRP_L_D */ 4806 FPR64, FPR64, 4807 /* FTINTRP_L_S */ 4808 FPR64, FPR32, 4809 /* FTINTRP_W_D */ 4810 FPR32, FPR64, 4811 /* FTINTRP_W_S */ 4812 FPR32, FPR32, 4813 /* FTINTRZ_L_D */ 4814 FPR64, FPR64, 4815 /* FTINTRZ_L_S */ 4816 FPR64, FPR32, 4817 /* FTINTRZ_W_D */ 4818 FPR32, FPR64, 4819 /* FTINTRZ_W_S */ 4820 FPR32, FPR32, 4821 /* FTINT_L_D */ 4822 FPR64, FPR64, 4823 /* FTINT_L_S */ 4824 FPR64, FPR32, 4825 /* FTINT_W_D */ 4826 FPR32, FPR64, 4827 /* FTINT_W_S */ 4828 FPR32, FPR32, 4829 /* IBAR */ 4830 uimm15, 4831 /* IDLE */ 4832 uimm15, 4833 /* INVTLB */ 4834 GPR, GPR, uimm5, 4835 /* IOCSRRD_B */ 4836 GPR, GPR, 4837 /* IOCSRRD_D */ 4838 GPR, GPR, 4839 /* IOCSRRD_H */ 4840 GPR, GPR, 4841 /* IOCSRRD_W */ 4842 GPR, GPR, 4843 /* IOCSRWR_B */ 4844 GPR, GPR, 4845 /* IOCSRWR_D */ 4846 GPR, GPR, 4847 /* IOCSRWR_H */ 4848 GPR, GPR, 4849 /* IOCSRWR_W */ 4850 GPR, GPR, 4851 /* JIRL */ 4852 GPR, GPR, simm16_lsl2, 4853 /* LDDIR */ 4854 GPR, GPR, uimm8, 4855 /* LDGT_B */ 4856 GPR, GPR, GPR, 4857 /* LDGT_D */ 4858 GPR, GPR, GPR, 4859 /* LDGT_H */ 4860 GPR, GPR, GPR, 4861 /* LDGT_W */ 4862 GPR, GPR, GPR, 4863 /* LDLE_B */ 4864 GPR, GPR, GPR, 4865 /* LDLE_D */ 4866 GPR, GPR, GPR, 4867 /* LDLE_H */ 4868 GPR, GPR, GPR, 4869 /* LDLE_W */ 4870 GPR, GPR, GPR, 4871 /* LDPTE */ 4872 GPR, uimm8, 4873 /* LDPTR_D */ 4874 GPR, GPR, simm14_lsl2, 4875 /* LDPTR_W */ 4876 GPR, GPR, simm14_lsl2, 4877 /* LDX_B */ 4878 GPR, GPR, GPR, 4879 /* LDX_BU */ 4880 GPR, GPR, GPR, 4881 /* LDX_D */ 4882 GPR, GPR, GPR, 4883 /* LDX_H */ 4884 GPR, GPR, GPR, 4885 /* LDX_HU */ 4886 GPR, GPR, GPR, 4887 /* LDX_W */ 4888 GPR, GPR, GPR, 4889 /* LDX_WU */ 4890 GPR, GPR, GPR, 4891 /* LD_B */ 4892 GPR, GPR, simm12_addlike, 4893 /* LD_BU */ 4894 GPR, GPR, simm12_addlike, 4895 /* LD_D */ 4896 GPR, GPR, simm12_addlike, 4897 /* LD_H */ 4898 GPR, GPR, simm12_addlike, 4899 /* LD_HU */ 4900 GPR, GPR, simm12_addlike, 4901 /* LD_W */ 4902 GPR, GPR, simm12_addlike, 4903 /* LD_WU */ 4904 GPR, GPR, simm12_addlike, 4905 /* LL_D */ 4906 GPR, GPR, simm14_lsl2, 4907 /* LL_W */ 4908 GPR, GPR, simm14_lsl2, 4909 /* LU12I_W */ 4910 GPR, simm20_lu12iw, 4911 /* LU32I_D */ 4912 GPR, GPR, simm20_lu32id, 4913 /* LU52I_D */ 4914 GPR, GPR, simm12_lu52id, 4915 /* MASKEQZ */ 4916 GPR, GPR, GPR, 4917 /* MASKNEZ */ 4918 GPR, GPR, GPR, 4919 /* MOD_D */ 4920 GPR, GPR, GPR, 4921 /* MOD_DU */ 4922 GPR, GPR, GPR, 4923 /* MOD_W */ 4924 GPR, GPR, GPR, 4925 /* MOD_WU */ 4926 GPR, GPR, GPR, 4927 /* MOVCF2FR_S */ 4928 FPR32, CFR, 4929 /* MOVCF2GR */ 4930 GPR, CFR, 4931 /* MOVFCSR2GR */ 4932 GPR, FCSR, 4933 /* MOVFR2CF_S */ 4934 CFR, FPR32, 4935 /* MOVFR2GR_D */ 4936 GPR, FPR64, 4937 /* MOVFR2GR_S */ 4938 GPR, FPR32, 4939 /* MOVFR2GR_S_64 */ 4940 GPR, FPR64, 4941 /* MOVFRH2GR_S */ 4942 GPR, FPR64, 4943 /* MOVGR2CF */ 4944 CFR, GPR, 4945 /* MOVGR2FCSR */ 4946 FCSR, GPR, 4947 /* MOVGR2FRH_W */ 4948 FPR64, FPR64, GPR, 4949 /* MOVGR2FR_D */ 4950 FPR64, GPR, 4951 /* MOVGR2FR_W */ 4952 FPR32, GPR, 4953 /* MOVGR2FR_W_64 */ 4954 FPR64, GPR, 4955 /* MULH_D */ 4956 GPR, GPR, GPR, 4957 /* MULH_DU */ 4958 GPR, GPR, GPR, 4959 /* MULH_W */ 4960 GPR, GPR, GPR, 4961 /* MULH_WU */ 4962 GPR, GPR, GPR, 4963 /* MULW_D_W */ 4964 GPR, GPR, GPR, 4965 /* MULW_D_WU */ 4966 GPR, GPR, GPR, 4967 /* MUL_D */ 4968 GPR, GPR, GPR, 4969 /* MUL_W */ 4970 GPR, GPR, GPR, 4971 /* NOR */ 4972 GPR, GPR, GPR, 4973 /* OR */ 4974 GPR, GPR, GPR, 4975 /* ORI */ 4976 GPR, GPR, uimm12_ori, 4977 /* ORN */ 4978 GPR, GPR, GPR, 4979 /* PCADDI */ 4980 GPR, simm20, 4981 /* PCADDU12I */ 4982 GPR, simm20, 4983 /* PCADDU18I */ 4984 GPR, simm20, 4985 /* PCALAU12I */ 4986 GPR, simm20_pcalau12i, 4987 /* PRELD */ 4988 uimm5, GPR, simm12, 4989 /* PRELDX */ 4990 uimm5, GPR, GPR, 4991 /* RDTIMEH_W */ 4992 GPR, GPR, 4993 /* RDTIMEL_W */ 4994 GPR, GPR, 4995 /* RDTIME_D */ 4996 GPR, GPR, 4997 /* REVB_2H */ 4998 GPR, GPR, 4999 /* REVB_2W */ 5000 GPR, GPR, 5001 /* REVB_4H */ 5002 GPR, GPR, 5003 /* REVB_D */ 5004 GPR, GPR, 5005 /* REVH_2W */ 5006 GPR, GPR, 5007 /* REVH_D */ 5008 GPR, GPR, 5009 /* ROTRI_D */ 5010 GPR, GPR, uimm6, 5011 /* ROTRI_W */ 5012 GPR, GPR, uimm5, 5013 /* ROTR_D */ 5014 GPR, GPR, GPR, 5015 /* ROTR_W */ 5016 GPR, GPR, GPR, 5017 /* SC_D */ 5018 GPR, GPR, GPR, simm14_lsl2, 5019 /* SC_W */ 5020 GPR, GPR, GPR, simm14_lsl2, 5021 /* SLLI_D */ 5022 GPR, GPR, uimm6, 5023 /* SLLI_W */ 5024 GPR, GPR, uimm5, 5025 /* SLL_D */ 5026 GPR, GPR, GPR, 5027 /* SLL_W */ 5028 GPR, GPR, GPR, 5029 /* SLT */ 5030 GPR, GPR, GPR, 5031 /* SLTI */ 5032 GPR, GPR, simm12, 5033 /* SLTU */ 5034 GPR, GPR, GPR, 5035 /* SLTUI */ 5036 GPR, GPR, simm12, 5037 /* SRAI_D */ 5038 GPR, GPR, uimm6, 5039 /* SRAI_W */ 5040 GPR, GPR, uimm5, 5041 /* SRA_D */ 5042 GPR, GPR, GPR, 5043 /* SRA_W */ 5044 GPR, GPR, GPR, 5045 /* SRLI_D */ 5046 GPR, GPR, uimm6, 5047 /* SRLI_W */ 5048 GPR, GPR, uimm5, 5049 /* SRL_D */ 5050 GPR, GPR, GPR, 5051 /* SRL_W */ 5052 GPR, GPR, GPR, 5053 /* STGT_B */ 5054 GPR, GPR, GPR, 5055 /* STGT_D */ 5056 GPR, GPR, GPR, 5057 /* STGT_H */ 5058 GPR, GPR, GPR, 5059 /* STGT_W */ 5060 GPR, GPR, GPR, 5061 /* STLE_B */ 5062 GPR, GPR, GPR, 5063 /* STLE_D */ 5064 GPR, GPR, GPR, 5065 /* STLE_H */ 5066 GPR, GPR, GPR, 5067 /* STLE_W */ 5068 GPR, GPR, GPR, 5069 /* STPTR_D */ 5070 GPR, GPR, simm14_lsl2, 5071 /* STPTR_W */ 5072 GPR, GPR, simm14_lsl2, 5073 /* STX_B */ 5074 GPR, GPR, GPR, 5075 /* STX_D */ 5076 GPR, GPR, GPR, 5077 /* STX_H */ 5078 GPR, GPR, GPR, 5079 /* STX_W */ 5080 GPR, GPR, GPR, 5081 /* ST_B */ 5082 GPR, GPR, simm12_addlike, 5083 /* ST_D */ 5084 GPR, GPR, simm12_addlike, 5085 /* ST_H */ 5086 GPR, GPR, simm12_addlike, 5087 /* ST_W */ 5088 GPR, GPR, simm12_addlike, 5089 /* SUB_D */ 5090 GPR, GPR, GPR, 5091 /* SUB_W */ 5092 GPR, GPR, GPR, 5093 /* SYSCALL */ 5094 uimm15, 5095 /* TLBCLR */ 5096 /* TLBFILL */ 5097 /* TLBFLUSH */ 5098 /* TLBRD */ 5099 /* TLBSRCH */ 5100 /* TLBWR */ 5101 /* XOR */ 5102 GPR, GPR, GPR, 5103 /* XORI */ 5104 GPR, GPR, uimm12, 5105 }; 5106 return OpcodeOperandTypes[Offsets[Opcode] + OpIdx]; 5107} 5108} // end namespace LoongArch 5109} // end namespace llvm 5110#endif // GET_INSTRINFO_OPERAND_TYPE 5111 5112#ifdef GET_INSTRINFO_MEM_OPERAND_SIZE 5113#undef GET_INSTRINFO_MEM_OPERAND_SIZE 5114namespace llvm { 5115namespace LoongArch { 5116LLVM_READONLY 5117static int getMemOperandSize(int OpType) { 5118 switch (OpType) { 5119 default: return 0; 5120 } 5121} 5122} // end namespace LoongArch 5123} // end namespace llvm 5124#endif // GET_INSTRINFO_MEM_OPERAND_SIZE 5125 5126#ifdef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP 5127#undef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP 5128namespace llvm { 5129namespace LoongArch { 5130LLVM_READONLY static unsigned 5131getLogicalOperandSize(uint16_t Opcode, uint16_t LogicalOpIdx) { 5132 return LogicalOpIdx; 5133} 5134LLVM_READONLY static inline unsigned 5135getLogicalOperandIdx(uint16_t Opcode, uint16_t LogicalOpIdx) { 5136 auto S = 0U; 5137 for (auto i = 0U; i < LogicalOpIdx; ++i) 5138 S += getLogicalOperandSize(Opcode, i); 5139 return S; 5140} 5141} // end namespace LoongArch 5142} // end namespace llvm 5143#endif // GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP 5144 5145#ifdef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP 5146#undef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP 5147namespace llvm { 5148namespace LoongArch { 5149LLVM_READONLY static int 5150getLogicalOperandType(uint16_t Opcode, uint16_t LogicalOpIdx) { 5151 return -1; 5152} 5153} // end namespace LoongArch 5154} // end namespace llvm 5155#endif // GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP 5156 5157#ifdef GET_INSTRINFO_MC_HELPER_DECLS 5158#undef GET_INSTRINFO_MC_HELPER_DECLS 5159 5160namespace llvm { 5161class MCInst; 5162class FeatureBitset; 5163 5164namespace LoongArch_MC { 5165 5166void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features); 5167 5168} // end namespace LoongArch_MC 5169} // end namespace llvm 5170 5171#endif // GET_INSTRINFO_MC_HELPER_DECLS 5172 5173#ifdef GET_INSTRINFO_MC_HELPERS 5174#undef GET_INSTRINFO_MC_HELPERS 5175 5176namespace llvm { 5177namespace LoongArch_MC { 5178 5179} // end namespace LoongArch_MC 5180} // end namespace llvm 5181 5182#endif // GET_GENISTRINFO_MC_HELPERS 5183 5184#ifdef ENABLE_INSTR_PREDICATE_VERIFIER 5185#undef ENABLE_INSTR_PREDICATE_VERIFIER 5186#include <sstream> 5187 5188namespace llvm { 5189namespace LoongArch_MC { 5190 5191// Bits for subtarget features that participate in instruction matching. 5192enum SubtargetFeatureBits : uint8_t { 5193 Feature_IsLA64Bit = 10, 5194 Feature_IsLA32Bit = 9, 5195 Feature_HasBasicFBit = 1, 5196 Feature_HasBasicDBit = 0, 5197 Feature_HasExtLSXBit = 4, 5198 Feature_HasExtLASXBit = 2, 5199 Feature_HasExtLVZBit = 5, 5200 Feature_HasExtLBTBit = 3, 5201 Feature_HasLaGlobalWithPcrelBit = 7, 5202 Feature_HasLaGlobalWithAbsBit = 6, 5203 Feature_HasLaLocalWithAbsBit = 8, 5204}; 5205 5206#ifndef NDEBUG 5207static const char *SubtargetFeatureNames[] = { 5208 "Feature_HasBasicD", 5209 "Feature_HasBasicF", 5210 "Feature_HasExtLASX", 5211 "Feature_HasExtLBT", 5212 "Feature_HasExtLSX", 5213 "Feature_HasExtLVZ", 5214 "Feature_HasLaGlobalWithAbs", 5215 "Feature_HasLaGlobalWithPcrel", 5216 "Feature_HasLaLocalWithAbs", 5217 "Feature_IsLA32", 5218 "Feature_IsLA64", 5219 nullptr 5220}; 5221 5222#endif // NDEBUG 5223 5224FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) { 5225 FeatureBitset Features; 5226 if (FB[LoongArch::Feature64Bit]) 5227 Features.set(Feature_IsLA64Bit); 5228 if (!FB[LoongArch::Feature64Bit]) 5229 Features.set(Feature_IsLA32Bit); 5230 if (FB[LoongArch::FeatureBasicF]) 5231 Features.set(Feature_HasBasicFBit); 5232 if (FB[LoongArch::FeatureBasicD]) 5233 Features.set(Feature_HasBasicDBit); 5234 if (FB[LoongArch::FeatureExtLSX]) 5235 Features.set(Feature_HasExtLSXBit); 5236 if (FB[LoongArch::FeatureExtLASX]) 5237 Features.set(Feature_HasExtLASXBit); 5238 if (FB[LoongArch::FeatureExtLVZ]) 5239 Features.set(Feature_HasExtLVZBit); 5240 if (FB[LoongArch::FeatureExtLBT]) 5241 Features.set(Feature_HasExtLBTBit); 5242 if (FB[LoongArch::LaGlobalWithPcrel]) 5243 Features.set(Feature_HasLaGlobalWithPcrelBit); 5244 if (FB[LoongArch::LaGlobalWithAbs]) 5245 Features.set(Feature_HasLaGlobalWithAbsBit); 5246 if (FB[LoongArch::LaLocalWithAbs]) 5247 Features.set(Feature_HasLaLocalWithAbsBit); 5248 return Features; 5249} 5250 5251#ifndef NDEBUG 5252// Feature bitsets. 5253enum : uint8_t { 5254 CEFBS_None, 5255 CEFBS_HasBasicD, 5256 CEFBS_HasBasicF, 5257 CEFBS_IsLA64, 5258 CEFBS_HasBasicD_IsLA32, 5259 CEFBS_HasBasicD_IsLA64, 5260}; 5261 5262static constexpr FeatureBitset FeatureBitsets[] = { 5263 {}, // CEFBS_None 5264 {Feature_HasBasicDBit, }, 5265 {Feature_HasBasicFBit, }, 5266 {Feature_IsLA64Bit, }, 5267 {Feature_HasBasicDBit, Feature_IsLA32Bit, }, 5268 {Feature_HasBasicDBit, Feature_IsLA64Bit, }, 5269}; 5270#endif // NDEBUG 5271 5272void verifyInstructionPredicates( 5273 unsigned Opcode, const FeatureBitset &Features) { 5274#ifndef NDEBUG 5275 static uint8_t RequiredFeaturesRefs[] = { 5276 CEFBS_None, // PHI = 0 5277 CEFBS_None, // INLINEASM = 1 5278 CEFBS_None, // INLINEASM_BR = 2 5279 CEFBS_None, // CFI_INSTRUCTION = 3 5280 CEFBS_None, // EH_LABEL = 4 5281 CEFBS_None, // GC_LABEL = 5 5282 CEFBS_None, // ANNOTATION_LABEL = 6 5283 CEFBS_None, // KILL = 7 5284 CEFBS_None, // EXTRACT_SUBREG = 8 5285 CEFBS_None, // INSERT_SUBREG = 9 5286 CEFBS_None, // IMPLICIT_DEF = 10 5287 CEFBS_None, // SUBREG_TO_REG = 11 5288 CEFBS_None, // COPY_TO_REGCLASS = 12 5289 CEFBS_None, // DBG_VALUE = 13 5290 CEFBS_None, // DBG_VALUE_LIST = 14 5291 CEFBS_None, // DBG_INSTR_REF = 15 5292 CEFBS_None, // DBG_PHI = 16 5293 CEFBS_None, // DBG_LABEL = 17 5294 CEFBS_None, // REG_SEQUENCE = 18 5295 CEFBS_None, // COPY = 19 5296 CEFBS_None, // BUNDLE = 20 5297 CEFBS_None, // LIFETIME_START = 21 5298 CEFBS_None, // LIFETIME_END = 22 5299 CEFBS_None, // PSEUDO_PROBE = 23 5300 CEFBS_None, // ARITH_FENCE = 24 5301 CEFBS_None, // STACKMAP = 25 5302 CEFBS_None, // FENTRY_CALL = 26 5303 CEFBS_None, // PATCHPOINT = 27 5304 CEFBS_None, // LOAD_STACK_GUARD = 28 5305 CEFBS_None, // PREALLOCATED_SETUP = 29 5306 CEFBS_None, // PREALLOCATED_ARG = 30 5307 CEFBS_None, // STATEPOINT = 31 5308 CEFBS_None, // LOCAL_ESCAPE = 32 5309 CEFBS_None, // FAULTING_OP = 33 5310 CEFBS_None, // PATCHABLE_OP = 34 5311 CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 35 5312 CEFBS_None, // PATCHABLE_RET = 36 5313 CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 37 5314 CEFBS_None, // PATCHABLE_TAIL_CALL = 38 5315 CEFBS_None, // PATCHABLE_EVENT_CALL = 39 5316 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 40 5317 CEFBS_None, // ICALL_BRANCH_FUNNEL = 41 5318 CEFBS_None, // MEMBARRIER = 42 5319 CEFBS_None, // G_ASSERT_SEXT = 43 5320 CEFBS_None, // G_ASSERT_ZEXT = 44 5321 CEFBS_None, // G_ASSERT_ALIGN = 45 5322 CEFBS_None, // G_ADD = 46 5323 CEFBS_None, // G_SUB = 47 5324 CEFBS_None, // G_MUL = 48 5325 CEFBS_None, // G_SDIV = 49 5326 CEFBS_None, // G_UDIV = 50 5327 CEFBS_None, // G_SREM = 51 5328 CEFBS_None, // G_UREM = 52 5329 CEFBS_None, // G_SDIVREM = 53 5330 CEFBS_None, // G_UDIVREM = 54 5331 CEFBS_None, // G_AND = 55 5332 CEFBS_None, // G_OR = 56 5333 CEFBS_None, // G_XOR = 57 5334 CEFBS_None, // G_IMPLICIT_DEF = 58 5335 CEFBS_None, // G_PHI = 59 5336 CEFBS_None, // G_FRAME_INDEX = 60 5337 CEFBS_None, // G_GLOBAL_VALUE = 61 5338 CEFBS_None, // G_EXTRACT = 62 5339 CEFBS_None, // G_UNMERGE_VALUES = 63 5340 CEFBS_None, // G_INSERT = 64 5341 CEFBS_None, // G_MERGE_VALUES = 65 5342 CEFBS_None, // G_BUILD_VECTOR = 66 5343 CEFBS_None, // G_BUILD_VECTOR_TRUNC = 67 5344 CEFBS_None, // G_CONCAT_VECTORS = 68 5345 CEFBS_None, // G_PTRTOINT = 69 5346 CEFBS_None, // G_INTTOPTR = 70 5347 CEFBS_None, // G_BITCAST = 71 5348 CEFBS_None, // G_FREEZE = 72 5349 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND = 73 5350 CEFBS_None, // G_INTRINSIC_TRUNC = 74 5351 CEFBS_None, // G_INTRINSIC_ROUND = 75 5352 CEFBS_None, // G_INTRINSIC_LRINT = 76 5353 CEFBS_None, // G_INTRINSIC_ROUNDEVEN = 77 5354 CEFBS_None, // G_READCYCLECOUNTER = 78 5355 CEFBS_None, // G_LOAD = 79 5356 CEFBS_None, // G_SEXTLOAD = 80 5357 CEFBS_None, // G_ZEXTLOAD = 81 5358 CEFBS_None, // G_INDEXED_LOAD = 82 5359 CEFBS_None, // G_INDEXED_SEXTLOAD = 83 5360 CEFBS_None, // G_INDEXED_ZEXTLOAD = 84 5361 CEFBS_None, // G_STORE = 85 5362 CEFBS_None, // G_INDEXED_STORE = 86 5363 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 87 5364 CEFBS_None, // G_ATOMIC_CMPXCHG = 88 5365 CEFBS_None, // G_ATOMICRMW_XCHG = 89 5366 CEFBS_None, // G_ATOMICRMW_ADD = 90 5367 CEFBS_None, // G_ATOMICRMW_SUB = 91 5368 CEFBS_None, // G_ATOMICRMW_AND = 92 5369 CEFBS_None, // G_ATOMICRMW_NAND = 93 5370 CEFBS_None, // G_ATOMICRMW_OR = 94 5371 CEFBS_None, // G_ATOMICRMW_XOR = 95 5372 CEFBS_None, // G_ATOMICRMW_MAX = 96 5373 CEFBS_None, // G_ATOMICRMW_MIN = 97 5374 CEFBS_None, // G_ATOMICRMW_UMAX = 98 5375 CEFBS_None, // G_ATOMICRMW_UMIN = 99 5376 CEFBS_None, // G_ATOMICRMW_FADD = 100 5377 CEFBS_None, // G_ATOMICRMW_FSUB = 101 5378 CEFBS_None, // G_ATOMICRMW_FMAX = 102 5379 CEFBS_None, // G_ATOMICRMW_FMIN = 103 5380 CEFBS_None, // G_ATOMICRMW_UINC_WRAP = 104 5381 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP = 105 5382 CEFBS_None, // G_FENCE = 106 5383 CEFBS_None, // G_BRCOND = 107 5384 CEFBS_None, // G_BRINDIRECT = 108 5385 CEFBS_None, // G_INVOKE_REGION_START = 109 5386 CEFBS_None, // G_INTRINSIC = 110 5387 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 111 5388 CEFBS_None, // G_ANYEXT = 112 5389 CEFBS_None, // G_TRUNC = 113 5390 CEFBS_None, // G_CONSTANT = 114 5391 CEFBS_None, // G_FCONSTANT = 115 5392 CEFBS_None, // G_VASTART = 116 5393 CEFBS_None, // G_VAARG = 117 5394 CEFBS_None, // G_SEXT = 118 5395 CEFBS_None, // G_SEXT_INREG = 119 5396 CEFBS_None, // G_ZEXT = 120 5397 CEFBS_None, // G_SHL = 121 5398 CEFBS_None, // G_LSHR = 122 5399 CEFBS_None, // G_ASHR = 123 5400 CEFBS_None, // G_FSHL = 124 5401 CEFBS_None, // G_FSHR = 125 5402 CEFBS_None, // G_ROTR = 126 5403 CEFBS_None, // G_ROTL = 127 5404 CEFBS_None, // G_ICMP = 128 5405 CEFBS_None, // G_FCMP = 129 5406 CEFBS_None, // G_SELECT = 130 5407 CEFBS_None, // G_UADDO = 131 5408 CEFBS_None, // G_UADDE = 132 5409 CEFBS_None, // G_USUBO = 133 5410 CEFBS_None, // G_USUBE = 134 5411 CEFBS_None, // G_SADDO = 135 5412 CEFBS_None, // G_SADDE = 136 5413 CEFBS_None, // G_SSUBO = 137 5414 CEFBS_None, // G_SSUBE = 138 5415 CEFBS_None, // G_UMULO = 139 5416 CEFBS_None, // G_SMULO = 140 5417 CEFBS_None, // G_UMULH = 141 5418 CEFBS_None, // G_SMULH = 142 5419 CEFBS_None, // G_UADDSAT = 143 5420 CEFBS_None, // G_SADDSAT = 144 5421 CEFBS_None, // G_USUBSAT = 145 5422 CEFBS_None, // G_SSUBSAT = 146 5423 CEFBS_None, // G_USHLSAT = 147 5424 CEFBS_None, // G_SSHLSAT = 148 5425 CEFBS_None, // G_SMULFIX = 149 5426 CEFBS_None, // G_UMULFIX = 150 5427 CEFBS_None, // G_SMULFIXSAT = 151 5428 CEFBS_None, // G_UMULFIXSAT = 152 5429 CEFBS_None, // G_SDIVFIX = 153 5430 CEFBS_None, // G_UDIVFIX = 154 5431 CEFBS_None, // G_SDIVFIXSAT = 155 5432 CEFBS_None, // G_UDIVFIXSAT = 156 5433 CEFBS_None, // G_FADD = 157 5434 CEFBS_None, // G_FSUB = 158 5435 CEFBS_None, // G_FMUL = 159 5436 CEFBS_None, // G_FMA = 160 5437 CEFBS_None, // G_FMAD = 161 5438 CEFBS_None, // G_FDIV = 162 5439 CEFBS_None, // G_FREM = 163 5440 CEFBS_None, // G_FPOW = 164 5441 CEFBS_None, // G_FPOWI = 165 5442 CEFBS_None, // G_FEXP = 166 5443 CEFBS_None, // G_FEXP2 = 167 5444 CEFBS_None, // G_FLOG = 168 5445 CEFBS_None, // G_FLOG2 = 169 5446 CEFBS_None, // G_FLOG10 = 170 5447 CEFBS_None, // G_FNEG = 171 5448 CEFBS_None, // G_FPEXT = 172 5449 CEFBS_None, // G_FPTRUNC = 173 5450 CEFBS_None, // G_FPTOSI = 174 5451 CEFBS_None, // G_FPTOUI = 175 5452 CEFBS_None, // G_SITOFP = 176 5453 CEFBS_None, // G_UITOFP = 177 5454 CEFBS_None, // G_FABS = 178 5455 CEFBS_None, // G_FCOPYSIGN = 179 5456 CEFBS_None, // G_IS_FPCLASS = 180 5457 CEFBS_None, // G_FCANONICALIZE = 181 5458 CEFBS_None, // G_FMINNUM = 182 5459 CEFBS_None, // G_FMAXNUM = 183 5460 CEFBS_None, // G_FMINNUM_IEEE = 184 5461 CEFBS_None, // G_FMAXNUM_IEEE = 185 5462 CEFBS_None, // G_FMINIMUM = 186 5463 CEFBS_None, // G_FMAXIMUM = 187 5464 CEFBS_None, // G_PTR_ADD = 188 5465 CEFBS_None, // G_PTRMASK = 189 5466 CEFBS_None, // G_SMIN = 190 5467 CEFBS_None, // G_SMAX = 191 5468 CEFBS_None, // G_UMIN = 192 5469 CEFBS_None, // G_UMAX = 193 5470 CEFBS_None, // G_ABS = 194 5471 CEFBS_None, // G_LROUND = 195 5472 CEFBS_None, // G_LLROUND = 196 5473 CEFBS_None, // G_BR = 197 5474 CEFBS_None, // G_BRJT = 198 5475 CEFBS_None, // G_INSERT_VECTOR_ELT = 199 5476 CEFBS_None, // G_EXTRACT_VECTOR_ELT = 200 5477 CEFBS_None, // G_SHUFFLE_VECTOR = 201 5478 CEFBS_None, // G_CTTZ = 202 5479 CEFBS_None, // G_CTTZ_ZERO_UNDEF = 203 5480 CEFBS_None, // G_CTLZ = 204 5481 CEFBS_None, // G_CTLZ_ZERO_UNDEF = 205 5482 CEFBS_None, // G_CTPOP = 206 5483 CEFBS_None, // G_BSWAP = 207 5484 CEFBS_None, // G_BITREVERSE = 208 5485 CEFBS_None, // G_FCEIL = 209 5486 CEFBS_None, // G_FCOS = 210 5487 CEFBS_None, // G_FSIN = 211 5488 CEFBS_None, // G_FSQRT = 212 5489 CEFBS_None, // G_FFLOOR = 213 5490 CEFBS_None, // G_FRINT = 214 5491 CEFBS_None, // G_FNEARBYINT = 215 5492 CEFBS_None, // G_ADDRSPACE_CAST = 216 5493 CEFBS_None, // G_BLOCK_ADDR = 217 5494 CEFBS_None, // G_JUMP_TABLE = 218 5495 CEFBS_None, // G_DYN_STACKALLOC = 219 5496 CEFBS_None, // G_STRICT_FADD = 220 5497 CEFBS_None, // G_STRICT_FSUB = 221 5498 CEFBS_None, // G_STRICT_FMUL = 222 5499 CEFBS_None, // G_STRICT_FDIV = 223 5500 CEFBS_None, // G_STRICT_FREM = 224 5501 CEFBS_None, // G_STRICT_FMA = 225 5502 CEFBS_None, // G_STRICT_FSQRT = 226 5503 CEFBS_None, // G_READ_REGISTER = 227 5504 CEFBS_None, // G_WRITE_REGISTER = 228 5505 CEFBS_None, // G_MEMCPY = 229 5506 CEFBS_None, // G_MEMCPY_INLINE = 230 5507 CEFBS_None, // G_MEMMOVE = 231 5508 CEFBS_None, // G_MEMSET = 232 5509 CEFBS_None, // G_BZERO = 233 5510 CEFBS_None, // G_VECREDUCE_SEQ_FADD = 234 5511 CEFBS_None, // G_VECREDUCE_SEQ_FMUL = 235 5512 CEFBS_None, // G_VECREDUCE_FADD = 236 5513 CEFBS_None, // G_VECREDUCE_FMUL = 237 5514 CEFBS_None, // G_VECREDUCE_FMAX = 238 5515 CEFBS_None, // G_VECREDUCE_FMIN = 239 5516 CEFBS_None, // G_VECREDUCE_ADD = 240 5517 CEFBS_None, // G_VECREDUCE_MUL = 241 5518 CEFBS_None, // G_VECREDUCE_AND = 242 5519 CEFBS_None, // G_VECREDUCE_OR = 243 5520 CEFBS_None, // G_VECREDUCE_XOR = 244 5521 CEFBS_None, // G_VECREDUCE_SMAX = 245 5522 CEFBS_None, // G_VECREDUCE_SMIN = 246 5523 CEFBS_None, // G_VECREDUCE_UMAX = 247 5524 CEFBS_None, // G_VECREDUCE_UMIN = 248 5525 CEFBS_None, // G_SBFX = 249 5526 CEFBS_None, // G_UBFX = 250 5527 CEFBS_None, // ADJCALLSTACKDOWN = 251 5528 CEFBS_None, // ADJCALLSTACKUP = 252 5529 CEFBS_None, // PseudoAtomicLoadAdd32 = 253 5530 CEFBS_None, // PseudoAtomicLoadAnd32 = 254 5531 CEFBS_None, // PseudoAtomicLoadNand32 = 255 5532 CEFBS_None, // PseudoAtomicLoadNand64 = 256 5533 CEFBS_None, // PseudoAtomicLoadOr32 = 257 5534 CEFBS_None, // PseudoAtomicLoadSub32 = 258 5535 CEFBS_None, // PseudoAtomicLoadXor32 = 259 5536 CEFBS_IsLA64, // PseudoAtomicStoreD = 260 5537 CEFBS_None, // PseudoAtomicStoreW = 261 5538 CEFBS_None, // PseudoAtomicSwap32 = 262 5539 CEFBS_None, // PseudoBR = 263 5540 CEFBS_None, // PseudoBRIND = 264 5541 CEFBS_None, // PseudoB_TAIL = 265 5542 CEFBS_None, // PseudoCALL = 266 5543 CEFBS_None, // PseudoCALLIndirect = 267 5544 CEFBS_None, // PseudoCmpXchg32 = 268 5545 CEFBS_None, // PseudoCmpXchg64 = 269 5546 CEFBS_None, // PseudoJIRL_CALL = 270 5547 CEFBS_None, // PseudoJIRL_TAIL = 271 5548 CEFBS_None, // PseudoLA_ABS = 272 5549 CEFBS_None, // PseudoLA_ABS_LARGE = 273 5550 CEFBS_None, // PseudoLA_GOT = 274 5551 CEFBS_IsLA64, // PseudoLA_GOT_LARGE = 275 5552 CEFBS_None, // PseudoLA_PCREL = 276 5553 CEFBS_IsLA64, // PseudoLA_PCREL_LARGE = 277 5554 CEFBS_None, // PseudoLA_TLS_GD = 278 5555 CEFBS_IsLA64, // PseudoLA_TLS_GD_LARGE = 279 5556 CEFBS_None, // PseudoLA_TLS_IE = 280 5557 CEFBS_IsLA64, // PseudoLA_TLS_IE_LARGE = 281 5558 CEFBS_None, // PseudoLA_TLS_LD = 282 5559 CEFBS_IsLA64, // PseudoLA_TLS_LD_LARGE = 283 5560 CEFBS_None, // PseudoLA_TLS_LE = 284 5561 CEFBS_HasBasicF, // PseudoLD_CFR = 285 5562 CEFBS_IsLA64, // PseudoLI_D = 286 5563 CEFBS_None, // PseudoLI_W = 287 5564 CEFBS_None, // PseudoMaskedAtomicLoadAdd32 = 288 5565 CEFBS_None, // PseudoMaskedAtomicLoadMax32 = 289 5566 CEFBS_None, // PseudoMaskedAtomicLoadMin32 = 290 5567 CEFBS_None, // PseudoMaskedAtomicLoadNand32 = 291 5568 CEFBS_None, // PseudoMaskedAtomicLoadSub32 = 292 5569 CEFBS_None, // PseudoMaskedAtomicLoadUMax32 = 293 5570 CEFBS_None, // PseudoMaskedAtomicLoadUMin32 = 294 5571 CEFBS_None, // PseudoMaskedAtomicSwap32 = 295 5572 CEFBS_None, // PseudoMaskedCmpXchg32 = 296 5573 CEFBS_None, // PseudoRET = 297 5574 CEFBS_HasBasicF, // PseudoST_CFR = 298 5575 CEFBS_None, // PseudoTAIL = 299 5576 CEFBS_None, // PseudoTAILIndirect = 300 5577 CEFBS_None, // PseudoUNIMP = 301 5578 CEFBS_HasBasicF, // RDFCSR = 302 5579 CEFBS_HasBasicF, // WRFCSR = 303 5580 CEFBS_IsLA64, // ADDI_D = 304 5581 CEFBS_None, // ADDI_W = 305 5582 CEFBS_IsLA64, // ADDU16I_D = 306 5583 CEFBS_IsLA64, // ADD_D = 307 5584 CEFBS_None, // ADD_W = 308 5585 CEFBS_IsLA64, // ALSL_D = 309 5586 CEFBS_None, // ALSL_W = 310 5587 CEFBS_IsLA64, // ALSL_WU = 311 5588 CEFBS_IsLA64, // AMADD_D = 312 5589 CEFBS_IsLA64, // AMADD_DB_D = 313 5590 CEFBS_IsLA64, // AMADD_DB_W = 314 5591 CEFBS_IsLA64, // AMADD_W = 315 5592 CEFBS_IsLA64, // AMAND_D = 316 5593 CEFBS_IsLA64, // AMAND_DB_D = 317 5594 CEFBS_IsLA64, // AMAND_DB_W = 318 5595 CEFBS_IsLA64, // AMAND_W = 319 5596 CEFBS_IsLA64, // AMMAX_D = 320 5597 CEFBS_IsLA64, // AMMAX_DB_D = 321 5598 CEFBS_IsLA64, // AMMAX_DB_DU = 322 5599 CEFBS_IsLA64, // AMMAX_DB_W = 323 5600 CEFBS_IsLA64, // AMMAX_DB_WU = 324 5601 CEFBS_IsLA64, // AMMAX_DU = 325 5602 CEFBS_IsLA64, // AMMAX_W = 326 5603 CEFBS_IsLA64, // AMMAX_WU = 327 5604 CEFBS_IsLA64, // AMMIN_D = 328 5605 CEFBS_IsLA64, // AMMIN_DB_D = 329 5606 CEFBS_IsLA64, // AMMIN_DB_DU = 330 5607 CEFBS_IsLA64, // AMMIN_DB_W = 331 5608 CEFBS_IsLA64, // AMMIN_DB_WU = 332 5609 CEFBS_IsLA64, // AMMIN_DU = 333 5610 CEFBS_IsLA64, // AMMIN_W = 334 5611 CEFBS_IsLA64, // AMMIN_WU = 335 5612 CEFBS_IsLA64, // AMOR_D = 336 5613 CEFBS_IsLA64, // AMOR_DB_D = 337 5614 CEFBS_IsLA64, // AMOR_DB_W = 338 5615 CEFBS_IsLA64, // AMOR_W = 339 5616 CEFBS_IsLA64, // AMSWAP_D = 340 5617 CEFBS_IsLA64, // AMSWAP_DB_D = 341 5618 CEFBS_IsLA64, // AMSWAP_DB_W = 342 5619 CEFBS_IsLA64, // AMSWAP_W = 343 5620 CEFBS_IsLA64, // AMXOR_D = 344 5621 CEFBS_IsLA64, // AMXOR_DB_D = 345 5622 CEFBS_IsLA64, // AMXOR_DB_W = 346 5623 CEFBS_IsLA64, // AMXOR_W = 347 5624 CEFBS_None, // AND = 348 5625 CEFBS_None, // ANDI = 349 5626 CEFBS_None, // ANDN = 350 5627 CEFBS_IsLA64, // ASRTGT_D = 351 5628 CEFBS_IsLA64, // ASRTLE_D = 352 5629 CEFBS_None, // B = 353 5630 CEFBS_HasBasicF, // BCEQZ = 354 5631 CEFBS_HasBasicF, // BCNEZ = 355 5632 CEFBS_None, // BEQ = 356 5633 CEFBS_None, // BEQZ = 357 5634 CEFBS_None, // BGE = 358 5635 CEFBS_None, // BGEU = 359 5636 CEFBS_None, // BITREV_4B = 360 5637 CEFBS_IsLA64, // BITREV_8B = 361 5638 CEFBS_IsLA64, // BITREV_D = 362 5639 CEFBS_None, // BITREV_W = 363 5640 CEFBS_None, // BL = 364 5641 CEFBS_None, // BLT = 365 5642 CEFBS_None, // BLTU = 366 5643 CEFBS_None, // BNE = 367 5644 CEFBS_None, // BNEZ = 368 5645 CEFBS_None, // BREAK = 369 5646 CEFBS_IsLA64, // BSTRINS_D = 370 5647 CEFBS_None, // BSTRINS_W = 371 5648 CEFBS_IsLA64, // BSTRPICK_D = 372 5649 CEFBS_None, // BSTRPICK_W = 373 5650 CEFBS_IsLA64, // BYTEPICK_D = 374 5651 CEFBS_None, // BYTEPICK_W = 375 5652 CEFBS_None, // CACOP = 376 5653 CEFBS_IsLA64, // CLO_D = 377 5654 CEFBS_None, // CLO_W = 378 5655 CEFBS_IsLA64, // CLZ_D = 379 5656 CEFBS_None, // CLZ_W = 380 5657 CEFBS_None, // CPUCFG = 381 5658 CEFBS_IsLA64, // CRCC_W_B_W = 382 5659 CEFBS_IsLA64, // CRCC_W_D_W = 383 5660 CEFBS_IsLA64, // CRCC_W_H_W = 384 5661 CEFBS_IsLA64, // CRCC_W_W_W = 385 5662 CEFBS_IsLA64, // CRC_W_B_W = 386 5663 CEFBS_IsLA64, // CRC_W_D_W = 387 5664 CEFBS_IsLA64, // CRC_W_H_W = 388 5665 CEFBS_IsLA64, // CRC_W_W_W = 389 5666 CEFBS_None, // CSRRD = 390 5667 CEFBS_None, // CSRWR = 391 5668 CEFBS_None, // CSRXCHG = 392 5669 CEFBS_IsLA64, // CTO_D = 393 5670 CEFBS_None, // CTO_W = 394 5671 CEFBS_IsLA64, // CTZ_D = 395 5672 CEFBS_None, // CTZ_W = 396 5673 CEFBS_None, // DBAR = 397 5674 CEFBS_None, // DBCL = 398 5675 CEFBS_IsLA64, // DIV_D = 399 5676 CEFBS_IsLA64, // DIV_DU = 400 5677 CEFBS_None, // DIV_W = 401 5678 CEFBS_None, // DIV_WU = 402 5679 CEFBS_None, // ERTN = 403 5680 CEFBS_None, // EXT_W_B = 404 5681 CEFBS_None, // EXT_W_H = 405 5682 CEFBS_HasBasicD, // FABS_D = 406 5683 CEFBS_HasBasicF, // FABS_S = 407 5684 CEFBS_HasBasicD, // FADD_D = 408 5685 CEFBS_HasBasicF, // FADD_S = 409 5686 CEFBS_HasBasicD, // FCLASS_D = 410 5687 CEFBS_HasBasicF, // FCLASS_S = 411 5688 CEFBS_HasBasicD, // FCMP_CAF_D = 412 5689 CEFBS_HasBasicF, // FCMP_CAF_S = 413 5690 CEFBS_HasBasicD, // FCMP_CEQ_D = 414 5691 CEFBS_HasBasicF, // FCMP_CEQ_S = 415 5692 CEFBS_HasBasicD, // FCMP_CLE_D = 416 5693 CEFBS_HasBasicF, // FCMP_CLE_S = 417 5694 CEFBS_HasBasicD, // FCMP_CLT_D = 418 5695 CEFBS_HasBasicF, // FCMP_CLT_S = 419 5696 CEFBS_HasBasicD, // FCMP_CNE_D = 420 5697 CEFBS_HasBasicF, // FCMP_CNE_S = 421 5698 CEFBS_HasBasicD, // FCMP_COR_D = 422 5699 CEFBS_HasBasicF, // FCMP_COR_S = 423 5700 CEFBS_HasBasicD, // FCMP_CUEQ_D = 424 5701 CEFBS_HasBasicF, // FCMP_CUEQ_S = 425 5702 CEFBS_HasBasicD, // FCMP_CULE_D = 426 5703 CEFBS_HasBasicF, // FCMP_CULE_S = 427 5704 CEFBS_HasBasicD, // FCMP_CULT_D = 428 5705 CEFBS_HasBasicF, // FCMP_CULT_S = 429 5706 CEFBS_HasBasicD, // FCMP_CUNE_D = 430 5707 CEFBS_HasBasicF, // FCMP_CUNE_S = 431 5708 CEFBS_HasBasicD, // FCMP_CUN_D = 432 5709 CEFBS_HasBasicF, // FCMP_CUN_S = 433 5710 CEFBS_HasBasicD, // FCMP_SAF_D = 434 5711 CEFBS_HasBasicF, // FCMP_SAF_S = 435 5712 CEFBS_HasBasicD, // FCMP_SEQ_D = 436 5713 CEFBS_HasBasicF, // FCMP_SEQ_S = 437 5714 CEFBS_HasBasicD, // FCMP_SLE_D = 438 5715 CEFBS_HasBasicF, // FCMP_SLE_S = 439 5716 CEFBS_HasBasicD, // FCMP_SLT_D = 440 5717 CEFBS_HasBasicF, // FCMP_SLT_S = 441 5718 CEFBS_HasBasicD, // FCMP_SNE_D = 442 5719 CEFBS_HasBasicF, // FCMP_SNE_S = 443 5720 CEFBS_HasBasicD, // FCMP_SOR_D = 444 5721 CEFBS_HasBasicF, // FCMP_SOR_S = 445 5722 CEFBS_HasBasicD, // FCMP_SUEQ_D = 446 5723 CEFBS_HasBasicF, // FCMP_SUEQ_S = 447 5724 CEFBS_HasBasicD, // FCMP_SULE_D = 448 5725 CEFBS_HasBasicF, // FCMP_SULE_S = 449 5726 CEFBS_HasBasicD, // FCMP_SULT_D = 450 5727 CEFBS_HasBasicF, // FCMP_SULT_S = 451 5728 CEFBS_HasBasicD, // FCMP_SUNE_D = 452 5729 CEFBS_HasBasicF, // FCMP_SUNE_S = 453 5730 CEFBS_HasBasicD, // FCMP_SUN_D = 454 5731 CEFBS_HasBasicF, // FCMP_SUN_S = 455 5732 CEFBS_HasBasicD, // FCOPYSIGN_D = 456 5733 CEFBS_HasBasicF, // FCOPYSIGN_S = 457 5734 CEFBS_HasBasicD, // FCVT_D_S = 458 5735 CEFBS_HasBasicD, // FCVT_S_D = 459 5736 CEFBS_HasBasicD, // FDIV_D = 460 5737 CEFBS_HasBasicF, // FDIV_S = 461 5738 CEFBS_HasBasicD, // FFINT_D_L = 462 5739 CEFBS_HasBasicD, // FFINT_D_W = 463 5740 CEFBS_HasBasicD, // FFINT_S_L = 464 5741 CEFBS_HasBasicF, // FFINT_S_W = 465 5742 CEFBS_HasBasicD, // FLDGT_D = 466 5743 CEFBS_HasBasicF, // FLDGT_S = 467 5744 CEFBS_HasBasicD, // FLDLE_D = 468 5745 CEFBS_HasBasicF, // FLDLE_S = 469 5746 CEFBS_HasBasicD, // FLDX_D = 470 5747 CEFBS_HasBasicF, // FLDX_S = 471 5748 CEFBS_HasBasicD, // FLD_D = 472 5749 CEFBS_HasBasicF, // FLD_S = 473 5750 CEFBS_HasBasicD, // FLOGB_D = 474 5751 CEFBS_HasBasicF, // FLOGB_S = 475 5752 CEFBS_HasBasicD, // FMADD_D = 476 5753 CEFBS_HasBasicF, // FMADD_S = 477 5754 CEFBS_HasBasicD, // FMAXA_D = 478 5755 CEFBS_HasBasicF, // FMAXA_S = 479 5756 CEFBS_HasBasicD, // FMAX_D = 480 5757 CEFBS_HasBasicF, // FMAX_S = 481 5758 CEFBS_HasBasicD, // FMINA_D = 482 5759 CEFBS_HasBasicF, // FMINA_S = 483 5760 CEFBS_HasBasicD, // FMIN_D = 484 5761 CEFBS_HasBasicF, // FMIN_S = 485 5762 CEFBS_HasBasicD, // FMOV_D = 486 5763 CEFBS_HasBasicF, // FMOV_S = 487 5764 CEFBS_HasBasicD, // FMSUB_D = 488 5765 CEFBS_HasBasicF, // FMSUB_S = 489 5766 CEFBS_HasBasicD, // FMUL_D = 490 5767 CEFBS_HasBasicF, // FMUL_S = 491 5768 CEFBS_HasBasicD, // FNEG_D = 492 5769 CEFBS_HasBasicF, // FNEG_S = 493 5770 CEFBS_HasBasicD, // FNMADD_D = 494 5771 CEFBS_HasBasicF, // FNMADD_S = 495 5772 CEFBS_HasBasicD, // FNMSUB_D = 496 5773 CEFBS_HasBasicF, // FNMSUB_S = 497 5774 CEFBS_HasBasicD, // FRECIP_D = 498 5775 CEFBS_HasBasicF, // FRECIP_S = 499 5776 CEFBS_HasBasicD, // FRINT_D = 500 5777 CEFBS_HasBasicF, // FRINT_S = 501 5778 CEFBS_HasBasicD, // FRSQRT_D = 502 5779 CEFBS_HasBasicF, // FRSQRT_S = 503 5780 CEFBS_HasBasicD, // FSCALEB_D = 504 5781 CEFBS_HasBasicF, // FSCALEB_S = 505 5782 CEFBS_HasBasicD, // FSEL_D = 506 5783 CEFBS_HasBasicF, // FSEL_S = 507 5784 CEFBS_HasBasicD, // FSQRT_D = 508 5785 CEFBS_HasBasicF, // FSQRT_S = 509 5786 CEFBS_HasBasicD, // FSTGT_D = 510 5787 CEFBS_HasBasicF, // FSTGT_S = 511 5788 CEFBS_HasBasicD, // FSTLE_D = 512 5789 CEFBS_HasBasicF, // FSTLE_S = 513 5790 CEFBS_HasBasicD, // FSTX_D = 514 5791 CEFBS_HasBasicF, // FSTX_S = 515 5792 CEFBS_HasBasicD, // FST_D = 516 5793 CEFBS_HasBasicF, // FST_S = 517 5794 CEFBS_HasBasicD, // FSUB_D = 518 5795 CEFBS_HasBasicF, // FSUB_S = 519 5796 CEFBS_HasBasicD, // FTINTRM_L_D = 520 5797 CEFBS_HasBasicD, // FTINTRM_L_S = 521 5798 CEFBS_HasBasicD, // FTINTRM_W_D = 522 5799 CEFBS_HasBasicF, // FTINTRM_W_S = 523 5800 CEFBS_HasBasicD, // FTINTRNE_L_D = 524 5801 CEFBS_HasBasicD, // FTINTRNE_L_S = 525 5802 CEFBS_HasBasicD, // FTINTRNE_W_D = 526 5803 CEFBS_HasBasicF, // FTINTRNE_W_S = 527 5804 CEFBS_HasBasicD, // FTINTRP_L_D = 528 5805 CEFBS_HasBasicD, // FTINTRP_L_S = 529 5806 CEFBS_HasBasicD, // FTINTRP_W_D = 530 5807 CEFBS_HasBasicF, // FTINTRP_W_S = 531 5808 CEFBS_HasBasicD, // FTINTRZ_L_D = 532 5809 CEFBS_HasBasicD, // FTINTRZ_L_S = 533 5810 CEFBS_HasBasicD, // FTINTRZ_W_D = 534 5811 CEFBS_HasBasicF, // FTINTRZ_W_S = 535 5812 CEFBS_HasBasicD, // FTINT_L_D = 536 5813 CEFBS_HasBasicD, // FTINT_L_S = 537 5814 CEFBS_HasBasicD, // FTINT_W_D = 538 5815 CEFBS_HasBasicF, // FTINT_W_S = 539 5816 CEFBS_None, // IBAR = 540 5817 CEFBS_None, // IDLE = 541 5818 CEFBS_None, // INVTLB = 542 5819 CEFBS_None, // IOCSRRD_B = 543 5820 CEFBS_IsLA64, // IOCSRRD_D = 544 5821 CEFBS_None, // IOCSRRD_H = 545 5822 CEFBS_None, // IOCSRRD_W = 546 5823 CEFBS_None, // IOCSRWR_B = 547 5824 CEFBS_IsLA64, // IOCSRWR_D = 548 5825 CEFBS_None, // IOCSRWR_H = 549 5826 CEFBS_None, // IOCSRWR_W = 550 5827 CEFBS_None, // JIRL = 551 5828 CEFBS_None, // LDDIR = 552 5829 CEFBS_IsLA64, // LDGT_B = 553 5830 CEFBS_IsLA64, // LDGT_D = 554 5831 CEFBS_IsLA64, // LDGT_H = 555 5832 CEFBS_IsLA64, // LDGT_W = 556 5833 CEFBS_IsLA64, // LDLE_B = 557 5834 CEFBS_IsLA64, // LDLE_D = 558 5835 CEFBS_IsLA64, // LDLE_H = 559 5836 CEFBS_IsLA64, // LDLE_W = 560 5837 CEFBS_None, // LDPTE = 561 5838 CEFBS_IsLA64, // LDPTR_D = 562 5839 CEFBS_IsLA64, // LDPTR_W = 563 5840 CEFBS_IsLA64, // LDX_B = 564 5841 CEFBS_IsLA64, // LDX_BU = 565 5842 CEFBS_IsLA64, // LDX_D = 566 5843 CEFBS_IsLA64, // LDX_H = 567 5844 CEFBS_IsLA64, // LDX_HU = 568 5845 CEFBS_IsLA64, // LDX_W = 569 5846 CEFBS_IsLA64, // LDX_WU = 570 5847 CEFBS_None, // LD_B = 571 5848 CEFBS_None, // LD_BU = 572 5849 CEFBS_IsLA64, // LD_D = 573 5850 CEFBS_None, // LD_H = 574 5851 CEFBS_None, // LD_HU = 575 5852 CEFBS_None, // LD_W = 576 5853 CEFBS_IsLA64, // LD_WU = 577 5854 CEFBS_IsLA64, // LL_D = 578 5855 CEFBS_None, // LL_W = 579 5856 CEFBS_None, // LU12I_W = 580 5857 CEFBS_IsLA64, // LU32I_D = 581 5858 CEFBS_IsLA64, // LU52I_D = 582 5859 CEFBS_None, // MASKEQZ = 583 5860 CEFBS_None, // MASKNEZ = 584 5861 CEFBS_IsLA64, // MOD_D = 585 5862 CEFBS_IsLA64, // MOD_DU = 586 5863 CEFBS_None, // MOD_W = 587 5864 CEFBS_None, // MOD_WU = 588 5865 CEFBS_HasBasicF, // MOVCF2FR_S = 589 5866 CEFBS_HasBasicF, // MOVCF2GR = 590 5867 CEFBS_HasBasicF, // MOVFCSR2GR = 591 5868 CEFBS_HasBasicF, // MOVFR2CF_S = 592 5869 CEFBS_HasBasicD_IsLA64, // MOVFR2GR_D = 593 5870 CEFBS_HasBasicF, // MOVFR2GR_S = 594 5871 CEFBS_HasBasicD, // MOVFR2GR_S_64 = 595 5872 CEFBS_HasBasicD, // MOVFRH2GR_S = 596 5873 CEFBS_HasBasicF, // MOVGR2CF = 597 5874 CEFBS_HasBasicF, // MOVGR2FCSR = 598 5875 CEFBS_HasBasicD, // MOVGR2FRH_W = 599 5876 CEFBS_HasBasicD_IsLA64, // MOVGR2FR_D = 600 5877 CEFBS_HasBasicF, // MOVGR2FR_W = 601 5878 CEFBS_HasBasicD_IsLA32, // MOVGR2FR_W_64 = 602 5879 CEFBS_IsLA64, // MULH_D = 603 5880 CEFBS_IsLA64, // MULH_DU = 604 5881 CEFBS_None, // MULH_W = 605 5882 CEFBS_None, // MULH_WU = 606 5883 CEFBS_IsLA64, // MULW_D_W = 607 5884 CEFBS_IsLA64, // MULW_D_WU = 608 5885 CEFBS_IsLA64, // MUL_D = 609 5886 CEFBS_None, // MUL_W = 610 5887 CEFBS_None, // NOR = 611 5888 CEFBS_None, // OR = 612 5889 CEFBS_None, // ORI = 613 5890 CEFBS_None, // ORN = 614 5891 CEFBS_None, // PCADDI = 615 5892 CEFBS_None, // PCADDU12I = 616 5893 CEFBS_IsLA64, // PCADDU18I = 617 5894 CEFBS_None, // PCALAU12I = 618 5895 CEFBS_None, // PRELD = 619 5896 CEFBS_IsLA64, // PRELDX = 620 5897 CEFBS_None, // RDTIMEH_W = 621 5898 CEFBS_None, // RDTIMEL_W = 622 5899 CEFBS_IsLA64, // RDTIME_D = 623 5900 CEFBS_None, // REVB_2H = 624 5901 CEFBS_IsLA64, // REVB_2W = 625 5902 CEFBS_IsLA64, // REVB_4H = 626 5903 CEFBS_IsLA64, // REVB_D = 627 5904 CEFBS_IsLA64, // REVH_2W = 628 5905 CEFBS_IsLA64, // REVH_D = 629 5906 CEFBS_IsLA64, // ROTRI_D = 630 5907 CEFBS_None, // ROTRI_W = 631 5908 CEFBS_IsLA64, // ROTR_D = 632 5909 CEFBS_None, // ROTR_W = 633 5910 CEFBS_IsLA64, // SC_D = 634 5911 CEFBS_None, // SC_W = 635 5912 CEFBS_IsLA64, // SLLI_D = 636 5913 CEFBS_None, // SLLI_W = 637 5914 CEFBS_IsLA64, // SLL_D = 638 5915 CEFBS_None, // SLL_W = 639 5916 CEFBS_None, // SLT = 640 5917 CEFBS_None, // SLTI = 641 5918 CEFBS_None, // SLTU = 642 5919 CEFBS_None, // SLTUI = 643 5920 CEFBS_IsLA64, // SRAI_D = 644 5921 CEFBS_None, // SRAI_W = 645 5922 CEFBS_IsLA64, // SRA_D = 646 5923 CEFBS_None, // SRA_W = 647 5924 CEFBS_IsLA64, // SRLI_D = 648 5925 CEFBS_None, // SRLI_W = 649 5926 CEFBS_IsLA64, // SRL_D = 650 5927 CEFBS_None, // SRL_W = 651 5928 CEFBS_IsLA64, // STGT_B = 652 5929 CEFBS_IsLA64, // STGT_D = 653 5930 CEFBS_IsLA64, // STGT_H = 654 5931 CEFBS_IsLA64, // STGT_W = 655 5932 CEFBS_IsLA64, // STLE_B = 656 5933 CEFBS_IsLA64, // STLE_D = 657 5934 CEFBS_IsLA64, // STLE_H = 658 5935 CEFBS_IsLA64, // STLE_W = 659 5936 CEFBS_IsLA64, // STPTR_D = 660 5937 CEFBS_IsLA64, // STPTR_W = 661 5938 CEFBS_IsLA64, // STX_B = 662 5939 CEFBS_IsLA64, // STX_D = 663 5940 CEFBS_IsLA64, // STX_H = 664 5941 CEFBS_IsLA64, // STX_W = 665 5942 CEFBS_None, // ST_B = 666 5943 CEFBS_IsLA64, // ST_D = 667 5944 CEFBS_None, // ST_H = 668 5945 CEFBS_None, // ST_W = 669 5946 CEFBS_IsLA64, // SUB_D = 670 5947 CEFBS_None, // SUB_W = 671 5948 CEFBS_None, // SYSCALL = 672 5949 CEFBS_None, // TLBCLR = 673 5950 CEFBS_None, // TLBFILL = 674 5951 CEFBS_None, // TLBFLUSH = 675 5952 CEFBS_None, // TLBRD = 676 5953 CEFBS_None, // TLBSRCH = 677 5954 CEFBS_None, // TLBWR = 678 5955 CEFBS_None, // XOR = 679 5956 CEFBS_None, // XORI = 680 5957 }; 5958 5959 assert(Opcode < 681); 5960 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features); 5961 const FeatureBitset &RequiredFeatures = FeatureBitsets[RequiredFeaturesRefs[Opcode]]; 5962 FeatureBitset MissingFeatures = 5963 (AvailableFeatures & RequiredFeatures) ^ 5964 RequiredFeatures; 5965 if (MissingFeatures.any()) { 5966 std::ostringstream Msg; 5967 Msg << "Attempting to emit " << &LoongArchInstrNameData[LoongArchInstrNameIndices[Opcode]] 5968 << " instruction but the "; 5969 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i) 5970 if (MissingFeatures.test(i)) 5971 Msg << SubtargetFeatureNames[i] << " "; 5972 Msg << "predicate(s) are not met"; 5973 report_fatal_error(Msg.str().c_str()); 5974 } 5975#endif // NDEBUG 5976} 5977} // end namespace LoongArch_MC 5978} // end namespace llvm 5979#endif // ENABLE_INSTR_PREDICATE_VERIFIER 5980 5981