1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2|* *| 3|* Target Register Enum Values *| 4|* *| 5|* Automatically generated file, do not edit! *| 6|* *| 7\*===----------------------------------------------------------------------===*/ 8 9 10#ifdef GET_REGINFO_ENUM 11#undef GET_REGINFO_ENUM 12 13namespace llvm { 14 15class MCRegisterClass; 16extern const MCRegisterClass LoongArchMCRegisterClasses[]; 17 18namespace LoongArch { 19enum { 20 NoRegister, 21 F0 = 1, 22 F1 = 2, 23 F2 = 3, 24 F3 = 4, 25 F4 = 5, 26 F5 = 6, 27 F6 = 7, 28 F7 = 8, 29 F8 = 9, 30 F9 = 10, 31 F10 = 11, 32 F11 = 12, 33 F12 = 13, 34 F13 = 14, 35 F14 = 15, 36 F15 = 16, 37 F16 = 17, 38 F17 = 18, 39 F18 = 19, 40 F19 = 20, 41 F20 = 21, 42 F21 = 22, 43 F22 = 23, 44 F23 = 24, 45 F24 = 25, 46 F25 = 26, 47 F26 = 27, 48 F27 = 28, 49 F28 = 29, 50 F29 = 30, 51 F30 = 31, 52 F31 = 32, 53 FCC0 = 33, 54 FCC1 = 34, 55 FCC2 = 35, 56 FCC3 = 36, 57 FCC4 = 37, 58 FCC5 = 38, 59 FCC6 = 39, 60 FCC7 = 40, 61 FCSR0 = 41, 62 FCSR1 = 42, 63 FCSR2 = 43, 64 FCSR3 = 44, 65 R0 = 45, 66 R1 = 46, 67 R2 = 47, 68 R3 = 48, 69 R4 = 49, 70 R5 = 50, 71 R6 = 51, 72 R7 = 52, 73 R8 = 53, 74 R9 = 54, 75 R10 = 55, 76 R11 = 56, 77 R12 = 57, 78 R13 = 58, 79 R14 = 59, 80 R15 = 60, 81 R16 = 61, 82 R17 = 62, 83 R18 = 63, 84 R19 = 64, 85 R20 = 65, 86 R21 = 66, 87 R22 = 67, 88 R23 = 68, 89 R24 = 69, 90 R25 = 70, 91 R26 = 71, 92 R27 = 72, 93 R28 = 73, 94 R29 = 74, 95 R30 = 75, 96 R31 = 76, 97 F0_64 = 77, 98 F1_64 = 78, 99 F2_64 = 79, 100 F3_64 = 80, 101 F4_64 = 81, 102 F5_64 = 82, 103 F6_64 = 83, 104 F7_64 = 84, 105 F8_64 = 85, 106 F9_64 = 86, 107 F10_64 = 87, 108 F11_64 = 88, 109 F12_64 = 89, 110 F13_64 = 90, 111 F14_64 = 91, 112 F15_64 = 92, 113 F16_64 = 93, 114 F17_64 = 94, 115 F18_64 = 95, 116 F19_64 = 96, 117 F20_64 = 97, 118 F21_64 = 98, 119 F22_64 = 99, 120 F23_64 = 100, 121 F24_64 = 101, 122 F25_64 = 102, 123 F26_64 = 103, 124 F27_64 = 104, 125 F28_64 = 105, 126 F29_64 = 106, 127 F30_64 = 107, 128 F31_64 = 108, 129 NUM_TARGET_REGS // 109 130}; 131} // end namespace LoongArch 132 133// Register classes 134 135namespace LoongArch { 136enum { 137 FPR32RegClassID = 0, 138 GPRRegClassID = 1, 139 GPRTRegClassID = 2, 140 CFRRegClassID = 3, 141 FCSRRegClassID = 4, 142 FPR64RegClassID = 5, 143 144}; 145} // end namespace LoongArch 146 147 148// Register alternate name indices 149 150namespace LoongArch { 151enum { 152 NoRegAltName, // 0 153 RegAliasName, // 1 154 NUM_TARGET_REG_ALT_NAMES = 2 155}; 156} // end namespace LoongArch 157 158 159// Subregister indices 160 161namespace LoongArch { 162enum : uint16_t { 163 NoSubRegister, 164 sub_32, // 1 165 NUM_TARGET_SUBREGS 166}; 167} // end namespace LoongArch 168 169// Register pressure sets enum. 170namespace LoongArch { 171enum RegisterPressureSets { 172 CFR = 0, 173 GPRT = 1, 174 FPR32 = 2, 175 GPR = 3, 176}; 177} // end namespace LoongArch 178 179} // end namespace llvm 180 181#endif // GET_REGINFO_ENUM 182 183/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 184|* *| 185|* MC Register Information *| 186|* *| 187|* Automatically generated file, do not edit! *| 188|* *| 189\*===----------------------------------------------------------------------===*/ 190 191 192#ifdef GET_REGINFO_MC_DESC 193#undef GET_REGINFO_MC_DESC 194 195namespace llvm { 196 197extern const MCPhysReg LoongArchRegDiffLists[] = { 198 /* 0 */ 76, 0, 199 /* 2 */ 65459, 0, 200 /* 4 */ 65460, 0, 201 /* 6 */ 65535, 0, 202}; 203 204extern const LaneBitmask LoongArchLaneMaskLists[] = { 205 /* 0 */ LaneBitmask(0x0000000000000000), LaneBitmask::getAll(), 206 /* 2 */ LaneBitmask(0x0000000000000001), LaneBitmask::getAll(), 207}; 208 209extern const uint16_t LoongArchSubRegIdxLists[] = { 210 /* 0 */ 1, 0, 211}; 212 213extern const MCRegisterInfo::SubRegCoveredBits LoongArchSubRegIdxRanges[] = { 214 { 65535, 65535 }, 215 { 0, 32 }, // sub_32 216}; 217 218 219#ifdef __GNUC__ 220#pragma GCC diagnostic push 221#pragma GCC diagnostic ignored "-Woverlength-strings" 222#endif 223extern const char LoongArchRegStrings[] = { 224 /* 0 */ "F10\0" 225 /* 4 */ "R10\0" 226 /* 8 */ "F20\0" 227 /* 12 */ "R20\0" 228 /* 16 */ "F30\0" 229 /* 20 */ "R30\0" 230 /* 24 */ "FCC0\0" 231 /* 29 */ "F0\0" 232 /* 32 */ "FCSR0\0" 233 /* 38 */ "F11\0" 234 /* 42 */ "R11\0" 235 /* 46 */ "F21\0" 236 /* 50 */ "R21\0" 237 /* 54 */ "F31\0" 238 /* 58 */ "R31\0" 239 /* 62 */ "FCC1\0" 240 /* 67 */ "F1\0" 241 /* 70 */ "FCSR1\0" 242 /* 76 */ "F12\0" 243 /* 80 */ "R12\0" 244 /* 84 */ "F22\0" 245 /* 88 */ "R22\0" 246 /* 92 */ "FCC2\0" 247 /* 97 */ "F2\0" 248 /* 100 */ "FCSR2\0" 249 /* 106 */ "F13\0" 250 /* 110 */ "R13\0" 251 /* 114 */ "F23\0" 252 /* 118 */ "R23\0" 253 /* 122 */ "FCC3\0" 254 /* 127 */ "F3\0" 255 /* 130 */ "FCSR3\0" 256 /* 136 */ "F14\0" 257 /* 140 */ "R14\0" 258 /* 144 */ "F24\0" 259 /* 148 */ "R24\0" 260 /* 152 */ "F10_64\0" 261 /* 159 */ "F20_64\0" 262 /* 166 */ "F30_64\0" 263 /* 173 */ "F0_64\0" 264 /* 179 */ "F11_64\0" 265 /* 186 */ "F21_64\0" 266 /* 193 */ "F31_64\0" 267 /* 200 */ "F1_64\0" 268 /* 206 */ "F12_64\0" 269 /* 213 */ "F22_64\0" 270 /* 220 */ "F2_64\0" 271 /* 226 */ "F13_64\0" 272 /* 233 */ "F23_64\0" 273 /* 240 */ "F3_64\0" 274 /* 246 */ "F14_64\0" 275 /* 253 */ "F24_64\0" 276 /* 260 */ "F4_64\0" 277 /* 266 */ "F15_64\0" 278 /* 273 */ "F25_64\0" 279 /* 280 */ "F5_64\0" 280 /* 286 */ "F16_64\0" 281 /* 293 */ "F26_64\0" 282 /* 300 */ "F6_64\0" 283 /* 306 */ "F17_64\0" 284 /* 313 */ "F27_64\0" 285 /* 320 */ "F7_64\0" 286 /* 326 */ "F18_64\0" 287 /* 333 */ "F28_64\0" 288 /* 340 */ "F8_64\0" 289 /* 346 */ "F19_64\0" 290 /* 353 */ "F29_64\0" 291 /* 360 */ "F9_64\0" 292 /* 366 */ "FCC4\0" 293 /* 371 */ "F4\0" 294 /* 374 */ "R4\0" 295 /* 377 */ "F15\0" 296 /* 381 */ "R15\0" 297 /* 385 */ "F25\0" 298 /* 389 */ "R25\0" 299 /* 393 */ "FCC5\0" 300 /* 398 */ "F5\0" 301 /* 401 */ "R5\0" 302 /* 404 */ "F16\0" 303 /* 408 */ "R16\0" 304 /* 412 */ "F26\0" 305 /* 416 */ "R26\0" 306 /* 420 */ "FCC6\0" 307 /* 425 */ "F6\0" 308 /* 428 */ "R6\0" 309 /* 431 */ "F17\0" 310 /* 435 */ "R17\0" 311 /* 439 */ "F27\0" 312 /* 443 */ "R27\0" 313 /* 447 */ "FCC7\0" 314 /* 452 */ "F7\0" 315 /* 455 */ "R7\0" 316 /* 458 */ "F18\0" 317 /* 462 */ "R18\0" 318 /* 466 */ "F28\0" 319 /* 470 */ "R28\0" 320 /* 474 */ "F8\0" 321 /* 477 */ "R8\0" 322 /* 480 */ "F19\0" 323 /* 484 */ "R19\0" 324 /* 488 */ "F29\0" 325 /* 492 */ "R29\0" 326 /* 496 */ "F9\0" 327 /* 499 */ "R9\0" 328}; 329#ifdef __GNUC__ 330#pragma GCC diagnostic pop 331#endif 332 333extern const MCRegisterDesc LoongArchRegDesc[] = { // Descriptors 334 { 3, 0, 0, 0, 0, 0 }, 335 { 29, 1, 0, 1, 97, 0 }, 336 { 67, 1, 0, 1, 97, 0 }, 337 { 97, 1, 0, 1, 97, 0 }, 338 { 127, 1, 0, 1, 97, 0 }, 339 { 371, 1, 0, 1, 97, 0 }, 340 { 398, 1, 0, 1, 97, 0 }, 341 { 425, 1, 0, 1, 97, 0 }, 342 { 452, 1, 0, 1, 97, 0 }, 343 { 474, 1, 0, 1, 97, 0 }, 344 { 496, 1, 0, 1, 97, 0 }, 345 { 0, 1, 0, 1, 97, 0 }, 346 { 38, 1, 0, 1, 97, 0 }, 347 { 76, 1, 0, 1, 97, 0 }, 348 { 106, 1, 0, 1, 97, 0 }, 349 { 136, 1, 0, 1, 97, 0 }, 350 { 377, 1, 0, 1, 97, 0 }, 351 { 404, 1, 0, 1, 97, 0 }, 352 { 431, 1, 0, 1, 97, 0 }, 353 { 458, 1, 0, 1, 97, 0 }, 354 { 480, 1, 0, 1, 97, 0 }, 355 { 8, 1, 0, 1, 97, 0 }, 356 { 46, 1, 0, 1, 97, 0 }, 357 { 84, 1, 0, 1, 97, 0 }, 358 { 114, 1, 0, 1, 97, 0 }, 359 { 144, 1, 0, 1, 97, 0 }, 360 { 385, 1, 0, 1, 97, 0 }, 361 { 412, 1, 0, 1, 97, 0 }, 362 { 439, 1, 0, 1, 97, 0 }, 363 { 466, 1, 0, 1, 97, 0 }, 364 { 488, 1, 0, 1, 97, 0 }, 365 { 16, 1, 0, 1, 97, 0 }, 366 { 54, 1, 0, 1, 97, 0 }, 367 { 24, 1, 1, 1, 97, 0 }, 368 { 62, 1, 1, 1, 97, 0 }, 369 { 92, 1, 1, 1, 97, 0 }, 370 { 122, 1, 1, 1, 97, 0 }, 371 { 366, 1, 1, 1, 97, 0 }, 372 { 393, 1, 1, 1, 97, 0 }, 373 { 420, 1, 1, 1, 97, 0 }, 374 { 447, 1, 1, 1, 97, 0 }, 375 { 32, 1, 1, 1, 97, 0 }, 376 { 70, 1, 1, 1, 97, 0 }, 377 { 100, 1, 1, 1, 97, 0 }, 378 { 130, 1, 1, 1, 97, 0 }, 379 { 35, 1, 1, 1, 97, 0 }, 380 { 73, 1, 1, 1, 97, 0 }, 381 { 103, 1, 1, 1, 97, 0 }, 382 { 133, 1, 1, 1, 97, 0 }, 383 { 374, 1, 1, 1, 97, 0 }, 384 { 401, 1, 1, 1, 97, 0 }, 385 { 428, 1, 1, 1, 97, 0 }, 386 { 455, 1, 1, 1, 97, 0 }, 387 { 477, 1, 1, 1, 97, 0 }, 388 { 499, 1, 1, 1, 97, 0 }, 389 { 4, 1, 1, 1, 97, 0 }, 390 { 42, 1, 1, 1, 97, 0 }, 391 { 80, 1, 1, 1, 97, 0 }, 392 { 110, 1, 1, 1, 97, 0 }, 393 { 140, 1, 1, 1, 97, 0 }, 394 { 381, 1, 1, 1, 97, 0 }, 395 { 408, 1, 1, 1, 97, 0 }, 396 { 435, 1, 1, 1, 97, 0 }, 397 { 462, 1, 1, 1, 97, 0 }, 398 { 484, 1, 1, 1, 97, 0 }, 399 { 12, 1, 1, 1, 97, 0 }, 400 { 50, 1, 1, 1, 97, 0 }, 401 { 88, 1, 1, 1, 97, 0 }, 402 { 118, 1, 1, 1, 97, 0 }, 403 { 148, 1, 1, 1, 97, 0 }, 404 { 389, 1, 1, 1, 97, 0 }, 405 { 416, 1, 1, 1, 97, 0 }, 406 { 443, 1, 1, 1, 97, 0 }, 407 { 470, 1, 1, 1, 97, 0 }, 408 { 492, 1, 1, 1, 97, 0 }, 409 { 20, 1, 1, 1, 97, 0 }, 410 { 58, 1, 1, 1, 97, 0 }, 411 { 173, 4, 1, 0, 33, 2 }, 412 { 200, 4, 1, 0, 33, 2 }, 413 { 220, 4, 1, 0, 33, 2 }, 414 { 240, 4, 1, 0, 33, 2 }, 415 { 260, 4, 1, 0, 33, 2 }, 416 { 280, 4, 1, 0, 33, 2 }, 417 { 300, 4, 1, 0, 33, 2 }, 418 { 320, 4, 1, 0, 33, 2 }, 419 { 340, 4, 1, 0, 33, 2 }, 420 { 360, 4, 1, 0, 33, 2 }, 421 { 152, 4, 1, 0, 33, 2 }, 422 { 179, 4, 1, 0, 33, 2 }, 423 { 206, 4, 1, 0, 33, 2 }, 424 { 226, 4, 1, 0, 33, 2 }, 425 { 246, 4, 1, 0, 33, 2 }, 426 { 266, 4, 1, 0, 33, 2 }, 427 { 286, 4, 1, 0, 33, 2 }, 428 { 306, 4, 1, 0, 33, 2 }, 429 { 326, 4, 1, 0, 33, 2 }, 430 { 346, 4, 1, 0, 33, 2 }, 431 { 159, 4, 1, 0, 33, 2 }, 432 { 186, 4, 1, 0, 33, 2 }, 433 { 213, 4, 1, 0, 33, 2 }, 434 { 233, 4, 1, 0, 33, 2 }, 435 { 253, 4, 1, 0, 33, 2 }, 436 { 273, 4, 1, 0, 33, 2 }, 437 { 293, 4, 1, 0, 33, 2 }, 438 { 313, 4, 1, 0, 33, 2 }, 439 { 333, 4, 1, 0, 33, 2 }, 440 { 353, 4, 1, 0, 33, 2 }, 441 { 166, 4, 1, 0, 33, 2 }, 442 { 193, 4, 1, 0, 33, 2 }, 443}; 444 445extern const MCPhysReg LoongArchRegUnitRoots[][2] = { 446 { LoongArch::F0 }, 447 { LoongArch::F1 }, 448 { LoongArch::F2 }, 449 { LoongArch::F3 }, 450 { LoongArch::F4 }, 451 { LoongArch::F5 }, 452 { LoongArch::F6 }, 453 { LoongArch::F7 }, 454 { LoongArch::F8 }, 455 { LoongArch::F9 }, 456 { LoongArch::F10 }, 457 { LoongArch::F11 }, 458 { LoongArch::F12 }, 459 { LoongArch::F13 }, 460 { LoongArch::F14 }, 461 { LoongArch::F15 }, 462 { LoongArch::F16 }, 463 { LoongArch::F17 }, 464 { LoongArch::F18 }, 465 { LoongArch::F19 }, 466 { LoongArch::F20 }, 467 { LoongArch::F21 }, 468 { LoongArch::F22 }, 469 { LoongArch::F23 }, 470 { LoongArch::F24 }, 471 { LoongArch::F25 }, 472 { LoongArch::F26 }, 473 { LoongArch::F27 }, 474 { LoongArch::F28 }, 475 { LoongArch::F29 }, 476 { LoongArch::F30 }, 477 { LoongArch::F31 }, 478 { LoongArch::FCC0 }, 479 { LoongArch::FCC1 }, 480 { LoongArch::FCC2 }, 481 { LoongArch::FCC3 }, 482 { LoongArch::FCC4 }, 483 { LoongArch::FCC5 }, 484 { LoongArch::FCC6 }, 485 { LoongArch::FCC7 }, 486 { LoongArch::FCSR0 }, 487 { LoongArch::FCSR1 }, 488 { LoongArch::FCSR2 }, 489 { LoongArch::FCSR3 }, 490 { LoongArch::R0 }, 491 { LoongArch::R1 }, 492 { LoongArch::R2 }, 493 { LoongArch::R3 }, 494 { LoongArch::R4 }, 495 { LoongArch::R5 }, 496 { LoongArch::R6 }, 497 { LoongArch::R7 }, 498 { LoongArch::R8 }, 499 { LoongArch::R9 }, 500 { LoongArch::R10 }, 501 { LoongArch::R11 }, 502 { LoongArch::R12 }, 503 { LoongArch::R13 }, 504 { LoongArch::R14 }, 505 { LoongArch::R15 }, 506 { LoongArch::R16 }, 507 { LoongArch::R17 }, 508 { LoongArch::R18 }, 509 { LoongArch::R19 }, 510 { LoongArch::R20 }, 511 { LoongArch::R21 }, 512 { LoongArch::R22 }, 513 { LoongArch::R23 }, 514 { LoongArch::R24 }, 515 { LoongArch::R25 }, 516 { LoongArch::R26 }, 517 { LoongArch::R27 }, 518 { LoongArch::R28 }, 519 { LoongArch::R29 }, 520 { LoongArch::R30 }, 521 { LoongArch::R31 }, 522}; 523 524namespace { // Register classes... 525 // FPR32 Register Class... 526 const MCPhysReg FPR32[] = { 527 LoongArch::F0, LoongArch::F1, LoongArch::F2, LoongArch::F3, LoongArch::F4, LoongArch::F5, LoongArch::F6, LoongArch::F7, LoongArch::F8, LoongArch::F9, LoongArch::F10, LoongArch::F11, LoongArch::F12, LoongArch::F13, LoongArch::F14, LoongArch::F15, LoongArch::F16, LoongArch::F17, LoongArch::F18, LoongArch::F19, LoongArch::F20, LoongArch::F21, LoongArch::F22, LoongArch::F23, LoongArch::F24, LoongArch::F25, LoongArch::F26, LoongArch::F27, LoongArch::F28, LoongArch::F29, LoongArch::F30, LoongArch::F31, 528 }; 529 530 // FPR32 Bit set. 531 const uint8_t FPR32Bits[] = { 532 0xfe, 0xff, 0xff, 0xff, 0x01, 533 }; 534 535 // GPR Register Class... 536 const MCPhysReg GPR[] = { 537 LoongArch::R4, LoongArch::R5, LoongArch::R6, LoongArch::R7, LoongArch::R8, LoongArch::R9, LoongArch::R10, LoongArch::R11, LoongArch::R12, LoongArch::R13, LoongArch::R14, LoongArch::R15, LoongArch::R16, LoongArch::R17, LoongArch::R18, LoongArch::R19, LoongArch::R20, LoongArch::R22, LoongArch::R23, LoongArch::R24, LoongArch::R25, LoongArch::R26, LoongArch::R27, LoongArch::R28, LoongArch::R29, LoongArch::R30, LoongArch::R31, LoongArch::R0, LoongArch::R1, LoongArch::R2, LoongArch::R3, LoongArch::R21, 538 }; 539 540 // GPR Bit set. 541 const uint8_t GPRBits[] = { 542 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 543 }; 544 545 // GPRT Register Class... 546 const MCPhysReg GPRT[] = { 547 LoongArch::R4, LoongArch::R5, LoongArch::R6, LoongArch::R7, LoongArch::R8, LoongArch::R9, LoongArch::R10, LoongArch::R11, LoongArch::R12, LoongArch::R13, LoongArch::R14, LoongArch::R15, LoongArch::R16, LoongArch::R17, LoongArch::R18, LoongArch::R19, LoongArch::R20, 548 }; 549 550 // GPRT Bit set. 551 const uint8_t GPRTBits[] = { 552 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x03, 553 }; 554 555 // CFR Register Class... 556 const MCPhysReg CFR[] = { 557 LoongArch::FCC0, LoongArch::FCC1, LoongArch::FCC2, LoongArch::FCC3, LoongArch::FCC4, LoongArch::FCC5, LoongArch::FCC6, LoongArch::FCC7, 558 }; 559 560 // CFR Bit set. 561 const uint8_t CFRBits[] = { 562 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01, 563 }; 564 565 // FCSR Register Class... 566 const MCPhysReg FCSR[] = { 567 LoongArch::FCSR0, LoongArch::FCSR1, LoongArch::FCSR2, LoongArch::FCSR3, 568 }; 569 570 // FCSR Bit set. 571 const uint8_t FCSRBits[] = { 572 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, 573 }; 574 575 // FPR64 Register Class... 576 const MCPhysReg FPR64[] = { 577 LoongArch::F0_64, LoongArch::F1_64, LoongArch::F2_64, LoongArch::F3_64, LoongArch::F4_64, LoongArch::F5_64, LoongArch::F6_64, LoongArch::F7_64, LoongArch::F8_64, LoongArch::F9_64, LoongArch::F10_64, LoongArch::F11_64, LoongArch::F12_64, LoongArch::F13_64, LoongArch::F14_64, LoongArch::F15_64, LoongArch::F16_64, LoongArch::F17_64, LoongArch::F18_64, LoongArch::F19_64, LoongArch::F20_64, LoongArch::F21_64, LoongArch::F22_64, LoongArch::F23_64, LoongArch::F24_64, LoongArch::F25_64, LoongArch::F26_64, LoongArch::F27_64, LoongArch::F28_64, LoongArch::F29_64, LoongArch::F30_64, LoongArch::F31_64, 578 }; 579 580 // FPR64 Bit set. 581 const uint8_t FPR64Bits[] = { 582 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 583 }; 584 585} // end anonymous namespace 586 587 588#ifdef __GNUC__ 589#pragma GCC diagnostic push 590#pragma GCC diagnostic ignored "-Woverlength-strings" 591#endif 592extern const char LoongArchRegClassStrings[] = { 593 /* 0 */ "FPR32\0" 594 /* 6 */ "FPR64\0" 595 /* 12 */ "CFR\0" 596 /* 16 */ "GPR\0" 597 /* 20 */ "FCSR\0" 598 /* 25 */ "GPRT\0" 599}; 600#ifdef __GNUC__ 601#pragma GCC diagnostic pop 602#endif 603 604extern const MCRegisterClass LoongArchMCRegisterClasses[] = { 605 { FPR32, FPR32Bits, 0, 32, sizeof(FPR32Bits), LoongArch::FPR32RegClassID, 32, 1, true }, 606 { GPR, GPRBits, 16, 32, sizeof(GPRBits), LoongArch::GPRRegClassID, 0, 1, true }, 607 { GPRT, GPRTBits, 25, 17, sizeof(GPRTBits), LoongArch::GPRTRegClassID, 0, 1, true }, 608 { CFR, CFRBits, 12, 8, sizeof(CFRBits), LoongArch::CFRRegClassID, 0, 1, true }, 609 { FCSR, FCSRBits, 20, 4, sizeof(FCSRBits), LoongArch::FCSRRegClassID, 32, 1, false }, 610 { FPR64, FPR64Bits, 6, 32, sizeof(FPR64Bits), LoongArch::FPR64RegClassID, 64, 1, true }, 611}; 612 613// LoongArch Dwarf<->LLVM register mappings. 614extern const MCRegisterInfo::DwarfLLVMRegPair LoongArchDwarfFlavour0Dwarf2L[] = { 615 { 0U, LoongArch::R0 }, 616 { 1U, LoongArch::R1 }, 617 { 2U, LoongArch::R2 }, 618 { 3U, LoongArch::R3 }, 619 { 4U, LoongArch::R4 }, 620 { 5U, LoongArch::R5 }, 621 { 6U, LoongArch::R6 }, 622 { 7U, LoongArch::R7 }, 623 { 8U, LoongArch::R8 }, 624 { 9U, LoongArch::R9 }, 625 { 10U, LoongArch::R10 }, 626 { 11U, LoongArch::R11 }, 627 { 12U, LoongArch::R12 }, 628 { 13U, LoongArch::R13 }, 629 { 14U, LoongArch::R14 }, 630 { 15U, LoongArch::R15 }, 631 { 16U, LoongArch::R16 }, 632 { 17U, LoongArch::R17 }, 633 { 18U, LoongArch::R18 }, 634 { 19U, LoongArch::R19 }, 635 { 20U, LoongArch::R20 }, 636 { 21U, LoongArch::R21 }, 637 { 22U, LoongArch::R22 }, 638 { 23U, LoongArch::R23 }, 639 { 24U, LoongArch::R24 }, 640 { 25U, LoongArch::R25 }, 641 { 26U, LoongArch::R26 }, 642 { 27U, LoongArch::R27 }, 643 { 28U, LoongArch::R28 }, 644 { 29U, LoongArch::R29 }, 645 { 30U, LoongArch::R30 }, 646 { 31U, LoongArch::R31 }, 647 { 32U, LoongArch::F0_64 }, 648 { 33U, LoongArch::F1_64 }, 649 { 34U, LoongArch::F2_64 }, 650 { 35U, LoongArch::F3_64 }, 651 { 36U, LoongArch::F4_64 }, 652 { 37U, LoongArch::F5_64 }, 653 { 38U, LoongArch::F6_64 }, 654 { 39U, LoongArch::F7_64 }, 655 { 40U, LoongArch::F8_64 }, 656 { 41U, LoongArch::F9_64 }, 657 { 42U, LoongArch::F10_64 }, 658 { 43U, LoongArch::F11_64 }, 659 { 44U, LoongArch::F12_64 }, 660 { 45U, LoongArch::F13_64 }, 661 { 46U, LoongArch::F14_64 }, 662 { 47U, LoongArch::F15_64 }, 663 { 48U, LoongArch::F16_64 }, 664 { 49U, LoongArch::F17_64 }, 665 { 50U, LoongArch::F18_64 }, 666 { 51U, LoongArch::F19_64 }, 667 { 52U, LoongArch::F20_64 }, 668 { 53U, LoongArch::F21_64 }, 669 { 54U, LoongArch::F22_64 }, 670 { 55U, LoongArch::F23_64 }, 671 { 56U, LoongArch::F24_64 }, 672 { 57U, LoongArch::F25_64 }, 673 { 58U, LoongArch::F26_64 }, 674 { 59U, LoongArch::F27_64 }, 675 { 60U, LoongArch::F28_64 }, 676 { 61U, LoongArch::F29_64 }, 677 { 62U, LoongArch::F30_64 }, 678 { 63U, LoongArch::F31_64 }, 679}; 680extern const unsigned LoongArchDwarfFlavour0Dwarf2LSize = std::size(LoongArchDwarfFlavour0Dwarf2L); 681 682extern const MCRegisterInfo::DwarfLLVMRegPair LoongArchEHFlavour0Dwarf2L[] = { 683 { 0U, LoongArch::R0 }, 684 { 1U, LoongArch::R1 }, 685 { 2U, LoongArch::R2 }, 686 { 3U, LoongArch::R3 }, 687 { 4U, LoongArch::R4 }, 688 { 5U, LoongArch::R5 }, 689 { 6U, LoongArch::R6 }, 690 { 7U, LoongArch::R7 }, 691 { 8U, LoongArch::R8 }, 692 { 9U, LoongArch::R9 }, 693 { 10U, LoongArch::R10 }, 694 { 11U, LoongArch::R11 }, 695 { 12U, LoongArch::R12 }, 696 { 13U, LoongArch::R13 }, 697 { 14U, LoongArch::R14 }, 698 { 15U, LoongArch::R15 }, 699 { 16U, LoongArch::R16 }, 700 { 17U, LoongArch::R17 }, 701 { 18U, LoongArch::R18 }, 702 { 19U, LoongArch::R19 }, 703 { 20U, LoongArch::R20 }, 704 { 21U, LoongArch::R21 }, 705 { 22U, LoongArch::R22 }, 706 { 23U, LoongArch::R23 }, 707 { 24U, LoongArch::R24 }, 708 { 25U, LoongArch::R25 }, 709 { 26U, LoongArch::R26 }, 710 { 27U, LoongArch::R27 }, 711 { 28U, LoongArch::R28 }, 712 { 29U, LoongArch::R29 }, 713 { 30U, LoongArch::R30 }, 714 { 31U, LoongArch::R31 }, 715 { 32U, LoongArch::F0_64 }, 716 { 33U, LoongArch::F1_64 }, 717 { 34U, LoongArch::F2_64 }, 718 { 35U, LoongArch::F3_64 }, 719 { 36U, LoongArch::F4_64 }, 720 { 37U, LoongArch::F5_64 }, 721 { 38U, LoongArch::F6_64 }, 722 { 39U, LoongArch::F7_64 }, 723 { 40U, LoongArch::F8_64 }, 724 { 41U, LoongArch::F9_64 }, 725 { 42U, LoongArch::F10_64 }, 726 { 43U, LoongArch::F11_64 }, 727 { 44U, LoongArch::F12_64 }, 728 { 45U, LoongArch::F13_64 }, 729 { 46U, LoongArch::F14_64 }, 730 { 47U, LoongArch::F15_64 }, 731 { 48U, LoongArch::F16_64 }, 732 { 49U, LoongArch::F17_64 }, 733 { 50U, LoongArch::F18_64 }, 734 { 51U, LoongArch::F19_64 }, 735 { 52U, LoongArch::F20_64 }, 736 { 53U, LoongArch::F21_64 }, 737 { 54U, LoongArch::F22_64 }, 738 { 55U, LoongArch::F23_64 }, 739 { 56U, LoongArch::F24_64 }, 740 { 57U, LoongArch::F25_64 }, 741 { 58U, LoongArch::F26_64 }, 742 { 59U, LoongArch::F27_64 }, 743 { 60U, LoongArch::F28_64 }, 744 { 61U, LoongArch::F29_64 }, 745 { 62U, LoongArch::F30_64 }, 746 { 63U, LoongArch::F31_64 }, 747}; 748extern const unsigned LoongArchEHFlavour0Dwarf2LSize = std::size(LoongArchEHFlavour0Dwarf2L); 749 750extern const MCRegisterInfo::DwarfLLVMRegPair LoongArchDwarfFlavour0L2Dwarf[] = { 751 { LoongArch::F0, 32U }, 752 { LoongArch::F1, 33U }, 753 { LoongArch::F2, 34U }, 754 { LoongArch::F3, 35U }, 755 { LoongArch::F4, 36U }, 756 { LoongArch::F5, 37U }, 757 { LoongArch::F6, 38U }, 758 { LoongArch::F7, 39U }, 759 { LoongArch::F8, 40U }, 760 { LoongArch::F9, 41U }, 761 { LoongArch::F10, 42U }, 762 { LoongArch::F11, 43U }, 763 { LoongArch::F12, 44U }, 764 { LoongArch::F13, 45U }, 765 { LoongArch::F14, 46U }, 766 { LoongArch::F15, 47U }, 767 { LoongArch::F16, 48U }, 768 { LoongArch::F17, 49U }, 769 { LoongArch::F18, 50U }, 770 { LoongArch::F19, 51U }, 771 { LoongArch::F20, 52U }, 772 { LoongArch::F21, 53U }, 773 { LoongArch::F22, 54U }, 774 { LoongArch::F23, 55U }, 775 { LoongArch::F24, 56U }, 776 { LoongArch::F25, 57U }, 777 { LoongArch::F26, 58U }, 778 { LoongArch::F27, 59U }, 779 { LoongArch::F28, 60U }, 780 { LoongArch::F29, 61U }, 781 { LoongArch::F30, 62U }, 782 { LoongArch::F31, 63U }, 783 { LoongArch::R0, 0U }, 784 { LoongArch::R1, 1U }, 785 { LoongArch::R2, 2U }, 786 { LoongArch::R3, 3U }, 787 { LoongArch::R4, 4U }, 788 { LoongArch::R5, 5U }, 789 { LoongArch::R6, 6U }, 790 { LoongArch::R7, 7U }, 791 { LoongArch::R8, 8U }, 792 { LoongArch::R9, 9U }, 793 { LoongArch::R10, 10U }, 794 { LoongArch::R11, 11U }, 795 { LoongArch::R12, 12U }, 796 { LoongArch::R13, 13U }, 797 { LoongArch::R14, 14U }, 798 { LoongArch::R15, 15U }, 799 { LoongArch::R16, 16U }, 800 { LoongArch::R17, 17U }, 801 { LoongArch::R18, 18U }, 802 { LoongArch::R19, 19U }, 803 { LoongArch::R20, 20U }, 804 { LoongArch::R21, 21U }, 805 { LoongArch::R22, 22U }, 806 { LoongArch::R23, 23U }, 807 { LoongArch::R24, 24U }, 808 { LoongArch::R25, 25U }, 809 { LoongArch::R26, 26U }, 810 { LoongArch::R27, 27U }, 811 { LoongArch::R28, 28U }, 812 { LoongArch::R29, 29U }, 813 { LoongArch::R30, 30U }, 814 { LoongArch::R31, 31U }, 815 { LoongArch::F0_64, 32U }, 816 { LoongArch::F1_64, 33U }, 817 { LoongArch::F2_64, 34U }, 818 { LoongArch::F3_64, 35U }, 819 { LoongArch::F4_64, 36U }, 820 { LoongArch::F5_64, 37U }, 821 { LoongArch::F6_64, 38U }, 822 { LoongArch::F7_64, 39U }, 823 { LoongArch::F8_64, 40U }, 824 { LoongArch::F9_64, 41U }, 825 { LoongArch::F10_64, 42U }, 826 { LoongArch::F11_64, 43U }, 827 { LoongArch::F12_64, 44U }, 828 { LoongArch::F13_64, 45U }, 829 { LoongArch::F14_64, 46U }, 830 { LoongArch::F15_64, 47U }, 831 { LoongArch::F16_64, 48U }, 832 { LoongArch::F17_64, 49U }, 833 { LoongArch::F18_64, 50U }, 834 { LoongArch::F19_64, 51U }, 835 { LoongArch::F20_64, 52U }, 836 { LoongArch::F21_64, 53U }, 837 { LoongArch::F22_64, 54U }, 838 { LoongArch::F23_64, 55U }, 839 { LoongArch::F24_64, 56U }, 840 { LoongArch::F25_64, 57U }, 841 { LoongArch::F26_64, 58U }, 842 { LoongArch::F27_64, 59U }, 843 { LoongArch::F28_64, 60U }, 844 { LoongArch::F29_64, 61U }, 845 { LoongArch::F30_64, 62U }, 846 { LoongArch::F31_64, 63U }, 847}; 848extern const unsigned LoongArchDwarfFlavour0L2DwarfSize = std::size(LoongArchDwarfFlavour0L2Dwarf); 849 850extern const MCRegisterInfo::DwarfLLVMRegPair LoongArchEHFlavour0L2Dwarf[] = { 851 { LoongArch::F0, 32U }, 852 { LoongArch::F1, 33U }, 853 { LoongArch::F2, 34U }, 854 { LoongArch::F3, 35U }, 855 { LoongArch::F4, 36U }, 856 { LoongArch::F5, 37U }, 857 { LoongArch::F6, 38U }, 858 { LoongArch::F7, 39U }, 859 { LoongArch::F8, 40U }, 860 { LoongArch::F9, 41U }, 861 { LoongArch::F10, 42U }, 862 { LoongArch::F11, 43U }, 863 { LoongArch::F12, 44U }, 864 { LoongArch::F13, 45U }, 865 { LoongArch::F14, 46U }, 866 { LoongArch::F15, 47U }, 867 { LoongArch::F16, 48U }, 868 { LoongArch::F17, 49U }, 869 { LoongArch::F18, 50U }, 870 { LoongArch::F19, 51U }, 871 { LoongArch::F20, 52U }, 872 { LoongArch::F21, 53U }, 873 { LoongArch::F22, 54U }, 874 { LoongArch::F23, 55U }, 875 { LoongArch::F24, 56U }, 876 { LoongArch::F25, 57U }, 877 { LoongArch::F26, 58U }, 878 { LoongArch::F27, 59U }, 879 { LoongArch::F28, 60U }, 880 { LoongArch::F29, 61U }, 881 { LoongArch::F30, 62U }, 882 { LoongArch::F31, 63U }, 883 { LoongArch::R0, 0U }, 884 { LoongArch::R1, 1U }, 885 { LoongArch::R2, 2U }, 886 { LoongArch::R3, 3U }, 887 { LoongArch::R4, 4U }, 888 { LoongArch::R5, 5U }, 889 { LoongArch::R6, 6U }, 890 { LoongArch::R7, 7U }, 891 { LoongArch::R8, 8U }, 892 { LoongArch::R9, 9U }, 893 { LoongArch::R10, 10U }, 894 { LoongArch::R11, 11U }, 895 { LoongArch::R12, 12U }, 896 { LoongArch::R13, 13U }, 897 { LoongArch::R14, 14U }, 898 { LoongArch::R15, 15U }, 899 { LoongArch::R16, 16U }, 900 { LoongArch::R17, 17U }, 901 { LoongArch::R18, 18U }, 902 { LoongArch::R19, 19U }, 903 { LoongArch::R20, 20U }, 904 { LoongArch::R21, 21U }, 905 { LoongArch::R22, 22U }, 906 { LoongArch::R23, 23U }, 907 { LoongArch::R24, 24U }, 908 { LoongArch::R25, 25U }, 909 { LoongArch::R26, 26U }, 910 { LoongArch::R27, 27U }, 911 { LoongArch::R28, 28U }, 912 { LoongArch::R29, 29U }, 913 { LoongArch::R30, 30U }, 914 { LoongArch::R31, 31U }, 915 { LoongArch::F0_64, 32U }, 916 { LoongArch::F1_64, 33U }, 917 { LoongArch::F2_64, 34U }, 918 { LoongArch::F3_64, 35U }, 919 { LoongArch::F4_64, 36U }, 920 { LoongArch::F5_64, 37U }, 921 { LoongArch::F6_64, 38U }, 922 { LoongArch::F7_64, 39U }, 923 { LoongArch::F8_64, 40U }, 924 { LoongArch::F9_64, 41U }, 925 { LoongArch::F10_64, 42U }, 926 { LoongArch::F11_64, 43U }, 927 { LoongArch::F12_64, 44U }, 928 { LoongArch::F13_64, 45U }, 929 { LoongArch::F14_64, 46U }, 930 { LoongArch::F15_64, 47U }, 931 { LoongArch::F16_64, 48U }, 932 { LoongArch::F17_64, 49U }, 933 { LoongArch::F18_64, 50U }, 934 { LoongArch::F19_64, 51U }, 935 { LoongArch::F20_64, 52U }, 936 { LoongArch::F21_64, 53U }, 937 { LoongArch::F22_64, 54U }, 938 { LoongArch::F23_64, 55U }, 939 { LoongArch::F24_64, 56U }, 940 { LoongArch::F25_64, 57U }, 941 { LoongArch::F26_64, 58U }, 942 { LoongArch::F27_64, 59U }, 943 { LoongArch::F28_64, 60U }, 944 { LoongArch::F29_64, 61U }, 945 { LoongArch::F30_64, 62U }, 946 { LoongArch::F31_64, 63U }, 947}; 948extern const unsigned LoongArchEHFlavour0L2DwarfSize = std::size(LoongArchEHFlavour0L2Dwarf); 949 950extern const uint16_t LoongArchRegEncodingTable[] = { 951 0, 952 0, 953 1, 954 2, 955 3, 956 4, 957 5, 958 6, 959 7, 960 8, 961 9, 962 10, 963 11, 964 12, 965 13, 966 14, 967 15, 968 16, 969 17, 970 18, 971 19, 972 20, 973 21, 974 22, 975 23, 976 24, 977 25, 978 26, 979 27, 980 28, 981 29, 982 30, 983 31, 984 0, 985 1, 986 2, 987 3, 988 4, 989 5, 990 6, 991 7, 992 0, 993 1, 994 2, 995 3, 996 0, 997 1, 998 2, 999 3, 1000 4, 1001 5, 1002 6, 1003 7, 1004 8, 1005 9, 1006 10, 1007 11, 1008 12, 1009 13, 1010 14, 1011 15, 1012 16, 1013 17, 1014 18, 1015 19, 1016 20, 1017 21, 1018 22, 1019 23, 1020 24, 1021 25, 1022 26, 1023 27, 1024 28, 1025 29, 1026 30, 1027 31, 1028 0, 1029 1, 1030 2, 1031 3, 1032 4, 1033 5, 1034 6, 1035 7, 1036 8, 1037 9, 1038 10, 1039 11, 1040 12, 1041 13, 1042 14, 1043 15, 1044 16, 1045 17, 1046 18, 1047 19, 1048 20, 1049 21, 1050 22, 1051 23, 1052 24, 1053 25, 1054 26, 1055 27, 1056 28, 1057 29, 1058 30, 1059 31, 1060}; 1061static inline void InitLoongArchMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) { 1062 RI->InitMCRegisterInfo(LoongArchRegDesc, 109, RA, PC, LoongArchMCRegisterClasses, 6, LoongArchRegUnitRoots, 76, LoongArchRegDiffLists, LoongArchLaneMaskLists, LoongArchRegStrings, LoongArchRegClassStrings, LoongArchSubRegIdxLists, 2, 1063LoongArchSubRegIdxRanges, LoongArchRegEncodingTable); 1064 1065 switch (DwarfFlavour) { 1066 default: 1067 llvm_unreachable("Unknown DWARF flavour"); 1068 case 0: 1069 RI->mapDwarfRegsToLLVMRegs(LoongArchDwarfFlavour0Dwarf2L, LoongArchDwarfFlavour0Dwarf2LSize, false); 1070 break; 1071 } 1072 switch (EHFlavour) { 1073 default: 1074 llvm_unreachable("Unknown DWARF flavour"); 1075 case 0: 1076 RI->mapDwarfRegsToLLVMRegs(LoongArchEHFlavour0Dwarf2L, LoongArchEHFlavour0Dwarf2LSize, true); 1077 break; 1078 } 1079 switch (DwarfFlavour) { 1080 default: 1081 llvm_unreachable("Unknown DWARF flavour"); 1082 case 0: 1083 RI->mapLLVMRegsToDwarfRegs(LoongArchDwarfFlavour0L2Dwarf, LoongArchDwarfFlavour0L2DwarfSize, false); 1084 break; 1085 } 1086 switch (EHFlavour) { 1087 default: 1088 llvm_unreachable("Unknown DWARF flavour"); 1089 case 0: 1090 RI->mapLLVMRegsToDwarfRegs(LoongArchEHFlavour0L2Dwarf, LoongArchEHFlavour0L2DwarfSize, true); 1091 break; 1092 } 1093} 1094 1095} // end namespace llvm 1096 1097#endif // GET_REGINFO_MC_DESC 1098 1099/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 1100|* *| 1101|* Register Information Header Fragment *| 1102|* *| 1103|* Automatically generated file, do not edit! *| 1104|* *| 1105\*===----------------------------------------------------------------------===*/ 1106 1107 1108#ifdef GET_REGINFO_HEADER 1109#undef GET_REGINFO_HEADER 1110 1111#include "llvm/CodeGen/TargetRegisterInfo.h" 1112 1113namespace llvm { 1114 1115class LoongArchFrameLowering; 1116 1117struct LoongArchGenRegisterInfo : public TargetRegisterInfo { 1118 explicit LoongArchGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0, 1119 unsigned PC = 0, unsigned HwMode = 0); 1120 unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override; 1121 LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override; 1122 LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override; 1123 const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass *, unsigned) const override; 1124 const TargetRegisterClass *getSubRegisterClass(const TargetRegisterClass *, unsigned) const override; 1125 const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override; 1126 unsigned getRegUnitWeight(unsigned RegUnit) const override; 1127 unsigned getNumRegPressureSets() const override; 1128 const char *getRegPressureSetName(unsigned Idx) const override; 1129 unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override; 1130 const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override; 1131 const int *getRegUnitPressureSets(unsigned RegUnit) const override; 1132 ArrayRef<const char *> getRegMaskNames() const override; 1133 ArrayRef<const uint32_t *> getRegMasks() const override; 1134 bool isGeneralPurposeRegister(const MachineFunction &, MCRegister) const override; 1135 bool isFixedRegister(const MachineFunction &, MCRegister) const override; 1136 bool isArgumentRegister(const MachineFunction &, MCRegister) const override; 1137 bool isConstantPhysReg(MCRegister PhysReg) const override final; 1138 /// Devirtualized TargetFrameLowering. 1139 static const LoongArchFrameLowering *getFrameLowering( 1140 const MachineFunction &MF); 1141}; 1142 1143namespace LoongArch { // Register classes 1144 extern const TargetRegisterClass FPR32RegClass; 1145 extern const TargetRegisterClass GPRRegClass; 1146 extern const TargetRegisterClass GPRTRegClass; 1147 extern const TargetRegisterClass CFRRegClass; 1148 extern const TargetRegisterClass FCSRRegClass; 1149 extern const TargetRegisterClass FPR64RegClass; 1150} // end namespace LoongArch 1151 1152} // end namespace llvm 1153 1154#endif // GET_REGINFO_HEADER 1155 1156/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 1157|* *| 1158|* Target Register and Register Classes Information *| 1159|* *| 1160|* Automatically generated file, do not edit! *| 1161|* *| 1162\*===----------------------------------------------------------------------===*/ 1163 1164 1165#ifdef GET_REGINFO_TARGET_DESC 1166#undef GET_REGINFO_TARGET_DESC 1167 1168namespace llvm { 1169 1170extern const MCRegisterClass LoongArchMCRegisterClasses[]; 1171 1172static const MVT::SimpleValueType VTLists[] = { 1173 /* 0 */ MVT::i32, MVT::Other, 1174 /* 2 */ MVT::i64, MVT::Other, 1175 /* 4 */ MVT::f32, MVT::Other, 1176 /* 6 */ MVT::f64, MVT::Other, 1177}; 1178 1179static const char *SubRegIndexNameTable[] = { "sub_32", "" }; 1180 1181 1182static const LaneBitmask SubRegIndexLaneMaskTable[] = { 1183 LaneBitmask::getAll(), 1184 LaneBitmask(0x0000000000000001), // sub_32 1185 }; 1186 1187 1188 1189static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = { 1190 // Mode = 0 (Default) 1191 { 32, 32, 32, VTLists+4 }, // FPR32 1192 { 32, 32, 32, VTLists+0 }, // GPR 1193 { 32, 32, 32, VTLists+0 }, // GPRT 1194 { 32, 32, 32, VTLists+0 }, // CFR 1195 { 32, 32, 32, VTLists+0 }, // FCSR 1196 { 64, 64, 64, VTLists+6 }, // FPR64 1197 // Mode = 1 (LA64) 1198 { 32, 32, 32, VTLists+4 }, // FPR32 1199 { 64, 64, 64, VTLists+2 }, // GPR 1200 { 64, 64, 64, VTLists+2 }, // GPRT 1201 { 64, 64, 64, VTLists+2 }, // CFR 1202 { 32, 32, 32, VTLists+0 }, // FCSR 1203 { 64, 64, 64, VTLists+6 }, // FPR64 1204}; 1205 1206static const TargetRegisterClass *const NullRegClasses[] = { nullptr }; 1207 1208static const uint32_t FPR32SubClassMask[] = { 1209 0x00000001, 1210 0x00000020, // sub_32 1211}; 1212 1213static const uint32_t GPRSubClassMask[] = { 1214 0x00000006, 1215}; 1216 1217static const uint32_t GPRTSubClassMask[] = { 1218 0x00000004, 1219}; 1220 1221static const uint32_t CFRSubClassMask[] = { 1222 0x00000008, 1223}; 1224 1225static const uint32_t FCSRSubClassMask[] = { 1226 0x00000010, 1227}; 1228 1229static const uint32_t FPR64SubClassMask[] = { 1230 0x00000020, 1231}; 1232 1233static const uint16_t SuperRegIdxSeqs[] = { 1234 /* 0 */ 1, 0, 1235}; 1236 1237static const TargetRegisterClass *const GPRTSuperclasses[] = { 1238 &LoongArch::GPRRegClass, 1239 nullptr 1240}; 1241 1242 1243namespace LoongArch { // Register class instances 1244 extern const TargetRegisterClass FPR32RegClass = { 1245 &LoongArchMCRegisterClasses[FPR32RegClassID], 1246 FPR32SubClassMask, 1247 SuperRegIdxSeqs + 0, 1248 LaneBitmask(0x0000000000000001), 1249 0, 1250 false, 1251 0x00, /* TSFlags */ 1252 false, /* HasDisjunctSubRegs */ 1253 false, /* CoveredBySubRegs */ 1254 NullRegClasses, 1255 nullptr 1256 }; 1257 1258 extern const TargetRegisterClass GPRRegClass = { 1259 &LoongArchMCRegisterClasses[GPRRegClassID], 1260 GPRSubClassMask, 1261 SuperRegIdxSeqs + 1, 1262 LaneBitmask(0x0000000000000001), 1263 0, 1264 false, 1265 0x00, /* TSFlags */ 1266 false, /* HasDisjunctSubRegs */ 1267 false, /* CoveredBySubRegs */ 1268 NullRegClasses, 1269 nullptr 1270 }; 1271 1272 extern const TargetRegisterClass GPRTRegClass = { 1273 &LoongArchMCRegisterClasses[GPRTRegClassID], 1274 GPRTSubClassMask, 1275 SuperRegIdxSeqs + 1, 1276 LaneBitmask(0x0000000000000001), 1277 0, 1278 false, 1279 0x00, /* TSFlags */ 1280 false, /* HasDisjunctSubRegs */ 1281 false, /* CoveredBySubRegs */ 1282 GPRTSuperclasses, 1283 nullptr 1284 }; 1285 1286 extern const TargetRegisterClass CFRRegClass = { 1287 &LoongArchMCRegisterClasses[CFRRegClassID], 1288 CFRSubClassMask, 1289 SuperRegIdxSeqs + 1, 1290 LaneBitmask(0x0000000000000001), 1291 0, 1292 false, 1293 0x00, /* TSFlags */ 1294 false, /* HasDisjunctSubRegs */ 1295 false, /* CoveredBySubRegs */ 1296 NullRegClasses, 1297 nullptr 1298 }; 1299 1300 extern const TargetRegisterClass FCSRRegClass = { 1301 &LoongArchMCRegisterClasses[FCSRRegClassID], 1302 FCSRSubClassMask, 1303 SuperRegIdxSeqs + 1, 1304 LaneBitmask(0x0000000000000001), 1305 0, 1306 false, 1307 0x00, /* TSFlags */ 1308 false, /* HasDisjunctSubRegs */ 1309 false, /* CoveredBySubRegs */ 1310 NullRegClasses, 1311 nullptr 1312 }; 1313 1314 extern const TargetRegisterClass FPR64RegClass = { 1315 &LoongArchMCRegisterClasses[FPR64RegClassID], 1316 FPR64SubClassMask, 1317 SuperRegIdxSeqs + 1, 1318 LaneBitmask(0x0000000000000001), 1319 0, 1320 false, 1321 0x00, /* TSFlags */ 1322 false, /* HasDisjunctSubRegs */ 1323 false, /* CoveredBySubRegs */ 1324 NullRegClasses, 1325 nullptr 1326 }; 1327 1328} // end namespace LoongArch 1329 1330namespace { 1331 const TargetRegisterClass *const RegisterClasses[] = { 1332 &LoongArch::FPR32RegClass, 1333 &LoongArch::GPRRegClass, 1334 &LoongArch::GPRTRegClass, 1335 &LoongArch::CFRRegClass, 1336 &LoongArch::FCSRRegClass, 1337 &LoongArch::FPR64RegClass, 1338 }; 1339} // end anonymous namespace 1340 1341static const uint8_t CostPerUseTable[] = { 13420, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; 1343 1344 1345static const bool InAllocatableClassTable[] = { 1346false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, }; 1347 1348 1349static const TargetRegisterInfoDesc LoongArchRegInfoDesc = { // Extra Descriptors 1350CostPerUseTable, 1, InAllocatableClassTable}; 1351 1352unsigned LoongArchGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const { 1353 static const uint8_t Rows[1][1] = { 1354 { 0, }, 1355 }; 1356 1357 --IdxA; assert(IdxA < 1); (void) IdxA; 1358 --IdxB; assert(IdxB < 1); 1359 return Rows[0][IdxB]; 1360} 1361 1362 struct MaskRolOp { 1363 LaneBitmask Mask; 1364 uint8_t RotateLeft; 1365 }; 1366 static const MaskRolOp LaneMaskComposeSequences[] = { 1367 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 0 }, { LaneBitmask::getNone(), 0 } // Sequence 0 1368 }; 1369 static const uint8_t CompositeSequences[] = { 1370 0 // to sub_32 1371 }; 1372 1373LaneBitmask LoongArchGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const { 1374 --IdxA; assert(IdxA < 1 && "Subregister index out of bounds"); 1375 LaneBitmask Result; 1376 for (const MaskRolOp *Ops = 1377 &LaneMaskComposeSequences[CompositeSequences[IdxA]]; 1378 Ops->Mask.any(); ++Ops) { 1379 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger(); 1380 if (unsigned S = Ops->RotateLeft) 1381 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S))); 1382 else 1383 Result |= LaneBitmask(M); 1384 } 1385 return Result; 1386} 1387 1388LaneBitmask LoongArchGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const { 1389 LaneMask &= getSubRegIndexLaneMask(IdxA); 1390 --IdxA; assert(IdxA < 1 && "Subregister index out of bounds"); 1391 LaneBitmask Result; 1392 for (const MaskRolOp *Ops = 1393 &LaneMaskComposeSequences[CompositeSequences[IdxA]]; 1394 Ops->Mask.any(); ++Ops) { 1395 LaneBitmask::Type M = LaneMask.getAsInteger(); 1396 if (unsigned S = Ops->RotateLeft) 1397 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S))); 1398 else 1399 Result |= LaneBitmask(M); 1400 } 1401 return Result; 1402} 1403 1404const TargetRegisterClass *LoongArchGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const { 1405 static const uint8_t Table[6][1] = { 1406 { // FPR32 1407 0, // sub_32 1408 }, 1409 { // GPR 1410 0, // sub_32 1411 }, 1412 { // GPRT 1413 0, // sub_32 1414 }, 1415 { // CFR 1416 0, // sub_32 1417 }, 1418 { // FCSR 1419 0, // sub_32 1420 }, 1421 { // FPR64 1422 6, // sub_32 -> FPR64 1423 }, 1424 }; 1425 assert(RC && "Missing regclass"); 1426 if (!Idx) return RC; 1427 --Idx; 1428 assert(Idx < 1 && "Bad subreg"); 1429 unsigned TV = Table[RC->getID()][Idx]; 1430 return TV ? getRegClass(TV - 1) : nullptr; 1431} 1432 1433const TargetRegisterClass *LoongArchGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const { 1434 static const uint8_t Table[6][1] = { 1435 { // FPR32 1436 0, // FPR32:sub_32 1437 }, 1438 { // GPR 1439 0, // GPR:sub_32 1440 }, 1441 { // GPRT 1442 0, // GPRT:sub_32 1443 }, 1444 { // CFR 1445 0, // CFR:sub_32 1446 }, 1447 { // FCSR 1448 0, // FCSR:sub_32 1449 }, 1450 { // FPR64 1451 1, // FPR64:sub_32 -> FPR32 1452 }, 1453 }; 1454 assert(RC && "Missing regclass"); 1455 if (!Idx) return RC; 1456 --Idx; 1457 assert(Idx < 1 && "Bad subreg"); 1458 unsigned TV = Table[RC->getID()][Idx]; 1459 return TV ? getRegClass(TV - 1) : nullptr; 1460} 1461 1462/// Get the weight in units of pressure for this register class. 1463const RegClassWeight &LoongArchGenRegisterInfo:: 1464getRegClassWeight(const TargetRegisterClass *RC) const { 1465 static const RegClassWeight RCWeightTable[] = { 1466 {1, 32}, // FPR32 1467 {1, 32}, // GPR 1468 {1, 17}, // GPRT 1469 {1, 8}, // CFR 1470 {0, 0}, // FCSR 1471 {1, 32}, // FPR64 1472 }; 1473 return RCWeightTable[RC->getID()]; 1474} 1475 1476/// Get the weight in units of pressure for this register unit. 1477unsigned LoongArchGenRegisterInfo:: 1478getRegUnitWeight(unsigned RegUnit) const { 1479 assert(RegUnit < 76 && "invalid register unit"); 1480 // All register units have unit weight. 1481 return 1; 1482} 1483 1484 1485// Get the number of dimensions of register pressure. 1486unsigned LoongArchGenRegisterInfo::getNumRegPressureSets() const { 1487 return 4; 1488} 1489 1490// Get the name of this register unit pressure set. 1491const char *LoongArchGenRegisterInfo:: 1492getRegPressureSetName(unsigned Idx) const { 1493 static const char *PressureNameTable[] = { 1494 "CFR", 1495 "GPRT", 1496 "FPR32", 1497 "GPR", 1498 }; 1499 return PressureNameTable[Idx]; 1500} 1501 1502// Get the register unit pressure limit for this dimension. 1503// This limit must be adjusted dynamically for reserved registers. 1504unsigned LoongArchGenRegisterInfo:: 1505getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const { 1506 static const uint8_t PressureLimitTable[] = { 1507 8, // 0: CFR 1508 17, // 1: GPRT 1509 32, // 2: FPR32 1510 32, // 3: GPR 1511 }; 1512 return PressureLimitTable[Idx]; 1513} 1514 1515/// Table of pressure sets per register class or unit. 1516static const int RCSetsTable[] = { 1517 /* 0 */ 0, -1, 1518 /* 2 */ 2, -1, 1519 /* 4 */ 1, 3, -1, 1520}; 1521 1522/// Get the dimensions of register pressure impacted by this register class. 1523/// Returns a -1 terminated array of pressure set IDs 1524const int *LoongArchGenRegisterInfo:: 1525getRegClassPressureSets(const TargetRegisterClass *RC) const { 1526 static const uint8_t RCSetStartTable[] = { 1527 2,5,4,0,1,2,}; 1528 return &RCSetsTable[RCSetStartTable[RC->getID()]]; 1529} 1530 1531/// Get the dimensions of register pressure impacted by this register unit. 1532/// Returns a -1 terminated array of pressure set IDs 1533const int *LoongArchGenRegisterInfo:: 1534getRegUnitPressureSets(unsigned RegUnit) const { 1535 assert(RegUnit < 76 && "invalid register unit"); 1536 static const uint8_t RUSetStartTable[] = { 1537 2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,0,0,0,0,0,0,0,0,1,1,1,1,5,5,5,5,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,}; 1538 return &RCSetsTable[RUSetStartTable[RegUnit]]; 1539} 1540 1541extern const MCRegisterDesc LoongArchRegDesc[]; 1542extern const MCPhysReg LoongArchRegDiffLists[]; 1543extern const LaneBitmask LoongArchLaneMaskLists[]; 1544extern const char LoongArchRegStrings[]; 1545extern const char LoongArchRegClassStrings[]; 1546extern const MCPhysReg LoongArchRegUnitRoots[][2]; 1547extern const uint16_t LoongArchSubRegIdxLists[]; 1548extern const MCRegisterInfo::SubRegCoveredBits LoongArchSubRegIdxRanges[]; 1549extern const uint16_t LoongArchRegEncodingTable[]; 1550// LoongArch Dwarf<->LLVM register mappings. 1551extern const MCRegisterInfo::DwarfLLVMRegPair LoongArchDwarfFlavour0Dwarf2L[]; 1552extern const unsigned LoongArchDwarfFlavour0Dwarf2LSize; 1553 1554extern const MCRegisterInfo::DwarfLLVMRegPair LoongArchEHFlavour0Dwarf2L[]; 1555extern const unsigned LoongArchEHFlavour0Dwarf2LSize; 1556 1557extern const MCRegisterInfo::DwarfLLVMRegPair LoongArchDwarfFlavour0L2Dwarf[]; 1558extern const unsigned LoongArchDwarfFlavour0L2DwarfSize; 1559 1560extern const MCRegisterInfo::DwarfLLVMRegPair LoongArchEHFlavour0L2Dwarf[]; 1561extern const unsigned LoongArchEHFlavour0L2DwarfSize; 1562 1563LoongArchGenRegisterInfo:: 1564LoongArchGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour, 1565 unsigned PC, unsigned HwMode) 1566 : TargetRegisterInfo(&LoongArchRegInfoDesc, RegisterClasses, RegisterClasses+6, 1567 SubRegIndexNameTable, SubRegIndexLaneMaskTable, 1568 LaneBitmask(0xFFFFFFFFFFFFFFFE), RegClassInfos, HwMode) { 1569 InitMCRegisterInfo(LoongArchRegDesc, 109, RA, PC, 1570 LoongArchMCRegisterClasses, 6, 1571 LoongArchRegUnitRoots, 1572 76, 1573 LoongArchRegDiffLists, 1574 LoongArchLaneMaskLists, 1575 LoongArchRegStrings, 1576 LoongArchRegClassStrings, 1577 LoongArchSubRegIdxLists, 1578 2, 1579 LoongArchSubRegIdxRanges, 1580 LoongArchRegEncodingTable); 1581 1582 switch (DwarfFlavour) { 1583 default: 1584 llvm_unreachable("Unknown DWARF flavour"); 1585 case 0: 1586 mapDwarfRegsToLLVMRegs(LoongArchDwarfFlavour0Dwarf2L, LoongArchDwarfFlavour0Dwarf2LSize, false); 1587 break; 1588 } 1589 switch (EHFlavour) { 1590 default: 1591 llvm_unreachable("Unknown DWARF flavour"); 1592 case 0: 1593 mapDwarfRegsToLLVMRegs(LoongArchEHFlavour0Dwarf2L, LoongArchEHFlavour0Dwarf2LSize, true); 1594 break; 1595 } 1596 switch (DwarfFlavour) { 1597 default: 1598 llvm_unreachable("Unknown DWARF flavour"); 1599 case 0: 1600 mapLLVMRegsToDwarfRegs(LoongArchDwarfFlavour0L2Dwarf, LoongArchDwarfFlavour0L2DwarfSize, false); 1601 break; 1602 } 1603 switch (EHFlavour) { 1604 default: 1605 llvm_unreachable("Unknown DWARF flavour"); 1606 case 0: 1607 mapLLVMRegsToDwarfRegs(LoongArchEHFlavour0L2Dwarf, LoongArchEHFlavour0L2DwarfSize, true); 1608 break; 1609 } 1610} 1611 1612static const MCPhysReg CSR_ILP32D_LP64D_SaveList[] = { LoongArch::R1, LoongArch::R22, LoongArch::R23, LoongArch::R24, LoongArch::R25, LoongArch::R26, LoongArch::R27, LoongArch::R28, LoongArch::R29, LoongArch::R30, LoongArch::R31, LoongArch::F24_64, LoongArch::F25_64, LoongArch::F26_64, LoongArch::F27_64, LoongArch::F28_64, LoongArch::F29_64, LoongArch::F30_64, LoongArch::F31_64, 0 }; 1613static const uint32_t CSR_ILP32D_LP64D_RegMask[] = { 0xfe000000, 0x00006001, 0x00001ff8, 0x00001fe0, }; 1614static const MCPhysReg CSR_ILP32F_LP64F_SaveList[] = { LoongArch::R1, LoongArch::R22, LoongArch::R23, LoongArch::R24, LoongArch::R25, LoongArch::R26, LoongArch::R27, LoongArch::R28, LoongArch::R29, LoongArch::R30, LoongArch::R31, LoongArch::F24, LoongArch::F25, LoongArch::F26, LoongArch::F27, LoongArch::F28, LoongArch::F29, LoongArch::F30, LoongArch::F31, 0 }; 1615static const uint32_t CSR_ILP32F_LP64F_RegMask[] = { 0xfe000000, 0x00006001, 0x00001ff8, 0x00000000, }; 1616static const MCPhysReg CSR_ILP32S_LP64S_SaveList[] = { LoongArch::R1, LoongArch::R22, LoongArch::R23, LoongArch::R24, LoongArch::R25, LoongArch::R26, LoongArch::R27, LoongArch::R28, LoongArch::R29, LoongArch::R30, LoongArch::R31, 0 }; 1617static const uint32_t CSR_ILP32S_LP64S_RegMask[] = { 0x00000000, 0x00006000, 0x00001ff8, 0x00000000, }; 1618static const MCPhysReg CSR_NoRegs_SaveList[] = { 0 }; 1619static const uint32_t CSR_NoRegs_RegMask[] = { 0x00000000, 0x00002000, 0x00000000, 0x00000000, }; 1620 1621 1622ArrayRef<const uint32_t *> LoongArchGenRegisterInfo::getRegMasks() const { 1623 static const uint32_t *const Masks[] = { 1624 CSR_ILP32D_LP64D_RegMask, 1625 CSR_ILP32F_LP64F_RegMask, 1626 CSR_ILP32S_LP64S_RegMask, 1627 CSR_NoRegs_RegMask, 1628 }; 1629 return ArrayRef(Masks); 1630} 1631 1632bool LoongArchGenRegisterInfo:: 1633isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const { 1634 return 1635 false; 1636} 1637 1638bool LoongArchGenRegisterInfo:: 1639isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const { 1640 return 1641 false; 1642} 1643 1644bool LoongArchGenRegisterInfo:: 1645isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const { 1646 return 1647 false; 1648} 1649 1650bool LoongArchGenRegisterInfo:: 1651isConstantPhysReg(MCRegister PhysReg) const { 1652 return 1653 PhysReg == LoongArch::R0 || 1654 false; 1655} 1656 1657ArrayRef<const char *> LoongArchGenRegisterInfo::getRegMaskNames() const { 1658 static const char *Names[] = { 1659 "CSR_ILP32D_LP64D", 1660 "CSR_ILP32F_LP64F", 1661 "CSR_ILP32S_LP64S", 1662 "CSR_NoRegs", 1663 }; 1664 return ArrayRef(Names); 1665} 1666 1667const LoongArchFrameLowering * 1668LoongArchGenRegisterInfo::getFrameLowering(const MachineFunction &MF) { 1669 return static_cast<const LoongArchFrameLowering *>( 1670 MF.getSubtarget().getFrameLowering()); 1671} 1672 1673} // end namespace llvm 1674 1675#endif // GET_REGINFO_TARGET_DESC 1676 1677