1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2|* *| 3|* Subtarget Enumeration Source Fragment *| 4|* *| 5|* Automatically generated file, do not edit! *| 6|* *| 7\*===----------------------------------------------------------------------===*/ 8 9 10#ifdef GET_SUBTARGETINFO_ENUM 11#undef GET_SUBTARGETINFO_ENUM 12 13namespace llvm { 14namespace LoongArch { 15enum { 16 Feature32Bit = 0, 17 Feature64Bit = 1, 18 FeatureBasicD = 2, 19 FeatureBasicF = 3, 20 FeatureExtLASX = 4, 21 FeatureExtLBT = 5, 22 FeatureExtLSX = 6, 23 FeatureExtLVZ = 7, 24 LaGlobalWithAbs = 8, 25 LaGlobalWithPcrel = 9, 26 LaLocalWithAbs = 10, 27 NumSubtargetFeatures = 11 28}; 29} // end namespace LoongArch 30} // end namespace llvm 31 32#endif // GET_SUBTARGETINFO_ENUM 33 34 35#ifdef GET_SUBTARGETINFO_MACRO 36GET_SUBTARGETINFO_MACRO(HasLA32, false, hasLA32) 37GET_SUBTARGETINFO_MACRO(HasLA64, false, hasLA64) 38GET_SUBTARGETINFO_MACRO(HasBasicD, false, hasBasicD) 39GET_SUBTARGETINFO_MACRO(HasBasicF, false, hasBasicF) 40GET_SUBTARGETINFO_MACRO(HasLaGlobalWithAbs, false, hasLaGlobalWithAbs) 41GET_SUBTARGETINFO_MACRO(HasLaGlobalWithPcrel, false, hasLaGlobalWithPcrel) 42GET_SUBTARGETINFO_MACRO(HasLaLocalWithAbs, false, hasLaLocalWithAbs) 43GET_SUBTARGETINFO_MACRO(HasExtLASX, false, hasExtLASX) 44GET_SUBTARGETINFO_MACRO(HasExtLBT, false, hasExtLBT) 45GET_SUBTARGETINFO_MACRO(HasExtLSX, false, hasExtLSX) 46GET_SUBTARGETINFO_MACRO(HasExtLVZ, false, hasExtLVZ) 47#undef GET_SUBTARGETINFO_MACRO 48#endif // GET_SUBTARGETINFO_MACRO 49 50 51#ifdef GET_SUBTARGETINFO_MC_DESC 52#undef GET_SUBTARGETINFO_MC_DESC 53 54namespace llvm { 55// Sorted (by key) array of values for CPU features. 56extern const llvm::SubtargetFeatureKV LoongArchFeatureKV[] = { 57 { "32bit", "LA32 Basic Integer and Privilege Instruction Set", LoongArch::Feature32Bit, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, 58 { "64bit", "LA64 Basic Integer and Privilege Instruction Set", LoongArch::Feature64Bit, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, 59 { "d", "'D' (Double-Precision Floating-Point)", LoongArch::FeatureBasicD, { { { 0x8ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, 60 { "f", "'F' (Single-Precision Floating-Point)", LoongArch::FeatureBasicF, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, 61 { "la-global-with-abs", "Expand la.global as la.abs", LoongArch::LaGlobalWithAbs, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, 62 { "la-global-with-pcrel", "Expand la.global as la.pcrel", LoongArch::LaGlobalWithPcrel, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, 63 { "la-local-with-abs", "Expand la.local as la.abs", LoongArch::LaLocalWithAbs, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, 64 { "lasx", "'LASX' (Loongson Advanced SIMD Extension)", LoongArch::FeatureExtLASX, { { { 0x40ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, 65 { "lbt", "'LBT' (Loongson Binary Translation Extension)", LoongArch::FeatureExtLBT, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, 66 { "lsx", "'LSX' (Loongson SIMD Extension)", LoongArch::FeatureExtLSX, { { { 0x4ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, 67 { "lvz", "'LVZ' (Loongson Virtualization Extension)", LoongArch::FeatureExtLVZ, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, 68}; 69 70#ifdef DBGFIELD 71#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro" 72#endif 73#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) 74#define DBGFIELD(x) x, 75#else 76#define DBGFIELD(x) 77#endif 78 79// =============================================================== 80// Data tables for the new per-operand machine model. 81 82// {ProcResourceIdx, Cycles} 83extern const llvm::MCWriteProcResEntry LoongArchWriteProcResTable[] = { 84 { 0, 0}, // Invalid 85}; // LoongArchWriteProcResTable 86 87// {Cycles, WriteResourceID} 88extern const llvm::MCWriteLatencyEntry LoongArchWriteLatencyTable[] = { 89 { 0, 0}, // Invalid 90}; // LoongArchWriteLatencyTable 91 92// {UseIdx, WriteResourceID, Cycles} 93extern const llvm::MCReadAdvanceEntry LoongArchReadAdvanceTable[] = { 94 {0, 0, 0}, // Invalid 95}; // LoongArchReadAdvanceTable 96 97#undef DBGFIELD 98 99static const llvm::MCSchedModel NoSchedModel = { 100 MCSchedModel::DefaultIssueWidth, 101 MCSchedModel::DefaultMicroOpBufferSize, 102 MCSchedModel::DefaultLoopMicroOpBufferSize, 103 MCSchedModel::DefaultLoadLatency, 104 MCSchedModel::DefaultHighLatency, 105 MCSchedModel::DefaultMispredictPenalty, 106 false, // PostRAScheduler 107 false, // CompleteModel 108 0, // Processor ID 109 nullptr, nullptr, 0, 0, // No instruction-level machine model. 110 nullptr, // No Itinerary 111 nullptr // No extra processor descriptor 112}; 113 114// Sorted (by key) array of values for CPU subtype. 115extern const llvm::SubtargetSubTypeKV LoongArchSubTypeKV[] = { 116 { "generic", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel }, 117 { "generic-la32", { { { 0x1ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel }, 118 { "generic-la64", { { { 0x2ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel }, 119 { "la464", { { { 0xb2ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel }, 120}; 121 122namespace LoongArch_MC { 123unsigned resolveVariantSchedClassImpl(unsigned SchedClass, 124 const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) { 125 // Don't know how to resolve this scheduling class. 126 return 0; 127} 128} // end namespace LoongArch_MC 129 130struct LoongArchGenMCSubtargetInfo : public MCSubtargetInfo { 131 LoongArchGenMCSubtargetInfo(const Triple &TT, 132 StringRef CPU, StringRef TuneCPU, StringRef FS, 133 ArrayRef<SubtargetFeatureKV> PF, 134 ArrayRef<SubtargetSubTypeKV> PD, 135 const MCWriteProcResEntry *WPR, 136 const MCWriteLatencyEntry *WL, 137 const MCReadAdvanceEntry *RA, const InstrStage *IS, 138 const unsigned *OC, const unsigned *FP) : 139 MCSubtargetInfo(TT, CPU, TuneCPU, FS, PF, PD, 140 WPR, WL, RA, IS, OC, FP) { } 141 142 unsigned resolveVariantSchedClass(unsigned SchedClass, 143 const MCInst *MI, const MCInstrInfo *MCII, 144 unsigned CPUID) const override { 145 return LoongArch_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID); 146 } 147 unsigned getHwMode() const override; 148}; 149unsigned LoongArchGenMCSubtargetInfo::getHwMode() const { 150 if (checkFeatures("+64bit")) return 1; 151 return 0; 152} 153 154static inline MCSubtargetInfo *createLoongArchMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) { 155 return new LoongArchGenMCSubtargetInfo(TT, CPU, TuneCPU, FS, LoongArchFeatureKV, LoongArchSubTypeKV, 156 LoongArchWriteProcResTable, LoongArchWriteLatencyTable, LoongArchReadAdvanceTable, 157 nullptr, nullptr, nullptr); 158} 159 160} // end namespace llvm 161 162#endif // GET_SUBTARGETINFO_MC_DESC 163 164 165#ifdef GET_SUBTARGETINFO_TARGET_DESC 166#undef GET_SUBTARGETINFO_TARGET_DESC 167 168#include "llvm/Support/Debug.h" 169#include "llvm/Support/raw_ostream.h" 170 171// ParseSubtargetFeatures - Parses features string setting specified 172// subtarget options. 173void llvm::LoongArchSubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) { 174 LLVM_DEBUG(dbgs() << "\nFeatures:" << FS); 175 LLVM_DEBUG(dbgs() << "\nCPU:" << CPU); 176 LLVM_DEBUG(dbgs() << "\nTuneCPU:" << TuneCPU << "\n\n"); 177 InitMCProcessorInfo(CPU, TuneCPU, FS); 178 const FeatureBitset &Bits = getFeatureBits(); 179 if (Bits[LoongArch::Feature32Bit]) HasLA32 = true; 180 if (Bits[LoongArch::Feature64Bit]) HasLA64 = true; 181 if (Bits[LoongArch::FeatureBasicD]) HasBasicD = true; 182 if (Bits[LoongArch::FeatureBasicF]) HasBasicF = true; 183 if (Bits[LoongArch::FeatureExtLASX]) HasExtLASX = true; 184 if (Bits[LoongArch::FeatureExtLBT]) HasExtLBT = true; 185 if (Bits[LoongArch::FeatureExtLSX]) HasExtLSX = true; 186 if (Bits[LoongArch::FeatureExtLVZ]) HasExtLVZ = true; 187 if (Bits[LoongArch::LaGlobalWithAbs]) HasLaGlobalWithAbs = true; 188 if (Bits[LoongArch::LaGlobalWithPcrel]) HasLaGlobalWithPcrel = true; 189 if (Bits[LoongArch::LaLocalWithAbs]) HasLaLocalWithAbs = true; 190} 191#endif // GET_SUBTARGETINFO_TARGET_DESC 192 193 194#ifdef GET_SUBTARGETINFO_HEADER 195#undef GET_SUBTARGETINFO_HEADER 196 197namespace llvm { 198class DFAPacketizer; 199namespace LoongArch_MC { 200unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID); 201} // end namespace LoongArch_MC 202 203struct LoongArchGenSubtargetInfo : public TargetSubtargetInfo { 204 explicit LoongArchGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS); 205public: 206 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override; 207 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const override; 208 DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const; 209 unsigned getHwMode() const override; 210}; 211} // end namespace llvm 212 213#endif // GET_SUBTARGETINFO_HEADER 214 215 216#ifdef GET_SUBTARGETINFO_CTOR 217#undef GET_SUBTARGETINFO_CTOR 218 219#include "llvm/CodeGen/TargetSchedule.h" 220 221namespace llvm { 222extern const llvm::SubtargetFeatureKV LoongArchFeatureKV[]; 223extern const llvm::SubtargetSubTypeKV LoongArchSubTypeKV[]; 224extern const llvm::MCWriteProcResEntry LoongArchWriteProcResTable[]; 225extern const llvm::MCWriteLatencyEntry LoongArchWriteLatencyTable[]; 226extern const llvm::MCReadAdvanceEntry LoongArchReadAdvanceTable[]; 227LoongArchGenSubtargetInfo::LoongArchGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) 228 : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, ArrayRef(LoongArchFeatureKV, 11), ArrayRef(LoongArchSubTypeKV, 4), 229 LoongArchWriteProcResTable, LoongArchWriteLatencyTable, LoongArchReadAdvanceTable, 230 nullptr, nullptr, nullptr) {} 231 232unsigned LoongArchGenSubtargetInfo 233::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const { 234 report_fatal_error("Expected a variant SchedClass"); 235} // LoongArchGenSubtargetInfo::resolveSchedClass 236 237unsigned LoongArchGenSubtargetInfo 238::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const { 239 return LoongArch_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID); 240} // LoongArchGenSubtargetInfo::resolveVariantSchedClass 241 242unsigned LoongArchGenSubtargetInfo::getHwMode() const { 243 if (checkFeatures("+64bit")) return 1; 244 return 0; 245} 246} // end namespace llvm 247 248#endif // GET_SUBTARGETINFO_CTOR 249 250 251#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS 252#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS 253 254#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS 255 256 257#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS 258#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS 259 260#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS 261 262