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1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|*                                                                            *|
3|* Global Instruction Selector for the Mips target                            *|
4|*                                                                            *|
5|* Automatically generated file, do not edit!                                 *|
6|*                                                                            *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_GLOBALISEL_PREDICATE_BITSET
10const unsigned MAX_SUBTARGET_PREDICATES = 44;
11using PredicateBitset = llvm::PredicateBitsetImpl<MAX_SUBTARGET_PREDICATES>;
12#endif // ifdef GET_GLOBALISEL_PREDICATE_BITSET
13
14#ifdef GET_GLOBALISEL_TEMPORARIES_DECL
15  mutable MatcherState State;
16  typedef ComplexRendererFns(MipsInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const;
17  typedef void(MipsInstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr &, int) const;
18  const ISelInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ISelInfo;
19  static MipsInstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[];
20  static MipsInstructionSelector::CustomRendererFn CustomRenderers[];
21  bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override;
22  bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override;
23  bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override;
24  const int64_t *getMatchTable() const override;
25  bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI, const std::array<const MachineOperand *, 3> &Operands) const override;
26#endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL
27
28#ifdef GET_GLOBALISEL_TEMPORARIES_INIT
29, State(0),
30ISelInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers)
31#endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT
32
33#ifdef GET_GLOBALISEL_IMPL
34// Bits for subtarget features that participate in instruction matching.
35enum SubtargetFeatureBits : uint8_t {
36  Feature_HasMips2Bit = 7,
37  Feature_HasMips3Bit = 17,
38  Feature_HasMips4_32Bit = 27,
39  Feature_NotMips4_32Bit = 28,
40  Feature_HasMips4_32r2Bit = 18,
41  Feature_HasMips32Bit = 3,
42  Feature_HasMips32r2Bit = 6,
43  Feature_HasMips32r6Bit = 29,
44  Feature_NotMips32r6Bit = 4,
45  Feature_IsGP64bitBit = 22,
46  Feature_IsPTR64bitBit = 24,
47  Feature_HasMips64Bit = 25,
48  Feature_HasMips64r2Bit = 23,
49  Feature_HasMips64r6Bit = 30,
50  Feature_NotMips64r6Bit = 5,
51  Feature_InMips16ModeBit = 31,
52  Feature_NotInMips16ModeBit = 0,
53  Feature_HasCnMipsBit = 26,
54  Feature_NotCnMipsBit = 8,
55  Feature_IsSym32Bit = 38,
56  Feature_IsSym64Bit = 39,
57  Feature_IsN64Bit = 40,
58  Feature_RelocNotPICBit = 9,
59  Feature_RelocPICBit = 37,
60  Feature_NoNaNsFPMathBit = 21,
61  Feature_UseAbsBit = 14,
62  Feature_HasStdEncBit = 1,
63  Feature_NotDSPBit = 11,
64  Feature_InMicroMipsBit = 35,
65  Feature_NotInMicroMipsBit = 2,
66  Feature_IsLEBit = 42,
67  Feature_IsBEBit = 43,
68  Feature_IsNotNaClBit = 19,
69  Feature_HasEVABit = 36,
70  Feature_HasMSABit = 34,
71  Feature_HasMadd4Bit = 20,
72  Feature_UseIndirectJumpsHazardBit = 12,
73  Feature_NoIndirectJumpGuardsBit = 10,
74  Feature_AllowFPOpFusionBit = 41,
75  Feature_IsFP64bitBit = 16,
76  Feature_NotFP64bitBit = 15,
77  Feature_IsNotSoftFloatBit = 13,
78  Feature_HasDSPBit = 32,
79  Feature_HasDSPR2Bit = 33,
80};
81
82PredicateBitset MipsInstructionSelector::
83computeAvailableModuleFeatures(const MipsSubtarget *Subtarget) const {
84  PredicateBitset Features;
85  if (Subtarget->hasMips2())
86    Features.set(Feature_HasMips2Bit);
87  if (Subtarget->hasMips3())
88    Features.set(Feature_HasMips3Bit);
89  if (Subtarget->hasMips4_32())
90    Features.set(Feature_HasMips4_32Bit);
91  if (!Subtarget->hasMips4_32())
92    Features.set(Feature_NotMips4_32Bit);
93  if (Subtarget->hasMips4_32r2())
94    Features.set(Feature_HasMips4_32r2Bit);
95  if (Subtarget->hasMips32())
96    Features.set(Feature_HasMips32Bit);
97  if (Subtarget->hasMips32r2())
98    Features.set(Feature_HasMips32r2Bit);
99  if (Subtarget->hasMips32r6())
100    Features.set(Feature_HasMips32r6Bit);
101  if (!Subtarget->hasMips32r6())
102    Features.set(Feature_NotMips32r6Bit);
103  if (Subtarget->isGP64bit())
104    Features.set(Feature_IsGP64bitBit);
105  if (Subtarget->isABI_N64())
106    Features.set(Feature_IsPTR64bitBit);
107  if (Subtarget->hasMips64())
108    Features.set(Feature_HasMips64Bit);
109  if (Subtarget->hasMips64r2())
110    Features.set(Feature_HasMips64r2Bit);
111  if (Subtarget->hasMips64r6())
112    Features.set(Feature_HasMips64r6Bit);
113  if (!Subtarget->hasMips64r6())
114    Features.set(Feature_NotMips64r6Bit);
115  if (Subtarget->inMips16Mode())
116    Features.set(Feature_InMips16ModeBit);
117  if (!Subtarget->inMips16Mode())
118    Features.set(Feature_NotInMips16ModeBit);
119  if (Subtarget->hasCnMips())
120    Features.set(Feature_HasCnMipsBit);
121  if (!Subtarget->hasCnMips())
122    Features.set(Feature_NotCnMipsBit);
123  if (Subtarget->hasSym32())
124    Features.set(Feature_IsSym32Bit);
125  if (!Subtarget->hasSym32())
126    Features.set(Feature_IsSym64Bit);
127  if (Subtarget->isABI_N64())
128    Features.set(Feature_IsN64Bit);
129  if (!TM.isPositionIndependent())
130    Features.set(Feature_RelocNotPICBit);
131  if (TM.isPositionIndependent())
132    Features.set(Feature_RelocPICBit);
133  if (TM.Options.NoNaNsFPMath)
134    Features.set(Feature_NoNaNsFPMathBit);
135  if (Subtarget->inAbs2008Mode() ||TM.Options.NoNaNsFPMath)
136    Features.set(Feature_UseAbsBit);
137  if (Subtarget->hasStandardEncoding())
138    Features.set(Feature_HasStdEncBit);
139  if (!Subtarget->hasDSP())
140    Features.set(Feature_NotDSPBit);
141  if (Subtarget->inMicroMipsMode())
142    Features.set(Feature_InMicroMipsBit);
143  if (!Subtarget->inMicroMipsMode())
144    Features.set(Feature_NotInMicroMipsBit);
145  if (Subtarget->isLittle())
146    Features.set(Feature_IsLEBit);
147  if (!Subtarget->isLittle())
148    Features.set(Feature_IsBEBit);
149  if (!Subtarget->isTargetNaCl())
150    Features.set(Feature_IsNotNaClBit);
151  if (Subtarget->hasEVA())
152    Features.set(Feature_HasEVABit);
153  if (Subtarget->hasMSA())
154    Features.set(Feature_HasMSABit);
155  if (!Subtarget->disableMadd4())
156    Features.set(Feature_HasMadd4Bit);
157  if (Subtarget->useIndirectJumpsHazard())
158    Features.set(Feature_UseIndirectJumpsHazardBit);
159  if (!Subtarget->useIndirectJumpsHazard())
160    Features.set(Feature_NoIndirectJumpGuardsBit);
161  if (TM.Options.AllowFPOpFusion == FPOpFusion::Fast)
162    Features.set(Feature_AllowFPOpFusionBit);
163  if (Subtarget->isFP64bit())
164    Features.set(Feature_IsFP64bitBit);
165  if (!Subtarget->isFP64bit())
166    Features.set(Feature_NotFP64bitBit);
167  if (!Subtarget->useSoftFloat())
168    Features.set(Feature_IsNotSoftFloatBit);
169  if (Subtarget->hasDSP())
170    Features.set(Feature_HasDSPBit);
171  if (Subtarget->hasDSPR2())
172    Features.set(Feature_HasDSPR2Bit);
173  return Features;
174}
175
176void MipsInstructionSelector::setupGeneratedPerFunctionState(MachineFunction &MF) {
177  AvailableFunctionFeatures = computeAvailableFunctionFeatures((const MipsSubtarget *)&MF.getSubtarget(), &MF);
178}
179PredicateBitset MipsInstructionSelector::
180computeAvailableFunctionFeatures(const MipsSubtarget *Subtarget, const MachineFunction *MF) const {
181  PredicateBitset Features;
182  return Features;
183}
184
185// LLT Objects.
186enum {
187  GILLT_s16,
188  GILLT_s32,
189  GILLT_s64,
190  GILLT_v2s16,
191  GILLT_v2s64,
192  GILLT_v4s8,
193  GILLT_v4s32,
194  GILLT_v8s16,
195  GILLT_v16s8,
196};
197const static size_t NumTypeObjects = 9;
198const static LLT TypeObjects[] = {
199  LLT::scalar(16),
200  LLT::scalar(32),
201  LLT::scalar(64),
202  LLT::vector(ElementCount::getFixed(2), 16),
203  LLT::vector(ElementCount::getFixed(2), 64),
204  LLT::vector(ElementCount::getFixed(4), 8),
205  LLT::vector(ElementCount::getFixed(4), 32),
206  LLT::vector(ElementCount::getFixed(8), 16),
207  LLT::vector(ElementCount::getFixed(16), 8),
208};
209
210// Feature bitsets.
211enum {
212  GIFBS_Invalid,
213  GIFBS_HasCnMips,
214  GIFBS_HasDSP,
215  GIFBS_HasDSPR2,
216  GIFBS_HasMSA,
217  GIFBS_InMicroMips,
218  GIFBS_InMips16Mode,
219  GIFBS_IsFP64bit,
220  GIFBS_NotFP64bit,
221  GIFBS_HasDSP_InMicroMips,
222  GIFBS_HasDSP_NotInMicroMips,
223  GIFBS_HasDSPR2_InMicroMips,
224  GIFBS_HasMSA_HasStdEnc,
225  GIFBS_HasMSA_IsBE,
226  GIFBS_HasMSA_IsLE,
227  GIFBS_HasMips32r6_HasStdEnc,
228  GIFBS_HasMips32r6_InMicroMips,
229  GIFBS_HasMips64r2_HasStdEnc,
230  GIFBS_HasMips64r6_HasStdEnc,
231  GIFBS_HasStdEnc_IsNotSoftFloat,
232  GIFBS_HasStdEnc_NotInMicroMips,
233  GIFBS_HasStdEnc_NotMips4_32,
234  GIFBS_InMicroMips_IsFP64bit,
235  GIFBS_InMicroMips_IsNotSoftFloat,
236  GIFBS_InMicroMips_NotFP64bit,
237  GIFBS_InMicroMips_NotMips32r6,
238  GIFBS_IsGP64bit_NotInMips16Mode,
239  GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc,
240  GIFBS_HasMSA_HasMips64_HasStdEnc,
241  GIFBS_HasMips3_HasStdEnc_IsGP64bit,
242  GIFBS_HasMips3_HasStdEnc_NotInMicroMips,
243  GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips,
244  GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
245  GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
246  GIFBS_HasMips64r2_HasStdEnc_NotInMicroMips,
247  GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
248  GIFBS_HasStdEnc_IsFP64bit_NotInMicroMips,
249  GIFBS_HasStdEnc_IsFP64bit_NotMips4_32,
250  GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
251  GIFBS_HasStdEnc_NotFP64bit_NotInMicroMips,
252  GIFBS_HasStdEnc_NotFP64bit_NotMips4_32,
253  GIFBS_HasStdEnc_NotInMicroMips_RelocNotPIC,
254  GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat,
255  GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit,
256  GIFBS_InMicroMips_IsNotSoftFloat_UseAbs,
257  GIFBS_InMicroMips_NotFP64bit_NotMips32r6,
258  GIFBS_InMicroMips_NotMips32r6_RelocNotPIC,
259  GIFBS_InMicroMips_NotMips32r6_RelocPIC,
260  GIFBS_IsFP64bit_IsNotSoftFloat_NotInMips16Mode,
261  GIFBS_IsNotSoftFloat_NotFP64bit_NotInMips16Mode,
262  GIFBS_HasMips2_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
263  GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips,
264  GIFBS_HasMips3_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
265  GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
266  GIFBS_HasMips4_32_HasStdEnc_NotMips32r6_NotMips64r6,
267  GIFBS_HasMips64r2_HasStdEnc_IsGP64bit_NotInMicroMips,
268  GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips,
269  GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips,
270  GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips_UseAbs,
271  GIFBS_HasMips2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips,
272  GIFBS_HasMips2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips,
273  GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
274  GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
275  GIFBS_HasMips64_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips64r6,
276  GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_UseAbs,
277  GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_UseAbs,
278  GIFBS_HasMadd4_InMicroMips_InMicroMips_NoNaNsFPMath_NotMips32r6_NotMips32r6,
279  GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
280  GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
281  GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
282  GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6,
283  GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6,
284  GIFBS_HasMadd4_InMicroMips_InMicroMips_NoNaNsFPMath_NotFP64bit_NotMips32r6_NotMips32r6,
285  GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6,
286  GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6,
287  GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
288  GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
289};
290const static PredicateBitset FeatureBitsets[] {
291  {}, // GIFBS_Invalid
292  {Feature_HasCnMipsBit, },
293  {Feature_HasDSPBit, },
294  {Feature_HasDSPR2Bit, },
295  {Feature_HasMSABit, },
296  {Feature_InMicroMipsBit, },
297  {Feature_InMips16ModeBit, },
298  {Feature_IsFP64bitBit, },
299  {Feature_NotFP64bitBit, },
300  {Feature_HasDSPBit, Feature_InMicroMipsBit, },
301  {Feature_HasDSPBit, Feature_NotInMicroMipsBit, },
302  {Feature_HasDSPR2Bit, Feature_InMicroMipsBit, },
303  {Feature_HasMSABit, Feature_HasStdEncBit, },
304  {Feature_HasMSABit, Feature_IsBEBit, },
305  {Feature_HasMSABit, Feature_IsLEBit, },
306  {Feature_HasMips32r6Bit, Feature_HasStdEncBit, },
307  {Feature_HasMips32r6Bit, Feature_InMicroMipsBit, },
308  {Feature_HasMips64r2Bit, Feature_HasStdEncBit, },
309  {Feature_HasMips64r6Bit, Feature_HasStdEncBit, },
310  {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, },
311  {Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
312  {Feature_HasStdEncBit, Feature_NotMips4_32Bit, },
313  {Feature_InMicroMipsBit, Feature_IsFP64bitBit, },
314  {Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, },
315  {Feature_InMicroMipsBit, Feature_NotFP64bitBit, },
316  {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, },
317  {Feature_IsGP64bitBit, Feature_NotInMips16ModeBit, },
318  {Feature_AllowFPOpFusionBit, Feature_HasMSABit, Feature_HasStdEncBit, },
319  {Feature_HasMSABit, Feature_HasMips64Bit, Feature_HasStdEncBit, },
320  {Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, },
321  {Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
322  {Feature_HasMips32r2Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
323  {Feature_HasMips32r6Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
324  {Feature_HasMips32r6Bit, Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, },
325  {Feature_HasMips64r2Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
326  {Feature_HasMips64r6Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
327  {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotInMicroMipsBit, },
328  {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotMips4_32Bit, },
329  {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
330  {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, },
331  {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotMips4_32Bit, },
332  {Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_RelocNotPICBit, },
333  {Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, },
334  {Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, },
335  {Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, Feature_UseAbsBit, },
336  {Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, },
337  {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_RelocNotPICBit, },
338  {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_RelocPICBit, },
339  {Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMips16ModeBit, },
340  {Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMips16ModeBit, },
341  {Feature_HasMips2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
342  {Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, },
343  {Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
344  {Feature_HasMips32r6Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
345  {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
346  {Feature_HasMips64r2Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, },
347  {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
348  {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, },
349  {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_UseAbsBit, },
350  {Feature_HasMips2Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
351  {Feature_HasMips2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, },
352  {Feature_HasMips32Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
353  {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
354  {Feature_HasMips64Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips64r6Bit, },
355  {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_UseAbsBit, },
356  {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_UseAbsBit, },
357  {Feature_HasMadd4Bit, Feature_InMicroMipsBit, Feature_InMicroMipsBit, Feature_NoNaNsFPMathBit, Feature_NotMips32r6Bit, Feature_NotMips32r6Bit, },
358  {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
359  {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
360  {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
361  {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
362  {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_NoNaNsFPMathBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
363  {Feature_HasMadd4Bit, Feature_InMicroMipsBit, Feature_InMicroMipsBit, Feature_NoNaNsFPMathBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, Feature_NotMips32r6Bit, },
364  {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
365  {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NoNaNsFPMathBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
366  {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
367  {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_NoNaNsFPMathBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
368};
369
370// ComplexPattern predicates.
371enum {
372  GICP_Invalid,
373};
374// See constructor for table contents
375
376// PatFrag predicates.
377enum {
378  GIPFP_I64_Predicate_immLi16 = GIPFP_I64_Invalid + 1,
379  GIPFP_I64_Predicate_immSExt10,
380  GIPFP_I64_Predicate_immSExt6,
381  GIPFP_I64_Predicate_immSExtAddiur2,
382  GIPFP_I64_Predicate_immSExtAddius5,
383  GIPFP_I64_Predicate_immZExt1,
384  GIPFP_I64_Predicate_immZExt10,
385  GIPFP_I64_Predicate_immZExt1Ptr,
386  GIPFP_I64_Predicate_immZExt2,
387  GIPFP_I64_Predicate_immZExt2Lsa,
388  GIPFP_I64_Predicate_immZExt2Ptr,
389  GIPFP_I64_Predicate_immZExt2Shift,
390  GIPFP_I64_Predicate_immZExt3,
391  GIPFP_I64_Predicate_immZExt3Ptr,
392  GIPFP_I64_Predicate_immZExt4,
393  GIPFP_I64_Predicate_immZExt4Ptr,
394  GIPFP_I64_Predicate_immZExt5,
395  GIPFP_I64_Predicate_immZExt5_64,
396  GIPFP_I64_Predicate_immZExt6,
397  GIPFP_I64_Predicate_immZExt8,
398  GIPFP_I64_Predicate_immZExtAndi16,
399  GIPFP_I64_Predicate_immi32Cst15,
400  GIPFP_I64_Predicate_immi32Cst31,
401  GIPFP_I64_Predicate_immi32Cst7,
402  GIPFP_I64_Predicate_timmSExt6,
403  GIPFP_I64_Predicate_timmZExt1,
404  GIPFP_I64_Predicate_timmZExt10,
405  GIPFP_I64_Predicate_timmZExt1Ptr,
406  GIPFP_I64_Predicate_timmZExt2,
407  GIPFP_I64_Predicate_timmZExt2Ptr,
408  GIPFP_I64_Predicate_timmZExt3,
409  GIPFP_I64_Predicate_timmZExt3Ptr,
410  GIPFP_I64_Predicate_timmZExt4,
411  GIPFP_I64_Predicate_timmZExt4Ptr,
412  GIPFP_I64_Predicate_timmZExt5,
413  GIPFP_I64_Predicate_timmZExt6,
414  GIPFP_I64_Predicate_timmZExt8,
415};
416bool MipsInstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const {
417  switch (PredicateID) {
418  case GIPFP_I64_Predicate_immLi16: {
419    return Imm >= -1 && Imm <= 126;
420    llvm_unreachable("ImmediateCode should have returned");
421    return false;
422  }
423  case GIPFP_I64_Predicate_immSExt10: {
424    return isInt<10>(Imm);
425    llvm_unreachable("ImmediateCode should have returned");
426    return false;
427  }
428  case GIPFP_I64_Predicate_immSExt6: {
429    return isInt<6>(Imm);
430    llvm_unreachable("ImmediateCode should have returned");
431    return false;
432  }
433  case GIPFP_I64_Predicate_immSExtAddiur2: {
434    return Imm == 1 || Imm == -1 ||
435                                           ((Imm % 4 == 0) &&
436                                            Imm < 28 && Imm > 0);
437    llvm_unreachable("ImmediateCode should have returned");
438    return false;
439  }
440  case GIPFP_I64_Predicate_immSExtAddius5: {
441    return Imm >= -8 && Imm <= 7;
442    llvm_unreachable("ImmediateCode should have returned");
443    return false;
444  }
445  case GIPFP_I64_Predicate_immZExt1: {
446    return isUInt<1>(Imm);
447    llvm_unreachable("ImmediateCode should have returned");
448    return false;
449  }
450  case GIPFP_I64_Predicate_immZExt10: {
451    return isUInt<10>(Imm);
452    llvm_unreachable("ImmediateCode should have returned");
453    return false;
454  }
455  case GIPFP_I64_Predicate_immZExt1Ptr: {
456    return isUInt<1>(Imm);
457    llvm_unreachable("ImmediateCode should have returned");
458    return false;
459  }
460  case GIPFP_I64_Predicate_immZExt2: {
461    return isUInt<2>(Imm);
462    llvm_unreachable("ImmediateCode should have returned");
463    return false;
464  }
465  case GIPFP_I64_Predicate_immZExt2Lsa: {
466    return isUInt<2>(Imm - 1);
467    llvm_unreachable("ImmediateCode should have returned");
468    return false;
469  }
470  case GIPFP_I64_Predicate_immZExt2Ptr: {
471    return isUInt<2>(Imm);
472    llvm_unreachable("ImmediateCode should have returned");
473    return false;
474  }
475  case GIPFP_I64_Predicate_immZExt2Shift: {
476    return Imm >= 1 && Imm <= 8;
477    llvm_unreachable("ImmediateCode should have returned");
478    return false;
479  }
480  case GIPFP_I64_Predicate_immZExt3: {
481    return isUInt<3>(Imm);
482    llvm_unreachable("ImmediateCode should have returned");
483    return false;
484  }
485  case GIPFP_I64_Predicate_immZExt3Ptr: {
486    return isUInt<3>(Imm);
487    llvm_unreachable("ImmediateCode should have returned");
488    return false;
489  }
490  case GIPFP_I64_Predicate_immZExt4: {
491    return isUInt<4>(Imm);
492    llvm_unreachable("ImmediateCode should have returned");
493    return false;
494  }
495  case GIPFP_I64_Predicate_immZExt4Ptr: {
496    return isUInt<4>(Imm);
497    llvm_unreachable("ImmediateCode should have returned");
498    return false;
499  }
500  case GIPFP_I64_Predicate_immZExt5: {
501    return Imm == (Imm & 0x1f);
502    llvm_unreachable("ImmediateCode should have returned");
503    return false;
504  }
505  case GIPFP_I64_Predicate_immZExt5_64: {
506     return Imm == (Imm & 0x1f);
507    llvm_unreachable("ImmediateCode should have returned");
508    return false;
509  }
510  case GIPFP_I64_Predicate_immZExt6: {
511    return Imm == (Imm & 0x3f);
512    llvm_unreachable("ImmediateCode should have returned");
513    return false;
514  }
515  case GIPFP_I64_Predicate_immZExt8: {
516    return isUInt<8>(Imm);
517    llvm_unreachable("ImmediateCode should have returned");
518    return false;
519  }
520  case GIPFP_I64_Predicate_immZExtAndi16: {
521    return (Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 ||
522            Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 ||
523            Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535 );
524    llvm_unreachable("ImmediateCode should have returned");
525    return false;
526  }
527  case GIPFP_I64_Predicate_immi32Cst15: {
528    return isUInt<32>(Imm) && Imm == 15;
529    llvm_unreachable("ImmediateCode should have returned");
530    return false;
531  }
532  case GIPFP_I64_Predicate_immi32Cst31: {
533    return isUInt<32>(Imm) && Imm == 31;
534    llvm_unreachable("ImmediateCode should have returned");
535    return false;
536  }
537  case GIPFP_I64_Predicate_immi32Cst7: {
538    return isUInt<32>(Imm) && Imm == 7;
539    llvm_unreachable("ImmediateCode should have returned");
540    return false;
541  }
542  case GIPFP_I64_Predicate_timmSExt6: {
543    return isInt<6>(Imm);
544    llvm_unreachable("ImmediateCode should have returned");
545    return false;
546  }
547  case GIPFP_I64_Predicate_timmZExt1: {
548    return isUInt<1>(Imm);
549    llvm_unreachable("ImmediateCode should have returned");
550    return false;
551  }
552  case GIPFP_I64_Predicate_timmZExt10: {
553    return isUInt<10>(Imm);
554    llvm_unreachable("ImmediateCode should have returned");
555    return false;
556  }
557  case GIPFP_I64_Predicate_timmZExt1Ptr: {
558    return isUInt<1>(Imm);
559    llvm_unreachable("ImmediateCode should have returned");
560    return false;
561  }
562  case GIPFP_I64_Predicate_timmZExt2: {
563    return isUInt<2>(Imm);
564    llvm_unreachable("ImmediateCode should have returned");
565    return false;
566  }
567  case GIPFP_I64_Predicate_timmZExt2Ptr: {
568    return isUInt<2>(Imm);
569    llvm_unreachable("ImmediateCode should have returned");
570    return false;
571  }
572  case GIPFP_I64_Predicate_timmZExt3: {
573    return isUInt<3>(Imm);
574    llvm_unreachable("ImmediateCode should have returned");
575    return false;
576  }
577  case GIPFP_I64_Predicate_timmZExt3Ptr: {
578    return isUInt<3>(Imm);
579    llvm_unreachable("ImmediateCode should have returned");
580    return false;
581  }
582  case GIPFP_I64_Predicate_timmZExt4: {
583    return isUInt<4>(Imm);
584    llvm_unreachable("ImmediateCode should have returned");
585    return false;
586  }
587  case GIPFP_I64_Predicate_timmZExt4Ptr: {
588    return isUInt<4>(Imm);
589    llvm_unreachable("ImmediateCode should have returned");
590    return false;
591  }
592  case GIPFP_I64_Predicate_timmZExt5: {
593    return Imm == (Imm & 0x1f);
594    llvm_unreachable("ImmediateCode should have returned");
595    return false;
596  }
597  case GIPFP_I64_Predicate_timmZExt6: {
598    return Imm == (Imm & 0x3f);
599    llvm_unreachable("ImmediateCode should have returned");
600    return false;
601  }
602  case GIPFP_I64_Predicate_timmZExt8: {
603    return isUInt<8>(Imm);
604    llvm_unreachable("ImmediateCode should have returned");
605    return false;
606  }
607  }
608  llvm_unreachable("Unknown predicate");
609  return false;
610}
611bool MipsInstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const {
612  llvm_unreachable("Unknown predicate");
613  return false;
614}
615// PatFrag predicates.
616enum {
617  GIPFP_APInt_Predicate_imm32SExt16 = GIPFP_APInt_Invalid + 1,
618  GIPFP_APInt_Predicate_imm32ZExt16,
619};
620bool MipsInstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const {
621  switch (PredicateID) {
622  case GIPFP_APInt_Predicate_imm32SExt16: {
623     return isInt<16>(Imm.getSExtValue());
624    llvm_unreachable("ImmediateCode should have returned");
625    return false;
626  }
627  case GIPFP_APInt_Predicate_imm32ZExt16: {
628
629  return (uint32_t)Imm.getZExtValue() == (unsigned short)Imm.getZExtValue();
630
631    llvm_unreachable("ImmediateCode should have returned");
632    return false;
633  }
634  }
635  llvm_unreachable("Unknown predicate");
636  return false;
637}
638bool MipsInstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI, const std::array<const MachineOperand *, 3> &Operands) const {
639  const MachineFunction &MF = *MI.getParent()->getParent();
640  const MachineRegisterInfo &MRI = MF.getRegInfo();
641  (void)MRI;
642  llvm_unreachable("Unknown predicate");
643  return false;
644}
645
646MipsInstructionSelector::ComplexMatcherMemFn
647MipsInstructionSelector::ComplexPredicateFns[] = {
648  nullptr, // GICP_Invalid
649};
650
651// Custom renderers.
652enum {
653  GICR_Invalid,
654};
655MipsInstructionSelector::CustomRendererFn
656MipsInstructionSelector::CustomRenderers[] = {
657  nullptr, // GICR_Invalid
658};
659
660bool MipsInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const {
661  MachineFunction &MF = *I.getParent()->getParent();
662  MachineRegisterInfo &MRI = MF.getRegInfo();
663  const PredicateBitset AvailableFeatures = getAvailableFeatures();
664  NewMIVector OutMIs;
665  State.MIs.clear();
666  State.MIs.push_back(&I);
667
668  if (executeMatchTable(*this, OutMIs, State, ISelInfo, getMatchTable(), TII, MRI, TRI, RBI, AvailableFeatures, CoverageInfo)) {
669    return true;
670  }
671
672  return false;
673}
674
675const int64_t *MipsInstructionSelector::getMatchTable() const {
676  constexpr static int64_t MatchTable0[] = {
677    GIM_SwitchOpcode, /*MI*/0, /*[*/46, 215, /*)*//*default:*//*Label 58*/ 60447,
678    /*TargetOpcode::G_ADD*//*Label 0*/ 174,
679    /*TargetOpcode::G_SUB*//*Label 1*/ 1394,
680    /*TargetOpcode::G_MUL*//*Label 2*/ 2006,
681    /*TargetOpcode::G_SDIV*//*Label 3*/ 2382,
682    /*TargetOpcode::G_UDIV*//*Label 4*/ 2603,
683    /*TargetOpcode::G_SREM*//*Label 5*/ 2824,
684    /*TargetOpcode::G_UREM*//*Label 6*/ 3045, 0, 0,
685    /*TargetOpcode::G_AND*//*Label 7*/ 3266,
686    /*TargetOpcode::G_OR*//*Label 8*/ 3753,
687    /*TargetOpcode::G_XOR*//*Label 9*/ 4098, 0, 0, 0, 0, 0, 0, 0,
688    /*TargetOpcode::G_MERGE_VALUES*//*Label 10*/ 4938,
689    /*TargetOpcode::G_BUILD_VECTOR*//*Label 11*/ 5003, 0, 0, 0, 0,
690    /*TargetOpcode::G_BITCAST*//*Label 12*/ 5364, 0, 0, 0, 0, 0, 0, 0,
691    /*TargetOpcode::G_LOAD*//*Label 13*/ 9017,
692    /*TargetOpcode::G_SEXTLOAD*//*Label 14*/ 9083,
693    /*TargetOpcode::G_ZEXTLOAD*//*Label 15*/ 9149, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
694    /*TargetOpcode::G_INTRINSIC*//*Label 16*/ 9215,
695    /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 17*/ 25490,
696    /*TargetOpcode::G_ANYEXT*//*Label 18*/ 30474,
697    /*TargetOpcode::G_TRUNC*//*Label 19*/ 30540,
698    /*TargetOpcode::G_CONSTANT*//*Label 20*/ 30603, 0, 0, 0,
699    /*TargetOpcode::G_SEXT*//*Label 21*/ 30663, 0,
700    /*TargetOpcode::G_ZEXT*//*Label 22*/ 31921,
701    /*TargetOpcode::G_SHL*//*Label 23*/ 32115,
702    /*TargetOpcode::G_LSHR*//*Label 24*/ 33868,
703    /*TargetOpcode::G_ASHR*//*Label 25*/ 35621, 0, 0,
704    /*TargetOpcode::G_ROTR*//*Label 26*/ 37331, 0,
705    /*TargetOpcode::G_ICMP*//*Label 27*/ 37594,
706    /*TargetOpcode::G_FCMP*//*Label 28*/ 40098,
707    /*TargetOpcode::G_SELECT*//*Label 29*/ 41818, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
708    /*TargetOpcode::G_UMULH*//*Label 30*/ 54098,
709    /*TargetOpcode::G_SMULH*//*Label 31*/ 54185, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
710    /*TargetOpcode::G_FADD*//*Label 32*/ 54272,
711    /*TargetOpcode::G_FSUB*//*Label 33*/ 55151,
712    /*TargetOpcode::G_FMUL*//*Label 34*/ 55727,
713    /*TargetOpcode::G_FMA*//*Label 35*/ 56164, 0,
714    /*TargetOpcode::G_FDIV*//*Label 36*/ 56254, 0, 0, 0, 0,
715    /*TargetOpcode::G_FEXP2*//*Label 37*/ 56505, 0,
716    /*TargetOpcode::G_FLOG2*//*Label 38*/ 56563, 0,
717    /*TargetOpcode::G_FNEG*//*Label 39*/ 56621,
718    /*TargetOpcode::G_FPEXT*//*Label 40*/ 57917,
719    /*TargetOpcode::G_FPTRUNC*//*Label 41*/ 58066,
720    /*TargetOpcode::G_FPTOSI*//*Label 42*/ 58194,
721    /*TargetOpcode::G_FPTOUI*//*Label 43*/ 58252,
722    /*TargetOpcode::G_SITOFP*//*Label 44*/ 58310,
723    /*TargetOpcode::G_UITOFP*//*Label 45*/ 58518,
724    /*TargetOpcode::G_FABS*//*Label 46*/ 58576, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
725    /*TargetOpcode::G_SMIN*//*Label 47*/ 58759,
726    /*TargetOpcode::G_SMAX*//*Label 48*/ 58899,
727    /*TargetOpcode::G_UMIN*//*Label 49*/ 59039,
728    /*TargetOpcode::G_UMAX*//*Label 50*/ 59179, 0, 0, 0,
729    /*TargetOpcode::G_BR*//*Label 51*/ 59319, 0, 0,
730    /*TargetOpcode::G_EXTRACT_VECTOR_ELT*//*Label 52*/ 59404, 0, 0, 0,
731    /*TargetOpcode::G_CTLZ*//*Label 53*/ 59460, 0,
732    /*TargetOpcode::G_CTPOP*//*Label 54*/ 59895,
733    /*TargetOpcode::G_BSWAP*//*Label 55*/ 60054, 0, 0, 0, 0,
734    /*TargetOpcode::G_FSQRT*//*Label 56*/ 60206, 0,
735    /*TargetOpcode::G_FRINT*//*Label 57*/ 60389,
736    // Label 0: @174
737    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 67*/ 1393,
738    /*GILLT_s32*//*Label 59*/ 188,
739    /*GILLT_s64*//*Label 60*/ 580,
740    /*GILLT_v2s16*//*Label 61*/ 743,
741    /*GILLT_v2s64*//*Label 62*/ 770,
742    /*GILLT_v4s8*//*Label 63*/ 919,
743    /*GILLT_v4s32*//*Label 64*/ 946,
744    /*GILLT_v8s16*//*Label 65*/ 1095,
745    /*GILLT_v16s8*//*Label 66*/ 1244,
746    // Label 59: @188
747    GIM_Try, /*On fail goto*//*Label 68*/ 579,
748      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
749      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
750      GIM_Try, /*On fail goto*//*Label 69*/ 266, // Rule ID 2348 //
751        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
752        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
753        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
754        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
755        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
756        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
757        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
758        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
759        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
760        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_immZExt2Lsa,
761        // MIs[2] Operand 1
762        // No operand predicates
763        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
764        GIM_CheckIsSafeToFold, /*InsnID*/1,
765        GIM_CheckIsSafeToFold, /*InsnID*/2,
766        // (add:{ *:[i32] } (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa), GPR32Opnd:{ *:[i32] }:$rt)  =>  (LSA:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$sa)
767        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LSA,
768        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
769        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
770        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
771        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
772        GIR_EraseFromParent, /*InsnID*/0,
773        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
774        // GIR_Coverage, 2348,
775        GIR_Done,
776      // Label 69: @266
777      GIM_Try, /*On fail goto*//*Label 70*/ 334, // Rule ID 822 //
778        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
779        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
780        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
781        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
782        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
783        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
784        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
785        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
786        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
787        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
788        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_immZExt2Lsa,
789        // MIs[2] Operand 1
790        // No operand predicates
791        GIM_CheckIsSafeToFold, /*InsnID*/1,
792        GIM_CheckIsSafeToFold, /*InsnID*/2,
793        // (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa))  =>  (LSA:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$sa)
794        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LSA,
795        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
796        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
797        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt
798        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
799        GIR_EraseFromParent, /*InsnID*/0,
800        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
801        // GIR_Coverage, 822,
802        GIR_Done,
803      // Label 70: @334
804      GIM_Try, /*On fail goto*//*Label 71*/ 377, // Rule ID 40 //
805        GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
806        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
807        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
808        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
809        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
810        GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIPFP_APInt_Predicate_imm32SExt16,
811        // MIs[1] Operand 1
812        // No operand predicates
813        GIM_CheckIsSafeToFold, /*InsnID*/1,
814        // (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm16)  =>  (ADDiu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$imm16)
815        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDiu,
816        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
817        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
818        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16
819        GIR_EraseFromParent, /*InsnID*/0,
820        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
821        // GIR_Coverage, 40,
822        GIR_Done,
823      // Label 71: @377
824      GIM_Try, /*On fail goto*//*Label 72*/ 420, // Rule ID 2123 //
825        GIM_CheckFeatures, GIFBS_InMicroMips,
826        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
827        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
828        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
829        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
830        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immSExtAddiur2,
831        // MIs[1] Operand 1
832        // No operand predicates
833        GIM_CheckIsSafeToFold, /*InsnID*/1,
834        // (add:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddiur2>>:$imm)  =>  (ADDIUR2_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddiur2>>:$imm)
835        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDIUR2_MM,
836        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
837        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
838        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
839        GIR_EraseFromParent, /*InsnID*/0,
840        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
841        // GIR_Coverage, 2123,
842        GIR_Done,
843      // Label 72: @420
844      GIM_Try, /*On fail goto*//*Label 73*/ 463, // Rule ID 2124 //
845        GIM_CheckFeatures, GIFBS_InMicroMips,
846        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
847        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
848        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
849        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
850        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immSExtAddius5,
851        // MIs[1] Operand 1
852        // No operand predicates
853        GIM_CheckIsSafeToFold, /*InsnID*/1,
854        // (add:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddius5>>:$imm)  =>  (ADDIUS5_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddius5>>:$imm)
855        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDIUS5_MM,
856        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
857        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
858        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
859        GIR_EraseFromParent, /*InsnID*/0,
860        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
861        // GIR_Coverage, 2124,
862        GIR_Done,
863      // Label 73: @463
864      GIM_Try, /*On fail goto*//*Label 74*/ 486, // Rule ID 1196 //
865        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
866        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
867        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
868        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID,
869        // (add:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)  =>  (ADDU16_MMR6:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
870        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDU16_MMR6,
871        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
872        // GIR_Coverage, 1196,
873        GIR_Done,
874      // Label 74: @486
875      GIM_Try, /*On fail goto*//*Label 75*/ 509, // Rule ID 46 //
876        GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
877        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
878        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
879        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
880        // (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (ADDu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
881        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDu,
882        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
883        // GIR_Coverage, 46,
884        GIR_Done,
885      // Label 75: @509
886      GIM_Try, /*On fail goto*//*Label 76*/ 532, // Rule ID 1048 //
887        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
888        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
889        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
890        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID,
891        // (add:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)  =>  (ADDU16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
892        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDU16_MM,
893        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
894        // GIR_Coverage, 1048,
895        GIR_Done,
896      // Label 76: @532
897      GIM_Try, /*On fail goto*//*Label 77*/ 555, // Rule ID 1060 //
898        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
899        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
900        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
901        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
902        // (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (ADDu_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
903        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDu_MM,
904        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
905        // GIR_Coverage, 1060,
906        GIR_Done,
907      // Label 77: @555
908      GIM_Try, /*On fail goto*//*Label 78*/ 578, // Rule ID 1783 //
909        GIM_CheckFeatures, GIFBS_InMips16Mode,
910        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
911        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
912        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
913        // (add:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)  =>  (AdduRxRyRz16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
914        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AdduRxRyRz16,
915        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
916        // GIR_Coverage, 1783,
917        GIR_Done,
918      // Label 78: @578
919      GIM_Reject,
920    // Label 68: @579
921    GIM_Reject,
922    // Label 60: @580
923    GIM_Try, /*On fail goto*//*Label 79*/ 742,
924      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
925      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
926      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
927      GIM_Try, /*On fail goto*//*Label 80*/ 658, // Rule ID 2349 //
928        GIM_CheckFeatures, GIFBS_HasMSA_HasMips64_HasStdEnc,
929        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
930        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
931        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
932        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
933        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
934        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
935        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
936        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_immZExt2Lsa,
937        // MIs[2] Operand 1
938        // No operand predicates
939        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
940        GIM_CheckIsSafeToFold, /*InsnID*/1,
941        GIM_CheckIsSafeToFold, /*InsnID*/2,
942        // (add:{ *:[i64] } (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa), GPR64Opnd:{ *:[i64] }:$rt)  =>  (DLSA:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$sa)
943        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DLSA,
944        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
945        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
946        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
947        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
948        GIR_EraseFromParent, /*InsnID*/0,
949        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
950        // GIR_Coverage, 2349,
951        GIR_Done,
952      // Label 80: @658
953      GIM_Try, /*On fail goto*//*Label 81*/ 722, // Rule ID 823 //
954        GIM_CheckFeatures, GIFBS_HasMSA_HasMips64_HasStdEnc,
955        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
956        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
957        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
958        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
959        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
960        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
961        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
962        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
963        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_immZExt2Lsa,
964        // MIs[2] Operand 1
965        // No operand predicates
966        GIM_CheckIsSafeToFold, /*InsnID*/1,
967        GIM_CheckIsSafeToFold, /*InsnID*/2,
968        // (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa))  =>  (DLSA:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$sa)
969        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DLSA,
970        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
971        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
972        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt
973        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
974        GIR_EraseFromParent, /*InsnID*/0,
975        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
976        // GIR_Coverage, 823,
977        GIR_Done,
978      // Label 81: @722
979      GIM_Try, /*On fail goto*//*Label 82*/ 741, // Rule ID 196 //
980        GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_NotInMicroMips,
981        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
982        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
983        // (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DADDu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
984        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DADDu,
985        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
986        // GIR_Coverage, 196,
987        GIR_Done,
988      // Label 82: @741
989      GIM_Reject,
990    // Label 79: @742
991    GIM_Reject,
992    // Label 61: @743
993    GIM_Try, /*On fail goto*//*Label 83*/ 769, // Rule ID 1882 //
994      GIM_CheckFeatures, GIFBS_HasDSP,
995      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
996      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
997      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
998      // (add:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)  =>  (ADDQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
999      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDQ_PH,
1000      GIR_AddImplicitDef, /*InsnID*/0, Mips::DSPOutFlag20,
1001      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1002      // GIR_Coverage, 1882,
1003      GIR_Done,
1004    // Label 83: @769
1005    GIM_Reject,
1006    // Label 62: @770
1007    GIM_Try, /*On fail goto*//*Label 84*/ 918,
1008      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1009      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
1010      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
1011      GIM_Try, /*On fail goto*//*Label 85*/ 841, // Rule ID 2353 //
1012        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1013        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1014        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1015        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
1016        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
1017        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
1018        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
1019        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
1020        GIM_CheckIsSafeToFold, /*InsnID*/1,
1021        // (add:{ *:[v2i64] } (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt), MSA128DOpnd:{ *:[v2i64] }:$wd_in)  =>  (MADDV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1022        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_D,
1023        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
1024        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
1025        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1026        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1027        GIR_EraseFromParent, /*InsnID*/0,
1028        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1029        // GIR_Coverage, 2353,
1030        GIR_Done,
1031      // Label 85: @841
1032      GIM_Try, /*On fail goto*//*Label 86*/ 898, // Rule ID 831 //
1033        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1034        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
1035        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1036        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1037        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
1038        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
1039        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
1040        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
1041        GIM_CheckIsSafeToFold, /*InsnID*/1,
1042        // (add:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt))  =>  (MADDV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1043        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_D,
1044        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
1045        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
1046        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1047        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1048        GIR_EraseFromParent, /*InsnID*/0,
1049        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1050        // GIR_Coverage, 831,
1051        GIR_Done,
1052      // Label 86: @898
1053      GIM_Try, /*On fail goto*//*Label 87*/ 917, // Rule ID 498 //
1054        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1055        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
1056        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
1057        // (add:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (ADDV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1058        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDV_D,
1059        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1060        // GIR_Coverage, 498,
1061        GIR_Done,
1062      // Label 87: @917
1063      GIM_Reject,
1064    // Label 84: @918
1065    GIM_Reject,
1066    // Label 63: @919
1067    GIM_Try, /*On fail goto*//*Label 88*/ 945, // Rule ID 1888 //
1068      GIM_CheckFeatures, GIFBS_HasDSP,
1069      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8,
1070      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
1071      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
1072      // (add:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)  =>  (ADDU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)
1073      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDU_QB,
1074      GIR_AddImplicitDef, /*InsnID*/0, Mips::DSPOutFlag20,
1075      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1076      // GIR_Coverage, 1888,
1077      GIR_Done,
1078    // Label 88: @945
1079    GIM_Reject,
1080    // Label 64: @946
1081    GIM_Try, /*On fail goto*//*Label 89*/ 1094,
1082      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1083      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
1084      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
1085      GIM_Try, /*On fail goto*//*Label 90*/ 1017, // Rule ID 2352 //
1086        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1087        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1088        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1089        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
1090        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1091        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
1092        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
1093        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
1094        GIM_CheckIsSafeToFold, /*InsnID*/1,
1095        // (add:{ *:[v4i32] } (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt), MSA128WOpnd:{ *:[v4i32] }:$wd_in)  =>  (MADDV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1096        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_W,
1097        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
1098        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
1099        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1100        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1101        GIR_EraseFromParent, /*InsnID*/0,
1102        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1103        // GIR_Coverage, 2352,
1104        GIR_Done,
1105      // Label 90: @1017
1106      GIM_Try, /*On fail goto*//*Label 91*/ 1074, // Rule ID 830 //
1107        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1108        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
1109        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1110        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1111        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
1112        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1113        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
1114        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
1115        GIM_CheckIsSafeToFold, /*InsnID*/1,
1116        // (add:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt))  =>  (MADDV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1117        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_W,
1118        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
1119        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
1120        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1121        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1122        GIR_EraseFromParent, /*InsnID*/0,
1123        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1124        // GIR_Coverage, 830,
1125        GIR_Done,
1126      // Label 91: @1074
1127      GIM_Try, /*On fail goto*//*Label 92*/ 1093, // Rule ID 497 //
1128        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1129        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
1130        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
1131        // (add:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (ADDV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1132        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDV_W,
1133        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1134        // GIR_Coverage, 497,
1135        GIR_Done,
1136      // Label 92: @1093
1137      GIM_Reject,
1138    // Label 89: @1094
1139    GIM_Reject,
1140    // Label 65: @1095
1141    GIM_Try, /*On fail goto*//*Label 93*/ 1243,
1142      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
1143      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
1144      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
1145      GIM_Try, /*On fail goto*//*Label 94*/ 1166, // Rule ID 2351 //
1146        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1147        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1148        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1149        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
1150        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
1151        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1152        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1153        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1154        GIM_CheckIsSafeToFold, /*InsnID*/1,
1155        // (add:{ *:[v8i16] } (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt), MSA128HOpnd:{ *:[v8i16] }:$wd_in)  =>  (MADDV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1156        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_H,
1157        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
1158        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
1159        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1160        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1161        GIR_EraseFromParent, /*InsnID*/0,
1162        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1163        // GIR_Coverage, 2351,
1164        GIR_Done,
1165      // Label 94: @1166
1166      GIM_Try, /*On fail goto*//*Label 95*/ 1223, // Rule ID 829 //
1167        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1168        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1169        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1170        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1171        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
1172        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
1173        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1174        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1175        GIM_CheckIsSafeToFold, /*InsnID*/1,
1176        // (add:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt))  =>  (MADDV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1177        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_H,
1178        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
1179        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
1180        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1181        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1182        GIR_EraseFromParent, /*InsnID*/0,
1183        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1184        // GIR_Coverage, 829,
1185        GIR_Done,
1186      // Label 95: @1223
1187      GIM_Try, /*On fail goto*//*Label 96*/ 1242, // Rule ID 496 //
1188        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1189        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1190        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1191        // (add:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (ADDV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1192        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDV_H,
1193        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1194        // GIR_Coverage, 496,
1195        GIR_Done,
1196      // Label 96: @1242
1197      GIM_Reject,
1198    // Label 93: @1243
1199    GIM_Reject,
1200    // Label 66: @1244
1201    GIM_Try, /*On fail goto*//*Label 97*/ 1392,
1202      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
1203      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
1204      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
1205      GIM_Try, /*On fail goto*//*Label 98*/ 1315, // Rule ID 2350 //
1206        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1207        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1208        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1209        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
1210        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
1211        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1212        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1213        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1214        GIM_CheckIsSafeToFold, /*InsnID*/1,
1215        // (add:{ *:[v16i8] } (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt), MSA128BOpnd:{ *:[v16i8] }:$wd_in)  =>  (MADDV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1216        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_B,
1217        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
1218        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
1219        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1220        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1221        GIR_EraseFromParent, /*InsnID*/0,
1222        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1223        // GIR_Coverage, 2350,
1224        GIR_Done,
1225      // Label 98: @1315
1226      GIM_Try, /*On fail goto*//*Label 99*/ 1372, // Rule ID 828 //
1227        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1228        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1229        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1230        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1231        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
1232        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
1233        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1234        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1235        GIM_CheckIsSafeToFold, /*InsnID*/1,
1236        // (add:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt))  =>  (MADDV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1237        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_B,
1238        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
1239        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
1240        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1241        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1242        GIR_EraseFromParent, /*InsnID*/0,
1243        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1244        // GIR_Coverage, 828,
1245        GIR_Done,
1246      // Label 99: @1372
1247      GIM_Try, /*On fail goto*//*Label 100*/ 1391, // Rule ID 495 //
1248        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1249        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1250        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1251        // (add:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (ADDV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1252        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDV_B,
1253        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1254        // GIR_Coverage, 495,
1255        GIR_Done,
1256      // Label 100: @1391
1257      GIM_Reject,
1258    // Label 97: @1392
1259    GIM_Reject,
1260    // Label 67: @1393
1261    GIM_Reject,
1262    // Label 1: @1394
1263    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 109*/ 2005,
1264    /*GILLT_s32*//*Label 101*/ 1408,
1265    /*GILLT_s64*//*Label 102*/ 1567,
1266    /*GILLT_v2s16*//*Label 103*/ 1599,
1267    /*GILLT_v2s64*//*Label 104*/ 1626,
1268    /*GILLT_v4s8*//*Label 105*/ 1714,
1269    /*GILLT_v4s32*//*Label 106*/ 1741,
1270    /*GILLT_v8s16*//*Label 107*/ 1829,
1271    /*GILLT_v16s8*//*Label 108*/ 1917,
1272    // Label 101: @1408
1273    GIM_Try, /*On fail goto*//*Label 110*/ 1566,
1274      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1275      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
1276      GIM_Try, /*On fail goto*//*Label 111*/ 1450, // Rule ID 1782 //
1277        GIM_CheckFeatures, GIFBS_InMips16Mode,
1278        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
1279        GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0,
1280        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
1281        // (sub:{ *:[i32] } 0:{ *:[i32] }, CPU16Regs:{ *:[i32] }:$r)  =>  (NegRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r)
1282        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NegRxRy16,
1283        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rx
1284        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // r
1285        GIR_EraseFromParent, /*InsnID*/0,
1286        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1287        // GIR_Coverage, 1782,
1288        GIR_Done,
1289      // Label 111: @1450
1290      GIM_Try, /*On fail goto*//*Label 112*/ 1473, // Rule ID 1198 //
1291        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
1292        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
1293        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
1294        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID,
1295        // (sub:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)  =>  (SUBU16_MMR6:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
1296        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBU16_MMR6,
1297        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1298        // GIR_Coverage, 1198,
1299        GIR_Done,
1300      // Label 112: @1473
1301      GIM_Try, /*On fail goto*//*Label 113*/ 1496, // Rule ID 47 //
1302        GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
1303        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1304        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1305        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1306        // (sub:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (SUBu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1307        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBu,
1308        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1309        // GIR_Coverage, 47,
1310        GIR_Done,
1311      // Label 113: @1496
1312      GIM_Try, /*On fail goto*//*Label 114*/ 1519, // Rule ID 1052 //
1313        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
1314        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
1315        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
1316        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID,
1317        // (sub:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)  =>  (SUBU16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
1318        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBU16_MM,
1319        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1320        // GIR_Coverage, 1052,
1321        GIR_Done,
1322      // Label 114: @1519
1323      GIM_Try, /*On fail goto*//*Label 115*/ 1542, // Rule ID 1061 //
1324        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
1325        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1326        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1327        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1328        // (sub:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (SUBu_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1329        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBu_MM,
1330        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1331        // GIR_Coverage, 1061,
1332        GIR_Done,
1333      // Label 115: @1542
1334      GIM_Try, /*On fail goto*//*Label 116*/ 1565, // Rule ID 1787 //
1335        GIM_CheckFeatures, GIFBS_InMips16Mode,
1336        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
1337        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
1338        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
1339        // (sub:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)  =>  (SubuRxRyRz16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
1340        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SubuRxRyRz16,
1341        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1342        // GIR_Coverage, 1787,
1343        GIR_Done,
1344      // Label 116: @1565
1345      GIM_Reject,
1346    // Label 110: @1566
1347    GIM_Reject,
1348    // Label 102: @1567
1349    GIM_Try, /*On fail goto*//*Label 117*/ 1598, // Rule ID 197 //
1350      GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_NotInMicroMips,
1351      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1352      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
1353      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
1354      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
1355      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
1356      // (sub:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DSUBu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1357      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DSUBu,
1358      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1359      // GIR_Coverage, 197,
1360      GIR_Done,
1361    // Label 117: @1598
1362    GIM_Reject,
1363    // Label 103: @1599
1364    GIM_Try, /*On fail goto*//*Label 118*/ 1625, // Rule ID 1884 //
1365      GIM_CheckFeatures, GIFBS_HasDSP,
1366      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
1367      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
1368      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
1369      // (sub:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)  =>  (SUBQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
1370      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBQ_PH,
1371      GIR_AddImplicitDef, /*InsnID*/0, Mips::DSPOutFlag20,
1372      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1373      // GIR_Coverage, 1884,
1374      GIR_Done,
1375    // Label 118: @1625
1376    GIM_Reject,
1377    // Label 104: @1626
1378    GIM_Try, /*On fail goto*//*Label 119*/ 1713,
1379      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1380      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
1381      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
1382      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
1383      GIM_Try, /*On fail goto*//*Label 120*/ 1697, // Rule ID 887 //
1384        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1385        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1386        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1387        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
1388        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
1389        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
1390        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
1391        GIM_CheckIsSafeToFold, /*InsnID*/1,
1392        // (sub:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt))  =>  (MSUBV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1393        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBV_D,
1394        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
1395        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
1396        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1397        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1398        GIR_EraseFromParent, /*InsnID*/0,
1399        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1400        // GIR_Coverage, 887,
1401        GIR_Done,
1402      // Label 120: @1697
1403      GIM_Try, /*On fail goto*//*Label 121*/ 1712, // Rule ID 1016 //
1404        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1405        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
1406        // (sub:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (SUBV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1407        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBV_D,
1408        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1409        // GIR_Coverage, 1016,
1410        GIR_Done,
1411      // Label 121: @1712
1412      GIM_Reject,
1413    // Label 119: @1713
1414    GIM_Reject,
1415    // Label 105: @1714
1416    GIM_Try, /*On fail goto*//*Label 122*/ 1740, // Rule ID 1890 //
1417      GIM_CheckFeatures, GIFBS_HasDSP,
1418      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8,
1419      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
1420      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
1421      // (sub:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)  =>  (SUBU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)
1422      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBU_QB,
1423      GIR_AddImplicitDef, /*InsnID*/0, Mips::DSPOutFlag20,
1424      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1425      // GIR_Coverage, 1890,
1426      GIR_Done,
1427    // Label 122: @1740
1428    GIM_Reject,
1429    // Label 106: @1741
1430    GIM_Try, /*On fail goto*//*Label 123*/ 1828,
1431      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1432      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
1433      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
1434      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
1435      GIM_Try, /*On fail goto*//*Label 124*/ 1812, // Rule ID 886 //
1436        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1437        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1438        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1439        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
1440        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1441        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
1442        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
1443        GIM_CheckIsSafeToFold, /*InsnID*/1,
1444        // (sub:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt))  =>  (MSUBV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1445        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBV_W,
1446        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
1447        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
1448        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1449        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1450        GIR_EraseFromParent, /*InsnID*/0,
1451        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1452        // GIR_Coverage, 886,
1453        GIR_Done,
1454      // Label 124: @1812
1455      GIM_Try, /*On fail goto*//*Label 125*/ 1827, // Rule ID 1015 //
1456        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1457        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
1458        // (sub:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (SUBV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1459        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBV_W,
1460        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1461        // GIR_Coverage, 1015,
1462        GIR_Done,
1463      // Label 125: @1827
1464      GIM_Reject,
1465    // Label 123: @1828
1466    GIM_Reject,
1467    // Label 107: @1829
1468    GIM_Try, /*On fail goto*//*Label 126*/ 1916,
1469      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
1470      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
1471      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
1472      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1473      GIM_Try, /*On fail goto*//*Label 127*/ 1900, // Rule ID 885 //
1474        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1475        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1476        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1477        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
1478        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
1479        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1480        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1481        GIM_CheckIsSafeToFold, /*InsnID*/1,
1482        // (sub:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt))  =>  (MSUBV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1483        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBV_H,
1484        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
1485        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
1486        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1487        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1488        GIR_EraseFromParent, /*InsnID*/0,
1489        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1490        // GIR_Coverage, 885,
1491        GIR_Done,
1492      // Label 127: @1900
1493      GIM_Try, /*On fail goto*//*Label 128*/ 1915, // Rule ID 1014 //
1494        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1495        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1496        // (sub:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (SUBV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1497        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBV_H,
1498        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1499        // GIR_Coverage, 1014,
1500        GIR_Done,
1501      // Label 128: @1915
1502      GIM_Reject,
1503    // Label 126: @1916
1504    GIM_Reject,
1505    // Label 108: @1917
1506    GIM_Try, /*On fail goto*//*Label 129*/ 2004,
1507      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
1508      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
1509      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
1510      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1511      GIM_Try, /*On fail goto*//*Label 130*/ 1988, // Rule ID 884 //
1512        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1513        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1514        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1515        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
1516        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
1517        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1518        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1519        GIM_CheckIsSafeToFold, /*InsnID*/1,
1520        // (sub:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt))  =>  (MSUBV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1521        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBV_B,
1522        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
1523        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
1524        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1525        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1526        GIR_EraseFromParent, /*InsnID*/0,
1527        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1528        // GIR_Coverage, 884,
1529        GIR_Done,
1530      // Label 130: @1988
1531      GIM_Try, /*On fail goto*//*Label 131*/ 2003, // Rule ID 1013 //
1532        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1533        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1534        // (sub:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (SUBV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1535        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBV_B,
1536        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1537        // GIR_Coverage, 1013,
1538        GIR_Done,
1539      // Label 131: @2003
1540      GIM_Reject,
1541    // Label 129: @2004
1542    GIM_Reject,
1543    // Label 109: @2005
1544    GIM_Reject,
1545    // Label 2: @2006
1546    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 139*/ 2381,
1547    /*GILLT_s32*//*Label 132*/ 2020,
1548    /*GILLT_s64*//*Label 133*/ 2165,
1549    /*GILLT_v2s16*//*Label 134*/ 2226,
1550    /*GILLT_v2s64*//*Label 135*/ 2253, 0,
1551    /*GILLT_v4s32*//*Label 136*/ 2285,
1552    /*GILLT_v8s16*//*Label 137*/ 2317,
1553    /*GILLT_v16s8*//*Label 138*/ 2349,
1554    // Label 132: @2020
1555    GIM_Try, /*On fail goto*//*Label 140*/ 2164,
1556      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1557      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
1558      GIM_Try, /*On fail goto*//*Label 141*/ 2059, // Rule ID 48 //
1559        GIM_CheckFeatures, GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
1560        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1561        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1562        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1563        // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MUL:{ *:[i32] }:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1564        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUL,
1565        GIR_AddImplicitDef, /*InsnID*/0, Mips::HI0,
1566        GIR_AddImplicitDef, /*InsnID*/0, Mips::LO0,
1567        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1568        // GIR_Coverage, 48,
1569        GIR_Done,
1570      // Label 141: @2059
1571      GIM_Try, /*On fail goto*//*Label 142*/ 2082, // Rule ID 320 //
1572        GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
1573        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1574        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1575        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1576        // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MUL_R6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1577        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUL_R6,
1578        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1579        // GIR_Coverage, 320,
1580        GIR_Done,
1581      // Label 142: @2082
1582      GIM_Try, /*On fail goto*//*Label 143*/ 2111, // Rule ID 1062 //
1583        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
1584        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1585        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1586        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1587        // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MUL_MM:{ *:[i32] }:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1588        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUL_MM,
1589        GIR_AddImplicitDef, /*InsnID*/0, Mips::HI0,
1590        GIR_AddImplicitDef, /*InsnID*/0, Mips::LO0,
1591        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1592        // GIR_Coverage, 1062,
1593        GIR_Done,
1594      // Label 143: @2111
1595      GIM_Try, /*On fail goto*//*Label 144*/ 2134, // Rule ID 1167 //
1596        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
1597        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1598        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1599        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1600        // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MUL_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1601        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUL_MMR6,
1602        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1603        // GIR_Coverage, 1167,
1604        GIR_Done,
1605      // Label 144: @2134
1606      GIM_Try, /*On fail goto*//*Label 145*/ 2163, // Rule ID 1785 //
1607        GIM_CheckFeatures, GIFBS_InMips16Mode,
1608        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
1609        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
1610        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
1611        // (mul:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)  =>  (MultRxRyRz16:{ *:[i32] }:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
1612        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MultRxRyRz16,
1613        GIR_AddImplicitDef, /*InsnID*/0, Mips::HI0,
1614        GIR_AddImplicitDef, /*InsnID*/0, Mips::LO0,
1615        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1616        // GIR_Coverage, 1785,
1617        GIR_Done,
1618      // Label 145: @2163
1619      GIM_Reject,
1620    // Label 140: @2164
1621    GIM_Reject,
1622    // Label 133: @2165
1623    GIM_Try, /*On fail goto*//*Label 146*/ 2225,
1624      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1625      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
1626      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
1627      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
1628      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
1629      GIM_Try, /*On fail goto*//*Label 147*/ 2213, // Rule ID 262 //
1630        GIM_CheckFeatures, GIFBS_HasCnMips,
1631        // (mul:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DMUL:{ *:[i64] }:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1632        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMUL,
1633        GIR_AddImplicitDef, /*InsnID*/0, Mips::HI0,
1634        GIR_AddImplicitDef, /*InsnID*/0, Mips::LO0,
1635        GIR_AddImplicitDef, /*InsnID*/0, Mips::P0,
1636        GIR_AddImplicitDef, /*InsnID*/0, Mips::P1,
1637        GIR_AddImplicitDef, /*InsnID*/0, Mips::P2,
1638        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1639        // GIR_Coverage, 262,
1640        GIR_Done,
1641      // Label 147: @2213
1642      GIM_Try, /*On fail goto*//*Label 148*/ 2224, // Rule ID 335 //
1643        GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
1644        // (mul:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DMUL_R6:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1645        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMUL_R6,
1646        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1647        // GIR_Coverage, 335,
1648        GIR_Done,
1649      // Label 148: @2224
1650      GIM_Reject,
1651    // Label 146: @2225
1652    GIM_Reject,
1653    // Label 134: @2226
1654    GIM_Try, /*On fail goto*//*Label 149*/ 2252, // Rule ID 1886 //
1655      GIM_CheckFeatures, GIFBS_HasDSPR2,
1656      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
1657      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
1658      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
1659      // (mul:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)  =>  (MUL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
1660      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUL_PH,
1661      GIR_AddImplicitDef, /*InsnID*/0, Mips::DSPOutFlag21,
1662      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1663      // GIR_Coverage, 1886,
1664      GIR_Done,
1665    // Label 149: @2252
1666    GIM_Reject,
1667    // Label 135: @2253
1668    GIM_Try, /*On fail goto*//*Label 150*/ 2284, // Rule ID 895 //
1669      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1670      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1671      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
1672      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
1673      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
1674      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
1675      // (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (MULV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1676      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MULV_D,
1677      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1678      // GIR_Coverage, 895,
1679      GIR_Done,
1680    // Label 150: @2284
1681    GIM_Reject,
1682    // Label 136: @2285
1683    GIM_Try, /*On fail goto*//*Label 151*/ 2316, // Rule ID 894 //
1684      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1685      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1686      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
1687      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
1688      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
1689      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
1690      // (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (MULV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1691      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MULV_W,
1692      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1693      // GIR_Coverage, 894,
1694      GIR_Done,
1695    // Label 151: @2316
1696    GIM_Reject,
1697    // Label 137: @2317
1698    GIM_Try, /*On fail goto*//*Label 152*/ 2348, // Rule ID 893 //
1699      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1700      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
1701      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
1702      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
1703      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1704      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1705      // (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (MULV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1706      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MULV_H,
1707      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1708      // GIR_Coverage, 893,
1709      GIR_Done,
1710    // Label 152: @2348
1711    GIM_Reject,
1712    // Label 138: @2349
1713    GIM_Try, /*On fail goto*//*Label 153*/ 2380, // Rule ID 892 //
1714      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1715      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
1716      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
1717      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
1718      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1719      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1720      // (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (MULV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1721      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MULV_B,
1722      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1723      // GIR_Coverage, 892,
1724      GIR_Done,
1725    // Label 153: @2380
1726    GIM_Reject,
1727    // Label 139: @2381
1728    GIM_Reject,
1729    // Label 3: @2382
1730    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 160*/ 2602,
1731    /*GILLT_s32*//*Label 154*/ 2396,
1732    /*GILLT_s64*//*Label 155*/ 2442, 0,
1733    /*GILLT_v2s64*//*Label 156*/ 2474, 0,
1734    /*GILLT_v4s32*//*Label 157*/ 2506,
1735    /*GILLT_v8s16*//*Label 158*/ 2538,
1736    /*GILLT_v16s8*//*Label 159*/ 2570,
1737    // Label 154: @2396
1738    GIM_Try, /*On fail goto*//*Label 161*/ 2441,
1739      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1740      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
1741      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1742      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1743      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1744      GIM_Try, /*On fail goto*//*Label 162*/ 2429, // Rule ID 314 //
1745        GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
1746        // (sdiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (DIV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1747        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV,
1748        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1749        // GIR_Coverage, 314,
1750        GIR_Done,
1751      // Label 162: @2429
1752      GIM_Try, /*On fail goto*//*Label 163*/ 2440, // Rule ID 1160 //
1753        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
1754        // (sdiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (DIV_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1755        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_MMR6,
1756        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1757        // GIR_Coverage, 1160,
1758        GIR_Done,
1759      // Label 163: @2440
1760      GIM_Reject,
1761    // Label 161: @2441
1762    GIM_Reject,
1763    // Label 155: @2442
1764    GIM_Try, /*On fail goto*//*Label 164*/ 2473, // Rule ID 329 //
1765      GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
1766      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1767      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
1768      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
1769      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
1770      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
1771      // (sdiv:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DDIV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1772      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DDIV,
1773      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1774      // GIR_Coverage, 329,
1775      GIR_Done,
1776    // Label 164: @2473
1777    GIM_Reject,
1778    // Label 156: @2474
1779    GIM_Try, /*On fail goto*//*Label 165*/ 2505, // Rule ID 635 //
1780      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1781      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1782      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
1783      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
1784      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
1785      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
1786      // (sdiv:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (DIV_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1787      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_S_D,
1788      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1789      // GIR_Coverage, 635,
1790      GIR_Done,
1791    // Label 165: @2505
1792    GIM_Reject,
1793    // Label 157: @2506
1794    GIM_Try, /*On fail goto*//*Label 166*/ 2537, // Rule ID 634 //
1795      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1796      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1797      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
1798      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
1799      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
1800      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
1801      // (sdiv:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (DIV_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1802      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_S_W,
1803      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1804      // GIR_Coverage, 634,
1805      GIR_Done,
1806    // Label 166: @2537
1807    GIM_Reject,
1808    // Label 158: @2538
1809    GIM_Try, /*On fail goto*//*Label 167*/ 2569, // Rule ID 633 //
1810      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1811      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
1812      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
1813      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
1814      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1815      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1816      // (sdiv:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (DIV_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1817      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_S_H,
1818      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1819      // GIR_Coverage, 633,
1820      GIR_Done,
1821    // Label 167: @2569
1822    GIM_Reject,
1823    // Label 159: @2570
1824    GIM_Try, /*On fail goto*//*Label 168*/ 2601, // Rule ID 632 //
1825      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1826      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
1827      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
1828      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
1829      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1830      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1831      // (sdiv:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (DIV_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1832      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_S_B,
1833      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1834      // GIR_Coverage, 632,
1835      GIR_Done,
1836    // Label 168: @2601
1837    GIM_Reject,
1838    // Label 160: @2602
1839    GIM_Reject,
1840    // Label 4: @2603
1841    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 175*/ 2823,
1842    /*GILLT_s32*//*Label 169*/ 2617,
1843    /*GILLT_s64*//*Label 170*/ 2663, 0,
1844    /*GILLT_v2s64*//*Label 171*/ 2695, 0,
1845    /*GILLT_v4s32*//*Label 172*/ 2727,
1846    /*GILLT_v8s16*//*Label 173*/ 2759,
1847    /*GILLT_v16s8*//*Label 174*/ 2791,
1848    // Label 169: @2617
1849    GIM_Try, /*On fail goto*//*Label 176*/ 2662,
1850      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1851      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
1852      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1853      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1854      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1855      GIM_Try, /*On fail goto*//*Label 177*/ 2650, // Rule ID 315 //
1856        GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
1857        // (udiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (DIVU:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1858        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIVU,
1859        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1860        // GIR_Coverage, 315,
1861        GIR_Done,
1862      // Label 177: @2650
1863      GIM_Try, /*On fail goto*//*Label 178*/ 2661, // Rule ID 1161 //
1864        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
1865        // (udiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (DIVU_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1866        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIVU_MMR6,
1867        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1868        // GIR_Coverage, 1161,
1869        GIR_Done,
1870      // Label 178: @2661
1871      GIM_Reject,
1872    // Label 176: @2662
1873    GIM_Reject,
1874    // Label 170: @2663
1875    GIM_Try, /*On fail goto*//*Label 179*/ 2694, // Rule ID 330 //
1876      GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
1877      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1878      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
1879      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
1880      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
1881      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
1882      // (udiv:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DDIVU:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1883      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DDIVU,
1884      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1885      // GIR_Coverage, 330,
1886      GIR_Done,
1887    // Label 179: @2694
1888    GIM_Reject,
1889    // Label 171: @2695
1890    GIM_Try, /*On fail goto*//*Label 180*/ 2726, // Rule ID 639 //
1891      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1892      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1893      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
1894      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
1895      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
1896      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
1897      // (udiv:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (DIV_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1898      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_U_D,
1899      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1900      // GIR_Coverage, 639,
1901      GIR_Done,
1902    // Label 180: @2726
1903    GIM_Reject,
1904    // Label 172: @2727
1905    GIM_Try, /*On fail goto*//*Label 181*/ 2758, // Rule ID 638 //
1906      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1907      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1908      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
1909      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
1910      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
1911      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
1912      // (udiv:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (DIV_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1913      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_U_W,
1914      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1915      // GIR_Coverage, 638,
1916      GIR_Done,
1917    // Label 181: @2758
1918    GIM_Reject,
1919    // Label 173: @2759
1920    GIM_Try, /*On fail goto*//*Label 182*/ 2790, // Rule ID 637 //
1921      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1922      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
1923      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
1924      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
1925      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1926      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1927      // (udiv:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (DIV_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1928      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_U_H,
1929      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1930      // GIR_Coverage, 637,
1931      GIR_Done,
1932    // Label 182: @2790
1933    GIM_Reject,
1934    // Label 174: @2791
1935    GIM_Try, /*On fail goto*//*Label 183*/ 2822, // Rule ID 636 //
1936      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1937      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
1938      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
1939      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
1940      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1941      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1942      // (udiv:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (DIV_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1943      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_U_B,
1944      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1945      // GIR_Coverage, 636,
1946      GIR_Done,
1947    // Label 183: @2822
1948    GIM_Reject,
1949    // Label 175: @2823
1950    GIM_Reject,
1951    // Label 5: @2824
1952    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 190*/ 3044,
1953    /*GILLT_s32*//*Label 184*/ 2838,
1954    /*GILLT_s64*//*Label 185*/ 2884, 0,
1955    /*GILLT_v2s64*//*Label 186*/ 2916, 0,
1956    /*GILLT_v4s32*//*Label 187*/ 2948,
1957    /*GILLT_v8s16*//*Label 188*/ 2980,
1958    /*GILLT_v16s8*//*Label 189*/ 3012,
1959    // Label 184: @2838
1960    GIM_Try, /*On fail goto*//*Label 191*/ 2883,
1961      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1962      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
1963      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1964      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1965      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1966      GIM_Try, /*On fail goto*//*Label 192*/ 2871, // Rule ID 316 //
1967        GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
1968        // (srem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MOD:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1969        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD,
1970        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1971        // GIR_Coverage, 316,
1972        GIR_Done,
1973      // Label 192: @2871
1974      GIM_Try, /*On fail goto*//*Label 193*/ 2882, // Rule ID 1165 //
1975        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
1976        // (srem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MOD_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1977        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_MMR6,
1978        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1979        // GIR_Coverage, 1165,
1980        GIR_Done,
1981      // Label 193: @2882
1982      GIM_Reject,
1983    // Label 191: @2883
1984    GIM_Reject,
1985    // Label 185: @2884
1986    GIM_Try, /*On fail goto*//*Label 194*/ 2915, // Rule ID 331 //
1987      GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
1988      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1989      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
1990      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
1991      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
1992      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
1993      // (srem:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DMOD:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1994      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMOD,
1995      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1996      // GIR_Coverage, 331,
1997      GIR_Done,
1998    // Label 194: @2915
1999    GIM_Reject,
2000    // Label 186: @2916
2001    GIM_Try, /*On fail goto*//*Label 195*/ 2947, // Rule ID 875 //
2002      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2003      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
2004      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
2005      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2006      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
2007      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
2008      // (srem:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (MOD_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
2009      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_S_D,
2010      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2011      // GIR_Coverage, 875,
2012      GIR_Done,
2013    // Label 195: @2947
2014    GIM_Reject,
2015    // Label 187: @2948
2016    GIM_Try, /*On fail goto*//*Label 196*/ 2979, // Rule ID 874 //
2017      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2018      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
2019      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
2020      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
2021      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
2022      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
2023      // (srem:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (MOD_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
2024      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_S_W,
2025      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2026      // GIR_Coverage, 874,
2027      GIR_Done,
2028    // Label 196: @2979
2029    GIM_Reject,
2030    // Label 188: @2980
2031    GIM_Try, /*On fail goto*//*Label 197*/ 3011, // Rule ID 873 //
2032      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2033      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
2034      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
2035      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
2036      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
2037      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
2038      // (srem:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (MOD_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
2039      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_S_H,
2040      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2041      // GIR_Coverage, 873,
2042      GIR_Done,
2043    // Label 197: @3011
2044    GIM_Reject,
2045    // Label 189: @3012
2046    GIM_Try, /*On fail goto*//*Label 198*/ 3043, // Rule ID 872 //
2047      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2048      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
2049      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
2050      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
2051      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
2052      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
2053      // (srem:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (MOD_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
2054      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_S_B,
2055      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2056      // GIR_Coverage, 872,
2057      GIR_Done,
2058    // Label 198: @3043
2059    GIM_Reject,
2060    // Label 190: @3044
2061    GIM_Reject,
2062    // Label 6: @3045
2063    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 205*/ 3265,
2064    /*GILLT_s32*//*Label 199*/ 3059,
2065    /*GILLT_s64*//*Label 200*/ 3105, 0,
2066    /*GILLT_v2s64*//*Label 201*/ 3137, 0,
2067    /*GILLT_v4s32*//*Label 202*/ 3169,
2068    /*GILLT_v8s16*//*Label 203*/ 3201,
2069    /*GILLT_v16s8*//*Label 204*/ 3233,
2070    // Label 199: @3059
2071    GIM_Try, /*On fail goto*//*Label 206*/ 3104,
2072      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2073      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2074      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2075      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2076      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2077      GIM_Try, /*On fail goto*//*Label 207*/ 3092, // Rule ID 317 //
2078        GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
2079        // (urem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MODU:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2080        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MODU,
2081        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2082        // GIR_Coverage, 317,
2083        GIR_Done,
2084      // Label 207: @3092
2085      GIM_Try, /*On fail goto*//*Label 208*/ 3103, // Rule ID 1166 //
2086        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
2087        // (urem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MODU_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2088        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MODU_MMR6,
2089        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2090        // GIR_Coverage, 1166,
2091        GIR_Done,
2092      // Label 208: @3103
2093      GIM_Reject,
2094    // Label 206: @3104
2095    GIM_Reject,
2096    // Label 200: @3105
2097    GIM_Try, /*On fail goto*//*Label 209*/ 3136, // Rule ID 332 //
2098      GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
2099      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
2100      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2101      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
2102      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
2103      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
2104      // (urem:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DMODU:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2105      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMODU,
2106      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2107      // GIR_Coverage, 332,
2108      GIR_Done,
2109    // Label 209: @3136
2110    GIM_Reject,
2111    // Label 201: @3137
2112    GIM_Try, /*On fail goto*//*Label 210*/ 3168, // Rule ID 879 //
2113      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2114      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
2115      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
2116      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2117      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
2118      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
2119      // (urem:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (MOD_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
2120      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_U_D,
2121      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2122      // GIR_Coverage, 879,
2123      GIR_Done,
2124    // Label 210: @3168
2125    GIM_Reject,
2126    // Label 202: @3169
2127    GIM_Try, /*On fail goto*//*Label 211*/ 3200, // Rule ID 878 //
2128      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2129      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
2130      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
2131      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
2132      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
2133      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
2134      // (urem:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (MOD_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
2135      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_U_W,
2136      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2137      // GIR_Coverage, 878,
2138      GIR_Done,
2139    // Label 211: @3200
2140    GIM_Reject,
2141    // Label 203: @3201
2142    GIM_Try, /*On fail goto*//*Label 212*/ 3232, // Rule ID 877 //
2143      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2144      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
2145      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
2146      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
2147      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
2148      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
2149      // (urem:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (MOD_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
2150      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_U_H,
2151      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2152      // GIR_Coverage, 877,
2153      GIR_Done,
2154    // Label 212: @3232
2155    GIM_Reject,
2156    // Label 204: @3233
2157    GIM_Try, /*On fail goto*//*Label 213*/ 3264, // Rule ID 876 //
2158      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2159      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
2160      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
2161      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
2162      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
2163      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
2164      // (urem:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (MOD_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
2165      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_U_B,
2166      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2167      // GIR_Coverage, 876,
2168      GIR_Done,
2169    // Label 213: @3264
2170    GIM_Reject,
2171    // Label 205: @3265
2172    GIM_Reject,
2173    // Label 7: @3266
2174    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 220*/ 3752,
2175    /*GILLT_s32*//*Label 214*/ 3280,
2176    /*GILLT_s64*//*Label 215*/ 3536, 0,
2177    /*GILLT_v2s64*//*Label 216*/ 3624, 0,
2178    /*GILLT_v4s32*//*Label 217*/ 3656,
2179    /*GILLT_v8s16*//*Label 218*/ 3688,
2180    /*GILLT_v16s8*//*Label 219*/ 3720,
2181    // Label 214: @3280
2182    GIM_Try, /*On fail goto*//*Label 221*/ 3535,
2183      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2184      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2185      GIM_Try, /*On fail goto*//*Label 222*/ 3333, // Rule ID 41 //
2186        GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
2187        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2188        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2189        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2190        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
2191        GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIPFP_APInt_Predicate_imm32ZExt16,
2192        // MIs[1] Operand 1
2193        // No operand predicates
2194        GIM_CheckIsSafeToFold, /*InsnID*/1,
2195        // (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_imm32ZExt16>>:$imm16)  =>  (ANDi:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$imm16)
2196        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ANDi,
2197        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
2198        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
2199        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16
2200        GIR_EraseFromParent, /*InsnID*/0,
2201        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2202        // GIR_Coverage, 41,
2203        GIR_Done,
2204      // Label 222: @3333
2205      GIM_Try, /*On fail goto*//*Label 223*/ 3376, // Rule ID 2126 //
2206        GIM_CheckFeatures, GIFBS_InMicroMips,
2207        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2208        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2209        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2210        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
2211        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExtAndi16,
2212        // MIs[1] Operand 1
2213        // No operand predicates
2214        GIM_CheckIsSafeToFold, /*InsnID*/1,
2215        // (and:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm)  =>  (ANDI16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm)
2216        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ANDI16_MM,
2217        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2218        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
2219        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
2220        GIR_EraseFromParent, /*InsnID*/0,
2221        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2222        // GIR_Coverage, 2126,
2223        GIR_Done,
2224      // Label 223: @3376
2225      GIM_Try, /*On fail goto*//*Label 224*/ 3419, // Rule ID 2285 //
2226        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
2227        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2228        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2229        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2230        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
2231        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExtAndi16,
2232        // MIs[1] Operand 1
2233        // No operand predicates
2234        GIM_CheckIsSafeToFold, /*InsnID*/1,
2235        // (and:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm)  =>  (ANDI16_MMR6:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm)
2236        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ANDI16_MMR6,
2237        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2238        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
2239        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
2240        GIR_EraseFromParent, /*InsnID*/0,
2241        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2242        // GIR_Coverage, 2285,
2243        GIR_Done,
2244      // Label 224: @3419
2245      GIM_Try, /*On fail goto*//*Label 225*/ 3442, // Rule ID 51 //
2246        GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
2247        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2248        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2249        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2250        // (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (AND:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2251        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND,
2252        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2253        // GIR_Coverage, 51,
2254        GIR_Done,
2255      // Label 225: @3442
2256      GIM_Try, /*On fail goto*//*Label 226*/ 3465, // Rule ID 1049 //
2257        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
2258        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2259        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2260        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID,
2261        // (and:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)  =>  (AND16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
2262        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND16_MM,
2263        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2264        // GIR_Coverage, 1049,
2265        GIR_Done,
2266      // Label 226: @3465
2267      GIM_Try, /*On fail goto*//*Label 227*/ 3488, // Rule ID 1065 //
2268        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
2269        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2270        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2271        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2272        // (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (AND_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2273        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_MM,
2274        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2275        // GIR_Coverage, 1065,
2276        GIR_Done,
2277      // Label 227: @3488
2278      GIM_Try, /*On fail goto*//*Label 228*/ 3511, // Rule ID 1158 //
2279        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
2280        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2281        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2282        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2283        // (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (AND_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2284        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_MMR6,
2285        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2286        // GIR_Coverage, 1158,
2287        GIR_Done,
2288      // Label 228: @3511
2289      GIM_Try, /*On fail goto*//*Label 229*/ 3534, // Rule ID 1784 //
2290        GIM_CheckFeatures, GIFBS_InMips16Mode,
2291        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
2292        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
2293        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
2294        // (and:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)  =>  (AndRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
2295        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AndRxRxRy16,
2296        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2297        // GIR_Coverage, 1784,
2298        GIR_Done,
2299      // Label 229: @3534
2300      GIM_Reject,
2301    // Label 221: @3535
2302    GIM_Reject,
2303    // Label 215: @3536
2304    GIM_Try, /*On fail goto*//*Label 230*/ 3623,
2305      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
2306      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2307      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
2308      GIM_Try, /*On fail goto*//*Label 231*/ 3603, // Rule ID 257 //
2309        GIM_CheckFeatures, GIFBS_HasCnMips,
2310        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2311        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
2312        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
2313        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
2314        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
2315        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
2316        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 255,
2317        GIM_CheckIsSafeToFold, /*InsnID*/1,
2318        // (and:{ *:[i64] } (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt), 255:{ *:[i64] })  =>  (BADDu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2319        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BADDu,
2320        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2321        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2322        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2323        GIR_EraseFromParent, /*InsnID*/0,
2324        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2325        // GIR_Coverage, 257,
2326        GIR_Done,
2327      // Label 231: @3603
2328      GIM_Try, /*On fail goto*//*Label 232*/ 3622, // Rule ID 200 //
2329        GIM_CheckFeatures, GIFBS_IsGP64bit_NotInMips16Mode,
2330        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
2331        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
2332        // (and:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (AND64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2333        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND64,
2334        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2335        // GIR_Coverage, 200,
2336        GIR_Done,
2337      // Label 232: @3622
2338      GIM_Reject,
2339    // Label 230: @3623
2340    GIM_Reject,
2341    // Label 216: @3624
2342    GIM_Try, /*On fail goto*//*Label 233*/ 3655, // Rule ID 506 //
2343      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2344      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
2345      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
2346      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2347      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
2348      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
2349      // (and:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (AND_V_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
2350      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_V_D_PSEUDO,
2351      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2352      // GIR_Coverage, 506,
2353      GIR_Done,
2354    // Label 233: @3655
2355    GIM_Reject,
2356    // Label 217: @3656
2357    GIM_Try, /*On fail goto*//*Label 234*/ 3687, // Rule ID 505 //
2358      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2359      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
2360      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
2361      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
2362      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
2363      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
2364      // (and:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (AND_V_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
2365      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_V_W_PSEUDO,
2366      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2367      // GIR_Coverage, 505,
2368      GIR_Done,
2369    // Label 234: @3687
2370    GIM_Reject,
2371    // Label 218: @3688
2372    GIM_Try, /*On fail goto*//*Label 235*/ 3719, // Rule ID 504 //
2373      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2374      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
2375      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
2376      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
2377      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
2378      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
2379      // (and:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (AND_V_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
2380      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_V_H_PSEUDO,
2381      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2382      // GIR_Coverage, 504,
2383      GIR_Done,
2384    // Label 235: @3719
2385    GIM_Reject,
2386    // Label 219: @3720
2387    GIM_Try, /*On fail goto*//*Label 236*/ 3751, // Rule ID 503 //
2388      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2389      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
2390      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
2391      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
2392      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
2393      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
2394      // (and:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (AND_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
2395      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_V,
2396      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2397      // GIR_Coverage, 503,
2398      GIR_Done,
2399    // Label 236: @3751
2400    GIM_Reject,
2401    // Label 220: @3752
2402    GIM_Reject,
2403    // Label 8: @3753
2404    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 243*/ 4097,
2405    /*GILLT_s32*//*Label 237*/ 3767,
2406    /*GILLT_s64*//*Label 238*/ 3937, 0,
2407    /*GILLT_v2s64*//*Label 239*/ 3969, 0,
2408    /*GILLT_v4s32*//*Label 240*/ 4001,
2409    /*GILLT_v8s16*//*Label 241*/ 4033,
2410    /*GILLT_v16s8*//*Label 242*/ 4065,
2411    // Label 237: @3767
2412    GIM_Try, /*On fail goto*//*Label 244*/ 3936,
2413      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2414      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2415      GIM_Try, /*On fail goto*//*Label 245*/ 3820, // Rule ID 42 //
2416        GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
2417        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2418        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2419        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2420        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
2421        GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIPFP_APInt_Predicate_imm32ZExt16,
2422        // MIs[1] Operand 1
2423        // No operand predicates
2424        GIM_CheckIsSafeToFold, /*InsnID*/1,
2425        // (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_imm32ZExt16>>:$imm16)  =>  (ORi:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$imm16)
2426        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ORi,
2427        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
2428        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
2429        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16
2430        GIR_EraseFromParent, /*InsnID*/0,
2431        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2432        // GIR_Coverage, 42,
2433        GIR_Done,
2434      // Label 245: @3820
2435      GIM_Try, /*On fail goto*//*Label 246*/ 3843, // Rule ID 52 //
2436        GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
2437        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2438        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2439        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2440        // (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (OR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2441        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR,
2442        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2443        // GIR_Coverage, 52,
2444        GIR_Done,
2445      // Label 246: @3843
2446      GIM_Try, /*On fail goto*//*Label 247*/ 3866, // Rule ID 1051 //
2447        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
2448        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2449        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2450        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID,
2451        // (or:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)  =>  (OR16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
2452        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR16_MM,
2453        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2454        // GIR_Coverage, 1051,
2455        GIR_Done,
2456      // Label 247: @3866
2457      GIM_Try, /*On fail goto*//*Label 248*/ 3889, // Rule ID 1066 //
2458        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
2459        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2460        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2461        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2462        // (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (OR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2463        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_MM,
2464        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2465        // GIR_Coverage, 1066,
2466        GIR_Done,
2467      // Label 248: @3889
2468      GIM_Try, /*On fail goto*//*Label 249*/ 3912, // Rule ID 1171 //
2469        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
2470        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2471        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2472        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2473        // (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (OR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2474        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_MMR6,
2475        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2476        // GIR_Coverage, 1171,
2477        GIR_Done,
2478      // Label 249: @3912
2479      GIM_Try, /*On fail goto*//*Label 250*/ 3935, // Rule ID 1786 //
2480        GIM_CheckFeatures, GIFBS_InMips16Mode,
2481        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
2482        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
2483        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
2484        // (or:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)  =>  (OrRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
2485        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OrRxRxRy16,
2486        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2487        // GIR_Coverage, 1786,
2488        GIR_Done,
2489      // Label 250: @3935
2490      GIM_Reject,
2491    // Label 244: @3936
2492    GIM_Reject,
2493    // Label 238: @3937
2494    GIM_Try, /*On fail goto*//*Label 251*/ 3968, // Rule ID 201 //
2495      GIM_CheckFeatures, GIFBS_IsGP64bit_NotInMips16Mode,
2496      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
2497      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2498      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
2499      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
2500      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
2501      // (or:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (OR64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2502      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR64,
2503      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2504      // GIR_Coverage, 201,
2505      GIR_Done,
2506    // Label 251: @3968
2507    GIM_Reject,
2508    // Label 239: @3969
2509    GIM_Try, /*On fail goto*//*Label 252*/ 4000, // Rule ID 912 //
2510      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2511      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
2512      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
2513      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2514      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
2515      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
2516      // (or:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (OR_V_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
2517      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_V_D_PSEUDO,
2518      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2519      // GIR_Coverage, 912,
2520      GIR_Done,
2521    // Label 252: @4000
2522    GIM_Reject,
2523    // Label 240: @4001
2524    GIM_Try, /*On fail goto*//*Label 253*/ 4032, // Rule ID 911 //
2525      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2526      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
2527      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
2528      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
2529      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
2530      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
2531      // (or:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (OR_V_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
2532      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_V_W_PSEUDO,
2533      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2534      // GIR_Coverage, 911,
2535      GIR_Done,
2536    // Label 253: @4032
2537    GIM_Reject,
2538    // Label 241: @4033
2539    GIM_Try, /*On fail goto*//*Label 254*/ 4064, // Rule ID 910 //
2540      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2541      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
2542      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
2543      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
2544      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
2545      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
2546      // (or:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (OR_V_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
2547      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_V_H_PSEUDO,
2548      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2549      // GIR_Coverage, 910,
2550      GIR_Done,
2551    // Label 254: @4064
2552    GIM_Reject,
2553    // Label 242: @4065
2554    GIM_Try, /*On fail goto*//*Label 255*/ 4096, // Rule ID 909 //
2555      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2556      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
2557      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
2558      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
2559      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
2560      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
2561      // (or:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (OR_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
2562      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_V,
2563      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2564      // GIR_Coverage, 909,
2565      GIR_Done,
2566    // Label 255: @4096
2567    GIM_Reject,
2568    // Label 243: @4097
2569    GIM_Reject,
2570    // Label 9: @4098
2571    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 262*/ 4937,
2572    /*GILLT_s32*//*Label 256*/ 4112,
2573    /*GILLT_s64*//*Label 257*/ 4721, 0,
2574    /*GILLT_v2s64*//*Label 258*/ 4809, 0,
2575    /*GILLT_v4s32*//*Label 259*/ 4841,
2576    /*GILLT_v8s16*//*Label 260*/ 4873,
2577    /*GILLT_v16s8*//*Label 261*/ 4905,
2578    // Label 256: @4112
2579    GIM_Try, /*On fail goto*//*Label 263*/ 4720,
2580      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2581      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2582      GIM_Try, /*On fail goto*//*Label 264*/ 4179, // Rule ID 54 //
2583        GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
2584        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2585        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2586        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR,
2587        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2588        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2589        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2590        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2591        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2592        GIM_CheckIsSafeToFold, /*InsnID*/1,
2593        // (xor:{ *:[i32] } (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt), -1:{ *:[i32] })  =>  (NOR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2594        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR,
2595        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2596        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2597        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2598        GIR_EraseFromParent, /*InsnID*/0,
2599        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2600        // GIR_Coverage, 54,
2601        GIR_Done,
2602      // Label 264: @4179
2603      GIM_Try, /*On fail goto*//*Label 265*/ 4236, // Rule ID 1068 //
2604        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
2605        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2606        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2607        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR,
2608        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2609        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2610        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2611        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2612        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2613        GIM_CheckIsSafeToFold, /*InsnID*/1,
2614        // (xor:{ *:[i32] } (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt), -1:{ *:[i32] })  =>  (NOR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2615        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MM,
2616        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2617        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2618        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2619        GIR_EraseFromParent, /*InsnID*/0,
2620        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2621        // GIR_Coverage, 1068,
2622        GIR_Done,
2623      // Label 265: @4236
2624      GIM_Try, /*On fail goto*//*Label 266*/ 4293, // Rule ID 1170 //
2625        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
2626        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2627        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2628        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR,
2629        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2630        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2631        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2632        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2633        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2634        GIM_CheckIsSafeToFold, /*InsnID*/1,
2635        // (xor:{ *:[i32] } (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt), -1:{ *:[i32] })  =>  (NOR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2636        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MMR6,
2637        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2638        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2639        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2640        GIR_EraseFromParent, /*InsnID*/0,
2641        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2642        // GIR_Coverage, 1170,
2643        GIR_Done,
2644      // Label 266: @4293
2645      GIM_Try, /*On fail goto*//*Label 267*/ 4325, // Rule ID 1197 //
2646        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
2647        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2648        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2649        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2650        // (xor:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] })  =>  (NOT16_MMR6:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs)
2651        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOT16_MMR6,
2652        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
2653        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
2654        GIR_EraseFromParent, /*InsnID*/0,
2655        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2656        // GIR_Coverage, 1197,
2657        GIR_Done,
2658      // Label 267: @4325
2659      GIM_Try, /*On fail goto*//*Label 268*/ 4357, // Rule ID 1050 //
2660        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
2661        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2662        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2663        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2664        // (xor:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] })  =>  (NOT16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs)
2665        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOT16_MM,
2666        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
2667        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
2668        GIR_EraseFromParent, /*InsnID*/0,
2669        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2670        // GIR_Coverage, 1050,
2671        GIR_Done,
2672      // Label 268: @4357
2673      GIM_Try, /*On fail goto*//*Label 269*/ 4393, // Rule ID 1385 //
2674        GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
2675        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2676        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2677        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2678        // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$in, -1:{ *:[i32] })  =>  (NOR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$in, ZERO:{ *:[i32] })
2679        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR,
2680        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2681        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in
2682        GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0,
2683        GIR_EraseFromParent, /*InsnID*/0,
2684        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2685        // GIR_Coverage, 1385,
2686        GIR_Done,
2687      // Label 269: @4393
2688      GIM_Try, /*On fail goto*//*Label 270*/ 4425, // Rule ID 1781 //
2689        GIM_CheckFeatures, GIFBS_InMips16Mode,
2690        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
2691        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
2692        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2693        // (xor:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, -1:{ *:[i32] })  =>  (NotRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r)
2694        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NotRxRy16,
2695        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rx
2696        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // r
2697        GIR_EraseFromParent, /*InsnID*/0,
2698        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2699        // GIR_Coverage, 1781,
2700        GIR_Done,
2701      // Label 270: @4425
2702      GIM_Try, /*On fail goto*//*Label 271*/ 4457, // Rule ID 2121 //
2703        GIM_CheckFeatures, GIFBS_InMicroMips,
2704        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2705        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2706        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2707        // (xor:{ *:[i32] } GPRMM16:{ *:[i32] }:$in, -1:{ *:[i32] })  =>  (NOT16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$in)
2708        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOT16_MM,
2709        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
2710        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in
2711        GIR_EraseFromParent, /*InsnID*/0,
2712        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2713        // GIR_Coverage, 2121,
2714        GIR_Done,
2715      // Label 271: @4457
2716      GIM_Try, /*On fail goto*//*Label 272*/ 4493, // Rule ID 2122 //
2717        GIM_CheckFeatures, GIFBS_InMicroMips,
2718        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2719        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2720        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2721        // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$in, -1:{ *:[i32] })  =>  (NOR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$in, ZERO:{ *:[i32] })
2722        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MM,
2723        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2724        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in
2725        GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0,
2726        GIR_EraseFromParent, /*InsnID*/0,
2727        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2728        // GIR_Coverage, 2122,
2729        GIR_Done,
2730      // Label 272: @4493
2731      GIM_Try, /*On fail goto*//*Label 273*/ 4525, // Rule ID 2288 //
2732        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
2733        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2734        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2735        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2736        // (xor:{ *:[i32] } GPRMM16:{ *:[i32] }:$in, -1:{ *:[i32] })  =>  (NOT16_MMR6:{ *:[i32] } GPRMM16:{ *:[i32] }:$in)
2737        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOT16_MMR6,
2738        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
2739        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in
2740        GIR_EraseFromParent, /*InsnID*/0,
2741        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2742        // GIR_Coverage, 2288,
2743        GIR_Done,
2744      // Label 273: @4525
2745      GIM_Try, /*On fail goto*//*Label 274*/ 4561, // Rule ID 2289 //
2746        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
2747        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2748        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2749        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2750        // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$in, -1:{ *:[i32] })  =>  (NOR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$in, ZERO:{ *:[i32] })
2751        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MMR6,
2752        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2753        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in
2754        GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0,
2755        GIR_EraseFromParent, /*InsnID*/0,
2756        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2757        // GIR_Coverage, 2289,
2758        GIR_Done,
2759      // Label 274: @4561
2760      GIM_Try, /*On fail goto*//*Label 275*/ 4604, // Rule ID 43 //
2761        GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
2762        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2763        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2764        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2765        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
2766        GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIPFP_APInt_Predicate_imm32ZExt16,
2767        // MIs[1] Operand 1
2768        // No operand predicates
2769        GIM_CheckIsSafeToFold, /*InsnID*/1,
2770        // (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_imm32ZExt16>>:$imm16)  =>  (XORi:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$imm16)
2771        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi,
2772        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
2773        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
2774        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16
2775        GIR_EraseFromParent, /*InsnID*/0,
2776        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2777        // GIR_Coverage, 43,
2778        GIR_Done,
2779      // Label 275: @4604
2780      GIM_Try, /*On fail goto*//*Label 276*/ 4627, // Rule ID 53 //
2781        GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
2782        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2783        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2784        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2785        // (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (XOR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2786        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR,
2787        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2788        // GIR_Coverage, 53,
2789        GIR_Done,
2790      // Label 276: @4627
2791      GIM_Try, /*On fail goto*//*Label 277*/ 4650, // Rule ID 1053 //
2792        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
2793        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2794        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2795        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID,
2796        // (xor:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)  =>  (XOR16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
2797        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR16_MM,
2798        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2799        // GIR_Coverage, 1053,
2800        GIR_Done,
2801      // Label 277: @4650
2802      GIM_Try, /*On fail goto*//*Label 278*/ 4673, // Rule ID 1067 //
2803        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
2804        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2805        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2806        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2807        // (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (XOR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2808        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_MM,
2809        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2810        // GIR_Coverage, 1067,
2811        GIR_Done,
2812      // Label 278: @4673
2813      GIM_Try, /*On fail goto*//*Label 279*/ 4696, // Rule ID 1174 //
2814        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
2815        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2816        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2817        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2818        // (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (XOR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2819        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_MMR6,
2820        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2821        // GIR_Coverage, 1174,
2822        GIR_Done,
2823      // Label 279: @4696
2824      GIM_Try, /*On fail goto*//*Label 280*/ 4719, // Rule ID 1788 //
2825        GIM_CheckFeatures, GIFBS_InMips16Mode,
2826        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
2827        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
2828        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
2829        // (xor:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)  =>  (XorRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
2830        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XorRxRxRy16,
2831        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2832        // GIR_Coverage, 1788,
2833        GIR_Done,
2834      // Label 280: @4719
2835      GIM_Reject,
2836    // Label 263: @4720
2837    GIM_Reject,
2838    // Label 257: @4721
2839    GIM_Try, /*On fail goto*//*Label 281*/ 4808,
2840      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
2841      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2842      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
2843      GIM_Try, /*On fail goto*//*Label 282*/ 4788, // Rule ID 203 //
2844        GIM_CheckFeatures, GIFBS_IsGP64bit_NotInMips16Mode,
2845        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2846        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR,
2847        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
2848        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
2849        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
2850        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
2851        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2852        GIM_CheckIsSafeToFold, /*InsnID*/1,
2853        // (xor:{ *:[i64] } (or:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt), -1:{ *:[i64] })  =>  (NOR64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2854        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR64,
2855        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2856        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2857        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2858        GIR_EraseFromParent, /*InsnID*/0,
2859        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2860        // GIR_Coverage, 203,
2861        GIR_Done,
2862      // Label 282: @4788
2863      GIM_Try, /*On fail goto*//*Label 283*/ 4807, // Rule ID 202 //
2864        GIM_CheckFeatures, GIFBS_IsGP64bit_NotInMips16Mode,
2865        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
2866        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
2867        // (xor:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (XOR64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2868        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR64,
2869        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2870        // GIR_Coverage, 202,
2871        GIR_Done,
2872      // Label 283: @4807
2873      GIM_Reject,
2874    // Label 281: @4808
2875    GIM_Reject,
2876    // Label 258: @4809
2877    GIM_Try, /*On fail goto*//*Label 284*/ 4840, // Rule ID 1028 //
2878      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2879      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
2880      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
2881      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2882      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
2883      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
2884      // (xor:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (XOR_V_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
2885      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_V_D_PSEUDO,
2886      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2887      // GIR_Coverage, 1028,
2888      GIR_Done,
2889    // Label 284: @4840
2890    GIM_Reject,
2891    // Label 259: @4841
2892    GIM_Try, /*On fail goto*//*Label 285*/ 4872, // Rule ID 1027 //
2893      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2894      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
2895      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
2896      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
2897      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
2898      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
2899      // (xor:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (XOR_V_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
2900      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_V_W_PSEUDO,
2901      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2902      // GIR_Coverage, 1027,
2903      GIR_Done,
2904    // Label 285: @4872
2905    GIM_Reject,
2906    // Label 260: @4873
2907    GIM_Try, /*On fail goto*//*Label 286*/ 4904, // Rule ID 1026 //
2908      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2909      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
2910      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
2911      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
2912      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
2913      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
2914      // (xor:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (XOR_V_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
2915      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_V_H_PSEUDO,
2916      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2917      // GIR_Coverage, 1026,
2918      GIR_Done,
2919    // Label 286: @4904
2920    GIM_Reject,
2921    // Label 261: @4905
2922    GIM_Try, /*On fail goto*//*Label 287*/ 4936, // Rule ID 1025 //
2923      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2924      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
2925      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
2926      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
2927      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
2928      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
2929      // (xor:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (XOR_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
2930      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_V,
2931      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2932      // GIR_Coverage, 1025,
2933      GIR_Done,
2934    // Label 287: @4936
2935    GIM_Reject,
2936    // Label 262: @4937
2937    GIM_Reject,
2938    // Label 10: @4938
2939    GIM_Try, /*On fail goto*//*Label 288*/ 5002,
2940      GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
2941      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
2942      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2943      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2944      GIM_Try, /*On fail goto*//*Label 289*/ 4978, // Rule ID 174 //
2945        GIM_CheckFeatures, GIFBS_IsNotSoftFloat_NotFP64bit_NotInMips16Mode,
2946        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
2947        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2948        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2949        // (MipsBuildPairF64:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$lo, GPR32Opnd:{ *:[i32] }:$hi)  =>  (BuildPairF64:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$lo, GPR32Opnd:{ *:[i32] }:$hi)
2950        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::BuildPairF64,
2951        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2952        // GIR_Coverage, 174,
2953        GIR_Done,
2954      // Label 289: @4978
2955      GIM_Try, /*On fail goto*//*Label 290*/ 5001, // Rule ID 175 //
2956        GIM_CheckFeatures, GIFBS_IsFP64bit_IsNotSoftFloat_NotInMips16Mode,
2957        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
2958        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2959        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2960        // (MipsBuildPairF64:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$lo, GPR32Opnd:{ *:[i32] }:$hi)  =>  (BuildPairF64_64:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$lo, GPR32Opnd:{ *:[i32] }:$hi)
2961        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::BuildPairF64_64,
2962        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2963        // GIR_Coverage, 175,
2964        GIR_Done,
2965      // Label 290: @5001
2966      GIM_Reject,
2967    // Label 288: @5002
2968    GIM_Reject,
2969    // Label 11: @5003
2970    GIM_Try, /*On fail goto*//*Label 291*/ 5079,
2971      GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
2972      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
2973      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
2974      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2975      GIM_Try, /*On fail goto*//*Label 292*/ 5049, // Rule ID 707 //
2976        GIM_CheckFeatures, GIFBS_HasMSA_HasMips64_HasStdEnc,
2977        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
2978        // MIs[0] rs
2979        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
2980        // (build_vector:{ *:[v2i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rs)  =>  (FILL_D:{ *:[v2i64] } GPR64Opnd:{ *:[i64] }:$rs)
2981        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FILL_D,
2982        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
2983        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
2984        GIR_EraseFromParent, /*InsnID*/0,
2985        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2986        // GIR_Coverage, 707,
2987        GIR_Done,
2988      // Label 292: @5049
2989      GIM_Try, /*On fail goto*//*Label 293*/ 5078, // Rule ID 709 //
2990        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2991        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
2992        // MIs[0] fs
2993        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
2994        // (build_vector:{ *:[v2f64] } FGR64:{ *:[f64] }:$fs, FGR64:{ *:[f64] }:$fs)  =>  (FILL_FD_PSEUDO:{ *:[v2f64] } FGR64:{ *:[f64] }:$fs)
2995        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FILL_FD_PSEUDO,
2996        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
2997        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fs
2998        GIR_EraseFromParent, /*InsnID*/0,
2999        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3000        // GIR_Coverage, 709,
3001        GIR_Done,
3002      // Label 293: @5078
3003      GIM_Reject,
3004    // Label 291: @5079
3005    GIM_Try, /*On fail goto*//*Label 294*/ 5175,
3006      GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
3007      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
3008      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3009      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3010      GIM_Try, /*On fail goto*//*Label 295*/ 5135, // Rule ID 706 //
3011        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
3012        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
3013        // MIs[0] rs
3014        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
3015        // MIs[0] rs
3016        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1,
3017        // MIs[0] rs
3018        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1,
3019        // (build_vector:{ *:[v4i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs)  =>  (FILL_W:{ *:[v4i32] } GPR32Opnd:{ *:[i32] }:$rs)
3020        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FILL_W,
3021        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
3022        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
3023        GIR_EraseFromParent, /*InsnID*/0,
3024        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3025        // GIR_Coverage, 706,
3026        GIR_Done,
3027      // Label 295: @5135
3028      GIM_Try, /*On fail goto*//*Label 296*/ 5174, // Rule ID 708 //
3029        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
3030        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
3031        // MIs[0] fs
3032        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
3033        // MIs[0] fs
3034        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1,
3035        // MIs[0] fs
3036        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1,
3037        // (build_vector:{ *:[v4f32] } FGR32:{ *:[f32] }:$fs, FGR32:{ *:[f32] }:$fs, FGR32:{ *:[f32] }:$fs, FGR32:{ *:[f32] }:$fs)  =>  (FILL_FW_PSEUDO:{ *:[v4f32] } FGR32:{ *:[f32] }:$fs)
3038        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FILL_FW_PSEUDO,
3039        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
3040        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fs
3041        GIR_EraseFromParent, /*InsnID*/0,
3042        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3043        // GIR_Coverage, 708,
3044        GIR_Done,
3045      // Label 296: @5174
3046      GIM_Reject,
3047    // Label 294: @5175
3048    GIM_Try, /*On fail goto*//*Label 297*/ 5249, // Rule ID 705 //
3049      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
3050      GIM_CheckNumOperands, /*MI*/0, /*Expected*/9,
3051      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
3052      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3053      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3054      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
3055      // MIs[0] rs
3056      GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
3057      // MIs[0] rs
3058      GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1,
3059      // MIs[0] rs
3060      GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1,
3061      // MIs[0] rs
3062      GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/5, /*OtherMI*/0, /*OtherOpIdx*/1,
3063      // MIs[0] rs
3064      GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/6, /*OtherMI*/0, /*OtherOpIdx*/1,
3065      // MIs[0] rs
3066      GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/7, /*OtherMI*/0, /*OtherOpIdx*/1,
3067      // MIs[0] rs
3068      GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/8, /*OtherMI*/0, /*OtherOpIdx*/1,
3069      // (build_vector:{ *:[v8i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs)  =>  (FILL_H:{ *:[v8i16] } GPR32Opnd:{ *:[i32] }:$rs)
3070      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FILL_H,
3071      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
3072      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
3073      GIR_EraseFromParent, /*InsnID*/0,
3074      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3075      // GIR_Coverage, 705,
3076      GIR_Done,
3077    // Label 297: @5249
3078    GIM_Try, /*On fail goto*//*Label 298*/ 5363, // Rule ID 704 //
3079      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
3080      GIM_CheckNumOperands, /*MI*/0, /*Expected*/17,
3081      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
3082      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3083      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
3084      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
3085      // MIs[0] rs
3086      GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
3087      // MIs[0] rs
3088      GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1,
3089      // MIs[0] rs
3090      GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1,
3091      // MIs[0] rs
3092      GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/5, /*OtherMI*/0, /*OtherOpIdx*/1,
3093      // MIs[0] rs
3094      GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/6, /*OtherMI*/0, /*OtherOpIdx*/1,
3095      // MIs[0] rs
3096      GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/7, /*OtherMI*/0, /*OtherOpIdx*/1,
3097      // MIs[0] rs
3098      GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/8, /*OtherMI*/0, /*OtherOpIdx*/1,
3099      // MIs[0] rs
3100      GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/9, /*OtherMI*/0, /*OtherOpIdx*/1,
3101      // MIs[0] rs
3102      GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/10, /*OtherMI*/0, /*OtherOpIdx*/1,
3103      // MIs[0] rs
3104      GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/11, /*OtherMI*/0, /*OtherOpIdx*/1,
3105      // MIs[0] rs
3106      GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/12, /*OtherMI*/0, /*OtherOpIdx*/1,
3107      // MIs[0] rs
3108      GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/13, /*OtherMI*/0, /*OtherOpIdx*/1,
3109      // MIs[0] rs
3110      GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/14, /*OtherMI*/0, /*OtherOpIdx*/1,
3111      // MIs[0] rs
3112      GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/15, /*OtherMI*/0, /*OtherOpIdx*/1,
3113      // MIs[0] rs
3114      GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/16, /*OtherMI*/0, /*OtherOpIdx*/1,
3115      // (build_vector:{ *:[v16i8] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs)  =>  (FILL_B:{ *:[v16i8] } GPR32Opnd:{ *:[i32] }:$rs)
3116      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FILL_B,
3117      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
3118      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
3119      GIR_EraseFromParent, /*InsnID*/0,
3120      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3121      // GIR_Coverage, 704,
3122      GIR_Done,
3123    // Label 298: @5363
3124    GIM_Reject,
3125    // Label 12: @5364
3126    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 307*/ 9016,
3127    /*GILLT_s32*//*Label 299*/ 5378,
3128    /*GILLT_s64*//*Label 300*/ 5617,
3129    /*GILLT_v2s16*//*Label 301*/ 5663,
3130    /*GILLT_v2s64*//*Label 302*/ 5709,
3131    /*GILLT_v4s8*//*Label 303*/ 6682,
3132    /*GILLT_v4s32*//*Label 304*/ 6728,
3133    /*GILLT_v8s16*//*Label 305*/ 7631,
3134    /*GILLT_v16s8*//*Label 306*/ 8429,
3135    // Label 299: @5378
3136    GIM_Try, /*On fail goto*//*Label 308*/ 5401, // Rule ID 129 //
3137      GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
3138      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3139      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
3140      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
3141      // (bitconvert:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)  =>  (MFC1:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)
3142      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MFC1,
3143      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3144      // GIR_Coverage, 129,
3145      GIR_Done,
3146    // Label 308: @5401
3147    GIM_Try, /*On fail goto*//*Label 309*/ 5424, // Rule ID 130 //
3148      GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
3149      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3150      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
3151      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
3152      // (bitconvert:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)  =>  (MTC1:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)
3153      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MTC1,
3154      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3155      // GIR_Coverage, 130,
3156      GIR_Done,
3157    // Label 309: @5424
3158    GIM_Try, /*On fail goto*//*Label 310*/ 5447, // Rule ID 1148 //
3159      GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat,
3160      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3161      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
3162      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
3163      // (bitconvert:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)  =>  (MFC1_MM:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)
3164      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MFC1_MM,
3165      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3166      // GIR_Coverage, 1148,
3167      GIR_Done,
3168    // Label 310: @5447
3169    GIM_Try, /*On fail goto*//*Label 311*/ 5470, // Rule ID 1149 //
3170      GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat,
3171      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3172      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
3173      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
3174      // (bitconvert:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)  =>  (MTC1_MM:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)
3175      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MTC1_MM,
3176      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3177      // GIR_Coverage, 1149,
3178      GIR_Done,
3179    // Label 311: @5470
3180    GIM_Try, /*On fail goto*//*Label 312*/ 5493, // Rule ID 1163 //
3181      GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
3182      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3183      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
3184      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
3185      // (bitconvert:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)  =>  (MTC1_MMR6:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)
3186      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MTC1_MMR6,
3187      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3188      // GIR_Coverage, 1163,
3189      GIR_Done,
3190    // Label 312: @5493
3191    GIM_Try, /*On fail goto*//*Label 313*/ 5516, // Rule ID 1164 //
3192      GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
3193      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3194      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
3195      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
3196      // (bitconvert:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)  =>  (MFC1_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)
3197      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MFC1_MMR6,
3198      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3199      // GIR_Coverage, 1164,
3200      GIR_Done,
3201    // Label 313: @5516
3202    GIM_Try, /*On fail goto*//*Label 314*/ 5541, // Rule ID 1869 //
3203      GIM_CheckFeatures, GIFBS_HasDSP,
3204      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
3205      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
3206      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
3207      // (bitconvert:{ *:[i32] } DSPR:{ *:[v2i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[i32] } DSPR:{ *:[v2i16] }:$src, GPR32:{ *:[i32] })
3208      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3209      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::GPR32RegClassID,
3210      // GIR_Coverage, 1869,
3211      GIR_Done,
3212    // Label 314: @5541
3213    GIM_Try, /*On fail goto*//*Label 315*/ 5566, // Rule ID 1870 //
3214      GIM_CheckFeatures, GIFBS_HasDSP,
3215      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8,
3216      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
3217      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
3218      // (bitconvert:{ *:[i32] } DSPR:{ *:[v4i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[i32] } DSPR:{ *:[v4i8] }:$src, GPR32:{ *:[i32] })
3219      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3220      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::GPR32RegClassID,
3221      // GIR_Coverage, 1870,
3222      GIR_Done,
3223    // Label 315: @5566
3224    GIM_Try, /*On fail goto*//*Label 316*/ 5591, // Rule ID 1873 //
3225      GIM_CheckFeatures, GIFBS_HasDSP,
3226      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
3227      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
3228      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
3229      // (bitconvert:{ *:[f32] } DSPR:{ *:[v2i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[f32] } DSPR:{ *:[v2i16] }:$src, FGR32:{ *:[i32] })
3230      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3231      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::FGR32RegClassID,
3232      // GIR_Coverage, 1873,
3233      GIR_Done,
3234    // Label 316: @5591
3235    GIM_Try, /*On fail goto*//*Label 317*/ 5616, // Rule ID 1874 //
3236      GIM_CheckFeatures, GIFBS_HasDSP,
3237      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8,
3238      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
3239      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
3240      // (bitconvert:{ *:[f32] } DSPR:{ *:[v4i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[f32] } DSPR:{ *:[v4i8] }:$src, FGR32:{ *:[i32] })
3241      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3242      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::FGR32RegClassID,
3243      // GIR_Coverage, 1874,
3244      GIR_Done,
3245    // Label 317: @5616
3246    GIM_Reject,
3247    // Label 300: @5617
3248    GIM_Try, /*On fail goto*//*Label 318*/ 5662,
3249      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
3250      GIM_Try, /*On fail goto*//*Label 319*/ 5642, // Rule ID 131 //
3251        GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
3252        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
3253        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
3254        // (bitconvert:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$rt)  =>  (DMTC1:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$rt)
3255        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMTC1,
3256        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3257        // GIR_Coverage, 131,
3258        GIR_Done,
3259      // Label 319: @5642
3260      GIM_Try, /*On fail goto*//*Label 320*/ 5661, // Rule ID 132 //
3261        GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
3262        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
3263        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
3264        // (bitconvert:{ *:[i64] } FGR64Opnd:{ *:[f64] }:$fs)  =>  (DMFC1:{ *:[i64] } FGR64Opnd:{ *:[f64] }:$fs)
3265        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMFC1,
3266        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3267        // GIR_Coverage, 132,
3268        GIR_Done,
3269      // Label 320: @5661
3270      GIM_Reject,
3271    // Label 318: @5662
3272    GIM_Reject,
3273    // Label 301: @5663
3274    GIM_Try, /*On fail goto*//*Label 321*/ 5708,
3275      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3276      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
3277      GIM_Try, /*On fail goto*//*Label 322*/ 5690, // Rule ID 1871 //
3278        GIM_CheckFeatures, GIFBS_HasDSP,
3279        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
3280        // (bitconvert:{ *:[v2i16] } GPR32:{ *:[i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i16] } GPR32:{ *:[i32] }:$src, DSPR:{ *:[i32] })
3281        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3282        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::DSPRRegClassID,
3283        // GIR_Coverage, 1871,
3284        GIR_Done,
3285      // Label 322: @5690
3286      GIM_Try, /*On fail goto*//*Label 323*/ 5707, // Rule ID 1875 //
3287        GIM_CheckFeatures, GIFBS_HasDSP,
3288        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
3289        // (bitconvert:{ *:[v2i16] } FGR32:{ *:[f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i16] } FGR32:{ *:[f32] }:$src, DSPR:{ *:[i32] })
3290        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3291        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::DSPRRegClassID,
3292        // GIR_Coverage, 1875,
3293        GIR_Done,
3294      // Label 323: @5707
3295      GIM_Reject,
3296    // Label 321: @5708
3297    GIM_Reject,
3298    // Label 302: @5709
3299    GIM_Try, /*On fail goto*//*Label 324*/ 5730, // Rule ID 1956 //
3300      GIM_CheckFeatures, GIFBS_HasMSA,
3301      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3302      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3303      // (bitconvert:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$src, MSA128D:{ *:[i32] })
3304      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3305      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128DRegClassID,
3306      // GIR_Coverage, 1956,
3307      GIR_Done,
3308    // Label 324: @5730
3309    GIM_Try, /*On fail goto*//*Label 325*/ 5751, // Rule ID 1959 //
3310      GIM_CheckFeatures, GIFBS_HasMSA,
3311      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3312      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3313      // (bitconvert:{ *:[v2f64] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } v2i64:{ *:[v2i64] }:$src, MSA128D:{ *:[i32] })
3314      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3315      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128DRegClassID,
3316      // GIR_Coverage, 1959,
3317      GIR_Done,
3318    // Label 325: @5751
3319    GIM_Try, /*On fail goto*//*Label 326*/ 5772, // Rule ID 1976 //
3320      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3321      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3322      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3323      // (bitconvert:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$src, MSA128D:{ *:[i32] })
3324      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3325      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128DRegClassID,
3326      // GIR_Coverage, 1976,
3327      GIR_Done,
3328    // Label 326: @5772
3329    GIM_Try, /*On fail goto*//*Label 327*/ 5793, // Rule ID 1977 //
3330      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3331      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3332      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3333      // (bitconvert:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$src, MSA128D:{ *:[i32] })
3334      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3335      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128DRegClassID,
3336      // GIR_Coverage, 1977,
3337      GIR_Done,
3338    // Label 327: @5793
3339    GIM_Try, /*On fail goto*//*Label 328*/ 5814, // Rule ID 1978 //
3340      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3341      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3342      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3343      // (bitconvert:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$src, MSA128D:{ *:[i32] })
3344      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3345      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128DRegClassID,
3346      // GIR_Coverage, 1978,
3347      GIR_Done,
3348    // Label 328: @5814
3349    GIM_Try, /*On fail goto*//*Label 329*/ 5835, // Rule ID 1979 //
3350      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3351      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3352      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3353      // (bitconvert:{ *:[v2i64] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } v8f16:{ *:[v8f16] }:$src, MSA128D:{ *:[i32] })
3354      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3355      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128DRegClassID,
3356      // GIR_Coverage, 1979,
3357      GIR_Done,
3358    // Label 329: @5835
3359    GIM_Try, /*On fail goto*//*Label 330*/ 5856, // Rule ID 1980 //
3360      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3361      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3362      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3363      // (bitconvert:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$src, MSA128D:{ *:[i32] })
3364      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3365      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128DRegClassID,
3366      // GIR_Coverage, 1980,
3367      GIR_Done,
3368    // Label 330: @5856
3369    GIM_Try, /*On fail goto*//*Label 331*/ 5877, // Rule ID 1986 //
3370      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3371      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3372      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3373      // (bitconvert:{ *:[v2f64] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } v16i8:{ *:[v16i8] }:$src, MSA128D:{ *:[i32] })
3374      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3375      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128DRegClassID,
3376      // GIR_Coverage, 1986,
3377      GIR_Done,
3378    // Label 331: @5877
3379    GIM_Try, /*On fail goto*//*Label 332*/ 5898, // Rule ID 1987 //
3380      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3381      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3382      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3383      // (bitconvert:{ *:[v2f64] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } v8i16:{ *:[v8i16] }:$src, MSA128D:{ *:[i32] })
3384      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3385      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128DRegClassID,
3386      // GIR_Coverage, 1987,
3387      GIR_Done,
3388    // Label 332: @5898
3389    GIM_Try, /*On fail goto*//*Label 333*/ 5919, // Rule ID 1988 //
3390      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3391      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3392      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3393      // (bitconvert:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$src, MSA128D:{ *:[i32] })
3394      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3395      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128DRegClassID,
3396      // GIR_Coverage, 1988,
3397      GIR_Done,
3398    // Label 333: @5919
3399    GIM_Try, /*On fail goto*//*Label 334*/ 5940, // Rule ID 1989 //
3400      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3401      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3402      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3403      // (bitconvert:{ *:[v2f64] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } v8f16:{ *:[v8f16] }:$src, MSA128D:{ *:[i32] })
3404      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3405      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128DRegClassID,
3406      // GIR_Coverage, 1989,
3407      GIR_Done,
3408    // Label 334: @5940
3409    GIM_Try, /*On fail goto*//*Label 335*/ 5961, // Rule ID 1990 //
3410      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3411      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3412      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3413      // (bitconvert:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$src, MSA128D:{ *:[i32] })
3414      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3415      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128DRegClassID,
3416      // GIR_Coverage, 1990,
3417      GIR_Done,
3418    // Label 335: @5961
3419    GIM_Try, /*On fail goto*//*Label 336*/ 6061, // Rule ID 1995 //
3420      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3421      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3422      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3423      // (bitconvert:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
3424      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3425      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3426      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
3427      GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
3428      GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
3429      GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
3430      GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
3431      GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
3432      GIR_BuildMI, /*InsnID*/3, /*Opcode*/Mips::SHF_B,
3433      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
3434      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
3435      GIR_AddImm, /*InsnID*/3, /*Imm*/27,
3436      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
3437      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3438      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3439      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
3440      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3441      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3442      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3443      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3444      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3445      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3446      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3447      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3448      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3449      GIR_EraseFromParent, /*InsnID*/0,
3450      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128DRegClassID,
3451      // GIR_Coverage, 1995,
3452      GIR_Done,
3453    // Label 336: @6061
3454    GIM_Try, /*On fail goto*//*Label 337*/ 6161, // Rule ID 1996 //
3455      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3456      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3457      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3458      // (bitconvert:{ *:[v2f64] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
3459      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3460      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3461      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
3462      GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
3463      GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
3464      GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
3465      GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
3466      GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
3467      GIR_BuildMI, /*InsnID*/3, /*Opcode*/Mips::SHF_B,
3468      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
3469      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
3470      GIR_AddImm, /*InsnID*/3, /*Imm*/27,
3471      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
3472      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3473      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3474      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
3475      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3476      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3477      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3478      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3479      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3480      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3481      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3482      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3483      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3484      GIR_EraseFromParent, /*InsnID*/0,
3485      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128DRegClassID,
3486      // GIR_Coverage, 1996,
3487      GIR_Done,
3488    // Label 337: @6161
3489    GIM_Try, /*On fail goto*//*Label 338*/ 6226, // Rule ID 2000 //
3490      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3491      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3492      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3493      // (bitconvert:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
3494      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3495      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3496      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3497      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3498      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3499      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3500      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3501      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3502      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3503      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3504      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3505      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3506      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3507      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3508      GIR_EraseFromParent, /*InsnID*/0,
3509      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128DRegClassID,
3510      // GIR_Coverage, 2000,
3511      GIR_Done,
3512    // Label 338: @6226
3513    GIM_Try, /*On fail goto*//*Label 339*/ 6291, // Rule ID 2001 //
3514      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3515      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3516      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3517      // (bitconvert:{ *:[v2f64] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
3518      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3519      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3520      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3521      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3522      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3523      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3524      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3525      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3526      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3527      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3528      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3529      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3530      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3531      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3532      GIR_EraseFromParent, /*InsnID*/0,
3533      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128DRegClassID,
3534      // GIR_Coverage, 2001,
3535      GIR_Done,
3536    // Label 339: @6291
3537    GIM_Try, /*On fail goto*//*Label 340*/ 6356, // Rule ID 2005 //
3538      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3539      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3540      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3541      // (bitconvert:{ *:[v2i64] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
3542      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3543      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3544      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3545      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3546      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3547      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3548      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3549      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3550      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3551      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3552      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3553      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3554      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3555      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3556      GIR_EraseFromParent, /*InsnID*/0,
3557      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128DRegClassID,
3558      // GIR_Coverage, 2005,
3559      GIR_Done,
3560    // Label 340: @6356
3561    GIM_Try, /*On fail goto*//*Label 341*/ 6421, // Rule ID 2006 //
3562      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3563      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3564      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3565      // (bitconvert:{ *:[v2f64] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
3566      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3567      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3568      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3569      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3570      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3571      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3572      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3573      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3574      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3575      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3576      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3577      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3578      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3579      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3580      GIR_EraseFromParent, /*InsnID*/0,
3581      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128DRegClassID,
3582      // GIR_Coverage, 2006,
3583      GIR_Done,
3584    // Label 341: @6421
3585    GIM_Try, /*On fail goto*//*Label 342*/ 6486, // Rule ID 2010 //
3586      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3587      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3588      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3589      // (bitconvert:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
3590      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3591      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3592      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3593      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3594      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3595      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3596      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3597      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3598      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3599      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3600      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3601      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3602      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3603      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3604      GIR_EraseFromParent, /*InsnID*/0,
3605      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128DRegClassID,
3606      // GIR_Coverage, 2010,
3607      GIR_Done,
3608    // Label 342: @6486
3609    GIM_Try, /*On fail goto*//*Label 343*/ 6551, // Rule ID 2011 //
3610      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3611      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3612      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3613      // (bitconvert:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
3614      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3615      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3616      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3617      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3618      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3619      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3620      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3621      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3622      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3623      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3624      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3625      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3626      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3627      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3628      GIR_EraseFromParent, /*InsnID*/0,
3629      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128DRegClassID,
3630      // GIR_Coverage, 2011,
3631      GIR_Done,
3632    // Label 343: @6551
3633    GIM_Try, /*On fail goto*//*Label 344*/ 6616, // Rule ID 2015 //
3634      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3635      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3636      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3637      // (bitconvert:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
3638      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3639      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3640      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3641      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3642      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3643      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3644      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3645      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3646      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3647      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3648      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3649      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3650      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3651      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3652      GIR_EraseFromParent, /*InsnID*/0,
3653      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128DRegClassID,
3654      // GIR_Coverage, 2015,
3655      GIR_Done,
3656    // Label 344: @6616
3657    GIM_Try, /*On fail goto*//*Label 345*/ 6681, // Rule ID 2016 //
3658      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3659      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3660      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3661      // (bitconvert:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
3662      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3663      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3664      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3665      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3666      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3667      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3668      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3669      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3670      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3671      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3672      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3673      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3674      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3675      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3676      GIR_EraseFromParent, /*InsnID*/0,
3677      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128DRegClassID,
3678      // GIR_Coverage, 2016,
3679      GIR_Done,
3680    // Label 345: @6681
3681    GIM_Reject,
3682    // Label 303: @6682
3683    GIM_Try, /*On fail goto*//*Label 346*/ 6727,
3684      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3685      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
3686      GIM_Try, /*On fail goto*//*Label 347*/ 6709, // Rule ID 1872 //
3687        GIM_CheckFeatures, GIFBS_HasDSP,
3688        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
3689        // (bitconvert:{ *:[v4i8] } GPR32:{ *:[i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i8] } GPR32:{ *:[i32] }:$src, DSPR:{ *:[i32] })
3690        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3691        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::DSPRRegClassID,
3692        // GIR_Coverage, 1872,
3693        GIR_Done,
3694      // Label 347: @6709
3695      GIM_Try, /*On fail goto*//*Label 348*/ 6726, // Rule ID 1876 //
3696        GIM_CheckFeatures, GIFBS_HasDSP,
3697        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
3698        // (bitconvert:{ *:[v4i8] } FGR32:{ *:[f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i8] } FGR32:{ *:[f32] }:$src, DSPR:{ *:[i32] })
3699        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3700        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::DSPRRegClassID,
3701        // GIR_Coverage, 1876,
3702        GIR_Done,
3703      // Label 348: @6726
3704      GIM_Reject,
3705    // Label 346: @6727
3706    GIM_Reject,
3707    // Label 304: @6728
3708    GIM_Try, /*On fail goto*//*Label 349*/ 6749, // Rule ID 1955 //
3709      GIM_CheckFeatures, GIFBS_HasMSA,
3710      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3711      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3712      // (bitconvert:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, MSA128W:{ *:[i32] })
3713      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3714      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128WRegClassID,
3715      // GIR_Coverage, 1955,
3716      GIR_Done,
3717    // Label 349: @6749
3718    GIM_Try, /*On fail goto*//*Label 350*/ 6770, // Rule ID 1958 //
3719      GIM_CheckFeatures, GIFBS_HasMSA,
3720      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3721      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3722      // (bitconvert:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src, MSA128W:{ *:[i32] })
3723      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3724      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128WRegClassID,
3725      // GIR_Coverage, 1958,
3726      GIR_Done,
3727    // Label 350: @6770
3728    GIM_Try, /*On fail goto*//*Label 351*/ 6791, // Rule ID 1971 //
3729      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3730      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3731      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3732      // (bitconvert:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$src, MSA128W:{ *:[i32] })
3733      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3734      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128WRegClassID,
3735      // GIR_Coverage, 1971,
3736      GIR_Done,
3737    // Label 351: @6791
3738    GIM_Try, /*On fail goto*//*Label 352*/ 6812, // Rule ID 1972 //
3739      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3740      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3741      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3742      // (bitconvert:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$src, MSA128W:{ *:[i32] })
3743      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3744      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128WRegClassID,
3745      // GIR_Coverage, 1972,
3746      GIR_Done,
3747    // Label 352: @6812
3748    GIM_Try, /*On fail goto*//*Label 353*/ 6833, // Rule ID 1973 //
3749      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3750      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3751      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3752      // (bitconvert:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] })
3753      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3754      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128WRegClassID,
3755      // GIR_Coverage, 1973,
3756      GIR_Done,
3757    // Label 353: @6833
3758    GIM_Try, /*On fail goto*//*Label 354*/ 6854, // Rule ID 1974 //
3759      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3760      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3761      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3762      // (bitconvert:{ *:[v4i32] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } v8f16:{ *:[v8f16] }:$src, MSA128W:{ *:[i32] })
3763      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3764      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128WRegClassID,
3765      // GIR_Coverage, 1974,
3766      GIR_Done,
3767    // Label 354: @6854
3768    GIM_Try, /*On fail goto*//*Label 355*/ 6875, // Rule ID 1975 //
3769      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3770      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3771      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3772      // (bitconvert:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] })
3773      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3774      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128WRegClassID,
3775      // GIR_Coverage, 1975,
3776      GIR_Done,
3777    // Label 355: @6875
3778    GIM_Try, /*On fail goto*//*Label 356*/ 6896, // Rule ID 1981 //
3779      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3780      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3781      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3782      // (bitconvert:{ *:[v4f32] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } v16i8:{ *:[v16i8] }:$src, MSA128W:{ *:[i32] })
3783      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3784      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128WRegClassID,
3785      // GIR_Coverage, 1981,
3786      GIR_Done,
3787    // Label 356: @6896
3788    GIM_Try, /*On fail goto*//*Label 357*/ 6917, // Rule ID 1982 //
3789      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3790      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3791      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3792      // (bitconvert:{ *:[v4f32] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } v8i16:{ *:[v8i16] }:$src, MSA128W:{ *:[i32] })
3793      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3794      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128WRegClassID,
3795      // GIR_Coverage, 1982,
3796      GIR_Done,
3797    // Label 357: @6917
3798    GIM_Try, /*On fail goto*//*Label 358*/ 6938, // Rule ID 1983 //
3799      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3800      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3801      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3802      // (bitconvert:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] })
3803      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3804      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128WRegClassID,
3805      // GIR_Coverage, 1983,
3806      GIR_Done,
3807    // Label 358: @6938
3808    GIM_Try, /*On fail goto*//*Label 359*/ 6959, // Rule ID 1984 //
3809      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3810      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3811      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3812      // (bitconvert:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src, MSA128W:{ *:[i32] })
3813      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3814      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128WRegClassID,
3815      // GIR_Coverage, 1984,
3816      GIR_Done,
3817    // Label 359: @6959
3818    GIM_Try, /*On fail goto*//*Label 360*/ 6980, // Rule ID 1985 //
3819      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3820      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3821      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3822      // (bitconvert:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] })
3823      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3824      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128WRegClassID,
3825      // GIR_Coverage, 1985,
3826      GIR_Done,
3827    // Label 360: @6980
3828    GIM_Try, /*On fail goto*//*Label 361*/ 7045, // Rule ID 1993 //
3829      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3830      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3831      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3832      // (bitconvert:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] })
3833      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
3834      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
3835      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3836      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3837      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3838      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3839      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
3840      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3841      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3842      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3843      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3844      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3845      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3846      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3847      GIR_EraseFromParent, /*InsnID*/0,
3848      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128WRegClassID,
3849      // GIR_Coverage, 1993,
3850      GIR_Done,
3851    // Label 361: @7045
3852    GIM_Try, /*On fail goto*//*Label 362*/ 7110, // Rule ID 1994 //
3853      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3854      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3855      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3856      // (bitconvert:{ *:[v4f32] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] })
3857      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
3858      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
3859      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3860      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3861      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3862      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3863      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
3864      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3865      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3866      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3867      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3868      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3869      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3870      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3871      GIR_EraseFromParent, /*InsnID*/0,
3872      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128WRegClassID,
3873      // GIR_Coverage, 1994,
3874      GIR_Done,
3875    // Label 362: @7110
3876    GIM_Try, /*On fail goto*//*Label 363*/ 7175, // Rule ID 1998 //
3877      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3878      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3879      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3880      // (bitconvert:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3881      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3882      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3883      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3884      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3885      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3886      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3887      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3888      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3889      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3890      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3891      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3892      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3893      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3894      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3895      GIR_EraseFromParent, /*InsnID*/0,
3896      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128WRegClassID,
3897      // GIR_Coverage, 1998,
3898      GIR_Done,
3899    // Label 363: @7175
3900    GIM_Try, /*On fail goto*//*Label 364*/ 7240, // Rule ID 1999 //
3901      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3902      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3903      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3904      // (bitconvert:{ *:[v4f32] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3905      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3906      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3907      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3908      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3909      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3910      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3911      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3912      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3913      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3914      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3915      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3916      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3917      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3918      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3919      GIR_EraseFromParent, /*InsnID*/0,
3920      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128WRegClassID,
3921      // GIR_Coverage, 1999,
3922      GIR_Done,
3923    // Label 364: @7240
3924    GIM_Try, /*On fail goto*//*Label 365*/ 7305, // Rule ID 2003 //
3925      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3926      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3927      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3928      // (bitconvert:{ *:[v4i32] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3929      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3930      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3931      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3932      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3933      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3934      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3935      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3936      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3937      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3938      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3939      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3940      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3941      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3942      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3943      GIR_EraseFromParent, /*InsnID*/0,
3944      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128WRegClassID,
3945      // GIR_Coverage, 2003,
3946      GIR_Done,
3947    // Label 365: @7305
3948    GIM_Try, /*On fail goto*//*Label 366*/ 7370, // Rule ID 2004 //
3949      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3950      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3951      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3952      // (bitconvert:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3953      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3954      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3955      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3956      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3957      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3958      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3959      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3960      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3961      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3962      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3963      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3964      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3965      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3966      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3967      GIR_EraseFromParent, /*InsnID*/0,
3968      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128WRegClassID,
3969      // GIR_Coverage, 2004,
3970      GIR_Done,
3971    // Label 366: @7370
3972    GIM_Try, /*On fail goto*//*Label 367*/ 7435, // Rule ID 2020 //
3973      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3974      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3975      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3976      // (bitconvert:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3977      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3978      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3979      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3980      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3981      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3982      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3983      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3984      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3985      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3986      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3987      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3988      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3989      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3990      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3991      GIR_EraseFromParent, /*InsnID*/0,
3992      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128WRegClassID,
3993      // GIR_Coverage, 2020,
3994      GIR_Done,
3995    // Label 367: @7435
3996    GIM_Try, /*On fail goto*//*Label 368*/ 7500, // Rule ID 2021 //
3997      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3998      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3999      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
4000      // (bitconvert:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
4001      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
4002      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
4003      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4004      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4005      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4006      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4007      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
4008      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4009      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4010      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
4011      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4012      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4013      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4014      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4015      GIR_EraseFromParent, /*InsnID*/0,
4016      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128WRegClassID,
4017      // GIR_Coverage, 2021,
4018      GIR_Done,
4019    // Label 368: @7500
4020    GIM_Try, /*On fail goto*//*Label 369*/ 7565, // Rule ID 2025 //
4021      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4022      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
4023      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
4024      // (bitconvert:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
4025      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
4026      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
4027      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4028      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4029      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4030      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4031      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
4032      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4033      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4034      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
4035      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4036      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4037      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4038      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4039      GIR_EraseFromParent, /*InsnID*/0,
4040      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128WRegClassID,
4041      // GIR_Coverage, 2025,
4042      GIR_Done,
4043    // Label 369: @7565
4044    GIM_Try, /*On fail goto*//*Label 370*/ 7630, // Rule ID 2026 //
4045      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4046      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
4047      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
4048      // (bitconvert:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
4049      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
4050      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
4051      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4052      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4053      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4054      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4055      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
4056      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4057      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4058      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
4059      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4060      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4061      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4062      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4063      GIR_EraseFromParent, /*InsnID*/0,
4064      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128WRegClassID,
4065      // GIR_Coverage, 2026,
4066      GIR_Done,
4067    // Label 370: @7630
4068    GIM_Reject,
4069    // Label 305: @7631
4070    GIM_Try, /*On fail goto*//*Label 371*/ 7652, // Rule ID 1954 //
4071      GIM_CheckFeatures, GIFBS_HasMSA,
4072      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
4073      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
4074      // (bitconvert:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] })
4075      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
4076      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128HRegClassID,
4077      // GIR_Coverage, 1954,
4078      GIR_Done,
4079    // Label 371: @7652
4080    GIM_Try, /*On fail goto*//*Label 372*/ 7673, // Rule ID 1957 //
4081      GIM_CheckFeatures, GIFBS_HasMSA,
4082      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
4083      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
4084      // (bitconvert:{ *:[v8f16] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8f16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] })
4085      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
4086      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128HRegClassID,
4087      // GIR_Coverage, 1957,
4088      GIR_Done,
4089    // Label 372: @7673
4090    GIM_Try, /*On fail goto*//*Label 373*/ 7694, // Rule ID 1966 //
4091      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
4092      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
4093      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
4094      // (bitconvert:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$src, MSA128H:{ *:[i32] })
4095      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
4096      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128HRegClassID,
4097      // GIR_Coverage, 1966,
4098      GIR_Done,
4099    // Label 373: @7694
4100    GIM_Try, /*On fail goto*//*Label 374*/ 7715, // Rule ID 1967 //
4101      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
4102      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
4103      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
4104      // (bitconvert:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src, MSA128H:{ *:[i32] })
4105      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
4106      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128HRegClassID,
4107      // GIR_Coverage, 1967,
4108      GIR_Done,
4109    // Label 374: @7715
4110    GIM_Try, /*On fail goto*//*Label 375*/ 7736, // Rule ID 1968 //
4111      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
4112      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
4113      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
4114      // (bitconvert:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src, MSA128H:{ *:[i32] })
4115      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
4116      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128HRegClassID,
4117      // GIR_Coverage, 1968,
4118      GIR_Done,
4119    // Label 375: @7736
4120    GIM_Try, /*On fail goto*//*Label 376*/ 7757, // Rule ID 1969 //
4121      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
4122      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
4123      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
4124      // (bitconvert:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src, MSA128H:{ *:[i32] })
4125      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
4126      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128HRegClassID,
4127      // GIR_Coverage, 1969,
4128      GIR_Done,
4129    // Label 376: @7757
4130    GIM_Try, /*On fail goto*//*Label 377*/ 7778, // Rule ID 1970 //
4131      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
4132      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
4133      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
4134      // (bitconvert:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src, MSA128H:{ *:[i32] })
4135      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
4136      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128HRegClassID,
4137      // GIR_Coverage, 1970,
4138      GIR_Done,
4139    // Label 377: @7778
4140    GIM_Try, /*On fail goto*//*Label 378*/ 7843, // Rule ID 1991 //
4141      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4142      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
4143      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
4144      // (bitconvert:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
4145      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
4146      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
4147      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4148      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4149      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4150      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4151      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
4152      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4153      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4154      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
4155      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4156      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4157      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4158      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4159      GIR_EraseFromParent, /*InsnID*/0,
4160      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128HRegClassID,
4161      // GIR_Coverage, 1991,
4162      GIR_Done,
4163    // Label 378: @7843
4164    GIM_Try, /*On fail goto*//*Label 379*/ 7908, // Rule ID 1992 //
4165      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4166      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
4167      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
4168      // (bitconvert:{ *:[v8f16] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
4169      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
4170      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
4171      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4172      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4173      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4174      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4175      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
4176      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4177      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4178      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
4179      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4180      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4181      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4182      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4183      GIR_EraseFromParent, /*InsnID*/0,
4184      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128HRegClassID,
4185      // GIR_Coverage, 1992,
4186      GIR_Done,
4187    // Label 379: @7908
4188    GIM_Try, /*On fail goto*//*Label 380*/ 7973, // Rule ID 2008 //
4189      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4190      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
4191      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
4192      // (bitconvert:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
4193      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
4194      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
4195      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4196      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4197      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4198      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4199      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
4200      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4201      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4202      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
4203      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4204      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4205      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4206      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4207      GIR_EraseFromParent, /*InsnID*/0,
4208      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128HRegClassID,
4209      // GIR_Coverage, 2008,
4210      GIR_Done,
4211    // Label 380: @7973
4212    GIM_Try, /*On fail goto*//*Label 381*/ 8038, // Rule ID 2009 //
4213      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4214      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
4215      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
4216      // (bitconvert:{ *:[v8f16] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
4217      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
4218      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
4219      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4220      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4221      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4222      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4223      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
4224      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4225      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4226      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
4227      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4228      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4229      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4230      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4231      GIR_EraseFromParent, /*InsnID*/0,
4232      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128HRegClassID,
4233      // GIR_Coverage, 2009,
4234      GIR_Done,
4235    // Label 381: @8038
4236    GIM_Try, /*On fail goto*//*Label 382*/ 8103, // Rule ID 2013 //
4237      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4238      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
4239      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
4240      // (bitconvert:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
4241      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
4242      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
4243      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4244      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4245      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4246      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4247      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
4248      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4249      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4250      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
4251      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4252      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4253      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4254      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4255      GIR_EraseFromParent, /*InsnID*/0,
4256      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128HRegClassID,
4257      // GIR_Coverage, 2013,
4258      GIR_Done,
4259    // Label 382: @8103
4260    GIM_Try, /*On fail goto*//*Label 383*/ 8168, // Rule ID 2014 //
4261      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4262      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
4263      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
4264      // (bitconvert:{ *:[v8f16] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
4265      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
4266      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
4267      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4268      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4269      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4270      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4271      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
4272      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4273      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4274      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
4275      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4276      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4277      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4278      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4279      GIR_EraseFromParent, /*InsnID*/0,
4280      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128HRegClassID,
4281      // GIR_Coverage, 2014,
4282      GIR_Done,
4283    // Label 383: @8168
4284    GIM_Try, /*On fail goto*//*Label 384*/ 8233, // Rule ID 2018 //
4285      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4286      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
4287      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
4288      // (bitconvert:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
4289      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
4290      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
4291      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4292      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4293      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4294      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4295      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
4296      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4297      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4298      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
4299      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4300      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4301      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4302      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4303      GIR_EraseFromParent, /*InsnID*/0,
4304      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128HRegClassID,
4305      // GIR_Coverage, 2018,
4306      GIR_Done,
4307    // Label 384: @8233
4308    GIM_Try, /*On fail goto*//*Label 385*/ 8298, // Rule ID 2019 //
4309      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4310      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
4311      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
4312      // (bitconvert:{ *:[v8f16] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
4313      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
4314      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
4315      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4316      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4317      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4318      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4319      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
4320      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4321      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4322      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
4323      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4324      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4325      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4326      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4327      GIR_EraseFromParent, /*InsnID*/0,
4328      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128HRegClassID,
4329      // GIR_Coverage, 2019,
4330      GIR_Done,
4331    // Label 385: @8298
4332    GIM_Try, /*On fail goto*//*Label 386*/ 8363, // Rule ID 2023 //
4333      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4334      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
4335      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
4336      // (bitconvert:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
4337      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
4338      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
4339      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4340      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4341      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4342      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4343      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
4344      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4345      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4346      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
4347      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4348      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4349      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4350      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4351      GIR_EraseFromParent, /*InsnID*/0,
4352      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128HRegClassID,
4353      // GIR_Coverage, 2023,
4354      GIR_Done,
4355    // Label 386: @8363
4356    GIM_Try, /*On fail goto*//*Label 387*/ 8428, // Rule ID 2024 //
4357      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4358      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
4359      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
4360      // (bitconvert:{ *:[v8f16] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
4361      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
4362      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
4363      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4364      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4365      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4366      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4367      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
4368      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4369      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4370      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
4371      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4372      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4373      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4374      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4375      GIR_EraseFromParent, /*InsnID*/0,
4376      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128HRegClassID,
4377      // GIR_Coverage, 2024,
4378      GIR_Done,
4379    // Label 387: @8428
4380    GIM_Reject,
4381    // Label 306: @8429
4382    GIM_Try, /*On fail goto*//*Label 388*/ 8450, // Rule ID 1960 //
4383      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
4384      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
4385      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4386      // (bitconvert:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src, MSA128B:{ *:[i32] })
4387      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
4388      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128BRegClassID,
4389      // GIR_Coverage, 1960,
4390      GIR_Done,
4391    // Label 388: @8450
4392    GIM_Try, /*On fail goto*//*Label 389*/ 8471, // Rule ID 1961 //
4393      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
4394      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
4395      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4396      // (bitconvert:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src, MSA128B:{ *:[i32] })
4397      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
4398      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128BRegClassID,
4399      // GIR_Coverage, 1961,
4400      GIR_Done,
4401    // Label 389: @8471
4402    GIM_Try, /*On fail goto*//*Label 390*/ 8492, // Rule ID 1962 //
4403      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
4404      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
4405      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4406      // (bitconvert:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src, MSA128B:{ *:[i32] })
4407      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
4408      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128BRegClassID,
4409      // GIR_Coverage, 1962,
4410      GIR_Done,
4411    // Label 390: @8492
4412    GIM_Try, /*On fail goto*//*Label 391*/ 8513, // Rule ID 1963 //
4413      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
4414      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
4415      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4416      // (bitconvert:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src, MSA128B:{ *:[i32] })
4417      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
4418      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128BRegClassID,
4419      // GIR_Coverage, 1963,
4420      GIR_Done,
4421    // Label 391: @8513
4422    GIM_Try, /*On fail goto*//*Label 392*/ 8534, // Rule ID 1964 //
4423      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
4424      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
4425      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4426      // (bitconvert:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src, MSA128B:{ *:[i32] })
4427      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
4428      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128BRegClassID,
4429      // GIR_Coverage, 1964,
4430      GIR_Done,
4431    // Label 392: @8534
4432    GIM_Try, /*On fail goto*//*Label 393*/ 8555, // Rule ID 1965 //
4433      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
4434      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
4435      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4436      // (bitconvert:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src, MSA128B:{ *:[i32] })
4437      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
4438      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128BRegClassID,
4439      // GIR_Coverage, 1965,
4440      GIR_Done,
4441    // Label 393: @8555
4442    GIM_Try, /*On fail goto*//*Label 394*/ 8620, // Rule ID 1997 //
4443      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4444      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
4445      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4446      // (bitconvert:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
4447      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
4448      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
4449      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4450      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4451      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4452      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4453      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
4454      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4455      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4456      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
4457      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4458      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4459      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4460      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4461      GIR_EraseFromParent, /*InsnID*/0,
4462      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128BRegClassID,
4463      // GIR_Coverage, 1997,
4464      GIR_Done,
4465    // Label 394: @8620
4466    GIM_Try, /*On fail goto*//*Label 395*/ 8685, // Rule ID 2002 //
4467      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4468      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
4469      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4470      // (bitconvert:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
4471      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
4472      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
4473      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4474      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4475      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4476      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4477      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
4478      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4479      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4480      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
4481      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4482      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4483      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4484      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4485      GIR_EraseFromParent, /*InsnID*/0,
4486      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128BRegClassID,
4487      // GIR_Coverage, 2002,
4488      GIR_Done,
4489    // Label 395: @8685
4490    GIM_Try, /*On fail goto*//*Label 396*/ 8750, // Rule ID 2007 //
4491      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4492      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
4493      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4494      // (bitconvert:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128B:{ *:[i32] })
4495      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
4496      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
4497      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4498      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4499      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4500      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4501      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
4502      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4503      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4504      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
4505      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4506      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4507      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4508      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4509      GIR_EraseFromParent, /*InsnID*/0,
4510      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128BRegClassID,
4511      // GIR_Coverage, 2007,
4512      GIR_Done,
4513    // Label 396: @8750
4514    GIM_Try, /*On fail goto*//*Label 397*/ 8815, // Rule ID 2012 //
4515      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4516      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
4517      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4518      // (bitconvert:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128B:{ *:[i32] })
4519      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
4520      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
4521      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4522      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4523      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4524      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4525      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
4526      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4527      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4528      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
4529      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4530      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4531      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4532      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4533      GIR_EraseFromParent, /*InsnID*/0,
4534      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128BRegClassID,
4535      // GIR_Coverage, 2012,
4536      GIR_Done,
4537    // Label 397: @8815
4538    GIM_Try, /*On fail goto*//*Label 398*/ 8915, // Rule ID 2017 //
4539      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4540      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
4541      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4542      // (bitconvert:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
4543      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
4544      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
4545      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
4546      GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
4547      GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
4548      GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
4549      GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
4550      GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
4551      GIR_BuildMI, /*InsnID*/3, /*Opcode*/Mips::SHF_B,
4552      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
4553      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
4554      GIR_AddImm, /*InsnID*/3, /*Imm*/27,
4555      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
4556      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4557      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4558      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
4559      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4560      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
4561      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4562      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4563      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
4564      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4565      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4566      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4567      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4568      GIR_EraseFromParent, /*InsnID*/0,
4569      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128BRegClassID,
4570      // GIR_Coverage, 2017,
4571      GIR_Done,
4572    // Label 398: @8915
4573    GIM_Try, /*On fail goto*//*Label 399*/ 9015, // Rule ID 2022 //
4574      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4575      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
4576      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4577      // (bitconvert:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
4578      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
4579      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
4580      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
4581      GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
4582      GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
4583      GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
4584      GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
4585      GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
4586      GIR_BuildMI, /*InsnID*/3, /*Opcode*/Mips::SHF_B,
4587      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
4588      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
4589      GIR_AddImm, /*InsnID*/3, /*Imm*/27,
4590      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
4591      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4592      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4593      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
4594      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4595      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
4596      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4597      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4598      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
4599      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4600      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4601      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4602      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4603      GIR_EraseFromParent, /*InsnID*/0,
4604      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128BRegClassID,
4605      // GIR_Coverage, 2022,
4606      GIR_Done,
4607    // Label 399: @9015
4608    GIM_Reject,
4609    // Label 307: @9016
4610    GIM_Reject,
4611    // Label 13: @9017
4612    GIM_Try, /*On fail goto*//*Label 400*/ 9082, // Rule ID 1945 //
4613      GIM_CheckFeatures, GIFBS_HasDSP,
4614      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4615      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
4616      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
4617      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
4618      // MIs[0] Operand 1
4619      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
4620      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4621      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
4622      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4623      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4624      GIM_CheckIsSafeToFold, /*InsnID*/1,
4625      // (ld:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LWX:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index)
4626      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LWX,
4627      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4628      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // base
4629      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // index
4630      GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
4631      GIR_EraseFromParent, /*InsnID*/0,
4632      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4633      // GIR_Coverage, 1945,
4634      GIR_Done,
4635    // Label 400: @9082
4636    GIM_Reject,
4637    // Label 14: @9083
4638    GIM_Try, /*On fail goto*//*Label 401*/ 9148, // Rule ID 1944 //
4639      GIM_CheckFeatures, GIFBS_HasDSP,
4640      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4641      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2,
4642      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
4643      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
4644      // MIs[0] Operand 1
4645      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
4646      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4647      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
4648      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4649      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4650      GIM_CheckIsSafeToFold, /*InsnID*/1,
4651      // (ld:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>  =>  (LHX:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index)
4652      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LHX,
4653      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4654      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // base
4655      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // index
4656      GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
4657      GIR_EraseFromParent, /*InsnID*/0,
4658      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4659      // GIR_Coverage, 1944,
4660      GIR_Done,
4661    // Label 401: @9148
4662    GIM_Reject,
4663    // Label 15: @9149
4664    GIM_Try, /*On fail goto*//*Label 402*/ 9214, // Rule ID 1943 //
4665      GIM_CheckFeatures, GIFBS_HasDSP,
4666      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4667      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1,
4668      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
4669      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
4670      // MIs[0] Operand 1
4671      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
4672      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4673      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
4674      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4675      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4676      GIM_CheckIsSafeToFold, /*InsnID*/1,
4677      // (ld:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>  =>  (LBUX:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index)
4678      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LBUX,
4679      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4680      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // base
4681      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // index
4682      GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
4683      GIR_EraseFromParent, /*InsnID*/0,
4684      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4685      // GIR_Coverage, 1943,
4686      GIR_Done,
4687    // Label 402: @9214
4688    GIM_Reject,
4689    // Label 16: @9215
4690    GIM_Try, /*On fail goto*//*Label 403*/ 11409,
4691      GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
4692      GIM_Try, /*On fail goto*//*Label 404*/ 9267, // Rule ID 416 //
4693        GIM_CheckFeatures, GIFBS_HasDSP,
4694        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_qb,
4695        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
4696        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4697        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4698        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4699        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
4700        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt8,
4701        // MIs[1] Operand 1
4702        // No operand predicates
4703        GIM_CheckIsSafeToFold, /*InsnID*/1,
4704        // (intrinsic_wo_chain:{ *:[v4i8] } 5395:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immZExt8>>:$imm)  =>  (REPL_QB:{ *:[v4i8] } (imm:{ *:[i32] }):$imm)
4705        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPL_QB,
4706        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4707        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
4708        GIR_EraseFromParent, /*InsnID*/0,
4709        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4710        // GIR_Coverage, 416,
4711        GIR_Done,
4712      // Label 404: @9267
4713      GIM_Try, /*On fail goto*//*Label 405*/ 9314, // Rule ID 417 //
4714        GIM_CheckFeatures, GIFBS_HasDSP,
4715        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_ph,
4716        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4717        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4718        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4719        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4720        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
4721        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immSExt10,
4722        // MIs[1] Operand 1
4723        // No operand predicates
4724        GIM_CheckIsSafeToFold, /*InsnID*/1,
4725        // (intrinsic_wo_chain:{ *:[v2i16] } 5394:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immSExt10>>:$imm)  =>  (REPL_PH:{ *:[v2i16] } (imm:{ *:[i32] }):$imm)
4726        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPL_PH,
4727        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4728        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
4729        GIR_EraseFromParent, /*InsnID*/0,
4730        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4731        // GIR_Coverage, 417,
4732        GIR_Done,
4733      // Label 405: @9314
4734      GIM_Try, /*On fail goto*//*Label 406*/ 9361, // Rule ID 1276 //
4735        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
4736        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_ph,
4737        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4738        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4739        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4740        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4741        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
4742        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immSExt10,
4743        // MIs[1] Operand 1
4744        // No operand predicates
4745        GIM_CheckIsSafeToFold, /*InsnID*/1,
4746        // (intrinsic_wo_chain:{ *:[v2i16] } 5394:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immSExt10>>:$imm)  =>  (REPL_PH_MM:{ *:[v2i16] } (imm:{ *:[i32] }):$imm)
4747        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPL_PH_MM,
4748        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4749        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
4750        GIR_EraseFromParent, /*InsnID*/0,
4751        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4752        // GIR_Coverage, 1276,
4753        GIR_Done,
4754      // Label 406: @9361
4755      GIM_Try, /*On fail goto*//*Label 407*/ 9408, // Rule ID 1277 //
4756        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
4757        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_qb,
4758        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
4759        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4760        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4761        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4762        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
4763        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt8,
4764        // MIs[1] Operand 1
4765        // No operand predicates
4766        GIM_CheckIsSafeToFold, /*InsnID*/1,
4767        // (intrinsic_wo_chain:{ *:[v4i8] } 5395:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immZExt8>>:$imm)  =>  (REPL_QB_MM:{ *:[v4i8] } (imm:{ *:[i32] }):$imm)
4768        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPL_QB_MM,
4769        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
4770        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
4771        GIR_EraseFromParent, /*InsnID*/0,
4772        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4773        // GIR_Coverage, 1277,
4774        GIR_Done,
4775      // Label 407: @9408
4776      GIM_Try, /*On fail goto*//*Label 408*/ 9448, // Rule ID 350 //
4777        GIM_CheckFeatures, GIFBS_HasDSP,
4778        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_raddu_w_qb,
4779        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4780        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4781        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
4782        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4783        // (intrinsic_wo_chain:{ *:[i32] } 5392:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs)  =>  (RADDU_W_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs)
4784        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::RADDU_W_QB,
4785        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4786        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
4787        GIR_EraseFromParent, /*InsnID*/0,
4788        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4789        // GIR_Coverage, 350,
4790        GIR_Done,
4791      // Label 408: @9448
4792      GIM_Try, /*On fail goto*//*Label 409*/ 9488, // Rule ID 357 //
4793        GIM_CheckFeatures, GIFBS_HasDSP,
4794        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceq_w_phl,
4795        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4796        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
4797        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
4798        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4799        // (intrinsic_wo_chain:{ *:[i32] } 5374:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (PRECEQ_W_PHL:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rt)
4800        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQ_W_PHL,
4801        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4802        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4803        GIR_EraseFromParent, /*InsnID*/0,
4804        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4805        // GIR_Coverage, 357,
4806        GIR_Done,
4807      // Label 409: @9488
4808      GIM_Try, /*On fail goto*//*Label 410*/ 9528, // Rule ID 358 //
4809        GIM_CheckFeatures, GIFBS_HasDSP,
4810        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceq_w_phr,
4811        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4812        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
4813        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
4814        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4815        // (intrinsic_wo_chain:{ *:[i32] } 5375:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (PRECEQ_W_PHR:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rt)
4816        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQ_W_PHR,
4817        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4818        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4819        GIR_EraseFromParent, /*InsnID*/0,
4820        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4821        // GIR_Coverage, 358,
4822        GIR_Done,
4823      // Label 410: @9528
4824      GIM_Try, /*On fail goto*//*Label 411*/ 9568, // Rule ID 359 //
4825        GIM_CheckFeatures, GIFBS_HasDSP,
4826        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbl,
4827        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4828        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4829        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4830        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4831        // (intrinsic_wo_chain:{ *:[v2i16] } 5376:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PRECEQU_PH_QBL:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
4832        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBL,
4833        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4834        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4835        GIR_EraseFromParent, /*InsnID*/0,
4836        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4837        // GIR_Coverage, 359,
4838        GIR_Done,
4839      // Label 411: @9568
4840      GIM_Try, /*On fail goto*//*Label 412*/ 9608, // Rule ID 360 //
4841        GIM_CheckFeatures, GIFBS_HasDSP,
4842        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbr,
4843        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4844        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4845        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4846        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4847        // (intrinsic_wo_chain:{ *:[v2i16] } 5378:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PRECEQU_PH_QBR:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
4848        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBR,
4849        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4850        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4851        GIR_EraseFromParent, /*InsnID*/0,
4852        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4853        // GIR_Coverage, 360,
4854        GIR_Done,
4855      // Label 412: @9608
4856      GIM_Try, /*On fail goto*//*Label 413*/ 9648, // Rule ID 361 //
4857        GIM_CheckFeatures, GIFBS_HasDSP,
4858        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbla,
4859        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4860        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4861        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4862        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4863        // (intrinsic_wo_chain:{ *:[v2i16] } 5377:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PRECEQU_PH_QBLA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
4864        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBLA,
4865        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4866        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4867        GIR_EraseFromParent, /*InsnID*/0,
4868        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4869        // GIR_Coverage, 361,
4870        GIR_Done,
4871      // Label 413: @9648
4872      GIM_Try, /*On fail goto*//*Label 414*/ 9688, // Rule ID 362 //
4873        GIM_CheckFeatures, GIFBS_HasDSP,
4874        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbra,
4875        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4876        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4877        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4878        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4879        // (intrinsic_wo_chain:{ *:[v2i16] } 5379:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PRECEQU_PH_QBRA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
4880        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBRA,
4881        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4882        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4883        GIR_EraseFromParent, /*InsnID*/0,
4884        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4885        // GIR_Coverage, 362,
4886        GIR_Done,
4887      // Label 414: @9688
4888      GIM_Try, /*On fail goto*//*Label 415*/ 9728, // Rule ID 363 //
4889        GIM_CheckFeatures, GIFBS_HasDSP,
4890        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbl,
4891        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4892        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4893        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4894        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4895        // (intrinsic_wo_chain:{ *:[v2i16] } 5380:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PRECEU_PH_QBL:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
4896        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBL,
4897        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4898        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4899        GIR_EraseFromParent, /*InsnID*/0,
4900        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4901        // GIR_Coverage, 363,
4902        GIR_Done,
4903      // Label 415: @9728
4904      GIM_Try, /*On fail goto*//*Label 416*/ 9768, // Rule ID 364 //
4905        GIM_CheckFeatures, GIFBS_HasDSP,
4906        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbr,
4907        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4908        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4909        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4910        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4911        // (intrinsic_wo_chain:{ *:[v2i16] } 5382:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PRECEU_PH_QBR:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
4912        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBR,
4913        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4914        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4915        GIR_EraseFromParent, /*InsnID*/0,
4916        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4917        // GIR_Coverage, 364,
4918        GIR_Done,
4919      // Label 416: @9768
4920      GIM_Try, /*On fail goto*//*Label 417*/ 9808, // Rule ID 365 //
4921        GIM_CheckFeatures, GIFBS_HasDSP,
4922        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbla,
4923        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4924        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4925        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4926        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4927        // (intrinsic_wo_chain:{ *:[v2i16] } 5381:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PRECEU_PH_QBLA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
4928        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBLA,
4929        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4930        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4931        GIR_EraseFromParent, /*InsnID*/0,
4932        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4933        // GIR_Coverage, 365,
4934        GIR_Done,
4935      // Label 417: @9808
4936      GIM_Try, /*On fail goto*//*Label 418*/ 9848, // Rule ID 366 //
4937        GIM_CheckFeatures, GIFBS_HasDSP,
4938        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbra,
4939        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4940        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4941        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4942        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4943        // (intrinsic_wo_chain:{ *:[v2i16] } 5383:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PRECEU_PH_QBRA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
4944        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBRA,
4945        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4946        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4947        GIR_EraseFromParent, /*InsnID*/0,
4948        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4949        // GIR_Coverage, 366,
4950        GIR_Done,
4951      // Label 418: @9848
4952      GIM_Try, /*On fail goto*//*Label 419*/ 9888, // Rule ID 414 //
4953        GIM_CheckFeatures, GIFBS_HasDSP,
4954        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_bitrev,
4955        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4956        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4957        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
4958        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
4959        // (intrinsic_wo_chain:{ *:[i32] } 4948:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt)  =>  (BITREV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt)
4960        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BITREV,
4961        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4962        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4963        GIR_EraseFromParent, /*InsnID*/0,
4964        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4965        // GIR_Coverage, 414,
4966        GIR_Done,
4967      // Label 419: @9888
4968      GIM_Try, /*On fail goto*//*Label 420*/ 9928, // Rule ID 418 //
4969        GIM_CheckFeatures, GIFBS_HasDSP,
4970        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_qb,
4971        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
4972        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4973        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4974        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
4975        // (intrinsic_wo_chain:{ *:[v4i8] } 5395:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt)  =>  (REPLV_QB:{ *:[v4i8] } GPR32Opnd:{ *:[i32] }:$rt)
4976        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPLV_QB,
4977        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4978        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4979        GIR_EraseFromParent, /*InsnID*/0,
4980        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4981        // GIR_Coverage, 418,
4982        GIR_Done,
4983      // Label 420: @9928
4984      GIM_Try, /*On fail goto*//*Label 421*/ 9968, // Rule ID 419 //
4985        GIM_CheckFeatures, GIFBS_HasDSP,
4986        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_ph,
4987        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4988        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4989        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4990        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
4991        // (intrinsic_wo_chain:{ *:[v2i16] } 5394:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt)  =>  (REPLV_PH:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rt)
4992        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPLV_PH,
4993        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4994        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4995        GIR_EraseFromParent, /*InsnID*/0,
4996        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4997        // GIR_Coverage, 419,
4998        GIR_Done,
4999      // Label 421: @9968
5000      GIM_Try, /*On fail goto*//*Label 422*/ 10008, // Rule ID 668 //
5001        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5002        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fclass_w,
5003        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
5004        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
5005        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
5006        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
5007        // (intrinsic_wo_chain:{ *:[v4i32] } 5100:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws)  =>  (FCLASS_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
5008        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FCLASS_W,
5009        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5010        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5011        GIR_EraseFromParent, /*InsnID*/0,
5012        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5013        // GIR_Coverage, 668,
5014        GIR_Done,
5015      // Label 422: @10008
5016      GIM_Try, /*On fail goto*//*Label 423*/ 10048, // Rule ID 669 //
5017        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5018        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fclass_d,
5019        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
5020        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
5021        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
5022        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
5023        // (intrinsic_wo_chain:{ *:[v2i64] } 5099:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws)  =>  (FCLASS_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
5024        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FCLASS_D,
5025        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5026        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5027        GIR_EraseFromParent, /*InsnID*/0,
5028        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5029        // GIR_Coverage, 669,
5030        GIR_Done,
5031      // Label 423: @10048
5032      GIM_Try, /*On fail goto*//*Label 424*/ 10088, // Rule ID 692 //
5033        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5034        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fexupl_w,
5035        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
5036        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
5037        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
5038        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
5039        // (intrinsic_wo_chain:{ *:[v4f32] } 5126:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8f16] }:$ws)  =>  (FEXUPL_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8f16] }:$ws)
5040        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXUPL_W,
5041        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5042        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5043        GIR_EraseFromParent, /*InsnID*/0,
5044        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5045        // GIR_Coverage, 692,
5046        GIR_Done,
5047      // Label 424: @10088
5048      GIM_Try, /*On fail goto*//*Label 425*/ 10128, // Rule ID 693 //
5049        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5050        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fexupl_d,
5051        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
5052        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
5053        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
5054        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
5055        // (intrinsic_wo_chain:{ *:[v2f64] } 5125:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws)  =>  (FEXUPL_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4f32] }:$ws)
5056        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXUPL_D,
5057        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5058        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5059        GIR_EraseFromParent, /*InsnID*/0,
5060        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5061        // GIR_Coverage, 693,
5062        GIR_Done,
5063      // Label 425: @10128
5064      GIM_Try, /*On fail goto*//*Label 426*/ 10168, // Rule ID 694 //
5065        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5066        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fexupr_w,
5067        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
5068        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
5069        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
5070        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
5071        // (intrinsic_wo_chain:{ *:[v4f32] } 5128:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8f16] }:$ws)  =>  (FEXUPR_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8f16] }:$ws)
5072        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXUPR_W,
5073        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5074        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5075        GIR_EraseFromParent, /*InsnID*/0,
5076        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5077        // GIR_Coverage, 694,
5078        GIR_Done,
5079      // Label 426: @10168
5080      GIM_Try, /*On fail goto*//*Label 427*/ 10208, // Rule ID 695 //
5081        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5082        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fexupr_d,
5083        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
5084        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
5085        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
5086        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
5087        // (intrinsic_wo_chain:{ *:[v2f64] } 5127:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws)  =>  (FEXUPR_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4f32] }:$ws)
5088        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXUPR_D,
5089        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5090        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5091        GIR_EraseFromParent, /*InsnID*/0,
5092        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5093        // GIR_Coverage, 695,
5094        GIR_Done,
5095      // Label 427: @10208
5096      GIM_Try, /*On fail goto*//*Label 428*/ 10248, // Rule ID 700 //
5097        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5098        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ffql_w,
5099        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
5100        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
5101        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
5102        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
5103        // (intrinsic_wo_chain:{ *:[v4f32] } 5134:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws)  =>  (FFQL_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8i16] }:$ws)
5104        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FFQL_W,
5105        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5106        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5107        GIR_EraseFromParent, /*InsnID*/0,
5108        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5109        // GIR_Coverage, 700,
5110        GIR_Done,
5111      // Label 428: @10248
5112      GIM_Try, /*On fail goto*//*Label 429*/ 10288, // Rule ID 701 //
5113        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5114        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ffql_d,
5115        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
5116        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
5117        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
5118        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
5119        // (intrinsic_wo_chain:{ *:[v2f64] } 5133:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws)  =>  (FFQL_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4i32] }:$ws)
5120        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FFQL_D,
5121        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5122        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5123        GIR_EraseFromParent, /*InsnID*/0,
5124        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5125        // GIR_Coverage, 701,
5126        GIR_Done,
5127      // Label 429: @10288
5128      GIM_Try, /*On fail goto*//*Label 430*/ 10328, // Rule ID 702 //
5129        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5130        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ffqr_w,
5131        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
5132        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
5133        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
5134        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
5135        // (intrinsic_wo_chain:{ *:[v4f32] } 5136:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws)  =>  (FFQR_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8i16] }:$ws)
5136        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FFQR_W,
5137        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5138        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5139        GIR_EraseFromParent, /*InsnID*/0,
5140        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5141        // GIR_Coverage, 702,
5142        GIR_Done,
5143      // Label 430: @10328
5144      GIM_Try, /*On fail goto*//*Label 431*/ 10368, // Rule ID 703 //
5145        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5146        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ffqr_d,
5147        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
5148        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
5149        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
5150        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
5151        // (intrinsic_wo_chain:{ *:[v2f64] } 5135:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws)  =>  (FFQR_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4i32] }:$ws)
5152        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FFQR_D,
5153        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5154        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5155        GIR_EraseFromParent, /*InsnID*/0,
5156        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5157        // GIR_Coverage, 703,
5158        GIR_Done,
5159      // Label 431: @10368
5160      GIM_Try, /*On fail goto*//*Label 432*/ 10408, // Rule ID 728 //
5161        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5162        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_frcp_w,
5163        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
5164        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
5165        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
5166        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
5167        // (intrinsic_wo_chain:{ *:[v4f32] } 5158:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws)  =>  (FRCP_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
5168        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FRCP_W,
5169        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5170        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5171        GIR_EraseFromParent, /*InsnID*/0,
5172        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5173        // GIR_Coverage, 728,
5174        GIR_Done,
5175      // Label 432: @10408
5176      GIM_Try, /*On fail goto*//*Label 433*/ 10448, // Rule ID 729 //
5177        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5178        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_frcp_d,
5179        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
5180        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
5181        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
5182        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
5183        // (intrinsic_wo_chain:{ *:[v2f64] } 5157:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws)  =>  (FRCP_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
5184        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FRCP_D,
5185        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5186        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5187        GIR_EraseFromParent, /*InsnID*/0,
5188        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5189        // GIR_Coverage, 729,
5190        GIR_Done,
5191      // Label 433: @10448
5192      GIM_Try, /*On fail goto*//*Label 434*/ 10488, // Rule ID 730 //
5193        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5194        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_frsqrt_w,
5195        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
5196        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
5197        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
5198        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
5199        // (intrinsic_wo_chain:{ *:[v4f32] } 5162:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws)  =>  (FRSQRT_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
5200        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FRSQRT_W,
5201        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5202        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5203        GIR_EraseFromParent, /*InsnID*/0,
5204        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5205        // GIR_Coverage, 730,
5206        GIR_Done,
5207      // Label 434: @10488
5208      GIM_Try, /*On fail goto*//*Label 435*/ 10528, // Rule ID 731 //
5209        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5210        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_frsqrt_d,
5211        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
5212        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
5213        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
5214        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
5215        // (intrinsic_wo_chain:{ *:[v2f64] } 5161:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws)  =>  (FRSQRT_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
5216        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FRSQRT_D,
5217        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5218        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5219        GIR_EraseFromParent, /*InsnID*/0,
5220        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5221        // GIR_Coverage, 731,
5222        GIR_Done,
5223      // Label 435: @10528
5224      GIM_Try, /*On fail goto*//*Label 436*/ 10568, // Rule ID 758 //
5225        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5226        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ftint_s_w,
5227        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
5228        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
5229        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
5230        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
5231        // (intrinsic_wo_chain:{ *:[v4i32] } 5190:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws)  =>  (FTINT_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
5232        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FTINT_S_W,
5233        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5234        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5235        GIR_EraseFromParent, /*InsnID*/0,
5236        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5237        // GIR_Coverage, 758,
5238        GIR_Done,
5239      // Label 436: @10568
5240      GIM_Try, /*On fail goto*//*Label 437*/ 10608, // Rule ID 759 //
5241        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5242        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ftint_s_d,
5243        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
5244        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
5245        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
5246        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
5247        // (intrinsic_wo_chain:{ *:[v2i64] } 5189:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws)  =>  (FTINT_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
5248        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FTINT_S_D,
5249        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5250        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5251        GIR_EraseFromParent, /*InsnID*/0,
5252        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5253        // GIR_Coverage, 759,
5254        GIR_Done,
5255      // Label 437: @10608
5256      GIM_Try, /*On fail goto*//*Label 438*/ 10648, // Rule ID 760 //
5257        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5258        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ftint_u_w,
5259        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
5260        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
5261        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
5262        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
5263        // (intrinsic_wo_chain:{ *:[v4i32] } 5192:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws)  =>  (FTINT_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
5264        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FTINT_U_W,
5265        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5266        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5267        GIR_EraseFromParent, /*InsnID*/0,
5268        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5269        // GIR_Coverage, 760,
5270        GIR_Done,
5271      // Label 438: @10648
5272      GIM_Try, /*On fail goto*//*Label 439*/ 10688, // Rule ID 761 //
5273        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5274        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ftint_u_d,
5275        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
5276        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
5277        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
5278        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
5279        // (intrinsic_wo_chain:{ *:[v2i64] } 5191:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws)  =>  (FTINT_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
5280        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FTINT_U_D,
5281        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5282        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5283        GIR_EraseFromParent, /*InsnID*/0,
5284        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5285        // GIR_Coverage, 761,
5286        GIR_Done,
5287      // Label 439: @10688
5288      GIM_Try, /*On fail goto*//*Label 440*/ 10728, // Rule ID 896 //
5289        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5290        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_nloc_b,
5291        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
5292        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
5293        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
5294        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
5295        // (intrinsic_wo_chain:{ *:[v16i8] } 5347:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws)  =>  (NLOC_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws)
5296        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NLOC_B,
5297        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5298        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5299        GIR_EraseFromParent, /*InsnID*/0,
5300        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5301        // GIR_Coverage, 896,
5302        GIR_Done,
5303      // Label 440: @10728
5304      GIM_Try, /*On fail goto*//*Label 441*/ 10768, // Rule ID 897 //
5305        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5306        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_nloc_h,
5307        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
5308        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
5309        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
5310        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
5311        // (intrinsic_wo_chain:{ *:[v8i16] } 5349:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws)  =>  (NLOC_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws)
5312        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NLOC_H,
5313        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5314        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5315        GIR_EraseFromParent, /*InsnID*/0,
5316        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5317        // GIR_Coverage, 897,
5318        GIR_Done,
5319      // Label 441: @10768
5320      GIM_Try, /*On fail goto*//*Label 442*/ 10808, // Rule ID 898 //
5321        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5322        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_nloc_w,
5323        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
5324        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
5325        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
5326        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
5327        // (intrinsic_wo_chain:{ *:[v4i32] } 5350:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws)  =>  (NLOC_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws)
5328        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NLOC_W,
5329        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5330        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5331        GIR_EraseFromParent, /*InsnID*/0,
5332        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5333        // GIR_Coverage, 898,
5334        GIR_Done,
5335      // Label 442: @10808
5336      GIM_Try, /*On fail goto*//*Label 443*/ 10848, // Rule ID 899 //
5337        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5338        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_nloc_d,
5339        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
5340        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
5341        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
5342        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
5343        // (intrinsic_wo_chain:{ *:[v2i64] } 5348:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws)  =>  (NLOC_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws)
5344        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NLOC_D,
5345        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5346        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5347        GIR_EraseFromParent, /*InsnID*/0,
5348        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5349        // GIR_Coverage, 899,
5350        GIR_Done,
5351      // Label 443: @10848
5352      GIM_Try, /*On fail goto*//*Label 444*/ 10888, // Rule ID 1239 //
5353        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
5354        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceq_w_phl,
5355        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
5356        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
5357        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
5358        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
5359        // (intrinsic_wo_chain:{ *:[i32] } 5374:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs)  =>  (PRECEQ_W_PHL_MM:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs)
5360        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQ_W_PHL_MM,
5361        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
5362        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5363        GIR_EraseFromParent, /*InsnID*/0,
5364        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5365        // GIR_Coverage, 1239,
5366        GIR_Done,
5367      // Label 444: @10888
5368      GIM_Try, /*On fail goto*//*Label 445*/ 10928, // Rule ID 1240 //
5369        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
5370        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceq_w_phr,
5371        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
5372        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
5373        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
5374        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
5375        // (intrinsic_wo_chain:{ *:[i32] } 5375:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs)  =>  (PRECEQ_W_PHR_MM:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs)
5376        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQ_W_PHR_MM,
5377        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
5378        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5379        GIR_EraseFromParent, /*InsnID*/0,
5380        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5381        // GIR_Coverage, 1240,
5382        GIR_Done,
5383      // Label 445: @10928
5384      GIM_Try, /*On fail goto*//*Label 446*/ 10968, // Rule ID 1241 //
5385        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
5386        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbl,
5387        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
5388        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
5389        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5390        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
5391        // (intrinsic_wo_chain:{ *:[v2i16] } 5376:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs)  =>  (PRECEQU_PH_QBL_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
5392        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBL_MM,
5393        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
5394        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5395        GIR_EraseFromParent, /*InsnID*/0,
5396        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5397        // GIR_Coverage, 1241,
5398        GIR_Done,
5399      // Label 446: @10968
5400      GIM_Try, /*On fail goto*//*Label 447*/ 11008, // Rule ID 1242 //
5401        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
5402        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbla,
5403        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
5404        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
5405        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5406        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
5407        // (intrinsic_wo_chain:{ *:[v2i16] } 5377:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs)  =>  (PRECEQU_PH_QBLA_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
5408        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBLA_MM,
5409        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
5410        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5411        GIR_EraseFromParent, /*InsnID*/0,
5412        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5413        // GIR_Coverage, 1242,
5414        GIR_Done,
5415      // Label 447: @11008
5416      GIM_Try, /*On fail goto*//*Label 448*/ 11048, // Rule ID 1243 //
5417        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
5418        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbr,
5419        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
5420        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
5421        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5422        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
5423        // (intrinsic_wo_chain:{ *:[v2i16] } 5378:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs)  =>  (PRECEQU_PH_QBR_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
5424        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBR_MM,
5425        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
5426        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5427        GIR_EraseFromParent, /*InsnID*/0,
5428        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5429        // GIR_Coverage, 1243,
5430        GIR_Done,
5431      // Label 448: @11048
5432      GIM_Try, /*On fail goto*//*Label 449*/ 11088, // Rule ID 1244 //
5433        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
5434        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbra,
5435        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
5436        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
5437        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5438        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
5439        // (intrinsic_wo_chain:{ *:[v2i16] } 5379:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs)  =>  (PRECEQU_PH_QBRA_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
5440        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBRA_MM,
5441        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
5442        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5443        GIR_EraseFromParent, /*InsnID*/0,
5444        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5445        // GIR_Coverage, 1244,
5446        GIR_Done,
5447      // Label 449: @11088
5448      GIM_Try, /*On fail goto*//*Label 450*/ 11128, // Rule ID 1245 //
5449        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
5450        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbl,
5451        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
5452        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
5453        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5454        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
5455        // (intrinsic_wo_chain:{ *:[v2i16] } 5380:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs)  =>  (PRECEU_PH_QBL_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
5456        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBL_MM,
5457        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
5458        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5459        GIR_EraseFromParent, /*InsnID*/0,
5460        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5461        // GIR_Coverage, 1245,
5462        GIR_Done,
5463      // Label 450: @11128
5464      GIM_Try, /*On fail goto*//*Label 451*/ 11168, // Rule ID 1246 //
5465        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
5466        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbla,
5467        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
5468        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
5469        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5470        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
5471        // (intrinsic_wo_chain:{ *:[v2i16] } 5381:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs)  =>  (PRECEU_PH_QBLA_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
5472        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBLA_MM,
5473        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
5474        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5475        GIR_EraseFromParent, /*InsnID*/0,
5476        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5477        // GIR_Coverage, 1246,
5478        GIR_Done,
5479      // Label 451: @11168
5480      GIM_Try, /*On fail goto*//*Label 452*/ 11208, // Rule ID 1247 //
5481        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
5482        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbr,
5483        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
5484        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
5485        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5486        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
5487        // (intrinsic_wo_chain:{ *:[v2i16] } 5382:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs)  =>  (PRECEU_PH_QBR_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
5488        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBR_MM,
5489        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
5490        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5491        GIR_EraseFromParent, /*InsnID*/0,
5492        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5493        // GIR_Coverage, 1247,
5494        GIR_Done,
5495      // Label 452: @11208
5496      GIM_Try, /*On fail goto*//*Label 453*/ 11248, // Rule ID 1248 //
5497        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
5498        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbra,
5499        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
5500        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
5501        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5502        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
5503        // (intrinsic_wo_chain:{ *:[v2i16] } 5383:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs)  =>  (PRECEU_PH_QBRA_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
5504        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBRA_MM,
5505        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
5506        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5507        GIR_EraseFromParent, /*InsnID*/0,
5508        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5509        // GIR_Coverage, 1248,
5510        GIR_Done,
5511      // Label 453: @11248
5512      GIM_Try, /*On fail goto*//*Label 454*/ 11288, // Rule ID 1274 //
5513        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
5514        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_raddu_w_qb,
5515        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
5516        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
5517        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
5518        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
5519        // (intrinsic_wo_chain:{ *:[i32] } 5392:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs)  =>  (RADDU_W_QB_MM:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs)
5520        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::RADDU_W_QB_MM,
5521        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
5522        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5523        GIR_EraseFromParent, /*InsnID*/0,
5524        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5525        // GIR_Coverage, 1274,
5526        GIR_Done,
5527      // Label 454: @11288
5528      GIM_Try, /*On fail goto*//*Label 455*/ 11328, // Rule ID 1278 //
5529        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
5530        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_ph,
5531        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
5532        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
5533        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5534        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
5535        // (intrinsic_wo_chain:{ *:[v2i16] } 5394:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs)  =>  (REPLV_PH_MM:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs)
5536        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPLV_PH_MM,
5537        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
5538        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5539        GIR_EraseFromParent, /*InsnID*/0,
5540        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5541        // GIR_Coverage, 1278,
5542        GIR_Done,
5543      // Label 455: @11328
5544      GIM_Try, /*On fail goto*//*Label 456*/ 11368, // Rule ID 1279 //
5545        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
5546        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_qb,
5547        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
5548        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
5549        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5550        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
5551        // (intrinsic_wo_chain:{ *:[v4i8] } 5395:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs)  =>  (REPLV_QB_MM:{ *:[v4i8] } GPR32Opnd:{ *:[i32] }:$rs)
5552        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPLV_QB_MM,
5553        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
5554        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5555        GIR_EraseFromParent, /*InsnID*/0,
5556        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5557        // GIR_Coverage, 1279,
5558        GIR_Done,
5559      // Label 456: @11368
5560      GIM_Try, /*On fail goto*//*Label 457*/ 11408, // Rule ID 1289 //
5561        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
5562        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_bitrev,
5563        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
5564        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
5565        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
5566        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
5567        // (intrinsic_wo_chain:{ *:[i32] } 4948:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs)  =>  (BITREV_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
5568        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BITREV_MM,
5569        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
5570        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5571        GIR_EraseFromParent, /*InsnID*/0,
5572        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5573        // GIR_Coverage, 1289,
5574        GIR_Done,
5575      // Label 457: @11408
5576      GIM_Reject,
5577    // Label 403: @11409
5578    GIM_Try, /*On fail goto*//*Label 458*/ 22549,
5579      GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
5580      GIM_Try, /*On fail goto*//*Label 459*/ 11465, // Rule ID 926 //
5581        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5582        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sat_s_b,
5583        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
5584        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
5585        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
5586        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
5587        // MIs[0] m
5588        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
5589        GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIPFP_I64_Predicate_timmZExt3,
5590        // (intrinsic_wo_chain:{ *:[v16i8] } 5396:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt3>>:$m)  =>  (SAT_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] }):$m)
5591        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_S_B,
5592        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5593        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5594        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // m
5595        GIR_EraseFromParent, /*InsnID*/0,
5596        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5597        // GIR_Coverage, 926,
5598        GIR_Done,
5599      // Label 459: @11465
5600      GIM_Try, /*On fail goto*//*Label 460*/ 11516, // Rule ID 927 //
5601        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5602        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sat_s_h,
5603        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
5604        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
5605        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
5606        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
5607        // MIs[0] m
5608        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
5609        GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIPFP_I64_Predicate_timmZExt4,
5610        // (intrinsic_wo_chain:{ *:[v8i16] } 5398:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt4>>:$m)  =>  (SAT_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] }):$m)
5611        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_S_H,
5612        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5613        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5614        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // m
5615        GIR_EraseFromParent, /*InsnID*/0,
5616        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5617        // GIR_Coverage, 927,
5618        GIR_Done,
5619      // Label 460: @11516
5620      GIM_Try, /*On fail goto*//*Label 461*/ 11567, // Rule ID 928 //
5621        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5622        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sat_s_w,
5623        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
5624        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
5625        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
5626        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
5627        // MIs[0] m
5628        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
5629        GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIPFP_I64_Predicate_timmZExt5,
5630        // (intrinsic_wo_chain:{ *:[v4i32] } 5399:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$m)  =>  (SAT_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] }):$m)
5631        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_S_W,
5632        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5633        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5634        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // m
5635        GIR_EraseFromParent, /*InsnID*/0,
5636        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5637        // GIR_Coverage, 928,
5638        GIR_Done,
5639      // Label 461: @11567
5640      GIM_Try, /*On fail goto*//*Label 462*/ 11618, // Rule ID 929 //
5641        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5642        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sat_s_d,
5643        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
5644        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
5645        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
5646        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
5647        // MIs[0] m
5648        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
5649        GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIPFP_I64_Predicate_timmZExt6,
5650        // (intrinsic_wo_chain:{ *:[v2i64] } 5397:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt6>>:$m)  =>  (SAT_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] }):$m)
5651        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_S_D,
5652        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5653        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5654        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // m
5655        GIR_EraseFromParent, /*InsnID*/0,
5656        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5657        // GIR_Coverage, 929,
5658        GIR_Done,
5659      // Label 462: @11618
5660      GIM_Try, /*On fail goto*//*Label 463*/ 11669, // Rule ID 930 //
5661        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5662        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sat_u_b,
5663        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
5664        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
5665        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
5666        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
5667        // MIs[0] m
5668        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
5669        GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIPFP_I64_Predicate_timmZExt3,
5670        // (intrinsic_wo_chain:{ *:[v16i8] } 5400:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt3>>:$m)  =>  (SAT_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] }):$m)
5671        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_U_B,
5672        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5673        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5674        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // m
5675        GIR_EraseFromParent, /*InsnID*/0,
5676        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5677        // GIR_Coverage, 930,
5678        GIR_Done,
5679      // Label 463: @11669
5680      GIM_Try, /*On fail goto*//*Label 464*/ 11720, // Rule ID 931 //
5681        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5682        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sat_u_h,
5683        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
5684        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
5685        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
5686        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
5687        // MIs[0] m
5688        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
5689        GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIPFP_I64_Predicate_timmZExt4,
5690        // (intrinsic_wo_chain:{ *:[v8i16] } 5402:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt4>>:$m)  =>  (SAT_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] }):$m)
5691        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_U_H,
5692        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5693        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5694        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // m
5695        GIR_EraseFromParent, /*InsnID*/0,
5696        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5697        // GIR_Coverage, 931,
5698        GIR_Done,
5699      // Label 464: @11720
5700      GIM_Try, /*On fail goto*//*Label 465*/ 11771, // Rule ID 932 //
5701        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5702        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sat_u_w,
5703        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
5704        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
5705        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
5706        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
5707        // MIs[0] m
5708        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
5709        GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIPFP_I64_Predicate_timmZExt5,
5710        // (intrinsic_wo_chain:{ *:[v4i32] } 5403:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$m)  =>  (SAT_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] }):$m)
5711        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_U_W,
5712        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5713        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5714        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // m
5715        GIR_EraseFromParent, /*InsnID*/0,
5716        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5717        // GIR_Coverage, 932,
5718        GIR_Done,
5719      // Label 465: @11771
5720      GIM_Try, /*On fail goto*//*Label 466*/ 11822, // Rule ID 933 //
5721        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5722        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sat_u_d,
5723        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
5724        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
5725        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
5726        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
5727        // MIs[0] m
5728        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
5729        GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIPFP_I64_Predicate_timmZExt6,
5730        // (intrinsic_wo_chain:{ *:[v2i64] } 5401:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt6>>:$m)  =>  (SAT_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] }):$m)
5731        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_U_D,
5732        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5733        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5734        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // m
5735        GIR_EraseFromParent, /*InsnID*/0,
5736        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5737        // GIR_Coverage, 933,
5738        GIR_Done,
5739      // Label 466: @11822
5740      GIM_Try, /*On fail goto*//*Label 467*/ 11873, // Rule ID 973 //
5741        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5742        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srari_b,
5743        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
5744        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
5745        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
5746        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
5747        // MIs[0] m
5748        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
5749        GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIPFP_I64_Predicate_timmZExt3,
5750        // (intrinsic_wo_chain:{ *:[v16i8] } 5455:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt3>>:$m)  =>  (SRARI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] }):$m)
5751        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRARI_B,
5752        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5753        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5754        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // m
5755        GIR_EraseFromParent, /*InsnID*/0,
5756        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5757        // GIR_Coverage, 973,
5758        GIR_Done,
5759      // Label 467: @11873
5760      GIM_Try, /*On fail goto*//*Label 468*/ 11924, // Rule ID 974 //
5761        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5762        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srari_h,
5763        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
5764        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
5765        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
5766        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
5767        // MIs[0] m
5768        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
5769        GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIPFP_I64_Predicate_timmZExt4,
5770        // (intrinsic_wo_chain:{ *:[v8i16] } 5457:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt4>>:$m)  =>  (SRARI_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] }):$m)
5771        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRARI_H,
5772        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5773        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5774        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // m
5775        GIR_EraseFromParent, /*InsnID*/0,
5776        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5777        // GIR_Coverage, 974,
5778        GIR_Done,
5779      // Label 468: @11924
5780      GIM_Try, /*On fail goto*//*Label 469*/ 11975, // Rule ID 975 //
5781        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5782        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srari_w,
5783        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
5784        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
5785        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
5786        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
5787        // MIs[0] m
5788        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
5789        GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIPFP_I64_Predicate_timmZExt5,
5790        // (intrinsic_wo_chain:{ *:[v4i32] } 5458:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$m)  =>  (SRARI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] }):$m)
5791        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRARI_W,
5792        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5793        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5794        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // m
5795        GIR_EraseFromParent, /*InsnID*/0,
5796        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5797        // GIR_Coverage, 975,
5798        GIR_Done,
5799      // Label 469: @11975
5800      GIM_Try, /*On fail goto*//*Label 470*/ 12026, // Rule ID 976 //
5801        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5802        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srari_d,
5803        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
5804        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
5805        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
5806        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
5807        // MIs[0] m
5808        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
5809        GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIPFP_I64_Predicate_timmZExt6,
5810        // (intrinsic_wo_chain:{ *:[v2i64] } 5456:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt6>>:$m)  =>  (SRARI_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] }):$m)
5811        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRARI_D,
5812        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5813        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5814        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // m
5815        GIR_EraseFromParent, /*InsnID*/0,
5816        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5817        // GIR_Coverage, 976,
5818        GIR_Done,
5819      // Label 470: @12026
5820      GIM_Try, /*On fail goto*//*Label 471*/ 12077, // Rule ID 989 //
5821        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5822        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srlri_b,
5823        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
5824        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
5825        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
5826        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
5827        // MIs[0] m
5828        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
5829        GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIPFP_I64_Predicate_timmZExt3,
5830        // (intrinsic_wo_chain:{ *:[v16i8] } 5471:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt3>>:$m)  =>  (SRLRI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] }):$m)
5831        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLRI_B,
5832        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5833        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5834        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // m
5835        GIR_EraseFromParent, /*InsnID*/0,
5836        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5837        // GIR_Coverage, 989,
5838        GIR_Done,
5839      // Label 471: @12077
5840      GIM_Try, /*On fail goto*//*Label 472*/ 12128, // Rule ID 990 //
5841        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5842        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srlri_h,
5843        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
5844        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
5845        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
5846        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
5847        // MIs[0] m
5848        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
5849        GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIPFP_I64_Predicate_timmZExt4,
5850        // (intrinsic_wo_chain:{ *:[v8i16] } 5473:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt4>>:$m)  =>  (SRLRI_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] }):$m)
5851        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLRI_H,
5852        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5853        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5854        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // m
5855        GIR_EraseFromParent, /*InsnID*/0,
5856        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5857        // GIR_Coverage, 990,
5858        GIR_Done,
5859      // Label 472: @12128
5860      GIM_Try, /*On fail goto*//*Label 473*/ 12179, // Rule ID 991 //
5861        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5862        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srlri_w,
5863        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
5864        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
5865        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
5866        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
5867        // MIs[0] m
5868        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
5869        GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIPFP_I64_Predicate_timmZExt5,
5870        // (intrinsic_wo_chain:{ *:[v4i32] } 5474:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$m)  =>  (SRLRI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] }):$m)
5871        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLRI_W,
5872        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5873        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5874        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // m
5875        GIR_EraseFromParent, /*InsnID*/0,
5876        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5877        // GIR_Coverage, 991,
5878        GIR_Done,
5879      // Label 473: @12179
5880      GIM_Try, /*On fail goto*//*Label 474*/ 12230, // Rule ID 992 //
5881        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5882        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srlri_d,
5883        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
5884        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
5885        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
5886        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
5887        // MIs[0] m
5888        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
5889        GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIPFP_I64_Predicate_timmZExt6,
5890        // (intrinsic_wo_chain:{ *:[v2i64] } 5472:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt6>>:$m)  =>  (SRLRI_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] }):$m)
5891        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLRI_D,
5892        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5893        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5894        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // m
5895        GIR_EraseFromParent, /*InsnID*/0,
5896        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5897        // GIR_Coverage, 992,
5898        GIR_Done,
5899      // Label 474: @12230
5900      GIM_Try, /*On fail goto*//*Label 475*/ 12289, // Rule ID 373 //
5901        GIM_CheckFeatures, GIFBS_HasDSP,
5902        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_ph,
5903        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
5904        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
5905        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5906        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5907        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
5908        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
5909        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
5910        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt4,
5911        // MIs[1] Operand 1
5912        // No operand predicates
5913        GIM_CheckIsSafeToFold, /*InsnID*/1,
5914        // (intrinsic_wo_chain:{ *:[v2i16] } 5414:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$rs_sa)  =>  (SHRA_R_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, (imm:{ *:[i32] }):$rs_sa)
5915        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_R_PH,
5916        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
5917        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
5918        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa
5919        GIR_EraseFromParent, /*InsnID*/0,
5920        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5921        // GIR_Coverage, 373,
5922        GIR_Done,
5923      // Label 475: @12289
5924      GIM_Try, /*On fail goto*//*Label 476*/ 12348, // Rule ID 377 //
5925        GIM_CheckFeatures, GIFBS_HasDSP,
5926        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_w,
5927        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
5928        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
5929        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5930        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
5931        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
5932        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
5933        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
5934        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
5935        // MIs[1] Operand 1
5936        // No operand predicates
5937        GIM_CheckIsSafeToFold, /*InsnID*/1,
5938        // (intrinsic_wo_chain:{ *:[i32] } 5416:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$rs_sa)  =>  (SHRA_R_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$rs_sa)
5939        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_R_W,
5940        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
5941        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
5942        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa
5943        GIR_EraseFromParent, /*InsnID*/0,
5944        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5945        // GIR_Coverage, 377,
5946        GIR_Done,
5947      // Label 476: @12348
5948      GIM_Try, /*On fail goto*//*Label 477*/ 12407, // Rule ID 468 //
5949        GIM_CheckFeatures, GIFBS_HasDSPR2,
5950        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_qb,
5951        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
5952        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
5953        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5954        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5955        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
5956        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
5957        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
5958        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt3,
5959        // MIs[1] Operand 1
5960        // No operand predicates
5961        GIM_CheckIsSafeToFold, /*InsnID*/1,
5962        // (intrinsic_wo_chain:{ *:[v4i8] } 5415:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$rs_sa)  =>  (SHRA_R_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, (imm:{ *:[i32] }):$rs_sa)
5963        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_R_QB,
5964        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
5965        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
5966        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa
5967        GIR_EraseFromParent, /*InsnID*/0,
5968        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5969        // GIR_Coverage, 468,
5970        GIR_Done,
5971      // Label 477: @12407
5972      GIM_Try, /*On fail goto*//*Label 478*/ 12466, // Rule ID 1233 //
5973        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
5974        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_ph,
5975        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
5976        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
5977        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5978        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5979        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
5980        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
5981        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
5982        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt4,
5983        // MIs[1] Operand 1
5984        // No operand predicates
5985        GIM_CheckIsSafeToFold, /*InsnID*/1,
5986        // (intrinsic_wo_chain:{ *:[v2i16] } 5414:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$sa)  =>  (SHRA_R_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, (imm:{ *:[i32] }):$sa)
5987        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_R_PH_MM,
5988        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
5989        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5990        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
5991        GIR_EraseFromParent, /*InsnID*/0,
5992        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5993        // GIR_Coverage, 1233,
5994        GIR_Done,
5995      // Label 478: @12466
5996      GIM_Try, /*On fail goto*//*Label 479*/ 12525, // Rule ID 1237 //
5997        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
5998        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_w,
5999        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
6000        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
6001        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
6002        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
6003        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
6004        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
6005        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
6006        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
6007        // MIs[1] Operand 1
6008        // No operand predicates
6009        GIM_CheckIsSafeToFold, /*InsnID*/1,
6010        // (intrinsic_wo_chain:{ *:[i32] } 5416:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$sa)  =>  (SHRA_R_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa)
6011        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_R_W_MM,
6012        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
6013        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
6014        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
6015        GIR_EraseFromParent, /*InsnID*/0,
6016        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6017        // GIR_Coverage, 1237,
6018        GIR_Done,
6019      // Label 479: @12525
6020      GIM_Try, /*On fail goto*//*Label 480*/ 12584, // Rule ID 1312 //
6021        GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
6022        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_qb,
6023        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
6024        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
6025        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
6026        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6027        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
6028        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
6029        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
6030        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt3,
6031        // MIs[1] Operand 1
6032        // No operand predicates
6033        GIM_CheckIsSafeToFold, /*InsnID*/1,
6034        // (intrinsic_wo_chain:{ *:[v4i8] } 5415:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$sa)  =>  (SHRA_R_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, (imm:{ *:[i32] }):$sa)
6035        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_R_QB_MMR2,
6036        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
6037        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
6038        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
6039        GIR_EraseFromParent, /*InsnID*/0,
6040        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6041        // GIR_Coverage, 1312,
6042        GIR_Done,
6043      // Label 480: @12584
6044      GIM_Try, /*On fail goto*//*Label 481*/ 12639, // Rule ID 1899 //
6045        GIM_CheckFeatures, GIFBS_HasDSP,
6046        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_ph,
6047        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
6048        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
6049        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
6050        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6051        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
6052        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
6053        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt4,
6054        // MIs[1] Operand 1
6055        // No operand predicates
6056        GIM_CheckIsSafeToFold, /*InsnID*/1,
6057        // (intrinsic_wo_chain:{ *:[v2i16] } 5412:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt)  =>  (SHRA_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt)
6058        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_PH,
6059        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6060        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
6061        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
6062        GIR_EraseFromParent, /*InsnID*/0,
6063        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6064        // GIR_Coverage, 1899,
6065        GIR_Done,
6066      // Label 481: @12639
6067      GIM_Try, /*On fail goto*//*Label 482*/ 12694, // Rule ID 1900 //
6068        GIM_CheckFeatures, GIFBS_HasDSPR2,
6069        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shrl_ph,
6070        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
6071        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
6072        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
6073        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6074        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
6075        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
6076        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt4,
6077        // MIs[1] Operand 1
6078        // No operand predicates
6079        GIM_CheckIsSafeToFold, /*InsnID*/1,
6080        // (intrinsic_wo_chain:{ *:[v2i16] } 5417:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt)  =>  (SHRL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt)
6081        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRL_PH,
6082        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6083        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
6084        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
6085        GIR_EraseFromParent, /*InsnID*/0,
6086        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6087        // GIR_Coverage, 1900,
6088        GIR_Done,
6089      // Label 482: @12694
6090      GIM_Try, /*On fail goto*//*Label 483*/ 12749, // Rule ID 1905 //
6091        GIM_CheckFeatures, GIFBS_HasDSPR2,
6092        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_qb,
6093        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
6094        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
6095        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
6096        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6097        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
6098        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
6099        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt3,
6100        // MIs[1] Operand 1
6101        // No operand predicates
6102        GIM_CheckIsSafeToFold, /*InsnID*/1,
6103        // (intrinsic_wo_chain:{ *:[v4i8] } 5413:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt)  =>  (SHRA_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt)
6104        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_QB,
6105        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6106        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
6107        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
6108        GIR_EraseFromParent, /*InsnID*/0,
6109        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6110        // GIR_Coverage, 1905,
6111        GIR_Done,
6112      // Label 483: @12749
6113      GIM_Try, /*On fail goto*//*Label 484*/ 12804, // Rule ID 1906 //
6114        GIM_CheckFeatures, GIFBS_HasDSP,
6115        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shrl_qb,
6116        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
6117        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
6118        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
6119        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6120        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
6121        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
6122        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt3,
6123        // MIs[1] Operand 1
6124        // No operand predicates
6125        GIM_CheckIsSafeToFold, /*InsnID*/1,
6126        // (intrinsic_wo_chain:{ *:[v4i8] } 5418:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt)  =>  (SHRL_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt)
6127        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRL_QB,
6128        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6129        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
6130        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
6131        GIR_EraseFromParent, /*InsnID*/0,
6132        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6133        // GIR_Coverage, 1906,
6134        GIR_Done,
6135      // Label 484: @12804
6136      GIM_Try, /*On fail goto*//*Label 485*/ 12856, // Rule ID 343 //
6137        GIM_CheckFeatures, GIFBS_HasDSP,
6138        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addu_s_qb,
6139        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
6140        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
6141        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
6142        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6143        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
6144        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
6145        // (intrinsic_wo_chain:{ *:[v4i8] } 4884:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (ADDU_S_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
6146        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDU_S_QB,
6147        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6148        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
6149        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
6150        GIR_EraseFromParent, /*InsnID*/0,
6151        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6152        // GIR_Coverage, 343,
6153        GIR_Done,
6154      // Label 485: @12856
6155      GIM_Try, /*On fail goto*//*Label 486*/ 12908, // Rule ID 344 //
6156        GIM_CheckFeatures, GIFBS_HasDSP,
6157        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subu_s_qb,
6158        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
6159        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
6160        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
6161        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6162        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
6163        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
6164        // (intrinsic_wo_chain:{ *:[v4i8] } 5507:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (SUBU_S_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
6165        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBU_S_QB,
6166        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6167        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
6168        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
6169        GIR_EraseFromParent, /*InsnID*/0,
6170        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6171        // GIR_Coverage, 344,
6172        GIR_Done,
6173      // Label 486: @12908
6174      GIM_Try, /*On fail goto*//*Label 487*/ 12960, // Rule ID 345 //
6175        GIM_CheckFeatures, GIFBS_HasDSP,
6176        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addq_s_ph,
6177        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
6178        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
6179        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
6180        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6181        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
6182        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
6183        // (intrinsic_wo_chain:{ *:[v2i16] } 4862:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (ADDQ_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
6184        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQ_S_PH,
6185        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6186        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
6187        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
6188        GIR_EraseFromParent, /*InsnID*/0,
6189        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6190        // GIR_Coverage, 345,
6191        GIR_Done,
6192      // Label 487: @12960
6193      GIM_Try, /*On fail goto*//*Label 488*/ 13012, // Rule ID 346 //
6194        GIM_CheckFeatures, GIFBS_HasDSP,
6195        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subq_s_ph,
6196        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
6197        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
6198        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
6199        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6200        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
6201        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
6202        // (intrinsic_wo_chain:{ *:[v2i16] } 5482:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (SUBQ_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
6203        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQ_S_PH,
6204        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6205        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
6206        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
6207        GIR_EraseFromParent, /*InsnID*/0,
6208        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6209        // GIR_Coverage, 346,
6210        GIR_Done,
6211      // Label 488: @13012
6212      GIM_Try, /*On fail goto*//*Label 489*/ 13064, // Rule ID 349 //
6213        GIM_CheckFeatures, GIFBS_HasDSP,
6214        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_modsub,
6215        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
6216        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
6217        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
6218        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
6219        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
6220        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
6221        // (intrinsic_wo_chain:{ *:[i32] } 5312:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MODSUB:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
6222        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MODSUB,
6223        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6224        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
6225        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
6226        GIR_EraseFromParent, /*InsnID*/0,
6227        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6228        // GIR_Coverage, 349,
6229        GIR_Done,
6230      // Label 489: @13064
6231      GIM_Try, /*On fail goto*//*Label 490*/ 13116, // Rule ID 353 //
6232        GIM_CheckFeatures, GIFBS_HasDSP,
6233        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precrq_qb_ph,
6234        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
6235        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
6236        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
6237        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6238        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
6239        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
6240        // (intrinsic_wo_chain:{ *:[v4i8] } 5388:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (PRECRQ_QB_PH:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
6241        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECRQ_QB_PH,
6242        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6243        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
6244        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
6245        GIR_EraseFromParent, /*InsnID*/0,
6246        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6247        // GIR_Coverage, 353,
6248        GIR_Done,
6249      // Label 490: @13116
6250      GIM_Try, /*On fail goto*//*Label 491*/ 13168, // Rule ID 354 //
6251        GIM_CheckFeatures, GIFBS_HasDSP,
6252        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precrq_ph_w,
6253        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
6254        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
6255        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
6256        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6257        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
6258        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
6259        // (intrinsic_wo_chain:{ *:[v2i16] } 5387:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (PRECRQ_PH_W:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
6260        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECRQ_PH_W,
6261        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6262        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
6263        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
6264        GIR_EraseFromParent, /*InsnID*/0,
6265        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6266        // GIR_Coverage, 354,
6267        GIR_Done,
6268      // Label 491: @13168
6269      GIM_Try, /*On fail goto*//*Label 492*/ 13220, // Rule ID 368 //
6270        GIM_CheckFeatures, GIFBS_HasDSP,
6271        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shrl_qb,
6272        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
6273        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
6274        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
6275        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6276        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
6277        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
6278        // (intrinsic_wo_chain:{ *:[v4i8] } 5418:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)  =>  (SHRLV_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
6279        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRLV_QB,
6280        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6281        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
6282        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa
6283        GIR_EraseFromParent, /*InsnID*/0,
6284        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6285        // GIR_Coverage, 368,
6286        GIR_Done,
6287      // Label 492: @13220
6288      GIM_Try, /*On fail goto*//*Label 493*/ 13272, // Rule ID 372 //
6289        GIM_CheckFeatures, GIFBS_HasDSP,
6290        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_ph,
6291        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
6292        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
6293        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
6294        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6295        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
6296        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
6297        // (intrinsic_wo_chain:{ *:[v2i16] } 5412:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)  =>  (SHRAV_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
6298        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_PH,
6299        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6300        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
6301        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa
6302        GIR_EraseFromParent, /*InsnID*/0,
6303        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6304        // GIR_Coverage, 372,
6305        GIR_Done,
6306      // Label 493: @13272
6307      GIM_Try, /*On fail goto*//*Label 494*/ 13324, // Rule ID 374 //
6308        GIM_CheckFeatures, GIFBS_HasDSP,
6309        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_ph,
6310        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
6311        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
6312        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
6313        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6314        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
6315        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
6316        // (intrinsic_wo_chain:{ *:[v2i16] } 5414:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)  =>  (SHRAV_R_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
6317        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_R_PH,
6318        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6319        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
6320        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa
6321        GIR_EraseFromParent, /*InsnID*/0,
6322        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6323        // GIR_Coverage, 374,
6324        GIR_Done,
6325      // Label 494: @13324
6326      GIM_Try, /*On fail goto*//*Label 495*/ 13376, // Rule ID 378 //
6327        GIM_CheckFeatures, GIFBS_HasDSP,
6328        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_w,
6329        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
6330        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
6331        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
6332        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
6333        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
6334        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
6335        // (intrinsic_wo_chain:{ *:[i32] } 5416:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)  =>  (SHRAV_R_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
6336        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_R_W,
6337        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6338        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
6339        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa
6340        GIR_EraseFromParent, /*InsnID*/0,
6341        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6342        // GIR_Coverage, 378,
6343        GIR_Done,
6344      // Label 495: @13376
6345      GIM_Try, /*On fail goto*//*Label 496*/ 13428, // Rule ID 415 //
6346        GIM_CheckFeatures, GIFBS_HasDSP,
6347        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_packrl_ph,
6348        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
6349        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
6350        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
6351        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6352        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
6353        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
6354        // (intrinsic_wo_chain:{ *:[v2i16] } 5359:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (PACKRL_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
6355        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PACKRL_PH,
6356        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6357        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
6358        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
6359        GIR_EraseFromParent, /*InsnID*/0,
6360        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6361        // GIR_Coverage, 415,
6362        GIR_Done,
6363      // Label 496: @13428
6364      GIM_Try, /*On fail goto*//*Label 497*/ 13480, // Rule ID 439 //
6365        GIM_CheckFeatures, GIFBS_HasDSPR2,
6366        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adduh_qb,
6367        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
6368        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
6369        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
6370        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6371        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
6372        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
6373        // (intrinsic_wo_chain:{ *:[v4i8] } 4885:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (ADDUH_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
6374        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDUH_QB,
6375        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6376        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
6377        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
6378        GIR_EraseFromParent, /*InsnID*/0,
6379        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6380        // GIR_Coverage, 439,
6381        GIR_Done,
6382      // Label 497: @13480
6383      GIM_Try, /*On fail goto*//*Label 498*/ 13532, // Rule ID 440 //
6384        GIM_CheckFeatures, GIFBS_HasDSPR2,
6385        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adduh_r_qb,
6386        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
6387        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
6388        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
6389        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6390        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
6391        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
6392        // (intrinsic_wo_chain:{ *:[v4i8] } 4886:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (ADDUH_R_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
6393        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDUH_R_QB,
6394        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6395        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
6396        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
6397        GIR_EraseFromParent, /*InsnID*/0,
6398        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6399        // GIR_Coverage, 440,
6400        GIR_Done,
6401      // Label 498: @13532
6402      GIM_Try, /*On fail goto*//*Label 499*/ 13584, // Rule ID 441 //
6403        GIM_CheckFeatures, GIFBS_HasDSPR2,
6404        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subuh_qb,
6405        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
6406        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
6407        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
6408        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6409        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
6410        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
6411        // (intrinsic_wo_chain:{ *:[v4i8] } 5508:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (SUBUH_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
6412        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBUH_QB,
6413        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6414        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
6415        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
6416        GIR_EraseFromParent, /*InsnID*/0,
6417        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6418        // GIR_Coverage, 441,
6419        GIR_Done,
6420      // Label 499: @13584
6421      GIM_Try, /*On fail goto*//*Label 500*/ 13636, // Rule ID 442 //
6422        GIM_CheckFeatures, GIFBS_HasDSPR2,
6423        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subuh_r_qb,
6424        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
6425        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
6426        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
6427        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6428        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
6429        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
6430        // (intrinsic_wo_chain:{ *:[v4i8] } 5509:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (SUBUH_R_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
6431        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBUH_R_QB,
6432        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6433        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
6434        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
6435        GIR_EraseFromParent, /*InsnID*/0,
6436        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6437        // GIR_Coverage, 442,
6438        GIR_Done,
6439      // Label 500: @13636
6440      GIM_Try, /*On fail goto*//*Label 501*/ 13688, // Rule ID 443 //
6441        GIM_CheckFeatures, GIFBS_HasDSPR2,
6442        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addqh_ph,
6443        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
6444        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
6445        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
6446        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6447        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
6448        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
6449        // (intrinsic_wo_chain:{ *:[v2i16] } 4864:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (ADDQH_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
6450        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_PH,
6451        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6452        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
6453        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
6454        GIR_EraseFromParent, /*InsnID*/0,
6455        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6456        // GIR_Coverage, 443,
6457        GIR_Done,
6458      // Label 501: @13688
6459      GIM_Try, /*On fail goto*//*Label 502*/ 13740, // Rule ID 444 //
6460        GIM_CheckFeatures, GIFBS_HasDSPR2,
6461        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addqh_r_ph,
6462        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
6463        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
6464        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
6465        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6466        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
6467        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
6468        // (intrinsic_wo_chain:{ *:[v2i16] } 4865:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (ADDQH_R_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
6469        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_R_PH,
6470        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6471        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
6472        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
6473        GIR_EraseFromParent, /*InsnID*/0,
6474        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6475        // GIR_Coverage, 444,
6476        GIR_Done,
6477      // Label 502: @13740
6478      GIM_Try, /*On fail goto*//*Label 503*/ 13792, // Rule ID 445 //
6479        GIM_CheckFeatures, GIFBS_HasDSPR2,
6480        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subqh_ph,
6481        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
6482        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
6483        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
6484        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6485        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
6486        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
6487        // (intrinsic_wo_chain:{ *:[v2i16] } 5484:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (SUBQH_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
6488        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQH_PH,
6489        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6490        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
6491        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
6492        GIR_EraseFromParent, /*InsnID*/0,
6493        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6494        // GIR_Coverage, 445,
6495        GIR_Done,
6496      // Label 503: @13792
6497      GIM_Try, /*On fail goto*//*Label 504*/ 13844, // Rule ID 446 //
6498        GIM_CheckFeatures, GIFBS_HasDSPR2,
6499        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subqh_r_ph,
6500        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
6501        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
6502        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
6503        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6504        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
6505        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
6506        // (intrinsic_wo_chain:{ *:[v2i16] } 5485:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (SUBQH_R_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
6507        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQH_R_PH,
6508        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6509        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
6510        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
6511        GIR_EraseFromParent, /*InsnID*/0,
6512        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6513        // GIR_Coverage, 446,
6514        GIR_Done,
6515      // Label 504: @13844
6516      GIM_Try, /*On fail goto*//*Label 505*/ 13896, // Rule ID 447 //
6517        GIM_CheckFeatures, GIFBS_HasDSPR2,
6518        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addqh_w,
6519        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
6520        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
6521        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
6522        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
6523        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
6524        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
6525        // (intrinsic_wo_chain:{ *:[i32] } 4867:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (ADDQH_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
6526        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_W,
6527        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6528        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
6529        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
6530        GIR_EraseFromParent, /*InsnID*/0,
6531        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6532        // GIR_Coverage, 447,
6533        GIR_Done,
6534      // Label 505: @13896
6535      GIM_Try, /*On fail goto*//*Label 506*/ 13948, // Rule ID 448 //
6536        GIM_CheckFeatures, GIFBS_HasDSPR2,
6537        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addqh_r_w,
6538        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
6539        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
6540        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
6541        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
6542        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
6543        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
6544        // (intrinsic_wo_chain:{ *:[i32] } 4866:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (ADDQH_R_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
6545        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_R_W,
6546        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6547        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
6548        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
6549        GIR_EraseFromParent, /*InsnID*/0,
6550        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6551        // GIR_Coverage, 448,
6552        GIR_Done,
6553      // Label 506: @13948
6554      GIM_Try, /*On fail goto*//*Label 507*/ 14000, // Rule ID 449 //
6555        GIM_CheckFeatures, GIFBS_HasDSPR2,
6556        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subqh_w,
6557        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
6558        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
6559        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
6560        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
6561        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
6562        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
6563        // (intrinsic_wo_chain:{ *:[i32] } 5487:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (SUBQH_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
6564        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQH_W,
6565        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6566        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
6567        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
6568        GIR_EraseFromParent, /*InsnID*/0,
6569        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6570        // GIR_Coverage, 449,
6571        GIR_Done,
6572      // Label 507: @14000
6573      GIM_Try, /*On fail goto*//*Label 508*/ 14052, // Rule ID 450 //
6574        GIM_CheckFeatures, GIFBS_HasDSPR2,
6575        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subqh_r_w,
6576        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
6577        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
6578        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
6579        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
6580        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
6581        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
6582        // (intrinsic_wo_chain:{ *:[i32] } 5486:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (SUBQH_R_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
6583        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQH_R_W,
6584        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6585        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
6586        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
6587        GIR_EraseFromParent, /*InsnID*/0,
6588        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6589        // GIR_Coverage, 450,
6590        GIR_Done,
6591      // Label 508: @14052
6592      GIM_Try, /*On fail goto*//*Label 509*/ 14104, // Rule ID 467 //
6593        GIM_CheckFeatures, GIFBS_HasDSPR2,
6594        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_qb,
6595        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
6596        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
6597        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
6598        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6599        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
6600        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
6601        // (intrinsic_wo_chain:{ *:[v4i8] } 5413:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)  =>  (SHRAV_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
6602        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_QB,
6603        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6604        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
6605        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa
6606        GIR_EraseFromParent, /*InsnID*/0,
6607        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6608        // GIR_Coverage, 467,
6609        GIR_Done,
6610      // Label 509: @14104
6611      GIM_Try, /*On fail goto*//*Label 510*/ 14156, // Rule ID 469 //
6612        GIM_CheckFeatures, GIFBS_HasDSPR2,
6613        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_qb,
6614        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
6615        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
6616        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
6617        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6618        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
6619        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
6620        // (intrinsic_wo_chain:{ *:[v4i8] } 5415:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)  =>  (SHRAV_R_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
6621        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_R_QB,
6622        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6623        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
6624        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa
6625        GIR_EraseFromParent, /*InsnID*/0,
6626        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6627        // GIR_Coverage, 469,
6628        GIR_Done,
6629      // Label 510: @14156
6630      GIM_Try, /*On fail goto*//*Label 511*/ 14208, // Rule ID 470 //
6631        GIM_CheckFeatures, GIFBS_HasDSPR2,
6632        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shrl_ph,
6633        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
6634        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
6635        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
6636        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6637        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
6638        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
6639        // (intrinsic_wo_chain:{ *:[v2i16] } 5417:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)  =>  (SHRLV_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
6640        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRLV_PH,
6641        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6642        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
6643        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa
6644        GIR_EraseFromParent, /*InsnID*/0,
6645        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6646        // GIR_Coverage, 470,
6647        GIR_Done,
6648      // Label 511: @14208
6649      GIM_Try, /*On fail goto*//*Label 512*/ 14260, // Rule ID 479 //
6650        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6651        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_add_a_b,
6652        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
6653        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
6654        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
6655        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
6656        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
6657        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
6658        // (intrinsic_wo_chain:{ *:[v16i8] } 4857:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (ADD_A_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
6659        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADD_A_B,
6660        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6661        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6662        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6663        GIR_EraseFromParent, /*InsnID*/0,
6664        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6665        // GIR_Coverage, 479,
6666        GIR_Done,
6667      // Label 512: @14260
6668      GIM_Try, /*On fail goto*//*Label 513*/ 14312, // Rule ID 480 //
6669        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6670        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_add_a_h,
6671        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
6672        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
6673        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
6674        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
6675        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
6676        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
6677        // (intrinsic_wo_chain:{ *:[v8i16] } 4859:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (ADD_A_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
6678        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADD_A_H,
6679        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6680        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6681        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6682        GIR_EraseFromParent, /*InsnID*/0,
6683        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6684        // GIR_Coverage, 480,
6685        GIR_Done,
6686      // Label 513: @14312
6687      GIM_Try, /*On fail goto*//*Label 514*/ 14364, // Rule ID 481 //
6688        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6689        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_add_a_w,
6690        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
6691        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
6692        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
6693        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
6694        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
6695        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
6696        // (intrinsic_wo_chain:{ *:[v4i32] } 4860:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (ADD_A_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
6697        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADD_A_W,
6698        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6699        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6700        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6701        GIR_EraseFromParent, /*InsnID*/0,
6702        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6703        // GIR_Coverage, 481,
6704        GIR_Done,
6705      // Label 514: @14364
6706      GIM_Try, /*On fail goto*//*Label 515*/ 14416, // Rule ID 482 //
6707        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6708        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_add_a_d,
6709        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
6710        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
6711        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
6712        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
6713        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
6714        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
6715        // (intrinsic_wo_chain:{ *:[v2i64] } 4858:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (ADD_A_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
6716        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADD_A_D,
6717        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6718        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6719        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6720        GIR_EraseFromParent, /*InsnID*/0,
6721        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6722        // GIR_Coverage, 482,
6723        GIR_Done,
6724      // Label 515: @14416
6725      GIM_Try, /*On fail goto*//*Label 516*/ 14468, // Rule ID 483 //
6726        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6727        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_a_b,
6728        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
6729        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
6730        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
6731        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
6732        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
6733        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
6734        // (intrinsic_wo_chain:{ *:[v16i8] } 4868:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (ADDS_A_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
6735        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_A_B,
6736        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6737        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6738        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6739        GIR_EraseFromParent, /*InsnID*/0,
6740        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6741        // GIR_Coverage, 483,
6742        GIR_Done,
6743      // Label 516: @14468
6744      GIM_Try, /*On fail goto*//*Label 517*/ 14520, // Rule ID 484 //
6745        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6746        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_a_h,
6747        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
6748        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
6749        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
6750        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
6751        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
6752        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
6753        // (intrinsic_wo_chain:{ *:[v8i16] } 4870:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (ADDS_A_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
6754        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_A_H,
6755        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6756        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6757        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6758        GIR_EraseFromParent, /*InsnID*/0,
6759        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6760        // GIR_Coverage, 484,
6761        GIR_Done,
6762      // Label 517: @14520
6763      GIM_Try, /*On fail goto*//*Label 518*/ 14572, // Rule ID 485 //
6764        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6765        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_a_w,
6766        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
6767        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
6768        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
6769        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
6770        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
6771        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
6772        // (intrinsic_wo_chain:{ *:[v4i32] } 4871:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (ADDS_A_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
6773        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_A_W,
6774        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6775        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6776        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6777        GIR_EraseFromParent, /*InsnID*/0,
6778        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6779        // GIR_Coverage, 485,
6780        GIR_Done,
6781      // Label 518: @14572
6782      GIM_Try, /*On fail goto*//*Label 519*/ 14624, // Rule ID 486 //
6783        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6784        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_a_d,
6785        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
6786        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
6787        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
6788        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
6789        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
6790        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
6791        // (intrinsic_wo_chain:{ *:[v2i64] } 4869:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (ADDS_A_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
6792        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_A_D,
6793        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6794        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6795        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6796        GIR_EraseFromParent, /*InsnID*/0,
6797        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6798        // GIR_Coverage, 486,
6799        GIR_Done,
6800      // Label 519: @14624
6801      GIM_Try, /*On fail goto*//*Label 520*/ 14676, // Rule ID 487 //
6802        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6803        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_s_b,
6804        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
6805        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
6806        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
6807        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
6808        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
6809        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
6810        // (intrinsic_wo_chain:{ *:[v16i8] } 4872:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (ADDS_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
6811        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_S_B,
6812        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6813        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6814        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6815        GIR_EraseFromParent, /*InsnID*/0,
6816        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6817        // GIR_Coverage, 487,
6818        GIR_Done,
6819      // Label 520: @14676
6820      GIM_Try, /*On fail goto*//*Label 521*/ 14728, // Rule ID 488 //
6821        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6822        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_s_h,
6823        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
6824        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
6825        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
6826        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
6827        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
6828        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
6829        // (intrinsic_wo_chain:{ *:[v8i16] } 4874:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (ADDS_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
6830        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_S_H,
6831        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6832        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6833        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6834        GIR_EraseFromParent, /*InsnID*/0,
6835        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6836        // GIR_Coverage, 488,
6837        GIR_Done,
6838      // Label 521: @14728
6839      GIM_Try, /*On fail goto*//*Label 522*/ 14780, // Rule ID 489 //
6840        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6841        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_s_w,
6842        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
6843        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
6844        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
6845        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
6846        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
6847        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
6848        // (intrinsic_wo_chain:{ *:[v4i32] } 4875:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (ADDS_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
6849        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_S_W,
6850        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6851        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6852        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6853        GIR_EraseFromParent, /*InsnID*/0,
6854        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6855        // GIR_Coverage, 489,
6856        GIR_Done,
6857      // Label 522: @14780
6858      GIM_Try, /*On fail goto*//*Label 523*/ 14832, // Rule ID 490 //
6859        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6860        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_s_d,
6861        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
6862        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
6863        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
6864        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
6865        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
6866        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
6867        // (intrinsic_wo_chain:{ *:[v2i64] } 4873:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (ADDS_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
6868        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_S_D,
6869        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6870        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6871        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6872        GIR_EraseFromParent, /*InsnID*/0,
6873        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6874        // GIR_Coverage, 490,
6875        GIR_Done,
6876      // Label 523: @14832
6877      GIM_Try, /*On fail goto*//*Label 524*/ 14884, // Rule ID 491 //
6878        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6879        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_u_b,
6880        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
6881        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
6882        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
6883        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
6884        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
6885        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
6886        // (intrinsic_wo_chain:{ *:[v16i8] } 4876:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (ADDS_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
6887        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_U_B,
6888        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6889        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6890        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6891        GIR_EraseFromParent, /*InsnID*/0,
6892        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6893        // GIR_Coverage, 491,
6894        GIR_Done,
6895      // Label 524: @14884
6896      GIM_Try, /*On fail goto*//*Label 525*/ 14936, // Rule ID 492 //
6897        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6898        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_u_h,
6899        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
6900        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
6901        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
6902        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
6903        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
6904        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
6905        // (intrinsic_wo_chain:{ *:[v8i16] } 4878:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (ADDS_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
6906        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_U_H,
6907        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6908        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6909        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6910        GIR_EraseFromParent, /*InsnID*/0,
6911        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6912        // GIR_Coverage, 492,
6913        GIR_Done,
6914      // Label 525: @14936
6915      GIM_Try, /*On fail goto*//*Label 526*/ 14988, // Rule ID 493 //
6916        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6917        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_u_w,
6918        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
6919        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
6920        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
6921        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
6922        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
6923        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
6924        // (intrinsic_wo_chain:{ *:[v4i32] } 4879:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (ADDS_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
6925        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_U_W,
6926        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6927        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6928        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6929        GIR_EraseFromParent, /*InsnID*/0,
6930        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6931        // GIR_Coverage, 493,
6932        GIR_Done,
6933      // Label 526: @14988
6934      GIM_Try, /*On fail goto*//*Label 527*/ 15040, // Rule ID 494 //
6935        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6936        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_u_d,
6937        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
6938        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
6939        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
6940        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
6941        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
6942        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
6943        // (intrinsic_wo_chain:{ *:[v2i64] } 4877:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (ADDS_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
6944        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_U_D,
6945        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6946        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6947        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6948        GIR_EraseFromParent, /*InsnID*/0,
6949        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6950        // GIR_Coverage, 494,
6951        GIR_Done,
6952      // Label 527: @15040
6953      GIM_Try, /*On fail goto*//*Label 528*/ 15092, // Rule ID 508 //
6954        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6955        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_asub_s_b,
6956        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
6957        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
6958        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
6959        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
6960        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
6961        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
6962        // (intrinsic_wo_chain:{ *:[v16i8] } 4899:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (ASUB_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
6963        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_S_B,
6964        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6965        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6966        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6967        GIR_EraseFromParent, /*InsnID*/0,
6968        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6969        // GIR_Coverage, 508,
6970        GIR_Done,
6971      // Label 528: @15092
6972      GIM_Try, /*On fail goto*//*Label 529*/ 15144, // Rule ID 509 //
6973        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6974        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_asub_s_h,
6975        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
6976        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
6977        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
6978        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
6979        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
6980        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
6981        // (intrinsic_wo_chain:{ *:[v8i16] } 4901:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (ASUB_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
6982        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_S_H,
6983        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6984        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6985        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6986        GIR_EraseFromParent, /*InsnID*/0,
6987        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6988        // GIR_Coverage, 509,
6989        GIR_Done,
6990      // Label 529: @15144
6991      GIM_Try, /*On fail goto*//*Label 530*/ 15196, // Rule ID 510 //
6992        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6993        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_asub_s_w,
6994        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
6995        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
6996        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
6997        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
6998        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
6999        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7000        // (intrinsic_wo_chain:{ *:[v4i32] } 4902:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (ASUB_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
7001        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_S_W,
7002        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7003        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7004        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7005        GIR_EraseFromParent, /*InsnID*/0,
7006        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7007        // GIR_Coverage, 510,
7008        GIR_Done,
7009      // Label 530: @15196
7010      GIM_Try, /*On fail goto*//*Label 531*/ 15248, // Rule ID 511 //
7011        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7012        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_asub_s_d,
7013        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7014        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7015        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7016        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7017        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7018        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7019        // (intrinsic_wo_chain:{ *:[v2i64] } 4900:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (ASUB_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
7020        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_S_D,
7021        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7022        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7023        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7024        GIR_EraseFromParent, /*InsnID*/0,
7025        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7026        // GIR_Coverage, 511,
7027        GIR_Done,
7028      // Label 531: @15248
7029      GIM_Try, /*On fail goto*//*Label 532*/ 15300, // Rule ID 512 //
7030        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7031        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_asub_u_b,
7032        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
7033        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
7034        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
7035        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
7036        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
7037        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
7038        // (intrinsic_wo_chain:{ *:[v16i8] } 4903:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (ASUB_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
7039        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_U_B,
7040        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7041        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7042        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7043        GIR_EraseFromParent, /*InsnID*/0,
7044        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7045        // GIR_Coverage, 512,
7046        GIR_Done,
7047      // Label 532: @15300
7048      GIM_Try, /*On fail goto*//*Label 533*/ 15352, // Rule ID 513 //
7049        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7050        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_asub_u_h,
7051        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
7052        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
7053        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
7054        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
7055        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
7056        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
7057        // (intrinsic_wo_chain:{ *:[v8i16] } 4905:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (ASUB_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
7058        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_U_H,
7059        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7060        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7061        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7062        GIR_EraseFromParent, /*InsnID*/0,
7063        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7064        // GIR_Coverage, 513,
7065        GIR_Done,
7066      // Label 533: @15352
7067      GIM_Try, /*On fail goto*//*Label 534*/ 15404, // Rule ID 514 //
7068        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7069        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_asub_u_w,
7070        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7071        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7072        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7073        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7074        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7075        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7076        // (intrinsic_wo_chain:{ *:[v4i32] } 4906:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (ASUB_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
7077        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_U_W,
7078        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7079        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7080        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7081        GIR_EraseFromParent, /*InsnID*/0,
7082        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7083        // GIR_Coverage, 514,
7084        GIR_Done,
7085      // Label 534: @15404
7086      GIM_Try, /*On fail goto*//*Label 535*/ 15456, // Rule ID 515 //
7087        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7088        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_asub_u_d,
7089        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7090        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7091        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7092        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7093        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7094        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7095        // (intrinsic_wo_chain:{ *:[v2i64] } 4904:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (ASUB_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
7096        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_U_D,
7097        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7098        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7099        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7100        GIR_EraseFromParent, /*InsnID*/0,
7101        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7102        // GIR_Coverage, 515,
7103        GIR_Done,
7104      // Label 535: @15456
7105      GIM_Try, /*On fail goto*//*Label 536*/ 15508, // Rule ID 516 //
7106        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7107        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ave_s_b,
7108        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
7109        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
7110        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
7111        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
7112        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
7113        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
7114        // (intrinsic_wo_chain:{ *:[v16i8] } 4907:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (AVE_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
7115        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_S_B,
7116        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7117        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7118        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7119        GIR_EraseFromParent, /*InsnID*/0,
7120        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7121        // GIR_Coverage, 516,
7122        GIR_Done,
7123      // Label 536: @15508
7124      GIM_Try, /*On fail goto*//*Label 537*/ 15560, // Rule ID 517 //
7125        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7126        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ave_s_h,
7127        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
7128        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
7129        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
7130        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
7131        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
7132        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
7133        // (intrinsic_wo_chain:{ *:[v8i16] } 4909:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (AVE_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
7134        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_S_H,
7135        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7136        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7137        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7138        GIR_EraseFromParent, /*InsnID*/0,
7139        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7140        // GIR_Coverage, 517,
7141        GIR_Done,
7142      // Label 537: @15560
7143      GIM_Try, /*On fail goto*//*Label 538*/ 15612, // Rule ID 518 //
7144        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7145        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ave_s_w,
7146        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7147        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7148        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7149        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7150        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7151        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7152        // (intrinsic_wo_chain:{ *:[v4i32] } 4910:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (AVE_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
7153        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_S_W,
7154        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7155        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7156        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7157        GIR_EraseFromParent, /*InsnID*/0,
7158        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7159        // GIR_Coverage, 518,
7160        GIR_Done,
7161      // Label 538: @15612
7162      GIM_Try, /*On fail goto*//*Label 539*/ 15664, // Rule ID 519 //
7163        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7164        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ave_s_d,
7165        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7166        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7167        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7168        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7169        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7170        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7171        // (intrinsic_wo_chain:{ *:[v2i64] } 4908:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (AVE_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
7172        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_S_D,
7173        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7174        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7175        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7176        GIR_EraseFromParent, /*InsnID*/0,
7177        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7178        // GIR_Coverage, 519,
7179        GIR_Done,
7180      // Label 539: @15664
7181      GIM_Try, /*On fail goto*//*Label 540*/ 15716, // Rule ID 520 //
7182        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7183        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ave_u_b,
7184        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
7185        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
7186        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
7187        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
7188        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
7189        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
7190        // (intrinsic_wo_chain:{ *:[v16i8] } 4911:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (AVE_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
7191        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_U_B,
7192        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7193        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7194        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7195        GIR_EraseFromParent, /*InsnID*/0,
7196        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7197        // GIR_Coverage, 520,
7198        GIR_Done,
7199      // Label 540: @15716
7200      GIM_Try, /*On fail goto*//*Label 541*/ 15768, // Rule ID 521 //
7201        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7202        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ave_u_h,
7203        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
7204        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
7205        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
7206        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
7207        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
7208        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
7209        // (intrinsic_wo_chain:{ *:[v8i16] } 4913:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (AVE_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
7210        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_U_H,
7211        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7212        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7213        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7214        GIR_EraseFromParent, /*InsnID*/0,
7215        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7216        // GIR_Coverage, 521,
7217        GIR_Done,
7218      // Label 541: @15768
7219      GIM_Try, /*On fail goto*//*Label 542*/ 15820, // Rule ID 522 //
7220        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7221        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ave_u_w,
7222        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7223        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7224        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7225        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7226        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7227        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7228        // (intrinsic_wo_chain:{ *:[v4i32] } 4914:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (AVE_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
7229        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_U_W,
7230        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7231        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7232        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7233        GIR_EraseFromParent, /*InsnID*/0,
7234        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7235        // GIR_Coverage, 522,
7236        GIR_Done,
7237      // Label 542: @15820
7238      GIM_Try, /*On fail goto*//*Label 543*/ 15872, // Rule ID 523 //
7239        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7240        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ave_u_d,
7241        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7242        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7243        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7244        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7245        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7246        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7247        // (intrinsic_wo_chain:{ *:[v2i64] } 4912:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (AVE_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
7248        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_U_D,
7249        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7250        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7251        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7252        GIR_EraseFromParent, /*InsnID*/0,
7253        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7254        // GIR_Coverage, 523,
7255        GIR_Done,
7256      // Label 543: @15872
7257      GIM_Try, /*On fail goto*//*Label 544*/ 15924, // Rule ID 524 //
7258        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7259        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_aver_s_b,
7260        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
7261        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
7262        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
7263        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
7264        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
7265        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
7266        // (intrinsic_wo_chain:{ *:[v16i8] } 4915:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (AVER_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
7267        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_S_B,
7268        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7269        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7270        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7271        GIR_EraseFromParent, /*InsnID*/0,
7272        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7273        // GIR_Coverage, 524,
7274        GIR_Done,
7275      // Label 544: @15924
7276      GIM_Try, /*On fail goto*//*Label 545*/ 15976, // Rule ID 525 //
7277        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7278        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_aver_s_h,
7279        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
7280        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
7281        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
7282        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
7283        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
7284        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
7285        // (intrinsic_wo_chain:{ *:[v8i16] } 4917:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (AVER_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
7286        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_S_H,
7287        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7288        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7289        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7290        GIR_EraseFromParent, /*InsnID*/0,
7291        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7292        // GIR_Coverage, 525,
7293        GIR_Done,
7294      // Label 545: @15976
7295      GIM_Try, /*On fail goto*//*Label 546*/ 16028, // Rule ID 526 //
7296        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7297        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_aver_s_w,
7298        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7299        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7300        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7301        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7302        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7303        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7304        // (intrinsic_wo_chain:{ *:[v4i32] } 4918:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (AVER_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
7305        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_S_W,
7306        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7307        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7308        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7309        GIR_EraseFromParent, /*InsnID*/0,
7310        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7311        // GIR_Coverage, 526,
7312        GIR_Done,
7313      // Label 546: @16028
7314      GIM_Try, /*On fail goto*//*Label 547*/ 16080, // Rule ID 527 //
7315        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7316        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_aver_s_d,
7317        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7318        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7319        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7320        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7321        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7322        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7323        // (intrinsic_wo_chain:{ *:[v2i64] } 4916:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (AVER_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
7324        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_S_D,
7325        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7326        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7327        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7328        GIR_EraseFromParent, /*InsnID*/0,
7329        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7330        // GIR_Coverage, 527,
7331        GIR_Done,
7332      // Label 547: @16080
7333      GIM_Try, /*On fail goto*//*Label 548*/ 16132, // Rule ID 528 //
7334        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7335        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_aver_u_b,
7336        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
7337        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
7338        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
7339        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
7340        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
7341        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
7342        // (intrinsic_wo_chain:{ *:[v16i8] } 4919:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (AVER_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
7343        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_U_B,
7344        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7345        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7346        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7347        GIR_EraseFromParent, /*InsnID*/0,
7348        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7349        // GIR_Coverage, 528,
7350        GIR_Done,
7351      // Label 548: @16132
7352      GIM_Try, /*On fail goto*//*Label 549*/ 16184, // Rule ID 529 //
7353        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7354        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_aver_u_h,
7355        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
7356        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
7357        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
7358        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
7359        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
7360        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
7361        // (intrinsic_wo_chain:{ *:[v8i16] } 4921:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (AVER_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
7362        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_U_H,
7363        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7364        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7365        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7366        GIR_EraseFromParent, /*InsnID*/0,
7367        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7368        // GIR_Coverage, 529,
7369        GIR_Done,
7370      // Label 549: @16184
7371      GIM_Try, /*On fail goto*//*Label 550*/ 16236, // Rule ID 530 //
7372        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7373        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_aver_u_w,
7374        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7375        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7376        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7377        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7378        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7379        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7380        // (intrinsic_wo_chain:{ *:[v4i32] } 4922:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (AVER_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
7381        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_U_W,
7382        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7383        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7384        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7385        GIR_EraseFromParent, /*InsnID*/0,
7386        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7387        // GIR_Coverage, 530,
7388        GIR_Done,
7389      // Label 550: @16236
7390      GIM_Try, /*On fail goto*//*Label 551*/ 16288, // Rule ID 531 //
7391        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7392        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_aver_u_d,
7393        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7394        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7395        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7396        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7397        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7398        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7399        // (intrinsic_wo_chain:{ *:[v2i64] } 4920:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (AVER_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
7400        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_U_D,
7401        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7402        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7403        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7404        GIR_EraseFromParent, /*InsnID*/0,
7405        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7406        // GIR_Coverage, 531,
7407        GIR_Done,
7408      // Label 551: @16288
7409      GIM_Try, /*On fail goto*//*Label 552*/ 16340, // Rule ID 640 //
7410        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7411        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dotp_s_h,
7412        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
7413        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
7414        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
7415        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
7416        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
7417        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
7418        // (intrinsic_wo_chain:{ *:[v8i16] } 5054:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (DOTP_S_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
7419        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DOTP_S_H,
7420        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7421        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7422        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7423        GIR_EraseFromParent, /*InsnID*/0,
7424        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7425        // GIR_Coverage, 640,
7426        GIR_Done,
7427      // Label 552: @16340
7428      GIM_Try, /*On fail goto*//*Label 553*/ 16392, // Rule ID 641 //
7429        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7430        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dotp_s_w,
7431        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7432        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
7433        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
7434        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7435        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
7436        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
7437        // (intrinsic_wo_chain:{ *:[v4i32] } 5055:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (DOTP_S_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
7438        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DOTP_S_W,
7439        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7440        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7441        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7442        GIR_EraseFromParent, /*InsnID*/0,
7443        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7444        // GIR_Coverage, 641,
7445        GIR_Done,
7446      // Label 553: @16392
7447      GIM_Try, /*On fail goto*//*Label 554*/ 16444, // Rule ID 642 //
7448        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7449        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dotp_s_d,
7450        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7451        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7452        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7453        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7454        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7455        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7456        // (intrinsic_wo_chain:{ *:[v2i64] } 5053:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (DOTP_S_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
7457        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DOTP_S_D,
7458        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7459        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7460        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7461        GIR_EraseFromParent, /*InsnID*/0,
7462        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7463        // GIR_Coverage, 642,
7464        GIR_Done,
7465      // Label 554: @16444
7466      GIM_Try, /*On fail goto*//*Label 555*/ 16496, // Rule ID 643 //
7467        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7468        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dotp_u_h,
7469        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
7470        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
7471        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
7472        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
7473        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
7474        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
7475        // (intrinsic_wo_chain:{ *:[v8i16] } 5057:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (DOTP_U_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
7476        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DOTP_U_H,
7477        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7478        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7479        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7480        GIR_EraseFromParent, /*InsnID*/0,
7481        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7482        // GIR_Coverage, 643,
7483        GIR_Done,
7484      // Label 555: @16496
7485      GIM_Try, /*On fail goto*//*Label 556*/ 16548, // Rule ID 644 //
7486        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7487        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dotp_u_w,
7488        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7489        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
7490        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
7491        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7492        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
7493        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
7494        // (intrinsic_wo_chain:{ *:[v4i32] } 5058:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (DOTP_U_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
7495        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DOTP_U_W,
7496        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7497        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7498        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7499        GIR_EraseFromParent, /*InsnID*/0,
7500        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7501        // GIR_Coverage, 644,
7502        GIR_Done,
7503      // Label 556: @16548
7504      GIM_Try, /*On fail goto*//*Label 557*/ 16600, // Rule ID 645 //
7505        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7506        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dotp_u_d,
7507        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7508        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7509        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7510        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7511        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7512        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7513        // (intrinsic_wo_chain:{ *:[v2i64] } 5056:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (DOTP_U_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
7514        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DOTP_U_D,
7515        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7516        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7517        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7518        GIR_EraseFromParent, /*InsnID*/0,
7519        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7520        // GIR_Coverage, 645,
7521        GIR_Done,
7522      // Label 557: @16600
7523      GIM_Try, /*On fail goto*//*Label 558*/ 16652, // Rule ID 660 //
7524        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7525        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fcaf_w,
7526        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7527        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7528        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7529        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7530        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7531        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7532        // (intrinsic_wo_chain:{ *:[v4i32] } 5096:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FCAF_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
7533        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FCAF_W,
7534        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7535        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7536        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7537        GIR_EraseFromParent, /*InsnID*/0,
7538        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7539        // GIR_Coverage, 660,
7540        GIR_Done,
7541      // Label 558: @16652
7542      GIM_Try, /*On fail goto*//*Label 559*/ 16704, // Rule ID 661 //
7543        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7544        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fcaf_d,
7545        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7546        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7547        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7548        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7549        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7550        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7551        // (intrinsic_wo_chain:{ *:[v2i64] } 5095:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FCAF_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
7552        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FCAF_D,
7553        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7554        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7555        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7556        GIR_EraseFromParent, /*InsnID*/0,
7557        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7558        // GIR_Coverage, 661,
7559        GIR_Done,
7560      // Label 559: @16704
7561      GIM_Try, /*On fail goto*//*Label 560*/ 16756, // Rule ID 686 //
7562        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7563        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fexdo_h,
7564        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
7565        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7566        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7567        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
7568        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7569        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7570        // (intrinsic_wo_chain:{ *:[v8f16] } 5121:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FEXDO_H:{ *:[v8f16] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
7571        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXDO_H,
7572        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7573        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7574        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7575        GIR_EraseFromParent, /*InsnID*/0,
7576        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7577        // GIR_Coverage, 686,
7578        GIR_Done,
7579      // Label 560: @16756
7580      GIM_Try, /*On fail goto*//*Label 561*/ 16808, // Rule ID 687 //
7581        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7582        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fexdo_w,
7583        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7584        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7585        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7586        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7587        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7588        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7589        // (intrinsic_wo_chain:{ *:[v4f32] } 5122:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FEXDO_W:{ *:[v4f32] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
7590        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXDO_W,
7591        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7592        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7593        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7594        GIR_EraseFromParent, /*InsnID*/0,
7595        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7596        // GIR_Coverage, 687,
7597        GIR_Done,
7598      // Label 561: @16808
7599      GIM_Try, /*On fail goto*//*Label 562*/ 16860, // Rule ID 714 //
7600        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7601        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fmax_w,
7602        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7603        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7604        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7605        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7606        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7607        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7608        // (intrinsic_wo_chain:{ *:[v4f32] } 5148:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FMAX_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
7609        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMAX_W,
7610        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7611        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7612        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7613        GIR_EraseFromParent, /*InsnID*/0,
7614        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7615        // GIR_Coverage, 714,
7616        GIR_Done,
7617      // Label 562: @16860
7618      GIM_Try, /*On fail goto*//*Label 563*/ 16912, // Rule ID 715 //
7619        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7620        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fmax_d,
7621        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7622        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7623        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7624        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7625        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7626        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7627        // (intrinsic_wo_chain:{ *:[v2f64] } 5147:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FMAX_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
7628        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMAX_D,
7629        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7630        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7631        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7632        GIR_EraseFromParent, /*InsnID*/0,
7633        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7634        // GIR_Coverage, 715,
7635        GIR_Done,
7636      // Label 563: @16912
7637      GIM_Try, /*On fail goto*//*Label 564*/ 16964, // Rule ID 716 //
7638        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7639        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fmax_a_w,
7640        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7641        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7642        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7643        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7644        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7645        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7646        // (intrinsic_wo_chain:{ *:[v4f32] } 5146:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FMAX_A_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
7647        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMAX_A_W,
7648        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7649        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7650        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7651        GIR_EraseFromParent, /*InsnID*/0,
7652        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7653        // GIR_Coverage, 716,
7654        GIR_Done,
7655      // Label 564: @16964
7656      GIM_Try, /*On fail goto*//*Label 565*/ 17016, // Rule ID 717 //
7657        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7658        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fmax_a_d,
7659        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7660        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7661        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7662        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7663        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7664        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7665        // (intrinsic_wo_chain:{ *:[v2f64] } 5145:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FMAX_A_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
7666        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMAX_A_D,
7667        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7668        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7669        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7670        GIR_EraseFromParent, /*InsnID*/0,
7671        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7672        // GIR_Coverage, 717,
7673        GIR_Done,
7674      // Label 565: @17016
7675      GIM_Try, /*On fail goto*//*Label 566*/ 17068, // Rule ID 718 //
7676        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7677        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fmin_w,
7678        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7679        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7680        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7681        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7682        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7683        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7684        // (intrinsic_wo_chain:{ *:[v4f32] } 5152:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FMIN_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
7685        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMIN_W,
7686        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7687        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7688        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7689        GIR_EraseFromParent, /*InsnID*/0,
7690        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7691        // GIR_Coverage, 718,
7692        GIR_Done,
7693      // Label 566: @17068
7694      GIM_Try, /*On fail goto*//*Label 567*/ 17120, // Rule ID 719 //
7695        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7696        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fmin_d,
7697        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7698        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7699        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7700        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7701        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7702        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7703        // (intrinsic_wo_chain:{ *:[v2f64] } 5151:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FMIN_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
7704        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMIN_D,
7705        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7706        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7707        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7708        GIR_EraseFromParent, /*InsnID*/0,
7709        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7710        // GIR_Coverage, 719,
7711        GIR_Done,
7712      // Label 567: @17120
7713      GIM_Try, /*On fail goto*//*Label 568*/ 17172, // Rule ID 720 //
7714        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7715        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fmin_a_w,
7716        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7717        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7718        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7719        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7720        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7721        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7722        // (intrinsic_wo_chain:{ *:[v4f32] } 5150:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FMIN_A_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
7723        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMIN_A_W,
7724        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7725        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7726        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7727        GIR_EraseFromParent, /*InsnID*/0,
7728        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7729        // GIR_Coverage, 720,
7730        GIR_Done,
7731      // Label 568: @17172
7732      GIM_Try, /*On fail goto*//*Label 569*/ 17224, // Rule ID 721 //
7733        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7734        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fmin_a_d,
7735        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7736        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7737        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7738        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7739        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7740        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7741        // (intrinsic_wo_chain:{ *:[v2f64] } 5149:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FMIN_A_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
7742        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMIN_A_D,
7743        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7744        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7745        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7746        GIR_EraseFromParent, /*InsnID*/0,
7747        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7748        // GIR_Coverage, 721,
7749        GIR_Done,
7750      // Label 569: @17224
7751      GIM_Try, /*On fail goto*//*Label 570*/ 17276, // Rule ID 732 //
7752        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7753        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsaf_w,
7754        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7755        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7756        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7757        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7758        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7759        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7760        // (intrinsic_wo_chain:{ *:[v4i32] } 5164:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FSAF_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
7761        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSAF_W,
7762        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7763        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7764        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7765        GIR_EraseFromParent, /*InsnID*/0,
7766        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7767        // GIR_Coverage, 732,
7768        GIR_Done,
7769      // Label 570: @17276
7770      GIM_Try, /*On fail goto*//*Label 571*/ 17328, // Rule ID 733 //
7771        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7772        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsaf_d,
7773        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7774        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7775        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7776        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7777        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7778        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7779        // (intrinsic_wo_chain:{ *:[v2i64] } 5163:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FSAF_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
7780        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSAF_D,
7781        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7782        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7783        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7784        GIR_EraseFromParent, /*InsnID*/0,
7785        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7786        // GIR_Coverage, 733,
7787        GIR_Done,
7788      // Label 571: @17328
7789      GIM_Try, /*On fail goto*//*Label 572*/ 17380, // Rule ID 734 //
7790        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7791        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fseq_w,
7792        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7793        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7794        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7795        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7796        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7797        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7798        // (intrinsic_wo_chain:{ *:[v4i32] } 5166:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FSEQ_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
7799        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSEQ_W,
7800        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7801        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7802        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7803        GIR_EraseFromParent, /*InsnID*/0,
7804        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7805        // GIR_Coverage, 734,
7806        GIR_Done,
7807      // Label 572: @17380
7808      GIM_Try, /*On fail goto*//*Label 573*/ 17432, // Rule ID 735 //
7809        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7810        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fseq_d,
7811        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7812        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7813        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7814        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7815        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7816        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7817        // (intrinsic_wo_chain:{ *:[v2i64] } 5165:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FSEQ_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
7818        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSEQ_D,
7819        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7820        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7821        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7822        GIR_EraseFromParent, /*InsnID*/0,
7823        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7824        // GIR_Coverage, 735,
7825        GIR_Done,
7826      // Label 573: @17432
7827      GIM_Try, /*On fail goto*//*Label 574*/ 17484, // Rule ID 736 //
7828        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7829        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsle_w,
7830        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7831        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7832        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7833        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7834        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7835        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7836        // (intrinsic_wo_chain:{ *:[v4i32] } 5168:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FSLE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
7837        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSLE_W,
7838        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7839        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7840        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7841        GIR_EraseFromParent, /*InsnID*/0,
7842        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7843        // GIR_Coverage, 736,
7844        GIR_Done,
7845      // Label 574: @17484
7846      GIM_Try, /*On fail goto*//*Label 575*/ 17536, // Rule ID 737 //
7847        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7848        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsle_d,
7849        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7850        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7851        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7852        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7853        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7854        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7855        // (intrinsic_wo_chain:{ *:[v2i64] } 5167:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FSLE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
7856        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSLE_D,
7857        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7858        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7859        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7860        GIR_EraseFromParent, /*InsnID*/0,
7861        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7862        // GIR_Coverage, 737,
7863        GIR_Done,
7864      // Label 575: @17536
7865      GIM_Try, /*On fail goto*//*Label 576*/ 17588, // Rule ID 738 //
7866        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7867        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fslt_w,
7868        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7869        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7870        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7871        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7872        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7873        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7874        // (intrinsic_wo_chain:{ *:[v4i32] } 5170:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FSLT_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
7875        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSLT_W,
7876        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7877        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7878        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7879        GIR_EraseFromParent, /*InsnID*/0,
7880        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7881        // GIR_Coverage, 738,
7882        GIR_Done,
7883      // Label 576: @17588
7884      GIM_Try, /*On fail goto*//*Label 577*/ 17640, // Rule ID 739 //
7885        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7886        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fslt_d,
7887        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7888        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7889        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7890        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7891        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7892        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7893        // (intrinsic_wo_chain:{ *:[v2i64] } 5169:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FSLT_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
7894        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSLT_D,
7895        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7896        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7897        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7898        GIR_EraseFromParent, /*InsnID*/0,
7899        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7900        // GIR_Coverage, 739,
7901        GIR_Done,
7902      // Label 577: @17640
7903      GIM_Try, /*On fail goto*//*Label 578*/ 17692, // Rule ID 740 //
7904        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7905        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsne_w,
7906        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7907        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7908        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7909        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7910        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7911        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7912        // (intrinsic_wo_chain:{ *:[v4i32] } 5172:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FSNE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
7913        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSNE_W,
7914        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7915        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7916        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7917        GIR_EraseFromParent, /*InsnID*/0,
7918        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7919        // GIR_Coverage, 740,
7920        GIR_Done,
7921      // Label 578: @17692
7922      GIM_Try, /*On fail goto*//*Label 579*/ 17744, // Rule ID 741 //
7923        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7924        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsne_d,
7925        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7926        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7927        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7928        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7929        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7930        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7931        // (intrinsic_wo_chain:{ *:[v2i64] } 5171:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FSNE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
7932        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSNE_D,
7933        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7934        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7935        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7936        GIR_EraseFromParent, /*InsnID*/0,
7937        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7938        // GIR_Coverage, 741,
7939        GIR_Done,
7940      // Label 579: @17744
7941      GIM_Try, /*On fail goto*//*Label 580*/ 17796, // Rule ID 742 //
7942        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7943        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsor_w,
7944        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7945        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7946        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7947        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7948        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7949        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7950        // (intrinsic_wo_chain:{ *:[v4i32] } 5174:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FSOR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
7951        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSOR_W,
7952        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7953        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7954        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7955        GIR_EraseFromParent, /*InsnID*/0,
7956        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7957        // GIR_Coverage, 742,
7958        GIR_Done,
7959      // Label 580: @17796
7960      GIM_Try, /*On fail goto*//*Label 581*/ 17848, // Rule ID 743 //
7961        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7962        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsor_d,
7963        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7964        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7965        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7966        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7967        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7968        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7969        // (intrinsic_wo_chain:{ *:[v2i64] } 5173:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FSOR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
7970        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSOR_D,
7971        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7972        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7973        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7974        GIR_EraseFromParent, /*InsnID*/0,
7975        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7976        // GIR_Coverage, 743,
7977        GIR_Done,
7978      // Label 581: @17848
7979      GIM_Try, /*On fail goto*//*Label 582*/ 17900, // Rule ID 748 //
7980        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7981        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsueq_w,
7982        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7983        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7984        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7985        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7986        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7987        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7988        // (intrinsic_wo_chain:{ *:[v4i32] } 5180:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FSUEQ_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
7989        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSUEQ_W,
7990        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7991        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7992        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7993        GIR_EraseFromParent, /*InsnID*/0,
7994        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7995        // GIR_Coverage, 748,
7996        GIR_Done,
7997      // Label 582: @17900
7998      GIM_Try, /*On fail goto*//*Label 583*/ 17952, // Rule ID 749 //
7999        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8000        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsueq_d,
8001        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
8002        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
8003        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
8004        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
8005        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
8006        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
8007        // (intrinsic_wo_chain:{ *:[v2i64] } 5179:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FSUEQ_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
8008        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSUEQ_D,
8009        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8010        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8011        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8012        GIR_EraseFromParent, /*InsnID*/0,
8013        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8014        // GIR_Coverage, 749,
8015        GIR_Done,
8016      // Label 583: @17952
8017      GIM_Try, /*On fail goto*//*Label 584*/ 18004, // Rule ID 750 //
8018        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8019        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsule_w,
8020        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
8021        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
8022        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
8023        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
8024        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
8025        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
8026        // (intrinsic_wo_chain:{ *:[v4i32] } 5182:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FSULE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
8027        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSULE_W,
8028        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8029        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8030        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8031        GIR_EraseFromParent, /*InsnID*/0,
8032        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8033        // GIR_Coverage, 750,
8034        GIR_Done,
8035      // Label 584: @18004
8036      GIM_Try, /*On fail goto*//*Label 585*/ 18056, // Rule ID 751 //
8037        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8038        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsule_d,
8039        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
8040        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
8041        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
8042        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
8043        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
8044        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
8045        // (intrinsic_wo_chain:{ *:[v2i64] } 5181:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FSULE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
8046        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSULE_D,
8047        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8048        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8049        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8050        GIR_EraseFromParent, /*InsnID*/0,
8051        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8052        // GIR_Coverage, 751,
8053        GIR_Done,
8054      // Label 585: @18056
8055      GIM_Try, /*On fail goto*//*Label 586*/ 18108, // Rule ID 752 //
8056        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8057        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsult_w,
8058        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
8059        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
8060        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
8061        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
8062        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
8063        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
8064        // (intrinsic_wo_chain:{ *:[v4i32] } 5184:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FSULT_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
8065        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSULT_W,
8066        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8067        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8068        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8069        GIR_EraseFromParent, /*InsnID*/0,
8070        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8071        // GIR_Coverage, 752,
8072        GIR_Done,
8073      // Label 586: @18108
8074      GIM_Try, /*On fail goto*//*Label 587*/ 18160, // Rule ID 753 //
8075        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8076        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsult_d,
8077        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
8078        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
8079        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
8080        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
8081        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
8082        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
8083        // (intrinsic_wo_chain:{ *:[v2i64] } 5183:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FSULT_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
8084        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSULT_D,
8085        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8086        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8087        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8088        GIR_EraseFromParent, /*InsnID*/0,
8089        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8090        // GIR_Coverage, 753,
8091        GIR_Done,
8092      // Label 587: @18160
8093      GIM_Try, /*On fail goto*//*Label 588*/ 18212, // Rule ID 754 //
8094        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8095        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsun_w,
8096        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
8097        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
8098        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
8099        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
8100        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
8101        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
8102        // (intrinsic_wo_chain:{ *:[v4i32] } 5186:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FSUN_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
8103        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSUN_W,
8104        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8105        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8106        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8107        GIR_EraseFromParent, /*InsnID*/0,
8108        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8109        // GIR_Coverage, 754,
8110        GIR_Done,
8111      // Label 588: @18212
8112      GIM_Try, /*On fail goto*//*Label 589*/ 18264, // Rule ID 755 //
8113        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8114        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsun_d,
8115        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
8116        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
8117        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
8118        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
8119        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
8120        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
8121        // (intrinsic_wo_chain:{ *:[v2i64] } 5185:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FSUN_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
8122        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSUN_D,
8123        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8124        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8125        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8126        GIR_EraseFromParent, /*InsnID*/0,
8127        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8128        // GIR_Coverage, 755,
8129        GIR_Done,
8130      // Label 589: @18264
8131      GIM_Try, /*On fail goto*//*Label 590*/ 18316, // Rule ID 756 //
8132        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8133        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsune_w,
8134        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
8135        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
8136        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
8137        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
8138        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
8139        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
8140        // (intrinsic_wo_chain:{ *:[v4i32] } 5188:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FSUNE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
8141        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSUNE_W,
8142        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8143        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8144        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8145        GIR_EraseFromParent, /*InsnID*/0,
8146        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8147        // GIR_Coverage, 756,
8148        GIR_Done,
8149      // Label 590: @18316
8150      GIM_Try, /*On fail goto*//*Label 591*/ 18368, // Rule ID 757 //
8151        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8152        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsune_d,
8153        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
8154        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
8155        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
8156        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
8157        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
8158        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
8159        // (intrinsic_wo_chain:{ *:[v2i64] } 5187:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FSUNE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
8160        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSUNE_D,
8161        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8162        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8163        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8164        GIR_EraseFromParent, /*InsnID*/0,
8165        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8166        // GIR_Coverage, 757,
8167        GIR_Done,
8168      // Label 591: @18368
8169      GIM_Try, /*On fail goto*//*Label 592*/ 18420, // Rule ID 762 //
8170        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8171        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ftq_h,
8172        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
8173        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
8174        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
8175        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
8176        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
8177        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
8178        // (intrinsic_wo_chain:{ *:[v8i16] } 5193:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FTQ_H:{ *:[v8i16] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
8179        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FTQ_H,
8180        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8181        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8182        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8183        GIR_EraseFromParent, /*InsnID*/0,
8184        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8185        // GIR_Coverage, 762,
8186        GIR_Done,
8187      // Label 592: @18420
8188      GIM_Try, /*On fail goto*//*Label 593*/ 18472, // Rule ID 763 //
8189        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8190        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ftq_w,
8191        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
8192        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
8193        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
8194        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
8195        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
8196        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
8197        // (intrinsic_wo_chain:{ *:[v4i32] } 5194:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FTQ_W:{ *:[v4i32] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
8198        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FTQ_W,
8199        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8200        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8201        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8202        GIR_EraseFromParent, /*InsnID*/0,
8203        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8204        // GIR_Coverage, 763,
8205        GIR_Done,
8206      // Label 593: @18472
8207      GIM_Try, /*On fail goto*//*Label 594*/ 18524, // Rule ID 768 //
8208        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8209        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hadd_s_h,
8210        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
8211        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
8212        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
8213        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
8214        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
8215        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
8216        // (intrinsic_wo_chain:{ *:[v8i16] } 5200:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (HADD_S_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
8217        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HADD_S_H,
8218        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8219        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8220        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8221        GIR_EraseFromParent, /*InsnID*/0,
8222        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8223        // GIR_Coverage, 768,
8224        GIR_Done,
8225      // Label 594: @18524
8226      GIM_Try, /*On fail goto*//*Label 595*/ 18576, // Rule ID 769 //
8227        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8228        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hadd_s_w,
8229        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
8230        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
8231        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
8232        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
8233        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
8234        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
8235        // (intrinsic_wo_chain:{ *:[v4i32] } 5201:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (HADD_S_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
8236        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HADD_S_W,
8237        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8238        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8239        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8240        GIR_EraseFromParent, /*InsnID*/0,
8241        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8242        // GIR_Coverage, 769,
8243        GIR_Done,
8244      // Label 595: @18576
8245      GIM_Try, /*On fail goto*//*Label 596*/ 18628, // Rule ID 770 //
8246        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8247        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hadd_s_d,
8248        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
8249        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
8250        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
8251        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
8252        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
8253        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
8254        // (intrinsic_wo_chain:{ *:[v2i64] } 5199:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (HADD_S_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
8255        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HADD_S_D,
8256        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8257        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8258        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8259        GIR_EraseFromParent, /*InsnID*/0,
8260        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8261        // GIR_Coverage, 770,
8262        GIR_Done,
8263      // Label 596: @18628
8264      GIM_Try, /*On fail goto*//*Label 597*/ 18680, // Rule ID 771 //
8265        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8266        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hadd_u_h,
8267        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
8268        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
8269        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
8270        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
8271        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
8272        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
8273        // (intrinsic_wo_chain:{ *:[v8i16] } 5203:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (HADD_U_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
8274        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HADD_U_H,
8275        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8276        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8277        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8278        GIR_EraseFromParent, /*InsnID*/0,
8279        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8280        // GIR_Coverage, 771,
8281        GIR_Done,
8282      // Label 597: @18680
8283      GIM_Try, /*On fail goto*//*Label 598*/ 18732, // Rule ID 772 //
8284        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8285        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hadd_u_w,
8286        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
8287        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
8288        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
8289        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
8290        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
8291        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
8292        // (intrinsic_wo_chain:{ *:[v4i32] } 5204:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (HADD_U_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
8293        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HADD_U_W,
8294        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8295        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8296        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8297        GIR_EraseFromParent, /*InsnID*/0,
8298        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8299        // GIR_Coverage, 772,
8300        GIR_Done,
8301      // Label 598: @18732
8302      GIM_Try, /*On fail goto*//*Label 599*/ 18784, // Rule ID 773 //
8303        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8304        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hadd_u_d,
8305        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
8306        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
8307        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
8308        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
8309        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
8310        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
8311        // (intrinsic_wo_chain:{ *:[v2i64] } 5202:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (HADD_U_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
8312        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HADD_U_D,
8313        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8314        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8315        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8316        GIR_EraseFromParent, /*InsnID*/0,
8317        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8318        // GIR_Coverage, 773,
8319        GIR_Done,
8320      // Label 599: @18784
8321      GIM_Try, /*On fail goto*//*Label 600*/ 18836, // Rule ID 774 //
8322        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8323        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hsub_s_h,
8324        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
8325        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
8326        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
8327        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
8328        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
8329        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
8330        // (intrinsic_wo_chain:{ *:[v8i16] } 5206:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (HSUB_S_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
8331        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HSUB_S_H,
8332        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8333        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8334        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8335        GIR_EraseFromParent, /*InsnID*/0,
8336        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8337        // GIR_Coverage, 774,
8338        GIR_Done,
8339      // Label 600: @18836
8340      GIM_Try, /*On fail goto*//*Label 601*/ 18888, // Rule ID 775 //
8341        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8342        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hsub_s_w,
8343        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
8344        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
8345        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
8346        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
8347        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
8348        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
8349        // (intrinsic_wo_chain:{ *:[v4i32] } 5207:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (HSUB_S_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
8350        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HSUB_S_W,
8351        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8352        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8353        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8354        GIR_EraseFromParent, /*InsnID*/0,
8355        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8356        // GIR_Coverage, 775,
8357        GIR_Done,
8358      // Label 601: @18888
8359      GIM_Try, /*On fail goto*//*Label 602*/ 18940, // Rule ID 776 //
8360        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8361        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hsub_s_d,
8362        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
8363        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
8364        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
8365        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
8366        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
8367        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
8368        // (intrinsic_wo_chain:{ *:[v2i64] } 5205:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (HSUB_S_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
8369        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HSUB_S_D,
8370        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8371        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8372        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8373        GIR_EraseFromParent, /*InsnID*/0,
8374        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8375        // GIR_Coverage, 776,
8376        GIR_Done,
8377      // Label 602: @18940
8378      GIM_Try, /*On fail goto*//*Label 603*/ 18992, // Rule ID 777 //
8379        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8380        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hsub_u_h,
8381        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
8382        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
8383        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
8384        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
8385        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
8386        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
8387        // (intrinsic_wo_chain:{ *:[v8i16] } 5209:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (HSUB_U_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
8388        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HSUB_U_H,
8389        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8390        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8391        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8392        GIR_EraseFromParent, /*InsnID*/0,
8393        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8394        // GIR_Coverage, 777,
8395        GIR_Done,
8396      // Label 603: @18992
8397      GIM_Try, /*On fail goto*//*Label 604*/ 19044, // Rule ID 778 //
8398        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8399        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hsub_u_w,
8400        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
8401        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
8402        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
8403        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
8404        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
8405        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
8406        // (intrinsic_wo_chain:{ *:[v4i32] } 5210:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (HSUB_U_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
8407        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HSUB_U_W,
8408        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8409        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8410        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8411        GIR_EraseFromParent, /*InsnID*/0,
8412        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8413        // GIR_Coverage, 778,
8414        GIR_Done,
8415      // Label 604: @19044
8416      GIM_Try, /*On fail goto*//*Label 605*/ 19096, // Rule ID 779 //
8417        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8418        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hsub_u_d,
8419        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
8420        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
8421        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
8422        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
8423        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
8424        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
8425        // (intrinsic_wo_chain:{ *:[v2i64] } 5208:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (HSUB_U_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
8426        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HSUB_U_D,
8427        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8428        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8429        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8430        GIR_EraseFromParent, /*InsnID*/0,
8431        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8432        // GIR_Coverage, 779,
8433        GIR_Done,
8434      // Label 605: @19096
8435      GIM_Try, /*On fail goto*//*Label 606*/ 19148, // Rule ID 832 //
8436        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8437        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_max_a_b,
8438        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
8439        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
8440        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
8441        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
8442        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
8443        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
8444        // (intrinsic_wo_chain:{ *:[v16i8] } 5264:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (MAX_A_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
8445        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MAX_A_B,
8446        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8447        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8448        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8449        GIR_EraseFromParent, /*InsnID*/0,
8450        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8451        // GIR_Coverage, 832,
8452        GIR_Done,
8453      // Label 606: @19148
8454      GIM_Try, /*On fail goto*//*Label 607*/ 19200, // Rule ID 833 //
8455        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8456        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_max_a_h,
8457        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
8458        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
8459        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
8460        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
8461        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
8462        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
8463        // (intrinsic_wo_chain:{ *:[v8i16] } 5266:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (MAX_A_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
8464        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MAX_A_H,
8465        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8466        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8467        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8468        GIR_EraseFromParent, /*InsnID*/0,
8469        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8470        // GIR_Coverage, 833,
8471        GIR_Done,
8472      // Label 607: @19200
8473      GIM_Try, /*On fail goto*//*Label 608*/ 19252, // Rule ID 834 //
8474        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8475        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_max_a_w,
8476        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
8477        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
8478        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
8479        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
8480        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
8481        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
8482        // (intrinsic_wo_chain:{ *:[v4i32] } 5267:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (MAX_A_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
8483        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MAX_A_W,
8484        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8485        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8486        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8487        GIR_EraseFromParent, /*InsnID*/0,
8488        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8489        // GIR_Coverage, 834,
8490        GIR_Done,
8491      // Label 608: @19252
8492      GIM_Try, /*On fail goto*//*Label 609*/ 19304, // Rule ID 835 //
8493        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8494        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_max_a_d,
8495        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
8496        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
8497        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
8498        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
8499        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
8500        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
8501        // (intrinsic_wo_chain:{ *:[v2i64] } 5265:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (MAX_A_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
8502        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MAX_A_D,
8503        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8504        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8505        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8506        GIR_EraseFromParent, /*InsnID*/0,
8507        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8508        // GIR_Coverage, 835,
8509        GIR_Done,
8510      // Label 609: @19304
8511      GIM_Try, /*On fail goto*//*Label 610*/ 19356, // Rule ID 852 //
8512        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8513        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_min_a_b,
8514        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
8515        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
8516        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
8517        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
8518        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
8519        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
8520        // (intrinsic_wo_chain:{ *:[v16i8] } 5284:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (MIN_A_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
8521        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MIN_A_B,
8522        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8523        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8524        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8525        GIR_EraseFromParent, /*InsnID*/0,
8526        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8527        // GIR_Coverage, 852,
8528        GIR_Done,
8529      // Label 610: @19356
8530      GIM_Try, /*On fail goto*//*Label 611*/ 19408, // Rule ID 853 //
8531        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8532        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_min_a_h,
8533        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
8534        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
8535        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
8536        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
8537        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
8538        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
8539        // (intrinsic_wo_chain:{ *:[v8i16] } 5286:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (MIN_A_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
8540        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MIN_A_H,
8541        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8542        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8543        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8544        GIR_EraseFromParent, /*InsnID*/0,
8545        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8546        // GIR_Coverage, 853,
8547        GIR_Done,
8548      // Label 611: @19408
8549      GIM_Try, /*On fail goto*//*Label 612*/ 19460, // Rule ID 854 //
8550        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8551        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_min_a_w,
8552        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
8553        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
8554        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
8555        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
8556        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
8557        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
8558        // (intrinsic_wo_chain:{ *:[v4i32] } 5287:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (MIN_A_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
8559        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MIN_A_W,
8560        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8561        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8562        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8563        GIR_EraseFromParent, /*InsnID*/0,
8564        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8565        // GIR_Coverage, 854,
8566        GIR_Done,
8567      // Label 612: @19460
8568      GIM_Try, /*On fail goto*//*Label 613*/ 19512, // Rule ID 855 //
8569        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8570        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_min_a_d,
8571        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
8572        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
8573        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
8574        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
8575        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
8576        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
8577        // (intrinsic_wo_chain:{ *:[v2i64] } 5285:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (MIN_A_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
8578        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MIN_A_D,
8579        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8580        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8581        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8582        GIR_EraseFromParent, /*InsnID*/0,
8583        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8584        // GIR_Coverage, 855,
8585        GIR_Done,
8586      // Label 613: @19512
8587      GIM_Try, /*On fail goto*//*Label 614*/ 19564, // Rule ID 888 //
8588        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8589        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mul_q_h,
8590        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
8591        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
8592        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
8593        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
8594        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
8595        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
8596        // (intrinsic_wo_chain:{ *:[v8i16] } 5326:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (MUL_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
8597        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MUL_Q_H,
8598        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8599        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8600        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8601        GIR_EraseFromParent, /*InsnID*/0,
8602        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8603        // GIR_Coverage, 888,
8604        GIR_Done,
8605      // Label 614: @19564
8606      GIM_Try, /*On fail goto*//*Label 615*/ 19616, // Rule ID 889 //
8607        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8608        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mul_q_w,
8609        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
8610        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
8611        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
8612        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
8613        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
8614        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
8615        // (intrinsic_wo_chain:{ *:[v4i32] } 5327:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (MUL_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
8616        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MUL_Q_W,
8617        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8618        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8619        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8620        GIR_EraseFromParent, /*InsnID*/0,
8621        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8622        // GIR_Coverage, 889,
8623        GIR_Done,
8624      // Label 615: @19616
8625      GIM_Try, /*On fail goto*//*Label 616*/ 19668, // Rule ID 890 //
8626        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8627        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulr_q_h,
8628        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
8629        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
8630        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
8631        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
8632        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
8633        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
8634        // (intrinsic_wo_chain:{ *:[v8i16] } 5337:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (MULR_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
8635        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULR_Q_H,
8636        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8637        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8638        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8639        GIR_EraseFromParent, /*InsnID*/0,
8640        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8641        // GIR_Coverage, 890,
8642        GIR_Done,
8643      // Label 616: @19668
8644      GIM_Try, /*On fail goto*//*Label 617*/ 19720, // Rule ID 891 //
8645        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8646        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulr_q_w,
8647        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
8648        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
8649        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
8650        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
8651        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
8652        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
8653        // (intrinsic_wo_chain:{ *:[v4i32] } 5338:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (MULR_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
8654        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULR_Q_W,
8655        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8656        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8657        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8658        GIR_EraseFromParent, /*InsnID*/0,
8659        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8660        // GIR_Coverage, 891,
8661        GIR_Done,
8662      // Label 617: @19720
8663      GIM_Try, /*On fail goto*//*Label 618*/ 19772, // Rule ID 969 //
8664        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8665        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srar_b,
8666        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
8667        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
8668        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
8669        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
8670        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
8671        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
8672        // (intrinsic_wo_chain:{ *:[v16i8] } 5451:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (SRAR_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
8673        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRAR_B,
8674        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8675        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8676        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8677        GIR_EraseFromParent, /*InsnID*/0,
8678        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8679        // GIR_Coverage, 969,
8680        GIR_Done,
8681      // Label 618: @19772
8682      GIM_Try, /*On fail goto*//*Label 619*/ 19824, // Rule ID 970 //
8683        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8684        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srar_h,
8685        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
8686        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
8687        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
8688        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
8689        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
8690        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
8691        // (intrinsic_wo_chain:{ *:[v8i16] } 5453:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (SRAR_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
8692        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRAR_H,
8693        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8694        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8695        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8696        GIR_EraseFromParent, /*InsnID*/0,
8697        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8698        // GIR_Coverage, 970,
8699        GIR_Done,
8700      // Label 619: @19824
8701      GIM_Try, /*On fail goto*//*Label 620*/ 19876, // Rule ID 971 //
8702        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8703        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srar_w,
8704        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
8705        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
8706        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
8707        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
8708        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
8709        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
8710        // (intrinsic_wo_chain:{ *:[v4i32] } 5454:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (SRAR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
8711        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRAR_W,
8712        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8713        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8714        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8715        GIR_EraseFromParent, /*InsnID*/0,
8716        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8717        // GIR_Coverage, 971,
8718        GIR_Done,
8719      // Label 620: @19876
8720      GIM_Try, /*On fail goto*//*Label 621*/ 19928, // Rule ID 972 //
8721        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8722        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srar_d,
8723        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
8724        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
8725        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
8726        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
8727        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
8728        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
8729        // (intrinsic_wo_chain:{ *:[v2i64] } 5452:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (SRAR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
8730        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRAR_D,
8731        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8732        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8733        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8734        GIR_EraseFromParent, /*InsnID*/0,
8735        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8736        // GIR_Coverage, 972,
8737        GIR_Done,
8738      // Label 621: @19928
8739      GIM_Try, /*On fail goto*//*Label 622*/ 19980, // Rule ID 985 //
8740        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8741        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srlr_b,
8742        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
8743        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
8744        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
8745        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
8746        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
8747        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
8748        // (intrinsic_wo_chain:{ *:[v16i8] } 5467:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (SRLR_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
8749        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLR_B,
8750        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8751        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8752        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8753        GIR_EraseFromParent, /*InsnID*/0,
8754        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8755        // GIR_Coverage, 985,
8756        GIR_Done,
8757      // Label 622: @19980
8758      GIM_Try, /*On fail goto*//*Label 623*/ 20032, // Rule ID 986 //
8759        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8760        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srlr_h,
8761        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
8762        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
8763        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
8764        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
8765        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
8766        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
8767        // (intrinsic_wo_chain:{ *:[v8i16] } 5469:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (SRLR_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
8768        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLR_H,
8769        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8770        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8771        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8772        GIR_EraseFromParent, /*InsnID*/0,
8773        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8774        // GIR_Coverage, 986,
8775        GIR_Done,
8776      // Label 623: @20032
8777      GIM_Try, /*On fail goto*//*Label 624*/ 20084, // Rule ID 987 //
8778        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8779        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srlr_w,
8780        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
8781        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
8782        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
8783        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
8784        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
8785        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
8786        // (intrinsic_wo_chain:{ *:[v4i32] } 5470:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (SRLR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
8787        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLR_W,
8788        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8789        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8790        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8791        GIR_EraseFromParent, /*InsnID*/0,
8792        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8793        // GIR_Coverage, 987,
8794        GIR_Done,
8795      // Label 624: @20084
8796      GIM_Try, /*On fail goto*//*Label 625*/ 20136, // Rule ID 988 //
8797        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8798        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srlr_d,
8799        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
8800        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
8801        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
8802        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
8803        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
8804        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
8805        // (intrinsic_wo_chain:{ *:[v2i64] } 5468:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (SRLR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
8806        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLR_D,
8807        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8808        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8809        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8810        GIR_EraseFromParent, /*InsnID*/0,
8811        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8812        // GIR_Coverage, 988,
8813        GIR_Done,
8814      // Label 625: @20136
8815      GIM_Try, /*On fail goto*//*Label 626*/ 20188, // Rule ID 997 //
8816        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8817        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subs_s_b,
8818        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
8819        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
8820        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
8821        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
8822        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
8823        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
8824        // (intrinsic_wo_chain:{ *:[v16i8] } 5488:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (SUBS_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
8825        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_S_B,
8826        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8827        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8828        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8829        GIR_EraseFromParent, /*InsnID*/0,
8830        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8831        // GIR_Coverage, 997,
8832        GIR_Done,
8833      // Label 626: @20188
8834      GIM_Try, /*On fail goto*//*Label 627*/ 20240, // Rule ID 998 //
8835        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8836        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subs_s_h,
8837        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
8838        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
8839        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
8840        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
8841        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
8842        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
8843        // (intrinsic_wo_chain:{ *:[v8i16] } 5490:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (SUBS_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
8844        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_S_H,
8845        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8846        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8847        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8848        GIR_EraseFromParent, /*InsnID*/0,
8849        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8850        // GIR_Coverage, 998,
8851        GIR_Done,
8852      // Label 627: @20240
8853      GIM_Try, /*On fail goto*//*Label 628*/ 20292, // Rule ID 999 //
8854        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8855        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subs_s_w,
8856        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
8857        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
8858        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
8859        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
8860        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
8861        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
8862        // (intrinsic_wo_chain:{ *:[v4i32] } 5491:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (SUBS_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
8863        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_S_W,
8864        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8865        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8866        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8867        GIR_EraseFromParent, /*InsnID*/0,
8868        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8869        // GIR_Coverage, 999,
8870        GIR_Done,
8871      // Label 628: @20292
8872      GIM_Try, /*On fail goto*//*Label 629*/ 20344, // Rule ID 1000 //
8873        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8874        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subs_s_d,
8875        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
8876        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
8877        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
8878        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
8879        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
8880        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
8881        // (intrinsic_wo_chain:{ *:[v2i64] } 5489:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (SUBS_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
8882        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_S_D,
8883        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8884        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8885        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8886        GIR_EraseFromParent, /*InsnID*/0,
8887        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8888        // GIR_Coverage, 1000,
8889        GIR_Done,
8890      // Label 629: @20344
8891      GIM_Try, /*On fail goto*//*Label 630*/ 20396, // Rule ID 1001 //
8892        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8893        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subs_u_b,
8894        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
8895        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
8896        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
8897        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
8898        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
8899        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
8900        // (intrinsic_wo_chain:{ *:[v16i8] } 5492:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (SUBS_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
8901        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_U_B,
8902        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8903        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8904        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8905        GIR_EraseFromParent, /*InsnID*/0,
8906        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8907        // GIR_Coverage, 1001,
8908        GIR_Done,
8909      // Label 630: @20396
8910      GIM_Try, /*On fail goto*//*Label 631*/ 20448, // Rule ID 1002 //
8911        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8912        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subs_u_h,
8913        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
8914        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
8915        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
8916        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
8917        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
8918        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
8919        // (intrinsic_wo_chain:{ *:[v8i16] } 5494:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (SUBS_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
8920        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_U_H,
8921        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8922        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8923        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8924        GIR_EraseFromParent, /*InsnID*/0,
8925        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8926        // GIR_Coverage, 1002,
8927        GIR_Done,
8928      // Label 631: @20448
8929      GIM_Try, /*On fail goto*//*Label 632*/ 20500, // Rule ID 1003 //
8930        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8931        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subs_u_w,
8932        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
8933        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
8934        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
8935        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
8936        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
8937        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
8938        // (intrinsic_wo_chain:{ *:[v4i32] } 5495:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (SUBS_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
8939        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_U_W,
8940        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8941        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8942        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8943        GIR_EraseFromParent, /*InsnID*/0,
8944        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8945        // GIR_Coverage, 1003,
8946        GIR_Done,
8947      // Label 632: @20500
8948      GIM_Try, /*On fail goto*//*Label 633*/ 20552, // Rule ID 1004 //
8949        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8950        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subs_u_d,
8951        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
8952        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
8953        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
8954        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
8955        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
8956        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
8957        // (intrinsic_wo_chain:{ *:[v2i64] } 5493:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (SUBS_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
8958        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_U_D,
8959        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8960        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8961        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8962        GIR_EraseFromParent, /*InsnID*/0,
8963        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8964        // GIR_Coverage, 1004,
8965        GIR_Done,
8966      // Label 633: @20552
8967      GIM_Try, /*On fail goto*//*Label 634*/ 20604, // Rule ID 1005 //
8968        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8969        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subsus_u_b,
8970        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
8971        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
8972        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
8973        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
8974        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
8975        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
8976        // (intrinsic_wo_chain:{ *:[v16i8] } 5496:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (SUBSUS_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
8977        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUS_U_B,
8978        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8979        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8980        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8981        GIR_EraseFromParent, /*InsnID*/0,
8982        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8983        // GIR_Coverage, 1005,
8984        GIR_Done,
8985      // Label 634: @20604
8986      GIM_Try, /*On fail goto*//*Label 635*/ 20656, // Rule ID 1006 //
8987        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8988        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subsus_u_h,
8989        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
8990        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
8991        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
8992        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
8993        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
8994        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
8995        // (intrinsic_wo_chain:{ *:[v8i16] } 5498:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (SUBSUS_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
8996        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUS_U_H,
8997        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8998        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8999        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
9000        GIR_EraseFromParent, /*InsnID*/0,
9001        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9002        // GIR_Coverage, 1006,
9003        GIR_Done,
9004      // Label 635: @20656
9005      GIM_Try, /*On fail goto*//*Label 636*/ 20708, // Rule ID 1007 //
9006        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
9007        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subsus_u_w,
9008        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
9009        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
9010        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
9011        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
9012        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
9013        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
9014        // (intrinsic_wo_chain:{ *:[v4i32] } 5499:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (SUBSUS_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
9015        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUS_U_W,
9016        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
9017        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
9018        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
9019        GIR_EraseFromParent, /*InsnID*/0,
9020        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9021        // GIR_Coverage, 1007,
9022        GIR_Done,
9023      // Label 636: @20708
9024      GIM_Try, /*On fail goto*//*Label 637*/ 20760, // Rule ID 1008 //
9025        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
9026        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subsus_u_d,
9027        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
9028        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
9029        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
9030        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
9031        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
9032        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
9033        // (intrinsic_wo_chain:{ *:[v2i64] } 5497:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (SUBSUS_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
9034        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUS_U_D,
9035        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
9036        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
9037        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
9038        GIR_EraseFromParent, /*InsnID*/0,
9039        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9040        // GIR_Coverage, 1008,
9041        GIR_Done,
9042      // Label 637: @20760
9043      GIM_Try, /*On fail goto*//*Label 638*/ 20812, // Rule ID 1009 //
9044        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
9045        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subsuu_s_b,
9046        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
9047        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
9048        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
9049        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
9050        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
9051        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
9052        // (intrinsic_wo_chain:{ *:[v16i8] } 5500:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (SUBSUU_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
9053        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUU_S_B,
9054        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
9055        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
9056        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
9057        GIR_EraseFromParent, /*InsnID*/0,
9058        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9059        // GIR_Coverage, 1009,
9060        GIR_Done,
9061      // Label 638: @20812
9062      GIM_Try, /*On fail goto*//*Label 639*/ 20864, // Rule ID 1010 //
9063        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
9064        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subsuu_s_h,
9065        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
9066        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
9067        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
9068        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
9069        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
9070        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
9071        // (intrinsic_wo_chain:{ *:[v8i16] } 5502:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (SUBSUU_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
9072        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUU_S_H,
9073        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
9074        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
9075        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
9076        GIR_EraseFromParent, /*InsnID*/0,
9077        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9078        // GIR_Coverage, 1010,
9079        GIR_Done,
9080      // Label 639: @20864
9081      GIM_Try, /*On fail goto*//*Label 640*/ 20916, // Rule ID 1011 //
9082        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
9083        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subsuu_s_w,
9084        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
9085        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
9086        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
9087        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
9088        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
9089        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
9090        // (intrinsic_wo_chain:{ *:[v4i32] } 5503:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (SUBSUU_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
9091        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUU_S_W,
9092        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
9093        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
9094        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
9095        GIR_EraseFromParent, /*InsnID*/0,
9096        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9097        // GIR_Coverage, 1011,
9098        GIR_Done,
9099      // Label 640: @20916
9100      GIM_Try, /*On fail goto*//*Label 641*/ 20968, // Rule ID 1012 //
9101        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
9102        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subsuu_s_d,
9103        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
9104        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
9105        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
9106        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
9107        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
9108        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
9109        // (intrinsic_wo_chain:{ *:[v2i64] } 5501:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (SUBSUU_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
9110        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUU_S_D,
9111        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
9112        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
9113        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
9114        GIR_EraseFromParent, /*InsnID*/0,
9115        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9116        // GIR_Coverage, 1012,
9117        GIR_Done,
9118      // Label 641: @20968
9119      GIM_Try, /*On fail goto*//*Label 642*/ 21020, // Rule ID 1211 //
9120        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
9121        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addq_s_ph,
9122        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
9123        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
9124        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
9125        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9126        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
9127        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
9128        // (intrinsic_wo_chain:{ *:[v2i16] } 4862:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (ADDQ_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
9129        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQ_S_PH_MM,
9130        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9131        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
9132        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
9133        GIR_EraseFromParent, /*InsnID*/0,
9134        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9135        // GIR_Coverage, 1211,
9136        GIR_Done,
9137      // Label 642: @21020
9138      GIM_Try, /*On fail goto*//*Label 643*/ 21072, // Rule ID 1213 //
9139        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
9140        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addu_s_qb,
9141        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
9142        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
9143        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
9144        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9145        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
9146        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
9147        // (intrinsic_wo_chain:{ *:[v4i8] } 4884:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (ADDU_S_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
9148        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDU_S_QB_MM,
9149        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9150        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
9151        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
9152        GIR_EraseFromParent, /*InsnID*/0,
9153        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9154        // GIR_Coverage, 1213,
9155        GIR_Done,
9156      // Label 643: @21072
9157      GIM_Try, /*On fail goto*//*Label 644*/ 21124, // Rule ID 1234 //
9158        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
9159        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_ph,
9160        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
9161        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
9162        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
9163        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9164        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
9165        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
9166        // (intrinsic_wo_chain:{ *:[v2i16] } 5412:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)  =>  (SHRAV_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
9167        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_PH_MM,
9168        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9169        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
9170        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
9171        GIR_EraseFromParent, /*InsnID*/0,
9172        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9173        // GIR_Coverage, 1234,
9174        GIR_Done,
9175      // Label 644: @21124
9176      GIM_Try, /*On fail goto*//*Label 645*/ 21176, // Rule ID 1235 //
9177        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
9178        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_ph,
9179        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
9180        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
9181        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
9182        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9183        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
9184        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
9185        // (intrinsic_wo_chain:{ *:[v2i16] } 5414:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)  =>  (SHRAV_R_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
9186        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_R_PH_MM,
9187        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9188        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
9189        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
9190        GIR_EraseFromParent, /*InsnID*/0,
9191        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9192        // GIR_Coverage, 1235,
9193        GIR_Done,
9194      // Label 645: @21176
9195      GIM_Try, /*On fail goto*//*Label 646*/ 21228, // Rule ID 1236 //
9196        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
9197        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_w,
9198        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
9199        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
9200        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
9201        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
9202        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
9203        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
9204        // (intrinsic_wo_chain:{ *:[i32] } 5416:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)  =>  (SHRAV_R_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
9205        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_R_W_MM,
9206        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9207        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
9208        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
9209        GIR_EraseFromParent, /*InsnID*/0,
9210        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9211        // GIR_Coverage, 1236,
9212        GIR_Done,
9213      // Label 646: @21228
9214      GIM_Try, /*On fail goto*//*Label 647*/ 21280, // Rule ID 1238 //
9215        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
9216        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shrl_qb,
9217        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
9218        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
9219        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
9220        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9221        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
9222        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
9223        // (intrinsic_wo_chain:{ *:[v4i8] } 5418:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)  =>  (SHRLV_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
9224        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRLV_QB_MM,
9225        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9226        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
9227        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
9228        GIR_EraseFromParent, /*InsnID*/0,
9229        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9230        // GIR_Coverage, 1238,
9231        GIR_Done,
9232      // Label 647: @21280
9233      GIM_Try, /*On fail goto*//*Label 648*/ 21332, // Rule ID 1249 //
9234        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
9235        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subq_s_ph,
9236        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
9237        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
9238        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
9239        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9240        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
9241        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
9242        // (intrinsic_wo_chain:{ *:[v2i16] } 5482:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (SUBQ_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
9243        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQ_S_PH_MM,
9244        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9245        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
9246        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
9247        GIR_EraseFromParent, /*InsnID*/0,
9248        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9249        // GIR_Coverage, 1249,
9250        GIR_Done,
9251      // Label 648: @21332
9252      GIM_Try, /*On fail goto*//*Label 649*/ 21384, // Rule ID 1251 //
9253        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
9254        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subu_s_qb,
9255        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
9256        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
9257        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
9258        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9259        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
9260        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
9261        // (intrinsic_wo_chain:{ *:[v4i8] } 5507:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (SUBU_S_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
9262        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBU_S_QB_MM,
9263        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9264        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
9265        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
9266        GIR_EraseFromParent, /*InsnID*/0,
9267        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9268        // GIR_Coverage, 1251,
9269        GIR_Done,
9270      // Label 649: @21384
9271      GIM_Try, /*On fail goto*//*Label 650*/ 21436, // Rule ID 1261 //
9272        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
9273        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precrq_ph_w,
9274        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
9275        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
9276        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
9277        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9278        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
9279        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
9280        // (intrinsic_wo_chain:{ *:[v2i16] } 5387:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (PRECRQ_PH_W_MM:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
9281        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECRQ_PH_W_MM,
9282        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9283        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
9284        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
9285        GIR_EraseFromParent, /*InsnID*/0,
9286        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9287        // GIR_Coverage, 1261,
9288        GIR_Done,
9289      // Label 650: @21436
9290      GIM_Try, /*On fail goto*//*Label 651*/ 21488, // Rule ID 1262 //
9291        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
9292        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precrq_qb_ph,
9293        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
9294        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
9295        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
9296        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9297        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
9298        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
9299        // (intrinsic_wo_chain:{ *:[v4i8] } 5388:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (PRECRQ_QB_PH_MM:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
9300        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECRQ_QB_PH_MM,
9301        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9302        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
9303        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
9304        GIR_EraseFromParent, /*InsnID*/0,
9305        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9306        // GIR_Coverage, 1262,
9307        GIR_Done,
9308      // Label 651: @21488
9309      GIM_Try, /*On fail goto*//*Label 652*/ 21540, // Rule ID 1281 //
9310        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
9311        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_packrl_ph,
9312        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
9313        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
9314        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
9315        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9316        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
9317        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
9318        // (intrinsic_wo_chain:{ *:[v2i16] } 5359:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (PACKRL_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
9319        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PACKRL_PH_MM,
9320        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9321        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
9322        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
9323        GIR_EraseFromParent, /*InsnID*/0,
9324        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9325        // GIR_Coverage, 1281,
9326        GIR_Done,
9327      // Label 652: @21540
9328      GIM_Try, /*On fail goto*//*Label 653*/ 21592, // Rule ID 1287 //
9329        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
9330        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_modsub,
9331        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
9332        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
9333        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
9334        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
9335        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
9336        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
9337        // (intrinsic_wo_chain:{ *:[i32] } 5312:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MODSUB_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
9338        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MODSUB_MM,
9339        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9340        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
9341        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
9342        GIR_EraseFromParent, /*InsnID*/0,
9343        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9344        // GIR_Coverage, 1287,
9345        GIR_Done,
9346      // Label 653: @21592
9347      GIM_Try, /*On fail goto*//*Label 654*/ 21644, // Rule ID 1300 //
9348        GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
9349        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addqh_ph,
9350        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
9351        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
9352        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
9353        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9354        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
9355        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
9356        // (intrinsic_wo_chain:{ *:[v2i16] } 4864:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (ADDQH_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
9357        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_PH_MMR2,
9358        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9359        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
9360        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
9361        GIR_EraseFromParent, /*InsnID*/0,
9362        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9363        // GIR_Coverage, 1300,
9364        GIR_Done,
9365      // Label 654: @21644
9366      GIM_Try, /*On fail goto*//*Label 655*/ 21696, // Rule ID 1301 //
9367        GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
9368        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addqh_r_ph,
9369        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
9370        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
9371        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
9372        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9373        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
9374        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
9375        // (intrinsic_wo_chain:{ *:[v2i16] } 4865:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (ADDQH_R_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
9376        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_R_PH_MMR2,
9377        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9378        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
9379        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
9380        GIR_EraseFromParent, /*InsnID*/0,
9381        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9382        // GIR_Coverage, 1301,
9383        GIR_Done,
9384      // Label 655: @21696
9385      GIM_Try, /*On fail goto*//*Label 656*/ 21748, // Rule ID 1302 //
9386        GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
9387        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addqh_w,
9388        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
9389        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
9390        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
9391        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
9392        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
9393        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
9394        // (intrinsic_wo_chain:{ *:[i32] } 4867:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (ADDQH_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
9395        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_W_MMR2,
9396        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9397        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
9398        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
9399        GIR_EraseFromParent, /*InsnID*/0,
9400        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9401        // GIR_Coverage, 1302,
9402        GIR_Done,
9403      // Label 656: @21748
9404      GIM_Try, /*On fail goto*//*Label 657*/ 21800, // Rule ID 1303 //
9405        GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
9406        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addqh_r_w,
9407        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
9408        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
9409        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
9410        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
9411        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
9412        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
9413        // (intrinsic_wo_chain:{ *:[i32] } 4866:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (ADDQH_R_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
9414        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_R_W_MMR2,
9415        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9416        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
9417        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
9418        GIR_EraseFromParent, /*InsnID*/0,
9419        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9420        // GIR_Coverage, 1303,
9421        GIR_Done,
9422      // Label 657: @21800
9423      GIM_Try, /*On fail goto*//*Label 658*/ 21852, // Rule ID 1306 //
9424        GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
9425        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adduh_qb,
9426        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
9427        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
9428        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
9429        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9430        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
9431        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
9432        // (intrinsic_wo_chain:{ *:[v4i8] } 4885:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (ADDUH_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
9433        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDUH_QB_MMR2,
9434        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9435        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
9436        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
9437        GIR_EraseFromParent, /*InsnID*/0,
9438        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9439        // GIR_Coverage, 1306,
9440        GIR_Done,
9441      // Label 658: @21852
9442      GIM_Try, /*On fail goto*//*Label 659*/ 21904, // Rule ID 1307 //
9443        GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
9444        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adduh_r_qb,
9445        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
9446        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
9447        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
9448        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9449        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
9450        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
9451        // (intrinsic_wo_chain:{ *:[v4i8] } 4886:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (ADDUH_R_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
9452        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDUH_R_QB_MMR2,
9453        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9454        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
9455        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
9456        GIR_EraseFromParent, /*InsnID*/0,
9457        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9458        // GIR_Coverage, 1307,
9459        GIR_Done,
9460      // Label 659: @21904
9461      GIM_Try, /*On fail goto*//*Label 660*/ 21956, // Rule ID 1313 //
9462        GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
9463        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_qb,
9464        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
9465        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
9466        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
9467        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9468        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
9469        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
9470        // (intrinsic_wo_chain:{ *:[v4i8] } 5413:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)  =>  (SHRAV_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
9471        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_QB_MMR2,
9472        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9473        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
9474        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
9475        GIR_EraseFromParent, /*InsnID*/0,
9476        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9477        // GIR_Coverage, 1313,
9478        GIR_Done,
9479      // Label 660: @21956
9480      GIM_Try, /*On fail goto*//*Label 661*/ 22008, // Rule ID 1314 //
9481        GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
9482        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_qb,
9483        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
9484        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
9485        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
9486        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9487        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
9488        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
9489        // (intrinsic_wo_chain:{ *:[v4i8] } 5415:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)  =>  (SHRAV_R_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
9490        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_R_QB_MMR2,
9491        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9492        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
9493        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
9494        GIR_EraseFromParent, /*InsnID*/0,
9495        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9496        // GIR_Coverage, 1314,
9497        GIR_Done,
9498      // Label 661: @22008
9499      GIM_Try, /*On fail goto*//*Label 662*/ 22060, // Rule ID 1319 //
9500        GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
9501        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shrl_ph,
9502        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
9503        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
9504        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
9505        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9506        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
9507        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
9508        // (intrinsic_wo_chain:{ *:[v2i16] } 5417:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)  =>  (SHRLV_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
9509        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRLV_PH_MMR2,
9510        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9511        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
9512        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
9513        GIR_EraseFromParent, /*InsnID*/0,
9514        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9515        // GIR_Coverage, 1319,
9516        GIR_Done,
9517      // Label 662: @22060
9518      GIM_Try, /*On fail goto*//*Label 663*/ 22112, // Rule ID 1320 //
9519        GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
9520        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subqh_ph,
9521        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
9522        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
9523        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
9524        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9525        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
9526        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
9527        // (intrinsic_wo_chain:{ *:[v2i16] } 5484:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (SUBQH_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
9528        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQH_PH_MMR2,
9529        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9530        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
9531        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
9532        GIR_EraseFromParent, /*InsnID*/0,
9533        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9534        // GIR_Coverage, 1320,
9535        GIR_Done,
9536      // Label 663: @22112
9537      GIM_Try, /*On fail goto*//*Label 664*/ 22164, // Rule ID 1321 //
9538        GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
9539        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subqh_r_ph,
9540        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
9541        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
9542        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
9543        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9544        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
9545        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
9546        // (intrinsic_wo_chain:{ *:[v2i16] } 5485:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (SUBQH_R_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
9547        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQH_R_PH_MMR2,
9548        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9549        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
9550        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
9551        GIR_EraseFromParent, /*InsnID*/0,
9552        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9553        // GIR_Coverage, 1321,
9554        GIR_Done,
9555      // Label 664: @22164
9556      GIM_Try, /*On fail goto*//*Label 665*/ 22216, // Rule ID 1322 //
9557        GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
9558        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subqh_w,
9559        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
9560        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
9561        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
9562        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
9563        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
9564        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
9565        // (intrinsic_wo_chain:{ *:[i32] } 5487:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (SUBQH_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
9566        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQH_W_MMR2,
9567        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9568        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
9569        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
9570        GIR_EraseFromParent, /*InsnID*/0,
9571        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9572        // GIR_Coverage, 1322,
9573        GIR_Done,
9574      // Label 665: @22216
9575      GIM_Try, /*On fail goto*//*Label 666*/ 22268, // Rule ID 1323 //
9576        GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
9577        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subqh_r_w,
9578        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
9579        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
9580        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
9581        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
9582        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
9583        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
9584        // (intrinsic_wo_chain:{ *:[i32] } 5486:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (SUBQH_R_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
9585        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQH_R_W_MMR2,
9586        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9587        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
9588        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
9589        GIR_EraseFromParent, /*InsnID*/0,
9590        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9591        // GIR_Coverage, 1323,
9592        GIR_Done,
9593      // Label 666: @22268
9594      GIM_Try, /*On fail goto*//*Label 667*/ 22320, // Rule ID 1326 //
9595        GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
9596        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subuh_qb,
9597        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
9598        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
9599        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
9600        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9601        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
9602        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
9603        // (intrinsic_wo_chain:{ *:[v4i8] } 5508:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (SUBUH_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
9604        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBUH_QB_MMR2,
9605        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9606        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
9607        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
9608        GIR_EraseFromParent, /*InsnID*/0,
9609        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9610        // GIR_Coverage, 1326,
9611        GIR_Done,
9612      // Label 667: @22320
9613      GIM_Try, /*On fail goto*//*Label 668*/ 22372, // Rule ID 1327 //
9614        GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
9615        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subuh_r_qb,
9616        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
9617        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
9618        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
9619        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9620        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
9621        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
9622        // (intrinsic_wo_chain:{ *:[v4i8] } 5509:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (SUBUH_R_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
9623        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBUH_R_QB_MMR2,
9624        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9625        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
9626        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
9627        GIR_EraseFromParent, /*InsnID*/0,
9628        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9629        // GIR_Coverage, 1327,
9630        GIR_Done,
9631      // Label 668: @22372
9632      GIM_Try, /*On fail goto*//*Label 669*/ 22416, // Rule ID 1881 //
9633        GIM_CheckFeatures, GIFBS_HasDSP,
9634        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addq_ph,
9635        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
9636        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
9637        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
9638        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9639        // (intrinsic_wo_chain:{ *:[v2i16] } 4861:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)  =>  (ADDQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
9640        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQ_PH,
9641        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9642        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
9643        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
9644        GIR_EraseFromParent, /*InsnID*/0,
9645        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9646        // GIR_Coverage, 1881,
9647        GIR_Done,
9648      // Label 669: @22416
9649      GIM_Try, /*On fail goto*//*Label 670*/ 22460, // Rule ID 1883 //
9650        GIM_CheckFeatures, GIFBS_HasDSP,
9651        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subq_ph,
9652        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
9653        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
9654        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
9655        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9656        // (intrinsic_wo_chain:{ *:[v2i16] } 5481:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)  =>  (SUBQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
9657        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQ_PH,
9658        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9659        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
9660        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
9661        GIR_EraseFromParent, /*InsnID*/0,
9662        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9663        // GIR_Coverage, 1883,
9664        GIR_Done,
9665      // Label 670: @22460
9666      GIM_Try, /*On fail goto*//*Label 671*/ 22504, // Rule ID 1887 //
9667        GIM_CheckFeatures, GIFBS_HasDSP,
9668        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addu_qb,
9669        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
9670        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
9671        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
9672        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9673        // (intrinsic_wo_chain:{ *:[v4i8] } 4882:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)  =>  (ADDU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)
9674        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDU_QB,
9675        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9676        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
9677        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
9678        GIR_EraseFromParent, /*InsnID*/0,
9679        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9680        // GIR_Coverage, 1887,
9681        GIR_Done,
9682      // Label 671: @22504
9683      GIM_Try, /*On fail goto*//*Label 672*/ 22548, // Rule ID 1889 //
9684        GIM_CheckFeatures, GIFBS_HasDSP,
9685        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subu_qb,
9686        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
9687        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
9688        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
9689        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9690        // (intrinsic_wo_chain:{ *:[v4i8] } 5505:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)  =>  (SUBU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)
9691        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBU_QB,
9692        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9693        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
9694        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
9695        GIR_EraseFromParent, /*InsnID*/0,
9696        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9697        // GIR_Coverage, 1889,
9698        GIR_Done,
9699      // Label 672: @22548
9700      GIM_Reject,
9701    // Label 458: @22549
9702    GIM_Try, /*On fail goto*//*Label 673*/ 25489,
9703      GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
9704      GIM_Try, /*On fail goto*//*Label 674*/ 22617, // Rule ID 465 //
9705        GIM_CheckFeatures, GIFBS_HasDSPR2,
9706        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precr_sra_ph_w,
9707        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
9708        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
9709        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
9710        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9711        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
9712        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
9713        // MIs[0] sa
9714        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
9715        GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIPFP_I64_Predicate_timmZExt5,
9716        // (intrinsic_wo_chain:{ *:[v2i16] } 5385:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa)  =>  (PRECR_SRA_PH_W:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
9717        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECR_SRA_PH_W,
9718        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
9719        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
9720        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // sa
9721        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
9722        GIR_EraseFromParent, /*InsnID*/0,
9723        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9724        // GIR_Coverage, 465,
9725        GIR_Done,
9726      // Label 674: @22617
9727      GIM_Try, /*On fail goto*//*Label 675*/ 22680, // Rule ID 466 //
9728        GIM_CheckFeatures, GIFBS_HasDSPR2,
9729        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precr_sra_r_ph_w,
9730        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
9731        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
9732        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
9733        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9734        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
9735        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
9736        // MIs[0] sa
9737        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
9738        GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIPFP_I64_Predicate_timmZExt5,
9739        // (intrinsic_wo_chain:{ *:[v2i16] } 5386:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa)  =>  (PRECR_SRA_R_PH_W:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
9740        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECR_SRA_R_PH_W,
9741        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
9742        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
9743        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // sa
9744        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
9745        GIR_EraseFromParent, /*InsnID*/0,
9746        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9747        // GIR_Coverage, 466,
9748        GIR_Done,
9749      // Label 675: @22680
9750      GIM_Try, /*On fail goto*//*Label 676*/ 22743, // Rule ID 471 //
9751        GIM_CheckFeatures, GIFBS_HasDSPR2,
9752        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_append,
9753        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
9754        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
9755        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
9756        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
9757        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
9758        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
9759        // MIs[0] sa
9760        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
9761        GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIPFP_I64_Predicate_timmZExt5,
9762        // (intrinsic_wo_chain:{ *:[i32] } 4898:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa)  =>  (APPEND:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
9763        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::APPEND,
9764        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
9765        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
9766        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // sa
9767        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
9768        GIR_EraseFromParent, /*InsnID*/0,
9769        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9770        // GIR_Coverage, 471,
9771        GIR_Done,
9772      // Label 676: @22743
9773      GIM_Try, /*On fail goto*//*Label 677*/ 22806, // Rule ID 472 //
9774        GIM_CheckFeatures, GIFBS_HasDSPR2,
9775        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_balign,
9776        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
9777        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
9778        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
9779        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
9780        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
9781        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
9782        // MIs[0] sa
9783        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
9784        GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIPFP_I64_Predicate_timmZExt2,
9785        // (intrinsic_wo_chain:{ *:[i32] } 4923:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt2>>:$sa)  =>  (BALIGN:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
9786        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BALIGN,
9787        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
9788        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
9789        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // sa
9790        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
9791        GIR_EraseFromParent, /*InsnID*/0,
9792        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9793        // GIR_Coverage, 472,
9794        GIR_Done,
9795      // Label 677: @22806
9796      GIM_Try, /*On fail goto*//*Label 678*/ 22869, // Rule ID 473 //
9797        GIM_CheckFeatures, GIFBS_HasDSPR2,
9798        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_prepend,
9799        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
9800        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
9801        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
9802        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
9803        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
9804        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
9805        // MIs[0] sa
9806        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
9807        GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIPFP_I64_Predicate_timmZExt5,
9808        // (intrinsic_wo_chain:{ *:[i32] } 5391:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa)  =>  (PREPEND:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
9809        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PREPEND,
9810        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
9811        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
9812        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // sa
9813        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
9814        GIR_EraseFromParent, /*InsnID*/0,
9815        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9816        // GIR_Coverage, 473,
9817        GIR_Done,
9818      // Label 678: @22869
9819      GIM_Try, /*On fail goto*//*Label 679*/ 22932, // Rule ID 941 //
9820        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
9821        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sldi_b,
9822        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
9823        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
9824        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
9825        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
9826        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
9827        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
9828        // MIs[0] n
9829        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
9830        GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIPFP_I64_Predicate_timmZExt4,
9831        // (intrinsic_wo_chain:{ *:[v16i8] } 5423:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt4>>:$n)  =>  (SLDI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] }):$n)
9832        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLDI_B,
9833        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
9834        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
9835        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
9836        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // n
9837        GIR_EraseFromParent, /*InsnID*/0,
9838        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9839        // GIR_Coverage, 941,
9840        GIR_Done,
9841      // Label 679: @22932
9842      GIM_Try, /*On fail goto*//*Label 680*/ 22995, // Rule ID 942 //
9843        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
9844        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sldi_h,
9845        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
9846        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
9847        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
9848        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
9849        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
9850        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
9851        // MIs[0] n
9852        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
9853        GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIPFP_I64_Predicate_timmZExt3,
9854        // (intrinsic_wo_chain:{ *:[v8i16] } 5425:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt3>>:$n)  =>  (SLDI_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] }):$n)
9855        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLDI_H,
9856        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
9857        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
9858        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
9859        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // n
9860        GIR_EraseFromParent, /*InsnID*/0,
9861        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9862        // GIR_Coverage, 942,
9863        GIR_Done,
9864      // Label 680: @22995
9865      GIM_Try, /*On fail goto*//*Label 681*/ 23058, // Rule ID 943 //
9866        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
9867        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sldi_w,
9868        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
9869        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
9870        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
9871        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
9872        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
9873        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
9874        // MIs[0] n
9875        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
9876        GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIPFP_I64_Predicate_timmZExt2,
9877        // (intrinsic_wo_chain:{ *:[v4i32] } 5426:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt2>>:$n)  =>  (SLDI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] }):$n)
9878        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLDI_W,
9879        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
9880        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
9881        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
9882        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // n
9883        GIR_EraseFromParent, /*InsnID*/0,
9884        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9885        // GIR_Coverage, 943,
9886        GIR_Done,
9887      // Label 681: @23058
9888      GIM_Try, /*On fail goto*//*Label 682*/ 23121, // Rule ID 944 //
9889        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
9890        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sldi_d,
9891        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
9892        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
9893        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
9894        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
9895        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
9896        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
9897        // MIs[0] n
9898        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
9899        GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIPFP_I64_Predicate_timmZExt1,
9900        // (intrinsic_wo_chain:{ *:[v2i64] } 5424:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt1>>:$n)  =>  (SLDI_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] }):$n)
9901        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLDI_D,
9902        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
9903        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
9904        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
9905        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // n
9906        GIR_EraseFromParent, /*InsnID*/0,
9907        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9908        // GIR_Coverage, 944,
9909        GIR_Done,
9910      // Label 682: @23121
9911      GIM_Try, /*On fail goto*//*Label 683*/ 23184, // Rule ID 1337 //
9912        GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
9913        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precr_sra_ph_w,
9914        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
9915        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
9916        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
9917        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9918        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
9919        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
9920        // MIs[0] sa
9921        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
9922        GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIPFP_I64_Predicate_timmZExt5,
9923        // (intrinsic_wo_chain:{ *:[v2i16] } 5385:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa)  =>  (PRECR_SRA_PH_W_MMR2:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
9924        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECR_SRA_PH_W_MMR2,
9925        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
9926        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
9927        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // sa
9928        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
9929        GIR_EraseFromParent, /*InsnID*/0,
9930        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9931        // GIR_Coverage, 1337,
9932        GIR_Done,
9933      // Label 683: @23184
9934      GIM_Try, /*On fail goto*//*Label 684*/ 23247, // Rule ID 1338 //
9935        GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
9936        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precr_sra_r_ph_w,
9937        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
9938        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
9939        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
9940        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9941        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
9942        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
9943        // MIs[0] sa
9944        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
9945        GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIPFP_I64_Predicate_timmZExt5,
9946        // (intrinsic_wo_chain:{ *:[v2i16] } 5386:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa)  =>  (PRECR_SRA_R_PH_W_MMR2:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
9947        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECR_SRA_R_PH_W_MMR2,
9948        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
9949        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
9950        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // sa
9951        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
9952        GIR_EraseFromParent, /*InsnID*/0,
9953        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9954        // GIR_Coverage, 1338,
9955        GIR_Done,
9956      // Label 684: @23247
9957      GIM_Try, /*On fail goto*//*Label 685*/ 23310, // Rule ID 1339 //
9958        GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
9959        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_prepend,
9960        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
9961        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
9962        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
9963        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
9964        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
9965        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
9966        // MIs[0] sa
9967        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
9968        GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIPFP_I64_Predicate_timmZExt5,
9969        // (intrinsic_wo_chain:{ *:[i32] } 5391:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa)  =>  (PREPEND_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
9970        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PREPEND_MMR2,
9971        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
9972        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
9973        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // sa
9974        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
9975        GIR_EraseFromParent, /*InsnID*/0,
9976        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9977        // GIR_Coverage, 1339,
9978        GIR_Done,
9979      // Label 685: @23310
9980      GIM_Try, /*On fail goto*//*Label 686*/ 23373, // Rule ID 1340 //
9981        GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
9982        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_append,
9983        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
9984        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
9985        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
9986        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
9987        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
9988        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
9989        // MIs[0] sa
9990        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
9991        GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIPFP_I64_Predicate_timmZExt5,
9992        // (intrinsic_wo_chain:{ *:[i32] } 4898:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa)  =>  (APPEND_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
9993        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::APPEND_MMR2,
9994        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
9995        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
9996        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // sa
9997        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
9998        GIR_EraseFromParent, /*InsnID*/0,
9999        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10000        // GIR_Coverage, 1340,
10001        GIR_Done,
10002      // Label 686: @23373
10003      GIM_Try, /*On fail goto*//*Label 687*/ 23440, // Rule ID 1315 //
10004        GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
10005        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_balign,
10006        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
10007        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
10008        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
10009        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
10010        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
10011        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
10012        // MIs[0] bp
10013        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
10014        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
10015        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt2,
10016        // MIs[1] Operand 1
10017        // No operand predicates
10018        GIM_CheckIsSafeToFold, /*InsnID*/1,
10019        // (intrinsic_wo_chain:{ *:[i32] } 4923:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2>>:$bp)  =>  (BALIGN_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$bp, GPR32Opnd:{ *:[i32] }:$src)
10020        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BALIGN_MMR2,
10021        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
10022        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
10023        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // bp
10024        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
10025        GIR_EraseFromParent, /*InsnID*/0,
10026        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10027        // GIR_Coverage, 1315,
10028        GIR_Done,
10029      // Label 687: @23440
10030      GIM_Try, /*On fail goto*//*Label 688*/ 23504, // Rule ID 540 //
10031        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10032        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_binsl_b,
10033        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
10034        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
10035        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
10036        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
10037        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
10038        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
10039        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
10040        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128BRegClassID,
10041        // (intrinsic_wo_chain:{ *:[v16i8] } 4932:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (BINSL_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
10042        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BINSL_B,
10043        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10044        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10045        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10046        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10047        GIR_EraseFromParent, /*InsnID*/0,
10048        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10049        // GIR_Coverage, 540,
10050        GIR_Done,
10051      // Label 688: @23504
10052      GIM_Try, /*On fail goto*//*Label 689*/ 23568, // Rule ID 541 //
10053        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10054        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_binsl_h,
10055        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
10056        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
10057        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
10058        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
10059        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
10060        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
10061        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
10062        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID,
10063        // (intrinsic_wo_chain:{ *:[v8i16] } 4934:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (BINSL_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10064        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BINSL_H,
10065        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10066        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10067        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10068        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10069        GIR_EraseFromParent, /*InsnID*/0,
10070        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10071        // GIR_Coverage, 541,
10072        GIR_Done,
10073      // Label 689: @23568
10074      GIM_Try, /*On fail goto*//*Label 690*/ 23632, // Rule ID 542 //
10075        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10076        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_binsl_w,
10077        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
10078        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
10079        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
10080        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
10081        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
10082        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
10083        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
10084        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID,
10085        // (intrinsic_wo_chain:{ *:[v4i32] } 4935:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (BINSL_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10086        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BINSL_W,
10087        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10088        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10089        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10090        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10091        GIR_EraseFromParent, /*InsnID*/0,
10092        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10093        // GIR_Coverage, 542,
10094        GIR_Done,
10095      // Label 690: @23632
10096      GIM_Try, /*On fail goto*//*Label 691*/ 23696, // Rule ID 543 //
10097        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10098        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_binsl_d,
10099        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
10100        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
10101        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
10102        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s64,
10103        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
10104        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
10105        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
10106        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128DRegClassID,
10107        // (intrinsic_wo_chain:{ *:[v2i64] } 4933:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (BINSL_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
10108        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BINSL_D,
10109        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10110        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10111        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10112        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10113        GIR_EraseFromParent, /*InsnID*/0,
10114        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10115        // GIR_Coverage, 543,
10116        GIR_Done,
10117      // Label 691: @23696
10118      GIM_Try, /*On fail goto*//*Label 692*/ 23760, // Rule ID 548 //
10119        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10120        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_binsr_b,
10121        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
10122        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
10123        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
10124        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
10125        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
10126        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
10127        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
10128        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128BRegClassID,
10129        // (intrinsic_wo_chain:{ *:[v16i8] } 4940:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (BINSR_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
10130        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BINSR_B,
10131        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10132        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10133        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10134        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10135        GIR_EraseFromParent, /*InsnID*/0,
10136        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10137        // GIR_Coverage, 548,
10138        GIR_Done,
10139      // Label 692: @23760
10140      GIM_Try, /*On fail goto*//*Label 693*/ 23824, // Rule ID 549 //
10141        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10142        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_binsr_h,
10143        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
10144        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
10145        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
10146        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
10147        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
10148        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
10149        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
10150        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID,
10151        // (intrinsic_wo_chain:{ *:[v8i16] } 4942:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (BINSR_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10152        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BINSR_H,
10153        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10154        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10155        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10156        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10157        GIR_EraseFromParent, /*InsnID*/0,
10158        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10159        // GIR_Coverage, 549,
10160        GIR_Done,
10161      // Label 693: @23824
10162      GIM_Try, /*On fail goto*//*Label 694*/ 23888, // Rule ID 550 //
10163        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10164        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_binsr_w,
10165        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
10166        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
10167        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
10168        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
10169        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
10170        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
10171        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
10172        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID,
10173        // (intrinsic_wo_chain:{ *:[v4i32] } 4943:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (BINSR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10174        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BINSR_W,
10175        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10176        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10177        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10178        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10179        GIR_EraseFromParent, /*InsnID*/0,
10180        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10181        // GIR_Coverage, 550,
10182        GIR_Done,
10183      // Label 694: @23888
10184      GIM_Try, /*On fail goto*//*Label 695*/ 23952, // Rule ID 551 //
10185        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10186        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_binsr_d,
10187        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
10188        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
10189        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
10190        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s64,
10191        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
10192        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
10193        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
10194        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128DRegClassID,
10195        // (intrinsic_wo_chain:{ *:[v2i64] } 4941:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (BINSR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
10196        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BINSR_D,
10197        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10198        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10199        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10200        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10201        GIR_EraseFromParent, /*InsnID*/0,
10202        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10203        // GIR_Coverage, 551,
10204        GIR_Done,
10205      // Label 695: @23952
10206      GIM_Try, /*On fail goto*//*Label 696*/ 24016, // Rule ID 646 //
10207        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10208        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpadd_s_h,
10209        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
10210        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
10211        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
10212        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
10213        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
10214        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
10215        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
10216        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128BRegClassID,
10217        // (intrinsic_wo_chain:{ *:[v8i16] } 5061:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (DPADD_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
10218        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPADD_S_H,
10219        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10220        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10221        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10222        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10223        GIR_EraseFromParent, /*InsnID*/0,
10224        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10225        // GIR_Coverage, 646,
10226        GIR_Done,
10227      // Label 696: @24016
10228      GIM_Try, /*On fail goto*//*Label 697*/ 24080, // Rule ID 647 //
10229        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10230        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpadd_s_w,
10231        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
10232        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
10233        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
10234        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
10235        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
10236        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
10237        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
10238        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID,
10239        // (intrinsic_wo_chain:{ *:[v4i32] } 5062:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (DPADD_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10240        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPADD_S_W,
10241        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10242        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10243        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10244        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10245        GIR_EraseFromParent, /*InsnID*/0,
10246        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10247        // GIR_Coverage, 647,
10248        GIR_Done,
10249      // Label 697: @24080
10250      GIM_Try, /*On fail goto*//*Label 698*/ 24144, // Rule ID 648 //
10251        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10252        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpadd_s_d,
10253        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
10254        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
10255        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
10256        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
10257        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
10258        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
10259        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
10260        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID,
10261        // (intrinsic_wo_chain:{ *:[v2i64] } 5060:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (DPADD_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10262        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPADD_S_D,
10263        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10264        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10265        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10266        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10267        GIR_EraseFromParent, /*InsnID*/0,
10268        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10269        // GIR_Coverage, 648,
10270        GIR_Done,
10271      // Label 698: @24144
10272      GIM_Try, /*On fail goto*//*Label 699*/ 24208, // Rule ID 649 //
10273        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10274        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpadd_u_h,
10275        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
10276        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
10277        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
10278        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
10279        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
10280        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
10281        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
10282        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128BRegClassID,
10283        // (intrinsic_wo_chain:{ *:[v8i16] } 5064:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (DPADD_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
10284        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPADD_U_H,
10285        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10286        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10287        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10288        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10289        GIR_EraseFromParent, /*InsnID*/0,
10290        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10291        // GIR_Coverage, 649,
10292        GIR_Done,
10293      // Label 699: @24208
10294      GIM_Try, /*On fail goto*//*Label 700*/ 24272, // Rule ID 650 //
10295        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10296        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpadd_u_w,
10297        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
10298        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
10299        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
10300        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
10301        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
10302        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
10303        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
10304        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID,
10305        // (intrinsic_wo_chain:{ *:[v4i32] } 5065:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (DPADD_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10306        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPADD_U_W,
10307        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10308        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10309        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10310        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10311        GIR_EraseFromParent, /*InsnID*/0,
10312        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10313        // GIR_Coverage, 650,
10314        GIR_Done,
10315      // Label 700: @24272
10316      GIM_Try, /*On fail goto*//*Label 701*/ 24336, // Rule ID 651 //
10317        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10318        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpadd_u_d,
10319        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
10320        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
10321        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
10322        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
10323        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
10324        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
10325        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
10326        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID,
10327        // (intrinsic_wo_chain:{ *:[v2i64] } 5063:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (DPADD_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10328        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPADD_U_D,
10329        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10330        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10331        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10332        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10333        GIR_EraseFromParent, /*InsnID*/0,
10334        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10335        // GIR_Coverage, 651,
10336        GIR_Done,
10337      // Label 701: @24336
10338      GIM_Try, /*On fail goto*//*Label 702*/ 24400, // Rule ID 652 //
10339        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10340        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpsub_s_h,
10341        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
10342        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
10343        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
10344        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
10345        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
10346        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
10347        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
10348        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128BRegClassID,
10349        // (intrinsic_wo_chain:{ *:[v8i16] } 5081:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (DPSUB_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
10350        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPSUB_S_H,
10351        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10352        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10353        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10354        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10355        GIR_EraseFromParent, /*InsnID*/0,
10356        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10357        // GIR_Coverage, 652,
10358        GIR_Done,
10359      // Label 702: @24400
10360      GIM_Try, /*On fail goto*//*Label 703*/ 24464, // Rule ID 653 //
10361        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10362        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpsub_s_w,
10363        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
10364        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
10365        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
10366        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
10367        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
10368        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
10369        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
10370        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID,
10371        // (intrinsic_wo_chain:{ *:[v4i32] } 5082:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (DPSUB_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10372        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPSUB_S_W,
10373        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10374        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10375        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10376        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10377        GIR_EraseFromParent, /*InsnID*/0,
10378        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10379        // GIR_Coverage, 653,
10380        GIR_Done,
10381      // Label 703: @24464
10382      GIM_Try, /*On fail goto*//*Label 704*/ 24528, // Rule ID 654 //
10383        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10384        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpsub_s_d,
10385        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
10386        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
10387        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
10388        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
10389        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
10390        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
10391        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
10392        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID,
10393        // (intrinsic_wo_chain:{ *:[v2i64] } 5080:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (DPSUB_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10394        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPSUB_S_D,
10395        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10396        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10397        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10398        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10399        GIR_EraseFromParent, /*InsnID*/0,
10400        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10401        // GIR_Coverage, 654,
10402        GIR_Done,
10403      // Label 704: @24528
10404      GIM_Try, /*On fail goto*//*Label 705*/ 24592, // Rule ID 655 //
10405        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10406        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpsub_u_h,
10407        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
10408        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
10409        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
10410        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
10411        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
10412        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
10413        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
10414        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128BRegClassID,
10415        // (intrinsic_wo_chain:{ *:[v8i16] } 5084:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (DPSUB_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
10416        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPSUB_U_H,
10417        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10418        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10419        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10420        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10421        GIR_EraseFromParent, /*InsnID*/0,
10422        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10423        // GIR_Coverage, 655,
10424        GIR_Done,
10425      // Label 705: @24592
10426      GIM_Try, /*On fail goto*//*Label 706*/ 24656, // Rule ID 656 //
10427        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10428        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpsub_u_w,
10429        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
10430        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
10431        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
10432        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
10433        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
10434        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
10435        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
10436        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID,
10437        // (intrinsic_wo_chain:{ *:[v4i32] } 5085:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (DPSUB_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10438        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPSUB_U_W,
10439        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10440        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10441        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10442        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10443        GIR_EraseFromParent, /*InsnID*/0,
10444        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10445        // GIR_Coverage, 656,
10446        GIR_Done,
10447      // Label 706: @24656
10448      GIM_Try, /*On fail goto*//*Label 707*/ 24720, // Rule ID 657 //
10449        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10450        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpsub_u_d,
10451        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
10452        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
10453        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
10454        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
10455        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
10456        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
10457        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
10458        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID,
10459        // (intrinsic_wo_chain:{ *:[v2i64] } 5083:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (DPSUB_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10460        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPSUB_U_D,
10461        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10462        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10463        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10464        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10465        GIR_EraseFromParent, /*InsnID*/0,
10466        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10467        // GIR_Coverage, 657,
10468        GIR_Done,
10469      // Label 707: @24720
10470      GIM_Try, /*On fail goto*//*Label 708*/ 24784, // Rule ID 824 //
10471        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10472        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_madd_q_h,
10473        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
10474        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
10475        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
10476        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
10477        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
10478        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
10479        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
10480        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID,
10481        // (intrinsic_wo_chain:{ *:[v8i16] } 5251:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (MADD_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10482        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADD_Q_H,
10483        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10484        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10485        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10486        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10487        GIR_EraseFromParent, /*InsnID*/0,
10488        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10489        // GIR_Coverage, 824,
10490        GIR_Done,
10491      // Label 708: @24784
10492      GIM_Try, /*On fail goto*//*Label 709*/ 24848, // Rule ID 825 //
10493        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10494        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_madd_q_w,
10495        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
10496        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
10497        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
10498        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
10499        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
10500        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
10501        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
10502        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID,
10503        // (intrinsic_wo_chain:{ *:[v4i32] } 5252:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (MADD_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10504        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADD_Q_W,
10505        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10506        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10507        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10508        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10509        GIR_EraseFromParent, /*InsnID*/0,
10510        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10511        // GIR_Coverage, 825,
10512        GIR_Done,
10513      // Label 709: @24848
10514      GIM_Try, /*On fail goto*//*Label 710*/ 24912, // Rule ID 826 //
10515        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10516        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_maddr_q_h,
10517        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
10518        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
10519        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
10520        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
10521        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
10522        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
10523        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
10524        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID,
10525        // (intrinsic_wo_chain:{ *:[v8i16] } 5253:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (MADDR_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10526        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDR_Q_H,
10527        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10528        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10529        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10530        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10531        GIR_EraseFromParent, /*InsnID*/0,
10532        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10533        // GIR_Coverage, 826,
10534        GIR_Done,
10535      // Label 710: @24912
10536      GIM_Try, /*On fail goto*//*Label 711*/ 24976, // Rule ID 827 //
10537        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10538        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_maddr_q_w,
10539        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
10540        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
10541        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
10542        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
10543        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
10544        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
10545        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
10546        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID,
10547        // (intrinsic_wo_chain:{ *:[v4i32] } 5254:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (MADDR_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10548        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDR_Q_W,
10549        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10550        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10551        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10552        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10553        GIR_EraseFromParent, /*InsnID*/0,
10554        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10555        // GIR_Coverage, 827,
10556        GIR_Done,
10557      // Label 711: @24976
10558      GIM_Try, /*On fail goto*//*Label 712*/ 25040, // Rule ID 880 //
10559        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10560        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_msub_q_h,
10561        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
10562        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
10563        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
10564        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
10565        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
10566        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
10567        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
10568        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID,
10569        // (intrinsic_wo_chain:{ *:[v8i16] } 5315:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (MSUB_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10570        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUB_Q_H,
10571        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10572        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10573        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10574        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10575        GIR_EraseFromParent, /*InsnID*/0,
10576        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10577        // GIR_Coverage, 880,
10578        GIR_Done,
10579      // Label 712: @25040
10580      GIM_Try, /*On fail goto*//*Label 713*/ 25104, // Rule ID 881 //
10581        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10582        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_msub_q_w,
10583        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
10584        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
10585        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
10586        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
10587        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
10588        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
10589        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
10590        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID,
10591        // (intrinsic_wo_chain:{ *:[v4i32] } 5316:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (MSUB_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10592        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUB_Q_W,
10593        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10594        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10595        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10596        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10597        GIR_EraseFromParent, /*InsnID*/0,
10598        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10599        // GIR_Coverage, 881,
10600        GIR_Done,
10601      // Label 713: @25104
10602      GIM_Try, /*On fail goto*//*Label 714*/ 25168, // Rule ID 882 //
10603        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10604        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_msubr_q_h,
10605        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
10606        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
10607        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
10608        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
10609        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
10610        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
10611        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
10612        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID,
10613        // (intrinsic_wo_chain:{ *:[v8i16] } 5317:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (MSUBR_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10614        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBR_Q_H,
10615        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10616        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10617        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10618        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10619        GIR_EraseFromParent, /*InsnID*/0,
10620        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10621        // GIR_Coverage, 882,
10622        GIR_Done,
10623      // Label 714: @25168
10624      GIM_Try, /*On fail goto*//*Label 715*/ 25232, // Rule ID 883 //
10625        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10626        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_msubr_q_w,
10627        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
10628        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
10629        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
10630        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
10631        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
10632        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
10633        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
10634        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID,
10635        // (intrinsic_wo_chain:{ *:[v4i32] } 5318:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (MSUBR_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10636        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBR_Q_W,
10637        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10638        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10639        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10640        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10641        GIR_EraseFromParent, /*InsnID*/0,
10642        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10643        // GIR_Coverage, 883,
10644        GIR_Done,
10645      // Label 715: @25232
10646      GIM_Try, /*On fail goto*//*Label 716*/ 25296, // Rule ID 937 //
10647        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10648        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sld_b,
10649        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
10650        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
10651        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
10652        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
10653        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
10654        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
10655        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
10656        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::GPR32RegClassID,
10657        // (intrinsic_wo_chain:{ *:[v16i8] } 5419:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)  =>  (SLD_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)
10658        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLD_B,
10659        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10660        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10661        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10662        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // rt
10663        GIR_EraseFromParent, /*InsnID*/0,
10664        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10665        // GIR_Coverage, 937,
10666        GIR_Done,
10667      // Label 716: @25296
10668      GIM_Try, /*On fail goto*//*Label 717*/ 25360, // Rule ID 938 //
10669        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10670        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sld_h,
10671        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
10672        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
10673        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
10674        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
10675        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
10676        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
10677        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
10678        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::GPR32RegClassID,
10679        // (intrinsic_wo_chain:{ *:[v8i16] } 5421:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)  =>  (SLD_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)
10680        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLD_H,
10681        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10682        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10683        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10684        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // rt
10685        GIR_EraseFromParent, /*InsnID*/0,
10686        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10687        // GIR_Coverage, 938,
10688        GIR_Done,
10689      // Label 717: @25360
10690      GIM_Try, /*On fail goto*//*Label 718*/ 25424, // Rule ID 939 //
10691        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10692        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sld_w,
10693        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
10694        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
10695        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
10696        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
10697        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
10698        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
10699        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
10700        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::GPR32RegClassID,
10701        // (intrinsic_wo_chain:{ *:[v4i32] } 5422:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)  =>  (SLD_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)
10702        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLD_W,
10703        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10704        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10705        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10706        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // rt
10707        GIR_EraseFromParent, /*InsnID*/0,
10708        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10709        // GIR_Coverage, 939,
10710        GIR_Done,
10711      // Label 718: @25424
10712      GIM_Try, /*On fail goto*//*Label 719*/ 25488, // Rule ID 940 //
10713        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10714        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sld_d,
10715        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
10716        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
10717        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
10718        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
10719        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
10720        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
10721        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
10722        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::GPR32RegClassID,
10723        // (intrinsic_wo_chain:{ *:[v2i64] } 5420:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)  =>  (SLD_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)
10724        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLD_D,
10725        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10726        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10727        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10728        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // rt
10729        GIR_EraseFromParent, /*InsnID*/0,
10730        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10731        // GIR_Coverage, 940,
10732        GIR_Done,
10733      // Label 719: @25488
10734      GIM_Reject,
10735    // Label 673: @25489
10736    GIM_Reject,
10737    // Label 17: @25490
10738    GIM_Try, /*On fail goto*//*Label 720*/ 25523, // Rule ID 342 //
10739      GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
10740      GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_bposge32,
10741      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
10742      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
10743      // (intrinsic_w_chain:{ *:[i32] } 4966:{ *:[iPTR] })  =>  (BPOSGE32_PSEUDO:{ *:[i32] })
10744      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BPOSGE32_PSEUDO,
10745      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10746      GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
10747      GIR_EraseFromParent, /*InsnID*/0,
10748      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10749      // GIR_Coverage, 342,
10750      GIR_Done,
10751    // Label 720: @25523
10752    GIM_Try, /*On fail goto*//*Label 721*/ 26485,
10753      GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
10754      GIM_Try, /*On fail goto*//*Label 722*/ 25571, // Rule ID 429 //
10755        GIM_CheckFeatures, GIFBS_HasDSP,
10756        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_rddsp,
10757        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
10758        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
10759        // MIs[0] mask
10760        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
10761        GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIPFP_I64_Predicate_timmZExt10,
10762        // (intrinsic_w_chain:{ *:[i32] } 5393:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timmZExt10>>:$mask)  =>  (RDDSP:{ *:[i32] } (timm:{ *:[i32] }):$mask)
10763        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::RDDSP,
10764        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
10765        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // mask
10766        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
10767        GIR_EraseFromParent, /*InsnID*/0,
10768        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10769        // GIR_Coverage, 429,
10770        GIR_Done,
10771      // Label 722: @25571
10772      GIM_Try, /*On fail goto*//*Label 723*/ 25610, // Rule ID 1275 //
10773        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
10774        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_rddsp,
10775        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
10776        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
10777        // MIs[0] mask
10778        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
10779        // (intrinsic_w_chain:{ *:[i32] } 5393:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timmZExt7>>:$mask)  =>  (RDDSP_MM:{ *:[i32] } (timm:{ *:[i32] }):$mask)
10780        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::RDDSP_MM,
10781        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
10782        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // mask
10783        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
10784        GIR_EraseFromParent, /*InsnID*/0,
10785        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10786        // GIR_Coverage, 1275,
10787        GIR_Done,
10788      // Label 723: @25610
10789      GIM_Try, /*On fail goto*//*Label 724*/ 25653, // Rule ID 430 //
10790        GIM_CheckFeatures, GIFBS_HasDSP_NotInMicroMips,
10791        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_wrdsp,
10792        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
10793        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
10794        // MIs[0] mask
10795        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
10796        GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIPFP_I64_Predicate_timmZExt10,
10797        // (intrinsic_void 5522:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt10>>:$mask)  =>  (WRDSP GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$mask)
10798        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::WRDSP,
10799        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
10800        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // mask
10801        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
10802        GIR_EraseFromParent, /*InsnID*/0,
10803        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10804        // GIR_Coverage, 430,
10805        GIR_Done,
10806      // Label 724: @25653
10807      GIM_Try, /*On fail goto*//*Label 725*/ 25692, // Rule ID 1286 //
10808        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
10809        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_wrdsp,
10810        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
10811        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
10812        // MIs[0] mask
10813        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
10814        // (intrinsic_void 5522:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, (timm:{ *:[i32] })<<P:Predicate_timmZExt7>>:$mask)  =>  (WRDSP_MM GPR32Opnd:{ *:[i32] }:$rt, (timm:{ *:[i32] }):$mask)
10815        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::WRDSP_MM,
10816        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt
10817        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // mask
10818        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
10819        GIR_EraseFromParent, /*InsnID*/0,
10820        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10821        // GIR_Coverage, 1286,
10822        GIR_Done,
10823      // Label 725: @25692
10824      GIM_Try, /*On fail goto*//*Label 726*/ 25736, // Rule ID 351 //
10825        GIM_CheckFeatures, GIFBS_HasDSP,
10826        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_absq_s_ph,
10827        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
10828        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
10829        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
10830        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
10831        // (intrinsic_w_chain:{ *:[v2i16] } 4854:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (ABSQ_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt)
10832        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ABSQ_S_PH,
10833        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
10834        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
10835        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
10836        GIR_EraseFromParent, /*InsnID*/0,
10837        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10838        // GIR_Coverage, 351,
10839        GIR_Done,
10840      // Label 726: @25736
10841      GIM_Try, /*On fail goto*//*Label 727*/ 25780, // Rule ID 352 //
10842        GIM_CheckFeatures, GIFBS_HasDSP,
10843        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_absq_s_w,
10844        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
10845        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
10846        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
10847        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
10848        // (intrinsic_w_chain:{ *:[i32] } 4856:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt)  =>  (ABSQ_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt)
10849        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ABSQ_S_W,
10850        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
10851        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
10852        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
10853        GIR_EraseFromParent, /*InsnID*/0,
10854        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10855        // GIR_Coverage, 352,
10856        GIR_Done,
10857      // Label 727: @25780
10858      GIM_Try, /*On fail goto*//*Label 728*/ 25824, // Rule ID 438 //
10859        GIM_CheckFeatures, GIFBS_HasDSPR2,
10860        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_absq_s_qb,
10861        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
10862        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
10863        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
10864        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
10865        // (intrinsic_w_chain:{ *:[v4i8] } 4855:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (ABSQ_S_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt)
10866        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ABSQ_S_QB,
10867        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
10868        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
10869        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
10870        GIR_EraseFromParent, /*InsnID*/0,
10871        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10872        // GIR_Coverage, 438,
10873        GIR_Done,
10874      // Label 728: @25824
10875      GIM_Try, /*On fail goto*//*Label 729*/ 25868, // Rule ID 1218 //
10876        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
10877        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_absq_s_ph,
10878        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
10879        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
10880        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
10881        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
10882        // (intrinsic_w_chain:{ *:[v2i16] } 4854:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs)  =>  (ABSQ_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs)
10883        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ABSQ_S_PH_MM,
10884        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
10885        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
10886        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
10887        GIR_EraseFromParent, /*InsnID*/0,
10888        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10889        // GIR_Coverage, 1218,
10890        GIR_Done,
10891      // Label 729: @25868
10892      GIM_Try, /*On fail goto*//*Label 730*/ 25912, // Rule ID 1219 //
10893        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
10894        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_absq_s_w,
10895        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
10896        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
10897        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
10898        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
10899        // (intrinsic_w_chain:{ *:[i32] } 4856:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs)  =>  (ABSQ_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
10900        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ABSQ_S_W_MM,
10901        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
10902        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
10903        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
10904        GIR_EraseFromParent, /*InsnID*/0,
10905        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10906        // GIR_Coverage, 1219,
10907        GIR_Done,
10908      // Label 730: @25912
10909      GIM_Try, /*On fail goto*//*Label 731*/ 25956, // Rule ID 1299 //
10910        GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
10911        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_absq_s_qb,
10912        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
10913        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
10914        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
10915        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
10916        // (intrinsic_w_chain:{ *:[v4i8] } 4855:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs)  =>  (ABSQ_S_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs)
10917        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ABSQ_S_QB_MMR2,
10918        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
10919        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
10920        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
10921        GIR_EraseFromParent, /*InsnID*/0,
10922        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10923        // GIR_Coverage, 1299,
10924        GIR_Done,
10925      // Label 731: @25956
10926      GIM_Try, /*On fail goto*//*Label 732*/ 26000, // Rule ID 405 //
10927        GIM_CheckFeatures, GIFBS_HasDSP,
10928        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmpu_eq_qb,
10929        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8,
10930        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
10931        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
10932        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
10933        // (intrinsic_void 5032:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPU_EQ_QB DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
10934        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPU_EQ_QB,
10935        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
10936        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
10937        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
10938        GIR_EraseFromParent, /*InsnID*/0,
10939        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10940        // GIR_Coverage, 405,
10941        GIR_Done,
10942      // Label 732: @26000
10943      GIM_Try, /*On fail goto*//*Label 733*/ 26044, // Rule ID 406 //
10944        GIM_CheckFeatures, GIFBS_HasDSP,
10945        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmpu_lt_qb,
10946        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8,
10947        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
10948        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
10949        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
10950        // (intrinsic_void 5034:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPU_LT_QB DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
10951        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPU_LT_QB,
10952        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
10953        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
10954        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
10955        GIR_EraseFromParent, /*InsnID*/0,
10956        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10957        // GIR_Coverage, 406,
10958        GIR_Done,
10959      // Label 733: @26044
10960      GIM_Try, /*On fail goto*//*Label 734*/ 26088, // Rule ID 407 //
10961        GIM_CheckFeatures, GIFBS_HasDSP,
10962        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmpu_le_qb,
10963        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8,
10964        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
10965        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
10966        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
10967        // (intrinsic_void 5033:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPU_LE_QB DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
10968        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPU_LE_QB,
10969        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
10970        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
10971        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
10972        GIR_EraseFromParent, /*InsnID*/0,
10973        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10974        // GIR_Coverage, 407,
10975        GIR_Done,
10976      // Label 734: @26088
10977      GIM_Try, /*On fail goto*//*Label 735*/ 26132, // Rule ID 411 //
10978        GIM_CheckFeatures, GIFBS_HasDSP,
10979        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmp_eq_ph,
10980        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
10981        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
10982        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
10983        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
10984        // (intrinsic_void 5023:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (CMP_EQ_PH DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
10985        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_EQ_PH,
10986        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
10987        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
10988        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
10989        GIR_EraseFromParent, /*InsnID*/0,
10990        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10991        // GIR_Coverage, 411,
10992        GIR_Done,
10993      // Label 735: @26132
10994      GIM_Try, /*On fail goto*//*Label 736*/ 26176, // Rule ID 412 //
10995        GIM_CheckFeatures, GIFBS_HasDSP,
10996        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmp_lt_ph,
10997        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
10998        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
10999        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
11000        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11001        // (intrinsic_void 5025:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (CMP_LT_PH DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11002        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LT_PH,
11003        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
11004        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
11005        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11006        GIR_EraseFromParent, /*InsnID*/0,
11007        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11008        // GIR_Coverage, 412,
11009        GIR_Done,
11010      // Label 736: @26176
11011      GIM_Try, /*On fail goto*//*Label 737*/ 26220, // Rule ID 413 //
11012        GIM_CheckFeatures, GIFBS_HasDSP,
11013        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmp_le_ph,
11014        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
11015        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
11016        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
11017        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11018        // (intrinsic_void 5024:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (CMP_LE_PH DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11019        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LE_PH,
11020        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
11021        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
11022        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11023        GIR_EraseFromParent, /*InsnID*/0,
11024        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11025        // GIR_Coverage, 413,
11026        GIR_Done,
11027      // Label 737: @26220
11028      GIM_Try, /*On fail goto*//*Label 738*/ 26264, // Rule ID 1290 //
11029        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
11030        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmp_eq_ph,
11031        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
11032        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
11033        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
11034        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11035        // (intrinsic_void 5023:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (CMP_EQ_PH_MM DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11036        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_EQ_PH_MM,
11037        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
11038        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
11039        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11040        GIR_EraseFromParent, /*InsnID*/0,
11041        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11042        // GIR_Coverage, 1290,
11043        GIR_Done,
11044      // Label 738: @26264
11045      GIM_Try, /*On fail goto*//*Label 739*/ 26308, // Rule ID 1291 //
11046        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
11047        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmp_lt_ph,
11048        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
11049        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
11050        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
11051        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11052        // (intrinsic_void 5025:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (CMP_LT_PH_MM DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11053        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LT_PH_MM,
11054        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
11055        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
11056        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11057        GIR_EraseFromParent, /*InsnID*/0,
11058        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11059        // GIR_Coverage, 1291,
11060        GIR_Done,
11061      // Label 739: @26308
11062      GIM_Try, /*On fail goto*//*Label 740*/ 26352, // Rule ID 1292 //
11063        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
11064        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmp_le_ph,
11065        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
11066        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
11067        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
11068        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11069        // (intrinsic_void 5024:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (CMP_LE_PH_MM DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11070        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LE_PH_MM,
11071        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
11072        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
11073        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11074        GIR_EraseFromParent, /*InsnID*/0,
11075        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11076        // GIR_Coverage, 1292,
11077        GIR_Done,
11078      // Label 740: @26352
11079      GIM_Try, /*On fail goto*//*Label 741*/ 26396, // Rule ID 1296 //
11080        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
11081        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmpu_eq_qb,
11082        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8,
11083        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
11084        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
11085        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11086        // (intrinsic_void 5032:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPU_EQ_QB_MM DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
11087        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPU_EQ_QB_MM,
11088        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
11089        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
11090        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11091        GIR_EraseFromParent, /*InsnID*/0,
11092        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11093        // GIR_Coverage, 1296,
11094        GIR_Done,
11095      // Label 741: @26396
11096      GIM_Try, /*On fail goto*//*Label 742*/ 26440, // Rule ID 1297 //
11097        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
11098        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmpu_lt_qb,
11099        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8,
11100        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
11101        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
11102        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11103        // (intrinsic_void 5034:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPU_LT_QB_MM DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
11104        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPU_LT_QB_MM,
11105        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
11106        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
11107        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11108        GIR_EraseFromParent, /*InsnID*/0,
11109        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11110        // GIR_Coverage, 1297,
11111        GIR_Done,
11112      // Label 742: @26440
11113      GIM_Try, /*On fail goto*//*Label 743*/ 26484, // Rule ID 1298 //
11114        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
11115        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmpu_le_qb,
11116        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8,
11117        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
11118        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
11119        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11120        // (intrinsic_void 5033:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPU_LE_QB_MM DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
11121        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPU_LE_QB_MM,
11122        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
11123        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
11124        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11125        GIR_EraseFromParent, /*InsnID*/0,
11126        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11127        // GIR_Coverage, 1298,
11128        GIR_Done,
11129      // Label 743: @26484
11130      GIM_Reject,
11131    // Label 721: @26485
11132    GIM_Try, /*On fail goto*//*Label 744*/ 30473,
11133      GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
11134      GIM_Try, /*On fail goto*//*Label 745*/ 26554, // Rule ID 370 //
11135        GIM_CheckFeatures, GIFBS_HasDSP,
11136        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_s_ph,
11137        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
11138        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
11139        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11140        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11141        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11142        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
11143        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
11144        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt4,
11145        // MIs[1] Operand 1
11146        // No operand predicates
11147        GIM_CheckIsSafeToFold, /*InsnID*/1,
11148        // (intrinsic_w_chain:{ *:[v2i16] } 5410:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$rs_sa)  =>  (SHLL_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, (imm:{ *:[i32] }):$rs_sa)
11149        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLL_S_PH,
11150        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11151        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
11152        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa
11153        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
11154        GIR_EraseFromParent, /*InsnID*/0,
11155        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11156        // GIR_Coverage, 370,
11157        GIR_Done,
11158      // Label 745: @26554
11159      GIM_Try, /*On fail goto*//*Label 746*/ 26618, // Rule ID 375 //
11160        GIM_CheckFeatures, GIFBS_HasDSP,
11161        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_s_w,
11162        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11163        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
11164        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11165        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
11166        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
11167        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
11168        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
11169        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
11170        // MIs[1] Operand 1
11171        // No operand predicates
11172        GIM_CheckIsSafeToFold, /*InsnID*/1,
11173        // (intrinsic_w_chain:{ *:[i32] } 5411:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$rs_sa)  =>  (SHLL_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$rs_sa)
11174        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLL_S_W,
11175        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11176        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
11177        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa
11178        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
11179        GIR_EraseFromParent, /*InsnID*/0,
11180        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11181        // GIR_Coverage, 375,
11182        GIR_Done,
11183      // Label 746: @26618
11184      GIM_Try, /*On fail goto*//*Label 747*/ 26682, // Rule ID 1227 //
11185        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
11186        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_s_ph,
11187        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
11188        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
11189        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11190        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11191        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11192        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
11193        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
11194        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt4,
11195        // MIs[1] Operand 1
11196        // No operand predicates
11197        GIM_CheckIsSafeToFold, /*InsnID*/1,
11198        // (intrinsic_w_chain:{ *:[v2i16] } 5410:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$sa)  =>  (SHLL_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, (imm:{ *:[i32] }):$sa)
11199        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLL_S_PH_MM,
11200        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
11201        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11202        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
11203        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
11204        GIR_EraseFromParent, /*InsnID*/0,
11205        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11206        // GIR_Coverage, 1227,
11207        GIR_Done,
11208      // Label 747: @26682
11209      GIM_Try, /*On fail goto*//*Label 748*/ 26746, // Rule ID 1232 //
11210        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
11211        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_s_w,
11212        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11213        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
11214        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11215        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
11216        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
11217        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
11218        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
11219        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
11220        // MIs[1] Operand 1
11221        // No operand predicates
11222        GIM_CheckIsSafeToFold, /*InsnID*/1,
11223        // (intrinsic_w_chain:{ *:[i32] } 5411:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$sa)  =>  (SHLL_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa)
11224        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLL_S_W_MM,
11225        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
11226        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11227        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
11228        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
11229        GIR_EraseFromParent, /*InsnID*/0,
11230        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11231        // GIR_Coverage, 1232,
11232        GIR_Done,
11233      // Label 748: @26746
11234      GIM_Try, /*On fail goto*//*Label 749*/ 26801, // Rule ID 1898 //
11235        GIM_CheckFeatures, GIFBS_HasDSP,
11236        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_ph,
11237        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
11238        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
11239        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11240        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11241        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
11242        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
11243        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt4,
11244        // MIs[1] Operand 1
11245        // No operand predicates
11246        GIM_CheckIsSafeToFold, /*InsnID*/1,
11247        // (intrinsic_w_chain:{ *:[v2i16] } 5408:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt)  =>  (SHLL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt)
11248        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLL_PH,
11249        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11250        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
11251        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
11252        GIR_EraseFromParent, /*InsnID*/0,
11253        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11254        // GIR_Coverage, 1898,
11255        GIR_Done,
11256      // Label 749: @26801
11257      GIM_Try, /*On fail goto*//*Label 750*/ 26856, // Rule ID 1904 //
11258        GIM_CheckFeatures, GIFBS_HasDSP,
11259        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_qb,
11260        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
11261        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
11262        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11263        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11264        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
11265        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
11266        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt3,
11267        // MIs[1] Operand 1
11268        // No operand predicates
11269        GIM_CheckIsSafeToFold, /*InsnID*/1,
11270        // (intrinsic_w_chain:{ *:[v4i8] } 5409:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt)  =>  (SHLL_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt)
11271        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLL_QB,
11272        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11273        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
11274        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
11275        GIR_EraseFromParent, /*InsnID*/0,
11276        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11277        // GIR_Coverage, 1904,
11278        GIR_Done,
11279      // Label 750: @26856
11280      GIM_Try, /*On fail goto*//*Label 751*/ 26912, // Rule ID 347 //
11281        GIM_CheckFeatures, GIFBS_HasDSP,
11282        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addq_s_w,
11283        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11284        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
11285        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11286        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
11287        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
11288        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
11289        // (intrinsic_w_chain:{ *:[i32] } 4863:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (ADDQ_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
11290        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQ_S_W,
11291        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11292        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11293        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11294        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11295        GIR_EraseFromParent, /*InsnID*/0,
11296        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11297        // GIR_Coverage, 347,
11298        GIR_Done,
11299      // Label 751: @26912
11300      GIM_Try, /*On fail goto*//*Label 752*/ 26968, // Rule ID 348 //
11301        GIM_CheckFeatures, GIFBS_HasDSP,
11302        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subq_s_w,
11303        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11304        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
11305        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11306        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
11307        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
11308        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
11309        // (intrinsic_w_chain:{ *:[i32] } 5483:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (SUBQ_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
11310        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQ_S_W,
11311        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11312        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11313        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11314        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11315        GIR_EraseFromParent, /*InsnID*/0,
11316        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11317        // GIR_Coverage, 348,
11318        GIR_Done,
11319      // Label 752: @26968
11320      GIM_Try, /*On fail goto*//*Label 753*/ 27024, // Rule ID 355 //
11321        GIM_CheckFeatures, GIFBS_HasDSP,
11322        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precrq_rs_ph_w,
11323        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
11324        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
11325        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11326        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11327        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
11328        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
11329        // (intrinsic_w_chain:{ *:[v2i16] } 5389:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (PRECRQ_RS_PH_W:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
11330        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECRQ_RS_PH_W,
11331        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11332        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11333        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11334        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11335        GIR_EraseFromParent, /*InsnID*/0,
11336        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11337        // GIR_Coverage, 355,
11338        GIR_Done,
11339      // Label 753: @27024
11340      GIM_Try, /*On fail goto*//*Label 754*/ 27080, // Rule ID 356 //
11341        GIM_CheckFeatures, GIFBS_HasDSP,
11342        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precrqu_s_qb_ph,
11343        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
11344        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
11345        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
11346        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11347        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11348        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11349        // (intrinsic_w_chain:{ *:[v4i8] } 5390:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (PRECRQU_S_QB_PH:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11350        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECRQU_S_QB_PH,
11351        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11352        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11353        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11354        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11355        GIR_EraseFromParent, /*InsnID*/0,
11356        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11357        // GIR_Coverage, 356,
11358        GIR_Done,
11359      // Label 754: @27080
11360      GIM_Try, /*On fail goto*//*Label 755*/ 27136, // Rule ID 367 //
11361        GIM_CheckFeatures, GIFBS_HasDSP,
11362        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_qb,
11363        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
11364        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
11365        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11366        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11367        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11368        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
11369        // (intrinsic_w_chain:{ *:[v4i8] } 5409:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)  =>  (SHLLV_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
11370        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLLV_QB,
11371        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11372        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
11373        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa
11374        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11375        GIR_EraseFromParent, /*InsnID*/0,
11376        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11377        // GIR_Coverage, 367,
11378        GIR_Done,
11379      // Label 755: @27136
11380      GIM_Try, /*On fail goto*//*Label 756*/ 27192, // Rule ID 369 //
11381        GIM_CheckFeatures, GIFBS_HasDSP,
11382        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_ph,
11383        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
11384        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
11385        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11386        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11387        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11388        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
11389        // (intrinsic_w_chain:{ *:[v2i16] } 5408:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)  =>  (SHLLV_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
11390        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLLV_PH,
11391        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11392        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
11393        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa
11394        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11395        GIR_EraseFromParent, /*InsnID*/0,
11396        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11397        // GIR_Coverage, 369,
11398        GIR_Done,
11399      // Label 756: @27192
11400      GIM_Try, /*On fail goto*//*Label 757*/ 27248, // Rule ID 371 //
11401        GIM_CheckFeatures, GIFBS_HasDSP,
11402        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_s_ph,
11403        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
11404        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
11405        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11406        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11407        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11408        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
11409        // (intrinsic_w_chain:{ *:[v2i16] } 5410:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)  =>  (SHLLV_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
11410        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLLV_S_PH,
11411        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11412        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
11413        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa
11414        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11415        GIR_EraseFromParent, /*InsnID*/0,
11416        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11417        // GIR_Coverage, 371,
11418        GIR_Done,
11419      // Label 757: @27248
11420      GIM_Try, /*On fail goto*//*Label 758*/ 27304, // Rule ID 376 //
11421        GIM_CheckFeatures, GIFBS_HasDSP,
11422        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_s_w,
11423        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11424        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
11425        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11426        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
11427        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
11428        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
11429        // (intrinsic_w_chain:{ *:[i32] } 5411:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)  =>  (SHLLV_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
11430        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLLV_S_W,
11431        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11432        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
11433        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa
11434        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11435        GIR_EraseFromParent, /*InsnID*/0,
11436        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11437        // GIR_Coverage, 376,
11438        GIR_Done,
11439      // Label 758: @27304
11440      GIM_Try, /*On fail goto*//*Label 759*/ 27360, // Rule ID 379 //
11441        GIM_CheckFeatures, GIFBS_HasDSP,
11442        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_muleu_s_ph_qbl,
11443        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
11444        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
11445        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
11446        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11447        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11448        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11449        // (intrinsic_w_chain:{ *:[v2i16] } 5331:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (MULEU_S_PH_QBL:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11450        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULEU_S_PH_QBL,
11451        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11452        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11453        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11454        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11455        GIR_EraseFromParent, /*InsnID*/0,
11456        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11457        // GIR_Coverage, 379,
11458        GIR_Done,
11459      // Label 759: @27360
11460      GIM_Try, /*On fail goto*//*Label 760*/ 27416, // Rule ID 380 //
11461        GIM_CheckFeatures, GIFBS_HasDSP,
11462        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_muleu_s_ph_qbr,
11463        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
11464        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
11465        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
11466        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11467        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11468        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11469        // (intrinsic_w_chain:{ *:[v2i16] } 5332:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (MULEU_S_PH_QBR:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11470        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULEU_S_PH_QBR,
11471        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11472        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11473        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11474        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11475        GIR_EraseFromParent, /*InsnID*/0,
11476        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11477        // GIR_Coverage, 380,
11478        GIR_Done,
11479      // Label 760: @27416
11480      GIM_Try, /*On fail goto*//*Label 761*/ 27472, // Rule ID 381 //
11481        GIM_CheckFeatures, GIFBS_HasDSP,
11482        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_muleq_s_w_phl,
11483        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11484        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
11485        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
11486        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
11487        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11488        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11489        // (intrinsic_w_chain:{ *:[i32] } 5329:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (MULEQ_S_W_PHL:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11490        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULEQ_S_W_PHL,
11491        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11492        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11493        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11494        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11495        GIR_EraseFromParent, /*InsnID*/0,
11496        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11497        // GIR_Coverage, 381,
11498        GIR_Done,
11499      // Label 761: @27472
11500      GIM_Try, /*On fail goto*//*Label 762*/ 27528, // Rule ID 382 //
11501        GIM_CheckFeatures, GIFBS_HasDSP,
11502        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_muleq_s_w_phr,
11503        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11504        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
11505        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
11506        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
11507        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11508        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11509        // (intrinsic_w_chain:{ *:[i32] } 5330:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (MULEQ_S_W_PHR:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11510        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULEQ_S_W_PHR,
11511        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11512        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11513        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11514        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11515        GIR_EraseFromParent, /*InsnID*/0,
11516        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11517        // GIR_Coverage, 382,
11518        GIR_Done,
11519      // Label 762: @27528
11520      GIM_Try, /*On fail goto*//*Label 763*/ 27584, // Rule ID 383 //
11521        GIM_CheckFeatures, GIFBS_HasDSP,
11522        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulq_rs_ph,
11523        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
11524        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
11525        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
11526        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11527        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11528        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11529        // (intrinsic_w_chain:{ *:[v2i16] } 5333:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (MULQ_RS_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11530        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULQ_RS_PH,
11531        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11532        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11533        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11534        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11535        GIR_EraseFromParent, /*InsnID*/0,
11536        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11537        // GIR_Coverage, 383,
11538        GIR_Done,
11539      // Label 763: @27584
11540      GIM_Try, /*On fail goto*//*Label 764*/ 27640, // Rule ID 408 //
11541        GIM_CheckFeatures, GIFBS_HasDSP,
11542        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgu_eq_qb,
11543        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11544        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
11545        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
11546        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
11547        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11548        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11549        // (intrinsic_w_chain:{ *:[i32] } 5029:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPGU_EQ_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
11550        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGU_EQ_QB,
11551        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11552        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11553        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11554        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11555        GIR_EraseFromParent, /*InsnID*/0,
11556        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11557        // GIR_Coverage, 408,
11558        GIR_Done,
11559      // Label 764: @27640
11560      GIM_Try, /*On fail goto*//*Label 765*/ 27696, // Rule ID 409 //
11561        GIM_CheckFeatures, GIFBS_HasDSP,
11562        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgu_lt_qb,
11563        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11564        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
11565        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
11566        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
11567        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11568        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11569        // (intrinsic_w_chain:{ *:[i32] } 5031:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPGU_LT_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
11570        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGU_LT_QB,
11571        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11572        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11573        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11574        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11575        GIR_EraseFromParent, /*InsnID*/0,
11576        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11577        // GIR_Coverage, 409,
11578        GIR_Done,
11579      // Label 765: @27696
11580      GIM_Try, /*On fail goto*//*Label 766*/ 27752, // Rule ID 410 //
11581        GIM_CheckFeatures, GIFBS_HasDSP,
11582        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgu_le_qb,
11583        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11584        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
11585        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
11586        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
11587        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11588        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11589        // (intrinsic_w_chain:{ *:[i32] } 5030:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPGU_LE_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
11590        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGU_LE_QB,
11591        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11592        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11593        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11594        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11595        GIR_EraseFromParent, /*InsnID*/0,
11596        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11597        // GIR_Coverage, 410,
11598        GIR_Done,
11599      // Label 766: @27752
11600      GIM_Try, /*On fail goto*//*Label 767*/ 27808, // Rule ID 420 //
11601        GIM_CheckFeatures, GIFBS_HasDSP,
11602        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_pick_qb,
11603        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
11604        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
11605        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
11606        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11607        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11608        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11609        // (intrinsic_w_chain:{ *:[v4i8] } 5373:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PICK_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
11610        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PICK_QB,
11611        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11612        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11613        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11614        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11615        GIR_EraseFromParent, /*InsnID*/0,
11616        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11617        // GIR_Coverage, 420,
11618        GIR_Done,
11619      // Label 767: @27808
11620      GIM_Try, /*On fail goto*//*Label 768*/ 27864, // Rule ID 421 //
11621        GIM_CheckFeatures, GIFBS_HasDSP,
11622        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_pick_ph,
11623        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
11624        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
11625        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
11626        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11627        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11628        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11629        // (intrinsic_w_chain:{ *:[v2i16] } 5372:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (PICK_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11630        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PICK_PH,
11631        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11632        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11633        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11634        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11635        GIR_EraseFromParent, /*InsnID*/0,
11636        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11637        // GIR_Coverage, 421,
11638        GIR_Done,
11639      // Label 768: @27864
11640      GIM_Try, /*On fail goto*//*Label 769*/ 27920, // Rule ID 425 //
11641        GIM_CheckFeatures, GIFBS_HasDSP,
11642        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_insv,
11643        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11644        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
11645        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11646        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
11647        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
11648        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
11649        // (intrinsic_w_chain:{ *:[i32] } 5231:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs)  =>  (INSV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs)
11650        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::INSV,
11651        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
11652        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
11653        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
11654        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11655        GIR_EraseFromParent, /*InsnID*/0,
11656        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11657        // GIR_Coverage, 425,
11658        GIR_Done,
11659      // Label 769: @27920
11660      GIM_Try, /*On fail goto*//*Label 770*/ 27976, // Rule ID 431 //
11661        GIM_CheckFeatures, GIFBS_HasDSPR2,
11662        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addu_ph,
11663        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
11664        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
11665        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
11666        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11667        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11668        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11669        // (intrinsic_w_chain:{ *:[v2i16] } 4881:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (ADDU_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11670        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDU_PH,
11671        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11672        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11673        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11674        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11675        GIR_EraseFromParent, /*InsnID*/0,
11676        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11677        // GIR_Coverage, 431,
11678        GIR_Done,
11679      // Label 770: @27976
11680      GIM_Try, /*On fail goto*//*Label 771*/ 28032, // Rule ID 432 //
11681        GIM_CheckFeatures, GIFBS_HasDSPR2,
11682        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addu_s_ph,
11683        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
11684        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
11685        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
11686        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11687        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11688        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11689        // (intrinsic_w_chain:{ *:[v2i16] } 4883:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (ADDU_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11690        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDU_S_PH,
11691        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11692        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11693        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11694        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11695        GIR_EraseFromParent, /*InsnID*/0,
11696        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11697        // GIR_Coverage, 432,
11698        GIR_Done,
11699      // Label 771: @28032
11700      GIM_Try, /*On fail goto*//*Label 772*/ 28088, // Rule ID 433 //
11701        GIM_CheckFeatures, GIFBS_HasDSPR2,
11702        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subu_ph,
11703        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
11704        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
11705        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
11706        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11707        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11708        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11709        // (intrinsic_w_chain:{ *:[v2i16] } 5504:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (SUBU_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11710        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBU_PH,
11711        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11712        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11713        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11714        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11715        GIR_EraseFromParent, /*InsnID*/0,
11716        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11717        // GIR_Coverage, 433,
11718        GIR_Done,
11719      // Label 772: @28088
11720      GIM_Try, /*On fail goto*//*Label 773*/ 28144, // Rule ID 434 //
11721        GIM_CheckFeatures, GIFBS_HasDSPR2,
11722        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subu_s_ph,
11723        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
11724        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
11725        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
11726        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11727        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11728        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11729        // (intrinsic_w_chain:{ *:[v2i16] } 5506:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (SUBU_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11730        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBU_S_PH,
11731        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11732        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11733        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11734        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11735        GIR_EraseFromParent, /*InsnID*/0,
11736        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11737        // GIR_Coverage, 434,
11738        GIR_Done,
11739      // Label 773: @28144
11740      GIM_Try, /*On fail goto*//*Label 774*/ 28200, // Rule ID 435 //
11741        GIM_CheckFeatures, GIFBS_HasDSPR2,
11742        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgdu_eq_qb,
11743        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11744        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
11745        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
11746        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
11747        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11748        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11749        // (intrinsic_w_chain:{ *:[i32] } 5026:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPGDU_EQ_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
11750        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGDU_EQ_QB,
11751        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11752        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11753        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11754        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11755        GIR_EraseFromParent, /*InsnID*/0,
11756        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11757        // GIR_Coverage, 435,
11758        GIR_Done,
11759      // Label 774: @28200
11760      GIM_Try, /*On fail goto*//*Label 775*/ 28256, // Rule ID 436 //
11761        GIM_CheckFeatures, GIFBS_HasDSPR2,
11762        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgdu_lt_qb,
11763        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11764        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
11765        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
11766        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
11767        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11768        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11769        // (intrinsic_w_chain:{ *:[i32] } 5028:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPGDU_LT_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
11770        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGDU_LT_QB,
11771        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11772        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11773        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11774        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11775        GIR_EraseFromParent, /*InsnID*/0,
11776        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11777        // GIR_Coverage, 436,
11778        GIR_Done,
11779      // Label 775: @28256
11780      GIM_Try, /*On fail goto*//*Label 776*/ 28312, // Rule ID 437 //
11781        GIM_CheckFeatures, GIFBS_HasDSPR2,
11782        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgdu_le_qb,
11783        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11784        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
11785        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
11786        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
11787        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11788        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11789        // (intrinsic_w_chain:{ *:[i32] } 5027:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPGDU_LE_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
11790        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGDU_LE_QB,
11791        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11792        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11793        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11794        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11795        GIR_EraseFromParent, /*InsnID*/0,
11796        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11797        // GIR_Coverage, 437,
11798        GIR_Done,
11799      // Label 776: @28312
11800      GIM_Try, /*On fail goto*//*Label 777*/ 28368, // Rule ID 451 //
11801        GIM_CheckFeatures, GIFBS_HasDSPR2,
11802        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mul_s_ph,
11803        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
11804        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
11805        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
11806        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11807        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11808        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11809        // (intrinsic_w_chain:{ *:[v2i16] } 5328:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (MUL_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11810        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MUL_S_PH,
11811        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11812        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11813        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11814        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11815        GIR_EraseFromParent, /*InsnID*/0,
11816        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11817        // GIR_Coverage, 451,
11818        GIR_Done,
11819      // Label 777: @28368
11820      GIM_Try, /*On fail goto*//*Label 778*/ 28424, // Rule ID 452 //
11821        GIM_CheckFeatures, GIFBS_HasDSPR2,
11822        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulq_s_w,
11823        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11824        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
11825        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11826        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
11827        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
11828        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
11829        // (intrinsic_w_chain:{ *:[i32] } 5336:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MULQ_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
11830        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULQ_S_W,
11831        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11832        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11833        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11834        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11835        GIR_EraseFromParent, /*InsnID*/0,
11836        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11837        // GIR_Coverage, 452,
11838        GIR_Done,
11839      // Label 778: @28424
11840      GIM_Try, /*On fail goto*//*Label 779*/ 28480, // Rule ID 453 //
11841        GIM_CheckFeatures, GIFBS_HasDSPR2,
11842        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulq_rs_w,
11843        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11844        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
11845        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11846        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
11847        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
11848        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
11849        // (intrinsic_w_chain:{ *:[i32] } 5334:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MULQ_RS_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
11850        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULQ_RS_W,
11851        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11852        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11853        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11854        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11855        GIR_EraseFromParent, /*InsnID*/0,
11856        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11857        // GIR_Coverage, 453,
11858        GIR_Done,
11859      // Label 779: @28480
11860      GIM_Try, /*On fail goto*//*Label 780*/ 28536, // Rule ID 454 //
11861        GIM_CheckFeatures, GIFBS_HasDSPR2,
11862        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulq_s_ph,
11863        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
11864        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
11865        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
11866        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11867        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11868        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11869        // (intrinsic_w_chain:{ *:[v2i16] } 5335:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (MULQ_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11870        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULQ_S_PH,
11871        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11872        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11873        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11874        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11875        GIR_EraseFromParent, /*InsnID*/0,
11876        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11877        // GIR_Coverage, 454,
11878        GIR_Done,
11879      // Label 780: @28536
11880      GIM_Try, /*On fail goto*//*Label 781*/ 28592, // Rule ID 464 //
11881        GIM_CheckFeatures, GIFBS_HasDSPR2,
11882        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precr_qb_ph,
11883        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
11884        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
11885        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
11886        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11887        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11888        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11889        // (intrinsic_w_chain:{ *:[v4i8] } 5384:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (PRECR_QB_PH:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11890        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECR_QB_PH,
11891        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11892        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11893        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11894        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11895        GIR_EraseFromParent, /*InsnID*/0,
11896        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11897        // GIR_Coverage, 464,
11898        GIR_Done,
11899      // Label 781: @28592
11900      GIM_Try, /*On fail goto*//*Label 782*/ 28648, // Rule ID 1212 //
11901        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
11902        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addq_s_w,
11903        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11904        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
11905        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11906        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
11907        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
11908        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
11909        // (intrinsic_w_chain:{ *:[i32] } 4863:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (ADDQ_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
11910        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQ_S_W_MM,
11911        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11912        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11913        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11914        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11915        GIR_EraseFromParent, /*InsnID*/0,
11916        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11917        // GIR_Coverage, 1212,
11918        GIR_Done,
11919      // Label 782: @28648
11920      GIM_Try, /*On fail goto*//*Label 783*/ 28704, // Rule ID 1220 //
11921        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
11922        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_insv,
11923        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11924        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
11925        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11926        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
11927        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
11928        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
11929        // (intrinsic_w_chain:{ *:[i32] } 5231:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs)  =>  (INSV_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs)
11930        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::INSV_MM,
11931        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
11932        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
11933        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
11934        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11935        GIR_EraseFromParent, /*InsnID*/0,
11936        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11937        // GIR_Coverage, 1220,
11938        GIR_Done,
11939      // Label 783: @28704
11940      GIM_Try, /*On fail goto*//*Label 784*/ 28760, // Rule ID 1228 //
11941        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
11942        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_ph,
11943        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
11944        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
11945        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11946        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11947        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11948        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
11949        // (intrinsic_w_chain:{ *:[v2i16] } 5408:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)  =>  (SHLLV_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
11950        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLLV_PH_MM,
11951        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11952        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
11953        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
11954        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11955        GIR_EraseFromParent, /*InsnID*/0,
11956        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11957        // GIR_Coverage, 1228,
11958        GIR_Done,
11959      // Label 784: @28760
11960      GIM_Try, /*On fail goto*//*Label 785*/ 28816, // Rule ID 1229 //
11961        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
11962        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_s_ph,
11963        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
11964        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
11965        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11966        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11967        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11968        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
11969        // (intrinsic_w_chain:{ *:[v2i16] } 5410:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)  =>  (SHLLV_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
11970        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLLV_S_PH_MM,
11971        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11972        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
11973        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
11974        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11975        GIR_EraseFromParent, /*InsnID*/0,
11976        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11977        // GIR_Coverage, 1229,
11978        GIR_Done,
11979      // Label 785: @28816
11980      GIM_Try, /*On fail goto*//*Label 786*/ 28872, // Rule ID 1230 //
11981        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
11982        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_qb,
11983        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
11984        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
11985        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11986        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11987        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11988        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
11989        // (intrinsic_w_chain:{ *:[v4i8] } 5409:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)  =>  (SHLLV_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
11990        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLLV_QB_MM,
11991        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11992        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
11993        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
11994        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11995        GIR_EraseFromParent, /*InsnID*/0,
11996        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11997        // GIR_Coverage, 1230,
11998        GIR_Done,
11999      // Label 786: @28872
12000      GIM_Try, /*On fail goto*//*Label 787*/ 28928, // Rule ID 1231 //
12001        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
12002        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_s_w,
12003        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12004        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12005        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
12006        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
12007        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
12008        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
12009        // (intrinsic_w_chain:{ *:[i32] } 5411:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)  =>  (SHLLV_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
12010        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLLV_S_W_MM,
12011        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12012        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
12013        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
12014        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
12015        GIR_EraseFromParent, /*InsnID*/0,
12016        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12017        // GIR_Coverage, 1231,
12018        GIR_Done,
12019      // Label 787: @28928
12020      GIM_Try, /*On fail goto*//*Label 788*/ 28984, // Rule ID 1250 //
12021        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
12022        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subq_s_w,
12023        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12024        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12025        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
12026        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
12027        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
12028        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
12029        // (intrinsic_w_chain:{ *:[i32] } 5483:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (SUBQ_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
12030        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQ_S_W_MM,
12031        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12032        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
12033        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
12034        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
12035        GIR_EraseFromParent, /*InsnID*/0,
12036        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12037        // GIR_Coverage, 1250,
12038        GIR_Done,
12039      // Label 788: @28984
12040      GIM_Try, /*On fail goto*//*Label 789*/ 29040, // Rule ID 1256 //
12041        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
12042        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_muleq_s_w_phl,
12043        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12044        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
12045        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
12046        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
12047        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
12048        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
12049        // (intrinsic_w_chain:{ *:[i32] } 5329:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (MULEQ_S_W_PHL_MM:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12050        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULEQ_S_W_PHL_MM,
12051        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12052        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
12053        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
12054        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
12055        GIR_EraseFromParent, /*InsnID*/0,
12056        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12057        // GIR_Coverage, 1256,
12058        GIR_Done,
12059      // Label 789: @29040
12060      GIM_Try, /*On fail goto*//*Label 790*/ 29096, // Rule ID 1257 //
12061        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
12062        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_muleq_s_w_phr,
12063        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12064        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
12065        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
12066        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
12067        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
12068        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
12069        // (intrinsic_w_chain:{ *:[i32] } 5330:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (MULEQ_S_W_PHR_MM:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12070        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULEQ_S_W_PHR_MM,
12071        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12072        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
12073        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
12074        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
12075        GIR_EraseFromParent, /*InsnID*/0,
12076        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12077        // GIR_Coverage, 1257,
12078        GIR_Done,
12079      // Label 790: @29096
12080      GIM_Try, /*On fail goto*//*Label 791*/ 29152, // Rule ID 1258 //
12081        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
12082        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_muleu_s_ph_qbl,
12083        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
12084        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
12085        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
12086        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
12087        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
12088        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
12089        // (intrinsic_w_chain:{ *:[v2i16] } 5331:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (MULEU_S_PH_QBL_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12090        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULEU_S_PH_QBL_MM,
12091        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12092        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
12093        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
12094        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
12095        GIR_EraseFromParent, /*InsnID*/0,
12096        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12097        // GIR_Coverage, 1258,
12098        GIR_Done,
12099      // Label 791: @29152
12100      GIM_Try, /*On fail goto*//*Label 792*/ 29208, // Rule ID 1259 //
12101        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
12102        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_muleu_s_ph_qbr,
12103        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
12104        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
12105        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
12106        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
12107        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
12108        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
12109        // (intrinsic_w_chain:{ *:[v2i16] } 5332:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (MULEU_S_PH_QBR_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12110        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULEU_S_PH_QBR_MM,
12111        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12112        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
12113        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
12114        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
12115        GIR_EraseFromParent, /*InsnID*/0,
12116        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12117        // GIR_Coverage, 1259,
12118        GIR_Done,
12119      // Label 792: @29208
12120      GIM_Try, /*On fail goto*//*Label 793*/ 29264, // Rule ID 1260 //
12121        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
12122        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulq_rs_ph,
12123        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
12124        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
12125        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
12126        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
12127        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
12128        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
12129        // (intrinsic_w_chain:{ *:[v2i16] } 5333:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (MULQ_RS_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12130        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULQ_RS_PH_MM,
12131        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12132        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
12133        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
12134        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
12135        GIR_EraseFromParent, /*InsnID*/0,
12136        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12137        // GIR_Coverage, 1260,
12138        GIR_Done,
12139      // Label 793: @29264
12140      GIM_Try, /*On fail goto*//*Label 794*/ 29320, // Rule ID 1263 //
12141        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
12142        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precrqu_s_qb_ph,
12143        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
12144        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
12145        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
12146        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
12147        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
12148        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
12149        // (intrinsic_w_chain:{ *:[v4i8] } 5390:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (PRECRQU_S_QB_PH_MM:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12150        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECRQU_S_QB_PH_MM,
12151        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12152        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
12153        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
12154        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
12155        GIR_EraseFromParent, /*InsnID*/0,
12156        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12157        // GIR_Coverage, 1263,
12158        GIR_Done,
12159      // Label 794: @29320
12160      GIM_Try, /*On fail goto*//*Label 795*/ 29376, // Rule ID 1264 //
12161        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
12162        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precrq_rs_ph_w,
12163        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
12164        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12165        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
12166        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
12167        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
12168        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
12169        // (intrinsic_w_chain:{ *:[v2i16] } 5389:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (PRECRQ_RS_PH_W_MM:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
12170        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECRQ_RS_PH_W_MM,
12171        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12172        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
12173        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
12174        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
12175        GIR_EraseFromParent, /*InsnID*/0,
12176        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12177        // GIR_Coverage, 1264,
12178        GIR_Done,
12179      // Label 795: @29376
12180      GIM_Try, /*On fail goto*//*Label 796*/ 29432, // Rule ID 1282 //
12181        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
12182        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_pick_ph,
12183        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
12184        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
12185        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
12186        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
12187        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
12188        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
12189        // (intrinsic_w_chain:{ *:[v2i16] } 5372:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (PICK_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12190        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PICK_PH_MM,
12191        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12192        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
12193        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
12194        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
12195        GIR_EraseFromParent, /*InsnID*/0,
12196        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12197        // GIR_Coverage, 1282,
12198        GIR_Done,
12199      // Label 796: @29432
12200      GIM_Try, /*On fail goto*//*Label 797*/ 29488, // Rule ID 1283 //
12201        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
12202        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_pick_qb,
12203        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
12204        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
12205        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
12206        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
12207        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
12208        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
12209        // (intrinsic_w_chain:{ *:[v4i8] } 5373:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PICK_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
12210        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PICK_QB_MM,
12211        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12212        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
12213        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
12214        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
12215        GIR_EraseFromParent, /*InsnID*/0,
12216        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12217        // GIR_Coverage, 1283,
12218        GIR_Done,
12219      // Label 797: @29488
12220      GIM_Try, /*On fail goto*//*Label 798*/ 29544, // Rule ID 1293 //
12221        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
12222        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgu_eq_qb,
12223        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12224        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
12225        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
12226        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
12227        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
12228        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
12229        // (intrinsic_w_chain:{ *:[i32] } 5029:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPGU_EQ_QB_MM:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
12230        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGU_EQ_QB_MM,
12231        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12232        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
12233        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
12234        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
12235        GIR_EraseFromParent, /*InsnID*/0,
12236        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12237        // GIR_Coverage, 1293,
12238        GIR_Done,
12239      // Label 798: @29544
12240      GIM_Try, /*On fail goto*//*Label 799*/ 29600, // Rule ID 1294 //
12241        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
12242        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgu_lt_qb,
12243        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12244        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
12245        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
12246        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
12247        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
12248        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
12249        // (intrinsic_w_chain:{ *:[i32] } 5031:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPGU_LT_QB_MM:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
12250        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGU_LT_QB_MM,
12251        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12252        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
12253        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
12254        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
12255        GIR_EraseFromParent, /*InsnID*/0,
12256        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12257        // GIR_Coverage, 1294,
12258        GIR_Done,
12259      // Label 799: @29600
12260      GIM_Try, /*On fail goto*//*Label 800*/ 29656, // Rule ID 1295 //
12261        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
12262        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgu_le_qb,
12263        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12264        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
12265        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
12266        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
12267        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
12268        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
12269        // (intrinsic_w_chain:{ *:[i32] } 5030:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPGU_LE_QB_MM:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
12270        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGU_LE_QB_MM,
12271        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12272        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
12273        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
12274        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
12275        GIR_EraseFromParent, /*InsnID*/0,
12276        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12277        // GIR_Coverage, 1295,
12278        GIR_Done,
12279      // Label 800: @29656
12280      GIM_Try, /*On fail goto*//*Label 801*/ 29712, // Rule ID 1304 //
12281        GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
12282        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addu_ph,
12283        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
12284        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
12285        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
12286        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
12287        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
12288        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
12289        // (intrinsic_w_chain:{ *:[v2i16] } 4881:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (ADDU_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12290        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDU_PH_MMR2,
12291        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12292        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
12293        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
12294        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
12295        GIR_EraseFromParent, /*InsnID*/0,
12296        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12297        // GIR_Coverage, 1304,
12298        GIR_Done,
12299      // Label 801: @29712
12300      GIM_Try, /*On fail goto*//*Label 802*/ 29768, // Rule ID 1305 //
12301        GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
12302        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addu_s_ph,
12303        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
12304        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
12305        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
12306        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
12307        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
12308        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
12309        // (intrinsic_w_chain:{ *:[v2i16] } 4883:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (ADDU_S_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12310        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDU_S_PH_MMR2,
12311        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12312        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
12313        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
12314        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
12315        GIR_EraseFromParent, /*InsnID*/0,
12316        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12317        // GIR_Coverage, 1305,
12318        GIR_Done,
12319      // Label 802: @29768
12320      GIM_Try, /*On fail goto*//*Label 803*/ 29824, // Rule ID 1316 //
12321        GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
12322        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgdu_eq_qb,
12323        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12324        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
12325        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
12326        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
12327        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
12328        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
12329        // (intrinsic_w_chain:{ *:[i32] } 5026:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPGDU_EQ_QB_MMR2:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
12330        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGDU_EQ_QB_MMR2,
12331        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12332        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
12333        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
12334        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
12335        GIR_EraseFromParent, /*InsnID*/0,
12336        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12337        // GIR_Coverage, 1316,
12338        GIR_Done,
12339      // Label 803: @29824
12340      GIM_Try, /*On fail goto*//*Label 804*/ 29880, // Rule ID 1317 //
12341        GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
12342        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgdu_lt_qb,
12343        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12344        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
12345        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
12346        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
12347        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
12348        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
12349        // (intrinsic_w_chain:{ *:[i32] } 5028:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPGDU_LT_QB_MMR2:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
12350        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGDU_LT_QB_MMR2,
12351        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12352        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
12353        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
12354        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
12355        GIR_EraseFromParent, /*InsnID*/0,
12356        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12357        // GIR_Coverage, 1317,
12358        GIR_Done,
12359      // Label 804: @29880
12360      GIM_Try, /*On fail goto*//*Label 805*/ 29936, // Rule ID 1318 //
12361        GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
12362        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgdu_le_qb,
12363        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12364        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
12365        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
12366        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
12367        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
12368        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
12369        // (intrinsic_w_chain:{ *:[i32] } 5027:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPGDU_LE_QB_MMR2:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
12370        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGDU_LE_QB_MMR2,
12371        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12372        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
12373        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
12374        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
12375        GIR_EraseFromParent, /*InsnID*/0,
12376        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12377        // GIR_Coverage, 1318,
12378        GIR_Done,
12379      // Label 805: @29936
12380      GIM_Try, /*On fail goto*//*Label 806*/ 29992, // Rule ID 1324 //
12381        GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
12382        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subu_ph,
12383        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
12384        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
12385        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
12386        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
12387        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
12388        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
12389        // (intrinsic_w_chain:{ *:[v2i16] } 5504:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (SUBU_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12390        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBU_PH_MMR2,
12391        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12392        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
12393        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
12394        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
12395        GIR_EraseFromParent, /*InsnID*/0,
12396        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12397        // GIR_Coverage, 1324,
12398        GIR_Done,
12399      // Label 806: @29992
12400      GIM_Try, /*On fail goto*//*Label 807*/ 30048, // Rule ID 1325 //
12401        GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
12402        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subu_s_ph,
12403        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
12404        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
12405        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
12406        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
12407        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
12408        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
12409        // (intrinsic_w_chain:{ *:[v2i16] } 5506:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (SUBU_S_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12410        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBU_S_PH_MMR2,
12411        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12412        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
12413        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
12414        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
12415        GIR_EraseFromParent, /*InsnID*/0,
12416        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12417        // GIR_Coverage, 1325,
12418        GIR_Done,
12419      // Label 807: @30048
12420      GIM_Try, /*On fail goto*//*Label 808*/ 30104, // Rule ID 1332 //
12421        GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
12422        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mul_s_ph,
12423        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
12424        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
12425        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
12426        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
12427        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
12428        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
12429        // (intrinsic_w_chain:{ *:[v2i16] } 5328:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (MUL_S_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12430        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MUL_S_PH_MMR2,
12431        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12432        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
12433        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
12434        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
12435        GIR_EraseFromParent, /*InsnID*/0,
12436        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12437        // GIR_Coverage, 1332,
12438        GIR_Done,
12439      // Label 808: @30104
12440      GIM_Try, /*On fail goto*//*Label 809*/ 30160, // Rule ID 1333 //
12441        GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
12442        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulq_rs_w,
12443        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12444        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12445        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
12446        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
12447        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
12448        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
12449        // (intrinsic_w_chain:{ *:[i32] } 5334:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MULQ_RS_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
12450        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULQ_RS_W_MMR2,
12451        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12452        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
12453        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
12454        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
12455        GIR_EraseFromParent, /*InsnID*/0,
12456        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12457        // GIR_Coverage, 1333,
12458        GIR_Done,
12459      // Label 809: @30160
12460      GIM_Try, /*On fail goto*//*Label 810*/ 30216, // Rule ID 1334 //
12461        GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
12462        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulq_s_ph,
12463        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
12464        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
12465        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
12466        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
12467        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
12468        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
12469        // (intrinsic_w_chain:{ *:[v2i16] } 5335:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (MULQ_S_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12470        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULQ_S_PH_MMR2,
12471        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12472        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
12473        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
12474        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
12475        GIR_EraseFromParent, /*InsnID*/0,
12476        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12477        // GIR_Coverage, 1334,
12478        GIR_Done,
12479      // Label 810: @30216
12480      GIM_Try, /*On fail goto*//*Label 811*/ 30272, // Rule ID 1335 //
12481        GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
12482        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulq_s_w,
12483        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12484        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12485        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
12486        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
12487        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
12488        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
12489        // (intrinsic_w_chain:{ *:[i32] } 5336:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MULQ_S_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
12490        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULQ_S_W_MMR2,
12491        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12492        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
12493        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
12494        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
12495        GIR_EraseFromParent, /*InsnID*/0,
12496        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12497        // GIR_Coverage, 1335,
12498        GIR_Done,
12499      // Label 811: @30272
12500      GIM_Try, /*On fail goto*//*Label 812*/ 30328, // Rule ID 1336 //
12501        GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
12502        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precr_qb_ph,
12503        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
12504        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
12505        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
12506        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
12507        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
12508        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
12509        // (intrinsic_w_chain:{ *:[v4i8] } 5384:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (PRECR_QB_PH_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12510        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECR_QB_PH_MMR2,
12511        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12512        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
12513        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
12514        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
12515        GIR_EraseFromParent, /*InsnID*/0,
12516        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12517        // GIR_Coverage, 1336,
12518        GIR_Done,
12519      // Label 812: @30328
12520      GIM_Try, /*On fail goto*//*Label 813*/ 30376, // Rule ID 1885 //
12521        GIM_CheckFeatures, GIFBS_HasDSPR2,
12522        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mul_ph,
12523        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
12524        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
12525        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
12526        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
12527        // (intrinsic_w_chain:{ *:[v2i16] } 5325:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)  =>  (MUL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
12528        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MUL_PH,
12529        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12530        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
12531        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
12532        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
12533        GIR_EraseFromParent, /*InsnID*/0,
12534        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12535        // GIR_Coverage, 1885,
12536        GIR_Done,
12537      // Label 813: @30376
12538      GIM_Try, /*On fail goto*//*Label 814*/ 30424, // Rule ID 1891 //
12539        GIM_CheckFeatures, GIFBS_HasDSP,
12540        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addsc,
12541        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12542        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12543        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
12544        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
12545        // (intrinsic_w_chain:{ *:[i32] } 4880:{ *:[iPTR] }, i32:{ *:[i32] }:$a, i32:{ *:[i32] }:$b)  =>  (ADDSC:{ *:[i32] } i32:{ *:[i32] }:$a, i32:{ *:[i32] }:$b)
12546        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDSC,
12547        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12548        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
12549        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
12550        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
12551        GIR_EraseFromParent, /*InsnID*/0,
12552        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12553        // GIR_Coverage, 1891,
12554        GIR_Done,
12555      // Label 814: @30424
12556      GIM_Try, /*On fail goto*//*Label 815*/ 30472, // Rule ID 1893 //
12557        GIM_CheckFeatures, GIFBS_HasDSP,
12558        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addwc,
12559        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12560        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12561        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
12562        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
12563        // (intrinsic_w_chain:{ *:[i32] } 4895:{ *:[iPTR] }, i32:{ *:[i32] }:$a, i32:{ *:[i32] }:$b)  =>  (ADDWC:{ *:[i32] } i32:{ *:[i32] }:$a, i32:{ *:[i32] }:$b)
12564        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDWC,
12565        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12566        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
12567        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
12568        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
12569        GIR_EraseFromParent, /*InsnID*/0,
12570        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12571        // GIR_Coverage, 1893,
12572        GIR_Done,
12573      // Label 815: @30472
12574      GIM_Reject,
12575    // Label 744: @30473
12576    GIM_Reject,
12577    // Label 18: @30474
12578    GIM_Try, /*On fail goto*//*Label 816*/ 30539, // Rule ID 1566 //
12579      GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit,
12580      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
12581      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
12582      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
12583      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
12584      // (anyext:{ *:[i64] } GPR32:{ *:[i32] }:$src)  =>  (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$src, sub_32:{ *:[i32] })
12585      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
12586      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
12587      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
12588      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
12589      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG,
12590      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12591      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
12592      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12593      GIR_AddImm, /*InsnID*/0, /*Imm*/1,
12594      GIR_EraseFromParent, /*InsnID*/0,
12595      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::GPR64RegClassID,
12596      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, Mips::GPR64RegClassID,
12597      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, Mips::GPR32RegClassID,
12598      // GIR_Coverage, 1566,
12599      GIR_Done,
12600    // Label 816: @30539
12601    GIM_Reject,
12602    // Label 19: @30540
12603    GIM_Try, /*On fail goto*//*Label 817*/ 30602, // Rule ID 1561 //
12604      GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit,
12605      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12606      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
12607      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
12608      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
12609      // (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$src)  =>  (SLL:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$src, sub_32:{ *:[i32] }), 0:{ *:[i32] })
12610      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
12611      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
12612      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
12613      GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/1, // src
12614      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, Mips::DSPRRegClassID,
12615      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, Mips::GPR64RegClassID,
12616      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLL,
12617      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12618      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
12619      GIR_AddImm, /*InsnID*/0, /*Imm*/0,
12620      GIR_EraseFromParent, /*InsnID*/0,
12621      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12622      // GIR_Coverage, 1561,
12623      GIR_Done,
12624    // Label 817: @30602
12625    GIM_Reject,
12626    // Label 20: @30603
12627    GIM_Try, /*On fail goto*//*Label 818*/ 30662,
12628      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12629      GIM_Try, /*On fail goto*//*Label 819*/ 30635, // Rule ID 2116 //
12630        GIM_CheckFeatures, GIFBS_InMicroMips,
12631        GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIPFP_I64_Predicate_immLi16,
12632        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
12633        // MIs[0] Operand 1
12634        // No operand predicates
12635        // (imm:{ *:[i32] })<<P:Predicate_immLi16>>:$imm  =>  (LI16_MM:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_immLi16>>:$imm)
12636        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LI16_MM,
12637        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12638        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
12639        GIR_EraseFromParent, /*InsnID*/0,
12640        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12641        // GIR_Coverage, 2116,
12642        GIR_Done,
12643      // Label 819: @30635
12644      GIM_Try, /*On fail goto*//*Label 820*/ 30661, // Rule ID 1809 //
12645        GIM_CheckFeatures, GIFBS_InMips16Mode,
12646        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
12647        // MIs[0] Operand 1
12648        // No operand predicates
12649        // (imm:{ *:[i32] }):$imm  =>  (LwConstant32:{ *:[i32] } (imm:{ *:[i32] }):$imm, -1:{ *:[i32] })
12650        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LwConstant32,
12651        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rx
12652        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
12653        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
12654        GIR_EraseFromParent, /*InsnID*/0,
12655        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12656        // GIR_Coverage, 1809,
12657        GIR_Done,
12658      // Label 820: @30661
12659      GIM_Reject,
12660    // Label 818: @30662
12661    GIM_Reject,
12662    // Label 21: @30663
12663    GIM_Try, /*On fail goto*//*Label 821*/ 31920,
12664      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
12665      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
12666      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
12667      GIM_Try, /*On fail goto*//*Label 822*/ 30776, // Rule ID 1600 //
12668        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
12669        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ASHR,
12670        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
12671        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
12672        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
12673        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
12674        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
12675        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
12676        // MIs[2] Operand 1
12677        // No operand predicates
12678        GIM_CheckIsSafeToFold, /*InsnID*/1,
12679        GIM_CheckIsSafeToFold, /*InsnID*/2,
12680        // (sext:{ *:[i64] } (sra:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm5))  =>  (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SRA:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm5), sub_32:{ *:[i32] })
12681        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
12682        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
12683        GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SRA,
12684        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
12685        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
12686        GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm5
12687        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
12688        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
12689        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
12690        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
12691        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG,
12692        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12693        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
12694        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
12695        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
12696        GIR_EraseFromParent, /*InsnID*/0,
12697        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::GPR64RegClassID,
12698        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, Mips::GPR64RegClassID,
12699        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, Mips::GPR32RegClassID,
12700        // GIR_Coverage, 1600,
12701        GIR_Done,
12702      // Label 822: @30776
12703      GIM_Try, /*On fail goto*//*Label 823*/ 30875, // Rule ID 1598 //
12704        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
12705        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LSHR,
12706        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
12707        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
12708        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
12709        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
12710        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
12711        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
12712        // MIs[2] Operand 1
12713        // No operand predicates
12714        GIM_CheckIsSafeToFold, /*InsnID*/1,
12715        GIM_CheckIsSafeToFold, /*InsnID*/2,
12716        // (sext:{ *:[i64] } (srl:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm5))  =>  (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SRL:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm5), sub_32:{ *:[i32] })
12717        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
12718        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
12719        GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SRL,
12720        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
12721        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
12722        GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm5
12723        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
12724        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
12725        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
12726        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
12727        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG,
12728        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12729        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
12730        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
12731        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
12732        GIR_EraseFromParent, /*InsnID*/0,
12733        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::GPR64RegClassID,
12734        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, Mips::GPR64RegClassID,
12735        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, Mips::GPR32RegClassID,
12736        // GIR_Coverage, 1598,
12737        GIR_Done,
12738      // Label 823: @30875
12739      GIM_Try, /*On fail goto*//*Label 824*/ 30974, // Rule ID 1596 //
12740        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
12741        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
12742        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
12743        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
12744        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
12745        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
12746        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
12747        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
12748        // MIs[2] Operand 1
12749        // No operand predicates
12750        GIM_CheckIsSafeToFold, /*InsnID*/1,
12751        GIM_CheckIsSafeToFold, /*InsnID*/2,
12752        // (sext:{ *:[i64] } (shl:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm5))  =>  (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SLL:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm5), sub_32:{ *:[i32] })
12753        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
12754        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
12755        GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SLL,
12756        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
12757        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
12758        GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm5
12759        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
12760        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
12761        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
12762        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
12763        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG,
12764        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12765        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
12766        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
12767        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
12768        GIR_EraseFromParent, /*InsnID*/0,
12769        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::GPR64RegClassID,
12770        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, Mips::GPR64RegClassID,
12771        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, Mips::GPR32RegClassID,
12772        // GIR_Coverage, 1596,
12773        GIR_Done,
12774      // Label 824: @30974
12775      GIM_Try, /*On fail goto*//*Label 825*/ 31066, // Rule ID 1591 //
12776        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
12777        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
12778        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
12779        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
12780        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
12781        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
12782        GIM_CheckIsSafeToFold, /*InsnID*/1,
12783        // (sext:{ *:[i64] } (add:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2))  =>  (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ADDu:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
12784        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
12785        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
12786        GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::ADDu,
12787        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
12788        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
12789        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
12790        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
12791        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
12792        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
12793        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
12794        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG,
12795        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12796        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
12797        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
12798        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
12799        GIR_EraseFromParent, /*InsnID*/0,
12800        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::GPR64RegClassID,
12801        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, Mips::GPR64RegClassID,
12802        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, Mips::GPR32RegClassID,
12803        // GIR_Coverage, 1591,
12804        GIR_Done,
12805      // Label 825: @31066
12806      GIM_Try, /*On fail goto*//*Label 826*/ 31158, // Rule ID 1601 //
12807        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
12808        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ASHR,
12809        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
12810        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
12811        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
12812        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
12813        GIM_CheckIsSafeToFold, /*InsnID*/1,
12814        // (sext:{ *:[i64] } (sra:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2))  =>  (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SRAV:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
12815        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
12816        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
12817        GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SRAV,
12818        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
12819        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
12820        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
12821        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
12822        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
12823        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
12824        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
12825        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG,
12826        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12827        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
12828        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
12829        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
12830        GIR_EraseFromParent, /*InsnID*/0,
12831        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::GPR64RegClassID,
12832        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, Mips::GPR64RegClassID,
12833        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, Mips::GPR32RegClassID,
12834        // GIR_Coverage, 1601,
12835        GIR_Done,
12836      // Label 826: @31158
12837      GIM_Try, /*On fail goto*//*Label 827*/ 31250, // Rule ID 1599 //
12838        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
12839        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LSHR,
12840        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
12841        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
12842        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
12843        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
12844        GIM_CheckIsSafeToFold, /*InsnID*/1,
12845        // (sext:{ *:[i64] } (srl:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2))  =>  (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SRLV:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
12846        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
12847        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
12848        GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SRLV,
12849        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
12850        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
12851        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
12852        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
12853        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
12854        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
12855        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
12856        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG,
12857        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12858        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
12859        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
12860        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
12861        GIR_EraseFromParent, /*InsnID*/0,
12862        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::GPR64RegClassID,
12863        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, Mips::GPR64RegClassID,
12864        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, Mips::GPR32RegClassID,
12865        // GIR_Coverage, 1599,
12866        GIR_Done,
12867      // Label 827: @31250
12868      GIM_Try, /*On fail goto*//*Label 828*/ 31344, // Rule ID 1776 //
12869        GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc,
12870        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
12871        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
12872        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
12873        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
12874        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
12875        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
12876        GIM_CheckIsSafeToFold, /*InsnID*/1,
12877        // (sext:{ *:[i64] } (mul:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2))  =>  (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (MUL_R6:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
12878        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
12879        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
12880        GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::MUL_R6,
12881        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
12882        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
12883        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
12884        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
12885        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
12886        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
12887        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
12888        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG,
12889        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12890        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
12891        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
12892        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
12893        GIR_EraseFromParent, /*InsnID*/0,
12894        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::GPR64RegClassID,
12895        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, Mips::GPR64RegClassID,
12896        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, Mips::GPR32RegClassID,
12897        // GIR_Coverage, 1776,
12898        GIR_Done,
12899      // Label 828: @31344
12900      GIM_Try, /*On fail goto*//*Label 829*/ 31438, // Rule ID 1777 //
12901        GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc,
12902        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
12903        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SDIV,
12904        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
12905        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
12906        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
12907        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
12908        GIM_CheckIsSafeToFold, /*InsnID*/1,
12909        // (sext:{ *:[i64] } (sdiv:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2))  =>  (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (DIV:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
12910        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
12911        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
12912        GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::DIV,
12913        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
12914        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
12915        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
12916        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
12917        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
12918        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
12919        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
12920        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG,
12921        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12922        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
12923        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
12924        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
12925        GIR_EraseFromParent, /*InsnID*/0,
12926        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::GPR64RegClassID,
12927        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, Mips::GPR64RegClassID,
12928        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, Mips::GPR32RegClassID,
12929        // GIR_Coverage, 1777,
12930        GIR_Done,
12931      // Label 829: @31438
12932      GIM_Try, /*On fail goto*//*Label 830*/ 31530, // Rule ID 1597 //
12933        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
12934        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
12935        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
12936        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
12937        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
12938        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
12939        GIM_CheckIsSafeToFold, /*InsnID*/1,
12940        // (sext:{ *:[i64] } (shl:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2))  =>  (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SLLV:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
12941        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
12942        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
12943        GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SLLV,
12944        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
12945        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
12946        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
12947        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
12948        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
12949        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
12950        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
12951        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG,
12952        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12953        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
12954        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
12955        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
12956        GIR_EraseFromParent, /*InsnID*/0,
12957        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::GPR64RegClassID,
12958        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, Mips::GPR64RegClassID,
12959        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, Mips::GPR32RegClassID,
12960        // GIR_Coverage, 1597,
12961        GIR_Done,
12962      // Label 830: @31530
12963      GIM_Try, /*On fail goto*//*Label 831*/ 31624, // Rule ID 1779 //
12964        GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc,
12965        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
12966        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SREM,
12967        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
12968        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
12969        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
12970        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
12971        GIM_CheckIsSafeToFold, /*InsnID*/1,
12972        // (sext:{ *:[i64] } (srem:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2))  =>  (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (MOD:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
12973        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
12974        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
12975        GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::MOD,
12976        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
12977        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
12978        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
12979        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
12980        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
12981        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
12982        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
12983        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG,
12984        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12985        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
12986        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
12987        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
12988        GIR_EraseFromParent, /*InsnID*/0,
12989        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::GPR64RegClassID,
12990        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, Mips::GPR64RegClassID,
12991        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, Mips::GPR32RegClassID,
12992        // GIR_Coverage, 1779,
12993        GIR_Done,
12994      // Label 831: @31624
12995      GIM_Try, /*On fail goto*//*Label 832*/ 31716, // Rule ID 1592 //
12996        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
12997        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB,
12998        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
12999        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
13000        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
13001        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
13002        GIM_CheckIsSafeToFold, /*InsnID*/1,
13003        // (sext:{ *:[i64] } (sub:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2))  =>  (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SUBu:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
13004        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
13005        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
13006        GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SUBu,
13007        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
13008        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
13009        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
13010        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
13011        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
13012        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
13013        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
13014        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG,
13015        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
13016        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
13017        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
13018        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
13019        GIR_EraseFromParent, /*InsnID*/0,
13020        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::GPR64RegClassID,
13021        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, Mips::GPR64RegClassID,
13022        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, Mips::GPR32RegClassID,
13023        // GIR_Coverage, 1592,
13024        GIR_Done,
13025      // Label 832: @31716
13026      GIM_Try, /*On fail goto*//*Label 833*/ 31810, // Rule ID 1778 //
13027        GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc,
13028        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
13029        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_UDIV,
13030        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
13031        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
13032        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
13033        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
13034        GIM_CheckIsSafeToFold, /*InsnID*/1,
13035        // (sext:{ *:[i64] } (udiv:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2))  =>  (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (DIVU:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
13036        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
13037        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
13038        GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::DIVU,
13039        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
13040        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
13041        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
13042        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
13043        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
13044        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
13045        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
13046        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG,
13047        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
13048        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
13049        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
13050        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
13051        GIR_EraseFromParent, /*InsnID*/0,
13052        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::GPR64RegClassID,
13053        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, Mips::GPR64RegClassID,
13054        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, Mips::GPR32RegClassID,
13055        // GIR_Coverage, 1778,
13056        GIR_Done,
13057      // Label 833: @31810
13058      GIM_Try, /*On fail goto*//*Label 834*/ 31904, // Rule ID 1780 //
13059        GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc,
13060        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
13061        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_UREM,
13062        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
13063        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
13064        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
13065        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
13066        GIM_CheckIsSafeToFold, /*InsnID*/1,
13067        // (sext:{ *:[i64] } (urem:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2))  =>  (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (MODU:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
13068        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
13069        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
13070        GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::MODU,
13071        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
13072        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
13073        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
13074        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
13075        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
13076        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
13077        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
13078        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG,
13079        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
13080        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
13081        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
13082        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
13083        GIR_EraseFromParent, /*InsnID*/0,
13084        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::GPR64RegClassID,
13085        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, Mips::GPR64RegClassID,
13086        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, Mips::GPR32RegClassID,
13087        // GIR_Coverage, 1780,
13088        GIR_Done,
13089      // Label 834: @31904
13090      GIM_Try, /*On fail goto*//*Label 835*/ 31919, // Rule ID 1568 //
13091        GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit,
13092        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
13093        // (sext:{ *:[i64] } GPR32:{ *:[i32] }:$src)  =>  (SLL64_32:{ *:[i64] } GPR32:{ *:[i32] }:$src)
13094        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SLL64_32,
13095        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13096        // GIR_Coverage, 1568,
13097        GIR_Done,
13098      // Label 835: @31919
13099      GIM_Reject,
13100    // Label 821: @31920
13101    GIM_Reject,
13102    // Label 22: @31921
13103    GIM_Try, /*On fail goto*//*Label 836*/ 32114,
13104      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
13105      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
13106      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
13107      GIM_Try, /*On fail goto*//*Label 837*/ 31988, // Rule ID 268 //
13108        GIM_CheckFeatures, GIFBS_HasCnMips,
13109        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
13110        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
13111        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
13112        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
13113        // MIs[1] Operand 1
13114        GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
13115        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
13116        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
13117        GIM_CheckIsSafeToFold, /*InsnID*/1,
13118        // (zext:{ *:[i64] } (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, SETEQ:{ *:[Other] }))  =>  (SEQ:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
13119        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SEQ,
13120        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
13121        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
13122        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
13123        GIR_EraseFromParent, /*InsnID*/0,
13124        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13125        // GIR_Coverage, 268,
13126        GIR_Done,
13127      // Label 837: @31988
13128      GIM_Try, /*On fail goto*//*Label 838*/ 32041, // Rule ID 270 //
13129        GIM_CheckFeatures, GIFBS_HasCnMips,
13130        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
13131        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
13132        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
13133        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
13134        // MIs[1] Operand 1
13135        GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
13136        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
13137        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
13138        GIM_CheckIsSafeToFold, /*InsnID*/1,
13139        // (zext:{ *:[i64] } (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, SETNE:{ *:[Other] }))  =>  (SNE:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
13140        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SNE,
13141        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
13142        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
13143        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
13144        GIR_EraseFromParent, /*InsnID*/0,
13145        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13146        // GIR_Coverage, 270,
13147        GIR_Done,
13148      // Label 838: @32041
13149      GIM_Try, /*On fail goto*//*Label 839*/ 32113,
13150        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
13151        GIM_Try, /*On fail goto*//*Label 840*/ 32086, // Rule ID 1567 //
13152          GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit,
13153          // (zext:{ *:[i64] } GPR32:{ *:[i32] }:$src)  =>  (DSRL:{ *:[i64] } (DSLL64_32:{ *:[i64] } GPR32:{ *:[i32] }:$src), 32:{ *:[i32] })
13154          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
13155          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::DSLL64_32,
13156          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
13157          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
13158          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
13159          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSRL,
13160          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
13161          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
13162          GIR_AddImm, /*InsnID*/0, /*Imm*/32,
13163          GIR_EraseFromParent, /*InsnID*/0,
13164          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13165          // GIR_Coverage, 1567,
13166          GIR_Done,
13167        // Label 840: @32086
13168        GIM_Try, /*On fail goto*//*Label 841*/ 32112, // Rule ID 1569 //
13169          GIM_CheckFeatures, GIFBS_HasMips64r2_HasStdEnc_IsGP64bit_NotInMicroMips,
13170          // (zext:{ *:[i64] } GPR32:{ *:[i32] }:$src)  =>  (DEXT64_32:{ *:[i64] } GPR32:{ *:[i32] }:$src, 0:{ *:[i32] }, 32:{ *:[i32] })
13171          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DEXT64_32,
13172          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
13173          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13174          GIR_AddImm, /*InsnID*/0, /*Imm*/0,
13175          GIR_AddImm, /*InsnID*/0, /*Imm*/32,
13176          GIR_EraseFromParent, /*InsnID*/0,
13177          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13178          // GIR_Coverage, 1569,
13179          GIR_Done,
13180        // Label 841: @32112
13181        GIM_Reject,
13182      // Label 839: @32113
13183      GIM_Reject,
13184    // Label 836: @32114
13185    GIM_Reject,
13186    // Label 23: @32115
13187    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 848*/ 33867,
13188    /*GILLT_s32*//*Label 842*/ 32129,
13189    /*GILLT_s64*//*Label 843*/ 32382, 0,
13190    /*GILLT_v2s64*//*Label 844*/ 32516, 0,
13191    /*GILLT_v4s32*//*Label 845*/ 32548,
13192    /*GILLT_v8s16*//*Label 846*/ 32817,
13193    /*GILLT_v16s8*//*Label 847*/ 33214,
13194    // Label 842: @32129
13195    GIM_Try, /*On fail goto*//*Label 849*/ 32381,
13196      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
13197      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
13198      GIM_Try, /*On fail goto*//*Label 850*/ 32182, // Rule ID 55 //
13199        GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
13200        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
13201        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
13202        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
13203        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
13204        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
13205        // MIs[1] Operand 1
13206        // No operand predicates
13207        GIM_CheckIsSafeToFold, /*InsnID*/1,
13208        // (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shamt)  =>  (SLL:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$shamt)
13209        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLL,
13210        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
13211        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt
13212        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
13213        GIR_EraseFromParent, /*InsnID*/0,
13214        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13215        // GIR_Coverage, 55,
13216        GIR_Done,
13217      // Label 850: @32182
13218      GIM_Try, /*On fail goto*//*Label 851*/ 32225, // Rule ID 1791 //
13219        GIM_CheckFeatures, GIFBS_InMips16Mode,
13220        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
13221        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
13222        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
13223        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
13224        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
13225        // MIs[1] Operand 1
13226        // No operand predicates
13227        GIM_CheckIsSafeToFold, /*InsnID*/1,
13228        // (shl:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)  =>  (SllX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
13229        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SllX16,
13230        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rx
13231        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in
13232        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
13233        GIR_EraseFromParent, /*InsnID*/0,
13234        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13235        // GIR_Coverage, 1791,
13236        GIR_Done,
13237      // Label 851: @32225
13238      GIM_Try, /*On fail goto*//*Label 852*/ 32268, // Rule ID 2128 //
13239        GIM_CheckFeatures, GIFBS_InMicroMips,
13240        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
13241        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
13242        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
13243        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
13244        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt2Shift,
13245        // MIs[1] Operand 1
13246        // No operand predicates
13247        GIM_CheckIsSafeToFold, /*InsnID*/1,
13248        // (shl:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt2Shift>>:$imm)  =>  (SLL16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt2Shift>>:$imm)
13249        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLL16_MM,
13250        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
13251        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13252        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
13253        GIR_EraseFromParent, /*InsnID*/0,
13254        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13255        // GIR_Coverage, 2128,
13256        GIR_Done,
13257      // Label 852: @32268
13258      GIM_Try, /*On fail goto*//*Label 853*/ 32311, // Rule ID 2129 //
13259        GIM_CheckFeatures, GIFBS_InMicroMips,
13260        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
13261        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
13262        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
13263        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
13264        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
13265        // MIs[1] Operand 1
13266        // No operand predicates
13267        GIM_CheckIsSafeToFold, /*InsnID*/1,
13268        // (shl:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)  =>  (SLL_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
13269        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLL_MM,
13270        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
13271        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13272        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
13273        GIR_EraseFromParent, /*InsnID*/0,
13274        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13275        // GIR_Coverage, 2129,
13276        GIR_Done,
13277      // Label 853: @32311
13278      GIM_Try, /*On fail goto*//*Label 854*/ 32334, // Rule ID 58 //
13279        GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
13280        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
13281        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
13282        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
13283        // (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)  =>  (SLLV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
13284        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SLLV,
13285        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13286        // GIR_Coverage, 58,
13287        GIR_Done,
13288      // Label 854: @32334
13289      GIM_Try, /*On fail goto*//*Label 855*/ 32357, // Rule ID 1794 //
13290        GIM_CheckFeatures, GIFBS_InMips16Mode,
13291        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
13292        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
13293        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
13294        // (shl:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra)  =>  (SllvRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra)
13295        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SllvRxRy16,
13296        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13297        // GIR_Coverage, 1794,
13298        GIR_Done,
13299      // Label 855: @32357
13300      GIM_Try, /*On fail goto*//*Label 856*/ 32380, // Rule ID 2130 //
13301        GIM_CheckFeatures, GIFBS_InMicroMips,
13302        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
13303        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
13304        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
13305        // (shl:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs)  =>  (SLLV_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs)
13306        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SLLV_MM,
13307        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13308        // GIR_Coverage, 2130,
13309        GIR_Done,
13310      // Label 856: @32380
13311      GIM_Reject,
13312    // Label 849: @32381
13313    GIM_Reject,
13314    // Label 843: @32382
13315    GIM_Try, /*On fail goto*//*Label 857*/ 32515,
13316      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
13317      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
13318      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
13319      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
13320      GIM_Try, /*On fail goto*//*Label 858*/ 32435, // Rule ID 204 //
13321        GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_NotInMicroMips,
13322        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
13323        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
13324        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt6,
13325        // MIs[1] Operand 1
13326        // No operand predicates
13327        GIM_CheckIsSafeToFold, /*InsnID*/1,
13328        // (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$shamt)  =>  (DSLL:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$shamt)
13329        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSLL,
13330        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
13331        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt
13332        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
13333        GIR_EraseFromParent, /*InsnID*/0,
13334        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13335        // GIR_Coverage, 204,
13336        GIR_Done,
13337      // Label 858: @32435
13338      GIM_Try, /*On fail goto*//*Label 859*/ 32499, // Rule ID 1562 //
13339        GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit,
13340        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
13341        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC,
13342        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
13343        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
13344        GIM_CheckIsSafeToFold, /*InsnID*/1,
13345        // (shl:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$rs))  =>  (DSLLV:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$rs, sub_32:{ *:[i32] }))
13346        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
13347        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
13348        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
13349        GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/1, // rs
13350        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, Mips::DSPRRegClassID,
13351        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, Mips::GPR64RegClassID,
13352        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSLLV,
13353        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
13354        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt
13355        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
13356        GIR_EraseFromParent, /*InsnID*/0,
13357        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13358        // GIR_Coverage, 1562,
13359        GIR_Done,
13360      // Label 859: @32499
13361      GIM_Try, /*On fail goto*//*Label 860*/ 32514, // Rule ID 207 //
13362        GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_NotInMicroMips,
13363        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
13364        // (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)  =>  (DSLLV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
13365        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DSLLV,
13366        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13367        // GIR_Coverage, 207,
13368        GIR_Done,
13369      // Label 860: @32514
13370      GIM_Reject,
13371    // Label 857: @32515
13372    GIM_Reject,
13373    // Label 844: @32516
13374    GIM_Try, /*On fail goto*//*Label 861*/ 32547, // Rule ID 948 //
13375      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
13376      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
13377      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
13378      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
13379      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
13380      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
13381      // (shl:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (SLL_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
13382      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SLL_D,
13383      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13384      // GIR_Coverage, 948,
13385      GIR_Done,
13386    // Label 861: @32547
13387    GIM_Reject,
13388    // Label 845: @32548
13389    GIM_Try, /*On fail goto*//*Label 862*/ 32816,
13390      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
13391      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
13392      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
13393      GIM_Try, /*On fail goto*//*Label 863*/ 32679, // Rule ID 2414 //
13394        GIM_CheckFeatures, GIFBS_HasMSA,
13395        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
13396        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
13397        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
13398        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
13399        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
13400        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR,
13401        GIM_CheckNumOperands, /*MI*/2, /*Expected*/5,
13402        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
13403        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
13404        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
13405        GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
13406        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
13407        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
13408        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_immi32Cst31,
13409        // MIs[3] Operand 1
13410        // No operand predicates
13411        GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
13412        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
13413        GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_immi32Cst31,
13414        // MIs[4] Operand 1
13415        // No operand predicates
13416        GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
13417        GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT,
13418        GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIPFP_I64_Predicate_immi32Cst31,
13419        // MIs[5] Operand 1
13420        // No operand predicates
13421        GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
13422        GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT,
13423        GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIPFP_I64_Predicate_immi32Cst31,
13424        // MIs[6] Operand 1
13425        // No operand predicates
13426        GIM_CheckIsSafeToFold, /*InsnID*/1,
13427        GIM_CheckIsSafeToFold, /*InsnID*/2,
13428        GIM_CheckIsSafeToFold, /*InsnID*/3,
13429        GIM_CheckIsSafeToFold, /*InsnID*/4,
13430        GIM_CheckIsSafeToFold, /*InsnID*/5,
13431        GIM_CheckIsSafeToFold, /*InsnID*/6,
13432        // (shl:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>), v4i32:{ *:[v4i32] }:$wt))  =>  (SLL_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
13433        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLL_W,
13434        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
13435        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws
13436        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
13437        GIR_EraseFromParent, /*InsnID*/0,
13438        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13439        // GIR_Coverage, 2414,
13440        GIR_Done,
13441      // Label 863: @32679
13442      GIM_Try, /*On fail goto*//*Label 864*/ 32796, // Rule ID 2031 //
13443        GIM_CheckFeatures, GIFBS_HasMSA,
13444        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
13445        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
13446        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
13447        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
13448        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
13449        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR,
13450        GIM_CheckNumOperands, /*MI*/2, /*Expected*/5,
13451        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
13452        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
13453        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
13454        GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
13455        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
13456        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
13457        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_immi32Cst31,
13458        // MIs[3] Operand 1
13459        // No operand predicates
13460        GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
13461        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
13462        GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_immi32Cst31,
13463        // MIs[4] Operand 1
13464        // No operand predicates
13465        GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
13466        GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT,
13467        GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIPFP_I64_Predicate_immi32Cst31,
13468        // MIs[5] Operand 1
13469        // No operand predicates
13470        GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
13471        GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT,
13472        GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIPFP_I64_Predicate_immi32Cst31,
13473        // MIs[6] Operand 1
13474        // No operand predicates
13475        GIM_CheckIsSafeToFold, /*InsnID*/1,
13476        GIM_CheckIsSafeToFold, /*InsnID*/2,
13477        GIM_CheckIsSafeToFold, /*InsnID*/3,
13478        GIM_CheckIsSafeToFold, /*InsnID*/4,
13479        GIM_CheckIsSafeToFold, /*InsnID*/5,
13480        GIM_CheckIsSafeToFold, /*InsnID*/6,
13481        // (shl:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$wt, (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>)))  =>  (SLL_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
13482        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLL_W,
13483        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
13484        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws
13485        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
13486        GIR_EraseFromParent, /*InsnID*/0,
13487        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13488        // GIR_Coverage, 2031,
13489        GIR_Done,
13490      // Label 864: @32796
13491      GIM_Try, /*On fail goto*//*Label 865*/ 32815, // Rule ID 947 //
13492        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
13493        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
13494        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
13495        // (shl:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (SLL_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
13496        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SLL_W,
13497        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13498        // GIR_Coverage, 947,
13499        GIR_Done,
13500      // Label 865: @32815
13501      GIM_Reject,
13502    // Label 862: @32816
13503    GIM_Reject,
13504    // Label 846: @32817
13505    GIM_Try, /*On fail goto*//*Label 866*/ 33213,
13506      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
13507      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
13508      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
13509      GIM_Try, /*On fail goto*//*Label 867*/ 33012, // Rule ID 2413 //
13510        GIM_CheckFeatures, GIFBS_HasMSA,
13511        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
13512        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
13513        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
13514        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
13515        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
13516        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR,
13517        GIM_CheckNumOperands, /*MI*/2, /*Expected*/9,
13518        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
13519        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
13520        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
13521        GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
13522        GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
13523        GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
13524        GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
13525        GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
13526        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
13527        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
13528        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
13529        // MIs[3] Operand 1
13530        // No operand predicates
13531        GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
13532        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
13533        GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
13534        // MIs[4] Operand 1
13535        // No operand predicates
13536        GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
13537        GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT,
13538        GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
13539        // MIs[5] Operand 1
13540        // No operand predicates
13541        GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
13542        GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT,
13543        GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
13544        // MIs[6] Operand 1
13545        // No operand predicates
13546        GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
13547        GIM_CheckOpcode, /*MI*/7, TargetOpcode::G_CONSTANT,
13548        GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
13549        // MIs[7] Operand 1
13550        // No operand predicates
13551        GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
13552        GIM_CheckOpcode, /*MI*/8, TargetOpcode::G_CONSTANT,
13553        GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
13554        // MIs[8] Operand 1
13555        // No operand predicates
13556        GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
13557        GIM_CheckOpcode, /*MI*/9, TargetOpcode::G_CONSTANT,
13558        GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
13559        // MIs[9] Operand 1
13560        // No operand predicates
13561        GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
13562        GIM_CheckOpcode, /*MI*/10, TargetOpcode::G_CONSTANT,
13563        GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
13564        // MIs[10] Operand 1
13565        // No operand predicates
13566        GIM_CheckIsSafeToFold, /*InsnID*/1,
13567        GIM_CheckIsSafeToFold, /*InsnID*/2,
13568        GIM_CheckIsSafeToFold, /*InsnID*/3,
13569        GIM_CheckIsSafeToFold, /*InsnID*/4,
13570        GIM_CheckIsSafeToFold, /*InsnID*/5,
13571        GIM_CheckIsSafeToFold, /*InsnID*/6,
13572        GIM_CheckIsSafeToFold, /*InsnID*/7,
13573        GIM_CheckIsSafeToFold, /*InsnID*/8,
13574        GIM_CheckIsSafeToFold, /*InsnID*/9,
13575        GIM_CheckIsSafeToFold, /*InsnID*/10,
13576        // (shl:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>), v8i16:{ *:[v8i16] }:$wt))  =>  (SLL_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
13577        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLL_H,
13578        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
13579        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws
13580        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
13581        GIR_EraseFromParent, /*InsnID*/0,
13582        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13583        // GIR_Coverage, 2413,
13584        GIR_Done,
13585      // Label 867: @33012
13586      GIM_Try, /*On fail goto*//*Label 868*/ 33193, // Rule ID 2030 //
13587        GIM_CheckFeatures, GIFBS_HasMSA,
13588        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
13589        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
13590        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
13591        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
13592        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
13593        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR,
13594        GIM_CheckNumOperands, /*MI*/2, /*Expected*/9,
13595        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
13596        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
13597        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
13598        GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
13599        GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
13600        GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
13601        GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
13602        GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
13603        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
13604        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
13605        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
13606        // MIs[3] Operand 1
13607        // No operand predicates
13608        GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
13609        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
13610        GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
13611        // MIs[4] Operand 1
13612        // No operand predicates
13613        GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
13614        GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT,
13615        GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
13616        // MIs[5] Operand 1
13617        // No operand predicates
13618        GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
13619        GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT,
13620        GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
13621        // MIs[6] Operand 1
13622        // No operand predicates
13623        GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
13624        GIM_CheckOpcode, /*MI*/7, TargetOpcode::G_CONSTANT,
13625        GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
13626        // MIs[7] Operand 1
13627        // No operand predicates
13628        GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
13629        GIM_CheckOpcode, /*MI*/8, TargetOpcode::G_CONSTANT,
13630        GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
13631        // MIs[8] Operand 1
13632        // No operand predicates
13633        GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
13634        GIM_CheckOpcode, /*MI*/9, TargetOpcode::G_CONSTANT,
13635        GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
13636        // MIs[9] Operand 1
13637        // No operand predicates
13638        GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
13639        GIM_CheckOpcode, /*MI*/10, TargetOpcode::G_CONSTANT,
13640        GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
13641        // MIs[10] Operand 1
13642        // No operand predicates
13643        GIM_CheckIsSafeToFold, /*InsnID*/1,
13644        GIM_CheckIsSafeToFold, /*InsnID*/2,
13645        GIM_CheckIsSafeToFold, /*InsnID*/3,
13646        GIM_CheckIsSafeToFold, /*InsnID*/4,
13647        GIM_CheckIsSafeToFold, /*InsnID*/5,
13648        GIM_CheckIsSafeToFold, /*InsnID*/6,
13649        GIM_CheckIsSafeToFold, /*InsnID*/7,
13650        GIM_CheckIsSafeToFold, /*InsnID*/8,
13651        GIM_CheckIsSafeToFold, /*InsnID*/9,
13652        GIM_CheckIsSafeToFold, /*InsnID*/10,
13653        // (shl:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$wt, (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>)))  =>  (SLL_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
13654        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLL_H,
13655        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
13656        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws
13657        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
13658        GIR_EraseFromParent, /*InsnID*/0,
13659        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13660        // GIR_Coverage, 2030,
13661        GIR_Done,
13662      // Label 868: @33193
13663      GIM_Try, /*On fail goto*//*Label 869*/ 33212, // Rule ID 946 //
13664        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
13665        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
13666        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
13667        // (shl:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (SLL_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
13668        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SLL_H,
13669        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13670        // GIR_Coverage, 946,
13671        GIR_Done,
13672      // Label 869: @33212
13673      GIM_Reject,
13674    // Label 866: @33213
13675    GIM_Reject,
13676    // Label 847: @33214
13677    GIM_Try, /*On fail goto*//*Label 870*/ 33866,
13678      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
13679      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
13680      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
13681      GIM_Try, /*On fail goto*//*Label 871*/ 33537, // Rule ID 2412 //
13682        GIM_CheckFeatures, GIFBS_HasMSA,
13683        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
13684        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
13685        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
13686        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
13687        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
13688        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR,
13689        GIM_CheckNumOperands, /*MI*/2, /*Expected*/17,
13690        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
13691        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
13692        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
13693        GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
13694        GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
13695        GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
13696        GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
13697        GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
13698        GIM_CheckType, /*MI*/2, /*Op*/9, /*Type*/GILLT_s32,
13699        GIM_CheckType, /*MI*/2, /*Op*/10, /*Type*/GILLT_s32,
13700        GIM_CheckType, /*MI*/2, /*Op*/11, /*Type*/GILLT_s32,
13701        GIM_CheckType, /*MI*/2, /*Op*/12, /*Type*/GILLT_s32,
13702        GIM_CheckType, /*MI*/2, /*Op*/13, /*Type*/GILLT_s32,
13703        GIM_CheckType, /*MI*/2, /*Op*/14, /*Type*/GILLT_s32,
13704        GIM_CheckType, /*MI*/2, /*Op*/15, /*Type*/GILLT_s32,
13705        GIM_CheckType, /*MI*/2, /*Op*/16, /*Type*/GILLT_s32,
13706        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
13707        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
13708        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
13709        // MIs[3] Operand 1
13710        // No operand predicates
13711        GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
13712        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
13713        GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
13714        // MIs[4] Operand 1
13715        // No operand predicates
13716        GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
13717        GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT,
13718        GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
13719        // MIs[5] Operand 1
13720        // No operand predicates
13721        GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
13722        GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT,
13723        GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
13724        // MIs[6] Operand 1
13725        // No operand predicates
13726        GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
13727        GIM_CheckOpcode, /*MI*/7, TargetOpcode::G_CONSTANT,
13728        GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
13729        // MIs[7] Operand 1
13730        // No operand predicates
13731        GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
13732        GIM_CheckOpcode, /*MI*/8, TargetOpcode::G_CONSTANT,
13733        GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
13734        // MIs[8] Operand 1
13735        // No operand predicates
13736        GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
13737        GIM_CheckOpcode, /*MI*/9, TargetOpcode::G_CONSTANT,
13738        GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
13739        // MIs[9] Operand 1
13740        // No operand predicates
13741        GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
13742        GIM_CheckOpcode, /*MI*/10, TargetOpcode::G_CONSTANT,
13743        GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
13744        // MIs[10] Operand 1
13745        // No operand predicates
13746        GIM_RecordInsn, /*DefineMI*/11, /*MI*/2, /*OpIdx*/9, // MIs[11]
13747        GIM_CheckOpcode, /*MI*/11, TargetOpcode::G_CONSTANT,
13748        GIM_CheckI64ImmPredicate, /*MI*/11, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
13749        // MIs[11] Operand 1
13750        // No operand predicates
13751        GIM_RecordInsn, /*DefineMI*/12, /*MI*/2, /*OpIdx*/10, // MIs[12]
13752        GIM_CheckOpcode, /*MI*/12, TargetOpcode::G_CONSTANT,
13753        GIM_CheckI64ImmPredicate, /*MI*/12, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
13754        // MIs[12] Operand 1
13755        // No operand predicates
13756        GIM_RecordInsn, /*DefineMI*/13, /*MI*/2, /*OpIdx*/11, // MIs[13]
13757        GIM_CheckOpcode, /*MI*/13, TargetOpcode::G_CONSTANT,
13758        GIM_CheckI64ImmPredicate, /*MI*/13, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
13759        // MIs[13] Operand 1
13760        // No operand predicates
13761        GIM_RecordInsn, /*DefineMI*/14, /*MI*/2, /*OpIdx*/12, // MIs[14]
13762        GIM_CheckOpcode, /*MI*/14, TargetOpcode::G_CONSTANT,
13763        GIM_CheckI64ImmPredicate, /*MI*/14, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
13764        // MIs[14] Operand 1
13765        // No operand predicates
13766        GIM_RecordInsn, /*DefineMI*/15, /*MI*/2, /*OpIdx*/13, // MIs[15]
13767        GIM_CheckOpcode, /*MI*/15, TargetOpcode::G_CONSTANT,
13768        GIM_CheckI64ImmPredicate, /*MI*/15, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
13769        // MIs[15] Operand 1
13770        // No operand predicates
13771        GIM_RecordInsn, /*DefineMI*/16, /*MI*/2, /*OpIdx*/14, // MIs[16]
13772        GIM_CheckOpcode, /*MI*/16, TargetOpcode::G_CONSTANT,
13773        GIM_CheckI64ImmPredicate, /*MI*/16, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
13774        // MIs[16] Operand 1
13775        // No operand predicates
13776        GIM_RecordInsn, /*DefineMI*/17, /*MI*/2, /*OpIdx*/15, // MIs[17]
13777        GIM_CheckOpcode, /*MI*/17, TargetOpcode::G_CONSTANT,
13778        GIM_CheckI64ImmPredicate, /*MI*/17, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
13779        // MIs[17] Operand 1
13780        // No operand predicates
13781        GIM_RecordInsn, /*DefineMI*/18, /*MI*/2, /*OpIdx*/16, // MIs[18]
13782        GIM_CheckOpcode, /*MI*/18, TargetOpcode::G_CONSTANT,
13783        GIM_CheckI64ImmPredicate, /*MI*/18, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
13784        // MIs[18] Operand 1
13785        // No operand predicates
13786        GIM_CheckIsSafeToFold, /*InsnID*/1,
13787        GIM_CheckIsSafeToFold, /*InsnID*/2,
13788        GIM_CheckIsSafeToFold, /*InsnID*/3,
13789        GIM_CheckIsSafeToFold, /*InsnID*/4,
13790        GIM_CheckIsSafeToFold, /*InsnID*/5,
13791        GIM_CheckIsSafeToFold, /*InsnID*/6,
13792        GIM_CheckIsSafeToFold, /*InsnID*/7,
13793        GIM_CheckIsSafeToFold, /*InsnID*/8,
13794        GIM_CheckIsSafeToFold, /*InsnID*/9,
13795        GIM_CheckIsSafeToFold, /*InsnID*/10,
13796        GIM_CheckIsSafeToFold, /*InsnID*/11,
13797        GIM_CheckIsSafeToFold, /*InsnID*/12,
13798        GIM_CheckIsSafeToFold, /*InsnID*/13,
13799        GIM_CheckIsSafeToFold, /*InsnID*/14,
13800        GIM_CheckIsSafeToFold, /*InsnID*/15,
13801        GIM_CheckIsSafeToFold, /*InsnID*/16,
13802        GIM_CheckIsSafeToFold, /*InsnID*/17,
13803        GIM_CheckIsSafeToFold, /*InsnID*/18,
13804        // (shl:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>), v16i8:{ *:[v16i8] }:$wt))  =>  (SLL_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
13805        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLL_B,
13806        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
13807        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws
13808        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
13809        GIR_EraseFromParent, /*InsnID*/0,
13810        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13811        // GIR_Coverage, 2412,
13812        GIR_Done,
13813      // Label 871: @33537
13814      GIM_Try, /*On fail goto*//*Label 872*/ 33846, // Rule ID 2029 //
13815        GIM_CheckFeatures, GIFBS_HasMSA,
13816        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
13817        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
13818        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
13819        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
13820        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
13821        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR,
13822        GIM_CheckNumOperands, /*MI*/2, /*Expected*/17,
13823        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
13824        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
13825        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
13826        GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
13827        GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
13828        GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
13829        GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
13830        GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
13831        GIM_CheckType, /*MI*/2, /*Op*/9, /*Type*/GILLT_s32,
13832        GIM_CheckType, /*MI*/2, /*Op*/10, /*Type*/GILLT_s32,
13833        GIM_CheckType, /*MI*/2, /*Op*/11, /*Type*/GILLT_s32,
13834        GIM_CheckType, /*MI*/2, /*Op*/12, /*Type*/GILLT_s32,
13835        GIM_CheckType, /*MI*/2, /*Op*/13, /*Type*/GILLT_s32,
13836        GIM_CheckType, /*MI*/2, /*Op*/14, /*Type*/GILLT_s32,
13837        GIM_CheckType, /*MI*/2, /*Op*/15, /*Type*/GILLT_s32,
13838        GIM_CheckType, /*MI*/2, /*Op*/16, /*Type*/GILLT_s32,
13839        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
13840        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
13841        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
13842        // MIs[3] Operand 1
13843        // No operand predicates
13844        GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
13845        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
13846        GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
13847        // MIs[4] Operand 1
13848        // No operand predicates
13849        GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
13850        GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT,
13851        GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
13852        // MIs[5] Operand 1
13853        // No operand predicates
13854        GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
13855        GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT,
13856        GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
13857        // MIs[6] Operand 1
13858        // No operand predicates
13859        GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
13860        GIM_CheckOpcode, /*MI*/7, TargetOpcode::G_CONSTANT,
13861        GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
13862        // MIs[7] Operand 1
13863        // No operand predicates
13864        GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
13865        GIM_CheckOpcode, /*MI*/8, TargetOpcode::G_CONSTANT,
13866        GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
13867        // MIs[8] Operand 1
13868        // No operand predicates
13869        GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
13870        GIM_CheckOpcode, /*MI*/9, TargetOpcode::G_CONSTANT,
13871        GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
13872        // MIs[9] Operand 1
13873        // No operand predicates
13874        GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
13875        GIM_CheckOpcode, /*MI*/10, TargetOpcode::G_CONSTANT,
13876        GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
13877        // MIs[10] Operand 1
13878        // No operand predicates
13879        GIM_RecordInsn, /*DefineMI*/11, /*MI*/2, /*OpIdx*/9, // MIs[11]
13880        GIM_CheckOpcode, /*MI*/11, TargetOpcode::G_CONSTANT,
13881        GIM_CheckI64ImmPredicate, /*MI*/11, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
13882        // MIs[11] Operand 1
13883        // No operand predicates
13884        GIM_RecordInsn, /*DefineMI*/12, /*MI*/2, /*OpIdx*/10, // MIs[12]
13885        GIM_CheckOpcode, /*MI*/12, TargetOpcode::G_CONSTANT,
13886        GIM_CheckI64ImmPredicate, /*MI*/12, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
13887        // MIs[12] Operand 1
13888        // No operand predicates
13889        GIM_RecordInsn, /*DefineMI*/13, /*MI*/2, /*OpIdx*/11, // MIs[13]
13890        GIM_CheckOpcode, /*MI*/13, TargetOpcode::G_CONSTANT,
13891        GIM_CheckI64ImmPredicate, /*MI*/13, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
13892        // MIs[13] Operand 1
13893        // No operand predicates
13894        GIM_RecordInsn, /*DefineMI*/14, /*MI*/2, /*OpIdx*/12, // MIs[14]
13895        GIM_CheckOpcode, /*MI*/14, TargetOpcode::G_CONSTANT,
13896        GIM_CheckI64ImmPredicate, /*MI*/14, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
13897        // MIs[14] Operand 1
13898        // No operand predicates
13899        GIM_RecordInsn, /*DefineMI*/15, /*MI*/2, /*OpIdx*/13, // MIs[15]
13900        GIM_CheckOpcode, /*MI*/15, TargetOpcode::G_CONSTANT,
13901        GIM_CheckI64ImmPredicate, /*MI*/15, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
13902        // MIs[15] Operand 1
13903        // No operand predicates
13904        GIM_RecordInsn, /*DefineMI*/16, /*MI*/2, /*OpIdx*/14, // MIs[16]
13905        GIM_CheckOpcode, /*MI*/16, TargetOpcode::G_CONSTANT,
13906        GIM_CheckI64ImmPredicate, /*MI*/16, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
13907        // MIs[16] Operand 1
13908        // No operand predicates
13909        GIM_RecordInsn, /*DefineMI*/17, /*MI*/2, /*OpIdx*/15, // MIs[17]
13910        GIM_CheckOpcode, /*MI*/17, TargetOpcode::G_CONSTANT,
13911        GIM_CheckI64ImmPredicate, /*MI*/17, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
13912        // MIs[17] Operand 1
13913        // No operand predicates
13914        GIM_RecordInsn, /*DefineMI*/18, /*MI*/2, /*OpIdx*/16, // MIs[18]
13915        GIM_CheckOpcode, /*MI*/18, TargetOpcode::G_CONSTANT,
13916        GIM_CheckI64ImmPredicate, /*MI*/18, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
13917        // MIs[18] Operand 1
13918        // No operand predicates
13919        GIM_CheckIsSafeToFold, /*InsnID*/1,
13920        GIM_CheckIsSafeToFold, /*InsnID*/2,
13921        GIM_CheckIsSafeToFold, /*InsnID*/3,
13922        GIM_CheckIsSafeToFold, /*InsnID*/4,
13923        GIM_CheckIsSafeToFold, /*InsnID*/5,
13924        GIM_CheckIsSafeToFold, /*InsnID*/6,
13925        GIM_CheckIsSafeToFold, /*InsnID*/7,
13926        GIM_CheckIsSafeToFold, /*InsnID*/8,
13927        GIM_CheckIsSafeToFold, /*InsnID*/9,
13928        GIM_CheckIsSafeToFold, /*InsnID*/10,
13929        GIM_CheckIsSafeToFold, /*InsnID*/11,
13930        GIM_CheckIsSafeToFold, /*InsnID*/12,
13931        GIM_CheckIsSafeToFold, /*InsnID*/13,
13932        GIM_CheckIsSafeToFold, /*InsnID*/14,
13933        GIM_CheckIsSafeToFold, /*InsnID*/15,
13934        GIM_CheckIsSafeToFold, /*InsnID*/16,
13935        GIM_CheckIsSafeToFold, /*InsnID*/17,
13936        GIM_CheckIsSafeToFold, /*InsnID*/18,
13937        // (shl:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$wt, (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>)))  =>  (SLL_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
13938        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLL_B,
13939        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
13940        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws
13941        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
13942        GIR_EraseFromParent, /*InsnID*/0,
13943        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13944        // GIR_Coverage, 2029,
13945        GIR_Done,
13946      // Label 872: @33846
13947      GIM_Try, /*On fail goto*//*Label 873*/ 33865, // Rule ID 945 //
13948        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
13949        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
13950        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
13951        // (shl:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (SLL_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
13952        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SLL_B,
13953        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13954        // GIR_Coverage, 945,
13955        GIR_Done,
13956      // Label 873: @33865
13957      GIM_Reject,
13958    // Label 870: @33866
13959    GIM_Reject,
13960    // Label 848: @33867
13961    GIM_Reject,
13962    // Label 24: @33868
13963    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 880*/ 35620,
13964    /*GILLT_s32*//*Label 874*/ 33882,
13965    /*GILLT_s64*//*Label 875*/ 34135, 0,
13966    /*GILLT_v2s64*//*Label 876*/ 34269, 0,
13967    /*GILLT_v4s32*//*Label 877*/ 34301,
13968    /*GILLT_v8s16*//*Label 878*/ 34570,
13969    /*GILLT_v16s8*//*Label 879*/ 34967,
13970    // Label 874: @33882
13971    GIM_Try, /*On fail goto*//*Label 881*/ 34134,
13972      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
13973      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
13974      GIM_Try, /*On fail goto*//*Label 882*/ 33935, // Rule ID 56 //
13975        GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
13976        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
13977        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
13978        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
13979        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
13980        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
13981        // MIs[1] Operand 1
13982        // No operand predicates
13983        GIM_CheckIsSafeToFold, /*InsnID*/1,
13984        // (srl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shamt)  =>  (SRL:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$shamt)
13985        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRL,
13986        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
13987        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt
13988        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
13989        GIR_EraseFromParent, /*InsnID*/0,
13990        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13991        // GIR_Coverage, 56,
13992        GIR_Done,
13993      // Label 882: @33935
13994      GIM_Try, /*On fail goto*//*Label 883*/ 33978, // Rule ID 1792 //
13995        GIM_CheckFeatures, GIFBS_InMips16Mode,
13996        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
13997        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
13998        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
13999        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
14000        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
14001        // MIs[1] Operand 1
14002        // No operand predicates
14003        GIM_CheckIsSafeToFold, /*InsnID*/1,
14004        // (srl:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)  =>  (SrlX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
14005        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SrlX16,
14006        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rx
14007        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in
14008        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
14009        GIR_EraseFromParent, /*InsnID*/0,
14010        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14011        // GIR_Coverage, 1792,
14012        GIR_Done,
14013      // Label 883: @33978
14014      GIM_Try, /*On fail goto*//*Label 884*/ 34021, // Rule ID 2131 //
14015        GIM_CheckFeatures, GIFBS_InMicroMips,
14016        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
14017        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
14018        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
14019        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
14020        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt2Shift,
14021        // MIs[1] Operand 1
14022        // No operand predicates
14023        GIM_CheckIsSafeToFold, /*InsnID*/1,
14024        // (srl:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt2Shift>>:$imm)  =>  (SRL16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt2Shift>>:$imm)
14025        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRL16_MM,
14026        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
14027        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
14028        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
14029        GIR_EraseFromParent, /*InsnID*/0,
14030        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14031        // GIR_Coverage, 2131,
14032        GIR_Done,
14033      // Label 884: @34021
14034      GIM_Try, /*On fail goto*//*Label 885*/ 34064, // Rule ID 2132 //
14035        GIM_CheckFeatures, GIFBS_InMicroMips,
14036        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
14037        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
14038        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
14039        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
14040        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
14041        // MIs[1] Operand 1
14042        // No operand predicates
14043        GIM_CheckIsSafeToFold, /*InsnID*/1,
14044        // (srl:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)  =>  (SRL_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
14045        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRL_MM,
14046        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
14047        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
14048        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
14049        GIR_EraseFromParent, /*InsnID*/0,
14050        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14051        // GIR_Coverage, 2132,
14052        GIR_Done,
14053      // Label 885: @34064
14054      GIM_Try, /*On fail goto*//*Label 886*/ 34087, // Rule ID 59 //
14055        GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
14056        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
14057        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
14058        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
14059        // (srl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)  =>  (SRLV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
14060        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRLV,
14061        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14062        // GIR_Coverage, 59,
14063        GIR_Done,
14064      // Label 886: @34087
14065      GIM_Try, /*On fail goto*//*Label 887*/ 34110, // Rule ID 1796 //
14066        GIM_CheckFeatures, GIFBS_InMips16Mode,
14067        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
14068        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
14069        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
14070        // (srl:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra)  =>  (SrlvRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra)
14071        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SrlvRxRy16,
14072        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14073        // GIR_Coverage, 1796,
14074        GIR_Done,
14075      // Label 887: @34110
14076      GIM_Try, /*On fail goto*//*Label 888*/ 34133, // Rule ID 2133 //
14077        GIM_CheckFeatures, GIFBS_InMicroMips,
14078        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
14079        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
14080        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
14081        // (srl:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs)  =>  (SRLV_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs)
14082        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRLV_MM,
14083        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14084        // GIR_Coverage, 2133,
14085        GIR_Done,
14086      // Label 888: @34133
14087      GIM_Reject,
14088    // Label 881: @34134
14089    GIM_Reject,
14090    // Label 875: @34135
14091    GIM_Try, /*On fail goto*//*Label 889*/ 34268,
14092      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
14093      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
14094      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
14095      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
14096      GIM_Try, /*On fail goto*//*Label 890*/ 34188, // Rule ID 205 //
14097        GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_NotInMicroMips,
14098        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
14099        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
14100        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt6,
14101        // MIs[1] Operand 1
14102        // No operand predicates
14103        GIM_CheckIsSafeToFold, /*InsnID*/1,
14104        // (srl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$shamt)  =>  (DSRL:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$shamt)
14105        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSRL,
14106        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
14107        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt
14108        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
14109        GIR_EraseFromParent, /*InsnID*/0,
14110        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14111        // GIR_Coverage, 205,
14112        GIR_Done,
14113      // Label 890: @34188
14114      GIM_Try, /*On fail goto*//*Label 891*/ 34252, // Rule ID 1563 //
14115        GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit,
14116        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
14117        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC,
14118        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
14119        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
14120        GIM_CheckIsSafeToFold, /*InsnID*/1,
14121        // (srl:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$rs))  =>  (DSRLV:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$rs, sub_32:{ *:[i32] }))
14122        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
14123        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
14124        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
14125        GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/1, // rs
14126        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, Mips::DSPRRegClassID,
14127        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, Mips::GPR64RegClassID,
14128        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSRLV,
14129        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
14130        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt
14131        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
14132        GIR_EraseFromParent, /*InsnID*/0,
14133        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14134        // GIR_Coverage, 1563,
14135        GIR_Done,
14136      // Label 891: @34252
14137      GIM_Try, /*On fail goto*//*Label 892*/ 34267, // Rule ID 209 //
14138        GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_NotInMicroMips,
14139        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
14140        // (srl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)  =>  (DSRLV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
14141        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DSRLV,
14142        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14143        // GIR_Coverage, 209,
14144        GIR_Done,
14145      // Label 892: @34267
14146      GIM_Reject,
14147    // Label 889: @34268
14148    GIM_Reject,
14149    // Label 876: @34269
14150    GIM_Try, /*On fail goto*//*Label 893*/ 34300, // Rule ID 980 //
14151      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
14152      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
14153      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
14154      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
14155      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
14156      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
14157      // (srl:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (SRL_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
14158      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRL_D,
14159      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14160      // GIR_Coverage, 980,
14161      GIR_Done,
14162    // Label 893: @34300
14163    GIM_Reject,
14164    // Label 877: @34301
14165    GIM_Try, /*On fail goto*//*Label 894*/ 34569,
14166      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
14167      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
14168      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
14169      GIM_Try, /*On fail goto*//*Label 895*/ 34432, // Rule ID 2430 //
14170        GIM_CheckFeatures, GIFBS_HasMSA,
14171        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
14172        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
14173        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
14174        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
14175        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
14176        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR,
14177        GIM_CheckNumOperands, /*MI*/2, /*Expected*/5,
14178        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
14179        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
14180        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
14181        GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
14182        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
14183        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
14184        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_immi32Cst31,
14185        // MIs[3] Operand 1
14186        // No operand predicates
14187        GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
14188        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
14189        GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_immi32Cst31,
14190        // MIs[4] Operand 1
14191        // No operand predicates
14192        GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
14193        GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT,
14194        GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIPFP_I64_Predicate_immi32Cst31,
14195        // MIs[5] Operand 1
14196        // No operand predicates
14197        GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
14198        GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT,
14199        GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIPFP_I64_Predicate_immi32Cst31,
14200        // MIs[6] Operand 1
14201        // No operand predicates
14202        GIM_CheckIsSafeToFold, /*InsnID*/1,
14203        GIM_CheckIsSafeToFold, /*InsnID*/2,
14204        GIM_CheckIsSafeToFold, /*InsnID*/3,
14205        GIM_CheckIsSafeToFold, /*InsnID*/4,
14206        GIM_CheckIsSafeToFold, /*InsnID*/5,
14207        GIM_CheckIsSafeToFold, /*InsnID*/6,
14208        // (srl:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>), v4i32:{ *:[v4i32] }:$wt))  =>  (SRL_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
14209        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRL_W,
14210        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
14211        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws
14212        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
14213        GIR_EraseFromParent, /*InsnID*/0,
14214        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14215        // GIR_Coverage, 2430,
14216        GIR_Done,
14217      // Label 895: @34432
14218      GIM_Try, /*On fail goto*//*Label 896*/ 34549, // Rule ID 2039 //
14219        GIM_CheckFeatures, GIFBS_HasMSA,
14220        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
14221        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
14222        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
14223        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
14224        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
14225        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR,
14226        GIM_CheckNumOperands, /*MI*/2, /*Expected*/5,
14227        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
14228        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
14229        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
14230        GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
14231        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
14232        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
14233        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_immi32Cst31,
14234        // MIs[3] Operand 1
14235        // No operand predicates
14236        GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
14237        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
14238        GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_immi32Cst31,
14239        // MIs[4] Operand 1
14240        // No operand predicates
14241        GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
14242        GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT,
14243        GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIPFP_I64_Predicate_immi32Cst31,
14244        // MIs[5] Operand 1
14245        // No operand predicates
14246        GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
14247        GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT,
14248        GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIPFP_I64_Predicate_immi32Cst31,
14249        // MIs[6] Operand 1
14250        // No operand predicates
14251        GIM_CheckIsSafeToFold, /*InsnID*/1,
14252        GIM_CheckIsSafeToFold, /*InsnID*/2,
14253        GIM_CheckIsSafeToFold, /*InsnID*/3,
14254        GIM_CheckIsSafeToFold, /*InsnID*/4,
14255        GIM_CheckIsSafeToFold, /*InsnID*/5,
14256        GIM_CheckIsSafeToFold, /*InsnID*/6,
14257        // (srl:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$wt, (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>)))  =>  (SRL_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
14258        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRL_W,
14259        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
14260        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws
14261        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
14262        GIR_EraseFromParent, /*InsnID*/0,
14263        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14264        // GIR_Coverage, 2039,
14265        GIR_Done,
14266      // Label 896: @34549
14267      GIM_Try, /*On fail goto*//*Label 897*/ 34568, // Rule ID 979 //
14268        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
14269        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
14270        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
14271        // (srl:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (SRL_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
14272        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRL_W,
14273        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14274        // GIR_Coverage, 979,
14275        GIR_Done,
14276      // Label 897: @34568
14277      GIM_Reject,
14278    // Label 894: @34569
14279    GIM_Reject,
14280    // Label 878: @34570
14281    GIM_Try, /*On fail goto*//*Label 898*/ 34966,
14282      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
14283      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
14284      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
14285      GIM_Try, /*On fail goto*//*Label 899*/ 34765, // Rule ID 2429 //
14286        GIM_CheckFeatures, GIFBS_HasMSA,
14287        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
14288        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
14289        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
14290        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
14291        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
14292        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR,
14293        GIM_CheckNumOperands, /*MI*/2, /*Expected*/9,
14294        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
14295        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
14296        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
14297        GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
14298        GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
14299        GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
14300        GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
14301        GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
14302        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
14303        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
14304        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
14305        // MIs[3] Operand 1
14306        // No operand predicates
14307        GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
14308        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
14309        GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
14310        // MIs[4] Operand 1
14311        // No operand predicates
14312        GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
14313        GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT,
14314        GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
14315        // MIs[5] Operand 1
14316        // No operand predicates
14317        GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
14318        GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT,
14319        GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
14320        // MIs[6] Operand 1
14321        // No operand predicates
14322        GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
14323        GIM_CheckOpcode, /*MI*/7, TargetOpcode::G_CONSTANT,
14324        GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
14325        // MIs[7] Operand 1
14326        // No operand predicates
14327        GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
14328        GIM_CheckOpcode, /*MI*/8, TargetOpcode::G_CONSTANT,
14329        GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
14330        // MIs[8] Operand 1
14331        // No operand predicates
14332        GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
14333        GIM_CheckOpcode, /*MI*/9, TargetOpcode::G_CONSTANT,
14334        GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
14335        // MIs[9] Operand 1
14336        // No operand predicates
14337        GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
14338        GIM_CheckOpcode, /*MI*/10, TargetOpcode::G_CONSTANT,
14339        GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
14340        // MIs[10] Operand 1
14341        // No operand predicates
14342        GIM_CheckIsSafeToFold, /*InsnID*/1,
14343        GIM_CheckIsSafeToFold, /*InsnID*/2,
14344        GIM_CheckIsSafeToFold, /*InsnID*/3,
14345        GIM_CheckIsSafeToFold, /*InsnID*/4,
14346        GIM_CheckIsSafeToFold, /*InsnID*/5,
14347        GIM_CheckIsSafeToFold, /*InsnID*/6,
14348        GIM_CheckIsSafeToFold, /*InsnID*/7,
14349        GIM_CheckIsSafeToFold, /*InsnID*/8,
14350        GIM_CheckIsSafeToFold, /*InsnID*/9,
14351        GIM_CheckIsSafeToFold, /*InsnID*/10,
14352        // (srl:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>), v8i16:{ *:[v8i16] }:$wt))  =>  (SRL_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
14353        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRL_H,
14354        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
14355        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws
14356        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
14357        GIR_EraseFromParent, /*InsnID*/0,
14358        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14359        // GIR_Coverage, 2429,
14360        GIR_Done,
14361      // Label 899: @34765
14362      GIM_Try, /*On fail goto*//*Label 900*/ 34946, // Rule ID 2038 //
14363        GIM_CheckFeatures, GIFBS_HasMSA,
14364        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
14365        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
14366        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
14367        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
14368        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
14369        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR,
14370        GIM_CheckNumOperands, /*MI*/2, /*Expected*/9,
14371        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
14372        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
14373        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
14374        GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
14375        GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
14376        GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
14377        GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
14378        GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
14379        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
14380        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
14381        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
14382        // MIs[3] Operand 1
14383        // No operand predicates
14384        GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
14385        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
14386        GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
14387        // MIs[4] Operand 1
14388        // No operand predicates
14389        GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
14390        GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT,
14391        GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
14392        // MIs[5] Operand 1
14393        // No operand predicates
14394        GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
14395        GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT,
14396        GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
14397        // MIs[6] Operand 1
14398        // No operand predicates
14399        GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
14400        GIM_CheckOpcode, /*MI*/7, TargetOpcode::G_CONSTANT,
14401        GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
14402        // MIs[7] Operand 1
14403        // No operand predicates
14404        GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
14405        GIM_CheckOpcode, /*MI*/8, TargetOpcode::G_CONSTANT,
14406        GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
14407        // MIs[8] Operand 1
14408        // No operand predicates
14409        GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
14410        GIM_CheckOpcode, /*MI*/9, TargetOpcode::G_CONSTANT,
14411        GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
14412        // MIs[9] Operand 1
14413        // No operand predicates
14414        GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
14415        GIM_CheckOpcode, /*MI*/10, TargetOpcode::G_CONSTANT,
14416        GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
14417        // MIs[10] Operand 1
14418        // No operand predicates
14419        GIM_CheckIsSafeToFold, /*InsnID*/1,
14420        GIM_CheckIsSafeToFold, /*InsnID*/2,
14421        GIM_CheckIsSafeToFold, /*InsnID*/3,
14422        GIM_CheckIsSafeToFold, /*InsnID*/4,
14423        GIM_CheckIsSafeToFold, /*InsnID*/5,
14424        GIM_CheckIsSafeToFold, /*InsnID*/6,
14425        GIM_CheckIsSafeToFold, /*InsnID*/7,
14426        GIM_CheckIsSafeToFold, /*InsnID*/8,
14427        GIM_CheckIsSafeToFold, /*InsnID*/9,
14428        GIM_CheckIsSafeToFold, /*InsnID*/10,
14429        // (srl:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$wt, (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>)))  =>  (SRL_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
14430        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRL_H,
14431        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
14432        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws
14433        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
14434        GIR_EraseFromParent, /*InsnID*/0,
14435        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14436        // GIR_Coverage, 2038,
14437        GIR_Done,
14438      // Label 900: @34946
14439      GIM_Try, /*On fail goto*//*Label 901*/ 34965, // Rule ID 978 //
14440        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
14441        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
14442        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
14443        // (srl:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (SRL_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
14444        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRL_H,
14445        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14446        // GIR_Coverage, 978,
14447        GIR_Done,
14448      // Label 901: @34965
14449      GIM_Reject,
14450    // Label 898: @34966
14451    GIM_Reject,
14452    // Label 879: @34967
14453    GIM_Try, /*On fail goto*//*Label 902*/ 35619,
14454      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
14455      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
14456      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
14457      GIM_Try, /*On fail goto*//*Label 903*/ 35290, // Rule ID 2428 //
14458        GIM_CheckFeatures, GIFBS_HasMSA,
14459        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
14460        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
14461        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
14462        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
14463        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
14464        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR,
14465        GIM_CheckNumOperands, /*MI*/2, /*Expected*/17,
14466        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
14467        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
14468        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
14469        GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
14470        GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
14471        GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
14472        GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
14473        GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
14474        GIM_CheckType, /*MI*/2, /*Op*/9, /*Type*/GILLT_s32,
14475        GIM_CheckType, /*MI*/2, /*Op*/10, /*Type*/GILLT_s32,
14476        GIM_CheckType, /*MI*/2, /*Op*/11, /*Type*/GILLT_s32,
14477        GIM_CheckType, /*MI*/2, /*Op*/12, /*Type*/GILLT_s32,
14478        GIM_CheckType, /*MI*/2, /*Op*/13, /*Type*/GILLT_s32,
14479        GIM_CheckType, /*MI*/2, /*Op*/14, /*Type*/GILLT_s32,
14480        GIM_CheckType, /*MI*/2, /*Op*/15, /*Type*/GILLT_s32,
14481        GIM_CheckType, /*MI*/2, /*Op*/16, /*Type*/GILLT_s32,
14482        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
14483        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
14484        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
14485        // MIs[3] Operand 1
14486        // No operand predicates
14487        GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
14488        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
14489        GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
14490        // MIs[4] Operand 1
14491        // No operand predicates
14492        GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
14493        GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT,
14494        GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
14495        // MIs[5] Operand 1
14496        // No operand predicates
14497        GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
14498        GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT,
14499        GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
14500        // MIs[6] Operand 1
14501        // No operand predicates
14502        GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
14503        GIM_CheckOpcode, /*MI*/7, TargetOpcode::G_CONSTANT,
14504        GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
14505        // MIs[7] Operand 1
14506        // No operand predicates
14507        GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
14508        GIM_CheckOpcode, /*MI*/8, TargetOpcode::G_CONSTANT,
14509        GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
14510        // MIs[8] Operand 1
14511        // No operand predicates
14512        GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
14513        GIM_CheckOpcode, /*MI*/9, TargetOpcode::G_CONSTANT,
14514        GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
14515        // MIs[9] Operand 1
14516        // No operand predicates
14517        GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
14518        GIM_CheckOpcode, /*MI*/10, TargetOpcode::G_CONSTANT,
14519        GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
14520        // MIs[10] Operand 1
14521        // No operand predicates
14522        GIM_RecordInsn, /*DefineMI*/11, /*MI*/2, /*OpIdx*/9, // MIs[11]
14523        GIM_CheckOpcode, /*MI*/11, TargetOpcode::G_CONSTANT,
14524        GIM_CheckI64ImmPredicate, /*MI*/11, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
14525        // MIs[11] Operand 1
14526        // No operand predicates
14527        GIM_RecordInsn, /*DefineMI*/12, /*MI*/2, /*OpIdx*/10, // MIs[12]
14528        GIM_CheckOpcode, /*MI*/12, TargetOpcode::G_CONSTANT,
14529        GIM_CheckI64ImmPredicate, /*MI*/12, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
14530        // MIs[12] Operand 1
14531        // No operand predicates
14532        GIM_RecordInsn, /*DefineMI*/13, /*MI*/2, /*OpIdx*/11, // MIs[13]
14533        GIM_CheckOpcode, /*MI*/13, TargetOpcode::G_CONSTANT,
14534        GIM_CheckI64ImmPredicate, /*MI*/13, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
14535        // MIs[13] Operand 1
14536        // No operand predicates
14537        GIM_RecordInsn, /*DefineMI*/14, /*MI*/2, /*OpIdx*/12, // MIs[14]
14538        GIM_CheckOpcode, /*MI*/14, TargetOpcode::G_CONSTANT,
14539        GIM_CheckI64ImmPredicate, /*MI*/14, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
14540        // MIs[14] Operand 1
14541        // No operand predicates
14542        GIM_RecordInsn, /*DefineMI*/15, /*MI*/2, /*OpIdx*/13, // MIs[15]
14543        GIM_CheckOpcode, /*MI*/15, TargetOpcode::G_CONSTANT,
14544        GIM_CheckI64ImmPredicate, /*MI*/15, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
14545        // MIs[15] Operand 1
14546        // No operand predicates
14547        GIM_RecordInsn, /*DefineMI*/16, /*MI*/2, /*OpIdx*/14, // MIs[16]
14548        GIM_CheckOpcode, /*MI*/16, TargetOpcode::G_CONSTANT,
14549        GIM_CheckI64ImmPredicate, /*MI*/16, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
14550        // MIs[16] Operand 1
14551        // No operand predicates
14552        GIM_RecordInsn, /*DefineMI*/17, /*MI*/2, /*OpIdx*/15, // MIs[17]
14553        GIM_CheckOpcode, /*MI*/17, TargetOpcode::G_CONSTANT,
14554        GIM_CheckI64ImmPredicate, /*MI*/17, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
14555        // MIs[17] Operand 1
14556        // No operand predicates
14557        GIM_RecordInsn, /*DefineMI*/18, /*MI*/2, /*OpIdx*/16, // MIs[18]
14558        GIM_CheckOpcode, /*MI*/18, TargetOpcode::G_CONSTANT,
14559        GIM_CheckI64ImmPredicate, /*MI*/18, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
14560        // MIs[18] Operand 1
14561        // No operand predicates
14562        GIM_CheckIsSafeToFold, /*InsnID*/1,
14563        GIM_CheckIsSafeToFold, /*InsnID*/2,
14564        GIM_CheckIsSafeToFold, /*InsnID*/3,
14565        GIM_CheckIsSafeToFold, /*InsnID*/4,
14566        GIM_CheckIsSafeToFold, /*InsnID*/5,
14567        GIM_CheckIsSafeToFold, /*InsnID*/6,
14568        GIM_CheckIsSafeToFold, /*InsnID*/7,
14569        GIM_CheckIsSafeToFold, /*InsnID*/8,
14570        GIM_CheckIsSafeToFold, /*InsnID*/9,
14571        GIM_CheckIsSafeToFold, /*InsnID*/10,
14572        GIM_CheckIsSafeToFold, /*InsnID*/11,
14573        GIM_CheckIsSafeToFold, /*InsnID*/12,
14574        GIM_CheckIsSafeToFold, /*InsnID*/13,
14575        GIM_CheckIsSafeToFold, /*InsnID*/14,
14576        GIM_CheckIsSafeToFold, /*InsnID*/15,
14577        GIM_CheckIsSafeToFold, /*InsnID*/16,
14578        GIM_CheckIsSafeToFold, /*InsnID*/17,
14579        GIM_CheckIsSafeToFold, /*InsnID*/18,
14580        // (srl:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>), v16i8:{ *:[v16i8] }:$wt))  =>  (SRL_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
14581        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRL_B,
14582        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
14583        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws
14584        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
14585        GIR_EraseFromParent, /*InsnID*/0,
14586        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14587        // GIR_Coverage, 2428,
14588        GIR_Done,
14589      // Label 903: @35290
14590      GIM_Try, /*On fail goto*//*Label 904*/ 35599, // Rule ID 2037 //
14591        GIM_CheckFeatures, GIFBS_HasMSA,
14592        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
14593        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
14594        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
14595        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
14596        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
14597        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR,
14598        GIM_CheckNumOperands, /*MI*/2, /*Expected*/17,
14599        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
14600        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
14601        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
14602        GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
14603        GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
14604        GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
14605        GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
14606        GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
14607        GIM_CheckType, /*MI*/2, /*Op*/9, /*Type*/GILLT_s32,
14608        GIM_CheckType, /*MI*/2, /*Op*/10, /*Type*/GILLT_s32,
14609        GIM_CheckType, /*MI*/2, /*Op*/11, /*Type*/GILLT_s32,
14610        GIM_CheckType, /*MI*/2, /*Op*/12, /*Type*/GILLT_s32,
14611        GIM_CheckType, /*MI*/2, /*Op*/13, /*Type*/GILLT_s32,
14612        GIM_CheckType, /*MI*/2, /*Op*/14, /*Type*/GILLT_s32,
14613        GIM_CheckType, /*MI*/2, /*Op*/15, /*Type*/GILLT_s32,
14614        GIM_CheckType, /*MI*/2, /*Op*/16, /*Type*/GILLT_s32,
14615        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
14616        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
14617        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
14618        // MIs[3] Operand 1
14619        // No operand predicates
14620        GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
14621        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
14622        GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
14623        // MIs[4] Operand 1
14624        // No operand predicates
14625        GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
14626        GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT,
14627        GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
14628        // MIs[5] Operand 1
14629        // No operand predicates
14630        GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
14631        GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT,
14632        GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
14633        // MIs[6] Operand 1
14634        // No operand predicates
14635        GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
14636        GIM_CheckOpcode, /*MI*/7, TargetOpcode::G_CONSTANT,
14637        GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
14638        // MIs[7] Operand 1
14639        // No operand predicates
14640        GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
14641        GIM_CheckOpcode, /*MI*/8, TargetOpcode::G_CONSTANT,
14642        GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
14643        // MIs[8] Operand 1
14644        // No operand predicates
14645        GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
14646        GIM_CheckOpcode, /*MI*/9, TargetOpcode::G_CONSTANT,
14647        GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
14648        // MIs[9] Operand 1
14649        // No operand predicates
14650        GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
14651        GIM_CheckOpcode, /*MI*/10, TargetOpcode::G_CONSTANT,
14652        GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
14653        // MIs[10] Operand 1
14654        // No operand predicates
14655        GIM_RecordInsn, /*DefineMI*/11, /*MI*/2, /*OpIdx*/9, // MIs[11]
14656        GIM_CheckOpcode, /*MI*/11, TargetOpcode::G_CONSTANT,
14657        GIM_CheckI64ImmPredicate, /*MI*/11, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
14658        // MIs[11] Operand 1
14659        // No operand predicates
14660        GIM_RecordInsn, /*DefineMI*/12, /*MI*/2, /*OpIdx*/10, // MIs[12]
14661        GIM_CheckOpcode, /*MI*/12, TargetOpcode::G_CONSTANT,
14662        GIM_CheckI64ImmPredicate, /*MI*/12, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
14663        // MIs[12] Operand 1
14664        // No operand predicates
14665        GIM_RecordInsn, /*DefineMI*/13, /*MI*/2, /*OpIdx*/11, // MIs[13]
14666        GIM_CheckOpcode, /*MI*/13, TargetOpcode::G_CONSTANT,
14667        GIM_CheckI64ImmPredicate, /*MI*/13, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
14668        // MIs[13] Operand 1
14669        // No operand predicates
14670        GIM_RecordInsn, /*DefineMI*/14, /*MI*/2, /*OpIdx*/12, // MIs[14]
14671        GIM_CheckOpcode, /*MI*/14, TargetOpcode::G_CONSTANT,
14672        GIM_CheckI64ImmPredicate, /*MI*/14, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
14673        // MIs[14] Operand 1
14674        // No operand predicates
14675        GIM_RecordInsn, /*DefineMI*/15, /*MI*/2, /*OpIdx*/13, // MIs[15]
14676        GIM_CheckOpcode, /*MI*/15, TargetOpcode::G_CONSTANT,
14677        GIM_CheckI64ImmPredicate, /*MI*/15, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
14678        // MIs[15] Operand 1
14679        // No operand predicates
14680        GIM_RecordInsn, /*DefineMI*/16, /*MI*/2, /*OpIdx*/14, // MIs[16]
14681        GIM_CheckOpcode, /*MI*/16, TargetOpcode::G_CONSTANT,
14682        GIM_CheckI64ImmPredicate, /*MI*/16, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
14683        // MIs[16] Operand 1
14684        // No operand predicates
14685        GIM_RecordInsn, /*DefineMI*/17, /*MI*/2, /*OpIdx*/15, // MIs[17]
14686        GIM_CheckOpcode, /*MI*/17, TargetOpcode::G_CONSTANT,
14687        GIM_CheckI64ImmPredicate, /*MI*/17, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
14688        // MIs[17] Operand 1
14689        // No operand predicates
14690        GIM_RecordInsn, /*DefineMI*/18, /*MI*/2, /*OpIdx*/16, // MIs[18]
14691        GIM_CheckOpcode, /*MI*/18, TargetOpcode::G_CONSTANT,
14692        GIM_CheckI64ImmPredicate, /*MI*/18, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
14693        // MIs[18] Operand 1
14694        // No operand predicates
14695        GIM_CheckIsSafeToFold, /*InsnID*/1,
14696        GIM_CheckIsSafeToFold, /*InsnID*/2,
14697        GIM_CheckIsSafeToFold, /*InsnID*/3,
14698        GIM_CheckIsSafeToFold, /*InsnID*/4,
14699        GIM_CheckIsSafeToFold, /*InsnID*/5,
14700        GIM_CheckIsSafeToFold, /*InsnID*/6,
14701        GIM_CheckIsSafeToFold, /*InsnID*/7,
14702        GIM_CheckIsSafeToFold, /*InsnID*/8,
14703        GIM_CheckIsSafeToFold, /*InsnID*/9,
14704        GIM_CheckIsSafeToFold, /*InsnID*/10,
14705        GIM_CheckIsSafeToFold, /*InsnID*/11,
14706        GIM_CheckIsSafeToFold, /*InsnID*/12,
14707        GIM_CheckIsSafeToFold, /*InsnID*/13,
14708        GIM_CheckIsSafeToFold, /*InsnID*/14,
14709        GIM_CheckIsSafeToFold, /*InsnID*/15,
14710        GIM_CheckIsSafeToFold, /*InsnID*/16,
14711        GIM_CheckIsSafeToFold, /*InsnID*/17,
14712        GIM_CheckIsSafeToFold, /*InsnID*/18,
14713        // (srl:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$wt, (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>)))  =>  (SRL_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
14714        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRL_B,
14715        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
14716        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws
14717        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
14718        GIR_EraseFromParent, /*InsnID*/0,
14719        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14720        // GIR_Coverage, 2037,
14721        GIR_Done,
14722      // Label 904: @35599
14723      GIM_Try, /*On fail goto*//*Label 905*/ 35618, // Rule ID 977 //
14724        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
14725        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
14726        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
14727        // (srl:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (SRL_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
14728        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRL_B,
14729        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14730        // GIR_Coverage, 977,
14731        GIR_Done,
14732      // Label 905: @35618
14733      GIM_Reject,
14734    // Label 902: @35619
14735    GIM_Reject,
14736    // Label 880: @35620
14737    GIM_Reject,
14738    // Label 25: @35621
14739    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 912*/ 37330,
14740    /*GILLT_s32*//*Label 906*/ 35635,
14741    /*GILLT_s64*//*Label 907*/ 35845, 0,
14742    /*GILLT_v2s64*//*Label 908*/ 35979, 0,
14743    /*GILLT_v4s32*//*Label 909*/ 36011,
14744    /*GILLT_v8s16*//*Label 910*/ 36280,
14745    /*GILLT_v16s8*//*Label 911*/ 36677,
14746    // Label 906: @35635
14747    GIM_Try, /*On fail goto*//*Label 913*/ 35844,
14748      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
14749      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
14750      GIM_Try, /*On fail goto*//*Label 914*/ 35688, // Rule ID 57 //
14751        GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
14752        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
14753        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
14754        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
14755        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
14756        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
14757        // MIs[1] Operand 1
14758        // No operand predicates
14759        GIM_CheckIsSafeToFold, /*InsnID*/1,
14760        // (sra:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shamt)  =>  (SRA:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$shamt)
14761        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRA,
14762        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
14763        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt
14764        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
14765        GIR_EraseFromParent, /*InsnID*/0,
14766        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14767        // GIR_Coverage, 57,
14768        GIR_Done,
14769      // Label 914: @35688
14770      GIM_Try, /*On fail goto*//*Label 915*/ 35731, // Rule ID 1793 //
14771        GIM_CheckFeatures, GIFBS_InMips16Mode,
14772        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
14773        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
14774        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
14775        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
14776        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
14777        // MIs[1] Operand 1
14778        // No operand predicates
14779        GIM_CheckIsSafeToFold, /*InsnID*/1,
14780        // (sra:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)  =>  (SraX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
14781        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SraX16,
14782        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rx
14783        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in
14784        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
14785        GIR_EraseFromParent, /*InsnID*/0,
14786        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14787        // GIR_Coverage, 1793,
14788        GIR_Done,
14789      // Label 915: @35731
14790      GIM_Try, /*On fail goto*//*Label 916*/ 35774, // Rule ID 2134 //
14791        GIM_CheckFeatures, GIFBS_InMicroMips,
14792        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
14793        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
14794        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
14795        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
14796        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
14797        // MIs[1] Operand 1
14798        // No operand predicates
14799        GIM_CheckIsSafeToFold, /*InsnID*/1,
14800        // (sra:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)  =>  (SRA_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
14801        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRA_MM,
14802        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
14803        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
14804        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
14805        GIR_EraseFromParent, /*InsnID*/0,
14806        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14807        // GIR_Coverage, 2134,
14808        GIR_Done,
14809      // Label 916: @35774
14810      GIM_Try, /*On fail goto*//*Label 917*/ 35797, // Rule ID 60 //
14811        GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
14812        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
14813        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
14814        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
14815        // (sra:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)  =>  (SRAV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
14816        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRAV,
14817        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14818        // GIR_Coverage, 60,
14819        GIR_Done,
14820      // Label 917: @35797
14821      GIM_Try, /*On fail goto*//*Label 918*/ 35820, // Rule ID 1795 //
14822        GIM_CheckFeatures, GIFBS_InMips16Mode,
14823        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
14824        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
14825        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
14826        // (sra:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra)  =>  (SravRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra)
14827        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SravRxRy16,
14828        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14829        // GIR_Coverage, 1795,
14830        GIR_Done,
14831      // Label 918: @35820
14832      GIM_Try, /*On fail goto*//*Label 919*/ 35843, // Rule ID 2135 //
14833        GIM_CheckFeatures, GIFBS_InMicroMips,
14834        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
14835        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
14836        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
14837        // (sra:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs)  =>  (SRAV_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs)
14838        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRAV_MM,
14839        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14840        // GIR_Coverage, 2135,
14841        GIR_Done,
14842      // Label 919: @35843
14843      GIM_Reject,
14844    // Label 913: @35844
14845    GIM_Reject,
14846    // Label 907: @35845
14847    GIM_Try, /*On fail goto*//*Label 920*/ 35978,
14848      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
14849      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
14850      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
14851      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
14852      GIM_Try, /*On fail goto*//*Label 921*/ 35898, // Rule ID 206 //
14853        GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_NotInMicroMips,
14854        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
14855        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
14856        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt6,
14857        // MIs[1] Operand 1
14858        // No operand predicates
14859        GIM_CheckIsSafeToFold, /*InsnID*/1,
14860        // (sra:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$shamt)  =>  (DSRA:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$shamt)
14861        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSRA,
14862        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
14863        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt
14864        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
14865        GIR_EraseFromParent, /*InsnID*/0,
14866        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14867        // GIR_Coverage, 206,
14868        GIR_Done,
14869      // Label 921: @35898
14870      GIM_Try, /*On fail goto*//*Label 922*/ 35962, // Rule ID 1564 //
14871        GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit,
14872        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
14873        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC,
14874        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
14875        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
14876        GIM_CheckIsSafeToFold, /*InsnID*/1,
14877        // (sra:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$rs))  =>  (DSRAV:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$rs, sub_32:{ *:[i32] }))
14878        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
14879        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
14880        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
14881        GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/1, // rs
14882        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, Mips::DSPRRegClassID,
14883        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, Mips::GPR64RegClassID,
14884        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSRAV,
14885        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
14886        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt
14887        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
14888        GIR_EraseFromParent, /*InsnID*/0,
14889        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14890        // GIR_Coverage, 1564,
14891        GIR_Done,
14892      // Label 922: @35962
14893      GIM_Try, /*On fail goto*//*Label 923*/ 35977, // Rule ID 208 //
14894        GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_NotInMicroMips,
14895        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
14896        // (sra:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)  =>  (DSRAV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
14897        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DSRAV,
14898        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14899        // GIR_Coverage, 208,
14900        GIR_Done,
14901      // Label 923: @35977
14902      GIM_Reject,
14903    // Label 920: @35978
14904    GIM_Reject,
14905    // Label 908: @35979
14906    GIM_Try, /*On fail goto*//*Label 924*/ 36010, // Rule ID 964 //
14907      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
14908      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
14909      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
14910      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
14911      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
14912      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
14913      // (sra:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (SRA_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
14914      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRA_D,
14915      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14916      // GIR_Coverage, 964,
14917      GIR_Done,
14918    // Label 924: @36010
14919    GIM_Reject,
14920    // Label 909: @36011
14921    GIM_Try, /*On fail goto*//*Label 925*/ 36279,
14922      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
14923      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
14924      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
14925      GIM_Try, /*On fail goto*//*Label 926*/ 36142, // Rule ID 2434 //
14926        GIM_CheckFeatures, GIFBS_HasMSA,
14927        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
14928        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
14929        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
14930        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
14931        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
14932        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR,
14933        GIM_CheckNumOperands, /*MI*/2, /*Expected*/5,
14934        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
14935        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
14936        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
14937        GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
14938        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
14939        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
14940        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_immi32Cst31,
14941        // MIs[3] Operand 1
14942        // No operand predicates
14943        GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
14944        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
14945        GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_immi32Cst31,
14946        // MIs[4] Operand 1
14947        // No operand predicates
14948        GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
14949        GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT,
14950        GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIPFP_I64_Predicate_immi32Cst31,
14951        // MIs[5] Operand 1
14952        // No operand predicates
14953        GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
14954        GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT,
14955        GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIPFP_I64_Predicate_immi32Cst31,
14956        // MIs[6] Operand 1
14957        // No operand predicates
14958        GIM_CheckIsSafeToFold, /*InsnID*/1,
14959        GIM_CheckIsSafeToFold, /*InsnID*/2,
14960        GIM_CheckIsSafeToFold, /*InsnID*/3,
14961        GIM_CheckIsSafeToFold, /*InsnID*/4,
14962        GIM_CheckIsSafeToFold, /*InsnID*/5,
14963        GIM_CheckIsSafeToFold, /*InsnID*/6,
14964        // (sra:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>), v4i32:{ *:[v4i32] }:$wt))  =>  (SRA_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
14965        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRA_W,
14966        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
14967        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws
14968        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
14969        GIR_EraseFromParent, /*InsnID*/0,
14970        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14971        // GIR_Coverage, 2434,
14972        GIR_Done,
14973      // Label 926: @36142
14974      GIM_Try, /*On fail goto*//*Label 927*/ 36259, // Rule ID 2043 //
14975        GIM_CheckFeatures, GIFBS_HasMSA,
14976        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
14977        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
14978        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
14979        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
14980        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
14981        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR,
14982        GIM_CheckNumOperands, /*MI*/2, /*Expected*/5,
14983        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
14984        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
14985        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
14986        GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
14987        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
14988        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
14989        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_immi32Cst31,
14990        // MIs[3] Operand 1
14991        // No operand predicates
14992        GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
14993        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
14994        GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_immi32Cst31,
14995        // MIs[4] Operand 1
14996        // No operand predicates
14997        GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
14998        GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT,
14999        GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIPFP_I64_Predicate_immi32Cst31,
15000        // MIs[5] Operand 1
15001        // No operand predicates
15002        GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
15003        GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT,
15004        GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIPFP_I64_Predicate_immi32Cst31,
15005        // MIs[6] Operand 1
15006        // No operand predicates
15007        GIM_CheckIsSafeToFold, /*InsnID*/1,
15008        GIM_CheckIsSafeToFold, /*InsnID*/2,
15009        GIM_CheckIsSafeToFold, /*InsnID*/3,
15010        GIM_CheckIsSafeToFold, /*InsnID*/4,
15011        GIM_CheckIsSafeToFold, /*InsnID*/5,
15012        GIM_CheckIsSafeToFold, /*InsnID*/6,
15013        // (sra:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$wt, (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>)))  =>  (SRA_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
15014        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRA_W,
15015        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
15016        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws
15017        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
15018        GIR_EraseFromParent, /*InsnID*/0,
15019        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15020        // GIR_Coverage, 2043,
15021        GIR_Done,
15022      // Label 927: @36259
15023      GIM_Try, /*On fail goto*//*Label 928*/ 36278, // Rule ID 963 //
15024        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
15025        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
15026        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
15027        // (sra:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (SRA_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
15028        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRA_W,
15029        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15030        // GIR_Coverage, 963,
15031        GIR_Done,
15032      // Label 928: @36278
15033      GIM_Reject,
15034    // Label 925: @36279
15035    GIM_Reject,
15036    // Label 910: @36280
15037    GIM_Try, /*On fail goto*//*Label 929*/ 36676,
15038      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
15039      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
15040      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
15041      GIM_Try, /*On fail goto*//*Label 930*/ 36475, // Rule ID 2433 //
15042        GIM_CheckFeatures, GIFBS_HasMSA,
15043        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15044        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
15045        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
15046        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
15047        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
15048        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR,
15049        GIM_CheckNumOperands, /*MI*/2, /*Expected*/9,
15050        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
15051        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
15052        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
15053        GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
15054        GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
15055        GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
15056        GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
15057        GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
15058        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
15059        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
15060        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
15061        // MIs[3] Operand 1
15062        // No operand predicates
15063        GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
15064        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
15065        GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
15066        // MIs[4] Operand 1
15067        // No operand predicates
15068        GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
15069        GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT,
15070        GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
15071        // MIs[5] Operand 1
15072        // No operand predicates
15073        GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
15074        GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT,
15075        GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
15076        // MIs[6] Operand 1
15077        // No operand predicates
15078        GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
15079        GIM_CheckOpcode, /*MI*/7, TargetOpcode::G_CONSTANT,
15080        GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
15081        // MIs[7] Operand 1
15082        // No operand predicates
15083        GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
15084        GIM_CheckOpcode, /*MI*/8, TargetOpcode::G_CONSTANT,
15085        GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
15086        // MIs[8] Operand 1
15087        // No operand predicates
15088        GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
15089        GIM_CheckOpcode, /*MI*/9, TargetOpcode::G_CONSTANT,
15090        GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
15091        // MIs[9] Operand 1
15092        // No operand predicates
15093        GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
15094        GIM_CheckOpcode, /*MI*/10, TargetOpcode::G_CONSTANT,
15095        GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
15096        // MIs[10] Operand 1
15097        // No operand predicates
15098        GIM_CheckIsSafeToFold, /*InsnID*/1,
15099        GIM_CheckIsSafeToFold, /*InsnID*/2,
15100        GIM_CheckIsSafeToFold, /*InsnID*/3,
15101        GIM_CheckIsSafeToFold, /*InsnID*/4,
15102        GIM_CheckIsSafeToFold, /*InsnID*/5,
15103        GIM_CheckIsSafeToFold, /*InsnID*/6,
15104        GIM_CheckIsSafeToFold, /*InsnID*/7,
15105        GIM_CheckIsSafeToFold, /*InsnID*/8,
15106        GIM_CheckIsSafeToFold, /*InsnID*/9,
15107        GIM_CheckIsSafeToFold, /*InsnID*/10,
15108        // (sra:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>), v8i16:{ *:[v8i16] }:$wt))  =>  (SRA_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
15109        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRA_H,
15110        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
15111        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws
15112        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
15113        GIR_EraseFromParent, /*InsnID*/0,
15114        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15115        // GIR_Coverage, 2433,
15116        GIR_Done,
15117      // Label 930: @36475
15118      GIM_Try, /*On fail goto*//*Label 931*/ 36656, // Rule ID 2042 //
15119        GIM_CheckFeatures, GIFBS_HasMSA,
15120        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15121        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
15122        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
15123        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
15124        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
15125        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR,
15126        GIM_CheckNumOperands, /*MI*/2, /*Expected*/9,
15127        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
15128        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
15129        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
15130        GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
15131        GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
15132        GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
15133        GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
15134        GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
15135        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
15136        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
15137        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
15138        // MIs[3] Operand 1
15139        // No operand predicates
15140        GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
15141        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
15142        GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
15143        // MIs[4] Operand 1
15144        // No operand predicates
15145        GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
15146        GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT,
15147        GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
15148        // MIs[5] Operand 1
15149        // No operand predicates
15150        GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
15151        GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT,
15152        GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
15153        // MIs[6] Operand 1
15154        // No operand predicates
15155        GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
15156        GIM_CheckOpcode, /*MI*/7, TargetOpcode::G_CONSTANT,
15157        GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
15158        // MIs[7] Operand 1
15159        // No operand predicates
15160        GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
15161        GIM_CheckOpcode, /*MI*/8, TargetOpcode::G_CONSTANT,
15162        GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
15163        // MIs[8] Operand 1
15164        // No operand predicates
15165        GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
15166        GIM_CheckOpcode, /*MI*/9, TargetOpcode::G_CONSTANT,
15167        GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
15168        // MIs[9] Operand 1
15169        // No operand predicates
15170        GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
15171        GIM_CheckOpcode, /*MI*/10, TargetOpcode::G_CONSTANT,
15172        GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIPFP_I64_Predicate_immi32Cst15,
15173        // MIs[10] Operand 1
15174        // No operand predicates
15175        GIM_CheckIsSafeToFold, /*InsnID*/1,
15176        GIM_CheckIsSafeToFold, /*InsnID*/2,
15177        GIM_CheckIsSafeToFold, /*InsnID*/3,
15178        GIM_CheckIsSafeToFold, /*InsnID*/4,
15179        GIM_CheckIsSafeToFold, /*InsnID*/5,
15180        GIM_CheckIsSafeToFold, /*InsnID*/6,
15181        GIM_CheckIsSafeToFold, /*InsnID*/7,
15182        GIM_CheckIsSafeToFold, /*InsnID*/8,
15183        GIM_CheckIsSafeToFold, /*InsnID*/9,
15184        GIM_CheckIsSafeToFold, /*InsnID*/10,
15185        // (sra:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$wt, (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>)))  =>  (SRA_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
15186        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRA_H,
15187        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
15188        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws
15189        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
15190        GIR_EraseFromParent, /*InsnID*/0,
15191        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15192        // GIR_Coverage, 2042,
15193        GIR_Done,
15194      // Label 931: @36656
15195      GIM_Try, /*On fail goto*//*Label 932*/ 36675, // Rule ID 962 //
15196        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
15197        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
15198        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
15199        // (sra:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (SRA_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
15200        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRA_H,
15201        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15202        // GIR_Coverage, 962,
15203        GIR_Done,
15204      // Label 932: @36675
15205      GIM_Reject,
15206    // Label 929: @36676
15207    GIM_Reject,
15208    // Label 911: @36677
15209    GIM_Try, /*On fail goto*//*Label 933*/ 37329,
15210      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
15211      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
15212      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
15213      GIM_Try, /*On fail goto*//*Label 934*/ 37000, // Rule ID 2432 //
15214        GIM_CheckFeatures, GIFBS_HasMSA,
15215        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15216        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
15217        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
15218        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
15219        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
15220        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR,
15221        GIM_CheckNumOperands, /*MI*/2, /*Expected*/17,
15222        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
15223        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
15224        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
15225        GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
15226        GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
15227        GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
15228        GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
15229        GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
15230        GIM_CheckType, /*MI*/2, /*Op*/9, /*Type*/GILLT_s32,
15231        GIM_CheckType, /*MI*/2, /*Op*/10, /*Type*/GILLT_s32,
15232        GIM_CheckType, /*MI*/2, /*Op*/11, /*Type*/GILLT_s32,
15233        GIM_CheckType, /*MI*/2, /*Op*/12, /*Type*/GILLT_s32,
15234        GIM_CheckType, /*MI*/2, /*Op*/13, /*Type*/GILLT_s32,
15235        GIM_CheckType, /*MI*/2, /*Op*/14, /*Type*/GILLT_s32,
15236        GIM_CheckType, /*MI*/2, /*Op*/15, /*Type*/GILLT_s32,
15237        GIM_CheckType, /*MI*/2, /*Op*/16, /*Type*/GILLT_s32,
15238        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
15239        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
15240        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
15241        // MIs[3] Operand 1
15242        // No operand predicates
15243        GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
15244        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
15245        GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
15246        // MIs[4] Operand 1
15247        // No operand predicates
15248        GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
15249        GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT,
15250        GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
15251        // MIs[5] Operand 1
15252        // No operand predicates
15253        GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
15254        GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT,
15255        GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
15256        // MIs[6] Operand 1
15257        // No operand predicates
15258        GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
15259        GIM_CheckOpcode, /*MI*/7, TargetOpcode::G_CONSTANT,
15260        GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
15261        // MIs[7] Operand 1
15262        // No operand predicates
15263        GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
15264        GIM_CheckOpcode, /*MI*/8, TargetOpcode::G_CONSTANT,
15265        GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
15266        // MIs[8] Operand 1
15267        // No operand predicates
15268        GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
15269        GIM_CheckOpcode, /*MI*/9, TargetOpcode::G_CONSTANT,
15270        GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
15271        // MIs[9] Operand 1
15272        // No operand predicates
15273        GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
15274        GIM_CheckOpcode, /*MI*/10, TargetOpcode::G_CONSTANT,
15275        GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
15276        // MIs[10] Operand 1
15277        // No operand predicates
15278        GIM_RecordInsn, /*DefineMI*/11, /*MI*/2, /*OpIdx*/9, // MIs[11]
15279        GIM_CheckOpcode, /*MI*/11, TargetOpcode::G_CONSTANT,
15280        GIM_CheckI64ImmPredicate, /*MI*/11, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
15281        // MIs[11] Operand 1
15282        // No operand predicates
15283        GIM_RecordInsn, /*DefineMI*/12, /*MI*/2, /*OpIdx*/10, // MIs[12]
15284        GIM_CheckOpcode, /*MI*/12, TargetOpcode::G_CONSTANT,
15285        GIM_CheckI64ImmPredicate, /*MI*/12, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
15286        // MIs[12] Operand 1
15287        // No operand predicates
15288        GIM_RecordInsn, /*DefineMI*/13, /*MI*/2, /*OpIdx*/11, // MIs[13]
15289        GIM_CheckOpcode, /*MI*/13, TargetOpcode::G_CONSTANT,
15290        GIM_CheckI64ImmPredicate, /*MI*/13, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
15291        // MIs[13] Operand 1
15292        // No operand predicates
15293        GIM_RecordInsn, /*DefineMI*/14, /*MI*/2, /*OpIdx*/12, // MIs[14]
15294        GIM_CheckOpcode, /*MI*/14, TargetOpcode::G_CONSTANT,
15295        GIM_CheckI64ImmPredicate, /*MI*/14, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
15296        // MIs[14] Operand 1
15297        // No operand predicates
15298        GIM_RecordInsn, /*DefineMI*/15, /*MI*/2, /*OpIdx*/13, // MIs[15]
15299        GIM_CheckOpcode, /*MI*/15, TargetOpcode::G_CONSTANT,
15300        GIM_CheckI64ImmPredicate, /*MI*/15, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
15301        // MIs[15] Operand 1
15302        // No operand predicates
15303        GIM_RecordInsn, /*DefineMI*/16, /*MI*/2, /*OpIdx*/14, // MIs[16]
15304        GIM_CheckOpcode, /*MI*/16, TargetOpcode::G_CONSTANT,
15305        GIM_CheckI64ImmPredicate, /*MI*/16, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
15306        // MIs[16] Operand 1
15307        // No operand predicates
15308        GIM_RecordInsn, /*DefineMI*/17, /*MI*/2, /*OpIdx*/15, // MIs[17]
15309        GIM_CheckOpcode, /*MI*/17, TargetOpcode::G_CONSTANT,
15310        GIM_CheckI64ImmPredicate, /*MI*/17, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
15311        // MIs[17] Operand 1
15312        // No operand predicates
15313        GIM_RecordInsn, /*DefineMI*/18, /*MI*/2, /*OpIdx*/16, // MIs[18]
15314        GIM_CheckOpcode, /*MI*/18, TargetOpcode::G_CONSTANT,
15315        GIM_CheckI64ImmPredicate, /*MI*/18, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
15316        // MIs[18] Operand 1
15317        // No operand predicates
15318        GIM_CheckIsSafeToFold, /*InsnID*/1,
15319        GIM_CheckIsSafeToFold, /*InsnID*/2,
15320        GIM_CheckIsSafeToFold, /*InsnID*/3,
15321        GIM_CheckIsSafeToFold, /*InsnID*/4,
15322        GIM_CheckIsSafeToFold, /*InsnID*/5,
15323        GIM_CheckIsSafeToFold, /*InsnID*/6,
15324        GIM_CheckIsSafeToFold, /*InsnID*/7,
15325        GIM_CheckIsSafeToFold, /*InsnID*/8,
15326        GIM_CheckIsSafeToFold, /*InsnID*/9,
15327        GIM_CheckIsSafeToFold, /*InsnID*/10,
15328        GIM_CheckIsSafeToFold, /*InsnID*/11,
15329        GIM_CheckIsSafeToFold, /*InsnID*/12,
15330        GIM_CheckIsSafeToFold, /*InsnID*/13,
15331        GIM_CheckIsSafeToFold, /*InsnID*/14,
15332        GIM_CheckIsSafeToFold, /*InsnID*/15,
15333        GIM_CheckIsSafeToFold, /*InsnID*/16,
15334        GIM_CheckIsSafeToFold, /*InsnID*/17,
15335        GIM_CheckIsSafeToFold, /*InsnID*/18,
15336        // (sra:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>), v16i8:{ *:[v16i8] }:$wt))  =>  (SRA_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
15337        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRA_B,
15338        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
15339        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws
15340        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
15341        GIR_EraseFromParent, /*InsnID*/0,
15342        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15343        // GIR_Coverage, 2432,
15344        GIR_Done,
15345      // Label 934: @37000
15346      GIM_Try, /*On fail goto*//*Label 935*/ 37309, // Rule ID 2041 //
15347        GIM_CheckFeatures, GIFBS_HasMSA,
15348        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15349        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
15350        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
15351        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
15352        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
15353        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR,
15354        GIM_CheckNumOperands, /*MI*/2, /*Expected*/17,
15355        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
15356        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
15357        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
15358        GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
15359        GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
15360        GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
15361        GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
15362        GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
15363        GIM_CheckType, /*MI*/2, /*Op*/9, /*Type*/GILLT_s32,
15364        GIM_CheckType, /*MI*/2, /*Op*/10, /*Type*/GILLT_s32,
15365        GIM_CheckType, /*MI*/2, /*Op*/11, /*Type*/GILLT_s32,
15366        GIM_CheckType, /*MI*/2, /*Op*/12, /*Type*/GILLT_s32,
15367        GIM_CheckType, /*MI*/2, /*Op*/13, /*Type*/GILLT_s32,
15368        GIM_CheckType, /*MI*/2, /*Op*/14, /*Type*/GILLT_s32,
15369        GIM_CheckType, /*MI*/2, /*Op*/15, /*Type*/GILLT_s32,
15370        GIM_CheckType, /*MI*/2, /*Op*/16, /*Type*/GILLT_s32,
15371        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
15372        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
15373        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
15374        // MIs[3] Operand 1
15375        // No operand predicates
15376        GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
15377        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
15378        GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
15379        // MIs[4] Operand 1
15380        // No operand predicates
15381        GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
15382        GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT,
15383        GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
15384        // MIs[5] Operand 1
15385        // No operand predicates
15386        GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
15387        GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT,
15388        GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
15389        // MIs[6] Operand 1
15390        // No operand predicates
15391        GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
15392        GIM_CheckOpcode, /*MI*/7, TargetOpcode::G_CONSTANT,
15393        GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
15394        // MIs[7] Operand 1
15395        // No operand predicates
15396        GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
15397        GIM_CheckOpcode, /*MI*/8, TargetOpcode::G_CONSTANT,
15398        GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
15399        // MIs[8] Operand 1
15400        // No operand predicates
15401        GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
15402        GIM_CheckOpcode, /*MI*/9, TargetOpcode::G_CONSTANT,
15403        GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
15404        // MIs[9] Operand 1
15405        // No operand predicates
15406        GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
15407        GIM_CheckOpcode, /*MI*/10, TargetOpcode::G_CONSTANT,
15408        GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
15409        // MIs[10] Operand 1
15410        // No operand predicates
15411        GIM_RecordInsn, /*DefineMI*/11, /*MI*/2, /*OpIdx*/9, // MIs[11]
15412        GIM_CheckOpcode, /*MI*/11, TargetOpcode::G_CONSTANT,
15413        GIM_CheckI64ImmPredicate, /*MI*/11, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
15414        // MIs[11] Operand 1
15415        // No operand predicates
15416        GIM_RecordInsn, /*DefineMI*/12, /*MI*/2, /*OpIdx*/10, // MIs[12]
15417        GIM_CheckOpcode, /*MI*/12, TargetOpcode::G_CONSTANT,
15418        GIM_CheckI64ImmPredicate, /*MI*/12, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
15419        // MIs[12] Operand 1
15420        // No operand predicates
15421        GIM_RecordInsn, /*DefineMI*/13, /*MI*/2, /*OpIdx*/11, // MIs[13]
15422        GIM_CheckOpcode, /*MI*/13, TargetOpcode::G_CONSTANT,
15423        GIM_CheckI64ImmPredicate, /*MI*/13, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
15424        // MIs[13] Operand 1
15425        // No operand predicates
15426        GIM_RecordInsn, /*DefineMI*/14, /*MI*/2, /*OpIdx*/12, // MIs[14]
15427        GIM_CheckOpcode, /*MI*/14, TargetOpcode::G_CONSTANT,
15428        GIM_CheckI64ImmPredicate, /*MI*/14, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
15429        // MIs[14] Operand 1
15430        // No operand predicates
15431        GIM_RecordInsn, /*DefineMI*/15, /*MI*/2, /*OpIdx*/13, // MIs[15]
15432        GIM_CheckOpcode, /*MI*/15, TargetOpcode::G_CONSTANT,
15433        GIM_CheckI64ImmPredicate, /*MI*/15, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
15434        // MIs[15] Operand 1
15435        // No operand predicates
15436        GIM_RecordInsn, /*DefineMI*/16, /*MI*/2, /*OpIdx*/14, // MIs[16]
15437        GIM_CheckOpcode, /*MI*/16, TargetOpcode::G_CONSTANT,
15438        GIM_CheckI64ImmPredicate, /*MI*/16, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
15439        // MIs[16] Operand 1
15440        // No operand predicates
15441        GIM_RecordInsn, /*DefineMI*/17, /*MI*/2, /*OpIdx*/15, // MIs[17]
15442        GIM_CheckOpcode, /*MI*/17, TargetOpcode::G_CONSTANT,
15443        GIM_CheckI64ImmPredicate, /*MI*/17, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
15444        // MIs[17] Operand 1
15445        // No operand predicates
15446        GIM_RecordInsn, /*DefineMI*/18, /*MI*/2, /*OpIdx*/16, // MIs[18]
15447        GIM_CheckOpcode, /*MI*/18, TargetOpcode::G_CONSTANT,
15448        GIM_CheckI64ImmPredicate, /*MI*/18, /*Predicate*/GIPFP_I64_Predicate_immi32Cst7,
15449        // MIs[18] Operand 1
15450        // No operand predicates
15451        GIM_CheckIsSafeToFold, /*InsnID*/1,
15452        GIM_CheckIsSafeToFold, /*InsnID*/2,
15453        GIM_CheckIsSafeToFold, /*InsnID*/3,
15454        GIM_CheckIsSafeToFold, /*InsnID*/4,
15455        GIM_CheckIsSafeToFold, /*InsnID*/5,
15456        GIM_CheckIsSafeToFold, /*InsnID*/6,
15457        GIM_CheckIsSafeToFold, /*InsnID*/7,
15458        GIM_CheckIsSafeToFold, /*InsnID*/8,
15459        GIM_CheckIsSafeToFold, /*InsnID*/9,
15460        GIM_CheckIsSafeToFold, /*InsnID*/10,
15461        GIM_CheckIsSafeToFold, /*InsnID*/11,
15462        GIM_CheckIsSafeToFold, /*InsnID*/12,
15463        GIM_CheckIsSafeToFold, /*InsnID*/13,
15464        GIM_CheckIsSafeToFold, /*InsnID*/14,
15465        GIM_CheckIsSafeToFold, /*InsnID*/15,
15466        GIM_CheckIsSafeToFold, /*InsnID*/16,
15467        GIM_CheckIsSafeToFold, /*InsnID*/17,
15468        GIM_CheckIsSafeToFold, /*InsnID*/18,
15469        // (sra:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$wt, (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>)))  =>  (SRA_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
15470        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRA_B,
15471        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
15472        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws
15473        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
15474        GIR_EraseFromParent, /*InsnID*/0,
15475        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15476        // GIR_Coverage, 2041,
15477        GIR_Done,
15478      // Label 935: @37309
15479      GIM_Try, /*On fail goto*//*Label 936*/ 37328, // Rule ID 961 //
15480        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
15481        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
15482        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
15483        // (sra:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (SRA_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
15484        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRA_B,
15485        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15486        // GIR_Coverage, 961,
15487        GIR_Done,
15488      // Label 936: @37328
15489      GIM_Reject,
15490    // Label 933: @37329
15491    GIM_Reject,
15492    // Label 912: @37330
15493    GIM_Reject,
15494    // Label 26: @37331
15495    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 939*/ 37593,
15496    /*GILLT_s32*//*Label 937*/ 37339,
15497    /*GILLT_s64*//*Label 938*/ 37459,
15498    // Label 937: @37339
15499    GIM_Try, /*On fail goto*//*Label 940*/ 37458,
15500      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
15501      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
15502      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
15503      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
15504      GIM_Try, /*On fail goto*//*Label 941*/ 37392, // Rule ID 61 //
15505        GIM_CheckFeatures, GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips,
15506        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15507        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
15508        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
15509        // MIs[1] Operand 1
15510        // No operand predicates
15511        GIM_CheckIsSafeToFold, /*InsnID*/1,
15512        // (rotr:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shamt)  =>  (ROTR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$shamt)
15513        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ROTR,
15514        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
15515        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt
15516        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
15517        GIR_EraseFromParent, /*InsnID*/0,
15518        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15519        // GIR_Coverage, 61,
15520        GIR_Done,
15521      // Label 941: @37392
15522      GIM_Try, /*On fail goto*//*Label 942*/ 37427, // Rule ID 1069 //
15523        GIM_CheckFeatures, GIFBS_InMicroMips,
15524        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15525        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
15526        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
15527        // MIs[1] Operand 1
15528        // No operand predicates
15529        GIM_CheckIsSafeToFold, /*InsnID*/1,
15530        // (rotr:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shamt)  =>  (ROTR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$shamt)
15531        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ROTR_MM,
15532        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
15533        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt
15534        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
15535        GIR_EraseFromParent, /*InsnID*/0,
15536        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15537        // GIR_Coverage, 1069,
15538        GIR_Done,
15539      // Label 942: @37427
15540      GIM_Try, /*On fail goto*//*Label 943*/ 37442, // Rule ID 62 //
15541        GIM_CheckFeatures, GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips,
15542        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
15543        // (rotr:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)  =>  (ROTRV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
15544        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ROTRV,
15545        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15546        // GIR_Coverage, 62,
15547        GIR_Done,
15548      // Label 943: @37442
15549      GIM_Try, /*On fail goto*//*Label 944*/ 37457, // Rule ID 1070 //
15550        GIM_CheckFeatures, GIFBS_InMicroMips,
15551        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
15552        // (rotr:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)  =>  (ROTRV_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
15553        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ROTRV_MM,
15554        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15555        // GIR_Coverage, 1070,
15556        GIR_Done,
15557      // Label 944: @37457
15558      GIM_Reject,
15559    // Label 940: @37458
15560    GIM_Reject,
15561    // Label 938: @37459
15562    GIM_Try, /*On fail goto*//*Label 945*/ 37592,
15563      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
15564      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
15565      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
15566      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
15567      GIM_Try, /*On fail goto*//*Label 946*/ 37512, // Rule ID 210 //
15568        GIM_CheckFeatures, GIFBS_HasMips64r2_HasStdEnc_NotInMicroMips,
15569        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15570        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
15571        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt6,
15572        // MIs[1] Operand 1
15573        // No operand predicates
15574        GIM_CheckIsSafeToFold, /*InsnID*/1,
15575        // (rotr:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$shamt)  =>  (DROTR:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$shamt)
15576        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DROTR,
15577        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
15578        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt
15579        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
15580        GIR_EraseFromParent, /*InsnID*/0,
15581        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15582        // GIR_Coverage, 210,
15583        GIR_Done,
15584      // Label 946: @37512
15585      GIM_Try, /*On fail goto*//*Label 947*/ 37576, // Rule ID 1565 //
15586        GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit,
15587        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15588        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC,
15589        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
15590        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
15591        GIM_CheckIsSafeToFold, /*InsnID*/1,
15592        // (rotr:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$rs))  =>  (DROTRV:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$rs, sub_32:{ *:[i32] }))
15593        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
15594        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
15595        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
15596        GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/1, // rs
15597        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, Mips::DSPRRegClassID,
15598        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, Mips::GPR64RegClassID,
15599        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DROTRV,
15600        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
15601        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt
15602        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
15603        GIR_EraseFromParent, /*InsnID*/0,
15604        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15605        // GIR_Coverage, 1565,
15606        GIR_Done,
15607      // Label 947: @37576
15608      GIM_Try, /*On fail goto*//*Label 948*/ 37591, // Rule ID 211 //
15609        GIM_CheckFeatures, GIFBS_HasMips64r2_HasStdEnc_NotInMicroMips,
15610        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
15611        // (rotr:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)  =>  (DROTRV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
15612        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DROTRV,
15613        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15614        // GIR_Coverage, 211,
15615        GIR_Done,
15616      // Label 948: @37591
15617      GIM_Reject,
15618    // Label 945: @37592
15619    GIM_Reject,
15620    // Label 939: @37593
15621    GIM_Reject,
15622    // Label 27: @37594
15623    GIM_Try, /*On fail goto*//*Label 949*/ 40097,
15624      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
15625      GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/1, 3, /*)*//*default:*//*Label 952*/ 37774,
15626      /*GILLT_s32*//*Label 950*/ 37608,
15627      /*GILLT_s64*//*Label 951*/ 37691,
15628      // Label 950: @37608
15629      GIM_Try, /*On fail goto*//*Label 953*/ 37690,
15630        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
15631        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
15632        GIM_Try, /*On fail goto*//*Label 954*/ 37653, // Rule ID 1403 //
15633          GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
15634          // MIs[0] Operand 1
15635          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
15636          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
15637          GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
15638          // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] })  =>  (SLTiu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 1:{ *:[i32] })
15639          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTiu,
15640          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
15641          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // lhs
15642          GIR_AddImm, /*InsnID*/0, /*Imm*/1,
15643          GIR_EraseFromParent, /*InsnID*/0,
15644          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15645          // GIR_Coverage, 1403,
15646          GIR_Done,
15647        // Label 954: @37653
15648        GIM_Try, /*On fail goto*//*Label 955*/ 37689, // Rule ID 1404 //
15649          GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
15650          // MIs[0] Operand 1
15651          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
15652          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
15653          GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
15654          // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] })  =>  (SLTu:{ *:[i32] } ZERO:{ *:[i32] }, GPR32:{ *:[i32] }:$lhs)
15655          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTu,
15656          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
15657          GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0,
15658          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // lhs
15659          GIR_EraseFromParent, /*InsnID*/0,
15660          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15661          // GIR_Coverage, 1404,
15662          GIR_Done,
15663        // Label 955: @37689
15664        GIM_Reject,
15665      // Label 953: @37690
15666      GIM_Reject,
15667      // Label 951: @37691
15668      GIM_Try, /*On fail goto*//*Label 956*/ 37773,
15669        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
15670        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
15671        GIM_Try, /*On fail goto*//*Label 957*/ 37736, // Rule ID 1547 //
15672          GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips,
15673          // MIs[0] Operand 1
15674          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
15675          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
15676          GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
15677          // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] })  =>  (SLTiu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 1:{ *:[i64] })
15678          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTiu64,
15679          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
15680          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // lhs
15681          GIR_AddImm, /*InsnID*/0, /*Imm*/1,
15682          GIR_EraseFromParent, /*InsnID*/0,
15683          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15684          // GIR_Coverage, 1547,
15685          GIR_Done,
15686        // Label 957: @37736
15687        GIM_Try, /*On fail goto*//*Label 958*/ 37772, // Rule ID 1548 //
15688          GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips,
15689          // MIs[0] Operand 1
15690          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
15691          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
15692          GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
15693          // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] })  =>  (SLTu64:{ *:[i32] } ZERO_64:{ *:[i64] }, GPR64:{ *:[i64] }:$lhs)
15694          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTu64,
15695          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
15696          GIR_AddRegister, /*InsnID*/0, Mips::ZERO_64, /*AddRegisterRegFlags*/0,
15697          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // lhs
15698          GIR_EraseFromParent, /*InsnID*/0,
15699          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15700          // GIR_Coverage, 1548,
15701          GIR_Done,
15702        // Label 958: @37772
15703        GIM_Reject,
15704      // Label 956: @37773
15705      GIM_Reject,
15706      // Label 952: @37774
15707      GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/1, 3, /*)*//*default:*//*Label 961*/ 38146,
15708      /*GILLT_s32*//*Label 959*/ 37782,
15709      /*GILLT_s64*//*Label 960*/ 38062,
15710      // Label 959: @37782
15711      GIM_Try, /*On fail goto*//*Label 962*/ 38061,
15712        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
15713        GIM_Try, /*On fail goto*//*Label 963*/ 37827, // Rule ID 1843 //
15714          GIM_CheckFeatures, GIFBS_InMips16Mode,
15715          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
15716          // MIs[0] Operand 1
15717          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
15718          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
15719          GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
15720          // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] })  =>  (SltiuCCRxImmX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, 1:{ *:[i32] })
15721          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SltiuCCRxImmX16,
15722          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // cc
15723          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // lhs
15724          GIR_AddImm, /*InsnID*/0, /*Imm*/1,
15725          GIR_EraseFromParent, /*InsnID*/0,
15726          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15727          // GIR_Coverage, 1843,
15728          GIR_Done,
15729        // Label 963: @37827
15730        GIM_Try, /*On fail goto*//*Label 964*/ 37901, // Rule ID 1845 //
15731          GIM_CheckFeatures, GIFBS_InMips16Mode,
15732          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
15733          // MIs[0] Operand 1
15734          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT,
15735          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
15736          GIM_CheckConstantInt, /*MI*/0, /*Op*/3, -32769,
15737          // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, -32769:{ *:[i32] }, SETGT:{ *:[Other] })  =>  (XorRxRxRy16:{ *:[i32] } (SltiCCRxImmX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, -32768:{ *:[i32] }), (LiRxImmX16:{ *:[i32] } 1:{ *:[i32] }))
15738          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
15739          GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
15740          GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::LiRxImmX16,
15741          GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
15742          GIR_AddImm, /*InsnID*/2, /*Imm*/1,
15743          GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
15744          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SltiCCRxImmX16,
15745          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
15746          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
15747          GIR_AddImm, /*InsnID*/1, /*Imm*/-32768,
15748          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15749          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XorRxRxRy16,
15750          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rz
15751          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
15752          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
15753          GIR_EraseFromParent, /*InsnID*/0,
15754          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15755          // GIR_Coverage, 1845,
15756          GIR_Done,
15757        // Label 964: @37901
15758        GIM_Try, /*On fail goto*//*Label 965*/ 37940, // Rule ID 2162 //
15759          GIM_CheckFeatures, GIFBS_InMicroMips,
15760          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
15761          // MIs[0] Operand 1
15762          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
15763          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
15764          GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
15765          // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] })  =>  (SLTiu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 1:{ *:[i32] })
15766          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTiu_MM,
15767          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
15768          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // lhs
15769          GIR_AddImm, /*InsnID*/0, /*Imm*/1,
15770          GIR_EraseFromParent, /*InsnID*/0,
15771          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15772          // GIR_Coverage, 2162,
15773          GIR_Done,
15774        // Label 965: @37940
15775        GIM_Try, /*On fail goto*//*Label 966*/ 37980, // Rule ID 2163 //
15776          GIM_CheckFeatures, GIFBS_InMicroMips,
15777          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
15778          // MIs[0] Operand 1
15779          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
15780          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
15781          GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
15782          // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] })  =>  (SLTu_MM:{ *:[i32] } ZERO:{ *:[i32] }, GPR32:{ *:[i32] }:$lhs)
15783          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTu_MM,
15784          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
15785          GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0,
15786          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // lhs
15787          GIR_EraseFromParent, /*InsnID*/0,
15788          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15789          // GIR_Coverage, 2163,
15790          GIR_Done,
15791        // Label 966: @37980
15792        GIM_Try, /*On fail goto*//*Label 967*/ 38020, // Rule ID 49 //
15793          GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
15794          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
15795          // MIs[0] Operand 1
15796          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT,
15797          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
15798          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
15799          // (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETLT:{ *:[Other] })  =>  (SLT:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
15800          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLT,
15801          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
15802          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
15803          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
15804          GIR_EraseFromParent, /*InsnID*/0,
15805          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15806          // GIR_Coverage, 49,
15807          GIR_Done,
15808        // Label 967: @38020
15809        GIM_Try, /*On fail goto*//*Label 968*/ 38060, // Rule ID 50 //
15810          GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
15811          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
15812          // MIs[0] Operand 1
15813          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT,
15814          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
15815          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
15816          // (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETULT:{ *:[Other] })  =>  (SLTu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
15817          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTu,
15818          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
15819          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
15820          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
15821          GIR_EraseFromParent, /*InsnID*/0,
15822          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15823          // GIR_Coverage, 50,
15824          GIR_Done,
15825        // Label 968: @38060
15826        GIM_Reject,
15827      // Label 962: @38061
15828      GIM_Reject,
15829      // Label 960: @38062
15830      GIM_Try, /*On fail goto*//*Label 969*/ 38145,
15831        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
15832        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
15833        GIM_Try, /*On fail goto*//*Label 970*/ 38108, // Rule ID 198 //
15834          GIM_CheckFeatures, GIFBS_IsGP64bit_NotInMips16Mode,
15835          // MIs[0] Operand 1
15836          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT,
15837          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
15838          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
15839          // (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, SETLT:{ *:[Other] })  =>  (SLT64:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
15840          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLT64,
15841          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
15842          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
15843          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
15844          GIR_EraseFromParent, /*InsnID*/0,
15845          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15846          // GIR_Coverage, 198,
15847          GIR_Done,
15848        // Label 970: @38108
15849        GIM_Try, /*On fail goto*//*Label 971*/ 38144, // Rule ID 199 //
15850          GIM_CheckFeatures, GIFBS_IsGP64bit_NotInMips16Mode,
15851          // MIs[0] Operand 1
15852          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT,
15853          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
15854          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
15855          // (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, SETULT:{ *:[Other] })  =>  (SLTu64:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
15856          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTu64,
15857          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
15858          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
15859          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
15860          GIR_EraseFromParent, /*InsnID*/0,
15861          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15862          // GIR_Coverage, 199,
15863          GIR_Done,
15864        // Label 971: @38144
15865        GIM_Reject,
15866      // Label 969: @38145
15867      GIM_Reject,
15868      // Label 961: @38146
15869      GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/1, 3, /*)*//*default:*//*Label 974*/ 39056,
15870      /*GILLT_s32*//*Label 972*/ 38154,
15871      /*GILLT_s64*//*Label 973*/ 38641,
15872      // Label 972: @38154
15873      GIM_Try, /*On fail goto*//*Label 975*/ 38640,
15874        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
15875        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
15876        GIM_Try, /*On fail goto*//*Label 976*/ 38200, // Rule ID 1063 //
15877          GIM_CheckFeatures, GIFBS_InMicroMips,
15878          // MIs[0] Operand 1
15879          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT,
15880          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
15881          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
15882          // (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETLT:{ *:[Other] })  =>  (SLT_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
15883          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLT_MM,
15884          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
15885          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
15886          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
15887          GIR_EraseFromParent, /*InsnID*/0,
15888          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15889          // GIR_Coverage, 1063,
15890          GIR_Done,
15891        // Label 976: @38200
15892        GIM_Try, /*On fail goto*//*Label 977*/ 38236, // Rule ID 1064 //
15893          GIM_CheckFeatures, GIFBS_InMicroMips,
15894          // MIs[0] Operand 1
15895          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT,
15896          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
15897          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
15898          // (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETULT:{ *:[Other] })  =>  (SLTu_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
15899          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTu_MM,
15900          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
15901          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
15902          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
15903          GIR_EraseFromParent, /*InsnID*/0,
15904          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15905          // GIR_Coverage, 1064,
15906          GIR_Done,
15907        // Label 977: @38236
15908        GIM_Try, /*On fail goto*//*Label 978*/ 38291, // Rule ID 1405 //
15909          GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
15910          // MIs[0] Operand 1
15911          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
15912          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
15913          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
15914          // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] })  =>  (SLTiu:{ *:[i32] } (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] })
15915          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
15916          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR,
15917          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
15918          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
15919          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
15920          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15921          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTiu,
15922          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
15923          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
15924          GIR_AddImm, /*InsnID*/0, /*Imm*/1,
15925          GIR_EraseFromParent, /*InsnID*/0,
15926          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15927          // GIR_Coverage, 1405,
15928          GIR_Done,
15929        // Label 978: @38291
15930        GIM_Try, /*On fail goto*//*Label 979*/ 38347, // Rule ID 1406 //
15931          GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
15932          // MIs[0] Operand 1
15933          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
15934          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
15935          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
15936          // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] })  =>  (SLTu:{ *:[i32] } ZERO:{ *:[i32] }, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs))
15937          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
15938          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR,
15939          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
15940          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
15941          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
15942          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15943          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTu,
15944          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
15945          GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0,
15946          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
15947          GIR_EraseFromParent, /*InsnID*/0,
15948          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15949          // GIR_Coverage, 1406,
15950          GIR_Done,
15951        // Label 979: @38347
15952        GIM_Try, /*On fail goto*//*Label 980*/ 38402, // Rule ID 1407 //
15953          GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
15954          // MIs[0] Operand 1
15955          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
15956          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
15957          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
15958          // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] })  =>  (XORi:{ *:[i32] } (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), 1:{ *:[i32] })
15959          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
15960          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT,
15961          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
15962          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
15963          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
15964          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15965          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi,
15966          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
15967          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
15968          GIR_AddImm, /*InsnID*/0, /*Imm*/1,
15969          GIR_EraseFromParent, /*InsnID*/0,
15970          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15971          // GIR_Coverage, 1407,
15972          GIR_Done,
15973        // Label 980: @38402
15974        GIM_Try, /*On fail goto*//*Label 981*/ 38457, // Rule ID 1408 //
15975          GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
15976          // MIs[0] Operand 1
15977          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
15978          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
15979          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
15980          // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] })  =>  (XORi:{ *:[i32] } (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), 1:{ *:[i32] })
15981          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
15982          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu,
15983          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
15984          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
15985          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
15986          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15987          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi,
15988          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
15989          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
15990          GIR_AddImm, /*InsnID*/0, /*Imm*/1,
15991          GIR_EraseFromParent, /*InsnID*/0,
15992          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15993          // GIR_Coverage, 1408,
15994          GIR_Done,
15995        // Label 981: @38457
15996        GIM_Try, /*On fail goto*//*Label 982*/ 38493, // Rule ID 1409 //
15997          GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
15998          // MIs[0] Operand 1
15999          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT,
16000          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
16001          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
16002          // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGT:{ *:[Other] })  =>  (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs)
16003          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLT,
16004          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
16005          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rhs
16006          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // lhs
16007          GIR_EraseFromParent, /*InsnID*/0,
16008          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16009          // GIR_Coverage, 1409,
16010          GIR_Done,
16011        // Label 982: @38493
16012        GIM_Try, /*On fail goto*//*Label 983*/ 38529, // Rule ID 1410 //
16013          GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
16014          // MIs[0] Operand 1
16015          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT,
16016          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
16017          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
16018          // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGT:{ *:[Other] })  =>  (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs)
16019          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTu,
16020          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
16021          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rhs
16022          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // lhs
16023          GIR_EraseFromParent, /*InsnID*/0,
16024          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16025          // GIR_Coverage, 1410,
16026          GIR_Done,
16027        // Label 983: @38529
16028        GIM_Try, /*On fail goto*//*Label 984*/ 38584, // Rule ID 1411 //
16029          GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
16030          // MIs[0] Operand 1
16031          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
16032          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
16033          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
16034          // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] })  =>  (XORi:{ *:[i32] } (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] })
16035          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16036          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT,
16037          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
16038          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
16039          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
16040          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16041          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi,
16042          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
16043          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16044          GIR_AddImm, /*InsnID*/0, /*Imm*/1,
16045          GIR_EraseFromParent, /*InsnID*/0,
16046          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16047          // GIR_Coverage, 1411,
16048          GIR_Done,
16049        // Label 984: @38584
16050        GIM_Try, /*On fail goto*//*Label 985*/ 38639, // Rule ID 1412 //
16051          GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
16052          // MIs[0] Operand 1
16053          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
16054          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
16055          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
16056          // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] })  =>  (XORi:{ *:[i32] } (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] })
16057          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16058          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu,
16059          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
16060          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
16061          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
16062          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16063          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi,
16064          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
16065          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16066          GIR_AddImm, /*InsnID*/0, /*Imm*/1,
16067          GIR_EraseFromParent, /*InsnID*/0,
16068          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16069          // GIR_Coverage, 1412,
16070          GIR_Done,
16071        // Label 985: @38639
16072        GIM_Reject,
16073      // Label 975: @38640
16074      GIM_Reject,
16075      // Label 973: @38641
16076      GIM_Try, /*On fail goto*//*Label 986*/ 39055,
16077        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
16078        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
16079        GIM_Try, /*On fail goto*//*Label 987*/ 38706, // Rule ID 1549 //
16080          GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips,
16081          // MIs[0] Operand 1
16082          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
16083          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
16084          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
16085          // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETEQ:{ *:[Other] })  =>  (SLTiu64:{ *:[i32] } (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), 1:{ *:[i64] })
16086          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
16087          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR64,
16088          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
16089          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
16090          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
16091          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16092          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTiu64,
16093          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
16094          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16095          GIR_AddImm, /*InsnID*/0, /*Imm*/1,
16096          GIR_EraseFromParent, /*InsnID*/0,
16097          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16098          // GIR_Coverage, 1549,
16099          GIR_Done,
16100        // Label 987: @38706
16101        GIM_Try, /*On fail goto*//*Label 988*/ 38762, // Rule ID 1550 //
16102          GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips,
16103          // MIs[0] Operand 1
16104          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
16105          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
16106          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
16107          // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETNE:{ *:[Other] })  =>  (SLTu64:{ *:[i32] } ZERO_64:{ *:[i64] }, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs))
16108          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
16109          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR64,
16110          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
16111          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
16112          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
16113          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16114          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTu64,
16115          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
16116          GIR_AddRegister, /*InsnID*/0, Mips::ZERO_64, /*AddRegisterRegFlags*/0,
16117          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16118          GIR_EraseFromParent, /*InsnID*/0,
16119          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16120          // GIR_Coverage, 1550,
16121          GIR_Done,
16122        // Label 988: @38762
16123        GIM_Try, /*On fail goto*//*Label 989*/ 38817, // Rule ID 1551 //
16124          GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips,
16125          // MIs[0] Operand 1
16126          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
16127          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
16128          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
16129          // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] })  =>  (XORi:{ *:[i32] } (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), 1:{ *:[i32] })
16130          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16131          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT64,
16132          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
16133          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
16134          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
16135          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16136          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi,
16137          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
16138          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16139          GIR_AddImm, /*InsnID*/0, /*Imm*/1,
16140          GIR_EraseFromParent, /*InsnID*/0,
16141          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16142          // GIR_Coverage, 1551,
16143          GIR_Done,
16144        // Label 989: @38817
16145        GIM_Try, /*On fail goto*//*Label 990*/ 38872, // Rule ID 1552 //
16146          GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips,
16147          // MIs[0] Operand 1
16148          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
16149          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
16150          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
16151          // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] })  =>  (XORi:{ *:[i32] } (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), 1:{ *:[i32] })
16152          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16153          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu64,
16154          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
16155          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
16156          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
16157          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16158          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi,
16159          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
16160          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16161          GIR_AddImm, /*InsnID*/0, /*Imm*/1,
16162          GIR_EraseFromParent, /*InsnID*/0,
16163          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16164          // GIR_Coverage, 1552,
16165          GIR_Done,
16166        // Label 990: @38872
16167        GIM_Try, /*On fail goto*//*Label 991*/ 38908, // Rule ID 1553 //
16168          GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips,
16169          // MIs[0] Operand 1
16170          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT,
16171          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
16172          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
16173          // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGT:{ *:[Other] })  =>  (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs)
16174          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLT64,
16175          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
16176          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rhs
16177          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // lhs
16178          GIR_EraseFromParent, /*InsnID*/0,
16179          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16180          // GIR_Coverage, 1553,
16181          GIR_Done,
16182        // Label 991: @38908
16183        GIM_Try, /*On fail goto*//*Label 992*/ 38944, // Rule ID 1554 //
16184          GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips,
16185          // MIs[0] Operand 1
16186          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT,
16187          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
16188          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
16189          // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGT:{ *:[Other] })  =>  (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs)
16190          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTu64,
16191          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
16192          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rhs
16193          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // lhs
16194          GIR_EraseFromParent, /*InsnID*/0,
16195          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16196          // GIR_Coverage, 1554,
16197          GIR_Done,
16198        // Label 992: @38944
16199        GIM_Try, /*On fail goto*//*Label 993*/ 38999, // Rule ID 1555 //
16200          GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips,
16201          // MIs[0] Operand 1
16202          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
16203          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
16204          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
16205          // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] })  =>  (XORi:{ *:[i32] } (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), 1:{ *:[i32] })
16206          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16207          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT64,
16208          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
16209          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
16210          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
16211          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16212          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi,
16213          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
16214          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16215          GIR_AddImm, /*InsnID*/0, /*Imm*/1,
16216          GIR_EraseFromParent, /*InsnID*/0,
16217          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16218          // GIR_Coverage, 1555,
16219          GIR_Done,
16220        // Label 993: @38999
16221        GIM_Try, /*On fail goto*//*Label 994*/ 39054, // Rule ID 1556 //
16222          GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips,
16223          // MIs[0] Operand 1
16224          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
16225          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
16226          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
16227          // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] })  =>  (XORi:{ *:[i32] } (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), 1:{ *:[i32] })
16228          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16229          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu64,
16230          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
16231          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
16232          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
16233          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16234          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi,
16235          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
16236          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16237          GIR_AddImm, /*InsnID*/0, /*Imm*/1,
16238          GIR_EraseFromParent, /*InsnID*/0,
16239          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16240          // GIR_Coverage, 1556,
16241          GIR_Done,
16242        // Label 994: @39054
16243        GIM_Reject,
16244      // Label 986: @39055
16245      GIM_Reject,
16246      // Label 974: @39056
16247      GIM_Try, /*On fail goto*//*Label 995*/ 40096,
16248        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16249        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16250        GIM_Try, /*On fail goto*//*Label 996*/ 39125, // Rule ID 1842 //
16251          GIM_CheckFeatures, GIFBS_InMips16Mode,
16252          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
16253          // MIs[0] Operand 1
16254          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
16255          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
16256          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID,
16257          // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] })  =>  (SltiuCCRxImmX16:{ *:[i32] } (XorRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs), 1:{ *:[i32] })
16258          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16259          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XorRxRxRy16,
16260          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
16261          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
16262          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
16263          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16264          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SltiuCCRxImmX16,
16265          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // cc
16266          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16267          GIR_AddImm, /*InsnID*/0, /*Imm*/1,
16268          GIR_EraseFromParent, /*InsnID*/0,
16269          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16270          // GIR_Coverage, 1842,
16271          GIR_Done,
16272        // Label 996: @39125
16273        GIM_Try, /*On fail goto*//*Label 997*/ 39200, // Rule ID 1844 //
16274          GIM_CheckFeatures, GIFBS_InMips16Mode,
16275          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
16276          // MIs[0] Operand 1
16277          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
16278          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
16279          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID,
16280          // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETGE:{ *:[Other] })  =>  (XorRxRxRy16:{ *:[i32] } (SltCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs), (LiRxImmX16:{ *:[i32] } 1:{ *:[i32] }))
16281          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16282          GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
16283          GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::LiRxImmX16,
16284          GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
16285          GIR_AddImm, /*InsnID*/2, /*Imm*/1,
16286          GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
16287          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SltCCRxRy16,
16288          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
16289          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
16290          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
16291          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16292          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XorRxRxRy16,
16293          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rz
16294          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16295          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
16296          GIR_EraseFromParent, /*InsnID*/0,
16297          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16298          // GIR_Coverage, 1844,
16299          GIR_Done,
16300        // Label 997: @39200
16301        GIM_Try, /*On fail goto*//*Label 998*/ 39240, // Rule ID 1846 //
16302          GIM_CheckFeatures, GIFBS_InMips16Mode,
16303          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
16304          // MIs[0] Operand 1
16305          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT,
16306          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
16307          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID,
16308          // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETGT:{ *:[Other] })  =>  (SltCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rhs, CPU16Regs:{ *:[i32] }:$lhs)
16309          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SltCCRxRy16,
16310          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // cc
16311          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rhs
16312          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // lhs
16313          GIR_EraseFromParent, /*InsnID*/0,
16314          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16315          // GIR_Coverage, 1846,
16316          GIR_Done,
16317        // Label 998: @39240
16318        GIM_Try, /*On fail goto*//*Label 999*/ 39315, // Rule ID 1847 //
16319          GIM_CheckFeatures, GIFBS_InMips16Mode,
16320          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
16321          // MIs[0] Operand 1
16322          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
16323          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
16324          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID,
16325          // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETLE:{ *:[Other] })  =>  (XorRxRxRy16:{ *:[i32] } (SltCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rhs, CPU16Regs:{ *:[i32] }:$lhs), (LiRxImm16:{ *:[i32] } 1:{ *:[i32] }))
16326          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16327          GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
16328          GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::LiRxImm16,
16329          GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
16330          GIR_AddImm, /*InsnID*/2, /*Imm*/1,
16331          GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
16332          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SltCCRxRy16,
16333          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
16334          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
16335          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
16336          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16337          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XorRxRxRy16,
16338          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rz
16339          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16340          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
16341          GIR_EraseFromParent, /*InsnID*/0,
16342          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16343          // GIR_Coverage, 1847,
16344          GIR_Done,
16345        // Label 999: @39315
16346        GIM_Try, /*On fail goto*//*Label 1000*/ 39355, // Rule ID 1848 //
16347          GIM_CheckFeatures, GIFBS_InMips16Mode,
16348          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
16349          // MIs[0] Operand 1
16350          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT,
16351          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
16352          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID,
16353          // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETLT:{ *:[Other] })  =>  (SltCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry)
16354          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SltCCRxRy16,
16355          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // cc
16356          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rx
16357          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ry
16358          GIR_EraseFromParent, /*InsnID*/0,
16359          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16360          // GIR_Coverage, 1848,
16361          GIR_Done,
16362        // Label 1000: @39355
16363        GIM_Try, /*On fail goto*//*Label 1001*/ 39430, // Rule ID 1850 //
16364          GIM_CheckFeatures, GIFBS_InMips16Mode,
16365          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
16366          // MIs[0] Operand 1
16367          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
16368          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
16369          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID,
16370          // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETNE:{ *:[Other] })  =>  (SltuCCRxRy16:{ *:[i32] } (LiRxImmX16:{ *:[i32] } 0:{ *:[i32] }), (XorRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs))
16371          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16372          GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
16373          GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::XorRxRxRy16,
16374          GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
16375          GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // lhs
16376          GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // rhs
16377          GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
16378          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::LiRxImmX16,
16379          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
16380          GIR_AddImm, /*InsnID*/1, /*Imm*/0,
16381          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16382          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SltuCCRxRy16,
16383          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // cc
16384          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16385          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
16386          GIR_EraseFromParent, /*InsnID*/0,
16387          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16388          // GIR_Coverage, 1850,
16389          GIR_Done,
16390        // Label 1001: @39430
16391        GIM_Try, /*On fail goto*//*Label 1002*/ 39505, // Rule ID 1851 //
16392          GIM_CheckFeatures, GIFBS_InMips16Mode,
16393          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
16394          // MIs[0] Operand 1
16395          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
16396          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
16397          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID,
16398          // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] })  =>  (XorRxRxRy16:{ *:[i32] } (SltuCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs), (LiRxImmX16:{ *:[i32] } 1:{ *:[i32] }))
16399          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16400          GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
16401          GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::LiRxImmX16,
16402          GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
16403          GIR_AddImm, /*InsnID*/2, /*Imm*/1,
16404          GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
16405          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SltuCCRxRy16,
16406          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
16407          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
16408          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
16409          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16410          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XorRxRxRy16,
16411          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rz
16412          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16413          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
16414          GIR_EraseFromParent, /*InsnID*/0,
16415          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16416          // GIR_Coverage, 1851,
16417          GIR_Done,
16418        // Label 1002: @39505
16419        GIM_Try, /*On fail goto*//*Label 1003*/ 39545, // Rule ID 1852 //
16420          GIM_CheckFeatures, GIFBS_InMips16Mode,
16421          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
16422          // MIs[0] Operand 1
16423          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT,
16424          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
16425          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID,
16426          // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETUGT:{ *:[Other] })  =>  (SltuCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rhs, CPU16Regs:{ *:[i32] }:$lhs)
16427          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SltuCCRxRy16,
16428          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // cc
16429          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rhs
16430          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // lhs
16431          GIR_EraseFromParent, /*InsnID*/0,
16432          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16433          // GIR_Coverage, 1852,
16434          GIR_Done,
16435        // Label 1003: @39545
16436        GIM_Try, /*On fail goto*//*Label 1004*/ 39620, // Rule ID 1853 //
16437          GIM_CheckFeatures, GIFBS_InMips16Mode,
16438          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
16439          // MIs[0] Operand 1
16440          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
16441          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
16442          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID,
16443          // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETULE:{ *:[Other] })  =>  (XorRxRxRy16:{ *:[i32] } (SltuCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rhs, CPU16Regs:{ *:[i32] }:$lhs), (LiRxImmX16:{ *:[i32] } 1:{ *:[i32] }))
16444          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16445          GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
16446          GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::LiRxImmX16,
16447          GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
16448          GIR_AddImm, /*InsnID*/2, /*Imm*/1,
16449          GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
16450          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SltuCCRxRy16,
16451          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
16452          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
16453          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
16454          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16455          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XorRxRxRy16,
16456          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rz
16457          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16458          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
16459          GIR_EraseFromParent, /*InsnID*/0,
16460          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16461          // GIR_Coverage, 1853,
16462          GIR_Done,
16463        // Label 1004: @39620
16464        GIM_Try, /*On fail goto*//*Label 1005*/ 39660, // Rule ID 1854 //
16465          GIM_CheckFeatures, GIFBS_InMips16Mode,
16466          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
16467          // MIs[0] Operand 1
16468          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT,
16469          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
16470          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID,
16471          // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETULT:{ *:[Other] })  =>  (SltuCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry)
16472          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SltuCCRxRy16,
16473          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // cc
16474          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rx
16475          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ry
16476          GIR_EraseFromParent, /*InsnID*/0,
16477          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16478          // GIR_Coverage, 1854,
16479          GIR_Done,
16480        // Label 1005: @39660
16481        GIM_Try, /*On fail goto*//*Label 1006*/ 39719, // Rule ID 2164 //
16482          GIM_CheckFeatures, GIFBS_InMicroMips,
16483          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
16484          // MIs[0] Operand 1
16485          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
16486          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
16487          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
16488          // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] })  =>  (SLTiu_MM:{ *:[i32] } (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] })
16489          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16490          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR_MM,
16491          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
16492          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
16493          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
16494          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16495          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTiu_MM,
16496          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
16497          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16498          GIR_AddImm, /*InsnID*/0, /*Imm*/1,
16499          GIR_EraseFromParent, /*InsnID*/0,
16500          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16501          // GIR_Coverage, 2164,
16502          GIR_Done,
16503        // Label 1006: @39719
16504        GIM_Try, /*On fail goto*//*Label 1007*/ 39779, // Rule ID 2165 //
16505          GIM_CheckFeatures, GIFBS_InMicroMips,
16506          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
16507          // MIs[0] Operand 1
16508          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
16509          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
16510          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
16511          // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] })  =>  (SLTu_MM:{ *:[i32] } ZERO:{ *:[i32] }, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs))
16512          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16513          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR_MM,
16514          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
16515          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
16516          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
16517          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16518          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTu_MM,
16519          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
16520          GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0,
16521          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16522          GIR_EraseFromParent, /*InsnID*/0,
16523          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16524          // GIR_Coverage, 2165,
16525          GIR_Done,
16526        // Label 1007: @39779
16527        GIM_Try, /*On fail goto*//*Label 1008*/ 39838, // Rule ID 2166 //
16528          GIM_CheckFeatures, GIFBS_InMicroMips,
16529          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
16530          // MIs[0] Operand 1
16531          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
16532          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
16533          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
16534          // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] })  =>  (XORi_MM:{ *:[i32] } (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), 1:{ *:[i32] })
16535          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16536          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT_MM,
16537          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
16538          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
16539          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
16540          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16541          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi_MM,
16542          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
16543          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16544          GIR_AddImm, /*InsnID*/0, /*Imm*/1,
16545          GIR_EraseFromParent, /*InsnID*/0,
16546          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16547          // GIR_Coverage, 2166,
16548          GIR_Done,
16549        // Label 1008: @39838
16550        GIM_Try, /*On fail goto*//*Label 1009*/ 39897, // Rule ID 2167 //
16551          GIM_CheckFeatures, GIFBS_InMicroMips,
16552          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
16553          // MIs[0] Operand 1
16554          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
16555          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
16556          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
16557          // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] })  =>  (XORi_MM:{ *:[i32] } (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), 1:{ *:[i32] })
16558          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16559          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu_MM,
16560          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
16561          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
16562          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
16563          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16564          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi_MM,
16565          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
16566          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16567          GIR_AddImm, /*InsnID*/0, /*Imm*/1,
16568          GIR_EraseFromParent, /*InsnID*/0,
16569          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16570          // GIR_Coverage, 2167,
16571          GIR_Done,
16572        // Label 1009: @39897
16573        GIM_Try, /*On fail goto*//*Label 1010*/ 39937, // Rule ID 2168 //
16574          GIM_CheckFeatures, GIFBS_InMicroMips,
16575          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
16576          // MIs[0] Operand 1
16577          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT,
16578          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
16579          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
16580          // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGT:{ *:[Other] })  =>  (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs)
16581          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLT_MM,
16582          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
16583          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rhs
16584          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // lhs
16585          GIR_EraseFromParent, /*InsnID*/0,
16586          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16587          // GIR_Coverage, 2168,
16588          GIR_Done,
16589        // Label 1010: @39937
16590        GIM_Try, /*On fail goto*//*Label 1011*/ 39977, // Rule ID 2169 //
16591          GIM_CheckFeatures, GIFBS_InMicroMips,
16592          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
16593          // MIs[0] Operand 1
16594          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT,
16595          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
16596          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
16597          // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGT:{ *:[Other] })  =>  (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs)
16598          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTu_MM,
16599          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
16600          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rhs
16601          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // lhs
16602          GIR_EraseFromParent, /*InsnID*/0,
16603          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16604          // GIR_Coverage, 2169,
16605          GIR_Done,
16606        // Label 1011: @39977
16607        GIM_Try, /*On fail goto*//*Label 1012*/ 40036, // Rule ID 2170 //
16608          GIM_CheckFeatures, GIFBS_InMicroMips,
16609          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
16610          // MIs[0] Operand 1
16611          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
16612          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
16613          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
16614          // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] })  =>  (XORi_MM:{ *:[i32] } (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] })
16615          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16616          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT_MM,
16617          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
16618          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
16619          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
16620          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16621          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi_MM,
16622          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
16623          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16624          GIR_AddImm, /*InsnID*/0, /*Imm*/1,
16625          GIR_EraseFromParent, /*InsnID*/0,
16626          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16627          // GIR_Coverage, 2170,
16628          GIR_Done,
16629        // Label 1012: @40036
16630        GIM_Try, /*On fail goto*//*Label 1013*/ 40095, // Rule ID 2171 //
16631          GIM_CheckFeatures, GIFBS_InMicroMips,
16632          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
16633          // MIs[0] Operand 1
16634          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
16635          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
16636          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
16637          // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] })  =>  (XORi_MM:{ *:[i32] } (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] })
16638          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16639          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu_MM,
16640          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
16641          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
16642          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
16643          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16644          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi_MM,
16645          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
16646          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16647          GIR_AddImm, /*InsnID*/0, /*Imm*/1,
16648          GIR_EraseFromParent, /*InsnID*/0,
16649          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16650          // GIR_Coverage, 2171,
16651          GIR_Done,
16652        // Label 1013: @40095
16653        GIM_Reject,
16654      // Label 995: @40096
16655      GIM_Reject,
16656    // Label 949: @40097
16657    GIM_Reject,
16658    // Label 28: @40098
16659    GIM_Try, /*On fail goto*//*Label 1014*/ 41817,
16660      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
16661      GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/1, 3, /*)*//*default:*//*Label 1017*/ 40640,
16662      /*GILLT_s32*//*Label 1015*/ 40112,
16663      /*GILLT_s64*//*Label 1016*/ 40376,
16664      // Label 1015: @40112
16665      GIM_Try, /*On fail goto*//*Label 1018*/ 40375,
16666        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16667        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGRCCRegClassID,
16668        GIM_Try, /*On fail goto*//*Label 1019*/ 40158, // Rule ID 300 //
16669          GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
16670          // MIs[0] Operand 1
16671          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNO,
16672          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
16673          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
16674          // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETUO:{ *:[Other] })  =>  (CMP_UN_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
16675          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_UN_S,
16676          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
16677          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs
16678          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft
16679          GIR_EraseFromParent, /*InsnID*/0,
16680          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16681          // GIR_Coverage, 300,
16682          GIR_Done,
16683        // Label 1019: @40158
16684        GIM_Try, /*On fail goto*//*Label 1020*/ 40194, // Rule ID 301 //
16685          GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
16686          // MIs[0] Operand 1
16687          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OEQ,
16688          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
16689          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
16690          // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETOEQ:{ *:[Other] })  =>  (CMP_EQ_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
16691          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_EQ_S,
16692          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
16693          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs
16694          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft
16695          GIR_EraseFromParent, /*InsnID*/0,
16696          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16697          // GIR_Coverage, 301,
16698          GIR_Done,
16699        // Label 1020: @40194
16700        GIM_Try, /*On fail goto*//*Label 1021*/ 40230, // Rule ID 302 //
16701          GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
16702          // MIs[0] Operand 1
16703          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UEQ,
16704          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
16705          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
16706          // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETUEQ:{ *:[Other] })  =>  (CMP_UEQ_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
16707          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_UEQ_S,
16708          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
16709          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs
16710          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft
16711          GIR_EraseFromParent, /*InsnID*/0,
16712          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16713          // GIR_Coverage, 302,
16714          GIR_Done,
16715        // Label 1021: @40230
16716        GIM_Try, /*On fail goto*//*Label 1022*/ 40266, // Rule ID 303 //
16717          GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
16718          // MIs[0] Operand 1
16719          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLT,
16720          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
16721          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
16722          // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETOLT:{ *:[Other] })  =>  (CMP_LT_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
16723          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LT_S,
16724          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
16725          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs
16726          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft
16727          GIR_EraseFromParent, /*InsnID*/0,
16728          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16729          // GIR_Coverage, 303,
16730          GIR_Done,
16731        // Label 1022: @40266
16732        GIM_Try, /*On fail goto*//*Label 1023*/ 40302, // Rule ID 304 //
16733          GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
16734          // MIs[0] Operand 1
16735          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ULT,
16736          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
16737          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
16738          // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETULT:{ *:[Other] })  =>  (CMP_ULT_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
16739          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_ULT_S,
16740          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
16741          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs
16742          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft
16743          GIR_EraseFromParent, /*InsnID*/0,
16744          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16745          // GIR_Coverage, 304,
16746          GIR_Done,
16747        // Label 1023: @40302
16748        GIM_Try, /*On fail goto*//*Label 1024*/ 40338, // Rule ID 305 //
16749          GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
16750          // MIs[0] Operand 1
16751          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLE,
16752          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
16753          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
16754          // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETOLE:{ *:[Other] })  =>  (CMP_LE_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
16755          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LE_S,
16756          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
16757          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs
16758          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft
16759          GIR_EraseFromParent, /*InsnID*/0,
16760          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16761          // GIR_Coverage, 305,
16762          GIR_Done,
16763        // Label 1024: @40338
16764        GIM_Try, /*On fail goto*//*Label 1025*/ 40374, // Rule ID 306 //
16765          GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
16766          // MIs[0] Operand 1
16767          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ULE,
16768          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
16769          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
16770          // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETULE:{ *:[Other] })  =>  (CMP_ULE_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
16771          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_ULE_S,
16772          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
16773          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs
16774          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft
16775          GIR_EraseFromParent, /*InsnID*/0,
16776          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16777          // GIR_Coverage, 306,
16778          GIR_Done,
16779        // Label 1025: @40374
16780        GIM_Reject,
16781      // Label 1018: @40375
16782      GIM_Reject,
16783      // Label 1016: @40376
16784      GIM_Try, /*On fail goto*//*Label 1026*/ 40639,
16785        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
16786        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGRCCRegClassID,
16787        GIM_Try, /*On fail goto*//*Label 1027*/ 40422, // Rule ID 307 //
16788          GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
16789          // MIs[0] Operand 1
16790          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNO,
16791          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
16792          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
16793          // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETUO:{ *:[Other] })  =>  (CMP_UN_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
16794          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_UN_D,
16795          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
16796          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs
16797          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft
16798          GIR_EraseFromParent, /*InsnID*/0,
16799          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16800          // GIR_Coverage, 307,
16801          GIR_Done,
16802        // Label 1027: @40422
16803        GIM_Try, /*On fail goto*//*Label 1028*/ 40458, // Rule ID 308 //
16804          GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
16805          // MIs[0] Operand 1
16806          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OEQ,
16807          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
16808          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
16809          // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETOEQ:{ *:[Other] })  =>  (CMP_EQ_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
16810          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_EQ_D,
16811          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
16812          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs
16813          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft
16814          GIR_EraseFromParent, /*InsnID*/0,
16815          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16816          // GIR_Coverage, 308,
16817          GIR_Done,
16818        // Label 1028: @40458
16819        GIM_Try, /*On fail goto*//*Label 1029*/ 40494, // Rule ID 309 //
16820          GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
16821          // MIs[0] Operand 1
16822          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UEQ,
16823          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
16824          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
16825          // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETUEQ:{ *:[Other] })  =>  (CMP_UEQ_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
16826          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_UEQ_D,
16827          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
16828          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs
16829          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft
16830          GIR_EraseFromParent, /*InsnID*/0,
16831          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16832          // GIR_Coverage, 309,
16833          GIR_Done,
16834        // Label 1029: @40494
16835        GIM_Try, /*On fail goto*//*Label 1030*/ 40530, // Rule ID 310 //
16836          GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
16837          // MIs[0] Operand 1
16838          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLT,
16839          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
16840          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
16841          // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETOLT:{ *:[Other] })  =>  (CMP_LT_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
16842          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LT_D,
16843          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
16844          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs
16845          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft
16846          GIR_EraseFromParent, /*InsnID*/0,
16847          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16848          // GIR_Coverage, 310,
16849          GIR_Done,
16850        // Label 1030: @40530
16851        GIM_Try, /*On fail goto*//*Label 1031*/ 40566, // Rule ID 311 //
16852          GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
16853          // MIs[0] Operand 1
16854          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ULT,
16855          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
16856          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
16857          // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETULT:{ *:[Other] })  =>  (CMP_ULT_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
16858          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_ULT_D,
16859          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
16860          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs
16861          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft
16862          GIR_EraseFromParent, /*InsnID*/0,
16863          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16864          // GIR_Coverage, 311,
16865          GIR_Done,
16866        // Label 1031: @40566
16867        GIM_Try, /*On fail goto*//*Label 1032*/ 40602, // Rule ID 312 //
16868          GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
16869          // MIs[0] Operand 1
16870          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLE,
16871          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
16872          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
16873          // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETOLE:{ *:[Other] })  =>  (CMP_LE_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
16874          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LE_D,
16875          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
16876          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs
16877          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft
16878          GIR_EraseFromParent, /*InsnID*/0,
16879          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16880          // GIR_Coverage, 312,
16881          GIR_Done,
16882        // Label 1032: @40602
16883        GIM_Try, /*On fail goto*//*Label 1033*/ 40638, // Rule ID 313 //
16884          GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
16885          // MIs[0] Operand 1
16886          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ULE,
16887          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
16888          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
16889          // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETULE:{ *:[Other] })  =>  (CMP_ULE_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
16890          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_ULE_D,
16891          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
16892          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs
16893          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft
16894          GIR_EraseFromParent, /*InsnID*/0,
16895          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16896          // GIR_Coverage, 313,
16897          GIR_Done,
16898        // Label 1033: @40638
16899        GIM_Reject,
16900      // Label 1026: @40639
16901      GIM_Reject,
16902      // Label 1017: @40640
16903      GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/1, 3, /*)*//*default:*//*Label 1036*/ 41176,
16904      /*GILLT_s32*//*Label 1034*/ 40648,
16905      /*GILLT_s64*//*Label 1035*/ 40912,
16906      // Label 1034: @40648
16907      GIM_Try, /*On fail goto*//*Label 1037*/ 40911,
16908        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16909        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGRCCRegClassID,
16910        GIM_Try, /*On fail goto*//*Label 1038*/ 40694, // Rule ID 1181 //
16911          GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
16912          // MIs[0] Operand 1
16913          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNO,
16914          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
16915          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
16916          // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETUO:{ *:[Other] })  =>  (CMP_UN_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
16917          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_UN_S_MMR6,
16918          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
16919          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs
16920          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft
16921          GIR_EraseFromParent, /*InsnID*/0,
16922          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16923          // GIR_Coverage, 1181,
16924          GIR_Done,
16925        // Label 1038: @40694
16926        GIM_Try, /*On fail goto*//*Label 1039*/ 40730, // Rule ID 1182 //
16927          GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
16928          // MIs[0] Operand 1
16929          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OEQ,
16930          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
16931          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
16932          // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETOEQ:{ *:[Other] })  =>  (CMP_EQ_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
16933          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_EQ_S_MMR6,
16934          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
16935          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs
16936          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft
16937          GIR_EraseFromParent, /*InsnID*/0,
16938          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16939          // GIR_Coverage, 1182,
16940          GIR_Done,
16941        // Label 1039: @40730
16942        GIM_Try, /*On fail goto*//*Label 1040*/ 40766, // Rule ID 1183 //
16943          GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
16944          // MIs[0] Operand 1
16945          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UEQ,
16946          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
16947          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
16948          // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETUEQ:{ *:[Other] })  =>  (CMP_UEQ_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
16949          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_UEQ_S_MMR6,
16950          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
16951          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs
16952          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft
16953          GIR_EraseFromParent, /*InsnID*/0,
16954          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16955          // GIR_Coverage, 1183,
16956          GIR_Done,
16957        // Label 1040: @40766
16958        GIM_Try, /*On fail goto*//*Label 1041*/ 40802, // Rule ID 1184 //
16959          GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
16960          // MIs[0] Operand 1
16961          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLT,
16962          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
16963          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
16964          // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETOLT:{ *:[Other] })  =>  (CMP_LT_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
16965          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LT_S_MMR6,
16966          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
16967          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs
16968          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft
16969          GIR_EraseFromParent, /*InsnID*/0,
16970          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16971          // GIR_Coverage, 1184,
16972          GIR_Done,
16973        // Label 1041: @40802
16974        GIM_Try, /*On fail goto*//*Label 1042*/ 40838, // Rule ID 1185 //
16975          GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
16976          // MIs[0] Operand 1
16977          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ULT,
16978          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
16979          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
16980          // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETULT:{ *:[Other] })  =>  (CMP_ULT_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
16981          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_ULT_S_MMR6,
16982          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
16983          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs
16984          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft
16985          GIR_EraseFromParent, /*InsnID*/0,
16986          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16987          // GIR_Coverage, 1185,
16988          GIR_Done,
16989        // Label 1042: @40838
16990        GIM_Try, /*On fail goto*//*Label 1043*/ 40874, // Rule ID 1186 //
16991          GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
16992          // MIs[0] Operand 1
16993          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLE,
16994          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
16995          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
16996          // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETOLE:{ *:[Other] })  =>  (CMP_LE_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
16997          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LE_S_MMR6,
16998          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
16999          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs
17000          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft
17001          GIR_EraseFromParent, /*InsnID*/0,
17002          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17003          // GIR_Coverage, 1186,
17004          GIR_Done,
17005        // Label 1043: @40874
17006        GIM_Try, /*On fail goto*//*Label 1044*/ 40910, // Rule ID 1187 //
17007          GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
17008          // MIs[0] Operand 1
17009          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ULE,
17010          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
17011          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
17012          // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETULE:{ *:[Other] })  =>  (CMP_ULE_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
17013          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_ULE_S_MMR6,
17014          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
17015          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs
17016          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft
17017          GIR_EraseFromParent, /*InsnID*/0,
17018          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17019          // GIR_Coverage, 1187,
17020          GIR_Done,
17021        // Label 1044: @40910
17022        GIM_Reject,
17023      // Label 1037: @40911
17024      GIM_Reject,
17025      // Label 1035: @40912
17026      GIM_Try, /*On fail goto*//*Label 1045*/ 41175,
17027        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
17028        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGRCCRegClassID,
17029        GIM_Try, /*On fail goto*//*Label 1046*/ 40958, // Rule ID 1188 //
17030          GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
17031          // MIs[0] Operand 1
17032          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNO,
17033          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
17034          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
17035          // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETUO:{ *:[Other] })  =>  (CMP_UN_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
17036          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_UN_D_MMR6,
17037          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
17038          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs
17039          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft
17040          GIR_EraseFromParent, /*InsnID*/0,
17041          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17042          // GIR_Coverage, 1188,
17043          GIR_Done,
17044        // Label 1046: @40958
17045        GIM_Try, /*On fail goto*//*Label 1047*/ 40994, // Rule ID 1189 //
17046          GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
17047          // MIs[0] Operand 1
17048          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OEQ,
17049          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
17050          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
17051          // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETOEQ:{ *:[Other] })  =>  (CMP_EQ_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
17052          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_EQ_D_MMR6,
17053          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
17054          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs
17055          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft
17056          GIR_EraseFromParent, /*InsnID*/0,
17057          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17058          // GIR_Coverage, 1189,
17059          GIR_Done,
17060        // Label 1047: @40994
17061        GIM_Try, /*On fail goto*//*Label 1048*/ 41030, // Rule ID 1190 //
17062          GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
17063          // MIs[0] Operand 1
17064          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UEQ,
17065          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
17066          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
17067          // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETUEQ:{ *:[Other] })  =>  (CMP_UEQ_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
17068          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_UEQ_D_MMR6,
17069          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
17070          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs
17071          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft
17072          GIR_EraseFromParent, /*InsnID*/0,
17073          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17074          // GIR_Coverage, 1190,
17075          GIR_Done,
17076        // Label 1048: @41030
17077        GIM_Try, /*On fail goto*//*Label 1049*/ 41066, // Rule ID 1191 //
17078          GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
17079          // MIs[0] Operand 1
17080          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLT,
17081          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
17082          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
17083          // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETOLT:{ *:[Other] })  =>  (CMP_LT_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
17084          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LT_D_MMR6,
17085          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
17086          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs
17087          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft
17088          GIR_EraseFromParent, /*InsnID*/0,
17089          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17090          // GIR_Coverage, 1191,
17091          GIR_Done,
17092        // Label 1049: @41066
17093        GIM_Try, /*On fail goto*//*Label 1050*/ 41102, // Rule ID 1192 //
17094          GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
17095          // MIs[0] Operand 1
17096          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ULT,
17097          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
17098          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
17099          // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETULT:{ *:[Other] })  =>  (CMP_ULT_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
17100          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_ULT_D_MMR6,
17101          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
17102          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs
17103          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft
17104          GIR_EraseFromParent, /*InsnID*/0,
17105          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17106          // GIR_Coverage, 1192,
17107          GIR_Done,
17108        // Label 1050: @41102
17109        GIM_Try, /*On fail goto*//*Label 1051*/ 41138, // Rule ID 1193 //
17110          GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
17111          // MIs[0] Operand 1
17112          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLE,
17113          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
17114          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
17115          // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETOLE:{ *:[Other] })  =>  (CMP_LE_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
17116          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LE_D_MMR6,
17117          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
17118          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs
17119          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft
17120          GIR_EraseFromParent, /*InsnID*/0,
17121          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17122          // GIR_Coverage, 1193,
17123          GIR_Done,
17124        // Label 1051: @41138
17125        GIM_Try, /*On fail goto*//*Label 1052*/ 41174, // Rule ID 1194 //
17126          GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
17127          // MIs[0] Operand 1
17128          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ULE,
17129          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
17130          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
17131          // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETULE:{ *:[Other] })  =>  (CMP_ULE_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
17132          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_ULE_D_MMR6,
17133          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
17134          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs
17135          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft
17136          GIR_EraseFromParent, /*InsnID*/0,
17137          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17138          // GIR_Coverage, 1194,
17139          GIR_Done,
17140        // Label 1052: @41174
17141        GIM_Reject,
17142      // Label 1045: @41175
17143      GIM_Reject,
17144      // Label 1036: @41176
17145      GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/1, 3, /*)*//*default:*//*Label 1055*/ 41496,
17146      /*GILLT_s32*//*Label 1053*/ 41184,
17147      /*GILLT_s64*//*Label 1054*/ 41340,
17148      // Label 1053: @41184
17149      GIM_Try, /*On fail goto*//*Label 1056*/ 41339,
17150        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17151        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
17152        GIM_Try, /*On fail goto*//*Label 1057*/ 41242, // Rule ID 1723 //
17153          GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
17154          // MIs[0] Operand 1
17155          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ONE,
17156          // (setcc:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs, SETONE:{ *:[Other] })  =>  (NOR:{ *:[i32] } (CMP_UEQ_S:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs), ZERO:{ *:[i32] })
17157          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17158          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::CMP_UEQ_S,
17159          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
17160          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
17161          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
17162          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17163          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR,
17164          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
17165          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
17166          GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0,
17167          GIR_EraseFromParent, /*InsnID*/0,
17168          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17169          // GIR_Coverage, 1723,
17170          GIR_Done,
17171        // Label 1057: @41242
17172        GIM_Try, /*On fail goto*//*Label 1058*/ 41290, // Rule ID 1724 //
17173          GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
17174          // MIs[0] Operand 1
17175          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ORD,
17176          // (setcc:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs, SETO:{ *:[Other] })  =>  (NOR:{ *:[i32] } (CMP_UN_S:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs), ZERO:{ *:[i32] })
17177          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17178          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::CMP_UN_S,
17179          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
17180          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
17181          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
17182          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17183          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR,
17184          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
17185          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
17186          GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0,
17187          GIR_EraseFromParent, /*InsnID*/0,
17188          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17189          // GIR_Coverage, 1724,
17190          GIR_Done,
17191        // Label 1058: @41290
17192        GIM_Try, /*On fail goto*//*Label 1059*/ 41338, // Rule ID 1725 //
17193          GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
17194          // MIs[0] Operand 1
17195          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE,
17196          // (setcc:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs, SETUNE:{ *:[Other] })  =>  (NOR:{ *:[i32] } (CMP_EQ_S:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs), ZERO:{ *:[i32] })
17197          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17198          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::CMP_EQ_S,
17199          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
17200          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
17201          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
17202          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17203          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR,
17204          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
17205          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
17206          GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0,
17207          GIR_EraseFromParent, /*InsnID*/0,
17208          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17209          // GIR_Coverage, 1725,
17210          GIR_Done,
17211        // Label 1059: @41338
17212        GIM_Reject,
17213      // Label 1056: @41339
17214      GIM_Reject,
17215      // Label 1054: @41340
17216      GIM_Try, /*On fail goto*//*Label 1060*/ 41495,
17217        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
17218        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
17219        GIM_Try, /*On fail goto*//*Label 1061*/ 41398, // Rule ID 1732 //
17220          GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
17221          // MIs[0] Operand 1
17222          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ONE,
17223          // (setcc:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs, SETONE:{ *:[Other] })  =>  (NOR:{ *:[i32] } (CMP_UEQ_D:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs), ZERO:{ *:[i32] })
17224          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17225          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::CMP_UEQ_D,
17226          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
17227          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
17228          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
17229          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17230          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR,
17231          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
17232          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
17233          GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0,
17234          GIR_EraseFromParent, /*InsnID*/0,
17235          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17236          // GIR_Coverage, 1732,
17237          GIR_Done,
17238        // Label 1061: @41398
17239        GIM_Try, /*On fail goto*//*Label 1062*/ 41446, // Rule ID 1733 //
17240          GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
17241          // MIs[0] Operand 1
17242          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ORD,
17243          // (setcc:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs, SETO:{ *:[Other] })  =>  (NOR:{ *:[i32] } (CMP_UN_D:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs), ZERO:{ *:[i32] })
17244          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17245          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::CMP_UN_D,
17246          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
17247          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
17248          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
17249          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17250          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR,
17251          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
17252          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
17253          GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0,
17254          GIR_EraseFromParent, /*InsnID*/0,
17255          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17256          // GIR_Coverage, 1733,
17257          GIR_Done,
17258        // Label 1062: @41446
17259        GIM_Try, /*On fail goto*//*Label 1063*/ 41494, // Rule ID 1734 //
17260          GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
17261          // MIs[0] Operand 1
17262          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE,
17263          // (setcc:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs, SETUNE:{ *:[Other] })  =>  (NOR:{ *:[i32] } (CMP_EQ_D:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs), ZERO:{ *:[i32] })
17264          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17265          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::CMP_EQ_D,
17266          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
17267          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
17268          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
17269          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17270          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR,
17271          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
17272          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
17273          GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0,
17274          GIR_EraseFromParent, /*InsnID*/0,
17275          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17276          // GIR_Coverage, 1734,
17277          GIR_Done,
17278        // Label 1063: @41494
17279        GIM_Reject,
17280      // Label 1060: @41495
17281      GIM_Reject,
17282      // Label 1055: @41496
17283      GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/1, 3, /*)*//*default:*//*Label 1066*/ 41816,
17284      /*GILLT_s32*//*Label 1064*/ 41504,
17285      /*GILLT_s64*//*Label 1065*/ 41660,
17286      // Label 1064: @41504
17287      GIM_Try, /*On fail goto*//*Label 1067*/ 41659,
17288        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17289        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
17290        GIM_Try, /*On fail goto*//*Label 1068*/ 41562, // Rule ID 2263 //
17291          GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
17292          // MIs[0] Operand 1
17293          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ONE,
17294          // (setcc:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs, SETONE:{ *:[Other] })  =>  (NOR_MMR6:{ *:[i32] } (CMP_UEQ_S_MMR6:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs), ZERO:{ *:[i32] })
17295          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17296          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::CMP_UEQ_S_MMR6,
17297          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
17298          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
17299          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
17300          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17301          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MMR6,
17302          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
17303          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
17304          GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0,
17305          GIR_EraseFromParent, /*InsnID*/0,
17306          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17307          // GIR_Coverage, 2263,
17308          GIR_Done,
17309        // Label 1068: @41562
17310        GIM_Try, /*On fail goto*//*Label 1069*/ 41610, // Rule ID 2264 //
17311          GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
17312          // MIs[0] Operand 1
17313          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ORD,
17314          // (setcc:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs, SETO:{ *:[Other] })  =>  (NOR_MMR6:{ *:[i32] } (CMP_UN_S_MMR6:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs), ZERO:{ *:[i32] })
17315          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17316          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::CMP_UN_S_MMR6,
17317          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
17318          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
17319          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
17320          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17321          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MMR6,
17322          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
17323          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
17324          GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0,
17325          GIR_EraseFromParent, /*InsnID*/0,
17326          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17327          // GIR_Coverage, 2264,
17328          GIR_Done,
17329        // Label 1069: @41610
17330        GIM_Try, /*On fail goto*//*Label 1070*/ 41658, // Rule ID 2265 //
17331          GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
17332          // MIs[0] Operand 1
17333          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE,
17334          // (setcc:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs, SETUNE:{ *:[Other] })  =>  (NOR_MMR6:{ *:[i32] } (CMP_EQ_S_MMR6:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs), ZERO:{ *:[i32] })
17335          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17336          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::CMP_EQ_S_MMR6,
17337          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
17338          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
17339          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
17340          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17341          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MMR6,
17342          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
17343          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
17344          GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0,
17345          GIR_EraseFromParent, /*InsnID*/0,
17346          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17347          // GIR_Coverage, 2265,
17348          GIR_Done,
17349        // Label 1070: @41658
17350        GIM_Reject,
17351      // Label 1067: @41659
17352      GIM_Reject,
17353      // Label 1065: @41660
17354      GIM_Try, /*On fail goto*//*Label 1071*/ 41815,
17355        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
17356        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
17357        GIM_Try, /*On fail goto*//*Label 1072*/ 41718, // Rule ID 2272 //
17358          GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
17359          // MIs[0] Operand 1
17360          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ONE,
17361          // (setcc:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs, SETONE:{ *:[Other] })  =>  (NOR_MMR6:{ *:[i32] } (CMP_UEQ_D_MMR6:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs), ZERO:{ *:[i32] })
17362          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17363          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::CMP_UEQ_D_MMR6,
17364          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
17365          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
17366          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
17367          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17368          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MMR6,
17369          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
17370          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
17371          GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0,
17372          GIR_EraseFromParent, /*InsnID*/0,
17373          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17374          // GIR_Coverage, 2272,
17375          GIR_Done,
17376        // Label 1072: @41718
17377        GIM_Try, /*On fail goto*//*Label 1073*/ 41766, // Rule ID 2273 //
17378          GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
17379          // MIs[0] Operand 1
17380          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ORD,
17381          // (setcc:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs, SETO:{ *:[Other] })  =>  (NOR_MMR6:{ *:[i32] } (CMP_UN_D_MMR6:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs), ZERO:{ *:[i32] })
17382          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17383          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::CMP_UN_D_MMR6,
17384          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
17385          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
17386          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
17387          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17388          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MMR6,
17389          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
17390          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
17391          GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0,
17392          GIR_EraseFromParent, /*InsnID*/0,
17393          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17394          // GIR_Coverage, 2273,
17395          GIR_Done,
17396        // Label 1073: @41766
17397        GIM_Try, /*On fail goto*//*Label 1074*/ 41814, // Rule ID 2274 //
17398          GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
17399          // MIs[0] Operand 1
17400          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE,
17401          // (setcc:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs, SETUNE:{ *:[Other] })  =>  (NOR_MMR6:{ *:[i32] } (CMP_EQ_D_MMR6:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs), ZERO:{ *:[i32] })
17402          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17403          GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::CMP_EQ_D_MMR6,
17404          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
17405          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
17406          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
17407          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17408          GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MMR6,
17409          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
17410          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
17411          GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0,
17412          GIR_EraseFromParent, /*InsnID*/0,
17413          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17414          // GIR_Coverage, 2274,
17415          GIR_Done,
17416        // Label 1074: @41814
17417        GIM_Reject,
17418      // Label 1071: @41815
17419      GIM_Reject,
17420      // Label 1066: @41816
17421      GIM_Reject,
17422    // Label 1014: @41817
17423    GIM_Reject,
17424    // Label 29: @41818
17425    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1077*/ 54097,
17426    /*GILLT_s32*//*Label 1075*/ 41826,
17427    /*GILLT_s64*//*Label 1076*/ 48843,
17428    // Label 1075: @41826
17429    GIM_Try, /*On fail goto*//*Label 1078*/ 41907, // Rule ID 1611 //
17430      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
17431      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
17432      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17433      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17434      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
17435      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17436      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
17437      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
17438      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
17439      // MIs[1] Operand 1
17440      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
17441      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
17442      GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0,
17443      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
17444      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
17445      GIM_CheckIsSafeToFold, /*InsnID*/1,
17446      // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F)
17447      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I,
17448      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
17449      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
17450      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
17451      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
17452      GIR_EraseFromParent, /*InsnID*/0,
17453      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17454      // GIR_Coverage, 1611,
17455      GIR_Done,
17456    // Label 1078: @41907
17457    GIM_Try, /*On fail goto*//*Label 1079*/ 41988, // Rule ID 1615 //
17458      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
17459      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
17460      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17461      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17462      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
17463      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17464      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
17465      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
17466      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
17467      // MIs[1] Operand 1
17468      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
17469      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
17470      GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0,
17471      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
17472      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
17473      GIM_CheckIsSafeToFold, /*InsnID*/1,
17474      // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVN_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F)
17475      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_I,
17476      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
17477      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
17478      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
17479      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
17480      GIR_EraseFromParent, /*InsnID*/0,
17481      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17482      // GIR_Coverage, 1615,
17483      GIR_Done,
17484    // Label 1079: @41988
17485    GIM_Try, /*On fail goto*//*Label 1080*/ 42069, // Rule ID 1643 //
17486      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
17487      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
17488      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17489      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17490      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
17491      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17492      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
17493      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
17494      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
17495      // MIs[1] Operand 1
17496      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
17497      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
17498      GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0,
17499      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
17500      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
17501      GIM_CheckIsSafeToFold, /*InsnID*/1,
17502      // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I64_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR64:{ *:[i64] }:$lhs, GPR32:{ *:[i32] }:$F)
17503      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I64_I,
17504      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
17505      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
17506      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
17507      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
17508      GIR_EraseFromParent, /*InsnID*/0,
17509      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17510      // GIR_Coverage, 1643,
17511      GIR_Done,
17512    // Label 1080: @42069
17513    GIM_Try, /*On fail goto*//*Label 1081*/ 42150, // Rule ID 1654 //
17514      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
17515      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
17516      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17517      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17518      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
17519      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17520      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
17521      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
17522      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
17523      // MIs[1] Operand 1
17524      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
17525      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
17526      GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0,
17527      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
17528      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
17529      GIM_CheckIsSafeToFold, /*InsnID*/1,
17530      // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVN_I64_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR64:{ *:[i64] }:$lhs, GPR32:{ *:[i32] }:$F)
17531      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_I,
17532      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
17533      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
17534      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
17535      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
17536      GIR_EraseFromParent, /*InsnID*/0,
17537      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17538      // GIR_Coverage, 1654,
17539      GIR_Done,
17540    // Label 1081: @42150
17541    GIM_Try, /*On fail goto*//*Label 1082*/ 42231, // Rule ID 1667 //
17542      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
17543      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
17544      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17545      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17546      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
17547      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17548      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
17549      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
17550      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
17551      // MIs[1] Operand 1
17552      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
17553      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
17554      GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0,
17555      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
17556      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
17557      GIM_CheckIsSafeToFold, /*InsnID*/1,
17558      // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$lhs, FGR32:{ *:[f32] }:$F)
17559      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S,
17560      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
17561      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
17562      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
17563      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
17564      GIR_EraseFromParent, /*InsnID*/0,
17565      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17566      // GIR_Coverage, 1667,
17567      GIR_Done,
17568    // Label 1082: @42231
17569    GIM_Try, /*On fail goto*//*Label 1083*/ 42312, // Rule ID 1670 //
17570      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
17571      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
17572      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17573      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17574      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
17575      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17576      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
17577      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
17578      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
17579      // MIs[1] Operand 1
17580      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
17581      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
17582      GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0,
17583      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
17584      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
17585      GIM_CheckIsSafeToFold, /*InsnID*/1,
17586      // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVN_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$lhs, FGR32:{ *:[f32] }:$F)
17587      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_S,
17588      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
17589      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
17590      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
17591      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
17592      GIR_EraseFromParent, /*InsnID*/0,
17593      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17594      // GIR_Coverage, 1670,
17595      GIR_Done,
17596    // Label 1083: @42312
17597    GIM_Try, /*On fail goto*//*Label 1084*/ 42393, // Rule ID 1680 //
17598      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
17599      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
17600      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17601      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17602      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
17603      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17604      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
17605      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
17606      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
17607      // MIs[1] Operand 1
17608      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
17609      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
17610      GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0,
17611      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
17612      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
17613      GIM_CheckIsSafeToFold, /*InsnID*/1,
17614      // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVZ_I64_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR64:{ *:[i64] }:$lhs, FGR32:{ *:[f32] }:$F)
17615      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I64_S,
17616      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
17617      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
17618      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
17619      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
17620      GIR_EraseFromParent, /*InsnID*/0,
17621      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17622      // GIR_Coverage, 1680,
17623      GIR_Done,
17624    // Label 1084: @42393
17625    GIM_Try, /*On fail goto*//*Label 1085*/ 42474, // Rule ID 1683 //
17626      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
17627      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
17628      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17629      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17630      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
17631      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17632      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
17633      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
17634      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
17635      // MIs[1] Operand 1
17636      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
17637      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
17638      GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0,
17639      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
17640      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
17641      GIM_CheckIsSafeToFold, /*InsnID*/1,
17642      // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVN_I64_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR64:{ *:[i64] }:$lhs, FGR32:{ *:[f32] }:$F)
17643      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_S,
17644      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
17645      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
17646      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
17647      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
17648      GIR_EraseFromParent, /*InsnID*/0,
17649      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17650      // GIR_Coverage, 1683,
17651      GIR_Done,
17652    // Label 1085: @42474
17653    GIM_Try, /*On fail goto*//*Label 1086*/ 42555, // Rule ID 1836 //
17654      GIM_CheckFeatures, GIFBS_InMips16Mode,
17655      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
17656      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17657      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17658      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
17659      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17660      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
17661      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
17662      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
17663      // MIs[1] Operand 1
17664      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
17665      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
17666      GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0,
17667      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
17668      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID,
17669      GIM_CheckIsSafeToFold, /*InsnID*/1,
17670      // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y)  =>  (SelBeqZ:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$a)
17671      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SelBeqZ,
17672      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd_
17673      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // x
17674      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // y
17675      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
17676      GIR_EraseFromParent, /*InsnID*/0,
17677      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17678      // GIR_Coverage, 1836,
17679      GIR_Done,
17680    // Label 1086: @42555
17681    GIM_Try, /*On fail goto*//*Label 1087*/ 42636, // Rule ID 1839 //
17682      GIM_CheckFeatures, GIFBS_InMips16Mode,
17683      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
17684      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17685      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17686      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
17687      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17688      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
17689      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
17690      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
17691      // MIs[1] Operand 1
17692      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
17693      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
17694      GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0,
17695      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
17696      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID,
17697      GIM_CheckIsSafeToFold, /*InsnID*/1,
17698      // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, 0:{ *:[i32] }, SETNE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y)  =>  (SelBneZ:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$a)
17699      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SelBneZ,
17700      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd_
17701      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // x
17702      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // y
17703      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
17704      GIR_EraseFromParent, /*InsnID*/0,
17705      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17706      // GIR_Coverage, 1839,
17707      GIR_Done,
17708    // Label 1087: @42636
17709    GIM_Try, /*On fail goto*//*Label 1088*/ 42717, // Rule ID 2183 //
17710      GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
17711      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
17712      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17713      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17714      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
17715      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17716      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
17717      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
17718      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
17719      // MIs[1] Operand 1
17720      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
17721      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
17722      GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0,
17723      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
17724      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
17725      GIM_CheckIsSafeToFold, /*InsnID*/1,
17726      // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F)
17727      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_MM,
17728      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
17729      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
17730      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
17731      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
17732      GIR_EraseFromParent, /*InsnID*/0,
17733      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17734      // GIR_Coverage, 2183,
17735      GIR_Done,
17736    // Label 1088: @42717
17737    GIM_Try, /*On fail goto*//*Label 1089*/ 42798, // Rule ID 2187 //
17738      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotMips32r6_NotMips64r6,
17739      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
17740      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17741      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17742      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
17743      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17744      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
17745      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
17746      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
17747      // MIs[1] Operand 1
17748      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
17749      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
17750      GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0,
17751      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
17752      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
17753      GIM_CheckIsSafeToFold, /*InsnID*/1,
17754      // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F)
17755      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_MM,
17756      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
17757      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
17758      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
17759      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
17760      GIR_EraseFromParent, /*InsnID*/0,
17761      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17762      // GIR_Coverage, 2187,
17763      GIR_Done,
17764    // Label 1089: @42798
17765    GIM_Try, /*On fail goto*//*Label 1090*/ 42879, // Rule ID 2197 //
17766      GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
17767      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
17768      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17769      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17770      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
17771      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17772      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
17773      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
17774      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
17775      // MIs[1] Operand 1
17776      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
17777      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
17778      GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0,
17779      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
17780      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
17781      GIM_CheckIsSafeToFold, /*InsnID*/1,
17782      // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F)
17783      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_MM,
17784      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
17785      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
17786      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
17787      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
17788      GIR_EraseFromParent, /*InsnID*/0,
17789      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17790      // GIR_Coverage, 2197,
17791      GIR_Done,
17792    // Label 1090: @42879
17793    GIM_Try, /*On fail goto*//*Label 1091*/ 42960, // Rule ID 2201 //
17794      GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
17795      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
17796      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17797      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17798      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
17799      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17800      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
17801      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
17802      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
17803      // MIs[1] Operand 1
17804      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
17805      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
17806      GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0,
17807      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
17808      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
17809      GIM_CheckIsSafeToFold, /*InsnID*/1,
17810      // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F)
17811      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_MM,
17812      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
17813      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
17814      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
17815      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
17816      GIR_EraseFromParent, /*InsnID*/0,
17817      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17818      // GIR_Coverage, 2201,
17819      GIR_Done,
17820    // Label 1091: @42960
17821    GIM_Try, /*On fail goto*//*Label 1092*/ 43041, // Rule ID 2231 //
17822      GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
17823      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
17824      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17825      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17826      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
17827      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17828      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
17829      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
17830      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
17831      // MIs[1] Operand 1
17832      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
17833      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
17834      GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0,
17835      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
17836      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
17837      GIM_CheckIsSafeToFold, /*InsnID*/1,
17838      // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$lhs, FGR32:{ *:[f32] }:$F)
17839      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S_MM,
17840      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
17841      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
17842      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
17843      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
17844      GIR_EraseFromParent, /*InsnID*/0,
17845      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17846      // GIR_Coverage, 2231,
17847      GIR_Done,
17848    // Label 1092: @43041
17849    GIM_Try, /*On fail goto*//*Label 1093*/ 43122, // Rule ID 2234 //
17850      GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
17851      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
17852      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17853      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17854      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
17855      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17856      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
17857      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
17858      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
17859      // MIs[1] Operand 1
17860      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
17861      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
17862      GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0,
17863      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
17864      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
17865      GIM_CheckIsSafeToFold, /*InsnID*/1,
17866      // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVN_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$lhs, FGR32:{ *:[f32] }:$F)
17867      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_S_MM,
17868      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
17869      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
17870      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
17871      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
17872      GIR_EraseFromParent, /*InsnID*/0,
17873      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17874      // GIR_Coverage, 2234,
17875      GIR_Done,
17876    // Label 1093: @43122
17877    GIM_Try, /*On fail goto*//*Label 1094*/ 43223, // Rule ID 1602 //
17878      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
17879      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
17880      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17881      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17882      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
17883      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17884      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
17885      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
17886      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
17887      // MIs[1] Operand 1
17888      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
17889      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
17890      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
17891      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
17892      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
17893      GIM_CheckIsSafeToFold, /*InsnID*/1,
17894      // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
17895      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17896      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT,
17897      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
17898      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
17899      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
17900      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17901      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I,
17902      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
17903      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
17904      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
17905      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
17906      GIR_EraseFromParent, /*InsnID*/0,
17907      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17908      // GIR_Coverage, 1602,
17909      GIR_Done,
17910    // Label 1094: @43223
17911    GIM_Try, /*On fail goto*//*Label 1095*/ 43324, // Rule ID 1603 //
17912      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
17913      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
17914      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17915      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17916      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
17917      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17918      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
17919      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
17920      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
17921      // MIs[1] Operand 1
17922      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
17923      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
17924      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
17925      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
17926      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
17927      GIM_CheckIsSafeToFold, /*InsnID*/1,
17928      // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
17929      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17930      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu,
17931      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
17932      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
17933      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
17934      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17935      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I,
17936      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
17937      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
17938      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
17939      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
17940      GIR_EraseFromParent, /*InsnID*/0,
17941      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17942      // GIR_Coverage, 1603,
17943      GIR_Done,
17944    // Label 1095: @43324
17945    GIM_Try, /*On fail goto*//*Label 1096*/ 43425, // Rule ID 1606 //
17946      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
17947      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
17948      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17949      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17950      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
17951      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17952      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
17953      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
17954      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
17955      // MIs[1] Operand 1
17956      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
17957      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
17958      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
17959      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
17960      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
17961      GIM_CheckIsSafeToFold, /*InsnID*/1,
17962      // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F)
17963      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17964      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT,
17965      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
17966      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
17967      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
17968      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17969      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I,
17970      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
17971      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
17972      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
17973      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
17974      GIR_EraseFromParent, /*InsnID*/0,
17975      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17976      // GIR_Coverage, 1606,
17977      GIR_Done,
17978    // Label 1096: @43425
17979    GIM_Try, /*On fail goto*//*Label 1097*/ 43526, // Rule ID 1607 //
17980      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
17981      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
17982      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17983      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17984      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
17985      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17986      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
17987      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
17988      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
17989      // MIs[1] Operand 1
17990      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
17991      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
17992      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
17993      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
17994      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
17995      GIM_CheckIsSafeToFold, /*InsnID*/1,
17996      // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F)
17997      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17998      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu,
17999      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
18000      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
18001      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18002      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18003      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I,
18004      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
18005      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
18006      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
18007      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
18008      GIR_EraseFromParent, /*InsnID*/0,
18009      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18010      // GIR_Coverage, 1607,
18011      GIR_Done,
18012    // Label 1097: @43526
18013    GIM_Try, /*On fail goto*//*Label 1098*/ 43627, // Rule ID 1610 //
18014      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
18015      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
18016      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18017      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18018      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
18019      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18020      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
18021      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
18022      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18023      // MIs[1] Operand 1
18024      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
18025      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
18026      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
18027      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
18028      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
18029      GIM_CheckIsSafeToFold, /*InsnID*/1,
18030      // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
18031      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18032      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR,
18033      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
18034      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18035      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
18036      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18037      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I,
18038      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
18039      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
18040      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
18041      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
18042      GIR_EraseFromParent, /*InsnID*/0,
18043      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18044      // GIR_Coverage, 1610,
18045      GIR_Done,
18046    // Label 1098: @43627
18047    GIM_Try, /*On fail goto*//*Label 1099*/ 43728, // Rule ID 1613 //
18048      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
18049      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
18050      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18051      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18052      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
18053      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18054      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
18055      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
18056      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18057      // MIs[1] Operand 1
18058      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
18059      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
18060      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
18061      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
18062      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
18063      GIM_CheckIsSafeToFold, /*InsnID*/1,
18064      // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVN_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
18065      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18066      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR,
18067      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
18068      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18069      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
18070      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18071      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_I,
18072      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
18073      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
18074      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
18075      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
18076      GIR_EraseFromParent, /*InsnID*/0,
18077      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18078      // GIR_Coverage, 1613,
18079      GIR_Done,
18080    // Label 1099: @43728
18081    GIM_Try, /*On fail goto*//*Label 1100*/ 43829, // Rule ID 1624 //
18082      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
18083      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
18084      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18085      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18086      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
18087      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18088      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
18089      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
18090      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
18091      // MIs[1] Operand 1
18092      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
18093      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
18094      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
18095      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
18096      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
18097      GIM_CheckIsSafeToFold, /*InsnID*/1,
18098      // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR32:{ *:[i32] }:$F)
18099      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18100      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT64,
18101      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
18102      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18103      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
18104      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18105      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I,
18106      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
18107      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
18108      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
18109      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
18110      GIR_EraseFromParent, /*InsnID*/0,
18111      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18112      // GIR_Coverage, 1624,
18113      GIR_Done,
18114    // Label 1100: @43829
18115    GIM_Try, /*On fail goto*//*Label 1101*/ 43930, // Rule ID 1625 //
18116      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
18117      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
18118      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18119      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18120      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
18121      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18122      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
18123      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
18124      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
18125      // MIs[1] Operand 1
18126      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
18127      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
18128      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
18129      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
18130      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
18131      GIM_CheckIsSafeToFold, /*InsnID*/1,
18132      // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR32:{ *:[i32] }:$F)
18133      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18134      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu64,
18135      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
18136      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18137      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
18138      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18139      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I,
18140      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
18141      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
18142      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
18143      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
18144      GIR_EraseFromParent, /*InsnID*/0,
18145      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18146      // GIR_Coverage, 1625,
18147      GIR_Done,
18148    // Label 1101: @43930
18149    GIM_Try, /*On fail goto*//*Label 1102*/ 44031, // Rule ID 1628 //
18150      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
18151      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
18152      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18153      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18154      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
18155      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18156      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
18157      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
18158      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
18159      // MIs[1] Operand 1
18160      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
18161      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
18162      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
18163      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
18164      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
18165      GIM_CheckIsSafeToFold, /*InsnID*/1,
18166      // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), GPR32:{ *:[i32] }:$F)
18167      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18168      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT64,
18169      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
18170      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
18171      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18172      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18173      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I,
18174      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
18175      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
18176      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
18177      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
18178      GIR_EraseFromParent, /*InsnID*/0,
18179      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18180      // GIR_Coverage, 1628,
18181      GIR_Done,
18182    // Label 1102: @44031
18183    GIM_Try, /*On fail goto*//*Label 1103*/ 44132, // Rule ID 1629 //
18184      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
18185      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
18186      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18187      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18188      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
18189      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18190      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
18191      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
18192      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
18193      // MIs[1] Operand 1
18194      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
18195      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
18196      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
18197      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
18198      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
18199      GIM_CheckIsSafeToFold, /*InsnID*/1,
18200      // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), GPR32:{ *:[i32] }:$F)
18201      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18202      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu64,
18203      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
18204      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
18205      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18206      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18207      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I,
18208      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
18209      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
18210      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
18211      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
18212      GIR_EraseFromParent, /*InsnID*/0,
18213      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18214      // GIR_Coverage, 1629,
18215      GIR_Done,
18216    // Label 1103: @44132
18217    GIM_Try, /*On fail goto*//*Label 1104*/ 44233, // Rule ID 1642 //
18218      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
18219      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
18220      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18221      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18222      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
18223      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18224      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
18225      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
18226      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
18227      // MIs[1] Operand 1
18228      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
18229      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
18230      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
18231      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
18232      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
18233      GIM_CheckIsSafeToFold, /*InsnID*/1,
18234      // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I64_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR32:{ *:[i32] }:$F)
18235      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
18236      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR64,
18237      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
18238      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18239      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
18240      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18241      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I64_I,
18242      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
18243      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
18244      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
18245      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
18246      GIR_EraseFromParent, /*InsnID*/0,
18247      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18248      // GIR_Coverage, 1642,
18249      GIR_Done,
18250    // Label 1104: @44233
18251    GIM_Try, /*On fail goto*//*Label 1105*/ 44334, // Rule ID 1652 //
18252      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
18253      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
18254      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18255      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18256      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
18257      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18258      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
18259      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
18260      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
18261      // MIs[1] Operand 1
18262      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
18263      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
18264      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
18265      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
18266      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
18267      GIM_CheckIsSafeToFold, /*InsnID*/1,
18268      // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVN_I64_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR32:{ *:[i32] }:$F)
18269      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
18270      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR64,
18271      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
18272      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18273      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
18274      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18275      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_I,
18276      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
18277      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
18278      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
18279      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
18280      GIR_EraseFromParent, /*InsnID*/0,
18281      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18282      // GIR_Coverage, 1652,
18283      GIR_Done,
18284    // Label 1105: @44334
18285    GIM_Try, /*On fail goto*//*Label 1106*/ 44435, // Rule ID 1658 //
18286      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
18287      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
18288      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18289      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18290      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
18291      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18292      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
18293      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
18294      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18295      // MIs[1] Operand 1
18296      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
18297      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
18298      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
18299      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
18300      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
18301      GIM_CheckIsSafeToFold, /*InsnID*/1,
18302      // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
18303      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18304      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT,
18305      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
18306      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18307      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
18308      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18309      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S,
18310      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
18311      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
18312      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
18313      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
18314      GIR_EraseFromParent, /*InsnID*/0,
18315      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18316      // GIR_Coverage, 1658,
18317      GIR_Done,
18318    // Label 1106: @44435
18319    GIM_Try, /*On fail goto*//*Label 1107*/ 44536, // Rule ID 1659 //
18320      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
18321      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
18322      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18323      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18324      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
18325      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18326      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
18327      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
18328      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18329      // MIs[1] Operand 1
18330      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
18331      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
18332      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
18333      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
18334      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
18335      GIM_CheckIsSafeToFold, /*InsnID*/1,
18336      // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
18337      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18338      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu,
18339      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
18340      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18341      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
18342      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18343      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S,
18344      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
18345      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
18346      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
18347      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
18348      GIR_EraseFromParent, /*InsnID*/0,
18349      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18350      // GIR_Coverage, 1659,
18351      GIR_Done,
18352    // Label 1107: @44536
18353    GIM_Try, /*On fail goto*//*Label 1108*/ 44637, // Rule ID 1662 //
18354      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
18355      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
18356      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18357      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18358      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
18359      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18360      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
18361      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
18362      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18363      // MIs[1] Operand 1
18364      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
18365      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
18366      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
18367      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
18368      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
18369      GIM_CheckIsSafeToFold, /*InsnID*/1,
18370      // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR32:{ *:[f32] }:$F)
18371      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18372      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT,
18373      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
18374      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
18375      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18376      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18377      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S,
18378      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
18379      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
18380      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
18381      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
18382      GIR_EraseFromParent, /*InsnID*/0,
18383      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18384      // GIR_Coverage, 1662,
18385      GIR_Done,
18386    // Label 1108: @44637
18387    GIM_Try, /*On fail goto*//*Label 1109*/ 44738, // Rule ID 1663 //
18388      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
18389      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
18390      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18391      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18392      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
18393      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18394      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
18395      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
18396      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18397      // MIs[1] Operand 1
18398      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
18399      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
18400      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
18401      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
18402      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
18403      GIM_CheckIsSafeToFold, /*InsnID*/1,
18404      // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR32:{ *:[f32] }:$F)
18405      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18406      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu,
18407      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
18408      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
18409      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18410      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18411      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S,
18412      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
18413      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
18414      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
18415      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
18416      GIR_EraseFromParent, /*InsnID*/0,
18417      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18418      // GIR_Coverage, 1663,
18419      GIR_Done,
18420    // Label 1109: @44738
18421    GIM_Try, /*On fail goto*//*Label 1110*/ 44839, // Rule ID 1666 //
18422      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
18423      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
18424      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18425      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18426      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
18427      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18428      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
18429      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
18430      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18431      // MIs[1] Operand 1
18432      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
18433      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
18434      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
18435      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
18436      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
18437      GIM_CheckIsSafeToFold, /*InsnID*/1,
18438      // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
18439      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18440      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR,
18441      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
18442      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18443      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
18444      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18445      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S,
18446      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
18447      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
18448      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
18449      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
18450      GIR_EraseFromParent, /*InsnID*/0,
18451      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18452      // GIR_Coverage, 1666,
18453      GIR_Done,
18454    // Label 1110: @44839
18455    GIM_Try, /*On fail goto*//*Label 1111*/ 44940, // Rule ID 1668 //
18456      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
18457      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
18458      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18459      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18460      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
18461      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18462      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
18463      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
18464      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18465      // MIs[1] Operand 1
18466      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
18467      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
18468      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
18469      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
18470      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
18471      GIM_CheckIsSafeToFold, /*InsnID*/1,
18472      // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVN_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
18473      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18474      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR,
18475      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
18476      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18477      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
18478      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18479      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_S,
18480      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
18481      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
18482      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
18483      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
18484      GIR_EraseFromParent, /*InsnID*/0,
18485      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18486      // GIR_Coverage, 1668,
18487      GIR_Done,
18488    // Label 1111: @44940
18489    GIM_Try, /*On fail goto*//*Label 1112*/ 45041, // Rule ID 1671 //
18490      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
18491      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
18492      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18493      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18494      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
18495      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18496      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
18497      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
18498      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
18499      // MIs[1] Operand 1
18500      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
18501      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
18502      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
18503      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
18504      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
18505      GIM_CheckIsSafeToFold, /*InsnID*/1,
18506      // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR32:{ *:[f32] }:$F)
18507      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18508      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT64,
18509      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
18510      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18511      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
18512      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18513      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S,
18514      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
18515      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
18516      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
18517      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
18518      GIR_EraseFromParent, /*InsnID*/0,
18519      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18520      // GIR_Coverage, 1671,
18521      GIR_Done,
18522    // Label 1112: @45041
18523    GIM_Try, /*On fail goto*//*Label 1113*/ 45142, // Rule ID 1672 //
18524      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
18525      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
18526      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18527      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18528      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
18529      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18530      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
18531      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
18532      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
18533      // MIs[1] Operand 1
18534      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
18535      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
18536      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
18537      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
18538      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
18539      GIM_CheckIsSafeToFold, /*InsnID*/1,
18540      // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR32:{ *:[f32] }:$F)
18541      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18542      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu64,
18543      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
18544      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18545      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
18546      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18547      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S,
18548      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
18549      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
18550      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
18551      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
18552      GIR_EraseFromParent, /*InsnID*/0,
18553      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18554      // GIR_Coverage, 1672,
18555      GIR_Done,
18556    // Label 1113: @45142
18557    GIM_Try, /*On fail goto*//*Label 1114*/ 45243, // Rule ID 1675 //
18558      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
18559      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
18560      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18561      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18562      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
18563      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18564      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
18565      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
18566      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
18567      // MIs[1] Operand 1
18568      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
18569      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
18570      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
18571      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
18572      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
18573      GIM_CheckIsSafeToFold, /*InsnID*/1,
18574      // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), FGR32:{ *:[f32] }:$F)
18575      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18576      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT64,
18577      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
18578      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
18579      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18580      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18581      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S,
18582      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
18583      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
18584      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
18585      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
18586      GIR_EraseFromParent, /*InsnID*/0,
18587      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18588      // GIR_Coverage, 1675,
18589      GIR_Done,
18590    // Label 1114: @45243
18591    GIM_Try, /*On fail goto*//*Label 1115*/ 45344, // Rule ID 1676 //
18592      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
18593      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
18594      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18595      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18596      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
18597      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18598      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
18599      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
18600      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
18601      // MIs[1] Operand 1
18602      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
18603      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
18604      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
18605      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
18606      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
18607      GIM_CheckIsSafeToFold, /*InsnID*/1,
18608      // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), FGR32:{ *:[f32] }:$F)
18609      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18610      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu64,
18611      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
18612      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
18613      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18614      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18615      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S,
18616      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
18617      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
18618      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
18619      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
18620      GIR_EraseFromParent, /*InsnID*/0,
18621      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18622      // GIR_Coverage, 1676,
18623      GIR_Done,
18624    // Label 1115: @45344
18625    GIM_Try, /*On fail goto*//*Label 1116*/ 45445, // Rule ID 1679 //
18626      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
18627      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
18628      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18629      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18630      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
18631      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18632      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
18633      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
18634      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
18635      // MIs[1] Operand 1
18636      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
18637      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
18638      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
18639      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
18640      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
18641      GIM_CheckIsSafeToFold, /*InsnID*/1,
18642      // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVZ_I64_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR32:{ *:[f32] }:$F)
18643      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
18644      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR64,
18645      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
18646      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18647      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
18648      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18649      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I64_S,
18650      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
18651      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
18652      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
18653      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
18654      GIR_EraseFromParent, /*InsnID*/0,
18655      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18656      // GIR_Coverage, 1679,
18657      GIR_Done,
18658    // Label 1116: @45445
18659    GIM_Try, /*On fail goto*//*Label 1117*/ 45546, // Rule ID 1681 //
18660      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
18661      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
18662      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18663      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18664      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
18665      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18666      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
18667      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
18668      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
18669      // MIs[1] Operand 1
18670      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
18671      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
18672      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
18673      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
18674      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
18675      GIM_CheckIsSafeToFold, /*InsnID*/1,
18676      // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVN_I64_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR32:{ *:[f32] }:$F)
18677      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
18678      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR64,
18679      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
18680      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18681      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
18682      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18683      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_S,
18684      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
18685      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
18686      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
18687      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
18688      GIR_EraseFromParent, /*InsnID*/0,
18689      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18690      // GIR_Coverage, 1681,
18691      GIR_Done,
18692    // Label 1117: @45546
18693    GIM_Try, /*On fail goto*//*Label 1118*/ 45631, // Rule ID 1828 //
18694      GIM_CheckFeatures, GIFBS_InMips16Mode,
18695      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
18696      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18697      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18698      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
18699      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18700      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
18701      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
18702      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18703      // MIs[1] Operand 1
18704      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
18705      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
18706      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID,
18707      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
18708      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID,
18709      GIM_CheckIsSafeToFold, /*InsnID*/1,
18710      // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETGE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y)  =>  (SelTBteqZSlt:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b)
18711      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SelTBteqZSlt,
18712      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd_
18713      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // x
18714      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // y
18715      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
18716      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
18717      GIR_EraseFromParent, /*InsnID*/0,
18718      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18719      // GIR_Coverage, 1828,
18720      GIR_Done,
18721    // Label 1118: @45631
18722    GIM_Try, /*On fail goto*//*Label 1119*/ 45716, // Rule ID 1829 //
18723      GIM_CheckFeatures, GIFBS_InMips16Mode,
18724      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
18725      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18726      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18727      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
18728      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18729      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
18730      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
18731      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18732      // MIs[1] Operand 1
18733      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT,
18734      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
18735      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID,
18736      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
18737      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID,
18738      GIM_CheckIsSafeToFold, /*InsnID*/1,
18739      // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETGT:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y)  =>  (SelTBtneZSlt:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a)
18740      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SelTBtneZSlt,
18741      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd_
18742      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // x
18743      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // y
18744      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
18745      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
18746      GIR_EraseFromParent, /*InsnID*/0,
18747      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18748      // GIR_Coverage, 1829,
18749      GIR_Done,
18750    // Label 1119: @45716
18751    GIM_Try, /*On fail goto*//*Label 1120*/ 45801, // Rule ID 1830 //
18752      GIM_CheckFeatures, GIFBS_InMips16Mode,
18753      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
18754      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18755      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18756      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
18757      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18758      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
18759      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
18760      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18761      // MIs[1] Operand 1
18762      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
18763      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
18764      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID,
18765      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
18766      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID,
18767      GIM_CheckIsSafeToFold, /*InsnID*/1,
18768      // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETUGE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y)  =>  (SelTBteqZSltu:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b)
18769      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SelTBteqZSltu,
18770      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd_
18771      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // x
18772      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // y
18773      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
18774      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
18775      GIR_EraseFromParent, /*InsnID*/0,
18776      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18777      // GIR_Coverage, 1830,
18778      GIR_Done,
18779    // Label 1120: @45801
18780    GIM_Try, /*On fail goto*//*Label 1121*/ 45886, // Rule ID 1831 //
18781      GIM_CheckFeatures, GIFBS_InMips16Mode,
18782      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
18783      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18784      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18785      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
18786      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18787      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
18788      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
18789      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18790      // MIs[1] Operand 1
18791      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT,
18792      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
18793      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID,
18794      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
18795      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID,
18796      GIM_CheckIsSafeToFold, /*InsnID*/1,
18797      // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETUGT:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y)  =>  (SelTBtneZSltu:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a)
18798      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SelTBtneZSltu,
18799      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd_
18800      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // x
18801      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // y
18802      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
18803      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
18804      GIR_EraseFromParent, /*InsnID*/0,
18805      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18806      // GIR_Coverage, 1831,
18807      GIR_Done,
18808    // Label 1121: @45886
18809    GIM_Try, /*On fail goto*//*Label 1122*/ 45971, // Rule ID 1833 //
18810      GIM_CheckFeatures, GIFBS_InMips16Mode,
18811      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
18812      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18813      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18814      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
18815      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18816      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
18817      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
18818      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18819      // MIs[1] Operand 1
18820      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
18821      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
18822      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID,
18823      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
18824      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID,
18825      GIM_CheckIsSafeToFold, /*InsnID*/1,
18826      // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETLE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y)  =>  (SelTBteqZSlt:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a)
18827      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SelTBteqZSlt,
18828      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd_
18829      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // x
18830      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // y
18831      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
18832      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
18833      GIR_EraseFromParent, /*InsnID*/0,
18834      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18835      // GIR_Coverage, 1833,
18836      GIR_Done,
18837    // Label 1122: @45971
18838    GIM_Try, /*On fail goto*//*Label 1123*/ 46056, // Rule ID 1834 //
18839      GIM_CheckFeatures, GIFBS_InMips16Mode,
18840      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
18841      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18842      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18843      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
18844      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18845      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
18846      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
18847      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18848      // MIs[1] Operand 1
18849      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
18850      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
18851      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID,
18852      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
18853      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID,
18854      GIM_CheckIsSafeToFold, /*InsnID*/1,
18855      // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETULE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y)  =>  (SelTBteqZSltu:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a)
18856      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SelTBteqZSltu,
18857      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd_
18858      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // x
18859      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // y
18860      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
18861      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
18862      GIR_EraseFromParent, /*InsnID*/0,
18863      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18864      // GIR_Coverage, 1834,
18865      GIR_Done,
18866    // Label 1123: @46056
18867    GIM_Try, /*On fail goto*//*Label 1124*/ 46141, // Rule ID 1835 //
18868      GIM_CheckFeatures, GIFBS_InMips16Mode,
18869      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
18870      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18871      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18872      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
18873      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18874      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
18875      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
18876      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18877      // MIs[1] Operand 1
18878      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
18879      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
18880      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID,
18881      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
18882      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID,
18883      GIM_CheckIsSafeToFold, /*InsnID*/1,
18884      // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETEQ:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y)  =>  (SelTBteqZCmp:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a)
18885      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SelTBteqZCmp,
18886      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd_
18887      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // x
18888      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // y
18889      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
18890      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
18891      GIR_EraseFromParent, /*InsnID*/0,
18892      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18893      // GIR_Coverage, 1835,
18894      GIR_Done,
18895    // Label 1124: @46141
18896    GIM_Try, /*On fail goto*//*Label 1125*/ 46226, // Rule ID 1838 //
18897      GIM_CheckFeatures, GIFBS_InMips16Mode,
18898      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
18899      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18900      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18901      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
18902      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18903      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
18904      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
18905      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18906      // MIs[1] Operand 1
18907      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
18908      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
18909      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID,
18910      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
18911      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID,
18912      GIM_CheckIsSafeToFold, /*InsnID*/1,
18913      // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETNE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y)  =>  (SelTBtneZCmp:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a)
18914      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SelTBtneZCmp,
18915      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd_
18916      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // x
18917      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // y
18918      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
18919      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
18920      GIR_EraseFromParent, /*InsnID*/0,
18921      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18922      // GIR_Coverage, 1838,
18923      GIR_Done,
18924    // Label 1125: @46226
18925    GIM_Try, /*On fail goto*//*Label 1126*/ 46327, // Rule ID 2174 //
18926      GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
18927      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
18928      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18929      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18930      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
18931      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18932      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
18933      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
18934      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18935      // MIs[1] Operand 1
18936      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
18937      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
18938      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
18939      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
18940      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
18941      GIM_CheckIsSafeToFold, /*InsnID*/1,
18942      // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
18943      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18944      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT_MM,
18945      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
18946      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18947      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
18948      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18949      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_MM,
18950      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
18951      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
18952      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
18953      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
18954      GIR_EraseFromParent, /*InsnID*/0,
18955      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18956      // GIR_Coverage, 2174,
18957      GIR_Done,
18958    // Label 1126: @46327
18959    GIM_Try, /*On fail goto*//*Label 1127*/ 46428, // Rule ID 2175 //
18960      GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
18961      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
18962      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18963      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18964      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
18965      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18966      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
18967      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
18968      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18969      // MIs[1] Operand 1
18970      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
18971      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
18972      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
18973      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
18974      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
18975      GIM_CheckIsSafeToFold, /*InsnID*/1,
18976      // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
18977      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18978      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu_MM,
18979      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
18980      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18981      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
18982      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18983      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_MM,
18984      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
18985      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
18986      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
18987      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
18988      GIR_EraseFromParent, /*InsnID*/0,
18989      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18990      // GIR_Coverage, 2175,
18991      GIR_Done,
18992    // Label 1127: @46428
18993    GIM_Try, /*On fail goto*//*Label 1128*/ 46529, // Rule ID 2178 //
18994      GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
18995      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
18996      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18997      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18998      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
18999      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19000      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
19001      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19002      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19003      // MIs[1] Operand 1
19004      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
19005      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
19006      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
19007      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
19008      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
19009      GIM_CheckIsSafeToFold, /*InsnID*/1,
19010      // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F)
19011      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19012      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT_MM,
19013      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
19014      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19015      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19016      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19017      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_MM,
19018      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
19019      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
19020      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
19021      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
19022      GIR_EraseFromParent, /*InsnID*/0,
19023      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19024      // GIR_Coverage, 2178,
19025      GIR_Done,
19026    // Label 1128: @46529
19027    GIM_Try, /*On fail goto*//*Label 1129*/ 46630, // Rule ID 2179 //
19028      GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
19029      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19030      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19031      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19032      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
19033      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19034      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
19035      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19036      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19037      // MIs[1] Operand 1
19038      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
19039      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
19040      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
19041      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
19042      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
19043      GIM_CheckIsSafeToFold, /*InsnID*/1,
19044      // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F)
19045      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19046      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu_MM,
19047      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
19048      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19049      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19050      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19051      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_MM,
19052      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
19053      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
19054      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
19055      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
19056      GIR_EraseFromParent, /*InsnID*/0,
19057      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19058      // GIR_Coverage, 2179,
19059      GIR_Done,
19060    // Label 1129: @46630
19061    GIM_Try, /*On fail goto*//*Label 1130*/ 46731, // Rule ID 2182 //
19062      GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
19063      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19064      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19065      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19066      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
19067      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19068      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
19069      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19070      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19071      // MIs[1] Operand 1
19072      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
19073      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
19074      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
19075      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
19076      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
19077      GIM_CheckIsSafeToFold, /*InsnID*/1,
19078      // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
19079      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19080      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR_MM,
19081      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
19082      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19083      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19084      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19085      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_MM,
19086      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
19087      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
19088      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
19089      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
19090      GIR_EraseFromParent, /*InsnID*/0,
19091      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19092      // GIR_Coverage, 2182,
19093      GIR_Done,
19094    // Label 1130: @46731
19095    GIM_Try, /*On fail goto*//*Label 1131*/ 46832, // Rule ID 2185 //
19096      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotMips32r6_NotMips64r6,
19097      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19098      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19099      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19100      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
19101      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19102      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
19103      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19104      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19105      // MIs[1] Operand 1
19106      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
19107      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
19108      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
19109      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
19110      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
19111      GIM_CheckIsSafeToFold, /*InsnID*/1,
19112      // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
19113      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19114      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR_MM,
19115      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
19116      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19117      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19118      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19119      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_MM,
19120      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
19121      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
19122      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
19123      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
19124      GIR_EraseFromParent, /*InsnID*/0,
19125      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19126      // GIR_Coverage, 2185,
19127      GIR_Done,
19128    // Label 1131: @46832
19129    GIM_Try, /*On fail goto*//*Label 1132*/ 46933, // Rule ID 2188 //
19130      GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
19131      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19132      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19133      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19134      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
19135      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19136      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
19137      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19138      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19139      // MIs[1] Operand 1
19140      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
19141      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
19142      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
19143      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
19144      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
19145      GIM_CheckIsSafeToFold, /*InsnID*/1,
19146      // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
19147      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19148      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT_MM,
19149      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
19150      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19151      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19152      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19153      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_MM,
19154      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
19155      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
19156      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
19157      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
19158      GIR_EraseFromParent, /*InsnID*/0,
19159      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19160      // GIR_Coverage, 2188,
19161      GIR_Done,
19162    // Label 1132: @46933
19163    GIM_Try, /*On fail goto*//*Label 1133*/ 47034, // Rule ID 2189 //
19164      GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
19165      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19166      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19167      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19168      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
19169      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19170      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
19171      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19172      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19173      // MIs[1] Operand 1
19174      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
19175      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
19176      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
19177      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
19178      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
19179      GIM_CheckIsSafeToFold, /*InsnID*/1,
19180      // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
19181      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19182      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu_MM,
19183      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
19184      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19185      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19186      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19187      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_MM,
19188      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
19189      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
19190      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
19191      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
19192      GIR_EraseFromParent, /*InsnID*/0,
19193      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19194      // GIR_Coverage, 2189,
19195      GIR_Done,
19196    // Label 1133: @47034
19197    GIM_Try, /*On fail goto*//*Label 1134*/ 47135, // Rule ID 2192 //
19198      GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
19199      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19200      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19201      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19202      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
19203      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19204      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
19205      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19206      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19207      // MIs[1] Operand 1
19208      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
19209      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
19210      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
19211      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
19212      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
19213      GIM_CheckIsSafeToFold, /*InsnID*/1,
19214      // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F)
19215      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19216      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT_MM,
19217      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
19218      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19219      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19220      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19221      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_MM,
19222      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
19223      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
19224      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
19225      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
19226      GIR_EraseFromParent, /*InsnID*/0,
19227      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19228      // GIR_Coverage, 2192,
19229      GIR_Done,
19230    // Label 1134: @47135
19231    GIM_Try, /*On fail goto*//*Label 1135*/ 47236, // Rule ID 2193 //
19232      GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
19233      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19234      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19235      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19236      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
19237      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19238      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
19239      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19240      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19241      // MIs[1] Operand 1
19242      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
19243      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
19244      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
19245      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
19246      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
19247      GIM_CheckIsSafeToFold, /*InsnID*/1,
19248      // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F)
19249      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19250      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu_MM,
19251      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
19252      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19253      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19254      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19255      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_MM,
19256      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
19257      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
19258      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
19259      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
19260      GIR_EraseFromParent, /*InsnID*/0,
19261      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19262      // GIR_Coverage, 2193,
19263      GIR_Done,
19264    // Label 1135: @47236
19265    GIM_Try, /*On fail goto*//*Label 1136*/ 47337, // Rule ID 2196 //
19266      GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
19267      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19268      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19269      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19270      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
19271      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19272      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
19273      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19274      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19275      // MIs[1] Operand 1
19276      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
19277      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
19278      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
19279      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
19280      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
19281      GIM_CheckIsSafeToFold, /*InsnID*/1,
19282      // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
19283      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19284      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR_MM,
19285      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
19286      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19287      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19288      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19289      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_MM,
19290      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
19291      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
19292      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
19293      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
19294      GIR_EraseFromParent, /*InsnID*/0,
19295      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19296      // GIR_Coverage, 2196,
19297      GIR_Done,
19298    // Label 1136: @47337
19299    GIM_Try, /*On fail goto*//*Label 1137*/ 47438, // Rule ID 2199 //
19300      GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
19301      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19302      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19303      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19304      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
19305      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19306      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
19307      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19308      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19309      // MIs[1] Operand 1
19310      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
19311      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
19312      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
19313      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
19314      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
19315      GIM_CheckIsSafeToFold, /*InsnID*/1,
19316      // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
19317      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19318      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR_MM,
19319      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
19320      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19321      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19322      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19323      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_MM,
19324      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
19325      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
19326      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
19327      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
19328      GIR_EraseFromParent, /*InsnID*/0,
19329      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19330      // GIR_Coverage, 2199,
19331      GIR_Done,
19332    // Label 1137: @47438
19333    GIM_Try, /*On fail goto*//*Label 1138*/ 47539, // Rule ID 2222 //
19334      GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
19335      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19336      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19337      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19338      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
19339      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19340      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
19341      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19342      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19343      // MIs[1] Operand 1
19344      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
19345      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
19346      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
19347      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
19348      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
19349      GIM_CheckIsSafeToFold, /*InsnID*/1,
19350      // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
19351      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19352      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT_MM,
19353      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
19354      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19355      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19356      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19357      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S_MM,
19358      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
19359      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
19360      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
19361      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
19362      GIR_EraseFromParent, /*InsnID*/0,
19363      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19364      // GIR_Coverage, 2222,
19365      GIR_Done,
19366    // Label 1138: @47539
19367    GIM_Try, /*On fail goto*//*Label 1139*/ 47640, // Rule ID 2223 //
19368      GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
19369      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19370      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19371      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19372      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
19373      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19374      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
19375      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19376      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19377      // MIs[1] Operand 1
19378      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
19379      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
19380      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
19381      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
19382      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
19383      GIM_CheckIsSafeToFold, /*InsnID*/1,
19384      // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
19385      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19386      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu_MM,
19387      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
19388      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19389      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19390      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19391      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S_MM,
19392      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
19393      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
19394      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
19395      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
19396      GIR_EraseFromParent, /*InsnID*/0,
19397      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19398      // GIR_Coverage, 2223,
19399      GIR_Done,
19400    // Label 1139: @47640
19401    GIM_Try, /*On fail goto*//*Label 1140*/ 47741, // Rule ID 2226 //
19402      GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
19403      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19404      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19405      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19406      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
19407      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19408      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
19409      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19410      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19411      // MIs[1] Operand 1
19412      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
19413      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
19414      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
19415      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
19416      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
19417      GIM_CheckIsSafeToFold, /*InsnID*/1,
19418      // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR32:{ *:[f32] }:$F)
19419      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19420      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT_MM,
19421      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
19422      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19423      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19424      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19425      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S_MM,
19426      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
19427      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
19428      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
19429      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
19430      GIR_EraseFromParent, /*InsnID*/0,
19431      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19432      // GIR_Coverage, 2226,
19433      GIR_Done,
19434    // Label 1140: @47741
19435    GIM_Try, /*On fail goto*//*Label 1141*/ 47842, // Rule ID 2227 //
19436      GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
19437      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19438      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19439      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19440      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
19441      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19442      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
19443      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19444      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19445      // MIs[1] Operand 1
19446      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
19447      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
19448      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
19449      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
19450      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
19451      GIM_CheckIsSafeToFold, /*InsnID*/1,
19452      // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR32:{ *:[f32] }:$F)
19453      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19454      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu_MM,
19455      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
19456      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19457      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19458      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19459      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S_MM,
19460      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
19461      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
19462      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
19463      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
19464      GIR_EraseFromParent, /*InsnID*/0,
19465      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19466      // GIR_Coverage, 2227,
19467      GIR_Done,
19468    // Label 1141: @47842
19469    GIM_Try, /*On fail goto*//*Label 1142*/ 47943, // Rule ID 2230 //
19470      GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
19471      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19472      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19473      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19474      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
19475      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19476      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
19477      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19478      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19479      // MIs[1] Operand 1
19480      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
19481      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
19482      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
19483      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
19484      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
19485      GIM_CheckIsSafeToFold, /*InsnID*/1,
19486      // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
19487      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19488      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR_MM,
19489      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
19490      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19491      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19492      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19493      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S_MM,
19494      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
19495      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
19496      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
19497      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
19498      GIR_EraseFromParent, /*InsnID*/0,
19499      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19500      // GIR_Coverage, 2230,
19501      GIR_Done,
19502    // Label 1142: @47943
19503    GIM_Try, /*On fail goto*//*Label 1143*/ 48044, // Rule ID 2232 //
19504      GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
19505      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19506      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19507      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19508      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
19509      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19510      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
19511      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19512      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19513      // MIs[1] Operand 1
19514      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
19515      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
19516      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
19517      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
19518      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
19519      GIM_CheckIsSafeToFold, /*InsnID*/1,
19520      // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVN_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
19521      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19522      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR_MM,
19523      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
19524      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19525      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19526      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19527      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_S_MM,
19528      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
19529      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
19530      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
19531      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
19532      GIR_EraseFromParent, /*InsnID*/0,
19533      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19534      // GIR_Coverage, 2232,
19535      GIR_Done,
19536    // Label 1143: @48044
19537    GIM_Try, /*On fail goto*//*Label 1144*/ 48083, // Rule ID 283 //
19538      GIM_CheckFeatures, GIFBS_HasStdEnc_NotMips4_32,
19539      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19540      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19541      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19542      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
19543      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
19544      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
19545      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
19546      // (select:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$cond, GPR32Opnd:{ *:[i32] }:$T, GPR32Opnd:{ *:[i32] }:$F)  =>  (PseudoSELECT_I:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$cond, GPR32Opnd:{ *:[i32] }:$T, GPR32Opnd:{ *:[i32] }:$F)
19547      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PseudoSELECT_I,
19548      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19549      // GIR_Coverage, 283,
19550      GIR_Done,
19551    // Label 1144: @48083
19552    GIM_Try, /*On fail goto*//*Label 1145*/ 48122, // Rule ID 285 //
19553      GIM_CheckFeatures, GIFBS_HasStdEnc_NotMips4_32,
19554      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19555      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19556      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19557      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
19558      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
19559      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
19560      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
19561      // (select:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$cond, FGR32Opnd:{ *:[f32] }:$T, FGR32Opnd:{ *:[f32] }:$F)  =>  (PseudoSELECT_S:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$cond, FGR32Opnd:{ *:[f32] }:$T, FGR32Opnd:{ *:[f32] }:$F)
19562      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PseudoSELECT_S,
19563      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19564      // GIR_Coverage, 285,
19565      GIR_Done,
19566    // Label 1145: @48122
19567    GIM_Try, /*On fail goto*//*Label 1146*/ 48178, // Rule ID 322 //
19568      GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
19569      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19570      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19571      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19572      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
19573      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGRCCRegClassID,
19574      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
19575      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
19576      // (select:{ *:[f32] } FGRCCOpnd:{ *:[i32] }:$fd_in, FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs)  =>  (SEL_S:{ *:[f32] } FGRCCOpnd:{ *:[i32] }:$fd_in, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
19577      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SEL_S,
19578      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
19579      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fd_in
19580      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // fs
19581      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ft
19582      GIR_EraseFromParent, /*InsnID*/0,
19583      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19584      // GIR_Coverage, 322,
19585      GIR_Done,
19586    // Label 1146: @48178
19587    GIM_Try, /*On fail goto*//*Label 1147*/ 48234, // Rule ID 1201 //
19588      GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
19589      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19590      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19591      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19592      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
19593      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGRCCRegClassID,
19594      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
19595      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
19596      // (select:{ *:[f32] } FGRCCOpnd:{ *:[i32] }:$fd_in, FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs)  =>  (SEL_S_MMR6:{ *:[f32] } FGRCCOpnd:{ *:[i32] }:$fd_in, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
19597      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SEL_S_MMR6,
19598      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
19599      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fd_in
19600      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // fs
19601      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ft
19602      GIR_EraseFromParent, /*InsnID*/0,
19603      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19604      // GIR_Coverage, 1201,
19605      GIR_Done,
19606    // Label 1147: @48234
19607    GIM_Try, /*On fail goto*//*Label 1148*/ 48290, // Rule ID 1614 //
19608      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
19609      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19610      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19611      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19612      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
19613      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
19614      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
19615      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
19616      // (select:{ *:[i32] } GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVN_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$F)
19617      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_I,
19618      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
19619      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
19620      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond
19621      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
19622      GIR_EraseFromParent, /*InsnID*/0,
19623      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19624      // GIR_Coverage, 1614,
19625      GIR_Done,
19626    // Label 1148: @48290
19627    GIM_Try, /*On fail goto*//*Label 1149*/ 48346, // Rule ID 1653 //
19628      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
19629      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
19630      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19631      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19632      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
19633      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
19634      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
19635      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
19636      // (select:{ *:[i32] } GPR64:{ *:[i64] }:$cond, GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVN_I64_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR64:{ *:[i64] }:$cond, GPR32:{ *:[i32] }:$F)
19637      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_I,
19638      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
19639      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
19640      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond
19641      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
19642      GIR_EraseFromParent, /*InsnID*/0,
19643      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19644      // GIR_Coverage, 1653,
19645      GIR_Done,
19646    // Label 1149: @48346
19647    GIM_Try, /*On fail goto*//*Label 1150*/ 48402, // Rule ID 1669 //
19648      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
19649      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19650      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19651      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19652      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
19653      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
19654      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
19655      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
19656      // (select:{ *:[f32] } GPR32:{ *:[i32] }:$cond, FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVN_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$cond, FGR32:{ *:[f32] }:$F)
19657      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_S,
19658      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
19659      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
19660      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond
19661      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
19662      GIR_EraseFromParent, /*InsnID*/0,
19663      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19664      // GIR_Coverage, 1669,
19665      GIR_Done,
19666    // Label 1150: @48402
19667    GIM_Try, /*On fail goto*//*Label 1151*/ 48458, // Rule ID 1682 //
19668      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
19669      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
19670      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19671      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19672      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
19673      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
19674      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
19675      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
19676      // (select:{ *:[f32] } GPR64:{ *:[i64] }:$cond, FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVN_I64_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR64:{ *:[i64] }:$cond, FGR32:{ *:[f32] }:$F)
19677      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_S,
19678      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
19679      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
19680      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond
19681      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
19682      GIR_EraseFromParent, /*InsnID*/0,
19683      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19684      // GIR_Coverage, 1682,
19685      GIR_Done,
19686    // Label 1151: @48458
19687    GIM_Try, /*On fail goto*//*Label 1152*/ 48514, // Rule ID 1840 //
19688      GIM_CheckFeatures, GIFBS_InMips16Mode,
19689      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19690      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19691      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19692      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
19693      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
19694      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
19695      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID,
19696      // (select:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y)  =>  (SelBneZ:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$a)
19697      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SelBneZ,
19698      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd_
19699      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // x
19700      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // y
19701      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // a
19702      GIR_EraseFromParent, /*InsnID*/0,
19703      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19704      // GIR_Coverage, 1840,
19705      GIR_Done,
19706    // Label 1152: @48514
19707    GIM_Try, /*On fail goto*//*Label 1153*/ 48570, // Rule ID 2186 //
19708      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotMips32r6_NotMips64r6,
19709      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19710      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19711      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19712      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
19713      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
19714      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
19715      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
19716      // (select:{ *:[i32] } GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$F)
19717      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_MM,
19718      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
19719      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
19720      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond
19721      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
19722      GIR_EraseFromParent, /*InsnID*/0,
19723      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19724      // GIR_Coverage, 2186,
19725      GIR_Done,
19726    // Label 1153: @48570
19727    GIM_Try, /*On fail goto*//*Label 1154*/ 48626, // Rule ID 2200 //
19728      GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
19729      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19730      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19731      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19732      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
19733      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
19734      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
19735      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
19736      // (select:{ *:[i32] } GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$F)
19737      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_MM,
19738      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
19739      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
19740      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond
19741      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
19742      GIR_EraseFromParent, /*InsnID*/0,
19743      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19744      // GIR_Coverage, 2200,
19745      GIR_Done,
19746    // Label 1154: @48626
19747    GIM_Try, /*On fail goto*//*Label 1155*/ 48682, // Rule ID 2233 //
19748      GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
19749      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19750      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19751      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19752      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
19753      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
19754      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
19755      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
19756      // (select:{ *:[f32] } GPR32:{ *:[i32] }:$cond, FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVN_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$cond, FGR32:{ *:[f32] }:$F)
19757      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_S_MM,
19758      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
19759      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
19760      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond
19761      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
19762      GIR_EraseFromParent, /*InsnID*/0,
19763      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19764      // GIR_Coverage, 2233,
19765      GIR_Done,
19766    // Label 1155: @48682
19767    GIM_Try, /*On fail goto*//*Label 1156*/ 48762, // Rule ID 1751 //
19768      GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
19769      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19770      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19771      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19772      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
19773      // (select:{ *:[i32] } i32:{ *:[i32] }:$cond, i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$f)  =>  (OR:{ *:[i32] } (SELNEZ:{ *:[i32] } i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$cond), (SELEQZ:{ *:[i32] } i32:{ *:[i32] }:$f, i32:{ *:[i32] }:$cond))
19774      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19775      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
19776      GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SELEQZ,
19777      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
19778      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // f
19779      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // cond
19780      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
19781      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SELNEZ,
19782      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
19783      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // t
19784      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // cond
19785      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19786      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::OR,
19787      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
19788      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
19789      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
19790      GIR_EraseFromParent, /*InsnID*/0,
19791      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19792      // GIR_Coverage, 1751,
19793      GIR_Done,
19794    // Label 1156: @48762
19795    GIM_Try, /*On fail goto*//*Label 1157*/ 48842, // Rule ID 2250 //
19796      GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
19797      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19798      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19799      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19800      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
19801      // (select:{ *:[i32] } i32:{ *:[i32] }:$cond, i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$f)  =>  (OR_MM:{ *:[i32] } (SELNEZ_MMR6:{ *:[i32] } i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$cond), (SELEQZ_MMR6:{ *:[i32] } i32:{ *:[i32] }:$f, i32:{ *:[i32] }:$cond))
19802      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19803      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
19804      GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SELEQZ_MMR6,
19805      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
19806      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // f
19807      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // cond
19808      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
19809      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SELNEZ_MMR6,
19810      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
19811      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // t
19812      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // cond
19813      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19814      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::OR_MM,
19815      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
19816      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
19817      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
19818      GIR_EraseFromParent, /*InsnID*/0,
19819      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19820      // GIR_Coverage, 2250,
19821      GIR_Done,
19822    // Label 1157: @48842
19823    GIM_Reject,
19824    // Label 1076: @48843
19825    GIM_Try, /*On fail goto*//*Label 1158*/ 48924, // Rule ID 1641 //
19826      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
19827      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19828      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
19829      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
19830      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
19831      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19832      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
19833      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19834      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19835      // MIs[1] Operand 1
19836      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
19837      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
19838      GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0,
19839      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
19840      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
19841      GIM_CheckIsSafeToFold, /*InsnID*/1,
19842      // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F)  =>  (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR32:{ *:[i32] }:$lhs, GPR64:{ *:[i64] }:$F)
19843      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I64,
19844      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
19845      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
19846      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19847      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
19848      GIR_EraseFromParent, /*InsnID*/0,
19849      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19850      // GIR_Coverage, 1641,
19851      GIR_Done,
19852    // Label 1158: @48924
19853    GIM_Try, /*On fail goto*//*Label 1159*/ 49005, // Rule ID 1645 //
19854      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
19855      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19856      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
19857      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
19858      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
19859      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19860      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
19861      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
19862      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
19863      // MIs[1] Operand 1
19864      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
19865      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
19866      GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0,
19867      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
19868      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
19869      GIM_CheckIsSafeToFold, /*InsnID*/1,
19870      // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F)  =>  (MOVZ_I64_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$F)
19871      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I64_I64,
19872      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
19873      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
19874      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19875      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
19876      GIR_EraseFromParent, /*InsnID*/0,
19877      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19878      // GIR_Coverage, 1645,
19879      GIR_Done,
19880    // Label 1159: @49005
19881    GIM_Try, /*On fail goto*//*Label 1160*/ 49086, // Rule ID 1651 //
19882      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
19883      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19884      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
19885      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
19886      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
19887      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19888      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
19889      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19890      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19891      // MIs[1] Operand 1
19892      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
19893      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
19894      GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0,
19895      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
19896      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
19897      GIM_CheckIsSafeToFold, /*InsnID*/1,
19898      // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F)  =>  (MOVN_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR32:{ *:[i32] }:$lhs, GPR64:{ *:[i64] }:$F)
19899      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_I64,
19900      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
19901      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
19902      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19903      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
19904      GIR_EraseFromParent, /*InsnID*/0,
19905      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19906      // GIR_Coverage, 1651,
19907      GIR_Done,
19908    // Label 1160: @49086
19909    GIM_Try, /*On fail goto*//*Label 1161*/ 49167, // Rule ID 1657 //
19910      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
19911      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19912      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
19913      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
19914      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
19915      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19916      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
19917      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
19918      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
19919      // MIs[1] Operand 1
19920      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
19921      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
19922      GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0,
19923      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
19924      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
19925      GIM_CheckIsSafeToFold, /*InsnID*/1,
19926      // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F)  =>  (MOVN_I64_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$F)
19927      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_I64,
19928      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
19929      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
19930      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19931      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
19932      GIR_EraseFromParent, /*InsnID*/0,
19933      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19934      // GIR_Coverage, 1657,
19935      GIR_Done,
19936    // Label 1161: @49167
19937    GIM_Try, /*On fail goto*//*Label 1162*/ 49248, // Rule ID 1693 //
19938      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
19939      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19940      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
19941      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
19942      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
19943      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19944      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
19945      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19946      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19947      // MIs[1] Operand 1
19948      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
19949      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
19950      GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0,
19951      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
19952      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID,
19953      GIM_CheckIsSafeToFold, /*InsnID*/1,
19954      // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F)  =>  (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, AFGR64:{ *:[f64] }:$F)
19955      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D32,
19956      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
19957      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
19958      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19959      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
19960      GIR_EraseFromParent, /*InsnID*/0,
19961      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19962      // GIR_Coverage, 1693,
19963      GIR_Done,
19964    // Label 1162: @49248
19965    GIM_Try, /*On fail goto*//*Label 1163*/ 49329, // Rule ID 1696 //
19966      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
19967      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19968      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
19969      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
19970      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
19971      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19972      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
19973      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19974      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19975      // MIs[1] Operand 1
19976      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
19977      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
19978      GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0,
19979      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
19980      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID,
19981      GIM_CheckIsSafeToFold, /*InsnID*/1,
19982      // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F)  =>  (MOVN_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, AFGR64:{ *:[f64] }:$F)
19983      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_D32,
19984      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
19985      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
19986      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19987      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
19988      GIR_EraseFromParent, /*InsnID*/0,
19989      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19990      // GIR_Coverage, 1696,
19991      GIR_Done,
19992    // Label 1163: @49329
19993    GIM_Try, /*On fail goto*//*Label 1164*/ 49410, // Rule ID 1714 //
19994      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
19995      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19996      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
19997      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
19998      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
19999      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20000      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
20001      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20002      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20003      // MIs[1] Operand 1
20004      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
20005      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
20006      GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0,
20007      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
20008      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
20009      GIM_CheckIsSafeToFold, /*InsnID*/1,
20010      // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F)  =>  (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, FGR64:{ *:[f64] }:$F)
20011      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D64,
20012      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
20013      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
20014      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20015      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
20016      GIR_EraseFromParent, /*InsnID*/0,
20017      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20018      // GIR_Coverage, 1714,
20019      GIR_Done,
20020    // Label 1164: @49410
20021    GIM_Try, /*On fail goto*//*Label 1165*/ 49491, // Rule ID 1716 //
20022      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
20023      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20024      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
20025      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
20026      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
20027      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20028      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
20029      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
20030      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
20031      // MIs[1] Operand 1
20032      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
20033      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
20034      GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0,
20035      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
20036      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
20037      GIM_CheckIsSafeToFold, /*InsnID*/1,
20038      // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F)  =>  (MOVZ_I64_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR64:{ *:[i64] }:$lhs, FGR64:{ *:[f64] }:$F)
20039      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I64_D64,
20040      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
20041      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
20042      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20043      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
20044      GIR_EraseFromParent, /*InsnID*/0,
20045      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20046      // GIR_Coverage, 1716,
20047      GIR_Done,
20048    // Label 1165: @49491
20049    GIM_Try, /*On fail goto*//*Label 1166*/ 49572, // Rule ID 1719 //
20050      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
20051      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20052      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
20053      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
20054      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
20055      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20056      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
20057      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20058      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20059      // MIs[1] Operand 1
20060      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
20061      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
20062      GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0,
20063      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
20064      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
20065      GIM_CheckIsSafeToFold, /*InsnID*/1,
20066      // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F)  =>  (MOVN_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, FGR64:{ *:[f64] }:$F)
20067      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_D64,
20068      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
20069      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
20070      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20071      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
20072      GIR_EraseFromParent, /*InsnID*/0,
20073      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20074      // GIR_Coverage, 1719,
20075      GIR_Done,
20076    // Label 1166: @49572
20077    GIM_Try, /*On fail goto*//*Label 1167*/ 49653, // Rule ID 1722 //
20078      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
20079      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20080      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
20081      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
20082      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
20083      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20084      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
20085      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
20086      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
20087      // MIs[1] Operand 1
20088      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
20089      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
20090      GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0,
20091      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
20092      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
20093      GIM_CheckIsSafeToFold, /*InsnID*/1,
20094      // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F)  =>  (MOVN_I64_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR64:{ *:[i64] }:$lhs, FGR64:{ *:[f64] }:$F)
20095      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_D64,
20096      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
20097      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
20098      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20099      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
20100      GIR_EraseFromParent, /*InsnID*/0,
20101      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20102      // GIR_Coverage, 1722,
20103      GIR_Done,
20104    // Label 1167: @49653
20105    GIM_Try, /*On fail goto*//*Label 1168*/ 49734, // Rule ID 2244 //
20106      GIM_CheckFeatures, GIFBS_InMicroMips_NotFP64bit_NotMips32r6,
20107      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20108      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
20109      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
20110      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
20111      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20112      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
20113      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20114      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20115      // MIs[1] Operand 1
20116      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
20117      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
20118      GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0,
20119      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
20120      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID,
20121      GIM_CheckIsSafeToFold, /*InsnID*/1,
20122      // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F)  =>  (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, AFGR64:{ *:[f64] }:$F)
20123      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D32_MM,
20124      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
20125      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
20126      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20127      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
20128      GIR_EraseFromParent, /*InsnID*/0,
20129      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20130      // GIR_Coverage, 2244,
20131      GIR_Done,
20132    // Label 1168: @49734
20133    GIM_Try, /*On fail goto*//*Label 1169*/ 49815, // Rule ID 2247 //
20134      GIM_CheckFeatures, GIFBS_InMicroMips_NotFP64bit_NotMips32r6,
20135      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20136      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
20137      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
20138      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
20139      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20140      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
20141      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20142      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20143      // MIs[1] Operand 1
20144      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
20145      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
20146      GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0,
20147      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
20148      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID,
20149      GIM_CheckIsSafeToFold, /*InsnID*/1,
20150      // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F)  =>  (MOVN_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, AFGR64:{ *:[f64] }:$F)
20151      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_D32_MM,
20152      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
20153      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
20154      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20155      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
20156      GIR_EraseFromParent, /*InsnID*/0,
20157      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20158      // GIR_Coverage, 2247,
20159      GIR_Done,
20160    // Label 1169: @49815
20161    GIM_Try, /*On fail goto*//*Label 1170*/ 49916, // Rule ID 1616 //
20162      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
20163      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20164      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
20165      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
20166      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
20167      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20168      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
20169      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20170      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20171      // MIs[1] Operand 1
20172      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
20173      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
20174      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
20175      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
20176      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
20177      GIM_CheckIsSafeToFold, /*InsnID*/1,
20178      // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F)  =>  (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR64:{ *:[i64] }:$F)
20179      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20180      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT,
20181      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
20182      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20183      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20184      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20185      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I64,
20186      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
20187      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
20188      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
20189      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
20190      GIR_EraseFromParent, /*InsnID*/0,
20191      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20192      // GIR_Coverage, 1616,
20193      GIR_Done,
20194    // Label 1170: @49916
20195    GIM_Try, /*On fail goto*//*Label 1171*/ 50017, // Rule ID 1617 //
20196      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
20197      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20198      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
20199      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
20200      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
20201      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20202      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
20203      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20204      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20205      // MIs[1] Operand 1
20206      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
20207      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
20208      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
20209      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
20210      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
20211      GIM_CheckIsSafeToFold, /*InsnID*/1,
20212      // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F)  =>  (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR64:{ *:[i64] }:$F)
20213      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20214      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu,
20215      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
20216      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20217      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20218      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20219      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I64,
20220      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
20221      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
20222      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
20223      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
20224      GIR_EraseFromParent, /*InsnID*/0,
20225      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20226      // GIR_Coverage, 1617,
20227      GIR_Done,
20228    // Label 1171: @50017
20229    GIM_Try, /*On fail goto*//*Label 1172*/ 50118, // Rule ID 1620 //
20230      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
20231      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20232      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
20233      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
20234      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
20235      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20236      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
20237      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20238      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20239      // MIs[1] Operand 1
20240      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
20241      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
20242      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
20243      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
20244      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
20245      GIM_CheckIsSafeToFold, /*InsnID*/1,
20246      // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F)  =>  (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR64:{ *:[i64] }:$F)
20247      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20248      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT,
20249      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
20250      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20251      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20252      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20253      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I64,
20254      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
20255      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
20256      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
20257      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
20258      GIR_EraseFromParent, /*InsnID*/0,
20259      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20260      // GIR_Coverage, 1620,
20261      GIR_Done,
20262    // Label 1172: @50118
20263    GIM_Try, /*On fail goto*//*Label 1173*/ 50219, // Rule ID 1621 //
20264      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
20265      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20266      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
20267      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
20268      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
20269      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20270      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
20271      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20272      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20273      // MIs[1] Operand 1
20274      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
20275      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
20276      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
20277      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
20278      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
20279      GIM_CheckIsSafeToFold, /*InsnID*/1,
20280      // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F)  =>  (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR64:{ *:[i64] }:$F)
20281      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20282      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu,
20283      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
20284      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20285      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20286      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20287      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I64,
20288      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
20289      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
20290      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
20291      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
20292      GIR_EraseFromParent, /*InsnID*/0,
20293      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20294      // GIR_Coverage, 1621,
20295      GIR_Done,
20296    // Label 1173: @50219
20297    GIM_Try, /*On fail goto*//*Label 1174*/ 50320, // Rule ID 1632 //
20298      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
20299      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20300      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
20301      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
20302      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
20303      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20304      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
20305      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
20306      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
20307      // MIs[1] Operand 1
20308      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
20309      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
20310      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
20311      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
20312      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
20313      GIM_CheckIsSafeToFold, /*InsnID*/1,
20314      // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F)  =>  (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR64:{ *:[i64] }:$F)
20315      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20316      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT64,
20317      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
20318      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20319      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20320      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20321      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I64,
20322      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
20323      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
20324      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
20325      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
20326      GIR_EraseFromParent, /*InsnID*/0,
20327      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20328      // GIR_Coverage, 1632,
20329      GIR_Done,
20330    // Label 1174: @50320
20331    GIM_Try, /*On fail goto*//*Label 1175*/ 50421, // Rule ID 1633 //
20332      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
20333      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20334      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
20335      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
20336      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
20337      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20338      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
20339      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
20340      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
20341      // MIs[1] Operand 1
20342      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
20343      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
20344      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
20345      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
20346      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
20347      GIM_CheckIsSafeToFold, /*InsnID*/1,
20348      // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F)  =>  (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR64:{ *:[i64] }:$F)
20349      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20350      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu64,
20351      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
20352      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20353      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20354      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20355      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I64,
20356      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
20357      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
20358      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
20359      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
20360      GIR_EraseFromParent, /*InsnID*/0,
20361      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20362      // GIR_Coverage, 1633,
20363      GIR_Done,
20364    // Label 1175: @50421
20365    GIM_Try, /*On fail goto*//*Label 1176*/ 50522, // Rule ID 1636 //
20366      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
20367      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20368      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
20369      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
20370      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
20371      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20372      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
20373      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
20374      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
20375      // MIs[1] Operand 1
20376      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
20377      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
20378      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
20379      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
20380      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
20381      GIM_CheckIsSafeToFold, /*InsnID*/1,
20382      // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F)  =>  (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), GPR64:{ *:[i64] }:$F)
20383      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20384      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT64,
20385      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
20386      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20387      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20388      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20389      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I64,
20390      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
20391      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
20392      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
20393      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
20394      GIR_EraseFromParent, /*InsnID*/0,
20395      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20396      // GIR_Coverage, 1636,
20397      GIR_Done,
20398    // Label 1176: @50522
20399    GIM_Try, /*On fail goto*//*Label 1177*/ 50623, // Rule ID 1637 //
20400      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
20401      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20402      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
20403      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
20404      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
20405      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20406      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
20407      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
20408      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
20409      // MIs[1] Operand 1
20410      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
20411      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
20412      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
20413      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
20414      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
20415      GIM_CheckIsSafeToFold, /*InsnID*/1,
20416      // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F)  =>  (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), GPR64:{ *:[i64] }:$F)
20417      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20418      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu64,
20419      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
20420      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20421      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20422      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20423      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I64,
20424      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
20425      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
20426      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
20427      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
20428      GIR_EraseFromParent, /*InsnID*/0,
20429      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20430      // GIR_Coverage, 1637,
20431      GIR_Done,
20432    // Label 1177: @50623
20433    GIM_Try, /*On fail goto*//*Label 1178*/ 50724, // Rule ID 1640 //
20434      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
20435      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20436      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
20437      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
20438      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
20439      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20440      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
20441      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20442      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20443      // MIs[1] Operand 1
20444      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
20445      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
20446      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
20447      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
20448      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
20449      GIM_CheckIsSafeToFold, /*InsnID*/1,
20450      // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F)  =>  (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR64:{ *:[i64] }:$F)
20451      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20452      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR,
20453      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
20454      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20455      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20456      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20457      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I64,
20458      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
20459      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
20460      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
20461      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
20462      GIR_EraseFromParent, /*InsnID*/0,
20463      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20464      // GIR_Coverage, 1640,
20465      GIR_Done,
20466    // Label 1178: @50724
20467    GIM_Try, /*On fail goto*//*Label 1179*/ 50825, // Rule ID 1644 //
20468      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
20469      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20470      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
20471      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
20472      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
20473      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20474      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
20475      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
20476      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
20477      // MIs[1] Operand 1
20478      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
20479      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
20480      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
20481      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
20482      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
20483      GIM_CheckIsSafeToFold, /*InsnID*/1,
20484      // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETEQ:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F)  =>  (MOVZ_I64_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR64:{ *:[i64] }:$F)
20485      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
20486      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR64,
20487      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
20488      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20489      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20490      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20491      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I64_I64,
20492      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
20493      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
20494      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
20495      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
20496      GIR_EraseFromParent, /*InsnID*/0,
20497      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20498      // GIR_Coverage, 1644,
20499      GIR_Done,
20500    // Label 1179: @50825
20501    GIM_Try, /*On fail goto*//*Label 1180*/ 50926, // Rule ID 1649 //
20502      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
20503      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20504      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
20505      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
20506      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
20507      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20508      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
20509      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20510      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20511      // MIs[1] Operand 1
20512      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
20513      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
20514      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
20515      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
20516      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
20517      GIM_CheckIsSafeToFold, /*InsnID*/1,
20518      // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F)  =>  (MOVN_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR64:{ *:[i64] }:$F)
20519      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20520      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR,
20521      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
20522      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20523      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20524      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20525      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_I64,
20526      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
20527      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
20528      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
20529      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
20530      GIR_EraseFromParent, /*InsnID*/0,
20531      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20532      // GIR_Coverage, 1649,
20533      GIR_Done,
20534    // Label 1180: @50926
20535    GIM_Try, /*On fail goto*//*Label 1181*/ 51027, // Rule ID 1655 //
20536      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
20537      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20538      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
20539      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
20540      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
20541      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20542      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
20543      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
20544      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
20545      // MIs[1] Operand 1
20546      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
20547      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
20548      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
20549      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
20550      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
20551      GIM_CheckIsSafeToFold, /*InsnID*/1,
20552      // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETNE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F)  =>  (MOVN_I64_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR64:{ *:[i64] }:$F)
20553      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
20554      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR64,
20555      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
20556      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20557      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20558      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20559      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_I64,
20560      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
20561      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
20562      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
20563      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
20564      GIR_EraseFromParent, /*InsnID*/0,
20565      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20566      // GIR_Coverage, 1655,
20567      GIR_Done,
20568    // Label 1181: @51027
20569    GIM_Try, /*On fail goto*//*Label 1182*/ 51128, // Rule ID 1684 //
20570      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
20571      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20572      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
20573      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
20574      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
20575      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20576      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
20577      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20578      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20579      // MIs[1] Operand 1
20580      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
20581      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
20582      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
20583      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
20584      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID,
20585      GIM_CheckIsSafeToFold, /*InsnID*/1,
20586      // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F)  =>  (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
20587      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20588      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT,
20589      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
20590      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20591      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20592      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20593      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D32,
20594      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
20595      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
20596      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
20597      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
20598      GIR_EraseFromParent, /*InsnID*/0,
20599      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20600      // GIR_Coverage, 1684,
20601      GIR_Done,
20602    // Label 1182: @51128
20603    GIM_Try, /*On fail goto*//*Label 1183*/ 51229, // Rule ID 1685 //
20604      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
20605      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20606      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
20607      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
20608      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
20609      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20610      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
20611      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20612      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20613      // MIs[1] Operand 1
20614      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
20615      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
20616      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
20617      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
20618      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID,
20619      GIM_CheckIsSafeToFold, /*InsnID*/1,
20620      // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F)  =>  (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
20621      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20622      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu,
20623      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
20624      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20625      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20626      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20627      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D32,
20628      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
20629      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
20630      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
20631      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
20632      GIR_EraseFromParent, /*InsnID*/0,
20633      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20634      // GIR_Coverage, 1685,
20635      GIR_Done,
20636    // Label 1183: @51229
20637    GIM_Try, /*On fail goto*//*Label 1184*/ 51330, // Rule ID 1688 //
20638      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
20639      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20640      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
20641      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
20642      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
20643      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20644      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
20645      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20646      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20647      // MIs[1] Operand 1
20648      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
20649      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
20650      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
20651      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
20652      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID,
20653      GIM_CheckIsSafeToFold, /*InsnID*/1,
20654      // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F)  =>  (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), AFGR64:{ *:[f64] }:$F)
20655      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20656      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT,
20657      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
20658      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20659      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20660      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20661      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D32,
20662      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
20663      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
20664      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
20665      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
20666      GIR_EraseFromParent, /*InsnID*/0,
20667      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20668      // GIR_Coverage, 1688,
20669      GIR_Done,
20670    // Label 1184: @51330
20671    GIM_Try, /*On fail goto*//*Label 1185*/ 51431, // Rule ID 1689 //
20672      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
20673      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20674      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
20675      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
20676      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
20677      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20678      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
20679      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20680      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20681      // MIs[1] Operand 1
20682      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
20683      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
20684      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
20685      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
20686      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID,
20687      GIM_CheckIsSafeToFold, /*InsnID*/1,
20688      // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F)  =>  (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), AFGR64:{ *:[f64] }:$F)
20689      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20690      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu,
20691      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
20692      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20693      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20694      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20695      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D32,
20696      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
20697      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
20698      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
20699      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
20700      GIR_EraseFromParent, /*InsnID*/0,
20701      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20702      // GIR_Coverage, 1689,
20703      GIR_Done,
20704    // Label 1185: @51431
20705    GIM_Try, /*On fail goto*//*Label 1186*/ 51532, // Rule ID 1692 //
20706      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
20707      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20708      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
20709      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
20710      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
20711      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20712      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
20713      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20714      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20715      // MIs[1] Operand 1
20716      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
20717      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
20718      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
20719      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
20720      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID,
20721      GIM_CheckIsSafeToFold, /*InsnID*/1,
20722      // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F)  =>  (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
20723      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20724      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR,
20725      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
20726      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20727      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20728      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20729      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D32,
20730      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
20731      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
20732      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
20733      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
20734      GIR_EraseFromParent, /*InsnID*/0,
20735      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20736      // GIR_Coverage, 1692,
20737      GIR_Done,
20738    // Label 1186: @51532
20739    GIM_Try, /*On fail goto*//*Label 1187*/ 51633, // Rule ID 1694 //
20740      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
20741      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20742      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
20743      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
20744      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
20745      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20746      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
20747      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20748      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20749      // MIs[1] Operand 1
20750      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
20751      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
20752      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
20753      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
20754      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID,
20755      GIM_CheckIsSafeToFold, /*InsnID*/1,
20756      // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F)  =>  (MOVN_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
20757      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20758      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR,
20759      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
20760      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20761      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20762      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20763      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_D32,
20764      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
20765      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
20766      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
20767      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
20768      GIR_EraseFromParent, /*InsnID*/0,
20769      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20770      // GIR_Coverage, 1694,
20771      GIR_Done,
20772    // Label 1187: @51633
20773    GIM_Try, /*On fail goto*//*Label 1188*/ 51734, // Rule ID 1697 //
20774      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
20775      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20776      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
20777      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
20778      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
20779      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20780      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
20781      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20782      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20783      // MIs[1] Operand 1
20784      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
20785      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
20786      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
20787      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
20788      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
20789      GIM_CheckIsSafeToFold, /*InsnID*/1,
20790      // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F)  =>  (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR64:{ *:[f64] }:$F)
20791      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20792      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT,
20793      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
20794      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20795      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20796      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20797      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D64,
20798      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
20799      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
20800      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
20801      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
20802      GIR_EraseFromParent, /*InsnID*/0,
20803      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20804      // GIR_Coverage, 1697,
20805      GIR_Done,
20806    // Label 1188: @51734
20807    GIM_Try, /*On fail goto*//*Label 1189*/ 51835, // Rule ID 1698 //
20808      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
20809      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20810      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
20811      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
20812      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
20813      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20814      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
20815      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20816      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20817      // MIs[1] Operand 1
20818      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
20819      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
20820      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
20821      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
20822      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
20823      GIM_CheckIsSafeToFold, /*InsnID*/1,
20824      // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F)  =>  (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR64:{ *:[f64] }:$F)
20825      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20826      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu,
20827      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
20828      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20829      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20830      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20831      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D64,
20832      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
20833      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
20834      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
20835      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
20836      GIR_EraseFromParent, /*InsnID*/0,
20837      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20838      // GIR_Coverage, 1698,
20839      GIR_Done,
20840    // Label 1189: @51835
20841    GIM_Try, /*On fail goto*//*Label 1190*/ 51936, // Rule ID 1701 //
20842      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
20843      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20844      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
20845      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
20846      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
20847      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20848      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
20849      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20850      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20851      // MIs[1] Operand 1
20852      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
20853      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
20854      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
20855      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
20856      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
20857      GIM_CheckIsSafeToFold, /*InsnID*/1,
20858      // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F)  =>  (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR64:{ *:[f64] }:$F)
20859      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20860      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT,
20861      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
20862      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20863      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20864      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20865      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D64,
20866      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
20867      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
20868      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
20869      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
20870      GIR_EraseFromParent, /*InsnID*/0,
20871      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20872      // GIR_Coverage, 1701,
20873      GIR_Done,
20874    // Label 1190: @51936
20875    GIM_Try, /*On fail goto*//*Label 1191*/ 52037, // Rule ID 1702 //
20876      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
20877      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20878      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
20879      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
20880      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
20881      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20882      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
20883      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20884      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20885      // MIs[1] Operand 1
20886      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
20887      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
20888      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
20889      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
20890      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
20891      GIM_CheckIsSafeToFold, /*InsnID*/1,
20892      // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F)  =>  (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR64:{ *:[f64] }:$F)
20893      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20894      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu,
20895      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
20896      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20897      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20898      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20899      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D64,
20900      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
20901      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
20902      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
20903      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
20904      GIR_EraseFromParent, /*InsnID*/0,
20905      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20906      // GIR_Coverage, 1702,
20907      GIR_Done,
20908    // Label 1191: @52037
20909    GIM_Try, /*On fail goto*//*Label 1192*/ 52138, // Rule ID 1705 //
20910      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
20911      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20912      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
20913      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
20914      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
20915      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20916      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
20917      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
20918      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
20919      // MIs[1] Operand 1
20920      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
20921      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
20922      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
20923      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
20924      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
20925      GIM_CheckIsSafeToFold, /*InsnID*/1,
20926      // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F)  =>  (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR64:{ *:[f64] }:$F)
20927      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20928      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT64,
20929      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
20930      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20931      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20932      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20933      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D64,
20934      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
20935      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
20936      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
20937      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
20938      GIR_EraseFromParent, /*InsnID*/0,
20939      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20940      // GIR_Coverage, 1705,
20941      GIR_Done,
20942    // Label 1192: @52138
20943    GIM_Try, /*On fail goto*//*Label 1193*/ 52239, // Rule ID 1706 //
20944      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
20945      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20946      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
20947      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
20948      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
20949      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20950      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
20951      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
20952      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
20953      // MIs[1] Operand 1
20954      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
20955      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
20956      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
20957      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
20958      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
20959      GIM_CheckIsSafeToFold, /*InsnID*/1,
20960      // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F)  =>  (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR64:{ *:[f64] }:$F)
20961      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20962      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu64,
20963      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
20964      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20965      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20966      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20967      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D64,
20968      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
20969      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
20970      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
20971      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
20972      GIR_EraseFromParent, /*InsnID*/0,
20973      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20974      // GIR_Coverage, 1706,
20975      GIR_Done,
20976    // Label 1193: @52239
20977    GIM_Try, /*On fail goto*//*Label 1194*/ 52340, // Rule ID 1709 //
20978      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
20979      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20980      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
20981      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
20982      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
20983      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20984      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
20985      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
20986      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
20987      // MIs[1] Operand 1
20988      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
20989      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
20990      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
20991      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
20992      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
20993      GIM_CheckIsSafeToFold, /*InsnID*/1,
20994      // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F)  =>  (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), FGR64:{ *:[f64] }:$F)
20995      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20996      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT64,
20997      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
20998      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20999      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21000      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21001      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D64,
21002      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
21003      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
21004      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
21005      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
21006      GIR_EraseFromParent, /*InsnID*/0,
21007      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21008      // GIR_Coverage, 1709,
21009      GIR_Done,
21010    // Label 1194: @52340
21011    GIM_Try, /*On fail goto*//*Label 1195*/ 52441, // Rule ID 1710 //
21012      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
21013      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
21014      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
21015      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
21016      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
21017      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21018      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
21019      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
21020      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
21021      // MIs[1] Operand 1
21022      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
21023      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
21024      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
21025      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
21026      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
21027      GIM_CheckIsSafeToFold, /*InsnID*/1,
21028      // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F)  =>  (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), FGR64:{ *:[f64] }:$F)
21029      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21030      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu64,
21031      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
21032      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21033      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21034      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21035      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D64,
21036      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
21037      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
21038      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
21039      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
21040      GIR_EraseFromParent, /*InsnID*/0,
21041      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21042      // GIR_Coverage, 1710,
21043      GIR_Done,
21044    // Label 1195: @52441
21045    GIM_Try, /*On fail goto*//*Label 1196*/ 52542, // Rule ID 1713 //
21046      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
21047      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
21048      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
21049      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
21050      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
21051      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21052      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
21053      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21054      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21055      // MIs[1] Operand 1
21056      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
21057      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
21058      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
21059      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
21060      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
21061      GIM_CheckIsSafeToFold, /*InsnID*/1,
21062      // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F)  =>  (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR64:{ *:[f64] }:$F)
21063      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21064      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR,
21065      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
21066      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21067      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21068      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21069      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D64,
21070      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
21071      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
21072      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
21073      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
21074      GIR_EraseFromParent, /*InsnID*/0,
21075      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21076      // GIR_Coverage, 1713,
21077      GIR_Done,
21078    // Label 1196: @52542
21079    GIM_Try, /*On fail goto*//*Label 1197*/ 52643, // Rule ID 1715 //
21080      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
21081      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
21082      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
21083      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
21084      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
21085      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21086      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
21087      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
21088      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
21089      // MIs[1] Operand 1
21090      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
21091      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
21092      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
21093      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
21094      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
21095      GIM_CheckIsSafeToFold, /*InsnID*/1,
21096      // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETEQ:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F)  =>  (MOVZ_I64_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR64:{ *:[f64] }:$F)
21097      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
21098      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR64,
21099      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
21100      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21101      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21102      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21103      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I64_D64,
21104      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
21105      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
21106      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
21107      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
21108      GIR_EraseFromParent, /*InsnID*/0,
21109      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21110      // GIR_Coverage, 1715,
21111      GIR_Done,
21112    // Label 1197: @52643
21113    GIM_Try, /*On fail goto*//*Label 1198*/ 52744, // Rule ID 1717 //
21114      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
21115      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
21116      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
21117      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
21118      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
21119      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21120      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
21121      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21122      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21123      // MIs[1] Operand 1
21124      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
21125      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
21126      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
21127      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
21128      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
21129      GIM_CheckIsSafeToFold, /*InsnID*/1,
21130      // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F)  =>  (MOVN_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR64:{ *:[f64] }:$F)
21131      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21132      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR,
21133      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
21134      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21135      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21136      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21137      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_D64,
21138      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
21139      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
21140      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
21141      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
21142      GIR_EraseFromParent, /*InsnID*/0,
21143      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21144      // GIR_Coverage, 1717,
21145      GIR_Done,
21146    // Label 1198: @52744
21147    GIM_Try, /*On fail goto*//*Label 1199*/ 52845, // Rule ID 1720 //
21148      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
21149      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
21150      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
21151      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
21152      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
21153      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21154      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
21155      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
21156      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
21157      // MIs[1] Operand 1
21158      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
21159      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
21160      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
21161      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
21162      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
21163      GIM_CheckIsSafeToFold, /*InsnID*/1,
21164      // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETNE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F)  =>  (MOVN_I64_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR64:{ *:[f64] }:$F)
21165      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
21166      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR64,
21167      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
21168      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21169      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21170      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21171      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_D64,
21172      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
21173      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
21174      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
21175      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
21176      GIR_EraseFromParent, /*InsnID*/0,
21177      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21178      // GIR_Coverage, 1720,
21179      GIR_Done,
21180    // Label 1199: @52845
21181    GIM_Try, /*On fail goto*//*Label 1200*/ 52946, // Rule ID 2235 //
21182      GIM_CheckFeatures, GIFBS_InMicroMips_NotFP64bit_NotMips32r6,
21183      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
21184      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
21185      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
21186      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
21187      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21188      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
21189      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21190      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21191      // MIs[1] Operand 1
21192      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
21193      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
21194      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
21195      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
21196      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID,
21197      GIM_CheckIsSafeToFold, /*InsnID*/1,
21198      // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F)  =>  (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
21199      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21200      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT_MM,
21201      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
21202      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21203      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21204      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21205      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D32_MM,
21206      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
21207      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
21208      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
21209      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
21210      GIR_EraseFromParent, /*InsnID*/0,
21211      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21212      // GIR_Coverage, 2235,
21213      GIR_Done,
21214    // Label 1200: @52946
21215    GIM_Try, /*On fail goto*//*Label 1201*/ 53047, // Rule ID 2236 //
21216      GIM_CheckFeatures, GIFBS_InMicroMips_NotFP64bit_NotMips32r6,
21217      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
21218      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
21219      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
21220      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
21221      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21222      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
21223      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21224      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21225      // MIs[1] Operand 1
21226      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
21227      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
21228      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
21229      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
21230      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID,
21231      GIM_CheckIsSafeToFold, /*InsnID*/1,
21232      // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F)  =>  (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
21233      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21234      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu_MM,
21235      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
21236      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21237      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21238      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21239      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D32_MM,
21240      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
21241      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
21242      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
21243      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
21244      GIR_EraseFromParent, /*InsnID*/0,
21245      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21246      // GIR_Coverage, 2236,
21247      GIR_Done,
21248    // Label 1201: @53047
21249    GIM_Try, /*On fail goto*//*Label 1202*/ 53148, // Rule ID 2239 //
21250      GIM_CheckFeatures, GIFBS_InMicroMips_NotFP64bit_NotMips32r6,
21251      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
21252      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
21253      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
21254      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
21255      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21256      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
21257      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21258      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21259      // MIs[1] Operand 1
21260      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
21261      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
21262      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
21263      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
21264      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID,
21265      GIM_CheckIsSafeToFold, /*InsnID*/1,
21266      // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F)  =>  (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), AFGR64:{ *:[f64] }:$F)
21267      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21268      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT_MM,
21269      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
21270      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21271      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21272      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21273      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D32_MM,
21274      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
21275      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
21276      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
21277      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
21278      GIR_EraseFromParent, /*InsnID*/0,
21279      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21280      // GIR_Coverage, 2239,
21281      GIR_Done,
21282    // Label 1202: @53148
21283    GIM_Try, /*On fail goto*//*Label 1203*/ 53249, // Rule ID 2240 //
21284      GIM_CheckFeatures, GIFBS_InMicroMips_NotFP64bit_NotMips32r6,
21285      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
21286      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
21287      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
21288      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
21289      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21290      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
21291      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21292      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21293      // MIs[1] Operand 1
21294      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
21295      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
21296      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
21297      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
21298      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID,
21299      GIM_CheckIsSafeToFold, /*InsnID*/1,
21300      // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F)  =>  (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), AFGR64:{ *:[f64] }:$F)
21301      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21302      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu_MM,
21303      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
21304      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21305      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21306      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21307      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D32_MM,
21308      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
21309      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
21310      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
21311      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
21312      GIR_EraseFromParent, /*InsnID*/0,
21313      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21314      // GIR_Coverage, 2240,
21315      GIR_Done,
21316    // Label 1203: @53249
21317    GIM_Try, /*On fail goto*//*Label 1204*/ 53350, // Rule ID 2243 //
21318      GIM_CheckFeatures, GIFBS_InMicroMips_NotFP64bit_NotMips32r6,
21319      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
21320      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
21321      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
21322      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
21323      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21324      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
21325      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21326      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21327      // MIs[1] Operand 1
21328      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
21329      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
21330      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
21331      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
21332      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID,
21333      GIM_CheckIsSafeToFold, /*InsnID*/1,
21334      // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F)  =>  (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
21335      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21336      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR_MM,
21337      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
21338      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21339      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21340      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21341      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D32_MM,
21342      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
21343      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
21344      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
21345      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
21346      GIR_EraseFromParent, /*InsnID*/0,
21347      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21348      // GIR_Coverage, 2243,
21349      GIR_Done,
21350    // Label 1204: @53350
21351    GIM_Try, /*On fail goto*//*Label 1205*/ 53451, // Rule ID 2245 //
21352      GIM_CheckFeatures, GIFBS_InMicroMips_NotFP64bit_NotMips32r6,
21353      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
21354      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
21355      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
21356      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
21357      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21358      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
21359      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21360      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21361      // MIs[1] Operand 1
21362      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
21363      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
21364      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
21365      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
21366      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID,
21367      GIM_CheckIsSafeToFold, /*InsnID*/1,
21368      // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F)  =>  (MOVN_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
21369      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21370      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR_MM,
21371      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
21372      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21373      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21374      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21375      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_D32_MM,
21376      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
21377      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
21378      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
21379      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
21380      GIR_EraseFromParent, /*InsnID*/0,
21381      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21382      // GIR_Coverage, 2245,
21383      GIR_Done,
21384    // Label 1205: @53451
21385    GIM_Try, /*On fail goto*//*Label 1206*/ 53490, // Rule ID 284 //
21386      GIM_CheckFeatures, GIFBS_HasStdEnc_NotMips4_32,
21387      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
21388      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
21389      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
21390      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
21391      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
21392      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
21393      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
21394      // (select:{ *:[i64] } GPR32Opnd:{ *:[i32] }:$cond, GPR64Opnd:{ *:[i64] }:$T, GPR64Opnd:{ *:[i64] }:$F)  =>  (PseudoSELECT_I64:{ *:[i64] } GPR32Opnd:{ *:[i32] }:$cond, GPR64Opnd:{ *:[i64] }:$T, GPR64Opnd:{ *:[i64] }:$F)
21395      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PseudoSELECT_I64,
21396      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21397      // GIR_Coverage, 284,
21398      GIR_Done,
21399    // Label 1206: @53490
21400    GIM_Try, /*On fail goto*//*Label 1207*/ 53529, // Rule ID 286 //
21401      GIM_CheckFeatures, GIFBS_HasStdEnc_NotFP64bit_NotMips4_32,
21402      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
21403      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
21404      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
21405      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
21406      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
21407      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
21408      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID,
21409      // (select:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$cond, AFGR64Opnd:{ *:[f64] }:$T, AFGR64Opnd:{ *:[f64] }:$F)  =>  (PseudoSELECT_D32:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$cond, AFGR64Opnd:{ *:[f64] }:$T, AFGR64Opnd:{ *:[f64] }:$F)
21410      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PseudoSELECT_D32,
21411      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21412      // GIR_Coverage, 286,
21413      GIR_Done,
21414    // Label 1207: @53529
21415    GIM_Try, /*On fail goto*//*Label 1208*/ 53568, // Rule ID 287 //
21416      GIM_CheckFeatures, GIFBS_HasStdEnc_IsFP64bit_NotMips4_32,
21417      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
21418      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
21419      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
21420      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
21421      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
21422      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
21423      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
21424      // (select:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$cond, FGR64Opnd:{ *:[f64] }:$T, FGR64Opnd:{ *:[f64] }:$F)  =>  (PseudoSELECT_D64:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$cond, FGR64Opnd:{ *:[f64] }:$T, FGR64Opnd:{ *:[f64] }:$F)
21425      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PseudoSELECT_D64,
21426      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21427      // GIR_Coverage, 287,
21428      GIR_Done,
21429    // Label 1208: @53568
21430    GIM_Try, /*On fail goto*//*Label 1209*/ 53624, // Rule ID 1650 //
21431      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
21432      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
21433      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
21434      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
21435      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
21436      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
21437      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
21438      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
21439      // (select:{ *:[i64] } GPR32:{ *:[i32] }:$cond, GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F)  =>  (MOVN_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR32:{ *:[i32] }:$cond, GPR64:{ *:[i64] }:$F)
21440      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_I64,
21441      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
21442      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
21443      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond
21444      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
21445      GIR_EraseFromParent, /*InsnID*/0,
21446      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21447      // GIR_Coverage, 1650,
21448      GIR_Done,
21449    // Label 1209: @53624
21450    GIM_Try, /*On fail goto*//*Label 1210*/ 53680, // Rule ID 1656 //
21451      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
21452      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
21453      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
21454      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
21455      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
21456      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
21457      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
21458      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
21459      // (select:{ *:[i64] } GPR64:{ *:[i64] }:$cond, GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F)  =>  (MOVN_I64_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$cond, GPR64:{ *:[i64] }:$F)
21460      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_I64,
21461      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
21462      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
21463      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond
21464      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
21465      GIR_EraseFromParent, /*InsnID*/0,
21466      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21467      // GIR_Coverage, 1656,
21468      GIR_Done,
21469    // Label 1210: @53680
21470    GIM_Try, /*On fail goto*//*Label 1211*/ 53736, // Rule ID 1695 //
21471      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
21472      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
21473      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
21474      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
21475      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
21476      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
21477      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
21478      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID,
21479      // (select:{ *:[f64] } GPR32:{ *:[i32] }:$cond, AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F)  =>  (MOVN_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$cond, AFGR64:{ *:[f64] }:$F)
21480      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_D32,
21481      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
21482      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
21483      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond
21484      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
21485      GIR_EraseFromParent, /*InsnID*/0,
21486      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21487      // GIR_Coverage, 1695,
21488      GIR_Done,
21489    // Label 1211: @53736
21490    GIM_Try, /*On fail goto*//*Label 1212*/ 53792, // Rule ID 1718 //
21491      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
21492      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
21493      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
21494      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
21495      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
21496      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
21497      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
21498      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
21499      // (select:{ *:[f64] } GPR32:{ *:[i32] }:$cond, FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F)  =>  (MOVN_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$cond, FGR64:{ *:[f64] }:$F)
21500      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_D64,
21501      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
21502      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
21503      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond
21504      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
21505      GIR_EraseFromParent, /*InsnID*/0,
21506      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21507      // GIR_Coverage, 1718,
21508      GIR_Done,
21509    // Label 1212: @53792
21510    GIM_Try, /*On fail goto*//*Label 1213*/ 53848, // Rule ID 1721 //
21511      GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
21512      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
21513      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
21514      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
21515      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
21516      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
21517      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
21518      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
21519      // (select:{ *:[f64] } GPR64:{ *:[i64] }:$cond, FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F)  =>  (MOVN_I64_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR64:{ *:[i64] }:$cond, FGR64:{ *:[f64] }:$F)
21520      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_D64,
21521      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
21522      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
21523      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond
21524      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
21525      GIR_EraseFromParent, /*InsnID*/0,
21526      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21527      // GIR_Coverage, 1721,
21528      GIR_Done,
21529    // Label 1213: @53848
21530    GIM_Try, /*On fail goto*//*Label 1214*/ 53904, // Rule ID 2246 //
21531      GIM_CheckFeatures, GIFBS_InMicroMips_NotFP64bit_NotMips32r6,
21532      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
21533      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
21534      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
21535      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
21536      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
21537      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
21538      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID,
21539      // (select:{ *:[f64] } GPR32:{ *:[i32] }:$cond, AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F)  =>  (MOVN_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$cond, AFGR64:{ *:[f64] }:$F)
21540      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_D32_MM,
21541      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
21542      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
21543      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond
21544      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
21545      GIR_EraseFromParent, /*InsnID*/0,
21546      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21547      // GIR_Coverage, 2246,
21548      GIR_Done,
21549    // Label 1214: @53904
21550    GIM_Try, /*On fail goto*//*Label 1215*/ 53984, // Rule ID 1754 //
21551      GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc,
21552      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
21553      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
21554      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
21555      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
21556      // (select:{ *:[i64] } i64:{ *:[i64] }:$cond, i64:{ *:[i64] }:$t, i64:{ *:[i64] }:$f)  =>  (OR64:{ *:[i64] } (SELNEZ64:{ *:[i64] } i64:{ *:[i64] }:$t, i64:{ *:[i64] }:$cond), (SELEQZ64:{ *:[i64] } i64:{ *:[i64] }:$f, i64:{ *:[i64] }:$cond))
21557      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
21558      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
21559      GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SELEQZ64,
21560      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
21561      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // f
21562      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // cond
21563      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
21564      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SELNEZ64,
21565      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
21566      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // t
21567      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // cond
21568      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21569      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::OR64,
21570      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
21571      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
21572      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
21573      GIR_EraseFromParent, /*InsnID*/0,
21574      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21575      // GIR_Coverage, 1754,
21576      GIR_Done,
21577    // Label 1215: @53984
21578    GIM_Try, /*On fail goto*//*Label 1216*/ 54096, // Rule ID 1765 //
21579      GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc,
21580      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
21581      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
21582      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
21583      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
21584      // (select:{ *:[i64] } i32:{ *:[i32] }:$cond, i64:{ *:[i64] }:$t, i64:{ *:[i64] }:$f)  =>  (OR64:{ *:[i64] } (SELNEZ64:{ *:[i64] } i64:{ *:[i64] }:$t, (SLL64_32:{ *:[i64] } i32:{ *:[i32] }:$cond)), (SELEQZ64:{ *:[i64] } i64:{ *:[i64] }:$f, (SLL64_32:{ *:[i64] } i32:{ *:[i32] }:$cond)))
21585      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
21586      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
21587      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
21588      GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
21589      GIR_BuildMI, /*InsnID*/4, /*Opcode*/Mips::SLL64_32,
21590      GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
21591      GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // cond
21592      GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
21593      GIR_BuildMI, /*InsnID*/3, /*Opcode*/Mips::SELEQZ64,
21594      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
21595      GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // f
21596      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
21597      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
21598      GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SLL64_32,
21599      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
21600      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // cond
21601      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
21602      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SELNEZ64,
21603      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
21604      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // t
21605      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
21606      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21607      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::OR64,
21608      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
21609      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
21610      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0,
21611      GIR_EraseFromParent, /*InsnID*/0,
21612      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21613      // GIR_Coverage, 1765,
21614      GIR_Done,
21615    // Label 1216: @54096
21616    GIM_Reject,
21617    // Label 1077: @54097
21618    GIM_Reject,
21619    // Label 30: @54098
21620    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1219*/ 54184,
21621    /*GILLT_s32*//*Label 1217*/ 54106,
21622    /*GILLT_s64*//*Label 1218*/ 54152,
21623    // Label 1217: @54106
21624    GIM_Try, /*On fail goto*//*Label 1220*/ 54151,
21625      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
21626      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
21627      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
21628      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
21629      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
21630      GIM_Try, /*On fail goto*//*Label 1221*/ 54139, // Rule ID 319 //
21631        GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
21632        // (mulhu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MUHU:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
21633        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUHU,
21634        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21635        // GIR_Coverage, 319,
21636        GIR_Done,
21637      // Label 1221: @54139
21638      GIM_Try, /*On fail goto*//*Label 1222*/ 54150, // Rule ID 1169 //
21639        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
21640        // (mulhu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MUHU_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
21641        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUHU_MMR6,
21642        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21643        // GIR_Coverage, 1169,
21644        GIR_Done,
21645      // Label 1222: @54150
21646      GIM_Reject,
21647    // Label 1220: @54151
21648    GIM_Reject,
21649    // Label 1218: @54152
21650    GIM_Try, /*On fail goto*//*Label 1223*/ 54183, // Rule ID 334 //
21651      GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
21652      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
21653      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
21654      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
21655      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
21656      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
21657      // (mulhu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DMUHU:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
21658      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMUHU,
21659      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21660      // GIR_Coverage, 334,
21661      GIR_Done,
21662    // Label 1223: @54183
21663    GIM_Reject,
21664    // Label 1219: @54184
21665    GIM_Reject,
21666    // Label 31: @54185
21667    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1226*/ 54271,
21668    /*GILLT_s32*//*Label 1224*/ 54193,
21669    /*GILLT_s64*//*Label 1225*/ 54239,
21670    // Label 1224: @54193
21671    GIM_Try, /*On fail goto*//*Label 1227*/ 54238,
21672      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
21673      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
21674      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
21675      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
21676      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
21677      GIM_Try, /*On fail goto*//*Label 1228*/ 54226, // Rule ID 318 //
21678        GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
21679        // (mulhs:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MUH:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
21680        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUH,
21681        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21682        // GIR_Coverage, 318,
21683        GIR_Done,
21684      // Label 1228: @54226
21685      GIM_Try, /*On fail goto*//*Label 1229*/ 54237, // Rule ID 1168 //
21686        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
21687        // (mulhs:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MUH_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
21688        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUH_MMR6,
21689        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21690        // GIR_Coverage, 1168,
21691        GIR_Done,
21692      // Label 1229: @54237
21693      GIM_Reject,
21694    // Label 1227: @54238
21695    GIM_Reject,
21696    // Label 1225: @54239
21697    GIM_Try, /*On fail goto*//*Label 1230*/ 54270, // Rule ID 333 //
21698      GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
21699      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
21700      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
21701      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
21702      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
21703      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
21704      // (mulhs:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DMUH:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
21705      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMUH,
21706      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21707      // GIR_Coverage, 333,
21708      GIR_Done,
21709    // Label 1230: @54270
21710    GIM_Reject,
21711    // Label 1226: @54271
21712    GIM_Reject,
21713    // Label 32: @54272
21714    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 7, /*)*//*default:*//*Label 1235*/ 55150,
21715    /*GILLT_s32*//*Label 1231*/ 54284,
21716    /*GILLT_s64*//*Label 1232*/ 54484, 0,
21717    /*GILLT_v2s64*//*Label 1233*/ 54832, 0,
21718    /*GILLT_v4s32*//*Label 1234*/ 54991,
21719    // Label 1231: @54284
21720    GIM_Try, /*On fail goto*//*Label 1236*/ 54483,
21721      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
21722      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
21723      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
21724      GIM_Try, /*On fail goto*//*Label 1237*/ 54355, // Rule ID 157 //
21725        GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6,
21726        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21727        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
21728        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
21729        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21730        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
21731        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
21732        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
21733        GIM_CheckIsSafeToFold, /*InsnID*/1,
21734        // (fadd:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr)  =>  (MADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
21735        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADD_S,
21736        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
21737        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fr
21738        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
21739        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
21740        GIR_EraseFromParent, /*InsnID*/0,
21741        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21742        // GIR_Coverage, 157,
21743        GIR_Done,
21744      // Label 1237: @54355
21745      GIM_Try, /*On fail goto*//*Label 1238*/ 54412, // Rule ID 2307 //
21746        GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6,
21747        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
21748        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
21749        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
21750        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
21751        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21752        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
21753        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
21754        GIM_CheckIsSafeToFold, /*InsnID*/1,
21755        // (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft))  =>  (MADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
21756        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADD_S,
21757        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
21758        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fr
21759        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
21760        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
21761        GIR_EraseFromParent, /*InsnID*/0,
21762        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21763        // GIR_Coverage, 2307,
21764        GIR_Done,
21765      // Label 1238: @54412
21766      GIM_Try, /*On fail goto*//*Label 1239*/ 54431, // Rule ID 145 //
21767        GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
21768        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
21769        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
21770        // (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)  =>  (FADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
21771        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FADD_S,
21772        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21773        // GIR_Coverage, 145,
21774        GIR_Done,
21775      // Label 1239: @54431
21776      GIM_Try, /*On fail goto*//*Label 1240*/ 54450, // Rule ID 1118 //
21777        GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat,
21778        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
21779        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
21780        // (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)  =>  (FADD_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
21781        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FADD_S_MM,
21782        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21783        // GIR_Coverage, 1118,
21784        GIR_Done,
21785      // Label 1240: @54450
21786      GIM_Try, /*On fail goto*//*Label 1241*/ 54482, // Rule ID 1176 //
21787        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
21788        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
21789        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
21790        // (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)  =>  (FADD_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs)
21791        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FADD_S_MMR6,
21792        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
21793        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ft
21794        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fs
21795        GIR_EraseFromParent, /*InsnID*/0,
21796        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21797        // GIR_Coverage, 1176,
21798        GIR_Done,
21799      // Label 1241: @54482
21800      GIM_Reject,
21801    // Label 1236: @54483
21802    GIM_Reject,
21803    // Label 1232: @54484
21804    GIM_Try, /*On fail goto*//*Label 1242*/ 54831,
21805      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
21806      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
21807      GIM_Try, /*On fail goto*//*Label 1243*/ 54555, // Rule ID 159 //
21808        GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
21809        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
21810        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21811        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
21812        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
21813        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
21814        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
21815        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
21816        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
21817        GIM_CheckIsSafeToFold, /*InsnID*/1,
21818        // (fadd:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr)  =>  (MADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
21819        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADD_D32,
21820        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
21821        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fr
21822        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
21823        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
21824        GIR_EraseFromParent, /*InsnID*/0,
21825        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21826        // GIR_Coverage, 159,
21827        GIR_Done,
21828      // Label 1243: @54555
21829      GIM_Try, /*On fail goto*//*Label 1244*/ 54616, // Rule ID 161 //
21830        GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6,
21831        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
21832        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21833        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
21834        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
21835        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
21836        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
21837        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
21838        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
21839        GIM_CheckIsSafeToFold, /*InsnID*/1,
21840        // (fadd:{ *:[f64] } (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr)  =>  (MADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
21841        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADD_D64,
21842        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
21843        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fr
21844        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
21845        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
21846        GIR_EraseFromParent, /*InsnID*/0,
21847        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21848        // GIR_Coverage, 161,
21849        GIR_Done,
21850      // Label 1244: @54616
21851      GIM_Try, /*On fail goto*//*Label 1245*/ 54677, // Rule ID 2308 //
21852        GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
21853        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
21854        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
21855        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
21856        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
21857        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
21858        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
21859        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
21860        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
21861        GIM_CheckIsSafeToFold, /*InsnID*/1,
21862        // (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft))  =>  (MADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
21863        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADD_D32,
21864        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
21865        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fr
21866        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
21867        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
21868        GIR_EraseFromParent, /*InsnID*/0,
21869        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21870        // GIR_Coverage, 2308,
21871        GIR_Done,
21872      // Label 1245: @54677
21873      GIM_Try, /*On fail goto*//*Label 1246*/ 54738, // Rule ID 2309 //
21874        GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6,
21875        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
21876        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
21877        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
21878        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
21879        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
21880        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
21881        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
21882        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
21883        GIM_CheckIsSafeToFold, /*InsnID*/1,
21884        // (fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft))  =>  (MADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
21885        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADD_D64,
21886        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
21887        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fr
21888        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
21889        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
21890        GIR_EraseFromParent, /*InsnID*/0,
21891        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21892        // GIR_Coverage, 2309,
21893        GIR_Done,
21894      // Label 1246: @54738
21895      GIM_Try, /*On fail goto*//*Label 1247*/ 54761, // Rule ID 146 //
21896        GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips,
21897        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
21898        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
21899        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
21900        // (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)  =>  (FADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
21901        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FADD_D32,
21902        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21903        // GIR_Coverage, 146,
21904        GIR_Done,
21905      // Label 1247: @54761
21906      GIM_Try, /*On fail goto*//*Label 1248*/ 54784, // Rule ID 147 //
21907        GIM_CheckFeatures, GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips,
21908        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
21909        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
21910        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
21911        // (fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)  =>  (FADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
21912        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FADD_D64,
21913        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21914        // GIR_Coverage, 147,
21915        GIR_Done,
21916      // Label 1248: @54784
21917      GIM_Try, /*On fail goto*//*Label 1249*/ 54807, // Rule ID 1122 //
21918        GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit,
21919        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
21920        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
21921        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
21922        // (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)  =>  (FADD_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
21923        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FADD_D32_MM,
21924        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21925        // GIR_Coverage, 1122,
21926        GIR_Done,
21927      // Label 1249: @54807
21928      GIM_Try, /*On fail goto*//*Label 1250*/ 54830, // Rule ID 1123 //
21929        GIM_CheckFeatures, GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat,
21930        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
21931        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
21932        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
21933        // (fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)  =>  (FADD_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
21934        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FADD_D64_MM,
21935        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21936        // GIR_Coverage, 1123,
21937        GIR_Done,
21938      // Label 1250: @54830
21939      GIM_Reject,
21940    // Label 1242: @54831
21941    GIM_Reject,
21942    // Label 1233: @54832
21943    GIM_Try, /*On fail goto*//*Label 1251*/ 54990,
21944      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
21945      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
21946      GIM_Try, /*On fail goto*//*Label 1252*/ 54904, // Rule ID 2411 //
21947        GIM_CheckFeatures, GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc,
21948        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
21949        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21950        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
21951        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
21952        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
21953        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
21954        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
21955        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
21956        GIM_CheckIsSafeToFold, /*InsnID*/1,
21957        // (fadd:{ *:[v2f64] } (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt), MSA128DOpnd:{ *:[v2f64] }:$wd)  =>  (FMADD_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
21958        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMADD_D,
21959        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd
21960        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd
21961        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
21962        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
21963        GIR_EraseFromParent, /*InsnID*/0,
21964        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21965        // GIR_Coverage, 2411,
21966        GIR_Done,
21967      // Label 1252: @54904
21968      GIM_Try, /*On fail goto*//*Label 1253*/ 54966, // Rule ID 1949 //
21969        GIM_CheckFeatures, GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc,
21970        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
21971        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
21972        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
21973        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
21974        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
21975        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
21976        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
21977        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
21978        GIM_CheckIsSafeToFold, /*InsnID*/1,
21979        // (fadd:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt))  =>  (FMADD_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
21980        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMADD_D,
21981        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd
21982        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd
21983        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
21984        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
21985        GIR_EraseFromParent, /*InsnID*/0,
21986        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21987        // GIR_Coverage, 1949,
21988        GIR_Done,
21989      // Label 1253: @54966
21990      GIM_Try, /*On fail goto*//*Label 1254*/ 54989, // Rule ID 659 //
21991        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
21992        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
21993        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
21994        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
21995        // (fadd:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FADD_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
21996        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FADD_D,
21997        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21998        // GIR_Coverage, 659,
21999        GIR_Done,
22000      // Label 1254: @54989
22001      GIM_Reject,
22002    // Label 1251: @54990
22003    GIM_Reject,
22004    // Label 1234: @54991
22005    GIM_Try, /*On fail goto*//*Label 1255*/ 55149,
22006      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
22007      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
22008      GIM_Try, /*On fail goto*//*Label 1256*/ 55063, // Rule ID 2410 //
22009        GIM_CheckFeatures, GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc,
22010        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
22011        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22012        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
22013        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
22014        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
22015        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
22016        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
22017        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
22018        GIM_CheckIsSafeToFold, /*InsnID*/1,
22019        // (fadd:{ *:[v4f32] } (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt), MSA128WOpnd:{ *:[v4f32] }:$wd)  =>  (FMADD_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
22020        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMADD_W,
22021        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd
22022        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd
22023        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
22024        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
22025        GIR_EraseFromParent, /*InsnID*/0,
22026        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22027        // GIR_Coverage, 2410,
22028        GIR_Done,
22029      // Label 1256: @55063
22030      GIM_Try, /*On fail goto*//*Label 1257*/ 55125, // Rule ID 1948 //
22031        GIM_CheckFeatures, GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc,
22032        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
22033        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
22034        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
22035        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
22036        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
22037        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
22038        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
22039        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
22040        GIM_CheckIsSafeToFold, /*InsnID*/1,
22041        // (fadd:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt))  =>  (FMADD_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
22042        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMADD_W,
22043        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd
22044        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd
22045        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
22046        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
22047        GIR_EraseFromParent, /*InsnID*/0,
22048        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22049        // GIR_Coverage, 1948,
22050        GIR_Done,
22051      // Label 1257: @55125
22052      GIM_Try, /*On fail goto*//*Label 1258*/ 55148, // Rule ID 658 //
22053        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
22054        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
22055        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
22056        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
22057        // (fadd:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FADD_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
22058        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FADD_W,
22059        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22060        // GIR_Coverage, 658,
22061        GIR_Done,
22062      // Label 1258: @55148
22063      GIM_Reject,
22064    // Label 1255: @55149
22065    GIM_Reject,
22066    // Label 1235: @55150
22067    GIM_Reject,
22068    // Label 33: @55151
22069    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 7, /*)*//*default:*//*Label 1263*/ 55726,
22070    /*GILLT_s32*//*Label 1259*/ 55163,
22071    /*GILLT_s64*//*Label 1260*/ 55306, 0,
22072    /*GILLT_v2s64*//*Label 1261*/ 55532, 0,
22073    /*GILLT_v4s32*//*Label 1262*/ 55629,
22074    // Label 1259: @55163
22075    GIM_Try, /*On fail goto*//*Label 1264*/ 55305,
22076      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
22077      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
22078      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
22079      GIM_Try, /*On fail goto*//*Label 1265*/ 55234, // Rule ID 158 //
22080        GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6,
22081        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22082        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
22083        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
22084        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22085        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
22086        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
22087        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
22088        GIM_CheckIsSafeToFold, /*InsnID*/1,
22089        // (fsub:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr)  =>  (MSUB_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
22090        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUB_S,
22091        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
22092        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fr
22093        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
22094        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
22095        GIR_EraseFromParent, /*InsnID*/0,
22096        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22097        // GIR_Coverage, 158,
22098        GIR_Done,
22099      // Label 1265: @55234
22100      GIM_Try, /*On fail goto*//*Label 1266*/ 55253, // Rule ID 154 //
22101        GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
22102        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
22103        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
22104        // (fsub:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)  =>  (FSUB_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
22105        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSUB_S,
22106        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22107        // GIR_Coverage, 154,
22108        GIR_Done,
22109      // Label 1266: @55253
22110      GIM_Try, /*On fail goto*//*Label 1267*/ 55272, // Rule ID 1121 //
22111        GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat,
22112        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
22113        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
22114        // (fsub:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)  =>  (FSUB_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
22115        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSUB_S_MM,
22116        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22117        // GIR_Coverage, 1121,
22118        GIR_Done,
22119      // Label 1267: @55272
22120      GIM_Try, /*On fail goto*//*Label 1268*/ 55304, // Rule ID 1177 //
22121        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
22122        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
22123        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
22124        // (fsub:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)  =>  (FSUB_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs)
22125        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSUB_S_MMR6,
22126        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
22127        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ft
22128        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fs
22129        GIR_EraseFromParent, /*InsnID*/0,
22130        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22131        // GIR_Coverage, 1177,
22132        GIR_Done,
22133      // Label 1268: @55304
22134      GIM_Reject,
22135    // Label 1264: @55305
22136    GIM_Reject,
22137    // Label 1260: @55306
22138    GIM_Try, /*On fail goto*//*Label 1269*/ 55531,
22139      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
22140      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
22141      GIM_Try, /*On fail goto*//*Label 1270*/ 55377, // Rule ID 160 //
22142        GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
22143        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
22144        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22145        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
22146        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
22147        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
22148        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
22149        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
22150        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
22151        GIM_CheckIsSafeToFold, /*InsnID*/1,
22152        // (fsub:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr)  =>  (MSUB_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
22153        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUB_D32,
22154        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
22155        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fr
22156        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
22157        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
22158        GIR_EraseFromParent, /*InsnID*/0,
22159        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22160        // GIR_Coverage, 160,
22161        GIR_Done,
22162      // Label 1270: @55377
22163      GIM_Try, /*On fail goto*//*Label 1271*/ 55438, // Rule ID 162 //
22164        GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6,
22165        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
22166        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22167        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
22168        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
22169        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
22170        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
22171        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
22172        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
22173        GIM_CheckIsSafeToFold, /*InsnID*/1,
22174        // (fsub:{ *:[f64] } (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr)  =>  (MSUB_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
22175        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUB_D64,
22176        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
22177        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fr
22178        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
22179        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
22180        GIR_EraseFromParent, /*InsnID*/0,
22181        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22182        // GIR_Coverage, 162,
22183        GIR_Done,
22184      // Label 1271: @55438
22185      GIM_Try, /*On fail goto*//*Label 1272*/ 55461, // Rule ID 155 //
22186        GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips,
22187        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
22188        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
22189        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
22190        // (fsub:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)  =>  (FSUB_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
22191        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSUB_D32,
22192        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22193        // GIR_Coverage, 155,
22194        GIR_Done,
22195      // Label 1272: @55461
22196      GIM_Try, /*On fail goto*//*Label 1273*/ 55484, // Rule ID 156 //
22197        GIM_CheckFeatures, GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips,
22198        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
22199        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
22200        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
22201        // (fsub:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)  =>  (FSUB_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
22202        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSUB_D64,
22203        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22204        // GIR_Coverage, 156,
22205        GIR_Done,
22206      // Label 1273: @55484
22207      GIM_Try, /*On fail goto*//*Label 1274*/ 55507, // Rule ID 1128 //
22208        GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit,
22209        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
22210        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
22211        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
22212        // (fsub:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)  =>  (FSUB_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
22213        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSUB_D32_MM,
22214        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22215        // GIR_Coverage, 1128,
22216        GIR_Done,
22217      // Label 1274: @55507
22218      GIM_Try, /*On fail goto*//*Label 1275*/ 55530, // Rule ID 1129 //
22219        GIM_CheckFeatures, GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat,
22220        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
22221        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
22222        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
22223        // (fsub:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)  =>  (FSUB_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
22224        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSUB_D64_MM,
22225        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22226        // GIR_Coverage, 1129,
22227        GIR_Done,
22228      // Label 1275: @55530
22229      GIM_Reject,
22230    // Label 1269: @55531
22231    GIM_Reject,
22232    // Label 1261: @55532
22233    GIM_Try, /*On fail goto*//*Label 1276*/ 55628,
22234      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
22235      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
22236      GIM_Try, /*On fail goto*//*Label 1277*/ 55604, // Rule ID 1947 //
22237        GIM_CheckFeatures, GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc,
22238        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
22239        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
22240        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
22241        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
22242        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
22243        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
22244        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
22245        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
22246        GIM_CheckIsSafeToFold, /*InsnID*/1,
22247        // (fsub:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt))  =>  (FMSUB_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
22248        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMSUB_D,
22249        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd
22250        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd
22251        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
22252        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
22253        GIR_EraseFromParent, /*InsnID*/0,
22254        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22255        // GIR_Coverage, 1947,
22256        GIR_Done,
22257      // Label 1277: @55604
22258      GIM_Try, /*On fail goto*//*Label 1278*/ 55627, // Rule ID 747 //
22259        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
22260        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
22261        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
22262        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
22263        // (fsub:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FSUB_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
22264        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSUB_D,
22265        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22266        // GIR_Coverage, 747,
22267        GIR_Done,
22268      // Label 1278: @55627
22269      GIM_Reject,
22270    // Label 1276: @55628
22271    GIM_Reject,
22272    // Label 1262: @55629
22273    GIM_Try, /*On fail goto*//*Label 1279*/ 55725,
22274      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
22275      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
22276      GIM_Try, /*On fail goto*//*Label 1280*/ 55701, // Rule ID 1946 //
22277        GIM_CheckFeatures, GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc,
22278        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
22279        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
22280        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
22281        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
22282        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
22283        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
22284        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
22285        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
22286        GIM_CheckIsSafeToFold, /*InsnID*/1,
22287        // (fsub:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt))  =>  (FMSUB_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
22288        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMSUB_W,
22289        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd
22290        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd
22291        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
22292        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
22293        GIR_EraseFromParent, /*InsnID*/0,
22294        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22295        // GIR_Coverage, 1946,
22296        GIR_Done,
22297      // Label 1280: @55701
22298      GIM_Try, /*On fail goto*//*Label 1281*/ 55724, // Rule ID 746 //
22299        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
22300        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
22301        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
22302        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
22303        // (fsub:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FSUB_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
22304        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSUB_W,
22305        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22306        // GIR_Coverage, 746,
22307        GIR_Done,
22308      // Label 1281: @55724
22309      GIM_Reject,
22310    // Label 1279: @55725
22311    GIM_Reject,
22312    // Label 1263: @55726
22313    GIM_Reject,
22314    // Label 34: @55727
22315    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 7, /*)*//*default:*//*Label 1286*/ 56163,
22316    /*GILLT_s32*//*Label 1282*/ 55739,
22317    /*GILLT_s64*//*Label 1283*/ 55809, 0,
22318    /*GILLT_v2s64*//*Label 1284*/ 55913, 0,
22319    /*GILLT_v4s32*//*Label 1285*/ 56038,
22320    // Label 1282: @55739
22321    GIM_Try, /*On fail goto*//*Label 1287*/ 55808,
22322      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
22323      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
22324      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
22325      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
22326      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
22327      GIM_Try, /*On fail goto*//*Label 1288*/ 55772, // Rule ID 151 //
22328        GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
22329        // (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)  =>  (FMUL_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
22330        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMUL_S,
22331        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22332        // GIR_Coverage, 151,
22333        GIR_Done,
22334      // Label 1288: @55772
22335      GIM_Try, /*On fail goto*//*Label 1289*/ 55783, // Rule ID 1120 //
22336        GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat,
22337        // (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)  =>  (FMUL_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
22338        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMUL_S_MM,
22339        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22340        // GIR_Coverage, 1120,
22341        GIR_Done,
22342      // Label 1289: @55783
22343      GIM_Try, /*On fail goto*//*Label 1290*/ 55807, // Rule ID 1178 //
22344        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
22345        // (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)  =>  (FMUL_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs)
22346        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMUL_S_MMR6,
22347        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
22348        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ft
22349        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fs
22350        GIR_EraseFromParent, /*InsnID*/0,
22351        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22352        // GIR_Coverage, 1178,
22353        GIR_Done,
22354      // Label 1290: @55807
22355      GIM_Reject,
22356    // Label 1287: @55808
22357    GIM_Reject,
22358    // Label 1283: @55809
22359    GIM_Try, /*On fail goto*//*Label 1291*/ 55912,
22360      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
22361      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
22362      GIM_Try, /*On fail goto*//*Label 1292*/ 55842, // Rule ID 152 //
22363        GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips,
22364        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
22365        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
22366        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
22367        // (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)  =>  (FMUL_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
22368        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMUL_D32,
22369        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22370        // GIR_Coverage, 152,
22371        GIR_Done,
22372      // Label 1292: @55842
22373      GIM_Try, /*On fail goto*//*Label 1293*/ 55865, // Rule ID 153 //
22374        GIM_CheckFeatures, GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips,
22375        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
22376        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
22377        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
22378        // (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)  =>  (FMUL_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
22379        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMUL_D64,
22380        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22381        // GIR_Coverage, 153,
22382        GIR_Done,
22383      // Label 1293: @55865
22384      GIM_Try, /*On fail goto*//*Label 1294*/ 55888, // Rule ID 1126 //
22385        GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit,
22386        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
22387        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
22388        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
22389        // (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)  =>  (FMUL_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
22390        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMUL_D32_MM,
22391        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22392        // GIR_Coverage, 1126,
22393        GIR_Done,
22394      // Label 1294: @55888
22395      GIM_Try, /*On fail goto*//*Label 1295*/ 55911, // Rule ID 1127 //
22396        GIM_CheckFeatures, GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat,
22397        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
22398        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
22399        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
22400        // (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)  =>  (FMUL_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
22401        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMUL_D64_MM,
22402        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22403        // GIR_Coverage, 1127,
22404        GIR_Done,
22405      // Label 1295: @55911
22406      GIM_Reject,
22407    // Label 1291: @55912
22408    GIM_Reject,
22409    // Label 1284: @55913
22410    GIM_Try, /*On fail goto*//*Label 1296*/ 56037,
22411      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
22412      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
22413      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
22414      GIM_Try, /*On fail goto*//*Label 1297*/ 55972, // Rule ID 2347 //
22415        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
22416        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22417        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FEXP2,
22418        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
22419        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
22420        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
22421        GIM_CheckIsSafeToFold, /*InsnID*/1,
22422        // (fmul:{ *:[v2f64] } (fexp2:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wt), MSA128DOpnd:{ *:[v2f64] }:$ws)  =>  (FEXP2_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
22423        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXP2_D,
22424        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
22425        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
22426        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
22427        GIR_EraseFromParent, /*InsnID*/0,
22428        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22429        // GIR_Coverage, 2347,
22430        GIR_Done,
22431      // Label 1297: @55972
22432      GIM_Try, /*On fail goto*//*Label 1298*/ 56017, // Rule ID 689 //
22433        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
22434        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
22435        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
22436        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FEXP2,
22437        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
22438        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
22439        GIM_CheckIsSafeToFold, /*InsnID*/1,
22440        // (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, (fexp2:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wt))  =>  (FEXP2_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
22441        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXP2_D,
22442        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
22443        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws
22444        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
22445        GIR_EraseFromParent, /*InsnID*/0,
22446        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22447        // GIR_Coverage, 689,
22448        GIR_Done,
22449      // Label 1298: @56017
22450      GIM_Try, /*On fail goto*//*Label 1299*/ 56036, // Rule ID 725 //
22451        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
22452        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
22453        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
22454        // (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FMUL_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
22455        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMUL_D,
22456        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22457        // GIR_Coverage, 725,
22458        GIR_Done,
22459      // Label 1299: @56036
22460      GIM_Reject,
22461    // Label 1296: @56037
22462    GIM_Reject,
22463    // Label 1285: @56038
22464    GIM_Try, /*On fail goto*//*Label 1300*/ 56162,
22465      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
22466      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
22467      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
22468      GIM_Try, /*On fail goto*//*Label 1301*/ 56097, // Rule ID 2346 //
22469        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
22470        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22471        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FEXP2,
22472        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
22473        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
22474        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
22475        GIM_CheckIsSafeToFold, /*InsnID*/1,
22476        // (fmul:{ *:[v4f32] } (fexp2:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wt), MSA128WOpnd:{ *:[v4f32] }:$ws)  =>  (FEXP2_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
22477        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXP2_W,
22478        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
22479        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
22480        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
22481        GIR_EraseFromParent, /*InsnID*/0,
22482        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22483        // GIR_Coverage, 2346,
22484        GIR_Done,
22485      // Label 1301: @56097
22486      GIM_Try, /*On fail goto*//*Label 1302*/ 56142, // Rule ID 688 //
22487        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
22488        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
22489        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
22490        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FEXP2,
22491        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
22492        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
22493        GIM_CheckIsSafeToFold, /*InsnID*/1,
22494        // (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, (fexp2:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wt))  =>  (FEXP2_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
22495        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXP2_W,
22496        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
22497        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws
22498        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
22499        GIR_EraseFromParent, /*InsnID*/0,
22500        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22501        // GIR_Coverage, 688,
22502        GIR_Done,
22503      // Label 1302: @56142
22504      GIM_Try, /*On fail goto*//*Label 1303*/ 56161, // Rule ID 724 //
22505        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
22506        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
22507        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
22508        // (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FMUL_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
22509        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMUL_W,
22510        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22511        // GIR_Coverage, 724,
22512        GIR_Done,
22513      // Label 1303: @56161
22514      GIM_Reject,
22515    // Label 1300: @56162
22516    GIM_Reject,
22517    // Label 1286: @56163
22518    GIM_Reject,
22519    // Label 35: @56164
22520    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 7, /*)*//*default:*//*Label 1306*/ 56253,
22521    /*GILLT_v2s64*//*Label 1304*/ 56173, 0,
22522    /*GILLT_v4s32*//*Label 1305*/ 56213,
22523    // Label 1304: @56173
22524    GIM_Try, /*On fail goto*//*Label 1307*/ 56212, // Rule ID 713 //
22525      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
22526      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
22527      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
22528      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
22529      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
22530      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
22531      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
22532      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
22533      // (fma:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd_in, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FMADD_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd_in, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
22534      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMADD_D,
22535      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22536      // GIR_Coverage, 713,
22537      GIR_Done,
22538    // Label 1307: @56212
22539    GIM_Reject,
22540    // Label 1305: @56213
22541    GIM_Try, /*On fail goto*//*Label 1308*/ 56252, // Rule ID 712 //
22542      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
22543      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
22544      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
22545      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
22546      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
22547      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
22548      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
22549      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
22550      // (fma:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd_in, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FMADD_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd_in, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
22551      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMADD_W,
22552      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22553      // GIR_Coverage, 712,
22554      GIR_Done,
22555    // Label 1308: @56252
22556    GIM_Reject,
22557    // Label 1306: @56253
22558    GIM_Reject,
22559    // Label 36: @56254
22560    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 7, /*)*//*default:*//*Label 1313*/ 56504,
22561    /*GILLT_s32*//*Label 1309*/ 56266,
22562    /*GILLT_s64*//*Label 1310*/ 56336, 0,
22563    /*GILLT_v2s64*//*Label 1311*/ 56440, 0,
22564    /*GILLT_v4s32*//*Label 1312*/ 56472,
22565    // Label 1309: @56266
22566    GIM_Try, /*On fail goto*//*Label 1314*/ 56335,
22567      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
22568      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
22569      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
22570      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
22571      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
22572      GIM_Try, /*On fail goto*//*Label 1315*/ 56299, // Rule ID 148 //
22573        GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
22574        // (fdiv:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)  =>  (FDIV_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
22575        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FDIV_S,
22576        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22577        // GIR_Coverage, 148,
22578        GIR_Done,
22579      // Label 1315: @56299
22580      GIM_Try, /*On fail goto*//*Label 1316*/ 56310, // Rule ID 1119 //
22581        GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat,
22582        // (fdiv:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)  =>  (FDIV_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
22583        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FDIV_S_MM,
22584        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22585        // GIR_Coverage, 1119,
22586        GIR_Done,
22587      // Label 1316: @56310
22588      GIM_Try, /*On fail goto*//*Label 1317*/ 56334, // Rule ID 1179 //
22589        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
22590        // (fdiv:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)  =>  (FDIV_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs)
22591        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FDIV_S_MMR6,
22592        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
22593        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ft
22594        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fs
22595        GIR_EraseFromParent, /*InsnID*/0,
22596        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22597        // GIR_Coverage, 1179,
22598        GIR_Done,
22599      // Label 1317: @56334
22600      GIM_Reject,
22601    // Label 1314: @56335
22602    GIM_Reject,
22603    // Label 1310: @56336
22604    GIM_Try, /*On fail goto*//*Label 1318*/ 56439,
22605      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
22606      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
22607      GIM_Try, /*On fail goto*//*Label 1319*/ 56369, // Rule ID 149 //
22608        GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips,
22609        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
22610        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
22611        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
22612        // (fdiv:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)  =>  (FDIV_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
22613        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FDIV_D32,
22614        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22615        // GIR_Coverage, 149,
22616        GIR_Done,
22617      // Label 1319: @56369
22618      GIM_Try, /*On fail goto*//*Label 1320*/ 56392, // Rule ID 150 //
22619        GIM_CheckFeatures, GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips,
22620        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
22621        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
22622        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
22623        // (fdiv:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)  =>  (FDIV_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
22624        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FDIV_D64,
22625        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22626        // GIR_Coverage, 150,
22627        GIR_Done,
22628      // Label 1320: @56392
22629      GIM_Try, /*On fail goto*//*Label 1321*/ 56415, // Rule ID 1124 //
22630        GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit,
22631        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
22632        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
22633        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
22634        // (fdiv:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)  =>  (FDIV_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
22635        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FDIV_D32_MM,
22636        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22637        // GIR_Coverage, 1124,
22638        GIR_Done,
22639      // Label 1321: @56415
22640      GIM_Try, /*On fail goto*//*Label 1322*/ 56438, // Rule ID 1125 //
22641        GIM_CheckFeatures, GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat,
22642        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
22643        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
22644        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
22645        // (fdiv:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)  =>  (FDIV_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
22646        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FDIV_D64_MM,
22647        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22648        // GIR_Coverage, 1125,
22649        GIR_Done,
22650      // Label 1322: @56438
22651      GIM_Reject,
22652    // Label 1318: @56439
22653    GIM_Reject,
22654    // Label 1311: @56440
22655    GIM_Try, /*On fail goto*//*Label 1323*/ 56471, // Rule ID 685 //
22656      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
22657      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
22658      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
22659      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
22660      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
22661      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
22662      // (fdiv:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FDIV_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
22663      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FDIV_D,
22664      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22665      // GIR_Coverage, 685,
22666      GIR_Done,
22667    // Label 1323: @56471
22668    GIM_Reject,
22669    // Label 1312: @56472
22670    GIM_Try, /*On fail goto*//*Label 1324*/ 56503, // Rule ID 684 //
22671      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
22672      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
22673      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
22674      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
22675      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
22676      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
22677      // (fdiv:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FDIV_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
22678      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FDIV_W,
22679      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22680      // GIR_Coverage, 684,
22681      GIR_Done,
22682    // Label 1324: @56503
22683    GIM_Reject,
22684    // Label 1313: @56504
22685    GIM_Reject,
22686    // Label 37: @56505
22687    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 7, /*)*//*default:*//*Label 1327*/ 56562,
22688    /*GILLT_v2s64*//*Label 1325*/ 56514, 0,
22689    /*GILLT_v4s32*//*Label 1326*/ 56538,
22690    // Label 1325: @56514
22691    GIM_Try, /*On fail goto*//*Label 1328*/ 56537, // Rule ID 691 //
22692      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
22693      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
22694      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
22695      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
22696      // (fexp2:{ *:[v2f64] } MSA128D:{ *:[v2f64] }:$ws)  =>  (FEXP2_D_1_PSEUDO:{ *:[v2f64] } MSA128D:{ *:[v2f64] }:$ws)
22697      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FEXP2_D_1_PSEUDO,
22698      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22699      // GIR_Coverage, 691,
22700      GIR_Done,
22701    // Label 1328: @56537
22702    GIM_Reject,
22703    // Label 1326: @56538
22704    GIM_Try, /*On fail goto*//*Label 1329*/ 56561, // Rule ID 690 //
22705      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
22706      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
22707      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
22708      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
22709      // (fexp2:{ *:[v4f32] } MSA128W:{ *:[v4f32] }:$ws)  =>  (FEXP2_W_1_PSEUDO:{ *:[v4f32] } MSA128W:{ *:[v4f32] }:$ws)
22710      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FEXP2_W_1_PSEUDO,
22711      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22712      // GIR_Coverage, 690,
22713      GIR_Done,
22714    // Label 1329: @56561
22715    GIM_Reject,
22716    // Label 1327: @56562
22717    GIM_Reject,
22718    // Label 38: @56563
22719    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 7, /*)*//*default:*//*Label 1332*/ 56620,
22720    /*GILLT_v2s64*//*Label 1330*/ 56572, 0,
22721    /*GILLT_v4s32*//*Label 1331*/ 56596,
22722    // Label 1330: @56572
22723    GIM_Try, /*On fail goto*//*Label 1333*/ 56595, // Rule ID 711 //
22724      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
22725      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
22726      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
22727      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
22728      // (flog2:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)  =>  (FLOG2_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
22729      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FLOG2_D,
22730      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22731      // GIR_Coverage, 711,
22732      GIR_Done,
22733    // Label 1333: @56595
22734    GIM_Reject,
22735    // Label 1331: @56596
22736    GIM_Try, /*On fail goto*//*Label 1334*/ 56619, // Rule ID 710 //
22737      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
22738      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
22739      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
22740      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
22741      // (flog2:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)  =>  (FLOG2_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
22742      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FLOG2_W,
22743      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22744      // GIR_Coverage, 710,
22745      GIR_Done,
22746    // Label 1334: @56619
22747    GIM_Reject,
22748    // Label 1332: @56620
22749    GIM_Reject,
22750    // Label 39: @56621
22751    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1337*/ 57916,
22752    /*GILLT_s32*//*Label 1335*/ 56629,
22753    /*GILLT_s64*//*Label 1336*/ 57130,
22754    // Label 1335: @56629
22755    GIM_Try, /*On fail goto*//*Label 1338*/ 57129,
22756      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
22757      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
22758      GIM_Try, /*On fail goto*//*Label 1339*/ 56713, // Rule ID 1446 //
22759        GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6,
22760        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22761        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD,
22762        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
22763        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22764        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
22765        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL,
22766        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
22767        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
22768        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
22769        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
22770        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
22771        GIM_CheckIsSafeToFold, /*InsnID*/1,
22772        GIM_CheckIsSafeToFold, /*InsnID*/2,
22773        // (fneg:{ *:[f32] } (fadd:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr))  =>  (NMADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
22774        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_S,
22775        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
22776        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
22777        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
22778        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
22779        GIR_EraseFromParent, /*InsnID*/0,
22780        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22781        // GIR_Coverage, 1446,
22782        GIR_Done,
22783      // Label 1339: @56713
22784      GIM_Try, /*On fail goto*//*Label 1340*/ 56787, // Rule ID 2202 //
22785        GIM_CheckFeatures, GIFBS_HasMadd4_InMicroMips_InMicroMips_NoNaNsFPMath_NotMips32r6_NotMips32r6,
22786        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22787        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD,
22788        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
22789        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22790        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
22791        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL,
22792        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
22793        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
22794        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
22795        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
22796        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
22797        GIM_CheckIsSafeToFold, /*InsnID*/1,
22798        GIM_CheckIsSafeToFold, /*InsnID*/2,
22799        // (fneg:{ *:[f32] } (fadd:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr))  =>  (NMADD_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
22800        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_S_MM,
22801        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
22802        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
22803        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
22804        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
22805        GIR_EraseFromParent, /*InsnID*/0,
22806        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22807        // GIR_Coverage, 2202,
22808        GIR_Done,
22809      // Label 1340: @56787
22810      GIM_Try, /*On fail goto*//*Label 1341*/ 56861, // Rule ID 2382 //
22811        GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6,
22812        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22813        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD,
22814        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
22815        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22816        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
22817        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
22818        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL,
22819        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
22820        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
22821        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
22822        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
22823        GIM_CheckIsSafeToFold, /*InsnID*/1,
22824        GIM_CheckIsSafeToFold, /*InsnID*/2,
22825        // (fneg:{ *:[f32] } (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)))  =>  (NMADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
22826        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_S,
22827        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
22828        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fr
22829        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
22830        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
22831        GIR_EraseFromParent, /*InsnID*/0,
22832        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22833        // GIR_Coverage, 2382,
22834        GIR_Done,
22835      // Label 1341: @56861
22836      GIM_Try, /*On fail goto*//*Label 1342*/ 56935, // Rule ID 2468 //
22837        GIM_CheckFeatures, GIFBS_HasMadd4_InMicroMips_InMicroMips_NoNaNsFPMath_NotMips32r6_NotMips32r6,
22838        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22839        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD,
22840        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
22841        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22842        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
22843        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
22844        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL,
22845        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
22846        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
22847        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
22848        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
22849        GIM_CheckIsSafeToFold, /*InsnID*/1,
22850        GIM_CheckIsSafeToFold, /*InsnID*/2,
22851        // (fneg:{ *:[f32] } (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)))  =>  (NMADD_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
22852        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_S_MM,
22853        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
22854        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fr
22855        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
22856        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
22857        GIR_EraseFromParent, /*InsnID*/0,
22858        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22859        // GIR_Coverage, 2468,
22860        GIR_Done,
22861      // Label 1342: @56935
22862      GIM_Try, /*On fail goto*//*Label 1343*/ 57009, // Rule ID 1447 //
22863        GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6,
22864        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22865        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB,
22866        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
22867        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22868        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
22869        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL,
22870        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
22871        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
22872        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
22873        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
22874        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
22875        GIM_CheckIsSafeToFold, /*InsnID*/1,
22876        GIM_CheckIsSafeToFold, /*InsnID*/2,
22877        // (fneg:{ *:[f32] } (fsub:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr))  =>  (NMSUB_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
22878        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMSUB_S,
22879        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
22880        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
22881        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
22882        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
22883        GIR_EraseFromParent, /*InsnID*/0,
22884        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22885        // GIR_Coverage, 1447,
22886        GIR_Done,
22887      // Label 1343: @57009
22888      GIM_Try, /*On fail goto*//*Label 1344*/ 57083, // Rule ID 2203 //
22889        GIM_CheckFeatures, GIFBS_HasMadd4_InMicroMips_InMicroMips_NoNaNsFPMath_NotMips32r6_NotMips32r6,
22890        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22891        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB,
22892        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
22893        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22894        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
22895        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL,
22896        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
22897        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
22898        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
22899        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
22900        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
22901        GIM_CheckIsSafeToFold, /*InsnID*/1,
22902        GIM_CheckIsSafeToFold, /*InsnID*/2,
22903        // (fneg:{ *:[f32] } (fsub:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr))  =>  (NMSUB_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
22904        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMSUB_S_MM,
22905        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
22906        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
22907        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
22908        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
22909        GIR_EraseFromParent, /*InsnID*/0,
22910        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22911        // GIR_Coverage, 2203,
22912        GIR_Done,
22913      // Label 1344: @57083
22914      GIM_Try, /*On fail goto*//*Label 1345*/ 57098, // Rule ID 123 //
22915        GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat,
22916        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
22917        // (fneg:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)  =>  (FNEG_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
22918        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FNEG_S,
22919        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22920        // GIR_Coverage, 123,
22921        GIR_Done,
22922      // Label 1345: @57098
22923      GIM_Try, /*On fail goto*//*Label 1346*/ 57113, // Rule ID 1141 //
22924        GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat,
22925        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
22926        // (fneg:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)  =>  (FNEG_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
22927        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FNEG_S_MM,
22928        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22929        // GIR_Coverage, 1141,
22930        GIR_Done,
22931      // Label 1346: @57113
22932      GIM_Try, /*On fail goto*//*Label 1347*/ 57128, // Rule ID 1180 //
22933        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
22934        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
22935        // (fneg:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)  =>  (FNEG_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
22936        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FNEG_S_MMR6,
22937        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22938        // GIR_Coverage, 1180,
22939        GIR_Done,
22940      // Label 1347: @57128
22941      GIM_Reject,
22942    // Label 1338: @57129
22943    GIM_Reject,
22944    // Label 1336: @57130
22945    GIM_Try, /*On fail goto*//*Label 1348*/ 57915,
22946      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
22947      GIM_Try, /*On fail goto*//*Label 1349*/ 57214, // Rule ID 1448 //
22948        GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
22949        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
22950        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22951        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD,
22952        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
22953        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
22954        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
22955        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL,
22956        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
22957        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
22958        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
22959        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
22960        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
22961        GIM_CheckIsSafeToFold, /*InsnID*/1,
22962        GIM_CheckIsSafeToFold, /*InsnID*/2,
22963        // (fneg:{ *:[f64] } (fadd:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr))  =>  (NMADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
22964        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_D32,
22965        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
22966        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
22967        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
22968        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
22969        GIR_EraseFromParent, /*InsnID*/0,
22970        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22971        // GIR_Coverage, 1448,
22972        GIR_Done,
22973      // Label 1349: @57214
22974      GIM_Try, /*On fail goto*//*Label 1350*/ 57292, // Rule ID 1450 //
22975        GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6,
22976        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
22977        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22978        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD,
22979        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
22980        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
22981        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
22982        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL,
22983        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
22984        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
22985        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
22986        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
22987        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
22988        GIM_CheckIsSafeToFold, /*InsnID*/1,
22989        GIM_CheckIsSafeToFold, /*InsnID*/2,
22990        // (fneg:{ *:[f64] } (fadd:{ *:[f64] } (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr))  =>  (NMADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
22991        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_D64,
22992        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
22993        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
22994        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
22995        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
22996        GIR_EraseFromParent, /*InsnID*/0,
22997        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22998        // GIR_Coverage, 1450,
22999        GIR_Done,
23000      // Label 1350: @57292
23001      GIM_Try, /*On fail goto*//*Label 1351*/ 57370, // Rule ID 2204 //
23002        GIM_CheckFeatures, GIFBS_HasMadd4_InMicroMips_InMicroMips_NoNaNsFPMath_NotFP64bit_NotMips32r6_NotMips32r6,
23003        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
23004        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23005        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD,
23006        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
23007        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
23008        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
23009        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL,
23010        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
23011        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
23012        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
23013        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
23014        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
23015        GIM_CheckIsSafeToFold, /*InsnID*/1,
23016        GIM_CheckIsSafeToFold, /*InsnID*/2,
23017        // (fneg:{ *:[f64] } (fadd:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr))  =>  (NMADD_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
23018        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_D32_MM,
23019        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
23020        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
23021        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
23022        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
23023        GIR_EraseFromParent, /*InsnID*/0,
23024        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23025        // GIR_Coverage, 2204,
23026        GIR_Done,
23027      // Label 1351: @57370
23028      GIM_Try, /*On fail goto*//*Label 1352*/ 57448, // Rule ID 2383 //
23029        GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
23030        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
23031        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23032        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD,
23033        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
23034        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
23035        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
23036        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
23037        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL,
23038        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
23039        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
23040        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
23041        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
23042        GIM_CheckIsSafeToFold, /*InsnID*/1,
23043        GIM_CheckIsSafeToFold, /*InsnID*/2,
23044        // (fneg:{ *:[f64] } (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)))  =>  (NMADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
23045        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_D32,
23046        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
23047        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fr
23048        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
23049        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
23050        GIR_EraseFromParent, /*InsnID*/0,
23051        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23052        // GIR_Coverage, 2383,
23053        GIR_Done,
23054      // Label 1352: @57448
23055      GIM_Try, /*On fail goto*//*Label 1353*/ 57526, // Rule ID 2384 //
23056        GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6,
23057        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
23058        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23059        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD,
23060        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
23061        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
23062        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
23063        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
23064        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL,
23065        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
23066        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
23067        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
23068        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
23069        GIM_CheckIsSafeToFold, /*InsnID*/1,
23070        GIM_CheckIsSafeToFold, /*InsnID*/2,
23071        // (fneg:{ *:[f64] } (fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)))  =>  (NMADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
23072        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_D64,
23073        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
23074        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fr
23075        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
23076        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
23077        GIR_EraseFromParent, /*InsnID*/0,
23078        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23079        // GIR_Coverage, 2384,
23080        GIR_Done,
23081      // Label 1353: @57526
23082      GIM_Try, /*On fail goto*//*Label 1354*/ 57604, // Rule ID 2469 //
23083        GIM_CheckFeatures, GIFBS_HasMadd4_InMicroMips_InMicroMips_NoNaNsFPMath_NotFP64bit_NotMips32r6_NotMips32r6,
23084        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
23085        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23086        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD,
23087        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
23088        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
23089        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
23090        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
23091        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL,
23092        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
23093        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
23094        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
23095        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
23096        GIM_CheckIsSafeToFold, /*InsnID*/1,
23097        GIM_CheckIsSafeToFold, /*InsnID*/2,
23098        // (fneg:{ *:[f64] } (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)))  =>  (NMADD_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
23099        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_D32_MM,
23100        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
23101        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fr
23102        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
23103        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
23104        GIR_EraseFromParent, /*InsnID*/0,
23105        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23106        // GIR_Coverage, 2469,
23107        GIR_Done,
23108      // Label 1354: @57604
23109      GIM_Try, /*On fail goto*//*Label 1355*/ 57682, // Rule ID 1449 //
23110        GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
23111        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
23112        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23113        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB,
23114        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
23115        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
23116        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
23117        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL,
23118        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
23119        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
23120        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
23121        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
23122        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
23123        GIM_CheckIsSafeToFold, /*InsnID*/1,
23124        GIM_CheckIsSafeToFold, /*InsnID*/2,
23125        // (fneg:{ *:[f64] } (fsub:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr))  =>  (NMSUB_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
23126        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMSUB_D32,
23127        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
23128        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
23129        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
23130        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
23131        GIR_EraseFromParent, /*InsnID*/0,
23132        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23133        // GIR_Coverage, 1449,
23134        GIR_Done,
23135      // Label 1355: @57682
23136      GIM_Try, /*On fail goto*//*Label 1356*/ 57760, // Rule ID 1451 //
23137        GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6,
23138        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
23139        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23140        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB,
23141        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
23142        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
23143        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
23144        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL,
23145        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
23146        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
23147        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
23148        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
23149        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
23150        GIM_CheckIsSafeToFold, /*InsnID*/1,
23151        GIM_CheckIsSafeToFold, /*InsnID*/2,
23152        // (fneg:{ *:[f64] } (fsub:{ *:[f64] } (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr))  =>  (NMSUB_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
23153        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMSUB_D64,
23154        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
23155        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
23156        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
23157        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
23158        GIR_EraseFromParent, /*InsnID*/0,
23159        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23160        // GIR_Coverage, 1451,
23161        GIR_Done,
23162      // Label 1356: @57760
23163      GIM_Try, /*On fail goto*//*Label 1357*/ 57838, // Rule ID 2205 //
23164        GIM_CheckFeatures, GIFBS_HasMadd4_InMicroMips_InMicroMips_NoNaNsFPMath_NotFP64bit_NotMips32r6_NotMips32r6,
23165        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
23166        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23167        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB,
23168        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
23169        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
23170        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
23171        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL,
23172        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
23173        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
23174        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
23175        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
23176        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
23177        GIM_CheckIsSafeToFold, /*InsnID*/1,
23178        GIM_CheckIsSafeToFold, /*InsnID*/2,
23179        // (fneg:{ *:[f64] } (fsub:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr))  =>  (NMSUB_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
23180        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMSUB_D32_MM,
23181        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
23182        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
23183        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
23184        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
23185        GIR_EraseFromParent, /*InsnID*/0,
23186        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23187        // GIR_Coverage, 2205,
23188        GIR_Done,
23189      // Label 1357: @57838
23190      GIM_Try, /*On fail goto*//*Label 1358*/ 57857, // Rule ID 124 //
23191        GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips,
23192        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
23193        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
23194        // (fneg:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)  =>  (FNEG_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)
23195        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FNEG_D32,
23196        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23197        // GIR_Coverage, 124,
23198        GIR_Done,
23199      // Label 1358: @57857
23200      GIM_Try, /*On fail goto*//*Label 1359*/ 57876, // Rule ID 125 //
23201        GIM_CheckFeatures, GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips,
23202        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
23203        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
23204        // (fneg:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)  =>  (FNEG_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)
23205        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FNEG_D64,
23206        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23207        // GIR_Coverage, 125,
23208        GIR_Done,
23209      // Label 1359: @57876
23210      GIM_Try, /*On fail goto*//*Label 1360*/ 57895, // Rule ID 1142 //
23211        GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit,
23212        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
23213        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
23214        // (fneg:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)  =>  (FNEG_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)
23215        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FNEG_D32_MM,
23216        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23217        // GIR_Coverage, 1142,
23218        GIR_Done,
23219      // Label 1360: @57895
23220      GIM_Try, /*On fail goto*//*Label 1361*/ 57914, // Rule ID 1143 //
23221        GIM_CheckFeatures, GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat,
23222        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
23223        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
23224        // (fneg:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)  =>  (FNEG_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)
23225        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FNEG_D64_MM,
23226        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23227        // GIR_Coverage, 1143,
23228        GIR_Done,
23229      // Label 1361: @57914
23230      GIM_Reject,
23231    // Label 1348: @57915
23232    GIM_Reject,
23233    // Label 1337: @57916
23234    GIM_Reject,
23235    // Label 40: @57917
23236    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1364*/ 58065,
23237    /*GILLT_s32*//*Label 1362*/ 57925,
23238    /*GILLT_s64*//*Label 1363*/ 57949,
23239    // Label 1362: @57925
23240    GIM_Try, /*On fail goto*//*Label 1365*/ 57948, // Rule ID 1044 //
23241      GIM_CheckFeatures, GIFBS_HasMSA,
23242      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
23243      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
23244      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128F16RegClassID,
23245      // (fpextend:{ *:[f32] } MSA128F16:{ *:[f16] }:$ws)  =>  (MSA_FP_EXTEND_W_PSEUDO:{ *:[f32] } MSA128F16:{ *:[f16] }:$ws)
23246      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MSA_FP_EXTEND_W_PSEUDO,
23247      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23248      // GIR_Coverage, 1044,
23249      GIR_Done,
23250    // Label 1365: @57948
23251    GIM_Reject,
23252    // Label 1363: @57949
23253    GIM_Try, /*On fail goto*//*Label 1366*/ 57972, // Rule ID 1046 //
23254      GIM_CheckFeatures, GIFBS_HasMSA,
23255      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
23256      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
23257      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128F16RegClassID,
23258      // (fpextend:{ *:[f64] } MSA128F16:{ *:[f16] }:$ws)  =>  (MSA_FP_EXTEND_D_PSEUDO:{ *:[f64] } MSA128F16:{ *:[f16] }:$ws)
23259      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MSA_FP_EXTEND_D_PSEUDO,
23260      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23261      // GIR_Coverage, 1046,
23262      GIR_Done,
23263    // Label 1366: @57972
23264    GIM_Try, /*On fail goto*//*Label 1367*/ 57995, // Rule ID 1435 //
23265      GIM_CheckFeatures, GIFBS_HasStdEnc_NotFP64bit_NotInMicroMips,
23266      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
23267      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
23268      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
23269      // (fpextend:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src)  =>  (CVT_D32_S:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src)
23270      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CVT_D32_S,
23271      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23272      // GIR_Coverage, 1435,
23273      GIR_Done,
23274    // Label 1367: @57995
23275    GIM_Try, /*On fail goto*//*Label 1368*/ 58018, // Rule ID 1445 //
23276      GIM_CheckFeatures, GIFBS_HasStdEnc_IsFP64bit_NotInMicroMips,
23277      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
23278      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
23279      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
23280      // (fpextend:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src)  =>  (CVT_D64_S:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src)
23281      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CVT_D64_S,
23282      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23283      // GIR_Coverage, 1445,
23284      GIR_Done,
23285    // Label 1368: @58018
23286    GIM_Try, /*On fail goto*//*Label 1369*/ 58041, // Rule ID 2216 //
23287      GIM_CheckFeatures, GIFBS_InMicroMips_IsFP64bit,
23288      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
23289      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
23290      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
23291      // (fpextend:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src)  =>  (CVT_D64_S_MM:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src)
23292      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CVT_D64_S_MM,
23293      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23294      // GIR_Coverage, 2216,
23295      GIR_Done,
23296    // Label 1369: @58041
23297    GIM_Try, /*On fail goto*//*Label 1370*/ 58064, // Rule ID 2218 //
23298      GIM_CheckFeatures, GIFBS_InMicroMips_NotFP64bit,
23299      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
23300      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
23301      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
23302      // (fpextend:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src)  =>  (CVT_D32_S_MM:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src)
23303      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CVT_D32_S_MM,
23304      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23305      // GIR_Coverage, 2218,
23306      GIR_Done,
23307    // Label 1370: @58064
23308    GIM_Reject,
23309    // Label 1364: @58065
23310    GIM_Reject,
23311    // Label 41: @58066
23312    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 1373*/ 58193,
23313    /*GILLT_s16*//*Label 1371*/ 58074,
23314    /*GILLT_s32*//*Label 1372*/ 58121,
23315    // Label 1371: @58074
23316    GIM_Try, /*On fail goto*//*Label 1374*/ 58097, // Rule ID 1045 //
23317      GIM_CheckFeatures, GIFBS_HasMSA,
23318      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
23319      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128F16RegClassID,
23320      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
23321      // (fpround:{ *:[f16] } FGR32Opnd:{ *:[f32] }:$fs)  =>  (MSA_FP_ROUND_W_PSEUDO:{ *:[f16] } FGR32Opnd:{ *:[f32] }:$fs)
23322      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MSA_FP_ROUND_W_PSEUDO,
23323      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23324      // GIR_Coverage, 1045,
23325      GIR_Done,
23326    // Label 1374: @58097
23327    GIM_Try, /*On fail goto*//*Label 1375*/ 58120, // Rule ID 1047 //
23328      GIM_CheckFeatures, GIFBS_HasMSA,
23329      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
23330      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128F16RegClassID,
23331      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
23332      // (fpround:{ *:[f16] } FGR64Opnd:{ *:[f64] }:$fs)  =>  (MSA_FP_ROUND_D_PSEUDO:{ *:[f16] } FGR64Opnd:{ *:[f64] }:$fs)
23333      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MSA_FP_ROUND_D_PSEUDO,
23334      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23335      // GIR_Coverage, 1047,
23336      GIR_Done,
23337    // Label 1375: @58120
23338    GIM_Reject,
23339    // Label 1372: @58121
23340    GIM_Try, /*On fail goto*//*Label 1376*/ 58192,
23341      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
23342      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
23343      GIM_Try, /*On fail goto*//*Label 1377*/ 58146, // Rule ID 1434 //
23344        GIM_CheckFeatures, GIFBS_HasStdEnc_NotFP64bit_NotInMicroMips,
23345        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
23346        // (fpround:{ *:[f32] } AFGR64Opnd:{ *:[f64] }:$src)  =>  (CVT_S_D32:{ *:[f32] } AFGR64Opnd:{ *:[f64] }:$src)
23347        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CVT_S_D32,
23348        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23349        // GIR_Coverage, 1434,
23350        GIR_Done,
23351      // Label 1377: @58146
23352      GIM_Try, /*On fail goto*//*Label 1378*/ 58161, // Rule ID 1444 //
23353        GIM_CheckFeatures, GIFBS_HasStdEnc_IsFP64bit_NotInMicroMips,
23354        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
23355        // (fpround:{ *:[f32] } FGR64Opnd:{ *:[f64] }:$src)  =>  (CVT_S_D64:{ *:[f32] } FGR64Opnd:{ *:[f64] }:$src)
23356        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CVT_S_D64,
23357        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23358        // GIR_Coverage, 1444,
23359        GIR_Done,
23360      // Label 1378: @58161
23361      GIM_Try, /*On fail goto*//*Label 1379*/ 58176, // Rule ID 2215 //
23362        GIM_CheckFeatures, GIFBS_InMicroMips_IsFP64bit,
23363        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
23364        // (fpround:{ *:[f32] } FGR64Opnd:{ *:[f64] }:$src)  =>  (CVT_S_D64_MM:{ *:[f32] } FGR64Opnd:{ *:[f64] }:$src)
23365        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CVT_S_D64_MM,
23366        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23367        // GIR_Coverage, 2215,
23368        GIR_Done,
23369      // Label 1379: @58176
23370      GIM_Try, /*On fail goto*//*Label 1380*/ 58191, // Rule ID 2217 //
23371        GIM_CheckFeatures, GIFBS_InMicroMips_NotFP64bit,
23372        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
23373        // (fpround:{ *:[f32] } AFGR64Opnd:{ *:[f64] }:$src)  =>  (CVT_S_D32_MM:{ *:[f32] } AFGR64Opnd:{ *:[f64] }:$src)
23374        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CVT_S_D32_MM,
23375        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23376        // GIR_Coverage, 2217,
23377        GIR_Done,
23378      // Label 1380: @58191
23379      GIM_Reject,
23380    // Label 1376: @58192
23381    GIM_Reject,
23382    // Label 1373: @58193
23383    GIM_Reject,
23384    // Label 42: @58194
23385    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 7, /*)*//*default:*//*Label 1383*/ 58251,
23386    /*GILLT_v2s64*//*Label 1381*/ 58203, 0,
23387    /*GILLT_v4s32*//*Label 1382*/ 58227,
23388    // Label 1381: @58203
23389    GIM_Try, /*On fail goto*//*Label 1384*/ 58226, // Rule ID 765 //
23390      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
23391      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
23392      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
23393      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
23394      // (fp_to_sint:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)  =>  (FTRUNC_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
23395      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FTRUNC_S_D,
23396      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23397      // GIR_Coverage, 765,
23398      GIR_Done,
23399    // Label 1384: @58226
23400    GIM_Reject,
23401    // Label 1382: @58227
23402    GIM_Try, /*On fail goto*//*Label 1385*/ 58250, // Rule ID 764 //
23403      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
23404      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
23405      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
23406      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
23407      // (fp_to_sint:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)  =>  (FTRUNC_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
23408      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FTRUNC_S_W,
23409      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23410      // GIR_Coverage, 764,
23411      GIR_Done,
23412    // Label 1385: @58250
23413    GIM_Reject,
23414    // Label 1383: @58251
23415    GIM_Reject,
23416    // Label 43: @58252
23417    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 7, /*)*//*default:*//*Label 1388*/ 58309,
23418    /*GILLT_v2s64*//*Label 1386*/ 58261, 0,
23419    /*GILLT_v4s32*//*Label 1387*/ 58285,
23420    // Label 1386: @58261
23421    GIM_Try, /*On fail goto*//*Label 1389*/ 58284, // Rule ID 767 //
23422      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
23423      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
23424      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
23425      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
23426      // (fp_to_uint:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)  =>  (FTRUNC_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
23427      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FTRUNC_U_D,
23428      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23429      // GIR_Coverage, 767,
23430      GIR_Done,
23431    // Label 1389: @58284
23432    GIM_Reject,
23433    // Label 1387: @58285
23434    GIM_Try, /*On fail goto*//*Label 1390*/ 58308, // Rule ID 766 //
23435      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
23436      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
23437      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
23438      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
23439      // (fp_to_uint:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)  =>  (FTRUNC_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
23440      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FTRUNC_U_W,
23441      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23442      // GIR_Coverage, 766,
23443      GIR_Done,
23444    // Label 1390: @58308
23445    GIM_Reject,
23446    // Label 1388: @58309
23447    GIM_Reject,
23448    // Label 44: @58310
23449    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 7, /*)*//*default:*//*Label 1395*/ 58517,
23450    /*GILLT_s32*//*Label 1391*/ 58322,
23451    /*GILLT_s64*//*Label 1392*/ 58399, 0,
23452    /*GILLT_v2s64*//*Label 1393*/ 58469, 0,
23453    /*GILLT_v4s32*//*Label 1394*/ 58493,
23454    // Label 1391: @58322
23455    GIM_Try, /*On fail goto*//*Label 1396*/ 58343, // Rule ID 1429 //
23456      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
23457      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
23458      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
23459      // (sint_to_fp:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$src)  =>  (PseudoCVT_S_W:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$src)
23460      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PseudoCVT_S_W,
23461      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23462      // GIR_Coverage, 1429,
23463      GIR_Done,
23464    // Label 1396: @58343
23465    GIM_Try, /*On fail goto*//*Label 1397*/ 58398, // Rule ID 1439 //
23466      GIM_CheckFeatures, GIFBS_IsFP64bit,
23467      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
23468      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
23469      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
23470      // (sint_to_fp:{ *:[f32] } GPR64Opnd:{ *:[i64] }:$src)  =>  (EXTRACT_SUBREG:{ *:[f32] } (PseudoCVT_S_L:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$src), sub_lo:{ *:[i32] })
23471      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
23472      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::PseudoCVT_S_L,
23473      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
23474      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
23475      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23476      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
23477      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
23478      GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, Mips::sub_lo,
23479      GIR_EraseFromParent, /*InsnID*/0,
23480      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::FGR32RegClassID,
23481      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, Mips::FGR64RegClassID,
23482      // GIR_Coverage, 1439,
23483      GIR_Done,
23484    // Label 1397: @58398
23485    GIM_Reject,
23486    // Label 1392: @58399
23487    GIM_Try, /*On fail goto*//*Label 1398*/ 58422, // Rule ID 1432 //
23488      GIM_CheckFeatures, GIFBS_NotFP64bit,
23489      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
23490      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
23491      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
23492      // (sint_to_fp:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$src)  =>  (PseudoCVT_D32_W:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$src)
23493      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PseudoCVT_D32_W,
23494      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23495      // GIR_Coverage, 1432,
23496      GIR_Done,
23497    // Label 1398: @58422
23498    GIM_Try, /*On fail goto*//*Label 1399*/ 58445, // Rule ID 1438 //
23499      GIM_CheckFeatures, GIFBS_IsFP64bit,
23500      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
23501      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
23502      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
23503      // (sint_to_fp:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$src)  =>  (PseudoCVT_D64_W:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$src)
23504      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PseudoCVT_D64_W,
23505      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23506      // GIR_Coverage, 1438,
23507      GIR_Done,
23508    // Label 1399: @58445
23509    GIM_Try, /*On fail goto*//*Label 1400*/ 58468, // Rule ID 1440 //
23510      GIM_CheckFeatures, GIFBS_IsFP64bit,
23511      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
23512      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
23513      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
23514      // (sint_to_fp:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$src)  =>  (PseudoCVT_D64_L:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$src)
23515      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PseudoCVT_D64_L,
23516      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23517      // GIR_Coverage, 1440,
23518      GIR_Done,
23519    // Label 1400: @58468
23520    GIM_Reject,
23521    // Label 1393: @58469
23522    GIM_Try, /*On fail goto*//*Label 1401*/ 58492, // Rule ID 697 //
23523      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
23524      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
23525      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
23526      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
23527      // (sint_to_fp:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$ws)  =>  (FFINT_S_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$ws)
23528      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FFINT_S_D,
23529      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23530      // GIR_Coverage, 697,
23531      GIR_Done,
23532    // Label 1401: @58492
23533    GIM_Reject,
23534    // Label 1394: @58493
23535    GIM_Try, /*On fail goto*//*Label 1402*/ 58516, // Rule ID 696 //
23536      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
23537      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
23538      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
23539      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
23540      // (sint_to_fp:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$ws)  =>  (FFINT_S_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$ws)
23541      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FFINT_S_W,
23542      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23543      // GIR_Coverage, 696,
23544      GIR_Done,
23545    // Label 1402: @58516
23546    GIM_Reject,
23547    // Label 1395: @58517
23548    GIM_Reject,
23549    // Label 45: @58518
23550    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 7, /*)*//*default:*//*Label 1405*/ 58575,
23551    /*GILLT_v2s64*//*Label 1403*/ 58527, 0,
23552    /*GILLT_v4s32*//*Label 1404*/ 58551,
23553    // Label 1403: @58527
23554    GIM_Try, /*On fail goto*//*Label 1406*/ 58550, // Rule ID 699 //
23555      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
23556      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
23557      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
23558      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
23559      // (uint_to_fp:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$ws)  =>  (FFINT_U_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$ws)
23560      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FFINT_U_D,
23561      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23562      // GIR_Coverage, 699,
23563      GIR_Done,
23564    // Label 1406: @58550
23565    GIM_Reject,
23566    // Label 1404: @58551
23567    GIM_Try, /*On fail goto*//*Label 1407*/ 58574, // Rule ID 698 //
23568      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
23569      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
23570      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
23571      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
23572      // (uint_to_fp:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$ws)  =>  (FFINT_U_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$ws)
23573      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FFINT_U_W,
23574      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23575      // GIR_Coverage, 698,
23576      GIR_Done,
23577    // Label 1407: @58574
23578    GIM_Reject,
23579    // Label 1405: @58575
23580    GIM_Reject,
23581    // Label 46: @58576
23582    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 7, /*)*//*default:*//*Label 1412*/ 58758,
23583    /*GILLT_s32*//*Label 1408*/ 58588,
23584    /*GILLT_s64*//*Label 1409*/ 58626, 0,
23585    /*GILLT_v2s64*//*Label 1410*/ 58710, 0,
23586    /*GILLT_v4s32*//*Label 1411*/ 58734,
23587    // Label 1408: @58588
23588    GIM_Try, /*On fail goto*//*Label 1413*/ 58625,
23589      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
23590      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
23591      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
23592      GIM_Try, /*On fail goto*//*Label 1414*/ 58613, // Rule ID 120 //
23593        GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips_UseAbs,
23594        // (fabs:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)  =>  (FABS_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
23595        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FABS_S,
23596        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23597        // GIR_Coverage, 120,
23598        GIR_Done,
23599      // Label 1414: @58613
23600      GIM_Try, /*On fail goto*//*Label 1415*/ 58624, // Rule ID 1140 //
23601        GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat_UseAbs,
23602        // (fabs:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)  =>  (FABS_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
23603        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FABS_S_MM,
23604        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23605        // GIR_Coverage, 1140,
23606        GIR_Done,
23607      // Label 1415: @58624
23608      GIM_Reject,
23609    // Label 1413: @58625
23610    GIM_Reject,
23611    // Label 1409: @58626
23612    GIM_Try, /*On fail goto*//*Label 1416*/ 58709,
23613      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
23614      GIM_Try, /*On fail goto*//*Label 1417*/ 58651, // Rule ID 121 //
23615        GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_UseAbs,
23616        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
23617        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
23618        // (fabs:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)  =>  (FABS_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)
23619        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FABS_D32,
23620        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23621        // GIR_Coverage, 121,
23622        GIR_Done,
23623      // Label 1417: @58651
23624      GIM_Try, /*On fail goto*//*Label 1418*/ 58670, // Rule ID 122 //
23625        GIM_CheckFeatures, GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_UseAbs,
23626        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
23627        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
23628        // (fabs:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)  =>  (FABS_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)
23629        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FABS_D64,
23630        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23631        // GIR_Coverage, 122,
23632        GIR_Done,
23633      // Label 1418: @58670
23634      GIM_Try, /*On fail goto*//*Label 1419*/ 58689, // Rule ID 1138 //
23635        GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit,
23636        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
23637        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
23638        // (fabs:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)  =>  (FABS_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)
23639        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FABS_D32_MM,
23640        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23641        // GIR_Coverage, 1138,
23642        GIR_Done,
23643      // Label 1419: @58689
23644      GIM_Try, /*On fail goto*//*Label 1420*/ 58708, // Rule ID 1139 //
23645        GIM_CheckFeatures, GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat,
23646        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
23647        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
23648        // (fabs:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)  =>  (FABS_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)
23649        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FABS_D64_MM,
23650        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23651        // GIR_Coverage, 1139,
23652        GIR_Done,
23653      // Label 1420: @58708
23654      GIM_Reject,
23655    // Label 1416: @58709
23656    GIM_Reject,
23657    // Label 1410: @58710
23658    GIM_Try, /*On fail goto*//*Label 1421*/ 58733, // Rule ID 1031 //
23659      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
23660      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
23661      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
23662      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
23663      // (fabs:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)  =>  (FABS_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
23664      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FABS_D,
23665      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23666      // GIR_Coverage, 1031,
23667      GIR_Done,
23668    // Label 1421: @58733
23669    GIM_Reject,
23670    // Label 1411: @58734
23671    GIM_Try, /*On fail goto*//*Label 1422*/ 58757, // Rule ID 1030 //
23672      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
23673      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
23674      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
23675      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
23676      // (fabs:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)  =>  (FABS_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
23677      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FABS_W,
23678      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23679      // GIR_Coverage, 1030,
23680      GIR_Done,
23681    // Label 1422: @58757
23682    GIM_Reject,
23683    // Label 1412: @58758
23684    GIM_Reject,
23685    // Label 47: @58759
23686    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 9, /*)*//*default:*//*Label 1427*/ 58898,
23687    /*GILLT_v2s64*//*Label 1423*/ 58770, 0,
23688    /*GILLT_v4s32*//*Label 1424*/ 58802,
23689    /*GILLT_v8s16*//*Label 1425*/ 58834,
23690    /*GILLT_v16s8*//*Label 1426*/ 58866,
23691    // Label 1423: @58770
23692    GIM_Try, /*On fail goto*//*Label 1428*/ 58801, // Rule ID 859 //
23693      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
23694      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
23695      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
23696      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
23697      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
23698      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
23699      // (smin:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (MIN_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
23700      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MIN_S_D,
23701      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23702      // GIR_Coverage, 859,
23703      GIR_Done,
23704    // Label 1428: @58801
23705    GIM_Reject,
23706    // Label 1424: @58802
23707    GIM_Try, /*On fail goto*//*Label 1429*/ 58833, // Rule ID 858 //
23708      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
23709      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
23710      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
23711      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
23712      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
23713      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
23714      // (smin:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (MIN_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
23715      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MIN_S_W,
23716      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23717      // GIR_Coverage, 858,
23718      GIR_Done,
23719    // Label 1429: @58833
23720    GIM_Reject,
23721    // Label 1425: @58834
23722    GIM_Try, /*On fail goto*//*Label 1430*/ 58865, // Rule ID 857 //
23723      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
23724      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
23725      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
23726      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
23727      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
23728      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
23729      // (smin:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (MIN_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
23730      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MIN_S_H,
23731      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23732      // GIR_Coverage, 857,
23733      GIR_Done,
23734    // Label 1430: @58865
23735    GIM_Reject,
23736    // Label 1426: @58866
23737    GIM_Try, /*On fail goto*//*Label 1431*/ 58897, // Rule ID 856 //
23738      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
23739      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
23740      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
23741      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
23742      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
23743      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
23744      // (smin:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (MIN_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
23745      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MIN_S_B,
23746      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23747      // GIR_Coverage, 856,
23748      GIR_Done,
23749    // Label 1431: @58897
23750    GIM_Reject,
23751    // Label 1427: @58898
23752    GIM_Reject,
23753    // Label 48: @58899
23754    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 9, /*)*//*default:*//*Label 1436*/ 59038,
23755    /*GILLT_v2s64*//*Label 1432*/ 58910, 0,
23756    /*GILLT_v4s32*//*Label 1433*/ 58942,
23757    /*GILLT_v8s16*//*Label 1434*/ 58974,
23758    /*GILLT_v16s8*//*Label 1435*/ 59006,
23759    // Label 1432: @58910
23760    GIM_Try, /*On fail goto*//*Label 1437*/ 58941, // Rule ID 839 //
23761      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
23762      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
23763      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
23764      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
23765      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
23766      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
23767      // (smax:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (MAX_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
23768      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MAX_S_D,
23769      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23770      // GIR_Coverage, 839,
23771      GIR_Done,
23772    // Label 1437: @58941
23773    GIM_Reject,
23774    // Label 1433: @58942
23775    GIM_Try, /*On fail goto*//*Label 1438*/ 58973, // Rule ID 838 //
23776      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
23777      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
23778      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
23779      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
23780      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
23781      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
23782      // (smax:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (MAX_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
23783      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MAX_S_W,
23784      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23785      // GIR_Coverage, 838,
23786      GIR_Done,
23787    // Label 1438: @58973
23788    GIM_Reject,
23789    // Label 1434: @58974
23790    GIM_Try, /*On fail goto*//*Label 1439*/ 59005, // Rule ID 837 //
23791      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
23792      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
23793      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
23794      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
23795      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
23796      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
23797      // (smax:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (MAX_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
23798      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MAX_S_H,
23799      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23800      // GIR_Coverage, 837,
23801      GIR_Done,
23802    // Label 1439: @59005
23803    GIM_Reject,
23804    // Label 1435: @59006
23805    GIM_Try, /*On fail goto*//*Label 1440*/ 59037, // Rule ID 836 //
23806      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
23807      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
23808      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
23809      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
23810      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
23811      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
23812      // (smax:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (MAX_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
23813      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MAX_S_B,
23814      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23815      // GIR_Coverage, 836,
23816      GIR_Done,
23817    // Label 1440: @59037
23818    GIM_Reject,
23819    // Label 1436: @59038
23820    GIM_Reject,
23821    // Label 49: @59039
23822    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 9, /*)*//*default:*//*Label 1445*/ 59178,
23823    /*GILLT_v2s64*//*Label 1441*/ 59050, 0,
23824    /*GILLT_v4s32*//*Label 1442*/ 59082,
23825    /*GILLT_v8s16*//*Label 1443*/ 59114,
23826    /*GILLT_v16s8*//*Label 1444*/ 59146,
23827    // Label 1441: @59050
23828    GIM_Try, /*On fail goto*//*Label 1446*/ 59081, // Rule ID 863 //
23829      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
23830      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
23831      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
23832      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
23833      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
23834      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
23835      // (umin:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (MIN_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
23836      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MIN_U_D,
23837      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23838      // GIR_Coverage, 863,
23839      GIR_Done,
23840    // Label 1446: @59081
23841    GIM_Reject,
23842    // Label 1442: @59082
23843    GIM_Try, /*On fail goto*//*Label 1447*/ 59113, // Rule ID 862 //
23844      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
23845      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
23846      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
23847      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
23848      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
23849      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
23850      // (umin:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (MIN_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
23851      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MIN_U_W,
23852      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23853      // GIR_Coverage, 862,
23854      GIR_Done,
23855    // Label 1447: @59113
23856    GIM_Reject,
23857    // Label 1443: @59114
23858    GIM_Try, /*On fail goto*//*Label 1448*/ 59145, // Rule ID 861 //
23859      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
23860      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
23861      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
23862      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
23863      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
23864      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
23865      // (umin:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (MIN_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
23866      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MIN_U_H,
23867      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23868      // GIR_Coverage, 861,
23869      GIR_Done,
23870    // Label 1448: @59145
23871    GIM_Reject,
23872    // Label 1444: @59146
23873    GIM_Try, /*On fail goto*//*Label 1449*/ 59177, // Rule ID 860 //
23874      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
23875      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
23876      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
23877      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
23878      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
23879      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
23880      // (umin:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (MIN_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
23881      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MIN_U_B,
23882      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23883      // GIR_Coverage, 860,
23884      GIR_Done,
23885    // Label 1449: @59177
23886    GIM_Reject,
23887    // Label 1445: @59178
23888    GIM_Reject,
23889    // Label 50: @59179
23890    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 9, /*)*//*default:*//*Label 1454*/ 59318,
23891    /*GILLT_v2s64*//*Label 1450*/ 59190, 0,
23892    /*GILLT_v4s32*//*Label 1451*/ 59222,
23893    /*GILLT_v8s16*//*Label 1452*/ 59254,
23894    /*GILLT_v16s8*//*Label 1453*/ 59286,
23895    // Label 1450: @59190
23896    GIM_Try, /*On fail goto*//*Label 1455*/ 59221, // Rule ID 843 //
23897      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
23898      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
23899      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
23900      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
23901      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
23902      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
23903      // (umax:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (MAX_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
23904      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MAX_U_D,
23905      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23906      // GIR_Coverage, 843,
23907      GIR_Done,
23908    // Label 1455: @59221
23909    GIM_Reject,
23910    // Label 1451: @59222
23911    GIM_Try, /*On fail goto*//*Label 1456*/ 59253, // Rule ID 842 //
23912      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
23913      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
23914      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
23915      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
23916      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
23917      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
23918      // (umax:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (MAX_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
23919      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MAX_U_W,
23920      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23921      // GIR_Coverage, 842,
23922      GIR_Done,
23923    // Label 1456: @59253
23924    GIM_Reject,
23925    // Label 1452: @59254
23926    GIM_Try, /*On fail goto*//*Label 1457*/ 59285, // Rule ID 841 //
23927      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
23928      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
23929      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
23930      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
23931      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
23932      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
23933      // (umax:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (MAX_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
23934      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MAX_U_H,
23935      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23936      // GIR_Coverage, 841,
23937      GIR_Done,
23938    // Label 1457: @59285
23939    GIM_Reject,
23940    // Label 1453: @59286
23941    GIM_Try, /*On fail goto*//*Label 1458*/ 59317, // Rule ID 840 //
23942      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
23943      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
23944      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
23945      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
23946      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
23947      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
23948      // (umax:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (MAX_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
23949      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MAX_U_B,
23950      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23951      // GIR_Coverage, 840,
23952      GIR_Done,
23953    // Label 1458: @59317
23954    GIM_Reject,
23955    // Label 1454: @59318
23956    GIM_Reject,
23957    // Label 51: @59319
23958    GIM_Try, /*On fail goto*//*Label 1459*/ 59403,
23959      GIM_CheckIsMBB, /*MI*/0, /*Op*/0,
23960      GIM_Try, /*On fail goto*//*Label 1460*/ 59338, // Rule ID 85 //
23961        GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips_RelocNotPIC,
23962        // (br (bb:{ *:[Other] }):$target)  =>  (J (bb:{ *:[Other] }):$target)
23963        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::J,
23964        GIR_AddImplicitDef, /*InsnID*/0, Mips::AT,
23965        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23966        // GIR_Coverage, 85,
23967        GIR_Done,
23968      // Label 1460: @59338
23969      GIM_Try, /*On fail goto*//*Label 1461*/ 59352, // Rule ID 92 //
23970        GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
23971        // (br (bb:{ *:[Other] }):$offset)  =>  (B (bb:{ *:[Other] }):$offset)
23972        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::B,
23973        GIR_AddImplicitDef, /*InsnID*/0, Mips::AT,
23974        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23975        // GIR_Coverage, 92,
23976        GIR_Done,
23977      // Label 1461: @59352
23978      GIM_Try, /*On fail goto*//*Label 1462*/ 59366, // Rule ID 1092 //
23979        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6_RelocNotPIC,
23980        // (br (bb:{ *:[Other] }):$target)  =>  (J_MM (bb:{ *:[Other] }):$target)
23981        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::J_MM,
23982        GIR_AddImplicitDef, /*InsnID*/0, Mips::AT,
23983        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23984        // GIR_Coverage, 1092,
23985        GIR_Done,
23986      // Label 1462: @59366
23987      GIM_Try, /*On fail goto*//*Label 1463*/ 59380, // Rule ID 1101 //
23988        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6_RelocPIC,
23989        // (br (bb:{ *:[Other] }):$offset)  =>  (B_MM (bb:{ *:[Other] }):$offset)
23990        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::B_MM,
23991        GIR_AddImplicitDef, /*InsnID*/0, Mips::AT,
23992        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23993        // GIR_Coverage, 1101,
23994        GIR_Done,
23995      // Label 1463: @59380
23996      GIM_Try, /*On fail goto*//*Label 1464*/ 59391, // Rule ID 1159 //
23997        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
23998        // (br (bb:{ *:[Other] }):$offset)  =>  (BC_MMR6 (bb:{ *:[Other] }):$offset)
23999        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::BC_MMR6,
24000        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24001        // GIR_Coverage, 1159,
24002        GIR_Done,
24003      // Label 1464: @59391
24004      GIM_Try, /*On fail goto*//*Label 1465*/ 59402, // Rule ID 1823 //
24005        GIM_CheckFeatures, GIFBS_InMips16Mode,
24006        // (br (bb:{ *:[Other] }):$imm16)  =>  (Bimm16 (bb:{ *:[Other] }):$imm16)
24007        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::Bimm16,
24008        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24009        // GIR_Coverage, 1823,
24010        GIR_Done,
24011      // Label 1465: @59402
24012      GIM_Reject,
24013    // Label 1459: @59403
24014    GIM_Reject,
24015    // Label 52: @59404
24016    GIM_Try, /*On fail goto*//*Label 1466*/ 59459, // Rule ID 1950 //
24017      GIM_CheckFeatures, GIFBS_HasMSA,
24018      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
24019      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
24020      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
24021      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
24022      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
24023      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
24024      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
24025      GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt4,
24026      // MIs[1] Operand 1
24027      // No operand predicates
24028      GIM_CheckIsSafeToFold, /*InsnID*/1,
24029      // (extractelt:{ *:[i32] } MSA128W:{ *:[v4i32] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$idx)  =>  (COPY_S_W:{ *:[i32] } MSA128W:{ *:[v4i32] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$idx)
24030      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::COPY_S_W,
24031      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
24032      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws
24033      GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
24034      GIR_EraseFromParent, /*InsnID*/0,
24035      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24036      // GIR_Coverage, 1950,
24037      GIR_Done,
24038    // Label 1466: @59459
24039    GIM_Reject,
24040    // Label 53: @59460
24041    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 1473*/ 59894,
24042    /*GILLT_s32*//*Label 1467*/ 59474,
24043    /*GILLT_s64*//*Label 1468*/ 59666, 0,
24044    /*GILLT_v2s64*//*Label 1469*/ 59798, 0,
24045    /*GILLT_v4s32*//*Label 1470*/ 59822,
24046    /*GILLT_v8s16*//*Label 1471*/ 59846,
24047    /*GILLT_v16s8*//*Label 1472*/ 59870,
24048    // Label 1467: @59474
24049    GIM_Try, /*On fail goto*//*Label 1474*/ 59665,
24050      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
24051      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
24052      GIM_Try, /*On fail goto*//*Label 1475*/ 59529, // Rule ID 103 //
24053        GIM_CheckFeatures, GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
24054        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
24055        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
24056        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
24057        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
24058        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
24059        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
24060        GIM_CheckIsSafeToFold, /*InsnID*/1,
24061        // (ctlz:{ *:[i32] } (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] }))  =>  (CLO:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
24062        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CLO,
24063        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
24064        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
24065        GIR_EraseFromParent, /*InsnID*/0,
24066        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24067        // GIR_Coverage, 103,
24068        GIR_Done,
24069      // Label 1475: @59529
24070      GIM_Try, /*On fail goto*//*Label 1476*/ 59574, // Rule ID 298 //
24071        GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc,
24072        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
24073        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
24074        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
24075        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
24076        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
24077        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
24078        GIM_CheckIsSafeToFold, /*InsnID*/1,
24079        // (ctlz:{ *:[i32] } (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] }))  =>  (CLO_R6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
24080        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CLO_R6,
24081        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
24082        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
24083        GIR_EraseFromParent, /*InsnID*/0,
24084        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24085        // GIR_Coverage, 298,
24086        GIR_Done,
24087      // Label 1476: @59574
24088      GIM_Try, /*On fail goto*//*Label 1477*/ 59619, // Rule ID 1088 //
24089        GIM_CheckFeatures, GIFBS_InMicroMips,
24090        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
24091        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
24092        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
24093        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
24094        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
24095        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
24096        GIM_CheckIsSafeToFold, /*InsnID*/1,
24097        // (ctlz:{ *:[i32] } (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] }))  =>  (CLO_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
24098        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CLO_MM,
24099        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
24100        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
24101        GIR_EraseFromParent, /*InsnID*/0,
24102        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24103        // GIR_Coverage, 1088,
24104        GIR_Done,
24105      // Label 1477: @59619
24106      GIM_Try, /*On fail goto*//*Label 1478*/ 59634, // Rule ID 102 //
24107        GIM_CheckFeatures, GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
24108        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
24109        // (ctlz:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)  =>  (CLZ:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
24110        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CLZ,
24111        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24112        // GIR_Coverage, 102,
24113        GIR_Done,
24114      // Label 1478: @59634
24115      GIM_Try, /*On fail goto*//*Label 1479*/ 59649, // Rule ID 299 //
24116        GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc,
24117        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
24118        // (ctlz:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)  =>  (CLZ_R6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
24119        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CLZ_R6,
24120        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24121        // GIR_Coverage, 299,
24122        GIR_Done,
24123      // Label 1479: @59649
24124      GIM_Try, /*On fail goto*//*Label 1480*/ 59664, // Rule ID 1087 //
24125        GIM_CheckFeatures, GIFBS_InMicroMips,
24126        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
24127        // (ctlz:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)  =>  (CLZ_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
24128        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CLZ_MM,
24129        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24130        // GIR_Coverage, 1087,
24131        GIR_Done,
24132      // Label 1480: @59664
24133      GIM_Reject,
24134    // Label 1474: @59665
24135    GIM_Reject,
24136    // Label 1468: @59666
24137    GIM_Try, /*On fail goto*//*Label 1481*/ 59797,
24138      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
24139      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
24140      GIM_Try, /*On fail goto*//*Label 1482*/ 59721, // Rule ID 252 //
24141        GIM_CheckFeatures, GIFBS_HasMips64_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips64r6,
24142        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
24143        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
24144        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
24145        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
24146        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
24147        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
24148        GIM_CheckIsSafeToFold, /*InsnID*/1,
24149        // (ctlz:{ *:[i64] } (xor:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, -1:{ *:[i64] }))  =>  (DCLO:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs)
24150        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DCLO,
24151        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
24152        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
24153        GIR_EraseFromParent, /*InsnID*/0,
24154        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24155        // GIR_Coverage, 252,
24156        GIR_Done,
24157      // Label 1482: @59721
24158      GIM_Try, /*On fail goto*//*Label 1483*/ 59766, // Rule ID 327 //
24159        GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
24160        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
24161        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
24162        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
24163        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
24164        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
24165        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
24166        GIM_CheckIsSafeToFold, /*InsnID*/1,
24167        // (ctlz:{ *:[i64] } (xor:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, -1:{ *:[i64] }))  =>  (DCLO_R6:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs)
24168        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DCLO_R6,
24169        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
24170        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
24171        GIR_EraseFromParent, /*InsnID*/0,
24172        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24173        // GIR_Coverage, 327,
24174        GIR_Done,
24175      // Label 1483: @59766
24176      GIM_Try, /*On fail goto*//*Label 1484*/ 59781, // Rule ID 251 //
24177        GIM_CheckFeatures, GIFBS_HasMips64_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips64r6,
24178        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
24179        // (ctlz:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs)  =>  (DCLZ:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs)
24180        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DCLZ,
24181        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24182        // GIR_Coverage, 251,
24183        GIR_Done,
24184      // Label 1484: @59781
24185      GIM_Try, /*On fail goto*//*Label 1485*/ 59796, // Rule ID 328 //
24186        GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
24187        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
24188        // (ctlz:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs)  =>  (DCLZ_R6:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs)
24189        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DCLZ_R6,
24190        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24191        // GIR_Coverage, 328,
24192        GIR_Done,
24193      // Label 1485: @59796
24194      GIM_Reject,
24195    // Label 1481: @59797
24196    GIM_Reject,
24197    // Label 1469: @59798
24198    GIM_Try, /*On fail goto*//*Label 1486*/ 59821, // Rule ID 903 //
24199      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
24200      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
24201      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
24202      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
24203      // (ctlz:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws)  =>  (NLZC_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws)
24204      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::NLZC_D,
24205      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24206      // GIR_Coverage, 903,
24207      GIR_Done,
24208    // Label 1486: @59821
24209    GIM_Reject,
24210    // Label 1470: @59822
24211    GIM_Try, /*On fail goto*//*Label 1487*/ 59845, // Rule ID 902 //
24212      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
24213      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
24214      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
24215      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
24216      // (ctlz:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws)  =>  (NLZC_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws)
24217      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::NLZC_W,
24218      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24219      // GIR_Coverage, 902,
24220      GIR_Done,
24221    // Label 1487: @59845
24222    GIM_Reject,
24223    // Label 1471: @59846
24224    GIM_Try, /*On fail goto*//*Label 1488*/ 59869, // Rule ID 901 //
24225      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
24226      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
24227      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
24228      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
24229      // (ctlz:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws)  =>  (NLZC_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws)
24230      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::NLZC_H,
24231      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24232      // GIR_Coverage, 901,
24233      GIR_Done,
24234    // Label 1488: @59869
24235    GIM_Reject,
24236    // Label 1472: @59870
24237    GIM_Try, /*On fail goto*//*Label 1489*/ 59893, // Rule ID 900 //
24238      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
24239      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
24240      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
24241      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
24242      // (ctlz:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws)  =>  (NLZC_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws)
24243      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::NLZC_B,
24244      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24245      // GIR_Coverage, 900,
24246      GIR_Done,
24247    // Label 1489: @59893
24248    GIM_Reject,
24249    // Label 1473: @59894
24250    GIM_Reject,
24251    // Label 54: @59895
24252    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 1496*/ 60053,
24253    /*GILLT_s32*//*Label 1490*/ 59909,
24254    /*GILLT_s64*//*Label 1491*/ 59933, 0,
24255    /*GILLT_v2s64*//*Label 1492*/ 59957, 0,
24256    /*GILLT_v4s32*//*Label 1493*/ 59981,
24257    /*GILLT_v8s16*//*Label 1494*/ 60005,
24258    /*GILLT_v16s8*//*Label 1495*/ 60029,
24259    // Label 1490: @59909
24260    GIM_Try, /*On fail goto*//*Label 1497*/ 59932, // Rule ID 266 //
24261      GIM_CheckFeatures, GIFBS_HasCnMips,
24262      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
24263      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
24264      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
24265      // (ctpop:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)  =>  (POP:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
24266      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::POP,
24267      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24268      // GIR_Coverage, 266,
24269      GIR_Done,
24270    // Label 1497: @59932
24271    GIM_Reject,
24272    // Label 1491: @59933
24273    GIM_Try, /*On fail goto*//*Label 1498*/ 59956, // Rule ID 267 //
24274      GIM_CheckFeatures, GIFBS_HasCnMips,
24275      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
24276      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
24277      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
24278      // (ctpop:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs)  =>  (DPOP:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs)
24279      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DPOP,
24280      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24281      // GIR_Coverage, 267,
24282      GIR_Done,
24283    // Label 1498: @59956
24284    GIM_Reject,
24285    // Label 1492: @59957
24286    GIM_Try, /*On fail goto*//*Label 1499*/ 59980, // Rule ID 925 //
24287      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
24288      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
24289      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
24290      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
24291      // (ctpop:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws)  =>  (PCNT_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws)
24292      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PCNT_D,
24293      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24294      // GIR_Coverage, 925,
24295      GIR_Done,
24296    // Label 1499: @59980
24297    GIM_Reject,
24298    // Label 1493: @59981
24299    GIM_Try, /*On fail goto*//*Label 1500*/ 60004, // Rule ID 924 //
24300      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
24301      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
24302      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
24303      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
24304      // (ctpop:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws)  =>  (PCNT_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws)
24305      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PCNT_W,
24306      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24307      // GIR_Coverage, 924,
24308      GIR_Done,
24309    // Label 1500: @60004
24310    GIM_Reject,
24311    // Label 1494: @60005
24312    GIM_Try, /*On fail goto*//*Label 1501*/ 60028, // Rule ID 923 //
24313      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
24314      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
24315      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
24316      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
24317      // (ctpop:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws)  =>  (PCNT_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws)
24318      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PCNT_H,
24319      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24320      // GIR_Coverage, 923,
24321      GIR_Done,
24322    // Label 1501: @60028
24323    GIM_Reject,
24324    // Label 1495: @60029
24325    GIM_Try, /*On fail goto*//*Label 1502*/ 60052, // Rule ID 922 //
24326      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
24327      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
24328      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
24329      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
24330      // (ctpop:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws)  =>  (PCNT_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws)
24331      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PCNT_B,
24332      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24333      // GIR_Coverage, 922,
24334      GIR_Done,
24335    // Label 1502: @60052
24336    GIM_Reject,
24337    // Label 1496: @60053
24338    GIM_Reject,
24339    // Label 55: @60054
24340    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1505*/ 60205,
24341    /*GILLT_s32*//*Label 1503*/ 60062,
24342    /*GILLT_s64*//*Label 1504*/ 60156,
24343    // Label 1503: @60062
24344    GIM_Try, /*On fail goto*//*Label 1506*/ 60155,
24345      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
24346      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
24347      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
24348      GIM_Try, /*On fail goto*//*Label 1507*/ 60115, // Rule ID 1415 //
24349        GIM_CheckFeatures, GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips,
24350        // (bswap:{ *:[i32] } GPR32:{ *:[i32] }:$rt)  =>  (ROTR:{ *:[i32] } (WSBH:{ *:[i32] } GPR32:{ *:[i32] }:$rt), 16:{ *:[i32] })
24351        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
24352        GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::WSBH,
24353        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
24354        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rt
24355        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
24356        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ROTR,
24357        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
24358        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24359        GIR_AddImm, /*InsnID*/0, /*Imm*/16,
24360        GIR_EraseFromParent, /*InsnID*/0,
24361        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24362        // GIR_Coverage, 1415,
24363        GIR_Done,
24364      // Label 1507: @60115
24365      GIM_Try, /*On fail goto*//*Label 1508*/ 60154, // Rule ID 2145 //
24366        GIM_CheckFeatures, GIFBS_InMicroMips,
24367        // (bswap:{ *:[i32] } GPR32:{ *:[i32] }:$rt)  =>  (ROTR_MM:{ *:[i32] } (WSBH_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rt), 16:{ *:[i32] })
24368        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
24369        GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::WSBH_MM,
24370        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
24371        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rt
24372        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
24373        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ROTR_MM,
24374        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
24375        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24376        GIR_AddImm, /*InsnID*/0, /*Imm*/16,
24377        GIR_EraseFromParent, /*InsnID*/0,
24378        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24379        // GIR_Coverage, 2145,
24380        GIR_Done,
24381      // Label 1508: @60154
24382      GIM_Reject,
24383    // Label 1506: @60155
24384    GIM_Reject,
24385    // Label 1504: @60156
24386    GIM_Try, /*On fail goto*//*Label 1509*/ 60204, // Rule ID 1572 //
24387      GIM_CheckFeatures, GIFBS_HasMips64r2_HasStdEnc,
24388      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
24389      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
24390      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
24391      // (bswap:{ *:[i64] } GPR64:{ *:[i64] }:$rt)  =>  (DSHD:{ *:[i64] } (DSBH:{ *:[i64] } GPR64:{ *:[i64] }:$rt))
24392      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
24393      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::DSBH,
24394      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
24395      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rt
24396      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
24397      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSHD,
24398      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
24399      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24400      GIR_EraseFromParent, /*InsnID*/0,
24401      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24402      // GIR_Coverage, 1572,
24403      GIR_Done,
24404    // Label 1509: @60204
24405    GIM_Reject,
24406    // Label 1505: @60205
24407    GIM_Reject,
24408    // Label 56: @60206
24409    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 7, /*)*//*default:*//*Label 1514*/ 60388,
24410    /*GILLT_s32*//*Label 1510*/ 60218,
24411    /*GILLT_s64*//*Label 1511*/ 60256, 0,
24412    /*GILLT_v2s64*//*Label 1512*/ 60340, 0,
24413    /*GILLT_v4s32*//*Label 1513*/ 60364,
24414    // Label 1510: @60218
24415    GIM_Try, /*On fail goto*//*Label 1515*/ 60255,
24416      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
24417      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
24418      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
24419      GIM_Try, /*On fail goto*//*Label 1516*/ 60243, // Rule ID 126 //
24420        GIM_CheckFeatures, GIFBS_HasMips2_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
24421        // (fsqrt:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)  =>  (FSQRT_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
24422        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSQRT_S,
24423        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24424        // GIR_Coverage, 126,
24425        GIR_Done,
24426      // Label 1516: @60243
24427      GIM_Try, /*On fail goto*//*Label 1517*/ 60254, // Rule ID 1150 //
24428        GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat,
24429        // (fsqrt:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)  =>  (FSQRT_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
24430        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSQRT_S_MM,
24431        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24432        // GIR_Coverage, 1150,
24433        GIR_Done,
24434      // Label 1517: @60254
24435      GIM_Reject,
24436    // Label 1515: @60255
24437    GIM_Reject,
24438    // Label 1511: @60256
24439    GIM_Try, /*On fail goto*//*Label 1518*/ 60339,
24440      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
24441      GIM_Try, /*On fail goto*//*Label 1519*/ 60281, // Rule ID 127 //
24442        GIM_CheckFeatures, GIFBS_HasMips2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips,
24443        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
24444        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
24445        // (fsqrt:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)  =>  (FSQRT_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)
24446        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSQRT_D32,
24447        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24448        // GIR_Coverage, 127,
24449        GIR_Done,
24450      // Label 1519: @60281
24451      GIM_Try, /*On fail goto*//*Label 1520*/ 60300, // Rule ID 128 //
24452        GIM_CheckFeatures, GIFBS_HasMips2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips,
24453        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
24454        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
24455        // (fsqrt:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)  =>  (FSQRT_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)
24456        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSQRT_D64,
24457        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24458        // GIR_Coverage, 128,
24459        GIR_Done,
24460      // Label 1520: @60300
24461      GIM_Try, /*On fail goto*//*Label 1521*/ 60319, // Rule ID 1136 //
24462        GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit,
24463        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
24464        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
24465        // (fsqrt:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)  =>  (FSQRT_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)
24466        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSQRT_D32_MM,
24467        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24468        // GIR_Coverage, 1136,
24469        GIR_Done,
24470      // Label 1521: @60319
24471      GIM_Try, /*On fail goto*//*Label 1522*/ 60338, // Rule ID 1137 //
24472        GIM_CheckFeatures, GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat,
24473        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
24474        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
24475        // (fsqrt:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)  =>  (FSQRT_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)
24476        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSQRT_D64_MM,
24477        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24478        // GIR_Coverage, 1137,
24479        GIR_Done,
24480      // Label 1522: @60338
24481      GIM_Reject,
24482    // Label 1518: @60339
24483    GIM_Reject,
24484    // Label 1512: @60340
24485    GIM_Try, /*On fail goto*//*Label 1523*/ 60363, // Rule ID 745 //
24486      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
24487      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
24488      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
24489      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
24490      // (fsqrt:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)  =>  (FSQRT_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
24491      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSQRT_D,
24492      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24493      // GIR_Coverage, 745,
24494      GIR_Done,
24495    // Label 1523: @60363
24496    GIM_Reject,
24497    // Label 1513: @60364
24498    GIM_Try, /*On fail goto*//*Label 1524*/ 60387, // Rule ID 744 //
24499      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
24500      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
24501      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
24502      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
24503      // (fsqrt:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)  =>  (FSQRT_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
24504      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSQRT_W,
24505      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24506      // GIR_Coverage, 744,
24507      GIR_Done,
24508    // Label 1524: @60387
24509    GIM_Reject,
24510    // Label 1514: @60388
24511    GIM_Reject,
24512    // Label 57: @60389
24513    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 7, /*)*//*default:*//*Label 1527*/ 60446,
24514    /*GILLT_v2s64*//*Label 1525*/ 60398, 0,
24515    /*GILLT_v4s32*//*Label 1526*/ 60422,
24516    // Label 1525: @60398
24517    GIM_Try, /*On fail goto*//*Label 1528*/ 60421, // Rule ID 727 //
24518      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
24519      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
24520      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
24521      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
24522      // (frint:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)  =>  (FRINT_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
24523      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FRINT_D,
24524      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24525      // GIR_Coverage, 727,
24526      GIR_Done,
24527    // Label 1528: @60421
24528    GIM_Reject,
24529    // Label 1526: @60422
24530    GIM_Try, /*On fail goto*//*Label 1529*/ 60445, // Rule ID 726 //
24531      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
24532      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
24533      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
24534      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
24535      // (frint:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)  =>  (FRINT_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
24536      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FRINT_W,
24537      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24538      // GIR_Coverage, 726,
24539      GIR_Done,
24540    // Label 1529: @60445
24541    GIM_Reject,
24542    // Label 1527: @60446
24543    GIM_Reject,
24544    // Label 58: @60447
24545    GIM_Reject,
24546    };
24547  return MatchTable0;
24548}
24549#endif // ifdef GET_GLOBALISEL_IMPL
24550#ifdef GET_GLOBALISEL_PREDICATES_DECL
24551PredicateBitset AvailableModuleFeatures;
24552mutable PredicateBitset AvailableFunctionFeatures;
24553PredicateBitset getAvailableFeatures() const {
24554  return AvailableModuleFeatures | AvailableFunctionFeatures;
24555}
24556PredicateBitset
24557computeAvailableModuleFeatures(const MipsSubtarget *Subtarget) const;
24558PredicateBitset
24559computeAvailableFunctionFeatures(const MipsSubtarget *Subtarget,
24560                                 const MachineFunction *MF) const;
24561void setupGeneratedPerFunctionState(MachineFunction &MF) override;
24562#endif // ifdef GET_GLOBALISEL_PREDICATES_DECL
24563#ifdef GET_GLOBALISEL_PREDICATES_INIT
24564AvailableModuleFeatures(computeAvailableModuleFeatures(&STI)),
24565AvailableFunctionFeatures()
24566#endif // ifdef GET_GLOBALISEL_PREDICATES_INIT
24567