1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2|* *| 3|* Target Instruction Enum Values and Descriptors *| 4|* *| 5|* Automatically generated file, do not edit! *| 6|* *| 7\*===----------------------------------------------------------------------===*/ 8 9#ifdef GET_INSTRINFO_ENUM 10#undef GET_INSTRINFO_ENUM 11namespace llvm { 12 13namespace Mips { 14 enum { 15 PHI = 0, 16 INLINEASM = 1, 17 INLINEASM_BR = 2, 18 CFI_INSTRUCTION = 3, 19 EH_LABEL = 4, 20 GC_LABEL = 5, 21 ANNOTATION_LABEL = 6, 22 KILL = 7, 23 EXTRACT_SUBREG = 8, 24 INSERT_SUBREG = 9, 25 IMPLICIT_DEF = 10, 26 SUBREG_TO_REG = 11, 27 COPY_TO_REGCLASS = 12, 28 DBG_VALUE = 13, 29 DBG_VALUE_LIST = 14, 30 DBG_INSTR_REF = 15, 31 DBG_PHI = 16, 32 DBG_LABEL = 17, 33 REG_SEQUENCE = 18, 34 COPY = 19, 35 BUNDLE = 20, 36 LIFETIME_START = 21, 37 LIFETIME_END = 22, 38 PSEUDO_PROBE = 23, 39 ARITH_FENCE = 24, 40 STACKMAP = 25, 41 FENTRY_CALL = 26, 42 PATCHPOINT = 27, 43 LOAD_STACK_GUARD = 28, 44 PREALLOCATED_SETUP = 29, 45 PREALLOCATED_ARG = 30, 46 STATEPOINT = 31, 47 LOCAL_ESCAPE = 32, 48 FAULTING_OP = 33, 49 PATCHABLE_OP = 34, 50 PATCHABLE_FUNCTION_ENTER = 35, 51 PATCHABLE_RET = 36, 52 PATCHABLE_FUNCTION_EXIT = 37, 53 PATCHABLE_TAIL_CALL = 38, 54 PATCHABLE_EVENT_CALL = 39, 55 PATCHABLE_TYPED_EVENT_CALL = 40, 56 ICALL_BRANCH_FUNNEL = 41, 57 MEMBARRIER = 42, 58 G_ASSERT_SEXT = 43, 59 G_ASSERT_ZEXT = 44, 60 G_ASSERT_ALIGN = 45, 61 G_ADD = 46, 62 G_SUB = 47, 63 G_MUL = 48, 64 G_SDIV = 49, 65 G_UDIV = 50, 66 G_SREM = 51, 67 G_UREM = 52, 68 G_SDIVREM = 53, 69 G_UDIVREM = 54, 70 G_AND = 55, 71 G_OR = 56, 72 G_XOR = 57, 73 G_IMPLICIT_DEF = 58, 74 G_PHI = 59, 75 G_FRAME_INDEX = 60, 76 G_GLOBAL_VALUE = 61, 77 G_EXTRACT = 62, 78 G_UNMERGE_VALUES = 63, 79 G_INSERT = 64, 80 G_MERGE_VALUES = 65, 81 G_BUILD_VECTOR = 66, 82 G_BUILD_VECTOR_TRUNC = 67, 83 G_CONCAT_VECTORS = 68, 84 G_PTRTOINT = 69, 85 G_INTTOPTR = 70, 86 G_BITCAST = 71, 87 G_FREEZE = 72, 88 G_INTRINSIC_FPTRUNC_ROUND = 73, 89 G_INTRINSIC_TRUNC = 74, 90 G_INTRINSIC_ROUND = 75, 91 G_INTRINSIC_LRINT = 76, 92 G_INTRINSIC_ROUNDEVEN = 77, 93 G_READCYCLECOUNTER = 78, 94 G_LOAD = 79, 95 G_SEXTLOAD = 80, 96 G_ZEXTLOAD = 81, 97 G_INDEXED_LOAD = 82, 98 G_INDEXED_SEXTLOAD = 83, 99 G_INDEXED_ZEXTLOAD = 84, 100 G_STORE = 85, 101 G_INDEXED_STORE = 86, 102 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 87, 103 G_ATOMIC_CMPXCHG = 88, 104 G_ATOMICRMW_XCHG = 89, 105 G_ATOMICRMW_ADD = 90, 106 G_ATOMICRMW_SUB = 91, 107 G_ATOMICRMW_AND = 92, 108 G_ATOMICRMW_NAND = 93, 109 G_ATOMICRMW_OR = 94, 110 G_ATOMICRMW_XOR = 95, 111 G_ATOMICRMW_MAX = 96, 112 G_ATOMICRMW_MIN = 97, 113 G_ATOMICRMW_UMAX = 98, 114 G_ATOMICRMW_UMIN = 99, 115 G_ATOMICRMW_FADD = 100, 116 G_ATOMICRMW_FSUB = 101, 117 G_ATOMICRMW_FMAX = 102, 118 G_ATOMICRMW_FMIN = 103, 119 G_ATOMICRMW_UINC_WRAP = 104, 120 G_ATOMICRMW_UDEC_WRAP = 105, 121 G_FENCE = 106, 122 G_BRCOND = 107, 123 G_BRINDIRECT = 108, 124 G_INVOKE_REGION_START = 109, 125 G_INTRINSIC = 110, 126 G_INTRINSIC_W_SIDE_EFFECTS = 111, 127 G_ANYEXT = 112, 128 G_TRUNC = 113, 129 G_CONSTANT = 114, 130 G_FCONSTANT = 115, 131 G_VASTART = 116, 132 G_VAARG = 117, 133 G_SEXT = 118, 134 G_SEXT_INREG = 119, 135 G_ZEXT = 120, 136 G_SHL = 121, 137 G_LSHR = 122, 138 G_ASHR = 123, 139 G_FSHL = 124, 140 G_FSHR = 125, 141 G_ROTR = 126, 142 G_ROTL = 127, 143 G_ICMP = 128, 144 G_FCMP = 129, 145 G_SELECT = 130, 146 G_UADDO = 131, 147 G_UADDE = 132, 148 G_USUBO = 133, 149 G_USUBE = 134, 150 G_SADDO = 135, 151 G_SADDE = 136, 152 G_SSUBO = 137, 153 G_SSUBE = 138, 154 G_UMULO = 139, 155 G_SMULO = 140, 156 G_UMULH = 141, 157 G_SMULH = 142, 158 G_UADDSAT = 143, 159 G_SADDSAT = 144, 160 G_USUBSAT = 145, 161 G_SSUBSAT = 146, 162 G_USHLSAT = 147, 163 G_SSHLSAT = 148, 164 G_SMULFIX = 149, 165 G_UMULFIX = 150, 166 G_SMULFIXSAT = 151, 167 G_UMULFIXSAT = 152, 168 G_SDIVFIX = 153, 169 G_UDIVFIX = 154, 170 G_SDIVFIXSAT = 155, 171 G_UDIVFIXSAT = 156, 172 G_FADD = 157, 173 G_FSUB = 158, 174 G_FMUL = 159, 175 G_FMA = 160, 176 G_FMAD = 161, 177 G_FDIV = 162, 178 G_FREM = 163, 179 G_FPOW = 164, 180 G_FPOWI = 165, 181 G_FEXP = 166, 182 G_FEXP2 = 167, 183 G_FLOG = 168, 184 G_FLOG2 = 169, 185 G_FLOG10 = 170, 186 G_FNEG = 171, 187 G_FPEXT = 172, 188 G_FPTRUNC = 173, 189 G_FPTOSI = 174, 190 G_FPTOUI = 175, 191 G_SITOFP = 176, 192 G_UITOFP = 177, 193 G_FABS = 178, 194 G_FCOPYSIGN = 179, 195 G_IS_FPCLASS = 180, 196 G_FCANONICALIZE = 181, 197 G_FMINNUM = 182, 198 G_FMAXNUM = 183, 199 G_FMINNUM_IEEE = 184, 200 G_FMAXNUM_IEEE = 185, 201 G_FMINIMUM = 186, 202 G_FMAXIMUM = 187, 203 G_PTR_ADD = 188, 204 G_PTRMASK = 189, 205 G_SMIN = 190, 206 G_SMAX = 191, 207 G_UMIN = 192, 208 G_UMAX = 193, 209 G_ABS = 194, 210 G_LROUND = 195, 211 G_LLROUND = 196, 212 G_BR = 197, 213 G_BRJT = 198, 214 G_INSERT_VECTOR_ELT = 199, 215 G_EXTRACT_VECTOR_ELT = 200, 216 G_SHUFFLE_VECTOR = 201, 217 G_CTTZ = 202, 218 G_CTTZ_ZERO_UNDEF = 203, 219 G_CTLZ = 204, 220 G_CTLZ_ZERO_UNDEF = 205, 221 G_CTPOP = 206, 222 G_BSWAP = 207, 223 G_BITREVERSE = 208, 224 G_FCEIL = 209, 225 G_FCOS = 210, 226 G_FSIN = 211, 227 G_FSQRT = 212, 228 G_FFLOOR = 213, 229 G_FRINT = 214, 230 G_FNEARBYINT = 215, 231 G_ADDRSPACE_CAST = 216, 232 G_BLOCK_ADDR = 217, 233 G_JUMP_TABLE = 218, 234 G_DYN_STACKALLOC = 219, 235 G_STRICT_FADD = 220, 236 G_STRICT_FSUB = 221, 237 G_STRICT_FMUL = 222, 238 G_STRICT_FDIV = 223, 239 G_STRICT_FREM = 224, 240 G_STRICT_FMA = 225, 241 G_STRICT_FSQRT = 226, 242 G_READ_REGISTER = 227, 243 G_WRITE_REGISTER = 228, 244 G_MEMCPY = 229, 245 G_MEMCPY_INLINE = 230, 246 G_MEMMOVE = 231, 247 G_MEMSET = 232, 248 G_BZERO = 233, 249 G_VECREDUCE_SEQ_FADD = 234, 250 G_VECREDUCE_SEQ_FMUL = 235, 251 G_VECREDUCE_FADD = 236, 252 G_VECREDUCE_FMUL = 237, 253 G_VECREDUCE_FMAX = 238, 254 G_VECREDUCE_FMIN = 239, 255 G_VECREDUCE_ADD = 240, 256 G_VECREDUCE_MUL = 241, 257 G_VECREDUCE_AND = 242, 258 G_VECREDUCE_OR = 243, 259 G_VECREDUCE_XOR = 244, 260 G_VECREDUCE_SMAX = 245, 261 G_VECREDUCE_SMIN = 246, 262 G_VECREDUCE_UMAX = 247, 263 G_VECREDUCE_UMIN = 248, 264 G_SBFX = 249, 265 G_UBFX = 250, 266 ABSMacro = 251, 267 ADJCALLSTACKDOWN = 252, 268 ADJCALLSTACKUP = 253, 269 AND_V_D_PSEUDO = 254, 270 AND_V_H_PSEUDO = 255, 271 AND_V_W_PSEUDO = 256, 272 ATOMIC_CMP_SWAP_I16 = 257, 273 ATOMIC_CMP_SWAP_I16_POSTRA = 258, 274 ATOMIC_CMP_SWAP_I32 = 259, 275 ATOMIC_CMP_SWAP_I32_POSTRA = 260, 276 ATOMIC_CMP_SWAP_I64 = 261, 277 ATOMIC_CMP_SWAP_I64_POSTRA = 262, 278 ATOMIC_CMP_SWAP_I8 = 263, 279 ATOMIC_CMP_SWAP_I8_POSTRA = 264, 280 ATOMIC_LOAD_ADD_I16 = 265, 281 ATOMIC_LOAD_ADD_I16_POSTRA = 266, 282 ATOMIC_LOAD_ADD_I32 = 267, 283 ATOMIC_LOAD_ADD_I32_POSTRA = 268, 284 ATOMIC_LOAD_ADD_I64 = 269, 285 ATOMIC_LOAD_ADD_I64_POSTRA = 270, 286 ATOMIC_LOAD_ADD_I8 = 271, 287 ATOMIC_LOAD_ADD_I8_POSTRA = 272, 288 ATOMIC_LOAD_AND_I16 = 273, 289 ATOMIC_LOAD_AND_I16_POSTRA = 274, 290 ATOMIC_LOAD_AND_I32 = 275, 291 ATOMIC_LOAD_AND_I32_POSTRA = 276, 292 ATOMIC_LOAD_AND_I64 = 277, 293 ATOMIC_LOAD_AND_I64_POSTRA = 278, 294 ATOMIC_LOAD_AND_I8 = 279, 295 ATOMIC_LOAD_AND_I8_POSTRA = 280, 296 ATOMIC_LOAD_MAX_I16 = 281, 297 ATOMIC_LOAD_MAX_I16_POSTRA = 282, 298 ATOMIC_LOAD_MAX_I32 = 283, 299 ATOMIC_LOAD_MAX_I32_POSTRA = 284, 300 ATOMIC_LOAD_MAX_I64 = 285, 301 ATOMIC_LOAD_MAX_I64_POSTRA = 286, 302 ATOMIC_LOAD_MAX_I8 = 287, 303 ATOMIC_LOAD_MAX_I8_POSTRA = 288, 304 ATOMIC_LOAD_MIN_I16 = 289, 305 ATOMIC_LOAD_MIN_I16_POSTRA = 290, 306 ATOMIC_LOAD_MIN_I32 = 291, 307 ATOMIC_LOAD_MIN_I32_POSTRA = 292, 308 ATOMIC_LOAD_MIN_I64 = 293, 309 ATOMIC_LOAD_MIN_I64_POSTRA = 294, 310 ATOMIC_LOAD_MIN_I8 = 295, 311 ATOMIC_LOAD_MIN_I8_POSTRA = 296, 312 ATOMIC_LOAD_NAND_I16 = 297, 313 ATOMIC_LOAD_NAND_I16_POSTRA = 298, 314 ATOMIC_LOAD_NAND_I32 = 299, 315 ATOMIC_LOAD_NAND_I32_POSTRA = 300, 316 ATOMIC_LOAD_NAND_I64 = 301, 317 ATOMIC_LOAD_NAND_I64_POSTRA = 302, 318 ATOMIC_LOAD_NAND_I8 = 303, 319 ATOMIC_LOAD_NAND_I8_POSTRA = 304, 320 ATOMIC_LOAD_OR_I16 = 305, 321 ATOMIC_LOAD_OR_I16_POSTRA = 306, 322 ATOMIC_LOAD_OR_I32 = 307, 323 ATOMIC_LOAD_OR_I32_POSTRA = 308, 324 ATOMIC_LOAD_OR_I64 = 309, 325 ATOMIC_LOAD_OR_I64_POSTRA = 310, 326 ATOMIC_LOAD_OR_I8 = 311, 327 ATOMIC_LOAD_OR_I8_POSTRA = 312, 328 ATOMIC_LOAD_SUB_I16 = 313, 329 ATOMIC_LOAD_SUB_I16_POSTRA = 314, 330 ATOMIC_LOAD_SUB_I32 = 315, 331 ATOMIC_LOAD_SUB_I32_POSTRA = 316, 332 ATOMIC_LOAD_SUB_I64 = 317, 333 ATOMIC_LOAD_SUB_I64_POSTRA = 318, 334 ATOMIC_LOAD_SUB_I8 = 319, 335 ATOMIC_LOAD_SUB_I8_POSTRA = 320, 336 ATOMIC_LOAD_UMAX_I16 = 321, 337 ATOMIC_LOAD_UMAX_I16_POSTRA = 322, 338 ATOMIC_LOAD_UMAX_I32 = 323, 339 ATOMIC_LOAD_UMAX_I32_POSTRA = 324, 340 ATOMIC_LOAD_UMAX_I64 = 325, 341 ATOMIC_LOAD_UMAX_I64_POSTRA = 326, 342 ATOMIC_LOAD_UMAX_I8 = 327, 343 ATOMIC_LOAD_UMAX_I8_POSTRA = 328, 344 ATOMIC_LOAD_UMIN_I16 = 329, 345 ATOMIC_LOAD_UMIN_I16_POSTRA = 330, 346 ATOMIC_LOAD_UMIN_I32 = 331, 347 ATOMIC_LOAD_UMIN_I32_POSTRA = 332, 348 ATOMIC_LOAD_UMIN_I64 = 333, 349 ATOMIC_LOAD_UMIN_I64_POSTRA = 334, 350 ATOMIC_LOAD_UMIN_I8 = 335, 351 ATOMIC_LOAD_UMIN_I8_POSTRA = 336, 352 ATOMIC_LOAD_XOR_I16 = 337, 353 ATOMIC_LOAD_XOR_I16_POSTRA = 338, 354 ATOMIC_LOAD_XOR_I32 = 339, 355 ATOMIC_LOAD_XOR_I32_POSTRA = 340, 356 ATOMIC_LOAD_XOR_I64 = 341, 357 ATOMIC_LOAD_XOR_I64_POSTRA = 342, 358 ATOMIC_LOAD_XOR_I8 = 343, 359 ATOMIC_LOAD_XOR_I8_POSTRA = 344, 360 ATOMIC_SWAP_I16 = 345, 361 ATOMIC_SWAP_I16_POSTRA = 346, 362 ATOMIC_SWAP_I32 = 347, 363 ATOMIC_SWAP_I32_POSTRA = 348, 364 ATOMIC_SWAP_I64 = 349, 365 ATOMIC_SWAP_I64_POSTRA = 350, 366 ATOMIC_SWAP_I8 = 351, 367 ATOMIC_SWAP_I8_POSTRA = 352, 368 B = 353, 369 BAL_BR = 354, 370 BAL_BR_MM = 355, 371 BEQLImmMacro = 356, 372 BGE = 357, 373 BGEImmMacro = 358, 374 BGEL = 359, 375 BGELImmMacro = 360, 376 BGEU = 361, 377 BGEUImmMacro = 362, 378 BGEUL = 363, 379 BGEULImmMacro = 364, 380 BGT = 365, 381 BGTImmMacro = 366, 382 BGTL = 367, 383 BGTLImmMacro = 368, 384 BGTU = 369, 385 BGTUImmMacro = 370, 386 BGTUL = 371, 387 BGTULImmMacro = 372, 388 BLE = 373, 389 BLEImmMacro = 374, 390 BLEL = 375, 391 BLELImmMacro = 376, 392 BLEU = 377, 393 BLEUImmMacro = 378, 394 BLEUL = 379, 395 BLEULImmMacro = 380, 396 BLT = 381, 397 BLTImmMacro = 382, 398 BLTL = 383, 399 BLTLImmMacro = 384, 400 BLTU = 385, 401 BLTUImmMacro = 386, 402 BLTUL = 387, 403 BLTULImmMacro = 388, 404 BNELImmMacro = 389, 405 BPOSGE32_PSEUDO = 390, 406 BSEL_D_PSEUDO = 391, 407 BSEL_FD_PSEUDO = 392, 408 BSEL_FW_PSEUDO = 393, 409 BSEL_H_PSEUDO = 394, 410 BSEL_W_PSEUDO = 395, 411 B_MM = 396, 412 B_MMR6_Pseudo = 397, 413 B_MM_Pseudo = 398, 414 BeqImm = 399, 415 BneImm = 400, 416 BteqzT8CmpX16 = 401, 417 BteqzT8CmpiX16 = 402, 418 BteqzT8SltX16 = 403, 419 BteqzT8SltiX16 = 404, 420 BteqzT8SltiuX16 = 405, 421 BteqzT8SltuX16 = 406, 422 BtnezT8CmpX16 = 407, 423 BtnezT8CmpiX16 = 408, 424 BtnezT8SltX16 = 409, 425 BtnezT8SltiX16 = 410, 426 BtnezT8SltiuX16 = 411, 427 BtnezT8SltuX16 = 412, 428 BuildPairF64 = 413, 429 BuildPairF64_64 = 414, 430 CFTC1 = 415, 431 CONSTPOOL_ENTRY = 416, 432 COPY_FD_PSEUDO = 417, 433 COPY_FW_PSEUDO = 418, 434 CTTC1 = 419, 435 Constant32 = 420, 436 DMULImmMacro = 421, 437 DMULMacro = 422, 438 DMULOMacro = 423, 439 DMULOUMacro = 424, 440 DROL = 425, 441 DROLImm = 426, 442 DROR = 427, 443 DRORImm = 428, 444 DSDivIMacro = 429, 445 DSDivMacro = 430, 446 DSRemIMacro = 431, 447 DSRemMacro = 432, 448 DUDivIMacro = 433, 449 DUDivMacro = 434, 450 DURemIMacro = 435, 451 DURemMacro = 436, 452 ERet = 437, 453 ExtractElementF64 = 438, 454 ExtractElementF64_64 = 439, 455 FABS_D = 440, 456 FABS_W = 441, 457 FEXP2_D_1_PSEUDO = 442, 458 FEXP2_W_1_PSEUDO = 443, 459 FILL_FD_PSEUDO = 444, 460 FILL_FW_PSEUDO = 445, 461 GotPrologue16 = 446, 462 INSERT_B_VIDX64_PSEUDO = 447, 463 INSERT_B_VIDX_PSEUDO = 448, 464 INSERT_D_VIDX64_PSEUDO = 449, 465 INSERT_D_VIDX_PSEUDO = 450, 466 INSERT_FD_PSEUDO = 451, 467 INSERT_FD_VIDX64_PSEUDO = 452, 468 INSERT_FD_VIDX_PSEUDO = 453, 469 INSERT_FW_PSEUDO = 454, 470 INSERT_FW_VIDX64_PSEUDO = 455, 471 INSERT_FW_VIDX_PSEUDO = 456, 472 INSERT_H_VIDX64_PSEUDO = 457, 473 INSERT_H_VIDX_PSEUDO = 458, 474 INSERT_W_VIDX64_PSEUDO = 459, 475 INSERT_W_VIDX_PSEUDO = 460, 476 JALR64Pseudo = 461, 477 JALRHB64Pseudo = 462, 478 JALRHBPseudo = 463, 479 JALRPseudo = 464, 480 JAL_MMR6 = 465, 481 JalOneReg = 466, 482 JalTwoReg = 467, 483 LDMacro = 468, 484 LDR_D = 469, 485 LDR_W = 470, 486 LD_F16 = 471, 487 LOAD_ACC128 = 472, 488 LOAD_ACC64 = 473, 489 LOAD_ACC64DSP = 474, 490 LOAD_CCOND_DSP = 475, 491 LONG_BRANCH_ADDiu = 476, 492 LONG_BRANCH_ADDiu2Op = 477, 493 LONG_BRANCH_DADDiu = 478, 494 LONG_BRANCH_DADDiu2Op = 479, 495 LONG_BRANCH_LUi = 480, 496 LONG_BRANCH_LUi2Op = 481, 497 LONG_BRANCH_LUi2Op_64 = 482, 498 LWM_MM = 483, 499 LoadAddrImm32 = 484, 500 LoadAddrImm64 = 485, 501 LoadAddrReg32 = 486, 502 LoadAddrReg64 = 487, 503 LoadImm32 = 488, 504 LoadImm64 = 489, 505 LoadImmDoubleFGR = 490, 506 LoadImmDoubleFGR_32 = 491, 507 LoadImmDoubleGPR = 492, 508 LoadImmSingleFGR = 493, 509 LoadImmSingleGPR = 494, 510 LwConstant32 = 495, 511 MFTACX = 496, 512 MFTC0 = 497, 513 MFTC1 = 498, 514 MFTDSP = 499, 515 MFTGPR = 500, 516 MFTHC1 = 501, 517 MFTHI = 502, 518 MFTLO = 503, 519 MIPSeh_return32 = 504, 520 MIPSeh_return64 = 505, 521 MSA_FP_EXTEND_D_PSEUDO = 506, 522 MSA_FP_EXTEND_W_PSEUDO = 507, 523 MSA_FP_ROUND_D_PSEUDO = 508, 524 MSA_FP_ROUND_W_PSEUDO = 509, 525 MTTACX = 510, 526 MTTC0 = 511, 527 MTTC1 = 512, 528 MTTDSP = 513, 529 MTTGPR = 514, 530 MTTHC1 = 515, 531 MTTHI = 516, 532 MTTLO = 517, 533 MULImmMacro = 518, 534 MULOMacro = 519, 535 MULOUMacro = 520, 536 MultRxRy16 = 521, 537 MultRxRyRz16 = 522, 538 MultuRxRy16 = 523, 539 MultuRxRyRz16 = 524, 540 NOP = 525, 541 NORImm = 526, 542 NORImm64 = 527, 543 NOR_V_D_PSEUDO = 528, 544 NOR_V_H_PSEUDO = 529, 545 NOR_V_W_PSEUDO = 530, 546 OR_V_D_PSEUDO = 531, 547 OR_V_H_PSEUDO = 532, 548 OR_V_W_PSEUDO = 533, 549 PseudoCMPU_EQ_QB = 534, 550 PseudoCMPU_LE_QB = 535, 551 PseudoCMPU_LT_QB = 536, 552 PseudoCMP_EQ_PH = 537, 553 PseudoCMP_LE_PH = 538, 554 PseudoCMP_LT_PH = 539, 555 PseudoCVT_D32_W = 540, 556 PseudoCVT_D64_L = 541, 557 PseudoCVT_D64_W = 542, 558 PseudoCVT_S_L = 543, 559 PseudoCVT_S_W = 544, 560 PseudoDMULT = 545, 561 PseudoDMULTu = 546, 562 PseudoDSDIV = 547, 563 PseudoDUDIV = 548, 564 PseudoD_SELECT_I = 549, 565 PseudoD_SELECT_I64 = 550, 566 PseudoIndirectBranch = 551, 567 PseudoIndirectBranch64 = 552, 568 PseudoIndirectBranch64R6 = 553, 569 PseudoIndirectBranchR6 = 554, 570 PseudoIndirectBranch_MM = 555, 571 PseudoIndirectBranch_MMR6 = 556, 572 PseudoIndirectHazardBranch = 557, 573 PseudoIndirectHazardBranch64 = 558, 574 PseudoIndrectHazardBranch64R6 = 559, 575 PseudoIndrectHazardBranchR6 = 560, 576 PseudoMADD = 561, 577 PseudoMADDU = 562, 578 PseudoMADDU_MM = 563, 579 PseudoMADD_MM = 564, 580 PseudoMFHI = 565, 581 PseudoMFHI64 = 566, 582 PseudoMFHI_MM = 567, 583 PseudoMFLO = 568, 584 PseudoMFLO64 = 569, 585 PseudoMFLO_MM = 570, 586 PseudoMSUB = 571, 587 PseudoMSUBU = 572, 588 PseudoMSUBU_MM = 573, 589 PseudoMSUB_MM = 574, 590 PseudoMTLOHI = 575, 591 PseudoMTLOHI64 = 576, 592 PseudoMTLOHI_DSP = 577, 593 PseudoMTLOHI_MM = 578, 594 PseudoMULT = 579, 595 PseudoMULT_MM = 580, 596 PseudoMULTu = 581, 597 PseudoMULTu_MM = 582, 598 PseudoPICK_PH = 583, 599 PseudoPICK_QB = 584, 600 PseudoReturn = 585, 601 PseudoReturn64 = 586, 602 PseudoSDIV = 587, 603 PseudoSELECTFP_F_D32 = 588, 604 PseudoSELECTFP_F_D64 = 589, 605 PseudoSELECTFP_F_I = 590, 606 PseudoSELECTFP_F_I64 = 591, 607 PseudoSELECTFP_F_S = 592, 608 PseudoSELECTFP_T_D32 = 593, 609 PseudoSELECTFP_T_D64 = 594, 610 PseudoSELECTFP_T_I = 595, 611 PseudoSELECTFP_T_I64 = 596, 612 PseudoSELECTFP_T_S = 597, 613 PseudoSELECT_D32 = 598, 614 PseudoSELECT_D64 = 599, 615 PseudoSELECT_I = 600, 616 PseudoSELECT_I64 = 601, 617 PseudoSELECT_S = 602, 618 PseudoTRUNC_W_D = 603, 619 PseudoTRUNC_W_D32 = 604, 620 PseudoTRUNC_W_S = 605, 621 PseudoUDIV = 606, 622 ROL = 607, 623 ROLImm = 608, 624 ROR = 609, 625 RORImm = 610, 626 RetRA = 611, 627 RetRA16 = 612, 628 SDC1_M1 = 613, 629 SDIV_MM_Pseudo = 614, 630 SDMacro = 615, 631 SDivIMacro = 616, 632 SDivMacro = 617, 633 SEQIMacro = 618, 634 SEQMacro = 619, 635 SGE = 620, 636 SGEImm = 621, 637 SGEImm64 = 622, 638 SGEU = 623, 639 SGEUImm = 624, 640 SGEUImm64 = 625, 641 SGTImm = 626, 642 SGTImm64 = 627, 643 SGTUImm = 628, 644 SGTUImm64 = 629, 645 SLE = 630, 646 SLEImm = 631, 647 SLEImm64 = 632, 648 SLEU = 633, 649 SLEUImm = 634, 650 SLEUImm64 = 635, 651 SLTImm64 = 636, 652 SLTUImm64 = 637, 653 SNEIMacro = 638, 654 SNEMacro = 639, 655 SNZ_B_PSEUDO = 640, 656 SNZ_D_PSEUDO = 641, 657 SNZ_H_PSEUDO = 642, 658 SNZ_V_PSEUDO = 643, 659 SNZ_W_PSEUDO = 644, 660 SRemIMacro = 645, 661 SRemMacro = 646, 662 STORE_ACC128 = 647, 663 STORE_ACC64 = 648, 664 STORE_ACC64DSP = 649, 665 STORE_CCOND_DSP = 650, 666 STR_D = 651, 667 STR_W = 652, 668 ST_F16 = 653, 669 SWM_MM = 654, 670 SZ_B_PSEUDO = 655, 671 SZ_D_PSEUDO = 656, 672 SZ_H_PSEUDO = 657, 673 SZ_V_PSEUDO = 658, 674 SZ_W_PSEUDO = 659, 675 SaaAddr = 660, 676 SaadAddr = 661, 677 SelBeqZ = 662, 678 SelBneZ = 663, 679 SelTBteqZCmp = 664, 680 SelTBteqZCmpi = 665, 681 SelTBteqZSlt = 666, 682 SelTBteqZSlti = 667, 683 SelTBteqZSltiu = 668, 684 SelTBteqZSltu = 669, 685 SelTBtneZCmp = 670, 686 SelTBtneZCmpi = 671, 687 SelTBtneZSlt = 672, 688 SelTBtneZSlti = 673, 689 SelTBtneZSltiu = 674, 690 SelTBtneZSltu = 675, 691 SltCCRxRy16 = 676, 692 SltiCCRxImmX16 = 677, 693 SltiuCCRxImmX16 = 678, 694 SltuCCRxRy16 = 679, 695 SltuRxRyRz16 = 680, 696 TAILCALL = 681, 697 TAILCALL64R6REG = 682, 698 TAILCALLHB64R6REG = 683, 699 TAILCALLHBR6REG = 684, 700 TAILCALLR6REG = 685, 701 TAILCALLREG = 686, 702 TAILCALLREG64 = 687, 703 TAILCALLREGHB = 688, 704 TAILCALLREGHB64 = 689, 705 TAILCALLREG_MM = 690, 706 TAILCALLREG_MMR6 = 691, 707 TAILCALL_MM = 692, 708 TAILCALL_MMR6 = 693, 709 TRAP = 694, 710 TRAP_MM = 695, 711 UDIV_MM_Pseudo = 696, 712 UDivIMacro = 697, 713 UDivMacro = 698, 714 URemIMacro = 699, 715 URemMacro = 700, 716 Ulh = 701, 717 Ulhu = 702, 718 Ulw = 703, 719 Ush = 704, 720 Usw = 705, 721 XOR_V_D_PSEUDO = 706, 722 XOR_V_H_PSEUDO = 707, 723 XOR_V_W_PSEUDO = 708, 724 ABSQ_S_PH = 709, 725 ABSQ_S_PH_MM = 710, 726 ABSQ_S_QB = 711, 727 ABSQ_S_QB_MMR2 = 712, 728 ABSQ_S_W = 713, 729 ABSQ_S_W_MM = 714, 730 ADD = 715, 731 ADDIUPC = 716, 732 ADDIUPC_MM = 717, 733 ADDIUPC_MMR6 = 718, 734 ADDIUR1SP_MM = 719, 735 ADDIUR2_MM = 720, 736 ADDIUS5_MM = 721, 737 ADDIUSP_MM = 722, 738 ADDIU_MMR6 = 723, 739 ADDQH_PH = 724, 740 ADDQH_PH_MMR2 = 725, 741 ADDQH_R_PH = 726, 742 ADDQH_R_PH_MMR2 = 727, 743 ADDQH_R_W = 728, 744 ADDQH_R_W_MMR2 = 729, 745 ADDQH_W = 730, 746 ADDQH_W_MMR2 = 731, 747 ADDQ_PH = 732, 748 ADDQ_PH_MM = 733, 749 ADDQ_S_PH = 734, 750 ADDQ_S_PH_MM = 735, 751 ADDQ_S_W = 736, 752 ADDQ_S_W_MM = 737, 753 ADDR_PS64 = 738, 754 ADDSC = 739, 755 ADDSC_MM = 740, 756 ADDS_A_B = 741, 757 ADDS_A_D = 742, 758 ADDS_A_H = 743, 759 ADDS_A_W = 744, 760 ADDS_S_B = 745, 761 ADDS_S_D = 746, 762 ADDS_S_H = 747, 763 ADDS_S_W = 748, 764 ADDS_U_B = 749, 765 ADDS_U_D = 750, 766 ADDS_U_H = 751, 767 ADDS_U_W = 752, 768 ADDU16_MM = 753, 769 ADDU16_MMR6 = 754, 770 ADDUH_QB = 755, 771 ADDUH_QB_MMR2 = 756, 772 ADDUH_R_QB = 757, 773 ADDUH_R_QB_MMR2 = 758, 774 ADDU_MMR6 = 759, 775 ADDU_PH = 760, 776 ADDU_PH_MMR2 = 761, 777 ADDU_QB = 762, 778 ADDU_QB_MM = 763, 779 ADDU_S_PH = 764, 780 ADDU_S_PH_MMR2 = 765, 781 ADDU_S_QB = 766, 782 ADDU_S_QB_MM = 767, 783 ADDVI_B = 768, 784 ADDVI_D = 769, 785 ADDVI_H = 770, 786 ADDVI_W = 771, 787 ADDV_B = 772, 788 ADDV_D = 773, 789 ADDV_H = 774, 790 ADDV_W = 775, 791 ADDWC = 776, 792 ADDWC_MM = 777, 793 ADD_A_B = 778, 794 ADD_A_D = 779, 795 ADD_A_H = 780, 796 ADD_A_W = 781, 797 ADD_MM = 782, 798 ADD_MMR6 = 783, 799 ADDi = 784, 800 ADDi_MM = 785, 801 ADDiu = 786, 802 ADDiu_MM = 787, 803 ADDu = 788, 804 ADDu_MM = 789, 805 ALIGN = 790, 806 ALIGN_MMR6 = 791, 807 ALUIPC = 792, 808 ALUIPC_MMR6 = 793, 809 AND = 794, 810 AND16_MM = 795, 811 AND16_MMR6 = 796, 812 AND64 = 797, 813 ANDI16_MM = 798, 814 ANDI16_MMR6 = 799, 815 ANDI_B = 800, 816 ANDI_MMR6 = 801, 817 AND_MM = 802, 818 AND_MMR6 = 803, 819 AND_V = 804, 820 ANDi = 805, 821 ANDi64 = 806, 822 ANDi_MM = 807, 823 APPEND = 808, 824 APPEND_MMR2 = 809, 825 ASUB_S_B = 810, 826 ASUB_S_D = 811, 827 ASUB_S_H = 812, 828 ASUB_S_W = 813, 829 ASUB_U_B = 814, 830 ASUB_U_D = 815, 831 ASUB_U_H = 816, 832 ASUB_U_W = 817, 833 AUI = 818, 834 AUIPC = 819, 835 AUIPC_MMR6 = 820, 836 AUI_MMR6 = 821, 837 AVER_S_B = 822, 838 AVER_S_D = 823, 839 AVER_S_H = 824, 840 AVER_S_W = 825, 841 AVER_U_B = 826, 842 AVER_U_D = 827, 843 AVER_U_H = 828, 844 AVER_U_W = 829, 845 AVE_S_B = 830, 846 AVE_S_D = 831, 847 AVE_S_H = 832, 848 AVE_S_W = 833, 849 AVE_U_B = 834, 850 AVE_U_D = 835, 851 AVE_U_H = 836, 852 AVE_U_W = 837, 853 AddiuRxImmX16 = 838, 854 AddiuRxPcImmX16 = 839, 855 AddiuRxRxImm16 = 840, 856 AddiuRxRxImmX16 = 841, 857 AddiuRxRyOffMemX16 = 842, 858 AddiuSpImm16 = 843, 859 AddiuSpImmX16 = 844, 860 AdduRxRyRz16 = 845, 861 AndRxRxRy16 = 846, 862 B16_MM = 847, 863 BADDu = 848, 864 BAL = 849, 865 BALC = 850, 866 BALC_MMR6 = 851, 867 BALIGN = 852, 868 BALIGN_MMR2 = 853, 869 BBIT0 = 854, 870 BBIT032 = 855, 871 BBIT1 = 856, 872 BBIT132 = 857, 873 BC = 858, 874 BC16_MMR6 = 859, 875 BC1EQZ = 860, 876 BC1EQZC_MMR6 = 861, 877 BC1F = 862, 878 BC1FL = 863, 879 BC1F_MM = 864, 880 BC1NEZ = 865, 881 BC1NEZC_MMR6 = 866, 882 BC1T = 867, 883 BC1TL = 868, 884 BC1T_MM = 869, 885 BC2EQZ = 870, 886 BC2EQZC_MMR6 = 871, 887 BC2NEZ = 872, 888 BC2NEZC_MMR6 = 873, 889 BCLRI_B = 874, 890 BCLRI_D = 875, 891 BCLRI_H = 876, 892 BCLRI_W = 877, 893 BCLR_B = 878, 894 BCLR_D = 879, 895 BCLR_H = 880, 896 BCLR_W = 881, 897 BC_MMR6 = 882, 898 BEQ = 883, 899 BEQ64 = 884, 900 BEQC = 885, 901 BEQC64 = 886, 902 BEQC_MMR6 = 887, 903 BEQL = 888, 904 BEQZ16_MM = 889, 905 BEQZALC = 890, 906 BEQZALC_MMR6 = 891, 907 BEQZC = 892, 908 BEQZC16_MMR6 = 893, 909 BEQZC64 = 894, 910 BEQZC_MM = 895, 911 BEQZC_MMR6 = 896, 912 BEQ_MM = 897, 913 BGEC = 898, 914 BGEC64 = 899, 915 BGEC_MMR6 = 900, 916 BGEUC = 901, 917 BGEUC64 = 902, 918 BGEUC_MMR6 = 903, 919 BGEZ = 904, 920 BGEZ64 = 905, 921 BGEZAL = 906, 922 BGEZALC = 907, 923 BGEZALC_MMR6 = 908, 924 BGEZALL = 909, 925 BGEZALS_MM = 910, 926 BGEZAL_MM = 911, 927 BGEZC = 912, 928 BGEZC64 = 913, 929 BGEZC_MMR6 = 914, 930 BGEZL = 915, 931 BGEZ_MM = 916, 932 BGTZ = 917, 933 BGTZ64 = 918, 934 BGTZALC = 919, 935 BGTZALC_MMR6 = 920, 936 BGTZC = 921, 937 BGTZC64 = 922, 938 BGTZC_MMR6 = 923, 939 BGTZL = 924, 940 BGTZ_MM = 925, 941 BINSLI_B = 926, 942 BINSLI_D = 927, 943 BINSLI_H = 928, 944 BINSLI_W = 929, 945 BINSL_B = 930, 946 BINSL_D = 931, 947 BINSL_H = 932, 948 BINSL_W = 933, 949 BINSRI_B = 934, 950 BINSRI_D = 935, 951 BINSRI_H = 936, 952 BINSRI_W = 937, 953 BINSR_B = 938, 954 BINSR_D = 939, 955 BINSR_H = 940, 956 BINSR_W = 941, 957 BITREV = 942, 958 BITREV_MM = 943, 959 BITSWAP = 944, 960 BITSWAP_MMR6 = 945, 961 BLEZ = 946, 962 BLEZ64 = 947, 963 BLEZALC = 948, 964 BLEZALC_MMR6 = 949, 965 BLEZC = 950, 966 BLEZC64 = 951, 967 BLEZC_MMR6 = 952, 968 BLEZL = 953, 969 BLEZ_MM = 954, 970 BLTC = 955, 971 BLTC64 = 956, 972 BLTC_MMR6 = 957, 973 BLTUC = 958, 974 BLTUC64 = 959, 975 BLTUC_MMR6 = 960, 976 BLTZ = 961, 977 BLTZ64 = 962, 978 BLTZAL = 963, 979 BLTZALC = 964, 980 BLTZALC_MMR6 = 965, 981 BLTZALL = 966, 982 BLTZALS_MM = 967, 983 BLTZAL_MM = 968, 984 BLTZC = 969, 985 BLTZC64 = 970, 986 BLTZC_MMR6 = 971, 987 BLTZL = 972, 988 BLTZ_MM = 973, 989 BMNZI_B = 974, 990 BMNZ_V = 975, 991 BMZI_B = 976, 992 BMZ_V = 977, 993 BNE = 978, 994 BNE64 = 979, 995 BNEC = 980, 996 BNEC64 = 981, 997 BNEC_MMR6 = 982, 998 BNEGI_B = 983, 999 BNEGI_D = 984, 1000 BNEGI_H = 985, 1001 BNEGI_W = 986, 1002 BNEG_B = 987, 1003 BNEG_D = 988, 1004 BNEG_H = 989, 1005 BNEG_W = 990, 1006 BNEL = 991, 1007 BNEZ16_MM = 992, 1008 BNEZALC = 993, 1009 BNEZALC_MMR6 = 994, 1010 BNEZC = 995, 1011 BNEZC16_MMR6 = 996, 1012 BNEZC64 = 997, 1013 BNEZC_MM = 998, 1014 BNEZC_MMR6 = 999, 1015 BNE_MM = 1000, 1016 BNVC = 1001, 1017 BNVC_MMR6 = 1002, 1018 BNZ_B = 1003, 1019 BNZ_D = 1004, 1020 BNZ_H = 1005, 1021 BNZ_V = 1006, 1022 BNZ_W = 1007, 1023 BOVC = 1008, 1024 BOVC_MMR6 = 1009, 1025 BPOSGE32 = 1010, 1026 BPOSGE32C_MMR3 = 1011, 1027 BPOSGE32_MM = 1012, 1028 BREAK = 1013, 1029 BREAK16_MM = 1014, 1030 BREAK16_MMR6 = 1015, 1031 BREAK_MM = 1016, 1032 BREAK_MMR6 = 1017, 1033 BSELI_B = 1018, 1034 BSEL_V = 1019, 1035 BSETI_B = 1020, 1036 BSETI_D = 1021, 1037 BSETI_H = 1022, 1038 BSETI_W = 1023, 1039 BSET_B = 1024, 1040 BSET_D = 1025, 1041 BSET_H = 1026, 1042 BSET_W = 1027, 1043 BZ_B = 1028, 1044 BZ_D = 1029, 1045 BZ_H = 1030, 1046 BZ_V = 1031, 1047 BZ_W = 1032, 1048 BeqzRxImm16 = 1033, 1049 BeqzRxImmX16 = 1034, 1050 Bimm16 = 1035, 1051 BimmX16 = 1036, 1052 BnezRxImm16 = 1037, 1053 BnezRxImmX16 = 1038, 1054 Break16 = 1039, 1055 Bteqz16 = 1040, 1056 BteqzX16 = 1041, 1057 Btnez16 = 1042, 1058 BtnezX16 = 1043, 1059 CACHE = 1044, 1060 CACHEE = 1045, 1061 CACHEE_MM = 1046, 1062 CACHE_MM = 1047, 1063 CACHE_MMR6 = 1048, 1064 CACHE_R6 = 1049, 1065 CEIL_L_D64 = 1050, 1066 CEIL_L_D_MMR6 = 1051, 1067 CEIL_L_S = 1052, 1068 CEIL_L_S_MMR6 = 1053, 1069 CEIL_W_D32 = 1054, 1070 CEIL_W_D64 = 1055, 1071 CEIL_W_D_MMR6 = 1056, 1072 CEIL_W_MM = 1057, 1073 CEIL_W_S = 1058, 1074 CEIL_W_S_MM = 1059, 1075 CEIL_W_S_MMR6 = 1060, 1076 CEQI_B = 1061, 1077 CEQI_D = 1062, 1078 CEQI_H = 1063, 1079 CEQI_W = 1064, 1080 CEQ_B = 1065, 1081 CEQ_D = 1066, 1082 CEQ_H = 1067, 1083 CEQ_W = 1068, 1084 CFC1 = 1069, 1085 CFC1_MM = 1070, 1086 CFC2_MM = 1071, 1087 CFCMSA = 1072, 1088 CINS = 1073, 1089 CINS32 = 1074, 1090 CINS64_32 = 1075, 1091 CINS_i32 = 1076, 1092 CLASS_D = 1077, 1093 CLASS_D_MMR6 = 1078, 1094 CLASS_S = 1079, 1095 CLASS_S_MMR6 = 1080, 1096 CLEI_S_B = 1081, 1097 CLEI_S_D = 1082, 1098 CLEI_S_H = 1083, 1099 CLEI_S_W = 1084, 1100 CLEI_U_B = 1085, 1101 CLEI_U_D = 1086, 1102 CLEI_U_H = 1087, 1103 CLEI_U_W = 1088, 1104 CLE_S_B = 1089, 1105 CLE_S_D = 1090, 1106 CLE_S_H = 1091, 1107 CLE_S_W = 1092, 1108 CLE_U_B = 1093, 1109 CLE_U_D = 1094, 1110 CLE_U_H = 1095, 1111 CLE_U_W = 1096, 1112 CLO = 1097, 1113 CLO_MM = 1098, 1114 CLO_MMR6 = 1099, 1115 CLO_R6 = 1100, 1116 CLTI_S_B = 1101, 1117 CLTI_S_D = 1102, 1118 CLTI_S_H = 1103, 1119 CLTI_S_W = 1104, 1120 CLTI_U_B = 1105, 1121 CLTI_U_D = 1106, 1122 CLTI_U_H = 1107, 1123 CLTI_U_W = 1108, 1124 CLT_S_B = 1109, 1125 CLT_S_D = 1110, 1126 CLT_S_H = 1111, 1127 CLT_S_W = 1112, 1128 CLT_U_B = 1113, 1129 CLT_U_D = 1114, 1130 CLT_U_H = 1115, 1131 CLT_U_W = 1116, 1132 CLZ = 1117, 1133 CLZ_MM = 1118, 1134 CLZ_MMR6 = 1119, 1135 CLZ_R6 = 1120, 1136 CMPGDU_EQ_QB = 1121, 1137 CMPGDU_EQ_QB_MMR2 = 1122, 1138 CMPGDU_LE_QB = 1123, 1139 CMPGDU_LE_QB_MMR2 = 1124, 1140 CMPGDU_LT_QB = 1125, 1141 CMPGDU_LT_QB_MMR2 = 1126, 1142 CMPGU_EQ_QB = 1127, 1143 CMPGU_EQ_QB_MM = 1128, 1144 CMPGU_LE_QB = 1129, 1145 CMPGU_LE_QB_MM = 1130, 1146 CMPGU_LT_QB = 1131, 1147 CMPGU_LT_QB_MM = 1132, 1148 CMPU_EQ_QB = 1133, 1149 CMPU_EQ_QB_MM = 1134, 1150 CMPU_LE_QB = 1135, 1151 CMPU_LE_QB_MM = 1136, 1152 CMPU_LT_QB = 1137, 1153 CMPU_LT_QB_MM = 1138, 1154 CMP_AF_D_MMR6 = 1139, 1155 CMP_AF_S_MMR6 = 1140, 1156 CMP_EQ_D = 1141, 1157 CMP_EQ_D_MMR6 = 1142, 1158 CMP_EQ_PH = 1143, 1159 CMP_EQ_PH_MM = 1144, 1160 CMP_EQ_S = 1145, 1161 CMP_EQ_S_MMR6 = 1146, 1162 CMP_F_D = 1147, 1163 CMP_F_S = 1148, 1164 CMP_LE_D = 1149, 1165 CMP_LE_D_MMR6 = 1150, 1166 CMP_LE_PH = 1151, 1167 CMP_LE_PH_MM = 1152, 1168 CMP_LE_S = 1153, 1169 CMP_LE_S_MMR6 = 1154, 1170 CMP_LT_D = 1155, 1171 CMP_LT_D_MMR6 = 1156, 1172 CMP_LT_PH = 1157, 1173 CMP_LT_PH_MM = 1158, 1174 CMP_LT_S = 1159, 1175 CMP_LT_S_MMR6 = 1160, 1176 CMP_SAF_D = 1161, 1177 CMP_SAF_D_MMR6 = 1162, 1178 CMP_SAF_S = 1163, 1179 CMP_SAF_S_MMR6 = 1164, 1180 CMP_SEQ_D = 1165, 1181 CMP_SEQ_D_MMR6 = 1166, 1182 CMP_SEQ_S = 1167, 1183 CMP_SEQ_S_MMR6 = 1168, 1184 CMP_SLE_D = 1169, 1185 CMP_SLE_D_MMR6 = 1170, 1186 CMP_SLE_S = 1171, 1187 CMP_SLE_S_MMR6 = 1172, 1188 CMP_SLT_D = 1173, 1189 CMP_SLT_D_MMR6 = 1174, 1190 CMP_SLT_S = 1175, 1191 CMP_SLT_S_MMR6 = 1176, 1192 CMP_SUEQ_D = 1177, 1193 CMP_SUEQ_D_MMR6 = 1178, 1194 CMP_SUEQ_S = 1179, 1195 CMP_SUEQ_S_MMR6 = 1180, 1196 CMP_SULE_D = 1181, 1197 CMP_SULE_D_MMR6 = 1182, 1198 CMP_SULE_S = 1183, 1199 CMP_SULE_S_MMR6 = 1184, 1200 CMP_SULT_D = 1185, 1201 CMP_SULT_D_MMR6 = 1186, 1202 CMP_SULT_S = 1187, 1203 CMP_SULT_S_MMR6 = 1188, 1204 CMP_SUN_D = 1189, 1205 CMP_SUN_D_MMR6 = 1190, 1206 CMP_SUN_S = 1191, 1207 CMP_SUN_S_MMR6 = 1192, 1208 CMP_UEQ_D = 1193, 1209 CMP_UEQ_D_MMR6 = 1194, 1210 CMP_UEQ_S = 1195, 1211 CMP_UEQ_S_MMR6 = 1196, 1212 CMP_ULE_D = 1197, 1213 CMP_ULE_D_MMR6 = 1198, 1214 CMP_ULE_S = 1199, 1215 CMP_ULE_S_MMR6 = 1200, 1216 CMP_ULT_D = 1201, 1217 CMP_ULT_D_MMR6 = 1202, 1218 CMP_ULT_S = 1203, 1219 CMP_ULT_S_MMR6 = 1204, 1220 CMP_UN_D = 1205, 1221 CMP_UN_D_MMR6 = 1206, 1222 CMP_UN_S = 1207, 1223 CMP_UN_S_MMR6 = 1208, 1224 COPY_S_B = 1209, 1225 COPY_S_D = 1210, 1226 COPY_S_H = 1211, 1227 COPY_S_W = 1212, 1228 COPY_U_B = 1213, 1229 COPY_U_H = 1214, 1230 COPY_U_W = 1215, 1231 CRC32B = 1216, 1232 CRC32CB = 1217, 1233 CRC32CD = 1218, 1234 CRC32CH = 1219, 1235 CRC32CW = 1220, 1236 CRC32D = 1221, 1237 CRC32H = 1222, 1238 CRC32W = 1223, 1239 CTC1 = 1224, 1240 CTC1_MM = 1225, 1241 CTC2_MM = 1226, 1242 CTCMSA = 1227, 1243 CVT_D32_S = 1228, 1244 CVT_D32_S_MM = 1229, 1245 CVT_D32_W = 1230, 1246 CVT_D32_W_MM = 1231, 1247 CVT_D64_L = 1232, 1248 CVT_D64_S = 1233, 1249 CVT_D64_S_MM = 1234, 1250 CVT_D64_W = 1235, 1251 CVT_D64_W_MM = 1236, 1252 CVT_D_L_MMR6 = 1237, 1253 CVT_L_D64 = 1238, 1254 CVT_L_D64_MM = 1239, 1255 CVT_L_D_MMR6 = 1240, 1256 CVT_L_S = 1241, 1257 CVT_L_S_MM = 1242, 1258 CVT_L_S_MMR6 = 1243, 1259 CVT_PS_PW64 = 1244, 1260 CVT_PS_S64 = 1245, 1261 CVT_PW_PS64 = 1246, 1262 CVT_S_D32 = 1247, 1263 CVT_S_D32_MM = 1248, 1264 CVT_S_D64 = 1249, 1265 CVT_S_D64_MM = 1250, 1266 CVT_S_L = 1251, 1267 CVT_S_L_MMR6 = 1252, 1268 CVT_S_PL64 = 1253, 1269 CVT_S_PU64 = 1254, 1270 CVT_S_W = 1255, 1271 CVT_S_W_MM = 1256, 1272 CVT_S_W_MMR6 = 1257, 1273 CVT_W_D32 = 1258, 1274 CVT_W_D32_MM = 1259, 1275 CVT_W_D64 = 1260, 1276 CVT_W_D64_MM = 1261, 1277 CVT_W_S = 1262, 1278 CVT_W_S_MM = 1263, 1279 CVT_W_S_MMR6 = 1264, 1280 C_EQ_D32 = 1265, 1281 C_EQ_D32_MM = 1266, 1282 C_EQ_D64 = 1267, 1283 C_EQ_D64_MM = 1268, 1284 C_EQ_S = 1269, 1285 C_EQ_S_MM = 1270, 1286 C_F_D32 = 1271, 1287 C_F_D32_MM = 1272, 1288 C_F_D64 = 1273, 1289 C_F_D64_MM = 1274, 1290 C_F_S = 1275, 1291 C_F_S_MM = 1276, 1292 C_LE_D32 = 1277, 1293 C_LE_D32_MM = 1278, 1294 C_LE_D64 = 1279, 1295 C_LE_D64_MM = 1280, 1296 C_LE_S = 1281, 1297 C_LE_S_MM = 1282, 1298 C_LT_D32 = 1283, 1299 C_LT_D32_MM = 1284, 1300 C_LT_D64 = 1285, 1301 C_LT_D64_MM = 1286, 1302 C_LT_S = 1287, 1303 C_LT_S_MM = 1288, 1304 C_NGE_D32 = 1289, 1305 C_NGE_D32_MM = 1290, 1306 C_NGE_D64 = 1291, 1307 C_NGE_D64_MM = 1292, 1308 C_NGE_S = 1293, 1309 C_NGE_S_MM = 1294, 1310 C_NGLE_D32 = 1295, 1311 C_NGLE_D32_MM = 1296, 1312 C_NGLE_D64 = 1297, 1313 C_NGLE_D64_MM = 1298, 1314 C_NGLE_S = 1299, 1315 C_NGLE_S_MM = 1300, 1316 C_NGL_D32 = 1301, 1317 C_NGL_D32_MM = 1302, 1318 C_NGL_D64 = 1303, 1319 C_NGL_D64_MM = 1304, 1320 C_NGL_S = 1305, 1321 C_NGL_S_MM = 1306, 1322 C_NGT_D32 = 1307, 1323 C_NGT_D32_MM = 1308, 1324 C_NGT_D64 = 1309, 1325 C_NGT_D64_MM = 1310, 1326 C_NGT_S = 1311, 1327 C_NGT_S_MM = 1312, 1328 C_OLE_D32 = 1313, 1329 C_OLE_D32_MM = 1314, 1330 C_OLE_D64 = 1315, 1331 C_OLE_D64_MM = 1316, 1332 C_OLE_S = 1317, 1333 C_OLE_S_MM = 1318, 1334 C_OLT_D32 = 1319, 1335 C_OLT_D32_MM = 1320, 1336 C_OLT_D64 = 1321, 1337 C_OLT_D64_MM = 1322, 1338 C_OLT_S = 1323, 1339 C_OLT_S_MM = 1324, 1340 C_SEQ_D32 = 1325, 1341 C_SEQ_D32_MM = 1326, 1342 C_SEQ_D64 = 1327, 1343 C_SEQ_D64_MM = 1328, 1344 C_SEQ_S = 1329, 1345 C_SEQ_S_MM = 1330, 1346 C_SF_D32 = 1331, 1347 C_SF_D32_MM = 1332, 1348 C_SF_D64 = 1333, 1349 C_SF_D64_MM = 1334, 1350 C_SF_S = 1335, 1351 C_SF_S_MM = 1336, 1352 C_UEQ_D32 = 1337, 1353 C_UEQ_D32_MM = 1338, 1354 C_UEQ_D64 = 1339, 1355 C_UEQ_D64_MM = 1340, 1356 C_UEQ_S = 1341, 1357 C_UEQ_S_MM = 1342, 1358 C_ULE_D32 = 1343, 1359 C_ULE_D32_MM = 1344, 1360 C_ULE_D64 = 1345, 1361 C_ULE_D64_MM = 1346, 1362 C_ULE_S = 1347, 1363 C_ULE_S_MM = 1348, 1364 C_ULT_D32 = 1349, 1365 C_ULT_D32_MM = 1350, 1366 C_ULT_D64 = 1351, 1367 C_ULT_D64_MM = 1352, 1368 C_ULT_S = 1353, 1369 C_ULT_S_MM = 1354, 1370 C_UN_D32 = 1355, 1371 C_UN_D32_MM = 1356, 1372 C_UN_D64 = 1357, 1373 C_UN_D64_MM = 1358, 1374 C_UN_S = 1359, 1375 C_UN_S_MM = 1360, 1376 CmpRxRy16 = 1361, 1377 CmpiRxImm16 = 1362, 1378 CmpiRxImmX16 = 1363, 1379 DADD = 1364, 1380 DADDi = 1365, 1381 DADDiu = 1366, 1382 DADDu = 1367, 1383 DAHI = 1368, 1384 DALIGN = 1369, 1385 DATI = 1370, 1386 DAUI = 1371, 1387 DBITSWAP = 1372, 1388 DCLO = 1373, 1389 DCLO_R6 = 1374, 1390 DCLZ = 1375, 1391 DCLZ_R6 = 1376, 1392 DDIV = 1377, 1393 DDIVU = 1378, 1394 DERET = 1379, 1395 DERET_MM = 1380, 1396 DERET_MMR6 = 1381, 1397 DEXT = 1382, 1398 DEXT64_32 = 1383, 1399 DEXTM = 1384, 1400 DEXTU = 1385, 1401 DI = 1386, 1402 DINS = 1387, 1403 DINSM = 1388, 1404 DINSU = 1389, 1405 DIV = 1390, 1406 DIVU = 1391, 1407 DIVU_MMR6 = 1392, 1408 DIV_MMR6 = 1393, 1409 DIV_S_B = 1394, 1410 DIV_S_D = 1395, 1411 DIV_S_H = 1396, 1412 DIV_S_W = 1397, 1413 DIV_U_B = 1398, 1414 DIV_U_D = 1399, 1415 DIV_U_H = 1400, 1416 DIV_U_W = 1401, 1417 DI_MM = 1402, 1418 DI_MMR6 = 1403, 1419 DLSA = 1404, 1420 DLSA_R6 = 1405, 1421 DMFC0 = 1406, 1422 DMFC1 = 1407, 1423 DMFC2 = 1408, 1424 DMFC2_OCTEON = 1409, 1425 DMFGC0 = 1410, 1426 DMOD = 1411, 1427 DMODU = 1412, 1428 DMT = 1413, 1429 DMTC0 = 1414, 1430 DMTC1 = 1415, 1431 DMTC2 = 1416, 1432 DMTC2_OCTEON = 1417, 1433 DMTGC0 = 1418, 1434 DMUH = 1419, 1435 DMUHU = 1420, 1436 DMUL = 1421, 1437 DMULT = 1422, 1438 DMULTu = 1423, 1439 DMULU = 1424, 1440 DMUL_R6 = 1425, 1441 DOTP_S_D = 1426, 1442 DOTP_S_H = 1427, 1443 DOTP_S_W = 1428, 1444 DOTP_U_D = 1429, 1445 DOTP_U_H = 1430, 1446 DOTP_U_W = 1431, 1447 DPADD_S_D = 1432, 1448 DPADD_S_H = 1433, 1449 DPADD_S_W = 1434, 1450 DPADD_U_D = 1435, 1451 DPADD_U_H = 1436, 1452 DPADD_U_W = 1437, 1453 DPAQX_SA_W_PH = 1438, 1454 DPAQX_SA_W_PH_MMR2 = 1439, 1455 DPAQX_S_W_PH = 1440, 1456 DPAQX_S_W_PH_MMR2 = 1441, 1457 DPAQ_SA_L_W = 1442, 1458 DPAQ_SA_L_W_MM = 1443, 1459 DPAQ_S_W_PH = 1444, 1460 DPAQ_S_W_PH_MM = 1445, 1461 DPAU_H_QBL = 1446, 1462 DPAU_H_QBL_MM = 1447, 1463 DPAU_H_QBR = 1448, 1464 DPAU_H_QBR_MM = 1449, 1465 DPAX_W_PH = 1450, 1466 DPAX_W_PH_MMR2 = 1451, 1467 DPA_W_PH = 1452, 1468 DPA_W_PH_MMR2 = 1453, 1469 DPOP = 1454, 1470 DPSQX_SA_W_PH = 1455, 1471 DPSQX_SA_W_PH_MMR2 = 1456, 1472 DPSQX_S_W_PH = 1457, 1473 DPSQX_S_W_PH_MMR2 = 1458, 1474 DPSQ_SA_L_W = 1459, 1475 DPSQ_SA_L_W_MM = 1460, 1476 DPSQ_S_W_PH = 1461, 1477 DPSQ_S_W_PH_MM = 1462, 1478 DPSUB_S_D = 1463, 1479 DPSUB_S_H = 1464, 1480 DPSUB_S_W = 1465, 1481 DPSUB_U_D = 1466, 1482 DPSUB_U_H = 1467, 1483 DPSUB_U_W = 1468, 1484 DPSU_H_QBL = 1469, 1485 DPSU_H_QBL_MM = 1470, 1486 DPSU_H_QBR = 1471, 1487 DPSU_H_QBR_MM = 1472, 1488 DPSX_W_PH = 1473, 1489 DPSX_W_PH_MMR2 = 1474, 1490 DPS_W_PH = 1475, 1491 DPS_W_PH_MMR2 = 1476, 1492 DROTR = 1477, 1493 DROTR32 = 1478, 1494 DROTRV = 1479, 1495 DSBH = 1480, 1496 DSDIV = 1481, 1497 DSHD = 1482, 1498 DSLL = 1483, 1499 DSLL32 = 1484, 1500 DSLL64_32 = 1485, 1501 DSLLV = 1486, 1502 DSRA = 1487, 1503 DSRA32 = 1488, 1504 DSRAV = 1489, 1505 DSRL = 1490, 1506 DSRL32 = 1491, 1507 DSRLV = 1492, 1508 DSUB = 1493, 1509 DSUBu = 1494, 1510 DUDIV = 1495, 1511 DVP = 1496, 1512 DVPE = 1497, 1513 DVP_MMR6 = 1498, 1514 DivRxRy16 = 1499, 1515 DivuRxRy16 = 1500, 1516 EHB = 1501, 1517 EHB_MM = 1502, 1518 EHB_MMR6 = 1503, 1519 EI = 1504, 1520 EI_MM = 1505, 1521 EI_MMR6 = 1506, 1522 EMT = 1507, 1523 ERET = 1508, 1524 ERETNC = 1509, 1525 ERETNC_MMR6 = 1510, 1526 ERET_MM = 1511, 1527 ERET_MMR6 = 1512, 1528 EVP = 1513, 1529 EVPE = 1514, 1530 EVP_MMR6 = 1515, 1531 EXT = 1516, 1532 EXTP = 1517, 1533 EXTPDP = 1518, 1534 EXTPDPV = 1519, 1535 EXTPDPV_MM = 1520, 1536 EXTPDP_MM = 1521, 1537 EXTPV = 1522, 1538 EXTPV_MM = 1523, 1539 EXTP_MM = 1524, 1540 EXTRV_RS_W = 1525, 1541 EXTRV_RS_W_MM = 1526, 1542 EXTRV_R_W = 1527, 1543 EXTRV_R_W_MM = 1528, 1544 EXTRV_S_H = 1529, 1545 EXTRV_S_H_MM = 1530, 1546 EXTRV_W = 1531, 1547 EXTRV_W_MM = 1532, 1548 EXTR_RS_W = 1533, 1549 EXTR_RS_W_MM = 1534, 1550 EXTR_R_W = 1535, 1551 EXTR_R_W_MM = 1536, 1552 EXTR_S_H = 1537, 1553 EXTR_S_H_MM = 1538, 1554 EXTR_W = 1539, 1555 EXTR_W_MM = 1540, 1556 EXTS = 1541, 1557 EXTS32 = 1542, 1558 EXT_MM = 1543, 1559 EXT_MMR6 = 1544, 1560 FABS_D32 = 1545, 1561 FABS_D32_MM = 1546, 1562 FABS_D64 = 1547, 1563 FABS_D64_MM = 1548, 1564 FABS_S = 1549, 1565 FABS_S_MM = 1550, 1566 FADD_D = 1551, 1567 FADD_D32 = 1552, 1568 FADD_D32_MM = 1553, 1569 FADD_D64 = 1554, 1570 FADD_D64_MM = 1555, 1571 FADD_PS64 = 1556, 1572 FADD_S = 1557, 1573 FADD_S_MM = 1558, 1574 FADD_S_MMR6 = 1559, 1575 FADD_W = 1560, 1576 FCAF_D = 1561, 1577 FCAF_W = 1562, 1578 FCEQ_D = 1563, 1579 FCEQ_W = 1564, 1580 FCLASS_D = 1565, 1581 FCLASS_W = 1566, 1582 FCLE_D = 1567, 1583 FCLE_W = 1568, 1584 FCLT_D = 1569, 1585 FCLT_W = 1570, 1586 FCMP_D32 = 1571, 1587 FCMP_D32_MM = 1572, 1588 FCMP_D64 = 1573, 1589 FCMP_S32 = 1574, 1590 FCMP_S32_MM = 1575, 1591 FCNE_D = 1576, 1592 FCNE_W = 1577, 1593 FCOR_D = 1578, 1594 FCOR_W = 1579, 1595 FCUEQ_D = 1580, 1596 FCUEQ_W = 1581, 1597 FCULE_D = 1582, 1598 FCULE_W = 1583, 1599 FCULT_D = 1584, 1600 FCULT_W = 1585, 1601 FCUNE_D = 1586, 1602 FCUNE_W = 1587, 1603 FCUN_D = 1588, 1604 FCUN_W = 1589, 1605 FDIV_D = 1590, 1606 FDIV_D32 = 1591, 1607 FDIV_D32_MM = 1592, 1608 FDIV_D64 = 1593, 1609 FDIV_D64_MM = 1594, 1610 FDIV_S = 1595, 1611 FDIV_S_MM = 1596, 1612 FDIV_S_MMR6 = 1597, 1613 FDIV_W = 1598, 1614 FEXDO_H = 1599, 1615 FEXDO_W = 1600, 1616 FEXP2_D = 1601, 1617 FEXP2_W = 1602, 1618 FEXUPL_D = 1603, 1619 FEXUPL_W = 1604, 1620 FEXUPR_D = 1605, 1621 FEXUPR_W = 1606, 1622 FFINT_S_D = 1607, 1623 FFINT_S_W = 1608, 1624 FFINT_U_D = 1609, 1625 FFINT_U_W = 1610, 1626 FFQL_D = 1611, 1627 FFQL_W = 1612, 1628 FFQR_D = 1613, 1629 FFQR_W = 1614, 1630 FILL_B = 1615, 1631 FILL_D = 1616, 1632 FILL_H = 1617, 1633 FILL_W = 1618, 1634 FLOG2_D = 1619, 1635 FLOG2_W = 1620, 1636 FLOOR_L_D64 = 1621, 1637 FLOOR_L_D_MMR6 = 1622, 1638 FLOOR_L_S = 1623, 1639 FLOOR_L_S_MMR6 = 1624, 1640 FLOOR_W_D32 = 1625, 1641 FLOOR_W_D64 = 1626, 1642 FLOOR_W_D_MMR6 = 1627, 1643 FLOOR_W_MM = 1628, 1644 FLOOR_W_S = 1629, 1645 FLOOR_W_S_MM = 1630, 1646 FLOOR_W_S_MMR6 = 1631, 1647 FMADD_D = 1632, 1648 FMADD_W = 1633, 1649 FMAX_A_D = 1634, 1650 FMAX_A_W = 1635, 1651 FMAX_D = 1636, 1652 FMAX_W = 1637, 1653 FMIN_A_D = 1638, 1654 FMIN_A_W = 1639, 1655 FMIN_D = 1640, 1656 FMIN_W = 1641, 1657 FMOV_D32 = 1642, 1658 FMOV_D32_MM = 1643, 1659 FMOV_D64 = 1644, 1660 FMOV_D64_MM = 1645, 1661 FMOV_D_MMR6 = 1646, 1662 FMOV_S = 1647, 1663 FMOV_S_MM = 1648, 1664 FMOV_S_MMR6 = 1649, 1665 FMSUB_D = 1650, 1666 FMSUB_W = 1651, 1667 FMUL_D = 1652, 1668 FMUL_D32 = 1653, 1669 FMUL_D32_MM = 1654, 1670 FMUL_D64 = 1655, 1671 FMUL_D64_MM = 1656, 1672 FMUL_PS64 = 1657, 1673 FMUL_S = 1658, 1674 FMUL_S_MM = 1659, 1675 FMUL_S_MMR6 = 1660, 1676 FMUL_W = 1661, 1677 FNEG_D32 = 1662, 1678 FNEG_D32_MM = 1663, 1679 FNEG_D64 = 1664, 1680 FNEG_D64_MM = 1665, 1681 FNEG_S = 1666, 1682 FNEG_S_MM = 1667, 1683 FNEG_S_MMR6 = 1668, 1684 FORK = 1669, 1685 FRCP_D = 1670, 1686 FRCP_W = 1671, 1687 FRINT_D = 1672, 1688 FRINT_W = 1673, 1689 FRSQRT_D = 1674, 1690 FRSQRT_W = 1675, 1691 FSAF_D = 1676, 1692 FSAF_W = 1677, 1693 FSEQ_D = 1678, 1694 FSEQ_W = 1679, 1695 FSLE_D = 1680, 1696 FSLE_W = 1681, 1697 FSLT_D = 1682, 1698 FSLT_W = 1683, 1699 FSNE_D = 1684, 1700 FSNE_W = 1685, 1701 FSOR_D = 1686, 1702 FSOR_W = 1687, 1703 FSQRT_D = 1688, 1704 FSQRT_D32 = 1689, 1705 FSQRT_D32_MM = 1690, 1706 FSQRT_D64 = 1691, 1707 FSQRT_D64_MM = 1692, 1708 FSQRT_S = 1693, 1709 FSQRT_S_MM = 1694, 1710 FSQRT_W = 1695, 1711 FSUB_D = 1696, 1712 FSUB_D32 = 1697, 1713 FSUB_D32_MM = 1698, 1714 FSUB_D64 = 1699, 1715 FSUB_D64_MM = 1700, 1716 FSUB_PS64 = 1701, 1717 FSUB_S = 1702, 1718 FSUB_S_MM = 1703, 1719 FSUB_S_MMR6 = 1704, 1720 FSUB_W = 1705, 1721 FSUEQ_D = 1706, 1722 FSUEQ_W = 1707, 1723 FSULE_D = 1708, 1724 FSULE_W = 1709, 1725 FSULT_D = 1710, 1726 FSULT_W = 1711, 1727 FSUNE_D = 1712, 1728 FSUNE_W = 1713, 1729 FSUN_D = 1714, 1730 FSUN_W = 1715, 1731 FTINT_S_D = 1716, 1732 FTINT_S_W = 1717, 1733 FTINT_U_D = 1718, 1734 FTINT_U_W = 1719, 1735 FTQ_H = 1720, 1736 FTQ_W = 1721, 1737 FTRUNC_S_D = 1722, 1738 FTRUNC_S_W = 1723, 1739 FTRUNC_U_D = 1724, 1740 FTRUNC_U_W = 1725, 1741 GINVI = 1726, 1742 GINVI_MMR6 = 1727, 1743 GINVT = 1728, 1744 GINVT_MMR6 = 1729, 1745 HADD_S_D = 1730, 1746 HADD_S_H = 1731, 1747 HADD_S_W = 1732, 1748 HADD_U_D = 1733, 1749 HADD_U_H = 1734, 1750 HADD_U_W = 1735, 1751 HSUB_S_D = 1736, 1752 HSUB_S_H = 1737, 1753 HSUB_S_W = 1738, 1754 HSUB_U_D = 1739, 1755 HSUB_U_H = 1740, 1756 HSUB_U_W = 1741, 1757 HYPCALL = 1742, 1758 HYPCALL_MM = 1743, 1759 ILVEV_B = 1744, 1760 ILVEV_D = 1745, 1761 ILVEV_H = 1746, 1762 ILVEV_W = 1747, 1763 ILVL_B = 1748, 1764 ILVL_D = 1749, 1765 ILVL_H = 1750, 1766 ILVL_W = 1751, 1767 ILVOD_B = 1752, 1768 ILVOD_D = 1753, 1769 ILVOD_H = 1754, 1770 ILVOD_W = 1755, 1771 ILVR_B = 1756, 1772 ILVR_D = 1757, 1773 ILVR_H = 1758, 1774 ILVR_W = 1759, 1775 INS = 1760, 1776 INSERT_B = 1761, 1777 INSERT_D = 1762, 1778 INSERT_H = 1763, 1779 INSERT_W = 1764, 1780 INSV = 1765, 1781 INSVE_B = 1766, 1782 INSVE_D = 1767, 1783 INSVE_H = 1768, 1784 INSVE_W = 1769, 1785 INSV_MM = 1770, 1786 INS_MM = 1771, 1787 INS_MMR6 = 1772, 1788 J = 1773, 1789 JAL = 1774, 1790 JALR = 1775, 1791 JALR16_MM = 1776, 1792 JALR64 = 1777, 1793 JALRC16_MMR6 = 1778, 1794 JALRC_HB_MMR6 = 1779, 1795 JALRC_MMR6 = 1780, 1796 JALRS16_MM = 1781, 1797 JALRS_MM = 1782, 1798 JALR_HB = 1783, 1799 JALR_HB64 = 1784, 1800 JALR_MM = 1785, 1801 JALS_MM = 1786, 1802 JALX = 1787, 1803 JALX_MM = 1788, 1804 JAL_MM = 1789, 1805 JIALC = 1790, 1806 JIALC64 = 1791, 1807 JIALC_MMR6 = 1792, 1808 JIC = 1793, 1809 JIC64 = 1794, 1810 JIC_MMR6 = 1795, 1811 JR = 1796, 1812 JR16_MM = 1797, 1813 JR64 = 1798, 1814 JRADDIUSP = 1799, 1815 JRC16_MM = 1800, 1816 JRC16_MMR6 = 1801, 1817 JRCADDIUSP_MMR6 = 1802, 1818 JR_HB = 1803, 1819 JR_HB64 = 1804, 1820 JR_HB64_R6 = 1805, 1821 JR_HB_R6 = 1806, 1822 JR_MM = 1807, 1823 J_MM = 1808, 1824 Jal16 = 1809, 1825 JalB16 = 1810, 1826 JrRa16 = 1811, 1827 JrcRa16 = 1812, 1828 JrcRx16 = 1813, 1829 JumpLinkReg16 = 1814, 1830 LB = 1815, 1831 LB64 = 1816, 1832 LBE = 1817, 1833 LBE_MM = 1818, 1834 LBU16_MM = 1819, 1835 LBUX = 1820, 1836 LBUX_MM = 1821, 1837 LBU_MMR6 = 1822, 1838 LB_MM = 1823, 1839 LB_MMR6 = 1824, 1840 LBu = 1825, 1841 LBu64 = 1826, 1842 LBuE = 1827, 1843 LBuE_MM = 1828, 1844 LBu_MM = 1829, 1845 LD = 1830, 1846 LDC1 = 1831, 1847 LDC164 = 1832, 1848 LDC1_D64_MMR6 = 1833, 1849 LDC1_MM_D32 = 1834, 1850 LDC1_MM_D64 = 1835, 1851 LDC2 = 1836, 1852 LDC2_MMR6 = 1837, 1853 LDC2_R6 = 1838, 1854 LDC3 = 1839, 1855 LDI_B = 1840, 1856 LDI_D = 1841, 1857 LDI_H = 1842, 1858 LDI_W = 1843, 1859 LDL = 1844, 1860 LDPC = 1845, 1861 LDR = 1846, 1862 LDXC1 = 1847, 1863 LDXC164 = 1848, 1864 LD_B = 1849, 1865 LD_D = 1850, 1866 LD_H = 1851, 1867 LD_W = 1852, 1868 LEA_ADDiu = 1853, 1869 LEA_ADDiu64 = 1854, 1870 LEA_ADDiu_MM = 1855, 1871 LH = 1856, 1872 LH64 = 1857, 1873 LHE = 1858, 1874 LHE_MM = 1859, 1875 LHU16_MM = 1860, 1876 LHX = 1861, 1877 LHX_MM = 1862, 1878 LH_MM = 1863, 1879 LHu = 1864, 1880 LHu64 = 1865, 1881 LHuE = 1866, 1882 LHuE_MM = 1867, 1883 LHu_MM = 1868, 1884 LI16_MM = 1869, 1885 LI16_MMR6 = 1870, 1886 LL = 1871, 1887 LL64 = 1872, 1888 LL64_R6 = 1873, 1889 LLD = 1874, 1890 LLD_R6 = 1875, 1891 LLE = 1876, 1892 LLE_MM = 1877, 1893 LL_MM = 1878, 1894 LL_MMR6 = 1879, 1895 LL_R6 = 1880, 1896 LSA = 1881, 1897 LSA_MMR6 = 1882, 1898 LSA_R6 = 1883, 1899 LUI_MMR6 = 1884, 1900 LUXC1 = 1885, 1901 LUXC164 = 1886, 1902 LUXC1_MM = 1887, 1903 LUi = 1888, 1904 LUi64 = 1889, 1905 LUi_MM = 1890, 1906 LW = 1891, 1907 LW16_MM = 1892, 1908 LW64 = 1893, 1909 LWC1 = 1894, 1910 LWC1_MM = 1895, 1911 LWC2 = 1896, 1912 LWC2_MMR6 = 1897, 1913 LWC2_R6 = 1898, 1914 LWC3 = 1899, 1915 LWDSP = 1900, 1916 LWDSP_MM = 1901, 1917 LWE = 1902, 1918 LWE_MM = 1903, 1919 LWGP_MM = 1904, 1920 LWL = 1905, 1921 LWL64 = 1906, 1922 LWLE = 1907, 1923 LWLE_MM = 1908, 1924 LWL_MM = 1909, 1925 LWM16_MM = 1910, 1926 LWM16_MMR6 = 1911, 1927 LWM32_MM = 1912, 1928 LWPC = 1913, 1929 LWPC_MMR6 = 1914, 1930 LWP_MM = 1915, 1931 LWR = 1916, 1932 LWR64 = 1917, 1933 LWRE = 1918, 1934 LWRE_MM = 1919, 1935 LWR_MM = 1920, 1936 LWSP_MM = 1921, 1937 LWUPC = 1922, 1938 LWU_MM = 1923, 1939 LWX = 1924, 1940 LWXC1 = 1925, 1941 LWXC1_MM = 1926, 1942 LWXS_MM = 1927, 1943 LWX_MM = 1928, 1944 LW_MM = 1929, 1945 LW_MMR6 = 1930, 1946 LWu = 1931, 1947 LbRxRyOffMemX16 = 1932, 1948 LbuRxRyOffMemX16 = 1933, 1949 LhRxRyOffMemX16 = 1934, 1950 LhuRxRyOffMemX16 = 1935, 1951 LiRxImm16 = 1936, 1952 LiRxImmAlignX16 = 1937, 1953 LiRxImmX16 = 1938, 1954 LwRxPcTcp16 = 1939, 1955 LwRxPcTcpX16 = 1940, 1956 LwRxRyOffMemX16 = 1941, 1957 LwRxSpImmX16 = 1942, 1958 MADD = 1943, 1959 MADDF_D = 1944, 1960 MADDF_D_MMR6 = 1945, 1961 MADDF_S = 1946, 1962 MADDF_S_MMR6 = 1947, 1963 MADDR_Q_H = 1948, 1964 MADDR_Q_W = 1949, 1965 MADDU = 1950, 1966 MADDU_DSP = 1951, 1967 MADDU_DSP_MM = 1952, 1968 MADDU_MM = 1953, 1969 MADDV_B = 1954, 1970 MADDV_D = 1955, 1971 MADDV_H = 1956, 1972 MADDV_W = 1957, 1973 MADD_D32 = 1958, 1974 MADD_D32_MM = 1959, 1975 MADD_D64 = 1960, 1976 MADD_DSP = 1961, 1977 MADD_DSP_MM = 1962, 1978 MADD_MM = 1963, 1979 MADD_Q_H = 1964, 1980 MADD_Q_W = 1965, 1981 MADD_S = 1966, 1982 MADD_S_MM = 1967, 1983 MAQ_SA_W_PHL = 1968, 1984 MAQ_SA_W_PHL_MM = 1969, 1985 MAQ_SA_W_PHR = 1970, 1986 MAQ_SA_W_PHR_MM = 1971, 1987 MAQ_S_W_PHL = 1972, 1988 MAQ_S_W_PHL_MM = 1973, 1989 MAQ_S_W_PHR = 1974, 1990 MAQ_S_W_PHR_MM = 1975, 1991 MAXA_D = 1976, 1992 MAXA_D_MMR6 = 1977, 1993 MAXA_S = 1978, 1994 MAXA_S_MMR6 = 1979, 1995 MAXI_S_B = 1980, 1996 MAXI_S_D = 1981, 1997 MAXI_S_H = 1982, 1998 MAXI_S_W = 1983, 1999 MAXI_U_B = 1984, 2000 MAXI_U_D = 1985, 2001 MAXI_U_H = 1986, 2002 MAXI_U_W = 1987, 2003 MAX_A_B = 1988, 2004 MAX_A_D = 1989, 2005 MAX_A_H = 1990, 2006 MAX_A_W = 1991, 2007 MAX_D = 1992, 2008 MAX_D_MMR6 = 1993, 2009 MAX_S = 1994, 2010 MAX_S_B = 1995, 2011 MAX_S_D = 1996, 2012 MAX_S_H = 1997, 2013 MAX_S_MMR6 = 1998, 2014 MAX_S_W = 1999, 2015 MAX_U_B = 2000, 2016 MAX_U_D = 2001, 2017 MAX_U_H = 2002, 2018 MAX_U_W = 2003, 2019 MFC0 = 2004, 2020 MFC0_MMR6 = 2005, 2021 MFC1 = 2006, 2022 MFC1_D64 = 2007, 2023 MFC1_MM = 2008, 2024 MFC1_MMR6 = 2009, 2025 MFC2 = 2010, 2026 MFC2_MMR6 = 2011, 2027 MFGC0 = 2012, 2028 MFGC0_MM = 2013, 2029 MFHC0_MMR6 = 2014, 2030 MFHC1_D32 = 2015, 2031 MFHC1_D32_MM = 2016, 2032 MFHC1_D64 = 2017, 2033 MFHC1_D64_MM = 2018, 2034 MFHC2_MMR6 = 2019, 2035 MFHGC0 = 2020, 2036 MFHGC0_MM = 2021, 2037 MFHI = 2022, 2038 MFHI16_MM = 2023, 2039 MFHI64 = 2024, 2040 MFHI_DSP = 2025, 2041 MFHI_DSP_MM = 2026, 2042 MFHI_MM = 2027, 2043 MFLO = 2028, 2044 MFLO16_MM = 2029, 2045 MFLO64 = 2030, 2046 MFLO_DSP = 2031, 2047 MFLO_DSP_MM = 2032, 2048 MFLO_MM = 2033, 2049 MFTR = 2034, 2050 MINA_D = 2035, 2051 MINA_D_MMR6 = 2036, 2052 MINA_S = 2037, 2053 MINA_S_MMR6 = 2038, 2054 MINI_S_B = 2039, 2055 MINI_S_D = 2040, 2056 MINI_S_H = 2041, 2057 MINI_S_W = 2042, 2058 MINI_U_B = 2043, 2059 MINI_U_D = 2044, 2060 MINI_U_H = 2045, 2061 MINI_U_W = 2046, 2062 MIN_A_B = 2047, 2063 MIN_A_D = 2048, 2064 MIN_A_H = 2049, 2065 MIN_A_W = 2050, 2066 MIN_D = 2051, 2067 MIN_D_MMR6 = 2052, 2068 MIN_S = 2053, 2069 MIN_S_B = 2054, 2070 MIN_S_D = 2055, 2071 MIN_S_H = 2056, 2072 MIN_S_MMR6 = 2057, 2073 MIN_S_W = 2058, 2074 MIN_U_B = 2059, 2075 MIN_U_D = 2060, 2076 MIN_U_H = 2061, 2077 MIN_U_W = 2062, 2078 MOD = 2063, 2079 MODSUB = 2064, 2080 MODSUB_MM = 2065, 2081 MODU = 2066, 2082 MODU_MMR6 = 2067, 2083 MOD_MMR6 = 2068, 2084 MOD_S_B = 2069, 2085 MOD_S_D = 2070, 2086 MOD_S_H = 2071, 2087 MOD_S_W = 2072, 2088 MOD_U_B = 2073, 2089 MOD_U_D = 2074, 2090 MOD_U_H = 2075, 2091 MOD_U_W = 2076, 2092 MOVE16_MM = 2077, 2093 MOVE16_MMR6 = 2078, 2094 MOVEP_MM = 2079, 2095 MOVEP_MMR6 = 2080, 2096 MOVE_V = 2081, 2097 MOVF_D32 = 2082, 2098 MOVF_D32_MM = 2083, 2099 MOVF_D64 = 2084, 2100 MOVF_I = 2085, 2101 MOVF_I64 = 2086, 2102 MOVF_I_MM = 2087, 2103 MOVF_S = 2088, 2104 MOVF_S_MM = 2089, 2105 MOVN_I64_D64 = 2090, 2106 MOVN_I64_I = 2091, 2107 MOVN_I64_I64 = 2092, 2108 MOVN_I64_S = 2093, 2109 MOVN_I_D32 = 2094, 2110 MOVN_I_D32_MM = 2095, 2111 MOVN_I_D64 = 2096, 2112 MOVN_I_I = 2097, 2113 MOVN_I_I64 = 2098, 2114 MOVN_I_MM = 2099, 2115 MOVN_I_S = 2100, 2116 MOVN_I_S_MM = 2101, 2117 MOVT_D32 = 2102, 2118 MOVT_D32_MM = 2103, 2119 MOVT_D64 = 2104, 2120 MOVT_I = 2105, 2121 MOVT_I64 = 2106, 2122 MOVT_I_MM = 2107, 2123 MOVT_S = 2108, 2124 MOVT_S_MM = 2109, 2125 MOVZ_I64_D64 = 2110, 2126 MOVZ_I64_I = 2111, 2127 MOVZ_I64_I64 = 2112, 2128 MOVZ_I64_S = 2113, 2129 MOVZ_I_D32 = 2114, 2130 MOVZ_I_D32_MM = 2115, 2131 MOVZ_I_D64 = 2116, 2132 MOVZ_I_I = 2117, 2133 MOVZ_I_I64 = 2118, 2134 MOVZ_I_MM = 2119, 2135 MOVZ_I_S = 2120, 2136 MOVZ_I_S_MM = 2121, 2137 MSUB = 2122, 2138 MSUBF_D = 2123, 2139 MSUBF_D_MMR6 = 2124, 2140 MSUBF_S = 2125, 2141 MSUBF_S_MMR6 = 2126, 2142 MSUBR_Q_H = 2127, 2143 MSUBR_Q_W = 2128, 2144 MSUBU = 2129, 2145 MSUBU_DSP = 2130, 2146 MSUBU_DSP_MM = 2131, 2147 MSUBU_MM = 2132, 2148 MSUBV_B = 2133, 2149 MSUBV_D = 2134, 2150 MSUBV_H = 2135, 2151 MSUBV_W = 2136, 2152 MSUB_D32 = 2137, 2153 MSUB_D32_MM = 2138, 2154 MSUB_D64 = 2139, 2155 MSUB_DSP = 2140, 2156 MSUB_DSP_MM = 2141, 2157 MSUB_MM = 2142, 2158 MSUB_Q_H = 2143, 2159 MSUB_Q_W = 2144, 2160 MSUB_S = 2145, 2161 MSUB_S_MM = 2146, 2162 MTC0 = 2147, 2163 MTC0_MMR6 = 2148, 2164 MTC1 = 2149, 2165 MTC1_D64 = 2150, 2166 MTC1_D64_MM = 2151, 2167 MTC1_MM = 2152, 2168 MTC1_MMR6 = 2153, 2169 MTC2 = 2154, 2170 MTC2_MMR6 = 2155, 2171 MTGC0 = 2156, 2172 MTGC0_MM = 2157, 2173 MTHC0_MMR6 = 2158, 2174 MTHC1_D32 = 2159, 2175 MTHC1_D32_MM = 2160, 2176 MTHC1_D64 = 2161, 2177 MTHC1_D64_MM = 2162, 2178 MTHC2_MMR6 = 2163, 2179 MTHGC0 = 2164, 2180 MTHGC0_MM = 2165, 2181 MTHI = 2166, 2182 MTHI64 = 2167, 2183 MTHI_DSP = 2168, 2184 MTHI_DSP_MM = 2169, 2185 MTHI_MM = 2170, 2186 MTHLIP = 2171, 2187 MTHLIP_MM = 2172, 2188 MTLO = 2173, 2189 MTLO64 = 2174, 2190 MTLO_DSP = 2175, 2191 MTLO_DSP_MM = 2176, 2192 MTLO_MM = 2177, 2193 MTM0 = 2178, 2194 MTM1 = 2179, 2195 MTM2 = 2180, 2196 MTP0 = 2181, 2197 MTP1 = 2182, 2198 MTP2 = 2183, 2199 MTTR = 2184, 2200 MUH = 2185, 2201 MUHU = 2186, 2202 MUHU_MMR6 = 2187, 2203 MUH_MMR6 = 2188, 2204 MUL = 2189, 2205 MULEQ_S_W_PHL = 2190, 2206 MULEQ_S_W_PHL_MM = 2191, 2207 MULEQ_S_W_PHR = 2192, 2208 MULEQ_S_W_PHR_MM = 2193, 2209 MULEU_S_PH_QBL = 2194, 2210 MULEU_S_PH_QBL_MM = 2195, 2211 MULEU_S_PH_QBR = 2196, 2212 MULEU_S_PH_QBR_MM = 2197, 2213 MULQ_RS_PH = 2198, 2214 MULQ_RS_PH_MM = 2199, 2215 MULQ_RS_W = 2200, 2216 MULQ_RS_W_MMR2 = 2201, 2217 MULQ_S_PH = 2202, 2218 MULQ_S_PH_MMR2 = 2203, 2219 MULQ_S_W = 2204, 2220 MULQ_S_W_MMR2 = 2205, 2221 MULR_PS64 = 2206, 2222 MULR_Q_H = 2207, 2223 MULR_Q_W = 2208, 2224 MULSAQ_S_W_PH = 2209, 2225 MULSAQ_S_W_PH_MM = 2210, 2226 MULSA_W_PH = 2211, 2227 MULSA_W_PH_MMR2 = 2212, 2228 MULT = 2213, 2229 MULTU_DSP = 2214, 2230 MULTU_DSP_MM = 2215, 2231 MULT_DSP = 2216, 2232 MULT_DSP_MM = 2217, 2233 MULT_MM = 2218, 2234 MULTu = 2219, 2235 MULTu_MM = 2220, 2236 MULU = 2221, 2237 MULU_MMR6 = 2222, 2238 MULV_B = 2223, 2239 MULV_D = 2224, 2240 MULV_H = 2225, 2241 MULV_W = 2226, 2242 MUL_MM = 2227, 2243 MUL_MMR6 = 2228, 2244 MUL_PH = 2229, 2245 MUL_PH_MMR2 = 2230, 2246 MUL_Q_H = 2231, 2247 MUL_Q_W = 2232, 2248 MUL_R6 = 2233, 2249 MUL_S_PH = 2234, 2250 MUL_S_PH_MMR2 = 2235, 2251 Mfhi16 = 2236, 2252 Mflo16 = 2237, 2253 Move32R16 = 2238, 2254 MoveR3216 = 2239, 2255 NLOC_B = 2240, 2256 NLOC_D = 2241, 2257 NLOC_H = 2242, 2258 NLOC_W = 2243, 2259 NLZC_B = 2244, 2260 NLZC_D = 2245, 2261 NLZC_H = 2246, 2262 NLZC_W = 2247, 2263 NMADD_D32 = 2248, 2264 NMADD_D32_MM = 2249, 2265 NMADD_D64 = 2250, 2266 NMADD_S = 2251, 2267 NMADD_S_MM = 2252, 2268 NMSUB_D32 = 2253, 2269 NMSUB_D32_MM = 2254, 2270 NMSUB_D64 = 2255, 2271 NMSUB_S = 2256, 2272 NMSUB_S_MM = 2257, 2273 NOR = 2258, 2274 NOR64 = 2259, 2275 NORI_B = 2260, 2276 NOR_MM = 2261, 2277 NOR_MMR6 = 2262, 2278 NOR_V = 2263, 2279 NOT16_MM = 2264, 2280 NOT16_MMR6 = 2265, 2281 NegRxRy16 = 2266, 2282 NotRxRy16 = 2267, 2283 OR = 2268, 2284 OR16_MM = 2269, 2285 OR16_MMR6 = 2270, 2286 OR64 = 2271, 2287 ORI_B = 2272, 2288 ORI_MMR6 = 2273, 2289 OR_MM = 2274, 2290 OR_MMR6 = 2275, 2291 OR_V = 2276, 2292 ORi = 2277, 2293 ORi64 = 2278, 2294 ORi_MM = 2279, 2295 OrRxRxRy16 = 2280, 2296 PACKRL_PH = 2281, 2297 PACKRL_PH_MM = 2282, 2298 PAUSE = 2283, 2299 PAUSE_MM = 2284, 2300 PAUSE_MMR6 = 2285, 2301 PCKEV_B = 2286, 2302 PCKEV_D = 2287, 2303 PCKEV_H = 2288, 2304 PCKEV_W = 2289, 2305 PCKOD_B = 2290, 2306 PCKOD_D = 2291, 2307 PCKOD_H = 2292, 2308 PCKOD_W = 2293, 2309 PCNT_B = 2294, 2310 PCNT_D = 2295, 2311 PCNT_H = 2296, 2312 PCNT_W = 2297, 2313 PICK_PH = 2298, 2314 PICK_PH_MM = 2299, 2315 PICK_QB = 2300, 2316 PICK_QB_MM = 2301, 2317 PLL_PS64 = 2302, 2318 PLU_PS64 = 2303, 2319 POP = 2304, 2320 PRECEQU_PH_QBL = 2305, 2321 PRECEQU_PH_QBLA = 2306, 2322 PRECEQU_PH_QBLA_MM = 2307, 2323 PRECEQU_PH_QBL_MM = 2308, 2324 PRECEQU_PH_QBR = 2309, 2325 PRECEQU_PH_QBRA = 2310, 2326 PRECEQU_PH_QBRA_MM = 2311, 2327 PRECEQU_PH_QBR_MM = 2312, 2328 PRECEQ_W_PHL = 2313, 2329 PRECEQ_W_PHL_MM = 2314, 2330 PRECEQ_W_PHR = 2315, 2331 PRECEQ_W_PHR_MM = 2316, 2332 PRECEU_PH_QBL = 2317, 2333 PRECEU_PH_QBLA = 2318, 2334 PRECEU_PH_QBLA_MM = 2319, 2335 PRECEU_PH_QBL_MM = 2320, 2336 PRECEU_PH_QBR = 2321, 2337 PRECEU_PH_QBRA = 2322, 2338 PRECEU_PH_QBRA_MM = 2323, 2339 PRECEU_PH_QBR_MM = 2324, 2340 PRECRQU_S_QB_PH = 2325, 2341 PRECRQU_S_QB_PH_MM = 2326, 2342 PRECRQ_PH_W = 2327, 2343 PRECRQ_PH_W_MM = 2328, 2344 PRECRQ_QB_PH = 2329, 2345 PRECRQ_QB_PH_MM = 2330, 2346 PRECRQ_RS_PH_W = 2331, 2347 PRECRQ_RS_PH_W_MM = 2332, 2348 PRECR_QB_PH = 2333, 2349 PRECR_QB_PH_MMR2 = 2334, 2350 PRECR_SRA_PH_W = 2335, 2351 PRECR_SRA_PH_W_MMR2 = 2336, 2352 PRECR_SRA_R_PH_W = 2337, 2353 PRECR_SRA_R_PH_W_MMR2 = 2338, 2354 PREF = 2339, 2355 PREFE = 2340, 2356 PREFE_MM = 2341, 2357 PREFX_MM = 2342, 2358 PREF_MM = 2343, 2359 PREF_MMR6 = 2344, 2360 PREF_R6 = 2345, 2361 PREPEND = 2346, 2362 PREPEND_MMR2 = 2347, 2363 PUL_PS64 = 2348, 2364 PUU_PS64 = 2349, 2365 RADDU_W_QB = 2350, 2366 RADDU_W_QB_MM = 2351, 2367 RDDSP = 2352, 2368 RDDSP_MM = 2353, 2369 RDHWR = 2354, 2370 RDHWR64 = 2355, 2371 RDHWR_MM = 2356, 2372 RDHWR_MMR6 = 2357, 2373 RDPGPR_MMR6 = 2358, 2374 RECIP_D32 = 2359, 2375 RECIP_D32_MM = 2360, 2376 RECIP_D64 = 2361, 2377 RECIP_D64_MM = 2362, 2378 RECIP_S = 2363, 2379 RECIP_S_MM = 2364, 2380 REPLV_PH = 2365, 2381 REPLV_PH_MM = 2366, 2382 REPLV_QB = 2367, 2383 REPLV_QB_MM = 2368, 2384 REPL_PH = 2369, 2385 REPL_PH_MM = 2370, 2386 REPL_QB = 2371, 2387 REPL_QB_MM = 2372, 2388 RINT_D = 2373, 2389 RINT_D_MMR6 = 2374, 2390 RINT_S = 2375, 2391 RINT_S_MMR6 = 2376, 2392 ROTR = 2377, 2393 ROTRV = 2378, 2394 ROTRV_MM = 2379, 2395 ROTR_MM = 2380, 2396 ROUND_L_D64 = 2381, 2397 ROUND_L_D_MMR6 = 2382, 2398 ROUND_L_S = 2383, 2399 ROUND_L_S_MMR6 = 2384, 2400 ROUND_W_D32 = 2385, 2401 ROUND_W_D64 = 2386, 2402 ROUND_W_D_MMR6 = 2387, 2403 ROUND_W_MM = 2388, 2404 ROUND_W_S = 2389, 2405 ROUND_W_S_MM = 2390, 2406 ROUND_W_S_MMR6 = 2391, 2407 RSQRT_D32 = 2392, 2408 RSQRT_D32_MM = 2393, 2409 RSQRT_D64 = 2394, 2410 RSQRT_D64_MM = 2395, 2411 RSQRT_S = 2396, 2412 RSQRT_S_MM = 2397, 2413 Restore16 = 2398, 2414 RestoreX16 = 2399, 2415 SAA = 2400, 2416 SAAD = 2401, 2417 SAT_S_B = 2402, 2418 SAT_S_D = 2403, 2419 SAT_S_H = 2404, 2420 SAT_S_W = 2405, 2421 SAT_U_B = 2406, 2422 SAT_U_D = 2407, 2423 SAT_U_H = 2408, 2424 SAT_U_W = 2409, 2425 SB = 2410, 2426 SB16_MM = 2411, 2427 SB16_MMR6 = 2412, 2428 SB64 = 2413, 2429 SBE = 2414, 2430 SBE_MM = 2415, 2431 SB_MM = 2416, 2432 SB_MMR6 = 2417, 2433 SC = 2418, 2434 SC64 = 2419, 2435 SC64_R6 = 2420, 2436 SCD = 2421, 2437 SCD_R6 = 2422, 2438 SCE = 2423, 2439 SCE_MM = 2424, 2440 SC_MM = 2425, 2441 SC_MMR6 = 2426, 2442 SC_R6 = 2427, 2443 SD = 2428, 2444 SDBBP = 2429, 2445 SDBBP16_MM = 2430, 2446 SDBBP16_MMR6 = 2431, 2447 SDBBP_MM = 2432, 2448 SDBBP_MMR6 = 2433, 2449 SDBBP_R6 = 2434, 2450 SDC1 = 2435, 2451 SDC164 = 2436, 2452 SDC1_D64_MMR6 = 2437, 2453 SDC1_MM_D32 = 2438, 2454 SDC1_MM_D64 = 2439, 2455 SDC2 = 2440, 2456 SDC2_MMR6 = 2441, 2457 SDC2_R6 = 2442, 2458 SDC3 = 2443, 2459 SDIV = 2444, 2460 SDIV_MM = 2445, 2461 SDL = 2446, 2462 SDR = 2447, 2463 SDXC1 = 2448, 2464 SDXC164 = 2449, 2465 SEB = 2450, 2466 SEB64 = 2451, 2467 SEB_MM = 2452, 2468 SEH = 2453, 2469 SEH64 = 2454, 2470 SEH_MM = 2455, 2471 SELEQZ = 2456, 2472 SELEQZ64 = 2457, 2473 SELEQZ_D = 2458, 2474 SELEQZ_D_MMR6 = 2459, 2475 SELEQZ_MMR6 = 2460, 2476 SELEQZ_S = 2461, 2477 SELEQZ_S_MMR6 = 2462, 2478 SELNEZ = 2463, 2479 SELNEZ64 = 2464, 2480 SELNEZ_D = 2465, 2481 SELNEZ_D_MMR6 = 2466, 2482 SELNEZ_MMR6 = 2467, 2483 SELNEZ_S = 2468, 2484 SELNEZ_S_MMR6 = 2469, 2485 SEL_D = 2470, 2486 SEL_D_MMR6 = 2471, 2487 SEL_S = 2472, 2488 SEL_S_MMR6 = 2473, 2489 SEQ = 2474, 2490 SEQi = 2475, 2491 SH = 2476, 2492 SH16_MM = 2477, 2493 SH16_MMR6 = 2478, 2494 SH64 = 2479, 2495 SHE = 2480, 2496 SHE_MM = 2481, 2497 SHF_B = 2482, 2498 SHF_H = 2483, 2499 SHF_W = 2484, 2500 SHILO = 2485, 2501 SHILOV = 2486, 2502 SHILOV_MM = 2487, 2503 SHILO_MM = 2488, 2504 SHLLV_PH = 2489, 2505 SHLLV_PH_MM = 2490, 2506 SHLLV_QB = 2491, 2507 SHLLV_QB_MM = 2492, 2508 SHLLV_S_PH = 2493, 2509 SHLLV_S_PH_MM = 2494, 2510 SHLLV_S_W = 2495, 2511 SHLLV_S_W_MM = 2496, 2512 SHLL_PH = 2497, 2513 SHLL_PH_MM = 2498, 2514 SHLL_QB = 2499, 2515 SHLL_QB_MM = 2500, 2516 SHLL_S_PH = 2501, 2517 SHLL_S_PH_MM = 2502, 2518 SHLL_S_W = 2503, 2519 SHLL_S_W_MM = 2504, 2520 SHRAV_PH = 2505, 2521 SHRAV_PH_MM = 2506, 2522 SHRAV_QB = 2507, 2523 SHRAV_QB_MMR2 = 2508, 2524 SHRAV_R_PH = 2509, 2525 SHRAV_R_PH_MM = 2510, 2526 SHRAV_R_QB = 2511, 2527 SHRAV_R_QB_MMR2 = 2512, 2528 SHRAV_R_W = 2513, 2529 SHRAV_R_W_MM = 2514, 2530 SHRA_PH = 2515, 2531 SHRA_PH_MM = 2516, 2532 SHRA_QB = 2517, 2533 SHRA_QB_MMR2 = 2518, 2534 SHRA_R_PH = 2519, 2535 SHRA_R_PH_MM = 2520, 2536 SHRA_R_QB = 2521, 2537 SHRA_R_QB_MMR2 = 2522, 2538 SHRA_R_W = 2523, 2539 SHRA_R_W_MM = 2524, 2540 SHRLV_PH = 2525, 2541 SHRLV_PH_MMR2 = 2526, 2542 SHRLV_QB = 2527, 2543 SHRLV_QB_MM = 2528, 2544 SHRL_PH = 2529, 2545 SHRL_PH_MMR2 = 2530, 2546 SHRL_QB = 2531, 2547 SHRL_QB_MM = 2532, 2548 SH_MM = 2533, 2549 SH_MMR6 = 2534, 2550 SIGRIE = 2535, 2551 SIGRIE_MMR6 = 2536, 2552 SLDI_B = 2537, 2553 SLDI_D = 2538, 2554 SLDI_H = 2539, 2555 SLDI_W = 2540, 2556 SLD_B = 2541, 2557 SLD_D = 2542, 2558 SLD_H = 2543, 2559 SLD_W = 2544, 2560 SLL = 2545, 2561 SLL16_MM = 2546, 2562 SLL16_MMR6 = 2547, 2563 SLL64_32 = 2548, 2564 SLL64_64 = 2549, 2565 SLLI_B = 2550, 2566 SLLI_D = 2551, 2567 SLLI_H = 2552, 2568 SLLI_W = 2553, 2569 SLLV = 2554, 2570 SLLV_MM = 2555, 2571 SLL_B = 2556, 2572 SLL_D = 2557, 2573 SLL_H = 2558, 2574 SLL_MM = 2559, 2575 SLL_MMR6 = 2560, 2576 SLL_W = 2561, 2577 SLT = 2562, 2578 SLT64 = 2563, 2579 SLT_MM = 2564, 2580 SLTi = 2565, 2581 SLTi64 = 2566, 2582 SLTi_MM = 2567, 2583 SLTiu = 2568, 2584 SLTiu64 = 2569, 2585 SLTiu_MM = 2570, 2586 SLTu = 2571, 2587 SLTu64 = 2572, 2588 SLTu_MM = 2573, 2589 SNE = 2574, 2590 SNEi = 2575, 2591 SPLATI_B = 2576, 2592 SPLATI_D = 2577, 2593 SPLATI_H = 2578, 2594 SPLATI_W = 2579, 2595 SPLAT_B = 2580, 2596 SPLAT_D = 2581, 2597 SPLAT_H = 2582, 2598 SPLAT_W = 2583, 2599 SRA = 2584, 2600 SRAI_B = 2585, 2601 SRAI_D = 2586, 2602 SRAI_H = 2587, 2603 SRAI_W = 2588, 2604 SRARI_B = 2589, 2605 SRARI_D = 2590, 2606 SRARI_H = 2591, 2607 SRARI_W = 2592, 2608 SRAR_B = 2593, 2609 SRAR_D = 2594, 2610 SRAR_H = 2595, 2611 SRAR_W = 2596, 2612 SRAV = 2597, 2613 SRAV_MM = 2598, 2614 SRA_B = 2599, 2615 SRA_D = 2600, 2616 SRA_H = 2601, 2617 SRA_MM = 2602, 2618 SRA_W = 2603, 2619 SRL = 2604, 2620 SRL16_MM = 2605, 2621 SRL16_MMR6 = 2606, 2622 SRLI_B = 2607, 2623 SRLI_D = 2608, 2624 SRLI_H = 2609, 2625 SRLI_W = 2610, 2626 SRLRI_B = 2611, 2627 SRLRI_D = 2612, 2628 SRLRI_H = 2613, 2629 SRLRI_W = 2614, 2630 SRLR_B = 2615, 2631 SRLR_D = 2616, 2632 SRLR_H = 2617, 2633 SRLR_W = 2618, 2634 SRLV = 2619, 2635 SRLV_MM = 2620, 2636 SRL_B = 2621, 2637 SRL_D = 2622, 2638 SRL_H = 2623, 2639 SRL_MM = 2624, 2640 SRL_W = 2625, 2641 SSNOP = 2626, 2642 SSNOP_MM = 2627, 2643 SSNOP_MMR6 = 2628, 2644 ST_B = 2629, 2645 ST_D = 2630, 2646 ST_H = 2631, 2647 ST_W = 2632, 2648 SUB = 2633, 2649 SUBQH_PH = 2634, 2650 SUBQH_PH_MMR2 = 2635, 2651 SUBQH_R_PH = 2636, 2652 SUBQH_R_PH_MMR2 = 2637, 2653 SUBQH_R_W = 2638, 2654 SUBQH_R_W_MMR2 = 2639, 2655 SUBQH_W = 2640, 2656 SUBQH_W_MMR2 = 2641, 2657 SUBQ_PH = 2642, 2658 SUBQ_PH_MM = 2643, 2659 SUBQ_S_PH = 2644, 2660 SUBQ_S_PH_MM = 2645, 2661 SUBQ_S_W = 2646, 2662 SUBQ_S_W_MM = 2647, 2663 SUBSUS_U_B = 2648, 2664 SUBSUS_U_D = 2649, 2665 SUBSUS_U_H = 2650, 2666 SUBSUS_U_W = 2651, 2667 SUBSUU_S_B = 2652, 2668 SUBSUU_S_D = 2653, 2669 SUBSUU_S_H = 2654, 2670 SUBSUU_S_W = 2655, 2671 SUBS_S_B = 2656, 2672 SUBS_S_D = 2657, 2673 SUBS_S_H = 2658, 2674 SUBS_S_W = 2659, 2675 SUBS_U_B = 2660, 2676 SUBS_U_D = 2661, 2677 SUBS_U_H = 2662, 2678 SUBS_U_W = 2663, 2679 SUBU16_MM = 2664, 2680 SUBU16_MMR6 = 2665, 2681 SUBUH_QB = 2666, 2682 SUBUH_QB_MMR2 = 2667, 2683 SUBUH_R_QB = 2668, 2684 SUBUH_R_QB_MMR2 = 2669, 2685 SUBU_MMR6 = 2670, 2686 SUBU_PH = 2671, 2687 SUBU_PH_MMR2 = 2672, 2688 SUBU_QB = 2673, 2689 SUBU_QB_MM = 2674, 2690 SUBU_S_PH = 2675, 2691 SUBU_S_PH_MMR2 = 2676, 2692 SUBU_S_QB = 2677, 2693 SUBU_S_QB_MM = 2678, 2694 SUBVI_B = 2679, 2695 SUBVI_D = 2680, 2696 SUBVI_H = 2681, 2697 SUBVI_W = 2682, 2698 SUBV_B = 2683, 2699 SUBV_D = 2684, 2700 SUBV_H = 2685, 2701 SUBV_W = 2686, 2702 SUB_MM = 2687, 2703 SUB_MMR6 = 2688, 2704 SUBu = 2689, 2705 SUBu_MM = 2690, 2706 SUXC1 = 2691, 2707 SUXC164 = 2692, 2708 SUXC1_MM = 2693, 2709 SW = 2694, 2710 SW16_MM = 2695, 2711 SW16_MMR6 = 2696, 2712 SW64 = 2697, 2713 SWC1 = 2698, 2714 SWC1_MM = 2699, 2715 SWC2 = 2700, 2716 SWC2_MMR6 = 2701, 2717 SWC2_R6 = 2702, 2718 SWC3 = 2703, 2719 SWDSP = 2704, 2720 SWDSP_MM = 2705, 2721 SWE = 2706, 2722 SWE_MM = 2707, 2723 SWL = 2708, 2724 SWL64 = 2709, 2725 SWLE = 2710, 2726 SWLE_MM = 2711, 2727 SWL_MM = 2712, 2728 SWM16_MM = 2713, 2729 SWM16_MMR6 = 2714, 2730 SWM32_MM = 2715, 2731 SWP_MM = 2716, 2732 SWR = 2717, 2733 SWR64 = 2718, 2734 SWRE = 2719, 2735 SWRE_MM = 2720, 2736 SWR_MM = 2721, 2737 SWSP_MM = 2722, 2738 SWSP_MMR6 = 2723, 2739 SWXC1 = 2724, 2740 SWXC1_MM = 2725, 2741 SW_MM = 2726, 2742 SW_MMR6 = 2727, 2743 SYNC = 2728, 2744 SYNCI = 2729, 2745 SYNCI_MM = 2730, 2746 SYNCI_MMR6 = 2731, 2747 SYNC_MM = 2732, 2748 SYNC_MMR6 = 2733, 2749 SYSCALL = 2734, 2750 SYSCALL_MM = 2735, 2751 Save16 = 2736, 2752 SaveX16 = 2737, 2753 SbRxRyOffMemX16 = 2738, 2754 SebRx16 = 2739, 2755 SehRx16 = 2740, 2756 ShRxRyOffMemX16 = 2741, 2757 SllX16 = 2742, 2758 SllvRxRy16 = 2743, 2759 SltRxRy16 = 2744, 2760 SltiRxImm16 = 2745, 2761 SltiRxImmX16 = 2746, 2762 SltiuRxImm16 = 2747, 2763 SltiuRxImmX16 = 2748, 2764 SltuRxRy16 = 2749, 2765 SraX16 = 2750, 2766 SravRxRy16 = 2751, 2767 SrlX16 = 2752, 2768 SrlvRxRy16 = 2753, 2769 SubuRxRyRz16 = 2754, 2770 SwRxRyOffMemX16 = 2755, 2771 SwRxSpImmX16 = 2756, 2772 TEQ = 2757, 2773 TEQI = 2758, 2774 TEQI_MM = 2759, 2775 TEQ_MM = 2760, 2776 TGE = 2761, 2777 TGEI = 2762, 2778 TGEIU = 2763, 2779 TGEIU_MM = 2764, 2780 TGEI_MM = 2765, 2781 TGEU = 2766, 2782 TGEU_MM = 2767, 2783 TGE_MM = 2768, 2784 TLBGINV = 2769, 2785 TLBGINVF = 2770, 2786 TLBGINVF_MM = 2771, 2787 TLBGINV_MM = 2772, 2788 TLBGP = 2773, 2789 TLBGP_MM = 2774, 2790 TLBGR = 2775, 2791 TLBGR_MM = 2776, 2792 TLBGWI = 2777, 2793 TLBGWI_MM = 2778, 2794 TLBGWR = 2779, 2795 TLBGWR_MM = 2780, 2796 TLBINV = 2781, 2797 TLBINVF = 2782, 2798 TLBINVF_MMR6 = 2783, 2799 TLBINV_MMR6 = 2784, 2800 TLBP = 2785, 2801 TLBP_MM = 2786, 2802 TLBR = 2787, 2803 TLBR_MM = 2788, 2804 TLBWI = 2789, 2805 TLBWI_MM = 2790, 2806 TLBWR = 2791, 2807 TLBWR_MM = 2792, 2808 TLT = 2793, 2809 TLTI = 2794, 2810 TLTIU_MM = 2795, 2811 TLTI_MM = 2796, 2812 TLTU = 2797, 2813 TLTU_MM = 2798, 2814 TLT_MM = 2799, 2815 TNE = 2800, 2816 TNEI = 2801, 2817 TNEI_MM = 2802, 2818 TNE_MM = 2803, 2819 TRUNC_L_D64 = 2804, 2820 TRUNC_L_D_MMR6 = 2805, 2821 TRUNC_L_S = 2806, 2822 TRUNC_L_S_MMR6 = 2807, 2823 TRUNC_W_D32 = 2808, 2824 TRUNC_W_D64 = 2809, 2825 TRUNC_W_D_MMR6 = 2810, 2826 TRUNC_W_MM = 2811, 2827 TRUNC_W_S = 2812, 2828 TRUNC_W_S_MM = 2813, 2829 TRUNC_W_S_MMR6 = 2814, 2830 TTLTIU = 2815, 2831 UDIV = 2816, 2832 UDIV_MM = 2817, 2833 V3MULU = 2818, 2834 VMM0 = 2819, 2835 VMULU = 2820, 2836 VSHF_B = 2821, 2837 VSHF_D = 2822, 2838 VSHF_H = 2823, 2839 VSHF_W = 2824, 2840 WAIT = 2825, 2841 WAIT_MM = 2826, 2842 WAIT_MMR6 = 2827, 2843 WRDSP = 2828, 2844 WRDSP_MM = 2829, 2845 WRPGPR_MMR6 = 2830, 2846 WSBH = 2831, 2847 WSBH_MM = 2832, 2848 WSBH_MMR6 = 2833, 2849 XOR = 2834, 2850 XOR16_MM = 2835, 2851 XOR16_MMR6 = 2836, 2852 XOR64 = 2837, 2853 XORI_B = 2838, 2854 XORI_MMR6 = 2839, 2855 XOR_MM = 2840, 2856 XOR_MMR6 = 2841, 2857 XOR_V = 2842, 2858 XORi = 2843, 2859 XORi64 = 2844, 2860 XORi_MM = 2845, 2861 XorRxRxRy16 = 2846, 2862 YIELD = 2847, 2863 INSTRUCTION_LIST_END = 2848 2864 }; 2865 2866} // end namespace Mips 2867} // end namespace llvm 2868#endif // GET_INSTRINFO_ENUM 2869 2870#ifdef GET_INSTRINFO_SCHED_ENUM 2871#undef GET_INSTRINFO_SCHED_ENUM 2872namespace llvm { 2873 2874namespace Mips { 2875namespace Sched { 2876 enum { 2877 NoInstrModel = 0, 2878 IIPseudo = 1, 2879 II_B = 2, 2880 II_BCCZAL = 3, 2881 II_MTC1 = 4, 2882 II_MFC1 = 5, 2883 II_JALR = 6, 2884 II_JAL = 7, 2885 II_CVT = 8, 2886 II_DMULT = 9, 2887 II_DMULTU = 10, 2888 II_DDIV = 11, 2889 II_DDIVU = 12, 2890 II_IndirectBranchPseudo = 13, 2891 II_MADD = 14, 2892 II_MADDU = 15, 2893 II_MFHI_MFLO = 16, 2894 II_MSUB = 17, 2895 II_MSUBU = 18, 2896 II_MTHI_MTLO = 19, 2897 II_MULT = 20, 2898 II_MULTU = 21, 2899 II_ReturnPseudo = 22, 2900 II_DIV = 23, 2901 II_DIVU = 24, 2902 II_J = 25, 2903 II_JR = 26, 2904 II_TRAP = 27, 2905 II_ADD = 28, 2906 II_ADDIUPC = 29, 2907 II_ADDIU = 30, 2908 II_ADDR_PS = 31, 2909 II_ADDU = 32, 2910 II_ADDI = 33, 2911 II_ALIGN = 34, 2912 II_ALUIPC = 35, 2913 II_AND = 36, 2914 II_ANDI = 37, 2915 II_AUI = 38, 2916 II_AUIPC = 39, 2917 IIM16Alu = 40, 2918 II_BADDU = 41, 2919 II_BC = 42, 2920 II_BALC = 43, 2921 II_BBIT = 44, 2922 II_BC1CCZ = 45, 2923 II_BC1F = 46, 2924 II_BC1FL = 47, 2925 II_BC1T = 48, 2926 II_BC1TL = 49, 2927 II_BC2CCZ = 50, 2928 II_BCC = 51, 2929 II_BCCC = 52, 2930 II_BCCZ = 53, 2931 II_BCCZC = 54, 2932 II_BCCZALS = 55, 2933 II_BITSWAP = 56, 2934 II_BREAK = 57, 2935 II_CACHE = 58, 2936 II_CACHEE = 59, 2937 II_CEIL = 60, 2938 II_CFC1 = 61, 2939 II_CFC2 = 62, 2940 II_INS = 63, 2941 II_CLASS_D = 64, 2942 II_CLASS_S = 65, 2943 II_CLO = 66, 2944 II_CLZ = 67, 2945 II_CMP_CC_D = 68, 2946 II_CMP_CC_S = 69, 2947 II_CRC32B = 70, 2948 II_CRC32CB = 71, 2949 II_CRC32CD = 72, 2950 II_CRC32CH = 73, 2951 II_CRC32CW = 74, 2952 II_CRC32D = 75, 2953 II_CRC32H = 76, 2954 II_CRC32W = 77, 2955 II_CTC1 = 78, 2956 II_CTC2 = 79, 2957 II_C_CC_D = 80, 2958 II_C_CC_S = 81, 2959 II_DADD = 82, 2960 II_DADDI = 83, 2961 II_DADDIU = 84, 2962 II_DADDU = 85, 2963 II_DAHI = 86, 2964 II_DALIGN = 87, 2965 II_DATI = 88, 2966 II_DAUI = 89, 2967 II_DBITSWAP = 90, 2968 II_DCLO = 91, 2969 II_DCLZ = 92, 2970 II_DERET = 93, 2971 II_EXT = 94, 2972 II_DI = 95, 2973 II_DLSA = 96, 2974 II_DMFC0 = 97, 2975 II_DMFC1 = 98, 2976 II_DMFC2 = 99, 2977 II_DMFGC0 = 100, 2978 II_DMOD = 101, 2979 II_DMODU = 102, 2980 II_DMT = 103, 2981 II_DMTC0 = 104, 2982 II_DMTC1 = 105, 2983 II_DMTC2 = 106, 2984 II_DMTGC0 = 107, 2985 II_DMUH = 108, 2986 II_DMUHU = 109, 2987 II_DMUL = 110, 2988 II_POP = 111, 2989 II_DROTR = 112, 2990 II_DROTR32 = 113, 2991 II_DROTRV = 114, 2992 II_DSBH = 115, 2993 II_DSHD = 116, 2994 II_DSLL = 117, 2995 II_DSLL32 = 118, 2996 II_DSLLV = 119, 2997 II_DSRA = 120, 2998 II_DSRA32 = 121, 2999 II_DSRAV = 122, 3000 II_DSRL = 123, 3001 II_DSRL32 = 124, 3002 II_DSRLV = 125, 3003 II_DSUB = 126, 3004 II_DSUBU = 127, 3005 II_DVP = 128, 3006 II_DVPE = 129, 3007 II_EHB = 130, 3008 II_EI = 131, 3009 II_EMT = 132, 3010 II_ERET = 133, 3011 II_ERETNC = 134, 3012 II_EVP = 135, 3013 II_EVPE = 136, 3014 II_ABS = 137, 3015 II_SQRT_D = 138, 3016 II_ADD_D = 139, 3017 II_ADD_PS = 140, 3018 II_ADD_S = 141, 3019 II_DIV_D = 142, 3020 II_DIV_S = 143, 3021 II_FLOOR = 144, 3022 II_MOV_D = 145, 3023 II_MOV_S = 146, 3024 II_MUL_D = 147, 3025 II_MUL_PS = 148, 3026 II_MUL_S = 149, 3027 II_NEG = 150, 3028 II_FORK = 151, 3029 II_SQRT_S = 152, 3030 II_SUB_D = 153, 3031 II_SUB_PS = 154, 3032 II_SUB_S = 155, 3033 II_GINVI = 156, 3034 II_GINVT = 157, 3035 II_HYPCALL = 158, 3036 II_JALR_HB = 159, 3037 II_JALRC = 160, 3038 II_JALRS = 161, 3039 II_JALS = 162, 3040 II_JIALC = 163, 3041 II_JIC = 164, 3042 II_JRADDIUSP = 165, 3043 II_JRC = 166, 3044 II_JR_HB = 167, 3045 II_LB = 168, 3046 II_LBE = 169, 3047 II_LBU = 170, 3048 II_LBUE = 171, 3049 II_LD = 172, 3050 II_LDC1 = 173, 3051 II_LDC2 = 174, 3052 II_LDC3 = 175, 3053 II_LDL = 176, 3054 II_LDPC = 177, 3055 II_LDR = 178, 3056 II_LDXC1 = 179, 3057 II_LH = 180, 3058 II_LHE = 181, 3059 II_LHU = 182, 3060 II_LHUE = 183, 3061 II_LI = 184, 3062 II_LL = 185, 3063 II_LLD = 186, 3064 II_LLE = 187, 3065 II_LSA = 188, 3066 II_LUI = 189, 3067 II_LUXC1 = 190, 3068 II_LW = 191, 3069 II_LWC1 = 192, 3070 II_LWC2 = 193, 3071 II_LWC3 = 194, 3072 II_LWE = 195, 3073 II_LWL = 196, 3074 II_LWLE = 197, 3075 II_LWM = 198, 3076 II_LWPC = 199, 3077 II_LWP = 200, 3078 II_LWR = 201, 3079 II_LWRE = 202, 3080 II_LWUPC = 203, 3081 II_LWU = 204, 3082 II_LWXC1 = 205, 3083 II_LWXS = 206, 3084 II_MADDF_D = 207, 3085 II_MADDF_S = 208, 3086 II_MADD_D = 209, 3087 II_MADD_S = 210, 3088 II_MAX_D = 211, 3089 II_MAXA_D = 212, 3090 II_MAX_S = 213, 3091 II_MAXA_S = 214, 3092 II_MFC0 = 215, 3093 II_MFC2 = 216, 3094 II_MFGC0 = 217, 3095 II_MFHC0 = 218, 3096 II_MFHC1 = 219, 3097 II_MFHGC0 = 220, 3098 II_MFTR = 221, 3099 II_MIN_S = 222, 3100 II_MINA_D = 223, 3101 II_MIN_D = 224, 3102 II_MINA_S = 225, 3103 II_MOD = 226, 3104 II_MODU = 227, 3105 II_MOVE = 228, 3106 II_MOVF_D = 229, 3107 II_MOVF = 230, 3108 II_MOVF_S = 231, 3109 II_MOVN_D = 232, 3110 II_MOVN = 233, 3111 II_MOVN_S = 234, 3112 II_MOVT_D = 235, 3113 II_MOVT = 236, 3114 II_MOVT_S = 237, 3115 II_MOVZ_D = 238, 3116 II_MOVZ = 239, 3117 II_MOVZ_S = 240, 3118 II_MSUBF_D = 241, 3119 II_MSUBF_S = 242, 3120 II_MSUB_D = 243, 3121 II_MSUB_S = 244, 3122 II_MTC0 = 245, 3123 II_MTC2 = 246, 3124 II_MTGC0 = 247, 3125 II_MTHC0 = 248, 3126 II_MTHC1 = 249, 3127 II_MTHGC0 = 250, 3128 II_MTTR = 251, 3129 II_MUH = 252, 3130 II_MUHU = 253, 3131 II_MUL = 254, 3132 II_MULR_PS = 255, 3133 II_MULU = 256, 3134 II_NMADD_D = 257, 3135 II_NMADD_S = 258, 3136 II_NMSUB_D = 259, 3137 II_NMSUB_S = 260, 3138 II_NOR = 261, 3139 II_NOT = 262, 3140 II_OR = 263, 3141 II_ORI = 264, 3142 II_PAUSE = 265, 3143 II_PREF = 266, 3144 II_PREFE = 267, 3145 II_RDHWR = 268, 3146 II_RDPGPR = 269, 3147 II_RECIP_D = 270, 3148 II_RECIP_S = 271, 3149 II_RINT_D = 272, 3150 II_RINT_S = 273, 3151 II_ROTR = 274, 3152 II_ROTRV = 275, 3153 II_ROUND = 276, 3154 II_RSQRT_D = 277, 3155 II_RSQRT_S = 278, 3156 II_RESTORE = 279, 3157 II_SB = 280, 3158 II_SBE = 281, 3159 II_SC = 282, 3160 II_SCD = 283, 3161 II_SCE = 284, 3162 II_SD = 285, 3163 II_SDBBP = 286, 3164 II_SDC1 = 287, 3165 II_SDC2 = 288, 3166 II_SDC3 = 289, 3167 II_SDL = 290, 3168 II_SDR = 291, 3169 II_SDXC1 = 292, 3170 II_SEB = 293, 3171 II_SEH = 294, 3172 II_SELCCZ = 295, 3173 II_SELCCZ_D = 296, 3174 II_SELCCZ_S = 297, 3175 II_SEL_D = 298, 3176 II_SEL_S = 299, 3177 II_SEQ_SNE = 300, 3178 II_SEQI_SNEI = 301, 3179 II_SH = 302, 3180 II_SHE = 303, 3181 II_SIGRIE = 304, 3182 II_SLL = 305, 3183 II_SLLV = 306, 3184 II_SLT_SLTU = 307, 3185 II_SLTI_SLTIU = 308, 3186 II_SRA = 309, 3187 II_SRAV = 310, 3188 II_SRL = 311, 3189 II_SRLV = 312, 3190 II_SSNOP = 313, 3191 II_SUB = 314, 3192 II_SUBU = 315, 3193 II_SUXC1 = 316, 3194 II_SW = 317, 3195 II_SWC1 = 318, 3196 II_SWC2 = 319, 3197 II_SWC3 = 320, 3198 II_SWE = 321, 3199 II_SWL = 322, 3200 II_SWLE = 323, 3201 II_SWM = 324, 3202 II_SWP = 325, 3203 II_SWR = 326, 3204 II_SWRE = 327, 3205 II_SWXC1 = 328, 3206 II_SYNC = 329, 3207 II_SYNCI = 330, 3208 II_SYSCALL = 331, 3209 II_SAVE = 332, 3210 II_TEQ = 333, 3211 II_TEQI = 334, 3212 II_TGE = 335, 3213 II_TGEI = 336, 3214 II_TGEIU = 337, 3215 II_TGEU = 338, 3216 II_TLBGINV = 339, 3217 II_TLBGINVF = 340, 3218 II_TLBGP = 341, 3219 II_TLBGR = 342, 3220 II_TLBGWI = 343, 3221 II_TLBGWR = 344, 3222 II_TLBINV = 345, 3223 II_TLBINVF = 346, 3224 II_TLBP = 347, 3225 II_TLBR = 348, 3226 II_TLBWI = 349, 3227 II_TLBWR = 350, 3228 II_TLT = 351, 3229 II_TLTI = 352, 3230 II_TTLTIU = 353, 3231 II_TLTU = 354, 3232 II_TNE = 355, 3233 II_TNEI = 356, 3234 II_TRUNC = 357, 3235 II_WAIT = 358, 3236 II_WRPGPR = 359, 3237 II_WSBH = 360, 3238 II_XOR = 361, 3239 II_XORI = 362, 3240 II_YIELD = 363, 3241 AND = 364, 3242 LUi = 365, 3243 NOR = 366, 3244 OR = 367, 3245 SLTi_SLTiu = 368, 3246 SUB = 369, 3247 SUBu = 370, 3248 XOR = 371, 3249 SSNOP = 372, 3250 NOP = 373, 3251 B = 374, 3252 BAL = 375, 3253 BAL_BR_BGEZAL_BGEZALL_BLTZAL_BLTZALL = 376, 3254 BEQ_BEQL_BNE_BNEL = 377, 3255 BGEZ_BGEZL_BGTZ_BGTZL_BLEZ_BLEZL_BLTZ_BLTZL = 378, 3256 BREAK = 379, 3257 DERET = 380, 3258 ERET = 381, 3259 ERet_RetRA = 382, 3260 ERETNC = 383, 3261 J_TAILCALL = 384, 3262 JR_TAILCALLREG_TAILCALLREGHB = 385, 3263 JR_HB = 386, 3264 PseudoIndirectBranch_PseudoIndirectHazardBranch = 387, 3265 PseudoReturn = 388, 3266 SDBBP = 389, 3267 SYSCALL = 390, 3268 TEQ = 391, 3269 TEQI = 392, 3270 TGE = 393, 3271 TGEI = 394, 3272 TGEIU = 395, 3273 TGEU = 396, 3274 TLT = 397, 3275 TLTI = 398, 3276 TLTU = 399, 3277 TNE = 400, 3278 TNEI = 401, 3279 TRAP = 402, 3280 TTLTIU = 403, 3281 WAIT = 404, 3282 PAUSE = 405, 3283 JAL = 406, 3284 JALR_JALRHBPseudo_JALRPseudo = 407, 3285 JALR_HB = 408, 3286 JALX = 409, 3287 TLBINV = 410, 3288 TLBINVF = 411, 3289 TLBP = 412, 3290 TLBR = 413, 3291 TLBWI = 414, 3292 TLBWR = 415, 3293 MFC0 = 416, 3294 MTC0 = 417, 3295 MFC2 = 418, 3296 MTC2 = 419, 3297 HYPCALL = 420, 3298 MFGC0 = 421, 3299 MFHGC0 = 422, 3300 MTGC0 = 423, 3301 MTHGC0 = 424, 3302 TLBGINV = 425, 3303 TLBGINVF = 426, 3304 TLBGP = 427, 3305 TLBGR = 428, 3306 TLBGWI = 429, 3307 TLBGWR = 430, 3308 LB = 431, 3309 LBu = 432, 3310 LH = 433, 3311 LHu = 434, 3312 LW = 435, 3313 LL = 436, 3314 LWC2 = 437, 3315 LWC3 = 438, 3316 LDC2 = 439, 3317 LDC3 = 440, 3318 LBE = 441, 3319 LBuE = 442, 3320 LHE = 443, 3321 LHuE = 444, 3322 LWE = 445, 3323 LLE = 446, 3324 LWPC = 447, 3325 LWL = 448, 3326 LWR = 449, 3327 LWLE = 450, 3328 LWRE = 451, 3329 SB = 452, 3330 SH = 453, 3331 SW = 454, 3332 SWC2 = 455, 3333 SWC3 = 456, 3334 SDC2 = 457, 3335 SDC3 = 458, 3336 SC = 459, 3337 SBE = 460, 3338 SHE = 461, 3339 SWE = 462, 3340 SCE = 463, 3341 SWL = 464, 3342 SWR = 465, 3343 SWLE = 466, 3344 SWRE = 467, 3345 PREF = 468, 3346 PREFE = 469, 3347 CACHE = 470, 3348 CACHEE = 471, 3349 SYNC = 472, 3350 SYNCI = 473, 3351 CLO = 474, 3352 CLZ = 475, 3353 DI = 476, 3354 EI = 477, 3355 MFHI_MFLO_PseudoMFHI_PseudoMFLO = 478, 3356 EHB = 479, 3357 RDHWR = 480, 3358 WSBH = 481, 3359 MOVN_I_I = 482, 3360 MOVZ_I_I = 483, 3361 DIV_PseudoSDIV_SDIV = 484, 3362 DIVU_PseudoUDIV_UDIV = 485, 3363 MUL = 486, 3364 MULT_PseudoMULT = 487, 3365 MULTu_PseudoMULTu = 488, 3366 MADD_PseudoMADD = 489, 3367 MADDU_PseudoMADDU = 490, 3368 MSUB_PseudoMSUB = 491, 3369 MSUBU_PseudoMSUBU = 492, 3370 MTHI_MTLO_PseudoMTLOHI = 493, 3371 EXT = 494, 3372 INS = 495, 3373 ADD = 496, 3374 ADDi = 497, 3375 ADDiu = 498, 3376 ANDi = 499, 3377 ORi = 500, 3378 ROTR = 501, 3379 SEB = 502, 3380 SEH = 503, 3381 SLT_SLTu = 504, 3382 SLL = 505, 3383 SRA = 506, 3384 SRL = 507, 3385 XORi = 508, 3386 ADDu = 509, 3387 SLLV = 510, 3388 SRAV = 511, 3389 SRLV = 512, 3390 LSA = 513, 3391 COPY = 514, 3392 VSHF_B_VSHF_D_VSHF_H_VSHF_W = 515, 3393 BINSLI_B_BINSLI_D_BINSLI_H_BINSLI_W_BINSL_B_BINSL_D_BINSL_H_BINSL_W = 516, 3394 BINSRI_B_BINSRI_D_BINSRI_H_BINSRI_W_BINSR_B_BINSR_D_BINSR_H_BINSR_W = 517, 3395 INSERT_B_INSERT_D_INSERT_H_INSERT_W = 518, 3396 SLDI_B_SLDI_D_SLDI_H_SLDI_W_SLD_B_SLD_D_SLD_H_SLD_W = 519, 3397 BSETI_B_BSETI_D_BSETI_H_BSETI_W_BSET_B_BSET_D_BSET_H_BSET_W = 520, 3398 BCLRI_B_BCLRI_D_BCLRI_H_BCLRI_W_BCLR_B_BCLR_D_BCLR_H_BCLR_W = 521, 3399 BNEGI_B_BNEGI_D_BNEGI_H_BNEGI_W_BNEG_B_BNEG_D_BNEG_H_BNEG_W = 522, 3400 BSELI_B_BSEL_V = 523, 3401 BMNZI_B_BMNZ_V_BMZI_B_BMZ_V = 524, 3402 BSEL_D_PSEUDO_BSEL_FD_PSEUDO_BSEL_FW_PSEUDO_BSEL_H_PSEUDO_BSEL_W_PSEUDO = 525, 3403 PCNT_B_PCNT_D_PCNT_H_PCNT_W = 526, 3404 SAT_S_B_SAT_S_D_SAT_S_H_SAT_S_W_SAT_U_B_SAT_U_D_SAT_U_H_SAT_U_W = 527, 3405 BNZ_B_BNZ_D_BNZ_H_BNZ_V_BNZ_W_BZ_B_BZ_D_BZ_H_BZ_V_BZ_W = 528, 3406 CFCMSA_CTCMSA = 529, 3407 FABS_S_FABS_D32_FABS_D64 = 530, 3408 MOVF_D32_MOVF_D64 = 531, 3409 MOVF_S = 532, 3410 MOVT_D32_MOVT_D64 = 533, 3411 MOVT_S = 534, 3412 FMOV_D32_FMOV_D64 = 535, 3413 FMOV_S = 536, 3414 FNEG_S_FNEG_D32_FNEG_D64 = 537, 3415 ADD_A_B_ADD_A_D_ADD_A_H_ADD_A_W = 538, 3416 ADDS_A_B_ADDS_A_D_ADDS_A_H_ADDS_A_W_ADDS_S_B_ADDS_S_D_ADDS_S_H_ADDS_S_W_ADDS_U_B_ADDS_U_D_ADDS_U_H_ADDS_U_W = 539, 3417 ADDVI_B_ADDVI_D_ADDVI_H_ADDVI_W_ADDV_B_ADDV_D_ADDV_H_ADDV_W = 540, 3418 ASUB_S_B_ASUB_S_D_ASUB_S_H_ASUB_S_W_ASUB_U_B_ASUB_U_D_ASUB_U_H_ASUB_U_W = 541, 3419 AVER_S_B_AVER_S_D_AVER_S_H_AVER_S_W_AVER_U_B_AVER_U_D_AVER_U_H_AVER_U_W_AVE_S_B_AVE_S_D_AVE_S_H_AVE_S_W_AVE_U_B_AVE_U_D_AVE_U_H_AVE_U_W = 542, 3420 SHF_B_SHF_H_SHF_W = 543, 3421 FILL_B_FILL_D_FILL_H_FILL_W = 544, 3422 SPLATI_B_SPLATI_D_SPLATI_H_SPLATI_W_SPLAT_B_SPLAT_D_SPLAT_H_SPLAT_W = 545, 3423 MOVE_V = 546, 3424 LDI_B_LDI_D_LDI_H_LDI_W = 547, 3425 AND_V_NOR_V_OR_V_XOR_V = 548, 3426 ANDI_B_NORI_B_ORI_B_XORI_B = 549, 3427 AND_V_D_PSEUDO_AND_V_H_PSEUDO_AND_V_W_PSEUDO_NOR_V_D_PSEUDO_NOR_V_H_PSEUDO_NOR_V_W_PSEUDO_OR_V_D_PSEUDO_OR_V_H_PSEUDO_OR_V_W_PSEUDO_XOR_V_D_PSEUDO_XOR_V_H_PSEUDO_XOR_V_W_PSEUDO = 550, 3428 FILL_FD_PSEUDO_FILL_FW_PSEUDO = 551, 3429 INSERT_FD_PSEUDO_INSERT_FW_PSEUDO = 552, 3430 FEXP2_D_FEXP2_W = 553, 3431 CLTI_S_B_CLTI_S_D_CLTI_S_H_CLTI_S_W_CLTI_U_B_CLTI_U_D_CLTI_U_H_CLTI_U_W_CLT_S_B_CLT_S_D_CLT_S_H_CLT_S_W_CLT_U_B_CLT_U_D_CLT_U_H_CLT_U_W = 554, 3432 CLEI_S_B_CLEI_S_D_CLEI_S_H_CLEI_S_W_CLEI_U_B_CLEI_U_D_CLEI_U_H_CLEI_U_W_CLE_S_B_CLE_S_D_CLE_S_H_CLE_S_W_CLE_U_B_CLE_U_D_CLE_U_H_CLE_U_W = 555, 3433 CEQI_B_CEQI_D_CEQI_H_CEQI_W_CEQ_B_CEQ_D_CEQ_H_CEQ_W = 556, 3434 CMP_UN_D = 557, 3435 CMP_UN_S = 558, 3436 CMP_UEQ_D = 559, 3437 CMP_UEQ_S = 560, 3438 CMP_EQ_D = 561, 3439 CMP_EQ_S = 562, 3440 CMP_LT_D = 563, 3441 CMP_LT_S = 564, 3442 CMP_ULT_D = 565, 3443 CMP_ULT_S = 566, 3444 CMP_LE_D = 567, 3445 CMP_LE_S = 568, 3446 CMP_ULE_D = 569, 3447 CMP_ULE_S = 570, 3448 FSAF_D_FSAF_W_FSEQ_D_FSEQ_W_FSLE_D_FSLE_W_FSLT_D_FSLT_W_FSNE_D_FSNE_W_FSOR_D_FSOR_W = 571, 3449 FSUEQ_D_FSUEQ_W = 572, 3450 FSULE_D_FSULE_W = 573, 3451 FSULT_D_FSULT_W = 574, 3452 FSUNE_D_FSUNE_W = 575, 3453 FSUN_D_FSUN_W = 576, 3454 FCAF_D_FCAF_W = 577, 3455 FCEQ_D_FCEQ_W = 578, 3456 FCLE_D_FCLE_W = 579, 3457 FCLT_D_FCLT_W = 580, 3458 FCNE_D_FCNE_W = 581, 3459 FCOR_D_FCOR_W = 582, 3460 FCUEQ_D_FCUEQ_W = 583, 3461 FCULE_D_FCULE_W = 584, 3462 FCULT_D_FCULT_W = 585, 3463 FCUNE_D_FCUNE_W = 586, 3464 FCUN_D_FCUN_W = 587, 3465 FABS_D_FABS_W = 588, 3466 FFINT_S_D_FFINT_S_W_FFINT_U_D_FFINT_U_W = 589, 3467 FFQL_D_FFQL_W = 590, 3468 FFQR_D_FFQR_W = 591, 3469 FTINT_S_D_FTINT_S_W_FTINT_U_D_FTINT_U_W = 592, 3470 FRINT_D_FRINT_W = 593, 3471 FTQ_H_FTQ_W = 594, 3472 FTRUNC_S_D_FTRUNC_S_W_FTRUNC_U_D_FTRUNC_U_W = 595, 3473 FEXDO_H_FEXDO_W = 596, 3474 FEXUPL_D_FEXUPL_W = 597, 3475 FEXUPR_D_FEXUPR_W = 598, 3476 FCLASS_D_FCLASS_W = 599, 3477 FMAX_A_D_FMAX_A_W = 600, 3478 FMAX_D_FMAX_W = 601, 3479 FMIN_A_D_FMIN_A_W = 602, 3480 FMIN_D_FMIN_W = 603, 3481 FLOG2_D_FLOG2_W = 604, 3482 ILVL_B_ILVL_D_ILVL_H_ILVL_W_ILVR_B_ILVR_D_ILVR_H_ILVR_W = 605, 3483 ILVEV_B_ILVEV_D_ILVEV_H_ILVEV_W_ILVOD_B_ILVOD_D_ILVOD_H_ILVOD_W = 606, 3484 INSVE_B_INSVE_D_INSVE_H_INSVE_W = 607, 3485 SUBS_S_B_SUBS_S_D_SUBS_S_H_SUBS_S_W_SUBS_U_B_SUBS_U_D_SUBS_U_H_SUBS_U_W = 608, 3486 SUBSUS_U_B_SUBSUS_U_D_SUBSUS_U_H_SUBSUS_U_W = 609, 3487 SUBSUU_S_B_SUBSUU_S_D_SUBSUU_S_H_SUBSUU_S_W = 610, 3488 SUBVI_B_SUBVI_D_SUBVI_H_SUBVI_W = 611, 3489 SUBV_B_SUBV_D_SUBV_H_SUBV_W = 612, 3490 MOD_S_B_MOD_S_D_MOD_S_H_MOD_S_W_MOD_U_B_MOD_U_D_MOD_U_H_MOD_U_W = 613, 3491 DIV_S_B_DIV_S_D_DIV_S_H_DIV_S_W_DIV_U_B_DIV_U_D_DIV_U_H_DIV_U_W = 614, 3492 HADD_S_D_HADD_S_H_HADD_S_W_HADD_U_D_HADD_U_H_HADD_U_W = 615, 3493 HSUB_S_D_HSUB_S_H_HSUB_S_W_HSUB_U_D_HSUB_U_H_HSUB_U_W = 616, 3494 MAX_S_B_MAX_S_D_MAX_S_H_MAX_S_W_MIN_S_B_MIN_S_D_MIN_S_H_MIN_S_W = 617, 3495 MAX_U_B_MAX_U_D_MAX_U_H_MAX_U_W_MIN_U_B_MIN_U_D_MIN_U_H_MIN_U_W = 618, 3496 MAX_A_B_MAX_A_D_MAX_A_H_MAX_A_W_MIN_A_B_MIN_A_D_MIN_A_H_MIN_A_W = 619, 3497 MAXI_S_B_MAXI_S_D_MAXI_S_H_MAXI_S_W_MAXI_U_B_MAXI_U_D_MAXI_U_H_MAXI_U_W_MINI_S_B_MINI_S_D_MINI_S_H_MINI_S_W_MINI_U_B_MINI_U_D_MINI_U_H_MINI_U_W = 620, 3498 SRAI_B_SRAI_D_SRAI_H_SRAI_W_SRA_B_SRA_D_SRA_H_SRA_W = 621, 3499 SRLI_B_SRLI_D_SRLI_H_SRLI_W_SRL_B_SRL_D_SRL_H_SRL_W = 622, 3500 SRARI_B_SRARI_D_SRARI_H_SRARI_W_SRAR_B_SRAR_D_SRAR_H_SRAR_W = 623, 3501 SRLRI_B_SRLRI_D_SRLRI_H_SRLRI_W_SRLR_B_SRLR_D_SRLR_H_SRLR_W = 624, 3502 SLLI_B_SLLI_D_SLLI_H_SLLI_W_SLL_B_SLL_D_SLL_H_SLL_W = 625, 3503 PCKEV_B_PCKEV_D_PCKEV_H_PCKEV_W_PCKOD_B_PCKOD_D_PCKOD_H_PCKOD_W = 626, 3504 NLOC_B_NLOC_D_NLOC_H_NLOC_W_NLZC_B_NLZC_D_NLZC_H_NLZC_W = 627, 3505 FADD_D32_FADD_D64 = 628, 3506 FADD_PS64 = 629, 3507 FADD_S = 630, 3508 FMUL_D32_FMUL_D64 = 631, 3509 FMUL_PS64 = 632, 3510 FMUL_S = 633, 3511 FSUB_D32_FSUB_D64 = 634, 3512 FSUB_PS64 = 635, 3513 FSUB_S = 636, 3514 TRUNC_L_D64_TRUNC_L_S_TRUNC_W_D32_TRUNC_W_D64_TRUNC_W_S = 637, 3515 CVT_D32_S_CVT_D32_W_CVT_D64_L_CVT_D64_S_CVT_D64_W_CVT_L_D64_CVT_L_S_CVT_S_D32_CVT_S_D64_CVT_S_L_CVT_S_W_CVT_W_D32_CVT_W_D64_CVT_W_S = 638, 3516 CVT_PS_S64_CVT_S_PL64_CVT_S_PU64 = 639, 3517 C_EQ_D32_C_EQ_D64_C_F_D32_C_F_D64_C_LE_D32_C_LE_D64_C_LT_D32_C_LT_D64_C_NGE_D32_C_NGE_D64_C_NGLE_D32_C_NGLE_D64_C_NGL_D32_C_NGL_D64_C_NGT_D32_C_NGT_D64_C_OLE_D32_C_OLE_D64_C_OLT_D32_C_OLT_D64_C_SEQ_D32_C_SEQ_D64_C_SF_D32_C_SF_D64_C_UEQ_D32_C_UEQ_D64_C_ULE_D32_C_ULE_D64_C_ULT_D32_C_ULT_D64_C_UN_D32_C_UN_D64 = 640, 3518 C_EQ_S_C_F_S_C_LE_S_C_LT_S_C_NGE_S_C_NGLE_S_C_NGL_S_C_NGT_S_C_OLE_S_C_OLT_S_C_SEQ_S_C_SF_S_C_UEQ_S_C_ULE_S_C_ULT_S_C_UN_S = 641, 3519 FCMP_D32_FCMP_D64 = 642, 3520 FCMP_S32 = 643, 3521 PseudoCVT_D32_W_PseudoCVT_D64_L_PseudoCVT_D64_W_PseudoCVT_S_L_PseudoCVT_S_W = 644, 3522 PLL_PS64_PLU_PS64_PUL_PS64_PUU_PS64 = 645, 3523 FDIV_S = 646, 3524 FDIV_D32_FDIV_D64 = 647, 3525 FSQRT_S = 648, 3526 FSQRT_D32_FSQRT_D64 = 649, 3527 FRCP_D_FRCP_W = 650, 3528 FRSQRT_D_FRSQRT_W = 651, 3529 RECIP_D32_RECIP_D64 = 652, 3530 RSQRT_D32_RSQRT_D64 = 653, 3531 RECIP_S = 654, 3532 RSQRT_S = 655, 3533 FMADD_D_FMADD_W = 656, 3534 FMSUB_D_FMSUB_W = 657, 3535 FDIV_W = 658, 3536 FDIV_D = 659, 3537 FSQRT_W = 660, 3538 FSQRT_D = 661, 3539 FMUL_D_FMUL_W = 662, 3540 FADD_D_FADD_W = 663, 3541 FSUB_D_FSUB_W = 664, 3542 DPADD_S_D_DPADD_S_H_DPADD_S_W_DPADD_U_D_DPADD_U_H_DPADD_U_W = 665, 3543 DPSUB_S_D_DPSUB_S_H_DPSUB_S_W_DPSUB_U_D_DPSUB_U_H_DPSUB_U_W = 666, 3544 DOTP_S_D_DOTP_S_H_DOTP_S_W_DOTP_U_D_DOTP_U_H_DOTP_U_W = 667, 3545 MSUBV_B_MSUBV_D_MSUBV_H_MSUBV_W = 668, 3546 MADDV_B_MADDV_D_MADDV_H_MADDV_W = 669, 3547 MULV_B_MULV_D_MULV_H_MULV_W = 670, 3548 MADDR_Q_H_MADDR_Q_W = 671, 3549 MADD_Q_H_MADD_Q_W = 672, 3550 MSUBR_Q_H_MSUBR_Q_W = 673, 3551 MSUB_Q_H_MSUB_Q_W = 674, 3552 MULR_Q_H_MULR_Q_W = 675, 3553 MUL_Q_H_MUL_Q_W = 676, 3554 MADD_D32_MADD_D64 = 677, 3555 MADD_S = 678, 3556 MSUB_D32_MSUB_D64 = 679, 3557 MSUB_S = 680, 3558 NMADD_D32_NMADD_D64 = 681, 3559 NMADD_S = 682, 3560 NMSUB_D32_NMSUB_D64 = 683, 3561 NMSUB_S = 684, 3562 CTC1 = 685, 3563 MTC1_MTC1_D64_BuildPairF64_BuildPairF64_64 = 686, 3564 MTHC1_D32_MTHC1_D64 = 687, 3565 COPY_U_B_COPY_U_H_COPY_U_W = 688, 3566 COPY_S_B_COPY_S_D_COPY_S_H_COPY_S_W = 689, 3567 BC1F = 690, 3568 BC1FL = 691, 3569 BC1T = 692, 3570 BC1TL = 693, 3571 CFC1 = 694, 3572 MFC1_MFC1_D64_ExtractElementF64_ExtractElementF64_64 = 695, 3573 MFHC1_D32_MFHC1_D64 = 696, 3574 MOVF_I = 697, 3575 MOVT_I = 698, 3576 SDC1_SDC164 = 699, 3577 SDXC1_SDXC164 = 700, 3578 SWC1 = 701, 3579 SWXC1 = 702, 3580 SUXC1_SUXC164 = 703, 3581 ST_B_ST_D_ST_H_ST_W = 704, 3582 ST_F16 = 705, 3583 MOVN_I_D32_MOVN_I_D64 = 706, 3584 MOVN_I_S = 707, 3585 MOVZ_I_D32_MOVZ_I_D64 = 708, 3586 MOVZ_I_S = 709, 3587 LDC1_LDC164 = 710, 3588 LDXC1_LDXC164 = 711, 3589 LWC1 = 712, 3590 LWXC1 = 713, 3591 LUXC1_LUXC164 = 714, 3592 LD_B_LD_D_LD_H_LD_W = 715, 3593 LD_F16 = 716, 3594 CEIL_L_D64_CEIL_L_S_CEIL_W_D32_CEIL_W_D64_CEIL_W_S = 717, 3595 FLOOR_L_D64_FLOOR_L_S_FLOOR_W_D32_FLOOR_W_D64_FLOOR_W_S = 718, 3596 ROUND_L_D64_ROUND_L_S_ROUND_W_D32_ROUND_W_D64_ROUND_W_S = 719, 3597 ROTRV = 720, 3598 ATOMIC_SWAP_I16_POSTRA_ATOMIC_SWAP_I32_POSTRA_ATOMIC_SWAP_I64_POSTRA_ATOMIC_SWAP_I8_POSTRA = 721, 3599 ATOMIC_CMP_SWAP_I16_POSTRA_ATOMIC_CMP_SWAP_I32_POSTRA_ATOMIC_CMP_SWAP_I64_POSTRA_ATOMIC_CMP_SWAP_I8_POSTRA = 722, 3600 ATOMIC_LOAD_ADD_I16_POSTRA_ATOMIC_LOAD_ADD_I32_POSTRA_ATOMIC_LOAD_ADD_I64_POSTRA_ATOMIC_LOAD_ADD_I8_POSTRA_ATOMIC_LOAD_AND_I16_POSTRA_ATOMIC_LOAD_AND_I32_POSTRA_ATOMIC_LOAD_AND_I64_POSTRA_ATOMIC_LOAD_AND_I8_POSTRA_ATOMIC_LOAD_MAX_I16_POSTRA_ATOMIC_LOAD_MAX_I32_POSTRA_ATOMIC_LOAD_MAX_I64_POSTRA_ATOMIC_LOAD_MAX_I8_POSTRA_ATOMIC_LOAD_MIN_I16_POSTRA_ATOMIC_LOAD_MIN_I32_POSTRA_ATOMIC_LOAD_MIN_I64_POSTRA_ATOMIC_LOAD_MIN_I8_POSTRA_ATOMIC_LOAD_NAND_I16_POSTRA_ATOMIC_LOAD_NAND_I32_POSTRA_ATOMIC_LOAD_NAND_I64_POSTRA_ATOMIC_LOAD_NAND_I8_POSTRA_ATOMIC_LOAD_OR_I16_POSTRA_ATOMIC_LOAD_OR_I32_POSTRA_ATOMIC_LOAD_OR_I64_POSTRA_ATOMIC_LOAD_OR_I8_POSTRA_ATOMIC_LOAD_SUB_I16_POSTRA_ATOMIC_LOAD_SUB_I32_POSTRA_ATOMIC_LOAD_SUB_I64_POSTRA_ATOMIC_LOAD_SUB_I8_POSTRA_ATOMIC_LOAD_UMAX_I16_POSTRA_ATOMIC_LOAD_UMAX_I32_POSTRA_ATOMIC_LOAD_UMAX_I64_POSTRA_ATOMIC_LOAD_UMAX_I8_POSTRA_ATOMIC_LOAD_UMIN_I16_POSTRA_ATOMIC_LOAD_UMIN_I32_POSTRA_ATOMIC_LOAD_UMIN_I64_POSTRA_ATOMIC_LOAD_UMIN_I8_POSTRA_ATOMIC_LOAD_XOR_I16_POSTRA_ATOMIC_LOAD_XOR_I32_POSTRA_ATOMIC_LOAD_XOR_I64_POSTRA_ATOMIC_LOAD_XOR_I8_POSTRA = 723, 3601 LEA_ADDiu = 724, 3602 ADDIUPC = 725, 3603 ALIGN = 726, 3604 ALUIPC = 727, 3605 AUI = 728, 3606 AUIPC = 729, 3607 BITSWAP = 730, 3608 CLO_R6 = 731, 3609 CLZ_R6 = 732, 3610 LSA_R6 = 733, 3611 SELEQZ_SELNEZ = 734, 3612 AddiuRxImmX16_AddiuRxRxImm16_AddiuRxRxImmX16_AddiuRxRyOffMemX16_AddiuRxPcImmX16_AddiuSpImm16_AddiuSpImmX16_AdduRxRyRz16_AndRxRxRy16_CmpRxRy16_CmpiRxImm16_CmpiRxImmX16_LiRxImm16_LiRxImmX16_LiRxImmAlignX16_Move32R16_MoveR3216_Mfhi16_Mflo16_NegRxRy16_NotRxRy16_OrRxRxRy16_SebRx16_SehRx16_SllX16_SllvRxRy16_SltiRxImm16_SltiRxImmX16_SltiuRxImm16_SltiuRxImmX16_SltRxRy16_SltuRxRy16_SravRxRy16_SraX16_SrlvRxRy16_SrlX16_SubuRxRyRz16_XorRxRxRy16 = 735, 3613 SltiCCRxImmX16_SltiuCCRxImmX16_SltCCRxRy16_SltuRxRyRz16_SltuCCRxRy16 = 736, 3614 Constant32_LwConstant32_GotPrologue16_CONSTPOOL_ENTRY = 737, 3615 ADDIUPC_MM_ADDIUR1SP_MM_ADDIUR2_MM_ADDIUS5_MM_ADDIUSP_MM_ADDiu_MM_LEA_ADDiu_MM = 738, 3616 ADDU16_MM_ADDu_MM = 739, 3617 ADD_MM = 740, 3618 ADDi_MM = 741, 3619 AND16_MM_ANDI16_MM_AND_MM = 742, 3620 ANDi_MM = 743, 3621 CLO_MM = 744, 3622 CLZ_MM = 745, 3623 EXT_MM = 746, 3624 INS_MM = 747, 3625 LI16_MM = 748, 3626 LUi_MM = 749, 3627 MOVE16_MM = 750, 3628 MOVEP_MM = 751, 3629 NOR_MM = 752, 3630 NOT16_MM = 753, 3631 OR16_MM_OR_MM = 754, 3632 ORi_MM = 755, 3633 ROTRV_MM = 756, 3634 ROTR_MM = 757, 3635 SEB_MM = 758, 3636 SEH_MM = 759, 3637 SLL16_MM_SLL_MM = 760, 3638 SLLV_MM = 761, 3639 SLT_MM_SLTu_MM = 762, 3640 SLTi_MM_SLTiu_MM = 763, 3641 SRAV_MM = 764, 3642 SRA_MM = 765, 3643 SRL16_MM_SRL_MM = 766, 3644 SRLV_MM = 767, 3645 SSNOP_MM = 768, 3646 SUBU16_MM_SUBu_MM = 769, 3647 SUB_MM = 770, 3648 WSBH_MM = 771, 3649 XOR16_MM_XOR_MM = 772, 3650 XORi_MM = 773, 3651 ADDIUPC_MMR6 = 774, 3652 ADDIU_MMR6 = 775, 3653 ADDU16_MMR6_ADDU_MMR6 = 776, 3654 ADD_MMR6 = 777, 3655 ALIGN_MMR6 = 778, 3656 ALUIPC_MMR6 = 779, 3657 AND16_MMR6_ANDI16_MMR6_AND_MMR6 = 780, 3658 ANDI_MMR6 = 781, 3659 AUIPC_MMR6 = 782, 3660 AUI_MMR6 = 783, 3661 BITSWAP_MMR6 = 784, 3662 CLO_MMR6 = 785, 3663 CLZ_MMR6 = 786, 3664 EXT_MMR6 = 787, 3665 INS_MMR6 = 788, 3666 LI16_MMR6 = 789, 3667 LSA_MMR6 = 790, 3668 LUI_MMR6 = 791, 3669 MOVE16_MMR6 = 792, 3670 NOR_MMR6 = 793, 3671 NOT16_MMR6 = 794, 3672 OR16_MMR6_OR_MMR6 = 795, 3673 ORI_MMR6 = 796, 3674 SELEQZ_MMR6_SELNEZ_MMR6 = 797, 3675 SLL16_MMR6_SLL_MMR6 = 798, 3676 SRL16_MMR6 = 799, 3677 SSNOP_MMR6 = 800, 3678 SUBU16_MMR6_SUBU_MMR6 = 801, 3679 SUB_MMR6 = 802, 3680 WSBH_MMR6 = 803, 3681 XOR16_MMR6_XOR_MMR6 = 804, 3682 XORI_MMR6 = 805, 3683 AND64_ANDi64 = 806, 3684 DEXT64_32 = 807, 3685 DSLL64_32 = 808, 3686 ORi64 = 809, 3687 SEB64 = 810, 3688 SEH64 = 811, 3689 SLL64_32_SLL64_64 = 812, 3690 SLT64_SLTu64 = 813, 3691 SLTi64_SLTiu64 = 814, 3692 XOR64_XORi64 = 815, 3693 DADD = 816, 3694 DADDi = 817, 3695 DADDiu = 818, 3696 DADDu = 819, 3697 DCLO = 820, 3698 DCLZ = 821, 3699 DEXT_DEXTM_DEXTU = 822, 3700 DINS_DINSM_DINSU = 823, 3701 DROTR = 824, 3702 DROTR32 = 825, 3703 DROTRV = 826, 3704 DSBH = 827, 3705 DSHD = 828, 3706 DSLL = 829, 3707 DSLL32 = 830, 3708 DSLLV = 831, 3709 DSRA = 832, 3710 DSRA32 = 833, 3711 DSRAV = 834, 3712 DSRL = 835, 3713 DSRL32 = 836, 3714 DSRLV = 837, 3715 DSUB = 838, 3716 DSUBu = 839, 3717 LEA_ADDiu64 = 840, 3718 LUi64 = 841, 3719 NOR64 = 842, 3720 OR64 = 843, 3721 DALIGN = 844, 3722 DAHI = 845, 3723 DATI = 846, 3724 DAUI = 847, 3725 DCLO_R6 = 848, 3726 DCLZ_R6 = 849, 3727 DBITSWAP = 850, 3728 DLSA_DLSA_R6 = 851, 3729 SELEQZ64_SELNEZ64 = 852, 3730 MADD = 853, 3731 MADDU = 854, 3732 MSUB = 855, 3733 MSUBU = 856, 3734 PseudoMADD_MM = 857, 3735 PseudoMADDU_MM = 858, 3736 PseudoMSUB_MM = 859, 3737 PseudoMSUBU_MM = 860, 3738 PseudoMULT_MM = 861, 3739 PseudoMULTu_MM = 862, 3740 PseudoMULT = 863, 3741 PseudoMULTu = 864, 3742 PseudoSDIV_SDIV = 865, 3743 PseudoUDIV_UDIV = 866, 3744 PseudoMFHI_MM_PseudoMFLO_MM = 867, 3745 PseudoMTLOHI_MM = 868, 3746 MUH = 869, 3747 MUHU = 870, 3748 MULU = 871, 3749 MUL_R6 = 872, 3750 MOD = 873, 3751 MODU = 874, 3752 MultRxRy16_MultuRxRy16_MultRxRyRz16_MultuRxRyRz16 = 875, 3753 DivRxRy16 = 876, 3754 DivuRxRy16 = 877, 3755 MULT_MM = 878, 3756 MULTu_MM = 879, 3757 MADD_MM = 880, 3758 MADDU_MM = 881, 3759 MSUB_MM = 882, 3760 MSUBU_MM = 883, 3761 MUL_MM = 884, 3762 SDIV_MM_SDIV_MM_Pseudo = 885, 3763 UDIV_MM_UDIV_MM_Pseudo = 886, 3764 MFHI16_MM_MFLO16_MM_MFHI_MM_MFLO_MM = 887, 3765 MOVF_I_MM = 888, 3766 MOVT_I_MM = 889, 3767 MTHI_MM_MTLO_MM = 890, 3768 RDHWR_MM = 891, 3769 MUHU_MMR6 = 892, 3770 MUH_MMR6 = 893, 3771 MULU_MMR6 = 894, 3772 MUL_MMR6 = 895, 3773 MODU_MMR6 = 896, 3774 MOD_MMR6 = 897, 3775 DIVU_MMR6 = 898, 3776 DIV_MMR6 = 899, 3777 RDHWR_MMR6 = 900, 3778 DMULU = 901, 3779 DMULT_PseudoDMULT = 902, 3780 DMULTu_PseudoDMULTu = 903, 3781 DSDIV_PseudoDSDIV = 904, 3782 DUDIV_PseudoDUDIV = 905, 3783 MFHI64_MFLO64_PseudoMFHI64_PseudoMFLO64 = 906, 3784 PseudoMTLOHI64 = 907, 3785 MTHI64_MTLO64 = 908, 3786 RDHWR64 = 909, 3787 MOVN_I_I64_MOVN_I64_I_MOVN_I64_I64 = 910, 3788 MOVZ_I_I64_MOVZ_I64_I_MOVZ_I64_I64 = 911, 3789 DMUH = 912, 3790 DMUHU = 913, 3791 DMUL_R6 = 914, 3792 DDIV = 915, 3793 DMOD = 916, 3794 DDIVU = 917, 3795 DMODU = 918, 3796 BAL_BR_BLTZAL = 919, 3797 BEQ_BNE = 920, 3798 BGTZ_BGEZ_BLEZ_BLTZ = 921, 3799 J = 922, 3800 JR = 923, 3801 ERet = 924, 3802 BGEZAL = 925, 3803 BALC = 926, 3804 BEQZALC_BGEZALC_BGTZALC_BLEZALC_BLTZALC_BNEZALC = 927, 3805 JIALC = 928, 3806 BC = 929, 3807 BC2EQZ_BC2NEZ = 930, 3808 BEQC_BGEC_BGEUC_BLTC_BLTUC_BNEC_BNVC_BOVC = 931, 3809 BEQZC_BGEZC_BGTZC_BLEZC_BLTZC_BNEZC = 932, 3810 JIC = 933, 3811 JR_HB_R6 = 934, 3812 SIGRIE = 935, 3813 PseudoIndirectBranchR6_PseudoIndrectHazardBranchR6 = 936, 3814 TAILCALLR6REG_TAILCALLHBR6REG = 937, 3815 SDBBP_R6 = 938, 3816 Bimm16_BimmX16_BeqzRxImm16_BeqzRxImmX16_BnezRxImm16_BnezRxImmX16_Bteqz16_BteqzX16_Btnez16_BtnezX16_JrRa16_JrcRa16_JrcRx16 = 939, 3817 BteqzT8CmpX16_BteqzT8CmpiX16_BteqzT8SltX16_BteqzT8SltuX16_BteqzT8SltiX16_BteqzT8SltiuX16_BtnezT8CmpX16_BtnezT8CmpiX16_BtnezT8SltX16_BtnezT8SltuX16_BtnezT8SltiX16_BtnezT8SltiuX16_RetRA16 = 940, 3818 Jal16_JalB16 = 941, 3819 JumpLinkReg16 = 942, 3820 Break16 = 943, 3821 SelBeqZ_SelTBteqZCmp_SelTBteqZCmpi_SelTBteqZSlt_SelTBteqZSlti_SelTBteqZSltu_SelTBteqZSltiu_SelBneZ_SelTBtneZCmp_SelTBtneZCmpi_SelTBtneZSlt_SelTBtneZSlti_SelTBtneZSltu_SelTBtneZSltiu = 944, 3822 B16_MM_B_MM = 945, 3823 BAL_BR_MM = 946, 3824 BC1F_MM = 947, 3825 BC1T_MM = 948, 3826 BEQZ16_MM_BGEZ_MM_BGTZ_MM_BLEZ_MM_BLTZ_MM_BNEZ16_MM = 949, 3827 BEQZC_MM_BNEZC_MM = 950, 3828 BEQ_MM_BNE_MM = 951, 3829 DERET_MM = 952, 3830 ERET_MM = 953, 3831 JR16_MM_JR_MM = 954, 3832 J_MM = 955, 3833 B_MM_Pseudo = 956, 3834 BGEZALS_MM_BLTZALS_MM = 957, 3835 BGEZAL_MM_BLTZAL_MM = 958, 3836 JALR16_MM_JALR_MM = 959, 3837 JALRS16_MM_JALRS_MM = 960, 3838 JALS_MM = 961, 3839 JALX_MM_JAL_MM = 962, 3840 TAILCALLREG_MM = 963, 3841 TAILCALL_MM = 964, 3842 PseudoIndirectBranch_MM = 965, 3843 BREAK16_MM_BREAK_MM = 966, 3844 SDBBP16_MM_SDBBP_MM = 967, 3845 SYSCALL_MM = 968, 3846 TEQI_MM = 969, 3847 TEQ_MM = 970, 3848 TGEIU_MM = 971, 3849 TGEI_MM = 972, 3850 TGEU_MM = 973, 3851 TGE_MM = 974, 3852 TLTIU_MM = 975, 3853 TLTI_MM = 976, 3854 TLTU_MM = 977, 3855 TLT_MM = 978, 3856 TNEI_MM = 979, 3857 TNE_MM = 980, 3858 TRAP_MM = 981, 3859 BC16_MMR6_BC_MMR6 = 982, 3860 BC1EQZC_MMR6_BC1NEZC_MMR6 = 983, 3861 BC2EQZC_MMR6_BC2NEZC_MMR6 = 984, 3862 BEQC_MMR6_BGEC_MMR6_BGEUC_MMR6_BLTC_MMR6_BLTUC_MMR6_BNEC_MMR6_BNVC_MMR6_BOVC_MMR6 = 985, 3863 BEQZC16_MMR6_BNEZC16_MMR6 = 986, 3864 BEQZC_MMR6_BGEZC_MMR6_BGTZC_MMR6_BLEZC_MMR6_BLTZC_MMR6_BNEZC_MMR6 = 987, 3865 DERET_MMR6 = 988, 3866 ERETNC_MMR6 = 989, 3867 JAL_MMR6 = 990, 3868 ERET_MMR6 = 991, 3869 JIC_MMR6 = 992, 3870 JRADDIUSP_JRCADDIUSP_MMR6 = 993, 3871 JRC16_MM = 994, 3872 JRC16_MMR6 = 995, 3873 SIGRIE_MMR6 = 996, 3874 B_MMR6_Pseudo = 997, 3875 PseudoIndirectBranch_MMR6 = 998, 3876 BALC_MMR6 = 999, 3877 BEQZALC_MMR6_BGEZALC_MMR6_BGTZALC_MMR6_BLEZALC_MMR6_BLTZALC_MMR6_BNEZALC_MMR6 = 1000, 3878 JALRC16_MMR6 = 1001, 3879 JALRC_HB_MMR6 = 1002, 3880 JALRC_MMR6 = 1003, 3881 JIALC_MMR6 = 1004, 3882 TAILCALLREG_MMR6 = 1005, 3883 TAILCALL_MMR6 = 1006, 3884 BREAK16_MMR6_BREAK_MMR6 = 1007, 3885 SDBBP_MMR6_SDBBP16_MMR6 = 1008, 3886 BEQ64_BNE64 = 1009, 3887 BGEZ64_BGTZ64_BLEZ64_BLTZ64 = 1010, 3888 JR64 = 1011, 3889 JALR64_JALR64Pseudo_JALRHB64Pseudo = 1012, 3890 JALR_HB64 = 1013, 3891 JR_HB64 = 1014, 3892 TAILCALLREG64_TAILCALLREGHB64 = 1015, 3893 PseudoReturn64 = 1016, 3894 BEQC64_BGEC64_BGEUC64_BLTC64_BLTUC64_BNEC64 = 1017, 3895 BEQZC64_BGEZC64_BGTZC64_BLEZC64_BLTZC64_BNEZC64 = 1018, 3896 JIC64 = 1019, 3897 PseudoIndirectBranch64_PseudoIndirectHazardBranch64 = 1020, 3898 JIALC64 = 1021, 3899 JR_HB64_R6 = 1022, 3900 TAILCALL64R6REG_TAILCALLHB64R6REG = 1023, 3901 PseudoIndirectBranch64R6_PseudoIndrectHazardBranch64R6 = 1024, 3902 EVP = 1025, 3903 DVP = 1026, 3904 TLBP_MM = 1027, 3905 TLBR_MM = 1028, 3906 TLBWI_MM = 1029, 3907 TLBWR_MM = 1030, 3908 DI_MM = 1031, 3909 EI_MM = 1032, 3910 EHB_MM = 1033, 3911 PAUSE_MM = 1034, 3912 WAIT_MM = 1035, 3913 RDPGPR_MMR6 = 1036, 3914 WRPGPR_MMR6 = 1037, 3915 TLBINV_MMR6 = 1038, 3916 TLBINVF_MMR6 = 1039, 3917 MFHC0_MMR6 = 1040, 3918 MFC0_MMR6 = 1041, 3919 MFHC2_MMR6_MFC2_MMR6 = 1042, 3920 MTHC0_MMR6 = 1043, 3921 MTC0_MMR6 = 1044, 3922 MTHC2_MMR6_MTC2_MMR6 = 1045, 3923 EVP_MMR6 = 1046, 3924 DVP_MMR6 = 1047, 3925 DI_MMR6 = 1048, 3926 EI_MMR6 = 1049, 3927 EHB_MMR6 = 1050, 3928 PAUSE_MMR6 = 1051, 3929 WAIT_MMR6 = 1052, 3930 DMFC0 = 1053, 3931 DMTC0 = 1054, 3932 DMFC2 = 1055, 3933 DMTC2 = 1056, 3934 CFC2_MM = 1057, 3935 CTC2_MM = 1058, 3936 DMT = 1059, 3937 DVPE = 1060, 3938 EMT = 1061, 3939 EVPE = 1062, 3940 MFTR = 1063, 3941 MTTR = 1064, 3942 YIELD = 1065, 3943 FORK = 1066, 3944 DMFGC0 = 1067, 3945 DMTGC0 = 1068, 3946 HYPCALL_MM = 1069, 3947 TLBGINVF_MM = 1070, 3948 TLBGINV_MM = 1071, 3949 TLBGP_MM = 1072, 3950 TLBGR_MM = 1073, 3951 TLBGWI_MM = 1074, 3952 TLBGWR_MM = 1075, 3953 MFGC0_MM = 1076, 3954 MFHGC0_MM = 1077, 3955 MTGC0_MM = 1078, 3956 MTHGC0_MM = 1079, 3957 SC_MMR6 = 1080, 3958 LDC2_R6 = 1081, 3959 LL_R6 = 1082, 3960 LWC2_R6 = 1083, 3961 SWC2_R6 = 1084, 3962 SDC2_R6 = 1085, 3963 SC_R6 = 1086, 3964 PREF_R6 = 1087, 3965 CACHE_R6 = 1088, 3966 GINVI = 1089, 3967 GINVT = 1090, 3968 LBE_MM = 1091, 3969 LBuE_MM = 1092, 3970 LHE_MM = 1093, 3971 LHuE_MM = 1094, 3972 LWE_MM = 1095, 3973 LWLE_MM = 1096, 3974 LWRE_MM = 1097, 3975 LLE_MM = 1098, 3976 SBE_MM = 1099, 3977 SB_MM = 1100, 3978 SHE_MM = 1101, 3979 SWE_MM = 1102, 3980 SWLE_MM = 1103, 3981 SWRE_MM = 1104, 3982 SCE_MM = 1105, 3983 PREFE_MM = 1106, 3984 CACHEE_MM = 1107, 3985 Restore16_RestoreX16 = 1108, 3986 LbRxRyOffMemX16 = 1109, 3987 LbuRxRyOffMemX16 = 1110, 3988 LhRxRyOffMemX16 = 1111, 3989 LhuRxRyOffMemX16 = 1112, 3990 LwRxRyOffMemX16_LwRxSpImmX16_LwRxPcTcp16_LwRxPcTcpX16 = 1113, 3991 Save16_SaveX16 = 1114, 3992 SbRxRyOffMemX16 = 1115, 3993 ShRxRyOffMemX16 = 1116, 3994 SwRxRyOffMemX16_SwRxSpImmX16 = 1117, 3995 LBU16_MM_LBu_MM = 1118, 3996 LB_MM = 1119, 3997 LHU16_MM_LHu_MM = 1120, 3998 LH_MM = 1121, 3999 LL_MM = 1122, 4000 LW16_MM_LWGP_MM_LWSP_MM_LW_MM = 1123, 4001 LWL_MM = 1124, 4002 LWM16_MM_LWM32_MM = 1125, 4003 LWP_MM = 1126, 4004 LWR_MM = 1127, 4005 LWU_MM = 1128, 4006 LWXS_MM = 1129, 4007 SB16_MM = 1130, 4008 SC_MM = 1131, 4009 SH16_MM_SH_MM = 1132, 4010 SW16_MM_SWSP_MM_SW_MM = 1133, 4011 SWL_MM = 1134, 4012 SWM16_MM_SWM32_MM = 1135, 4013 SWM_MM = 1136, 4014 SWP_MM = 1137, 4015 SWR_MM = 1138, 4016 PREF_MM_PREFX_MM = 1139, 4017 CACHE_MM = 1140, 4018 SYNC_MM = 1141, 4019 SYNCI_MM = 1142, 4020 GINVI_MMR6 = 1143, 4021 GINVT_MMR6 = 1144, 4022 LBU_MMR6 = 1145, 4023 LB_MMR6 = 1146, 4024 LDC2_MMR6 = 1147, 4025 LL_MMR6 = 1148, 4026 LWM16_MMR6 = 1149, 4027 LWC2_MMR6 = 1150, 4028 LWPC_MMR6 = 1151, 4029 LW_MMR6 = 1152, 4030 SB16_MMR6_SB_MMR6 = 1153, 4031 SDC2_MMR6 = 1154, 4032 SH16_MMR6_SH_MMR6 = 1155, 4033 SW16_MMR6_SWSP_MMR6_SW_MMR6 = 1156, 4034 SWC2_MMR6 = 1157, 4035 SWM16_MMR6 = 1158, 4036 SYNC_MMR6 = 1159, 4037 SYNCI_MMR6 = 1160, 4038 PREF_MMR6 = 1161, 4039 CACHE_MMR6 = 1162, 4040 LD = 1163, 4041 LL64_LLD = 1164, 4042 LWu = 1165, 4043 LB64 = 1166, 4044 LBu64 = 1167, 4045 LH64 = 1168, 4046 LHu64 = 1169, 4047 LW64 = 1170, 4048 LWL64 = 1171, 4049 LWR64 = 1172, 4050 LDL = 1173, 4051 LDR = 1174, 4052 SD = 1175, 4053 SC64_SCD = 1176, 4054 SB64 = 1177, 4055 SH64 = 1178, 4056 SW64 = 1179, 4057 SWL64 = 1180, 4058 SWR64 = 1181, 4059 SDL = 1182, 4060 SDR = 1183, 4061 LWUPC = 1184, 4062 LDPC = 1185, 4063 LLD_R6 = 1186, 4064 LL64_R6 = 1187, 4065 SC64_R6 = 1188, 4066 SCD_R6 = 1189, 4067 CRC32B = 1190, 4068 CRC32H = 1191, 4069 CRC32W = 1192, 4070 CRC32CB = 1193, 4071 CRC32CH = 1194, 4072 CRC32CW = 1195, 4073 CRC32D = 1196, 4074 CRC32CD = 1197, 4075 BADDu = 1198, 4076 BBIT0_BBIT032_BBIT1_BBIT132 = 1199, 4077 CINS_CINS32_CINS64_32_CINS_i32 = 1200, 4078 DMFC2_OCTEON = 1201, 4079 DMTC2_OCTEON = 1202, 4080 DPOP_POP = 1203, 4081 EXTS_EXTS32 = 1204, 4082 MTM0_MTM1_MTM2_MTP0_MTP1_MTP2 = 1205, 4083 SEQ_SNE = 1206, 4084 SEQi_SNEi = 1207, 4085 V3MULU_VMM0_VMULU = 1208, 4086 DMUL = 1209, 4087 SAA_SAAD = 1210, 4088 ADDR_PS64 = 1211, 4089 CVT_PS_PW64_CVT_PW_PS64 = 1212, 4090 MULR_PS64 = 1213, 4091 PseudoTRUNC_W_D_PseudoTRUNC_W_D32_PseudoTRUNC_W_S = 1214, 4092 MOVT_I64 = 1215, 4093 MOVF_I64 = 1216, 4094 MOVZ_I64_S = 1217, 4095 MOVN_I64_D64 = 1218, 4096 MOVN_I64_S = 1219, 4097 MOVZ_I64_D64 = 1220, 4098 SELEQZ_S_SELNEZ_S = 1221, 4099 SELEQZ_D_SELNEZ_D = 1222, 4100 MAX_S_MAXA_S = 1223, 4101 MAX_D_MAXA_D = 1224, 4102 MIN_S_MINA_D = 1225, 4103 MIN_D_MINA_S = 1226, 4104 CLASS_S = 1227, 4105 CLASS_D = 1228, 4106 RINT_S = 1229, 4107 RINT_D = 1230, 4108 BC1EQZ_BC1NEZ = 1231, 4109 SEL_D = 1232, 4110 SEL_S = 1233, 4111 MADDF_S = 1234, 4112 MSUBF_S = 1235, 4113 MADDF_D = 1236, 4114 MSUBF_D = 1237, 4115 MOVF_D32_MM = 1238, 4116 MOVF_S_MM = 1239, 4117 MOVN_I_D32_MM = 1240, 4118 MOVN_I_S_MM = 1241, 4119 MOVT_D32_MM = 1242, 4120 MOVT_S_MM = 1243, 4121 MOVZ_I_D32_MM = 1244, 4122 MOVZ_I_S_MM = 1245, 4123 CVT_D32_S_MM_CVT_D32_W_MM_CVT_D64_S_MM_CVT_D64_W_MM_CVT_L_D64_MM_CVT_L_S_MM_CVT_S_D32_MM_CVT_S_D64_MM_CVT_S_W_MM_CVT_W_D32_MM_CVT_W_D64_MM_CVT_W_S_MM = 1246, 4124 CEIL_W_MM_CEIL_W_S_MM = 1247, 4125 FLOOR_W_MM_FLOOR_W_S_MM = 1248, 4126 NMADD_S_MM = 1249, 4127 NMADD_D32_MM = 1250, 4128 NMSUB_S_MM = 1251, 4129 NMSUB_D32_MM = 1252, 4130 MADD_S_MM = 1253, 4131 MADD_D32_MM = 1254, 4132 ROUND_W_MM_ROUND_W_S_MM = 1255, 4133 TRUNC_W_MM_TRUNC_W_S_MM = 1256, 4134 C_F_D32_MM_C_F_D64_MM = 1257, 4135 C_F_S_MM = 1258, 4136 C_EQ_D32_MM_C_EQ_D64_MM_C_LE_D32_MM_C_LE_D64_MM_C_LT_D32_MM_C_LT_D64_MM_C_SF_D32_MM_C_SF_D64_MM_C_UN_D32_MM_C_UN_D64_MM = 1259, 4137 C_EQ_S_MM_C_LE_S_MM_C_LT_S_MM_C_SF_S_MM_C_UN_S_MM = 1260, 4138 C_NGE_D32_MM_C_NGE_D64_MM_C_NGL_D32_MM_C_NGL_D64_MM_C_NGT_D32_MM_C_NGT_D64_MM_C_OLE_D32_MM_C_OLE_D64_MM_C_OLT_D32_MM_C_OLT_D64_MM_C_SEQ_D32_MM_C_SEQ_D64_MM_C_UEQ_D32_MM_C_UEQ_D64_MM_C_ULE_D32_MM_C_ULE_D64_MM_C_ULT_D32_MM_C_ULT_D64_MM = 1261, 4139 C_NGE_S_MM_C_NGL_S_MM_C_NGT_S_MM_C_OLE_S_MM_C_OLT_S_MM_C_SEQ_S_MM_C_UEQ_S_MM_C_ULE_S_MM_C_ULT_S_MM = 1262, 4140 C_NGLE_D32_MM_C_NGLE_D64_MM = 1263, 4141 C_NGLE_S_MM = 1264, 4142 FCMP_S32_MM = 1265, 4143 FCMP_D32_MM = 1266, 4144 MFC1_MM = 1267, 4145 MFHC1_D32_MM_MFHC1_D64_MM = 1268, 4146 MTC1_MM_MTC1_D64_MM = 1269, 4147 MTHC1_D32_MM_MTHC1_D64_MM = 1270, 4148 FABS_D32_MM_FABS_D64_MM = 1271, 4149 FABS_S_MM = 1272, 4150 FNEG_D32_MM_FNEG_D64_MM_FNEG_S_MM = 1273, 4151 FADD_D32_MM_FADD_D64_MM = 1274, 4152 FADD_S_MM = 1275, 4153 FMOV_D32_MM_FMOV_D64_MM = 1276, 4154 FMOV_S_MM = 1277, 4155 FMUL_D32_MM_FMUL_D64_MM = 1278, 4156 FMUL_S_MM = 1279, 4157 FSUB_D32_MM_FSUB_D64_MM = 1280, 4158 FSUB_S_MM = 1281, 4159 MSUB_S_MM = 1282, 4160 MSUB_D32_MM = 1283, 4161 FDIV_S_MM = 1284, 4162 FDIV_D32_MM_FDIV_D64_MM = 1285, 4163 FSQRT_S_MM = 1286, 4164 FSQRT_D32_MM_FSQRT_D64_MM = 1287, 4165 RECIP_S_MM_RSQRT_S_MM = 1288, 4166 RECIP_D32_MM_RECIP_D64_MM_RSQRT_D32_MM_RSQRT_D64_MM = 1289, 4167 SDC1_MM_D32_SDC1_MM_D64 = 1290, 4168 SWC1_MM = 1291, 4169 SUXC1_MM = 1292, 4170 SWXC1_MM = 1293, 4171 CFC1_MM = 1294, 4172 CTC1_MM = 1295, 4173 LDC1_MM_D32_LDC1_MM_D64 = 1296, 4174 LUXC1_MM = 1297, 4175 LWC1_MM = 1298, 4176 LWXC1_MM = 1299, 4177 FNEG_S_MMR6 = 1300, 4178 CMP_AF_D_MMR6_CMP_EQ_D_MMR6_CMP_LE_D_MMR6_CMP_LT_D_MMR6_CMP_UN_D_MMR6 = 1301, 4179 CMP_AF_S_MMR6_CMP_EQ_S_MMR6_CMP_LE_S_MMR6_CMP_LT_S_MMR6_CMP_UN_S_MMR6 = 1302, 4180 CMP_SAF_D_MMR6_CMP_SEQ_D_MMR6_CMP_SLE_D_MMR6_CMP_SLT_D_MMR6_CMP_SUN_D_MMR6_CMP_UEQ_D_MMR6_CMP_ULE_D_MMR6_CMP_ULT_D_MMR6 = 1303, 4181 CMP_SAF_S_MMR6_CMP_SEQ_S_MMR6_CMP_SLE_S_MMR6_CMP_SLT_S_MMR6_CMP_SUN_S_MMR6_CMP_UEQ_S_MMR6_CMP_ULE_S_MMR6_CMP_ULT_S_MMR6 = 1304, 4182 CMP_SUEQ_D_MMR6_CMP_SULE_D_MMR6_CMP_SULT_D_MMR6 = 1305, 4183 CMP_SUEQ_S_MMR6_CMP_SULE_S_MMR6_CMP_SULT_S_MMR6 = 1306, 4184 CVT_D_L_MMR6_CVT_L_D_MMR6_CVT_L_S_MMR6_CVT_S_L_MMR6_CVT_S_W_MMR6_CVT_W_S_MMR6 = 1307, 4185 TRUNC_L_D_MMR6_TRUNC_L_S_MMR6_TRUNC_W_D_MMR6_TRUNC_W_S_MMR6 = 1308, 4186 ROUND_L_D_MMR6_ROUND_L_S_MMR6_ROUND_W_D_MMR6_ROUND_W_S_MMR6 = 1309, 4187 FLOOR_L_D_MMR6_FLOOR_L_S_MMR6_FLOOR_W_D_MMR6_FLOOR_W_S_MMR6 = 1310, 4188 CEIL_L_D_MMR6_CEIL_L_S_MMR6_CEIL_W_D_MMR6_CEIL_W_S_MMR6 = 1311, 4189 MFC1_MMR6 = 1312, 4190 MTC1_MMR6 = 1313, 4191 CLASS_S_MMR6_CLASS_D_MMR6 = 1314, 4192 FADD_S_MMR6 = 1315, 4193 MAX_D_MMR6 = 1316, 4194 MAX_S_MMR6 = 1317, 4195 MIN_D_MMR6 = 1318, 4196 MIN_S_MMR6 = 1319, 4197 MAXA_D_MMR6 = 1320, 4198 MAXA_S_MMR6 = 1321, 4199 MINA_D_MMR6 = 1322, 4200 MINA_S_MMR6 = 1323, 4201 SELEQZ_D_MMR6_SELNEZ_D_MMR6 = 1324, 4202 SELEQZ_S_MMR6_SELNEZ_S_MMR6 = 1325, 4203 SEL_D_MMR6 = 1326, 4204 SEL_S_MMR6 = 1327, 4205 RINT_S_MMR6_RINT_D_MMR6 = 1328, 4206 MADDF_D_MMR6 = 1329, 4207 MADDF_S_MMR6 = 1330, 4208 MSUBF_D_MMR6 = 1331, 4209 MSUBF_S_MMR6 = 1332, 4210 FMOV_S_MMR6 = 1333, 4211 FMUL_S_MMR6 = 1334, 4212 FSUB_S_MMR6 = 1335, 4213 FMOV_D_MMR6 = 1336, 4214 FDIV_S_MMR6 = 1337, 4215 SDC1_D64_MMR6 = 1338, 4216 LDC1_D64_MMR6 = 1339, 4217 DMFC1 = 1340, 4218 DMTC1 = 1341, 4219 SWDSP = 1342, 4220 LWDSP = 1343, 4221 PseudoMTLOHI_DSP = 1344, 4222 EXTRV_RS_W = 1345, 4223 EXTRV_R_W = 1346, 4224 EXTRV_S_H = 1347, 4225 EXTRV_W = 1348, 4226 EXTR_RS_W = 1349, 4227 EXTR_R_W = 1350, 4228 EXTR_S_H = 1351, 4229 EXTR_W = 1352, 4230 INSV = 1353, 4231 MTHLIP = 1354, 4232 MTHI_DSP = 1355, 4233 MTLO_DSP = 1356, 4234 ABSQ_S_PH = 1357, 4235 ABSQ_S_W = 1358, 4236 ADDQ_PH = 1359, 4237 ADDQ_S_PH = 1360, 4238 ADDQ_S_W = 1361, 4239 ADDSC = 1362, 4240 ADDU_QB = 1363, 4241 ADDU_S_QB = 1364, 4242 ADDWC = 1365, 4243 BITREV = 1366, 4244 BPOSGE32 = 1367, 4245 CMPGU_EQ_QB = 1368, 4246 CMPGU_LE_QB = 1369, 4247 CMPGU_LT_QB = 1370, 4248 CMPU_EQ_QB = 1371, 4249 CMPU_LE_QB = 1372, 4250 CMPU_LT_QB = 1373, 4251 CMP_EQ_PH = 1374, 4252 CMP_LE_PH = 1375, 4253 CMP_LT_PH = 1376, 4254 DPAQ_SA_L_W = 1377, 4255 DPAQ_S_W_PH = 1378, 4256 DPAU_H_QBL = 1379, 4257 DPAU_H_QBR = 1380, 4258 DPSQ_SA_L_W = 1381, 4259 DPSQ_S_W_PH = 1382, 4260 DPSU_H_QBL = 1383, 4261 DPSU_H_QBR = 1384, 4262 EXTPDPV = 1385, 4263 EXTPDP = 1386, 4264 EXTPV = 1387, 4265 EXTP = 1388, 4266 LBUX = 1389, 4267 LHX = 1390, 4268 LWX = 1391, 4269 MADDU_DSP = 1392, 4270 MADD_DSP = 1393, 4271 MAQ_SA_W_PHL = 1394, 4272 MAQ_SA_W_PHR = 1395, 4273 MAQ_S_W_PHL = 1396, 4274 MAQ_S_W_PHR = 1397, 4275 MFHI_DSP = 1398, 4276 MFLO_DSP = 1399, 4277 MODSUB = 1400, 4278 MSUBU_DSP = 1401, 4279 MSUB_DSP = 1402, 4280 MULEQ_S_W_PHL = 1403, 4281 MULEQ_S_W_PHR = 1404, 4282 MULEU_S_PH_QBL = 1405, 4283 MULEU_S_PH_QBR = 1406, 4284 MULQ_RS_PH = 1407, 4285 MULSAQ_S_W_PH = 1408, 4286 MULTU_DSP = 1409, 4287 MULT_DSP = 1410, 4288 PACKRL_PH = 1411, 4289 PICK_PH = 1412, 4290 PICK_QB = 1413, 4291 PRECEQU_PH_QBLA = 1414, 4292 PRECEQU_PH_QBL = 1415, 4293 PRECEQU_PH_QBRA = 1416, 4294 PRECEQU_PH_QBR = 1417, 4295 PRECEQ_W_PHL = 1418, 4296 PRECEQ_W_PHR = 1419, 4297 PRECEU_PH_QBLA = 1420, 4298 PRECEU_PH_QBL = 1421, 4299 PRECEU_PH_QBRA = 1422, 4300 PRECEU_PH_QBR = 1423, 4301 PRECRQU_S_QB_PH = 1424, 4302 PRECRQ_PH_W = 1425, 4303 PRECRQ_QB_PH = 1426, 4304 PRECRQ_RS_PH_W = 1427, 4305 RADDU_W_QB = 1428, 4306 RDDSP = 1429, 4307 REPLV_PH = 1430, 4308 REPLV_QB = 1431, 4309 REPL_PH = 1432, 4310 REPL_QB = 1433, 4311 SHILOV = 1434, 4312 SHILO = 1435, 4313 SHLLV_PH = 1436, 4314 SHLLV_QB = 1437, 4315 SHLLV_S_PH = 1438, 4316 SHLLV_S_W = 1439, 4317 SHLL_PH = 1440, 4318 SHLL_QB = 1441, 4319 SHLL_S_PH = 1442, 4320 SHLL_S_W = 1443, 4321 SHRAV_PH = 1444, 4322 SHRAV_R_PH = 1445, 4323 SHRAV_R_W = 1446, 4324 SHRA_PH = 1447, 4325 SHRA_R_PH = 1448, 4326 SHRA_R_W = 1449, 4327 SHRLV_QB = 1450, 4328 SHRL_QB = 1451, 4329 SUBQ_PH = 1452, 4330 SUBQ_S_PH = 1453, 4331 SUBQ_S_W = 1454, 4332 SUBU_QB = 1455, 4333 SUBU_S_QB = 1456, 4334 WRDSP = 1457, 4335 PseudoCMPU_EQ_QB_PseudoCMPU_LE_QB_PseudoCMPU_LT_QB_PseudoCMP_EQ_PH_PseudoCMP_LE_PH_PseudoCMP_LT_PH = 1458, 4336 PseudoPICK_PH_PseudoPICK_QB = 1459, 4337 ABSQ_S_QB = 1460, 4338 ADDQH_PH = 1461, 4339 ADDQH_R_PH = 1462, 4340 ADDQH_R_W = 1463, 4341 ADDQH_W = 1464, 4342 ADDUH_QB = 1465, 4343 ADDUH_R_QB = 1466, 4344 ADDU_PH = 1467, 4345 ADDU_S_PH = 1468, 4346 APPEND = 1469, 4347 BALIGN = 1470, 4348 CMPGDU_EQ_QB = 1471, 4349 CMPGDU_LE_QB = 1472, 4350 CMPGDU_LT_QB = 1473, 4351 DPA_W_PH = 1474, 4352 DPAQX_SA_W_PH = 1475, 4353 DPAQX_S_W_PH = 1476, 4354 DPAX_W_PH = 1477, 4355 DPS_W_PH = 1478, 4356 DPSQX_S_W_PH = 1479, 4357 DPSQX_SA_W_PH = 1480, 4358 DPSX_W_PH = 1481, 4359 MUL_PH = 1482, 4360 MUL_S_PH = 1483, 4361 MULQ_RS_W = 1484, 4362 MULQ_S_PH = 1485, 4363 MULQ_S_W = 1486, 4364 MULSA_W_PH = 1487, 4365 PRECR_QB_PH = 1488, 4366 PRECR_SRA_PH_W = 1489, 4367 PRECR_SRA_R_PH_W = 1490, 4368 PREPEND = 1491, 4369 SHRA_QB = 1492, 4370 SHRA_R_QB = 1493, 4371 SHRAV_QB = 1494, 4372 SHRAV_R_QB = 1495, 4373 SHRL_PH = 1496, 4374 SHRLV_PH = 1497, 4375 SUBQH_PH = 1498, 4376 SUBQH_R_PH = 1499, 4377 SUBQH_W = 1500, 4378 SUBQH_R_W = 1501, 4379 SUBU_PH = 1502, 4380 SUBU_S_PH = 1503, 4381 SUBUH_QB = 1504, 4382 SUBUH_R_QB = 1505, 4383 LWDSP_MM = 1506, 4384 SWDSP_MM = 1507, 4385 ABSQ_S_PH_MM = 1508, 4386 ABSQ_S_W_MM = 1509, 4387 ADDQ_PH_MM = 1510, 4388 ADDQ_S_PH_MM = 1511, 4389 ADDQ_S_W_MM = 1512, 4390 ADDSC_MM = 1513, 4391 ADDU_QB_MM = 1514, 4392 ADDU_S_QB_MM = 1515, 4393 ADDWC_MM = 1516, 4394 BITREV_MM = 1517, 4395 BPOSGE32_MM = 1518, 4396 CMPGU_EQ_QB_MM = 1519, 4397 CMPGU_LE_QB_MM = 1520, 4398 CMPGU_LT_QB_MM = 1521, 4399 CMPU_EQ_QB_MM = 1522, 4400 CMPU_LE_QB_MM = 1523, 4401 CMPU_LT_QB_MM = 1524, 4402 CMP_EQ_PH_MM = 1525, 4403 CMP_LE_PH_MM = 1526, 4404 CMP_LT_PH_MM = 1527, 4405 DPAQ_SA_L_W_MM = 1528, 4406 DPAQ_S_W_PH_MM = 1529, 4407 DPAU_H_QBL_MM = 1530, 4408 DPAU_H_QBR_MM = 1531, 4409 DPSQ_SA_L_W_MM = 1532, 4410 DPSQ_S_W_PH_MM = 1533, 4411 DPSU_H_QBL_MM = 1534, 4412 DPSU_H_QBR_MM = 1535, 4413 EXTPDPV_MM = 1536, 4414 EXTPDP_MM = 1537, 4415 EXTPV_MM = 1538, 4416 EXTP_MM = 1539, 4417 EXTRV_RS_W_MM = 1540, 4418 EXTRV_R_W_MM = 1541, 4419 EXTRV_S_H_MM = 1542, 4420 EXTRV_W_MM = 1543, 4421 EXTR_RS_W_MM = 1544, 4422 EXTR_R_W_MM = 1545, 4423 EXTR_S_H_MM = 1546, 4424 EXTR_W_MM = 1547, 4425 INSV_MM = 1548, 4426 LBUX_MM = 1549, 4427 LHX_MM = 1550, 4428 LWX_MM = 1551, 4429 MADDU_DSP_MM = 1552, 4430 MADD_DSP_MM = 1553, 4431 MAQ_SA_W_PHL_MM = 1554, 4432 MAQ_SA_W_PHR_MM = 1555, 4433 MAQ_S_W_PHL_MM = 1556, 4434 MAQ_S_W_PHR_MM = 1557, 4435 MFHI_DSP_MM = 1558, 4436 MFLO_DSP_MM = 1559, 4437 MODSUB_MM = 1560, 4438 MOVEP_MMR6 = 1561, 4439 MOVN_I_MM = 1562, 4440 MOVZ_I_MM = 1563, 4441 MSUBU_DSP_MM = 1564, 4442 MSUB_DSP_MM = 1565, 4443 MTHI_DSP_MM = 1566, 4444 MTHLIP_MM = 1567, 4445 MTLO_DSP_MM = 1568, 4446 MULEQ_S_W_PHL_MM = 1569, 4447 MULEQ_S_W_PHR_MM = 1570, 4448 MULEU_S_PH_QBL_MM = 1571, 4449 MULEU_S_PH_QBR_MM = 1572, 4450 MULQ_RS_PH_MM = 1573, 4451 MULSAQ_S_W_PH_MM = 1574, 4452 MULTU_DSP_MM = 1575, 4453 MULT_DSP_MM = 1576, 4454 PACKRL_PH_MM = 1577, 4455 PICK_PH_MM = 1578, 4456 PICK_QB_MM = 1579, 4457 PRECEQU_PH_QBLA_MM = 1580, 4458 PRECEQU_PH_QBL_MM = 1581, 4459 PRECEQU_PH_QBRA_MM = 1582, 4460 PRECEQU_PH_QBR_MM = 1583, 4461 PRECEQ_W_PHL_MM = 1584, 4462 PRECEQ_W_PHR_MM = 1585, 4463 PRECEU_PH_QBLA_MM = 1586, 4464 PRECEU_PH_QBL_MM = 1587, 4465 PRECEU_PH_QBRA_MM = 1588, 4466 PRECEU_PH_QBR_MM = 1589, 4467 PRECRQU_S_QB_PH_MM = 1590, 4468 PRECRQ_PH_W_MM = 1591, 4469 PRECRQ_QB_PH_MM = 1592, 4470 PRECRQ_RS_PH_W_MM = 1593, 4471 RADDU_W_QB_MM = 1594, 4472 RDDSP_MM = 1595, 4473 REPLV_PH_MM = 1596, 4474 REPLV_QB_MM = 1597, 4475 REPL_PH_MM = 1598, 4476 REPL_QB_MM = 1599, 4477 SHILOV_MM = 1600, 4478 SHILO_MM = 1601, 4479 SHLLV_PH_MM = 1602, 4480 SHLLV_QB_MM = 1603, 4481 SHLLV_S_PH_MM = 1604, 4482 SHLLV_S_W_MM = 1605, 4483 SHLL_PH_MM = 1606, 4484 SHLL_QB_MM = 1607, 4485 SHLL_S_PH_MM = 1608, 4486 SHLL_S_W_MM = 1609, 4487 SHRAV_PH_MM = 1610, 4488 SHRAV_R_PH_MM = 1611, 4489 SHRAV_R_W_MM = 1612, 4490 SHRA_PH_MM = 1613, 4491 SHRA_R_PH_MM = 1614, 4492 SHRA_R_W_MM = 1615, 4493 SHRLV_QB_MM = 1616, 4494 SHRL_QB_MM = 1617, 4495 SUBQ_PH_MM = 1618, 4496 SUBQ_S_PH_MM = 1619, 4497 SUBQ_S_W_MM = 1620, 4498 SUBU_QB_MM = 1621, 4499 SUBU_S_QB_MM = 1622, 4500 WRDSP_MM = 1623, 4501 ABSQ_S_QB_MMR2 = 1624, 4502 ADDQH_PH_MMR2 = 1625, 4503 ADDQH_R_PH_MMR2 = 1626, 4504 ADDQH_R_W_MMR2 = 1627, 4505 ADDQH_W_MMR2 = 1628, 4506 ADDUH_QB_MMR2 = 1629, 4507 ADDUH_R_QB_MMR2 = 1630, 4508 ADDU_PH_MMR2 = 1631, 4509 ADDU_S_PH_MMR2 = 1632, 4510 APPEND_MMR2 = 1633, 4511 BALIGN_MMR2 = 1634, 4512 CMPGDU_EQ_QB_MMR2 = 1635, 4513 CMPGDU_LE_QB_MMR2 = 1636, 4514 CMPGDU_LT_QB_MMR2 = 1637, 4515 DPA_W_PH_MMR2 = 1638, 4516 DPAQX_SA_W_PH_MMR2 = 1639, 4517 DPAQX_S_W_PH_MMR2 = 1640, 4518 DPAX_W_PH_MMR2 = 1641, 4519 DPS_W_PH_MMR2 = 1642, 4520 DPSQX_S_W_PH_MMR2 = 1643, 4521 DPSQX_SA_W_PH_MMR2 = 1644, 4522 DPSX_W_PH_MMR2 = 1645, 4523 MUL_PH_MMR2 = 1646, 4524 MUL_S_PH_MMR2 = 1647, 4525 MULQ_RS_W_MMR2 = 1648, 4526 MULQ_S_PH_MMR2 = 1649, 4527 MULQ_S_W_MMR2 = 1650, 4528 MULSA_W_PH_MMR2 = 1651, 4529 PRECR_QB_PH_MMR2 = 1652, 4530 PRECR_SRA_PH_W_MMR2 = 1653, 4531 PRECR_SRA_R_PH_W_MMR2 = 1654, 4532 PREPEND_MMR2 = 1655, 4533 SHRA_QB_MMR2 = 1656, 4534 SHRA_R_QB_MMR2 = 1657, 4535 SHRAV_QB_MMR2 = 1658, 4536 SHRAV_R_QB_MMR2 = 1659, 4537 SHRL_PH_MMR2 = 1660, 4538 SHRLV_PH_MMR2 = 1661, 4539 SUBQH_PH_MMR2 = 1662, 4540 SUBQH_R_PH_MMR2 = 1663, 4541 SUBQH_W_MMR2 = 1664, 4542 SUBQH_R_W_MMR2 = 1665, 4543 SUBU_PH_MMR2 = 1666, 4544 SUBU_S_PH_MMR2 = 1667, 4545 SUBUH_QB_MMR2 = 1668, 4546 SUBUH_R_QB_MMR2 = 1669, 4547 BPOSGE32C_MMR3 = 1670, 4548 CMP_F_D = 1671, 4549 CMP_F_S = 1672, 4550 CMP_SAF_D = 1673, 4551 CMP_SAF_S = 1674, 4552 CMP_SEQ_D = 1675, 4553 CMP_SEQ_S = 1676, 4554 CMP_SLE_D = 1677, 4555 CMP_SLE_S = 1678, 4556 CMP_SLT_D = 1679, 4557 CMP_SLT_S = 1680, 4558 CMP_SUEQ_D = 1681, 4559 CMP_SUEQ_S = 1682, 4560 CMP_SULE_D = 1683, 4561 CMP_SULE_S = 1684, 4562 CMP_SULT_D = 1685, 4563 CMP_SULT_S = 1686, 4564 CMP_SUN_D = 1687, 4565 CMP_SUN_S = 1688, 4566 SCHED_LIST_END = 1689 4567 }; 4568} // end namespace Sched 4569} // end namespace Mips 4570} // end namespace llvm 4571#endif // GET_INSTRINFO_SCHED_ENUM 4572 4573#ifdef GET_INSTRINFO_MC_DESC 4574#undef GET_INSTRINFO_MC_DESC 4575namespace llvm { 4576 4577static const MCPhysReg ImplicitList1[] = { Mips::SP, Mips::SP }; 4578static const MCPhysReg ImplicitList2[] = { Mips::AT }; 4579static const MCPhysReg ImplicitList3[] = { Mips::RA }; 4580static const MCPhysReg ImplicitList4[] = { Mips::DSPPos }; 4581static const MCPhysReg ImplicitList5[] = { Mips::V0, Mips::V1 }; 4582static const MCPhysReg ImplicitList6[] = { Mips::HI0, Mips::LO0 }; 4583static const MCPhysReg ImplicitList7[] = { Mips::T8 }; 4584static const MCPhysReg ImplicitList8[] = { Mips::DSPOutFlag20 }; 4585static const MCPhysReg ImplicitList9[] = { Mips::DSPCarry }; 4586static const MCPhysReg ImplicitList10[] = { Mips::DSPCarry, Mips::DSPOutFlag20 }; 4587static const MCPhysReg ImplicitList11[] = { Mips::DSPCCond }; 4588static const MCPhysReg ImplicitList12[] = { Mips::HI0, Mips::LO0, Mips::P0, Mips::P1, Mips::P2 }; 4589static const MCPhysReg ImplicitList13[] = { Mips::HI0_64, Mips::LO0_64 }; 4590static const MCPhysReg ImplicitList14[] = { Mips::DSPOutFlag16_19 }; 4591static const MCPhysReg ImplicitList15[] = { Mips::DSPPos, Mips::DSPEFI }; 4592static const MCPhysReg ImplicitList16[] = { Mips::DSPPos, Mips::DSPPos, Mips::DSPEFI }; 4593static const MCPhysReg ImplicitList17[] = { Mips::DSPOutFlag23 }; 4594static const MCPhysReg ImplicitList18[] = { Mips::FCC0 }; 4595static const MCPhysReg ImplicitList19[] = { Mips::DSPPos, Mips::DSPSCount }; 4596static const MCPhysReg ImplicitList20[] = { Mips::HI0, Mips::LO0, Mips::HI0, Mips::LO0 }; 4597static const MCPhysReg ImplicitList21[] = { Mips::AC0 }; 4598static const MCPhysReg ImplicitList22[] = { Mips::AC0_64 }; 4599static const MCPhysReg ImplicitList23[] = { Mips::HI0 }; 4600static const MCPhysReg ImplicitList24[] = { Mips::HI0_64 }; 4601static const MCPhysReg ImplicitList25[] = { Mips::LO0 }; 4602static const MCPhysReg ImplicitList26[] = { Mips::LO0_64 }; 4603static const MCPhysReg ImplicitList27[] = { Mips::MPL0, Mips::P0, Mips::P1, Mips::P2 }; 4604static const MCPhysReg ImplicitList28[] = { Mips::MPL1, Mips::P0, Mips::P1, Mips::P2 }; 4605static const MCPhysReg ImplicitList29[] = { Mips::MPL2, Mips::P0, Mips::P1, Mips::P2 }; 4606static const MCPhysReg ImplicitList30[] = { Mips::P0 }; 4607static const MCPhysReg ImplicitList31[] = { Mips::P1 }; 4608static const MCPhysReg ImplicitList32[] = { Mips::P2 }; 4609static const MCPhysReg ImplicitList33[] = { Mips::DSPOutFlag21 }; 4610static const MCPhysReg ImplicitList34[] = { Mips::DSPOutFlag22 }; 4611static const MCPhysReg ImplicitList35[] = { Mips::P0, Mips::P1, Mips::P2 }; 4612static const MCPhysReg ImplicitList36[] = { Mips::MPL1, Mips::MPL2, Mips::P0, Mips::P1, Mips::P2 }; 4613 4614static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4615static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; 4616static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; 4617static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; 4618static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; 4619static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4620static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; 4621static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, }; 4622static const MCOperandInfo OperandInfo10[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; 4623static const MCOperandInfo OperandInfo11[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; 4624static const MCOperandInfo OperandInfo12[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; 4625static const MCOperandInfo OperandInfo13[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; 4626static const MCOperandInfo OperandInfo14[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; 4627static const MCOperandInfo OperandInfo15[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4628static const MCOperandInfo OperandInfo16[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4629static const MCOperandInfo OperandInfo17[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, }; 4630static const MCOperandInfo OperandInfo18[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; 4631static const MCOperandInfo OperandInfo19[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; 4632static const MCOperandInfo OperandInfo20[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; 4633static const MCOperandInfo OperandInfo21[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4634static const MCOperandInfo OperandInfo22[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, }; 4635static const MCOperandInfo OperandInfo23[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, }; 4636static const MCOperandInfo OperandInfo24[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, }; 4637static const MCOperandInfo OperandInfo25[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; 4638static const MCOperandInfo OperandInfo26[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; 4639static const MCOperandInfo OperandInfo27[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4640static const MCOperandInfo OperandInfo28[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4641static const MCOperandInfo OperandInfo29[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; 4642static const MCOperandInfo OperandInfo30[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; 4643static const MCOperandInfo OperandInfo31[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; 4644static const MCOperandInfo OperandInfo32[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4645static const MCOperandInfo OperandInfo33[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, }; 4646static const MCOperandInfo OperandInfo34[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, }; 4647static const MCOperandInfo OperandInfo35[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, }; 4648static const MCOperandInfo OperandInfo36[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, }; 4649static const MCOperandInfo OperandInfo37[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, }; 4650static const MCOperandInfo OperandInfo38[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, }; 4651static const MCOperandInfo OperandInfo39[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, }; 4652static const MCOperandInfo OperandInfo40[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, }; 4653static const MCOperandInfo OperandInfo41[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4654static const MCOperandInfo OperandInfo42[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; 4655static const MCOperandInfo OperandInfo43[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, }; 4656static const MCOperandInfo OperandInfo44[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, }; 4657static const MCOperandInfo OperandInfo45[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4658static const MCOperandInfo OperandInfo46[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4659static const MCOperandInfo OperandInfo47[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4660static const MCOperandInfo OperandInfo48[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4661static const MCOperandInfo OperandInfo49[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4662static const MCOperandInfo OperandInfo50[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4663static const MCOperandInfo OperandInfo51[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4664static const MCOperandInfo OperandInfo52[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4665static const MCOperandInfo OperandInfo53[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4666static const MCOperandInfo OperandInfo54[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4667static const MCOperandInfo OperandInfo55[] = { { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; 4668static const MCOperandInfo OperandInfo56[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; 4669static const MCOperandInfo OperandInfo57[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; 4670static const MCOperandInfo OperandInfo58[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4671static const MCOperandInfo OperandInfo59[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4672static const MCOperandInfo OperandInfo60[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4673static const MCOperandInfo OperandInfo61[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4674static const MCOperandInfo OperandInfo62[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; 4675static const MCOperandInfo OperandInfo63[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; 4676static const MCOperandInfo OperandInfo64[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4677static const MCOperandInfo OperandInfo65[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4678static const MCOperandInfo OperandInfo66[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4679static const MCOperandInfo OperandInfo67[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4680static const MCOperandInfo OperandInfo68[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4681static const MCOperandInfo OperandInfo69[] = { { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4682static const MCOperandInfo OperandInfo70[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4683static const MCOperandInfo OperandInfo71[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4684static const MCOperandInfo OperandInfo72[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4685static const MCOperandInfo OperandInfo73[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4686static const MCOperandInfo OperandInfo74[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; 4687static const MCOperandInfo OperandInfo75[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; 4688static const MCOperandInfo OperandInfo76[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4689static const MCOperandInfo OperandInfo77[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4690static const MCOperandInfo OperandInfo78[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4691static const MCOperandInfo OperandInfo79[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4692static const MCOperandInfo OperandInfo80[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4693static const MCOperandInfo OperandInfo81[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4694static const MCOperandInfo OperandInfo82[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4695static const MCOperandInfo OperandInfo83[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4696static const MCOperandInfo OperandInfo84[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4697static const MCOperandInfo OperandInfo85[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4698static const MCOperandInfo OperandInfo86[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4699static const MCOperandInfo OperandInfo87[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4700static const MCOperandInfo OperandInfo88[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4701static const MCOperandInfo OperandInfo89[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4702static const MCOperandInfo OperandInfo90[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4703static const MCOperandInfo OperandInfo91[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4704static const MCOperandInfo OperandInfo92[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4705static const MCOperandInfo OperandInfo93[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4706static const MCOperandInfo OperandInfo94[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4707static const MCOperandInfo OperandInfo95[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4708static const MCOperandInfo OperandInfo96[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; 4709static const MCOperandInfo OperandInfo97[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4710static const MCOperandInfo OperandInfo98[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4711static const MCOperandInfo OperandInfo99[] = { { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; 4712static const MCOperandInfo OperandInfo100[] = { { Mips::ACC128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; 4713static const MCOperandInfo OperandInfo101[] = { { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; 4714static const MCOperandInfo OperandInfo102[] = { { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; 4715static const MCOperandInfo OperandInfo103[] = { { Mips::DSPCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; 4716static const MCOperandInfo OperandInfo104[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; 4717static const MCOperandInfo OperandInfo105[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; 4718static const MCOperandInfo OperandInfo106[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; 4719static const MCOperandInfo OperandInfo107[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; 4720static const MCOperandInfo OperandInfo108[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; 4721static const MCOperandInfo OperandInfo109[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; 4722static const MCOperandInfo OperandInfo110[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; 4723static const MCOperandInfo OperandInfo111[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; 4724static const MCOperandInfo OperandInfo112[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4725static const MCOperandInfo OperandInfo113[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; 4726static const MCOperandInfo OperandInfo114[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4727static const MCOperandInfo OperandInfo115[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4728static const MCOperandInfo OperandInfo116[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4729static const MCOperandInfo OperandInfo117[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4730static const MCOperandInfo OperandInfo118[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4731static const MCOperandInfo OperandInfo119[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4732static const MCOperandInfo OperandInfo120[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4733static const MCOperandInfo OperandInfo121[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4734static const MCOperandInfo OperandInfo122[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4735static const MCOperandInfo OperandInfo123[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4736static const MCOperandInfo OperandInfo124[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4737static const MCOperandInfo OperandInfo125[] = { { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4738static const MCOperandInfo OperandInfo126[] = { { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4739static const MCOperandInfo OperandInfo127[] = { { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4740static const MCOperandInfo OperandInfo128[] = { { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4741static const MCOperandInfo OperandInfo129[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4742static const MCOperandInfo OperandInfo130[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4743static const MCOperandInfo OperandInfo131[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4744static const MCOperandInfo OperandInfo132[] = { { Mips::DSPCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4745static const MCOperandInfo OperandInfo133[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4746static const MCOperandInfo OperandInfo134[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4747static const MCOperandInfo OperandInfo135[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4748static const MCOperandInfo OperandInfo136[] = { { Mips::ACC128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4749static const MCOperandInfo OperandInfo137[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4750static const MCOperandInfo OperandInfo138[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4751static const MCOperandInfo OperandInfo139[] = { { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; 4752static const MCOperandInfo OperandInfo140[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4753static const MCOperandInfo OperandInfo141[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4754static const MCOperandInfo OperandInfo142[] = { { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4755static const MCOperandInfo OperandInfo143[] = { { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4756static const MCOperandInfo OperandInfo144[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4757static const MCOperandInfo OperandInfo145[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4758static const MCOperandInfo OperandInfo146[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4759static const MCOperandInfo OperandInfo147[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4760static const MCOperandInfo OperandInfo148[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4761static const MCOperandInfo OperandInfo149[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4762static const MCOperandInfo OperandInfo150[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4763static const MCOperandInfo OperandInfo151[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4764static const MCOperandInfo OperandInfo152[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4765static const MCOperandInfo OperandInfo153[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4766static const MCOperandInfo OperandInfo154[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4767static const MCOperandInfo OperandInfo155[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4768static const MCOperandInfo OperandInfo156[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4769static const MCOperandInfo OperandInfo157[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4770static const MCOperandInfo OperandInfo158[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; 4771static const MCOperandInfo OperandInfo159[] = { { Mips::GPR32NONZERORegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4772static const MCOperandInfo OperandInfo160[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4773static const MCOperandInfo OperandInfo161[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4774static const MCOperandInfo OperandInfo162[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4775static const MCOperandInfo OperandInfo163[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4776static const MCOperandInfo OperandInfo164[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4777static const MCOperandInfo OperandInfo165[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4778static const MCOperandInfo OperandInfo166[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4779static const MCOperandInfo OperandInfo167[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4780static const MCOperandInfo OperandInfo168[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4781static const MCOperandInfo OperandInfo169[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4782static const MCOperandInfo OperandInfo170[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4783static const MCOperandInfo OperandInfo171[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4784static const MCOperandInfo OperandInfo172[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4785static const MCOperandInfo OperandInfo173[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4786static const MCOperandInfo OperandInfo174[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4787static const MCOperandInfo OperandInfo175[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4788static const MCOperandInfo OperandInfo176[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4789static const MCOperandInfo OperandInfo177[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4790static const MCOperandInfo OperandInfo178[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4791static const MCOperandInfo OperandInfo179[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4792static const MCOperandInfo OperandInfo180[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4793static const MCOperandInfo OperandInfo181[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; 4794static const MCOperandInfo OperandInfo182[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; 4795static const MCOperandInfo OperandInfo183[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4796static const MCOperandInfo OperandInfo184[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4797static const MCOperandInfo OperandInfo185[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsPlusSPRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4798static const MCOperandInfo OperandInfo186[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4799static const MCOperandInfo OperandInfo187[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; 4800static const MCOperandInfo OperandInfo188[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; 4801static const MCOperandInfo OperandInfo189[] = { { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; 4802static const MCOperandInfo OperandInfo190[] = { { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; 4803static const MCOperandInfo OperandInfo191[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; 4804static const MCOperandInfo OperandInfo192[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4805static const MCOperandInfo OperandInfo193[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4806static const MCOperandInfo OperandInfo194[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4807static const MCOperandInfo OperandInfo195[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4808static const MCOperandInfo OperandInfo196[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4809static const MCOperandInfo OperandInfo197[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; 4810static const MCOperandInfo OperandInfo198[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; 4811static const MCOperandInfo OperandInfo199[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; 4812static const MCOperandInfo OperandInfo200[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; 4813static const MCOperandInfo OperandInfo201[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; 4814static const MCOperandInfo OperandInfo202[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4815static const MCOperandInfo OperandInfo203[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4816static const MCOperandInfo OperandInfo204[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4817static const MCOperandInfo OperandInfo205[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4818static const MCOperandInfo OperandInfo206[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4819static const MCOperandInfo OperandInfo207[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4820static const MCOperandInfo OperandInfo208[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4821static const MCOperandInfo OperandInfo209[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4822static const MCOperandInfo OperandInfo210[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSACtrlRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4823static const MCOperandInfo OperandInfo211[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4824static const MCOperandInfo OperandInfo212[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4825static const MCOperandInfo OperandInfo213[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4826static const MCOperandInfo OperandInfo214[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4827static const MCOperandInfo OperandInfo215[] = { { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4828static const MCOperandInfo OperandInfo216[] = { { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4829static const MCOperandInfo OperandInfo217[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4830static const MCOperandInfo OperandInfo218[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4831static const MCOperandInfo OperandInfo219[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4832static const MCOperandInfo OperandInfo220[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4833static const MCOperandInfo OperandInfo221[] = { { Mips::CCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4834static const MCOperandInfo OperandInfo222[] = { { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4835static const MCOperandInfo OperandInfo223[] = { { Mips::MSACtrlRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4836static const MCOperandInfo OperandInfo224[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4837static const MCOperandInfo OperandInfo225[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4838static const MCOperandInfo OperandInfo226[] = { { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4839static const MCOperandInfo OperandInfo227[] = { { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4840static const MCOperandInfo OperandInfo228[] = { { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4841static const MCOperandInfo OperandInfo229[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4842static const MCOperandInfo OperandInfo230[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4843static const MCOperandInfo OperandInfo231[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; 4844static const MCOperandInfo OperandInfo232[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4845static const MCOperandInfo OperandInfo233[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4846static const MCOperandInfo OperandInfo234[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4847static const MCOperandInfo OperandInfo235[] = { { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4848static const MCOperandInfo OperandInfo236[] = { { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4849static const MCOperandInfo OperandInfo237[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4850static const MCOperandInfo OperandInfo238[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4851static const MCOperandInfo OperandInfo239[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4852static const MCOperandInfo OperandInfo240[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4853static const MCOperandInfo OperandInfo241[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4854static const MCOperandInfo OperandInfo242[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4855static const MCOperandInfo OperandInfo243[] = { { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; 4856static const MCOperandInfo OperandInfo244[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4857static const MCOperandInfo OperandInfo245[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4858static const MCOperandInfo OperandInfo246[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4859static const MCOperandInfo OperandInfo247[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4860static const MCOperandInfo OperandInfo248[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4861static const MCOperandInfo OperandInfo249[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4862static const MCOperandInfo OperandInfo250[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4863static const MCOperandInfo OperandInfo251[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4864static const MCOperandInfo OperandInfo252[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4865static const MCOperandInfo OperandInfo253[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4866static const MCOperandInfo OperandInfo254[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4867static const MCOperandInfo OperandInfo255[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4868static const MCOperandInfo OperandInfo256[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4869static const MCOperandInfo OperandInfo257[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4870static const MCOperandInfo OperandInfo258[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4871static const MCOperandInfo OperandInfo259[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4872static const MCOperandInfo OperandInfo260[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4873static const MCOperandInfo OperandInfo261[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4874static const MCOperandInfo OperandInfo262[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; 4875static const MCOperandInfo OperandInfo263[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4876static const MCOperandInfo OperandInfo264[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4877static const MCOperandInfo OperandInfo265[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4878static const MCOperandInfo OperandInfo266[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4879static const MCOperandInfo OperandInfo267[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4880static const MCOperandInfo OperandInfo268[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4881static const MCOperandInfo OperandInfo269[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4882static const MCOperandInfo OperandInfo270[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4883static const MCOperandInfo OperandInfo271[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4884static const MCOperandInfo OperandInfo272[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4885static const MCOperandInfo OperandInfo273[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; 4886static const MCOperandInfo OperandInfo274[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; 4887static const MCOperandInfo OperandInfo275[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; 4888static const MCOperandInfo OperandInfo276[] = { { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; 4889static const MCOperandInfo OperandInfo277[] = { { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; 4890static const MCOperandInfo OperandInfo278[] = { { Mips::COP3RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; 4891static const MCOperandInfo OperandInfo279[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4892static const MCOperandInfo OperandInfo280[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4893static const MCOperandInfo OperandInfo281[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4894static const MCOperandInfo OperandInfo282[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4895static const MCOperandInfo OperandInfo283[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; 4896static const MCOperandInfo OperandInfo284[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; 4897static const MCOperandInfo OperandInfo285[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; 4898static const MCOperandInfo OperandInfo286[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; 4899static const MCOperandInfo OperandInfo287[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; 4900static const MCOperandInfo OperandInfo288[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; 4901static const MCOperandInfo OperandInfo289[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; 4902static const MCOperandInfo OperandInfo290[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MipsII::OPERAND_MEM_SIMM9, 0 }, { -1, 0, MipsII::OPERAND_MEM_SIMM9, 0 }, }; 4903static const MCOperandInfo OperandInfo291[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MipsII::OPERAND_MEM_SIMM9, 0 }, { -1, 0, MipsII::OPERAND_MEM_SIMM9, 0 }, }; 4904static const MCOperandInfo OperandInfo292[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; 4905static const MCOperandInfo OperandInfo293[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; 4906static const MCOperandInfo OperandInfo294[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 3, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; 4907static const MCOperandInfo OperandInfo295[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; 4908static const MCOperandInfo OperandInfo296[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 2, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; 4909static const MCOperandInfo OperandInfo297[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; 4910static const MCOperandInfo OperandInfo298[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 2, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; 4911static const MCOperandInfo OperandInfo299[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; 4912static const MCOperandInfo OperandInfo300[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4913static const MCOperandInfo OperandInfo301[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; 4914static const MCOperandInfo OperandInfo302[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4915static const MCOperandInfo OperandInfo303[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4916static const MCOperandInfo OperandInfo304[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4917static const MCOperandInfo OperandInfo305[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4918static const MCOperandInfo OperandInfo306[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4919static const MCOperandInfo OperandInfo307[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4920static const MCOperandInfo OperandInfo308[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4921static const MCOperandInfo OperandInfo309[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4922static const MCOperandInfo OperandInfo310[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4923static const MCOperandInfo OperandInfo311[] = { { Mips::GPRMM16MovePPairFirstRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16MovePPairSecondRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16MovePRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16MovePRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4924static const MCOperandInfo OperandInfo312[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4925static const MCOperandInfo OperandInfo313[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; 4926static const MCOperandInfo OperandInfo314[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; 4927static const MCOperandInfo OperandInfo315[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; 4928static const MCOperandInfo OperandInfo316[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; 4929static const MCOperandInfo OperandInfo317[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; 4930static const MCOperandInfo OperandInfo318[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; 4931static const MCOperandInfo OperandInfo319[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; 4932static const MCOperandInfo OperandInfo320[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; 4933static const MCOperandInfo OperandInfo321[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; 4934static const MCOperandInfo OperandInfo322[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; 4935static const MCOperandInfo OperandInfo323[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; 4936static const MCOperandInfo OperandInfo324[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; 4937static const MCOperandInfo OperandInfo325[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; 4938static const MCOperandInfo OperandInfo326[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; 4939static const MCOperandInfo OperandInfo327[] = { { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4940static const MCOperandInfo OperandInfo328[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4941static const MCOperandInfo OperandInfo329[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4942static const MCOperandInfo OperandInfo330[] = { { Mips::HI32DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4943static const MCOperandInfo OperandInfo331[] = { { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; 4944static const MCOperandInfo OperandInfo332[] = { { Mips::LO32DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4945static const MCOperandInfo OperandInfo333[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4946static const MCOperandInfo OperandInfo334[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4947static const MCOperandInfo OperandInfo335[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4948static const MCOperandInfo OperandInfo336[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4949static const MCOperandInfo OperandInfo337[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4950static const MCOperandInfo OperandInfo338[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4951static const MCOperandInfo OperandInfo339[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; 4952static const MCOperandInfo OperandInfo340[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4953static const MCOperandInfo OperandInfo341[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::HWRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4954static const MCOperandInfo OperandInfo342[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::HWRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4955static const MCOperandInfo OperandInfo343[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4956static const MCOperandInfo OperandInfo344[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4957static const MCOperandInfo OperandInfo345[] = { { Mips::GPRMM16ZeroRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; 4958static const MCOperandInfo OperandInfo346[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; 4959static const MCOperandInfo OperandInfo347[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MipsII::OPERAND_MEM_SIMM9, 0 }, { -1, 0, MipsII::OPERAND_MEM_SIMM9, 0 }, }; 4960static const MCOperandInfo OperandInfo348[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; 4961static const MCOperandInfo OperandInfo349[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MipsII::OPERAND_MEM_SIMM9, 0 }, { -1, 0, MipsII::OPERAND_MEM_SIMM9, 0 }, }; 4962static const MCOperandInfo OperandInfo350[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4963static const MCOperandInfo OperandInfo351[] = { { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; 4964static const MCOperandInfo OperandInfo352[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4965static const MCOperandInfo OperandInfo353[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4966static const MCOperandInfo OperandInfo354[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4967static const MCOperandInfo OperandInfo355[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4968static const MCOperandInfo OperandInfo356[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4969static const MCOperandInfo OperandInfo357[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4970static const MCOperandInfo OperandInfo358[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4971static const MCOperandInfo OperandInfo359[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4972static const MCOperandInfo OperandInfo360[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4973static const MCOperandInfo OperandInfo361[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4974static const MCOperandInfo OperandInfo362[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4975static const MCOperandInfo OperandInfo363[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4976static const MCOperandInfo OperandInfo364[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; 4977static const MCOperandInfo OperandInfo365[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; 4978 4979extern const MCInstrDesc MipsInsts[] = { 4980 { 2847, 2, 1, 4, 1065, 0, 0, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo45 }, // Inst #2847 = YIELD 4981 { 2846, 3, 1, 2, 735, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, OperandInfo186 }, // Inst #2846 = XorRxRxRy16 4982 { 2845, 3, 1, 4, 773, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, OperandInfo73 }, // Inst #2845 = XORi_MM 4983 { 2844, 3, 1, 4, 815, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, OperandInfo70 }, // Inst #2844 = XORi64 4984 { 2843, 3, 1, 4, 508, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, OperandInfo73 }, // Inst #2843 = XORi 4985 { 2842, 3, 1, 4, 548, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #2842 = XOR_V 4986 { 2841, 3, 1, 4, 804, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, OperandInfo72 }, // Inst #2841 = XOR_MMR6 4987 { 2840, 3, 1, 4, 772, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, OperandInfo72 }, // Inst #2840 = XOR_MM 4988 { 2839, 3, 1, 4, 805, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, OperandInfo73 }, // Inst #2839 = XORI_MMR6 4989 { 2838, 3, 1, 4, 549, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #2838 = XORI_B 4990 { 2837, 3, 1, 4, 815, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, OperandInfo71 }, // Inst #2837 = XOR64 4991 { 2836, 3, 1, 2, 804, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo181 }, // Inst #2836 = XOR16_MMR6 4992 { 2835, 3, 1, 2, 772, 0, 0, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo181 }, // Inst #2835 = XOR16_MM 4993 { 2834, 3, 1, 4, 371, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, OperandInfo72 }, // Inst #2834 = XOR 4994 { 2833, 2, 1, 4, 803, 0, 0, 0, 0x6ULL, nullptr, OperandInfo45 }, // Inst #2833 = WSBH_MMR6 4995 { 2832, 2, 1, 4, 771, 0, 0, 0, 0x1ULL, nullptr, OperandInfo45 }, // Inst #2832 = WSBH_MM 4996 { 2831, 2, 1, 4, 481, 0, 0, 0, 0x1ULL, nullptr, OperandInfo45 }, // Inst #2831 = WSBH 4997 { 2830, 2, 1, 4, 1037, 0, 0, 0, 0x6ULL, nullptr, OperandInfo45 }, // Inst #2830 = WRPGPR_MMR6 4998 { 2829, 2, 0, 4, 1623, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo114 }, // Inst #2829 = WRDSP_MM 4999 { 2828, 2, 0, 4, 1457, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo114 }, // Inst #2828 = WRDSP 5000 { 2827, 1, 0, 4, 1052, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo2 }, // Inst #2827 = WAIT_MMR6 5001 { 2826, 1, 0, 4, 1035, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo2 }, // Inst #2826 = WAIT_MM 5002 { 2825, 0, 0, 4, 404, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr }, // Inst #2825 = WAIT 5003 { 2824, 4, 1, 4, 515, 0, 0, 0, 0x6ULL, nullptr, OperandInfo60 }, // Inst #2824 = VSHF_W 5004 { 2823, 4, 1, 4, 515, 0, 0, 0, 0x6ULL, nullptr, OperandInfo61 }, // Inst #2823 = VSHF_H 5005 { 2822, 4, 1, 4, 515, 0, 0, 0, 0x6ULL, nullptr, OperandInfo59 }, // Inst #2822 = VSHF_D 5006 { 2821, 4, 1, 4, 515, 0, 0, 0, 0x6ULL, nullptr, OperandInfo196 }, // Inst #2821 = VSHF_B 5007 { 2820, 3, 1, 4, 1208, 0, 5, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList36, OperandInfo71 }, // Inst #2820 = VMULU 5008 { 2819, 3, 1, 4, 1208, 0, 4, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList27, OperandInfo71 }, // Inst #2819 = VMM0 5009 { 2818, 3, 1, 4, 1208, 0, 3, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList35, OperandInfo71 }, // Inst #2818 = V3MULU 5010 { 2817, 2, 0, 4, 886, 0, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList6, OperandInfo45 }, // Inst #2817 = UDIV_MM 5011 { 2816, 2, 0, 4, 866, 0, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList6, OperandInfo45 }, // Inst #2816 = UDIV 5012 { 2815, 2, 0, 4, 403, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo114 }, // Inst #2815 = TTLTIU 5013 { 2814, 2, 1, 4, 1308, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #2814 = TRUNC_W_S_MMR6 5014 { 2813, 2, 1, 4, 1256, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #2813 = TRUNC_W_S_MM 5015 { 2812, 2, 1, 4, 637, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #2812 = TRUNC_W_S 5016 { 2811, 2, 1, 4, 1256, 0, 0, 0, 0x4ULL, nullptr, OperandInfo205 }, // Inst #2811 = TRUNC_W_MM 5017 { 2810, 2, 1, 4, 1308, 0, 0, 0, 0x4ULL, nullptr, OperandInfo206 }, // Inst #2810 = TRUNC_W_D_MMR6 5018 { 2809, 2, 1, 4, 637, 0, 0, 0, 0x4ULL, nullptr, OperandInfo206 }, // Inst #2809 = TRUNC_W_D64 5019 { 2808, 2, 1, 4, 637, 0, 0, 0, 0x4ULL, nullptr, OperandInfo205 }, // Inst #2808 = TRUNC_W_D32 5020 { 2807, 2, 1, 4, 1308, 0, 0, 0, 0x4ULL, nullptr, OperandInfo204 }, // Inst #2807 = TRUNC_L_S_MMR6 5021 { 2806, 2, 1, 4, 637, 0, 0, 0, 0x4ULL, nullptr, OperandInfo204 }, // Inst #2806 = TRUNC_L_S 5022 { 2805, 2, 1, 4, 1308, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #2805 = TRUNC_L_D_MMR6 5023 { 2804, 2, 1, 4, 637, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #2804 = TRUNC_L_D64 5024 { 2803, 3, 0, 4, 980, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, OperandInfo73 }, // Inst #2803 = TNE_MM 5025 { 2802, 2, 0, 4, 979, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo114 }, // Inst #2802 = TNEI_MM 5026 { 2801, 2, 0, 4, 401, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo114 }, // Inst #2801 = TNEI 5027 { 2800, 3, 0, 4, 400, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, OperandInfo73 }, // Inst #2800 = TNE 5028 { 2799, 3, 0, 4, 978, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, OperandInfo73 }, // Inst #2799 = TLT_MM 5029 { 2798, 3, 0, 4, 977, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, OperandInfo73 }, // Inst #2798 = TLTU_MM 5030 { 2797, 3, 0, 4, 399, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, OperandInfo73 }, // Inst #2797 = TLTU 5031 { 2796, 2, 0, 4, 976, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo114 }, // Inst #2796 = TLTI_MM 5032 { 2795, 2, 0, 4, 975, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo114 }, // Inst #2795 = TLTIU_MM 5033 { 2794, 2, 0, 4, 398, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo114 }, // Inst #2794 = TLTI 5034 { 2793, 3, 0, 4, 397, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, OperandInfo73 }, // Inst #2793 = TLT 5035 { 2792, 0, 0, 4, 1030, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2792 = TLBWR_MM 5036 { 2791, 0, 0, 4, 415, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2791 = TLBWR 5037 { 2790, 0, 0, 4, 1029, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2790 = TLBWI_MM 5038 { 2789, 0, 0, 4, 414, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2789 = TLBWI 5039 { 2788, 0, 0, 4, 1028, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2788 = TLBR_MM 5040 { 2787, 0, 0, 4, 413, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2787 = TLBR 5041 { 2786, 0, 0, 4, 1027, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2786 = TLBP_MM 5042 { 2785, 0, 0, 4, 412, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2785 = TLBP 5043 { 2784, 0, 0, 4, 1038, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2784 = TLBINV_MMR6 5044 { 2783, 0, 0, 4, 1039, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2783 = TLBINVF_MMR6 5045 { 2782, 0, 0, 4, 411, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2782 = TLBINVF 5046 { 2781, 0, 0, 4, 410, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2781 = TLBINV 5047 { 2780, 0, 0, 4, 1075, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2780 = TLBGWR_MM 5048 { 2779, 0, 0, 4, 430, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2779 = TLBGWR 5049 { 2778, 0, 0, 4, 1074, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2778 = TLBGWI_MM 5050 { 2777, 0, 0, 4, 429, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2777 = TLBGWI 5051 { 2776, 0, 0, 4, 1073, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2776 = TLBGR_MM 5052 { 2775, 0, 0, 4, 428, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2775 = TLBGR 5053 { 2774, 0, 0, 4, 1072, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2774 = TLBGP_MM 5054 { 2773, 0, 0, 4, 427, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2773 = TLBGP 5055 { 2772, 0, 0, 4, 1071, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2772 = TLBGINV_MM 5056 { 2771, 0, 0, 4, 1070, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2771 = TLBGINVF_MM 5057 { 2770, 0, 0, 4, 426, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2770 = TLBGINVF 5058 { 2769, 0, 0, 4, 425, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2769 = TLBGINV 5059 { 2768, 3, 0, 4, 974, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, OperandInfo73 }, // Inst #2768 = TGE_MM 5060 { 2767, 3, 0, 4, 973, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, OperandInfo73 }, // Inst #2767 = TGEU_MM 5061 { 2766, 3, 0, 4, 396, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, OperandInfo73 }, // Inst #2766 = TGEU 5062 { 2765, 2, 0, 4, 972, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo114 }, // Inst #2765 = TGEI_MM 5063 { 2764, 2, 0, 4, 971, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo114 }, // Inst #2764 = TGEIU_MM 5064 { 2763, 2, 0, 4, 395, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo114 }, // Inst #2763 = TGEIU 5065 { 2762, 2, 0, 4, 394, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo114 }, // Inst #2762 = TGEI 5066 { 2761, 3, 0, 4, 393, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, OperandInfo73 }, // Inst #2761 = TGE 5067 { 2760, 3, 0, 4, 970, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, OperandInfo73 }, // Inst #2760 = TEQ_MM 5068 { 2759, 2, 0, 4, 969, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo114 }, // Inst #2759 = TEQI_MM 5069 { 2758, 2, 0, 4, 392, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo114 }, // Inst #2758 = TEQI 5070 { 2757, 3, 0, 4, 391, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, OperandInfo73 }, // Inst #2757 = TEQ 5071 { 2756, 3, 0, 4, 1117, 0, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo185 }, // Inst #2756 = SwRxSpImmX16 5072 { 2755, 3, 0, 4, 1117, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo300 }, // Inst #2755 = SwRxRyOffMemX16 5073 { 2754, 3, 1, 2, 735, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, OperandInfo131 }, // Inst #2754 = SubuRxRyRz16 5074 { 2753, 3, 1, 2, 735, 0, 0, 0, 0x0ULL, nullptr, OperandInfo186 }, // Inst #2753 = SrlvRxRy16 5075 { 2752, 3, 1, 4, 735, 0, 0, 0, 0x0ULL, nullptr, OperandInfo167 }, // Inst #2752 = SrlX16 5076 { 2751, 3, 1, 2, 735, 0, 0, 0, 0x0ULL, nullptr, OperandInfo186 }, // Inst #2751 = SravRxRy16 5077 { 2750, 3, 1, 4, 735, 0, 0, 0, 0x0ULL, nullptr, OperandInfo167 }, // Inst #2750 = SraX16 5078 { 2749, 2, 0, 2, 735, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList7, OperandInfo130 }, // Inst #2749 = SltuRxRy16 5079 { 2748, 2, 0, 4, 735, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList7, OperandInfo183 }, // Inst #2748 = SltiuRxImmX16 5080 { 2747, 2, 0, 2, 735, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList7, OperandInfo183 }, // Inst #2747 = SltiuRxImm16 5081 { 2746, 2, 0, 4, 735, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList7, OperandInfo183 }, // Inst #2746 = SltiRxImmX16 5082 { 2745, 2, 0, 2, 735, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList7, OperandInfo183 }, // Inst #2745 = SltiRxImm16 5083 { 2744, 2, 0, 2, 735, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList7, OperandInfo130 }, // Inst #2744 = SltRxRy16 5084 { 2743, 3, 1, 2, 735, 0, 0, 0, 0x0ULL, nullptr, OperandInfo186 }, // Inst #2743 = SllvRxRy16 5085 { 2742, 3, 1, 4, 735, 0, 0, 0, 0x0ULL, nullptr, OperandInfo167 }, // Inst #2742 = SllX16 5086 { 2741, 3, 0, 4, 1116, 0, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo300 }, // Inst #2741 = ShRxRyOffMemX16 5087 { 2740, 2, 1, 2, 735, 0, 0, 0, 0x0ULL, nullptr, OperandInfo365 }, // Inst #2740 = SehRx16 5088 { 2739, 2, 1, 2, 735, 0, 0, 0, 0x0ULL, nullptr, OperandInfo365 }, // Inst #2739 = SebRx16 5089 { 2738, 3, 0, 4, 1115, 0, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo300 }, // Inst #2738 = SbRxRyOffMemX16 5090 { 2737, 0, 0, 2, 1114, 1, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr }, // Inst #2737 = SaveX16 5091 { 2736, 0, 0, 2, 1114, 1, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr }, // Inst #2736 = Save16 5092 { 2735, 1, 0, 4, 968, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, OperandInfo2 }, // Inst #2735 = SYSCALL_MM 5093 { 2734, 1, 0, 4, 390, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, OperandInfo2 }, // Inst #2734 = SYSCALL 5094 { 2733, 1, 0, 4, 1159, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo2 }, // Inst #2733 = SYNC_MMR6 5095 { 2732, 1, 0, 4, 1141, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo2 }, // Inst #2732 = SYNC_MM 5096 { 2731, 2, 0, 4, 1160, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo364 }, // Inst #2731 = SYNCI_MMR6 5097 { 2730, 2, 0, 4, 1142, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo364 }, // Inst #2730 = SYNCI_MM 5098 { 2729, 2, 0, 4, 473, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo364 }, // Inst #2729 = SYNCI 5099 { 2728, 1, 0, 4, 472, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo2 }, // Inst #2728 = SYNC 5100 { 2727, 3, 0, 4, 1156, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo96 }, // Inst #2727 = SW_MMR6 5101 { 2726, 3, 0, 4, 1133, 0, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, OperandInfo96 }, // Inst #2726 = SW_MM 5102 { 2725, 3, 0, 4, 1293, 0, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, OperandInfo299 }, // Inst #2725 = SWXC1_MM 5103 { 2724, 3, 0, 4, 702, 0, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, OperandInfo299 }, // Inst #2724 = SWXC1 5104 { 2723, 3, 0, 2, 1156, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo298 }, // Inst #2723 = SWSP_MMR6 5105 { 2722, 3, 0, 2, 1133, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo298 }, // Inst #2722 = SWSP_MM 5106 { 2721, 3, 0, 4, 1138, 0, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, OperandInfo96 }, // Inst #2721 = SWR_MM 5107 { 2720, 3, 0, 4, 1104, 0, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, OperandInfo96 }, // Inst #2720 = SWRE_MM 5108 { 2719, 3, 0, 4, 467, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo96 }, // Inst #2719 = SWRE 5109 { 2718, 3, 0, 4, 1181, 0, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, OperandInfo113 }, // Inst #2718 = SWR64 5110 { 2717, 3, 0, 4, 465, 0, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, OperandInfo96 }, // Inst #2717 = SWR 5111 { 2716, 4, 0, 4, 1137, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo297 }, // Inst #2716 = SWP_MM 5112 { 2715, 3, 0, 4, 1135, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo110 }, // Inst #2715 = SWM32_MM 5113 { 2714, 3, 0, 2, 1158, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo296 }, // Inst #2714 = SWM16_MMR6 5114 { 2713, 3, 0, 2, 1135, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo296 }, // Inst #2713 = SWM16_MM 5115 { 2712, 3, 0, 4, 1134, 0, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, OperandInfo96 }, // Inst #2712 = SWL_MM 5116 { 2711, 3, 0, 4, 1103, 0, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, OperandInfo96 }, // Inst #2711 = SWLE_MM 5117 { 2710, 3, 0, 4, 466, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo96 }, // Inst #2710 = SWLE 5118 { 2709, 3, 0, 4, 1180, 0, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, OperandInfo113 }, // Inst #2709 = SWL64 5119 { 2708, 3, 0, 4, 464, 0, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, OperandInfo96 }, // Inst #2708 = SWL 5120 { 2707, 3, 0, 4, 1102, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo96 }, // Inst #2707 = SWE_MM 5121 { 2706, 3, 0, 4, 462, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo96 }, // Inst #2706 = SWE 5122 { 2705, 3, 0, 4, 1507, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo293 }, // Inst #2705 = SWDSP_MM 5123 { 2704, 3, 0, 4, 1342, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo293 }, // Inst #2704 = SWDSP 5124 { 2703, 3, 0, 4, 456, 0, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, OperandInfo278 }, // Inst #2703 = SWC3 5125 { 2702, 3, 0, 4, 1084, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo276 }, // Inst #2702 = SWC2_R6 5126 { 2701, 3, 0, 4, 1157, 0, 0, 0|(1ULL<<MCID::MayStore), 0x6ULL, nullptr, OperandInfo277 }, // Inst #2701 = SWC2_MMR6 5127 { 2700, 3, 0, 4, 455, 0, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, OperandInfo276 }, // Inst #2700 = SWC2 5128 { 2699, 3, 0, 4, 1291, 0, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, OperandInfo292 }, // Inst #2699 = SWC1_MM 5129 { 2698, 3, 0, 4, 701, 0, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, OperandInfo292 }, // Inst #2698 = SWC1 5130 { 2697, 3, 0, 4, 1179, 0, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, OperandInfo113 }, // Inst #2697 = SW64 5131 { 2696, 3, 0, 2, 1156, 0, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo345 }, // Inst #2696 = SW16_MMR6 5132 { 2695, 3, 0, 2, 1133, 0, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo345 }, // Inst #2695 = SW16_MM 5133 { 2694, 3, 0, 4, 454, 0, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, OperandInfo96 }, // Inst #2694 = SW 5134 { 2693, 3, 0, 4, 1292, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, nullptr, OperandInfo285 }, // Inst #2693 = SUXC1_MM 5135 { 2692, 3, 0, 4, 703, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, nullptr, OperandInfo285 }, // Inst #2692 = SUXC164 5136 { 2691, 3, 0, 4, 703, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, nullptr, OperandInfo284 }, // Inst #2691 = SUXC1 5137 { 2690, 3, 1, 4, 769, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, OperandInfo72 }, // Inst #2690 = SUBu_MM 5138 { 2689, 3, 1, 4, 370, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, OperandInfo72 }, // Inst #2689 = SUBu 5139 { 2688, 3, 1, 4, 802, 0, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo72 }, // Inst #2688 = SUB_MMR6 5140 { 2687, 3, 1, 4, 770, 0, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo72 }, // Inst #2687 = SUB_MM 5141 { 2686, 3, 1, 4, 612, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #2686 = SUBV_W 5142 { 2685, 3, 1, 4, 612, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #2685 = SUBV_H 5143 { 2684, 3, 1, 4, 612, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #2684 = SUBV_D 5144 { 2683, 3, 1, 4, 612, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #2683 = SUBV_B 5145 { 2682, 3, 1, 4, 611, 0, 0, 0, 0x6ULL, nullptr, OperandInfo179 }, // Inst #2682 = SUBVI_W 5146 { 2681, 3, 1, 4, 611, 0, 0, 0, 0x6ULL, nullptr, OperandInfo178 }, // Inst #2681 = SUBVI_H 5147 { 2680, 3, 1, 4, 611, 0, 0, 0, 0x6ULL, nullptr, OperandInfo177 }, // Inst #2680 = SUBVI_D 5148 { 2679, 3, 1, 4, 611, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #2679 = SUBVI_B 5149 { 2678, 3, 1, 4, 1622, 0, 1, 0, 0x6ULL, ImplicitList8, OperandInfo172 }, // Inst #2678 = SUBU_S_QB_MM 5150 { 2677, 3, 1, 4, 1456, 0, 1, 0, 0x6ULL, ImplicitList8, OperandInfo172 }, // Inst #2677 = SUBU_S_QB 5151 { 2676, 3, 1, 4, 1667, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList8, OperandInfo172 }, // Inst #2676 = SUBU_S_PH_MMR2 5152 { 2675, 3, 1, 4, 1503, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList8, OperandInfo172 }, // Inst #2675 = SUBU_S_PH 5153 { 2674, 3, 1, 4, 1621, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList8, OperandInfo172 }, // Inst #2674 = SUBU_QB_MM 5154 { 2673, 3, 1, 4, 1455, 0, 1, 0, 0x6ULL, ImplicitList8, OperandInfo172 }, // Inst #2673 = SUBU_QB 5155 { 2672, 3, 1, 4, 1666, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList8, OperandInfo172 }, // Inst #2672 = SUBU_PH_MMR2 5156 { 2671, 3, 1, 4, 1502, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList8, OperandInfo172 }, // Inst #2671 = SUBU_PH 5157 { 2670, 3, 1, 4, 801, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, OperandInfo72 }, // Inst #2670 = SUBU_MMR6 5158 { 2669, 3, 1, 4, 1669, 0, 0, 0, 0x6ULL, nullptr, OperandInfo172 }, // Inst #2669 = SUBUH_R_QB_MMR2 5159 { 2668, 3, 1, 4, 1505, 0, 0, 0, 0x6ULL, nullptr, OperandInfo172 }, // Inst #2668 = SUBUH_R_QB 5160 { 2667, 3, 1, 4, 1668, 0, 0, 0, 0x6ULL, nullptr, OperandInfo172 }, // Inst #2667 = SUBUH_QB_MMR2 5161 { 2666, 3, 1, 4, 1504, 0, 0, 0, 0x6ULL, nullptr, OperandInfo172 }, // Inst #2666 = SUBUH_QB 5162 { 2665, 3, 1, 2, 801, 0, 0, 0, 0x0ULL, nullptr, OperandInfo175 }, // Inst #2665 = SUBU16_MMR6 5163 { 2664, 3, 1, 2, 769, 0, 0, 0, 0x0ULL, nullptr, OperandInfo175 }, // Inst #2664 = SUBU16_MM 5164 { 2663, 3, 1, 4, 608, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #2663 = SUBS_U_W 5165 { 2662, 3, 1, 4, 608, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #2662 = SUBS_U_H 5166 { 2661, 3, 1, 4, 608, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #2661 = SUBS_U_D 5167 { 2660, 3, 1, 4, 608, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #2660 = SUBS_U_B 5168 { 2659, 3, 1, 4, 608, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #2659 = SUBS_S_W 5169 { 2658, 3, 1, 4, 608, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #2658 = SUBS_S_H 5170 { 2657, 3, 1, 4, 608, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #2657 = SUBS_S_D 5171 { 2656, 3, 1, 4, 608, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #2656 = SUBS_S_B 5172 { 2655, 3, 1, 4, 610, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #2655 = SUBSUU_S_W 5173 { 2654, 3, 1, 4, 610, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #2654 = SUBSUU_S_H 5174 { 2653, 3, 1, 4, 610, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #2653 = SUBSUU_S_D 5175 { 2652, 3, 1, 4, 610, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #2652 = SUBSUU_S_B 5176 { 2651, 3, 1, 4, 609, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #2651 = SUBSUS_U_W 5177 { 2650, 3, 1, 4, 609, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #2650 = SUBSUS_U_H 5178 { 2649, 3, 1, 4, 609, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #2649 = SUBSUS_U_D 5179 { 2648, 3, 1, 4, 609, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #2648 = SUBSUS_U_B 5180 { 2647, 3, 1, 4, 1620, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList8, OperandInfo72 }, // Inst #2647 = SUBQ_S_W_MM 5181 { 2646, 3, 1, 4, 1454, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList8, OperandInfo72 }, // Inst #2646 = SUBQ_S_W 5182 { 2645, 3, 1, 4, 1619, 0, 1, 0, 0x6ULL, ImplicitList8, OperandInfo172 }, // Inst #2645 = SUBQ_S_PH_MM 5183 { 2644, 3, 1, 4, 1453, 0, 1, 0, 0x6ULL, ImplicitList8, OperandInfo172 }, // Inst #2644 = SUBQ_S_PH 5184 { 2643, 3, 1, 4, 1618, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList8, OperandInfo172 }, // Inst #2643 = SUBQ_PH_MM 5185 { 2642, 3, 1, 4, 1452, 0, 1, 0, 0x6ULL, ImplicitList8, OperandInfo172 }, // Inst #2642 = SUBQ_PH 5186 { 2641, 3, 1, 4, 1664, 0, 0, 0, 0x6ULL, nullptr, OperandInfo72 }, // Inst #2641 = SUBQH_W_MMR2 5187 { 2640, 3, 1, 4, 1500, 0, 0, 0, 0x6ULL, nullptr, OperandInfo72 }, // Inst #2640 = SUBQH_W 5188 { 2639, 3, 1, 4, 1665, 0, 0, 0, 0x6ULL, nullptr, OperandInfo72 }, // Inst #2639 = SUBQH_R_W_MMR2 5189 { 2638, 3, 1, 4, 1501, 0, 0, 0, 0x6ULL, nullptr, OperandInfo72 }, // Inst #2638 = SUBQH_R_W 5190 { 2637, 3, 1, 4, 1663, 0, 0, 0, 0x6ULL, nullptr, OperandInfo172 }, // Inst #2637 = SUBQH_R_PH_MMR2 5191 { 2636, 3, 1, 4, 1499, 0, 0, 0, 0x6ULL, nullptr, OperandInfo172 }, // Inst #2636 = SUBQH_R_PH 5192 { 2635, 3, 1, 4, 1662, 0, 0, 0, 0x6ULL, nullptr, OperandInfo172 }, // Inst #2635 = SUBQH_PH_MMR2 5193 { 2634, 3, 1, 4, 1498, 0, 0, 0, 0x6ULL, nullptr, OperandInfo172 }, // Inst #2634 = SUBQH_PH 5194 { 2633, 3, 1, 4, 369, 0, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo72 }, // Inst #2633 = SUB 5195 { 2632, 3, 0, 4, 704, 0, 0, 0|(1ULL<<MCID::MayStore), 0x6ULL, nullptr, OperandInfo289 }, // Inst #2632 = ST_W 5196 { 2631, 3, 0, 4, 704, 0, 0, 0|(1ULL<<MCID::MayStore), 0x6ULL, nullptr, OperandInfo288 }, // Inst #2631 = ST_H 5197 { 2630, 3, 0, 4, 704, 0, 0, 0|(1ULL<<MCID::MayStore), 0x6ULL, nullptr, OperandInfo287 }, // Inst #2630 = ST_D 5198 { 2629, 3, 0, 4, 704, 0, 0, 0|(1ULL<<MCID::MayStore), 0x6ULL, nullptr, OperandInfo286 }, // Inst #2629 = ST_B 5199 { 2628, 0, 0, 4, 800, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2628 = SSNOP_MMR6 5200 { 2627, 0, 0, 4, 768, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2627 = SSNOP_MM 5201 { 2626, 0, 0, 4, 372, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2626 = SSNOP 5202 { 2625, 3, 1, 4, 622, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #2625 = SRL_W 5203 { 2624, 3, 1, 4, 766, 0, 0, 0, 0x1ULL, nullptr, OperandInfo73 }, // Inst #2624 = SRL_MM 5204 { 2623, 3, 1, 4, 622, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #2623 = SRL_H 5205 { 2622, 3, 1, 4, 622, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #2622 = SRL_D 5206 { 2621, 3, 1, 4, 622, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #2621 = SRL_B 5207 { 2620, 3, 1, 4, 767, 0, 0, 0, 0x1ULL, nullptr, OperandInfo72 }, // Inst #2620 = SRLV_MM 5208 { 2619, 3, 1, 4, 512, 0, 0, 0, 0x1ULL, nullptr, OperandInfo72 }, // Inst #2619 = SRLV 5209 { 2618, 3, 1, 4, 624, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #2618 = SRLR_W 5210 { 2617, 3, 1, 4, 624, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #2617 = SRLR_H 5211 { 2616, 3, 1, 4, 624, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #2616 = SRLR_D 5212 { 2615, 3, 1, 4, 624, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #2615 = SRLR_B 5213 { 2614, 3, 1, 4, 624, 0, 0, 0, 0x6ULL, nullptr, OperandInfo179 }, // Inst #2614 = SRLRI_W 5214 { 2613, 3, 1, 4, 624, 0, 0, 0, 0x6ULL, nullptr, OperandInfo178 }, // Inst #2613 = SRLRI_H 5215 { 2612, 3, 1, 4, 624, 0, 0, 0, 0x6ULL, nullptr, OperandInfo177 }, // Inst #2612 = SRLRI_D 5216 { 2611, 3, 1, 4, 624, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #2611 = SRLRI_B 5217 { 2610, 3, 1, 4, 622, 0, 0, 0, 0x6ULL, nullptr, OperandInfo179 }, // Inst #2610 = SRLI_W 5218 { 2609, 3, 1, 4, 622, 0, 0, 0, 0x6ULL, nullptr, OperandInfo178 }, // Inst #2609 = SRLI_H 5219 { 2608, 3, 1, 4, 622, 0, 0, 0, 0x6ULL, nullptr, OperandInfo177 }, // Inst #2608 = SRLI_D 5220 { 2607, 3, 1, 4, 622, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #2607 = SRLI_B 5221 { 2606, 3, 1, 2, 799, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo170 }, // Inst #2606 = SRL16_MMR6 5222 { 2605, 3, 1, 2, 766, 0, 0, 0, 0x0ULL, nullptr, OperandInfo170 }, // Inst #2605 = SRL16_MM 5223 { 2604, 3, 1, 4, 507, 0, 0, 0, 0x1ULL, nullptr, OperandInfo73 }, // Inst #2604 = SRL 5224 { 2603, 3, 1, 4, 621, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #2603 = SRA_W 5225 { 2602, 3, 1, 4, 765, 0, 0, 0, 0x1ULL, nullptr, OperandInfo73 }, // Inst #2602 = SRA_MM 5226 { 2601, 3, 1, 4, 621, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #2601 = SRA_H 5227 { 2600, 3, 1, 4, 621, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #2600 = SRA_D 5228 { 2599, 3, 1, 4, 621, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #2599 = SRA_B 5229 { 2598, 3, 1, 4, 764, 0, 0, 0, 0x1ULL, nullptr, OperandInfo72 }, // Inst #2598 = SRAV_MM 5230 { 2597, 3, 1, 4, 511, 0, 0, 0, 0x1ULL, nullptr, OperandInfo72 }, // Inst #2597 = SRAV 5231 { 2596, 3, 1, 4, 623, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #2596 = SRAR_W 5232 { 2595, 3, 1, 4, 623, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #2595 = SRAR_H 5233 { 2594, 3, 1, 4, 623, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #2594 = SRAR_D 5234 { 2593, 3, 1, 4, 623, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #2593 = SRAR_B 5235 { 2592, 3, 1, 4, 623, 0, 0, 0, 0x6ULL, nullptr, OperandInfo179 }, // Inst #2592 = SRARI_W 5236 { 2591, 3, 1, 4, 623, 0, 0, 0, 0x6ULL, nullptr, OperandInfo178 }, // Inst #2591 = SRARI_H 5237 { 2590, 3, 1, 4, 623, 0, 0, 0, 0x6ULL, nullptr, OperandInfo177 }, // Inst #2590 = SRARI_D 5238 { 2589, 3, 1, 4, 623, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #2589 = SRARI_B 5239 { 2588, 3, 1, 4, 621, 0, 0, 0, 0x6ULL, nullptr, OperandInfo179 }, // Inst #2588 = SRAI_W 5240 { 2587, 3, 1, 4, 621, 0, 0, 0, 0x6ULL, nullptr, OperandInfo178 }, // Inst #2587 = SRAI_H 5241 { 2586, 3, 1, 4, 621, 0, 0, 0, 0x6ULL, nullptr, OperandInfo177 }, // Inst #2586 = SRAI_D 5242 { 2585, 3, 1, 4, 621, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #2585 = SRAI_B 5243 { 2584, 3, 1, 4, 506, 0, 0, 0, 0x1ULL, nullptr, OperandInfo73 }, // Inst #2584 = SRA 5244 { 2583, 3, 1, 4, 545, 0, 0, 0, 0x6ULL, nullptr, OperandInfo363 }, // Inst #2583 = SPLAT_W 5245 { 2582, 3, 1, 4, 545, 0, 0, 0, 0x6ULL, nullptr, OperandInfo362 }, // Inst #2582 = SPLAT_H 5246 { 2581, 3, 1, 4, 545, 0, 0, 0, 0x6ULL, nullptr, OperandInfo361 }, // Inst #2581 = SPLAT_D 5247 { 2580, 3, 1, 4, 545, 0, 0, 0, 0x6ULL, nullptr, OperandInfo360 }, // Inst #2580 = SPLAT_B 5248 { 2579, 3, 1, 4, 545, 0, 0, 0, 0x6ULL, nullptr, OperandInfo179 }, // Inst #2579 = SPLATI_W 5249 { 2578, 3, 1, 4, 545, 0, 0, 0, 0x6ULL, nullptr, OperandInfo178 }, // Inst #2578 = SPLATI_H 5250 { 2577, 3, 1, 4, 545, 0, 0, 0, 0x6ULL, nullptr, OperandInfo177 }, // Inst #2577 = SPLATI_D 5251 { 2576, 3, 1, 4, 545, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #2576 = SPLATI_B 5252 { 2575, 3, 1, 4, 1207, 0, 0, 0, 0x2ULL, nullptr, OperandInfo70 }, // Inst #2575 = SNEi 5253 { 2574, 3, 1, 4, 1206, 0, 0, 0, 0x1ULL, nullptr, OperandInfo71 }, // Inst #2574 = SNE 5254 { 2573, 3, 1, 4, 762, 0, 0, 0, 0x1ULL, nullptr, OperandInfo72 }, // Inst #2573 = SLTu_MM 5255 { 2572, 3, 1, 4, 813, 0, 0, 0, 0x1ULL, nullptr, OperandInfo358 }, // Inst #2572 = SLTu64 5256 { 2571, 3, 1, 4, 504, 0, 0, 0, 0x1ULL, nullptr, OperandInfo72 }, // Inst #2571 = SLTu 5257 { 2570, 3, 1, 4, 763, 0, 0, 0, 0x2ULL, nullptr, OperandInfo73 }, // Inst #2570 = SLTiu_MM 5258 { 2569, 3, 1, 4, 814, 0, 0, 0, 0x2ULL, nullptr, OperandInfo359 }, // Inst #2569 = SLTiu64 5259 { 2568, 3, 1, 4, 368, 0, 0, 0, 0x2ULL, nullptr, OperandInfo73 }, // Inst #2568 = SLTiu 5260 { 2567, 3, 1, 4, 763, 0, 0, 0, 0x2ULL, nullptr, OperandInfo73 }, // Inst #2567 = SLTi_MM 5261 { 2566, 3, 1, 4, 814, 0, 0, 0, 0x2ULL, nullptr, OperandInfo359 }, // Inst #2566 = SLTi64 5262 { 2565, 3, 1, 4, 368, 0, 0, 0, 0x2ULL, nullptr, OperandInfo73 }, // Inst #2565 = SLTi 5263 { 2564, 3, 1, 4, 762, 0, 0, 0, 0x1ULL, nullptr, OperandInfo72 }, // Inst #2564 = SLT_MM 5264 { 2563, 3, 1, 4, 813, 0, 0, 0, 0x1ULL, nullptr, OperandInfo358 }, // Inst #2563 = SLT64 5265 { 2562, 3, 1, 4, 504, 0, 0, 0, 0x1ULL, nullptr, OperandInfo72 }, // Inst #2562 = SLT 5266 { 2561, 3, 1, 4, 625, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #2561 = SLL_W 5267 { 2560, 3, 1, 4, 798, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo73 }, // Inst #2560 = SLL_MMR6 5268 { 2559, 3, 1, 4, 760, 0, 0, 0, 0x1ULL, nullptr, OperandInfo73 }, // Inst #2559 = SLL_MM 5269 { 2558, 3, 1, 4, 625, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #2558 = SLL_H 5270 { 2557, 3, 1, 4, 625, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #2557 = SLL_D 5271 { 2556, 3, 1, 4, 625, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #2556 = SLL_B 5272 { 2555, 3, 1, 4, 761, 0, 0, 0, 0x1ULL, nullptr, OperandInfo72 }, // Inst #2555 = SLLV_MM 5273 { 2554, 3, 1, 4, 510, 0, 0, 0, 0x1ULL, nullptr, OperandInfo72 }, // Inst #2554 = SLLV 5274 { 2553, 3, 1, 4, 625, 0, 0, 0, 0x6ULL, nullptr, OperandInfo179 }, // Inst #2553 = SLLI_W 5275 { 2552, 3, 1, 4, 625, 0, 0, 0, 0x6ULL, nullptr, OperandInfo178 }, // Inst #2552 = SLLI_H 5276 { 2551, 3, 1, 4, 625, 0, 0, 0, 0x6ULL, nullptr, OperandInfo177 }, // Inst #2551 = SLLI_D 5277 { 2550, 3, 1, 4, 625, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #2550 = SLLI_B 5278 { 2549, 2, 1, 4, 812, 0, 0, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, OperandInfo122 }, // Inst #2549 = SLL64_64 5279 { 2548, 2, 1, 4, 812, 0, 0, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, OperandInfo245 }, // Inst #2548 = SLL64_32 5280 { 2547, 3, 1, 2, 798, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo170 }, // Inst #2547 = SLL16_MMR6 5281 { 2546, 3, 1, 2, 760, 0, 0, 0, 0x0ULL, nullptr, OperandInfo170 }, // Inst #2546 = SLL16_MM 5282 { 2545, 3, 1, 4, 505, 0, 0, 0, 0x1ULL, nullptr, OperandInfo73 }, // Inst #2545 = SLL 5283 { 2544, 4, 1, 4, 519, 0, 0, 0, 0x6ULL, nullptr, OperandInfo357 }, // Inst #2544 = SLD_W 5284 { 2543, 4, 1, 4, 519, 0, 0, 0, 0x6ULL, nullptr, OperandInfo356 }, // Inst #2543 = SLD_H 5285 { 2542, 4, 1, 4, 519, 0, 0, 0, 0x6ULL, nullptr, OperandInfo355 }, // Inst #2542 = SLD_D 5286 { 2541, 4, 1, 4, 519, 0, 0, 0, 0x6ULL, nullptr, OperandInfo354 }, // Inst #2541 = SLD_B 5287 { 2540, 4, 1, 4, 519, 0, 0, 0, 0x6ULL, nullptr, OperandInfo195 }, // Inst #2540 = SLDI_W 5288 { 2539, 4, 1, 4, 519, 0, 0, 0, 0x6ULL, nullptr, OperandInfo194 }, // Inst #2539 = SLDI_H 5289 { 2538, 4, 1, 4, 519, 0, 0, 0, 0x6ULL, nullptr, OperandInfo193 }, // Inst #2538 = SLDI_D 5290 { 2537, 4, 1, 4, 519, 0, 0, 0, 0x6ULL, nullptr, OperandInfo192 }, // Inst #2537 = SLDI_B 5291 { 2536, 1, 0, 4, 996, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo2 }, // Inst #2536 = SIGRIE_MMR6 5292 { 2535, 1, 0, 4, 935, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo2 }, // Inst #2535 = SIGRIE 5293 { 2534, 3, 0, 4, 1155, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo96 }, // Inst #2534 = SH_MMR6 5294 { 2533, 3, 0, 4, 1132, 0, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, OperandInfo96 }, // Inst #2533 = SH_MM 5295 { 2532, 3, 1, 4, 1617, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo353 }, // Inst #2532 = SHRL_QB_MM 5296 { 2531, 3, 1, 4, 1451, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo353 }, // Inst #2531 = SHRL_QB 5297 { 2530, 3, 1, 4, 1660, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo353 }, // Inst #2530 = SHRL_PH_MMR2 5298 { 2529, 3, 1, 4, 1496, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo353 }, // Inst #2529 = SHRL_PH 5299 { 2528, 3, 1, 4, 1616, 0, 0, 0, 0x6ULL, nullptr, OperandInfo352 }, // Inst #2528 = SHRLV_QB_MM 5300 { 2527, 3, 1, 4, 1450, 0, 0, 0, 0x6ULL, nullptr, OperandInfo352 }, // Inst #2527 = SHRLV_QB 5301 { 2526, 3, 1, 4, 1661, 0, 0, 0, 0x6ULL, nullptr, OperandInfo352 }, // Inst #2526 = SHRLV_PH_MMR2 5302 { 2525, 3, 1, 4, 1497, 0, 0, 0, 0x6ULL, nullptr, OperandInfo352 }, // Inst #2525 = SHRLV_PH 5303 { 2524, 3, 1, 4, 1615, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo73 }, // Inst #2524 = SHRA_R_W_MM 5304 { 2523, 3, 1, 4, 1449, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo73 }, // Inst #2523 = SHRA_R_W 5305 { 2522, 3, 1, 4, 1657, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo353 }, // Inst #2522 = SHRA_R_QB_MMR2 5306 { 2521, 3, 1, 4, 1493, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo353 }, // Inst #2521 = SHRA_R_QB 5307 { 2520, 3, 1, 4, 1614, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo353 }, // Inst #2520 = SHRA_R_PH_MM 5308 { 2519, 3, 1, 4, 1448, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo353 }, // Inst #2519 = SHRA_R_PH 5309 { 2518, 3, 1, 4, 1656, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo353 }, // Inst #2518 = SHRA_QB_MMR2 5310 { 2517, 3, 1, 4, 1492, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo353 }, // Inst #2517 = SHRA_QB 5311 { 2516, 3, 1, 4, 1613, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo353 }, // Inst #2516 = SHRA_PH_MM 5312 { 2515, 3, 1, 4, 1447, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo353 }, // Inst #2515 = SHRA_PH 5313 { 2514, 3, 1, 4, 1612, 0, 0, 0, 0x6ULL, nullptr, OperandInfo72 }, // Inst #2514 = SHRAV_R_W_MM 5314 { 2513, 3, 1, 4, 1446, 0, 0, 0, 0x6ULL, nullptr, OperandInfo72 }, // Inst #2513 = SHRAV_R_W 5315 { 2512, 3, 1, 4, 1659, 0, 0, 0, 0x6ULL, nullptr, OperandInfo352 }, // Inst #2512 = SHRAV_R_QB_MMR2 5316 { 2511, 3, 1, 4, 1495, 0, 0, 0, 0x6ULL, nullptr, OperandInfo352 }, // Inst #2511 = SHRAV_R_QB 5317 { 2510, 3, 1, 4, 1611, 0, 0, 0, 0x6ULL, nullptr, OperandInfo352 }, // Inst #2510 = SHRAV_R_PH_MM 5318 { 2509, 3, 1, 4, 1445, 0, 0, 0, 0x6ULL, nullptr, OperandInfo352 }, // Inst #2509 = SHRAV_R_PH 5319 { 2508, 3, 1, 4, 1658, 0, 0, 0, 0x6ULL, nullptr, OperandInfo352 }, // Inst #2508 = SHRAV_QB_MMR2 5320 { 2507, 3, 1, 4, 1494, 0, 0, 0, 0x6ULL, nullptr, OperandInfo352 }, // Inst #2507 = SHRAV_QB 5321 { 2506, 3, 1, 4, 1610, 0, 0, 0, 0x6ULL, nullptr, OperandInfo352 }, // Inst #2506 = SHRAV_PH_MM 5322 { 2505, 3, 1, 4, 1444, 0, 0, 0, 0x6ULL, nullptr, OperandInfo352 }, // Inst #2505 = SHRAV_PH 5323 { 2504, 3, 1, 4, 1609, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList34, OperandInfo73 }, // Inst #2504 = SHLL_S_W_MM 5324 { 2503, 3, 1, 4, 1443, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList34, OperandInfo73 }, // Inst #2503 = SHLL_S_W 5325 { 2502, 3, 1, 4, 1608, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList34, OperandInfo353 }, // Inst #2502 = SHLL_S_PH_MM 5326 { 2501, 3, 1, 4, 1442, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList34, OperandInfo353 }, // Inst #2501 = SHLL_S_PH 5327 { 2500, 3, 1, 4, 1607, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList34, OperandInfo353 }, // Inst #2500 = SHLL_QB_MM 5328 { 2499, 3, 1, 4, 1441, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList34, OperandInfo353 }, // Inst #2499 = SHLL_QB 5329 { 2498, 3, 1, 4, 1606, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList34, OperandInfo353 }, // Inst #2498 = SHLL_PH_MM 5330 { 2497, 3, 1, 4, 1440, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList34, OperandInfo353 }, // Inst #2497 = SHLL_PH 5331 { 2496, 3, 1, 4, 1605, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList34, OperandInfo72 }, // Inst #2496 = SHLLV_S_W_MM 5332 { 2495, 3, 1, 4, 1439, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList34, OperandInfo72 }, // Inst #2495 = SHLLV_S_W 5333 { 2494, 3, 1, 4, 1604, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList34, OperandInfo352 }, // Inst #2494 = SHLLV_S_PH_MM 5334 { 2493, 3, 1, 4, 1438, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList34, OperandInfo352 }, // Inst #2493 = SHLLV_S_PH 5335 { 2492, 3, 1, 4, 1603, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList34, OperandInfo352 }, // Inst #2492 = SHLLV_QB_MM 5336 { 2491, 3, 1, 4, 1437, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList34, OperandInfo352 }, // Inst #2491 = SHLLV_QB 5337 { 2490, 3, 1, 4, 1602, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList34, OperandInfo352 }, // Inst #2490 = SHLLV_PH_MM 5338 { 2489, 3, 1, 4, 1436, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList34, OperandInfo352 }, // Inst #2489 = SHLLV_PH 5339 { 2488, 3, 1, 4, 1601, 0, 0, 0, 0x6ULL, nullptr, OperandInfo351 }, // Inst #2488 = SHILO_MM 5340 { 2487, 3, 1, 4, 1600, 0, 0, 0, 0x6ULL, nullptr, OperandInfo331 }, // Inst #2487 = SHILOV_MM 5341 { 2486, 3, 1, 4, 1434, 0, 0, 0, 0x6ULL, nullptr, OperandInfo331 }, // Inst #2486 = SHILOV 5342 { 2485, 3, 1, 4, 1435, 0, 0, 0, 0x6ULL, nullptr, OperandInfo351 }, // Inst #2485 = SHILO 5343 { 2484, 3, 1, 4, 543, 0, 0, 0, 0x6ULL, nullptr, OperandInfo179 }, // Inst #2484 = SHF_W 5344 { 2483, 3, 1, 4, 543, 0, 0, 0, 0x6ULL, nullptr, OperandInfo178 }, // Inst #2483 = SHF_H 5345 { 2482, 3, 1, 4, 543, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #2482 = SHF_B 5346 { 2481, 3, 0, 4, 1101, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo96 }, // Inst #2481 = SHE_MM 5347 { 2480, 3, 0, 4, 461, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo96 }, // Inst #2480 = SHE 5348 { 2479, 3, 0, 4, 1178, 0, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, OperandInfo113 }, // Inst #2479 = SH64 5349 { 2478, 3, 0, 2, 1155, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo345 }, // Inst #2478 = SH16_MMR6 5350 { 2477, 3, 0, 2, 1132, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo345 }, // Inst #2477 = SH16_MM 5351 { 2476, 3, 0, 4, 453, 0, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, OperandInfo96 }, // Inst #2476 = SH 5352 { 2475, 3, 1, 4, 1207, 0, 0, 0, 0x2ULL, nullptr, OperandInfo70 }, // Inst #2475 = SEQi 5353 { 2474, 3, 1, 4, 1206, 0, 0, 0, 0x1ULL, nullptr, OperandInfo71 }, // Inst #2474 = SEQ 5354 { 2473, 4, 1, 4, 1327, 0, 0, 0, 0x6ULL, nullptr, OperandInfo350 }, // Inst #2473 = SEL_S_MMR6 5355 { 2472, 4, 1, 4, 1233, 0, 0, 0, 0x6ULL, nullptr, OperandInfo350 }, // Inst #2472 = SEL_S 5356 { 2471, 4, 1, 4, 1326, 0, 0, 0, 0x6ULL, nullptr, OperandInfo302 }, // Inst #2471 = SEL_D_MMR6 5357 { 2470, 4, 1, 4, 1232, 0, 0, 0, 0x6ULL, nullptr, OperandInfo302 }, // Inst #2470 = SEL_D 5358 { 2469, 3, 1, 4, 1325, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo250 }, // Inst #2469 = SELNEZ_S_MMR6 5359 { 2468, 3, 1, 4, 1221, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo250 }, // Inst #2468 = SELNEZ_S 5360 { 2467, 3, 1, 4, 797, 0, 0, 0, 0x6ULL, nullptr, OperandInfo72 }, // Inst #2467 = SELNEZ_MMR6 5361 { 2466, 3, 1, 4, 1324, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo173 }, // Inst #2466 = SELNEZ_D_MMR6 5362 { 2465, 3, 1, 4, 1222, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo173 }, // Inst #2465 = SELNEZ_D 5363 { 2464, 3, 1, 4, 852, 0, 0, 0, 0x6ULL, nullptr, OperandInfo71 }, // Inst #2464 = SELNEZ64 5364 { 2463, 3, 1, 4, 734, 0, 0, 0, 0x6ULL, nullptr, OperandInfo72 }, // Inst #2463 = SELNEZ 5365 { 2462, 3, 1, 4, 1325, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo250 }, // Inst #2462 = SELEQZ_S_MMR6 5366 { 2461, 3, 1, 4, 1221, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo250 }, // Inst #2461 = SELEQZ_S 5367 { 2460, 3, 1, 4, 797, 0, 0, 0, 0x6ULL, nullptr, OperandInfo72 }, // Inst #2460 = SELEQZ_MMR6 5368 { 2459, 3, 1, 4, 1324, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo173 }, // Inst #2459 = SELEQZ_D_MMR6 5369 { 2458, 3, 1, 4, 1222, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo173 }, // Inst #2458 = SELEQZ_D 5370 { 2457, 3, 1, 4, 852, 0, 0, 0, 0x6ULL, nullptr, OperandInfo71 }, // Inst #2457 = SELEQZ64 5371 { 2456, 3, 1, 4, 734, 0, 0, 0, 0x6ULL, nullptr, OperandInfo72 }, // Inst #2456 = SELEQZ 5372 { 2455, 2, 1, 4, 759, 0, 0, 0, 0x1ULL, nullptr, OperandInfo45 }, // Inst #2455 = SEH_MM 5373 { 2454, 2, 1, 4, 811, 0, 0, 0, 0x1ULL, nullptr, OperandInfo122 }, // Inst #2454 = SEH64 5374 { 2453, 2, 1, 4, 503, 0, 0, 0, 0x1ULL, nullptr, OperandInfo45 }, // Inst #2453 = SEH 5375 { 2452, 2, 1, 4, 758, 0, 0, 0, 0x1ULL, nullptr, OperandInfo45 }, // Inst #2452 = SEB_MM 5376 { 2451, 2, 1, 4, 810, 0, 0, 0, 0x1ULL, nullptr, OperandInfo122 }, // Inst #2451 = SEB64 5377 { 2450, 2, 1, 4, 502, 0, 0, 0, 0x1ULL, nullptr, OperandInfo45 }, // Inst #2450 = SEB 5378 { 2449, 3, 0, 4, 700, 0, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, OperandInfo285 }, // Inst #2449 = SDXC164 5379 { 2448, 3, 0, 4, 700, 0, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, OperandInfo284 }, // Inst #2448 = SDXC1 5380 { 2447, 3, 0, 4, 1183, 0, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, OperandInfo113 }, // Inst #2447 = SDR 5381 { 2446, 3, 0, 4, 1182, 0, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, OperandInfo113 }, // Inst #2446 = SDL 5382 { 2445, 2, 0, 4, 885, 0, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList6, OperandInfo45 }, // Inst #2445 = SDIV_MM 5383 { 2444, 2, 0, 4, 865, 0, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList6, OperandInfo45 }, // Inst #2444 = SDIV 5384 { 2443, 3, 0, 4, 458, 0, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, OperandInfo278 }, // Inst #2443 = SDC3 5385 { 2442, 3, 0, 4, 1085, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo276 }, // Inst #2442 = SDC2_R6 5386 { 2441, 3, 0, 4, 1154, 0, 0, 0|(1ULL<<MCID::MayStore), 0x6ULL, nullptr, OperandInfo277 }, // Inst #2441 = SDC2_MMR6 5387 { 2440, 3, 0, 4, 457, 0, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, OperandInfo276 }, // Inst #2440 = SDC2 5388 { 2439, 3, 0, 4, 1290, 0, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, OperandInfo275 }, // Inst #2439 = SDC1_MM_D64 5389 { 2438, 3, 0, 4, 1290, 0, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, OperandInfo158 }, // Inst #2438 = SDC1_MM_D32 5390 { 2437, 3, 0, 4, 1338, 0, 0, 0|(1ULL<<MCID::MayStore), 0x6ULL, nullptr, OperandInfo275 }, // Inst #2437 = SDC1_D64_MMR6 5391 { 2436, 3, 0, 4, 699, 0, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, OperandInfo275 }, // Inst #2436 = SDC164 5392 { 2435, 3, 0, 4, 699, 0, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, OperandInfo158 }, // Inst #2435 = SDC1 5393 { 2434, 1, 0, 4, 938, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo2 }, // Inst #2434 = SDBBP_R6 5394 { 2433, 1, 0, 4, 1008, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo2 }, // Inst #2433 = SDBBP_MMR6 5395 { 2432, 1, 0, 4, 967, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, OperandInfo2 }, // Inst #2432 = SDBBP_MM 5396 { 2431, 1, 0, 2, 1008, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo2 }, // Inst #2431 = SDBBP16_MMR6 5397 { 2430, 1, 0, 2, 967, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo2 }, // Inst #2430 = SDBBP16_MM 5398 { 2429, 1, 0, 4, 389, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, OperandInfo2 }, // Inst #2429 = SDBBP 5399 { 2428, 3, 0, 4, 1175, 0, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, OperandInfo113 }, // Inst #2428 = SD 5400 { 2427, 4, 1, 4, 1086, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo347 }, // Inst #2427 = SC_R6 5401 { 2426, 4, 1, 4, 1080, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo346 }, // Inst #2426 = SC_MMR6 5402 { 2425, 4, 1, 4, 1131, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo346 }, // Inst #2425 = SC_MM 5403 { 2424, 4, 1, 4, 1105, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo346 }, // Inst #2424 = SCE_MM 5404 { 2423, 4, 1, 4, 463, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo346 }, // Inst #2423 = SCE 5405 { 2422, 4, 1, 4, 1189, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo349 }, // Inst #2422 = SCD_R6 5406 { 2421, 4, 1, 4, 1176, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo348 }, // Inst #2421 = SCD 5407 { 2420, 4, 1, 4, 1188, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo347 }, // Inst #2420 = SC64_R6 5408 { 2419, 4, 1, 4, 1176, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo346 }, // Inst #2419 = SC64 5409 { 2418, 4, 1, 4, 459, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo346 }, // Inst #2418 = SC 5410 { 2417, 3, 0, 4, 1153, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo96 }, // Inst #2417 = SB_MMR6 5411 { 2416, 3, 0, 4, 1100, 0, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, OperandInfo96 }, // Inst #2416 = SB_MM 5412 { 2415, 3, 0, 4, 1099, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo96 }, // Inst #2415 = SBE_MM 5413 { 2414, 3, 0, 4, 460, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo96 }, // Inst #2414 = SBE 5414 { 2413, 3, 0, 4, 1177, 0, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, OperandInfo113 }, // Inst #2413 = SB64 5415 { 2412, 3, 0, 2, 1153, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo345 }, // Inst #2412 = SB16_MMR6 5416 { 2411, 3, 0, 2, 1130, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo345 }, // Inst #2411 = SB16_MM 5417 { 2410, 3, 0, 4, 452, 0, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, OperandInfo96 }, // Inst #2410 = SB 5418 { 2409, 3, 1, 4, 527, 0, 0, 0, 0x6ULL, nullptr, OperandInfo179 }, // Inst #2409 = SAT_U_W 5419 { 2408, 3, 1, 4, 527, 0, 0, 0, 0x6ULL, nullptr, OperandInfo178 }, // Inst #2408 = SAT_U_H 5420 { 2407, 3, 1, 4, 527, 0, 0, 0, 0x6ULL, nullptr, OperandInfo177 }, // Inst #2407 = SAT_U_D 5421 { 2406, 3, 1, 4, 527, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #2406 = SAT_U_B 5422 { 2405, 3, 1, 4, 527, 0, 0, 0, 0x6ULL, nullptr, OperandInfo179 }, // Inst #2405 = SAT_S_W 5423 { 2404, 3, 1, 4, 527, 0, 0, 0, 0x6ULL, nullptr, OperandInfo178 }, // Inst #2404 = SAT_S_H 5424 { 2403, 3, 1, 4, 527, 0, 0, 0, 0x6ULL, nullptr, OperandInfo177 }, // Inst #2403 = SAT_S_D 5425 { 2402, 3, 1, 4, 527, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #2402 = SAT_S_B 5426 { 2401, 2, 0, 4, 1210, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo122 }, // Inst #2401 = SAAD 5427 { 2400, 2, 0, 4, 1210, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo122 }, // Inst #2400 = SAA 5428 { 2399, 0, 0, 2, 1108, 1, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr }, // Inst #2399 = RestoreX16 5429 { 2398, 0, 0, 2, 1108, 1, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr }, // Inst #2398 = Restore16 5430 { 2397, 2, 1, 4, 1288, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #2397 = RSQRT_S_MM 5431 { 2396, 2, 1, 4, 655, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #2396 = RSQRT_S 5432 { 2395, 2, 1, 4, 1289, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #2395 = RSQRT_D64_MM 5433 { 2394, 2, 1, 4, 653, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #2394 = RSQRT_D64 5434 { 2393, 2, 1, 4, 1289, 0, 0, 0, 0x4ULL, nullptr, OperandInfo248 }, // Inst #2393 = RSQRT_D32_MM 5435 { 2392, 2, 1, 4, 653, 0, 0, 0, 0x4ULL, nullptr, OperandInfo248 }, // Inst #2392 = RSQRT_D32 5436 { 2391, 2, 1, 4, 1309, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #2391 = ROUND_W_S_MMR6 5437 { 2390, 2, 1, 4, 1255, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #2390 = ROUND_W_S_MM 5438 { 2389, 2, 1, 4, 719, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #2389 = ROUND_W_S 5439 { 2388, 2, 1, 4, 1255, 0, 0, 0, 0x4ULL, nullptr, OperandInfo205 }, // Inst #2388 = ROUND_W_MM 5440 { 2387, 2, 1, 4, 1309, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #2387 = ROUND_W_D_MMR6 5441 { 2386, 2, 1, 4, 719, 0, 0, 0, 0x4ULL, nullptr, OperandInfo206 }, // Inst #2386 = ROUND_W_D64 5442 { 2385, 2, 1, 4, 719, 0, 0, 0, 0x4ULL, nullptr, OperandInfo205 }, // Inst #2385 = ROUND_W_D32 5443 { 2384, 2, 1, 4, 1309, 0, 0, 0, 0x4ULL, nullptr, OperandInfo204 }, // Inst #2384 = ROUND_L_S_MMR6 5444 { 2383, 2, 1, 4, 719, 0, 0, 0, 0x4ULL, nullptr, OperandInfo204 }, // Inst #2383 = ROUND_L_S 5445 { 2382, 2, 1, 4, 1309, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #2382 = ROUND_L_D_MMR6 5446 { 2381, 2, 1, 4, 719, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #2381 = ROUND_L_D64 5447 { 2380, 3, 1, 4, 757, 0, 0, 0, 0x1ULL, nullptr, OperandInfo73 }, // Inst #2380 = ROTR_MM 5448 { 2379, 3, 1, 4, 756, 0, 0, 0, 0x1ULL, nullptr, OperandInfo72 }, // Inst #2379 = ROTRV_MM 5449 { 2378, 3, 1, 4, 720, 0, 0, 0, 0x1ULL, nullptr, OperandInfo72 }, // Inst #2378 = ROTRV 5450 { 2377, 3, 1, 4, 501, 0, 0, 0, 0x1ULL, nullptr, OperandInfo73 }, // Inst #2377 = ROTR 5451 { 2376, 2, 1, 4, 1328, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo207 }, // Inst #2376 = RINT_S_MMR6 5452 { 2375, 2, 1, 4, 1229, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo207 }, // Inst #2375 = RINT_S 5453 { 2374, 2, 1, 4, 1328, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo203 }, // Inst #2374 = RINT_D_MMR6 5454 { 2373, 2, 1, 4, 1230, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo203 }, // Inst #2373 = RINT_D 5455 { 2372, 2, 1, 4, 1599, 0, 0, 0, 0x6ULL, nullptr, OperandInfo344 }, // Inst #2372 = REPL_QB_MM 5456 { 2371, 2, 1, 4, 1433, 0, 0, 0, 0x6ULL, nullptr, OperandInfo344 }, // Inst #2371 = REPL_QB 5457 { 2370, 2, 1, 4, 1598, 0, 0, 0, 0x6ULL, nullptr, OperandInfo344 }, // Inst #2370 = REPL_PH_MM 5458 { 2369, 2, 1, 4, 1432, 0, 0, 0, 0x6ULL, nullptr, OperandInfo344 }, // Inst #2369 = REPL_PH 5459 { 2368, 2, 1, 4, 1597, 0, 0, 0, 0x6ULL, nullptr, OperandInfo343 }, // Inst #2368 = REPLV_QB_MM 5460 { 2367, 2, 1, 4, 1431, 0, 0, 0, 0x6ULL, nullptr, OperandInfo343 }, // Inst #2367 = REPLV_QB 5461 { 2366, 2, 1, 4, 1596, 0, 0, 0, 0x6ULL, nullptr, OperandInfo343 }, // Inst #2366 = REPLV_PH_MM 5462 { 2365, 2, 1, 4, 1430, 0, 0, 0, 0x6ULL, nullptr, OperandInfo343 }, // Inst #2365 = REPLV_PH 5463 { 2364, 2, 1, 4, 1288, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #2364 = RECIP_S_MM 5464 { 2363, 2, 1, 4, 654, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #2363 = RECIP_S 5465 { 2362, 2, 1, 4, 1289, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #2362 = RECIP_D64_MM 5466 { 2361, 2, 1, 4, 652, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #2361 = RECIP_D64 5467 { 2360, 2, 1, 4, 1289, 0, 0, 0, 0x4ULL, nullptr, OperandInfo248 }, // Inst #2360 = RECIP_D32_MM 5468 { 2359, 2, 1, 4, 652, 0, 0, 0, 0x4ULL, nullptr, OperandInfo248 }, // Inst #2359 = RECIP_D32 5469 { 2358, 2, 1, 4, 1036, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo45 }, // Inst #2358 = RDPGPR_MMR6 5470 { 2357, 3, 1, 4, 900, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo341 }, // Inst #2357 = RDHWR_MMR6 5471 { 2356, 3, 1, 4, 891, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo341 }, // Inst #2356 = RDHWR_MM 5472 { 2355, 3, 1, 4, 909, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo342 }, // Inst #2355 = RDHWR64 5473 { 2354, 3, 1, 4, 480, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo341 }, // Inst #2354 = RDHWR 5474 { 2353, 2, 1, 4, 1595, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, OperandInfo114 }, // Inst #2353 = RDDSP_MM 5475 { 2352, 2, 1, 4, 1429, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, OperandInfo114 }, // Inst #2352 = RDDSP 5476 { 2351, 2, 1, 4, 1594, 0, 0, 0, 0x6ULL, nullptr, OperandInfo337 }, // Inst #2351 = RADDU_W_QB_MM 5477 { 2350, 2, 1, 4, 1428, 0, 0, 0, 0x6ULL, nullptr, OperandInfo337 }, // Inst #2350 = RADDU_W_QB 5478 { 2349, 3, 1, 4, 645, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo173 }, // Inst #2349 = PUU_PS64 5479 { 2348, 3, 1, 4, 645, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo173 }, // Inst #2348 = PUL_PS64 5480 { 2347, 4, 1, 4, 1655, 0, 0, 0, 0x6ULL, nullptr, OperandInfo182 }, // Inst #2347 = PREPEND_MMR2 5481 { 2346, 4, 1, 4, 1491, 0, 0, 0, 0x6ULL, nullptr, OperandInfo182 }, // Inst #2346 = PREPEND 5482 { 2345, 3, 0, 4, 1087, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo202 }, // Inst #2345 = PREF_R6 5483 { 2344, 3, 0, 4, 1161, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo202 }, // Inst #2344 = PREF_MMR6 5484 { 2343, 3, 0, 4, 1139, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo202 }, // Inst #2343 = PREF_MM 5485 { 2342, 3, 0, 4, 1139, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo340 }, // Inst #2342 = PREFX_MM 5486 { 2341, 3, 0, 4, 1106, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo202 }, // Inst #2341 = PREFE_MM 5487 { 2340, 3, 0, 4, 469, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo202 }, // Inst #2340 = PREFE 5488 { 2339, 3, 0, 4, 468, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo202 }, // Inst #2339 = PREF 5489 { 2338, 4, 1, 4, 1654, 0, 0, 0, 0x6ULL, nullptr, OperandInfo339 }, // Inst #2338 = PRECR_SRA_R_PH_W_MMR2 5490 { 2337, 4, 1, 4, 1490, 0, 0, 0, 0x6ULL, nullptr, OperandInfo339 }, // Inst #2337 = PRECR_SRA_R_PH_W 5491 { 2336, 4, 1, 4, 1653, 0, 0, 0, 0x6ULL, nullptr, OperandInfo339 }, // Inst #2336 = PRECR_SRA_PH_W_MMR2 5492 { 2335, 4, 1, 4, 1489, 0, 0, 0, 0x6ULL, nullptr, OperandInfo339 }, // Inst #2335 = PRECR_SRA_PH_W 5493 { 2334, 3, 1, 4, 1652, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo172 }, // Inst #2334 = PRECR_QB_PH_MMR2 5494 { 2333, 3, 1, 4, 1488, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo172 }, // Inst #2333 = PRECR_QB_PH 5495 { 2332, 3, 1, 4, 1593, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList34, OperandInfo338 }, // Inst #2332 = PRECRQ_RS_PH_W_MM 5496 { 2331, 3, 1, 4, 1427, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList34, OperandInfo338 }, // Inst #2331 = PRECRQ_RS_PH_W 5497 { 2330, 3, 1, 4, 1592, 0, 0, 0, 0x6ULL, nullptr, OperandInfo172 }, // Inst #2330 = PRECRQ_QB_PH_MM 5498 { 2329, 3, 1, 4, 1426, 0, 0, 0, 0x6ULL, nullptr, OperandInfo172 }, // Inst #2329 = PRECRQ_QB_PH 5499 { 2328, 3, 1, 4, 1591, 0, 0, 0, 0x6ULL, nullptr, OperandInfo338 }, // Inst #2328 = PRECRQ_PH_W_MM 5500 { 2327, 3, 1, 4, 1425, 0, 0, 0, 0x6ULL, nullptr, OperandInfo338 }, // Inst #2327 = PRECRQ_PH_W 5501 { 2326, 3, 1, 4, 1590, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList34, OperandInfo172 }, // Inst #2326 = PRECRQU_S_QB_PH_MM 5502 { 2325, 3, 1, 4, 1424, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList34, OperandInfo172 }, // Inst #2325 = PRECRQU_S_QB_PH 5503 { 2324, 2, 1, 4, 1589, 0, 0, 0, 0x6ULL, nullptr, OperandInfo168 }, // Inst #2324 = PRECEU_PH_QBR_MM 5504 { 2323, 2, 1, 4, 1588, 0, 0, 0, 0x6ULL, nullptr, OperandInfo168 }, // Inst #2323 = PRECEU_PH_QBRA_MM 5505 { 2322, 2, 1, 4, 1422, 0, 0, 0, 0x6ULL, nullptr, OperandInfo168 }, // Inst #2322 = PRECEU_PH_QBRA 5506 { 2321, 2, 1, 4, 1423, 0, 0, 0, 0x6ULL, nullptr, OperandInfo168 }, // Inst #2321 = PRECEU_PH_QBR 5507 { 2320, 2, 1, 4, 1587, 0, 0, 0, 0x6ULL, nullptr, OperandInfo168 }, // Inst #2320 = PRECEU_PH_QBL_MM 5508 { 2319, 2, 1, 4, 1586, 0, 0, 0, 0x6ULL, nullptr, OperandInfo168 }, // Inst #2319 = PRECEU_PH_QBLA_MM 5509 { 2318, 2, 1, 4, 1420, 0, 0, 0, 0x6ULL, nullptr, OperandInfo168 }, // Inst #2318 = PRECEU_PH_QBLA 5510 { 2317, 2, 1, 4, 1421, 0, 0, 0, 0x6ULL, nullptr, OperandInfo168 }, // Inst #2317 = PRECEU_PH_QBL 5511 { 2316, 2, 1, 4, 1585, 0, 0, 0, 0x6ULL, nullptr, OperandInfo337 }, // Inst #2316 = PRECEQ_W_PHR_MM 5512 { 2315, 2, 1, 4, 1419, 0, 0, 0, 0x6ULL, nullptr, OperandInfo337 }, // Inst #2315 = PRECEQ_W_PHR 5513 { 2314, 2, 1, 4, 1584, 0, 0, 0, 0x6ULL, nullptr, OperandInfo337 }, // Inst #2314 = PRECEQ_W_PHL_MM 5514 { 2313, 2, 1, 4, 1418, 0, 0, 0, 0x6ULL, nullptr, OperandInfo337 }, // Inst #2313 = PRECEQ_W_PHL 5515 { 2312, 2, 1, 4, 1583, 0, 0, 0, 0x6ULL, nullptr, OperandInfo168 }, // Inst #2312 = PRECEQU_PH_QBR_MM 5516 { 2311, 2, 1, 4, 1582, 0, 0, 0, 0x6ULL, nullptr, OperandInfo168 }, // Inst #2311 = PRECEQU_PH_QBRA_MM 5517 { 2310, 2, 1, 4, 1416, 0, 0, 0, 0x6ULL, nullptr, OperandInfo168 }, // Inst #2310 = PRECEQU_PH_QBRA 5518 { 2309, 2, 1, 4, 1417, 0, 0, 0, 0x6ULL, nullptr, OperandInfo168 }, // Inst #2309 = PRECEQU_PH_QBR 5519 { 2308, 2, 1, 4, 1581, 0, 0, 0, 0x6ULL, nullptr, OperandInfo168 }, // Inst #2308 = PRECEQU_PH_QBL_MM 5520 { 2307, 2, 1, 4, 1580, 0, 0, 0, 0x6ULL, nullptr, OperandInfo168 }, // Inst #2307 = PRECEQU_PH_QBLA_MM 5521 { 2306, 2, 1, 4, 1414, 0, 0, 0, 0x6ULL, nullptr, OperandInfo168 }, // Inst #2306 = PRECEQU_PH_QBLA 5522 { 2305, 2, 1, 4, 1415, 0, 0, 0, 0x6ULL, nullptr, OperandInfo168 }, // Inst #2305 = PRECEQU_PH_QBL 5523 { 2304, 2, 1, 4, 1203, 0, 0, 0, 0x1ULL, nullptr, OperandInfo45 }, // Inst #2304 = POP 5524 { 2303, 3, 1, 4, 645, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo173 }, // Inst #2303 = PLU_PS64 5525 { 2302, 3, 1, 4, 645, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo173 }, // Inst #2302 = PLL_PS64 5526 { 2301, 3, 1, 4, 1579, 1, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL, ImplicitList11, OperandInfo172 }, // Inst #2301 = PICK_QB_MM 5527 { 2300, 3, 1, 4, 1413, 1, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL, ImplicitList11, OperandInfo172 }, // Inst #2300 = PICK_QB 5528 { 2299, 3, 1, 4, 1578, 1, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL, ImplicitList11, OperandInfo172 }, // Inst #2299 = PICK_PH_MM 5529 { 2298, 3, 1, 4, 1412, 1, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL, ImplicitList11, OperandInfo172 }, // Inst #2298 = PICK_PH 5530 { 2297, 2, 1, 4, 526, 0, 0, 0, 0x6ULL, nullptr, OperandInfo77 }, // Inst #2297 = PCNT_W 5531 { 2296, 2, 1, 4, 526, 0, 0, 0, 0x6ULL, nullptr, OperandInfo335 }, // Inst #2296 = PCNT_H 5532 { 2295, 2, 1, 4, 526, 0, 0, 0, 0x6ULL, nullptr, OperandInfo76 }, // Inst #2295 = PCNT_D 5533 { 2294, 2, 1, 4, 526, 0, 0, 0, 0x6ULL, nullptr, OperandInfo312 }, // Inst #2294 = PCNT_B 5534 { 2293, 3, 1, 4, 626, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #2293 = PCKOD_W 5535 { 2292, 3, 1, 4, 626, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #2292 = PCKOD_H 5536 { 2291, 3, 1, 4, 626, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #2291 = PCKOD_D 5537 { 2290, 3, 1, 4, 626, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #2290 = PCKOD_B 5538 { 2289, 3, 1, 4, 626, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #2289 = PCKEV_W 5539 { 2288, 3, 1, 4, 626, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #2288 = PCKEV_H 5540 { 2287, 3, 1, 4, 626, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #2287 = PCKEV_D 5541 { 2286, 3, 1, 4, 626, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #2286 = PCKEV_B 5542 { 2285, 0, 0, 4, 1051, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2285 = PAUSE_MMR6 5543 { 2284, 0, 0, 4, 1034, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2284 = PAUSE_MM 5544 { 2283, 0, 0, 4, 405, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr }, // Inst #2283 = PAUSE 5545 { 2282, 3, 1, 4, 1577, 0, 0, 0, 0x6ULL, nullptr, OperandInfo172 }, // Inst #2282 = PACKRL_PH_MM 5546 { 2281, 3, 1, 4, 1411, 0, 0, 0, 0x6ULL, nullptr, OperandInfo172 }, // Inst #2281 = PACKRL_PH 5547 { 2280, 3, 1, 2, 735, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, OperandInfo186 }, // Inst #2280 = OrRxRxRy16 5548 { 2279, 3, 1, 4, 755, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, OperandInfo73 }, // Inst #2279 = ORi_MM 5549 { 2278, 3, 1, 4, 809, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, OperandInfo70 }, // Inst #2278 = ORi64 5550 { 2277, 3, 1, 4, 500, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, OperandInfo73 }, // Inst #2277 = ORi 5551 { 2276, 3, 1, 4, 548, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #2276 = OR_V 5552 { 2275, 3, 1, 4, 795, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, OperandInfo72 }, // Inst #2275 = OR_MMR6 5553 { 2274, 3, 1, 4, 754, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, OperandInfo72 }, // Inst #2274 = OR_MM 5554 { 2273, 3, 1, 4, 796, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, OperandInfo73 }, // Inst #2273 = ORI_MMR6 5555 { 2272, 3, 1, 4, 549, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #2272 = ORI_B 5556 { 2271, 3, 1, 4, 843, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, OperandInfo71 }, // Inst #2271 = OR64 5557 { 2270, 3, 1, 2, 795, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo181 }, // Inst #2270 = OR16_MMR6 5558 { 2269, 3, 1, 2, 754, 0, 0, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo181 }, // Inst #2269 = OR16_MM 5559 { 2268, 3, 1, 4, 367, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, OperandInfo72 }, // Inst #2268 = OR 5560 { 2267, 2, 1, 2, 735, 0, 0, 0, 0x0ULL, nullptr, OperandInfo130 }, // Inst #2267 = NotRxRy16 5561 { 2266, 2, 1, 2, 735, 0, 0, 0, 0x0ULL, nullptr, OperandInfo130 }, // Inst #2266 = NegRxRy16 5562 { 2265, 2, 1, 2, 794, 0, 0, 0, 0x0ULL, nullptr, OperandInfo336 }, // Inst #2265 = NOT16_MMR6 5563 { 2264, 2, 1, 2, 753, 0, 0, 0, 0x0ULL, nullptr, OperandInfo336 }, // Inst #2264 = NOT16_MM 5564 { 2263, 3, 1, 4, 548, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #2263 = NOR_V 5565 { 2262, 3, 1, 4, 793, 0, 0, 0|(1ULL<<MCID::Commutable), 0x1ULL, nullptr, OperandInfo72 }, // Inst #2262 = NOR_MMR6 5566 { 2261, 3, 1, 4, 752, 0, 0, 0|(1ULL<<MCID::Commutable), 0x1ULL, nullptr, OperandInfo72 }, // Inst #2261 = NOR_MM 5567 { 2260, 3, 1, 4, 549, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #2260 = NORI_B 5568 { 2259, 3, 1, 4, 842, 0, 0, 0|(1ULL<<MCID::Commutable), 0x1ULL, nullptr, OperandInfo71 }, // Inst #2259 = NOR64 5569 { 2258, 3, 1, 4, 366, 0, 0, 0|(1ULL<<MCID::Commutable), 0x1ULL, nullptr, OperandInfo72 }, // Inst #2258 = NOR 5570 { 2257, 4, 1, 4, 1251, 0, 0, 0, 0x4ULL, nullptr, OperandInfo306 }, // Inst #2257 = NMSUB_S_MM 5571 { 2256, 4, 1, 4, 684, 0, 0, 0, 0x4ULL, nullptr, OperandInfo306 }, // Inst #2256 = NMSUB_S 5572 { 2255, 4, 1, 4, 683, 0, 0, 0, 0x4ULL, nullptr, OperandInfo305 }, // Inst #2255 = NMSUB_D64 5573 { 2254, 4, 1, 4, 1252, 0, 0, 0, 0x4ULL, nullptr, OperandInfo304 }, // Inst #2254 = NMSUB_D32_MM 5574 { 2253, 4, 1, 4, 683, 0, 0, 0, 0x4ULL, nullptr, OperandInfo304 }, // Inst #2253 = NMSUB_D32 5575 { 2252, 4, 1, 4, 1249, 0, 0, 0, 0x4ULL, nullptr, OperandInfo306 }, // Inst #2252 = NMADD_S_MM 5576 { 2251, 4, 1, 4, 682, 0, 0, 0, 0x4ULL, nullptr, OperandInfo306 }, // Inst #2251 = NMADD_S 5577 { 2250, 4, 1, 4, 681, 0, 0, 0, 0x4ULL, nullptr, OperandInfo305 }, // Inst #2250 = NMADD_D64 5578 { 2249, 4, 1, 4, 1250, 0, 0, 0, 0x4ULL, nullptr, OperandInfo304 }, // Inst #2249 = NMADD_D32_MM 5579 { 2248, 4, 1, 4, 681, 0, 0, 0, 0x4ULL, nullptr, OperandInfo304 }, // Inst #2248 = NMADD_D32 5580 { 2247, 2, 1, 4, 627, 0, 0, 0, 0x6ULL, nullptr, OperandInfo77 }, // Inst #2247 = NLZC_W 5581 { 2246, 2, 1, 4, 627, 0, 0, 0, 0x6ULL, nullptr, OperandInfo335 }, // Inst #2246 = NLZC_H 5582 { 2245, 2, 1, 4, 627, 0, 0, 0, 0x6ULL, nullptr, OperandInfo76 }, // Inst #2245 = NLZC_D 5583 { 2244, 2, 1, 4, 627, 0, 0, 0, 0x6ULL, nullptr, OperandInfo312 }, // Inst #2244 = NLZC_B 5584 { 2243, 2, 1, 4, 627, 0, 0, 0, 0x6ULL, nullptr, OperandInfo77 }, // Inst #2243 = NLOC_W 5585 { 2242, 2, 1, 4, 627, 0, 0, 0, 0x6ULL, nullptr, OperandInfo335 }, // Inst #2242 = NLOC_H 5586 { 2241, 2, 1, 4, 627, 0, 0, 0, 0x6ULL, nullptr, OperandInfo76 }, // Inst #2241 = NLOC_D 5587 { 2240, 2, 1, 4, 627, 0, 0, 0, 0x6ULL, nullptr, OperandInfo312 }, // Inst #2240 = NLOC_B 5588 { 2239, 2, 1, 2, 735, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo334 }, // Inst #2239 = MoveR3216 5589 { 2238, 2, 1, 2, 735, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo333 }, // Inst #2238 = Move32R16 5590 { 2237, 1, 1, 2, 735, 1, 0, 0, 0x0ULL, ImplicitList25, OperandInfo272 }, // Inst #2237 = Mflo16 5591 { 2236, 1, 1, 2, 735, 1, 0, 0|(1ULL<<MCID::MoveReg), 0x0ULL, ImplicitList23, OperandInfo272 }, // Inst #2236 = Mfhi16 5592 { 2235, 3, 1, 4, 1647, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList33, OperandInfo172 }, // Inst #2235 = MUL_S_PH_MMR2 5593 { 2234, 3, 1, 4, 1483, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList33, OperandInfo172 }, // Inst #2234 = MUL_S_PH 5594 { 2233, 3, 1, 4, 872, 0, 0, 0, 0x6ULL, nullptr, OperandInfo72 }, // Inst #2233 = MUL_R6 5595 { 2232, 3, 1, 4, 676, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #2232 = MUL_Q_W 5596 { 2231, 3, 1, 4, 676, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #2231 = MUL_Q_H 5597 { 2230, 3, 1, 4, 1646, 0, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList33, OperandInfo172 }, // Inst #2230 = MUL_PH_MMR2 5598 { 2229, 3, 1, 4, 1482, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList33, OperandInfo172 }, // Inst #2229 = MUL_PH 5599 { 2228, 3, 1, 4, 895, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, OperandInfo72 }, // Inst #2228 = MUL_MMR6 5600 { 2227, 3, 1, 4, 884, 0, 2, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, ImplicitList6, OperandInfo72 }, // Inst #2227 = MUL_MM 5601 { 2226, 3, 1, 4, 670, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #2226 = MULV_W 5602 { 2225, 3, 1, 4, 670, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #2225 = MULV_H 5603 { 2224, 3, 1, 4, 670, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #2224 = MULV_D 5604 { 2223, 3, 1, 4, 670, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #2223 = MULV_B 5605 { 2222, 3, 1, 4, 894, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo72 }, // Inst #2222 = MULU_MMR6 5606 { 2221, 3, 1, 4, 871, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo72 }, // Inst #2221 = MULU 5607 { 2220, 2, 0, 4, 879, 0, 2, 0|(1ULL<<MCID::Commutable), 0x1ULL, ImplicitList6, OperandInfo45 }, // Inst #2220 = MULTu_MM 5608 { 2219, 2, 0, 4, 488, 0, 2, 0|(1ULL<<MCID::Commutable), 0x1ULL, ImplicitList6, OperandInfo45 }, // Inst #2219 = MULTu 5609 { 2218, 2, 0, 4, 878, 0, 2, 0|(1ULL<<MCID::Commutable), 0x1ULL, ImplicitList6, OperandInfo45 }, // Inst #2218 = MULT_MM 5610 { 2217, 3, 1, 4, 1576, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo143 }, // Inst #2217 = MULT_DSP_MM 5611 { 2216, 3, 1, 4, 1410, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo143 }, // Inst #2216 = MULT_DSP 5612 { 2215, 3, 1, 4, 1575, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo143 }, // Inst #2215 = MULTU_DSP_MM 5613 { 2214, 3, 1, 4, 1409, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo143 }, // Inst #2214 = MULTU_DSP 5614 { 2213, 2, 0, 4, 487, 0, 2, 0|(1ULL<<MCID::Commutable), 0x1ULL, ImplicitList6, OperandInfo45 }, // Inst #2213 = MULT 5615 { 2212, 4, 1, 4, 1651, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #2212 = MULSA_W_PH_MMR2 5616 { 2211, 4, 1, 4, 1487, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #2211 = MULSA_W_PH 5617 { 2210, 4, 1, 4, 1574, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #2210 = MULSAQ_S_W_PH_MM 5618 { 2209, 4, 1, 4, 1408, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #2209 = MULSAQ_S_W_PH 5619 { 2208, 3, 1, 4, 675, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #2208 = MULR_Q_W 5620 { 2207, 3, 1, 4, 675, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #2207 = MULR_Q_H 5621 { 2206, 3, 1, 4, 1213, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo173 }, // Inst #2206 = MULR_PS64 5622 { 2205, 3, 1, 4, 1650, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList33, OperandInfo72 }, // Inst #2205 = MULQ_S_W_MMR2 5623 { 2204, 3, 1, 4, 1486, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList33, OperandInfo72 }, // Inst #2204 = MULQ_S_W 5624 { 2203, 3, 1, 4, 1649, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList33, OperandInfo172 }, // Inst #2203 = MULQ_S_PH_MMR2 5625 { 2202, 3, 1, 4, 1485, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList33, OperandInfo172 }, // Inst #2202 = MULQ_S_PH 5626 { 2201, 3, 1, 4, 1648, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList33, OperandInfo72 }, // Inst #2201 = MULQ_RS_W_MMR2 5627 { 2200, 3, 1, 4, 1484, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList33, OperandInfo72 }, // Inst #2200 = MULQ_RS_W 5628 { 2199, 3, 1, 4, 1573, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList33, OperandInfo172 }, // Inst #2199 = MULQ_RS_PH_MM 5629 { 2198, 3, 1, 4, 1407, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList33, OperandInfo172 }, // Inst #2198 = MULQ_RS_PH 5630 { 2197, 3, 1, 4, 1572, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList33, OperandInfo172 }, // Inst #2197 = MULEU_S_PH_QBR_MM 5631 { 2196, 3, 1, 4, 1406, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList33, OperandInfo172 }, // Inst #2196 = MULEU_S_PH_QBR 5632 { 2195, 3, 1, 4, 1571, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList33, OperandInfo172 }, // Inst #2195 = MULEU_S_PH_QBL_MM 5633 { 2194, 3, 1, 4, 1405, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList33, OperandInfo172 }, // Inst #2194 = MULEU_S_PH_QBL 5634 { 2193, 3, 1, 4, 1570, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList33, OperandInfo214 }, // Inst #2193 = MULEQ_S_W_PHR_MM 5635 { 2192, 3, 1, 4, 1404, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList33, OperandInfo214 }, // Inst #2192 = MULEQ_S_W_PHR 5636 { 2191, 3, 1, 4, 1569, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList33, OperandInfo214 }, // Inst #2191 = MULEQ_S_W_PHL_MM 5637 { 2190, 3, 1, 4, 1403, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList33, OperandInfo214 }, // Inst #2190 = MULEQ_S_W_PHL 5638 { 2189, 3, 1, 4, 486, 0, 2, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, ImplicitList6, OperandInfo72 }, // Inst #2189 = MUL 5639 { 2188, 3, 1, 4, 893, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, OperandInfo72 }, // Inst #2188 = MUH_MMR6 5640 { 2187, 3, 1, 4, 892, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, OperandInfo72 }, // Inst #2187 = MUHU_MMR6 5641 { 2186, 3, 1, 4, 870, 0, 0, 0, 0x6ULL, nullptr, OperandInfo72 }, // Inst #2186 = MUHU 5642 { 2185, 3, 1, 4, 869, 0, 0, 0, 0x6ULL, nullptr, OperandInfo72 }, // Inst #2185 = MUH 5643 { 2184, 5, 1, 4, 1064, 0, 0, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo310 }, // Inst #2184 = MTTR 5644 { 2183, 1, 0, 4, 1205, 0, 1, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList32, OperandInfo95 }, // Inst #2183 = MTP2 5645 { 2182, 1, 0, 4, 1205, 0, 1, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList31, OperandInfo95 }, // Inst #2182 = MTP1 5646 { 2181, 1, 0, 4, 1205, 0, 1, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList30, OperandInfo95 }, // Inst #2181 = MTP0 5647 { 2180, 1, 0, 4, 1205, 0, 4, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList29, OperandInfo95 }, // Inst #2180 = MTM2 5648 { 2179, 1, 0, 4, 1205, 0, 4, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList28, OperandInfo95 }, // Inst #2179 = MTM1 5649 { 2178, 1, 0, 4, 1205, 0, 4, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList27, OperandInfo95 }, // Inst #2178 = MTM0 5650 { 2177, 1, 0, 4, 890, 0, 1, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList25, OperandInfo58 }, // Inst #2177 = MTLO_MM 5651 { 2176, 2, 1, 4, 1568, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo332 }, // Inst #2176 = MTLO_DSP_MM 5652 { 2175, 2, 1, 4, 1356, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo332 }, // Inst #2175 = MTLO_DSP 5653 { 2174, 1, 0, 4, 908, 0, 1, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList26, OperandInfo95 }, // Inst #2174 = MTLO64 5654 { 2173, 1, 0, 4, 493, 0, 1, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList25, OperandInfo58 }, // Inst #2173 = MTLO 5655 { 2172, 3, 1, 4, 1567, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList4, OperandInfo331 }, // Inst #2172 = MTHLIP_MM 5656 { 2171, 3, 1, 4, 1354, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList4, OperandInfo331 }, // Inst #2171 = MTHLIP 5657 { 2170, 1, 0, 4, 890, 0, 1, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList23, OperandInfo58 }, // Inst #2170 = MTHI_MM 5658 { 2169, 2, 1, 4, 1566, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo330 }, // Inst #2169 = MTHI_DSP_MM 5659 { 2168, 2, 1, 4, 1355, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo330 }, // Inst #2168 = MTHI_DSP 5660 { 2167, 1, 0, 4, 908, 0, 1, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList24, OperandInfo95 }, // Inst #2167 = MTHI64 5661 { 2166, 1, 0, 4, 493, 0, 1, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList23, OperandInfo58 }, // Inst #2166 = MTHI 5662 { 2165, 3, 1, 4, 1079, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo128 }, // Inst #2165 = MTHGC0_MM 5663 { 2164, 3, 1, 4, 424, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo128 }, // Inst #2164 = MTHGC0 5664 { 2163, 2, 1, 4, 1045, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo222 }, // Inst #2163 = MTHC2_MMR6 5665 { 2162, 3, 1, 4, 1270, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo329 }, // Inst #2162 = MTHC1_D64_MM 5666 { 2161, 3, 1, 4, 687, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo329 }, // Inst #2161 = MTHC1_D64 5667 { 2160, 3, 1, 4, 1270, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo328 }, // Inst #2160 = MTHC1_D32_MM 5668 { 2159, 3, 1, 4, 687, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo328 }, // Inst #2159 = MTHC1_D32 5669 { 2158, 3, 1, 4, 1043, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo128 }, // Inst #2158 = MTHC0_MMR6 5670 { 2157, 3, 1, 4, 1078, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo128 }, // Inst #2157 = MTGC0_MM 5671 { 2156, 3, 1, 4, 423, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo128 }, // Inst #2156 = MTGC0 5672 { 2155, 2, 1, 4, 1045, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo222 }, // Inst #2155 = MTC2_MMR6 5673 { 2154, 3, 1, 4, 419, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo327 }, // Inst #2154 = MTC2 5674 { 2153, 2, 1, 4, 1313, 0, 0, 0|(1ULL<<MCID::Bitcast), 0x6ULL, nullptr, OperandInfo129 }, // Inst #2153 = MTC1_MMR6 5675 { 2152, 2, 1, 4, 1269, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL, nullptr, OperandInfo129 }, // Inst #2152 = MTC1_MM 5676 { 2151, 2, 1, 4, 1269, 0, 0, 0|(1ULL<<MCID::MoveReg), 0x4ULL, nullptr, OperandInfo135 }, // Inst #2151 = MTC1_D64_MM 5677 { 2150, 2, 1, 4, 686, 0, 0, 0|(1ULL<<MCID::MoveReg), 0x4ULL, nullptr, OperandInfo135 }, // Inst #2150 = MTC1_D64 5678 { 2149, 2, 1, 4, 686, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL, nullptr, OperandInfo129 }, // Inst #2149 = MTC1 5679 { 2148, 3, 1, 4, 1044, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo128 }, // Inst #2148 = MTC0_MMR6 5680 { 2147, 3, 1, 4, 417, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo128 }, // Inst #2147 = MTC0 5681 { 2146, 4, 1, 4, 1282, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo306 }, // Inst #2146 = MSUB_S_MM 5682 { 2145, 4, 1, 4, 680, 0, 0, 0, 0x4ULL, nullptr, OperandInfo306 }, // Inst #2145 = MSUB_S 5683 { 2144, 4, 1, 4, 674, 0, 0, 0, 0x6ULL, nullptr, OperandInfo60 }, // Inst #2144 = MSUB_Q_W 5684 { 2143, 4, 1, 4, 674, 0, 0, 0, 0x6ULL, nullptr, OperandInfo61 }, // Inst #2143 = MSUB_Q_H 5685 { 2142, 2, 0, 4, 882, 2, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList20, OperandInfo45 }, // Inst #2142 = MSUB_MM 5686 { 2141, 4, 1, 4, 1565, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #2141 = MSUB_DSP_MM 5687 { 2140, 4, 1, 4, 1402, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #2140 = MSUB_DSP 5688 { 2139, 4, 1, 4, 679, 0, 0, 0, 0x4ULL, nullptr, OperandInfo305 }, // Inst #2139 = MSUB_D64 5689 { 2138, 4, 1, 4, 1283, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo304 }, // Inst #2138 = MSUB_D32_MM 5690 { 2137, 4, 1, 4, 679, 0, 0, 0, 0x4ULL, nullptr, OperandInfo304 }, // Inst #2137 = MSUB_D32 5691 { 2136, 4, 1, 4, 668, 0, 0, 0, 0x6ULL, nullptr, OperandInfo60 }, // Inst #2136 = MSUBV_W 5692 { 2135, 4, 1, 4, 668, 0, 0, 0, 0x6ULL, nullptr, OperandInfo61 }, // Inst #2135 = MSUBV_H 5693 { 2134, 4, 1, 4, 668, 0, 0, 0, 0x6ULL, nullptr, OperandInfo59 }, // Inst #2134 = MSUBV_D 5694 { 2133, 4, 1, 4, 668, 0, 0, 0, 0x6ULL, nullptr, OperandInfo196 }, // Inst #2133 = MSUBV_B 5695 { 2132, 2, 0, 4, 883, 2, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList20, OperandInfo45 }, // Inst #2132 = MSUBU_MM 5696 { 2131, 4, 1, 4, 1564, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #2131 = MSUBU_DSP_MM 5697 { 2130, 4, 1, 4, 1401, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #2130 = MSUBU_DSP 5698 { 2129, 2, 0, 4, 856, 2, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList20, OperandInfo45 }, // Inst #2129 = MSUBU 5699 { 2128, 4, 1, 4, 673, 0, 0, 0, 0x6ULL, nullptr, OperandInfo60 }, // Inst #2128 = MSUBR_Q_W 5700 { 2127, 4, 1, 4, 673, 0, 0, 0, 0x6ULL, nullptr, OperandInfo61 }, // Inst #2127 = MSUBR_Q_H 5701 { 2126, 4, 1, 4, 1332, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo303 }, // Inst #2126 = MSUBF_S_MMR6 5702 { 2125, 4, 1, 4, 1235, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo303 }, // Inst #2125 = MSUBF_S 5703 { 2124, 4, 1, 4, 1331, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo302 }, // Inst #2124 = MSUBF_D_MMR6 5704 { 2123, 4, 1, 4, 1237, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo302 }, // Inst #2123 = MSUBF_D 5705 { 2122, 2, 0, 4, 855, 2, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList20, OperandInfo45 }, // Inst #2122 = MSUB 5706 { 2121, 4, 1, 4, 1245, 0, 0, 0, 0x4ULL, nullptr, OperandInfo326 }, // Inst #2121 = MOVZ_I_S_MM 5707 { 2120, 4, 1, 4, 709, 0, 0, 0, 0x4ULL, nullptr, OperandInfo326 }, // Inst #2120 = MOVZ_I_S 5708 { 2119, 4, 1, 4, 1563, 0, 0, 0, 0x4ULL, nullptr, OperandInfo324 }, // Inst #2119 = MOVZ_I_MM 5709 { 2118, 4, 1, 4, 911, 0, 0, 0, 0x4ULL, nullptr, OperandInfo325 }, // Inst #2118 = MOVZ_I_I64 5710 { 2117, 4, 1, 4, 483, 0, 0, 0, 0x4ULL, nullptr, OperandInfo324 }, // Inst #2117 = MOVZ_I_I 5711 { 2116, 4, 1, 4, 708, 0, 0, 0, 0x4ULL, nullptr, OperandInfo323 }, // Inst #2116 = MOVZ_I_D64 5712 { 2115, 4, 1, 4, 1244, 0, 0, 0, 0x4ULL, nullptr, OperandInfo322 }, // Inst #2115 = MOVZ_I_D32_MM 5713 { 2114, 4, 1, 4, 708, 0, 0, 0, 0x4ULL, nullptr, OperandInfo322 }, // Inst #2114 = MOVZ_I_D32 5714 { 2113, 4, 1, 4, 1217, 0, 0, 0, 0x4ULL, nullptr, OperandInfo321 }, // Inst #2113 = MOVZ_I64_S 5715 { 2112, 4, 1, 4, 911, 0, 0, 0, 0x4ULL, nullptr, OperandInfo320 }, // Inst #2112 = MOVZ_I64_I64 5716 { 2111, 4, 1, 4, 911, 0, 0, 0, 0x4ULL, nullptr, OperandInfo319 }, // Inst #2111 = MOVZ_I64_I 5717 { 2110, 4, 1, 4, 1220, 0, 0, 0, 0x4ULL, nullptr, OperandInfo318 }, // Inst #2110 = MOVZ_I64_D64 5718 { 2109, 4, 1, 4, 1243, 0, 0, 0, 0x4ULL, nullptr, OperandInfo317 }, // Inst #2109 = MOVT_S_MM 5719 { 2108, 4, 1, 4, 534, 0, 0, 0, 0x4ULL, nullptr, OperandInfo317 }, // Inst #2108 = MOVT_S 5720 { 2107, 4, 1, 4, 889, 0, 0, 0, 0x4ULL, nullptr, OperandInfo315 }, // Inst #2107 = MOVT_I_MM 5721 { 2106, 4, 1, 4, 1215, 0, 0, 0, 0x4ULL, nullptr, OperandInfo316 }, // Inst #2106 = MOVT_I64 5722 { 2105, 4, 1, 4, 698, 0, 0, 0, 0x4ULL, nullptr, OperandInfo315 }, // Inst #2105 = MOVT_I 5723 { 2104, 4, 1, 4, 533, 0, 0, 0, 0x4ULL, nullptr, OperandInfo314 }, // Inst #2104 = MOVT_D64 5724 { 2103, 4, 1, 4, 1242, 0, 0, 0, 0x4ULL, nullptr, OperandInfo313 }, // Inst #2103 = MOVT_D32_MM 5725 { 2102, 4, 1, 4, 533, 0, 0, 0, 0x4ULL, nullptr, OperandInfo313 }, // Inst #2102 = MOVT_D32 5726 { 2101, 4, 1, 4, 1241, 0, 0, 0, 0x4ULL, nullptr, OperandInfo326 }, // Inst #2101 = MOVN_I_S_MM 5727 { 2100, 4, 1, 4, 707, 0, 0, 0, 0x4ULL, nullptr, OperandInfo326 }, // Inst #2100 = MOVN_I_S 5728 { 2099, 4, 1, 4, 1562, 0, 0, 0, 0x4ULL, nullptr, OperandInfo324 }, // Inst #2099 = MOVN_I_MM 5729 { 2098, 4, 1, 4, 910, 0, 0, 0, 0x4ULL, nullptr, OperandInfo325 }, // Inst #2098 = MOVN_I_I64 5730 { 2097, 4, 1, 4, 482, 0, 0, 0, 0x4ULL, nullptr, OperandInfo324 }, // Inst #2097 = MOVN_I_I 5731 { 2096, 4, 1, 4, 706, 0, 0, 0, 0x4ULL, nullptr, OperandInfo323 }, // Inst #2096 = MOVN_I_D64 5732 { 2095, 4, 1, 4, 1240, 0, 0, 0, 0x4ULL, nullptr, OperandInfo322 }, // Inst #2095 = MOVN_I_D32_MM 5733 { 2094, 4, 1, 4, 706, 0, 0, 0, 0x4ULL, nullptr, OperandInfo322 }, // Inst #2094 = MOVN_I_D32 5734 { 2093, 4, 1, 4, 1219, 0, 0, 0, 0x4ULL, nullptr, OperandInfo321 }, // Inst #2093 = MOVN_I64_S 5735 { 2092, 4, 1, 4, 910, 0, 0, 0, 0x4ULL, nullptr, OperandInfo320 }, // Inst #2092 = MOVN_I64_I64 5736 { 2091, 4, 1, 4, 910, 0, 0, 0, 0x4ULL, nullptr, OperandInfo319 }, // Inst #2091 = MOVN_I64_I 5737 { 2090, 4, 1, 4, 1218, 0, 0, 0, 0x4ULL, nullptr, OperandInfo318 }, // Inst #2090 = MOVN_I64_D64 5738 { 2089, 4, 1, 4, 1239, 0, 0, 0, 0x4ULL, nullptr, OperandInfo317 }, // Inst #2089 = MOVF_S_MM 5739 { 2088, 4, 1, 4, 532, 0, 0, 0, 0x4ULL, nullptr, OperandInfo317 }, // Inst #2088 = MOVF_S 5740 { 2087, 4, 1, 4, 888, 0, 0, 0, 0x4ULL, nullptr, OperandInfo315 }, // Inst #2087 = MOVF_I_MM 5741 { 2086, 4, 1, 4, 1216, 0, 0, 0, 0x4ULL, nullptr, OperandInfo316 }, // Inst #2086 = MOVF_I64 5742 { 2085, 4, 1, 4, 697, 0, 0, 0, 0x4ULL, nullptr, OperandInfo315 }, // Inst #2085 = MOVF_I 5743 { 2084, 4, 1, 4, 531, 0, 0, 0, 0x4ULL, nullptr, OperandInfo314 }, // Inst #2084 = MOVF_D64 5744 { 2083, 4, 1, 4, 1238, 0, 0, 0, 0x4ULL, nullptr, OperandInfo313 }, // Inst #2083 = MOVF_D32_MM 5745 { 2082, 4, 1, 4, 531, 0, 0, 0, 0x4ULL, nullptr, OperandInfo313 }, // Inst #2082 = MOVF_D32 5746 { 2081, 2, 1, 4, 546, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo312 }, // Inst #2081 = MOVE_V 5747 { 2080, 4, 2, 2, 1561, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo311 }, // Inst #2080 = MOVEP_MMR6 5748 { 2079, 4, 2, 2, 751, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo311 }, // Inst #2079 = MOVEP_MM 5749 { 2078, 2, 1, 2, 792, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo45 }, // Inst #2078 = MOVE16_MMR6 5750 { 2077, 2, 1, 2, 750, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo45 }, // Inst #2077 = MOVE16_MM 5751 { 2076, 3, 1, 4, 613, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #2076 = MOD_U_W 5752 { 2075, 3, 1, 4, 613, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #2075 = MOD_U_H 5753 { 2074, 3, 1, 4, 613, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #2074 = MOD_U_D 5754 { 2073, 3, 1, 4, 613, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #2073 = MOD_U_B 5755 { 2072, 3, 1, 4, 613, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #2072 = MOD_S_W 5756 { 2071, 3, 1, 4, 613, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #2071 = MOD_S_H 5757 { 2070, 3, 1, 4, 613, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #2070 = MOD_S_D 5758 { 2069, 3, 1, 4, 613, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #2069 = MOD_S_B 5759 { 2068, 3, 1, 4, 897, 0, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, OperandInfo72 }, // Inst #2068 = MOD_MMR6 5760 { 2067, 3, 1, 4, 896, 0, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, OperandInfo72 }, // Inst #2067 = MODU_MMR6 5761 { 2066, 3, 1, 4, 874, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, OperandInfo72 }, // Inst #2066 = MODU 5762 { 2065, 3, 1, 4, 1560, 0, 0, 0, 0x6ULL, nullptr, OperandInfo72 }, // Inst #2065 = MODSUB_MM 5763 { 2064, 3, 1, 4, 1400, 0, 0, 0, 0x6ULL, nullptr, OperandInfo72 }, // Inst #2064 = MODSUB 5764 { 2063, 3, 1, 4, 873, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, OperandInfo72 }, // Inst #2063 = MOD 5765 { 2062, 3, 1, 4, 618, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #2062 = MIN_U_W 5766 { 2061, 3, 1, 4, 618, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #2061 = MIN_U_H 5767 { 2060, 3, 1, 4, 618, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #2060 = MIN_U_D 5768 { 2059, 3, 1, 4, 618, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #2059 = MIN_U_B 5769 { 2058, 3, 1, 4, 617, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #2058 = MIN_S_W 5770 { 2057, 3, 1, 4, 1319, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo250 }, // Inst #2057 = MIN_S_MMR6 5771 { 2056, 3, 1, 4, 617, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #2056 = MIN_S_H 5772 { 2055, 3, 1, 4, 617, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #2055 = MIN_S_D 5773 { 2054, 3, 1, 4, 617, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #2054 = MIN_S_B 5774 { 2053, 3, 1, 4, 1225, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo250 }, // Inst #2053 = MIN_S 5775 { 2052, 3, 1, 4, 1318, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo173 }, // Inst #2052 = MIN_D_MMR6 5776 { 2051, 3, 1, 4, 1226, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo173 }, // Inst #2051 = MIN_D 5777 { 2050, 3, 1, 4, 619, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #2050 = MIN_A_W 5778 { 2049, 3, 1, 4, 619, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #2049 = MIN_A_H 5779 { 2048, 3, 1, 4, 619, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #2048 = MIN_A_D 5780 { 2047, 3, 1, 4, 619, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #2047 = MIN_A_B 5781 { 2046, 3, 1, 4, 620, 0, 0, 0, 0x6ULL, nullptr, OperandInfo179 }, // Inst #2046 = MINI_U_W 5782 { 2045, 3, 1, 4, 620, 0, 0, 0, 0x6ULL, nullptr, OperandInfo178 }, // Inst #2045 = MINI_U_H 5783 { 2044, 3, 1, 4, 620, 0, 0, 0, 0x6ULL, nullptr, OperandInfo177 }, // Inst #2044 = MINI_U_D 5784 { 2043, 3, 1, 4, 620, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #2043 = MINI_U_B 5785 { 2042, 3, 1, 4, 620, 0, 0, 0, 0x6ULL, nullptr, OperandInfo179 }, // Inst #2042 = MINI_S_W 5786 { 2041, 3, 1, 4, 620, 0, 0, 0, 0x6ULL, nullptr, OperandInfo178 }, // Inst #2041 = MINI_S_H 5787 { 2040, 3, 1, 4, 620, 0, 0, 0, 0x6ULL, nullptr, OperandInfo177 }, // Inst #2040 = MINI_S_D 5788 { 2039, 3, 1, 4, 620, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #2039 = MINI_S_B 5789 { 2038, 3, 1, 4, 1323, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo250 }, // Inst #2038 = MINA_S_MMR6 5790 { 2037, 3, 1, 4, 1226, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo250 }, // Inst #2037 = MINA_S 5791 { 2036, 3, 1, 4, 1322, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo173 }, // Inst #2036 = MINA_D_MMR6 5792 { 2035, 3, 1, 4, 1225, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo173 }, // Inst #2035 = MINA_D 5793 { 2034, 5, 1, 4, 1063, 0, 0, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo310 }, // Inst #2034 = MFTR 5794 { 2033, 1, 1, 4, 887, 1, 0, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList21, OperandInfo58 }, // Inst #2033 = MFLO_MM 5795 { 2032, 2, 1, 4, 1559, 0, 0, 0, 0x6ULL, nullptr, OperandInfo119 }, // Inst #2032 = MFLO_DSP_MM 5796 { 2031, 2, 1, 4, 1399, 0, 0, 0|(1ULL<<MCID::MoveReg), 0x6ULL, nullptr, OperandInfo119 }, // Inst #2031 = MFLO_DSP 5797 { 2030, 1, 1, 4, 906, 1, 0, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList22, OperandInfo95 }, // Inst #2030 = MFLO64 5798 { 2029, 1, 1, 2, 887, 1, 0, 0|(1ULL<<MCID::MoveReg), 0x0ULL, ImplicitList21, OperandInfo58 }, // Inst #2029 = MFLO16_MM 5799 { 2028, 1, 1, 4, 478, 1, 0, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList21, OperandInfo58 }, // Inst #2028 = MFLO 5800 { 2027, 1, 1, 4, 887, 1, 0, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList21, OperandInfo58 }, // Inst #2027 = MFHI_MM 5801 { 2026, 2, 1, 4, 1558, 0, 0, 0, 0x6ULL, nullptr, OperandInfo119 }, // Inst #2026 = MFHI_DSP_MM 5802 { 2025, 2, 1, 4, 1398, 0, 0, 0|(1ULL<<MCID::MoveReg), 0x6ULL, nullptr, OperandInfo119 }, // Inst #2025 = MFHI_DSP 5803 { 2024, 1, 1, 4, 906, 1, 0, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList22, OperandInfo95 }, // Inst #2024 = MFHI64 5804 { 2023, 1, 1, 2, 887, 1, 0, 0|(1ULL<<MCID::MoveReg), 0x0ULL, ImplicitList21, OperandInfo58 }, // Inst #2023 = MFHI16_MM 5805 { 2022, 1, 1, 4, 478, 1, 0, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList21, OperandInfo58 }, // Inst #2022 = MFHI 5806 { 2021, 3, 1, 4, 1077, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo120 }, // Inst #2021 = MFHGC0_MM 5807 { 2020, 3, 1, 4, 422, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo120 }, // Inst #2020 = MFHGC0 5808 { 2019, 2, 1, 4, 1042, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo209 }, // Inst #2019 = MFHC2_MMR6 5809 { 2018, 2, 1, 4, 1268, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo307 }, // Inst #2018 = MFHC1_D64_MM 5810 { 2017, 2, 1, 4, 696, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo307 }, // Inst #2017 = MFHC1_D64 5811 { 2016, 2, 1, 4, 1268, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo309 }, // Inst #2016 = MFHC1_D32_MM 5812 { 2015, 2, 1, 4, 696, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo309 }, // Inst #2015 = MFHC1_D32 5813 { 2014, 3, 1, 4, 1040, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo120 }, // Inst #2014 = MFHC0_MMR6 5814 { 2013, 3, 1, 4, 1076, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo120 }, // Inst #2013 = MFGC0_MM 5815 { 2012, 3, 1, 4, 421, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo120 }, // Inst #2012 = MFGC0 5816 { 2011, 2, 1, 4, 1042, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo209 }, // Inst #2011 = MFC2_MMR6 5817 { 2010, 3, 1, 4, 418, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo308 }, // Inst #2010 = MFC2 5818 { 2009, 2, 1, 4, 1312, 0, 0, 0|(1ULL<<MCID::Bitcast), 0x6ULL, nullptr, OperandInfo121 }, // Inst #2009 = MFC1_MMR6 5819 { 2008, 2, 1, 4, 1267, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL, nullptr, OperandInfo121 }, // Inst #2008 = MFC1_MM 5820 { 2007, 2, 1, 4, 695, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo307 }, // Inst #2007 = MFC1_D64 5821 { 2006, 2, 1, 4, 695, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL, nullptr, OperandInfo121 }, // Inst #2006 = MFC1 5822 { 2005, 3, 1, 4, 1041, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo120 }, // Inst #2005 = MFC0_MMR6 5823 { 2004, 3, 1, 4, 416, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo120 }, // Inst #2004 = MFC0 5824 { 2003, 3, 1, 4, 618, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #2003 = MAX_U_W 5825 { 2002, 3, 1, 4, 618, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #2002 = MAX_U_H 5826 { 2001, 3, 1, 4, 618, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #2001 = MAX_U_D 5827 { 2000, 3, 1, 4, 618, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #2000 = MAX_U_B 5828 { 1999, 3, 1, 4, 617, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1999 = MAX_S_W 5829 { 1998, 3, 1, 4, 1317, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo250 }, // Inst #1998 = MAX_S_MMR6 5830 { 1997, 3, 1, 4, 617, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #1997 = MAX_S_H 5831 { 1996, 3, 1, 4, 617, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1996 = MAX_S_D 5832 { 1995, 3, 1, 4, 617, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #1995 = MAX_S_B 5833 { 1994, 3, 1, 4, 1223, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo250 }, // Inst #1994 = MAX_S 5834 { 1993, 3, 1, 4, 1316, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo173 }, // Inst #1993 = MAX_D_MMR6 5835 { 1992, 3, 1, 4, 1224, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo173 }, // Inst #1992 = MAX_D 5836 { 1991, 3, 1, 4, 619, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1991 = MAX_A_W 5837 { 1990, 3, 1, 4, 619, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #1990 = MAX_A_H 5838 { 1989, 3, 1, 4, 619, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1989 = MAX_A_D 5839 { 1988, 3, 1, 4, 619, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #1988 = MAX_A_B 5840 { 1987, 3, 1, 4, 620, 0, 0, 0, 0x6ULL, nullptr, OperandInfo179 }, // Inst #1987 = MAXI_U_W 5841 { 1986, 3, 1, 4, 620, 0, 0, 0, 0x6ULL, nullptr, OperandInfo178 }, // Inst #1986 = MAXI_U_H 5842 { 1985, 3, 1, 4, 620, 0, 0, 0, 0x6ULL, nullptr, OperandInfo177 }, // Inst #1985 = MAXI_U_D 5843 { 1984, 3, 1, 4, 620, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #1984 = MAXI_U_B 5844 { 1983, 3, 1, 4, 620, 0, 0, 0, 0x6ULL, nullptr, OperandInfo179 }, // Inst #1983 = MAXI_S_W 5845 { 1982, 3, 1, 4, 620, 0, 0, 0, 0x6ULL, nullptr, OperandInfo178 }, // Inst #1982 = MAXI_S_H 5846 { 1981, 3, 1, 4, 620, 0, 0, 0, 0x6ULL, nullptr, OperandInfo177 }, // Inst #1981 = MAXI_S_D 5847 { 1980, 3, 1, 4, 620, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #1980 = MAXI_S_B 5848 { 1979, 3, 1, 4, 1321, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo250 }, // Inst #1979 = MAXA_S_MMR6 5849 { 1978, 3, 1, 4, 1223, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo250 }, // Inst #1978 = MAXA_S 5850 { 1977, 3, 1, 4, 1320, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo173 }, // Inst #1977 = MAXA_D_MMR6 5851 { 1976, 3, 1, 4, 1224, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo173 }, // Inst #1976 = MAXA_D 5852 { 1975, 4, 1, 4, 1557, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1975 = MAQ_S_W_PHR_MM 5853 { 1974, 4, 1, 4, 1397, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1974 = MAQ_S_W_PHR 5854 { 1973, 4, 1, 4, 1556, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1973 = MAQ_S_W_PHL_MM 5855 { 1972, 4, 1, 4, 1396, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1972 = MAQ_S_W_PHL 5856 { 1971, 4, 1, 4, 1555, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1971 = MAQ_SA_W_PHR_MM 5857 { 1970, 4, 1, 4, 1395, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1970 = MAQ_SA_W_PHR 5858 { 1969, 4, 1, 4, 1554, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1969 = MAQ_SA_W_PHL_MM 5859 { 1968, 4, 1, 4, 1394, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1968 = MAQ_SA_W_PHL 5860 { 1967, 4, 1, 4, 1253, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo306 }, // Inst #1967 = MADD_S_MM 5861 { 1966, 4, 1, 4, 678, 0, 0, 0, 0x4ULL, nullptr, OperandInfo306 }, // Inst #1966 = MADD_S 5862 { 1965, 4, 1, 4, 672, 0, 0, 0, 0x6ULL, nullptr, OperandInfo60 }, // Inst #1965 = MADD_Q_W 5863 { 1964, 4, 1, 4, 672, 0, 0, 0, 0x6ULL, nullptr, OperandInfo61 }, // Inst #1964 = MADD_Q_H 5864 { 1963, 2, 0, 4, 880, 2, 2, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList20, OperandInfo45 }, // Inst #1963 = MADD_MM 5865 { 1962, 4, 1, 4, 1553, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #1962 = MADD_DSP_MM 5866 { 1961, 4, 1, 4, 1393, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #1961 = MADD_DSP 5867 { 1960, 4, 1, 4, 677, 0, 0, 0, 0x4ULL, nullptr, OperandInfo305 }, // Inst #1960 = MADD_D64 5868 { 1959, 4, 1, 4, 1254, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo304 }, // Inst #1959 = MADD_D32_MM 5869 { 1958, 4, 1, 4, 677, 0, 0, 0, 0x4ULL, nullptr, OperandInfo304 }, // Inst #1958 = MADD_D32 5870 { 1957, 4, 1, 4, 669, 0, 0, 0, 0x6ULL, nullptr, OperandInfo60 }, // Inst #1957 = MADDV_W 5871 { 1956, 4, 1, 4, 669, 0, 0, 0, 0x6ULL, nullptr, OperandInfo61 }, // Inst #1956 = MADDV_H 5872 { 1955, 4, 1, 4, 669, 0, 0, 0, 0x6ULL, nullptr, OperandInfo59 }, // Inst #1955 = MADDV_D 5873 { 1954, 4, 1, 4, 669, 0, 0, 0, 0x6ULL, nullptr, OperandInfo196 }, // Inst #1954 = MADDV_B 5874 { 1953, 2, 0, 4, 881, 2, 2, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList20, OperandInfo45 }, // Inst #1953 = MADDU_MM 5875 { 1952, 4, 1, 4, 1552, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #1952 = MADDU_DSP_MM 5876 { 1951, 4, 1, 4, 1392, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #1951 = MADDU_DSP 5877 { 1950, 2, 0, 4, 854, 2, 2, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList20, OperandInfo45 }, // Inst #1950 = MADDU 5878 { 1949, 4, 1, 4, 671, 0, 0, 0, 0x6ULL, nullptr, OperandInfo60 }, // Inst #1949 = MADDR_Q_W 5879 { 1948, 4, 1, 4, 671, 0, 0, 0, 0x6ULL, nullptr, OperandInfo61 }, // Inst #1948 = MADDR_Q_H 5880 { 1947, 4, 1, 4, 1330, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo303 }, // Inst #1947 = MADDF_S_MMR6 5881 { 1946, 4, 1, 4, 1234, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo303 }, // Inst #1946 = MADDF_S 5882 { 1945, 4, 1, 4, 1329, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo302 }, // Inst #1945 = MADDF_D_MMR6 5883 { 1944, 4, 1, 4, 1236, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo302 }, // Inst #1944 = MADDF_D 5884 { 1943, 2, 0, 4, 853, 2, 2, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList20, OperandInfo45 }, // Inst #1943 = MADD 5885 { 1942, 3, 1, 4, 1113, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo185 }, // Inst #1942 = LwRxSpImmX16 5886 { 1941, 3, 1, 4, 1113, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo300 }, // Inst #1941 = LwRxRyOffMemX16 5887 { 1940, 3, 1, 4, 1113, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo301 }, // Inst #1940 = LwRxPcTcpX16 5888 { 1939, 3, 1, 2, 1113, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo301 }, // Inst #1939 = LwRxPcTcp16 5889 { 1938, 2, 1, 4, 735, 0, 0, 0, 0x0ULL, nullptr, OperandInfo183 }, // Inst #1938 = LiRxImmX16 5890 { 1937, 2, 1, 4, 735, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo183 }, // Inst #1937 = LiRxImmAlignX16 5891 { 1936, 2, 1, 2, 735, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo183 }, // Inst #1936 = LiRxImm16 5892 { 1935, 3, 1, 4, 1112, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo300 }, // Inst #1935 = LhuRxRyOffMemX16 5893 { 1934, 3, 1, 4, 1111, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo300 }, // Inst #1934 = LhRxRyOffMemX16 5894 { 1933, 3, 1, 4, 1110, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo300 }, // Inst #1933 = LbuRxRyOffMemX16 5895 { 1932, 3, 1, 4, 1109, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo300 }, // Inst #1932 = LbRxRyOffMemX16 5896 { 1931, 3, 1, 4, 1165, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo113 }, // Inst #1931 = LWu 5897 { 1930, 3, 1, 4, 1152, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, OperandInfo96 }, // Inst #1930 = LW_MMR6 5898 { 1929, 3, 1, 4, 1123, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo96 }, // Inst #1929 = LW_MM 5899 { 1928, 3, 1, 4, 1551, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, OperandInfo274 }, // Inst #1928 = LWX_MM 5900 { 1927, 3, 1, 4, 1129, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, nullptr, OperandInfo274 }, // Inst #1927 = LWXS_MM 5901 { 1926, 3, 1, 4, 1299, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, OperandInfo299 }, // Inst #1926 = LWXC1_MM 5902 { 1925, 3, 1, 4, 713, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, OperandInfo299 }, // Inst #1925 = LWXC1 5903 { 1924, 3, 1, 4, 1391, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, OperandInfo274 }, // Inst #1924 = LWX 5904 { 1923, 3, 1, 4, 1128, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo96 }, // Inst #1923 = LWU_MM 5905 { 1922, 2, 1, 4, 1184, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo114 }, // Inst #1922 = LWUPC 5906 { 1921, 3, 1, 2, 1123, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo298 }, // Inst #1921 = LWSP_MM 5907 { 1920, 4, 1, 4, 1127, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo295 }, // Inst #1920 = LWR_MM 5908 { 1919, 4, 1, 4, 1097, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo295 }, // Inst #1919 = LWRE_MM 5909 { 1918, 4, 1, 4, 451, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo295 }, // Inst #1918 = LWRE 5910 { 1917, 4, 1, 4, 1172, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo283 }, // Inst #1917 = LWR64 5911 { 1916, 4, 1, 4, 449, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo295 }, // Inst #1916 = LWR 5912 { 1915, 4, 2, 4, 1126, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo297 }, // Inst #1915 = LWP_MM 5913 { 1914, 2, 1, 4, 1151, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo114 }, // Inst #1914 = LWPC_MMR6 5914 { 1913, 2, 1, 4, 447, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo114 }, // Inst #1913 = LWPC 5915 { 1912, 3, 1, 4, 1125, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo110 }, // Inst #1912 = LWM32_MM 5916 { 1911, 3, 1, 2, 1149, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo296 }, // Inst #1911 = LWM16_MMR6 5917 { 1910, 3, 1, 2, 1125, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo296 }, // Inst #1910 = LWM16_MM 5918 { 1909, 4, 1, 4, 1124, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo295 }, // Inst #1909 = LWL_MM 5919 { 1908, 4, 1, 4, 1096, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo295 }, // Inst #1908 = LWLE_MM 5920 { 1907, 4, 1, 4, 450, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo295 }, // Inst #1907 = LWLE 5921 { 1906, 4, 1, 4, 1171, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo283 }, // Inst #1906 = LWL64 5922 { 1905, 4, 1, 4, 448, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo295 }, // Inst #1905 = LWL 5923 { 1904, 3, 1, 2, 1123, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo294 }, // Inst #1904 = LWGP_MM 5924 { 1903, 3, 1, 4, 1095, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo96 }, // Inst #1903 = LWE_MM 5925 { 1902, 3, 1, 4, 445, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo96 }, // Inst #1902 = LWE 5926 { 1901, 3, 1, 4, 1506, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo293 }, // Inst #1901 = LWDSP_MM 5927 { 1900, 3, 1, 4, 1343, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo293 }, // Inst #1900 = LWDSP 5928 { 1899, 3, 1, 4, 438, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, OperandInfo278 }, // Inst #1899 = LWC3 5929 { 1898, 3, 1, 4, 1083, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo276 }, // Inst #1898 = LWC2_R6 5930 { 1897, 3, 1, 4, 1150, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, OperandInfo277 }, // Inst #1897 = LWC2_MMR6 5931 { 1896, 3, 1, 4, 437, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, OperandInfo276 }, // Inst #1896 = LWC2 5932 { 1895, 3, 1, 4, 1298, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, OperandInfo292 }, // Inst #1895 = LWC1_MM 5933 { 1894, 3, 1, 4, 712, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, OperandInfo292 }, // Inst #1894 = LWC1 5934 { 1893, 3, 1, 4, 1170, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo113 }, // Inst #1893 = LW64 5935 { 1892, 3, 1, 2, 1123, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo273 }, // Inst #1892 = LW16_MM 5936 { 1891, 3, 1, 4, 435, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo96 }, // Inst #1891 = LW 5937 { 1890, 2, 1, 4, 749, 0, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL, nullptr, OperandInfo114 }, // Inst #1890 = LUi_MM 5938 { 1889, 2, 1, 4, 841, 0, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL, nullptr, OperandInfo112 }, // Inst #1889 = LUi64 5939 { 1888, 2, 1, 4, 365, 0, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL, nullptr, OperandInfo114 }, // Inst #1888 = LUi 5940 { 1887, 3, 1, 4, 1297, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, nullptr, OperandInfo285 }, // Inst #1887 = LUXC1_MM 5941 { 1886, 3, 1, 4, 714, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, nullptr, OperandInfo285 }, // Inst #1886 = LUXC164 5942 { 1885, 3, 1, 4, 714, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, nullptr, OperandInfo284 }, // Inst #1885 = LUXC1 5943 { 1884, 2, 1, 4, 791, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, OperandInfo114 }, // Inst #1884 = LUI_MMR6 5944 { 1883, 4, 1, 4, 733, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo180 }, // Inst #1883 = LSA_R6 5945 { 1882, 4, 1, 4, 790, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo180 }, // Inst #1882 = LSA_MMR6 5946 { 1881, 4, 1, 4, 513, 0, 0, 0, 0x6ULL, nullptr, OperandInfo180 }, // Inst #1881 = LSA 5947 { 1880, 3, 1, 4, 1082, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo290 }, // Inst #1880 = LL_R6 5948 { 1879, 3, 1, 4, 1148, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo96 }, // Inst #1879 = LL_MMR6 5949 { 1878, 3, 1, 4, 1122, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo96 }, // Inst #1878 = LL_MM 5950 { 1877, 3, 1, 4, 1098, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo96 }, // Inst #1877 = LLE_MM 5951 { 1876, 3, 1, 4, 446, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo96 }, // Inst #1876 = LLE 5952 { 1875, 3, 1, 4, 1186, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo291 }, // Inst #1875 = LLD_R6 5953 { 1874, 3, 1, 4, 1164, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo113 }, // Inst #1874 = LLD 5954 { 1873, 3, 1, 4, 1187, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo290 }, // Inst #1873 = LL64_R6 5955 { 1872, 3, 1, 4, 1164, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo96 }, // Inst #1872 = LL64 5956 { 1871, 3, 1, 4, 436, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo96 }, // Inst #1871 = LL 5957 { 1870, 2, 1, 2, 789, 0, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, OperandInfo169 }, // Inst #1870 = LI16_MMR6 5958 { 1869, 2, 1, 2, 748, 0, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, OperandInfo169 }, // Inst #1869 = LI16_MM 5959 { 1868, 3, 1, 4, 1120, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo96 }, // Inst #1868 = LHu_MM 5960 { 1867, 3, 1, 4, 1094, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo96 }, // Inst #1867 = LHuE_MM 5961 { 1866, 3, 1, 4, 444, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo96 }, // Inst #1866 = LHuE 5962 { 1865, 3, 1, 4, 1169, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo113 }, // Inst #1865 = LHu64 5963 { 1864, 3, 1, 4, 434, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo96 }, // Inst #1864 = LHu 5964 { 1863, 3, 1, 4, 1121, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo96 }, // Inst #1863 = LH_MM 5965 { 1862, 3, 1, 4, 1550, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, OperandInfo274 }, // Inst #1862 = LHX_MM 5966 { 1861, 3, 1, 4, 1390, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, OperandInfo274 }, // Inst #1861 = LHX 5967 { 1860, 3, 1, 2, 1120, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo273 }, // Inst #1860 = LHU16_MM 5968 { 1859, 3, 1, 4, 1093, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo96 }, // Inst #1859 = LHE_MM 5969 { 1858, 3, 1, 4, 443, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo96 }, // Inst #1858 = LHE 5970 { 1857, 3, 1, 4, 1168, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo113 }, // Inst #1857 = LH64 5971 { 1856, 3, 1, 4, 433, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo96 }, // Inst #1856 = LH 5972 { 1855, 3, 1, 4, 738, 0, 0, 0, 0x2ULL, nullptr, OperandInfo96 }, // Inst #1855 = LEA_ADDiu_MM 5973 { 1854, 3, 1, 4, 840, 0, 0, 0, 0x2ULL, nullptr, OperandInfo113 }, // Inst #1854 = LEA_ADDiu64 5974 { 1853, 3, 1, 4, 724, 0, 0, 0, 0x2ULL, nullptr, OperandInfo96 }, // Inst #1853 = LEA_ADDiu 5975 { 1852, 3, 1, 4, 715, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, OperandInfo289 }, // Inst #1852 = LD_W 5976 { 1851, 3, 1, 4, 715, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, OperandInfo288 }, // Inst #1851 = LD_H 5977 { 1850, 3, 1, 4, 715, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, OperandInfo287 }, // Inst #1850 = LD_D 5978 { 1849, 3, 1, 4, 715, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, OperandInfo286 }, // Inst #1849 = LD_B 5979 { 1848, 3, 1, 4, 711, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, OperandInfo285 }, // Inst #1848 = LDXC164 5980 { 1847, 3, 1, 4, 711, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, OperandInfo284 }, // Inst #1847 = LDXC1 5981 { 1846, 4, 1, 4, 1174, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo283 }, // Inst #1846 = LDR 5982 { 1845, 2, 1, 4, 1185, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo112 }, // Inst #1845 = LDPC 5983 { 1844, 4, 1, 4, 1173, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo283 }, // Inst #1844 = LDL 5984 { 1843, 2, 1, 4, 547, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x6ULL, nullptr, OperandInfo282 }, // Inst #1843 = LDI_W 5985 { 1842, 2, 1, 4, 547, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x6ULL, nullptr, OperandInfo281 }, // Inst #1842 = LDI_H 5986 { 1841, 2, 1, 4, 547, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x6ULL, nullptr, OperandInfo280 }, // Inst #1841 = LDI_D 5987 { 1840, 2, 1, 4, 547, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x6ULL, nullptr, OperandInfo279 }, // Inst #1840 = LDI_B 5988 { 1839, 3, 1, 4, 440, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, OperandInfo278 }, // Inst #1839 = LDC3 5989 { 1838, 3, 1, 4, 1081, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo276 }, // Inst #1838 = LDC2_R6 5990 { 1837, 3, 1, 4, 1147, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, OperandInfo277 }, // Inst #1837 = LDC2_MMR6 5991 { 1836, 3, 1, 4, 439, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, OperandInfo276 }, // Inst #1836 = LDC2 5992 { 1835, 3, 1, 4, 1296, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, OperandInfo275 }, // Inst #1835 = LDC1_MM_D64 5993 { 1834, 3, 1, 4, 1296, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, OperandInfo158 }, // Inst #1834 = LDC1_MM_D32 5994 { 1833, 3, 1, 4, 1339, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, OperandInfo275 }, // Inst #1833 = LDC1_D64_MMR6 5995 { 1832, 3, 1, 4, 710, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, OperandInfo275 }, // Inst #1832 = LDC164 5996 { 1831, 3, 1, 4, 710, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, OperandInfo158 }, // Inst #1831 = LDC1 5997 { 1830, 3, 1, 4, 1163, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo113 }, // Inst #1830 = LD 5998 { 1829, 3, 1, 4, 1118, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo96 }, // Inst #1829 = LBu_MM 5999 { 1828, 3, 1, 4, 1092, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo96 }, // Inst #1828 = LBuE_MM 6000 { 1827, 3, 1, 4, 442, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo96 }, // Inst #1827 = LBuE 6001 { 1826, 3, 1, 4, 1167, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo113 }, // Inst #1826 = LBu64 6002 { 1825, 3, 1, 4, 432, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo96 }, // Inst #1825 = LBu 6003 { 1824, 3, 1, 4, 1146, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo96 }, // Inst #1824 = LB_MMR6 6004 { 1823, 3, 1, 4, 1119, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo96 }, // Inst #1823 = LB_MM 6005 { 1822, 3, 1, 4, 1145, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo96 }, // Inst #1822 = LBU_MMR6 6006 { 1821, 3, 1, 4, 1549, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, OperandInfo274 }, // Inst #1821 = LBUX_MM 6007 { 1820, 3, 1, 4, 1389, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, OperandInfo274 }, // Inst #1820 = LBUX 6008 { 1819, 3, 1, 2, 1118, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo273 }, // Inst #1819 = LBU16_MM 6009 { 1818, 3, 1, 4, 1091, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo96 }, // Inst #1818 = LBE_MM 6010 { 1817, 3, 1, 4, 441, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo96 }, // Inst #1817 = LBE 6011 { 1816, 3, 1, 4, 1166, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo113 }, // Inst #1816 = LB64 6012 { 1815, 3, 1, 4, 431, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo96 }, // Inst #1815 = LB 6013 { 1814, 1, 0, 2, 942, 0, 1, 0|(1ULL<<MCID::Call), 0x0ULL, ImplicitList3, OperandInfo272 }, // Inst #1814 = JumpLinkReg16 6014 { 1813, 1, 0, 2, 939, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, OperandInfo272 }, // Inst #1813 = JrcRx16 6015 { 1812, 0, 0, 2, 939, 0, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #1812 = JrcRa16 6016 { 1811, 0, 0, 2, 939, 0, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #1811 = JrRa16 6017 { 1810, 1, 0, 6, 941, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList3, OperandInfo2 }, // Inst #1810 = JalB16 6018 { 1809, 1, 0, 6, 941, 0, 1, 0|(1ULL<<MCID::Call), 0x0ULL, ImplicitList3, OperandInfo2 }, // Inst #1809 = Jal16 6019 { 1808, 1, 0, 4, 955, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x13ULL, ImplicitList2, OperandInfo2 }, // Inst #1808 = J_MM 6020 { 1807, 1, 0, 4, 954, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL, nullptr, OperandInfo58 }, // Inst #1807 = JR_MM 6021 { 1806, 1, 0, 4, 934, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo58 }, // Inst #1806 = JR_HB_R6 6022 { 1805, 1, 0, 4, 1022, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo95 }, // Inst #1805 = JR_HB64_R6 6023 { 1804, 1, 0, 4, 1014, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x13ULL, nullptr, OperandInfo95 }, // Inst #1804 = JR_HB64 6024 { 1803, 1, 0, 4, 386, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x13ULL, nullptr, OperandInfo58 }, // Inst #1803 = JR_HB 6025 { 1802, 1, 0, 2, 993, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo2 }, // Inst #1802 = JRCADDIUSP_MMR6 6026 { 1801, 1, 0, 2, 995, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo58 }, // Inst #1801 = JRC16_MMR6 6027 { 1800, 1, 0, 2, 994, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo58 }, // Inst #1800 = JRC16_MM 6028 { 1799, 1, 0, 2, 993, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo2 }, // Inst #1799 = JRADDIUSP 6029 { 1798, 1, 0, 4, 1011, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL, nullptr, OperandInfo95 }, // Inst #1798 = JR64 6030 { 1797, 1, 0, 2, 954, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo58 }, // Inst #1797 = JR16_MM 6031 { 1796, 1, 0, 4, 923, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL, nullptr, OperandInfo58 }, // Inst #1796 = JR 6032 { 1795, 2, 0, 4, 992, 0, 1, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList2, OperandInfo114 }, // Inst #1795 = JIC_MMR6 6033 { 1794, 2, 0, 4, 1019, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList2, OperandInfo112 }, // Inst #1794 = JIC64 6034 { 1793, 2, 0, 4, 933, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList2, OperandInfo114 }, // Inst #1793 = JIC 6035 { 1792, 2, 0, 4, 1004, 0, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList3, OperandInfo114 }, // Inst #1792 = JIALC_MMR6 6036 { 1791, 2, 0, 4, 1021, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList3, OperandInfo112 }, // Inst #1791 = JIALC64 6037 { 1790, 2, 0, 4, 928, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList3, OperandInfo114 }, // Inst #1790 = JIALC 6038 { 1789, 1, 0, 4, 962, 0, 1, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x13ULL, ImplicitList3, OperandInfo2 }, // Inst #1789 = JAL_MM 6039 { 1788, 1, 0, 4, 962, 0, 1, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x13ULL, ImplicitList3, OperandInfo2 }, // Inst #1788 = JALX_MM 6040 { 1787, 1, 0, 4, 409, 0, 1, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x13ULL, ImplicitList3, OperandInfo2 }, // Inst #1787 = JALX 6041 { 1786, 1, 0, 4, 961, 0, 1, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x3ULL, ImplicitList3, OperandInfo2 }, // Inst #1786 = JALS_MM 6042 { 1785, 2, 1, 4, 959, 0, 1, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL, ImplicitList3, OperandInfo45 }, // Inst #1785 = JALR_MM 6043 { 1784, 2, 1, 4, 1013, 0, 0, 0|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x13ULL, nullptr, OperandInfo122 }, // Inst #1784 = JALR_HB64 6044 { 1783, 2, 1, 4, 408, 0, 0, 0|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x13ULL, nullptr, OperandInfo45 }, // Inst #1783 = JALR_HB 6045 { 1782, 2, 1, 4, 960, 0, 1, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList3, OperandInfo45 }, // Inst #1782 = JALRS_MM 6046 { 1781, 1, 0, 2, 960, 0, 1, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList3, OperandInfo58 }, // Inst #1781 = JALRS16_MM 6047 { 1780, 2, 1, 4, 1003, 0, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList3, OperandInfo45 }, // Inst #1780 = JALRC_MMR6 6048 { 1779, 2, 1, 4, 1002, 0, 0, 0|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::UnmodeledSideEffects), 0x3ULL, nullptr, OperandInfo45 }, // Inst #1779 = JALRC_HB_MMR6 6049 { 1778, 1, 0, 2, 1001, 0, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, ImplicitList3, OperandInfo58 }, // Inst #1778 = JALRC16_MMR6 6050 { 1777, 2, 1, 4, 1012, 0, 1, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL, ImplicitList3, OperandInfo122 }, // Inst #1777 = JALR64 6051 { 1776, 1, 0, 2, 959, 0, 1, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, ImplicitList3, OperandInfo58 }, // Inst #1776 = JALR16_MM 6052 { 1775, 2, 1, 4, 407, 0, 1, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL, ImplicitList3, OperandInfo45 }, // Inst #1775 = JALR 6053 { 1774, 1, 0, 4, 406, 0, 1, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x13ULL, ImplicitList3, OperandInfo2 }, // Inst #1774 = JAL 6054 { 1773, 1, 0, 4, 922, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x13ULL, ImplicitList2, OperandInfo2 }, // Inst #1773 = J 6055 { 1772, 5, 1, 4, 788, 0, 0, 0, 0x1ULL, nullptr, OperandInfo262 }, // Inst #1772 = INS_MMR6 6056 { 1771, 5, 1, 4, 747, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo262 }, // Inst #1771 = INS_MM 6057 { 1770, 3, 1, 4, 1548, 2, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL, ImplicitList19, OperandInfo267 }, // Inst #1770 = INSV_MM 6058 { 1769, 5, 1, 4, 607, 0, 0, 0, 0x6ULL, nullptr, OperandInfo271 }, // Inst #1769 = INSVE_W 6059 { 1768, 5, 1, 4, 607, 0, 0, 0, 0x6ULL, nullptr, OperandInfo270 }, // Inst #1768 = INSVE_H 6060 { 1767, 5, 1, 4, 607, 0, 0, 0, 0x6ULL, nullptr, OperandInfo269 }, // Inst #1767 = INSVE_D 6061 { 1766, 5, 1, 4, 607, 0, 0, 0, 0x6ULL, nullptr, OperandInfo268 }, // Inst #1766 = INSVE_B 6062 { 1765, 3, 1, 4, 1353, 2, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL, ImplicitList19, OperandInfo267 }, // Inst #1765 = INSV 6063 { 1764, 4, 1, 4, 518, 0, 0, 0, 0x6ULL, nullptr, OperandInfo266 }, // Inst #1764 = INSERT_W 6064 { 1763, 4, 1, 4, 518, 0, 0, 0, 0x6ULL, nullptr, OperandInfo265 }, // Inst #1763 = INSERT_H 6065 { 1762, 4, 1, 4, 518, 0, 0, 0, 0x6ULL, nullptr, OperandInfo264 }, // Inst #1762 = INSERT_D 6066 { 1761, 4, 1, 4, 518, 0, 0, 0, 0x6ULL, nullptr, OperandInfo263 }, // Inst #1761 = INSERT_B 6067 { 1760, 5, 1, 4, 495, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo262 }, // Inst #1760 = INS 6068 { 1759, 3, 1, 4, 605, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1759 = ILVR_W 6069 { 1758, 3, 1, 4, 605, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #1758 = ILVR_H 6070 { 1757, 3, 1, 4, 605, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1757 = ILVR_D 6071 { 1756, 3, 1, 4, 605, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #1756 = ILVR_B 6072 { 1755, 3, 1, 4, 606, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1755 = ILVOD_W 6073 { 1754, 3, 1, 4, 606, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #1754 = ILVOD_H 6074 { 1753, 3, 1, 4, 606, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1753 = ILVOD_D 6075 { 1752, 3, 1, 4, 606, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #1752 = ILVOD_B 6076 { 1751, 3, 1, 4, 605, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1751 = ILVL_W 6077 { 1750, 3, 1, 4, 605, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #1750 = ILVL_H 6078 { 1749, 3, 1, 4, 605, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1749 = ILVL_D 6079 { 1748, 3, 1, 4, 605, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #1748 = ILVL_B 6080 { 1747, 3, 1, 4, 606, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1747 = ILVEV_W 6081 { 1746, 3, 1, 4, 606, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #1746 = ILVEV_H 6082 { 1745, 3, 1, 4, 606, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1745 = ILVEV_D 6083 { 1744, 3, 1, 4, 606, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #1744 = ILVEV_B 6084 { 1743, 1, 0, 4, 1069, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo2 }, // Inst #1743 = HYPCALL_MM 6085 { 1742, 1, 0, 4, 420, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo2 }, // Inst #1742 = HYPCALL 6086 { 1741, 3, 1, 4, 616, 0, 0, 0, 0x6ULL, nullptr, OperandInfo239 }, // Inst #1741 = HSUB_U_W 6087 { 1740, 3, 1, 4, 616, 0, 0, 0, 0x6ULL, nullptr, OperandInfo238 }, // Inst #1740 = HSUB_U_H 6088 { 1739, 3, 1, 4, 616, 0, 0, 0, 0x6ULL, nullptr, OperandInfo237 }, // Inst #1739 = HSUB_U_D 6089 { 1738, 3, 1, 4, 616, 0, 0, 0, 0x6ULL, nullptr, OperandInfo239 }, // Inst #1738 = HSUB_S_W 6090 { 1737, 3, 1, 4, 616, 0, 0, 0, 0x6ULL, nullptr, OperandInfo238 }, // Inst #1737 = HSUB_S_H 6091 { 1736, 3, 1, 4, 616, 0, 0, 0, 0x6ULL, nullptr, OperandInfo237 }, // Inst #1736 = HSUB_S_D 6092 { 1735, 3, 1, 4, 615, 0, 0, 0, 0x6ULL, nullptr, OperandInfo239 }, // Inst #1735 = HADD_U_W 6093 { 1734, 3, 1, 4, 615, 0, 0, 0, 0x6ULL, nullptr, OperandInfo238 }, // Inst #1734 = HADD_U_H 6094 { 1733, 3, 1, 4, 615, 0, 0, 0, 0x6ULL, nullptr, OperandInfo237 }, // Inst #1733 = HADD_U_D 6095 { 1732, 3, 1, 4, 615, 0, 0, 0, 0x6ULL, nullptr, OperandInfo239 }, // Inst #1732 = HADD_S_W 6096 { 1731, 3, 1, 4, 615, 0, 0, 0, 0x6ULL, nullptr, OperandInfo238 }, // Inst #1731 = HADD_S_H 6097 { 1730, 3, 1, 4, 615, 0, 0, 0, 0x6ULL, nullptr, OperandInfo237 }, // Inst #1730 = HADD_S_D 6098 { 1729, 2, 0, 4, 1144, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo114 }, // Inst #1729 = GINVT_MMR6 6099 { 1728, 2, 0, 4, 1090, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo114 }, // Inst #1728 = GINVT 6100 { 1727, 1, 0, 4, 1143, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo58 }, // Inst #1727 = GINVI_MMR6 6101 { 1726, 1, 0, 4, 1089, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo58 }, // Inst #1726 = GINVI 6102 { 1725, 2, 1, 4, 595, 0, 0, 0, 0x6ULL, nullptr, OperandInfo77 }, // Inst #1725 = FTRUNC_U_W 6103 { 1724, 2, 1, 4, 595, 0, 0, 0, 0x6ULL, nullptr, OperandInfo76 }, // Inst #1724 = FTRUNC_U_D 6104 { 1723, 2, 1, 4, 595, 0, 0, 0, 0x6ULL, nullptr, OperandInfo77 }, // Inst #1723 = FTRUNC_S_W 6105 { 1722, 2, 1, 4, 595, 0, 0, 0, 0x6ULL, nullptr, OperandInfo76 }, // Inst #1722 = FTRUNC_S_D 6106 { 1721, 3, 1, 4, 594, 0, 0, 0, 0x6ULL, nullptr, OperandInfo255 }, // Inst #1721 = FTQ_W 6107 { 1720, 3, 1, 4, 594, 0, 0, 0, 0x6ULL, nullptr, OperandInfo254 }, // Inst #1720 = FTQ_H 6108 { 1719, 2, 1, 4, 592, 0, 0, 0, 0x6ULL, nullptr, OperandInfo77 }, // Inst #1719 = FTINT_U_W 6109 { 1718, 2, 1, 4, 592, 0, 0, 0, 0x6ULL, nullptr, OperandInfo76 }, // Inst #1718 = FTINT_U_D 6110 { 1717, 2, 1, 4, 592, 0, 0, 0, 0x6ULL, nullptr, OperandInfo77 }, // Inst #1717 = FTINT_S_W 6111 { 1716, 2, 1, 4, 592, 0, 0, 0, 0x6ULL, nullptr, OperandInfo76 }, // Inst #1716 = FTINT_S_D 6112 { 1715, 3, 1, 4, 576, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1715 = FSUN_W 6113 { 1714, 3, 1, 4, 576, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1714 = FSUN_D 6114 { 1713, 3, 1, 4, 575, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1713 = FSUNE_W 6115 { 1712, 3, 1, 4, 575, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1712 = FSUNE_D 6116 { 1711, 3, 1, 4, 574, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1711 = FSULT_W 6117 { 1710, 3, 1, 4, 574, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1710 = FSULT_D 6118 { 1709, 3, 1, 4, 573, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1709 = FSULE_W 6119 { 1708, 3, 1, 4, 573, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1708 = FSULE_D 6120 { 1707, 3, 1, 4, 572, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1707 = FSUEQ_W 6121 { 1706, 3, 1, 4, 572, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1706 = FSUEQ_D 6122 { 1705, 3, 1, 4, 664, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1705 = FSUB_W 6123 { 1704, 3, 1, 4, 1335, 0, 0, 0, 0x6ULL, nullptr, OperandInfo250 }, // Inst #1704 = FSUB_S_MMR6 6124 { 1703, 3, 1, 4, 1281, 0, 0, 0, 0x4ULL, nullptr, OperandInfo250 }, // Inst #1703 = FSUB_S_MM 6125 { 1702, 3, 1, 4, 636, 0, 0, 0, 0x4ULL, nullptr, OperandInfo250 }, // Inst #1702 = FSUB_S 6126 { 1701, 3, 1, 4, 635, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo173 }, // Inst #1701 = FSUB_PS64 6127 { 1700, 3, 1, 4, 1280, 0, 0, 0, 0x4ULL, nullptr, OperandInfo173 }, // Inst #1700 = FSUB_D64_MM 6128 { 1699, 3, 1, 4, 634, 0, 0, 0, 0x4ULL, nullptr, OperandInfo173 }, // Inst #1699 = FSUB_D64 6129 { 1698, 3, 1, 4, 1280, 0, 0, 0, 0x4ULL, nullptr, OperandInfo249 }, // Inst #1698 = FSUB_D32_MM 6130 { 1697, 3, 1, 4, 634, 0, 0, 0, 0x4ULL, nullptr, OperandInfo249 }, // Inst #1697 = FSUB_D32 6131 { 1696, 3, 1, 4, 664, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1696 = FSUB_D 6132 { 1695, 2, 1, 4, 660, 0, 0, 0, 0x6ULL, nullptr, OperandInfo77 }, // Inst #1695 = FSQRT_W 6133 { 1694, 2, 1, 4, 1286, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #1694 = FSQRT_S_MM 6134 { 1693, 2, 1, 4, 648, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #1693 = FSQRT_S 6135 { 1692, 2, 1, 4, 1287, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #1692 = FSQRT_D64_MM 6136 { 1691, 2, 1, 4, 649, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #1691 = FSQRT_D64 6137 { 1690, 2, 1, 4, 1287, 0, 0, 0, 0x4ULL, nullptr, OperandInfo248 }, // Inst #1690 = FSQRT_D32_MM 6138 { 1689, 2, 1, 4, 649, 0, 0, 0, 0x4ULL, nullptr, OperandInfo248 }, // Inst #1689 = FSQRT_D32 6139 { 1688, 2, 1, 4, 661, 0, 0, 0, 0x6ULL, nullptr, OperandInfo76 }, // Inst #1688 = FSQRT_D 6140 { 1687, 3, 1, 4, 571, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1687 = FSOR_W 6141 { 1686, 3, 1, 4, 571, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1686 = FSOR_D 6142 { 1685, 3, 1, 4, 571, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1685 = FSNE_W 6143 { 1684, 3, 1, 4, 571, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1684 = FSNE_D 6144 { 1683, 3, 1, 4, 571, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1683 = FSLT_W 6145 { 1682, 3, 1, 4, 571, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1682 = FSLT_D 6146 { 1681, 3, 1, 4, 571, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1681 = FSLE_W 6147 { 1680, 3, 1, 4, 571, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1680 = FSLE_D 6148 { 1679, 3, 1, 4, 571, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1679 = FSEQ_W 6149 { 1678, 3, 1, 4, 571, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1678 = FSEQ_D 6150 { 1677, 3, 1, 4, 571, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1677 = FSAF_W 6151 { 1676, 3, 1, 4, 571, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1676 = FSAF_D 6152 { 1675, 2, 1, 4, 651, 0, 0, 0, 0x6ULL, nullptr, OperandInfo77 }, // Inst #1675 = FRSQRT_W 6153 { 1674, 2, 1, 4, 651, 0, 0, 0, 0x6ULL, nullptr, OperandInfo76 }, // Inst #1674 = FRSQRT_D 6154 { 1673, 2, 1, 4, 593, 0, 0, 0, 0x6ULL, nullptr, OperandInfo77 }, // Inst #1673 = FRINT_W 6155 { 1672, 2, 1, 4, 593, 0, 0, 0, 0x6ULL, nullptr, OperandInfo76 }, // Inst #1672 = FRINT_D 6156 { 1671, 2, 1, 4, 650, 0, 0, 0, 0x6ULL, nullptr, OperandInfo77 }, // Inst #1671 = FRCP_W 6157 { 1670, 2, 1, 4, 650, 0, 0, 0, 0x6ULL, nullptr, OperandInfo76 }, // Inst #1670 = FRCP_D 6158 { 1669, 3, 2, 4, 1066, 0, 0, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo72 }, // Inst #1669 = FORK 6159 { 1668, 2, 1, 4, 1300, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #1668 = FNEG_S_MMR6 6160 { 1667, 2, 1, 4, 1273, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #1667 = FNEG_S_MM 6161 { 1666, 2, 1, 4, 537, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #1666 = FNEG_S 6162 { 1665, 2, 1, 4, 1273, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #1665 = FNEG_D64_MM 6163 { 1664, 2, 1, 4, 537, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #1664 = FNEG_D64 6164 { 1663, 2, 1, 4, 1273, 0, 0, 0, 0x4ULL, nullptr, OperandInfo248 }, // Inst #1663 = FNEG_D32_MM 6165 { 1662, 2, 1, 4, 537, 0, 0, 0, 0x4ULL, nullptr, OperandInfo248 }, // Inst #1662 = FNEG_D32 6166 { 1661, 3, 1, 4, 662, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1661 = FMUL_W 6167 { 1660, 3, 1, 4, 1334, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo250 }, // Inst #1660 = FMUL_S_MMR6 6168 { 1659, 3, 1, 4, 1279, 0, 0, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, OperandInfo250 }, // Inst #1659 = FMUL_S_MM 6169 { 1658, 3, 1, 4, 633, 0, 0, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, OperandInfo250 }, // Inst #1658 = FMUL_S 6170 { 1657, 3, 1, 4, 632, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo173 }, // Inst #1657 = FMUL_PS64 6171 { 1656, 3, 1, 4, 1278, 0, 0, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, OperandInfo173 }, // Inst #1656 = FMUL_D64_MM 6172 { 1655, 3, 1, 4, 631, 0, 0, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, OperandInfo173 }, // Inst #1655 = FMUL_D64 6173 { 1654, 3, 1, 4, 1278, 0, 0, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, OperandInfo249 }, // Inst #1654 = FMUL_D32_MM 6174 { 1653, 3, 1, 4, 631, 0, 0, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, OperandInfo249 }, // Inst #1653 = FMUL_D32 6175 { 1652, 3, 1, 4, 662, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1652 = FMUL_D 6176 { 1651, 4, 1, 4, 657, 0, 0, 0, 0x6ULL, nullptr, OperandInfo60 }, // Inst #1651 = FMSUB_W 6177 { 1650, 4, 1, 4, 657, 0, 0, 0, 0x6ULL, nullptr, OperandInfo59 }, // Inst #1650 = FMSUB_D 6178 { 1649, 2, 1, 4, 1333, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #1649 = FMOV_S_MMR6 6179 { 1648, 2, 1, 4, 1277, 0, 0, 0|(1ULL<<MCID::MoveReg), 0x4ULL, nullptr, OperandInfo207 }, // Inst #1648 = FMOV_S_MM 6180 { 1647, 2, 1, 4, 536, 0, 0, 0|(1ULL<<MCID::MoveReg), 0x4ULL, nullptr, OperandInfo207 }, // Inst #1647 = FMOV_S 6181 { 1646, 2, 1, 4, 1336, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #1646 = FMOV_D_MMR6 6182 { 1645, 2, 1, 4, 1276, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #1645 = FMOV_D64_MM 6183 { 1644, 2, 1, 4, 535, 0, 0, 0|(1ULL<<MCID::MoveReg), 0x4ULL, nullptr, OperandInfo203 }, // Inst #1644 = FMOV_D64 6184 { 1643, 2, 1, 4, 1276, 0, 0, 0, 0x4ULL, nullptr, OperandInfo248 }, // Inst #1643 = FMOV_D32_MM 6185 { 1642, 2, 1, 4, 535, 0, 0, 0|(1ULL<<MCID::MoveReg), 0x4ULL, nullptr, OperandInfo248 }, // Inst #1642 = FMOV_D32 6186 { 1641, 3, 1, 4, 603, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1641 = FMIN_W 6187 { 1640, 3, 1, 4, 603, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1640 = FMIN_D 6188 { 1639, 3, 1, 4, 602, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1639 = FMIN_A_W 6189 { 1638, 3, 1, 4, 602, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1638 = FMIN_A_D 6190 { 1637, 3, 1, 4, 601, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1637 = FMAX_W 6191 { 1636, 3, 1, 4, 601, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1636 = FMAX_D 6192 { 1635, 3, 1, 4, 600, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1635 = FMAX_A_W 6193 { 1634, 3, 1, 4, 600, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1634 = FMAX_A_D 6194 { 1633, 4, 1, 4, 656, 0, 0, 0, 0x6ULL, nullptr, OperandInfo60 }, // Inst #1633 = FMADD_W 6195 { 1632, 4, 1, 4, 656, 0, 0, 0, 0x6ULL, nullptr, OperandInfo59 }, // Inst #1632 = FMADD_D 6196 { 1631, 2, 1, 4, 1310, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #1631 = FLOOR_W_S_MMR6 6197 { 1630, 2, 1, 4, 1248, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #1630 = FLOOR_W_S_MM 6198 { 1629, 2, 1, 4, 718, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #1629 = FLOOR_W_S 6199 { 1628, 2, 1, 4, 1248, 0, 0, 0, 0x4ULL, nullptr, OperandInfo205 }, // Inst #1628 = FLOOR_W_MM 6200 { 1627, 2, 1, 4, 1310, 0, 0, 0, 0x4ULL, nullptr, OperandInfo205 }, // Inst #1627 = FLOOR_W_D_MMR6 6201 { 1626, 2, 1, 4, 718, 0, 0, 0, 0x4ULL, nullptr, OperandInfo206 }, // Inst #1626 = FLOOR_W_D64 6202 { 1625, 2, 1, 4, 718, 0, 0, 0, 0x4ULL, nullptr, OperandInfo205 }, // Inst #1625 = FLOOR_W_D32 6203 { 1624, 2, 1, 4, 1310, 0, 0, 0, 0x4ULL, nullptr, OperandInfo204 }, // Inst #1624 = FLOOR_L_S_MMR6 6204 { 1623, 2, 1, 4, 718, 0, 0, 0, 0x4ULL, nullptr, OperandInfo204 }, // Inst #1623 = FLOOR_L_S 6205 { 1622, 2, 1, 4, 1310, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #1622 = FLOOR_L_D_MMR6 6206 { 1621, 2, 1, 4, 718, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #1621 = FLOOR_L_D64 6207 { 1620, 2, 1, 4, 604, 0, 0, 0, 0x6ULL, nullptr, OperandInfo77 }, // Inst #1620 = FLOG2_W 6208 { 1619, 2, 1, 4, 604, 0, 0, 0, 0x6ULL, nullptr, OperandInfo76 }, // Inst #1619 = FLOG2_D 6209 { 1618, 2, 1, 4, 544, 0, 0, 0, 0x6ULL, nullptr, OperandInfo261 }, // Inst #1618 = FILL_W 6210 { 1617, 2, 1, 4, 544, 0, 0, 0, 0x6ULL, nullptr, OperandInfo260 }, // Inst #1617 = FILL_H 6211 { 1616, 2, 1, 4, 544, 0, 0, 0, 0x6ULL, nullptr, OperandInfo259 }, // Inst #1616 = FILL_D 6212 { 1615, 2, 1, 4, 544, 0, 0, 0, 0x6ULL, nullptr, OperandInfo258 }, // Inst #1615 = FILL_B 6213 { 1614, 2, 1, 4, 591, 0, 0, 0, 0x6ULL, nullptr, OperandInfo257 }, // Inst #1614 = FFQR_W 6214 { 1613, 2, 1, 4, 591, 0, 0, 0, 0x6ULL, nullptr, OperandInfo256 }, // Inst #1613 = FFQR_D 6215 { 1612, 2, 1, 4, 590, 0, 0, 0, 0x6ULL, nullptr, OperandInfo257 }, // Inst #1612 = FFQL_W 6216 { 1611, 2, 1, 4, 590, 0, 0, 0, 0x6ULL, nullptr, OperandInfo256 }, // Inst #1611 = FFQL_D 6217 { 1610, 2, 1, 4, 589, 0, 0, 0, 0x6ULL, nullptr, OperandInfo77 }, // Inst #1610 = FFINT_U_W 6218 { 1609, 2, 1, 4, 589, 0, 0, 0, 0x6ULL, nullptr, OperandInfo76 }, // Inst #1609 = FFINT_U_D 6219 { 1608, 2, 1, 4, 589, 0, 0, 0, 0x6ULL, nullptr, OperandInfo77 }, // Inst #1608 = FFINT_S_W 6220 { 1607, 2, 1, 4, 589, 0, 0, 0, 0x6ULL, nullptr, OperandInfo76 }, // Inst #1607 = FFINT_S_D 6221 { 1606, 2, 1, 4, 598, 0, 0, 0, 0x6ULL, nullptr, OperandInfo257 }, // Inst #1606 = FEXUPR_W 6222 { 1605, 2, 1, 4, 598, 0, 0, 0, 0x6ULL, nullptr, OperandInfo256 }, // Inst #1605 = FEXUPR_D 6223 { 1604, 2, 1, 4, 597, 0, 0, 0, 0x6ULL, nullptr, OperandInfo257 }, // Inst #1604 = FEXUPL_W 6224 { 1603, 2, 1, 4, 597, 0, 0, 0, 0x6ULL, nullptr, OperandInfo256 }, // Inst #1603 = FEXUPL_D 6225 { 1602, 3, 1, 4, 553, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1602 = FEXP2_W 6226 { 1601, 3, 1, 4, 553, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1601 = FEXP2_D 6227 { 1600, 3, 1, 4, 596, 0, 0, 0, 0x6ULL, nullptr, OperandInfo255 }, // Inst #1600 = FEXDO_W 6228 { 1599, 3, 1, 4, 596, 0, 0, 0, 0x6ULL, nullptr, OperandInfo254 }, // Inst #1599 = FEXDO_H 6229 { 1598, 3, 1, 4, 658, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1598 = FDIV_W 6230 { 1597, 3, 1, 4, 1337, 0, 0, 0, 0x6ULL, nullptr, OperandInfo250 }, // Inst #1597 = FDIV_S_MMR6 6231 { 1596, 3, 1, 4, 1284, 0, 0, 0, 0x4ULL, nullptr, OperandInfo250 }, // Inst #1596 = FDIV_S_MM 6232 { 1595, 3, 1, 4, 646, 0, 0, 0, 0x4ULL, nullptr, OperandInfo250 }, // Inst #1595 = FDIV_S 6233 { 1594, 3, 1, 4, 1285, 0, 0, 0, 0x4ULL, nullptr, OperandInfo173 }, // Inst #1594 = FDIV_D64_MM 6234 { 1593, 3, 1, 4, 647, 0, 0, 0, 0x4ULL, nullptr, OperandInfo173 }, // Inst #1593 = FDIV_D64 6235 { 1592, 3, 1, 4, 1285, 0, 0, 0, 0x4ULL, nullptr, OperandInfo249 }, // Inst #1592 = FDIV_D32_MM 6236 { 1591, 3, 1, 4, 647, 0, 0, 0, 0x4ULL, nullptr, OperandInfo249 }, // Inst #1591 = FDIV_D32 6237 { 1590, 3, 1, 4, 659, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1590 = FDIV_D 6238 { 1589, 3, 1, 4, 587, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo48 }, // Inst #1589 = FCUN_W 6239 { 1588, 3, 1, 4, 587, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo46 }, // Inst #1588 = FCUN_D 6240 { 1587, 3, 1, 4, 586, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo48 }, // Inst #1587 = FCUNE_W 6241 { 1586, 3, 1, 4, 586, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo46 }, // Inst #1586 = FCUNE_D 6242 { 1585, 3, 1, 4, 585, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo48 }, // Inst #1585 = FCULT_W 6243 { 1584, 3, 1, 4, 585, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo46 }, // Inst #1584 = FCULT_D 6244 { 1583, 3, 1, 4, 584, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo48 }, // Inst #1583 = FCULE_W 6245 { 1582, 3, 1, 4, 584, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo46 }, // Inst #1582 = FCULE_D 6246 { 1581, 3, 1, 4, 583, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo48 }, // Inst #1581 = FCUEQ_W 6247 { 1580, 3, 1, 4, 583, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo46 }, // Inst #1580 = FCUEQ_D 6248 { 1579, 3, 1, 4, 582, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo48 }, // Inst #1579 = FCOR_W 6249 { 1578, 3, 1, 4, 582, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo46 }, // Inst #1578 = FCOR_D 6250 { 1577, 3, 1, 4, 581, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo48 }, // Inst #1577 = FCNE_W 6251 { 1576, 3, 1, 4, 581, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo46 }, // Inst #1576 = FCNE_D 6252 { 1575, 3, 0, 4, 1265, 0, 1, 0, 0x44ULL, ImplicitList18, OperandInfo253 }, // Inst #1575 = FCMP_S32_MM 6253 { 1574, 3, 0, 4, 643, 0, 1, 0, 0x44ULL, ImplicitList18, OperandInfo253 }, // Inst #1574 = FCMP_S32 6254 { 1573, 3, 0, 4, 642, 0, 1, 0, 0x44ULL, ImplicitList18, OperandInfo252 }, // Inst #1573 = FCMP_D64 6255 { 1572, 3, 0, 4, 1266, 0, 1, 0, 0x44ULL, ImplicitList18, OperandInfo251 }, // Inst #1572 = FCMP_D32_MM 6256 { 1571, 3, 0, 4, 642, 0, 1, 0, 0x44ULL, ImplicitList18, OperandInfo251 }, // Inst #1571 = FCMP_D32 6257 { 1570, 3, 1, 4, 580, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1570 = FCLT_W 6258 { 1569, 3, 1, 4, 580, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1569 = FCLT_D 6259 { 1568, 3, 1, 4, 579, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1568 = FCLE_W 6260 { 1567, 3, 1, 4, 579, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1567 = FCLE_D 6261 { 1566, 2, 1, 4, 599, 0, 0, 0, 0x6ULL, nullptr, OperandInfo77 }, // Inst #1566 = FCLASS_W 6262 { 1565, 2, 1, 4, 599, 0, 0, 0, 0x6ULL, nullptr, OperandInfo76 }, // Inst #1565 = FCLASS_D 6263 { 1564, 3, 1, 4, 578, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo48 }, // Inst #1564 = FCEQ_W 6264 { 1563, 3, 1, 4, 578, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo46 }, // Inst #1563 = FCEQ_D 6265 { 1562, 3, 1, 4, 577, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo48 }, // Inst #1562 = FCAF_W 6266 { 1561, 3, 1, 4, 577, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo46 }, // Inst #1561 = FCAF_D 6267 { 1560, 3, 1, 4, 663, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo48 }, // Inst #1560 = FADD_W 6268 { 1559, 3, 1, 4, 1315, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo250 }, // Inst #1559 = FADD_S_MMR6 6269 { 1558, 3, 1, 4, 1275, 0, 0, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, OperandInfo250 }, // Inst #1558 = FADD_S_MM 6270 { 1557, 3, 1, 4, 630, 0, 0, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, OperandInfo250 }, // Inst #1557 = FADD_S 6271 { 1556, 3, 1, 4, 629, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo173 }, // Inst #1556 = FADD_PS64 6272 { 1555, 3, 1, 4, 1274, 0, 0, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, OperandInfo173 }, // Inst #1555 = FADD_D64_MM 6273 { 1554, 3, 1, 4, 628, 0, 0, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, OperandInfo173 }, // Inst #1554 = FADD_D64 6274 { 1553, 3, 1, 4, 1274, 0, 0, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, OperandInfo249 }, // Inst #1553 = FADD_D32_MM 6275 { 1552, 3, 1, 4, 628, 0, 0, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, OperandInfo249 }, // Inst #1552 = FADD_D32 6276 { 1551, 3, 1, 4, 663, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo46 }, // Inst #1551 = FADD_D 6277 { 1550, 2, 1, 4, 1272, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #1550 = FABS_S_MM 6278 { 1549, 2, 1, 4, 530, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #1549 = FABS_S 6279 { 1548, 2, 1, 4, 1271, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #1548 = FABS_D64_MM 6280 { 1547, 2, 1, 4, 530, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #1547 = FABS_D64 6281 { 1546, 2, 1, 4, 1271, 0, 0, 0, 0x4ULL, nullptr, OperandInfo248 }, // Inst #1546 = FABS_D32_MM 6282 { 1545, 2, 1, 4, 530, 0, 0, 0, 0x4ULL, nullptr, OperandInfo248 }, // Inst #1545 = FABS_D32 6283 { 1544, 4, 1, 4, 787, 0, 0, 0, 0x1ULL, nullptr, OperandInfo213 }, // Inst #1544 = EXT_MMR6 6284 { 1543, 4, 1, 4, 746, 0, 0, 0, 0x1ULL, nullptr, OperandInfo213 }, // Inst #1543 = EXT_MM 6285 { 1542, 4, 1, 4, 1204, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo211 }, // Inst #1542 = EXTS32 6286 { 1541, 4, 1, 4, 1204, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo211 }, // Inst #1541 = EXTS 6287 { 1540, 3, 1, 4, 1547, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList17, OperandInfo246 }, // Inst #1540 = EXTR_W_MM 6288 { 1539, 3, 1, 4, 1352, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList17, OperandInfo246 }, // Inst #1539 = EXTR_W 6289 { 1538, 3, 1, 4, 1546, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList17, OperandInfo246 }, // Inst #1538 = EXTR_S_H_MM 6290 { 1537, 3, 1, 4, 1351, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList17, OperandInfo246 }, // Inst #1537 = EXTR_S_H 6291 { 1536, 3, 1, 4, 1545, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList17, OperandInfo246 }, // Inst #1536 = EXTR_R_W_MM 6292 { 1535, 3, 1, 4, 1350, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList17, OperandInfo246 }, // Inst #1535 = EXTR_R_W 6293 { 1534, 3, 1, 4, 1544, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList17, OperandInfo246 }, // Inst #1534 = EXTR_RS_W_MM 6294 { 1533, 3, 1, 4, 1349, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList17, OperandInfo246 }, // Inst #1533 = EXTR_RS_W 6295 { 1532, 3, 1, 4, 1543, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList17, OperandInfo247 }, // Inst #1532 = EXTRV_W_MM 6296 { 1531, 3, 1, 4, 1348, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList17, OperandInfo247 }, // Inst #1531 = EXTRV_W 6297 { 1530, 3, 1, 4, 1542, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList17, OperandInfo247 }, // Inst #1530 = EXTRV_S_H_MM 6298 { 1529, 3, 1, 4, 1347, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList17, OperandInfo247 }, // Inst #1529 = EXTRV_S_H 6299 { 1528, 3, 1, 4, 1541, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList17, OperandInfo247 }, // Inst #1528 = EXTRV_R_W_MM 6300 { 1527, 3, 1, 4, 1346, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList17, OperandInfo247 }, // Inst #1527 = EXTRV_R_W 6301 { 1526, 3, 1, 4, 1540, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList17, OperandInfo247 }, // Inst #1526 = EXTRV_RS_W_MM 6302 { 1525, 3, 1, 4, 1345, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList17, OperandInfo247 }, // Inst #1525 = EXTRV_RS_W 6303 { 1524, 3, 1, 4, 1539, 1, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList15, OperandInfo246 }, // Inst #1524 = EXTP_MM 6304 { 1523, 3, 1, 4, 1538, 1, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList15, OperandInfo247 }, // Inst #1523 = EXTPV_MM 6305 { 1522, 3, 1, 4, 1387, 1, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList15, OperandInfo247 }, // Inst #1522 = EXTPV 6306 { 1521, 3, 1, 4, 1537, 1, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList16, OperandInfo246 }, // Inst #1521 = EXTPDP_MM 6307 { 1520, 3, 1, 4, 1536, 1, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList16, OperandInfo247 }, // Inst #1520 = EXTPDPV_MM 6308 { 1519, 3, 1, 4, 1385, 1, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList16, OperandInfo247 }, // Inst #1519 = EXTPDPV 6309 { 1518, 3, 1, 4, 1386, 1, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList16, OperandInfo246 }, // Inst #1518 = EXTPDP 6310 { 1517, 3, 1, 4, 1388, 1, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList15, OperandInfo246 }, // Inst #1517 = EXTP 6311 { 1516, 4, 1, 4, 494, 0, 0, 0, 0x1ULL, nullptr, OperandInfo213 }, // Inst #1516 = EXT 6312 { 1515, 1, 1, 4, 1046, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo58 }, // Inst #1515 = EVP_MMR6 6313 { 1514, 1, 1, 4, 1062, 0, 0, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo58 }, // Inst #1514 = EVPE 6314 { 1513, 1, 1, 4, 1025, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo58 }, // Inst #1513 = EVP 6315 { 1512, 0, 0, 4, 991, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr }, // Inst #1512 = ERET_MMR6 6316 { 1511, 0, 0, 4, 953, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr }, // Inst #1511 = ERET_MM 6317 { 1510, 0, 0, 4, 989, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr }, // Inst #1510 = ERETNC_MMR6 6318 { 1509, 0, 0, 4, 383, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr }, // Inst #1509 = ERETNC 6319 { 1508, 0, 0, 4, 381, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr }, // Inst #1508 = ERET 6320 { 1507, 1, 1, 4, 1061, 0, 0, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo58 }, // Inst #1507 = EMT 6321 { 1506, 1, 1, 4, 1049, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo58 }, // Inst #1506 = EI_MMR6 6322 { 1505, 1, 1, 4, 1032, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo58 }, // Inst #1505 = EI_MM 6323 { 1504, 1, 1, 4, 477, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo58 }, // Inst #1504 = EI 6324 { 1503, 0, 0, 4, 1050, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #1503 = EHB_MMR6 6325 { 1502, 0, 0, 4, 1033, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #1502 = EHB_MM 6326 { 1501, 0, 0, 4, 479, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #1501 = EHB 6327 { 1500, 2, 0, 2, 877, 0, 2, 0, 0x0ULL, ImplicitList6, OperandInfo130 }, // Inst #1500 = DivuRxRy16 6328 { 1499, 2, 0, 2, 876, 0, 2, 0, 0x0ULL, ImplicitList6, OperandInfo130 }, // Inst #1499 = DivRxRy16 6329 { 1498, 1, 1, 4, 1047, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo58 }, // Inst #1498 = DVP_MMR6 6330 { 1497, 1, 1, 4, 1060, 0, 0, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo58 }, // Inst #1497 = DVPE 6331 { 1496, 1, 1, 4, 1026, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo58 }, // Inst #1496 = DVP 6332 { 1495, 2, 0, 4, 905, 0, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList13, OperandInfo122 }, // Inst #1495 = DUDIV 6333 { 1494, 3, 1, 4, 839, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, OperandInfo71 }, // Inst #1494 = DSUBu 6334 { 1493, 3, 1, 4, 838, 0, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo71 }, // Inst #1493 = DSUB 6335 { 1492, 3, 1, 4, 837, 0, 0, 0, 0x1ULL, nullptr, OperandInfo244 }, // Inst #1492 = DSRLV 6336 { 1491, 3, 1, 4, 836, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo70 }, // Inst #1491 = DSRL32 6337 { 1490, 3, 1, 4, 835, 0, 0, 0, 0x1ULL, nullptr, OperandInfo70 }, // Inst #1490 = DSRL 6338 { 1489, 3, 1, 4, 834, 0, 0, 0, 0x1ULL, nullptr, OperandInfo244 }, // Inst #1489 = DSRAV 6339 { 1488, 3, 1, 4, 833, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo70 }, // Inst #1488 = DSRA32 6340 { 1487, 3, 1, 4, 832, 0, 0, 0, 0x1ULL, nullptr, OperandInfo70 }, // Inst #1487 = DSRA 6341 { 1486, 3, 1, 4, 831, 0, 0, 0, 0x1ULL, nullptr, OperandInfo244 }, // Inst #1486 = DSLLV 6342 { 1485, 2, 1, 4, 808, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo245 }, // Inst #1485 = DSLL64_32 6343 { 1484, 3, 1, 4, 830, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo70 }, // Inst #1484 = DSLL32 6344 { 1483, 3, 1, 4, 829, 0, 0, 0, 0x1ULL, nullptr, OperandInfo70 }, // Inst #1483 = DSLL 6345 { 1482, 2, 1, 4, 828, 0, 0, 0, 0x1ULL, nullptr, OperandInfo122 }, // Inst #1482 = DSHD 6346 { 1481, 2, 0, 4, 904, 0, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList13, OperandInfo122 }, // Inst #1481 = DSDIV 6347 { 1480, 2, 1, 4, 827, 0, 0, 0, 0x1ULL, nullptr, OperandInfo122 }, // Inst #1480 = DSBH 6348 { 1479, 3, 1, 4, 826, 0, 0, 0, 0x1ULL, nullptr, OperandInfo244 }, // Inst #1479 = DROTRV 6349 { 1478, 3, 1, 4, 825, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo70 }, // Inst #1478 = DROTR32 6350 { 1477, 3, 1, 4, 824, 0, 0, 0, 0x1ULL, nullptr, OperandInfo70 }, // Inst #1477 = DROTR 6351 { 1476, 4, 1, 4, 1642, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #1476 = DPS_W_PH_MMR2 6352 { 1475, 4, 1, 4, 1478, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #1475 = DPS_W_PH 6353 { 1474, 4, 1, 4, 1645, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #1474 = DPSX_W_PH_MMR2 6354 { 1473, 4, 1, 4, 1481, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #1473 = DPSX_W_PH 6355 { 1472, 4, 1, 4, 1535, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #1472 = DPSU_H_QBR_MM 6356 { 1471, 4, 1, 4, 1384, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #1471 = DPSU_H_QBR 6357 { 1470, 4, 1, 4, 1534, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #1470 = DPSU_H_QBL_MM 6358 { 1469, 4, 1, 4, 1383, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #1469 = DPSU_H_QBL 6359 { 1468, 4, 1, 4, 666, 0, 0, 0, 0x6ULL, nullptr, OperandInfo242 }, // Inst #1468 = DPSUB_U_W 6360 { 1467, 4, 1, 4, 666, 0, 0, 0, 0x6ULL, nullptr, OperandInfo241 }, // Inst #1467 = DPSUB_U_H 6361 { 1466, 4, 1, 4, 666, 0, 0, 0, 0x6ULL, nullptr, OperandInfo240 }, // Inst #1466 = DPSUB_U_D 6362 { 1465, 4, 1, 4, 666, 0, 0, 0, 0x6ULL, nullptr, OperandInfo242 }, // Inst #1465 = DPSUB_S_W 6363 { 1464, 4, 1, 4, 666, 0, 0, 0, 0x6ULL, nullptr, OperandInfo241 }, // Inst #1464 = DPSUB_S_H 6364 { 1463, 4, 1, 4, 666, 0, 0, 0, 0x6ULL, nullptr, OperandInfo240 }, // Inst #1463 = DPSUB_S_D 6365 { 1462, 4, 1, 4, 1533, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1462 = DPSQ_S_W_PH_MM 6366 { 1461, 4, 1, 4, 1382, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1461 = DPSQ_S_W_PH 6367 { 1460, 4, 1, 4, 1532, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1460 = DPSQ_SA_L_W_MM 6368 { 1459, 4, 1, 4, 1381, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1459 = DPSQ_SA_L_W 6369 { 1458, 4, 1, 4, 1643, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1458 = DPSQX_S_W_PH_MMR2 6370 { 1457, 4, 1, 4, 1479, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1457 = DPSQX_S_W_PH 6371 { 1456, 4, 1, 4, 1644, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1456 = DPSQX_SA_W_PH_MMR2 6372 { 1455, 4, 1, 4, 1480, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1455 = DPSQX_SA_W_PH 6373 { 1454, 2, 1, 4, 1203, 0, 0, 0, 0x1ULL, nullptr, OperandInfo122 }, // Inst #1454 = DPOP 6374 { 1453, 4, 1, 4, 1638, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #1453 = DPA_W_PH_MMR2 6375 { 1452, 4, 1, 4, 1474, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #1452 = DPA_W_PH 6376 { 1451, 4, 1, 4, 1641, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #1451 = DPAX_W_PH_MMR2 6377 { 1450, 4, 1, 4, 1477, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #1450 = DPAX_W_PH 6378 { 1449, 4, 1, 4, 1531, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #1449 = DPAU_H_QBR_MM 6379 { 1448, 4, 1, 4, 1380, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #1448 = DPAU_H_QBR 6380 { 1447, 4, 1, 4, 1530, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #1447 = DPAU_H_QBL_MM 6381 { 1446, 4, 1, 4, 1379, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #1446 = DPAU_H_QBL 6382 { 1445, 4, 1, 4, 1529, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1445 = DPAQ_S_W_PH_MM 6383 { 1444, 4, 1, 4, 1378, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1444 = DPAQ_S_W_PH 6384 { 1443, 4, 1, 4, 1528, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1443 = DPAQ_SA_L_W_MM 6385 { 1442, 4, 1, 4, 1377, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1442 = DPAQ_SA_L_W 6386 { 1441, 4, 1, 4, 1640, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1441 = DPAQX_S_W_PH_MMR2 6387 { 1440, 4, 1, 4, 1476, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1440 = DPAQX_S_W_PH 6388 { 1439, 4, 1, 4, 1639, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1439 = DPAQX_SA_W_PH_MMR2 6389 { 1438, 4, 1, 4, 1475, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1438 = DPAQX_SA_W_PH 6390 { 1437, 4, 1, 4, 665, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo242 }, // Inst #1437 = DPADD_U_W 6391 { 1436, 4, 1, 4, 665, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo241 }, // Inst #1436 = DPADD_U_H 6392 { 1435, 4, 1, 4, 665, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo240 }, // Inst #1435 = DPADD_U_D 6393 { 1434, 4, 1, 4, 665, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo242 }, // Inst #1434 = DPADD_S_W 6394 { 1433, 4, 1, 4, 665, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo241 }, // Inst #1433 = DPADD_S_H 6395 { 1432, 4, 1, 4, 665, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo240 }, // Inst #1432 = DPADD_S_D 6396 { 1431, 3, 1, 4, 667, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo239 }, // Inst #1431 = DOTP_U_W 6397 { 1430, 3, 1, 4, 667, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo238 }, // Inst #1430 = DOTP_U_H 6398 { 1429, 3, 1, 4, 667, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo237 }, // Inst #1429 = DOTP_U_D 6399 { 1428, 3, 1, 4, 667, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo239 }, // Inst #1428 = DOTP_S_W 6400 { 1427, 3, 1, 4, 667, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo238 }, // Inst #1427 = DOTP_S_H 6401 { 1426, 3, 1, 4, 667, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo237 }, // Inst #1426 = DOTP_S_D 6402 { 1425, 3, 1, 4, 914, 0, 0, 0, 0x6ULL, nullptr, OperandInfo71 }, // Inst #1425 = DMUL_R6 6403 { 1424, 3, 1, 4, 901, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo71 }, // Inst #1424 = DMULU 6404 { 1423, 2, 0, 4, 903, 0, 2, 0|(1ULL<<MCID::Commutable), 0x1ULL, ImplicitList13, OperandInfo122 }, // Inst #1423 = DMULTu 6405 { 1422, 2, 0, 4, 902, 0, 2, 0|(1ULL<<MCID::Commutable), 0x1ULL, ImplicitList13, OperandInfo122 }, // Inst #1422 = DMULT 6406 { 1421, 3, 1, 4, 1209, 0, 5, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, ImplicitList12, OperandInfo71 }, // Inst #1421 = DMUL 6407 { 1420, 3, 1, 4, 913, 0, 0, 0, 0x6ULL, nullptr, OperandInfo71 }, // Inst #1420 = DMUHU 6408 { 1419, 3, 1, 4, 912, 0, 0, 0, 0x6ULL, nullptr, OperandInfo71 }, // Inst #1419 = DMUH 6409 { 1418, 3, 1, 4, 1068, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo235 }, // Inst #1418 = DMTGC0 6410 { 1417, 2, 2, 4, 1202, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo112 }, // Inst #1417 = DMTC2_OCTEON 6411 { 1416, 3, 1, 4, 1056, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo236 }, // Inst #1416 = DMTC2 6412 { 1415, 2, 1, 4, 1341, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL, nullptr, OperandInfo134 }, // Inst #1415 = DMTC1 6413 { 1414, 3, 1, 4, 1054, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo235 }, // Inst #1414 = DMTC0 6414 { 1413, 1, 1, 4, 1059, 0, 0, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo58 }, // Inst #1413 = DMT 6415 { 1412, 3, 1, 4, 918, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, OperandInfo71 }, // Inst #1412 = DMODU 6416 { 1411, 3, 1, 4, 916, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, OperandInfo71 }, // Inst #1411 = DMOD 6417 { 1410, 3, 1, 4, 1067, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo232 }, // Inst #1410 = DMFGC0 6418 { 1409, 2, 2, 4, 1201, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo112 }, // Inst #1409 = DMFC2_OCTEON 6419 { 1408, 3, 1, 4, 1055, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo234 }, // Inst #1408 = DMFC2 6420 { 1407, 2, 1, 4, 1340, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL, nullptr, OperandInfo233 }, // Inst #1407 = DMFC1 6421 { 1406, 3, 1, 4, 1053, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo232 }, // Inst #1406 = DMFC0 6422 { 1405, 4, 1, 4, 851, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo230 }, // Inst #1405 = DLSA_R6 6423 { 1404, 4, 1, 4, 851, 0, 0, 0, 0x6ULL, nullptr, OperandInfo230 }, // Inst #1404 = DLSA 6424 { 1403, 1, 1, 4, 1048, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo58 }, // Inst #1403 = DI_MMR6 6425 { 1402, 1, 1, 4, 1031, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo58 }, // Inst #1402 = DI_MM 6426 { 1401, 3, 1, 4, 614, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1401 = DIV_U_W 6427 { 1400, 3, 1, 4, 614, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #1400 = DIV_U_H 6428 { 1399, 3, 1, 4, 614, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1399 = DIV_U_D 6429 { 1398, 3, 1, 4, 614, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #1398 = DIV_U_B 6430 { 1397, 3, 1, 4, 614, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1397 = DIV_S_W 6431 { 1396, 3, 1, 4, 614, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #1396 = DIV_S_H 6432 { 1395, 3, 1, 4, 614, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1395 = DIV_S_D 6433 { 1394, 3, 1, 4, 614, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #1394 = DIV_S_B 6434 { 1393, 3, 1, 4, 899, 0, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, OperandInfo72 }, // Inst #1393 = DIV_MMR6 6435 { 1392, 3, 1, 4, 898, 0, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, OperandInfo72 }, // Inst #1392 = DIVU_MMR6 6436 { 1391, 3, 1, 4, 485, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, OperandInfo72 }, // Inst #1391 = DIVU 6437 { 1390, 3, 1, 4, 484, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, OperandInfo72 }, // Inst #1390 = DIV 6438 { 1389, 5, 1, 4, 823, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo231 }, // Inst #1389 = DINSU 6439 { 1388, 5, 1, 4, 823, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo231 }, // Inst #1388 = DINSM 6440 { 1387, 5, 1, 4, 823, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo231 }, // Inst #1387 = DINS 6441 { 1386, 1, 1, 4, 476, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo58 }, // Inst #1386 = DI 6442 { 1385, 4, 1, 4, 822, 0, 0, 0, 0x1ULL, nullptr, OperandInfo211 }, // Inst #1385 = DEXTU 6443 { 1384, 4, 1, 4, 822, 0, 0, 0, 0x1ULL, nullptr, OperandInfo211 }, // Inst #1384 = DEXTM 6444 { 1383, 4, 1, 4, 807, 0, 0, 0, 0x1ULL, nullptr, OperandInfo212 }, // Inst #1383 = DEXT64_32 6445 { 1382, 4, 1, 4, 822, 0, 0, 0, 0x1ULL, nullptr, OperandInfo211 }, // Inst #1382 = DEXT 6446 { 1381, 0, 0, 4, 988, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr }, // Inst #1381 = DERET_MMR6 6447 { 1380, 0, 0, 4, 952, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr }, // Inst #1380 = DERET_MM 6448 { 1379, 0, 0, 4, 380, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr }, // Inst #1379 = DERET 6449 { 1378, 3, 1, 4, 917, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, OperandInfo71 }, // Inst #1378 = DDIVU 6450 { 1377, 3, 1, 4, 915, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, OperandInfo71 }, // Inst #1377 = DDIV 6451 { 1376, 2, 1, 4, 849, 0, 0, 0, 0x6ULL, nullptr, OperandInfo122 }, // Inst #1376 = DCLZ_R6 6452 { 1375, 2, 1, 4, 821, 0, 0, 0, 0x1ULL, nullptr, OperandInfo122 }, // Inst #1375 = DCLZ 6453 { 1374, 2, 1, 4, 848, 0, 0, 0, 0x6ULL, nullptr, OperandInfo122 }, // Inst #1374 = DCLO_R6 6454 { 1373, 2, 1, 4, 820, 0, 0, 0, 0x1ULL, nullptr, OperandInfo122 }, // Inst #1373 = DCLO 6455 { 1372, 2, 1, 4, 850, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo122 }, // Inst #1372 = DBITSWAP 6456 { 1371, 3, 1, 4, 847, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo70 }, // Inst #1371 = DAUI 6457 { 1370, 3, 1, 4, 846, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo229 }, // Inst #1370 = DATI 6458 { 1369, 4, 1, 4, 844, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo230 }, // Inst #1369 = DALIGN 6459 { 1368, 3, 1, 4, 845, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo229 }, // Inst #1368 = DAHI 6460 { 1367, 3, 1, 4, 819, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, OperandInfo71 }, // Inst #1367 = DADDu 6461 { 1366, 3, 1, 4, 818, 0, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL, nullptr, OperandInfo70 }, // Inst #1366 = DADDiu 6462 { 1365, 3, 1, 4, 817, 0, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo70 }, // Inst #1365 = DADDi 6463 { 1364, 3, 1, 4, 816, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo71 }, // Inst #1364 = DADD 6464 { 1363, 2, 0, 4, 735, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList7, OperandInfo183 }, // Inst #1363 = CmpiRxImmX16 6465 { 1362, 2, 0, 2, 735, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList7, OperandInfo183 }, // Inst #1362 = CmpiRxImm16 6466 { 1361, 2, 0, 2, 735, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList7, OperandInfo130 }, // Inst #1361 = CmpRxRy16 6467 { 1360, 3, 1, 4, 1260, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1360 = C_UN_S_MM 6468 { 1359, 3, 1, 4, 641, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1359 = C_UN_S 6469 { 1358, 3, 1, 4, 1259, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1358 = C_UN_D64_MM 6470 { 1357, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1357 = C_UN_D64 6471 { 1356, 3, 1, 4, 1259, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1356 = C_UN_D32_MM 6472 { 1355, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1355 = C_UN_D32 6473 { 1354, 3, 1, 4, 1262, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1354 = C_ULT_S_MM 6474 { 1353, 3, 1, 4, 641, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1353 = C_ULT_S 6475 { 1352, 3, 1, 4, 1261, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1352 = C_ULT_D64_MM 6476 { 1351, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1351 = C_ULT_D64 6477 { 1350, 3, 1, 4, 1261, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1350 = C_ULT_D32_MM 6478 { 1349, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1349 = C_ULT_D32 6479 { 1348, 3, 1, 4, 1262, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1348 = C_ULE_S_MM 6480 { 1347, 3, 1, 4, 641, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1347 = C_ULE_S 6481 { 1346, 3, 1, 4, 1261, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1346 = C_ULE_D64_MM 6482 { 1345, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1345 = C_ULE_D64 6483 { 1344, 3, 1, 4, 1261, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1344 = C_ULE_D32_MM 6484 { 1343, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1343 = C_ULE_D32 6485 { 1342, 3, 1, 4, 1262, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1342 = C_UEQ_S_MM 6486 { 1341, 3, 1, 4, 641, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1341 = C_UEQ_S 6487 { 1340, 3, 1, 4, 1261, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1340 = C_UEQ_D64_MM 6488 { 1339, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1339 = C_UEQ_D64 6489 { 1338, 3, 1, 4, 1261, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1338 = C_UEQ_D32_MM 6490 { 1337, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1337 = C_UEQ_D32 6491 { 1336, 3, 1, 4, 1260, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1336 = C_SF_S_MM 6492 { 1335, 3, 1, 4, 641, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1335 = C_SF_S 6493 { 1334, 3, 1, 4, 1259, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1334 = C_SF_D64_MM 6494 { 1333, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1333 = C_SF_D64 6495 { 1332, 3, 1, 4, 1259, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1332 = C_SF_D32_MM 6496 { 1331, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1331 = C_SF_D32 6497 { 1330, 3, 1, 4, 1262, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1330 = C_SEQ_S_MM 6498 { 1329, 3, 1, 4, 641, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1329 = C_SEQ_S 6499 { 1328, 3, 1, 4, 1261, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1328 = C_SEQ_D64_MM 6500 { 1327, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1327 = C_SEQ_D64 6501 { 1326, 3, 1, 4, 1261, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1326 = C_SEQ_D32_MM 6502 { 1325, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1325 = C_SEQ_D32 6503 { 1324, 3, 1, 4, 1262, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1324 = C_OLT_S_MM 6504 { 1323, 3, 1, 4, 641, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1323 = C_OLT_S 6505 { 1322, 3, 1, 4, 1261, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1322 = C_OLT_D64_MM 6506 { 1321, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1321 = C_OLT_D64 6507 { 1320, 3, 1, 4, 1261, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1320 = C_OLT_D32_MM 6508 { 1319, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1319 = C_OLT_D32 6509 { 1318, 3, 1, 4, 1262, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1318 = C_OLE_S_MM 6510 { 1317, 3, 1, 4, 641, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1317 = C_OLE_S 6511 { 1316, 3, 1, 4, 1261, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1316 = C_OLE_D64_MM 6512 { 1315, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1315 = C_OLE_D64 6513 { 1314, 3, 1, 4, 1261, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1314 = C_OLE_D32_MM 6514 { 1313, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1313 = C_OLE_D32 6515 { 1312, 3, 1, 4, 1262, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1312 = C_NGT_S_MM 6516 { 1311, 3, 1, 4, 641, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1311 = C_NGT_S 6517 { 1310, 3, 1, 4, 1261, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1310 = C_NGT_D64_MM 6518 { 1309, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1309 = C_NGT_D64 6519 { 1308, 3, 1, 4, 1261, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1308 = C_NGT_D32_MM 6520 { 1307, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1307 = C_NGT_D32 6521 { 1306, 3, 1, 4, 1262, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1306 = C_NGL_S_MM 6522 { 1305, 3, 1, 4, 641, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1305 = C_NGL_S 6523 { 1304, 3, 1, 4, 1261, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1304 = C_NGL_D64_MM 6524 { 1303, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1303 = C_NGL_D64 6525 { 1302, 3, 1, 4, 1261, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1302 = C_NGL_D32_MM 6526 { 1301, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1301 = C_NGL_D32 6527 { 1300, 3, 1, 4, 1264, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1300 = C_NGLE_S_MM 6528 { 1299, 3, 1, 4, 641, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1299 = C_NGLE_S 6529 { 1298, 3, 1, 4, 1263, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1298 = C_NGLE_D64_MM 6530 { 1297, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1297 = C_NGLE_D64 6531 { 1296, 3, 1, 4, 1263, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1296 = C_NGLE_D32_MM 6532 { 1295, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1295 = C_NGLE_D32 6533 { 1294, 3, 1, 4, 1262, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1294 = C_NGE_S_MM 6534 { 1293, 3, 1, 4, 641, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1293 = C_NGE_S 6535 { 1292, 3, 1, 4, 1261, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1292 = C_NGE_D64_MM 6536 { 1291, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1291 = C_NGE_D64 6537 { 1290, 3, 1, 4, 1261, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1290 = C_NGE_D32_MM 6538 { 1289, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1289 = C_NGE_D32 6539 { 1288, 3, 1, 4, 1260, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1288 = C_LT_S_MM 6540 { 1287, 3, 1, 4, 641, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1287 = C_LT_S 6541 { 1286, 3, 1, 4, 1259, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1286 = C_LT_D64_MM 6542 { 1285, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1285 = C_LT_D64 6543 { 1284, 3, 1, 4, 1259, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1284 = C_LT_D32_MM 6544 { 1283, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1283 = C_LT_D32 6545 { 1282, 3, 1, 4, 1260, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1282 = C_LE_S_MM 6546 { 1281, 3, 1, 4, 641, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1281 = C_LE_S 6547 { 1280, 3, 1, 4, 1259, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1280 = C_LE_D64_MM 6548 { 1279, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1279 = C_LE_D64 6549 { 1278, 3, 1, 4, 1259, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1278 = C_LE_D32_MM 6550 { 1277, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1277 = C_LE_D32 6551 { 1276, 3, 1, 4, 1258, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1276 = C_F_S_MM 6552 { 1275, 3, 1, 4, 641, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1275 = C_F_S 6553 { 1274, 3, 1, 4, 1257, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1274 = C_F_D64_MM 6554 { 1273, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1273 = C_F_D64 6555 { 1272, 3, 1, 4, 1257, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1272 = C_F_D32_MM 6556 { 1271, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1271 = C_F_D32 6557 { 1270, 3, 1, 4, 1260, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1270 = C_EQ_S_MM 6558 { 1269, 3, 1, 4, 641, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1269 = C_EQ_S 6559 { 1268, 3, 1, 4, 1259, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1268 = C_EQ_D64_MM 6560 { 1267, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1267 = C_EQ_D64 6561 { 1266, 3, 1, 4, 1259, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1266 = C_EQ_D32_MM 6562 { 1265, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1265 = C_EQ_D32 6563 { 1264, 2, 1, 4, 1307, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #1264 = CVT_W_S_MMR6 6564 { 1263, 2, 1, 4, 1246, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #1263 = CVT_W_S_MM 6565 { 1262, 2, 1, 4, 638, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #1262 = CVT_W_S 6566 { 1261, 2, 1, 4, 1246, 0, 0, 0, 0x4ULL, nullptr, OperandInfo206 }, // Inst #1261 = CVT_W_D64_MM 6567 { 1260, 2, 1, 4, 638, 0, 0, 0, 0x4ULL, nullptr, OperandInfo206 }, // Inst #1260 = CVT_W_D64 6568 { 1259, 2, 1, 4, 1246, 0, 0, 0, 0x4ULL, nullptr, OperandInfo205 }, // Inst #1259 = CVT_W_D32_MM 6569 { 1258, 2, 1, 4, 638, 0, 0, 0, 0x4ULL, nullptr, OperandInfo205 }, // Inst #1258 = CVT_W_D32 6570 { 1257, 2, 1, 4, 1307, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #1257 = CVT_S_W_MMR6 6571 { 1256, 2, 1, 4, 1246, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #1256 = CVT_S_W_MM 6572 { 1255, 2, 1, 4, 638, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #1255 = CVT_S_W 6573 { 1254, 2, 1, 4, 639, 0, 0, 0, 0x4ULL, nullptr, OperandInfo206 }, // Inst #1254 = CVT_S_PU64 6574 { 1253, 2, 1, 4, 639, 0, 0, 0, 0x4ULL, nullptr, OperandInfo206 }, // Inst #1253 = CVT_S_PL64 6575 { 1252, 2, 1, 4, 1307, 0, 0, 0, 0x4ULL, nullptr, OperandInfo204 }, // Inst #1252 = CVT_S_L_MMR6 6576 { 1251, 2, 1, 4, 638, 0, 0, 0, 0x4ULL, nullptr, OperandInfo206 }, // Inst #1251 = CVT_S_L 6577 { 1250, 2, 1, 4, 1246, 0, 0, 0, 0x4ULL, nullptr, OperandInfo206 }, // Inst #1250 = CVT_S_D64_MM 6578 { 1249, 2, 1, 4, 638, 0, 0, 0, 0x4ULL, nullptr, OperandInfo206 }, // Inst #1249 = CVT_S_D64 6579 { 1248, 2, 1, 4, 1246, 0, 0, 0, 0x4ULL, nullptr, OperandInfo205 }, // Inst #1248 = CVT_S_D32_MM 6580 { 1247, 2, 1, 4, 638, 0, 0, 0, 0x4ULL, nullptr, OperandInfo205 }, // Inst #1247 = CVT_S_D32 6581 { 1246, 2, 1, 4, 1212, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #1246 = CVT_PW_PS64 6582 { 1245, 3, 1, 4, 639, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo225 }, // Inst #1245 = CVT_PS_S64 6583 { 1244, 2, 1, 4, 1212, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #1244 = CVT_PS_PW64 6584 { 1243, 2, 1, 4, 1307, 0, 0, 0, 0x4ULL, nullptr, OperandInfo204 }, // Inst #1243 = CVT_L_S_MMR6 6585 { 1242, 2, 1, 4, 1246, 0, 0, 0, 0x4ULL, nullptr, OperandInfo204 }, // Inst #1242 = CVT_L_S_MM 6586 { 1241, 2, 1, 4, 638, 0, 0, 0, 0x4ULL, nullptr, OperandInfo204 }, // Inst #1241 = CVT_L_S 6587 { 1240, 2, 1, 4, 1307, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #1240 = CVT_L_D_MMR6 6588 { 1239, 2, 1, 4, 1246, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #1239 = CVT_L_D64_MM 6589 { 1238, 2, 1, 4, 638, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #1238 = CVT_L_D64 6590 { 1237, 2, 1, 4, 1307, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #1237 = CVT_D_L_MMR6 6591 { 1236, 2, 1, 4, 1246, 0, 0, 0, 0x4ULL, nullptr, OperandInfo204 }, // Inst #1236 = CVT_D64_W_MM 6592 { 1235, 2, 1, 4, 638, 0, 0, 0, 0x4ULL, nullptr, OperandInfo204 }, // Inst #1235 = CVT_D64_W 6593 { 1234, 2, 1, 4, 1246, 0, 0, 0, 0x4ULL, nullptr, OperandInfo204 }, // Inst #1234 = CVT_D64_S_MM 6594 { 1233, 2, 1, 4, 638, 0, 0, 0, 0x4ULL, nullptr, OperandInfo204 }, // Inst #1233 = CVT_D64_S 6595 { 1232, 2, 1, 4, 638, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #1232 = CVT_D64_L 6596 { 1231, 2, 1, 4, 1246, 0, 0, 0, 0x4ULL, nullptr, OperandInfo224 }, // Inst #1231 = CVT_D32_W_MM 6597 { 1230, 2, 1, 4, 638, 0, 0, 0, 0x4ULL, nullptr, OperandInfo224 }, // Inst #1230 = CVT_D32_W 6598 { 1229, 2, 1, 4, 1246, 0, 0, 0, 0x4ULL, nullptr, OperandInfo224 }, // Inst #1229 = CVT_D32_S_MM 6599 { 1228, 2, 1, 4, 638, 0, 0, 0, 0x4ULL, nullptr, OperandInfo224 }, // Inst #1228 = CVT_D32_S 6600 { 1227, 2, 0, 4, 529, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo223 }, // Inst #1227 = CTCMSA 6601 { 1226, 2, 1, 4, 1058, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo222 }, // Inst #1226 = CTC2_MM 6602 { 1225, 2, 1, 4, 1295, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo221 }, // Inst #1225 = CTC1_MM 6603 { 1224, 2, 1, 4, 685, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo221 }, // Inst #1224 = CTC1 6604 { 1223, 3, 1, 4, 1192, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo72 }, // Inst #1223 = CRC32W 6605 { 1222, 3, 1, 4, 1191, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo72 }, // Inst #1222 = CRC32H 6606 { 1221, 3, 1, 4, 1196, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo72 }, // Inst #1221 = CRC32D 6607 { 1220, 3, 1, 4, 1195, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo72 }, // Inst #1220 = CRC32CW 6608 { 1219, 3, 1, 4, 1194, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo72 }, // Inst #1219 = CRC32CH 6609 { 1218, 3, 1, 4, 1197, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo72 }, // Inst #1218 = CRC32CD 6610 { 1217, 3, 1, 4, 1193, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo72 }, // Inst #1217 = CRC32CB 6611 { 1216, 3, 1, 4, 1190, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo72 }, // Inst #1216 = CRC32B 6612 { 1215, 3, 1, 4, 688, 0, 0, 0, 0x6ULL, nullptr, OperandInfo220 }, // Inst #1215 = COPY_U_W 6613 { 1214, 3, 1, 4, 688, 0, 0, 0, 0x6ULL, nullptr, OperandInfo219 }, // Inst #1214 = COPY_U_H 6614 { 1213, 3, 1, 4, 688, 0, 0, 0, 0x6ULL, nullptr, OperandInfo217 }, // Inst #1213 = COPY_U_B 6615 { 1212, 3, 1, 4, 689, 0, 0, 0, 0x6ULL, nullptr, OperandInfo220 }, // Inst #1212 = COPY_S_W 6616 { 1211, 3, 1, 4, 689, 0, 0, 0, 0x6ULL, nullptr, OperandInfo219 }, // Inst #1211 = COPY_S_H 6617 { 1210, 3, 1, 4, 689, 0, 0, 0, 0x6ULL, nullptr, OperandInfo218 }, // Inst #1210 = COPY_S_D 6618 { 1209, 3, 1, 4, 689, 0, 0, 0, 0x6ULL, nullptr, OperandInfo217 }, // Inst #1209 = COPY_S_B 6619 { 1208, 3, 1, 4, 1302, 0, 0, 0, 0x16ULL, nullptr, OperandInfo216 }, // Inst #1208 = CMP_UN_S_MMR6 6620 { 1207, 3, 1, 4, 558, 0, 0, 0, 0x16ULL, nullptr, OperandInfo216 }, // Inst #1207 = CMP_UN_S 6621 { 1206, 3, 1, 4, 1301, 0, 0, 0, 0x16ULL, nullptr, OperandInfo215 }, // Inst #1206 = CMP_UN_D_MMR6 6622 { 1205, 3, 1, 4, 557, 0, 0, 0, 0x16ULL, nullptr, OperandInfo215 }, // Inst #1205 = CMP_UN_D 6623 { 1204, 3, 1, 4, 1304, 0, 0, 0, 0x16ULL, nullptr, OperandInfo216 }, // Inst #1204 = CMP_ULT_S_MMR6 6624 { 1203, 3, 1, 4, 566, 0, 0, 0, 0x16ULL, nullptr, OperandInfo216 }, // Inst #1203 = CMP_ULT_S 6625 { 1202, 3, 1, 4, 1303, 0, 0, 0, 0x16ULL, nullptr, OperandInfo215 }, // Inst #1202 = CMP_ULT_D_MMR6 6626 { 1201, 3, 1, 4, 565, 0, 0, 0, 0x16ULL, nullptr, OperandInfo215 }, // Inst #1201 = CMP_ULT_D 6627 { 1200, 3, 1, 4, 1304, 0, 0, 0, 0x16ULL, nullptr, OperandInfo216 }, // Inst #1200 = CMP_ULE_S_MMR6 6628 { 1199, 3, 1, 4, 570, 0, 0, 0, 0x16ULL, nullptr, OperandInfo216 }, // Inst #1199 = CMP_ULE_S 6629 { 1198, 3, 1, 4, 1303, 0, 0, 0, 0x16ULL, nullptr, OperandInfo215 }, // Inst #1198 = CMP_ULE_D_MMR6 6630 { 1197, 3, 1, 4, 569, 0, 0, 0, 0x16ULL, nullptr, OperandInfo215 }, // Inst #1197 = CMP_ULE_D 6631 { 1196, 3, 1, 4, 1304, 0, 0, 0, 0x16ULL, nullptr, OperandInfo216 }, // Inst #1196 = CMP_UEQ_S_MMR6 6632 { 1195, 3, 1, 4, 560, 0, 0, 0, 0x16ULL, nullptr, OperandInfo216 }, // Inst #1195 = CMP_UEQ_S 6633 { 1194, 3, 1, 4, 1303, 0, 0, 0, 0x16ULL, nullptr, OperandInfo215 }, // Inst #1194 = CMP_UEQ_D_MMR6 6634 { 1193, 3, 1, 4, 559, 0, 0, 0, 0x16ULL, nullptr, OperandInfo215 }, // Inst #1193 = CMP_UEQ_D 6635 { 1192, 3, 1, 4, 1304, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo216 }, // Inst #1192 = CMP_SUN_S_MMR6 6636 { 1191, 3, 1, 4, 1688, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo216 }, // Inst #1191 = CMP_SUN_S 6637 { 1190, 3, 1, 4, 1303, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo215 }, // Inst #1190 = CMP_SUN_D_MMR6 6638 { 1189, 3, 1, 4, 1687, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo215 }, // Inst #1189 = CMP_SUN_D 6639 { 1188, 3, 1, 4, 1306, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo216 }, // Inst #1188 = CMP_SULT_S_MMR6 6640 { 1187, 3, 1, 4, 1686, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo216 }, // Inst #1187 = CMP_SULT_S 6641 { 1186, 3, 1, 4, 1305, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo215 }, // Inst #1186 = CMP_SULT_D_MMR6 6642 { 1185, 3, 1, 4, 1685, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo215 }, // Inst #1185 = CMP_SULT_D 6643 { 1184, 3, 1, 4, 1306, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo216 }, // Inst #1184 = CMP_SULE_S_MMR6 6644 { 1183, 3, 1, 4, 1684, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo216 }, // Inst #1183 = CMP_SULE_S 6645 { 1182, 3, 1, 4, 1305, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo215 }, // Inst #1182 = CMP_SULE_D_MMR6 6646 { 1181, 3, 1, 4, 1683, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo215 }, // Inst #1181 = CMP_SULE_D 6647 { 1180, 3, 1, 4, 1306, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo216 }, // Inst #1180 = CMP_SUEQ_S_MMR6 6648 { 1179, 3, 1, 4, 1682, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo216 }, // Inst #1179 = CMP_SUEQ_S 6649 { 1178, 3, 1, 4, 1305, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo215 }, // Inst #1178 = CMP_SUEQ_D_MMR6 6650 { 1177, 3, 1, 4, 1681, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo215 }, // Inst #1177 = CMP_SUEQ_D 6651 { 1176, 3, 1, 4, 1304, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo216 }, // Inst #1176 = CMP_SLT_S_MMR6 6652 { 1175, 3, 1, 4, 1680, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo216 }, // Inst #1175 = CMP_SLT_S 6653 { 1174, 3, 1, 4, 1303, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo215 }, // Inst #1174 = CMP_SLT_D_MMR6 6654 { 1173, 3, 1, 4, 1679, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo215 }, // Inst #1173 = CMP_SLT_D 6655 { 1172, 3, 1, 4, 1304, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo216 }, // Inst #1172 = CMP_SLE_S_MMR6 6656 { 1171, 3, 1, 4, 1678, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo216 }, // Inst #1171 = CMP_SLE_S 6657 { 1170, 3, 1, 4, 1303, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo215 }, // Inst #1170 = CMP_SLE_D_MMR6 6658 { 1169, 3, 1, 4, 1677, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo215 }, // Inst #1169 = CMP_SLE_D 6659 { 1168, 3, 1, 4, 1304, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo216 }, // Inst #1168 = CMP_SEQ_S_MMR6 6660 { 1167, 3, 1, 4, 1676, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo216 }, // Inst #1167 = CMP_SEQ_S 6661 { 1166, 3, 1, 4, 1303, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo215 }, // Inst #1166 = CMP_SEQ_D_MMR6 6662 { 1165, 3, 1, 4, 1675, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo215 }, // Inst #1165 = CMP_SEQ_D 6663 { 1164, 3, 1, 4, 1304, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo216 }, // Inst #1164 = CMP_SAF_S_MMR6 6664 { 1163, 3, 1, 4, 1674, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo216 }, // Inst #1163 = CMP_SAF_S 6665 { 1162, 3, 1, 4, 1303, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo215 }, // Inst #1162 = CMP_SAF_D_MMR6 6666 { 1161, 3, 1, 4, 1673, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo215 }, // Inst #1161 = CMP_SAF_D 6667 { 1160, 3, 1, 4, 1302, 0, 0, 0, 0x16ULL, nullptr, OperandInfo216 }, // Inst #1160 = CMP_LT_S_MMR6 6668 { 1159, 3, 1, 4, 564, 0, 0, 0, 0x16ULL, nullptr, OperandInfo216 }, // Inst #1159 = CMP_LT_S 6669 { 1158, 2, 0, 4, 1527, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList11, OperandInfo168 }, // Inst #1158 = CMP_LT_PH_MM 6670 { 1157, 2, 0, 4, 1376, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList11, OperandInfo168 }, // Inst #1157 = CMP_LT_PH 6671 { 1156, 3, 1, 4, 1301, 0, 0, 0, 0x16ULL, nullptr, OperandInfo215 }, // Inst #1156 = CMP_LT_D_MMR6 6672 { 1155, 3, 1, 4, 563, 0, 0, 0, 0x16ULL, nullptr, OperandInfo215 }, // Inst #1155 = CMP_LT_D 6673 { 1154, 3, 1, 4, 1302, 0, 0, 0, 0x16ULL, nullptr, OperandInfo216 }, // Inst #1154 = CMP_LE_S_MMR6 6674 { 1153, 3, 1, 4, 568, 0, 0, 0, 0x16ULL, nullptr, OperandInfo216 }, // Inst #1153 = CMP_LE_S 6675 { 1152, 2, 0, 4, 1526, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList11, OperandInfo168 }, // Inst #1152 = CMP_LE_PH_MM 6676 { 1151, 2, 0, 4, 1375, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList11, OperandInfo168 }, // Inst #1151 = CMP_LE_PH 6677 { 1150, 3, 1, 4, 1301, 0, 0, 0, 0x16ULL, nullptr, OperandInfo215 }, // Inst #1150 = CMP_LE_D_MMR6 6678 { 1149, 3, 1, 4, 567, 0, 0, 0, 0x16ULL, nullptr, OperandInfo215 }, // Inst #1149 = CMP_LE_D 6679 { 1148, 3, 1, 4, 1672, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo216 }, // Inst #1148 = CMP_F_S 6680 { 1147, 3, 1, 4, 1671, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo215 }, // Inst #1147 = CMP_F_D 6681 { 1146, 3, 1, 4, 1302, 0, 0, 0, 0x16ULL, nullptr, OperandInfo216 }, // Inst #1146 = CMP_EQ_S_MMR6 6682 { 1145, 3, 1, 4, 562, 0, 0, 0, 0x16ULL, nullptr, OperandInfo216 }, // Inst #1145 = CMP_EQ_S 6683 { 1144, 2, 0, 4, 1525, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList11, OperandInfo168 }, // Inst #1144 = CMP_EQ_PH_MM 6684 { 1143, 2, 0, 4, 1374, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList11, OperandInfo168 }, // Inst #1143 = CMP_EQ_PH 6685 { 1142, 3, 1, 4, 1301, 0, 0, 0, 0x16ULL, nullptr, OperandInfo215 }, // Inst #1142 = CMP_EQ_D_MMR6 6686 { 1141, 3, 1, 4, 561, 0, 0, 0, 0x16ULL, nullptr, OperandInfo215 }, // Inst #1141 = CMP_EQ_D 6687 { 1140, 3, 1, 4, 1302, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo216 }, // Inst #1140 = CMP_AF_S_MMR6 6688 { 1139, 3, 1, 4, 1301, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo215 }, // Inst #1139 = CMP_AF_D_MMR6 6689 { 1138, 2, 0, 4, 1524, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList11, OperandInfo168 }, // Inst #1138 = CMPU_LT_QB_MM 6690 { 1137, 2, 0, 4, 1373, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList11, OperandInfo168 }, // Inst #1137 = CMPU_LT_QB 6691 { 1136, 2, 0, 4, 1523, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList11, OperandInfo168 }, // Inst #1136 = CMPU_LE_QB_MM 6692 { 1135, 2, 0, 4, 1372, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList11, OperandInfo168 }, // Inst #1135 = CMPU_LE_QB 6693 { 1134, 2, 0, 4, 1522, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList11, OperandInfo168 }, // Inst #1134 = CMPU_EQ_QB_MM 6694 { 1133, 2, 0, 4, 1371, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList11, OperandInfo168 }, // Inst #1133 = CMPU_EQ_QB 6695 { 1132, 3, 1, 4, 1521, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo214 }, // Inst #1132 = CMPGU_LT_QB_MM 6696 { 1131, 3, 1, 4, 1370, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo214 }, // Inst #1131 = CMPGU_LT_QB 6697 { 1130, 3, 1, 4, 1520, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo214 }, // Inst #1130 = CMPGU_LE_QB_MM 6698 { 1129, 3, 1, 4, 1369, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo214 }, // Inst #1129 = CMPGU_LE_QB 6699 { 1128, 3, 1, 4, 1519, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo214 }, // Inst #1128 = CMPGU_EQ_QB_MM 6700 { 1127, 3, 1, 4, 1368, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo214 }, // Inst #1127 = CMPGU_EQ_QB 6701 { 1126, 3, 1, 4, 1637, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList11, OperandInfo214 }, // Inst #1126 = CMPGDU_LT_QB_MMR2 6702 { 1125, 3, 1, 4, 1473, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList11, OperandInfo214 }, // Inst #1125 = CMPGDU_LT_QB 6703 { 1124, 3, 1, 4, 1636, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList11, OperandInfo214 }, // Inst #1124 = CMPGDU_LE_QB_MMR2 6704 { 1123, 3, 1, 4, 1472, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList11, OperandInfo214 }, // Inst #1123 = CMPGDU_LE_QB 6705 { 1122, 3, 1, 4, 1635, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList11, OperandInfo214 }, // Inst #1122 = CMPGDU_EQ_QB_MMR2 6706 { 1121, 3, 1, 4, 1471, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList11, OperandInfo214 }, // Inst #1121 = CMPGDU_EQ_QB 6707 { 1120, 2, 1, 4, 732, 0, 0, 0, 0x6ULL, nullptr, OperandInfo45 }, // Inst #1120 = CLZ_R6 6708 { 1119, 2, 1, 4, 786, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo45 }, // Inst #1119 = CLZ_MMR6 6709 { 1118, 2, 1, 4, 745, 0, 0, 0, 0x1ULL, nullptr, OperandInfo45 }, // Inst #1118 = CLZ_MM 6710 { 1117, 2, 1, 4, 475, 0, 0, 0, 0x1ULL, nullptr, OperandInfo45 }, // Inst #1117 = CLZ 6711 { 1116, 3, 1, 4, 554, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1116 = CLT_U_W 6712 { 1115, 3, 1, 4, 554, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #1115 = CLT_U_H 6713 { 1114, 3, 1, 4, 554, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1114 = CLT_U_D 6714 { 1113, 3, 1, 4, 554, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #1113 = CLT_U_B 6715 { 1112, 3, 1, 4, 554, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1112 = CLT_S_W 6716 { 1111, 3, 1, 4, 554, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #1111 = CLT_S_H 6717 { 1110, 3, 1, 4, 554, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1110 = CLT_S_D 6718 { 1109, 3, 1, 4, 554, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #1109 = CLT_S_B 6719 { 1108, 3, 1, 4, 554, 0, 0, 0, 0x6ULL, nullptr, OperandInfo179 }, // Inst #1108 = CLTI_U_W 6720 { 1107, 3, 1, 4, 554, 0, 0, 0, 0x6ULL, nullptr, OperandInfo178 }, // Inst #1107 = CLTI_U_H 6721 { 1106, 3, 1, 4, 554, 0, 0, 0, 0x6ULL, nullptr, OperandInfo177 }, // Inst #1106 = CLTI_U_D 6722 { 1105, 3, 1, 4, 554, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #1105 = CLTI_U_B 6723 { 1104, 3, 1, 4, 554, 0, 0, 0, 0x6ULL, nullptr, OperandInfo179 }, // Inst #1104 = CLTI_S_W 6724 { 1103, 3, 1, 4, 554, 0, 0, 0, 0x6ULL, nullptr, OperandInfo178 }, // Inst #1103 = CLTI_S_H 6725 { 1102, 3, 1, 4, 554, 0, 0, 0, 0x6ULL, nullptr, OperandInfo177 }, // Inst #1102 = CLTI_S_D 6726 { 1101, 3, 1, 4, 554, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #1101 = CLTI_S_B 6727 { 1100, 2, 1, 4, 731, 0, 0, 0, 0x6ULL, nullptr, OperandInfo45 }, // Inst #1100 = CLO_R6 6728 { 1099, 2, 1, 4, 785, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo45 }, // Inst #1099 = CLO_MMR6 6729 { 1098, 2, 1, 4, 744, 0, 0, 0, 0x1ULL, nullptr, OperandInfo45 }, // Inst #1098 = CLO_MM 6730 { 1097, 2, 1, 4, 474, 0, 0, 0, 0x1ULL, nullptr, OperandInfo45 }, // Inst #1097 = CLO 6731 { 1096, 3, 1, 4, 555, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1096 = CLE_U_W 6732 { 1095, 3, 1, 4, 555, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #1095 = CLE_U_H 6733 { 1094, 3, 1, 4, 555, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1094 = CLE_U_D 6734 { 1093, 3, 1, 4, 555, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #1093 = CLE_U_B 6735 { 1092, 3, 1, 4, 555, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1092 = CLE_S_W 6736 { 1091, 3, 1, 4, 555, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #1091 = CLE_S_H 6737 { 1090, 3, 1, 4, 555, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1090 = CLE_S_D 6738 { 1089, 3, 1, 4, 555, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #1089 = CLE_S_B 6739 { 1088, 3, 1, 4, 555, 0, 0, 0, 0x6ULL, nullptr, OperandInfo179 }, // Inst #1088 = CLEI_U_W 6740 { 1087, 3, 1, 4, 555, 0, 0, 0, 0x6ULL, nullptr, OperandInfo178 }, // Inst #1087 = CLEI_U_H 6741 { 1086, 3, 1, 4, 555, 0, 0, 0, 0x6ULL, nullptr, OperandInfo177 }, // Inst #1086 = CLEI_U_D 6742 { 1085, 3, 1, 4, 555, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #1085 = CLEI_U_B 6743 { 1084, 3, 1, 4, 555, 0, 0, 0, 0x6ULL, nullptr, OperandInfo179 }, // Inst #1084 = CLEI_S_W 6744 { 1083, 3, 1, 4, 555, 0, 0, 0, 0x6ULL, nullptr, OperandInfo178 }, // Inst #1083 = CLEI_S_H 6745 { 1082, 3, 1, 4, 555, 0, 0, 0, 0x6ULL, nullptr, OperandInfo177 }, // Inst #1082 = CLEI_S_D 6746 { 1081, 3, 1, 4, 555, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #1081 = CLEI_S_B 6747 { 1080, 2, 1, 4, 1314, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo207 }, // Inst #1080 = CLASS_S_MMR6 6748 { 1079, 2, 1, 4, 1227, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo207 }, // Inst #1079 = CLASS_S 6749 { 1078, 2, 1, 4, 1314, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo203 }, // Inst #1078 = CLASS_D_MMR6 6750 { 1077, 2, 1, 4, 1228, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo203 }, // Inst #1077 = CLASS_D 6751 { 1076, 4, 1, 4, 1200, 0, 0, 0, 0x1ULL, nullptr, OperandInfo213 }, // Inst #1076 = CINS_i32 6752 { 1075, 4, 1, 4, 1200, 0, 0, 0, 0x1ULL, nullptr, OperandInfo212 }, // Inst #1075 = CINS64_32 6753 { 1074, 4, 1, 4, 1200, 0, 0, 0, 0x1ULL, nullptr, OperandInfo211 }, // Inst #1074 = CINS32 6754 { 1073, 4, 1, 4, 1200, 0, 0, 0, 0x1ULL, nullptr, OperandInfo211 }, // Inst #1073 = CINS 6755 { 1072, 2, 1, 4, 529, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo210 }, // Inst #1072 = CFCMSA 6756 { 1071, 2, 1, 4, 1057, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo209 }, // Inst #1071 = CFC2_MM 6757 { 1070, 2, 1, 4, 1294, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo208 }, // Inst #1070 = CFC1_MM 6758 { 1069, 2, 1, 4, 694, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo208 }, // Inst #1069 = CFC1 6759 { 1068, 3, 1, 4, 556, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo48 }, // Inst #1068 = CEQ_W 6760 { 1067, 3, 1, 4, 556, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo47 }, // Inst #1067 = CEQ_H 6761 { 1066, 3, 1, 4, 556, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo46 }, // Inst #1066 = CEQ_D 6762 { 1065, 3, 1, 4, 556, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo174 }, // Inst #1065 = CEQ_B 6763 { 1064, 3, 1, 4, 556, 0, 0, 0, 0x6ULL, nullptr, OperandInfo179 }, // Inst #1064 = CEQI_W 6764 { 1063, 3, 1, 4, 556, 0, 0, 0, 0x6ULL, nullptr, OperandInfo178 }, // Inst #1063 = CEQI_H 6765 { 1062, 3, 1, 4, 556, 0, 0, 0, 0x6ULL, nullptr, OperandInfo177 }, // Inst #1062 = CEQI_D 6766 { 1061, 3, 1, 4, 556, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #1061 = CEQI_B 6767 { 1060, 2, 1, 4, 1311, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #1060 = CEIL_W_S_MMR6 6768 { 1059, 2, 1, 4, 1247, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #1059 = CEIL_W_S_MM 6769 { 1058, 2, 1, 4, 717, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #1058 = CEIL_W_S 6770 { 1057, 2, 1, 4, 1247, 0, 0, 0, 0x4ULL, nullptr, OperandInfo205 }, // Inst #1057 = CEIL_W_MM 6771 { 1056, 2, 1, 4, 1311, 0, 0, 0, 0x4ULL, nullptr, OperandInfo205 }, // Inst #1056 = CEIL_W_D_MMR6 6772 { 1055, 2, 1, 4, 717, 0, 0, 0, 0x4ULL, nullptr, OperandInfo206 }, // Inst #1055 = CEIL_W_D64 6773 { 1054, 2, 1, 4, 717, 0, 0, 0, 0x4ULL, nullptr, OperandInfo205 }, // Inst #1054 = CEIL_W_D32 6774 { 1053, 2, 1, 4, 1311, 0, 0, 0, 0x4ULL, nullptr, OperandInfo204 }, // Inst #1053 = CEIL_L_S_MMR6 6775 { 1052, 2, 1, 4, 717, 0, 0, 0, 0x4ULL, nullptr, OperandInfo204 }, // Inst #1052 = CEIL_L_S 6776 { 1051, 2, 1, 4, 1311, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #1051 = CEIL_L_D_MMR6 6777 { 1050, 2, 1, 4, 717, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #1050 = CEIL_L_D64 6778 { 1049, 3, 0, 4, 1088, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo202 }, // Inst #1049 = CACHE_R6 6779 { 1048, 3, 0, 4, 1162, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo202 }, // Inst #1048 = CACHE_MMR6 6780 { 1047, 3, 0, 4, 1140, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo202 }, // Inst #1047 = CACHE_MM 6781 { 1046, 3, 0, 4, 1107, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo202 }, // Inst #1046 = CACHEE_MM 6782 { 1045, 3, 0, 4, 471, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo202 }, // Inst #1045 = CACHEE 6783 { 1044, 3, 0, 4, 470, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo202 }, // Inst #1044 = CACHE 6784 { 1043, 1, 0, 4, 939, 1, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList7, OperandInfo2 }, // Inst #1043 = BtnezX16 6785 { 1042, 1, 0, 2, 939, 1, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList7, OperandInfo2 }, // Inst #1042 = Btnez16 6786 { 1041, 1, 0, 4, 939, 1, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList7, OperandInfo2 }, // Inst #1041 = BteqzX16 6787 { 1040, 1, 0, 2, 939, 1, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList7, OperandInfo2 }, // Inst #1040 = Bteqz16 6788 { 1039, 0, 0, 2, 943, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #1039 = Break16 6789 { 1038, 2, 0, 4, 939, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo201 }, // Inst #1038 = BnezRxImmX16 6790 { 1037, 2, 0, 2, 939, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, OperandInfo201 }, // Inst #1037 = BnezRxImm16 6791 { 1036, 1, 0, 4, 939, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo55 }, // Inst #1036 = BimmX16 6792 { 1035, 1, 0, 2, 939, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, OperandInfo55 }, // Inst #1035 = Bimm16 6793 { 1034, 2, 0, 4, 939, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo201 }, // Inst #1034 = BeqzRxImmX16 6794 { 1033, 2, 0, 2, 939, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, OperandInfo201 }, // Inst #1033 = BeqzRxImm16 6795 { 1032, 2, 0, 4, 528, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList2, OperandInfo200 }, // Inst #1032 = BZ_W 6796 { 1031, 2, 0, 4, 528, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList2, OperandInfo197 }, // Inst #1031 = BZ_V 6797 { 1030, 2, 0, 4, 528, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList2, OperandInfo199 }, // Inst #1030 = BZ_H 6798 { 1029, 2, 0, 4, 528, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList2, OperandInfo198 }, // Inst #1029 = BZ_D 6799 { 1028, 2, 0, 4, 528, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList2, OperandInfo197 }, // Inst #1028 = BZ_B 6800 { 1027, 3, 1, 4, 520, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1027 = BSET_W 6801 { 1026, 3, 1, 4, 520, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #1026 = BSET_H 6802 { 1025, 3, 1, 4, 520, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1025 = BSET_D 6803 { 1024, 3, 1, 4, 520, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #1024 = BSET_B 6804 { 1023, 3, 1, 4, 520, 0, 0, 0, 0x6ULL, nullptr, OperandInfo179 }, // Inst #1023 = BSETI_W 6805 { 1022, 3, 1, 4, 520, 0, 0, 0, 0x6ULL, nullptr, OperandInfo178 }, // Inst #1022 = BSETI_H 6806 { 1021, 3, 1, 4, 520, 0, 0, 0, 0x6ULL, nullptr, OperandInfo177 }, // Inst #1021 = BSETI_D 6807 { 1020, 3, 1, 4, 520, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #1020 = BSETI_B 6808 { 1019, 4, 1, 4, 523, 0, 0, 0, 0x6ULL, nullptr, OperandInfo196 }, // Inst #1019 = BSEL_V 6809 { 1018, 4, 1, 4, 523, 0, 0, 0, 0x6ULL, nullptr, OperandInfo192 }, // Inst #1018 = BSELI_B 6810 { 1017, 2, 0, 4, 1007, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo7 }, // Inst #1017 = BREAK_MMR6 6811 { 1016, 2, 0, 4, 966, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo7 }, // Inst #1016 = BREAK_MM 6812 { 1015, 1, 0, 2, 1007, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo2 }, // Inst #1015 = BREAK16_MMR6 6813 { 1014, 1, 0, 2, 966, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo2 }, // Inst #1014 = BREAK16_MM 6814 { 1013, 2, 0, 4, 379, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo7 }, // Inst #1013 = BREAK 6815 { 1012, 1, 0, 4, 1518, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo55 }, // Inst #1012 = BPOSGE32_MM 6816 { 1011, 1, 0, 4, 1670, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo55 }, // Inst #1011 = BPOSGE32C_MMR3 6817 { 1010, 1, 0, 4, 1367, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo55 }, // Inst #1010 = BPOSGE32 6818 { 1009, 3, 0, 4, 985, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList2, OperandInfo57 }, // Inst #1009 = BOVC_MMR6 6819 { 1008, 3, 0, 4, 931, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo57 }, // Inst #1008 = BOVC 6820 { 1007, 2, 0, 4, 528, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList2, OperandInfo200 }, // Inst #1007 = BNZ_W 6821 { 1006, 2, 0, 4, 528, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList2, OperandInfo197 }, // Inst #1006 = BNZ_V 6822 { 1005, 2, 0, 4, 528, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList2, OperandInfo199 }, // Inst #1005 = BNZ_H 6823 { 1004, 2, 0, 4, 528, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList2, OperandInfo198 }, // Inst #1004 = BNZ_D 6824 { 1003, 2, 0, 4, 528, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList2, OperandInfo197 }, // Inst #1003 = BNZ_B 6825 { 1002, 3, 0, 4, 985, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList2, OperandInfo57 }, // Inst #1002 = BNVC_MMR6 6826 { 1001, 3, 0, 4, 931, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo57 }, // Inst #1001 = BNVC 6827 { 1000, 3, 0, 4, 951, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, ImplicitList2, OperandInfo57 }, // Inst #1000 = BNE_MM 6828 { 999, 2, 0, 4, 987, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x36ULL, ImplicitList2, OperandInfo108 }, // Inst #999 = BNEZC_MMR6 6829 { 998, 2, 0, 4, 950, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, ImplicitList2, OperandInfo108 }, // Inst #998 = BNEZC_MM 6830 { 997, 2, 0, 4, 1018, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo109 }, // Inst #997 = BNEZC64 6831 { 996, 2, 0, 2, 986, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, OperandInfo191 }, // Inst #996 = BNEZC16_MMR6 6832 { 995, 2, 0, 4, 932, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo108 }, // Inst #995 = BNEZC 6833 { 994, 2, 0, 4, 1000, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList3, OperandInfo108 }, // Inst #994 = BNEZALC_MMR6 6834 { 993, 2, 0, 4, 927, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList3, OperandInfo108 }, // Inst #993 = BNEZALC 6835 { 992, 2, 0, 2, 949, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, OperandInfo191 }, // Inst #992 = BNEZ16_MM 6836 { 991, 3, 0, 4, 377, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, ImplicitList2, OperandInfo57 }, // Inst #991 = BNEL 6837 { 990, 3, 1, 4, 522, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #990 = BNEG_W 6838 { 989, 3, 1, 4, 522, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #989 = BNEG_H 6839 { 988, 3, 1, 4, 522, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #988 = BNEG_D 6840 { 987, 3, 1, 4, 522, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #987 = BNEG_B 6841 { 986, 3, 1, 4, 522, 0, 0, 0, 0x6ULL, nullptr, OperandInfo179 }, // Inst #986 = BNEGI_W 6842 { 985, 3, 1, 4, 522, 0, 0, 0, 0x6ULL, nullptr, OperandInfo178 }, // Inst #985 = BNEGI_H 6843 { 984, 3, 1, 4, 522, 0, 0, 0, 0x6ULL, nullptr, OperandInfo177 }, // Inst #984 = BNEGI_D 6844 { 983, 3, 1, 4, 522, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #983 = BNEGI_B 6845 { 982, 3, 0, 4, 985, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList2, OperandInfo57 }, // Inst #982 = BNEC_MMR6 6846 { 981, 3, 0, 4, 1017, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo106 }, // Inst #981 = BNEC64 6847 { 980, 3, 0, 4, 931, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo57 }, // Inst #980 = BNEC 6848 { 979, 3, 0, 4, 1009, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, ImplicitList2, OperandInfo106 }, // Inst #979 = BNE64 6849 { 978, 3, 0, 4, 920, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, ImplicitList2, OperandInfo57 }, // Inst #978 = BNE 6850 { 977, 4, 1, 4, 524, 0, 0, 0, 0x6ULL, nullptr, OperandInfo196 }, // Inst #977 = BMZ_V 6851 { 976, 4, 1, 4, 524, 0, 0, 0, 0x6ULL, nullptr, OperandInfo192 }, // Inst #976 = BMZI_B 6852 { 975, 4, 1, 4, 524, 0, 0, 0, 0x6ULL, nullptr, OperandInfo196 }, // Inst #975 = BMNZ_V 6853 { 974, 4, 1, 4, 524, 0, 0, 0, 0x6ULL, nullptr, OperandInfo192 }, // Inst #974 = BMNZI_B 6854 { 973, 2, 0, 4, 949, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, ImplicitList2, OperandInfo108 }, // Inst #973 = BLTZ_MM 6855 { 972, 2, 0, 4, 378, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, ImplicitList2, OperandInfo108 }, // Inst #972 = BLTZL 6856 { 971, 2, 0, 4, 987, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList2, OperandInfo108 }, // Inst #971 = BLTZC_MMR6 6857 { 970, 2, 0, 4, 1018, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo109 }, // Inst #970 = BLTZC64 6858 { 969, 2, 0, 4, 932, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo108 }, // Inst #969 = BLTZC 6859 { 968, 2, 0, 4, 958, 0, 1, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, ImplicitList3, OperandInfo108 }, // Inst #968 = BLTZAL_MM 6860 { 967, 2, 0, 4, 957, 0, 1, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, ImplicitList3, OperandInfo108 }, // Inst #967 = BLTZALS_MM 6861 { 966, 2, 0, 4, 376, 0, 1, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, ImplicitList3, OperandInfo108 }, // Inst #966 = BLTZALL 6862 { 965, 2, 0, 4, 1000, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList3, OperandInfo108 }, // Inst #965 = BLTZALC_MMR6 6863 { 964, 2, 0, 4, 927, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList3, OperandInfo108 }, // Inst #964 = BLTZALC 6864 { 963, 2, 0, 4, 919, 0, 1, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, ImplicitList3, OperandInfo108 }, // Inst #963 = BLTZAL 6865 { 962, 2, 0, 4, 1010, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, ImplicitList2, OperandInfo109 }, // Inst #962 = BLTZ64 6866 { 961, 2, 0, 4, 921, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, ImplicitList2, OperandInfo108 }, // Inst #961 = BLTZ 6867 { 960, 3, 0, 4, 985, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList2, OperandInfo57 }, // Inst #960 = BLTUC_MMR6 6868 { 959, 3, 0, 4, 1017, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo106 }, // Inst #959 = BLTUC64 6869 { 958, 3, 0, 4, 931, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo57 }, // Inst #958 = BLTUC 6870 { 957, 3, 0, 4, 985, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList2, OperandInfo57 }, // Inst #957 = BLTC_MMR6 6871 { 956, 3, 0, 4, 1017, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo106 }, // Inst #956 = BLTC64 6872 { 955, 3, 0, 4, 931, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo57 }, // Inst #955 = BLTC 6873 { 954, 2, 0, 4, 949, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, ImplicitList2, OperandInfo108 }, // Inst #954 = BLEZ_MM 6874 { 953, 2, 0, 4, 378, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, ImplicitList2, OperandInfo108 }, // Inst #953 = BLEZL 6875 { 952, 2, 0, 4, 987, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList2, OperandInfo108 }, // Inst #952 = BLEZC_MMR6 6876 { 951, 2, 0, 4, 1018, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo109 }, // Inst #951 = BLEZC64 6877 { 950, 2, 0, 4, 932, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo108 }, // Inst #950 = BLEZC 6878 { 949, 2, 0, 4, 1000, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList3, OperandInfo108 }, // Inst #949 = BLEZALC_MMR6 6879 { 948, 2, 0, 4, 927, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList3, OperandInfo108 }, // Inst #948 = BLEZALC 6880 { 947, 2, 0, 4, 1010, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, ImplicitList2, OperandInfo109 }, // Inst #947 = BLEZ64 6881 { 946, 2, 0, 4, 921, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, ImplicitList2, OperandInfo108 }, // Inst #946 = BLEZ 6882 { 945, 2, 1, 4, 784, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo45 }, // Inst #945 = BITSWAP_MMR6 6883 { 944, 2, 1, 4, 730, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo45 }, // Inst #944 = BITSWAP 6884 { 943, 2, 1, 4, 1517, 0, 0, 0, 0x6ULL, nullptr, OperandInfo45 }, // Inst #943 = BITREV_MM 6885 { 942, 2, 1, 4, 1366, 0, 0, 0, 0x6ULL, nullptr, OperandInfo45 }, // Inst #942 = BITREV 6886 { 941, 4, 1, 4, 517, 0, 0, 0, 0x6ULL, nullptr, OperandInfo60 }, // Inst #941 = BINSR_W 6887 { 940, 4, 1, 4, 517, 0, 0, 0, 0x6ULL, nullptr, OperandInfo61 }, // Inst #940 = BINSR_H 6888 { 939, 4, 1, 4, 517, 0, 0, 0, 0x6ULL, nullptr, OperandInfo59 }, // Inst #939 = BINSR_D 6889 { 938, 4, 1, 4, 517, 0, 0, 0, 0x6ULL, nullptr, OperandInfo196 }, // Inst #938 = BINSR_B 6890 { 937, 4, 1, 4, 517, 0, 0, 0, 0x6ULL, nullptr, OperandInfo195 }, // Inst #937 = BINSRI_W 6891 { 936, 4, 1, 4, 517, 0, 0, 0, 0x6ULL, nullptr, OperandInfo194 }, // Inst #936 = BINSRI_H 6892 { 935, 4, 1, 4, 517, 0, 0, 0, 0x6ULL, nullptr, OperandInfo193 }, // Inst #935 = BINSRI_D 6893 { 934, 4, 1, 4, 517, 0, 0, 0, 0x6ULL, nullptr, OperandInfo192 }, // Inst #934 = BINSRI_B 6894 { 933, 4, 1, 4, 516, 0, 0, 0, 0x6ULL, nullptr, OperandInfo60 }, // Inst #933 = BINSL_W 6895 { 932, 4, 1, 4, 516, 0, 0, 0, 0x6ULL, nullptr, OperandInfo61 }, // Inst #932 = BINSL_H 6896 { 931, 4, 1, 4, 516, 0, 0, 0, 0x6ULL, nullptr, OperandInfo59 }, // Inst #931 = BINSL_D 6897 { 930, 4, 1, 4, 516, 0, 0, 0, 0x6ULL, nullptr, OperandInfo196 }, // Inst #930 = BINSL_B 6898 { 929, 4, 1, 4, 516, 0, 0, 0, 0x6ULL, nullptr, OperandInfo195 }, // Inst #929 = BINSLI_W 6899 { 928, 4, 1, 4, 516, 0, 0, 0, 0x6ULL, nullptr, OperandInfo194 }, // Inst #928 = BINSLI_H 6900 { 927, 4, 1, 4, 516, 0, 0, 0, 0x6ULL, nullptr, OperandInfo193 }, // Inst #927 = BINSLI_D 6901 { 926, 4, 1, 4, 516, 0, 0, 0, 0x6ULL, nullptr, OperandInfo192 }, // Inst #926 = BINSLI_B 6902 { 925, 2, 0, 4, 949, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, ImplicitList2, OperandInfo108 }, // Inst #925 = BGTZ_MM 6903 { 924, 2, 0, 4, 378, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, ImplicitList2, OperandInfo108 }, // Inst #924 = BGTZL 6904 { 923, 2, 0, 4, 987, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList2, OperandInfo108 }, // Inst #923 = BGTZC_MMR6 6905 { 922, 2, 0, 4, 1018, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo109 }, // Inst #922 = BGTZC64 6906 { 921, 2, 0, 4, 932, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo108 }, // Inst #921 = BGTZC 6907 { 920, 2, 0, 4, 1000, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList3, OperandInfo108 }, // Inst #920 = BGTZALC_MMR6 6908 { 919, 2, 0, 4, 927, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList3, OperandInfo108 }, // Inst #919 = BGTZALC 6909 { 918, 2, 0, 4, 1010, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, ImplicitList2, OperandInfo109 }, // Inst #918 = BGTZ64 6910 { 917, 2, 0, 4, 921, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, ImplicitList2, OperandInfo108 }, // Inst #917 = BGTZ 6911 { 916, 2, 0, 4, 949, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, ImplicitList2, OperandInfo108 }, // Inst #916 = BGEZ_MM 6912 { 915, 2, 0, 4, 378, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, ImplicitList2, OperandInfo108 }, // Inst #915 = BGEZL 6913 { 914, 2, 0, 4, 987, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList2, OperandInfo108 }, // Inst #914 = BGEZC_MMR6 6914 { 913, 2, 0, 4, 1018, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo109 }, // Inst #913 = BGEZC64 6915 { 912, 2, 0, 4, 932, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo108 }, // Inst #912 = BGEZC 6916 { 911, 2, 0, 4, 958, 0, 1, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, ImplicitList3, OperandInfo108 }, // Inst #911 = BGEZAL_MM 6917 { 910, 2, 0, 4, 957, 0, 1, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, ImplicitList3, OperandInfo108 }, // Inst #910 = BGEZALS_MM 6918 { 909, 2, 0, 4, 376, 0, 1, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, ImplicitList3, OperandInfo108 }, // Inst #909 = BGEZALL 6919 { 908, 2, 0, 4, 1000, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList3, OperandInfo108 }, // Inst #908 = BGEZALC_MMR6 6920 { 907, 2, 0, 4, 927, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList3, OperandInfo108 }, // Inst #907 = BGEZALC 6921 { 906, 2, 0, 4, 925, 0, 1, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, ImplicitList3, OperandInfo108 }, // Inst #906 = BGEZAL 6922 { 905, 2, 0, 4, 1010, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, ImplicitList2, OperandInfo109 }, // Inst #905 = BGEZ64 6923 { 904, 2, 0, 4, 921, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, ImplicitList2, OperandInfo108 }, // Inst #904 = BGEZ 6924 { 903, 3, 0, 4, 985, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList2, OperandInfo57 }, // Inst #903 = BGEUC_MMR6 6925 { 902, 3, 0, 4, 1017, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo106 }, // Inst #902 = BGEUC64 6926 { 901, 3, 0, 4, 931, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo57 }, // Inst #901 = BGEUC 6927 { 900, 3, 0, 4, 985, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList2, OperandInfo57 }, // Inst #900 = BGEC_MMR6 6928 { 899, 3, 0, 4, 1017, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo106 }, // Inst #899 = BGEC64 6929 { 898, 3, 0, 4, 931, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo57 }, // Inst #898 = BGEC 6930 { 897, 3, 0, 4, 951, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, ImplicitList2, OperandInfo57 }, // Inst #897 = BEQ_MM 6931 { 896, 2, 0, 4, 987, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x36ULL, ImplicitList2, OperandInfo108 }, // Inst #896 = BEQZC_MMR6 6932 { 895, 2, 0, 4, 950, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, ImplicitList2, OperandInfo108 }, // Inst #895 = BEQZC_MM 6933 { 894, 2, 0, 4, 1018, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo109 }, // Inst #894 = BEQZC64 6934 { 893, 2, 0, 2, 986, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, OperandInfo191 }, // Inst #893 = BEQZC16_MMR6 6935 { 892, 2, 0, 4, 932, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo108 }, // Inst #892 = BEQZC 6936 { 891, 2, 0, 4, 1000, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList3, OperandInfo108 }, // Inst #891 = BEQZALC_MMR6 6937 { 890, 2, 0, 4, 927, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList3, OperandInfo108 }, // Inst #890 = BEQZALC 6938 { 889, 2, 0, 2, 949, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, OperandInfo191 }, // Inst #889 = BEQZ16_MM 6939 { 888, 3, 0, 4, 377, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, ImplicitList2, OperandInfo57 }, // Inst #888 = BEQL 6940 { 887, 3, 0, 4, 985, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList2, OperandInfo57 }, // Inst #887 = BEQC_MMR6 6941 { 886, 3, 0, 4, 1017, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo106 }, // Inst #886 = BEQC64 6942 { 885, 3, 0, 4, 931, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo57 }, // Inst #885 = BEQC 6943 { 884, 3, 0, 4, 1009, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, ImplicitList2, OperandInfo106 }, // Inst #884 = BEQ64 6944 { 883, 3, 0, 4, 920, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, ImplicitList2, OperandInfo57 }, // Inst #883 = BEQ 6945 { 882, 1, 0, 4, 982, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x16ULL, nullptr, OperandInfo55 }, // Inst #882 = BC_MMR6 6946 { 881, 3, 1, 4, 521, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #881 = BCLR_W 6947 { 880, 3, 1, 4, 521, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #880 = BCLR_H 6948 { 879, 3, 1, 4, 521, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #879 = BCLR_D 6949 { 878, 3, 1, 4, 521, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #878 = BCLR_B 6950 { 877, 3, 1, 4, 521, 0, 0, 0, 0x6ULL, nullptr, OperandInfo179 }, // Inst #877 = BCLRI_W 6951 { 876, 3, 1, 4, 521, 0, 0, 0, 0x6ULL, nullptr, OperandInfo178 }, // Inst #876 = BCLRI_H 6952 { 875, 3, 1, 4, 521, 0, 0, 0, 0x6ULL, nullptr, OperandInfo177 }, // Inst #875 = BCLRI_D 6953 { 874, 3, 1, 4, 521, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #874 = BCLRI_B 6954 { 873, 2, 0, 4, 984, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList2, OperandInfo190 }, // Inst #873 = BC2NEZC_MMR6 6955 { 872, 2, 0, 4, 930, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo190 }, // Inst #872 = BC2NEZ 6956 { 871, 2, 0, 4, 984, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList2, OperandInfo190 }, // Inst #871 = BC2EQZC_MMR6 6957 { 870, 2, 0, 4, 930, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo190 }, // Inst #870 = BC2EQZ 6958 { 869, 2, 0, 4, 948, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x45ULL, ImplicitList2, OperandInfo189 }, // Inst #869 = BC1T_MM 6959 { 868, 2, 0, 4, 693, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x45ULL, ImplicitList2, OperandInfo189 }, // Inst #868 = BC1TL 6960 { 867, 2, 0, 4, 692, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x45ULL, ImplicitList2, OperandInfo189 }, // Inst #867 = BC1T 6961 { 866, 2, 0, 4, 983, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, ImplicitList2, OperandInfo188 }, // Inst #866 = BC1NEZC_MMR6 6962 { 865, 2, 0, 4, 1231, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo188 }, // Inst #865 = BC1NEZ 6963 { 864, 2, 0, 4, 947, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x45ULL, ImplicitList2, OperandInfo189 }, // Inst #864 = BC1F_MM 6964 { 863, 2, 0, 4, 691, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x45ULL, ImplicitList2, OperandInfo189 }, // Inst #863 = BC1FL 6965 { 862, 2, 0, 4, 690, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x45ULL, ImplicitList2, OperandInfo189 }, // Inst #862 = BC1F 6966 { 861, 2, 0, 4, 983, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, ImplicitList2, OperandInfo188 }, // Inst #861 = BC1EQZC_MMR6 6967 { 860, 2, 0, 4, 1231, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo188 }, // Inst #860 = BC1EQZ 6968 { 859, 1, 0, 2, 982, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, OperandInfo55 }, // Inst #859 = BC16_MMR6 6969 { 858, 1, 0, 4, 929, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo55 }, // Inst #858 = BC 6970 { 857, 3, 0, 4, 1199, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x2ULL, ImplicitList2, OperandInfo187 }, // Inst #857 = BBIT132 6971 { 856, 3, 0, 4, 1199, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x2ULL, ImplicitList2, OperandInfo187 }, // Inst #856 = BBIT1 6972 { 855, 3, 0, 4, 1199, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x2ULL, ImplicitList2, OperandInfo187 }, // Inst #855 = BBIT032 6973 { 854, 3, 0, 4, 1199, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x2ULL, ImplicitList2, OperandInfo187 }, // Inst #854 = BBIT0 6974 { 853, 4, 1, 4, 1634, 0, 0, 0, 0x6ULL, nullptr, OperandInfo182 }, // Inst #853 = BALIGN_MMR2 6975 { 852, 4, 1, 4, 1470, 0, 0, 0, 0x6ULL, nullptr, OperandInfo182 }, // Inst #852 = BALIGN 6976 { 851, 1, 0, 4, 999, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList3, OperandInfo55 }, // Inst #851 = BALC_MMR6 6977 { 850, 1, 0, 4, 926, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList3, OperandInfo55 }, // Inst #850 = BALC 6978 { 849, 1, 0, 4, 375, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList3, OperandInfo55 }, // Inst #849 = BAL 6979 { 848, 3, 1, 4, 1198, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, OperandInfo71 }, // Inst #848 = BADDu 6980 { 847, 1, 0, 2, 945, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, OperandInfo55 }, // Inst #847 = B16_MM 6981 { 846, 3, 1, 2, 735, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, OperandInfo186 }, // Inst #846 = AndRxRxRy16 6982 { 845, 3, 1, 2, 735, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, OperandInfo131 }, // Inst #845 = AdduRxRyRz16 6983 { 844, 1, 0, 4, 735, 1, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, OperandInfo2 }, // Inst #844 = AddiuSpImmX16 6984 { 843, 1, 0, 2, 735, 1, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, OperandInfo2 }, // Inst #843 = AddiuSpImm16 6985 { 842, 3, 1, 4, 735, 0, 0, 0, 0x0ULL, nullptr, OperandInfo185 }, // Inst #842 = AddiuRxRyOffMemX16 6986 { 841, 3, 1, 4, 735, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, OperandInfo184 }, // Inst #841 = AddiuRxRxImmX16 6987 { 840, 3, 1, 2, 735, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, OperandInfo184 }, // Inst #840 = AddiuRxRxImm16 6988 { 839, 2, 1, 4, 735, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo183 }, // Inst #839 = AddiuRxPcImmX16 6989 { 838, 2, 1, 4, 735, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo183 }, // Inst #838 = AddiuRxImmX16 6990 { 837, 3, 1, 4, 542, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo48 }, // Inst #837 = AVE_U_W 6991 { 836, 3, 1, 4, 542, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo47 }, // Inst #836 = AVE_U_H 6992 { 835, 3, 1, 4, 542, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo46 }, // Inst #835 = AVE_U_D 6993 { 834, 3, 1, 4, 542, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo174 }, // Inst #834 = AVE_U_B 6994 { 833, 3, 1, 4, 542, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo48 }, // Inst #833 = AVE_S_W 6995 { 832, 3, 1, 4, 542, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo47 }, // Inst #832 = AVE_S_H 6996 { 831, 3, 1, 4, 542, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo46 }, // Inst #831 = AVE_S_D 6997 { 830, 3, 1, 4, 542, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo174 }, // Inst #830 = AVE_S_B 6998 { 829, 3, 1, 4, 542, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo48 }, // Inst #829 = AVER_U_W 6999 { 828, 3, 1, 4, 542, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo47 }, // Inst #828 = AVER_U_H 7000 { 827, 3, 1, 4, 542, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo46 }, // Inst #827 = AVER_U_D 7001 { 826, 3, 1, 4, 542, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo174 }, // Inst #826 = AVER_U_B 7002 { 825, 3, 1, 4, 542, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo48 }, // Inst #825 = AVER_S_W 7003 { 824, 3, 1, 4, 542, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo47 }, // Inst #824 = AVER_S_H 7004 { 823, 3, 1, 4, 542, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo46 }, // Inst #823 = AVER_S_D 7005 { 822, 3, 1, 4, 542, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo174 }, // Inst #822 = AVER_S_B 7006 { 821, 3, 1, 4, 783, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo73 }, // Inst #821 = AUI_MMR6 7007 { 820, 2, 1, 4, 782, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo114 }, // Inst #820 = AUIPC_MMR6 7008 { 819, 2, 1, 4, 729, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo114 }, // Inst #819 = AUIPC 7009 { 818, 3, 1, 4, 728, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo73 }, // Inst #818 = AUI 7010 { 817, 3, 1, 4, 541, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #817 = ASUB_U_W 7011 { 816, 3, 1, 4, 541, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #816 = ASUB_U_H 7012 { 815, 3, 1, 4, 541, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #815 = ASUB_U_D 7013 { 814, 3, 1, 4, 541, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #814 = ASUB_U_B 7014 { 813, 3, 1, 4, 541, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #813 = ASUB_S_W 7015 { 812, 3, 1, 4, 541, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #812 = ASUB_S_H 7016 { 811, 3, 1, 4, 541, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #811 = ASUB_S_D 7017 { 810, 3, 1, 4, 541, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #810 = ASUB_S_B 7018 { 809, 4, 1, 4, 1633, 0, 0, 0, 0x6ULL, nullptr, OperandInfo182 }, // Inst #809 = APPEND_MMR2 7019 { 808, 4, 1, 4, 1469, 0, 0, 0, 0x6ULL, nullptr, OperandInfo182 }, // Inst #808 = APPEND 7020 { 807, 3, 1, 4, 743, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, OperandInfo73 }, // Inst #807 = ANDi_MM 7021 { 806, 3, 1, 4, 806, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, OperandInfo70 }, // Inst #806 = ANDi64 7022 { 805, 3, 1, 4, 499, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, OperandInfo73 }, // Inst #805 = ANDi 7023 { 804, 3, 1, 4, 548, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #804 = AND_V 7024 { 803, 3, 1, 4, 780, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, OperandInfo72 }, // Inst #803 = AND_MMR6 7025 { 802, 3, 1, 4, 742, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, OperandInfo72 }, // Inst #802 = AND_MM 7026 { 801, 3, 1, 4, 781, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, OperandInfo73 }, // Inst #801 = ANDI_MMR6 7027 { 800, 3, 1, 4, 549, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #800 = ANDI_B 7028 { 799, 3, 1, 2, 780, 0, 0, 0, 0x0ULL, nullptr, OperandInfo170 }, // Inst #799 = ANDI16_MMR6 7029 { 798, 3, 1, 2, 742, 0, 0, 0, 0x0ULL, nullptr, OperandInfo170 }, // Inst #798 = ANDI16_MM 7030 { 797, 3, 1, 4, 806, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, OperandInfo71 }, // Inst #797 = AND64 7031 { 796, 3, 1, 2, 780, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo181 }, // Inst #796 = AND16_MMR6 7032 { 795, 3, 1, 2, 742, 0, 0, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo181 }, // Inst #795 = AND16_MM 7033 { 794, 3, 1, 4, 364, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, OperandInfo72 }, // Inst #794 = AND 7034 { 793, 2, 1, 4, 779, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo114 }, // Inst #793 = ALUIPC_MMR6 7035 { 792, 2, 1, 4, 727, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo114 }, // Inst #792 = ALUIPC 7036 { 791, 4, 1, 4, 778, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo180 }, // Inst #791 = ALIGN_MMR6 7037 { 790, 4, 1, 4, 726, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo180 }, // Inst #790 = ALIGN 7038 { 789, 3, 1, 4, 739, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, OperandInfo72 }, // Inst #789 = ADDu_MM 7039 { 788, 3, 1, 4, 509, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, OperandInfo72 }, // Inst #788 = ADDu 7040 { 787, 3, 1, 4, 738, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, OperandInfo73 }, // Inst #787 = ADDiu_MM 7041 { 786, 3, 1, 4, 498, 0, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL, nullptr, OperandInfo73 }, // Inst #786 = ADDiu 7042 { 785, 3, 1, 4, 741, 0, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo73 }, // Inst #785 = ADDi_MM 7043 { 784, 3, 1, 4, 497, 0, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo73 }, // Inst #784 = ADDi 7044 { 783, 3, 1, 4, 777, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo72 }, // Inst #783 = ADD_MMR6 7045 { 782, 3, 1, 4, 740, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo72 }, // Inst #782 = ADD_MM 7046 { 781, 3, 1, 4, 538, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo48 }, // Inst #781 = ADD_A_W 7047 { 780, 3, 1, 4, 538, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo47 }, // Inst #780 = ADD_A_H 7048 { 779, 3, 1, 4, 538, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo46 }, // Inst #779 = ADD_A_D 7049 { 778, 3, 1, 4, 538, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo174 }, // Inst #778 = ADD_A_B 7050 { 777, 3, 1, 4, 1516, 1, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList10, OperandInfo72 }, // Inst #777 = ADDWC_MM 7051 { 776, 3, 1, 4, 1365, 1, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList10, OperandInfo72 }, // Inst #776 = ADDWC 7052 { 775, 3, 1, 4, 540, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo48 }, // Inst #775 = ADDV_W 7053 { 774, 3, 1, 4, 540, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo47 }, // Inst #774 = ADDV_H 7054 { 773, 3, 1, 4, 540, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo46 }, // Inst #773 = ADDV_D 7055 { 772, 3, 1, 4, 540, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo174 }, // Inst #772 = ADDV_B 7056 { 771, 3, 1, 4, 540, 0, 0, 0, 0x6ULL, nullptr, OperandInfo179 }, // Inst #771 = ADDVI_W 7057 { 770, 3, 1, 4, 540, 0, 0, 0, 0x6ULL, nullptr, OperandInfo178 }, // Inst #770 = ADDVI_H 7058 { 769, 3, 1, 4, 540, 0, 0, 0, 0x6ULL, nullptr, OperandInfo177 }, // Inst #769 = ADDVI_D 7059 { 768, 3, 1, 4, 540, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #768 = ADDVI_B 7060 { 767, 3, 1, 4, 1515, 0, 1, 0|(1ULL<<MCID::Commutable), 0x6ULL, ImplicitList8, OperandInfo172 }, // Inst #767 = ADDU_S_QB_MM 7061 { 766, 3, 1, 4, 1364, 0, 1, 0|(1ULL<<MCID::Commutable), 0x6ULL, ImplicitList8, OperandInfo172 }, // Inst #766 = ADDU_S_QB 7062 { 765, 3, 1, 4, 1632, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList8, OperandInfo172 }, // Inst #765 = ADDU_S_PH_MMR2 7063 { 764, 3, 1, 4, 1468, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList8, OperandInfo172 }, // Inst #764 = ADDU_S_PH 7064 { 763, 3, 1, 4, 1514, 0, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList8, OperandInfo172 }, // Inst #763 = ADDU_QB_MM 7065 { 762, 3, 1, 4, 1363, 0, 1, 0|(1ULL<<MCID::Commutable), 0x6ULL, ImplicitList8, OperandInfo172 }, // Inst #762 = ADDU_QB 7066 { 761, 3, 1, 4, 1631, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList8, OperandInfo172 }, // Inst #761 = ADDU_PH_MMR2 7067 { 760, 3, 1, 4, 1467, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList8, OperandInfo172 }, // Inst #760 = ADDU_PH 7068 { 759, 3, 1, 4, 776, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo72 }, // Inst #759 = ADDU_MMR6 7069 { 758, 3, 1, 4, 1630, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo172 }, // Inst #758 = ADDUH_R_QB_MMR2 7070 { 757, 3, 1, 4, 1466, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo172 }, // Inst #757 = ADDUH_R_QB 7071 { 756, 3, 1, 4, 1629, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo172 }, // Inst #756 = ADDUH_QB_MMR2 7072 { 755, 3, 1, 4, 1465, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo172 }, // Inst #755 = ADDUH_QB 7073 { 754, 3, 1, 2, 776, 0, 0, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo175 }, // Inst #754 = ADDU16_MMR6 7074 { 753, 3, 1, 2, 739, 0, 0, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo175 }, // Inst #753 = ADDU16_MM 7075 { 752, 3, 1, 4, 539, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo48 }, // Inst #752 = ADDS_U_W 7076 { 751, 3, 1, 4, 539, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo47 }, // Inst #751 = ADDS_U_H 7077 { 750, 3, 1, 4, 539, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo46 }, // Inst #750 = ADDS_U_D 7078 { 749, 3, 1, 4, 539, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo174 }, // Inst #749 = ADDS_U_B 7079 { 748, 3, 1, 4, 539, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo48 }, // Inst #748 = ADDS_S_W 7080 { 747, 3, 1, 4, 539, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo47 }, // Inst #747 = ADDS_S_H 7081 { 746, 3, 1, 4, 539, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo46 }, // Inst #746 = ADDS_S_D 7082 { 745, 3, 1, 4, 539, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo174 }, // Inst #745 = ADDS_S_B 7083 { 744, 3, 1, 4, 539, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo48 }, // Inst #744 = ADDS_A_W 7084 { 743, 3, 1, 4, 539, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo47 }, // Inst #743 = ADDS_A_H 7085 { 742, 3, 1, 4, 539, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo46 }, // Inst #742 = ADDS_A_D 7086 { 741, 3, 1, 4, 539, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo174 }, // Inst #741 = ADDS_A_B 7087 { 740, 3, 1, 4, 1513, 0, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList9, OperandInfo72 }, // Inst #740 = ADDSC_MM 7088 { 739, 3, 1, 4, 1362, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList9, OperandInfo72 }, // Inst #739 = ADDSC 7089 { 738, 3, 1, 4, 1211, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo173 }, // Inst #738 = ADDR_PS64 7090 { 737, 3, 1, 4, 1512, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList8, OperandInfo72 }, // Inst #737 = ADDQ_S_W_MM 7091 { 736, 3, 1, 4, 1361, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList8, OperandInfo72 }, // Inst #736 = ADDQ_S_W 7092 { 735, 3, 1, 4, 1511, 0, 1, 0|(1ULL<<MCID::Commutable), 0x6ULL, ImplicitList8, OperandInfo172 }, // Inst #735 = ADDQ_S_PH_MM 7093 { 734, 3, 1, 4, 1360, 0, 1, 0|(1ULL<<MCID::Commutable), 0x6ULL, ImplicitList8, OperandInfo172 }, // Inst #734 = ADDQ_S_PH 7094 { 733, 3, 1, 4, 1510, 0, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList8, OperandInfo172 }, // Inst #733 = ADDQ_PH_MM 7095 { 732, 3, 1, 4, 1359, 0, 1, 0|(1ULL<<MCID::Commutable), 0x6ULL, ImplicitList8, OperandInfo172 }, // Inst #732 = ADDQ_PH 7096 { 731, 3, 1, 4, 1628, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo72 }, // Inst #731 = ADDQH_W_MMR2 7097 { 730, 3, 1, 4, 1464, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo72 }, // Inst #730 = ADDQH_W 7098 { 729, 3, 1, 4, 1627, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo72 }, // Inst #729 = ADDQH_R_W_MMR2 7099 { 728, 3, 1, 4, 1463, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo72 }, // Inst #728 = ADDQH_R_W 7100 { 727, 3, 1, 4, 1626, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo172 }, // Inst #727 = ADDQH_R_PH_MMR2 7101 { 726, 3, 1, 4, 1462, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo172 }, // Inst #726 = ADDQH_R_PH 7102 { 725, 3, 1, 4, 1625, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo172 }, // Inst #725 = ADDQH_PH_MMR2 7103 { 724, 3, 1, 4, 1461, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo172 }, // Inst #724 = ADDQH_PH 7104 { 723, 3, 1, 4, 775, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, OperandInfo73 }, // Inst #723 = ADDIU_MMR6 7105 { 722, 1, 0, 2, 738, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo2 }, // Inst #722 = ADDIUSP_MM 7106 { 721, 3, 1, 2, 738, 0, 0, 0, 0x0ULL, nullptr, OperandInfo171 }, // Inst #721 = ADDIUS5_MM 7107 { 720, 3, 1, 2, 738, 0, 0, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo170 }, // Inst #720 = ADDIUR2_MM 7108 { 719, 2, 1, 2, 738, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo169 }, // Inst #719 = ADDIUR1SP_MM 7109 { 718, 2, 1, 4, 774, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo114 }, // Inst #718 = ADDIUPC_MMR6 7110 { 717, 2, 1, 4, 738, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo169 }, // Inst #717 = ADDIUPC_MM 7111 { 716, 2, 1, 4, 725, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo114 }, // Inst #716 = ADDIUPC 7112 { 715, 3, 1, 4, 496, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo72 }, // Inst #715 = ADD 7113 { 714, 2, 1, 4, 1509, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList8, OperandInfo45 }, // Inst #714 = ABSQ_S_W_MM 7114 { 713, 2, 1, 4, 1358, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList8, OperandInfo45 }, // Inst #713 = ABSQ_S_W 7115 { 712, 2, 1, 4, 1624, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList8, OperandInfo168 }, // Inst #712 = ABSQ_S_QB_MMR2 7116 { 711, 2, 1, 4, 1460, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList8, OperandInfo168 }, // Inst #711 = ABSQ_S_QB 7117 { 710, 2, 1, 4, 1508, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList8, OperandInfo168 }, // Inst #710 = ABSQ_S_PH_MM 7118 { 709, 2, 1, 4, 1357, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList8, OperandInfo168 }, // Inst #709 = ABSQ_S_PH 7119 { 708, 3, 1, 4, 550, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo48 }, // Inst #708 = XOR_V_W_PSEUDO 7120 { 707, 3, 1, 4, 550, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo47 }, // Inst #707 = XOR_V_H_PSEUDO 7121 { 706, 3, 1, 4, 550, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo46 }, // Inst #706 = XOR_V_D_PSEUDO 7122 { 705, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo96 }, // Inst #705 = Usw 7123 { 704, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo96 }, // Inst #704 = Ush 7124 { 703, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo96 }, // Inst #703 = Ulw 7125 { 702, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo96 }, // Inst #702 = Ulhu 7126 { 701, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo96 }, // Inst #701 = Ulh 7127 { 700, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo72 }, // Inst #700 = URemMacro 7128 { 699, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo73 }, // Inst #699 = URemIMacro 7129 { 698, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo72 }, // Inst #698 = UDivMacro 7130 { 697, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo73 }, // Inst #697 = UDivIMacro 7131 { 696, 3, 1, 4, 886, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo142 }, // Inst #696 = UDIV_MM_Pseudo 7132 { 695, 0, 0, 4, 981, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Trap)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #695 = TRAP_MM 7133 { 694, 0, 0, 4, 402, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Trap)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #694 = TRAP 7134 { 693, 1, 0, 4, 1006, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, ImplicitList2, OperandInfo2 }, // Inst #693 = TAILCALL_MMR6 7135 { 692, 1, 0, 4, 964, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, ImplicitList2, OperandInfo2 }, // Inst #692 = TAILCALL_MM 7136 { 691, 1, 0, 4, 1005, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, ImplicitList2, OperandInfo58 }, // Inst #691 = TAILCALLREG_MMR6 7137 { 690, 1, 0, 4, 963, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, ImplicitList2, OperandInfo58 }, // Inst #690 = TAILCALLREG_MM 7138 { 689, 1, 0, 4, 1015, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, ImplicitList2, OperandInfo95 }, // Inst #689 = TAILCALLREGHB64 7139 { 688, 1, 0, 4, 385, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, ImplicitList2, OperandInfo58 }, // Inst #688 = TAILCALLREGHB 7140 { 687, 1, 0, 4, 1015, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, ImplicitList2, OperandInfo95 }, // Inst #687 = TAILCALLREG64 7141 { 686, 1, 0, 4, 385, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, ImplicitList2, OperandInfo58 }, // Inst #686 = TAILCALLREG 7142 { 685, 1, 0, 4, 937, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, ImplicitList2, OperandInfo58 }, // Inst #685 = TAILCALLR6REG 7143 { 684, 1, 0, 4, 937, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, ImplicitList2, OperandInfo58 }, // Inst #684 = TAILCALLHBR6REG 7144 { 683, 1, 0, 4, 1023, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, ImplicitList2, OperandInfo95 }, // Inst #683 = TAILCALLHB64R6REG 7145 { 682, 1, 0, 4, 1023, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, ImplicitList2, OperandInfo95 }, // Inst #682 = TAILCALL64R6REG 7146 { 681, 1, 0, 4, 384, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, ImplicitList2, OperandInfo2 }, // Inst #681 = TAILCALL 7147 { 680, 3, 1, 2, 736, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList7, OperandInfo131 }, // Inst #680 = SltuRxRyRz16 7148 { 679, 3, 1, 2, 736, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo131 }, // Inst #679 = SltuCCRxRy16 7149 { 678, 3, 1, 2, 736, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo167 }, // Inst #678 = SltiuCCRxImmX16 7150 { 677, 3, 1, 2, 736, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo167 }, // Inst #677 = SltiCCRxImmX16 7151 { 676, 3, 1, 2, 736, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo131 }, // Inst #676 = SltCCRxRy16 7152 { 675, 5, 1, 2, 944, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo165 }, // Inst #675 = SelTBtneZSltu 7153 { 674, 5, 1, 2, 944, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo166 }, // Inst #674 = SelTBtneZSltiu 7154 { 673, 5, 1, 2, 944, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo166 }, // Inst #673 = SelTBtneZSlti 7155 { 672, 5, 1, 2, 944, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo165 }, // Inst #672 = SelTBtneZSlt 7156 { 671, 5, 1, 2, 944, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo166 }, // Inst #671 = SelTBtneZCmpi 7157 { 670, 5, 1, 2, 944, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo165 }, // Inst #670 = SelTBtneZCmp 7158 { 669, 5, 1, 2, 944, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo165 }, // Inst #669 = SelTBteqZSltu 7159 { 668, 5, 1, 2, 944, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo166 }, // Inst #668 = SelTBteqZSltiu 7160 { 667, 5, 1, 2, 944, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo166 }, // Inst #667 = SelTBteqZSlti 7161 { 666, 5, 1, 2, 944, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo165 }, // Inst #666 = SelTBteqZSlt 7162 { 665, 5, 1, 2, 944, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo166 }, // Inst #665 = SelTBteqZCmpi 7163 { 664, 5, 1, 2, 944, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo165 }, // Inst #664 = SelTBteqZCmp 7164 { 663, 4, 1, 2, 944, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo164 }, // Inst #663 = SelBneZ 7165 { 662, 4, 1, 2, 944, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo164 }, // Inst #662 = SelBeqZ 7166 { 661, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo113 }, // Inst #661 = SaadAddr 7167 { 660, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo113 }, // Inst #660 = SaaAddr 7168 { 659, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo163 }, // Inst #659 = SZ_W_PSEUDO 7169 { 658, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo160 }, // Inst #658 = SZ_V_PSEUDO 7170 { 657, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo162 }, // Inst #657 = SZ_H_PSEUDO 7171 { 656, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo161 }, // Inst #656 = SZ_D_PSEUDO 7172 { 655, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo160 }, // Inst #655 = SZ_B_PSEUDO 7173 { 654, 3, 0, 4, 1136, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo110 }, // Inst #654 = SWM_MM 7174 { 653, 3, 0, 4, 705, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo99 }, // Inst #653 = ST_F16 7175 { 652, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo98 }, // Inst #652 = STR_W 7176 { 651, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo97 }, // Inst #651 = STR_D 7177 { 650, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo103 }, // Inst #650 = STORE_CCOND_DSP 7178 { 649, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo102 }, // Inst #649 = STORE_ACC64DSP 7179 { 648, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo101 }, // Inst #648 = STORE_ACC64 7180 { 647, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo100 }, // Inst #647 = STORE_ACC128 7181 { 646, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo72 }, // Inst #646 = SRemMacro 7182 { 645, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo73 }, // Inst #645 = SRemIMacro 7183 { 644, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo163 }, // Inst #644 = SNZ_W_PSEUDO 7184 { 643, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo160 }, // Inst #643 = SNZ_V_PSEUDO 7185 { 642, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo162 }, // Inst #642 = SNZ_H_PSEUDO 7186 { 641, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo161 }, // Inst #641 = SNZ_D_PSEUDO 7187 { 640, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo160 }, // Inst #640 = SNZ_B_PSEUDO 7188 { 639, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo72 }, // Inst #639 = SNEMacro 7189 { 638, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo73 }, // Inst #638 = SNEIMacro 7190 { 637, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo70 }, // Inst #637 = SLTUImm64 7191 { 636, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo70 }, // Inst #636 = SLTImm64 7192 { 635, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo70 }, // Inst #635 = SLEUImm64 7193 { 634, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo73 }, // Inst #634 = SLEUImm 7194 { 633, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo72 }, // Inst #633 = SLEU 7195 { 632, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo70 }, // Inst #632 = SLEImm64 7196 { 631, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo73 }, // Inst #631 = SLEImm 7197 { 630, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo72 }, // Inst #630 = SLE 7198 { 629, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo70 }, // Inst #629 = SGTUImm64 7199 { 628, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo73 }, // Inst #628 = SGTUImm 7200 { 627, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo70 }, // Inst #627 = SGTImm64 7201 { 626, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo73 }, // Inst #626 = SGTImm 7202 { 625, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo70 }, // Inst #625 = SGEUImm64 7203 { 624, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo73 }, // Inst #624 = SGEUImm 7204 { 623, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo72 }, // Inst #623 = SGEU 7205 { 622, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo70 }, // Inst #622 = SGEImm64 7206 { 621, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo73 }, // Inst #621 = SGEImm 7207 { 620, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo72 }, // Inst #620 = SGE 7208 { 619, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo72 }, // Inst #619 = SEQMacro 7209 { 618, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo73 }, // Inst #618 = SEQIMacro 7210 { 617, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo159 }, // Inst #617 = SDivMacro 7211 { 616, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo73 }, // Inst #616 = SDivIMacro 7212 { 615, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo96 }, // Inst #615 = SDMacro 7213 { 614, 3, 1, 4, 885, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo142 }, // Inst #614 = SDIV_MM_Pseudo 7214 { 613, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo158 }, // Inst #613 = SDC1_M1 7215 { 612, 0, 0, 2, 940, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x0ULL, nullptr, nullptr }, // Inst #612 = RetRA16 7216 { 611, 0, 0, 4, 382, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr }, // Inst #611 = RetRA 7217 { 610, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo73 }, // Inst #610 = RORImm 7218 { 609, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo72 }, // Inst #609 = ROR 7219 { 608, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo73 }, // Inst #608 = ROLImm 7220 { 607, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo72 }, // Inst #607 = ROL 7221 { 606, 3, 1, 4, 866, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo142 }, // Inst #606 = PseudoUDIV 7222 { 605, 3, 1, 4, 1214, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo157 }, // Inst #605 = PseudoTRUNC_W_S 7223 { 604, 3, 1, 4, 1214, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo156 }, // Inst #604 = PseudoTRUNC_W_D32 7224 { 603, 3, 1, 4, 1214, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo155 }, // Inst #603 = PseudoTRUNC_W_D 7225 { 602, 4, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo154 }, // Inst #602 = PseudoSELECT_S 7226 { 601, 4, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo153 }, // Inst #601 = PseudoSELECT_I64 7227 { 600, 4, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo152 }, // Inst #600 = PseudoSELECT_I 7228 { 599, 4, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo151 }, // Inst #599 = PseudoSELECT_D64 7229 { 598, 4, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo150 }, // Inst #598 = PseudoSELECT_D32 7230 { 597, 4, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo149 }, // Inst #597 = PseudoSELECTFP_T_S 7231 { 596, 4, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo148 }, // Inst #596 = PseudoSELECTFP_T_I64 7232 { 595, 4, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo147 }, // Inst #595 = PseudoSELECTFP_T_I 7233 { 594, 4, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo146 }, // Inst #594 = PseudoSELECTFP_T_D64 7234 { 593, 4, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo145 }, // Inst #593 = PseudoSELECTFP_T_D32 7235 { 592, 4, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo149 }, // Inst #592 = PseudoSELECTFP_F_S 7236 { 591, 4, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo148 }, // Inst #591 = PseudoSELECTFP_F_I64 7237 { 590, 4, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo147 }, // Inst #590 = PseudoSELECTFP_F_I 7238 { 589, 4, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo146 }, // Inst #589 = PseudoSELECTFP_F_D64 7239 { 588, 4, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo145 }, // Inst #588 = PseudoSELECTFP_F_D32 7240 { 587, 3, 1, 4, 865, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo142 }, // Inst #587 = PseudoSDIV 7241 { 586, 1, 0, 4, 1016, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, OperandInfo95 }, // Inst #586 = PseudoReturn64 7242 { 585, 1, 0, 4, 388, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, OperandInfo58 }, // Inst #585 = PseudoReturn 7243 { 584, 4, 1, 4, 1459, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo144 }, // Inst #584 = PseudoPICK_QB 7244 { 583, 4, 1, 4, 1459, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo144 }, // Inst #583 = PseudoPICK_PH 7245 { 582, 3, 1, 4, 862, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo142 }, // Inst #582 = PseudoMULTu_MM 7246 { 581, 3, 1, 4, 864, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo142 }, // Inst #581 = PseudoMULTu 7247 { 580, 3, 1, 4, 861, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo142 }, // Inst #580 = PseudoMULT_MM 7248 { 579, 3, 1, 4, 863, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo142 }, // Inst #579 = PseudoMULT 7249 { 578, 3, 1, 4, 868, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo142 }, // Inst #578 = PseudoMTLOHI_MM 7250 { 577, 3, 1, 4, 1344, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo143 }, // Inst #577 = PseudoMTLOHI_DSP 7251 { 576, 3, 1, 4, 907, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo136 }, // Inst #576 = PseudoMTLOHI64 7252 { 575, 3, 1, 4, 493, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo142 }, // Inst #575 = PseudoMTLOHI 7253 { 574, 4, 1, 4, 859, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo139 }, // Inst #574 = PseudoMSUB_MM 7254 { 573, 4, 1, 4, 860, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo139 }, // Inst #573 = PseudoMSUBU_MM 7255 { 572, 4, 1, 4, 492, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo139 }, // Inst #572 = PseudoMSUBU 7256 { 571, 4, 1, 4, 491, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo139 }, // Inst #571 = PseudoMSUB 7257 { 570, 2, 1, 4, 867, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo140 }, // Inst #570 = PseudoMFLO_MM 7258 { 569, 2, 1, 4, 906, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo141 }, // Inst #569 = PseudoMFLO64 7259 { 568, 2, 1, 4, 478, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo140 }, // Inst #568 = PseudoMFLO 7260 { 567, 2, 1, 4, 867, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo140 }, // Inst #567 = PseudoMFHI_MM 7261 { 566, 2, 1, 4, 906, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo141 }, // Inst #566 = PseudoMFHI64 7262 { 565, 2, 1, 4, 478, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo140 }, // Inst #565 = PseudoMFHI 7263 { 564, 4, 1, 4, 857, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo139 }, // Inst #564 = PseudoMADD_MM 7264 { 563, 4, 1, 4, 858, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo139 }, // Inst #563 = PseudoMADDU_MM 7265 { 562, 4, 1, 4, 490, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo139 }, // Inst #562 = PseudoMADDU 7266 { 561, 4, 1, 4, 489, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo139 }, // Inst #561 = PseudoMADD 7267 { 560, 1, 0, 4, 936, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, OperandInfo58 }, // Inst #560 = PseudoIndrectHazardBranchR6 7268 { 559, 1, 0, 4, 1024, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, OperandInfo95 }, // Inst #559 = PseudoIndrectHazardBranch64R6 7269 { 558, 1, 0, 4, 1020, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, OperandInfo95 }, // Inst #558 = PseudoIndirectHazardBranch64 7270 { 557, 1, 0, 4, 387, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, OperandInfo58 }, // Inst #557 = PseudoIndirectHazardBranch 7271 { 556, 1, 0, 4, 998, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, OperandInfo58 }, // Inst #556 = PseudoIndirectBranch_MMR6 7272 { 555, 1, 0, 4, 965, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, OperandInfo58 }, // Inst #555 = PseudoIndirectBranch_MM 7273 { 554, 1, 0, 4, 936, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, OperandInfo58 }, // Inst #554 = PseudoIndirectBranchR6 7274 { 553, 1, 0, 4, 1024, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, OperandInfo95 }, // Inst #553 = PseudoIndirectBranch64R6 7275 { 552, 1, 0, 4, 1020, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, OperandInfo95 }, // Inst #552 = PseudoIndirectBranch64 7276 { 551, 1, 0, 4, 387, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, OperandInfo58 }, // Inst #551 = PseudoIndirectBranch 7277 { 550, 7, 2, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo138 }, // Inst #550 = PseudoD_SELECT_I64 7278 { 549, 7, 2, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo137 }, // Inst #549 = PseudoD_SELECT_I 7279 { 548, 3, 1, 4, 905, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo136 }, // Inst #548 = PseudoDUDIV 7280 { 547, 3, 1, 4, 904, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo136 }, // Inst #547 = PseudoDSDIV 7281 { 546, 3, 1, 4, 903, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo136 }, // Inst #546 = PseudoDMULTu 7282 { 545, 3, 1, 4, 902, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo136 }, // Inst #545 = PseudoDMULT 7283 { 544, 2, 1, 4, 644, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x4ULL, nullptr, OperandInfo129 }, // Inst #544 = PseudoCVT_S_W 7284 { 543, 2, 1, 4, 644, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x4ULL, nullptr, OperandInfo134 }, // Inst #543 = PseudoCVT_S_L 7285 { 542, 2, 1, 4, 644, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x4ULL, nullptr, OperandInfo135 }, // Inst #542 = PseudoCVT_D64_W 7286 { 541, 2, 1, 4, 644, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x4ULL, nullptr, OperandInfo134 }, // Inst #541 = PseudoCVT_D64_L 7287 { 540, 2, 1, 4, 644, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x4ULL, nullptr, OperandInfo133 }, // Inst #540 = PseudoCVT_D32_W 7288 { 539, 3, 1, 4, 1458, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo132 }, // Inst #539 = PseudoCMP_LT_PH 7289 { 538, 3, 1, 4, 1458, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo132 }, // Inst #538 = PseudoCMP_LE_PH 7290 { 537, 3, 1, 4, 1458, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo132 }, // Inst #537 = PseudoCMP_EQ_PH 7291 { 536, 3, 1, 4, 1458, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo132 }, // Inst #536 = PseudoCMPU_LT_QB 7292 { 535, 3, 1, 4, 1458, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo132 }, // Inst #535 = PseudoCMPU_LE_QB 7293 { 534, 3, 1, 4, 1458, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo132 }, // Inst #534 = PseudoCMPU_EQ_QB 7294 { 533, 3, 1, 4, 550, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo48 }, // Inst #533 = OR_V_W_PSEUDO 7295 { 532, 3, 1, 4, 550, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo47 }, // Inst #532 = OR_V_H_PSEUDO 7296 { 531, 3, 1, 4, 550, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo46 }, // Inst #531 = OR_V_D_PSEUDO 7297 { 530, 3, 1, 4, 550, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo48 }, // Inst #530 = NOR_V_W_PSEUDO 7298 { 529, 3, 1, 4, 550, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo47 }, // Inst #529 = NOR_V_H_PSEUDO 7299 { 528, 3, 1, 4, 550, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo46 }, // Inst #528 = NOR_V_D_PSEUDO 7300 { 527, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo70 }, // Inst #527 = NORImm64 7301 { 526, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo73 }, // Inst #526 = NORImm 7302 { 525, 0, 0, 4, 373, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #525 = NOP 7303 { 524, 3, 1, 2, 875, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList6, OperandInfo131 }, // Inst #524 = MultuRxRyRz16 7304 { 523, 2, 0, 2, 875, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList6, OperandInfo130 }, // Inst #523 = MultuRxRy16 7305 { 522, 3, 1, 2, 875, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList6, OperandInfo131 }, // Inst #522 = MultRxRyRz16 7306 { 521, 2, 0, 2, 875, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList6, OperandInfo130 }, // Inst #521 = MultRxRy16 7307 { 520, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo72 }, // Inst #520 = MULOUMacro 7308 { 519, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo72 }, // Inst #519 = MULOMacro 7309 { 518, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo73 }, // Inst #518 = MULImmMacro 7310 { 517, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo127 }, // Inst #517 = MTTLO 7311 { 516, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo127 }, // Inst #516 = MTTHI 7312 { 515, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo129 }, // Inst #515 = MTTHC1 7313 { 514, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo45 }, // Inst #514 = MTTGPR 7314 { 513, 1, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo58 }, // Inst #513 = MTTDSP 7315 { 512, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo129 }, // Inst #512 = MTTC1 7316 { 511, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo128 }, // Inst #511 = MTTC0 7317 { 510, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo127 }, // Inst #510 = MTTACX 7318 { 509, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo126 }, // Inst #509 = MSA_FP_ROUND_W_PSEUDO 7319 { 508, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo125 }, // Inst #508 = MSA_FP_ROUND_D_PSEUDO 7320 { 507, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo124 }, // Inst #507 = MSA_FP_EXTEND_W_PSEUDO 7321 { 506, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo123 }, // Inst #506 = MSA_FP_EXTEND_D_PSEUDO 7322 { 505, 2, 0, 4, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x10ULL, ImplicitList5, OperandInfo122 }, // Inst #505 = MIPSeh_return64 7323 { 504, 2, 0, 4, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x10ULL, ImplicitList5, OperandInfo45 }, // Inst #504 = MIPSeh_return32 7324 { 503, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo119 }, // Inst #503 = MFTLO 7325 { 502, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo119 }, // Inst #502 = MFTHI 7326 { 501, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo121 }, // Inst #501 = MFTHC1 7327 { 500, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo73 }, // Inst #500 = MFTGPR 7328 { 499, 1, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo58 }, // Inst #499 = MFTDSP 7329 { 498, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo121 }, // Inst #498 = MFTC1 7330 { 497, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo120 }, // Inst #497 = MFTC0 7331 { 496, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo119 }, // Inst #496 = MFTACX 7332 { 495, 3, 1, 2, 737, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo118 }, // Inst #495 = LwConstant32 7333 { 494, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo114 }, // Inst #494 = LoadImmSingleGPR 7334 { 493, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo117 }, // Inst #493 = LoadImmSingleFGR 7335 { 492, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo114 }, // Inst #492 = LoadImmDoubleGPR 7336 { 491, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo116 }, // Inst #491 = LoadImmDoubleFGR_32 7337 { 490, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo115 }, // Inst #490 = LoadImmDoubleFGR 7338 { 489, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo112 }, // Inst #489 = LoadImm64 7339 { 488, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo114 }, // Inst #488 = LoadImm32 7340 { 487, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo113 }, // Inst #487 = LoadAddrReg64 7341 { 486, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo96 }, // Inst #486 = LoadAddrReg32 7342 { 485, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo112 }, // Inst #485 = LoadAddrImm64 7343 { 484, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo111 }, // Inst #484 = LoadAddrImm32 7344 { 483, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo110 }, // Inst #483 = LWM_MM 7345 { 482, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo109 }, // Inst #482 = LONG_BRANCH_LUi2Op_64 7346 { 481, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo108 }, // Inst #481 = LONG_BRANCH_LUi2Op 7347 { 480, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo107 }, // Inst #480 = LONG_BRANCH_LUi 7348 { 479, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo106 }, // Inst #479 = LONG_BRANCH_DADDiu2Op 7349 { 478, 4, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo105 }, // Inst #478 = LONG_BRANCH_DADDiu 7350 { 477, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo57 }, // Inst #477 = LONG_BRANCH_ADDiu2Op 7351 { 476, 4, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo104 }, // Inst #476 = LONG_BRANCH_ADDiu 7352 { 475, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo103 }, // Inst #475 = LOAD_CCOND_DSP 7353 { 474, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo102 }, // Inst #474 = LOAD_ACC64DSP 7354 { 473, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo101 }, // Inst #473 = LOAD_ACC64 7355 { 472, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo100 }, // Inst #472 = LOAD_ACC128 7356 { 471, 3, 1, 4, 716, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo99 }, // Inst #471 = LD_F16 7357 { 470, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo98 }, // Inst #470 = LDR_W 7358 { 469, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo97 }, // Inst #469 = LDR_D 7359 { 468, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo96 }, // Inst #468 = LDMacro 7360 { 467, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo45 }, // Inst #467 = JalTwoReg 7361 { 466, 1, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo58 }, // Inst #466 = JalOneReg 7362 { 465, 1, 0, 4, 990, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x10ULL, ImplicitList3, OperandInfo2 }, // Inst #465 = JAL_MMR6 7363 { 464, 1, 0, 4, 407, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x10ULL, ImplicitList3, OperandInfo58 }, // Inst #464 = JALRPseudo 7364 { 463, 1, 0, 4, 407, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x10ULL, ImplicitList3, OperandInfo58 }, // Inst #463 = JALRHBPseudo 7365 { 462, 1, 0, 4, 1012, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x10ULL, ImplicitList3, OperandInfo95 }, // Inst #462 = JALRHB64Pseudo 7366 { 461, 1, 0, 4, 1012, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x10ULL, ImplicitList3, OperandInfo95 }, // Inst #461 = JALR64Pseudo 7367 { 460, 4, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo94 }, // Inst #460 = INSERT_W_VIDX_PSEUDO 7368 { 459, 4, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo93 }, // Inst #459 = INSERT_W_VIDX64_PSEUDO 7369 { 458, 4, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo92 }, // Inst #458 = INSERT_H_VIDX_PSEUDO 7370 { 457, 4, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo91 }, // Inst #457 = INSERT_H_VIDX64_PSEUDO 7371 { 456, 4, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo90 }, // Inst #456 = INSERT_FW_VIDX_PSEUDO 7372 { 455, 4, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo89 }, // Inst #455 = INSERT_FW_VIDX64_PSEUDO 7373 { 454, 4, 1, 4, 552, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo88 }, // Inst #454 = INSERT_FW_PSEUDO 7374 { 453, 4, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo87 }, // Inst #453 = INSERT_FD_VIDX_PSEUDO 7375 { 452, 4, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo86 }, // Inst #452 = INSERT_FD_VIDX64_PSEUDO 7376 { 451, 4, 1, 4, 552, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo85 }, // Inst #451 = INSERT_FD_PSEUDO 7377 { 450, 4, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo84 }, // Inst #450 = INSERT_D_VIDX_PSEUDO 7378 { 449, 4, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo83 }, // Inst #449 = INSERT_D_VIDX64_PSEUDO 7379 { 448, 4, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo82 }, // Inst #448 = INSERT_B_VIDX_PSEUDO 7380 { 447, 4, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo81 }, // Inst #447 = INSERT_B_VIDX64_PSEUDO 7381 { 446, 4, 2, 2, 737, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo80 }, // Inst #446 = GotPrologue16 7382 { 445, 2, 1, 4, 551, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo79 }, // Inst #445 = FILL_FW_PSEUDO 7383 { 444, 2, 1, 4, 551, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo78 }, // Inst #444 = FILL_FD_PSEUDO 7384 { 443, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo77 }, // Inst #443 = FEXP2_W_1_PSEUDO 7385 { 442, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo76 }, // Inst #442 = FEXP2_D_1_PSEUDO 7386 { 441, 2, 1, 4, 588, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo77 }, // Inst #441 = FABS_W 7387 { 440, 2, 1, 4, 588, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo76 }, // Inst #440 = FABS_D 7388 { 439, 3, 1, 4, 695, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo75 }, // Inst #439 = ExtractElementF64_64 7389 { 438, 3, 1, 4, 695, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo74 }, // Inst #438 = ExtractElementF64 7390 { 437, 0, 0, 4, 924, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr }, // Inst #437 = ERet 7391 { 436, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo71 }, // Inst #436 = DURemMacro 7392 { 435, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo70 }, // Inst #435 = DURemIMacro 7393 { 434, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo71 }, // Inst #434 = DUDivMacro 7394 { 433, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo70 }, // Inst #433 = DUDivIMacro 7395 { 432, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo71 }, // Inst #432 = DSRemMacro 7396 { 431, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo70 }, // Inst #431 = DSRemIMacro 7397 { 430, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo71 }, // Inst #430 = DSDivMacro 7398 { 429, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo70 }, // Inst #429 = DSDivIMacro 7399 { 428, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo73 }, // Inst #428 = DRORImm 7400 { 427, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo72 }, // Inst #427 = DROR 7401 { 426, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo73 }, // Inst #426 = DROLImm 7402 { 425, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo72 }, // Inst #425 = DROL 7403 { 424, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo71 }, // Inst #424 = DMULOUMacro 7404 { 423, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo71 }, // Inst #423 = DMULOMacro 7405 { 422, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo71 }, // Inst #422 = DMULMacro 7406 { 421, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo70 }, // Inst #421 = DMULImmMacro 7407 { 420, 1, 0, 2, 737, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo2 }, // Inst #420 = Constant32 7408 { 419, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo69 }, // Inst #419 = CTTC1 7409 { 418, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo68 }, // Inst #418 = COPY_FW_PSEUDO 7410 { 417, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo67 }, // Inst #417 = COPY_FD_PSEUDO 7411 { 416, 3, 0, 2, 737, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, OperandInfo4 }, // Inst #416 = CONSTPOOL_ENTRY 7412 { 415, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo66 }, // Inst #415 = CFTC1 7413 { 414, 3, 1, 4, 686, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo65 }, // Inst #414 = BuildPairF64_64 7414 { 413, 3, 1, 4, 686, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo64 }, // Inst #413 = BuildPairF64 7415 { 412, 3, 0, 2, 940, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo62 }, // Inst #412 = BtnezT8SltuX16 7416 { 411, 3, 0, 2, 940, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo63 }, // Inst #411 = BtnezT8SltiuX16 7417 { 410, 3, 0, 2, 940, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo63 }, // Inst #410 = BtnezT8SltiX16 7418 { 409, 3, 0, 2, 940, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo62 }, // Inst #409 = BtnezT8SltX16 7419 { 408, 3, 0, 2, 940, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo63 }, // Inst #408 = BtnezT8CmpiX16 7420 { 407, 3, 0, 2, 940, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo62 }, // Inst #407 = BtnezT8CmpX16 7421 { 406, 3, 0, 2, 940, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo62 }, // Inst #406 = BteqzT8SltuX16 7422 { 405, 3, 0, 2, 940, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo63 }, // Inst #405 = BteqzT8SltiuX16 7423 { 404, 3, 0, 2, 940, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo63 }, // Inst #404 = BteqzT8SltiX16 7424 { 403, 3, 0, 2, 940, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo62 }, // Inst #403 = BteqzT8SltX16 7425 { 402, 3, 0, 2, 940, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo63 }, // Inst #402 = BteqzT8CmpiX16 7426 { 401, 3, 0, 2, 940, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo62 }, // Inst #401 = BteqzT8CmpX16 7427 { 400, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo56 }, // Inst #400 = BneImm 7428 { 399, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo56 }, // Inst #399 = BeqImm 7429 { 398, 1, 0, 4, 956, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo55 }, // Inst #398 = B_MM_Pseudo 7430 { 397, 1, 0, 4, 997, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo55 }, // Inst #397 = B_MMR6_Pseudo 7431 { 396, 1, 0, 4, 945, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, ImplicitList2, OperandInfo55 }, // Inst #396 = B_MM 7432 { 395, 4, 1, 4, 525, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo60 }, // Inst #395 = BSEL_W_PSEUDO 7433 { 394, 4, 1, 4, 525, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo61 }, // Inst #394 = BSEL_H_PSEUDO 7434 { 393, 4, 1, 4, 525, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo60 }, // Inst #393 = BSEL_FW_PSEUDO 7435 { 392, 4, 1, 4, 525, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo59 }, // Inst #392 = BSEL_FD_PSEUDO 7436 { 391, 4, 1, 4, 525, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo59 }, // Inst #391 = BSEL_D_PSEUDO 7437 { 390, 1, 1, 4, 1, 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList4, OperandInfo58 }, // Inst #390 = BPOSGE32_PSEUDO 7438 { 389, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo56 }, // Inst #389 = BNELImmMacro 7439 { 388, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo56 }, // Inst #388 = BLTULImmMacro 7440 { 387, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo57 }, // Inst #387 = BLTUL 7441 { 386, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo56 }, // Inst #386 = BLTUImmMacro 7442 { 385, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo57 }, // Inst #385 = BLTU 7443 { 384, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo56 }, // Inst #384 = BLTLImmMacro 7444 { 383, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo57 }, // Inst #383 = BLTL 7445 { 382, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo56 }, // Inst #382 = BLTImmMacro 7446 { 381, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo57 }, // Inst #381 = BLT 7447 { 380, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo56 }, // Inst #380 = BLEULImmMacro 7448 { 379, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo57 }, // Inst #379 = BLEUL 7449 { 378, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo56 }, // Inst #378 = BLEUImmMacro 7450 { 377, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo57 }, // Inst #377 = BLEU 7451 { 376, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo56 }, // Inst #376 = BLELImmMacro 7452 { 375, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo57 }, // Inst #375 = BLEL 7453 { 374, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo56 }, // Inst #374 = BLEImmMacro 7454 { 373, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo57 }, // Inst #373 = BLE 7455 { 372, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo56 }, // Inst #372 = BGTULImmMacro 7456 { 371, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo57 }, // Inst #371 = BGTUL 7457 { 370, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo56 }, // Inst #370 = BGTUImmMacro 7458 { 369, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo57 }, // Inst #369 = BGTU 7459 { 368, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo56 }, // Inst #368 = BGTLImmMacro 7460 { 367, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo57 }, // Inst #367 = BGTL 7461 { 366, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo56 }, // Inst #366 = BGTImmMacro 7462 { 365, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo57 }, // Inst #365 = BGT 7463 { 364, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo56 }, // Inst #364 = BGEULImmMacro 7464 { 363, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo57 }, // Inst #363 = BGEUL 7465 { 362, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo56 }, // Inst #362 = BGEUImmMacro 7466 { 361, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo57 }, // Inst #361 = BGEU 7467 { 360, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo56 }, // Inst #360 = BGELImmMacro 7468 { 359, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo57 }, // Inst #359 = BGEL 7469 { 358, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo56 }, // Inst #358 = BGEImmMacro 7470 { 357, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo57 }, // Inst #357 = BGE 7471 { 356, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo56 }, // Inst #356 = BEQLImmMacro 7472 { 355, 1, 0, 4, 946, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, ImplicitList3, OperandInfo55 }, // Inst #355 = BAL_BR_MM 7473 { 354, 1, 0, 4, 919, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, ImplicitList3, OperandInfo55 }, // Inst #354 = BAL_BR 7474 { 353, 1, 0, 4, 374, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, ImplicitList2, OperandInfo55 }, // Inst #353 = B 7475 { 352, 6, 1, 4, 721, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo53 }, // Inst #352 = ATOMIC_SWAP_I8_POSTRA 7476 { 351, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo52 }, // Inst #351 = ATOMIC_SWAP_I8 7477 { 350, 3, 1, 4, 721, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo54 }, // Inst #350 = ATOMIC_SWAP_I64_POSTRA 7478 { 349, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo54 }, // Inst #349 = ATOMIC_SWAP_I64 7479 { 348, 3, 1, 4, 721, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo52 }, // Inst #348 = ATOMIC_SWAP_I32_POSTRA 7480 { 347, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo52 }, // Inst #347 = ATOMIC_SWAP_I32 7481 { 346, 6, 1, 4, 721, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo53 }, // Inst #346 = ATOMIC_SWAP_I16_POSTRA 7482 { 345, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo52 }, // Inst #345 = ATOMIC_SWAP_I16 7483 { 344, 6, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo53 }, // Inst #344 = ATOMIC_LOAD_XOR_I8_POSTRA 7484 { 343, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo52 }, // Inst #343 = ATOMIC_LOAD_XOR_I8 7485 { 342, 3, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo54 }, // Inst #342 = ATOMIC_LOAD_XOR_I64_POSTRA 7486 { 341, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo54 }, // Inst #341 = ATOMIC_LOAD_XOR_I64 7487 { 340, 3, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo52 }, // Inst #340 = ATOMIC_LOAD_XOR_I32_POSTRA 7488 { 339, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo52 }, // Inst #339 = ATOMIC_LOAD_XOR_I32 7489 { 338, 6, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo53 }, // Inst #338 = ATOMIC_LOAD_XOR_I16_POSTRA 7490 { 337, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo52 }, // Inst #337 = ATOMIC_LOAD_XOR_I16 7491 { 336, 6, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo53 }, // Inst #336 = ATOMIC_LOAD_UMIN_I8_POSTRA 7492 { 335, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo52 }, // Inst #335 = ATOMIC_LOAD_UMIN_I8 7493 { 334, 3, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo54 }, // Inst #334 = ATOMIC_LOAD_UMIN_I64_POSTRA 7494 { 333, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo54 }, // Inst #333 = ATOMIC_LOAD_UMIN_I64 7495 { 332, 3, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo52 }, // Inst #332 = ATOMIC_LOAD_UMIN_I32_POSTRA 7496 { 331, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo52 }, // Inst #331 = ATOMIC_LOAD_UMIN_I32 7497 { 330, 6, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo53 }, // Inst #330 = ATOMIC_LOAD_UMIN_I16_POSTRA 7498 { 329, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo52 }, // Inst #329 = ATOMIC_LOAD_UMIN_I16 7499 { 328, 6, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo53 }, // Inst #328 = ATOMIC_LOAD_UMAX_I8_POSTRA 7500 { 327, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo52 }, // Inst #327 = ATOMIC_LOAD_UMAX_I8 7501 { 326, 3, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo54 }, // Inst #326 = ATOMIC_LOAD_UMAX_I64_POSTRA 7502 { 325, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo54 }, // Inst #325 = ATOMIC_LOAD_UMAX_I64 7503 { 324, 3, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo52 }, // Inst #324 = ATOMIC_LOAD_UMAX_I32_POSTRA 7504 { 323, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo52 }, // Inst #323 = ATOMIC_LOAD_UMAX_I32 7505 { 322, 6, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo53 }, // Inst #322 = ATOMIC_LOAD_UMAX_I16_POSTRA 7506 { 321, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo52 }, // Inst #321 = ATOMIC_LOAD_UMAX_I16 7507 { 320, 6, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo53 }, // Inst #320 = ATOMIC_LOAD_SUB_I8_POSTRA 7508 { 319, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo52 }, // Inst #319 = ATOMIC_LOAD_SUB_I8 7509 { 318, 3, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo54 }, // Inst #318 = ATOMIC_LOAD_SUB_I64_POSTRA 7510 { 317, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo54 }, // Inst #317 = ATOMIC_LOAD_SUB_I64 7511 { 316, 3, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo52 }, // Inst #316 = ATOMIC_LOAD_SUB_I32_POSTRA 7512 { 315, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo52 }, // Inst #315 = ATOMIC_LOAD_SUB_I32 7513 { 314, 6, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo53 }, // Inst #314 = ATOMIC_LOAD_SUB_I16_POSTRA 7514 { 313, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo52 }, // Inst #313 = ATOMIC_LOAD_SUB_I16 7515 { 312, 6, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo53 }, // Inst #312 = ATOMIC_LOAD_OR_I8_POSTRA 7516 { 311, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo52 }, // Inst #311 = ATOMIC_LOAD_OR_I8 7517 { 310, 3, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo54 }, // Inst #310 = ATOMIC_LOAD_OR_I64_POSTRA 7518 { 309, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo54 }, // Inst #309 = ATOMIC_LOAD_OR_I64 7519 { 308, 3, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo52 }, // Inst #308 = ATOMIC_LOAD_OR_I32_POSTRA 7520 { 307, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo52 }, // Inst #307 = ATOMIC_LOAD_OR_I32 7521 { 306, 6, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo53 }, // Inst #306 = ATOMIC_LOAD_OR_I16_POSTRA 7522 { 305, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo52 }, // Inst #305 = ATOMIC_LOAD_OR_I16 7523 { 304, 6, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo53 }, // Inst #304 = ATOMIC_LOAD_NAND_I8_POSTRA 7524 { 303, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo52 }, // Inst #303 = ATOMIC_LOAD_NAND_I8 7525 { 302, 3, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo54 }, // Inst #302 = ATOMIC_LOAD_NAND_I64_POSTRA 7526 { 301, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo54 }, // Inst #301 = ATOMIC_LOAD_NAND_I64 7527 { 300, 3, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo52 }, // Inst #300 = ATOMIC_LOAD_NAND_I32_POSTRA 7528 { 299, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo52 }, // Inst #299 = ATOMIC_LOAD_NAND_I32 7529 { 298, 6, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo53 }, // Inst #298 = ATOMIC_LOAD_NAND_I16_POSTRA 7530 { 297, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo52 }, // Inst #297 = ATOMIC_LOAD_NAND_I16 7531 { 296, 6, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo53 }, // Inst #296 = ATOMIC_LOAD_MIN_I8_POSTRA 7532 { 295, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo52 }, // Inst #295 = ATOMIC_LOAD_MIN_I8 7533 { 294, 3, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo54 }, // Inst #294 = ATOMIC_LOAD_MIN_I64_POSTRA 7534 { 293, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo54 }, // Inst #293 = ATOMIC_LOAD_MIN_I64 7535 { 292, 3, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo52 }, // Inst #292 = ATOMIC_LOAD_MIN_I32_POSTRA 7536 { 291, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo52 }, // Inst #291 = ATOMIC_LOAD_MIN_I32 7537 { 290, 6, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo53 }, // Inst #290 = ATOMIC_LOAD_MIN_I16_POSTRA 7538 { 289, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo52 }, // Inst #289 = ATOMIC_LOAD_MIN_I16 7539 { 288, 6, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo53 }, // Inst #288 = ATOMIC_LOAD_MAX_I8_POSTRA 7540 { 287, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo52 }, // Inst #287 = ATOMIC_LOAD_MAX_I8 7541 { 286, 3, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo54 }, // Inst #286 = ATOMIC_LOAD_MAX_I64_POSTRA 7542 { 285, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo54 }, // Inst #285 = ATOMIC_LOAD_MAX_I64 7543 { 284, 3, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo52 }, // Inst #284 = ATOMIC_LOAD_MAX_I32_POSTRA 7544 { 283, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo52 }, // Inst #283 = ATOMIC_LOAD_MAX_I32 7545 { 282, 6, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo53 }, // Inst #282 = ATOMIC_LOAD_MAX_I16_POSTRA 7546 { 281, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo52 }, // Inst #281 = ATOMIC_LOAD_MAX_I16 7547 { 280, 6, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo53 }, // Inst #280 = ATOMIC_LOAD_AND_I8_POSTRA 7548 { 279, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo52 }, // Inst #279 = ATOMIC_LOAD_AND_I8 7549 { 278, 3, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo54 }, // Inst #278 = ATOMIC_LOAD_AND_I64_POSTRA 7550 { 277, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo54 }, // Inst #277 = ATOMIC_LOAD_AND_I64 7551 { 276, 3, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo52 }, // Inst #276 = ATOMIC_LOAD_AND_I32_POSTRA 7552 { 275, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo52 }, // Inst #275 = ATOMIC_LOAD_AND_I32 7553 { 274, 6, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo53 }, // Inst #274 = ATOMIC_LOAD_AND_I16_POSTRA 7554 { 273, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo52 }, // Inst #273 = ATOMIC_LOAD_AND_I16 7555 { 272, 6, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo53 }, // Inst #272 = ATOMIC_LOAD_ADD_I8_POSTRA 7556 { 271, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo52 }, // Inst #271 = ATOMIC_LOAD_ADD_I8 7557 { 270, 3, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo54 }, // Inst #270 = ATOMIC_LOAD_ADD_I64_POSTRA 7558 { 269, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo54 }, // Inst #269 = ATOMIC_LOAD_ADD_I64 7559 { 268, 3, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo52 }, // Inst #268 = ATOMIC_LOAD_ADD_I32_POSTRA 7560 { 267, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo52 }, // Inst #267 = ATOMIC_LOAD_ADD_I32 7561 { 266, 6, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo53 }, // Inst #266 = ATOMIC_LOAD_ADD_I16_POSTRA 7562 { 265, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo52 }, // Inst #265 = ATOMIC_LOAD_ADD_I16 7563 { 264, 7, 1, 4, 722, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo50 }, // Inst #264 = ATOMIC_CMP_SWAP_I8_POSTRA 7564 { 263, 4, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo49 }, // Inst #263 = ATOMIC_CMP_SWAP_I8 7565 { 262, 4, 1, 4, 722, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo51 }, // Inst #262 = ATOMIC_CMP_SWAP_I64_POSTRA 7566 { 261, 4, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo51 }, // Inst #261 = ATOMIC_CMP_SWAP_I64 7567 { 260, 4, 1, 4, 722, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo49 }, // Inst #260 = ATOMIC_CMP_SWAP_I32_POSTRA 7568 { 259, 4, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo49 }, // Inst #259 = ATOMIC_CMP_SWAP_I32 7569 { 258, 7, 1, 4, 722, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo50 }, // Inst #258 = ATOMIC_CMP_SWAP_I16_POSTRA 7570 { 257, 4, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo49 }, // Inst #257 = ATOMIC_CMP_SWAP_I16 7571 { 256, 3, 1, 4, 550, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo48 }, // Inst #256 = AND_V_W_PSEUDO 7572 { 255, 3, 1, 4, 550, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo47 }, // Inst #255 = AND_V_H_PSEUDO 7573 { 254, 3, 1, 4, 550, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo46 }, // Inst #254 = AND_V_D_PSEUDO 7574 { 253, 2, 0, 4, 1, 1, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, OperandInfo10 }, // Inst #253 = ADJCALLSTACKUP 7575 { 252, 2, 0, 4, 1, 1, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, OperandInfo10 }, // Inst #252 = ADJCALLSTACKDOWN 7576 { 251, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo45 }, // Inst #251 = ABSMacro 7577 { 250, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo44 }, // Inst #250 = G_UBFX 7578 { 249, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo44 }, // Inst #249 = G_SBFX 7579 { 248, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #248 = G_VECREDUCE_UMIN 7580 { 247, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #247 = G_VECREDUCE_UMAX 7581 { 246, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #246 = G_VECREDUCE_SMIN 7582 { 245, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #245 = G_VECREDUCE_SMAX 7583 { 244, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #244 = G_VECREDUCE_XOR 7584 { 243, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #243 = G_VECREDUCE_OR 7585 { 242, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #242 = G_VECREDUCE_AND 7586 { 241, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #241 = G_VECREDUCE_MUL 7587 { 240, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #240 = G_VECREDUCE_ADD 7588 { 239, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #239 = G_VECREDUCE_FMIN 7589 { 238, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #238 = G_VECREDUCE_FMAX 7590 { 237, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #237 = G_VECREDUCE_FMUL 7591 { 236, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #236 = G_VECREDUCE_FADD 7592 { 235, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo40 }, // Inst #235 = G_VECREDUCE_SEQ_FMUL 7593 { 234, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo40 }, // Inst #234 = G_VECREDUCE_SEQ_FADD 7594 { 233, 3, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo22 }, // Inst #233 = G_BZERO 7595 { 232, 4, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo43 }, // Inst #232 = G_MEMSET 7596 { 231, 4, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo43 }, // Inst #231 = G_MEMMOVE 7597 { 230, 3, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo40 }, // Inst #230 = G_MEMCPY_INLINE 7598 { 229, 4, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo43 }, // Inst #229 = G_MEMCPY 7599 { 228, 2, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, OperandInfo42 }, // Inst #228 = G_WRITE_REGISTER 7600 { 227, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, OperandInfo21 }, // Inst #227 = G_READ_REGISTER 7601 { 226, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo25 }, // Inst #226 = G_STRICT_FSQRT 7602 { 225, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo19 }, // Inst #225 = G_STRICT_FMA 7603 { 224, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo18 }, // Inst #224 = G_STRICT_FREM 7604 { 223, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo18 }, // Inst #223 = G_STRICT_FDIV 7605 { 222, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo18 }, // Inst #222 = G_STRICT_FMUL 7606 { 221, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo18 }, // Inst #221 = G_STRICT_FSUB 7607 { 220, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo18 }, // Inst #220 = G_STRICT_FADD 7608 { 219, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo26 }, // Inst #219 = G_DYN_STACKALLOC 7609 { 218, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo21 }, // Inst #218 = G_JUMP_TABLE 7610 { 217, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo21 }, // Inst #217 = G_BLOCK_ADDR 7611 { 216, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #216 = G_ADDRSPACE_CAST 7612 { 215, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #215 = G_FNEARBYINT 7613 { 214, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #214 = G_FRINT 7614 { 213, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #213 = G_FFLOOR 7615 { 212, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #212 = G_FSQRT 7616 { 211, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #211 = G_FSIN 7617 { 210, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #210 = G_FCOS 7618 { 209, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #209 = G_FCEIL 7619 { 208, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #208 = G_BITREVERSE 7620 { 207, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #207 = G_BSWAP 7621 { 206, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #206 = G_CTPOP 7622 { 205, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #205 = G_CTLZ_ZERO_UNDEF 7623 { 204, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #204 = G_CTLZ 7624 { 203, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #203 = G_CTTZ_ZERO_UNDEF 7625 { 202, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #202 = G_CTTZ 7626 { 201, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo41 }, // Inst #201 = G_SHUFFLE_VECTOR 7627 { 200, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo40 }, // Inst #200 = G_EXTRACT_VECTOR_ELT 7628 { 199, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo39 }, // Inst #199 = G_INSERT_VECTOR_ELT 7629 { 198, 3, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, OperandInfo38 }, // Inst #198 = G_BRJT 7630 { 197, 1, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, OperandInfo2 }, // Inst #197 = G_BR 7631 { 196, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #196 = G_LLROUND 7632 { 195, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #195 = G_LROUND 7633 { 194, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #194 = G_ABS 7634 { 193, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #193 = G_UMAX 7635 { 192, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #192 = G_UMIN 7636 { 191, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #191 = G_SMAX 7637 { 190, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #190 = G_SMIN 7638 { 189, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo33 }, // Inst #189 = G_PTRMASK 7639 { 188, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo33 }, // Inst #188 = G_PTR_ADD 7640 { 187, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #187 = G_FMAXIMUM 7641 { 186, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #186 = G_FMINIMUM 7642 { 185, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #185 = G_FMAXNUM_IEEE 7643 { 184, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #184 = G_FMINNUM_IEEE 7644 { 183, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #183 = G_FMAXNUM 7645 { 182, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #182 = G_FMINNUM 7646 { 181, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #181 = G_FCANONICALIZE 7647 { 180, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo32 }, // Inst #180 = G_IS_FPCLASS 7648 { 179, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo33 }, // Inst #179 = G_FCOPYSIGN 7649 { 178, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #178 = G_FABS 7650 { 177, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #177 = G_UITOFP 7651 { 176, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #176 = G_SITOFP 7652 { 175, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #175 = G_FPTOUI 7653 { 174, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #174 = G_FPTOSI 7654 { 173, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #173 = G_FPTRUNC 7655 { 172, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #172 = G_FPEXT 7656 { 171, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #171 = G_FNEG 7657 { 170, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #170 = G_FLOG10 7658 { 169, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #169 = G_FLOG2 7659 { 168, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #168 = G_FLOG 7660 { 167, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #167 = G_FEXP2 7661 { 166, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #166 = G_FEXP 7662 { 165, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo33 }, // Inst #165 = G_FPOWI 7663 { 164, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo18 }, // Inst #164 = G_FPOW 7664 { 163, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo18 }, // Inst #163 = G_FREM 7665 { 162, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo18 }, // Inst #162 = G_FDIV 7666 { 161, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo19 }, // Inst #161 = G_FMAD 7667 { 160, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo19 }, // Inst #160 = G_FMA 7668 { 159, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #159 = G_FMUL 7669 { 158, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo18 }, // Inst #158 = G_FSUB 7670 { 157, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #157 = G_FADD 7671 { 156, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo37 }, // Inst #156 = G_UDIVFIXSAT 7672 { 155, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo37 }, // Inst #155 = G_SDIVFIXSAT 7673 { 154, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo37 }, // Inst #154 = G_UDIVFIX 7674 { 153, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo37 }, // Inst #153 = G_SDIVFIX 7675 { 152, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo37 }, // Inst #152 = G_UMULFIXSAT 7676 { 151, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo37 }, // Inst #151 = G_SMULFIXSAT 7677 { 150, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo37 }, // Inst #150 = G_UMULFIX 7678 { 149, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo37 }, // Inst #149 = G_SMULFIX 7679 { 148, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo33 }, // Inst #148 = G_SSHLSAT 7680 { 147, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo33 }, // Inst #147 = G_USHLSAT 7681 { 146, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo18 }, // Inst #146 = G_SSUBSAT 7682 { 145, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo18 }, // Inst #145 = G_USUBSAT 7683 { 144, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #144 = G_SADDSAT 7684 { 143, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #143 = G_UADDSAT 7685 { 142, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #142 = G_SMULH 7686 { 141, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #141 = G_UMULH 7687 { 140, 4, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo30 }, // Inst #140 = G_SMULO 7688 { 139, 4, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo30 }, // Inst #139 = G_UMULO 7689 { 138, 5, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo36 }, // Inst #138 = G_SSUBE 7690 { 137, 4, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo30 }, // Inst #137 = G_SSUBO 7691 { 136, 5, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo36 }, // Inst #136 = G_SADDE 7692 { 135, 4, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo30 }, // Inst #135 = G_SADDO 7693 { 134, 5, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo36 }, // Inst #134 = G_USUBE 7694 { 133, 4, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo30 }, // Inst #133 = G_USUBO 7695 { 132, 5, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo36 }, // Inst #132 = G_UADDE 7696 { 131, 4, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo30 }, // Inst #131 = G_UADDO 7697 { 130, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo30 }, // Inst #130 = G_SELECT 7698 { 129, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo35 }, // Inst #129 = G_FCMP 7699 { 128, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo35 }, // Inst #128 = G_ICMP 7700 { 127, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo33 }, // Inst #127 = G_ROTL 7701 { 126, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo33 }, // Inst #126 = G_ROTR 7702 { 125, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo34 }, // Inst #125 = G_FSHR 7703 { 124, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo34 }, // Inst #124 = G_FSHL 7704 { 123, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo33 }, // Inst #123 = G_ASHR 7705 { 122, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo33 }, // Inst #122 = G_LSHR 7706 { 121, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo33 }, // Inst #121 = G_SHL 7707 { 120, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #120 = G_ZEXT 7708 { 119, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo17 }, // Inst #119 = G_SEXT_INREG 7709 { 118, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #118 = G_SEXT 7710 { 117, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo32 }, // Inst #117 = G_VAARG 7711 { 116, 1, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo20 }, // Inst #116 = G_VASTART 7712 { 115, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo21 }, // Inst #115 = G_FCONSTANT 7713 { 114, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo21 }, // Inst #114 = G_CONSTANT 7714 { 113, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #113 = G_TRUNC 7715 { 112, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #112 = G_ANYEXT 7716 { 111, 1, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, OperandInfo2 }, // Inst #111 = G_INTRINSIC_W_SIDE_EFFECTS 7717 { 110, 1, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, OperandInfo2 }, // Inst #110 = G_INTRINSIC 7718 { 109, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr }, // Inst #109 = G_INVOKE_REGION_START 7719 { 108, 1, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, OperandInfo20 }, // Inst #108 = G_BRINDIRECT 7720 { 107, 2, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, OperandInfo21 }, // Inst #107 = G_BRCOND 7721 { 106, 2, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo10 }, // Inst #106 = G_FENCE 7722 { 105, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #105 = G_ATOMICRMW_UDEC_WRAP 7723 { 104, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #104 = G_ATOMICRMW_UINC_WRAP 7724 { 103, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #103 = G_ATOMICRMW_FMIN 7725 { 102, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #102 = G_ATOMICRMW_FMAX 7726 { 101, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #101 = G_ATOMICRMW_FSUB 7727 { 100, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #100 = G_ATOMICRMW_FADD 7728 { 99, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #99 = G_ATOMICRMW_UMIN 7729 { 98, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #98 = G_ATOMICRMW_UMAX 7730 { 97, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #97 = G_ATOMICRMW_MIN 7731 { 96, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #96 = G_ATOMICRMW_MAX 7732 { 95, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #95 = G_ATOMICRMW_XOR 7733 { 94, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #94 = G_ATOMICRMW_OR 7734 { 93, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #93 = G_ATOMICRMW_NAND 7735 { 92, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #92 = G_ATOMICRMW_AND 7736 { 91, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #91 = G_ATOMICRMW_SUB 7737 { 90, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #90 = G_ATOMICRMW_ADD 7738 { 89, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #89 = G_ATOMICRMW_XCHG 7739 { 88, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo30 }, // Inst #88 = G_ATOMIC_CMPXCHG 7740 { 87, 5, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo29 }, // Inst #87 = G_ATOMIC_CMPXCHG_WITH_SUCCESS 7741 { 86, 5, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo28 }, // Inst #86 = G_INDEXED_STORE 7742 { 85, 2, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo23 }, // Inst #85 = G_STORE 7743 { 84, 5, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo27 }, // Inst #84 = G_INDEXED_ZEXTLOAD 7744 { 83, 5, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo27 }, // Inst #83 = G_INDEXED_SEXTLOAD 7745 { 82, 5, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo27 }, // Inst #82 = G_INDEXED_LOAD 7746 { 81, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo23 }, // Inst #81 = G_ZEXTLOAD 7747 { 80, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo23 }, // Inst #80 = G_SEXTLOAD 7748 { 79, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo23 }, // Inst #79 = G_LOAD 7749 { 78, 1, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo20 }, // Inst #78 = G_READCYCLECOUNTER 7750 { 77, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #77 = G_INTRINSIC_ROUNDEVEN 7751 { 76, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #76 = G_INTRINSIC_LRINT 7752 { 75, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #75 = G_INTRINSIC_ROUND 7753 { 74, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #74 = G_INTRINSIC_TRUNC 7754 { 73, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo26 }, // Inst #73 = G_INTRINSIC_FPTRUNC_ROUND 7755 { 72, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #72 = G_FREEZE 7756 { 71, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #71 = G_BITCAST 7757 { 70, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #70 = G_INTTOPTR 7758 { 69, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #69 = G_PTRTOINT 7759 { 68, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, OperandInfo23 }, // Inst #68 = G_CONCAT_VECTORS 7760 { 67, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, OperandInfo23 }, // Inst #67 = G_BUILD_VECTOR_TRUNC 7761 { 66, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, OperandInfo23 }, // Inst #66 = G_BUILD_VECTOR 7762 { 65, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, OperandInfo23 }, // Inst #65 = G_MERGE_VALUES 7763 { 64, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo24 }, // Inst #64 = G_INSERT 7764 { 63, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, OperandInfo23 }, // Inst #63 = G_UNMERGE_VALUES 7765 { 62, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo22 }, // Inst #62 = G_EXTRACT 7766 { 61, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo21 }, // Inst #61 = G_GLOBAL_VALUE 7767 { 60, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo21 }, // Inst #60 = G_FRAME_INDEX 7768 { 59, 1, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, OperandInfo20 }, // Inst #59 = G_PHI 7769 { 58, 1, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo20 }, // Inst #58 = G_IMPLICIT_DEF 7770 { 57, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #57 = G_XOR 7771 { 56, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #56 = G_OR 7772 { 55, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #55 = G_AND 7773 { 54, 4, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo19 }, // Inst #54 = G_UDIVREM 7774 { 53, 4, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo19 }, // Inst #53 = G_SDIVREM 7775 { 52, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo18 }, // Inst #52 = G_UREM 7776 { 51, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo18 }, // Inst #51 = G_SREM 7777 { 50, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo18 }, // Inst #50 = G_UDIV 7778 { 49, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo18 }, // Inst #49 = G_SDIV 7779 { 48, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #48 = G_MUL 7780 { 47, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo18 }, // Inst #47 = G_SUB 7781 { 46, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #46 = G_ADD 7782 { 45, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo17 }, // Inst #45 = G_ASSERT_ALIGN 7783 { 44, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo17 }, // Inst #44 = G_ASSERT_ZEXT 7784 { 43, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo17 }, // Inst #43 = G_ASSERT_SEXT 7785 { 42, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #42 = MEMBARRIER 7786 { 41, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #41 = ICALL_BRANCH_FUNNEL 7787 { 40, 3, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo16 }, // Inst #40 = PATCHABLE_TYPED_EVENT_CALL 7788 { 39, 2, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo15 }, // Inst #39 = PATCHABLE_EVENT_CALL 7789 { 38, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #38 = PATCHABLE_TAIL_CALL 7790 { 37, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #37 = PATCHABLE_FUNCTION_EXIT 7791 { 36, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #36 = PATCHABLE_RET 7792 { 35, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #35 = PATCHABLE_FUNCTION_ENTER 7793 { 34, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #34 = PATCHABLE_OP 7794 { 33, 1, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo2 }, // Inst #33 = FAULTING_OP 7795 { 32, 2, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo14 }, // Inst #32 = LOCAL_ESCAPE 7796 { 31, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #31 = STATEPOINT 7797 { 30, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo13 }, // Inst #30 = PREALLOCATED_ARG 7798 { 29, 1, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo3 }, // Inst #29 = PREALLOCATED_SETUP 7799 { 28, 1, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, OperandInfo12 }, // Inst #28 = LOAD_STACK_GUARD 7800 { 27, 6, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo11 }, // Inst #27 = PATCHPOINT 7801 { 26, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #26 = FENTRY_CALL 7802 { 25, 2, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo10 }, // Inst #25 = STACKMAP 7803 { 24, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL, nullptr, OperandInfo9 }, // Inst #24 = ARITH_FENCE 7804 { 23, 4, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo8 }, // Inst #23 = PSEUDO_PROBE 7805 { 22, 1, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL, nullptr, OperandInfo3 }, // Inst #22 = LIFETIME_END 7806 { 21, 1, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL, nullptr, OperandInfo3 }, // Inst #21 = LIFETIME_START 7807 { 20, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr }, // Inst #20 = BUNDLE 7808 { 19, 2, 1, 0, 514, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, OperandInfo7 }, // Inst #19 = COPY 7809 { 18, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, OperandInfo7 }, // Inst #18 = REG_SEQUENCE 7810 { 17, 1, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL, nullptr, OperandInfo2 }, // Inst #17 = DBG_LABEL 7811 { 16, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr }, // Inst #16 = DBG_PHI 7812 { 15, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr }, // Inst #15 = DBG_INSTR_REF 7813 { 14, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr }, // Inst #14 = DBG_VALUE_LIST 7814 { 13, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr }, // Inst #13 = DBG_VALUE 7815 { 12, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, OperandInfo4 }, // Inst #12 = COPY_TO_REGCLASS 7816 { 11, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo6 }, // Inst #11 = SUBREG_TO_REG 7817 { 10, 1, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, OperandInfo2 }, // Inst #10 = IMPLICIT_DEF 7818 { 9, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo5 }, // Inst #9 = INSERT_SUBREG 7819 { 8, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo4 }, // Inst #8 = EXTRACT_SUBREG 7820 { 7, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr }, // Inst #7 = KILL 7821 { 6, 1, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, OperandInfo3 }, // Inst #6 = ANNOTATION_LABEL 7822 { 5, 1, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, OperandInfo3 }, // Inst #5 = GC_LABEL 7823 { 4, 1, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, OperandInfo3 }, // Inst #4 = EH_LABEL 7824 { 3, 1, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, OperandInfo3 }, // Inst #3 = CFI_INSTRUCTION 7825 { 2, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #2 = INLINEASM_BR 7826 { 1, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr }, // Inst #1 = INLINEASM 7827 { 0, 1, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, OperandInfo2 }, // Inst #0 = PHI 7828}; 7829 7830extern const char MipsInstrNameData[] = { 7831 /* 0 */ 'G', '_', 'F', 'L', 'O', 'G', '1', '0', 0, 7832 /* 9 */ 'D', 'M', 'F', 'C', '0', 0, 7833 /* 15 */ 'D', 'M', 'F', 'G', 'C', '0', 0, 7834 /* 22 */ 'M', 'F', 'H', 'G', 'C', '0', 0, 7835 /* 29 */ 'M', 'T', 'H', 'G', 'C', '0', 0, 7836 /* 36 */ 'D', 'M', 'T', 'G', 'C', '0', 0, 7837 /* 43 */ 'M', 'F', 'T', 'C', '0', 0, 7838 /* 49 */ 'D', 'M', 'T', 'C', '0', 0, 7839 /* 55 */ 'M', 'T', 'T', 'C', '0', 0, 7840 /* 61 */ 'V', 'M', 'M', '0', 0, 7841 /* 66 */ 'M', 'T', 'M', '0', 0, 7842 /* 71 */ 'M', 'T', 'P', '0', 0, 7843 /* 76 */ 'B', 'B', 'I', 'T', '0', 0, 7844 /* 82 */ 'L', 'D', 'C', '1', 0, 7845 /* 87 */ 'S', 'D', 'C', '1', 0, 7846 /* 92 */ 'C', 'F', 'C', '1', 0, 7847 /* 97 */ 'D', 'M', 'F', 'C', '1', 0, 7848 /* 103 */ 'M', 'F', 'T', 'H', 'C', '1', 0, 7849 /* 110 */ 'M', 'T', 'T', 'H', 'C', '1', 0, 7850 /* 117 */ 'C', 'T', 'C', '1', 0, 7851 /* 122 */ 'C', 'F', 'T', 'C', '1', 0, 7852 /* 128 */ 'M', 'F', 'T', 'C', '1', 0, 7853 /* 134 */ 'D', 'M', 'T', 'C', '1', 0, 7854 /* 140 */ 'C', 'T', 'T', 'C', '1', 0, 7855 /* 146 */ 'M', 'T', 'T', 'C', '1', 0, 7856 /* 152 */ 'L', 'W', 'C', '1', 0, 7857 /* 157 */ 'S', 'W', 'C', '1', 0, 7858 /* 162 */ 'L', 'D', 'X', 'C', '1', 0, 7859 /* 168 */ 'S', 'D', 'X', 'C', '1', 0, 7860 /* 174 */ 'L', 'U', 'X', 'C', '1', 0, 7861 /* 180 */ 'S', 'U', 'X', 'C', '1', 0, 7862 /* 186 */ 'L', 'W', 'X', 'C', '1', 0, 7863 /* 192 */ 'S', 'W', 'X', 'C', '1', 0, 7864 /* 198 */ 'M', 'T', 'M', '1', 0, 7865 /* 203 */ 'S', 'D', 'C', '1', '_', 'M', '1', 0, 7866 /* 211 */ 'M', 'T', 'P', '1', 0, 7867 /* 216 */ 'B', 'B', 'I', 'T', '1', 0, 7868 /* 222 */ 'B', 'B', 'I', 'T', '0', '3', '2', 0, 7869 /* 230 */ 'B', 'B', 'I', 'T', '1', '3', '2', 0, 7870 /* 238 */ 'D', 'S', 'R', 'A', '3', '2', 0, 7871 /* 245 */ 'M', 'F', 'H', 'C', '1', '_', 'D', '3', '2', 0, 7872 /* 255 */ 'M', 'T', 'H', 'C', '1', '_', 'D', '3', '2', 0, 7873 /* 265 */ 'F', 'S', 'U', 'B', '_', 'D', '3', '2', 0, 7874 /* 274 */ 'N', 'M', 'S', 'U', 'B', '_', 'D', '3', '2', 0, 7875 /* 284 */ 'F', 'A', 'D', 'D', '_', 'D', '3', '2', 0, 7876 /* 293 */ 'N', 'M', 'A', 'D', 'D', '_', 'D', '3', '2', 0, 7877 /* 303 */ 'C', '_', 'N', 'G', 'E', '_', 'D', '3', '2', 0, 7878 /* 313 */ 'C', '_', 'N', 'G', 'L', 'E', '_', 'D', '3', '2', 0, 7879 /* 324 */ 'C', '_', 'O', 'L', 'E', '_', 'D', '3', '2', 0, 7880 /* 334 */ 'C', '_', 'U', 'L', 'E', '_', 'D', '3', '2', 0, 7881 /* 344 */ 'C', '_', 'L', 'E', '_', 'D', '3', '2', 0, 7882 /* 353 */ 'C', '_', 'S', 'F', '_', 'D', '3', '2', 0, 7883 /* 362 */ 'M', 'O', 'V', 'F', '_', 'D', '3', '2', 0, 7884 /* 371 */ 'C', '_', 'F', '_', 'D', '3', '2', 0, 7885 /* 379 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'E', 'L', 'E', 'C', 'T', 'F', 'P', '_', 'F', '_', 'D', '3', '2', 0, 7886 /* 400 */ 'F', 'N', 'E', 'G', '_', 'D', '3', '2', 0, 7887 /* 409 */ 'M', 'O', 'V', 'N', '_', 'I', '_', 'D', '3', '2', 0, 7888 /* 420 */ 'M', 'O', 'V', 'Z', '_', 'I', '_', 'D', '3', '2', 0, 7889 /* 431 */ 'C', '_', 'N', 'G', 'L', '_', 'D', '3', '2', 0, 7890 /* 441 */ 'F', 'M', 'U', 'L', '_', 'D', '3', '2', 0, 7891 /* 450 */ 'L', 'D', 'C', '1', '_', 'M', 'M', '_', 'D', '3', '2', 0, 7892 /* 462 */ 'S', 'D', 'C', '1', '_', 'M', 'M', '_', 'D', '3', '2', 0, 7893 /* 474 */ 'C', '_', 'U', 'N', '_', 'D', '3', '2', 0, 7894 /* 483 */ 'R', 'E', 'C', 'I', 'P', '_', 'D', '3', '2', 0, 7895 /* 493 */ 'F', 'C', 'M', 'P', '_', 'D', '3', '2', 0, 7896 /* 502 */ 'C', '_', 'S', 'E', 'Q', '_', 'D', '3', '2', 0, 7897 /* 512 */ 'C', '_', 'U', 'E', 'Q', '_', 'D', '3', '2', 0, 7898 /* 522 */ 'C', '_', 'E', 'Q', '_', 'D', '3', '2', 0, 7899 /* 531 */ 'F', 'A', 'B', 'S', '_', 'D', '3', '2', 0, 7900 /* 540 */ 'C', 'V', 'T', '_', 'S', '_', 'D', '3', '2', 0, 7901 /* 550 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'D', '3', '2', 0, 7902 /* 567 */ 'C', '_', 'N', 'G', 'T', '_', 'D', '3', '2', 0, 7903 /* 577 */ 'C', '_', 'O', 'L', 'T', '_', 'D', '3', '2', 0, 7904 /* 587 */ 'C', '_', 'U', 'L', 'T', '_', 'D', '3', '2', 0, 7905 /* 597 */ 'C', '_', 'L', 'T', '_', 'D', '3', '2', 0, 7906 /* 606 */ 'F', 'S', 'Q', 'R', 'T', '_', 'D', '3', '2', 0, 7907 /* 616 */ 'R', 'S', 'Q', 'R', 'T', '_', 'D', '3', '2', 0, 7908 /* 626 */ 'M', 'O', 'V', 'T', '_', 'D', '3', '2', 0, 7909 /* 635 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'E', 'L', 'E', 'C', 'T', 'F', 'P', '_', 'T', '_', 'D', '3', '2', 0, 7910 /* 656 */ 'F', 'D', 'I', 'V', '_', 'D', '3', '2', 0, 7911 /* 665 */ 'F', 'M', 'O', 'V', '_', 'D', '3', '2', 0, 7912 /* 674 */ 'P', 's', 'e', 'u', 'd', 'o', 'T', 'R', 'U', 'N', 'C', '_', 'W', '_', 'D', '3', '2', 0, 7913 /* 692 */ 'R', 'O', 'U', 'N', 'D', '_', 'W', '_', 'D', '3', '2', 0, 7914 /* 704 */ 'C', 'E', 'I', 'L', '_', 'W', '_', 'D', '3', '2', 0, 7915 /* 715 */ 'F', 'L', 'O', 'O', 'R', '_', 'W', '_', 'D', '3', '2', 0, 7916 /* 727 */ 'C', 'V', 'T', '_', 'W', '_', 'D', '3', '2', 0, 7917 /* 737 */ 'B', 'P', 'O', 'S', 'G', 'E', '3', '2', 0, 7918 /* 746 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'S', 'U', 'B', '_', 'I', '3', '2', 0, 7919 /* 766 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'D', 'D', '_', 'I', '3', '2', 0, 7920 /* 786 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'N', 'A', 'N', 'D', '_', 'I', '3', '2', 0, 7921 /* 807 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'N', 'D', '_', 'I', '3', '2', 0, 7922 /* 827 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'U', 'M', 'I', 'N', '_', 'I', '3', '2', 0, 7923 /* 848 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'M', 'I', 'N', '_', 'I', '3', '2', 0, 7924 /* 868 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'S', 'W', 'A', 'P', '_', 'I', '3', '2', 0, 7925 /* 884 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', '_', 'S', 'W', 'A', 'P', '_', 'I', '3', '2', 0, 7926 /* 904 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'X', 'O', 'R', '_', 'I', '3', '2', 0, 7927 /* 924 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'O', 'R', '_', 'I', '3', '2', 0, 7928 /* 943 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'U', 'M', 'A', 'X', '_', 'I', '3', '2', 0, 7929 /* 964 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'M', 'A', 'X', '_', 'I', '3', '2', 0, 7930 /* 984 */ 'D', 'S', 'L', 'L', '3', '2', 0, 7931 /* 991 */ 'D', 'S', 'R', 'L', '3', '2', 0, 7932 /* 998 */ 'D', 'R', 'O', 'T', 'R', '3', '2', 0, 7933 /* 1006 */ 'C', 'I', 'N', 'S', '3', '2', 0, 7934 /* 1013 */ 'E', 'X', 'T', 'S', '3', '2', 0, 7935 /* 1020 */ 'F', 'C', 'M', 'P', '_', 'S', '3', '2', 0, 7936 /* 1029 */ 'D', 'S', 'L', 'L', '6', '4', '_', '3', '2', 0, 7937 /* 1039 */ 'C', 'I', 'N', 'S', '6', '4', '_', '3', '2', 0, 7938 /* 1049 */ 'D', 'E', 'X', 'T', '6', '4', '_', '3', '2', 0, 7939 /* 1059 */ 'L', 'o', 'a', 'd', 'I', 'm', 'm', 'D', 'o', 'u', 'b', 'l', 'e', 'F', 'G', 'R', '_', '3', '2', 0, 7940 /* 1079 */ 'L', 'o', 'a', 'd', 'A', 'd', 'd', 'r', 'R', 'e', 'g', '3', '2', 0, 7941 /* 1093 */ 'C', 'I', 'N', 'S', '_', 'i', '3', '2', 0, 7942 /* 1102 */ 'L', 'o', 'a', 'd', 'I', 'm', 'm', '3', '2', 0, 7943 /* 1112 */ 'L', 'o', 'a', 'd', 'A', 'd', 'd', 'r', 'I', 'm', 'm', '3', '2', 0, 7944 /* 1126 */ 'M', 'I', 'P', 'S', 'e', 'h', '_', 'r', 'e', 't', 'u', 'r', 'n', '3', '2', 0, 7945 /* 1142 */ 'L', 'w', 'C', 'o', 'n', 's', 't', 'a', 'n', 't', '3', '2', 0, 7946 /* 1155 */ 'L', 'D', 'C', '2', 0, 7947 /* 1160 */ 'S', 'D', 'C', '2', 0, 7948 /* 1165 */ 'D', 'M', 'F', 'C', '2', 0, 7949 /* 1171 */ 'D', 'M', 'T', 'C', '2', 0, 7950 /* 1177 */ 'L', 'W', 'C', '2', 0, 7951 /* 1182 */ 'S', 'W', 'C', '2', 0, 7952 /* 1187 */ 'G', '_', 'F', 'L', 'O', 'G', '2', 0, 7953 /* 1195 */ 'M', 'T', 'M', '2', 0, 7954 /* 1200 */ 'M', 'T', 'P', '2', 0, 7955 /* 1205 */ 'G', '_', 'F', 'E', 'X', 'P', '2', 0, 7956 /* 1213 */ 'S', 'H', 'R', 'A', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0, 7957 /* 1226 */ 'C', 'M', 'P', 'G', 'D', 'U', '_', 'L', 'E', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0, 7958 /* 1244 */ 'S', 'U', 'B', 'U', 'H', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0, 7959 /* 1258 */ 'A', 'D', 'D', 'U', 'H', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0, 7960 /* 1272 */ 'C', 'M', 'P', 'G', 'D', 'U', '_', 'E', 'Q', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0, 7961 /* 1290 */ 'S', 'H', 'R', 'A', '_', 'R', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0, 7962 /* 1305 */ 'S', 'U', 'B', 'U', 'H', '_', 'R', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0, 7963 /* 1321 */ 'A', 'D', 'D', 'U', 'H', '_', 'R', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0, 7964 /* 1337 */ 'S', 'H', 'R', 'A', 'V', '_', 'R', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0, 7965 /* 1353 */ 'A', 'B', 'S', 'Q', '_', 'S', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0, 7966 /* 1368 */ 'C', 'M', 'P', 'G', 'D', 'U', '_', 'L', 'T', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0, 7967 /* 1386 */ 'S', 'H', 'R', 'A', 'V', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0, 7968 /* 1400 */ 'P', 'R', 'E', 'P', 'E', 'N', 'D', '_', 'M', 'M', 'R', '2', 0, 7969 /* 1413 */ 'A', 'P', 'P', 'E', 'N', 'D', '_', 'M', 'M', 'R', '2', 0, 7970 /* 1425 */ 'P', 'R', 'E', 'C', 'R', '_', 'Q', 'B', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, 7971 /* 1442 */ 'S', 'U', 'B', 'Q', 'H', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, 7972 /* 1456 */ 'A', 'D', 'D', 'Q', 'H', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, 7973 /* 1470 */ 'S', 'H', 'R', 'L', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, 7974 /* 1483 */ 'M', 'U', 'L', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, 7975 /* 1495 */ 'S', 'U', 'B', 'Q', 'H', '_', 'R', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, 7976 /* 1511 */ 'A', 'D', 'D', 'Q', 'H', '_', 'R', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, 7977 /* 1527 */ 'M', 'U', 'L', '_', 'S', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, 7978 /* 1541 */ 'M', 'U', 'L', 'Q', '_', 'S', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, 7979 /* 1556 */ 'S', 'U', 'B', 'U', '_', 'S', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, 7980 /* 1571 */ 'A', 'D', 'D', 'U', '_', 'S', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, 7981 /* 1586 */ 'S', 'U', 'B', 'U', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, 7982 /* 1599 */ 'A', 'D', 'D', 'U', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, 7983 /* 1612 */ 'S', 'H', 'R', 'L', 'V', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, 7984 /* 1626 */ 'D', 'P', 'A', '_', 'W', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, 7985 /* 1640 */ 'M', 'U', 'L', 'S', 'A', '_', 'W', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, 7986 /* 1656 */ 'D', 'P', 'A', 'Q', 'X', '_', 'S', 'A', '_', 'W', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, 7987 /* 1675 */ 'D', 'P', 'S', 'Q', 'X', '_', 'S', 'A', '_', 'W', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, 7988 /* 1694 */ 'D', 'P', 'S', '_', 'W', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, 7989 /* 1708 */ 'D', 'P', 'A', 'Q', 'X', '_', 'S', '_', 'W', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, 7990 /* 1726 */ 'D', 'P', 'S', 'Q', 'X', '_', 'S', '_', 'W', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, 7991 /* 1744 */ 'D', 'P', 'A', 'X', '_', 'W', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, 7992 /* 1759 */ 'D', 'P', 'S', 'X', '_', 'W', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, 7993 /* 1774 */ 'B', 'A', 'L', 'I', 'G', 'N', '_', 'M', 'M', 'R', '2', 0, 7994 /* 1786 */ 'P', 'R', 'E', 'C', 'R', '_', 'S', 'R', 'A', '_', 'P', 'H', '_', 'W', '_', 'M', 'M', 'R', '2', 0, 7995 /* 1806 */ 'P', 'R', 'E', 'C', 'R', '_', 'S', 'R', 'A', '_', 'R', '_', 'P', 'H', '_', 'W', '_', 'M', 'M', 'R', '2', 0, 7996 /* 1828 */ 'S', 'U', 'B', 'Q', 'H', '_', 'W', '_', 'M', 'M', 'R', '2', 0, 7997 /* 1841 */ 'A', 'D', 'D', 'Q', 'H', '_', 'W', '_', 'M', 'M', 'R', '2', 0, 7998 /* 1854 */ 'S', 'U', 'B', 'Q', 'H', '_', 'R', '_', 'W', '_', 'M', 'M', 'R', '2', 0, 7999 /* 1869 */ 'A', 'D', 'D', 'Q', 'H', '_', 'R', '_', 'W', '_', 'M', 'M', 'R', '2', 0, 8000 /* 1884 */ 'M', 'U', 'L', 'Q', '_', 'R', 'S', '_', 'W', '_', 'M', 'M', 'R', '2', 0, 8001 /* 1899 */ 'M', 'U', 'L', 'Q', '_', 'S', '_', 'W', '_', 'M', 'M', 'R', '2', 0, 8002 /* 1913 */ 'L', 'D', 'C', '3', 0, 8003 /* 1918 */ 'S', 'D', 'C', '3', 0, 8004 /* 1923 */ 'L', 'W', 'C', '3', 0, 8005 /* 1928 */ 'S', 'W', 'C', '3', 0, 8006 /* 1933 */ 'B', 'P', 'O', 'S', 'G', 'E', '3', '2', 'C', '_', 'M', 'M', 'R', '3', 0, 8007 /* 1948 */ 'L', 'D', 'C', '1', '6', '4', 0, 8008 /* 1955 */ 'S', 'D', 'C', '1', '6', '4', 0, 8009 /* 1962 */ 'L', 'D', 'X', 'C', '1', '6', '4', 0, 8010 /* 1970 */ 'S', 'D', 'X', 'C', '1', '6', '4', 0, 8011 /* 1978 */ 'L', 'U', 'X', 'C', '1', '6', '4', 0, 8012 /* 1986 */ 'S', 'U', 'X', 'C', '1', '6', '4', 0, 8013 /* 1994 */ 'S', 'E', 'B', '6', '4', 0, 8014 /* 2000 */ 'T', 'A', 'I', 'L', 'C', 'A', 'L', 'L', 'R', 'E', 'G', 'H', 'B', '6', '4', 0, 8015 /* 2016 */ 'J', 'R', '_', 'H', 'B', '6', '4', 0, 8016 /* 2024 */ 'J', 'A', 'L', 'R', '_', 'H', 'B', '6', '4', 0, 8017 /* 2034 */ 'L', 'B', '6', '4', 0, 8018 /* 2039 */ 'S', 'B', '6', '4', 0, 8019 /* 2044 */ 'L', 'O', 'A', 'D', '_', 'A', 'C', 'C', '6', '4', 0, 8020 /* 2055 */ 'S', 'T', 'O', 'R', 'E', '_', 'A', 'C', 'C', '6', '4', 0, 8021 /* 2067 */ 'B', 'G', 'E', 'C', '6', '4', 0, 8022 /* 2074 */ 'B', 'N', 'E', 'C', '6', '4', 0, 8023 /* 2081 */ 'J', 'I', 'C', '6', '4', 0, 8024 /* 2087 */ 'J', 'I', 'A', 'L', 'C', '6', '4', 0, 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10129 /* 24657 */ 'V', '3', 'M', 'U', 'L', 'U', 0, 10130 /* 24664 */ 'D', 'M', 'U', 'L', 'U', 0, 10131 /* 24670 */ 'V', 'M', 'U', 'L', 'U', 0, 10132 /* 24676 */ 'D', 'I', 'N', 'S', 'U', 0, 10133 /* 24682 */ 'B', 'G', 'T', 'U', 0, 10134 /* 24687 */ 'B', 'L', 'T', 'U', 0, 10135 /* 24692 */ 'T', 'L', 'T', 'U', 0, 10136 /* 24697 */ 'D', 'E', 'X', 'T', 'U', 0, 10137 /* 24703 */ 'D', 'D', 'I', 'V', 'U', 0, 10138 /* 24709 */ 'D', 'S', 'R', 'A', 'V', 0, 10139 /* 24715 */ 'B', 'I', 'T', 'R', 'E', 'V', 0, 10140 /* 24722 */ 'D', 'D', 'I', 'V', 0, 10141 /* 24727 */ 'G', '_', 'F', 'D', 'I', 'V', 0, 10142 /* 24734 */ 'G', '_', 'S', 'T', 'R', 'I', 'C', 'T', '_', 'F', 'D', 'I', 'V', 0, 10143 /* 24748 */ 'P', 's', 'e', 'u', 'd', 'o', 'D', 'S', 'D', 'I', 'V', 0, 10144 /* 24760 */ 'G', '_', 'S', 'D', 'I', 'V', 0, 10145 /* 24767 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'D', 'I', 'V', 0, 10146 /* 24778 */ 'P', 's', 'e', 'u', 'd', 'o', 'D', 'U', 'D', 'I', 'V', 0, 10147 /* 24790 */ 'G', '_', 'U', 'D', 'I', 'V', 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25363 */ 'S', 'P', 'L', 'A', 'T', 'I', '_', 'W', 0, 10221 /* 25372 */ 'B', 'S', 'E', 'T', 'I', '_', 'W', 0, 10222 /* 25380 */ 'S', 'U', 'B', 'V', 'I', '_', 'W', 0, 10223 /* 25388 */ 'A', 'D', 'D', 'V', 'I', '_', 'W', 0, 10224 /* 25396 */ 'F', 'I', 'L', 'L', '_', 'W', 0, 10225 /* 25403 */ 'S', 'L', 'L', '_', 'W', 0, 10226 /* 25409 */ 'F', 'E', 'X', 'U', 'P', 'L', '_', 'W', 0, 10227 /* 25418 */ 'F', 'F', 'Q', 'L', '_', 'W', 0, 10228 /* 25425 */ 'S', 'R', 'L', '_', 'W', 0, 10229 /* 25431 */ 'B', 'I', 'N', 'S', 'L', '_', 'W', 0, 10230 /* 25439 */ 'F', 'M', 'U', 'L', '_', 'W', 0, 10231 /* 25446 */ 'I', 'L', 'V', 'L', '_', 'W', 0, 10232 /* 25453 */ 'D', 'P', 'A', 'Q', '_', 'S', 'A', '_', 'L', '_', 'W', 0, 10233 /* 25465 */ 'D', 'P', 'S', 'Q', '_', 'S', 'A', '_', 'L', '_', 'W', 0, 10234 /* 25477 */ 'F', 'M', 'I', 'N', '_', 'W', 0, 10235 /* 25484 */ 'F', 'C', 'U', 'N', '_', 'W', 0, 10236 /* 25491 */ 'F', 'S', 'U', 'N', '_', 'W', 0, 10237 /* 25498 */ 'F', 'E', 'X', 'D', 'O', '_', 'W', 0, 10238 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'C', 'T', 'T', 'Z', 0, 10391 /* 26820 */ 'S', 'e', 'l', 'B', 'n', 'e', 'Z', 0, 10392 /* 26828 */ 'S', 'e', 'l', 'B', 'e', 'q', 'Z', 0, 10393 /* 26836 */ 'J', 'a', 'l', 'O', 'n', 'e', 'R', 'e', 'g', 0, 10394 /* 26846 */ 'J', 'a', 'l', 'T', 'w', 'o', 'R', 'e', 'g', 0, 10395 /* 26856 */ 'P', 's', 'e', 'u', 'd', 'o', 'I', 'n', 'd', 'i', 'r', 'e', 'c', 't', 'H', 'a', 'z', 'a', 'r', 'd', 'B', 'r', 'a', 'n', 'c', 'h', 0, 10396 /* 26883 */ 'P', 's', 'e', 'u', 'd', 'o', 'I', 'n', 'd', 'i', 'r', 'e', 'c', 't', 'B', 'r', 'a', 'n', 'c', 'h', 0, 10397 /* 26904 */ 'U', 'l', 'h', 0, 10398 /* 26908 */ 'U', 's', 'h', 0, 10399 /* 26912 */ 'D', 'A', 'D', 'D', 'i', 0, 10400 /* 26918 */ 'A', 'N', 'D', 'i', 0, 10401 /* 26923 */ 'S', 'N', 'E', 'i', 0, 10402 /* 26928 */ 'S', 'E', 'Q', 'i', 0, 10403 /* 26933 */ 'X', 'O', 'R', 'i', 0, 10404 /* 26938 */ 'S', 'L', 'T', 'i', 0, 10405 /* 26943 */ 'L', 'O', 'N', 'G', '_', 'B', 'R', 'A', 'N', 'C', 'H', '_', 'L', 'U', 'i', 0, 10406 /* 26959 */ 'S', 'e', 'l', 'T', 'B', 't', 'n', 'e', 'Z', 'C', 'm', 'p', 'i', 0, 10407 /* 26973 */ 'S', 'e', 'l', 'T', 'B', 't', 'e', 'q', 'Z', 'C', 'm', 'p', 'i', 0, 10408 /* 26987 */ 'S', 'e', 'l', 'T', 'B', 't', 'n', 'e', 'Z', 'S', 'l', 't', 'i', 0, 10409 /* 27001 */ 'S', 'e', 'l', 'T', 'B', 't', 'e', 'q', 'Z', 'S', 'l', 't', 'i', 0, 10410 /* 27015 */ 'S', 'G', 'E', 'I', 'm', 'm', 0, 10411 /* 27022 */ 'S', 'L', 'E', 'I', 'm', 'm', 0, 10412 /* 27029 */ 'D', 'R', 'O', 'L', 'I', 'm', 'm', 0, 10413 /* 27037 */ 'N', 'O', 'R', 'I', 'm', 'm', 0, 10414 /* 27044 */ 'D', 'R', 'O', 'R', 'I', 'm', 'm', 0, 10415 /* 27052 */ 'S', 'G', 'T', 'I', 'm', 'm', 0, 10416 /* 27059 */ 'S', 'G', 'E', 'U', 'I', 'm', 'm', 0, 10417 /* 27067 */ 'S', 'L', 'E', 'U', 'I', 'm', 'm', 0, 10418 /* 27075 */ 'S', 'G', 'T', 'U', 'I', 'm', 'm', 0, 10419 /* 27083 */ 'B', 'n', 'e', 'I', 'm', 'm', 0, 10420 /* 27090 */ 'B', 'e', 'q', 'I', 'm', 'm', 0, 10421 /* 27097 */ 'P', 's', 'e', 'u', 'd', 'o', 'R', 'e', 't', 'u', 'r', 'n', 0, 10422 /* 27110 */ 'J', 'A', 'L', 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'c', 'r', 'o', 0, 10436 /* 27275 */ 'D', 'U', 'R', 'e', 'm', 'I', 'M', 'a', 'c', 'r', 'o', 0, 10437 /* 27287 */ 'D', 'S', 'D', 'i', 'v', 'I', 'M', 'a', 'c', 'r', 'o', 0, 10438 /* 27299 */ 'D', 'U', 'D', 'i', 'v', 'I', 'M', 'a', 'c', 'r', 'o', 0, 10439 /* 27311 */ 'D', 'M', 'U', 'L', 'M', 'a', 'c', 'r', 'o', 0, 10440 /* 27321 */ 'D', 'M', 'U', 'L', 'O', 'M', 'a', 'c', 'r', 'o', 0, 10441 /* 27332 */ 'S', 'E', 'Q', 'M', 'a', 'c', 'r', 'o', 0, 10442 /* 27341 */ 'A', 'B', 'S', 'M', 'a', 'c', 'r', 'o', 0, 10443 /* 27350 */ 'D', 'M', 'U', 'L', 'O', 'U', 'M', 'a', 'c', 'r', 'o', 0, 10444 /* 27362 */ 'D', 'S', 'R', 'e', 'm', 'M', 'a', 'c', 'r', 'o', 0, 10445 /* 27373 */ 'D', 'U', 'R', 'e', 'm', 'M', 'a', 'c', 'r', 'o', 0, 10446 /* 27384 */ 'B', 'G', 'E', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0, 10447 /* 27396 */ 'B', 'L', 'E', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0, 10448 /* 27408 */ 'B', 'G', 'E', 'L', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0, 10449 /* 27421 */ 'B', 'L', 'E', 'L', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0, 10450 /* 27434 */ 'B', 'N', 'E', 'L', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0, 10451 /* 27447 */ 'B', 'E', 'Q', 'L', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0, 10452 /* 27460 */ 'B', 'G', 'T', 'L', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0, 10453 /* 27473 */ 'B', 'L', 'T', 'L', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0, 10454 /* 27486 */ 'B', 'G', 'E', 'U', 'L', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0, 10455 /* 27500 */ 'B', 'L', 'E', 'U', 'L', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0, 10456 /* 27514 */ 'D', 'M', 'U', 'L', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0, 10457 /* 27527 */ 'B', 'G', 'T', 'U', 'L', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0, 10458 /* 27541 */ 'B', 'L', 'T', 'U', 'L', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0, 10459 /* 27555 */ 'B', 'G', 'T', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0, 10460 /* 27567 */ 'B', 'L', 'T', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0, 10461 /* 27579 */ 'B', 'G', 'E', 'U', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0, 10462 /* 27592 */ 'B', 'L', 'E', 'U', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0, 10463 /* 27605 */ 'B', 'G', 'T', 'U', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0, 10464 /* 27618 */ 'B', 'L', 'T', 'U', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0, 10465 /* 27631 */ 'D', 'S', 'D', 'i', 'v', 'M', 'a', 'c', 'r', 'o', 0, 10466 /* 27642 */ 'D', 'U', 'D', 'i', 'v', 'M', 'a', 'c', 'r', 'o', 0, 10467 /* 27653 */ 'L', 'O', 'N', 'G', '_', 'B', 'R', 'A', 'N', 'C', 'H', '_', 'L', 'U', 'i', '2', 'O', 'p', 0, 10468 /* 27672 */ 'L', 'O', 'N', 'G', '_', 'B', 'R', 'A', 'N', 'C', 'H', '_', 'D', 'A', 'D', 'D', 'i', 'u', '2', 'O', 'p', 0, 10469 /* 27694 */ 'L', 'O', 'N', 'G', '_', 'B', 'R', 'A', 'N', 'C', 'H', '_', 'A', 'D', 'D', 'i', 'u', '2', 'O', 'p', 0, 10470 /* 27715 */ 'S', 'e', 'l', 'T', 'B', 't', 'n', 'e', 'Z', 'C', 'm', 'p', 0, 10471 /* 27728 */ 'S', 'e', 'l', 'T', 'B', 't', 'e', 'q', 'Z', 'C', 'm', 'p', 0, 10472 /* 27741 */ 'S', 'a', 'a', 'A', 'd', 'd', 'r', 0, 10473 /* 27749 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'D', 'i', 'u', 0, 10490 /* 27901 */ 'S', 'L', 'T', 'i', 'u', 0, 10491 /* 27907 */ 'S', 'e', 'l', 'T', 'B', 't', 'n', 'e', 'Z', 'S', 'l', 't', 'i', 'u', 0, 10492 /* 27922 */ 'S', 'e', 'l', 'T', 'B', 't', 'e', 'q', 'Z', 'S', 'l', 't', 'i', 'u', 0, 10493 /* 27937 */ 'S', 'e', 'l', 'T', 'B', 't', 'n', 'e', 'Z', 'S', 'l', 't', 'u', 0, 10494 /* 27951 */ 'S', 'e', 'l', 'T', 'B', 't', 'e', 'q', 'Z', 'S', 'l', 't', 'u', 0, 10495 /* 27965 */ 'U', 'l', 'w', 0, 10496 /* 27969 */ 'U', 's', 'w', 0, 10497 0 10498}; 10499 10500extern const unsigned MipsInstrNameIndices[] = { 10501 15358U, 20887U, 22673U, 21162U, 15706U, 15687U, 15715U, 15967U, 10502 13725U, 13740U, 13605U, 13779U, 23227U, 13484U, 24498U, 13623U, 10503 15354U, 15696U, 13233U, 26718U, 13355U, 24402U, 11679U, 13180U, 10504 13221U, 22124U, 15939U, 24331U, 11769U, 22544U, 13842U, 24320U, 10505 13408U, 22294U, 22281U, 22718U, 24150U, 24182U, 15871U, 15918U, 10506 15891U, 15747U, 22707U, 24539U, 24569U, 20987U, 11562U, 10295U, 10507 16107U, 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24601U, 22494U, 10745 19287U, 20199U, 11008U, 13086U, 15264U, 26430U, 294U, 16428U, 10746 2277U, 22382U, 19202U, 17995U, 14713U, 25558U, 23398U, 19738U, 10747 15773U, 18876U, 22835U, 19484U, 15799U, 18908U, 22861U, 19516U, 10748 11818U, 6267U, 23368U, 7203U, 10712U, 12597U, 14893U, 25903U, 10749 10904U, 12962U, 15151U, 26297U, 10348U, 11852U, 14466U, 25033U, 10750 13141U, 6733U, 23971U, 10791U, 12705U, 15000U, 7742U, 26080U, 10751 10983U, 13070U, 15239U, 26405U, 10U, 5345U, 98U, 2184U, 10752 16288U, 5387U, 1166U, 5427U, 16U, 16242U, 5355U, 245U, 10753 16364U, 2193U, 16900U, 5437U, 22U, 16251U, 15336U, 17367U, 10754 2844U, 22422U, 19214U, 18647U, 22072U, 17432U, 3289U, 22457U, 10755 19238U, 19036U, 23087U, 11805U, 6255U, 23361U, 7191U, 10694U, 10756 12579U, 14875U, 25885U, 10886U, 12944U, 15133U, 26279U, 10331U, 10757 11834U, 14449U, 25015U, 12278U, 6477U, 23651U, 10721U, 12606U, 10758 14902U, 7461U, 25921U, 10913U, 12971U, 15160U, 26306U, 11765U, 10759 10239U, 17910U, 24608U, 7851U, 6246U, 10661U, 12546U, 14842U, 10760 25852U, 10853U, 12911U, 15100U, 26246U, 17339U, 5598U, 19096U, 10761 7063U, 24874U, 362U, 16517U, 2345U, 15466U, 2980U, 18714U, 10762 23518U, 19813U, 2222U, 15444U, 2873U, 23339U, 409U, 16552U, 10763 2392U, 15492U, 3010U, 18724U, 23565U, 19842U, 626U, 16782U, 10764 2666U, 15542U, 3184U, 18734U, 23878U, 20026U, 2235U, 15455U, 10765 2886U, 23350U, 420U, 16566U, 2403U, 15501U, 3021U, 18744U, 10766 23574U, 19854U, 10290U, 12058U, 6368U, 23495U, 7328U, 14730U, 10767 25575U, 24589U, 22484U, 19274U, 20184U, 11000U, 13078U, 15256U, 10768 26422U, 275U, 16403U, 2258U, 22373U, 19190U, 17926U, 14704U, 10769 25549U, 23383U, 19717U, 50U, 5377U, 135U, 2213U, 16926U, 10770 16304U, 5397U, 1172U, 5459U, 37U, 16271U, 5366U, 255U, 10771 16377U, 2203U, 16913U, 5448U, 29U, 16261U, 15368U, 2866U, 10772 22448U, 19226U, 18671U, 22241U, 19122U, 22089U, 3296U, 22466U, 10773 19250U, 19053U, 66U, 198U, 1195U, 71U, 211U, 1200U, 10774 23116U, 14431U, 24639U, 7861U, 6864U, 16028U, 15811U, 18923U, 10775 22873U, 19531U, 15613U, 18795U, 22595U, 19384U, 14117U, 18403U, 10776 25754U, 1884U, 14167U, 1541U, 25956U, 1899U, 3411U, 14750U, 10777 25595U, 14355U, 18547U, 14295U, 1640U, 24273U, 22504U, 19300U, 10778 22475U, 19262U, 20163U, 27827U, 20856U, 24659U, 7882U, 11032U, 10779 13117U, 15288U, 26461U, 18988U, 6984U, 14035U, 1483U, 14722U, 10780 25567U, 8131U, 14138U, 1527U, 4850U, 4977U, 4164U, 3887U, 10781 10356U, 11875U, 14474U, 25056U, 10363U, 11882U, 14481U, 25063U, 10782 293U, 16427U, 2276U, 23397U, 19737U, 274U, 16402U, 2257U, 10783 23382U, 19716U, 22916U, 3321U, 10505U, 19562U, 7129U, 24888U, 10784 17491U, 5723U, 5045U, 5086U, 22917U, 17472U, 5713U, 3322U, 10785 10506U, 6903U, 19563U, 7130U, 24889U, 26934U, 3689U, 20790U, 10786 5185U, 14025U, 18328U, 13478U, 18133U, 6795U, 11016U, 13094U, 10787 15272U, 26438U, 10376U, 11910U, 14494U, 25091U, 10823U, 12807U, 10788 15032U, 26142U, 13993U, 18295U, 9984U, 17704U, 3373U, 3421U, 10789 22269U, 15642U, 8484U, 17592U, 18830U, 22624U, 8534U, 17629U, 10790 19419U, 15786U, 18892U, 22848U, 19500U, 15628U, 8469U, 17574U, 10791 18813U, 22610U, 8519U, 17611U, 19402U, 13937U, 18263U, 25218U, 10792 20417U, 13912U, 18247U, 25247U, 20432U, 13925U, 1425U, 25203U, 10793 1786U, 25230U, 1806U, 13618U, 13303U, 18041U, 20671U, 18180U, 10794 6806U, 8116U, 11664U, 1400U, 3392U, 3430U, 10225U, 17890U, 10795 22335U, 19154U, 23134U, 3333U, 19603U, 7171U, 7147U, 483U, 10796 16617U, 2523U, 17112U, 23683U, 19908U, 14268U, 18520U, 10207U, 10797 17866U, 14009U, 18317U, 10000U, 17726U, 12815U, 6650U, 23855U, 10798 7634U, 23093U, 24857U, 20340U, 19576U, 2445U, 6420U, 23614U, 10799 7404U, 692U, 2726U, 6689U, 20406U, 23934U, 20069U, 7685U, 10800 616U, 16769U, 2656U, 17252U, 23870U, 20015U, 4805U, 4181U, 10801 8465U, 11348U, 10756U, 12650U, 14955U, 26001U, 10959U, 13026U, 10802 15215U, 26361U, 10236U, 17313U, 5517U, 2039U, 13193U, 18017U, 10803 17904U, 5808U, 11269U, 2102U, 8054U, 11450U, 8093U, 13246U, 10804 18024U, 17956U, 6050U, 8087U, 11786U, 22199U, 17442U, 5699U, 10805 19069U, 7052U, 8146U, 87U, 1955U, 5503U, 462U, 2502U, 10806 1160U, 5417U, 8019U, 1918U, 24755U, 20267U, 15683U, 22703U, 10807 168U, 1970U, 9871U, 1994U, 17655U, 13884U, 2822U, 18223U, 10808 26796U, 3524U, 13167U, 6758U, 7973U, 23986U, 7767U, 26763U, 10809 3515U, 13152U, 6744U, 7952U, 23977U, 7753U, 12214U, 6394U, 10810 23583U, 7366U, 22582U, 26928U, 14427U, 17349U, 5610U, 2833U, 10811 13331U, 18073U, 10401U, 14519U, 25190U, 22077U, 24835U, 20310U, 10812 19044U, 14259U, 18508U, 10198U, 17854U, 14207U, 18469U, 26070U, 10813 20647U, 14001U, 18306U, 9992U, 17715U, 14128U, 18417U, 25912U, 10814 20588U, 14250U, 18496U, 10189U, 1386U, 14106U, 18389U, 10090U, 10815 1337U, 25727U, 20535U, 13904U, 18236U, 9910U, 1213U, 14074U, 10816 18376U, 10058U, 1290U, 25689U, 20511U, 14277U, 1612U, 10216U, 10817 17878U, 14017U, 1470U, 10008U, 17737U, 18579U, 6856U, 13335U, 10818 6783U, 10421U, 12103U, 14539U, 25285U, 10370U, 11904U, 14488U, 10819 25085U, 15973U, 17396U, 5655U, 1030U, 3584U, 10451U, 12118U, 10820 14554U, 25300U, 24809U, 20283U, 10583U, 12227U, 14657U, 18974U, 10821 6975U, 25403U, 24258U, 3462U, 20143U, 26938U, 3695U, 20797U, 10822 27901U, 3879U, 20878U, 27815U, 3860U, 20842U, 13400U, 26923U, 10823 10528U, 12181U, 14617U, 25363U, 10808U, 12722U, 15017U, 26097U, 10824 8551U, 10414U, 12096U, 14532U, 25278U, 10481U, 12148U, 14584U, 10825 25330U, 10616U, 12394U, 14759U, 25604U, 24710U, 20249U, 10317U, 10826 11812U, 14435U, 17648U, 25000U, 15988U, 17405U, 5666U, 10458U, 10827 12125U, 14561U, 25307U, 10497U, 12164U, 14600U, 25346U, 10630U, 10828 12414U, 14773U, 25624U, 24815U, 20291U, 10589U, 12249U, 14663U, 10829 18981U, 25425U, 22262U, 19132U, 7074U, 10839U, 12848U, 15048U, 10830 26183U, 10242U, 13969U, 1442U, 14084U, 1495U, 25698U, 1854U, 10831 25262U, 1828U, 14042U, 18341U, 14147U, 18430U, 25938U, 20600U, 10832 10948U, 13015U, 15204U, 26350U, 10772U, 12686U, 14971U, 26051U, 10833 10738U, 12632U, 14937U, 25983U, 10930U, 12997U, 15186U, 26332U, 10834 17509U, 5734U, 9960U, 1244U, 10068U, 1305U, 7831U, 14234U, 10835 1586U, 10173U, 17832U, 14187U, 1556U, 10111U, 17777U, 10545U, 10836 12198U, 14634U, 25380U, 11001U, 13079U, 15257U, 26423U, 17913U, 10837 5816U, 27794U, 20819U, 180U, 1986U, 16337U, 24949U, 17546U, 10838 5758U, 3496U, 157U, 16320U, 1182U, 5479U, 8035U, 1928U, 10839 22367U, 19181U, 13523U, 18149U, 16129U, 3277U, 13375U, 18095U, 10840 19002U, 17423U, 5688U, 16852U, 19355U, 23144U, 3347U, 13460U, 10841 18125U, 19619U, 19332U, 7101U, 192U, 16355U, 20363U, 7931U, 10842 11202U, 15306U, 18610U, 6873U, 17934U, 5973U, 15863U, 18963U, 10843 4829U, 4192U, 4290U, 4996U, 5012U, 4322U, 4260U, 5151U, 10844 5065U, 4906U, 4534U, 4918U, 4561U, 5096U, 4174U, 5130U, 10845 4267U, 5162U, 5221U, 4407U, 4466U, 22586U, 15379U, 18679U, 10846 19369U, 13317U, 15315U, 24644U, 20216U, 18625U, 24623U, 20208U, 10847 18050U, 24827U, 13645U, 18188U, 20299U, 22235U, 19105U, 22795U, 10848 19475U, 15429U, 18704U, 23127U, 19593U, 24820U, 13637U, 6816U, 10849 7911U, 22205U, 19078U, 22590U, 19376U, 15423U, 18695U, 23121U, 10850 19584U, 24262U, 15398U, 20225U, 18687U, 24692U, 20234U, 20150U, 10851 13404U, 15320U, 18633U, 18110U, 2433U, 6405U, 23604U, 7389U, 10852 680U, 2714U, 6674U, 20395U, 23924U, 20056U, 7670U, 24650U, 10853 24785U, 20275U, 24657U, 61U, 24670U, 10400U, 12074U, 14518U, 10854 25189U, 24177U, 20135U, 7792U, 22341U, 19163U, 7159U, 13871U, 10855 18215U, 6846U, 22978U, 17471U, 5712U, 3327U, 10512U, 6902U, 10856 19569U, 7138U, 24894U, 26933U, 3688U, 20789U, 5196U, 11599U, 10857}; 10858 10859static inline void InitMipsMCInstrInfo(MCInstrInfo *II) { 10860 II->InitMCInstrInfo(MipsInsts, MipsInstrNameIndices, MipsInstrNameData, nullptr, nullptr, 2848); 10861} 10862 10863} // end namespace llvm 10864#endif // GET_INSTRINFO_MC_DESC 10865 10866#ifdef GET_INSTRINFO_HEADER 10867#undef GET_INSTRINFO_HEADER 10868namespace llvm { 10869struct MipsGenInstrInfo : public TargetInstrInfo { 10870 explicit MipsGenInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u); 10871 ~MipsGenInstrInfo() override = default; 10872 10873}; 10874} // end namespace llvm 10875#endif // GET_INSTRINFO_HEADER 10876 10877#ifdef GET_INSTRINFO_HELPER_DECLS 10878#undef GET_INSTRINFO_HELPER_DECLS 10879 10880 10881#endif // GET_INSTRINFO_HELPER_DECLS 10882 10883#ifdef GET_INSTRINFO_HELPERS 10884#undef GET_INSTRINFO_HELPERS 10885 10886#endif // GET_INSTRINFO_HELPERS 10887 10888#ifdef GET_INSTRINFO_CTOR_DTOR 10889#undef GET_INSTRINFO_CTOR_DTOR 10890namespace llvm { 10891extern const MCInstrDesc MipsInsts[]; 10892extern const unsigned MipsInstrNameIndices[]; 10893extern const char MipsInstrNameData[]; 10894MipsGenInstrInfo::MipsGenInstrInfo(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode) 10895 : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) { 10896 InitMCInstrInfo(MipsInsts, MipsInstrNameIndices, MipsInstrNameData, nullptr, nullptr, 2848); 10897} 10898} // end namespace llvm 10899#endif // GET_INSTRINFO_CTOR_DTOR 10900 10901#ifdef GET_INSTRINFO_OPERAND_ENUM 10902#undef GET_INSTRINFO_OPERAND_ENUM 10903namespace llvm { 10904namespace Mips { 10905namespace OpName { 10906enum { 10907 OPERAND_LAST 10908}; 10909} // end namespace OpName 10910} // end namespace Mips 10911} // end namespace llvm 10912#endif //GET_INSTRINFO_OPERAND_ENUM 10913 10914#ifdef GET_INSTRINFO_NAMED_OPS 10915#undef GET_INSTRINFO_NAMED_OPS 10916namespace llvm { 10917namespace Mips { 10918LLVM_READONLY 10919int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) { 10920 return -1; 10921} 10922} // end namespace Mips 10923} // end namespace llvm 10924#endif //GET_INSTRINFO_NAMED_OPS 10925 10926#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM 10927#undef GET_INSTRINFO_OPERAND_TYPES_ENUM 10928namespace llvm { 10929namespace Mips { 10930namespace OpTypes { 10931enum OperandType { 10932 InvertedImOperand = 0, 10933 InvertedImOperand64 = 1, 10934 PtrRC = 2, 10935 brtarget = 3, 10936 brtarget10_mm = 4, 10937 brtarget1SImm16 = 5, 10938 brtarget21 = 6, 10939 brtarget21_mm = 7, 10940 brtarget26 = 8, 10941 brtarget26_mm = 9, 10942 brtarget7_mm = 10, 10943 brtarget_lsl2_mm = 11, 10944 brtarget_mm = 12, 10945 brtargetr6 = 13, 10946 calloffset16 = 14, 10947 calltarget = 15, 10948 calltarget_mm = 16, 10949 condcode = 17, 10950 cpinst_operand = 18, 10951 f32imm = 19, 10952 f64imm = 20, 10953 i16imm = 21, 10954 i1imm = 22, 10955 i32imm = 23, 10956 i64imm = 24, 10957 i8imm = 25, 10958 imm64 = 26, 10959 jmpoffset16 = 27, 10960 jmptarget = 28, 10961 jmptarget_mm = 29, 10962 li16_imm = 30, 10963 mem = 31, 10964 mem16 = 32, 10965 mem16_ea = 33, 10966 mem16sp = 34, 10967 mem_ea = 35, 10968 mem_mm_11 = 36, 10969 mem_mm_12 = 37, 10970 mem_mm_16 = 38, 10971 mem_mm_4 = 39, 10972 mem_mm_4_lsl1 = 40, 10973 mem_mm_4_lsl2 = 41, 10974 mem_mm_4sp = 42, 10975 mem_mm_9 = 43, 10976 mem_mm_gp_simm7_lsl2 = 44, 10977 mem_mm_sp_imm5_lsl2 = 45, 10978 mem_msa = 46, 10979 mem_simm10 = 47, 10980 mem_simm10_lsl1 = 48, 10981 mem_simm10_lsl2 = 49, 10982 mem_simm10_lsl3 = 50, 10983 mem_simm11 = 51, 10984 mem_simm12 = 52, 10985 mem_simm16 = 53, 10986 mem_simm9 = 54, 10987 mem_simm9_exp = 55, 10988 mem_simmptr = 56, 10989 pcrel16 = 57, 10990 ptype0 = 58, 10991 ptype1 = 59, 10992 ptype2 = 60, 10993 ptype3 = 61, 10994 ptype4 = 62, 10995 ptype5 = 63, 10996 reglist = 64, 10997 reglist16 = 65, 10998 simm10 = 66, 10999 simm10_64 = 67, 11000 simm10_lsl1 = 68, 11001 simm10_lsl2 = 69, 11002 simm10_lsl3 = 70, 11003 simm11 = 71, 11004 simm12 = 72, 11005 simm16 = 73, 11006 simm16_64 = 74, 11007 simm16_relaxed = 75, 11008 simm18_lsl3 = 76, 11009 simm19_lsl2 = 77, 11010 simm23_lsl2 = 78, 11011 simm32 = 79, 11012 simm32_relaxed = 80, 11013 simm3_lsa2 = 81, 11014 simm4 = 82, 11015 simm5 = 83, 11016 simm6 = 84, 11017 simm7_lsl2 = 85, 11018 simm9 = 86, 11019 simm9_addiusp = 87, 11020 size_ins = 88, 11021 type0 = 89, 11022 type1 = 90, 11023 type2 = 91, 11024 type3 = 92, 11025 type4 = 93, 11026 type5 = 94, 11027 uimm1 = 95, 11028 uimm10 = 96, 11029 uimm16 = 97, 11030 uimm16_64 = 98, 11031 uimm16_64_relaxed = 99, 11032 uimm16_altrelaxed = 100, 11033 uimm16_relaxed = 101, 11034 uimm1_ptr = 102, 11035 uimm2 = 103, 11036 uimm20 = 104, 11037 uimm26 = 105, 11038 uimm2_plus1 = 106, 11039 uimm2_ptr = 107, 11040 uimm3 = 108, 11041 uimm32_coerced = 109, 11042 uimm3_ptr = 110, 11043 uimm3_shift = 111, 11044 uimm4 = 112, 11045 uimm4_andi = 113, 11046 uimm4_ptr = 114, 11047 uimm5 = 115, 11048 uimm5_64 = 116, 11049 uimm5_64_report_uimm6 = 117, 11050 uimm5_inssize_plus1 = 118, 11051 uimm5_lsl2 = 119, 11052 uimm5_plus1 = 120, 11053 uimm5_plus1_report_uimm6 = 121, 11054 uimm5_plus32 = 122, 11055 uimm5_plus32_normalize = 123, 11056 uimm5_plus32_normalize_64 = 124, 11057 uimm5_plus33 = 125, 11058 uimm5_report_uimm6 = 126, 11059 uimm6 = 127, 11060 uimm6_lsl2 = 128, 11061 uimm7 = 129, 11062 uimm8 = 130, 11063 uimm_range_2_64 = 131, 11064 uimmz = 132, 11065 untyped_imm_0 = 133, 11066 vsplat_simm10 = 134, 11067 vsplat_simm5 = 135, 11068 vsplat_uimm1 = 136, 11069 vsplat_uimm2 = 137, 11070 vsplat_uimm3 = 138, 11071 vsplat_uimm4 = 139, 11072 vsplat_uimm5 = 140, 11073 vsplat_uimm6 = 141, 11074 vsplat_uimm8 = 142, 11075 ACC64DSPOpnd = 143, 11076 AFGR64Opnd = 144, 11077 CCROpnd = 145, 11078 COP0Opnd = 146, 11079 COP2Opnd = 147, 11080 COP3Opnd = 148, 11081 DSPROpnd = 149, 11082 FCCRegsOpnd = 150, 11083 FGR32Opnd = 151, 11084 FGR64Opnd = 152, 11085 FGRCCOpnd = 153, 11086 GPR32NonZeroOpnd = 154, 11087 GPR32Opnd = 155, 11088 GPR32ZeroOpnd = 156, 11089 GPR64Opnd = 157, 11090 GPRMM16Opnd = 158, 11091 GPRMM16OpndMoveP = 159, 11092 GPRMM16OpndMovePPairFirst = 160, 11093 GPRMM16OpndMovePPairSecond = 161, 11094 GPRMM16OpndZero = 162, 11095 HI32DSPOpnd = 163, 11096 HWRegsOpnd = 164, 11097 LO32DSPOpnd = 165, 11098 MSA128BOpnd = 166, 11099 MSA128CROpnd = 167, 11100 MSA128DOpnd = 168, 11101 MSA128F16Opnd = 169, 11102 MSA128HOpnd = 170, 11103 MSA128WOpnd = 171, 11104 StrictlyAFGR64Opnd = 172, 11105 StrictlyFGR32Opnd = 173, 11106 StrictlyFGR64Opnd = 174, 11107 ACC128 = 175, 11108 ACC64 = 176, 11109 ACC64DSP = 177, 11110 AFGR64 = 178, 11111 CCR = 179, 11112 COP0 = 180, 11113 COP2 = 181, 11114 COP3 = 182, 11115 CPU16Regs = 183, 11116 CPU16RegsPlusSP = 184, 11117 CPURAReg = 185, 11118 CPUSPReg = 186, 11119 DSPCC = 187, 11120 DSPR = 188, 11121 FCC = 189, 11122 FGR32 = 190, 11123 FGR64 = 191, 11124 FGRCC = 192, 11125 GP32 = 193, 11126 GP64 = 194, 11127 GPR32 = 195, 11128 GPR32NONZERO = 196, 11129 GPR32ZERO = 197, 11130 GPR64 = 198, 11131 GPRMM16 = 199, 11132 GPRMM16MoveP = 200, 11133 GPRMM16MovePPairFirst = 201, 11134 GPRMM16MovePPairSecond = 202, 11135 GPRMM16Zero = 203, 11136 HI32 = 204, 11137 HI32DSP = 205, 11138 HI64 = 206, 11139 HWRegs = 207, 11140 LO32 = 208, 11141 LO32DSP = 209, 11142 LO64 = 210, 11143 MSA128B = 211, 11144 MSA128D = 212, 11145 MSA128F16 = 213, 11146 MSA128H = 214, 11147 MSA128W = 215, 11148 MSA128WEvens = 216, 11149 MSACtrl = 217, 11150 OCTEON_MPL = 218, 11151 OCTEON_P = 219, 11152 SP32 = 220, 11153 SP64 = 221, 11154 OPERAND_TYPE_LIST_END 11155}; 11156} // end namespace OpTypes 11157} // end namespace Mips 11158} // end namespace llvm 11159#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM 11160 11161#ifdef GET_INSTRINFO_OPERAND_TYPE 11162#undef GET_INSTRINFO_OPERAND_TYPE 11163namespace llvm { 11164namespace Mips { 11165LLVM_READONLY 11166static int getOperandType(uint16_t Opcode, uint16_t OpIdx) { 11167 const uint16_t Offsets[] = { 11168 /* PHI */ 11169 0, 11170 /* INLINEASM */ 11171 1, 11172 /* INLINEASM_BR */ 11173 1, 11174 /* CFI_INSTRUCTION */ 11175 1, 11176 /* EH_LABEL */ 11177 2, 11178 /* GC_LABEL */ 11179 3, 11180 /* ANNOTATION_LABEL */ 11181 4, 11182 /* KILL */ 11183 5, 11184 /* EXTRACT_SUBREG */ 11185 5, 11186 /* INSERT_SUBREG */ 11187 8, 11188 /* IMPLICIT_DEF */ 11189 12, 11190 /* SUBREG_TO_REG */ 11191 13, 11192 /* COPY_TO_REGCLASS */ 11193 17, 11194 /* DBG_VALUE */ 11195 20, 11196 /* DBG_VALUE_LIST */ 11197 20, 11198 /* DBG_INSTR_REF */ 11199 20, 11200 /* DBG_PHI */ 11201 20, 11202 /* DBG_LABEL */ 11203 20, 11204 /* REG_SEQUENCE */ 11205 21, 11206 /* COPY */ 11207 23, 11208 /* BUNDLE */ 11209 25, 11210 /* LIFETIME_START */ 11211 25, 11212 /* LIFETIME_END */ 11213 26, 11214 /* PSEUDO_PROBE */ 11215 27, 11216 /* ARITH_FENCE */ 11217 31, 11218 /* STACKMAP */ 11219 33, 11220 /* FENTRY_CALL */ 11221 35, 11222 /* PATCHPOINT */ 11223 35, 11224 /* LOAD_STACK_GUARD */ 11225 41, 11226 /* PREALLOCATED_SETUP */ 11227 42, 11228 /* PREALLOCATED_ARG */ 11229 43, 11230 /* STATEPOINT */ 11231 46, 11232 /* LOCAL_ESCAPE */ 11233 46, 11234 /* FAULTING_OP */ 11235 48, 11236 /* PATCHABLE_OP */ 11237 49, 11238 /* PATCHABLE_FUNCTION_ENTER */ 11239 49, 11240 /* PATCHABLE_RET */ 11241 49, 11242 /* PATCHABLE_FUNCTION_EXIT */ 11243 49, 11244 /* PATCHABLE_TAIL_CALL */ 11245 49, 11246 /* PATCHABLE_EVENT_CALL */ 11247 49, 11248 /* PATCHABLE_TYPED_EVENT_CALL */ 11249 51, 11250 /* ICALL_BRANCH_FUNNEL */ 11251 54, 11252 /* MEMBARRIER */ 11253 54, 11254 /* G_ASSERT_SEXT */ 11255 54, 11256 /* G_ASSERT_ZEXT */ 11257 57, 11258 /* G_ASSERT_ALIGN */ 11259 60, 11260 /* G_ADD */ 11261 63, 11262 /* G_SUB */ 11263 66, 11264 /* G_MUL */ 11265 69, 11266 /* G_SDIV */ 11267 72, 11268 /* G_UDIV */ 11269 75, 11270 /* G_SREM */ 11271 78, 11272 /* G_UREM */ 11273 81, 11274 /* G_SDIVREM */ 11275 84, 11276 /* G_UDIVREM */ 11277 88, 11278 /* G_AND */ 11279 92, 11280 /* G_OR */ 11281 95, 11282 /* G_XOR */ 11283 98, 11284 /* G_IMPLICIT_DEF */ 11285 101, 11286 /* G_PHI */ 11287 102, 11288 /* G_FRAME_INDEX */ 11289 103, 11290 /* G_GLOBAL_VALUE */ 11291 105, 11292 /* G_EXTRACT */ 11293 107, 11294 /* G_UNMERGE_VALUES */ 11295 110, 11296 /* G_INSERT */ 11297 112, 11298 /* G_MERGE_VALUES */ 11299 116, 11300 /* G_BUILD_VECTOR */ 11301 118, 11302 /* G_BUILD_VECTOR_TRUNC */ 11303 120, 11304 /* G_CONCAT_VECTORS */ 11305 122, 11306 /* G_PTRTOINT */ 11307 124, 11308 /* G_INTTOPTR */ 11309 126, 11310 /* G_BITCAST */ 11311 128, 11312 /* G_FREEZE */ 11313 130, 11314 /* G_INTRINSIC_FPTRUNC_ROUND */ 11315 132, 11316 /* G_INTRINSIC_TRUNC */ 11317 135, 11318 /* G_INTRINSIC_ROUND */ 11319 137, 11320 /* G_INTRINSIC_LRINT */ 11321 139, 11322 /* G_INTRINSIC_ROUNDEVEN */ 11323 141, 11324 /* G_READCYCLECOUNTER */ 11325 143, 11326 /* G_LOAD */ 11327 144, 11328 /* G_SEXTLOAD */ 11329 146, 11330 /* G_ZEXTLOAD */ 11331 148, 11332 /* G_INDEXED_LOAD */ 11333 150, 11334 /* G_INDEXED_SEXTLOAD */ 11335 155, 11336 /* G_INDEXED_ZEXTLOAD */ 11337 160, 11338 /* G_STORE */ 11339 165, 11340 /* G_INDEXED_STORE */ 11341 167, 11342 /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */ 11343 172, 11344 /* G_ATOMIC_CMPXCHG */ 11345 177, 11346 /* G_ATOMICRMW_XCHG */ 11347 181, 11348 /* G_ATOMICRMW_ADD */ 11349 184, 11350 /* G_ATOMICRMW_SUB */ 11351 187, 11352 /* G_ATOMICRMW_AND */ 11353 190, 11354 /* G_ATOMICRMW_NAND */ 11355 193, 11356 /* G_ATOMICRMW_OR */ 11357 196, 11358 /* G_ATOMICRMW_XOR */ 11359 199, 11360 /* G_ATOMICRMW_MAX */ 11361 202, 11362 /* G_ATOMICRMW_MIN */ 11363 205, 11364 /* G_ATOMICRMW_UMAX */ 11365 208, 11366 /* G_ATOMICRMW_UMIN */ 11367 211, 11368 /* G_ATOMICRMW_FADD */ 11369 214, 11370 /* G_ATOMICRMW_FSUB */ 11371 217, 11372 /* G_ATOMICRMW_FMAX */ 11373 220, 11374 /* G_ATOMICRMW_FMIN */ 11375 223, 11376 /* G_ATOMICRMW_UINC_WRAP */ 11377 226, 11378 /* G_ATOMICRMW_UDEC_WRAP */ 11379 229, 11380 /* G_FENCE */ 11381 232, 11382 /* G_BRCOND */ 11383 234, 11384 /* G_BRINDIRECT */ 11385 236, 11386 /* G_INVOKE_REGION_START */ 11387 237, 11388 /* G_INTRINSIC */ 11389 237, 11390 /* G_INTRINSIC_W_SIDE_EFFECTS */ 11391 238, 11392 /* G_ANYEXT */ 11393 239, 11394 /* G_TRUNC */ 11395 241, 11396 /* G_CONSTANT */ 11397 243, 11398 /* G_FCONSTANT */ 11399 245, 11400 /* G_VASTART */ 11401 247, 11402 /* G_VAARG */ 11403 248, 11404 /* G_SEXT */ 11405 251, 11406 /* G_SEXT_INREG */ 11407 253, 11408 /* G_ZEXT */ 11409 256, 11410 /* G_SHL */ 11411 258, 11412 /* G_LSHR */ 11413 261, 11414 /* G_ASHR */ 11415 264, 11416 /* G_FSHL */ 11417 267, 11418 /* G_FSHR */ 11419 271, 11420 /* G_ROTR */ 11421 275, 11422 /* G_ROTL */ 11423 278, 11424 /* G_ICMP */ 11425 281, 11426 /* G_FCMP */ 11427 285, 11428 /* G_SELECT */ 11429 289, 11430 /* G_UADDO */ 11431 293, 11432 /* G_UADDE */ 11433 297, 11434 /* G_USUBO */ 11435 302, 11436 /* G_USUBE */ 11437 306, 11438 /* G_SADDO */ 11439 311, 11440 /* G_SADDE */ 11441 315, 11442 /* G_SSUBO */ 11443 320, 11444 /* G_SSUBE */ 11445 324, 11446 /* G_UMULO */ 11447 329, 11448 /* G_SMULO */ 11449 333, 11450 /* G_UMULH */ 11451 337, 11452 /* G_SMULH */ 11453 340, 11454 /* G_UADDSAT */ 11455 343, 11456 /* G_SADDSAT */ 11457 346, 11458 /* G_USUBSAT */ 11459 349, 11460 /* G_SSUBSAT */ 11461 352, 11462 /* G_USHLSAT */ 11463 355, 11464 /* G_SSHLSAT */ 11465 358, 11466 /* G_SMULFIX */ 11467 361, 11468 /* G_UMULFIX */ 11469 365, 11470 /* G_SMULFIXSAT */ 11471 369, 11472 /* G_UMULFIXSAT */ 11473 373, 11474 /* G_SDIVFIX */ 11475 377, 11476 /* G_UDIVFIX */ 11477 381, 11478 /* G_SDIVFIXSAT */ 11479 385, 11480 /* G_UDIVFIXSAT */ 11481 389, 11482 /* G_FADD */ 11483 393, 11484 /* G_FSUB */ 11485 396, 11486 /* G_FMUL */ 11487 399, 11488 /* G_FMA */ 11489 402, 11490 /* G_FMAD */ 11491 406, 11492 /* G_FDIV */ 11493 410, 11494 /* G_FREM */ 11495 413, 11496 /* G_FPOW */ 11497 416, 11498 /* G_FPOWI */ 11499 419, 11500 /* G_FEXP */ 11501 422, 11502 /* G_FEXP2 */ 11503 424, 11504 /* G_FLOG */ 11505 426, 11506 /* G_FLOG2 */ 11507 428, 11508 /* G_FLOG10 */ 11509 430, 11510 /* G_FNEG */ 11511 432, 11512 /* G_FPEXT */ 11513 434, 11514 /* G_FPTRUNC */ 11515 436, 11516 /* G_FPTOSI */ 11517 438, 11518 /* G_FPTOUI */ 11519 440, 11520 /* G_SITOFP */ 11521 442, 11522 /* G_UITOFP */ 11523 444, 11524 /* G_FABS */ 11525 446, 11526 /* G_FCOPYSIGN */ 11527 448, 11528 /* G_IS_FPCLASS */ 11529 451, 11530 /* G_FCANONICALIZE */ 11531 454, 11532 /* G_FMINNUM */ 11533 456, 11534 /* G_FMAXNUM */ 11535 459, 11536 /* G_FMINNUM_IEEE */ 11537 462, 11538 /* G_FMAXNUM_IEEE */ 11539 465, 11540 /* G_FMINIMUM */ 11541 468, 11542 /* G_FMAXIMUM */ 11543 471, 11544 /* G_PTR_ADD */ 11545 474, 11546 /* G_PTRMASK */ 11547 477, 11548 /* G_SMIN */ 11549 480, 11550 /* G_SMAX */ 11551 483, 11552 /* G_UMIN */ 11553 486, 11554 /* G_UMAX */ 11555 489, 11556 /* G_ABS */ 11557 492, 11558 /* G_LROUND */ 11559 494, 11560 /* G_LLROUND */ 11561 496, 11562 /* G_BR */ 11563 498, 11564 /* G_BRJT */ 11565 499, 11566 /* G_INSERT_VECTOR_ELT */ 11567 502, 11568 /* G_EXTRACT_VECTOR_ELT */ 11569 506, 11570 /* G_SHUFFLE_VECTOR */ 11571 509, 11572 /* G_CTTZ */ 11573 513, 11574 /* G_CTTZ_ZERO_UNDEF */ 11575 515, 11576 /* G_CTLZ */ 11577 517, 11578 /* G_CTLZ_ZERO_UNDEF */ 11579 519, 11580 /* G_CTPOP */ 11581 521, 11582 /* G_BSWAP */ 11583 523, 11584 /* G_BITREVERSE */ 11585 525, 11586 /* G_FCEIL */ 11587 527, 11588 /* G_FCOS */ 11589 529, 11590 /* G_FSIN */ 11591 531, 11592 /* G_FSQRT */ 11593 533, 11594 /* G_FFLOOR */ 11595 535, 11596 /* G_FRINT */ 11597 537, 11598 /* G_FNEARBYINT */ 11599 539, 11600 /* G_ADDRSPACE_CAST */ 11601 541, 11602 /* G_BLOCK_ADDR */ 11603 543, 11604 /* G_JUMP_TABLE */ 11605 545, 11606 /* G_DYN_STACKALLOC */ 11607 547, 11608 /* G_STRICT_FADD */ 11609 550, 11610 /* G_STRICT_FSUB */ 11611 553, 11612 /* G_STRICT_FMUL */ 11613 556, 11614 /* G_STRICT_FDIV */ 11615 559, 11616 /* G_STRICT_FREM */ 11617 562, 11618 /* G_STRICT_FMA */ 11619 565, 11620 /* G_STRICT_FSQRT */ 11621 569, 11622 /* G_READ_REGISTER */ 11623 571, 11624 /* G_WRITE_REGISTER */ 11625 573, 11626 /* G_MEMCPY */ 11627 575, 11628 /* G_MEMCPY_INLINE */ 11629 579, 11630 /* G_MEMMOVE */ 11631 582, 11632 /* G_MEMSET */ 11633 586, 11634 /* G_BZERO */ 11635 590, 11636 /* G_VECREDUCE_SEQ_FADD */ 11637 593, 11638 /* G_VECREDUCE_SEQ_FMUL */ 11639 596, 11640 /* G_VECREDUCE_FADD */ 11641 599, 11642 /* G_VECREDUCE_FMUL */ 11643 601, 11644 /* G_VECREDUCE_FMAX */ 11645 603, 11646 /* G_VECREDUCE_FMIN */ 11647 605, 11648 /* G_VECREDUCE_ADD */ 11649 607, 11650 /* G_VECREDUCE_MUL */ 11651 609, 11652 /* G_VECREDUCE_AND */ 11653 611, 11654 /* G_VECREDUCE_OR */ 11655 613, 11656 /* G_VECREDUCE_XOR */ 11657 615, 11658 /* G_VECREDUCE_SMAX */ 11659 617, 11660 /* G_VECREDUCE_SMIN */ 11661 619, 11662 /* G_VECREDUCE_UMAX */ 11663 621, 11664 /* G_VECREDUCE_UMIN */ 11665 623, 11666 /* G_SBFX */ 11667 625, 11668 /* G_UBFX */ 11669 629, 11670 /* ABSMacro */ 11671 633, 11672 /* ADJCALLSTACKDOWN */ 11673 635, 11674 /* ADJCALLSTACKUP */ 11675 637, 11676 /* AND_V_D_PSEUDO */ 11677 639, 11678 /* AND_V_H_PSEUDO */ 11679 642, 11680 /* AND_V_W_PSEUDO */ 11681 645, 11682 /* ATOMIC_CMP_SWAP_I16 */ 11683 648, 11684 /* ATOMIC_CMP_SWAP_I16_POSTRA */ 11685 652, 11686 /* ATOMIC_CMP_SWAP_I32 */ 11687 659, 11688 /* ATOMIC_CMP_SWAP_I32_POSTRA */ 11689 663, 11690 /* ATOMIC_CMP_SWAP_I64 */ 11691 667, 11692 /* ATOMIC_CMP_SWAP_I64_POSTRA */ 11693 671, 11694 /* ATOMIC_CMP_SWAP_I8 */ 11695 675, 11696 /* ATOMIC_CMP_SWAP_I8_POSTRA */ 11697 679, 11698 /* ATOMIC_LOAD_ADD_I16 */ 11699 686, 11700 /* ATOMIC_LOAD_ADD_I16_POSTRA */ 11701 689, 11702 /* ATOMIC_LOAD_ADD_I32 */ 11703 695, 11704 /* ATOMIC_LOAD_ADD_I32_POSTRA */ 11705 698, 11706 /* ATOMIC_LOAD_ADD_I64 */ 11707 701, 11708 /* ATOMIC_LOAD_ADD_I64_POSTRA */ 11709 704, 11710 /* ATOMIC_LOAD_ADD_I8 */ 11711 707, 11712 /* ATOMIC_LOAD_ADD_I8_POSTRA */ 11713 710, 11714 /* ATOMIC_LOAD_AND_I16 */ 11715 716, 11716 /* ATOMIC_LOAD_AND_I16_POSTRA */ 11717 719, 11718 /* ATOMIC_LOAD_AND_I32 */ 11719 725, 11720 /* ATOMIC_LOAD_AND_I32_POSTRA */ 11721 728, 11722 /* ATOMIC_LOAD_AND_I64 */ 11723 731, 11724 /* ATOMIC_LOAD_AND_I64_POSTRA */ 11725 734, 11726 /* ATOMIC_LOAD_AND_I8 */ 11727 737, 11728 /* ATOMIC_LOAD_AND_I8_POSTRA */ 11729 740, 11730 /* ATOMIC_LOAD_MAX_I16 */ 11731 746, 11732 /* ATOMIC_LOAD_MAX_I16_POSTRA */ 11733 749, 11734 /* ATOMIC_LOAD_MAX_I32 */ 11735 755, 11736 /* ATOMIC_LOAD_MAX_I32_POSTRA */ 11737 758, 11738 /* ATOMIC_LOAD_MAX_I64 */ 11739 761, 11740 /* ATOMIC_LOAD_MAX_I64_POSTRA */ 11741 764, 11742 /* ATOMIC_LOAD_MAX_I8 */ 11743 767, 11744 /* ATOMIC_LOAD_MAX_I8_POSTRA */ 11745 770, 11746 /* ATOMIC_LOAD_MIN_I16 */ 11747 776, 11748 /* ATOMIC_LOAD_MIN_I16_POSTRA */ 11749 779, 11750 /* ATOMIC_LOAD_MIN_I32 */ 11751 785, 11752 /* ATOMIC_LOAD_MIN_I32_POSTRA */ 11753 788, 11754 /* ATOMIC_LOAD_MIN_I64 */ 11755 791, 11756 /* ATOMIC_LOAD_MIN_I64_POSTRA */ 11757 794, 11758 /* ATOMIC_LOAD_MIN_I8 */ 11759 797, 11760 /* ATOMIC_LOAD_MIN_I8_POSTRA */ 11761 800, 11762 /* ATOMIC_LOAD_NAND_I16 */ 11763 806, 11764 /* ATOMIC_LOAD_NAND_I16_POSTRA */ 11765 809, 11766 /* ATOMIC_LOAD_NAND_I32 */ 11767 815, 11768 /* ATOMIC_LOAD_NAND_I32_POSTRA */ 11769 818, 11770 /* ATOMIC_LOAD_NAND_I64 */ 11771 821, 11772 /* ATOMIC_LOAD_NAND_I64_POSTRA */ 11773 824, 11774 /* ATOMIC_LOAD_NAND_I8 */ 11775 827, 11776 /* ATOMIC_LOAD_NAND_I8_POSTRA */ 11777 830, 11778 /* ATOMIC_LOAD_OR_I16 */ 11779 836, 11780 /* ATOMIC_LOAD_OR_I16_POSTRA */ 11781 839, 11782 /* ATOMIC_LOAD_OR_I32 */ 11783 845, 11784 /* ATOMIC_LOAD_OR_I32_POSTRA */ 11785 848, 11786 /* ATOMIC_LOAD_OR_I64 */ 11787 851, 11788 /* ATOMIC_LOAD_OR_I64_POSTRA */ 11789 854, 11790 /* ATOMIC_LOAD_OR_I8 */ 11791 857, 11792 /* ATOMIC_LOAD_OR_I8_POSTRA */ 11793 860, 11794 /* ATOMIC_LOAD_SUB_I16 */ 11795 866, 11796 /* ATOMIC_LOAD_SUB_I16_POSTRA */ 11797 869, 11798 /* ATOMIC_LOAD_SUB_I32 */ 11799 875, 11800 /* ATOMIC_LOAD_SUB_I32_POSTRA */ 11801 878, 11802 /* ATOMIC_LOAD_SUB_I64 */ 11803 881, 11804 /* ATOMIC_LOAD_SUB_I64_POSTRA */ 11805 884, 11806 /* ATOMIC_LOAD_SUB_I8 */ 11807 887, 11808 /* ATOMIC_LOAD_SUB_I8_POSTRA */ 11809 890, 11810 /* ATOMIC_LOAD_UMAX_I16 */ 11811 896, 11812 /* ATOMIC_LOAD_UMAX_I16_POSTRA */ 11813 899, 11814 /* ATOMIC_LOAD_UMAX_I32 */ 11815 905, 11816 /* ATOMIC_LOAD_UMAX_I32_POSTRA */ 11817 908, 11818 /* ATOMIC_LOAD_UMAX_I64 */ 11819 911, 11820 /* ATOMIC_LOAD_UMAX_I64_POSTRA */ 11821 914, 11822 /* ATOMIC_LOAD_UMAX_I8 */ 11823 917, 11824 /* ATOMIC_LOAD_UMAX_I8_POSTRA */ 11825 920, 11826 /* ATOMIC_LOAD_UMIN_I16 */ 11827 926, 11828 /* ATOMIC_LOAD_UMIN_I16_POSTRA */ 11829 929, 11830 /* ATOMIC_LOAD_UMIN_I32 */ 11831 935, 11832 /* ATOMIC_LOAD_UMIN_I32_POSTRA */ 11833 938, 11834 /* ATOMIC_LOAD_UMIN_I64 */ 11835 941, 11836 /* ATOMIC_LOAD_UMIN_I64_POSTRA */ 11837 944, 11838 /* ATOMIC_LOAD_UMIN_I8 */ 11839 947, 11840 /* ATOMIC_LOAD_UMIN_I8_POSTRA */ 11841 950, 11842 /* ATOMIC_LOAD_XOR_I16 */ 11843 956, 11844 /* ATOMIC_LOAD_XOR_I16_POSTRA */ 11845 959, 11846 /* ATOMIC_LOAD_XOR_I32 */ 11847 965, 11848 /* ATOMIC_LOAD_XOR_I32_POSTRA */ 11849 968, 11850 /* ATOMIC_LOAD_XOR_I64 */ 11851 971, 11852 /* ATOMIC_LOAD_XOR_I64_POSTRA */ 11853 974, 11854 /* ATOMIC_LOAD_XOR_I8 */ 11855 977, 11856 /* ATOMIC_LOAD_XOR_I8_POSTRA */ 11857 980, 11858 /* ATOMIC_SWAP_I16 */ 11859 986, 11860 /* ATOMIC_SWAP_I16_POSTRA */ 11861 989, 11862 /* ATOMIC_SWAP_I32 */ 11863 995, 11864 /* ATOMIC_SWAP_I32_POSTRA */ 11865 998, 11866 /* ATOMIC_SWAP_I64 */ 11867 1001, 11868 /* ATOMIC_SWAP_I64_POSTRA */ 11869 1004, 11870 /* ATOMIC_SWAP_I8 */ 11871 1007, 11872 /* ATOMIC_SWAP_I8_POSTRA */ 11873 1010, 11874 /* B */ 11875 1016, 11876 /* BAL_BR */ 11877 1017, 11878 /* BAL_BR_MM */ 11879 1018, 11880 /* BEQLImmMacro */ 11881 1019, 11882 /* BGE */ 11883 1022, 11884 /* BGEImmMacro */ 11885 1025, 11886 /* BGEL */ 11887 1028, 11888 /* BGELImmMacro */ 11889 1031, 11890 /* BGEU */ 11891 1034, 11892 /* BGEUImmMacro */ 11893 1037, 11894 /* BGEUL */ 11895 1040, 11896 /* BGEULImmMacro */ 11897 1043, 11898 /* BGT */ 11899 1046, 11900 /* BGTImmMacro */ 11901 1049, 11902 /* BGTL */ 11903 1052, 11904 /* BGTLImmMacro */ 11905 1055, 11906 /* BGTU */ 11907 1058, 11908 /* BGTUImmMacro */ 11909 1061, 11910 /* BGTUL */ 11911 1064, 11912 /* BGTULImmMacro */ 11913 1067, 11914 /* BLE */ 11915 1070, 11916 /* BLEImmMacro */ 11917 1073, 11918 /* BLEL */ 11919 1076, 11920 /* BLELImmMacro */ 11921 1079, 11922 /* BLEU */ 11923 1082, 11924 /* BLEUImmMacro */ 11925 1085, 11926 /* BLEUL */ 11927 1088, 11928 /* BLEULImmMacro */ 11929 1091, 11930 /* BLT */ 11931 1094, 11932 /* BLTImmMacro */ 11933 1097, 11934 /* BLTL */ 11935 1100, 11936 /* BLTLImmMacro */ 11937 1103, 11938 /* BLTU */ 11939 1106, 11940 /* BLTUImmMacro */ 11941 1109, 11942 /* BLTUL */ 11943 1112, 11944 /* BLTULImmMacro */ 11945 1115, 11946 /* BNELImmMacro */ 11947 1118, 11948 /* BPOSGE32_PSEUDO */ 11949 1121, 11950 /* BSEL_D_PSEUDO */ 11951 1122, 11952 /* BSEL_FD_PSEUDO */ 11953 1126, 11954 /* BSEL_FW_PSEUDO */ 11955 1130, 11956 /* BSEL_H_PSEUDO */ 11957 1134, 11958 /* BSEL_W_PSEUDO */ 11959 1138, 11960 /* B_MM */ 11961 1142, 11962 /* B_MMR6_Pseudo */ 11963 1143, 11964 /* B_MM_Pseudo */ 11965 1144, 11966 /* BeqImm */ 11967 1145, 11968 /* BneImm */ 11969 1148, 11970 /* BteqzT8CmpX16 */ 11971 1151, 11972 /* BteqzT8CmpiX16 */ 11973 1154, 11974 /* BteqzT8SltX16 */ 11975 1157, 11976 /* BteqzT8SltiX16 */ 11977 1160, 11978 /* BteqzT8SltiuX16 */ 11979 1163, 11980 /* BteqzT8SltuX16 */ 11981 1166, 11982 /* BtnezT8CmpX16 */ 11983 1169, 11984 /* BtnezT8CmpiX16 */ 11985 1172, 11986 /* BtnezT8SltX16 */ 11987 1175, 11988 /* BtnezT8SltiX16 */ 11989 1178, 11990 /* BtnezT8SltiuX16 */ 11991 1181, 11992 /* BtnezT8SltuX16 */ 11993 1184, 11994 /* BuildPairF64 */ 11995 1187, 11996 /* BuildPairF64_64 */ 11997 1190, 11998 /* CFTC1 */ 11999 1193, 12000 /* CONSTPOOL_ENTRY */ 12001 1195, 12002 /* COPY_FD_PSEUDO */ 12003 1198, 12004 /* COPY_FW_PSEUDO */ 12005 1201, 12006 /* CTTC1 */ 12007 1204, 12008 /* Constant32 */ 12009 1206, 12010 /* DMULImmMacro */ 12011 1207, 12012 /* DMULMacro */ 12013 1210, 12014 /* DMULOMacro */ 12015 1213, 12016 /* DMULOUMacro */ 12017 1216, 12018 /* DROL */ 12019 1219, 12020 /* DROLImm */ 12021 1222, 12022 /* DROR */ 12023 1225, 12024 /* DRORImm */ 12025 1228, 12026 /* DSDivIMacro */ 12027 1231, 12028 /* DSDivMacro */ 12029 1234, 12030 /* DSRemIMacro */ 12031 1237, 12032 /* DSRemMacro */ 12033 1240, 12034 /* DUDivIMacro */ 12035 1243, 12036 /* DUDivMacro */ 12037 1246, 12038 /* DURemIMacro */ 12039 1249, 12040 /* DURemMacro */ 12041 1252, 12042 /* ERet */ 12043 1255, 12044 /* ExtractElementF64 */ 12045 1255, 12046 /* ExtractElementF64_64 */ 12047 1258, 12048 /* FABS_D */ 12049 1261, 12050 /* FABS_W */ 12051 1263, 12052 /* FEXP2_D_1_PSEUDO */ 12053 1265, 12054 /* FEXP2_W_1_PSEUDO */ 12055 1267, 12056 /* FILL_FD_PSEUDO */ 12057 1269, 12058 /* FILL_FW_PSEUDO */ 12059 1271, 12060 /* GotPrologue16 */ 12061 1273, 12062 /* INSERT_B_VIDX64_PSEUDO */ 12063 1277, 12064 /* INSERT_B_VIDX_PSEUDO */ 12065 1281, 12066 /* INSERT_D_VIDX64_PSEUDO */ 12067 1285, 12068 /* INSERT_D_VIDX_PSEUDO */ 12069 1289, 12070 /* INSERT_FD_PSEUDO */ 12071 1293, 12072 /* INSERT_FD_VIDX64_PSEUDO */ 12073 1297, 12074 /* INSERT_FD_VIDX_PSEUDO */ 12075 1301, 12076 /* INSERT_FW_PSEUDO */ 12077 1305, 12078 /* INSERT_FW_VIDX64_PSEUDO */ 12079 1309, 12080 /* INSERT_FW_VIDX_PSEUDO */ 12081 1313, 12082 /* INSERT_H_VIDX64_PSEUDO */ 12083 1317, 12084 /* INSERT_H_VIDX_PSEUDO */ 12085 1321, 12086 /* INSERT_W_VIDX64_PSEUDO */ 12087 1325, 12088 /* INSERT_W_VIDX_PSEUDO */ 12089 1329, 12090 /* JALR64Pseudo */ 12091 1333, 12092 /* JALRHB64Pseudo */ 12093 1334, 12094 /* JALRHBPseudo */ 12095 1335, 12096 /* JALRPseudo */ 12097 1336, 12098 /* JAL_MMR6 */ 12099 1337, 12100 /* JalOneReg */ 12101 1338, 12102 /* JalTwoReg */ 12103 1339, 12104 /* LDMacro */ 12105 1341, 12106 /* LDR_D */ 12107 1344, 12108 /* LDR_W */ 12109 1347, 12110 /* LD_F16 */ 12111 1350, 12112 /* LOAD_ACC128 */ 12113 1353, 12114 /* LOAD_ACC64 */ 12115 1356, 12116 /* LOAD_ACC64DSP */ 12117 1359, 12118 /* LOAD_CCOND_DSP */ 12119 1362, 12120 /* LONG_BRANCH_ADDiu */ 12121 1365, 12122 /* LONG_BRANCH_ADDiu2Op */ 12123 1369, 12124 /* LONG_BRANCH_DADDiu */ 12125 1372, 12126 /* LONG_BRANCH_DADDiu2Op */ 12127 1376, 12128 /* LONG_BRANCH_LUi */ 12129 1379, 12130 /* LONG_BRANCH_LUi2Op */ 12131 1382, 12132 /* LONG_BRANCH_LUi2Op_64 */ 12133 1384, 12134 /* LWM_MM */ 12135 1386, 12136 /* LoadAddrImm32 */ 12137 1389, 12138 /* LoadAddrImm64 */ 12139 1391, 12140 /* LoadAddrReg32 */ 12141 1393, 12142 /* LoadAddrReg64 */ 12143 1396, 12144 /* LoadImm32 */ 12145 1399, 12146 /* LoadImm64 */ 12147 1401, 12148 /* LoadImmDoubleFGR */ 12149 1403, 12150 /* LoadImmDoubleFGR_32 */ 12151 1405, 12152 /* LoadImmDoubleGPR */ 12153 1407, 12154 /* LoadImmSingleFGR */ 12155 1409, 12156 /* LoadImmSingleGPR */ 12157 1411, 12158 /* LwConstant32 */ 12159 1413, 12160 /* MFTACX */ 12161 1416, 12162 /* MFTC0 */ 12163 1418, 12164 /* MFTC1 */ 12165 1421, 12166 /* MFTDSP */ 12167 1423, 12168 /* MFTGPR */ 12169 1424, 12170 /* MFTHC1 */ 12171 1427, 12172 /* MFTHI */ 12173 1429, 12174 /* MFTLO */ 12175 1431, 12176 /* MIPSeh_return32 */ 12177 1433, 12178 /* MIPSeh_return64 */ 12179 1435, 12180 /* MSA_FP_EXTEND_D_PSEUDO */ 12181 1437, 12182 /* MSA_FP_EXTEND_W_PSEUDO */ 12183 1439, 12184 /* MSA_FP_ROUND_D_PSEUDO */ 12185 1441, 12186 /* MSA_FP_ROUND_W_PSEUDO */ 12187 1443, 12188 /* MTTACX */ 12189 1445, 12190 /* MTTC0 */ 12191 1447, 12192 /* MTTC1 */ 12193 1450, 12194 /* MTTDSP */ 12195 1452, 12196 /* MTTGPR */ 12197 1453, 12198 /* MTTHC1 */ 12199 1455, 12200 /* MTTHI */ 12201 1457, 12202 /* MTTLO */ 12203 1459, 12204 /* MULImmMacro */ 12205 1461, 12206 /* MULOMacro */ 12207 1464, 12208 /* MULOUMacro */ 12209 1467, 12210 /* MultRxRy16 */ 12211 1470, 12212 /* MultRxRyRz16 */ 12213 1472, 12214 /* MultuRxRy16 */ 12215 1475, 12216 /* MultuRxRyRz16 */ 12217 1477, 12218 /* NOP */ 12219 1480, 12220 /* NORImm */ 12221 1480, 12222 /* NORImm64 */ 12223 1483, 12224 /* NOR_V_D_PSEUDO */ 12225 1486, 12226 /* NOR_V_H_PSEUDO */ 12227 1489, 12228 /* NOR_V_W_PSEUDO */ 12229 1492, 12230 /* OR_V_D_PSEUDO */ 12231 1495, 12232 /* OR_V_H_PSEUDO */ 12233 1498, 12234 /* OR_V_W_PSEUDO */ 12235 1501, 12236 /* PseudoCMPU_EQ_QB */ 12237 1504, 12238 /* PseudoCMPU_LE_QB */ 12239 1507, 12240 /* PseudoCMPU_LT_QB */ 12241 1510, 12242 /* PseudoCMP_EQ_PH */ 12243 1513, 12244 /* PseudoCMP_LE_PH */ 12245 1516, 12246 /* PseudoCMP_LT_PH */ 12247 1519, 12248 /* PseudoCVT_D32_W */ 12249 1522, 12250 /* PseudoCVT_D64_L */ 12251 1524, 12252 /* PseudoCVT_D64_W */ 12253 1526, 12254 /* PseudoCVT_S_L */ 12255 1528, 12256 /* PseudoCVT_S_W */ 12257 1530, 12258 /* PseudoDMULT */ 12259 1532, 12260 /* PseudoDMULTu */ 12261 1535, 12262 /* PseudoDSDIV */ 12263 1538, 12264 /* PseudoDUDIV */ 12265 1541, 12266 /* PseudoD_SELECT_I */ 12267 1544, 12268 /* PseudoD_SELECT_I64 */ 12269 1551, 12270 /* PseudoIndirectBranch */ 12271 1558, 12272 /* PseudoIndirectBranch64 */ 12273 1559, 12274 /* PseudoIndirectBranch64R6 */ 12275 1560, 12276 /* PseudoIndirectBranchR6 */ 12277 1561, 12278 /* PseudoIndirectBranch_MM */ 12279 1562, 12280 /* PseudoIndirectBranch_MMR6 */ 12281 1563, 12282 /* PseudoIndirectHazardBranch */ 12283 1564, 12284 /* PseudoIndirectHazardBranch64 */ 12285 1565, 12286 /* PseudoIndrectHazardBranch64R6 */ 12287 1566, 12288 /* PseudoIndrectHazardBranchR6 */ 12289 1567, 12290 /* PseudoMADD */ 12291 1568, 12292 /* PseudoMADDU */ 12293 1572, 12294 /* PseudoMADDU_MM */ 12295 1576, 12296 /* PseudoMADD_MM */ 12297 1580, 12298 /* PseudoMFHI */ 12299 1584, 12300 /* PseudoMFHI64 */ 12301 1586, 12302 /* PseudoMFHI_MM */ 12303 1588, 12304 /* PseudoMFLO */ 12305 1590, 12306 /* PseudoMFLO64 */ 12307 1592, 12308 /* PseudoMFLO_MM */ 12309 1594, 12310 /* PseudoMSUB */ 12311 1596, 12312 /* PseudoMSUBU */ 12313 1600, 12314 /* PseudoMSUBU_MM */ 12315 1604, 12316 /* PseudoMSUB_MM */ 12317 1608, 12318 /* PseudoMTLOHI */ 12319 1612, 12320 /* PseudoMTLOHI64 */ 12321 1615, 12322 /* PseudoMTLOHI_DSP */ 12323 1618, 12324 /* PseudoMTLOHI_MM */ 12325 1621, 12326 /* PseudoMULT */ 12327 1624, 12328 /* PseudoMULT_MM */ 12329 1627, 12330 /* PseudoMULTu */ 12331 1630, 12332 /* PseudoMULTu_MM */ 12333 1633, 12334 /* PseudoPICK_PH */ 12335 1636, 12336 /* PseudoPICK_QB */ 12337 1640, 12338 /* PseudoReturn */ 12339 1644, 12340 /* PseudoReturn64 */ 12341 1645, 12342 /* PseudoSDIV */ 12343 1646, 12344 /* PseudoSELECTFP_F_D32 */ 12345 1649, 12346 /* PseudoSELECTFP_F_D64 */ 12347 1653, 12348 /* PseudoSELECTFP_F_I */ 12349 1657, 12350 /* PseudoSELECTFP_F_I64 */ 12351 1661, 12352 /* PseudoSELECTFP_F_S */ 12353 1665, 12354 /* PseudoSELECTFP_T_D32 */ 12355 1669, 12356 /* PseudoSELECTFP_T_D64 */ 12357 1673, 12358 /* PseudoSELECTFP_T_I */ 12359 1677, 12360 /* PseudoSELECTFP_T_I64 */ 12361 1681, 12362 /* PseudoSELECTFP_T_S */ 12363 1685, 12364 /* PseudoSELECT_D32 */ 12365 1689, 12366 /* PseudoSELECT_D64 */ 12367 1693, 12368 /* PseudoSELECT_I */ 12369 1697, 12370 /* PseudoSELECT_I64 */ 12371 1701, 12372 /* PseudoSELECT_S */ 12373 1705, 12374 /* PseudoTRUNC_W_D */ 12375 1709, 12376 /* PseudoTRUNC_W_D32 */ 12377 1712, 12378 /* PseudoTRUNC_W_S */ 12379 1715, 12380 /* PseudoUDIV */ 12381 1718, 12382 /* ROL */ 12383 1721, 12384 /* ROLImm */ 12385 1724, 12386 /* ROR */ 12387 1727, 12388 /* RORImm */ 12389 1730, 12390 /* RetRA */ 12391 1733, 12392 /* RetRA16 */ 12393 1733, 12394 /* SDC1_M1 */ 12395 1733, 12396 /* SDIV_MM_Pseudo */ 12397 1736, 12398 /* SDMacro */ 12399 1739, 12400 /* SDivIMacro */ 12401 1742, 12402 /* SDivMacro */ 12403 1745, 12404 /* SEQIMacro */ 12405 1748, 12406 /* SEQMacro */ 12407 1751, 12408 /* SGE */ 12409 1754, 12410 /* SGEImm */ 12411 1757, 12412 /* SGEImm64 */ 12413 1760, 12414 /* SGEU */ 12415 1763, 12416 /* SGEUImm */ 12417 1766, 12418 /* SGEUImm64 */ 12419 1769, 12420 /* SGTImm */ 12421 1772, 12422 /* SGTImm64 */ 12423 1775, 12424 /* SGTUImm */ 12425 1778, 12426 /* SGTUImm64 */ 12427 1781, 12428 /* SLE */ 12429 1784, 12430 /* SLEImm */ 12431 1787, 12432 /* SLEImm64 */ 12433 1790, 12434 /* SLEU */ 12435 1793, 12436 /* SLEUImm */ 12437 1796, 12438 /* SLEUImm64 */ 12439 1799, 12440 /* SLTImm64 */ 12441 1802, 12442 /* SLTUImm64 */ 12443 1805, 12444 /* SNEIMacro */ 12445 1808, 12446 /* SNEMacro */ 12447 1811, 12448 /* SNZ_B_PSEUDO */ 12449 1814, 12450 /* SNZ_D_PSEUDO */ 12451 1816, 12452 /* SNZ_H_PSEUDO */ 12453 1818, 12454 /* SNZ_V_PSEUDO */ 12455 1820, 12456 /* SNZ_W_PSEUDO */ 12457 1822, 12458 /* SRemIMacro */ 12459 1824, 12460 /* SRemMacro */ 12461 1827, 12462 /* STORE_ACC128 */ 12463 1830, 12464 /* STORE_ACC64 */ 12465 1833, 12466 /* STORE_ACC64DSP */ 12467 1836, 12468 /* STORE_CCOND_DSP */ 12469 1839, 12470 /* STR_D */ 12471 1842, 12472 /* STR_W */ 12473 1845, 12474 /* ST_F16 */ 12475 1848, 12476 /* SWM_MM */ 12477 1851, 12478 /* SZ_B_PSEUDO */ 12479 1854, 12480 /* SZ_D_PSEUDO */ 12481 1856, 12482 /* SZ_H_PSEUDO */ 12483 1858, 12484 /* SZ_V_PSEUDO */ 12485 1860, 12486 /* SZ_W_PSEUDO */ 12487 1862, 12488 /* SaaAddr */ 12489 1864, 12490 /* SaadAddr */ 12491 1867, 12492 /* SelBeqZ */ 12493 1870, 12494 /* SelBneZ */ 12495 1874, 12496 /* SelTBteqZCmp */ 12497 1878, 12498 /* SelTBteqZCmpi */ 12499 1883, 12500 /* SelTBteqZSlt */ 12501 1888, 12502 /* SelTBteqZSlti */ 12503 1893, 12504 /* SelTBteqZSltiu */ 12505 1898, 12506 /* SelTBteqZSltu */ 12507 1903, 12508 /* SelTBtneZCmp */ 12509 1908, 12510 /* SelTBtneZCmpi */ 12511 1913, 12512 /* SelTBtneZSlt */ 12513 1918, 12514 /* SelTBtneZSlti */ 12515 1923, 12516 /* SelTBtneZSltiu */ 12517 1928, 12518 /* SelTBtneZSltu */ 12519 1933, 12520 /* SltCCRxRy16 */ 12521 1938, 12522 /* SltiCCRxImmX16 */ 12523 1941, 12524 /* SltiuCCRxImmX16 */ 12525 1944, 12526 /* SltuCCRxRy16 */ 12527 1947, 12528 /* SltuRxRyRz16 */ 12529 1950, 12530 /* TAILCALL */ 12531 1953, 12532 /* TAILCALL64R6REG */ 12533 1954, 12534 /* TAILCALLHB64R6REG */ 12535 1955, 12536 /* TAILCALLHBR6REG */ 12537 1956, 12538 /* TAILCALLR6REG */ 12539 1957, 12540 /* TAILCALLREG */ 12541 1958, 12542 /* TAILCALLREG64 */ 12543 1959, 12544 /* TAILCALLREGHB */ 12545 1960, 12546 /* TAILCALLREGHB64 */ 12547 1961, 12548 /* TAILCALLREG_MM */ 12549 1962, 12550 /* TAILCALLREG_MMR6 */ 12551 1963, 12552 /* TAILCALL_MM */ 12553 1964, 12554 /* TAILCALL_MMR6 */ 12555 1965, 12556 /* TRAP */ 12557 1966, 12558 /* TRAP_MM */ 12559 1966, 12560 /* UDIV_MM_Pseudo */ 12561 1966, 12562 /* UDivIMacro */ 12563 1969, 12564 /* UDivMacro */ 12565 1972, 12566 /* URemIMacro */ 12567 1975, 12568 /* URemMacro */ 12569 1978, 12570 /* Ulh */ 12571 1981, 12572 /* Ulhu */ 12573 1984, 12574 /* Ulw */ 12575 1987, 12576 /* Ush */ 12577 1990, 12578 /* Usw */ 12579 1993, 12580 /* XOR_V_D_PSEUDO */ 12581 1996, 12582 /* XOR_V_H_PSEUDO */ 12583 1999, 12584 /* XOR_V_W_PSEUDO */ 12585 2002, 12586 /* ABSQ_S_PH */ 12587 2005, 12588 /* ABSQ_S_PH_MM */ 12589 2007, 12590 /* ABSQ_S_QB */ 12591 2009, 12592 /* ABSQ_S_QB_MMR2 */ 12593 2011, 12594 /* ABSQ_S_W */ 12595 2013, 12596 /* ABSQ_S_W_MM */ 12597 2015, 12598 /* ADD */ 12599 2017, 12600 /* ADDIUPC */ 12601 2020, 12602 /* ADDIUPC_MM */ 12603 2022, 12604 /* ADDIUPC_MMR6 */ 12605 2024, 12606 /* ADDIUR1SP_MM */ 12607 2026, 12608 /* ADDIUR2_MM */ 12609 2028, 12610 /* ADDIUS5_MM */ 12611 2031, 12612 /* ADDIUSP_MM */ 12613 2034, 12614 /* ADDIU_MMR6 */ 12615 2035, 12616 /* ADDQH_PH */ 12617 2038, 12618 /* ADDQH_PH_MMR2 */ 12619 2041, 12620 /* ADDQH_R_PH */ 12621 2044, 12622 /* ADDQH_R_PH_MMR2 */ 12623 2047, 12624 /* ADDQH_R_W */ 12625 2050, 12626 /* ADDQH_R_W_MMR2 */ 12627 2053, 12628 /* ADDQH_W */ 12629 2056, 12630 /* ADDQH_W_MMR2 */ 12631 2059, 12632 /* ADDQ_PH */ 12633 2062, 12634 /* ADDQ_PH_MM */ 12635 2065, 12636 /* ADDQ_S_PH */ 12637 2068, 12638 /* ADDQ_S_PH_MM */ 12639 2071, 12640 /* ADDQ_S_W */ 12641 2074, 12642 /* ADDQ_S_W_MM */ 12643 2077, 12644 /* ADDR_PS64 */ 12645 2080, 12646 /* ADDSC */ 12647 2083, 12648 /* ADDSC_MM */ 12649 2086, 12650 /* ADDS_A_B */ 12651 2089, 12652 /* ADDS_A_D */ 12653 2092, 12654 /* ADDS_A_H */ 12655 2095, 12656 /* ADDS_A_W */ 12657 2098, 12658 /* ADDS_S_B */ 12659 2101, 12660 /* ADDS_S_D */ 12661 2104, 12662 /* ADDS_S_H */ 12663 2107, 12664 /* ADDS_S_W */ 12665 2110, 12666 /* ADDS_U_B */ 12667 2113, 12668 /* ADDS_U_D */ 12669 2116, 12670 /* ADDS_U_H */ 12671 2119, 12672 /* ADDS_U_W */ 12673 2122, 12674 /* ADDU16_MM */ 12675 2125, 12676 /* ADDU16_MMR6 */ 12677 2128, 12678 /* ADDUH_QB */ 12679 2131, 12680 /* ADDUH_QB_MMR2 */ 12681 2134, 12682 /* ADDUH_R_QB */ 12683 2137, 12684 /* ADDUH_R_QB_MMR2 */ 12685 2140, 12686 /* ADDU_MMR6 */ 12687 2143, 12688 /* ADDU_PH */ 12689 2146, 12690 /* ADDU_PH_MMR2 */ 12691 2149, 12692 /* ADDU_QB */ 12693 2152, 12694 /* ADDU_QB_MM */ 12695 2155, 12696 /* ADDU_S_PH */ 12697 2158, 12698 /* ADDU_S_PH_MMR2 */ 12699 2161, 12700 /* ADDU_S_QB */ 12701 2164, 12702 /* ADDU_S_QB_MM */ 12703 2167, 12704 /* ADDVI_B */ 12705 2170, 12706 /* ADDVI_D */ 12707 2173, 12708 /* ADDVI_H */ 12709 2176, 12710 /* ADDVI_W */ 12711 2179, 12712 /* ADDV_B */ 12713 2182, 12714 /* ADDV_D */ 12715 2185, 12716 /* ADDV_H */ 12717 2188, 12718 /* ADDV_W */ 12719 2191, 12720 /* ADDWC */ 12721 2194, 12722 /* ADDWC_MM */ 12723 2197, 12724 /* ADD_A_B */ 12725 2200, 12726 /* ADD_A_D */ 12727 2203, 12728 /* ADD_A_H */ 12729 2206, 12730 /* ADD_A_W */ 12731 2209, 12732 /* ADD_MM */ 12733 2212, 12734 /* ADD_MMR6 */ 12735 2215, 12736 /* ADDi */ 12737 2218, 12738 /* ADDi_MM */ 12739 2221, 12740 /* ADDiu */ 12741 2224, 12742 /* ADDiu_MM */ 12743 2227, 12744 /* ADDu */ 12745 2230, 12746 /* ADDu_MM */ 12747 2233, 12748 /* ALIGN */ 12749 2236, 12750 /* ALIGN_MMR6 */ 12751 2240, 12752 /* ALUIPC */ 12753 2244, 12754 /* ALUIPC_MMR6 */ 12755 2246, 12756 /* AND */ 12757 2248, 12758 /* AND16_MM */ 12759 2251, 12760 /* AND16_MMR6 */ 12761 2254, 12762 /* AND64 */ 12763 2257, 12764 /* ANDI16_MM */ 12765 2260, 12766 /* ANDI16_MMR6 */ 12767 2263, 12768 /* ANDI_B */ 12769 2266, 12770 /* ANDI_MMR6 */ 12771 2269, 12772 /* AND_MM */ 12773 2272, 12774 /* AND_MMR6 */ 12775 2275, 12776 /* AND_V */ 12777 2278, 12778 /* ANDi */ 12779 2281, 12780 /* ANDi64 */ 12781 2284, 12782 /* ANDi_MM */ 12783 2287, 12784 /* APPEND */ 12785 2290, 12786 /* APPEND_MMR2 */ 12787 2294, 12788 /* ASUB_S_B */ 12789 2298, 12790 /* ASUB_S_D */ 12791 2301, 12792 /* ASUB_S_H */ 12793 2304, 12794 /* ASUB_S_W */ 12795 2307, 12796 /* ASUB_U_B */ 12797 2310, 12798 /* ASUB_U_D */ 12799 2313, 12800 /* ASUB_U_H */ 12801 2316, 12802 /* ASUB_U_W */ 12803 2319, 12804 /* AUI */ 12805 2322, 12806 /* AUIPC */ 12807 2325, 12808 /* AUIPC_MMR6 */ 12809 2327, 12810 /* AUI_MMR6 */ 12811 2329, 12812 /* AVER_S_B */ 12813 2332, 12814 /* AVER_S_D */ 12815 2335, 12816 /* AVER_S_H */ 12817 2338, 12818 /* AVER_S_W */ 12819 2341, 12820 /* AVER_U_B */ 12821 2344, 12822 /* AVER_U_D */ 12823 2347, 12824 /* AVER_U_H */ 12825 2350, 12826 /* AVER_U_W */ 12827 2353, 12828 /* AVE_S_B */ 12829 2356, 12830 /* AVE_S_D */ 12831 2359, 12832 /* AVE_S_H */ 12833 2362, 12834 /* AVE_S_W */ 12835 2365, 12836 /* AVE_U_B */ 12837 2368, 12838 /* AVE_U_D */ 12839 2371, 12840 /* AVE_U_H */ 12841 2374, 12842 /* AVE_U_W */ 12843 2377, 12844 /* AddiuRxImmX16 */ 12845 2380, 12846 /* AddiuRxPcImmX16 */ 12847 2382, 12848 /* AddiuRxRxImm16 */ 12849 2384, 12850 /* AddiuRxRxImmX16 */ 12851 2387, 12852 /* AddiuRxRyOffMemX16 */ 12853 2390, 12854 /* AddiuSpImm16 */ 12855 2393, 12856 /* AddiuSpImmX16 */ 12857 2394, 12858 /* AdduRxRyRz16 */ 12859 2395, 12860 /* AndRxRxRy16 */ 12861 2398, 12862 /* B16_MM */ 12863 2401, 12864 /* BADDu */ 12865 2402, 12866 /* BAL */ 12867 2405, 12868 /* BALC */ 12869 2406, 12870 /* BALC_MMR6 */ 12871 2407, 12872 /* BALIGN */ 12873 2408, 12874 /* BALIGN_MMR2 */ 12875 2412, 12876 /* BBIT0 */ 12877 2416, 12878 /* BBIT032 */ 12879 2419, 12880 /* BBIT1 */ 12881 2422, 12882 /* BBIT132 */ 12883 2425, 12884 /* BC */ 12885 2428, 12886 /* BC16_MMR6 */ 12887 2429, 12888 /* BC1EQZ */ 12889 2430, 12890 /* BC1EQZC_MMR6 */ 12891 2432, 12892 /* BC1F */ 12893 2434, 12894 /* BC1FL */ 12895 2436, 12896 /* BC1F_MM */ 12897 2438, 12898 /* BC1NEZ */ 12899 2440, 12900 /* BC1NEZC_MMR6 */ 12901 2442, 12902 /* BC1T */ 12903 2444, 12904 /* BC1TL */ 12905 2446, 12906 /* BC1T_MM */ 12907 2448, 12908 /* BC2EQZ */ 12909 2450, 12910 /* BC2EQZC_MMR6 */ 12911 2452, 12912 /* BC2NEZ */ 12913 2454, 12914 /* BC2NEZC_MMR6 */ 12915 2456, 12916 /* BCLRI_B */ 12917 2458, 12918 /* BCLRI_D */ 12919 2461, 12920 /* BCLRI_H */ 12921 2464, 12922 /* BCLRI_W */ 12923 2467, 12924 /* BCLR_B */ 12925 2470, 12926 /* BCLR_D */ 12927 2473, 12928 /* BCLR_H */ 12929 2476, 12930 /* BCLR_W */ 12931 2479, 12932 /* BC_MMR6 */ 12933 2482, 12934 /* BEQ */ 12935 2483, 12936 /* BEQ64 */ 12937 2486, 12938 /* BEQC */ 12939 2489, 12940 /* BEQC64 */ 12941 2492, 12942 /* BEQC_MMR6 */ 12943 2495, 12944 /* BEQL */ 12945 2498, 12946 /* BEQZ16_MM */ 12947 2501, 12948 /* BEQZALC */ 12949 2503, 12950 /* BEQZALC_MMR6 */ 12951 2505, 12952 /* BEQZC */ 12953 2507, 12954 /* BEQZC16_MMR6 */ 12955 2509, 12956 /* BEQZC64 */ 12957 2511, 12958 /* BEQZC_MM */ 12959 2513, 12960 /* BEQZC_MMR6 */ 12961 2515, 12962 /* BEQ_MM */ 12963 2517, 12964 /* BGEC */ 12965 2520, 12966 /* BGEC64 */ 12967 2523, 12968 /* BGEC_MMR6 */ 12969 2526, 12970 /* BGEUC */ 12971 2529, 12972 /* BGEUC64 */ 12973 2532, 12974 /* BGEUC_MMR6 */ 12975 2535, 12976 /* BGEZ */ 12977 2538, 12978 /* BGEZ64 */ 12979 2540, 12980 /* BGEZAL */ 12981 2542, 12982 /* BGEZALC */ 12983 2544, 12984 /* BGEZALC_MMR6 */ 12985 2546, 12986 /* BGEZALL */ 12987 2548, 12988 /* BGEZALS_MM */ 12989 2550, 12990 /* BGEZAL_MM */ 12991 2552, 12992 /* BGEZC */ 12993 2554, 12994 /* BGEZC64 */ 12995 2556, 12996 /* BGEZC_MMR6 */ 12997 2558, 12998 /* BGEZL */ 12999 2560, 13000 /* BGEZ_MM */ 13001 2562, 13002 /* BGTZ */ 13003 2564, 13004 /* BGTZ64 */ 13005 2566, 13006 /* BGTZALC */ 13007 2568, 13008 /* BGTZALC_MMR6 */ 13009 2570, 13010 /* BGTZC */ 13011 2572, 13012 /* BGTZC64 */ 13013 2574, 13014 /* BGTZC_MMR6 */ 13015 2576, 13016 /* BGTZL */ 13017 2578, 13018 /* BGTZ_MM */ 13019 2580, 13020 /* BINSLI_B */ 13021 2582, 13022 /* BINSLI_D */ 13023 2586, 13024 /* BINSLI_H */ 13025 2590, 13026 /* BINSLI_W */ 13027 2594, 13028 /* BINSL_B */ 13029 2598, 13030 /* BINSL_D */ 13031 2602, 13032 /* BINSL_H */ 13033 2606, 13034 /* BINSL_W */ 13035 2610, 13036 /* BINSRI_B */ 13037 2614, 13038 /* BINSRI_D */ 13039 2618, 13040 /* BINSRI_H */ 13041 2622, 13042 /* BINSRI_W */ 13043 2626, 13044 /* BINSR_B */ 13045 2630, 13046 /* BINSR_D */ 13047 2634, 13048 /* BINSR_H */ 13049 2638, 13050 /* BINSR_W */ 13051 2642, 13052 /* BITREV */ 13053 2646, 13054 /* BITREV_MM */ 13055 2648, 13056 /* BITSWAP */ 13057 2650, 13058 /* BITSWAP_MMR6 */ 13059 2652, 13060 /* BLEZ */ 13061 2654, 13062 /* BLEZ64 */ 13063 2656, 13064 /* BLEZALC */ 13065 2658, 13066 /* BLEZALC_MMR6 */ 13067 2660, 13068 /* BLEZC */ 13069 2662, 13070 /* BLEZC64 */ 13071 2664, 13072 /* BLEZC_MMR6 */ 13073 2666, 13074 /* BLEZL */ 13075 2668, 13076 /* BLEZ_MM */ 13077 2670, 13078 /* BLTC */ 13079 2672, 13080 /* BLTC64 */ 13081 2675, 13082 /* BLTC_MMR6 */ 13083 2678, 13084 /* BLTUC */ 13085 2681, 13086 /* BLTUC64 */ 13087 2684, 13088 /* BLTUC_MMR6 */ 13089 2687, 13090 /* BLTZ */ 13091 2690, 13092 /* BLTZ64 */ 13093 2692, 13094 /* BLTZAL */ 13095 2694, 13096 /* BLTZALC */ 13097 2696, 13098 /* BLTZALC_MMR6 */ 13099 2698, 13100 /* BLTZALL */ 13101 2700, 13102 /* BLTZALS_MM */ 13103 2702, 13104 /* BLTZAL_MM */ 13105 2704, 13106 /* BLTZC */ 13107 2706, 13108 /* BLTZC64 */ 13109 2708, 13110 /* BLTZC_MMR6 */ 13111 2710, 13112 /* BLTZL */ 13113 2712, 13114 /* BLTZ_MM */ 13115 2714, 13116 /* BMNZI_B */ 13117 2716, 13118 /* BMNZ_V */ 13119 2720, 13120 /* BMZI_B */ 13121 2724, 13122 /* BMZ_V */ 13123 2728, 13124 /* BNE */ 13125 2732, 13126 /* BNE64 */ 13127 2735, 13128 /* BNEC */ 13129 2738, 13130 /* BNEC64 */ 13131 2741, 13132 /* BNEC_MMR6 */ 13133 2744, 13134 /* BNEGI_B */ 13135 2747, 13136 /* BNEGI_D */ 13137 2750, 13138 /* BNEGI_H */ 13139 2753, 13140 /* BNEGI_W */ 13141 2756, 13142 /* BNEG_B */ 13143 2759, 13144 /* BNEG_D */ 13145 2762, 13146 /* BNEG_H */ 13147 2765, 13148 /* BNEG_W */ 13149 2768, 13150 /* BNEL */ 13151 2771, 13152 /* BNEZ16_MM */ 13153 2774, 13154 /* BNEZALC */ 13155 2776, 13156 /* BNEZALC_MMR6 */ 13157 2778, 13158 /* BNEZC */ 13159 2780, 13160 /* BNEZC16_MMR6 */ 13161 2782, 13162 /* BNEZC64 */ 13163 2784, 13164 /* BNEZC_MM */ 13165 2786, 13166 /* BNEZC_MMR6 */ 13167 2788, 13168 /* BNE_MM */ 13169 2790, 13170 /* BNVC */ 13171 2793, 13172 /* BNVC_MMR6 */ 13173 2796, 13174 /* BNZ_B */ 13175 2799, 13176 /* BNZ_D */ 13177 2801, 13178 /* BNZ_H */ 13179 2803, 13180 /* BNZ_V */ 13181 2805, 13182 /* BNZ_W */ 13183 2807, 13184 /* BOVC */ 13185 2809, 13186 /* BOVC_MMR6 */ 13187 2812, 13188 /* BPOSGE32 */ 13189 2815, 13190 /* BPOSGE32C_MMR3 */ 13191 2816, 13192 /* BPOSGE32_MM */ 13193 2817, 13194 /* BREAK */ 13195 2818, 13196 /* BREAK16_MM */ 13197 2820, 13198 /* BREAK16_MMR6 */ 13199 2821, 13200 /* BREAK_MM */ 13201 2822, 13202 /* BREAK_MMR6 */ 13203 2824, 13204 /* BSELI_B */ 13205 2826, 13206 /* BSEL_V */ 13207 2830, 13208 /* BSETI_B */ 13209 2834, 13210 /* BSETI_D */ 13211 2837, 13212 /* BSETI_H */ 13213 2840, 13214 /* BSETI_W */ 13215 2843, 13216 /* BSET_B */ 13217 2846, 13218 /* BSET_D */ 13219 2849, 13220 /* BSET_H */ 13221 2852, 13222 /* BSET_W */ 13223 2855, 13224 /* BZ_B */ 13225 2858, 13226 /* BZ_D */ 13227 2860, 13228 /* BZ_H */ 13229 2862, 13230 /* BZ_V */ 13231 2864, 13232 /* BZ_W */ 13233 2866, 13234 /* BeqzRxImm16 */ 13235 2868, 13236 /* BeqzRxImmX16 */ 13237 2870, 13238 /* Bimm16 */ 13239 2872, 13240 /* BimmX16 */ 13241 2873, 13242 /* BnezRxImm16 */ 13243 2874, 13244 /* BnezRxImmX16 */ 13245 2876, 13246 /* Break16 */ 13247 2878, 13248 /* Bteqz16 */ 13249 2878, 13250 /* BteqzX16 */ 13251 2879, 13252 /* Btnez16 */ 13253 2880, 13254 /* BtnezX16 */ 13255 2881, 13256 /* CACHE */ 13257 2882, 13258 /* CACHEE */ 13259 2885, 13260 /* CACHEE_MM */ 13261 2888, 13262 /* CACHE_MM */ 13263 2891, 13264 /* CACHE_MMR6 */ 13265 2894, 13266 /* CACHE_R6 */ 13267 2897, 13268 /* CEIL_L_D64 */ 13269 2900, 13270 /* CEIL_L_D_MMR6 */ 13271 2902, 13272 /* CEIL_L_S */ 13273 2904, 13274 /* CEIL_L_S_MMR6 */ 13275 2906, 13276 /* CEIL_W_D32 */ 13277 2908, 13278 /* CEIL_W_D64 */ 13279 2910, 13280 /* CEIL_W_D_MMR6 */ 13281 2912, 13282 /* CEIL_W_MM */ 13283 2914, 13284 /* CEIL_W_S */ 13285 2916, 13286 /* CEIL_W_S_MM */ 13287 2918, 13288 /* CEIL_W_S_MMR6 */ 13289 2920, 13290 /* CEQI_B */ 13291 2922, 13292 /* CEQI_D */ 13293 2925, 13294 /* CEQI_H */ 13295 2928, 13296 /* CEQI_W */ 13297 2931, 13298 /* CEQ_B */ 13299 2934, 13300 /* CEQ_D */ 13301 2937, 13302 /* CEQ_H */ 13303 2940, 13304 /* CEQ_W */ 13305 2943, 13306 /* CFC1 */ 13307 2946, 13308 /* CFC1_MM */ 13309 2948, 13310 /* CFC2_MM */ 13311 2950, 13312 /* CFCMSA */ 13313 2952, 13314 /* CINS */ 13315 2954, 13316 /* CINS32 */ 13317 2958, 13318 /* CINS64_32 */ 13319 2962, 13320 /* CINS_i32 */ 13321 2966, 13322 /* CLASS_D */ 13323 2970, 13324 /* CLASS_D_MMR6 */ 13325 2972, 13326 /* CLASS_S */ 13327 2974, 13328 /* CLASS_S_MMR6 */ 13329 2976, 13330 /* CLEI_S_B */ 13331 2978, 13332 /* CLEI_S_D */ 13333 2981, 13334 /* CLEI_S_H */ 13335 2984, 13336 /* CLEI_S_W */ 13337 2987, 13338 /* CLEI_U_B */ 13339 2990, 13340 /* CLEI_U_D */ 13341 2993, 13342 /* CLEI_U_H */ 13343 2996, 13344 /* CLEI_U_W */ 13345 2999, 13346 /* CLE_S_B */ 13347 3002, 13348 /* CLE_S_D */ 13349 3005, 13350 /* CLE_S_H */ 13351 3008, 13352 /* CLE_S_W */ 13353 3011, 13354 /* CLE_U_B */ 13355 3014, 13356 /* CLE_U_D */ 13357 3017, 13358 /* CLE_U_H */ 13359 3020, 13360 /* CLE_U_W */ 13361 3023, 13362 /* CLO */ 13363 3026, 13364 /* CLO_MM */ 13365 3028, 13366 /* CLO_MMR6 */ 13367 3030, 13368 /* CLO_R6 */ 13369 3032, 13370 /* CLTI_S_B */ 13371 3034, 13372 /* CLTI_S_D */ 13373 3037, 13374 /* CLTI_S_H */ 13375 3040, 13376 /* CLTI_S_W */ 13377 3043, 13378 /* CLTI_U_B */ 13379 3046, 13380 /* CLTI_U_D */ 13381 3049, 13382 /* CLTI_U_H */ 13383 3052, 13384 /* CLTI_U_W */ 13385 3055, 13386 /* CLT_S_B */ 13387 3058, 13388 /* CLT_S_D */ 13389 3061, 13390 /* CLT_S_H */ 13391 3064, 13392 /* CLT_S_W */ 13393 3067, 13394 /* CLT_U_B */ 13395 3070, 13396 /* CLT_U_D */ 13397 3073, 13398 /* CLT_U_H */ 13399 3076, 13400 /* CLT_U_W */ 13401 3079, 13402 /* CLZ */ 13403 3082, 13404 /* CLZ_MM */ 13405 3084, 13406 /* CLZ_MMR6 */ 13407 3086, 13408 /* CLZ_R6 */ 13409 3088, 13410 /* CMPGDU_EQ_QB */ 13411 3090, 13412 /* CMPGDU_EQ_QB_MMR2 */ 13413 3093, 13414 /* CMPGDU_LE_QB */ 13415 3096, 13416 /* CMPGDU_LE_QB_MMR2 */ 13417 3099, 13418 /* CMPGDU_LT_QB */ 13419 3102, 13420 /* CMPGDU_LT_QB_MMR2 */ 13421 3105, 13422 /* CMPGU_EQ_QB */ 13423 3108, 13424 /* CMPGU_EQ_QB_MM */ 13425 3111, 13426 /* CMPGU_LE_QB */ 13427 3114, 13428 /* CMPGU_LE_QB_MM */ 13429 3117, 13430 /* CMPGU_LT_QB */ 13431 3120, 13432 /* CMPGU_LT_QB_MM */ 13433 3123, 13434 /* CMPU_EQ_QB */ 13435 3126, 13436 /* CMPU_EQ_QB_MM */ 13437 3128, 13438 /* CMPU_LE_QB */ 13439 3130, 13440 /* CMPU_LE_QB_MM */ 13441 3132, 13442 /* CMPU_LT_QB */ 13443 3134, 13444 /* CMPU_LT_QB_MM */ 13445 3136, 13446 /* CMP_AF_D_MMR6 */ 13447 3138, 13448 /* CMP_AF_S_MMR6 */ 13449 3141, 13450 /* CMP_EQ_D */ 13451 3144, 13452 /* CMP_EQ_D_MMR6 */ 13453 3147, 13454 /* CMP_EQ_PH */ 13455 3150, 13456 /* CMP_EQ_PH_MM */ 13457 3152, 13458 /* CMP_EQ_S */ 13459 3154, 13460 /* CMP_EQ_S_MMR6 */ 13461 3157, 13462 /* CMP_F_D */ 13463 3160, 13464 /* CMP_F_S */ 13465 3163, 13466 /* CMP_LE_D */ 13467 3166, 13468 /* CMP_LE_D_MMR6 */ 13469 3169, 13470 /* CMP_LE_PH */ 13471 3172, 13472 /* CMP_LE_PH_MM */ 13473 3174, 13474 /* CMP_LE_S */ 13475 3176, 13476 /* CMP_LE_S_MMR6 */ 13477 3179, 13478 /* CMP_LT_D */ 13479 3182, 13480 /* CMP_LT_D_MMR6 */ 13481 3185, 13482 /* CMP_LT_PH */ 13483 3188, 13484 /* CMP_LT_PH_MM */ 13485 3190, 13486 /* CMP_LT_S */ 13487 3192, 13488 /* CMP_LT_S_MMR6 */ 13489 3195, 13490 /* CMP_SAF_D */ 13491 3198, 13492 /* CMP_SAF_D_MMR6 */ 13493 3201, 13494 /* CMP_SAF_S */ 13495 3204, 13496 /* CMP_SAF_S_MMR6 */ 13497 3207, 13498 /* CMP_SEQ_D */ 13499 3210, 13500 /* CMP_SEQ_D_MMR6 */ 13501 3213, 13502 /* CMP_SEQ_S */ 13503 3216, 13504 /* CMP_SEQ_S_MMR6 */ 13505 3219, 13506 /* CMP_SLE_D */ 13507 3222, 13508 /* CMP_SLE_D_MMR6 */ 13509 3225, 13510 /* CMP_SLE_S */ 13511 3228, 13512 /* CMP_SLE_S_MMR6 */ 13513 3231, 13514 /* CMP_SLT_D */ 13515 3234, 13516 /* CMP_SLT_D_MMR6 */ 13517 3237, 13518 /* CMP_SLT_S */ 13519 3240, 13520 /* CMP_SLT_S_MMR6 */ 13521 3243, 13522 /* CMP_SUEQ_D */ 13523 3246, 13524 /* CMP_SUEQ_D_MMR6 */ 13525 3249, 13526 /* CMP_SUEQ_S */ 13527 3252, 13528 /* CMP_SUEQ_S_MMR6 */ 13529 3255, 13530 /* CMP_SULE_D */ 13531 3258, 13532 /* CMP_SULE_D_MMR6 */ 13533 3261, 13534 /* CMP_SULE_S */ 13535 3264, 13536 /* CMP_SULE_S_MMR6 */ 13537 3267, 13538 /* CMP_SULT_D */ 13539 3270, 13540 /* CMP_SULT_D_MMR6 */ 13541 3273, 13542 /* CMP_SULT_S */ 13543 3276, 13544 /* CMP_SULT_S_MMR6 */ 13545 3279, 13546 /* CMP_SUN_D */ 13547 3282, 13548 /* CMP_SUN_D_MMR6 */ 13549 3285, 13550 /* CMP_SUN_S */ 13551 3288, 13552 /* CMP_SUN_S_MMR6 */ 13553 3291, 13554 /* CMP_UEQ_D */ 13555 3294, 13556 /* CMP_UEQ_D_MMR6 */ 13557 3297, 13558 /* CMP_UEQ_S */ 13559 3300, 13560 /* CMP_UEQ_S_MMR6 */ 13561 3303, 13562 /* CMP_ULE_D */ 13563 3306, 13564 /* CMP_ULE_D_MMR6 */ 13565 3309, 13566 /* CMP_ULE_S */ 13567 3312, 13568 /* CMP_ULE_S_MMR6 */ 13569 3315, 13570 /* CMP_ULT_D */ 13571 3318, 13572 /* CMP_ULT_D_MMR6 */ 13573 3321, 13574 /* CMP_ULT_S */ 13575 3324, 13576 /* CMP_ULT_S_MMR6 */ 13577 3327, 13578 /* CMP_UN_D */ 13579 3330, 13580 /* CMP_UN_D_MMR6 */ 13581 3333, 13582 /* CMP_UN_S */ 13583 3336, 13584 /* CMP_UN_S_MMR6 */ 13585 3339, 13586 /* COPY_S_B */ 13587 3342, 13588 /* COPY_S_D */ 13589 3345, 13590 /* COPY_S_H */ 13591 3348, 13592 /* COPY_S_W */ 13593 3351, 13594 /* COPY_U_B */ 13595 3354, 13596 /* COPY_U_H */ 13597 3357, 13598 /* COPY_U_W */ 13599 3360, 13600 /* CRC32B */ 13601 3363, 13602 /* CRC32CB */ 13603 3366, 13604 /* CRC32CD */ 13605 3369, 13606 /* CRC32CH */ 13607 3372, 13608 /* CRC32CW */ 13609 3375, 13610 /* CRC32D */ 13611 3378, 13612 /* CRC32H */ 13613 3381, 13614 /* CRC32W */ 13615 3384, 13616 /* CTC1 */ 13617 3387, 13618 /* CTC1_MM */ 13619 3389, 13620 /* CTC2_MM */ 13621 3391, 13622 /* CTCMSA */ 13623 3393, 13624 /* CVT_D32_S */ 13625 3395, 13626 /* CVT_D32_S_MM */ 13627 3397, 13628 /* CVT_D32_W */ 13629 3399, 13630 /* CVT_D32_W_MM */ 13631 3401, 13632 /* CVT_D64_L */ 13633 3403, 13634 /* CVT_D64_S */ 13635 3405, 13636 /* CVT_D64_S_MM */ 13637 3407, 13638 /* CVT_D64_W */ 13639 3409, 13640 /* CVT_D64_W_MM */ 13641 3411, 13642 /* CVT_D_L_MMR6 */ 13643 3413, 13644 /* CVT_L_D64 */ 13645 3415, 13646 /* CVT_L_D64_MM */ 13647 3417, 13648 /* CVT_L_D_MMR6 */ 13649 3419, 13650 /* CVT_L_S */ 13651 3421, 13652 /* CVT_L_S_MM */ 13653 3423, 13654 /* CVT_L_S_MMR6 */ 13655 3425, 13656 /* CVT_PS_PW64 */ 13657 3427, 13658 /* CVT_PS_S64 */ 13659 3429, 13660 /* CVT_PW_PS64 */ 13661 3432, 13662 /* CVT_S_D32 */ 13663 3434, 13664 /* CVT_S_D32_MM */ 13665 3436, 13666 /* CVT_S_D64 */ 13667 3438, 13668 /* CVT_S_D64_MM */ 13669 3440, 13670 /* CVT_S_L */ 13671 3442, 13672 /* CVT_S_L_MMR6 */ 13673 3444, 13674 /* CVT_S_PL64 */ 13675 3446, 13676 /* CVT_S_PU64 */ 13677 3448, 13678 /* CVT_S_W */ 13679 3450, 13680 /* CVT_S_W_MM */ 13681 3452, 13682 /* CVT_S_W_MMR6 */ 13683 3454, 13684 /* CVT_W_D32 */ 13685 3456, 13686 /* CVT_W_D32_MM */ 13687 3458, 13688 /* CVT_W_D64 */ 13689 3460, 13690 /* CVT_W_D64_MM */ 13691 3462, 13692 /* CVT_W_S */ 13693 3464, 13694 /* CVT_W_S_MM */ 13695 3466, 13696 /* CVT_W_S_MMR6 */ 13697 3468, 13698 /* C_EQ_D32 */ 13699 3470, 13700 /* C_EQ_D32_MM */ 13701 3473, 13702 /* C_EQ_D64 */ 13703 3476, 13704 /* C_EQ_D64_MM */ 13705 3479, 13706 /* C_EQ_S */ 13707 3482, 13708 /* C_EQ_S_MM */ 13709 3485, 13710 /* C_F_D32 */ 13711 3488, 13712 /* C_F_D32_MM */ 13713 3491, 13714 /* C_F_D64 */ 13715 3494, 13716 /* C_F_D64_MM */ 13717 3497, 13718 /* C_F_S */ 13719 3500, 13720 /* C_F_S_MM */ 13721 3503, 13722 /* C_LE_D32 */ 13723 3506, 13724 /* C_LE_D32_MM */ 13725 3509, 13726 /* C_LE_D64 */ 13727 3512, 13728 /* C_LE_D64_MM */ 13729 3515, 13730 /* C_LE_S */ 13731 3518, 13732 /* C_LE_S_MM */ 13733 3521, 13734 /* C_LT_D32 */ 13735 3524, 13736 /* C_LT_D32_MM */ 13737 3527, 13738 /* C_LT_D64 */ 13739 3530, 13740 /* C_LT_D64_MM */ 13741 3533, 13742 /* C_LT_S */ 13743 3536, 13744 /* C_LT_S_MM */ 13745 3539, 13746 /* C_NGE_D32 */ 13747 3542, 13748 /* C_NGE_D32_MM */ 13749 3545, 13750 /* C_NGE_D64 */ 13751 3548, 13752 /* C_NGE_D64_MM */ 13753 3551, 13754 /* C_NGE_S */ 13755 3554, 13756 /* C_NGE_S_MM */ 13757 3557, 13758 /* C_NGLE_D32 */ 13759 3560, 13760 /* C_NGLE_D32_MM */ 13761 3563, 13762 /* C_NGLE_D64 */ 13763 3566, 13764 /* C_NGLE_D64_MM */ 13765 3569, 13766 /* C_NGLE_S */ 13767 3572, 13768 /* C_NGLE_S_MM */ 13769 3575, 13770 /* C_NGL_D32 */ 13771 3578, 13772 /* C_NGL_D32_MM */ 13773 3581, 13774 /* C_NGL_D64 */ 13775 3584, 13776 /* C_NGL_D64_MM */ 13777 3587, 13778 /* C_NGL_S */ 13779 3590, 13780 /* C_NGL_S_MM */ 13781 3593, 13782 /* C_NGT_D32 */ 13783 3596, 13784 /* C_NGT_D32_MM */ 13785 3599, 13786 /* C_NGT_D64 */ 13787 3602, 13788 /* C_NGT_D64_MM */ 13789 3605, 13790 /* C_NGT_S */ 13791 3608, 13792 /* C_NGT_S_MM */ 13793 3611, 13794 /* C_OLE_D32 */ 13795 3614, 13796 /* C_OLE_D32_MM */ 13797 3617, 13798 /* C_OLE_D64 */ 13799 3620, 13800 /* C_OLE_D64_MM */ 13801 3623, 13802 /* C_OLE_S */ 13803 3626, 13804 /* C_OLE_S_MM */ 13805 3629, 13806 /* C_OLT_D32 */ 13807 3632, 13808 /* C_OLT_D32_MM */ 13809 3635, 13810 /* C_OLT_D64 */ 13811 3638, 13812 /* C_OLT_D64_MM */ 13813 3641, 13814 /* C_OLT_S */ 13815 3644, 13816 /* C_OLT_S_MM */ 13817 3647, 13818 /* C_SEQ_D32 */ 13819 3650, 13820 /* C_SEQ_D32_MM */ 13821 3653, 13822 /* C_SEQ_D64 */ 13823 3656, 13824 /* C_SEQ_D64_MM */ 13825 3659, 13826 /* C_SEQ_S */ 13827 3662, 13828 /* C_SEQ_S_MM */ 13829 3665, 13830 /* C_SF_D32 */ 13831 3668, 13832 /* C_SF_D32_MM */ 13833 3671, 13834 /* C_SF_D64 */ 13835 3674, 13836 /* C_SF_D64_MM */ 13837 3677, 13838 /* C_SF_S */ 13839 3680, 13840 /* C_SF_S_MM */ 13841 3683, 13842 /* C_UEQ_D32 */ 13843 3686, 13844 /* C_UEQ_D32_MM */ 13845 3689, 13846 /* C_UEQ_D64 */ 13847 3692, 13848 /* C_UEQ_D64_MM */ 13849 3695, 13850 /* C_UEQ_S */ 13851 3698, 13852 /* C_UEQ_S_MM */ 13853 3701, 13854 /* C_ULE_D32 */ 13855 3704, 13856 /* C_ULE_D32_MM */ 13857 3707, 13858 /* C_ULE_D64 */ 13859 3710, 13860 /* C_ULE_D64_MM */ 13861 3713, 13862 /* C_ULE_S */ 13863 3716, 13864 /* C_ULE_S_MM */ 13865 3719, 13866 /* C_ULT_D32 */ 13867 3722, 13868 /* C_ULT_D32_MM */ 13869 3725, 13870 /* C_ULT_D64 */ 13871 3728, 13872 /* C_ULT_D64_MM */ 13873 3731, 13874 /* C_ULT_S */ 13875 3734, 13876 /* C_ULT_S_MM */ 13877 3737, 13878 /* C_UN_D32 */ 13879 3740, 13880 /* C_UN_D32_MM */ 13881 3743, 13882 /* C_UN_D64 */ 13883 3746, 13884 /* C_UN_D64_MM */ 13885 3749, 13886 /* C_UN_S */ 13887 3752, 13888 /* C_UN_S_MM */ 13889 3755, 13890 /* CmpRxRy16 */ 13891 3758, 13892 /* CmpiRxImm16 */ 13893 3760, 13894 /* CmpiRxImmX16 */ 13895 3762, 13896 /* DADD */ 13897 3764, 13898 /* DADDi */ 13899 3767, 13900 /* DADDiu */ 13901 3770, 13902 /* DADDu */ 13903 3773, 13904 /* DAHI */ 13905 3776, 13906 /* DALIGN */ 13907 3779, 13908 /* DATI */ 13909 3783, 13910 /* DAUI */ 13911 3786, 13912 /* DBITSWAP */ 13913 3789, 13914 /* DCLO */ 13915 3791, 13916 /* DCLO_R6 */ 13917 3793, 13918 /* DCLZ */ 13919 3795, 13920 /* DCLZ_R6 */ 13921 3797, 13922 /* DDIV */ 13923 3799, 13924 /* DDIVU */ 13925 3802, 13926 /* DERET */ 13927 3805, 13928 /* DERET_MM */ 13929 3805, 13930 /* DERET_MMR6 */ 13931 3805, 13932 /* DEXT */ 13933 3805, 13934 /* DEXT64_32 */ 13935 3809, 13936 /* DEXTM */ 13937 3813, 13938 /* DEXTU */ 13939 3817, 13940 /* DI */ 13941 3821, 13942 /* DINS */ 13943 3822, 13944 /* DINSM */ 13945 3827, 13946 /* DINSU */ 13947 3832, 13948 /* DIV */ 13949 3837, 13950 /* DIVU */ 13951 3840, 13952 /* DIVU_MMR6 */ 13953 3843, 13954 /* DIV_MMR6 */ 13955 3846, 13956 /* DIV_S_B */ 13957 3849, 13958 /* DIV_S_D */ 13959 3852, 13960 /* DIV_S_H */ 13961 3855, 13962 /* DIV_S_W */ 13963 3858, 13964 /* DIV_U_B */ 13965 3861, 13966 /* DIV_U_D */ 13967 3864, 13968 /* DIV_U_H */ 13969 3867, 13970 /* DIV_U_W */ 13971 3870, 13972 /* DI_MM */ 13973 3873, 13974 /* DI_MMR6 */ 13975 3874, 13976 /* DLSA */ 13977 3875, 13978 /* DLSA_R6 */ 13979 3879, 13980 /* DMFC0 */ 13981 3883, 13982 /* DMFC1 */ 13983 3886, 13984 /* DMFC2 */ 13985 3888, 13986 /* DMFC2_OCTEON */ 13987 3891, 13988 /* DMFGC0 */ 13989 3893, 13990 /* DMOD */ 13991 3896, 13992 /* DMODU */ 13993 3899, 13994 /* DMT */ 13995 3902, 13996 /* DMTC0 */ 13997 3903, 13998 /* DMTC1 */ 13999 3906, 14000 /* DMTC2 */ 14001 3908, 14002 /* DMTC2_OCTEON */ 14003 3911, 14004 /* DMTGC0 */ 14005 3913, 14006 /* DMUH */ 14007 3916, 14008 /* DMUHU */ 14009 3919, 14010 /* DMUL */ 14011 3922, 14012 /* DMULT */ 14013 3925, 14014 /* DMULTu */ 14015 3927, 14016 /* DMULU */ 14017 3929, 14018 /* DMUL_R6 */ 14019 3932, 14020 /* DOTP_S_D */ 14021 3935, 14022 /* DOTP_S_H */ 14023 3938, 14024 /* DOTP_S_W */ 14025 3941, 14026 /* DOTP_U_D */ 14027 3944, 14028 /* DOTP_U_H */ 14029 3947, 14030 /* DOTP_U_W */ 14031 3950, 14032 /* DPADD_S_D */ 14033 3953, 14034 /* DPADD_S_H */ 14035 3957, 14036 /* DPADD_S_W */ 14037 3961, 14038 /* DPADD_U_D */ 14039 3965, 14040 /* DPADD_U_H */ 14041 3969, 14042 /* DPADD_U_W */ 14043 3973, 14044 /* DPAQX_SA_W_PH */ 14045 3977, 14046 /* DPAQX_SA_W_PH_MMR2 */ 14047 3981, 14048 /* DPAQX_S_W_PH */ 14049 3985, 14050 /* DPAQX_S_W_PH_MMR2 */ 14051 3989, 14052 /* DPAQ_SA_L_W */ 14053 3993, 14054 /* DPAQ_SA_L_W_MM */ 14055 3997, 14056 /* DPAQ_S_W_PH */ 14057 4001, 14058 /* DPAQ_S_W_PH_MM */ 14059 4005, 14060 /* DPAU_H_QBL */ 14061 4009, 14062 /* DPAU_H_QBL_MM */ 14063 4013, 14064 /* DPAU_H_QBR */ 14065 4017, 14066 /* DPAU_H_QBR_MM */ 14067 4021, 14068 /* DPAX_W_PH */ 14069 4025, 14070 /* DPAX_W_PH_MMR2 */ 14071 4029, 14072 /* DPA_W_PH */ 14073 4033, 14074 /* DPA_W_PH_MMR2 */ 14075 4037, 14076 /* DPOP */ 14077 4041, 14078 /* DPSQX_SA_W_PH */ 14079 4043, 14080 /* DPSQX_SA_W_PH_MMR2 */ 14081 4047, 14082 /* DPSQX_S_W_PH */ 14083 4051, 14084 /* DPSQX_S_W_PH_MMR2 */ 14085 4055, 14086 /* DPSQ_SA_L_W */ 14087 4059, 14088 /* DPSQ_SA_L_W_MM */ 14089 4063, 14090 /* DPSQ_S_W_PH */ 14091 4067, 14092 /* DPSQ_S_W_PH_MM */ 14093 4071, 14094 /* DPSUB_S_D */ 14095 4075, 14096 /* DPSUB_S_H */ 14097 4079, 14098 /* DPSUB_S_W */ 14099 4083, 14100 /* DPSUB_U_D */ 14101 4087, 14102 /* DPSUB_U_H */ 14103 4091, 14104 /* DPSUB_U_W */ 14105 4095, 14106 /* DPSU_H_QBL */ 14107 4099, 14108 /* DPSU_H_QBL_MM */ 14109 4103, 14110 /* DPSU_H_QBR */ 14111 4107, 14112 /* DPSU_H_QBR_MM */ 14113 4111, 14114 /* DPSX_W_PH */ 14115 4115, 14116 /* DPSX_W_PH_MMR2 */ 14117 4119, 14118 /* DPS_W_PH */ 14119 4123, 14120 /* DPS_W_PH_MMR2 */ 14121 4127, 14122 /* DROTR */ 14123 4131, 14124 /* DROTR32 */ 14125 4134, 14126 /* DROTRV */ 14127 4137, 14128 /* DSBH */ 14129 4140, 14130 /* DSDIV */ 14131 4142, 14132 /* DSHD */ 14133 4144, 14134 /* DSLL */ 14135 4146, 14136 /* DSLL32 */ 14137 4149, 14138 /* DSLL64_32 */ 14139 4152, 14140 /* DSLLV */ 14141 4154, 14142 /* DSRA */ 14143 4157, 14144 /* DSRA32 */ 14145 4160, 14146 /* DSRAV */ 14147 4163, 14148 /* DSRL */ 14149 4166, 14150 /* DSRL32 */ 14151 4169, 14152 /* DSRLV */ 14153 4172, 14154 /* DSUB */ 14155 4175, 14156 /* DSUBu */ 14157 4178, 14158 /* DUDIV */ 14159 4181, 14160 /* DVP */ 14161 4183, 14162 /* DVPE */ 14163 4184, 14164 /* DVP_MMR6 */ 14165 4185, 14166 /* DivRxRy16 */ 14167 4186, 14168 /* DivuRxRy16 */ 14169 4188, 14170 /* EHB */ 14171 4190, 14172 /* EHB_MM */ 14173 4190, 14174 /* EHB_MMR6 */ 14175 4190, 14176 /* EI */ 14177 4190, 14178 /* EI_MM */ 14179 4191, 14180 /* EI_MMR6 */ 14181 4192, 14182 /* EMT */ 14183 4193, 14184 /* ERET */ 14185 4194, 14186 /* ERETNC */ 14187 4194, 14188 /* ERETNC_MMR6 */ 14189 4194, 14190 /* ERET_MM */ 14191 4194, 14192 /* ERET_MMR6 */ 14193 4194, 14194 /* EVP */ 14195 4194, 14196 /* EVPE */ 14197 4195, 14198 /* EVP_MMR6 */ 14199 4196, 14200 /* EXT */ 14201 4197, 14202 /* EXTP */ 14203 4201, 14204 /* EXTPDP */ 14205 4204, 14206 /* EXTPDPV */ 14207 4207, 14208 /* EXTPDPV_MM */ 14209 4210, 14210 /* EXTPDP_MM */ 14211 4213, 14212 /* EXTPV */ 14213 4216, 14214 /* EXTPV_MM */ 14215 4219, 14216 /* EXTP_MM */ 14217 4222, 14218 /* EXTRV_RS_W */ 14219 4225, 14220 /* EXTRV_RS_W_MM */ 14221 4228, 14222 /* EXTRV_R_W */ 14223 4231, 14224 /* EXTRV_R_W_MM */ 14225 4234, 14226 /* EXTRV_S_H */ 14227 4237, 14228 /* EXTRV_S_H_MM */ 14229 4240, 14230 /* EXTRV_W */ 14231 4243, 14232 /* EXTRV_W_MM */ 14233 4246, 14234 /* EXTR_RS_W */ 14235 4249, 14236 /* EXTR_RS_W_MM */ 14237 4252, 14238 /* EXTR_R_W */ 14239 4255, 14240 /* EXTR_R_W_MM */ 14241 4258, 14242 /* EXTR_S_H */ 14243 4261, 14244 /* EXTR_S_H_MM */ 14245 4264, 14246 /* EXTR_W */ 14247 4267, 14248 /* EXTR_W_MM */ 14249 4270, 14250 /* EXTS */ 14251 4273, 14252 /* EXTS32 */ 14253 4277, 14254 /* EXT_MM */ 14255 4281, 14256 /* EXT_MMR6 */ 14257 4285, 14258 /* FABS_D32 */ 14259 4289, 14260 /* FABS_D32_MM */ 14261 4291, 14262 /* FABS_D64 */ 14263 4293, 14264 /* FABS_D64_MM */ 14265 4295, 14266 /* FABS_S */ 14267 4297, 14268 /* FABS_S_MM */ 14269 4299, 14270 /* FADD_D */ 14271 4301, 14272 /* FADD_D32 */ 14273 4304, 14274 /* FADD_D32_MM */ 14275 4307, 14276 /* FADD_D64 */ 14277 4310, 14278 /* FADD_D64_MM */ 14279 4313, 14280 /* FADD_PS64 */ 14281 4316, 14282 /* FADD_S */ 14283 4319, 14284 /* FADD_S_MM */ 14285 4322, 14286 /* FADD_S_MMR6 */ 14287 4325, 14288 /* FADD_W */ 14289 4328, 14290 /* FCAF_D */ 14291 4331, 14292 /* FCAF_W */ 14293 4334, 14294 /* FCEQ_D */ 14295 4337, 14296 /* FCEQ_W */ 14297 4340, 14298 /* FCLASS_D */ 14299 4343, 14300 /* FCLASS_W */ 14301 4345, 14302 /* FCLE_D */ 14303 4347, 14304 /* FCLE_W */ 14305 4350, 14306 /* FCLT_D */ 14307 4353, 14308 /* FCLT_W */ 14309 4356, 14310 /* FCMP_D32 */ 14311 4359, 14312 /* FCMP_D32_MM */ 14313 4362, 14314 /* FCMP_D64 */ 14315 4365, 14316 /* FCMP_S32 */ 14317 4368, 14318 /* FCMP_S32_MM */ 14319 4371, 14320 /* FCNE_D */ 14321 4374, 14322 /* FCNE_W */ 14323 4377, 14324 /* FCOR_D */ 14325 4380, 14326 /* FCOR_W */ 14327 4383, 14328 /* FCUEQ_D */ 14329 4386, 14330 /* FCUEQ_W */ 14331 4389, 14332 /* FCULE_D */ 14333 4392, 14334 /* FCULE_W */ 14335 4395, 14336 /* FCULT_D */ 14337 4398, 14338 /* FCULT_W */ 14339 4401, 14340 /* FCUNE_D */ 14341 4404, 14342 /* FCUNE_W */ 14343 4407, 14344 /* FCUN_D */ 14345 4410, 14346 /* FCUN_W */ 14347 4413, 14348 /* FDIV_D */ 14349 4416, 14350 /* FDIV_D32 */ 14351 4419, 14352 /* FDIV_D32_MM */ 14353 4422, 14354 /* FDIV_D64 */ 14355 4425, 14356 /* FDIV_D64_MM */ 14357 4428, 14358 /* FDIV_S */ 14359 4431, 14360 /* FDIV_S_MM */ 14361 4434, 14362 /* FDIV_S_MMR6 */ 14363 4437, 14364 /* FDIV_W */ 14365 4440, 14366 /* FEXDO_H */ 14367 4443, 14368 /* FEXDO_W */ 14369 4446, 14370 /* FEXP2_D */ 14371 4449, 14372 /* FEXP2_W */ 14373 4452, 14374 /* FEXUPL_D */ 14375 4455, 14376 /* FEXUPL_W */ 14377 4457, 14378 /* FEXUPR_D */ 14379 4459, 14380 /* FEXUPR_W */ 14381 4461, 14382 /* FFINT_S_D */ 14383 4463, 14384 /* FFINT_S_W */ 14385 4465, 14386 /* FFINT_U_D */ 14387 4467, 14388 /* FFINT_U_W */ 14389 4469, 14390 /* FFQL_D */ 14391 4471, 14392 /* FFQL_W */ 14393 4473, 14394 /* FFQR_D */ 14395 4475, 14396 /* FFQR_W */ 14397 4477, 14398 /* FILL_B */ 14399 4479, 14400 /* FILL_D */ 14401 4481, 14402 /* FILL_H */ 14403 4483, 14404 /* FILL_W */ 14405 4485, 14406 /* FLOG2_D */ 14407 4487, 14408 /* FLOG2_W */ 14409 4489, 14410 /* FLOOR_L_D64 */ 14411 4491, 14412 /* FLOOR_L_D_MMR6 */ 14413 4493, 14414 /* FLOOR_L_S */ 14415 4495, 14416 /* FLOOR_L_S_MMR6 */ 14417 4497, 14418 /* FLOOR_W_D32 */ 14419 4499, 14420 /* FLOOR_W_D64 */ 14421 4501, 14422 /* FLOOR_W_D_MMR6 */ 14423 4503, 14424 /* FLOOR_W_MM */ 14425 4505, 14426 /* FLOOR_W_S */ 14427 4507, 14428 /* FLOOR_W_S_MM */ 14429 4509, 14430 /* FLOOR_W_S_MMR6 */ 14431 4511, 14432 /* FMADD_D */ 14433 4513, 14434 /* FMADD_W */ 14435 4517, 14436 /* FMAX_A_D */ 14437 4521, 14438 /* FMAX_A_W */ 14439 4524, 14440 /* FMAX_D */ 14441 4527, 14442 /* FMAX_W */ 14443 4530, 14444 /* FMIN_A_D */ 14445 4533, 14446 /* FMIN_A_W */ 14447 4536, 14448 /* FMIN_D */ 14449 4539, 14450 /* FMIN_W */ 14451 4542, 14452 /* FMOV_D32 */ 14453 4545, 14454 /* FMOV_D32_MM */ 14455 4547, 14456 /* FMOV_D64 */ 14457 4549, 14458 /* FMOV_D64_MM */ 14459 4551, 14460 /* FMOV_D_MMR6 */ 14461 4553, 14462 /* FMOV_S */ 14463 4555, 14464 /* FMOV_S_MM */ 14465 4557, 14466 /* FMOV_S_MMR6 */ 14467 4559, 14468 /* FMSUB_D */ 14469 4561, 14470 /* FMSUB_W */ 14471 4565, 14472 /* FMUL_D */ 14473 4569, 14474 /* FMUL_D32 */ 14475 4572, 14476 /* FMUL_D32_MM */ 14477 4575, 14478 /* FMUL_D64 */ 14479 4578, 14480 /* FMUL_D64_MM */ 14481 4581, 14482 /* FMUL_PS64 */ 14483 4584, 14484 /* FMUL_S */ 14485 4587, 14486 /* FMUL_S_MM */ 14487 4590, 14488 /* FMUL_S_MMR6 */ 14489 4593, 14490 /* FMUL_W */ 14491 4596, 14492 /* FNEG_D32 */ 14493 4599, 14494 /* FNEG_D32_MM */ 14495 4601, 14496 /* FNEG_D64 */ 14497 4603, 14498 /* FNEG_D64_MM */ 14499 4605, 14500 /* FNEG_S */ 14501 4607, 14502 /* FNEG_S_MM */ 14503 4609, 14504 /* FNEG_S_MMR6 */ 14505 4611, 14506 /* FORK */ 14507 4613, 14508 /* FRCP_D */ 14509 4616, 14510 /* FRCP_W */ 14511 4618, 14512 /* FRINT_D */ 14513 4620, 14514 /* FRINT_W */ 14515 4622, 14516 /* FRSQRT_D */ 14517 4624, 14518 /* FRSQRT_W */ 14519 4626, 14520 /* FSAF_D */ 14521 4628, 14522 /* FSAF_W */ 14523 4631, 14524 /* FSEQ_D */ 14525 4634, 14526 /* FSEQ_W */ 14527 4637, 14528 /* FSLE_D */ 14529 4640, 14530 /* FSLE_W */ 14531 4643, 14532 /* FSLT_D */ 14533 4646, 14534 /* FSLT_W */ 14535 4649, 14536 /* FSNE_D */ 14537 4652, 14538 /* FSNE_W */ 14539 4655, 14540 /* FSOR_D */ 14541 4658, 14542 /* FSOR_W */ 14543 4661, 14544 /* FSQRT_D */ 14545 4664, 14546 /* FSQRT_D32 */ 14547 4666, 14548 /* FSQRT_D32_MM */ 14549 4668, 14550 /* FSQRT_D64 */ 14551 4670, 14552 /* FSQRT_D64_MM */ 14553 4672, 14554 /* FSQRT_S */ 14555 4674, 14556 /* FSQRT_S_MM */ 14557 4676, 14558 /* FSQRT_W */ 14559 4678, 14560 /* FSUB_D */ 14561 4680, 14562 /* FSUB_D32 */ 14563 4683, 14564 /* FSUB_D32_MM */ 14565 4686, 14566 /* FSUB_D64 */ 14567 4689, 14568 /* FSUB_D64_MM */ 14569 4692, 14570 /* FSUB_PS64 */ 14571 4695, 14572 /* FSUB_S */ 14573 4698, 14574 /* FSUB_S_MM */ 14575 4701, 14576 /* FSUB_S_MMR6 */ 14577 4704, 14578 /* FSUB_W */ 14579 4707, 14580 /* FSUEQ_D */ 14581 4710, 14582 /* FSUEQ_W */ 14583 4713, 14584 /* FSULE_D */ 14585 4716, 14586 /* FSULE_W */ 14587 4719, 14588 /* FSULT_D */ 14589 4722, 14590 /* FSULT_W */ 14591 4725, 14592 /* FSUNE_D */ 14593 4728, 14594 /* FSUNE_W */ 14595 4731, 14596 /* FSUN_D */ 14597 4734, 14598 /* FSUN_W */ 14599 4737, 14600 /* FTINT_S_D */ 14601 4740, 14602 /* FTINT_S_W */ 14603 4742, 14604 /* FTINT_U_D */ 14605 4744, 14606 /* FTINT_U_W */ 14607 4746, 14608 /* FTQ_H */ 14609 4748, 14610 /* FTQ_W */ 14611 4751, 14612 /* FTRUNC_S_D */ 14613 4754, 14614 /* FTRUNC_S_W */ 14615 4756, 14616 /* FTRUNC_U_D */ 14617 4758, 14618 /* FTRUNC_U_W */ 14619 4760, 14620 /* GINVI */ 14621 4762, 14622 /* GINVI_MMR6 */ 14623 4763, 14624 /* GINVT */ 14625 4764, 14626 /* GINVT_MMR6 */ 14627 4766, 14628 /* HADD_S_D */ 14629 4768, 14630 /* HADD_S_H */ 14631 4771, 14632 /* HADD_S_W */ 14633 4774, 14634 /* HADD_U_D */ 14635 4777, 14636 /* HADD_U_H */ 14637 4780, 14638 /* HADD_U_W */ 14639 4783, 14640 /* HSUB_S_D */ 14641 4786, 14642 /* HSUB_S_H */ 14643 4789, 14644 /* HSUB_S_W */ 14645 4792, 14646 /* HSUB_U_D */ 14647 4795, 14648 /* HSUB_U_H */ 14649 4798, 14650 /* HSUB_U_W */ 14651 4801, 14652 /* HYPCALL */ 14653 4804, 14654 /* HYPCALL_MM */ 14655 4805, 14656 /* ILVEV_B */ 14657 4806, 14658 /* ILVEV_D */ 14659 4809, 14660 /* ILVEV_H */ 14661 4812, 14662 /* ILVEV_W */ 14663 4815, 14664 /* ILVL_B */ 14665 4818, 14666 /* ILVL_D */ 14667 4821, 14668 /* ILVL_H */ 14669 4824, 14670 /* ILVL_W */ 14671 4827, 14672 /* ILVOD_B */ 14673 4830, 14674 /* ILVOD_D */ 14675 4833, 14676 /* ILVOD_H */ 14677 4836, 14678 /* ILVOD_W */ 14679 4839, 14680 /* ILVR_B */ 14681 4842, 14682 /* ILVR_D */ 14683 4845, 14684 /* ILVR_H */ 14685 4848, 14686 /* ILVR_W */ 14687 4851, 14688 /* INS */ 14689 4854, 14690 /* INSERT_B */ 14691 4859, 14692 /* INSERT_D */ 14693 4863, 14694 /* INSERT_H */ 14695 4867, 14696 /* INSERT_W */ 14697 4871, 14698 /* INSV */ 14699 4875, 14700 /* INSVE_B */ 14701 4878, 14702 /* INSVE_D */ 14703 4883, 14704 /* INSVE_H */ 14705 4888, 14706 /* INSVE_W */ 14707 4893, 14708 /* INSV_MM */ 14709 4898, 14710 /* INS_MM */ 14711 4901, 14712 /* INS_MMR6 */ 14713 4906, 14714 /* J */ 14715 4911, 14716 /* JAL */ 14717 4912, 14718 /* JALR */ 14719 4913, 14720 /* JALR16_MM */ 14721 4915, 14722 /* JALR64 */ 14723 4916, 14724 /* JALRC16_MMR6 */ 14725 4918, 14726 /* JALRC_HB_MMR6 */ 14727 4919, 14728 /* JALRC_MMR6 */ 14729 4921, 14730 /* JALRS16_MM */ 14731 4923, 14732 /* JALRS_MM */ 14733 4924, 14734 /* JALR_HB */ 14735 4926, 14736 /* JALR_HB64 */ 14737 4928, 14738 /* JALR_MM */ 14739 4930, 14740 /* JALS_MM */ 14741 4932, 14742 /* JALX */ 14743 4933, 14744 /* JALX_MM */ 14745 4934, 14746 /* JAL_MM */ 14747 4935, 14748 /* JIALC */ 14749 4936, 14750 /* JIALC64 */ 14751 4938, 14752 /* JIALC_MMR6 */ 14753 4940, 14754 /* JIC */ 14755 4942, 14756 /* JIC64 */ 14757 4944, 14758 /* JIC_MMR6 */ 14759 4946, 14760 /* JR */ 14761 4948, 14762 /* JR16_MM */ 14763 4949, 14764 /* JR64 */ 14765 4950, 14766 /* JRADDIUSP */ 14767 4951, 14768 /* JRC16_MM */ 14769 4952, 14770 /* JRC16_MMR6 */ 14771 4953, 14772 /* JRCADDIUSP_MMR6 */ 14773 4954, 14774 /* JR_HB */ 14775 4955, 14776 /* JR_HB64 */ 14777 4956, 14778 /* JR_HB64_R6 */ 14779 4957, 14780 /* JR_HB_R6 */ 14781 4958, 14782 /* JR_MM */ 14783 4959, 14784 /* J_MM */ 14785 4960, 14786 /* Jal16 */ 14787 4961, 14788 /* JalB16 */ 14789 4962, 14790 /* JrRa16 */ 14791 4963, 14792 /* JrcRa16 */ 14793 4963, 14794 /* JrcRx16 */ 14795 4963, 14796 /* JumpLinkReg16 */ 14797 4964, 14798 /* LB */ 14799 4965, 14800 /* LB64 */ 14801 4968, 14802 /* LBE */ 14803 4971, 14804 /* LBE_MM */ 14805 4974, 14806 /* LBU16_MM */ 14807 4977, 14808 /* LBUX */ 14809 4980, 14810 /* LBUX_MM */ 14811 4983, 14812 /* LBU_MMR6 */ 14813 4986, 14814 /* LB_MM */ 14815 4989, 14816 /* LB_MMR6 */ 14817 4992, 14818 /* LBu */ 14819 4995, 14820 /* LBu64 */ 14821 4998, 14822 /* LBuE */ 14823 5001, 14824 /* LBuE_MM */ 14825 5004, 14826 /* LBu_MM */ 14827 5007, 14828 /* LD */ 14829 5010, 14830 /* LDC1 */ 14831 5013, 14832 /* LDC164 */ 14833 5016, 14834 /* LDC1_D64_MMR6 */ 14835 5019, 14836 /* LDC1_MM_D32 */ 14837 5022, 14838 /* LDC1_MM_D64 */ 14839 5025, 14840 /* LDC2 */ 14841 5028, 14842 /* LDC2_MMR6 */ 14843 5031, 14844 /* LDC2_R6 */ 14845 5034, 14846 /* LDC3 */ 14847 5037, 14848 /* LDI_B */ 14849 5040, 14850 /* LDI_D */ 14851 5042, 14852 /* LDI_H */ 14853 5044, 14854 /* LDI_W */ 14855 5046, 14856 /* LDL */ 14857 5048, 14858 /* LDPC */ 14859 5052, 14860 /* LDR */ 14861 5054, 14862 /* LDXC1 */ 14863 5058, 14864 /* LDXC164 */ 14865 5061, 14866 /* LD_B */ 14867 5064, 14868 /* LD_D */ 14869 5067, 14870 /* LD_H */ 14871 5070, 14872 /* LD_W */ 14873 5073, 14874 /* LEA_ADDiu */ 14875 5076, 14876 /* LEA_ADDiu64 */ 14877 5079, 14878 /* LEA_ADDiu_MM */ 14879 5082, 14880 /* LH */ 14881 5085, 14882 /* LH64 */ 14883 5088, 14884 /* LHE */ 14885 5091, 14886 /* LHE_MM */ 14887 5094, 14888 /* LHU16_MM */ 14889 5097, 14890 /* LHX */ 14891 5100, 14892 /* LHX_MM */ 14893 5103, 14894 /* LH_MM */ 14895 5106, 14896 /* LHu */ 14897 5109, 14898 /* LHu64 */ 14899 5112, 14900 /* LHuE */ 14901 5115, 14902 /* LHuE_MM */ 14903 5118, 14904 /* LHu_MM */ 14905 5121, 14906 /* LI16_MM */ 14907 5124, 14908 /* LI16_MMR6 */ 14909 5126, 14910 /* LL */ 14911 5128, 14912 /* LL64 */ 14913 5131, 14914 /* LL64_R6 */ 14915 5134, 14916 /* LLD */ 14917 5137, 14918 /* LLD_R6 */ 14919 5140, 14920 /* LLE */ 14921 5143, 14922 /* LLE_MM */ 14923 5146, 14924 /* LL_MM */ 14925 5149, 14926 /* LL_MMR6 */ 14927 5152, 14928 /* LL_R6 */ 14929 5155, 14930 /* LSA */ 14931 5158, 14932 /* LSA_MMR6 */ 14933 5162, 14934 /* LSA_R6 */ 14935 5166, 14936 /* LUI_MMR6 */ 14937 5170, 14938 /* LUXC1 */ 14939 5172, 14940 /* LUXC164 */ 14941 5175, 14942 /* LUXC1_MM */ 14943 5178, 14944 /* LUi */ 14945 5181, 14946 /* LUi64 */ 14947 5183, 14948 /* LUi_MM */ 14949 5185, 14950 /* LW */ 14951 5187, 14952 /* LW16_MM */ 14953 5190, 14954 /* LW64 */ 14955 5193, 14956 /* LWC1 */ 14957 5196, 14958 /* LWC1_MM */ 14959 5199, 14960 /* LWC2 */ 14961 5202, 14962 /* LWC2_MMR6 */ 14963 5205, 14964 /* LWC2_R6 */ 14965 5208, 14966 /* LWC3 */ 14967 5211, 14968 /* LWDSP */ 14969 5214, 14970 /* LWDSP_MM */ 14971 5217, 14972 /* LWE */ 14973 5220, 14974 /* LWE_MM */ 14975 5223, 14976 /* LWGP_MM */ 14977 5226, 14978 /* LWL */ 14979 5229, 14980 /* LWL64 */ 14981 5233, 14982 /* LWLE */ 14983 5237, 14984 /* LWLE_MM */ 14985 5241, 14986 /* LWL_MM */ 14987 5245, 14988 /* LWM16_MM */ 14989 5249, 14990 /* LWM16_MMR6 */ 14991 5252, 14992 /* LWM32_MM */ 14993 5255, 14994 /* LWPC */ 14995 5258, 14996 /* LWPC_MMR6 */ 14997 5260, 14998 /* LWP_MM */ 14999 5262, 15000 /* LWR */ 15001 5266, 15002 /* LWR64 */ 15003 5270, 15004 /* LWRE */ 15005 5274, 15006 /* LWRE_MM */ 15007 5278, 15008 /* LWR_MM */ 15009 5282, 15010 /* LWSP_MM */ 15011 5286, 15012 /* LWUPC */ 15013 5289, 15014 /* LWU_MM */ 15015 5291, 15016 /* LWX */ 15017 5294, 15018 /* LWXC1 */ 15019 5297, 15020 /* LWXC1_MM */ 15021 5300, 15022 /* LWXS_MM */ 15023 5303, 15024 /* LWX_MM */ 15025 5306, 15026 /* LW_MM */ 15027 5309, 15028 /* LW_MMR6 */ 15029 5312, 15030 /* LWu */ 15031 5315, 15032 /* LbRxRyOffMemX16 */ 15033 5318, 15034 /* LbuRxRyOffMemX16 */ 15035 5321, 15036 /* LhRxRyOffMemX16 */ 15037 5324, 15038 /* LhuRxRyOffMemX16 */ 15039 5327, 15040 /* LiRxImm16 */ 15041 5330, 15042 /* LiRxImmAlignX16 */ 15043 5332, 15044 /* LiRxImmX16 */ 15045 5334, 15046 /* LwRxPcTcp16 */ 15047 5336, 15048 /* LwRxPcTcpX16 */ 15049 5339, 15050 /* LwRxRyOffMemX16 */ 15051 5342, 15052 /* LwRxSpImmX16 */ 15053 5345, 15054 /* MADD */ 15055 5348, 15056 /* MADDF_D */ 15057 5350, 15058 /* MADDF_D_MMR6 */ 15059 5354, 15060 /* MADDF_S */ 15061 5358, 15062 /* MADDF_S_MMR6 */ 15063 5362, 15064 /* MADDR_Q_H */ 15065 5366, 15066 /* MADDR_Q_W */ 15067 5370, 15068 /* MADDU */ 15069 5374, 15070 /* MADDU_DSP */ 15071 5376, 15072 /* MADDU_DSP_MM */ 15073 5380, 15074 /* MADDU_MM */ 15075 5384, 15076 /* MADDV_B */ 15077 5386, 15078 /* MADDV_D */ 15079 5390, 15080 /* MADDV_H */ 15081 5394, 15082 /* MADDV_W */ 15083 5398, 15084 /* MADD_D32 */ 15085 5402, 15086 /* MADD_D32_MM */ 15087 5406, 15088 /* MADD_D64 */ 15089 5410, 15090 /* MADD_DSP */ 15091 5414, 15092 /* MADD_DSP_MM */ 15093 5418, 15094 /* MADD_MM */ 15095 5422, 15096 /* MADD_Q_H */ 15097 5424, 15098 /* MADD_Q_W */ 15099 5428, 15100 /* MADD_S */ 15101 5432, 15102 /* MADD_S_MM */ 15103 5436, 15104 /* MAQ_SA_W_PHL */ 15105 5440, 15106 /* MAQ_SA_W_PHL_MM */ 15107 5444, 15108 /* MAQ_SA_W_PHR */ 15109 5448, 15110 /* MAQ_SA_W_PHR_MM */ 15111 5452, 15112 /* MAQ_S_W_PHL */ 15113 5456, 15114 /* MAQ_S_W_PHL_MM */ 15115 5460, 15116 /* MAQ_S_W_PHR */ 15117 5464, 15118 /* MAQ_S_W_PHR_MM */ 15119 5468, 15120 /* MAXA_D */ 15121 5472, 15122 /* MAXA_D_MMR6 */ 15123 5475, 15124 /* MAXA_S */ 15125 5478, 15126 /* MAXA_S_MMR6 */ 15127 5481, 15128 /* MAXI_S_B */ 15129 5484, 15130 /* MAXI_S_D */ 15131 5487, 15132 /* MAXI_S_H */ 15133 5490, 15134 /* MAXI_S_W */ 15135 5493, 15136 /* MAXI_U_B */ 15137 5496, 15138 /* MAXI_U_D */ 15139 5499, 15140 /* MAXI_U_H */ 15141 5502, 15142 /* MAXI_U_W */ 15143 5505, 15144 /* MAX_A_B */ 15145 5508, 15146 /* MAX_A_D */ 15147 5511, 15148 /* MAX_A_H */ 15149 5514, 15150 /* MAX_A_W */ 15151 5517, 15152 /* MAX_D */ 15153 5520, 15154 /* MAX_D_MMR6 */ 15155 5523, 15156 /* MAX_S */ 15157 5526, 15158 /* MAX_S_B */ 15159 5529, 15160 /* MAX_S_D */ 15161 5532, 15162 /* MAX_S_H */ 15163 5535, 15164 /* MAX_S_MMR6 */ 15165 5538, 15166 /* MAX_S_W */ 15167 5541, 15168 /* MAX_U_B */ 15169 5544, 15170 /* MAX_U_D */ 15171 5547, 15172 /* MAX_U_H */ 15173 5550, 15174 /* MAX_U_W */ 15175 5553, 15176 /* MFC0 */ 15177 5556, 15178 /* MFC0_MMR6 */ 15179 5559, 15180 /* MFC1 */ 15181 5562, 15182 /* MFC1_D64 */ 15183 5564, 15184 /* MFC1_MM */ 15185 5566, 15186 /* MFC1_MMR6 */ 15187 5568, 15188 /* MFC2 */ 15189 5570, 15190 /* MFC2_MMR6 */ 15191 5573, 15192 /* MFGC0 */ 15193 5575, 15194 /* MFGC0_MM */ 15195 5578, 15196 /* MFHC0_MMR6 */ 15197 5581, 15198 /* MFHC1_D32 */ 15199 5584, 15200 /* MFHC1_D32_MM */ 15201 5586, 15202 /* MFHC1_D64 */ 15203 5588, 15204 /* MFHC1_D64_MM */ 15205 5590, 15206 /* MFHC2_MMR6 */ 15207 5592, 15208 /* MFHGC0 */ 15209 5594, 15210 /* MFHGC0_MM */ 15211 5597, 15212 /* MFHI */ 15213 5600, 15214 /* MFHI16_MM */ 15215 5601, 15216 /* MFHI64 */ 15217 5602, 15218 /* MFHI_DSP */ 15219 5603, 15220 /* MFHI_DSP_MM */ 15221 5605, 15222 /* MFHI_MM */ 15223 5607, 15224 /* MFLO */ 15225 5608, 15226 /* MFLO16_MM */ 15227 5609, 15228 /* MFLO64 */ 15229 5610, 15230 /* MFLO_DSP */ 15231 5611, 15232 /* MFLO_DSP_MM */ 15233 5613, 15234 /* MFLO_MM */ 15235 5615, 15236 /* MFTR */ 15237 5616, 15238 /* MINA_D */ 15239 5621, 15240 /* MINA_D_MMR6 */ 15241 5624, 15242 /* MINA_S */ 15243 5627, 15244 /* MINA_S_MMR6 */ 15245 5630, 15246 /* MINI_S_B */ 15247 5633, 15248 /* MINI_S_D */ 15249 5636, 15250 /* MINI_S_H */ 15251 5639, 15252 /* MINI_S_W */ 15253 5642, 15254 /* MINI_U_B */ 15255 5645, 15256 /* MINI_U_D */ 15257 5648, 15258 /* MINI_U_H */ 15259 5651, 15260 /* MINI_U_W */ 15261 5654, 15262 /* MIN_A_B */ 15263 5657, 15264 /* MIN_A_D */ 15265 5660, 15266 /* MIN_A_H */ 15267 5663, 15268 /* MIN_A_W */ 15269 5666, 15270 /* MIN_D */ 15271 5669, 15272 /* MIN_D_MMR6 */ 15273 5672, 15274 /* MIN_S */ 15275 5675, 15276 /* MIN_S_B */ 15277 5678, 15278 /* MIN_S_D */ 15279 5681, 15280 /* MIN_S_H */ 15281 5684, 15282 /* MIN_S_MMR6 */ 15283 5687, 15284 /* MIN_S_W */ 15285 5690, 15286 /* MIN_U_B */ 15287 5693, 15288 /* MIN_U_D */ 15289 5696, 15290 /* MIN_U_H */ 15291 5699, 15292 /* MIN_U_W */ 15293 5702, 15294 /* MOD */ 15295 5705, 15296 /* MODSUB */ 15297 5708, 15298 /* MODSUB_MM */ 15299 5711, 15300 /* MODU */ 15301 5714, 15302 /* MODU_MMR6 */ 15303 5717, 15304 /* MOD_MMR6 */ 15305 5720, 15306 /* MOD_S_B */ 15307 5723, 15308 /* MOD_S_D */ 15309 5726, 15310 /* MOD_S_H */ 15311 5729, 15312 /* MOD_S_W */ 15313 5732, 15314 /* MOD_U_B */ 15315 5735, 15316 /* MOD_U_D */ 15317 5738, 15318 /* MOD_U_H */ 15319 5741, 15320 /* MOD_U_W */ 15321 5744, 15322 /* MOVE16_MM */ 15323 5747, 15324 /* MOVE16_MMR6 */ 15325 5749, 15326 /* MOVEP_MM */ 15327 5751, 15328 /* MOVEP_MMR6 */ 15329 5755, 15330 /* MOVE_V */ 15331 5759, 15332 /* MOVF_D32 */ 15333 5761, 15334 /* MOVF_D32_MM */ 15335 5765, 15336 /* MOVF_D64 */ 15337 5769, 15338 /* MOVF_I */ 15339 5773, 15340 /* MOVF_I64 */ 15341 5777, 15342 /* MOVF_I_MM */ 15343 5781, 15344 /* MOVF_S */ 15345 5785, 15346 /* MOVF_S_MM */ 15347 5789, 15348 /* MOVN_I64_D64 */ 15349 5793, 15350 /* MOVN_I64_I */ 15351 5797, 15352 /* MOVN_I64_I64 */ 15353 5801, 15354 /* MOVN_I64_S */ 15355 5805, 15356 /* MOVN_I_D32 */ 15357 5809, 15358 /* MOVN_I_D32_MM */ 15359 5813, 15360 /* MOVN_I_D64 */ 15361 5817, 15362 /* MOVN_I_I */ 15363 5821, 15364 /* MOVN_I_I64 */ 15365 5825, 15366 /* MOVN_I_MM */ 15367 5829, 15368 /* MOVN_I_S */ 15369 5833, 15370 /* MOVN_I_S_MM */ 15371 5837, 15372 /* MOVT_D32 */ 15373 5841, 15374 /* MOVT_D32_MM */ 15375 5845, 15376 /* MOVT_D64 */ 15377 5849, 15378 /* MOVT_I */ 15379 5853, 15380 /* MOVT_I64 */ 15381 5857, 15382 /* MOVT_I_MM */ 15383 5861, 15384 /* MOVT_S */ 15385 5865, 15386 /* MOVT_S_MM */ 15387 5869, 15388 /* MOVZ_I64_D64 */ 15389 5873, 15390 /* MOVZ_I64_I */ 15391 5877, 15392 /* MOVZ_I64_I64 */ 15393 5881, 15394 /* MOVZ_I64_S */ 15395 5885, 15396 /* MOVZ_I_D32 */ 15397 5889, 15398 /* MOVZ_I_D32_MM */ 15399 5893, 15400 /* MOVZ_I_D64 */ 15401 5897, 15402 /* MOVZ_I_I */ 15403 5901, 15404 /* MOVZ_I_I64 */ 15405 5905, 15406 /* MOVZ_I_MM */ 15407 5909, 15408 /* MOVZ_I_S */ 15409 5913, 15410 /* MOVZ_I_S_MM */ 15411 5917, 15412 /* MSUB */ 15413 5921, 15414 /* MSUBF_D */ 15415 5923, 15416 /* MSUBF_D_MMR6 */ 15417 5927, 15418 /* MSUBF_S */ 15419 5931, 15420 /* MSUBF_S_MMR6 */ 15421 5935, 15422 /* MSUBR_Q_H */ 15423 5939, 15424 /* MSUBR_Q_W */ 15425 5943, 15426 /* MSUBU */ 15427 5947, 15428 /* MSUBU_DSP */ 15429 5949, 15430 /* MSUBU_DSP_MM */ 15431 5953, 15432 /* MSUBU_MM */ 15433 5957, 15434 /* MSUBV_B */ 15435 5959, 15436 /* MSUBV_D */ 15437 5963, 15438 /* MSUBV_H */ 15439 5967, 15440 /* MSUBV_W */ 15441 5971, 15442 /* MSUB_D32 */ 15443 5975, 15444 /* MSUB_D32_MM */ 15445 5979, 15446 /* MSUB_D64 */ 15447 5983, 15448 /* MSUB_DSP */ 15449 5987, 15450 /* MSUB_DSP_MM */ 15451 5991, 15452 /* MSUB_MM */ 15453 5995, 15454 /* MSUB_Q_H */ 15455 5997, 15456 /* MSUB_Q_W */ 15457 6001, 15458 /* MSUB_S */ 15459 6005, 15460 /* MSUB_S_MM */ 15461 6009, 15462 /* MTC0 */ 15463 6013, 15464 /* MTC0_MMR6 */ 15465 6016, 15466 /* MTC1 */ 15467 6019, 15468 /* MTC1_D64 */ 15469 6021, 15470 /* MTC1_D64_MM */ 15471 6023, 15472 /* MTC1_MM */ 15473 6025, 15474 /* MTC1_MMR6 */ 15475 6027, 15476 /* MTC2 */ 15477 6029, 15478 /* MTC2_MMR6 */ 15479 6032, 15480 /* MTGC0 */ 15481 6034, 15482 /* MTGC0_MM */ 15483 6037, 15484 /* MTHC0_MMR6 */ 15485 6040, 15486 /* MTHC1_D32 */ 15487 6043, 15488 /* MTHC1_D32_MM */ 15489 6046, 15490 /* MTHC1_D64 */ 15491 6049, 15492 /* MTHC1_D64_MM */ 15493 6052, 15494 /* MTHC2_MMR6 */ 15495 6055, 15496 /* MTHGC0 */ 15497 6057, 15498 /* MTHGC0_MM */ 15499 6060, 15500 /* MTHI */ 15501 6063, 15502 /* MTHI64 */ 15503 6064, 15504 /* MTHI_DSP */ 15505 6065, 15506 /* MTHI_DSP_MM */ 15507 6067, 15508 /* MTHI_MM */ 15509 6069, 15510 /* MTHLIP */ 15511 6070, 15512 /* MTHLIP_MM */ 15513 6073, 15514 /* MTLO */ 15515 6076, 15516 /* MTLO64 */ 15517 6077, 15518 /* MTLO_DSP */ 15519 6078, 15520 /* MTLO_DSP_MM */ 15521 6080, 15522 /* MTLO_MM */ 15523 6082, 15524 /* MTM0 */ 15525 6083, 15526 /* MTM1 */ 15527 6084, 15528 /* MTM2 */ 15529 6085, 15530 /* MTP0 */ 15531 6086, 15532 /* MTP1 */ 15533 6087, 15534 /* MTP2 */ 15535 6088, 15536 /* MTTR */ 15537 6089, 15538 /* MUH */ 15539 6094, 15540 /* MUHU */ 15541 6097, 15542 /* MUHU_MMR6 */ 15543 6100, 15544 /* MUH_MMR6 */ 15545 6103, 15546 /* MUL */ 15547 6106, 15548 /* MULEQ_S_W_PHL */ 15549 6109, 15550 /* MULEQ_S_W_PHL_MM */ 15551 6112, 15552 /* MULEQ_S_W_PHR */ 15553 6115, 15554 /* MULEQ_S_W_PHR_MM */ 15555 6118, 15556 /* MULEU_S_PH_QBL */ 15557 6121, 15558 /* MULEU_S_PH_QBL_MM */ 15559 6124, 15560 /* MULEU_S_PH_QBR */ 15561 6127, 15562 /* MULEU_S_PH_QBR_MM */ 15563 6130, 15564 /* MULQ_RS_PH */ 15565 6133, 15566 /* MULQ_RS_PH_MM */ 15567 6136, 15568 /* MULQ_RS_W */ 15569 6139, 15570 /* MULQ_RS_W_MMR2 */ 15571 6142, 15572 /* MULQ_S_PH */ 15573 6145, 15574 /* MULQ_S_PH_MMR2 */ 15575 6148, 15576 /* MULQ_S_W */ 15577 6151, 15578 /* MULQ_S_W_MMR2 */ 15579 6154, 15580 /* MULR_PS64 */ 15581 6157, 15582 /* MULR_Q_H */ 15583 6160, 15584 /* MULR_Q_W */ 15585 6163, 15586 /* MULSAQ_S_W_PH */ 15587 6166, 15588 /* MULSAQ_S_W_PH_MM */ 15589 6170, 15590 /* MULSA_W_PH */ 15591 6174, 15592 /* MULSA_W_PH_MMR2 */ 15593 6178, 15594 /* MULT */ 15595 6182, 15596 /* MULTU_DSP */ 15597 6184, 15598 /* MULTU_DSP_MM */ 15599 6187, 15600 /* MULT_DSP */ 15601 6190, 15602 /* MULT_DSP_MM */ 15603 6193, 15604 /* MULT_MM */ 15605 6196, 15606 /* MULTu */ 15607 6198, 15608 /* MULTu_MM */ 15609 6200, 15610 /* MULU */ 15611 6202, 15612 /* MULU_MMR6 */ 15613 6205, 15614 /* MULV_B */ 15615 6208, 15616 /* MULV_D */ 15617 6211, 15618 /* MULV_H */ 15619 6214, 15620 /* MULV_W */ 15621 6217, 15622 /* MUL_MM */ 15623 6220, 15624 /* MUL_MMR6 */ 15625 6223, 15626 /* MUL_PH */ 15627 6226, 15628 /* MUL_PH_MMR2 */ 15629 6229, 15630 /* MUL_Q_H */ 15631 6232, 15632 /* MUL_Q_W */ 15633 6235, 15634 /* MUL_R6 */ 15635 6238, 15636 /* MUL_S_PH */ 15637 6241, 15638 /* MUL_S_PH_MMR2 */ 15639 6244, 15640 /* Mfhi16 */ 15641 6247, 15642 /* Mflo16 */ 15643 6248, 15644 /* Move32R16 */ 15645 6249, 15646 /* MoveR3216 */ 15647 6251, 15648 /* NLOC_B */ 15649 6253, 15650 /* NLOC_D */ 15651 6255, 15652 /* NLOC_H */ 15653 6257, 15654 /* NLOC_W */ 15655 6259, 15656 /* NLZC_B */ 15657 6261, 15658 /* NLZC_D */ 15659 6263, 15660 /* NLZC_H */ 15661 6265, 15662 /* NLZC_W */ 15663 6267, 15664 /* NMADD_D32 */ 15665 6269, 15666 /* NMADD_D32_MM */ 15667 6273, 15668 /* NMADD_D64 */ 15669 6277, 15670 /* NMADD_S */ 15671 6281, 15672 /* NMADD_S_MM */ 15673 6285, 15674 /* NMSUB_D32 */ 15675 6289, 15676 /* NMSUB_D32_MM */ 15677 6293, 15678 /* NMSUB_D64 */ 15679 6297, 15680 /* NMSUB_S */ 15681 6301, 15682 /* NMSUB_S_MM */ 15683 6305, 15684 /* NOR */ 15685 6309, 15686 /* NOR64 */ 15687 6312, 15688 /* NORI_B */ 15689 6315, 15690 /* NOR_MM */ 15691 6318, 15692 /* NOR_MMR6 */ 15693 6321, 15694 /* NOR_V */ 15695 6324, 15696 /* NOT16_MM */ 15697 6327, 15698 /* NOT16_MMR6 */ 15699 6329, 15700 /* NegRxRy16 */ 15701 6331, 15702 /* NotRxRy16 */ 15703 6333, 15704 /* OR */ 15705 6335, 15706 /* OR16_MM */ 15707 6338, 15708 /* OR16_MMR6 */ 15709 6341, 15710 /* OR64 */ 15711 6344, 15712 /* ORI_B */ 15713 6347, 15714 /* ORI_MMR6 */ 15715 6350, 15716 /* OR_MM */ 15717 6353, 15718 /* OR_MMR6 */ 15719 6356, 15720 /* OR_V */ 15721 6359, 15722 /* ORi */ 15723 6362, 15724 /* ORi64 */ 15725 6365, 15726 /* ORi_MM */ 15727 6368, 15728 /* OrRxRxRy16 */ 15729 6371, 15730 /* PACKRL_PH */ 15731 6374, 15732 /* PACKRL_PH_MM */ 15733 6377, 15734 /* PAUSE */ 15735 6380, 15736 /* PAUSE_MM */ 15737 6380, 15738 /* PAUSE_MMR6 */ 15739 6380, 15740 /* PCKEV_B */ 15741 6380, 15742 /* PCKEV_D */ 15743 6383, 15744 /* PCKEV_H */ 15745 6386, 15746 /* PCKEV_W */ 15747 6389, 15748 /* PCKOD_B */ 15749 6392, 15750 /* PCKOD_D */ 15751 6395, 15752 /* PCKOD_H */ 15753 6398, 15754 /* PCKOD_W */ 15755 6401, 15756 /* PCNT_B */ 15757 6404, 15758 /* PCNT_D */ 15759 6406, 15760 /* PCNT_H */ 15761 6408, 15762 /* PCNT_W */ 15763 6410, 15764 /* PICK_PH */ 15765 6412, 15766 /* PICK_PH_MM */ 15767 6415, 15768 /* PICK_QB */ 15769 6418, 15770 /* PICK_QB_MM */ 15771 6421, 15772 /* PLL_PS64 */ 15773 6424, 15774 /* PLU_PS64 */ 15775 6427, 15776 /* POP */ 15777 6430, 15778 /* PRECEQU_PH_QBL */ 15779 6432, 15780 /* PRECEQU_PH_QBLA */ 15781 6434, 15782 /* PRECEQU_PH_QBLA_MM */ 15783 6436, 15784 /* PRECEQU_PH_QBL_MM */ 15785 6438, 15786 /* PRECEQU_PH_QBR */ 15787 6440, 15788 /* PRECEQU_PH_QBRA */ 15789 6442, 15790 /* PRECEQU_PH_QBRA_MM */ 15791 6444, 15792 /* PRECEQU_PH_QBR_MM */ 15793 6446, 15794 /* PRECEQ_W_PHL */ 15795 6448, 15796 /* PRECEQ_W_PHL_MM */ 15797 6450, 15798 /* PRECEQ_W_PHR */ 15799 6452, 15800 /* PRECEQ_W_PHR_MM */ 15801 6454, 15802 /* PRECEU_PH_QBL */ 15803 6456, 15804 /* PRECEU_PH_QBLA */ 15805 6458, 15806 /* PRECEU_PH_QBLA_MM */ 15807 6460, 15808 /* PRECEU_PH_QBL_MM */ 15809 6462, 15810 /* PRECEU_PH_QBR */ 15811 6464, 15812 /* PRECEU_PH_QBRA */ 15813 6466, 15814 /* PRECEU_PH_QBRA_MM */ 15815 6468, 15816 /* PRECEU_PH_QBR_MM */ 15817 6470, 15818 /* PRECRQU_S_QB_PH */ 15819 6472, 15820 /* PRECRQU_S_QB_PH_MM */ 15821 6475, 15822 /* PRECRQ_PH_W */ 15823 6478, 15824 /* PRECRQ_PH_W_MM */ 15825 6481, 15826 /* PRECRQ_QB_PH */ 15827 6484, 15828 /* PRECRQ_QB_PH_MM */ 15829 6487, 15830 /* PRECRQ_RS_PH_W */ 15831 6490, 15832 /* PRECRQ_RS_PH_W_MM */ 15833 6493, 15834 /* PRECR_QB_PH */ 15835 6496, 15836 /* PRECR_QB_PH_MMR2 */ 15837 6499, 15838 /* PRECR_SRA_PH_W */ 15839 6502, 15840 /* PRECR_SRA_PH_W_MMR2 */ 15841 6506, 15842 /* PRECR_SRA_R_PH_W */ 15843 6510, 15844 /* PRECR_SRA_R_PH_W_MMR2 */ 15845 6514, 15846 /* PREF */ 15847 6518, 15848 /* PREFE */ 15849 6521, 15850 /* PREFE_MM */ 15851 6524, 15852 /* PREFX_MM */ 15853 6527, 15854 /* PREF_MM */ 15855 6530, 15856 /* PREF_MMR6 */ 15857 6533, 15858 /* PREF_R6 */ 15859 6536, 15860 /* PREPEND */ 15861 6539, 15862 /* PREPEND_MMR2 */ 15863 6543, 15864 /* PUL_PS64 */ 15865 6547, 15866 /* PUU_PS64 */ 15867 6550, 15868 /* RADDU_W_QB */ 15869 6553, 15870 /* RADDU_W_QB_MM */ 15871 6555, 15872 /* RDDSP */ 15873 6557, 15874 /* RDDSP_MM */ 15875 6559, 15876 /* RDHWR */ 15877 6561, 15878 /* RDHWR64 */ 15879 6564, 15880 /* RDHWR_MM */ 15881 6567, 15882 /* RDHWR_MMR6 */ 15883 6570, 15884 /* RDPGPR_MMR6 */ 15885 6573, 15886 /* RECIP_D32 */ 15887 6575, 15888 /* RECIP_D32_MM */ 15889 6577, 15890 /* RECIP_D64 */ 15891 6579, 15892 /* RECIP_D64_MM */ 15893 6581, 15894 /* RECIP_S */ 15895 6583, 15896 /* RECIP_S_MM */ 15897 6585, 15898 /* REPLV_PH */ 15899 6587, 15900 /* REPLV_PH_MM */ 15901 6589, 15902 /* REPLV_QB */ 15903 6591, 15904 /* REPLV_QB_MM */ 15905 6593, 15906 /* REPL_PH */ 15907 6595, 15908 /* REPL_PH_MM */ 15909 6597, 15910 /* REPL_QB */ 15911 6599, 15912 /* REPL_QB_MM */ 15913 6601, 15914 /* RINT_D */ 15915 6603, 15916 /* RINT_D_MMR6 */ 15917 6605, 15918 /* RINT_S */ 15919 6607, 15920 /* RINT_S_MMR6 */ 15921 6609, 15922 /* ROTR */ 15923 6611, 15924 /* ROTRV */ 15925 6614, 15926 /* ROTRV_MM */ 15927 6617, 15928 /* ROTR_MM */ 15929 6620, 15930 /* ROUND_L_D64 */ 15931 6623, 15932 /* ROUND_L_D_MMR6 */ 15933 6625, 15934 /* ROUND_L_S */ 15935 6627, 15936 /* ROUND_L_S_MMR6 */ 15937 6629, 15938 /* ROUND_W_D32 */ 15939 6631, 15940 /* ROUND_W_D64 */ 15941 6633, 15942 /* ROUND_W_D_MMR6 */ 15943 6635, 15944 /* ROUND_W_MM */ 15945 6637, 15946 /* ROUND_W_S */ 15947 6639, 15948 /* ROUND_W_S_MM */ 15949 6641, 15950 /* ROUND_W_S_MMR6 */ 15951 6643, 15952 /* RSQRT_D32 */ 15953 6645, 15954 /* RSQRT_D32_MM */ 15955 6647, 15956 /* RSQRT_D64 */ 15957 6649, 15958 /* RSQRT_D64_MM */ 15959 6651, 15960 /* RSQRT_S */ 15961 6653, 15962 /* RSQRT_S_MM */ 15963 6655, 15964 /* Restore16 */ 15965 6657, 15966 /* RestoreX16 */ 15967 6657, 15968 /* SAA */ 15969 6657, 15970 /* SAAD */ 15971 6659, 15972 /* SAT_S_B */ 15973 6661, 15974 /* SAT_S_D */ 15975 6664, 15976 /* SAT_S_H */ 15977 6667, 15978 /* SAT_S_W */ 15979 6670, 15980 /* SAT_U_B */ 15981 6673, 15982 /* SAT_U_D */ 15983 6676, 15984 /* SAT_U_H */ 15985 6679, 15986 /* SAT_U_W */ 15987 6682, 15988 /* SB */ 15989 6685, 15990 /* SB16_MM */ 15991 6688, 15992 /* SB16_MMR6 */ 15993 6691, 15994 /* SB64 */ 15995 6694, 15996 /* SBE */ 15997 6697, 15998 /* SBE_MM */ 15999 6700, 16000 /* SB_MM */ 16001 6703, 16002 /* SB_MMR6 */ 16003 6706, 16004 /* SC */ 16005 6709, 16006 /* SC64 */ 16007 6713, 16008 /* SC64_R6 */ 16009 6717, 16010 /* SCD */ 16011 6721, 16012 /* SCD_R6 */ 16013 6725, 16014 /* SCE */ 16015 6729, 16016 /* SCE_MM */ 16017 6733, 16018 /* SC_MM */ 16019 6737, 16020 /* SC_MMR6 */ 16021 6741, 16022 /* SC_R6 */ 16023 6745, 16024 /* SD */ 16025 6749, 16026 /* SDBBP */ 16027 6752, 16028 /* SDBBP16_MM */ 16029 6753, 16030 /* SDBBP16_MMR6 */ 16031 6754, 16032 /* SDBBP_MM */ 16033 6755, 16034 /* SDBBP_MMR6 */ 16035 6756, 16036 /* SDBBP_R6 */ 16037 6757, 16038 /* SDC1 */ 16039 6758, 16040 /* SDC164 */ 16041 6761, 16042 /* SDC1_D64_MMR6 */ 16043 6764, 16044 /* SDC1_MM_D32 */ 16045 6767, 16046 /* SDC1_MM_D64 */ 16047 6770, 16048 /* SDC2 */ 16049 6773, 16050 /* SDC2_MMR6 */ 16051 6776, 16052 /* SDC2_R6 */ 16053 6779, 16054 /* SDC3 */ 16055 6782, 16056 /* SDIV */ 16057 6785, 16058 /* SDIV_MM */ 16059 6787, 16060 /* SDL */ 16061 6789, 16062 /* SDR */ 16063 6792, 16064 /* SDXC1 */ 16065 6795, 16066 /* SDXC164 */ 16067 6798, 16068 /* SEB */ 16069 6801, 16070 /* SEB64 */ 16071 6803, 16072 /* SEB_MM */ 16073 6805, 16074 /* SEH */ 16075 6807, 16076 /* SEH64 */ 16077 6809, 16078 /* SEH_MM */ 16079 6811, 16080 /* SELEQZ */ 16081 6813, 16082 /* SELEQZ64 */ 16083 6816, 16084 /* SELEQZ_D */ 16085 6819, 16086 /* SELEQZ_D_MMR6 */ 16087 6822, 16088 /* SELEQZ_MMR6 */ 16089 6825, 16090 /* SELEQZ_S */ 16091 6828, 16092 /* SELEQZ_S_MMR6 */ 16093 6831, 16094 /* SELNEZ */ 16095 6834, 16096 /* SELNEZ64 */ 16097 6837, 16098 /* SELNEZ_D */ 16099 6840, 16100 /* SELNEZ_D_MMR6 */ 16101 6843, 16102 /* SELNEZ_MMR6 */ 16103 6846, 16104 /* SELNEZ_S */ 16105 6849, 16106 /* SELNEZ_S_MMR6 */ 16107 6852, 16108 /* SEL_D */ 16109 6855, 16110 /* SEL_D_MMR6 */ 16111 6859, 16112 /* SEL_S */ 16113 6863, 16114 /* SEL_S_MMR6 */ 16115 6867, 16116 /* SEQ */ 16117 6871, 16118 /* SEQi */ 16119 6874, 16120 /* SH */ 16121 6877, 16122 /* SH16_MM */ 16123 6880, 16124 /* SH16_MMR6 */ 16125 6883, 16126 /* SH64 */ 16127 6886, 16128 /* SHE */ 16129 6889, 16130 /* SHE_MM */ 16131 6892, 16132 /* SHF_B */ 16133 6895, 16134 /* SHF_H */ 16135 6898, 16136 /* SHF_W */ 16137 6901, 16138 /* SHILO */ 16139 6904, 16140 /* SHILOV */ 16141 6907, 16142 /* SHILOV_MM */ 16143 6910, 16144 /* SHILO_MM */ 16145 6913, 16146 /* SHLLV_PH */ 16147 6916, 16148 /* SHLLV_PH_MM */ 16149 6919, 16150 /* SHLLV_QB */ 16151 6922, 16152 /* SHLLV_QB_MM */ 16153 6925, 16154 /* SHLLV_S_PH */ 16155 6928, 16156 /* SHLLV_S_PH_MM */ 16157 6931, 16158 /* SHLLV_S_W */ 16159 6934, 16160 /* SHLLV_S_W_MM */ 16161 6937, 16162 /* SHLL_PH */ 16163 6940, 16164 /* SHLL_PH_MM */ 16165 6943, 16166 /* SHLL_QB */ 16167 6946, 16168 /* SHLL_QB_MM */ 16169 6949, 16170 /* SHLL_S_PH */ 16171 6952, 16172 /* SHLL_S_PH_MM */ 16173 6955, 16174 /* SHLL_S_W */ 16175 6958, 16176 /* SHLL_S_W_MM */ 16177 6961, 16178 /* SHRAV_PH */ 16179 6964, 16180 /* SHRAV_PH_MM */ 16181 6967, 16182 /* SHRAV_QB */ 16183 6970, 16184 /* SHRAV_QB_MMR2 */ 16185 6973, 16186 /* SHRAV_R_PH */ 16187 6976, 16188 /* SHRAV_R_PH_MM */ 16189 6979, 16190 /* SHRAV_R_QB */ 16191 6982, 16192 /* SHRAV_R_QB_MMR2 */ 16193 6985, 16194 /* SHRAV_R_W */ 16195 6988, 16196 /* SHRAV_R_W_MM */ 16197 6991, 16198 /* SHRA_PH */ 16199 6994, 16200 /* SHRA_PH_MM */ 16201 6997, 16202 /* SHRA_QB */ 16203 7000, 16204 /* SHRA_QB_MMR2 */ 16205 7003, 16206 /* SHRA_R_PH */ 16207 7006, 16208 /* SHRA_R_PH_MM */ 16209 7009, 16210 /* SHRA_R_QB */ 16211 7012, 16212 /* SHRA_R_QB_MMR2 */ 16213 7015, 16214 /* SHRA_R_W */ 16215 7018, 16216 /* SHRA_R_W_MM */ 16217 7021, 16218 /* SHRLV_PH */ 16219 7024, 16220 /* SHRLV_PH_MMR2 */ 16221 7027, 16222 /* SHRLV_QB */ 16223 7030, 16224 /* SHRLV_QB_MM */ 16225 7033, 16226 /* SHRL_PH */ 16227 7036, 16228 /* SHRL_PH_MMR2 */ 16229 7039, 16230 /* SHRL_QB */ 16231 7042, 16232 /* SHRL_QB_MM */ 16233 7045, 16234 /* SH_MM */ 16235 7048, 16236 /* SH_MMR6 */ 16237 7051, 16238 /* SIGRIE */ 16239 7054, 16240 /* SIGRIE_MMR6 */ 16241 7055, 16242 /* SLDI_B */ 16243 7056, 16244 /* SLDI_D */ 16245 7060, 16246 /* SLDI_H */ 16247 7064, 16248 /* SLDI_W */ 16249 7068, 16250 /* SLD_B */ 16251 7072, 16252 /* SLD_D */ 16253 7076, 16254 /* SLD_H */ 16255 7080, 16256 /* SLD_W */ 16257 7084, 16258 /* SLL */ 16259 7088, 16260 /* SLL16_MM */ 16261 7091, 16262 /* SLL16_MMR6 */ 16263 7094, 16264 /* SLL64_32 */ 16265 7097, 16266 /* SLL64_64 */ 16267 7099, 16268 /* SLLI_B */ 16269 7101, 16270 /* SLLI_D */ 16271 7104, 16272 /* SLLI_H */ 16273 7107, 16274 /* SLLI_W */ 16275 7110, 16276 /* SLLV */ 16277 7113, 16278 /* SLLV_MM */ 16279 7116, 16280 /* SLL_B */ 16281 7119, 16282 /* SLL_D */ 16283 7122, 16284 /* SLL_H */ 16285 7125, 16286 /* SLL_MM */ 16287 7128, 16288 /* SLL_MMR6 */ 16289 7131, 16290 /* SLL_W */ 16291 7134, 16292 /* SLT */ 16293 7137, 16294 /* SLT64 */ 16295 7140, 16296 /* SLT_MM */ 16297 7143, 16298 /* SLTi */ 16299 7146, 16300 /* SLTi64 */ 16301 7149, 16302 /* SLTi_MM */ 16303 7152, 16304 /* SLTiu */ 16305 7155, 16306 /* SLTiu64 */ 16307 7158, 16308 /* SLTiu_MM */ 16309 7161, 16310 /* SLTu */ 16311 7164, 16312 /* SLTu64 */ 16313 7167, 16314 /* SLTu_MM */ 16315 7170, 16316 /* SNE */ 16317 7173, 16318 /* SNEi */ 16319 7176, 16320 /* SPLATI_B */ 16321 7179, 16322 /* SPLATI_D */ 16323 7182, 16324 /* SPLATI_H */ 16325 7185, 16326 /* SPLATI_W */ 16327 7188, 16328 /* SPLAT_B */ 16329 7191, 16330 /* SPLAT_D */ 16331 7194, 16332 /* SPLAT_H */ 16333 7197, 16334 /* SPLAT_W */ 16335 7200, 16336 /* SRA */ 16337 7203, 16338 /* SRAI_B */ 16339 7206, 16340 /* SRAI_D */ 16341 7209, 16342 /* SRAI_H */ 16343 7212, 16344 /* SRAI_W */ 16345 7215, 16346 /* SRARI_B */ 16347 7218, 16348 /* SRARI_D */ 16349 7221, 16350 /* SRARI_H */ 16351 7224, 16352 /* SRARI_W */ 16353 7227, 16354 /* SRAR_B */ 16355 7230, 16356 /* SRAR_D */ 16357 7233, 16358 /* SRAR_H */ 16359 7236, 16360 /* SRAR_W */ 16361 7239, 16362 /* SRAV */ 16363 7242, 16364 /* SRAV_MM */ 16365 7245, 16366 /* SRA_B */ 16367 7248, 16368 /* SRA_D */ 16369 7251, 16370 /* SRA_H */ 16371 7254, 16372 /* SRA_MM */ 16373 7257, 16374 /* SRA_W */ 16375 7260, 16376 /* SRL */ 16377 7263, 16378 /* SRL16_MM */ 16379 7266, 16380 /* SRL16_MMR6 */ 16381 7269, 16382 /* SRLI_B */ 16383 7272, 16384 /* SRLI_D */ 16385 7275, 16386 /* SRLI_H */ 16387 7278, 16388 /* SRLI_W */ 16389 7281, 16390 /* SRLRI_B */ 16391 7284, 16392 /* SRLRI_D */ 16393 7287, 16394 /* SRLRI_H */ 16395 7290, 16396 /* SRLRI_W */ 16397 7293, 16398 /* SRLR_B */ 16399 7296, 16400 /* SRLR_D */ 16401 7299, 16402 /* SRLR_H */ 16403 7302, 16404 /* SRLR_W */ 16405 7305, 16406 /* SRLV */ 16407 7308, 16408 /* SRLV_MM */ 16409 7311, 16410 /* SRL_B */ 16411 7314, 16412 /* SRL_D */ 16413 7317, 16414 /* SRL_H */ 16415 7320, 16416 /* SRL_MM */ 16417 7323, 16418 /* SRL_W */ 16419 7326, 16420 /* SSNOP */ 16421 7329, 16422 /* SSNOP_MM */ 16423 7329, 16424 /* SSNOP_MMR6 */ 16425 7329, 16426 /* ST_B */ 16427 7329, 16428 /* ST_D */ 16429 7332, 16430 /* ST_H */ 16431 7335, 16432 /* ST_W */ 16433 7338, 16434 /* SUB */ 16435 7341, 16436 /* SUBQH_PH */ 16437 7344, 16438 /* SUBQH_PH_MMR2 */ 16439 7347, 16440 /* SUBQH_R_PH */ 16441 7350, 16442 /* SUBQH_R_PH_MMR2 */ 16443 7353, 16444 /* SUBQH_R_W */ 16445 7356, 16446 /* SUBQH_R_W_MMR2 */ 16447 7359, 16448 /* SUBQH_W */ 16449 7362, 16450 /* SUBQH_W_MMR2 */ 16451 7365, 16452 /* SUBQ_PH */ 16453 7368, 16454 /* SUBQ_PH_MM */ 16455 7371, 16456 /* SUBQ_S_PH */ 16457 7374, 16458 /* SUBQ_S_PH_MM */ 16459 7377, 16460 /* SUBQ_S_W */ 16461 7380, 16462 /* SUBQ_S_W_MM */ 16463 7383, 16464 /* SUBSUS_U_B */ 16465 7386, 16466 /* SUBSUS_U_D */ 16467 7389, 16468 /* SUBSUS_U_H */ 16469 7392, 16470 /* SUBSUS_U_W */ 16471 7395, 16472 /* SUBSUU_S_B */ 16473 7398, 16474 /* SUBSUU_S_D */ 16475 7401, 16476 /* SUBSUU_S_H */ 16477 7404, 16478 /* SUBSUU_S_W */ 16479 7407, 16480 /* SUBS_S_B */ 16481 7410, 16482 /* SUBS_S_D */ 16483 7413, 16484 /* SUBS_S_H */ 16485 7416, 16486 /* SUBS_S_W */ 16487 7419, 16488 /* SUBS_U_B */ 16489 7422, 16490 /* SUBS_U_D */ 16491 7425, 16492 /* SUBS_U_H */ 16493 7428, 16494 /* SUBS_U_W */ 16495 7431, 16496 /* SUBU16_MM */ 16497 7434, 16498 /* SUBU16_MMR6 */ 16499 7437, 16500 /* SUBUH_QB */ 16501 7440, 16502 /* SUBUH_QB_MMR2 */ 16503 7443, 16504 /* SUBUH_R_QB */ 16505 7446, 16506 /* SUBUH_R_QB_MMR2 */ 16507 7449, 16508 /* SUBU_MMR6 */ 16509 7452, 16510 /* SUBU_PH */ 16511 7455, 16512 /* SUBU_PH_MMR2 */ 16513 7458, 16514 /* SUBU_QB */ 16515 7461, 16516 /* SUBU_QB_MM */ 16517 7464, 16518 /* SUBU_S_PH */ 16519 7467, 16520 /* SUBU_S_PH_MMR2 */ 16521 7470, 16522 /* SUBU_S_QB */ 16523 7473, 16524 /* SUBU_S_QB_MM */ 16525 7476, 16526 /* SUBVI_B */ 16527 7479, 16528 /* SUBVI_D */ 16529 7482, 16530 /* SUBVI_H */ 16531 7485, 16532 /* SUBVI_W */ 16533 7488, 16534 /* SUBV_B */ 16535 7491, 16536 /* SUBV_D */ 16537 7494, 16538 /* SUBV_H */ 16539 7497, 16540 /* SUBV_W */ 16541 7500, 16542 /* SUB_MM */ 16543 7503, 16544 /* SUB_MMR6 */ 16545 7506, 16546 /* SUBu */ 16547 7509, 16548 /* SUBu_MM */ 16549 7512, 16550 /* SUXC1 */ 16551 7515, 16552 /* SUXC164 */ 16553 7518, 16554 /* SUXC1_MM */ 16555 7521, 16556 /* SW */ 16557 7524, 16558 /* SW16_MM */ 16559 7527, 16560 /* SW16_MMR6 */ 16561 7530, 16562 /* SW64 */ 16563 7533, 16564 /* SWC1 */ 16565 7536, 16566 /* SWC1_MM */ 16567 7539, 16568 /* SWC2 */ 16569 7542, 16570 /* SWC2_MMR6 */ 16571 7545, 16572 /* SWC2_R6 */ 16573 7548, 16574 /* SWC3 */ 16575 7551, 16576 /* SWDSP */ 16577 7554, 16578 /* SWDSP_MM */ 16579 7557, 16580 /* SWE */ 16581 7560, 16582 /* SWE_MM */ 16583 7563, 16584 /* SWL */ 16585 7566, 16586 /* SWL64 */ 16587 7569, 16588 /* SWLE */ 16589 7572, 16590 /* SWLE_MM */ 16591 7575, 16592 /* SWL_MM */ 16593 7578, 16594 /* SWM16_MM */ 16595 7581, 16596 /* SWM16_MMR6 */ 16597 7584, 16598 /* SWM32_MM */ 16599 7587, 16600 /* SWP_MM */ 16601 7590, 16602 /* SWR */ 16603 7594, 16604 /* SWR64 */ 16605 7597, 16606 /* SWRE */ 16607 7600, 16608 /* SWRE_MM */ 16609 7603, 16610 /* SWR_MM */ 16611 7606, 16612 /* SWSP_MM */ 16613 7609, 16614 /* SWSP_MMR6 */ 16615 7612, 16616 /* SWXC1 */ 16617 7615, 16618 /* SWXC1_MM */ 16619 7618, 16620 /* SW_MM */ 16621 7621, 16622 /* SW_MMR6 */ 16623 7624, 16624 /* SYNC */ 16625 7627, 16626 /* SYNCI */ 16627 7628, 16628 /* SYNCI_MM */ 16629 7630, 16630 /* SYNCI_MMR6 */ 16631 7632, 16632 /* SYNC_MM */ 16633 7634, 16634 /* SYNC_MMR6 */ 16635 7635, 16636 /* SYSCALL */ 16637 7636, 16638 /* SYSCALL_MM */ 16639 7637, 16640 /* Save16 */ 16641 7638, 16642 /* SaveX16 */ 16643 7638, 16644 /* SbRxRyOffMemX16 */ 16645 7638, 16646 /* SebRx16 */ 16647 7641, 16648 /* SehRx16 */ 16649 7643, 16650 /* ShRxRyOffMemX16 */ 16651 7645, 16652 /* SllX16 */ 16653 7648, 16654 /* SllvRxRy16 */ 16655 7651, 16656 /* SltRxRy16 */ 16657 7654, 16658 /* SltiRxImm16 */ 16659 7656, 16660 /* SltiRxImmX16 */ 16661 7658, 16662 /* SltiuRxImm16 */ 16663 7660, 16664 /* SltiuRxImmX16 */ 16665 7662, 16666 /* SltuRxRy16 */ 16667 7664, 16668 /* SraX16 */ 16669 7666, 16670 /* SravRxRy16 */ 16671 7669, 16672 /* SrlX16 */ 16673 7672, 16674 /* SrlvRxRy16 */ 16675 7675, 16676 /* SubuRxRyRz16 */ 16677 7678, 16678 /* SwRxRyOffMemX16 */ 16679 7681, 16680 /* SwRxSpImmX16 */ 16681 7684, 16682 /* TEQ */ 16683 7687, 16684 /* TEQI */ 16685 7690, 16686 /* TEQI_MM */ 16687 7692, 16688 /* TEQ_MM */ 16689 7694, 16690 /* TGE */ 16691 7697, 16692 /* TGEI */ 16693 7700, 16694 /* TGEIU */ 16695 7702, 16696 /* TGEIU_MM */ 16697 7704, 16698 /* TGEI_MM */ 16699 7706, 16700 /* TGEU */ 16701 7708, 16702 /* TGEU_MM */ 16703 7711, 16704 /* TGE_MM */ 16705 7714, 16706 /* TLBGINV */ 16707 7717, 16708 /* TLBGINVF */ 16709 7717, 16710 /* TLBGINVF_MM */ 16711 7717, 16712 /* TLBGINV_MM */ 16713 7717, 16714 /* TLBGP */ 16715 7717, 16716 /* TLBGP_MM */ 16717 7717, 16718 /* TLBGR */ 16719 7717, 16720 /* TLBGR_MM */ 16721 7717, 16722 /* TLBGWI */ 16723 7717, 16724 /* TLBGWI_MM */ 16725 7717, 16726 /* TLBGWR */ 16727 7717, 16728 /* TLBGWR_MM */ 16729 7717, 16730 /* TLBINV */ 16731 7717, 16732 /* TLBINVF */ 16733 7717, 16734 /* TLBINVF_MMR6 */ 16735 7717, 16736 /* TLBINV_MMR6 */ 16737 7717, 16738 /* TLBP */ 16739 7717, 16740 /* TLBP_MM */ 16741 7717, 16742 /* TLBR */ 16743 7717, 16744 /* TLBR_MM */ 16745 7717, 16746 /* TLBWI */ 16747 7717, 16748 /* TLBWI_MM */ 16749 7717, 16750 /* TLBWR */ 16751 7717, 16752 /* TLBWR_MM */ 16753 7717, 16754 /* TLT */ 16755 7717, 16756 /* TLTI */ 16757 7720, 16758 /* TLTIU_MM */ 16759 7722, 16760 /* TLTI_MM */ 16761 7724, 16762 /* TLTU */ 16763 7726, 16764 /* TLTU_MM */ 16765 7729, 16766 /* TLT_MM */ 16767 7732, 16768 /* TNE */ 16769 7735, 16770 /* TNEI */ 16771 7738, 16772 /* TNEI_MM */ 16773 7740, 16774 /* TNE_MM */ 16775 7742, 16776 /* TRUNC_L_D64 */ 16777 7745, 16778 /* TRUNC_L_D_MMR6 */ 16779 7747, 16780 /* TRUNC_L_S */ 16781 7749, 16782 /* TRUNC_L_S_MMR6 */ 16783 7751, 16784 /* TRUNC_W_D32 */ 16785 7753, 16786 /* TRUNC_W_D64 */ 16787 7755, 16788 /* TRUNC_W_D_MMR6 */ 16789 7757, 16790 /* TRUNC_W_MM */ 16791 7759, 16792 /* TRUNC_W_S */ 16793 7761, 16794 /* TRUNC_W_S_MM */ 16795 7763, 16796 /* TRUNC_W_S_MMR6 */ 16797 7765, 16798 /* TTLTIU */ 16799 7767, 16800 /* UDIV */ 16801 7769, 16802 /* UDIV_MM */ 16803 7771, 16804 /* V3MULU */ 16805 7773, 16806 /* VMM0 */ 16807 7776, 16808 /* VMULU */ 16809 7779, 16810 /* VSHF_B */ 16811 7782, 16812 /* VSHF_D */ 16813 7786, 16814 /* VSHF_H */ 16815 7790, 16816 /* VSHF_W */ 16817 7794, 16818 /* WAIT */ 16819 7798, 16820 /* WAIT_MM */ 16821 7798, 16822 /* WAIT_MMR6 */ 16823 7799, 16824 /* WRDSP */ 16825 7800, 16826 /* WRDSP_MM */ 16827 7802, 16828 /* WRPGPR_MMR6 */ 16829 7804, 16830 /* WSBH */ 16831 7806, 16832 /* WSBH_MM */ 16833 7808, 16834 /* WSBH_MMR6 */ 16835 7810, 16836 /* XOR */ 16837 7812, 16838 /* XOR16_MM */ 16839 7815, 16840 /* XOR16_MMR6 */ 16841 7818, 16842 /* XOR64 */ 16843 7821, 16844 /* XORI_B */ 16845 7824, 16846 /* XORI_MMR6 */ 16847 7827, 16848 /* XOR_MM */ 16849 7830, 16850 /* XOR_MMR6 */ 16851 7833, 16852 /* XOR_V */ 16853 7836, 16854 /* XORi */ 16855 7839, 16856 /* XORi64 */ 16857 7842, 16858 /* XORi_MM */ 16859 7845, 16860 /* XorRxRxRy16 */ 16861 7848, 16862 /* YIELD */ 16863 7851, 16864 }; 16865 16866 using namespace OpTypes; 16867 const int16_t OpcodeOperandTypes[] = { 16868 16869 /* PHI */ 16870 -1, 16871 /* INLINEASM */ 16872 /* INLINEASM_BR */ 16873 /* CFI_INSTRUCTION */ 16874 i32imm, 16875 /* EH_LABEL */ 16876 i32imm, 16877 /* GC_LABEL */ 16878 i32imm, 16879 /* ANNOTATION_LABEL */ 16880 i32imm, 16881 /* KILL */ 16882 /* EXTRACT_SUBREG */ 16883 -1, -1, i32imm, 16884 /* INSERT_SUBREG */ 16885 -1, -1, -1, i32imm, 16886 /* IMPLICIT_DEF */ 16887 -1, 16888 /* SUBREG_TO_REG */ 16889 -1, -1, -1, i32imm, 16890 /* COPY_TO_REGCLASS */ 16891 -1, -1, i32imm, 16892 /* DBG_VALUE */ 16893 /* DBG_VALUE_LIST */ 16894 /* DBG_INSTR_REF */ 16895 /* DBG_PHI */ 16896 /* DBG_LABEL */ 16897 -1, 16898 /* REG_SEQUENCE */ 16899 -1, -1, 16900 /* COPY */ 16901 -1, -1, 16902 /* BUNDLE */ 16903 /* LIFETIME_START */ 16904 i32imm, 16905 /* LIFETIME_END */ 16906 i32imm, 16907 /* PSEUDO_PROBE */ 16908 i64imm, i64imm, i8imm, i32imm, 16909 /* ARITH_FENCE */ 16910 -1, -1, 16911 /* STACKMAP */ 16912 i64imm, i32imm, 16913 /* FENTRY_CALL */ 16914 /* PATCHPOINT */ 16915 -1, i64imm, i32imm, -1, i32imm, i32imm, 16916 /* LOAD_STACK_GUARD */ 16917 -1, 16918 /* PREALLOCATED_SETUP */ 16919 i32imm, 16920 /* PREALLOCATED_ARG */ 16921 -1, i32imm, i32imm, 16922 /* STATEPOINT */ 16923 /* LOCAL_ESCAPE */ 16924 -1, i32imm, 16925 /* FAULTING_OP */ 16926 -1, 16927 /* PATCHABLE_OP */ 16928 /* PATCHABLE_FUNCTION_ENTER */ 16929 /* PATCHABLE_RET */ 16930 /* PATCHABLE_FUNCTION_EXIT */ 16931 /* PATCHABLE_TAIL_CALL */ 16932 /* PATCHABLE_EVENT_CALL */ 16933 -1, -1, 16934 /* PATCHABLE_TYPED_EVENT_CALL */ 16935 -1, -1, -1, 16936 /* ICALL_BRANCH_FUNNEL */ 16937 /* MEMBARRIER */ 16938 /* G_ASSERT_SEXT */ 16939 type0, type0, untyped_imm_0, 16940 /* G_ASSERT_ZEXT */ 16941 type0, type0, untyped_imm_0, 16942 /* G_ASSERT_ALIGN */ 16943 type0, type0, untyped_imm_0, 16944 /* G_ADD */ 16945 type0, type0, type0, 16946 /* G_SUB */ 16947 type0, type0, type0, 16948 /* G_MUL */ 16949 type0, type0, type0, 16950 /* G_SDIV */ 16951 type0, type0, type0, 16952 /* G_UDIV */ 16953 type0, type0, type0, 16954 /* G_SREM */ 16955 type0, type0, type0, 16956 /* G_UREM */ 16957 type0, type0, type0, 16958 /* G_SDIVREM */ 16959 type0, type0, type0, type0, 16960 /* G_UDIVREM */ 16961 type0, type0, type0, type0, 16962 /* G_AND */ 16963 type0, type0, type0, 16964 /* G_OR */ 16965 type0, type0, type0, 16966 /* G_XOR */ 16967 type0, type0, type0, 16968 /* G_IMPLICIT_DEF */ 16969 type0, 16970 /* G_PHI */ 16971 type0, 16972 /* G_FRAME_INDEX */ 16973 type0, -1, 16974 /* G_GLOBAL_VALUE */ 16975 type0, -1, 16976 /* G_EXTRACT */ 16977 type0, type1, untyped_imm_0, 16978 /* G_UNMERGE_VALUES */ 16979 type0, type1, 16980 /* G_INSERT */ 16981 type0, type0, type1, untyped_imm_0, 16982 /* G_MERGE_VALUES */ 16983 type0, type1, 16984 /* G_BUILD_VECTOR */ 16985 type0, type1, 16986 /* G_BUILD_VECTOR_TRUNC */ 16987 type0, type1, 16988 /* G_CONCAT_VECTORS */ 16989 type0, type1, 16990 /* G_PTRTOINT */ 16991 type0, type1, 16992 /* G_INTTOPTR */ 16993 type0, type1, 16994 /* G_BITCAST */ 16995 type0, type1, 16996 /* G_FREEZE */ 16997 type0, type0, 16998 /* G_INTRINSIC_FPTRUNC_ROUND */ 16999 type0, type1, i32imm, 17000 /* G_INTRINSIC_TRUNC */ 17001 type0, type0, 17002 /* G_INTRINSIC_ROUND */ 17003 type0, type0, 17004 /* G_INTRINSIC_LRINT */ 17005 type0, type1, 17006 /* G_INTRINSIC_ROUNDEVEN */ 17007 type0, type0, 17008 /* G_READCYCLECOUNTER */ 17009 type0, 17010 /* G_LOAD */ 17011 type0, ptype1, 17012 /* G_SEXTLOAD */ 17013 type0, ptype1, 17014 /* G_ZEXTLOAD */ 17015 type0, ptype1, 17016 /* G_INDEXED_LOAD */ 17017 type0, ptype1, ptype1, type2, -1, 17018 /* G_INDEXED_SEXTLOAD */ 17019 type0, ptype1, ptype1, type2, -1, 17020 /* G_INDEXED_ZEXTLOAD */ 17021 type0, ptype1, ptype1, type2, -1, 17022 /* G_STORE */ 17023 type0, ptype1, 17024 /* G_INDEXED_STORE */ 17025 ptype0, type1, ptype0, ptype2, -1, 17026 /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */ 17027 type0, type1, type2, type0, type0, 17028 /* G_ATOMIC_CMPXCHG */ 17029 type0, ptype1, type0, type0, 17030 /* G_ATOMICRMW_XCHG */ 17031 type0, ptype1, type0, 17032 /* G_ATOMICRMW_ADD */ 17033 type0, ptype1, type0, 17034 /* G_ATOMICRMW_SUB */ 17035 type0, ptype1, type0, 17036 /* G_ATOMICRMW_AND */ 17037 type0, ptype1, type0, 17038 /* G_ATOMICRMW_NAND */ 17039 type0, ptype1, type0, 17040 /* G_ATOMICRMW_OR */ 17041 type0, ptype1, type0, 17042 /* G_ATOMICRMW_XOR */ 17043 type0, ptype1, type0, 17044 /* G_ATOMICRMW_MAX */ 17045 type0, ptype1, type0, 17046 /* G_ATOMICRMW_MIN */ 17047 type0, ptype1, type0, 17048 /* G_ATOMICRMW_UMAX */ 17049 type0, ptype1, type0, 17050 /* G_ATOMICRMW_UMIN */ 17051 type0, ptype1, type0, 17052 /* G_ATOMICRMW_FADD */ 17053 type0, ptype1, type0, 17054 /* G_ATOMICRMW_FSUB */ 17055 type0, ptype1, type0, 17056 /* G_ATOMICRMW_FMAX */ 17057 type0, ptype1, type0, 17058 /* G_ATOMICRMW_FMIN */ 17059 type0, ptype1, type0, 17060 /* G_ATOMICRMW_UINC_WRAP */ 17061 type0, ptype1, type0, 17062 /* G_ATOMICRMW_UDEC_WRAP */ 17063 type0, ptype1, type0, 17064 /* G_FENCE */ 17065 i32imm, i32imm, 17066 /* G_BRCOND */ 17067 type0, -1, 17068 /* G_BRINDIRECT */ 17069 type0, 17070 /* G_INVOKE_REGION_START */ 17071 /* G_INTRINSIC */ 17072 -1, 17073 /* G_INTRINSIC_W_SIDE_EFFECTS */ 17074 -1, 17075 /* G_ANYEXT */ 17076 type0, type1, 17077 /* G_TRUNC */ 17078 type0, type1, 17079 /* G_CONSTANT */ 17080 type0, -1, 17081 /* G_FCONSTANT */ 17082 type0, -1, 17083 /* G_VASTART */ 17084 type0, 17085 /* G_VAARG */ 17086 type0, type1, -1, 17087 /* G_SEXT */ 17088 type0, type1, 17089 /* G_SEXT_INREG */ 17090 type0, type0, untyped_imm_0, 17091 /* G_ZEXT */ 17092 type0, type1, 17093 /* G_SHL */ 17094 type0, type0, type1, 17095 /* G_LSHR */ 17096 type0, type0, type1, 17097 /* G_ASHR */ 17098 type0, type0, type1, 17099 /* G_FSHL */ 17100 type0, type0, type0, type1, 17101 /* G_FSHR */ 17102 type0, type0, type0, type1, 17103 /* G_ROTR */ 17104 type0, type0, type1, 17105 /* G_ROTL */ 17106 type0, type0, type1, 17107 /* G_ICMP */ 17108 type0, -1, type1, type1, 17109 /* G_FCMP */ 17110 type0, -1, type1, type1, 17111 /* G_SELECT */ 17112 type0, type1, type0, type0, 17113 /* G_UADDO */ 17114 type0, type1, type0, type0, 17115 /* G_UADDE */ 17116 type0, type1, type0, type0, type1, 17117 /* G_USUBO */ 17118 type0, type1, type0, type0, 17119 /* G_USUBE */ 17120 type0, type1, type0, type0, type1, 17121 /* G_SADDO */ 17122 type0, type1, type0, type0, 17123 /* G_SADDE */ 17124 type0, type1, type0, type0, type1, 17125 /* G_SSUBO */ 17126 type0, type1, type0, type0, 17127 /* G_SSUBE */ 17128 type0, type1, type0, type0, type1, 17129 /* G_UMULO */ 17130 type0, type1, type0, type0, 17131 /* G_SMULO */ 17132 type0, type1, type0, type0, 17133 /* G_UMULH */ 17134 type0, type0, type0, 17135 /* G_SMULH */ 17136 type0, type0, type0, 17137 /* G_UADDSAT */ 17138 type0, type0, type0, 17139 /* G_SADDSAT */ 17140 type0, type0, type0, 17141 /* G_USUBSAT */ 17142 type0, type0, type0, 17143 /* G_SSUBSAT */ 17144 type0, type0, type0, 17145 /* G_USHLSAT */ 17146 type0, type0, type1, 17147 /* G_SSHLSAT */ 17148 type0, type0, type1, 17149 /* G_SMULFIX */ 17150 type0, type0, type0, untyped_imm_0, 17151 /* G_UMULFIX */ 17152 type0, type0, type0, untyped_imm_0, 17153 /* G_SMULFIXSAT */ 17154 type0, type0, type0, untyped_imm_0, 17155 /* G_UMULFIXSAT */ 17156 type0, type0, type0, untyped_imm_0, 17157 /* G_SDIVFIX */ 17158 type0, type0, type0, untyped_imm_0, 17159 /* G_UDIVFIX */ 17160 type0, type0, type0, untyped_imm_0, 17161 /* G_SDIVFIXSAT */ 17162 type0, type0, type0, untyped_imm_0, 17163 /* G_UDIVFIXSAT */ 17164 type0, type0, type0, untyped_imm_0, 17165 /* G_FADD */ 17166 type0, type0, type0, 17167 /* G_FSUB */ 17168 type0, type0, type0, 17169 /* G_FMUL */ 17170 type0, type0, type0, 17171 /* G_FMA */ 17172 type0, type0, type0, type0, 17173 /* G_FMAD */ 17174 type0, type0, type0, type0, 17175 /* G_FDIV */ 17176 type0, type0, type0, 17177 /* G_FREM */ 17178 type0, type0, type0, 17179 /* G_FPOW */ 17180 type0, type0, type0, 17181 /* G_FPOWI */ 17182 type0, type0, type1, 17183 /* G_FEXP */ 17184 type0, type0, 17185 /* G_FEXP2 */ 17186 type0, type0, 17187 /* G_FLOG */ 17188 type0, type0, 17189 /* G_FLOG2 */ 17190 type0, type0, 17191 /* G_FLOG10 */ 17192 type0, type0, 17193 /* G_FNEG */ 17194 type0, type0, 17195 /* G_FPEXT */ 17196 type0, type1, 17197 /* G_FPTRUNC */ 17198 type0, type1, 17199 /* G_FPTOSI */ 17200 type0, type1, 17201 /* G_FPTOUI */ 17202 type0, type1, 17203 /* G_SITOFP */ 17204 type0, type1, 17205 /* G_UITOFP */ 17206 type0, type1, 17207 /* G_FABS */ 17208 type0, type0, 17209 /* G_FCOPYSIGN */ 17210 type0, type0, type1, 17211 /* G_IS_FPCLASS */ 17212 type0, type1, -1, 17213 /* G_FCANONICALIZE */ 17214 type0, type0, 17215 /* G_FMINNUM */ 17216 type0, type0, type0, 17217 /* G_FMAXNUM */ 17218 type0, type0, type0, 17219 /* G_FMINNUM_IEEE */ 17220 type0, type0, type0, 17221 /* G_FMAXNUM_IEEE */ 17222 type0, type0, type0, 17223 /* G_FMINIMUM */ 17224 type0, type0, type0, 17225 /* G_FMAXIMUM */ 17226 type0, type0, type0, 17227 /* G_PTR_ADD */ 17228 ptype0, ptype0, type1, 17229 /* G_PTRMASK */ 17230 ptype0, ptype0, type1, 17231 /* G_SMIN */ 17232 type0, type0, type0, 17233 /* G_SMAX */ 17234 type0, type0, type0, 17235 /* G_UMIN */ 17236 type0, type0, type0, 17237 /* G_UMAX */ 17238 type0, type0, type0, 17239 /* G_ABS */ 17240 type0, type0, 17241 /* G_LROUND */ 17242 type0, type1, 17243 /* G_LLROUND */ 17244 type0, type1, 17245 /* G_BR */ 17246 -1, 17247 /* G_BRJT */ 17248 ptype0, -1, type1, 17249 /* G_INSERT_VECTOR_ELT */ 17250 type0, type0, type1, type2, 17251 /* G_EXTRACT_VECTOR_ELT */ 17252 type0, type1, type2, 17253 /* G_SHUFFLE_VECTOR */ 17254 type0, type1, type1, -1, 17255 /* G_CTTZ */ 17256 type0, type1, 17257 /* G_CTTZ_ZERO_UNDEF */ 17258 type0, type1, 17259 /* G_CTLZ */ 17260 type0, type1, 17261 /* G_CTLZ_ZERO_UNDEF */ 17262 type0, type1, 17263 /* G_CTPOP */ 17264 type0, type1, 17265 /* G_BSWAP */ 17266 type0, type0, 17267 /* G_BITREVERSE */ 17268 type0, type0, 17269 /* G_FCEIL */ 17270 type0, type0, 17271 /* G_FCOS */ 17272 type0, type0, 17273 /* G_FSIN */ 17274 type0, type0, 17275 /* G_FSQRT */ 17276 type0, type0, 17277 /* G_FFLOOR */ 17278 type0, type0, 17279 /* G_FRINT */ 17280 type0, type0, 17281 /* G_FNEARBYINT */ 17282 type0, type0, 17283 /* G_ADDRSPACE_CAST */ 17284 type0, type1, 17285 /* G_BLOCK_ADDR */ 17286 type0, -1, 17287 /* G_JUMP_TABLE */ 17288 type0, -1, 17289 /* G_DYN_STACKALLOC */ 17290 ptype0, type1, i32imm, 17291 /* G_STRICT_FADD */ 17292 type0, type0, type0, 17293 /* G_STRICT_FSUB */ 17294 type0, type0, type0, 17295 /* G_STRICT_FMUL */ 17296 type0, type0, type0, 17297 /* G_STRICT_FDIV */ 17298 type0, type0, type0, 17299 /* G_STRICT_FREM */ 17300 type0, type0, type0, 17301 /* G_STRICT_FMA */ 17302 type0, type0, type0, type0, 17303 /* G_STRICT_FSQRT */ 17304 type0, type0, 17305 /* G_READ_REGISTER */ 17306 type0, -1, 17307 /* G_WRITE_REGISTER */ 17308 -1, type0, 17309 /* G_MEMCPY */ 17310 ptype0, ptype1, type2, untyped_imm_0, 17311 /* G_MEMCPY_INLINE */ 17312 ptype0, ptype1, type2, 17313 /* G_MEMMOVE */ 17314 ptype0, ptype1, type2, untyped_imm_0, 17315 /* G_MEMSET */ 17316 ptype0, type1, type2, untyped_imm_0, 17317 /* G_BZERO */ 17318 ptype0, type1, untyped_imm_0, 17319 /* G_VECREDUCE_SEQ_FADD */ 17320 type0, type1, type2, 17321 /* G_VECREDUCE_SEQ_FMUL */ 17322 type0, type1, type2, 17323 /* G_VECREDUCE_FADD */ 17324 type0, type1, 17325 /* G_VECREDUCE_FMUL */ 17326 type0, type1, 17327 /* G_VECREDUCE_FMAX */ 17328 type0, type1, 17329 /* G_VECREDUCE_FMIN */ 17330 type0, type1, 17331 /* G_VECREDUCE_ADD */ 17332 type0, type1, 17333 /* G_VECREDUCE_MUL */ 17334 type0, type1, 17335 /* G_VECREDUCE_AND */ 17336 type0, type1, 17337 /* G_VECREDUCE_OR */ 17338 type0, type1, 17339 /* G_VECREDUCE_XOR */ 17340 type0, type1, 17341 /* G_VECREDUCE_SMAX */ 17342 type0, type1, 17343 /* G_VECREDUCE_SMIN */ 17344 type0, type1, 17345 /* G_VECREDUCE_UMAX */ 17346 type0, type1, 17347 /* G_VECREDUCE_UMIN */ 17348 type0, type1, 17349 /* G_SBFX */ 17350 type0, type0, type1, type1, 17351 /* G_UBFX */ 17352 type0, type0, type1, type1, 17353 /* ABSMacro */ 17354 GPR32Opnd, GPR32Opnd, 17355 /* ADJCALLSTACKDOWN */ 17356 i32imm, i32imm, 17357 /* ADJCALLSTACKUP */ 17358 i32imm, i32imm, 17359 /* AND_V_D_PSEUDO */ 17360 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 17361 /* AND_V_H_PSEUDO */ 17362 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, 17363 /* AND_V_W_PSEUDO */ 17364 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 17365 /* ATOMIC_CMP_SWAP_I16 */ 17366 GPR32, -1, GPR32, GPR32, 17367 /* ATOMIC_CMP_SWAP_I16_POSTRA */ 17368 GPR32, -1, GPR32, GPR32, GPR32, GPR32, GPR32, 17369 /* ATOMIC_CMP_SWAP_I32 */ 17370 GPR32, -1, GPR32, GPR32, 17371 /* ATOMIC_CMP_SWAP_I32_POSTRA */ 17372 GPR32, -1, GPR32, GPR32, 17373 /* ATOMIC_CMP_SWAP_I64 */ 17374 GPR64, -1, GPR64, GPR64, 17375 /* ATOMIC_CMP_SWAP_I64_POSTRA */ 17376 GPR64, -1, GPR64, GPR64, 17377 /* ATOMIC_CMP_SWAP_I8 */ 17378 GPR32, -1, GPR32, GPR32, 17379 /* ATOMIC_CMP_SWAP_I8_POSTRA */ 17380 GPR32, -1, GPR32, GPR32, GPR32, GPR32, GPR32, 17381 /* ATOMIC_LOAD_ADD_I16 */ 17382 GPR32, -1, GPR32, 17383 /* ATOMIC_LOAD_ADD_I16_POSTRA */ 17384 GPR32, -1, GPR32, GPR32, GPR32, GPR32, 17385 /* ATOMIC_LOAD_ADD_I32 */ 17386 GPR32, -1, GPR32, 17387 /* ATOMIC_LOAD_ADD_I32_POSTRA */ 17388 GPR32, -1, GPR32, 17389 /* ATOMIC_LOAD_ADD_I64 */ 17390 GPR64, -1, GPR64, 17391 /* ATOMIC_LOAD_ADD_I64_POSTRA */ 17392 GPR64, -1, GPR64, 17393 /* ATOMIC_LOAD_ADD_I8 */ 17394 GPR32, -1, GPR32, 17395 /* ATOMIC_LOAD_ADD_I8_POSTRA */ 17396 GPR32, -1, GPR32, GPR32, GPR32, GPR32, 17397 /* ATOMIC_LOAD_AND_I16 */ 17398 GPR32, -1, GPR32, 17399 /* ATOMIC_LOAD_AND_I16_POSTRA */ 17400 GPR32, -1, GPR32, GPR32, GPR32, GPR32, 17401 /* ATOMIC_LOAD_AND_I32 */ 17402 GPR32, -1, GPR32, 17403 /* ATOMIC_LOAD_AND_I32_POSTRA */ 17404 GPR32, -1, GPR32, 17405 /* ATOMIC_LOAD_AND_I64 */ 17406 GPR64, -1, GPR64, 17407 /* ATOMIC_LOAD_AND_I64_POSTRA */ 17408 GPR64, -1, GPR64, 17409 /* ATOMIC_LOAD_AND_I8 */ 17410 GPR32, -1, GPR32, 17411 /* ATOMIC_LOAD_AND_I8_POSTRA */ 17412 GPR32, -1, GPR32, GPR32, GPR32, GPR32, 17413 /* ATOMIC_LOAD_MAX_I16 */ 17414 GPR32, -1, GPR32, 17415 /* ATOMIC_LOAD_MAX_I16_POSTRA */ 17416 GPR32, -1, GPR32, GPR32, GPR32, GPR32, 17417 /* ATOMIC_LOAD_MAX_I32 */ 17418 GPR32, -1, GPR32, 17419 /* ATOMIC_LOAD_MAX_I32_POSTRA */ 17420 GPR32, -1, GPR32, 17421 /* ATOMIC_LOAD_MAX_I64 */ 17422 GPR64, -1, GPR64, 17423 /* ATOMIC_LOAD_MAX_I64_POSTRA */ 17424 GPR64, -1, GPR64, 17425 /* ATOMIC_LOAD_MAX_I8 */ 17426 GPR32, -1, GPR32, 17427 /* ATOMIC_LOAD_MAX_I8_POSTRA */ 17428 GPR32, -1, GPR32, GPR32, GPR32, GPR32, 17429 /* ATOMIC_LOAD_MIN_I16 */ 17430 GPR32, -1, GPR32, 17431 /* ATOMIC_LOAD_MIN_I16_POSTRA */ 17432 GPR32, -1, GPR32, GPR32, GPR32, GPR32, 17433 /* ATOMIC_LOAD_MIN_I32 */ 17434 GPR32, -1, GPR32, 17435 /* ATOMIC_LOAD_MIN_I32_POSTRA */ 17436 GPR32, -1, GPR32, 17437 /* ATOMIC_LOAD_MIN_I64 */ 17438 GPR64, -1, GPR64, 17439 /* ATOMIC_LOAD_MIN_I64_POSTRA */ 17440 GPR64, -1, GPR64, 17441 /* ATOMIC_LOAD_MIN_I8 */ 17442 GPR32, -1, GPR32, 17443 /* ATOMIC_LOAD_MIN_I8_POSTRA */ 17444 GPR32, -1, GPR32, GPR32, GPR32, GPR32, 17445 /* ATOMIC_LOAD_NAND_I16 */ 17446 GPR32, -1, GPR32, 17447 /* ATOMIC_LOAD_NAND_I16_POSTRA */ 17448 GPR32, -1, GPR32, GPR32, GPR32, GPR32, 17449 /* ATOMIC_LOAD_NAND_I32 */ 17450 GPR32, -1, GPR32, 17451 /* ATOMIC_LOAD_NAND_I32_POSTRA */ 17452 GPR32, -1, GPR32, 17453 /* ATOMIC_LOAD_NAND_I64 */ 17454 GPR64, -1, GPR64, 17455 /* ATOMIC_LOAD_NAND_I64_POSTRA */ 17456 GPR64, -1, GPR64, 17457 /* ATOMIC_LOAD_NAND_I8 */ 17458 GPR32, -1, GPR32, 17459 /* ATOMIC_LOAD_NAND_I8_POSTRA */ 17460 GPR32, -1, GPR32, GPR32, GPR32, GPR32, 17461 /* ATOMIC_LOAD_OR_I16 */ 17462 GPR32, -1, GPR32, 17463 /* ATOMIC_LOAD_OR_I16_POSTRA */ 17464 GPR32, -1, GPR32, GPR32, GPR32, GPR32, 17465 /* ATOMIC_LOAD_OR_I32 */ 17466 GPR32, -1, GPR32, 17467 /* ATOMIC_LOAD_OR_I32_POSTRA */ 17468 GPR32, -1, GPR32, 17469 /* ATOMIC_LOAD_OR_I64 */ 17470 GPR64, -1, GPR64, 17471 /* ATOMIC_LOAD_OR_I64_POSTRA */ 17472 GPR64, -1, GPR64, 17473 /* ATOMIC_LOAD_OR_I8 */ 17474 GPR32, -1, GPR32, 17475 /* ATOMIC_LOAD_OR_I8_POSTRA */ 17476 GPR32, -1, GPR32, GPR32, GPR32, GPR32, 17477 /* ATOMIC_LOAD_SUB_I16 */ 17478 GPR32, -1, GPR32, 17479 /* ATOMIC_LOAD_SUB_I16_POSTRA */ 17480 GPR32, -1, GPR32, GPR32, GPR32, GPR32, 17481 /* ATOMIC_LOAD_SUB_I32 */ 17482 GPR32, -1, GPR32, 17483 /* ATOMIC_LOAD_SUB_I32_POSTRA */ 17484 GPR32, -1, GPR32, 17485 /* ATOMIC_LOAD_SUB_I64 */ 17486 GPR64, -1, GPR64, 17487 /* ATOMIC_LOAD_SUB_I64_POSTRA */ 17488 GPR64, -1, GPR64, 17489 /* ATOMIC_LOAD_SUB_I8 */ 17490 GPR32, -1, GPR32, 17491 /* ATOMIC_LOAD_SUB_I8_POSTRA */ 17492 GPR32, -1, GPR32, GPR32, GPR32, GPR32, 17493 /* ATOMIC_LOAD_UMAX_I16 */ 17494 GPR32, -1, GPR32, 17495 /* ATOMIC_LOAD_UMAX_I16_POSTRA */ 17496 GPR32, -1, GPR32, GPR32, GPR32, GPR32, 17497 /* ATOMIC_LOAD_UMAX_I32 */ 17498 GPR32, -1, GPR32, 17499 /* ATOMIC_LOAD_UMAX_I32_POSTRA */ 17500 GPR32, -1, GPR32, 17501 /* ATOMIC_LOAD_UMAX_I64 */ 17502 GPR64, -1, GPR64, 17503 /* ATOMIC_LOAD_UMAX_I64_POSTRA */ 17504 GPR64, -1, GPR64, 17505 /* ATOMIC_LOAD_UMAX_I8 */ 17506 GPR32, -1, GPR32, 17507 /* ATOMIC_LOAD_UMAX_I8_POSTRA */ 17508 GPR32, -1, GPR32, GPR32, GPR32, GPR32, 17509 /* ATOMIC_LOAD_UMIN_I16 */ 17510 GPR32, -1, GPR32, 17511 /* ATOMIC_LOAD_UMIN_I16_POSTRA */ 17512 GPR32, -1, GPR32, GPR32, GPR32, GPR32, 17513 /* ATOMIC_LOAD_UMIN_I32 */ 17514 GPR32, -1, GPR32, 17515 /* ATOMIC_LOAD_UMIN_I32_POSTRA */ 17516 GPR32, -1, GPR32, 17517 /* ATOMIC_LOAD_UMIN_I64 */ 17518 GPR64, -1, GPR64, 17519 /* ATOMIC_LOAD_UMIN_I64_POSTRA */ 17520 GPR64, -1, GPR64, 17521 /* ATOMIC_LOAD_UMIN_I8 */ 17522 GPR32, -1, GPR32, 17523 /* ATOMIC_LOAD_UMIN_I8_POSTRA */ 17524 GPR32, -1, GPR32, GPR32, GPR32, GPR32, 17525 /* ATOMIC_LOAD_XOR_I16 */ 17526 GPR32, -1, GPR32, 17527 /* ATOMIC_LOAD_XOR_I16_POSTRA */ 17528 GPR32, -1, GPR32, GPR32, GPR32, GPR32, 17529 /* ATOMIC_LOAD_XOR_I32 */ 17530 GPR32, -1, GPR32, 17531 /* ATOMIC_LOAD_XOR_I32_POSTRA */ 17532 GPR32, -1, GPR32, 17533 /* ATOMIC_LOAD_XOR_I64 */ 17534 GPR64, -1, GPR64, 17535 /* ATOMIC_LOAD_XOR_I64_POSTRA */ 17536 GPR64, -1, GPR64, 17537 /* ATOMIC_LOAD_XOR_I8 */ 17538 GPR32, -1, GPR32, 17539 /* ATOMIC_LOAD_XOR_I8_POSTRA */ 17540 GPR32, -1, GPR32, GPR32, GPR32, GPR32, 17541 /* ATOMIC_SWAP_I16 */ 17542 GPR32, -1, GPR32, 17543 /* ATOMIC_SWAP_I16_POSTRA */ 17544 GPR32, -1, GPR32, GPR32, GPR32, GPR32, 17545 /* ATOMIC_SWAP_I32 */ 17546 GPR32, -1, GPR32, 17547 /* ATOMIC_SWAP_I32_POSTRA */ 17548 GPR32, -1, GPR32, 17549 /* ATOMIC_SWAP_I64 */ 17550 GPR64, -1, GPR64, 17551 /* ATOMIC_SWAP_I64_POSTRA */ 17552 GPR64, -1, GPR64, 17553 /* ATOMIC_SWAP_I8 */ 17554 GPR32, -1, GPR32, 17555 /* ATOMIC_SWAP_I8_POSTRA */ 17556 GPR32, -1, GPR32, GPR32, GPR32, GPR32, 17557 /* B */ 17558 brtarget, 17559 /* BAL_BR */ 17560 brtarget, 17561 /* BAL_BR_MM */ 17562 brtarget_mm, 17563 /* BEQLImmMacro */ 17564 GPR32Opnd, imm64, brtarget, 17565 /* BGE */ 17566 GPR32Opnd, GPR32Opnd, brtarget, 17567 /* BGEImmMacro */ 17568 GPR32Opnd, imm64, brtarget, 17569 /* BGEL */ 17570 GPR32Opnd, GPR32Opnd, brtarget, 17571 /* BGELImmMacro */ 17572 GPR32Opnd, imm64, brtarget, 17573 /* BGEU */ 17574 GPR32Opnd, GPR32Opnd, brtarget, 17575 /* BGEUImmMacro */ 17576 GPR32Opnd, imm64, brtarget, 17577 /* BGEUL */ 17578 GPR32Opnd, GPR32Opnd, brtarget, 17579 /* BGEULImmMacro */ 17580 GPR32Opnd, imm64, brtarget, 17581 /* BGT */ 17582 GPR32Opnd, GPR32Opnd, brtarget, 17583 /* BGTImmMacro */ 17584 GPR32Opnd, imm64, brtarget, 17585 /* BGTL */ 17586 GPR32Opnd, GPR32Opnd, brtarget, 17587 /* BGTLImmMacro */ 17588 GPR32Opnd, imm64, brtarget, 17589 /* BGTU */ 17590 GPR32Opnd, GPR32Opnd, brtarget, 17591 /* BGTUImmMacro */ 17592 GPR32Opnd, imm64, brtarget, 17593 /* BGTUL */ 17594 GPR32Opnd, GPR32Opnd, brtarget, 17595 /* BGTULImmMacro */ 17596 GPR32Opnd, imm64, brtarget, 17597 /* BLE */ 17598 GPR32Opnd, GPR32Opnd, brtarget, 17599 /* BLEImmMacro */ 17600 GPR32Opnd, imm64, brtarget, 17601 /* BLEL */ 17602 GPR32Opnd, GPR32Opnd, brtarget, 17603 /* BLELImmMacro */ 17604 GPR32Opnd, imm64, brtarget, 17605 /* BLEU */ 17606 GPR32Opnd, GPR32Opnd, brtarget, 17607 /* BLEUImmMacro */ 17608 GPR32Opnd, imm64, brtarget, 17609 /* BLEUL */ 17610 GPR32Opnd, GPR32Opnd, brtarget, 17611 /* BLEULImmMacro */ 17612 GPR32Opnd, imm64, brtarget, 17613 /* BLT */ 17614 GPR32Opnd, GPR32Opnd, brtarget, 17615 /* BLTImmMacro */ 17616 GPR32Opnd, imm64, brtarget, 17617 /* BLTL */ 17618 GPR32Opnd, GPR32Opnd, brtarget, 17619 /* BLTLImmMacro */ 17620 GPR32Opnd, imm64, brtarget, 17621 /* BLTU */ 17622 GPR32Opnd, GPR32Opnd, brtarget, 17623 /* BLTUImmMacro */ 17624 GPR32Opnd, imm64, brtarget, 17625 /* BLTUL */ 17626 GPR32Opnd, GPR32Opnd, brtarget, 17627 /* BLTULImmMacro */ 17628 GPR32Opnd, imm64, brtarget, 17629 /* BNELImmMacro */ 17630 GPR32Opnd, imm64, brtarget, 17631 /* BPOSGE32_PSEUDO */ 17632 GPR32Opnd, 17633 /* BSEL_D_PSEUDO */ 17634 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 17635 /* BSEL_FD_PSEUDO */ 17636 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 17637 /* BSEL_FW_PSEUDO */ 17638 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 17639 /* BSEL_H_PSEUDO */ 17640 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, 17641 /* BSEL_W_PSEUDO */ 17642 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 17643 /* B_MM */ 17644 brtarget, 17645 /* B_MMR6_Pseudo */ 17646 brtarget_mm, 17647 /* B_MM_Pseudo */ 17648 brtarget_mm, 17649 /* BeqImm */ 17650 GPR32Opnd, imm64, brtarget, 17651 /* BneImm */ 17652 GPR32Opnd, imm64, brtarget, 17653 /* BteqzT8CmpX16 */ 17654 CPU16Regs, CPU16Regs, brtarget, 17655 /* BteqzT8CmpiX16 */ 17656 CPU16Regs, simm16, brtarget, 17657 /* BteqzT8SltX16 */ 17658 CPU16Regs, CPU16Regs, brtarget, 17659 /* BteqzT8SltiX16 */ 17660 CPU16Regs, simm16, brtarget, 17661 /* BteqzT8SltiuX16 */ 17662 CPU16Regs, simm16, brtarget, 17663 /* BteqzT8SltuX16 */ 17664 CPU16Regs, CPU16Regs, brtarget, 17665 /* BtnezT8CmpX16 */ 17666 CPU16Regs, CPU16Regs, brtarget, 17667 /* BtnezT8CmpiX16 */ 17668 CPU16Regs, simm16, brtarget, 17669 /* BtnezT8SltX16 */ 17670 CPU16Regs, CPU16Regs, brtarget, 17671 /* BtnezT8SltiX16 */ 17672 CPU16Regs, simm16, brtarget, 17673 /* BtnezT8SltiuX16 */ 17674 CPU16Regs, simm16, brtarget, 17675 /* BtnezT8SltuX16 */ 17676 CPU16Regs, CPU16Regs, brtarget, 17677 /* BuildPairF64 */ 17678 AFGR64Opnd, GPR32Opnd, GPR32Opnd, 17679 /* BuildPairF64_64 */ 17680 FGR64Opnd, GPR32Opnd, GPR32Opnd, 17681 /* CFTC1 */ 17682 GPR32Opnd, FGRCCOpnd, 17683 /* CONSTPOOL_ENTRY */ 17684 cpinst_operand, cpinst_operand, i32imm, 17685 /* COPY_FD_PSEUDO */ 17686 FGR64, MSA128D, uimm1_ptr, 17687 /* COPY_FW_PSEUDO */ 17688 FGR32, MSA128W, uimm2_ptr, 17689 /* CTTC1 */ 17690 FGRCCOpnd, GPR32Opnd, 17691 /* Constant32 */ 17692 simm32, 17693 /* DMULImmMacro */ 17694 GPR64Opnd, GPR64Opnd, simm32_relaxed, 17695 /* DMULMacro */ 17696 GPR64Opnd, GPR64Opnd, GPR64Opnd, 17697 /* DMULOMacro */ 17698 GPR64Opnd, GPR64Opnd, GPR64Opnd, 17699 /* DMULOUMacro */ 17700 GPR64Opnd, GPR64Opnd, GPR64Opnd, 17701 /* DROL */ 17702 GPR32Opnd, GPR32Opnd, GPR32Opnd, 17703 /* DROLImm */ 17704 GPR32Opnd, GPR32Opnd, simm16, 17705 /* DROR */ 17706 GPR32Opnd, GPR32Opnd, GPR32Opnd, 17707 /* DRORImm */ 17708 GPR32Opnd, GPR32Opnd, simm16, 17709 /* DSDivIMacro */ 17710 GPR64Opnd, GPR64Opnd, imm64, 17711 /* DSDivMacro */ 17712 GPR64Opnd, GPR64Opnd, GPR64Opnd, 17713 /* DSRemIMacro */ 17714 GPR64Opnd, GPR64Opnd, simm32_relaxed, 17715 /* DSRemMacro */ 17716 GPR64Opnd, GPR64Opnd, GPR64Opnd, 17717 /* DUDivIMacro */ 17718 GPR64Opnd, GPR64Opnd, imm64, 17719 /* DUDivMacro */ 17720 GPR64Opnd, GPR64Opnd, GPR64Opnd, 17721 /* DURemIMacro */ 17722 GPR64Opnd, GPR64Opnd, simm32_relaxed, 17723 /* DURemMacro */ 17724 GPR64Opnd, GPR64Opnd, GPR64Opnd, 17725 /* ERet */ 17726 /* ExtractElementF64 */ 17727 GPR32Opnd, AFGR64Opnd, i32imm, 17728 /* ExtractElementF64_64 */ 17729 GPR32Opnd, FGR64Opnd, i32imm, 17730 /* FABS_D */ 17731 MSA128DOpnd, MSA128DOpnd, 17732 /* FABS_W */ 17733 MSA128WOpnd, MSA128WOpnd, 17734 /* FEXP2_D_1_PSEUDO */ 17735 MSA128D, MSA128D, 17736 /* FEXP2_W_1_PSEUDO */ 17737 MSA128W, MSA128W, 17738 /* FILL_FD_PSEUDO */ 17739 MSA128D, FGR64, 17740 /* FILL_FW_PSEUDO */ 17741 MSA128W, FGR32, 17742 /* GotPrologue16 */ 17743 CPU16Regs, CPU16Regs, simm16, simm16, 17744 /* INSERT_B_VIDX64_PSEUDO */ 17745 MSA128BOpnd, MSA128BOpnd, GPR64Opnd, GPR32Opnd, 17746 /* INSERT_B_VIDX_PSEUDO */ 17747 MSA128BOpnd, MSA128BOpnd, GPR32Opnd, GPR32Opnd, 17748 /* INSERT_D_VIDX64_PSEUDO */ 17749 MSA128DOpnd, MSA128DOpnd, GPR64Opnd, GPR64Opnd, 17750 /* INSERT_D_VIDX_PSEUDO */ 17751 MSA128DOpnd, MSA128DOpnd, GPR32Opnd, GPR64Opnd, 17752 /* INSERT_FD_PSEUDO */ 17753 MSA128DOpnd, MSA128DOpnd, uimm1, FGR64Opnd, 17754 /* INSERT_FD_VIDX64_PSEUDO */ 17755 MSA128DOpnd, MSA128DOpnd, GPR64Opnd, FGR64Opnd, 17756 /* INSERT_FD_VIDX_PSEUDO */ 17757 MSA128DOpnd, MSA128DOpnd, GPR32Opnd, FGR64Opnd, 17758 /* INSERT_FW_PSEUDO */ 17759 MSA128WOpnd, MSA128WOpnd, uimm2, FGR32Opnd, 17760 /* INSERT_FW_VIDX64_PSEUDO */ 17761 MSA128WOpnd, MSA128WOpnd, GPR64Opnd, FGR32Opnd, 17762 /* INSERT_FW_VIDX_PSEUDO */ 17763 MSA128WOpnd, MSA128WOpnd, GPR32Opnd, FGR32Opnd, 17764 /* INSERT_H_VIDX64_PSEUDO */ 17765 MSA128HOpnd, MSA128HOpnd, GPR64Opnd, GPR32Opnd, 17766 /* INSERT_H_VIDX_PSEUDO */ 17767 MSA128HOpnd, MSA128HOpnd, GPR32Opnd, GPR32Opnd, 17768 /* INSERT_W_VIDX64_PSEUDO */ 17769 MSA128WOpnd, MSA128WOpnd, GPR64Opnd, GPR32Opnd, 17770 /* INSERT_W_VIDX_PSEUDO */ 17771 MSA128WOpnd, MSA128WOpnd, GPR32Opnd, GPR32Opnd, 17772 /* JALR64Pseudo */ 17773 GPR64Opnd, 17774 /* JALRHB64Pseudo */ 17775 GPR64Opnd, 17776 /* JALRHBPseudo */ 17777 GPR32Opnd, 17778 /* JALRPseudo */ 17779 GPR32Opnd, 17780 /* JAL_MMR6 */ 17781 calltarget, 17782 /* JalOneReg */ 17783 GPR32Opnd, 17784 /* JalTwoReg */ 17785 GPR32Opnd, GPR32Opnd, 17786 /* LDMacro */ 17787 GPR32Opnd, -1, simm16, 17788 /* LDR_D */ 17789 MSA128DOpnd, -1, GPR32, 17790 /* LDR_W */ 17791 MSA128WOpnd, -1, GPR32, 17792 /* LD_F16 */ 17793 MSA128F16, -1, simm10, 17794 /* LOAD_ACC128 */ 17795 ACC128, -1, simm16, 17796 /* LOAD_ACC64 */ 17797 ACC64, -1, simm16, 17798 /* LOAD_ACC64DSP */ 17799 ACC64DSPOpnd, -1, simm16, 17800 /* LOAD_CCOND_DSP */ 17801 DSPCC, -1, simm16, 17802 /* LONG_BRANCH_ADDiu */ 17803 GPR32Opnd, GPR32Opnd, brtarget, brtarget, 17804 /* LONG_BRANCH_ADDiu2Op */ 17805 GPR32Opnd, GPR32Opnd, brtarget, 17806 /* LONG_BRANCH_DADDiu */ 17807 GPR64Opnd, GPR64Opnd, brtarget, brtarget, 17808 /* LONG_BRANCH_DADDiu2Op */ 17809 GPR64Opnd, GPR64Opnd, brtarget, 17810 /* LONG_BRANCH_LUi */ 17811 GPR32Opnd, brtarget, brtarget, 17812 /* LONG_BRANCH_LUi2Op */ 17813 GPR32Opnd, brtarget, 17814 /* LONG_BRANCH_LUi2Op_64 */ 17815 GPR64Opnd, brtarget, 17816 /* LWM_MM */ 17817 reglist, -1, simm12, 17818 /* LoadAddrImm32 */ 17819 GPR32Opnd, i32imm, 17820 /* LoadAddrImm64 */ 17821 GPR64Opnd, imm64, 17822 /* LoadAddrReg32 */ 17823 GPR32Opnd, -1, simm16, 17824 /* LoadAddrReg64 */ 17825 GPR64Opnd, -1, simm16, 17826 /* LoadImm32 */ 17827 GPR32Opnd, uimm32_coerced, 17828 /* LoadImm64 */ 17829 GPR64Opnd, imm64, 17830 /* LoadImmDoubleFGR */ 17831 StrictlyFGR64Opnd, imm64, 17832 /* LoadImmDoubleFGR_32 */ 17833 StrictlyAFGR64Opnd, imm64, 17834 /* LoadImmDoubleGPR */ 17835 GPR32Opnd, imm64, 17836 /* LoadImmSingleFGR */ 17837 StrictlyFGR32Opnd, imm64, 17838 /* LoadImmSingleGPR */ 17839 GPR32Opnd, imm64, 17840 /* LwConstant32 */ 17841 CPU16Regs, simm32, simm32, 17842 /* MFTACX */ 17843 GPR32Opnd, ACC64DSPOpnd, 17844 /* MFTC0 */ 17845 GPR32Opnd, COP0Opnd, uimm3, 17846 /* MFTC1 */ 17847 GPR32Opnd, FGR32Opnd, 17848 /* MFTDSP */ 17849 GPR32Opnd, 17850 /* MFTGPR */ 17851 GPR32Opnd, GPR32Opnd, uimm3, 17852 /* MFTHC1 */ 17853 GPR32Opnd, FGR32Opnd, 17854 /* MFTHI */ 17855 GPR32Opnd, ACC64DSPOpnd, 17856 /* MFTLO */ 17857 GPR32Opnd, ACC64DSPOpnd, 17858 /* MIPSeh_return32 */ 17859 GPR32, GPR32, 17860 /* MIPSeh_return64 */ 17861 GPR64, GPR64, 17862 /* MSA_FP_EXTEND_D_PSEUDO */ 17863 FGR64Opnd, MSA128F16, 17864 /* MSA_FP_EXTEND_W_PSEUDO */ 17865 FGR32Opnd, MSA128F16, 17866 /* MSA_FP_ROUND_D_PSEUDO */ 17867 MSA128F16, FGR64Opnd, 17868 /* MSA_FP_ROUND_W_PSEUDO */ 17869 MSA128F16, FGR32Opnd, 17870 /* MTTACX */ 17871 ACC64DSPOpnd, GPR32Opnd, 17872 /* MTTC0 */ 17873 COP0Opnd, GPR32Opnd, uimm3, 17874 /* MTTC1 */ 17875 FGR32Opnd, GPR32Opnd, 17876 /* MTTDSP */ 17877 GPR32Opnd, 17878 /* MTTGPR */ 17879 GPR32Opnd, GPR32Opnd, 17880 /* MTTHC1 */ 17881 FGR32Opnd, GPR32Opnd, 17882 /* MTTHI */ 17883 ACC64DSPOpnd, GPR32Opnd, 17884 /* MTTLO */ 17885 ACC64DSPOpnd, GPR32Opnd, 17886 /* MULImmMacro */ 17887 GPR32Opnd, GPR32Opnd, simm32_relaxed, 17888 /* MULOMacro */ 17889 GPR32Opnd, GPR32Opnd, GPR32Opnd, 17890 /* MULOUMacro */ 17891 GPR32Opnd, GPR32Opnd, GPR32Opnd, 17892 /* MultRxRy16 */ 17893 CPU16Regs, CPU16Regs, 17894 /* MultRxRyRz16 */ 17895 CPU16Regs, CPU16Regs, CPU16Regs, 17896 /* MultuRxRy16 */ 17897 CPU16Regs, CPU16Regs, 17898 /* MultuRxRyRz16 */ 17899 CPU16Regs, CPU16Regs, CPU16Regs, 17900 /* NOP */ 17901 /* NORImm */ 17902 GPR32Opnd, GPR32Opnd, simm32_relaxed, 17903 /* NORImm64 */ 17904 GPR64Opnd, GPR64Opnd, imm64, 17905 /* NOR_V_D_PSEUDO */ 17906 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 17907 /* NOR_V_H_PSEUDO */ 17908 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, 17909 /* NOR_V_W_PSEUDO */ 17910 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 17911 /* OR_V_D_PSEUDO */ 17912 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 17913 /* OR_V_H_PSEUDO */ 17914 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, 17915 /* OR_V_W_PSEUDO */ 17916 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 17917 /* PseudoCMPU_EQ_QB */ 17918 DSPCC, DSPROpnd, DSPROpnd, 17919 /* PseudoCMPU_LE_QB */ 17920 DSPCC, DSPROpnd, DSPROpnd, 17921 /* PseudoCMPU_LT_QB */ 17922 DSPCC, DSPROpnd, DSPROpnd, 17923 /* PseudoCMP_EQ_PH */ 17924 DSPCC, DSPROpnd, DSPROpnd, 17925 /* PseudoCMP_LE_PH */ 17926 DSPCC, DSPROpnd, DSPROpnd, 17927 /* PseudoCMP_LT_PH */ 17928 DSPCC, DSPROpnd, DSPROpnd, 17929 /* PseudoCVT_D32_W */ 17930 AFGR64Opnd, GPR32Opnd, 17931 /* PseudoCVT_D64_L */ 17932 FGR64Opnd, GPR64Opnd, 17933 /* PseudoCVT_D64_W */ 17934 FGR64Opnd, GPR32Opnd, 17935 /* PseudoCVT_S_L */ 17936 FGR64Opnd, GPR64Opnd, 17937 /* PseudoCVT_S_W */ 17938 FGR32Opnd, GPR32Opnd, 17939 /* PseudoDMULT */ 17940 ACC128, GPR64Opnd, GPR64Opnd, 17941 /* PseudoDMULTu */ 17942 ACC128, GPR64Opnd, GPR64Opnd, 17943 /* PseudoDSDIV */ 17944 ACC128, GPR64Opnd, GPR64Opnd, 17945 /* PseudoDUDIV */ 17946 ACC128, GPR64Opnd, GPR64Opnd, 17947 /* PseudoD_SELECT_I */ 17948 GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd, 17949 /* PseudoD_SELECT_I64 */ 17950 GPR64Opnd, GPR64Opnd, GPR32Opnd, GPR64Opnd, GPR64Opnd, GPR64Opnd, GPR64Opnd, 17951 /* PseudoIndirectBranch */ 17952 GPR32Opnd, 17953 /* PseudoIndirectBranch64 */ 17954 GPR64Opnd, 17955 /* PseudoIndirectBranch64R6 */ 17956 GPR64Opnd, 17957 /* PseudoIndirectBranchR6 */ 17958 GPR32Opnd, 17959 /* PseudoIndirectBranch_MM */ 17960 GPR32Opnd, 17961 /* PseudoIndirectBranch_MMR6 */ 17962 GPR32Opnd, 17963 /* PseudoIndirectHazardBranch */ 17964 GPR32Opnd, 17965 /* PseudoIndirectHazardBranch64 */ 17966 GPR64Opnd, 17967 /* PseudoIndrectHazardBranch64R6 */ 17968 GPR64Opnd, 17969 /* PseudoIndrectHazardBranchR6 */ 17970 GPR32Opnd, 17971 /* PseudoMADD */ 17972 ACC64, GPR32Opnd, GPR32Opnd, ACC64, 17973 /* PseudoMADDU */ 17974 ACC64, GPR32Opnd, GPR32Opnd, ACC64, 17975 /* PseudoMADDU_MM */ 17976 ACC64, GPR32Opnd, GPR32Opnd, ACC64, 17977 /* PseudoMADD_MM */ 17978 ACC64, GPR32Opnd, GPR32Opnd, ACC64, 17979 /* PseudoMFHI */ 17980 GPR32, ACC64, 17981 /* PseudoMFHI64 */ 17982 GPR64, ACC128, 17983 /* PseudoMFHI_MM */ 17984 GPR32, ACC64, 17985 /* PseudoMFLO */ 17986 GPR32, ACC64, 17987 /* PseudoMFLO64 */ 17988 GPR64, ACC128, 17989 /* PseudoMFLO_MM */ 17990 GPR32, ACC64, 17991 /* PseudoMSUB */ 17992 ACC64, GPR32Opnd, GPR32Opnd, ACC64, 17993 /* PseudoMSUBU */ 17994 ACC64, GPR32Opnd, GPR32Opnd, ACC64, 17995 /* PseudoMSUBU_MM */ 17996 ACC64, GPR32Opnd, GPR32Opnd, ACC64, 17997 /* PseudoMSUB_MM */ 17998 ACC64, GPR32Opnd, GPR32Opnd, ACC64, 17999 /* PseudoMTLOHI */ 18000 ACC64, GPR32, GPR32, 18001 /* PseudoMTLOHI64 */ 18002 ACC128, GPR64, GPR64, 18003 /* PseudoMTLOHI_DSP */ 18004 ACC64DSP, GPR32, GPR32, 18005 /* PseudoMTLOHI_MM */ 18006 ACC64, GPR32, GPR32, 18007 /* PseudoMULT */ 18008 ACC64, GPR32Opnd, GPR32Opnd, 18009 /* PseudoMULT_MM */ 18010 ACC64, GPR32Opnd, GPR32Opnd, 18011 /* PseudoMULTu */ 18012 ACC64, GPR32Opnd, GPR32Opnd, 18013 /* PseudoMULTu_MM */ 18014 ACC64, GPR32Opnd, GPR32Opnd, 18015 /* PseudoPICK_PH */ 18016 DSPROpnd, DSPCC, DSPROpnd, DSPROpnd, 18017 /* PseudoPICK_QB */ 18018 DSPROpnd, DSPCC, DSPROpnd, DSPROpnd, 18019 /* PseudoReturn */ 18020 GPR32Opnd, 18021 /* PseudoReturn64 */ 18022 GPR64Opnd, 18023 /* PseudoSDIV */ 18024 ACC64, GPR32Opnd, GPR32Opnd, 18025 /* PseudoSELECTFP_F_D32 */ 18026 AFGR64Opnd, FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, 18027 /* PseudoSELECTFP_F_D64 */ 18028 FGR64Opnd, FCCRegsOpnd, FGR64Opnd, FGR64Opnd, 18029 /* PseudoSELECTFP_F_I */ 18030 GPR32Opnd, FCCRegsOpnd, GPR32Opnd, GPR32Opnd, 18031 /* PseudoSELECTFP_F_I64 */ 18032 GPR64Opnd, FCCRegsOpnd, GPR64Opnd, GPR64Opnd, 18033 /* PseudoSELECTFP_F_S */ 18034 FGR32Opnd, FCCRegsOpnd, FGR32Opnd, FGR32Opnd, 18035 /* PseudoSELECTFP_T_D32 */ 18036 AFGR64Opnd, FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, 18037 /* PseudoSELECTFP_T_D64 */ 18038 FGR64Opnd, FCCRegsOpnd, FGR64Opnd, FGR64Opnd, 18039 /* PseudoSELECTFP_T_I */ 18040 GPR32Opnd, FCCRegsOpnd, GPR32Opnd, GPR32Opnd, 18041 /* PseudoSELECTFP_T_I64 */ 18042 GPR64Opnd, FCCRegsOpnd, GPR64Opnd, GPR64Opnd, 18043 /* PseudoSELECTFP_T_S */ 18044 FGR32Opnd, FCCRegsOpnd, FGR32Opnd, FGR32Opnd, 18045 /* PseudoSELECT_D32 */ 18046 AFGR64Opnd, GPR32Opnd, AFGR64Opnd, AFGR64Opnd, 18047 /* PseudoSELECT_D64 */ 18048 FGR64Opnd, GPR32Opnd, FGR64Opnd, FGR64Opnd, 18049 /* PseudoSELECT_I */ 18050 GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd, 18051 /* PseudoSELECT_I64 */ 18052 GPR64Opnd, GPR32Opnd, GPR64Opnd, GPR64Opnd, 18053 /* PseudoSELECT_S */ 18054 FGR32Opnd, GPR32Opnd, FGR32Opnd, FGR32Opnd, 18055 /* PseudoTRUNC_W_D */ 18056 FGR32Opnd, FGR64Opnd, GPR32Opnd, 18057 /* PseudoTRUNC_W_D32 */ 18058 FGR32Opnd, AFGR64Opnd, GPR32Opnd, 18059 /* PseudoTRUNC_W_S */ 18060 FGR32Opnd, FGR32Opnd, GPR32Opnd, 18061 /* PseudoUDIV */ 18062 ACC64, GPR32Opnd, GPR32Opnd, 18063 /* ROL */ 18064 GPR32Opnd, GPR32Opnd, GPR32Opnd, 18065 /* ROLImm */ 18066 GPR32Opnd, GPR32Opnd, simm16, 18067 /* ROR */ 18068 GPR32Opnd, GPR32Opnd, GPR32Opnd, 18069 /* RORImm */ 18070 GPR32Opnd, GPR32Opnd, simm16, 18071 /* RetRA */ 18072 /* RetRA16 */ 18073 /* SDC1_M1 */ 18074 AFGR64Opnd, -1, simm16, 18075 /* SDIV_MM_Pseudo */ 18076 ACC64, GPR32Opnd, GPR32Opnd, 18077 /* SDMacro */ 18078 GPR32Opnd, -1, simm16, 18079 /* SDivIMacro */ 18080 GPR32Opnd, GPR32Opnd, simm32, 18081 /* SDivMacro */ 18082 GPR32NonZeroOpnd, GPR32Opnd, GPR32Opnd, 18083 /* SEQIMacro */ 18084 GPR32Opnd, GPR32Opnd, simm32_relaxed, 18085 /* SEQMacro */ 18086 GPR32Opnd, GPR32Opnd, GPR32Opnd, 18087 /* SGE */ 18088 GPR32Opnd, GPR32Opnd, GPR32Opnd, 18089 /* SGEImm */ 18090 GPR32Opnd, GPR32Opnd, simm32, 18091 /* SGEImm64 */ 18092 GPR64Opnd, GPR64Opnd, imm64, 18093 /* SGEU */ 18094 GPR32Opnd, GPR32Opnd, GPR32Opnd, 18095 /* SGEUImm */ 18096 GPR32Opnd, GPR32Opnd, uimm32_coerced, 18097 /* SGEUImm64 */ 18098 GPR64Opnd, GPR64Opnd, imm64, 18099 /* SGTImm */ 18100 GPR32Opnd, GPR32Opnd, simm32, 18101 /* SGTImm64 */ 18102 GPR64Opnd, GPR64Opnd, imm64, 18103 /* SGTUImm */ 18104 GPR32Opnd, GPR32Opnd, uimm32_coerced, 18105 /* SGTUImm64 */ 18106 GPR64Opnd, GPR64Opnd, imm64, 18107 /* SLE */ 18108 GPR32Opnd, GPR32Opnd, GPR32Opnd, 18109 /* SLEImm */ 18110 GPR32Opnd, GPR32Opnd, simm32, 18111 /* SLEImm64 */ 18112 GPR64Opnd, GPR64Opnd, imm64, 18113 /* SLEU */ 18114 GPR32Opnd, GPR32Opnd, GPR32Opnd, 18115 /* SLEUImm */ 18116 GPR32Opnd, GPR32Opnd, uimm32_coerced, 18117 /* SLEUImm64 */ 18118 GPR64Opnd, GPR64Opnd, imm64, 18119 /* SLTImm64 */ 18120 GPR64Opnd, GPR64Opnd, imm64, 18121 /* SLTUImm64 */ 18122 GPR64Opnd, GPR64Opnd, imm64, 18123 /* SNEIMacro */ 18124 GPR32Opnd, GPR32Opnd, simm32_relaxed, 18125 /* SNEMacro */ 18126 GPR32Opnd, GPR32Opnd, GPR32Opnd, 18127 /* SNZ_B_PSEUDO */ 18128 GPR32, MSA128B, 18129 /* SNZ_D_PSEUDO */ 18130 GPR32, MSA128D, 18131 /* SNZ_H_PSEUDO */ 18132 GPR32, MSA128H, 18133 /* SNZ_V_PSEUDO */ 18134 GPR32, MSA128B, 18135 /* SNZ_W_PSEUDO */ 18136 GPR32, MSA128W, 18137 /* SRemIMacro */ 18138 GPR32Opnd, GPR32Opnd, simm32_relaxed, 18139 /* SRemMacro */ 18140 GPR32Opnd, GPR32Opnd, GPR32Opnd, 18141 /* STORE_ACC128 */ 18142 ACC128, -1, simm16, 18143 /* STORE_ACC64 */ 18144 ACC64, -1, simm16, 18145 /* STORE_ACC64DSP */ 18146 ACC64DSPOpnd, -1, simm16, 18147 /* STORE_CCOND_DSP */ 18148 DSPCC, -1, simm16, 18149 /* STR_D */ 18150 MSA128DOpnd, -1, GPR32, 18151 /* STR_W */ 18152 MSA128WOpnd, -1, GPR32, 18153 /* ST_F16 */ 18154 MSA128F16, -1, simm10, 18155 /* SWM_MM */ 18156 reglist, -1, simm12, 18157 /* SZ_B_PSEUDO */ 18158 GPR32, MSA128B, 18159 /* SZ_D_PSEUDO */ 18160 GPR32, MSA128D, 18161 /* SZ_H_PSEUDO */ 18162 GPR32, MSA128H, 18163 /* SZ_V_PSEUDO */ 18164 GPR32, MSA128B, 18165 /* SZ_W_PSEUDO */ 18166 GPR32, MSA128W, 18167 /* SaaAddr */ 18168 GPR64Opnd, -1, simm16, 18169 /* SaadAddr */ 18170 GPR64Opnd, -1, simm16, 18171 /* SelBeqZ */ 18172 CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, 18173 /* SelBneZ */ 18174 CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, 18175 /* SelTBteqZCmp */ 18176 CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, 18177 /* SelTBteqZCmpi */ 18178 CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, simm16, 18179 /* SelTBteqZSlt */ 18180 CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, 18181 /* SelTBteqZSlti */ 18182 CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, simm16, 18183 /* SelTBteqZSltiu */ 18184 CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, simm16, 18185 /* SelTBteqZSltu */ 18186 CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, 18187 /* SelTBtneZCmp */ 18188 CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, 18189 /* SelTBtneZCmpi */ 18190 CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, simm16, 18191 /* SelTBtneZSlt */ 18192 CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, 18193 /* SelTBtneZSlti */ 18194 CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, simm16, 18195 /* SelTBtneZSltiu */ 18196 CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, simm16, 18197 /* SelTBtneZSltu */ 18198 CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, 18199 /* SltCCRxRy16 */ 18200 CPU16Regs, CPU16Regs, CPU16Regs, 18201 /* SltiCCRxImmX16 */ 18202 CPU16Regs, CPU16Regs, simm16, 18203 /* SltiuCCRxImmX16 */ 18204 CPU16Regs, CPU16Regs, simm16, 18205 /* SltuCCRxRy16 */ 18206 CPU16Regs, CPU16Regs, CPU16Regs, 18207 /* SltuRxRyRz16 */ 18208 CPU16Regs, CPU16Regs, CPU16Regs, 18209 /* TAILCALL */ 18210 calltarget, 18211 /* TAILCALL64R6REG */ 18212 GPR64Opnd, 18213 /* TAILCALLHB64R6REG */ 18214 GPR64Opnd, 18215 /* TAILCALLHBR6REG */ 18216 GPR32Opnd, 18217 /* TAILCALLR6REG */ 18218 GPR32Opnd, 18219 /* TAILCALLREG */ 18220 GPR32Opnd, 18221 /* TAILCALLREG64 */ 18222 GPR64Opnd, 18223 /* TAILCALLREGHB */ 18224 GPR32Opnd, 18225 /* TAILCALLREGHB64 */ 18226 GPR64Opnd, 18227 /* TAILCALLREG_MM */ 18228 GPR32Opnd, 18229 /* TAILCALLREG_MMR6 */ 18230 GPR32Opnd, 18231 /* TAILCALL_MM */ 18232 calltarget, 18233 /* TAILCALL_MMR6 */ 18234 calltarget, 18235 /* TRAP */ 18236 /* TRAP_MM */ 18237 /* UDIV_MM_Pseudo */ 18238 ACC64, GPR32Opnd, GPR32Opnd, 18239 /* UDivIMacro */ 18240 GPR32Opnd, GPR32Opnd, simm32, 18241 /* UDivMacro */ 18242 GPR32Opnd, GPR32Opnd, GPR32Opnd, 18243 /* URemIMacro */ 18244 GPR32Opnd, GPR32Opnd, simm32_relaxed, 18245 /* URemMacro */ 18246 GPR32Opnd, GPR32Opnd, GPR32Opnd, 18247 /* Ulh */ 18248 GPR32Opnd, -1, simm16, 18249 /* Ulhu */ 18250 GPR32Opnd, -1, simm16, 18251 /* Ulw */ 18252 GPR32Opnd, -1, simm16, 18253 /* Ush */ 18254 GPR32Opnd, -1, simm16, 18255 /* Usw */ 18256 GPR32Opnd, -1, simm16, 18257 /* XOR_V_D_PSEUDO */ 18258 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 18259 /* XOR_V_H_PSEUDO */ 18260 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, 18261 /* XOR_V_W_PSEUDO */ 18262 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 18263 /* ABSQ_S_PH */ 18264 DSPROpnd, DSPROpnd, 18265 /* ABSQ_S_PH_MM */ 18266 DSPROpnd, DSPROpnd, 18267 /* ABSQ_S_QB */ 18268 DSPROpnd, DSPROpnd, 18269 /* ABSQ_S_QB_MMR2 */ 18270 DSPROpnd, DSPROpnd, 18271 /* ABSQ_S_W */ 18272 GPR32Opnd, GPR32Opnd, 18273 /* ABSQ_S_W_MM */ 18274 GPR32Opnd, GPR32Opnd, 18275 /* ADD */ 18276 GPR32Opnd, GPR32Opnd, GPR32Opnd, 18277 /* ADDIUPC */ 18278 GPR32Opnd, simm19_lsl2, 18279 /* ADDIUPC_MM */ 18280 GPRMM16Opnd, simm23_lsl2, 18281 /* ADDIUPC_MMR6 */ 18282 GPR32Opnd, simm19_lsl2, 18283 /* ADDIUR1SP_MM */ 18284 GPRMM16Opnd, uimm6_lsl2, 18285 /* ADDIUR2_MM */ 18286 GPRMM16Opnd, GPRMM16Opnd, simm3_lsa2, 18287 /* ADDIUS5_MM */ 18288 GPR32Opnd, GPR32Opnd, simm4, 18289 /* ADDIUSP_MM */ 18290 simm9_addiusp, 18291 /* ADDIU_MMR6 */ 18292 GPR32Opnd, GPR32Opnd, simm16, 18293 /* ADDQH_PH */ 18294 DSPROpnd, DSPROpnd, DSPROpnd, 18295 /* ADDQH_PH_MMR2 */ 18296 DSPROpnd, DSPROpnd, DSPROpnd, 18297 /* ADDQH_R_PH */ 18298 DSPROpnd, DSPROpnd, DSPROpnd, 18299 /* ADDQH_R_PH_MMR2 */ 18300 DSPROpnd, DSPROpnd, DSPROpnd, 18301 /* ADDQH_R_W */ 18302 GPR32Opnd, GPR32Opnd, GPR32Opnd, 18303 /* ADDQH_R_W_MMR2 */ 18304 GPR32Opnd, GPR32Opnd, GPR32Opnd, 18305 /* ADDQH_W */ 18306 GPR32Opnd, GPR32Opnd, GPR32Opnd, 18307 /* ADDQH_W_MMR2 */ 18308 GPR32Opnd, GPR32Opnd, GPR32Opnd, 18309 /* ADDQ_PH */ 18310 DSPROpnd, DSPROpnd, DSPROpnd, 18311 /* ADDQ_PH_MM */ 18312 DSPROpnd, DSPROpnd, DSPROpnd, 18313 /* ADDQ_S_PH */ 18314 DSPROpnd, DSPROpnd, DSPROpnd, 18315 /* ADDQ_S_PH_MM */ 18316 DSPROpnd, DSPROpnd, DSPROpnd, 18317 /* ADDQ_S_W */ 18318 GPR32Opnd, GPR32Opnd, GPR32Opnd, 18319 /* ADDQ_S_W_MM */ 18320 GPR32Opnd, GPR32Opnd, GPR32Opnd, 18321 /* ADDR_PS64 */ 18322 FGR64Opnd, FGR64Opnd, FGR64Opnd, 18323 /* ADDSC */ 18324 GPR32Opnd, GPR32Opnd, GPR32Opnd, 18325 /* ADDSC_MM */ 18326 GPR32Opnd, GPR32Opnd, GPR32Opnd, 18327 /* ADDS_A_B */ 18328 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, 18329 /* ADDS_A_D */ 18330 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 18331 /* ADDS_A_H */ 18332 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, 18333 /* ADDS_A_W */ 18334 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 18335 /* ADDS_S_B */ 18336 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, 18337 /* ADDS_S_D */ 18338 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 18339 /* ADDS_S_H */ 18340 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, 18341 /* ADDS_S_W */ 18342 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 18343 /* ADDS_U_B */ 18344 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, 18345 /* ADDS_U_D */ 18346 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 18347 /* ADDS_U_H */ 18348 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, 18349 /* ADDS_U_W */ 18350 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 18351 /* ADDU16_MM */ 18352 GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd, 18353 /* ADDU16_MMR6 */ 18354 GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd, 18355 /* ADDUH_QB */ 18356 DSPROpnd, DSPROpnd, DSPROpnd, 18357 /* ADDUH_QB_MMR2 */ 18358 DSPROpnd, DSPROpnd, DSPROpnd, 18359 /* ADDUH_R_QB */ 18360 DSPROpnd, DSPROpnd, DSPROpnd, 18361 /* ADDUH_R_QB_MMR2 */ 18362 DSPROpnd, DSPROpnd, DSPROpnd, 18363 /* ADDU_MMR6 */ 18364 GPR32Opnd, GPR32Opnd, GPR32Opnd, 18365 /* ADDU_PH */ 18366 DSPROpnd, DSPROpnd, DSPROpnd, 18367 /* ADDU_PH_MMR2 */ 18368 DSPROpnd, DSPROpnd, DSPROpnd, 18369 /* ADDU_QB */ 18370 DSPROpnd, DSPROpnd, DSPROpnd, 18371 /* ADDU_QB_MM */ 18372 DSPROpnd, DSPROpnd, DSPROpnd, 18373 /* ADDU_S_PH */ 18374 DSPROpnd, DSPROpnd, DSPROpnd, 18375 /* ADDU_S_PH_MMR2 */ 18376 DSPROpnd, DSPROpnd, DSPROpnd, 18377 /* ADDU_S_QB */ 18378 DSPROpnd, DSPROpnd, DSPROpnd, 18379 /* ADDU_S_QB_MM */ 18380 DSPROpnd, DSPROpnd, DSPROpnd, 18381 /* ADDVI_B */ 18382 MSA128BOpnd, MSA128BOpnd, vsplat_uimm5, 18383 /* ADDVI_D */ 18384 MSA128DOpnd, MSA128DOpnd, vsplat_uimm5, 18385 /* ADDVI_H */ 18386 MSA128HOpnd, MSA128HOpnd, vsplat_uimm5, 18387 /* ADDVI_W */ 18388 MSA128WOpnd, MSA128WOpnd, vsplat_uimm5, 18389 /* ADDV_B */ 18390 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, 18391 /* ADDV_D */ 18392 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 18393 /* ADDV_H */ 18394 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, 18395 /* ADDV_W */ 18396 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 18397 /* ADDWC */ 18398 GPR32Opnd, GPR32Opnd, GPR32Opnd, 18399 /* ADDWC_MM */ 18400 GPR32Opnd, GPR32Opnd, GPR32Opnd, 18401 /* ADD_A_B */ 18402 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, 18403 /* ADD_A_D */ 18404 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 18405 /* ADD_A_H */ 18406 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, 18407 /* ADD_A_W */ 18408 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 18409 /* ADD_MM */ 18410 GPR32Opnd, GPR32Opnd, GPR32Opnd, 18411 /* ADD_MMR6 */ 18412 GPR32Opnd, GPR32Opnd, GPR32Opnd, 18413 /* ADDi */ 18414 GPR32Opnd, GPR32Opnd, simm16_relaxed, 18415 /* ADDi_MM */ 18416 GPR32Opnd, GPR32Opnd, simm16, 18417 /* ADDiu */ 18418 GPR32Opnd, GPR32Opnd, simm16_relaxed, 18419 /* ADDiu_MM */ 18420 GPR32Opnd, GPR32Opnd, simm16, 18421 /* ADDu */ 18422 GPR32Opnd, GPR32Opnd, GPR32Opnd, 18423 /* ADDu_MM */ 18424 GPR32Opnd, GPR32Opnd, GPR32Opnd, 18425 /* ALIGN */ 18426 GPR32Opnd, GPR32Opnd, GPR32Opnd, uimm2, 18427 /* ALIGN_MMR6 */ 18428 GPR32Opnd, GPR32Opnd, GPR32Opnd, uimm2, 18429 /* ALUIPC */ 18430 GPR32Opnd, simm16, 18431 /* ALUIPC_MMR6 */ 18432 GPR32Opnd, simm16, 18433 /* AND */ 18434 GPR32Opnd, GPR32Opnd, GPR32Opnd, 18435 /* AND16_MM */ 18436 GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd, 18437 /* AND16_MMR6 */ 18438 GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd, 18439 /* AND64 */ 18440 GPR64Opnd, GPR64Opnd, GPR64Opnd, 18441 /* ANDI16_MM */ 18442 GPRMM16Opnd, GPRMM16Opnd, uimm4_andi, 18443 /* ANDI16_MMR6 */ 18444 GPRMM16Opnd, GPRMM16Opnd, uimm4_andi, 18445 /* ANDI_B */ 18446 MSA128BOpnd, MSA128BOpnd, vsplat_uimm8, 18447 /* ANDI_MMR6 */ 18448 GPR32Opnd, GPR32Opnd, uimm16, 18449 /* AND_MM */ 18450 GPR32Opnd, GPR32Opnd, GPR32Opnd, 18451 /* AND_MMR6 */ 18452 GPR32Opnd, GPR32Opnd, GPR32Opnd, 18453 /* AND_V */ 18454 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, 18455 /* ANDi */ 18456 GPR32Opnd, GPR32Opnd, uimm16, 18457 /* ANDi64 */ 18458 GPR64Opnd, GPR64Opnd, uimm16_64, 18459 /* ANDi_MM */ 18460 GPR32Opnd, GPR32Opnd, uimm16, 18461 /* APPEND */ 18462 GPR32Opnd, GPR32Opnd, uimm5, GPR32Opnd, 18463 /* APPEND_MMR2 */ 18464 GPR32Opnd, GPR32Opnd, uimm5, GPR32Opnd, 18465 /* ASUB_S_B */ 18466 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, 18467 /* ASUB_S_D */ 18468 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 18469 /* ASUB_S_H */ 18470 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, 18471 /* ASUB_S_W */ 18472 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 18473 /* ASUB_U_B */ 18474 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, 18475 /* ASUB_U_D */ 18476 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 18477 /* ASUB_U_H */ 18478 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, 18479 /* ASUB_U_W */ 18480 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 18481 /* AUI */ 18482 GPR32Opnd, GPR32Opnd, uimm16, 18483 /* AUIPC */ 18484 GPR32Opnd, simm16, 18485 /* AUIPC_MMR6 */ 18486 GPR32Opnd, simm16, 18487 /* AUI_MMR6 */ 18488 GPR32Opnd, GPR32Opnd, uimm16, 18489 /* AVER_S_B */ 18490 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, 18491 /* AVER_S_D */ 18492 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 18493 /* AVER_S_H */ 18494 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, 18495 /* AVER_S_W */ 18496 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 18497 /* AVER_U_B */ 18498 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, 18499 /* AVER_U_D */ 18500 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 18501 /* AVER_U_H */ 18502 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, 18503 /* AVER_U_W */ 18504 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 18505 /* AVE_S_B */ 18506 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, 18507 /* AVE_S_D */ 18508 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 18509 /* AVE_S_H */ 18510 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, 18511 /* AVE_S_W */ 18512 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 18513 /* AVE_U_B */ 18514 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, 18515 /* AVE_U_D */ 18516 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 18517 /* AVE_U_H */ 18518 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, 18519 /* AVE_U_W */ 18520 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 18521 /* AddiuRxImmX16 */ 18522 CPU16Regs, simm16, 18523 /* AddiuRxPcImmX16 */ 18524 CPU16Regs, simm16, 18525 /* AddiuRxRxImm16 */ 18526 CPU16Regs, CPU16Regs, simm16, 18527 /* AddiuRxRxImmX16 */ 18528 CPU16Regs, CPU16Regs, simm16, 18529 /* AddiuRxRyOffMemX16 */ 18530 CPU16Regs, CPU16RegsPlusSP, simm16, 18531 /* AddiuSpImm16 */ 18532 simm16, 18533 /* AddiuSpImmX16 */ 18534 simm16, 18535 /* AdduRxRyRz16 */ 18536 CPU16Regs, CPU16Regs, CPU16Regs, 18537 /* AndRxRxRy16 */ 18538 CPU16Regs, CPU16Regs, CPU16Regs, 18539 /* B16_MM */ 18540 brtarget10_mm, 18541 /* BADDu */ 18542 GPR64Opnd, GPR64Opnd, GPR64Opnd, 18543 /* BAL */ 18544 brtarget, 18545 /* BALC */ 18546 brtarget26, 18547 /* BALC_MMR6 */ 18548 brtarget26_mm, 18549 /* BALIGN */ 18550 GPR32Opnd, GPR32Opnd, uimm2, GPR32Opnd, 18551 /* BALIGN_MMR2 */ 18552 GPR32Opnd, GPR32Opnd, uimm2, GPR32Opnd, 18553 /* BBIT0 */ 18554 GPR64Opnd, uimm5_64_report_uimm6, brtarget, 18555 /* BBIT032 */ 18556 GPR64Opnd, uimm5_64, brtarget, 18557 /* BBIT1 */ 18558 GPR64Opnd, uimm5_64_report_uimm6, brtarget, 18559 /* BBIT132 */ 18560 GPR64Opnd, uimm5_64, brtarget, 18561 /* BC */ 18562 brtarget26, 18563 /* BC16_MMR6 */ 18564 brtarget10_mm, 18565 /* BC1EQZ */ 18566 FGR64Opnd, brtarget, 18567 /* BC1EQZC_MMR6 */ 18568 FGR64Opnd, brtarget_mm, 18569 /* BC1F */ 18570 FCCRegsOpnd, brtarget, 18571 /* BC1FL */ 18572 FCCRegsOpnd, brtarget, 18573 /* BC1F_MM */ 18574 FCCRegsOpnd, brtarget_mm, 18575 /* BC1NEZ */ 18576 FGR64Opnd, brtarget, 18577 /* BC1NEZC_MMR6 */ 18578 FGR64Opnd, brtarget_mm, 18579 /* BC1T */ 18580 FCCRegsOpnd, brtarget, 18581 /* BC1TL */ 18582 FCCRegsOpnd, brtarget, 18583 /* BC1T_MM */ 18584 FCCRegsOpnd, brtarget_mm, 18585 /* BC2EQZ */ 18586 COP2Opnd, brtarget, 18587 /* BC2EQZC_MMR6 */ 18588 COP2Opnd, brtarget_mm, 18589 /* BC2NEZ */ 18590 COP2Opnd, brtarget, 18591 /* BC2NEZC_MMR6 */ 18592 COP2Opnd, brtarget_mm, 18593 /* BCLRI_B */ 18594 MSA128BOpnd, MSA128BOpnd, vsplat_uimm3, 18595 /* BCLRI_D */ 18596 MSA128DOpnd, MSA128DOpnd, vsplat_uimm6, 18597 /* BCLRI_H */ 18598 MSA128HOpnd, MSA128HOpnd, vsplat_uimm4, 18599 /* BCLRI_W */ 18600 MSA128WOpnd, MSA128WOpnd, vsplat_uimm5, 18601 /* BCLR_B */ 18602 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, 18603 /* BCLR_D */ 18604 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 18605 /* BCLR_H */ 18606 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, 18607 /* BCLR_W */ 18608 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 18609 /* BC_MMR6 */ 18610 brtarget26_mm, 18611 /* BEQ */ 18612 GPR32Opnd, GPR32Opnd, brtarget, 18613 /* BEQ64 */ 18614 GPR64Opnd, GPR64Opnd, brtarget, 18615 /* BEQC */ 18616 GPR32Opnd, GPR32Opnd, brtarget, 18617 /* BEQC64 */ 18618 GPR64Opnd, GPR64Opnd, brtarget, 18619 /* BEQC_MMR6 */ 18620 GPR32Opnd, GPR32Opnd, brtarget_lsl2_mm, 18621 /* BEQL */ 18622 GPR32Opnd, GPR32Opnd, brtarget, 18623 /* BEQZ16_MM */ 18624 GPRMM16Opnd, brtarget7_mm, 18625 /* BEQZALC */ 18626 GPR32Opnd, brtarget, 18627 /* BEQZALC_MMR6 */ 18628 GPR32Opnd, brtarget_mm, 18629 /* BEQZC */ 18630 GPR32Opnd, brtarget21, 18631 /* BEQZC16_MMR6 */ 18632 GPRMM16Opnd, brtarget7_mm, 18633 /* BEQZC64 */ 18634 GPR64Opnd, brtarget21, 18635 /* BEQZC_MM */ 18636 GPR32Opnd, brtarget_mm, 18637 /* BEQZC_MMR6 */ 18638 GPR32Opnd, brtarget21_mm, 18639 /* BEQ_MM */ 18640 GPR32Opnd, GPR32Opnd, brtarget_mm, 18641 /* BGEC */ 18642 GPR32Opnd, GPR32Opnd, brtarget, 18643 /* BGEC64 */ 18644 GPR64Opnd, GPR64Opnd, brtarget, 18645 /* BGEC_MMR6 */ 18646 GPR32Opnd, GPR32Opnd, brtarget_lsl2_mm, 18647 /* BGEUC */ 18648 GPR32Opnd, GPR32Opnd, brtarget, 18649 /* BGEUC64 */ 18650 GPR64Opnd, GPR64Opnd, brtarget, 18651 /* BGEUC_MMR6 */ 18652 GPR32Opnd, GPR32Opnd, brtarget_lsl2_mm, 18653 /* BGEZ */ 18654 GPR32Opnd, brtarget, 18655 /* BGEZ64 */ 18656 GPR64Opnd, brtarget, 18657 /* BGEZAL */ 18658 GPR32Opnd, brtarget, 18659 /* BGEZALC */ 18660 GPR32Opnd, brtarget, 18661 /* BGEZALC_MMR6 */ 18662 GPR32Opnd, brtarget_mm, 18663 /* BGEZALL */ 18664 GPR32Opnd, brtarget, 18665 /* BGEZALS_MM */ 18666 GPR32Opnd, brtarget_mm, 18667 /* BGEZAL_MM */ 18668 GPR32Opnd, brtarget_mm, 18669 /* BGEZC */ 18670 GPR32Opnd, brtarget, 18671 /* BGEZC64 */ 18672 GPR64Opnd, brtarget, 18673 /* BGEZC_MMR6 */ 18674 GPR32Opnd, brtarget_lsl2_mm, 18675 /* BGEZL */ 18676 GPR32Opnd, brtarget, 18677 /* BGEZ_MM */ 18678 GPR32Opnd, brtarget_mm, 18679 /* BGTZ */ 18680 GPR32Opnd, brtarget, 18681 /* BGTZ64 */ 18682 GPR64Opnd, brtarget, 18683 /* BGTZALC */ 18684 GPR32Opnd, brtarget, 18685 /* BGTZALC_MMR6 */ 18686 GPR32Opnd, brtarget_mm, 18687 /* BGTZC */ 18688 GPR32Opnd, brtarget, 18689 /* BGTZC64 */ 18690 GPR64Opnd, brtarget, 18691 /* BGTZC_MMR6 */ 18692 GPR32Opnd, brtarget_lsl2_mm, 18693 /* BGTZL */ 18694 GPR32Opnd, brtarget, 18695 /* BGTZ_MM */ 18696 GPR32Opnd, brtarget_mm, 18697 /* BINSLI_B */ 18698 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, vsplat_uimm3, 18699 /* BINSLI_D */ 18700 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, vsplat_uimm6, 18701 /* BINSLI_H */ 18702 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, vsplat_uimm4, 18703 /* BINSLI_W */ 18704 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, vsplat_uimm5, 18705 /* BINSL_B */ 18706 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, 18707 /* BINSL_D */ 18708 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 18709 /* BINSL_H */ 18710 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, 18711 /* BINSL_W */ 18712 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 18713 /* BINSRI_B */ 18714 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, vsplat_uimm3, 18715 /* BINSRI_D */ 18716 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, vsplat_uimm6, 18717 /* BINSRI_H */ 18718 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, vsplat_uimm4, 18719 /* BINSRI_W */ 18720 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, vsplat_uimm5, 18721 /* BINSR_B */ 18722 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, 18723 /* BINSR_D */ 18724 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 18725 /* BINSR_H */ 18726 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, 18727 /* BINSR_W */ 18728 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 18729 /* BITREV */ 18730 GPR32Opnd, GPR32Opnd, 18731 /* BITREV_MM */ 18732 GPR32Opnd, GPR32Opnd, 18733 /* BITSWAP */ 18734 GPR32Opnd, GPR32Opnd, 18735 /* BITSWAP_MMR6 */ 18736 GPR32Opnd, GPR32Opnd, 18737 /* BLEZ */ 18738 GPR32Opnd, brtarget, 18739 /* BLEZ64 */ 18740 GPR64Opnd, brtarget, 18741 /* BLEZALC */ 18742 GPR32Opnd, brtarget, 18743 /* BLEZALC_MMR6 */ 18744 GPR32Opnd, brtarget_mm, 18745 /* BLEZC */ 18746 GPR32Opnd, brtarget, 18747 /* BLEZC64 */ 18748 GPR64Opnd, brtarget, 18749 /* BLEZC_MMR6 */ 18750 GPR32Opnd, brtarget_lsl2_mm, 18751 /* BLEZL */ 18752 GPR32Opnd, brtarget, 18753 /* BLEZ_MM */ 18754 GPR32Opnd, brtarget_mm, 18755 /* BLTC */ 18756 GPR32Opnd, GPR32Opnd, brtarget, 18757 /* BLTC64 */ 18758 GPR64Opnd, GPR64Opnd, brtarget, 18759 /* BLTC_MMR6 */ 18760 GPR32Opnd, GPR32Opnd, brtarget_lsl2_mm, 18761 /* BLTUC */ 18762 GPR32Opnd, GPR32Opnd, brtarget, 18763 /* BLTUC64 */ 18764 GPR64Opnd, GPR64Opnd, brtarget, 18765 /* BLTUC_MMR6 */ 18766 GPR32Opnd, GPR32Opnd, brtarget_lsl2_mm, 18767 /* BLTZ */ 18768 GPR32Opnd, brtarget, 18769 /* BLTZ64 */ 18770 GPR64Opnd, brtarget, 18771 /* BLTZAL */ 18772 GPR32Opnd, brtarget, 18773 /* BLTZALC */ 18774 GPR32Opnd, brtarget, 18775 /* BLTZALC_MMR6 */ 18776 GPR32Opnd, brtarget_mm, 18777 /* BLTZALL */ 18778 GPR32Opnd, brtarget, 18779 /* BLTZALS_MM */ 18780 GPR32Opnd, brtarget_mm, 18781 /* BLTZAL_MM */ 18782 GPR32Opnd, brtarget_mm, 18783 /* BLTZC */ 18784 GPR32Opnd, brtarget, 18785 /* BLTZC64 */ 18786 GPR64Opnd, brtarget, 18787 /* BLTZC_MMR6 */ 18788 GPR32Opnd, brtarget_lsl2_mm, 18789 /* BLTZL */ 18790 GPR32Opnd, brtarget, 18791 /* BLTZ_MM */ 18792 GPR32Opnd, brtarget_mm, 18793 /* BMNZI_B */ 18794 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, vsplat_uimm8, 18795 /* BMNZ_V */ 18796 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, 18797 /* BMZI_B */ 18798 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, vsplat_uimm8, 18799 /* BMZ_V */ 18800 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, 18801 /* BNE */ 18802 GPR32Opnd, GPR32Opnd, brtarget, 18803 /* BNE64 */ 18804 GPR64Opnd, GPR64Opnd, brtarget, 18805 /* BNEC */ 18806 GPR32Opnd, GPR32Opnd, brtarget, 18807 /* BNEC64 */ 18808 GPR64Opnd, GPR64Opnd, brtarget, 18809 /* BNEC_MMR6 */ 18810 GPR32Opnd, GPR32Opnd, brtarget_lsl2_mm, 18811 /* BNEGI_B */ 18812 MSA128BOpnd, MSA128BOpnd, vsplat_uimm3, 18813 /* BNEGI_D */ 18814 MSA128DOpnd, MSA128DOpnd, vsplat_uimm6, 18815 /* BNEGI_H */ 18816 MSA128HOpnd, MSA128HOpnd, vsplat_uimm4, 18817 /* BNEGI_W */ 18818 MSA128WOpnd, MSA128WOpnd, vsplat_uimm5, 18819 /* BNEG_B */ 18820 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, 18821 /* BNEG_D */ 18822 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 18823 /* BNEG_H */ 18824 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, 18825 /* BNEG_W */ 18826 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 18827 /* BNEL */ 18828 GPR32Opnd, GPR32Opnd, brtarget, 18829 /* BNEZ16_MM */ 18830 GPRMM16Opnd, brtarget7_mm, 18831 /* BNEZALC */ 18832 GPR32Opnd, brtarget, 18833 /* BNEZALC_MMR6 */ 18834 GPR32Opnd, brtarget_mm, 18835 /* BNEZC */ 18836 GPR32Opnd, brtarget21, 18837 /* BNEZC16_MMR6 */ 18838 GPRMM16Opnd, brtarget7_mm, 18839 /* BNEZC64 */ 18840 GPR64Opnd, brtarget21, 18841 /* BNEZC_MM */ 18842 GPR32Opnd, brtarget_mm, 18843 /* BNEZC_MMR6 */ 18844 GPR32Opnd, brtarget21_mm, 18845 /* BNE_MM */ 18846 GPR32Opnd, GPR32Opnd, brtarget_mm, 18847 /* BNVC */ 18848 GPR32Opnd, GPR32Opnd, brtarget, 18849 /* BNVC_MMR6 */ 18850 GPR32Opnd, GPR32Opnd, brtargetr6, 18851 /* BNZ_B */ 18852 MSA128BOpnd, brtarget, 18853 /* BNZ_D */ 18854 MSA128DOpnd, brtarget, 18855 /* BNZ_H */ 18856 MSA128HOpnd, brtarget, 18857 /* BNZ_V */ 18858 MSA128BOpnd, brtarget, 18859 /* BNZ_W */ 18860 MSA128WOpnd, brtarget, 18861 /* BOVC */ 18862 GPR32Opnd, GPR32Opnd, brtarget, 18863 /* BOVC_MMR6 */ 18864 GPR32Opnd, GPR32Opnd, brtargetr6, 18865 /* BPOSGE32 */ 18866 brtarget, 18867 /* BPOSGE32C_MMR3 */ 18868 brtarget1SImm16, 18869 /* BPOSGE32_MM */ 18870 brtarget_mm, 18871 /* BREAK */ 18872 uimm10, uimm10, 18873 /* BREAK16_MM */ 18874 uimm4, 18875 /* BREAK16_MMR6 */ 18876 uimm4, 18877 /* BREAK_MM */ 18878 uimm10, uimm10, 18879 /* BREAK_MMR6 */ 18880 uimm10, uimm10, 18881 /* BSELI_B */ 18882 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, vsplat_uimm8, 18883 /* BSEL_V */ 18884 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, 18885 /* BSETI_B */ 18886 MSA128BOpnd, MSA128BOpnd, vsplat_uimm3, 18887 /* BSETI_D */ 18888 MSA128DOpnd, MSA128DOpnd, vsplat_uimm6, 18889 /* BSETI_H */ 18890 MSA128HOpnd, MSA128HOpnd, vsplat_uimm4, 18891 /* BSETI_W */ 18892 MSA128WOpnd, MSA128WOpnd, vsplat_uimm5, 18893 /* BSET_B */ 18894 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, 18895 /* BSET_D */ 18896 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 18897 /* BSET_H */ 18898 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, 18899 /* BSET_W */ 18900 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 18901 /* BZ_B */ 18902 MSA128BOpnd, brtarget, 18903 /* BZ_D */ 18904 MSA128DOpnd, brtarget, 18905 /* BZ_H */ 18906 MSA128HOpnd, brtarget, 18907 /* BZ_V */ 18908 MSA128BOpnd, brtarget, 18909 /* BZ_W */ 18910 MSA128WOpnd, brtarget, 18911 /* BeqzRxImm16 */ 18912 CPU16Regs, brtarget, 18913 /* BeqzRxImmX16 */ 18914 CPU16Regs, brtarget, 18915 /* Bimm16 */ 18916 brtarget, 18917 /* BimmX16 */ 18918 brtarget, 18919 /* BnezRxImm16 */ 18920 CPU16Regs, brtarget, 18921 /* BnezRxImmX16 */ 18922 CPU16Regs, brtarget, 18923 /* Break16 */ 18924 /* Bteqz16 */ 18925 simm16, 18926 /* BteqzX16 */ 18927 simm16, 18928 /* Btnez16 */ 18929 simm16, 18930 /* BtnezX16 */ 18931 simm16, 18932 /* CACHE */ 18933 -1, simm16, uimm5, 18934 /* CACHEE */ 18935 -1, simm9, uimm5, 18936 /* CACHEE_MM */ 18937 -1, simm9, uimm5, 18938 /* CACHE_MM */ 18939 -1, simm12, uimm5, 18940 /* CACHE_MMR6 */ 18941 -1, simm12, uimm5, 18942 /* CACHE_R6 */ 18943 -1, simm9, uimm5, 18944 /* CEIL_L_D64 */ 18945 FGR64Opnd, FGR64Opnd, 18946 /* CEIL_L_D_MMR6 */ 18947 FGR64Opnd, FGR64Opnd, 18948 /* CEIL_L_S */ 18949 FGR64Opnd, FGR32Opnd, 18950 /* CEIL_L_S_MMR6 */ 18951 FGR64Opnd, FGR32Opnd, 18952 /* CEIL_W_D32 */ 18953 FGR32Opnd, AFGR64Opnd, 18954 /* CEIL_W_D64 */ 18955 FGR32Opnd, FGR64Opnd, 18956 /* CEIL_W_D_MMR6 */ 18957 FGR32Opnd, AFGR64Opnd, 18958 /* CEIL_W_MM */ 18959 FGR32Opnd, AFGR64Opnd, 18960 /* CEIL_W_S */ 18961 FGR32Opnd, FGR32Opnd, 18962 /* CEIL_W_S_MM */ 18963 FGR32Opnd, FGR32Opnd, 18964 /* CEIL_W_S_MMR6 */ 18965 FGR32Opnd, FGR32Opnd, 18966 /* CEQI_B */ 18967 MSA128BOpnd, MSA128BOpnd, vsplat_simm5, 18968 /* CEQI_D */ 18969 MSA128DOpnd, MSA128DOpnd, vsplat_simm5, 18970 /* CEQI_H */ 18971 MSA128HOpnd, MSA128HOpnd, vsplat_simm5, 18972 /* CEQI_W */ 18973 MSA128WOpnd, MSA128WOpnd, vsplat_simm5, 18974 /* CEQ_B */ 18975 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, 18976 /* CEQ_D */ 18977 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 18978 /* CEQ_H */ 18979 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, 18980 /* CEQ_W */ 18981 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 18982 /* CFC1 */ 18983 GPR32Opnd, CCROpnd, 18984 /* CFC1_MM */ 18985 GPR32Opnd, CCROpnd, 18986 /* CFC2_MM */ 18987 GPR32Opnd, COP2Opnd, 18988 /* CFCMSA */ 18989 GPR32Opnd, MSA128CROpnd, 18990 /* CINS */ 18991 GPR64Opnd, GPR64Opnd, uimm5, uimm5, 18992 /* CINS32 */ 18993 GPR64Opnd, GPR64Opnd, uimm5, uimm5, 18994 /* CINS64_32 */ 18995 GPR64Opnd, GPR32Opnd, uimm5, uimm5, 18996 /* CINS_i32 */ 18997 GPR32Opnd, GPR32Opnd, uimm5, uimm5, 18998 /* CLASS_D */ 18999 FGR64Opnd, FGR64Opnd, 19000 /* CLASS_D_MMR6 */ 19001 FGR64Opnd, FGR64Opnd, 19002 /* CLASS_S */ 19003 FGR32Opnd, FGR32Opnd, 19004 /* CLASS_S_MMR6 */ 19005 FGR32Opnd, FGR32Opnd, 19006 /* CLEI_S_B */ 19007 MSA128BOpnd, MSA128BOpnd, vsplat_simm5, 19008 /* CLEI_S_D */ 19009 MSA128DOpnd, MSA128DOpnd, vsplat_simm5, 19010 /* CLEI_S_H */ 19011 MSA128HOpnd, MSA128HOpnd, vsplat_simm5, 19012 /* CLEI_S_W */ 19013 MSA128WOpnd, MSA128WOpnd, vsplat_simm5, 19014 /* CLEI_U_B */ 19015 MSA128BOpnd, MSA128BOpnd, vsplat_uimm5, 19016 /* CLEI_U_D */ 19017 MSA128DOpnd, MSA128DOpnd, vsplat_uimm5, 19018 /* CLEI_U_H */ 19019 MSA128HOpnd, MSA128HOpnd, vsplat_uimm5, 19020 /* CLEI_U_W */ 19021 MSA128WOpnd, MSA128WOpnd, vsplat_uimm5, 19022 /* CLE_S_B */ 19023 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, 19024 /* CLE_S_D */ 19025 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 19026 /* CLE_S_H */ 19027 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, 19028 /* CLE_S_W */ 19029 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 19030 /* CLE_U_B */ 19031 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, 19032 /* CLE_U_D */ 19033 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 19034 /* CLE_U_H */ 19035 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, 19036 /* CLE_U_W */ 19037 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 19038 /* CLO */ 19039 GPR32Opnd, GPR32Opnd, 19040 /* CLO_MM */ 19041 GPR32Opnd, GPR32Opnd, 19042 /* CLO_MMR6 */ 19043 GPR32Opnd, GPR32Opnd, 19044 /* CLO_R6 */ 19045 GPR32Opnd, GPR32Opnd, 19046 /* CLTI_S_B */ 19047 MSA128BOpnd, MSA128BOpnd, vsplat_simm5, 19048 /* CLTI_S_D */ 19049 MSA128DOpnd, MSA128DOpnd, vsplat_simm5, 19050 /* CLTI_S_H */ 19051 MSA128HOpnd, MSA128HOpnd, vsplat_simm5, 19052 /* CLTI_S_W */ 19053 MSA128WOpnd, MSA128WOpnd, vsplat_simm5, 19054 /* CLTI_U_B */ 19055 MSA128BOpnd, MSA128BOpnd, vsplat_uimm5, 19056 /* CLTI_U_D */ 19057 MSA128DOpnd, MSA128DOpnd, vsplat_uimm5, 19058 /* CLTI_U_H */ 19059 MSA128HOpnd, MSA128HOpnd, vsplat_uimm5, 19060 /* CLTI_U_W */ 19061 MSA128WOpnd, MSA128WOpnd, vsplat_uimm5, 19062 /* CLT_S_B */ 19063 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, 19064 /* CLT_S_D */ 19065 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 19066 /* CLT_S_H */ 19067 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, 19068 /* CLT_S_W */ 19069 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 19070 /* CLT_U_B */ 19071 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, 19072 /* CLT_U_D */ 19073 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 19074 /* CLT_U_H */ 19075 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, 19076 /* CLT_U_W */ 19077 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 19078 /* CLZ */ 19079 GPR32Opnd, GPR32Opnd, 19080 /* CLZ_MM */ 19081 GPR32Opnd, GPR32Opnd, 19082 /* CLZ_MMR6 */ 19083 GPR32Opnd, GPR32Opnd, 19084 /* CLZ_R6 */ 19085 GPR32Opnd, GPR32Opnd, 19086 /* CMPGDU_EQ_QB */ 19087 GPR32Opnd, DSPROpnd, DSPROpnd, 19088 /* CMPGDU_EQ_QB_MMR2 */ 19089 GPR32Opnd, DSPROpnd, DSPROpnd, 19090 /* CMPGDU_LE_QB */ 19091 GPR32Opnd, DSPROpnd, DSPROpnd, 19092 /* CMPGDU_LE_QB_MMR2 */ 19093 GPR32Opnd, DSPROpnd, DSPROpnd, 19094 /* CMPGDU_LT_QB */ 19095 GPR32Opnd, DSPROpnd, DSPROpnd, 19096 /* CMPGDU_LT_QB_MMR2 */ 19097 GPR32Opnd, DSPROpnd, DSPROpnd, 19098 /* CMPGU_EQ_QB */ 19099 GPR32Opnd, DSPROpnd, DSPROpnd, 19100 /* CMPGU_EQ_QB_MM */ 19101 GPR32Opnd, DSPROpnd, DSPROpnd, 19102 /* CMPGU_LE_QB */ 19103 GPR32Opnd, DSPROpnd, DSPROpnd, 19104 /* CMPGU_LE_QB_MM */ 19105 GPR32Opnd, DSPROpnd, DSPROpnd, 19106 /* CMPGU_LT_QB */ 19107 GPR32Opnd, DSPROpnd, DSPROpnd, 19108 /* CMPGU_LT_QB_MM */ 19109 GPR32Opnd, DSPROpnd, DSPROpnd, 19110 /* CMPU_EQ_QB */ 19111 DSPROpnd, DSPROpnd, 19112 /* CMPU_EQ_QB_MM */ 19113 DSPROpnd, DSPROpnd, 19114 /* CMPU_LE_QB */ 19115 DSPROpnd, DSPROpnd, 19116 /* CMPU_LE_QB_MM */ 19117 DSPROpnd, DSPROpnd, 19118 /* CMPU_LT_QB */ 19119 DSPROpnd, DSPROpnd, 19120 /* CMPU_LT_QB_MM */ 19121 DSPROpnd, DSPROpnd, 19122 /* CMP_AF_D_MMR6 */ 19123 FGRCCOpnd, FGR64Opnd, FGR64Opnd, 19124 /* CMP_AF_S_MMR6 */ 19125 FGRCCOpnd, FGR32Opnd, FGR32Opnd, 19126 /* CMP_EQ_D */ 19127 FGRCCOpnd, FGR64Opnd, FGR64Opnd, 19128 /* CMP_EQ_D_MMR6 */ 19129 FGRCCOpnd, FGR64Opnd, FGR64Opnd, 19130 /* CMP_EQ_PH */ 19131 DSPROpnd, DSPROpnd, 19132 /* CMP_EQ_PH_MM */ 19133 DSPROpnd, DSPROpnd, 19134 /* CMP_EQ_S */ 19135 FGRCCOpnd, FGR32Opnd, FGR32Opnd, 19136 /* CMP_EQ_S_MMR6 */ 19137 FGRCCOpnd, FGR32Opnd, FGR32Opnd, 19138 /* CMP_F_D */ 19139 FGRCCOpnd, FGR64Opnd, FGR64Opnd, 19140 /* CMP_F_S */ 19141 FGRCCOpnd, FGR32Opnd, FGR32Opnd, 19142 /* CMP_LE_D */ 19143 FGRCCOpnd, FGR64Opnd, FGR64Opnd, 19144 /* CMP_LE_D_MMR6 */ 19145 FGRCCOpnd, FGR64Opnd, FGR64Opnd, 19146 /* CMP_LE_PH */ 19147 DSPROpnd, DSPROpnd, 19148 /* CMP_LE_PH_MM */ 19149 DSPROpnd, DSPROpnd, 19150 /* CMP_LE_S */ 19151 FGRCCOpnd, FGR32Opnd, FGR32Opnd, 19152 /* CMP_LE_S_MMR6 */ 19153 FGRCCOpnd, FGR32Opnd, FGR32Opnd, 19154 /* CMP_LT_D */ 19155 FGRCCOpnd, FGR64Opnd, FGR64Opnd, 19156 /* CMP_LT_D_MMR6 */ 19157 FGRCCOpnd, FGR64Opnd, FGR64Opnd, 19158 /* CMP_LT_PH */ 19159 DSPROpnd, DSPROpnd, 19160 /* CMP_LT_PH_MM */ 19161 DSPROpnd, DSPROpnd, 19162 /* CMP_LT_S */ 19163 FGRCCOpnd, FGR32Opnd, FGR32Opnd, 19164 /* CMP_LT_S_MMR6 */ 19165 FGRCCOpnd, FGR32Opnd, FGR32Opnd, 19166 /* CMP_SAF_D */ 19167 FGRCCOpnd, FGR64Opnd, FGR64Opnd, 19168 /* CMP_SAF_D_MMR6 */ 19169 FGRCCOpnd, FGR64Opnd, FGR64Opnd, 19170 /* CMP_SAF_S */ 19171 FGRCCOpnd, FGR32Opnd, FGR32Opnd, 19172 /* CMP_SAF_S_MMR6 */ 19173 FGRCCOpnd, FGR32Opnd, FGR32Opnd, 19174 /* CMP_SEQ_D */ 19175 FGRCCOpnd, FGR64Opnd, FGR64Opnd, 19176 /* CMP_SEQ_D_MMR6 */ 19177 FGRCCOpnd, FGR64Opnd, FGR64Opnd, 19178 /* CMP_SEQ_S */ 19179 FGRCCOpnd, FGR32Opnd, FGR32Opnd, 19180 /* CMP_SEQ_S_MMR6 */ 19181 FGRCCOpnd, FGR32Opnd, FGR32Opnd, 19182 /* CMP_SLE_D */ 19183 FGRCCOpnd, FGR64Opnd, FGR64Opnd, 19184 /* CMP_SLE_D_MMR6 */ 19185 FGRCCOpnd, FGR64Opnd, FGR64Opnd, 19186 /* CMP_SLE_S */ 19187 FGRCCOpnd, FGR32Opnd, FGR32Opnd, 19188 /* CMP_SLE_S_MMR6 */ 19189 FGRCCOpnd, FGR32Opnd, FGR32Opnd, 19190 /* CMP_SLT_D */ 19191 FGRCCOpnd, FGR64Opnd, FGR64Opnd, 19192 /* CMP_SLT_D_MMR6 */ 19193 FGRCCOpnd, FGR64Opnd, FGR64Opnd, 19194 /* CMP_SLT_S */ 19195 FGRCCOpnd, FGR32Opnd, FGR32Opnd, 19196 /* CMP_SLT_S_MMR6 */ 19197 FGRCCOpnd, FGR32Opnd, FGR32Opnd, 19198 /* CMP_SUEQ_D */ 19199 FGRCCOpnd, FGR64Opnd, FGR64Opnd, 19200 /* CMP_SUEQ_D_MMR6 */ 19201 FGRCCOpnd, FGR64Opnd, FGR64Opnd, 19202 /* CMP_SUEQ_S */ 19203 FGRCCOpnd, FGR32Opnd, FGR32Opnd, 19204 /* CMP_SUEQ_S_MMR6 */ 19205 FGRCCOpnd, FGR32Opnd, FGR32Opnd, 19206 /* CMP_SULE_D */ 19207 FGRCCOpnd, FGR64Opnd, FGR64Opnd, 19208 /* CMP_SULE_D_MMR6 */ 19209 FGRCCOpnd, FGR64Opnd, FGR64Opnd, 19210 /* CMP_SULE_S */ 19211 FGRCCOpnd, FGR32Opnd, FGR32Opnd, 19212 /* CMP_SULE_S_MMR6 */ 19213 FGRCCOpnd, FGR32Opnd, FGR32Opnd, 19214 /* CMP_SULT_D */ 19215 FGRCCOpnd, FGR64Opnd, FGR64Opnd, 19216 /* CMP_SULT_D_MMR6 */ 19217 FGRCCOpnd, FGR64Opnd, FGR64Opnd, 19218 /* CMP_SULT_S */ 19219 FGRCCOpnd, FGR32Opnd, FGR32Opnd, 19220 /* CMP_SULT_S_MMR6 */ 19221 FGRCCOpnd, FGR32Opnd, FGR32Opnd, 19222 /* CMP_SUN_D */ 19223 FGRCCOpnd, FGR64Opnd, FGR64Opnd, 19224 /* CMP_SUN_D_MMR6 */ 19225 FGRCCOpnd, FGR64Opnd, FGR64Opnd, 19226 /* CMP_SUN_S */ 19227 FGRCCOpnd, FGR32Opnd, FGR32Opnd, 19228 /* CMP_SUN_S_MMR6 */ 19229 FGRCCOpnd, FGR32Opnd, FGR32Opnd, 19230 /* CMP_UEQ_D */ 19231 FGRCCOpnd, FGR64Opnd, FGR64Opnd, 19232 /* CMP_UEQ_D_MMR6 */ 19233 FGRCCOpnd, FGR64Opnd, FGR64Opnd, 19234 /* CMP_UEQ_S */ 19235 FGRCCOpnd, FGR32Opnd, FGR32Opnd, 19236 /* CMP_UEQ_S_MMR6 */ 19237 FGRCCOpnd, FGR32Opnd, FGR32Opnd, 19238 /* CMP_ULE_D */ 19239 FGRCCOpnd, FGR64Opnd, FGR64Opnd, 19240 /* CMP_ULE_D_MMR6 */ 19241 FGRCCOpnd, FGR64Opnd, FGR64Opnd, 19242 /* CMP_ULE_S */ 19243 FGRCCOpnd, FGR32Opnd, FGR32Opnd, 19244 /* CMP_ULE_S_MMR6 */ 19245 FGRCCOpnd, FGR32Opnd, FGR32Opnd, 19246 /* CMP_ULT_D */ 19247 FGRCCOpnd, FGR64Opnd, FGR64Opnd, 19248 /* CMP_ULT_D_MMR6 */ 19249 FGRCCOpnd, FGR64Opnd, FGR64Opnd, 19250 /* CMP_ULT_S */ 19251 FGRCCOpnd, FGR32Opnd, FGR32Opnd, 19252 /* CMP_ULT_S_MMR6 */ 19253 FGRCCOpnd, FGR32Opnd, FGR32Opnd, 19254 /* CMP_UN_D */ 19255 FGRCCOpnd, FGR64Opnd, FGR64Opnd, 19256 /* CMP_UN_D_MMR6 */ 19257 FGRCCOpnd, FGR64Opnd, FGR64Opnd, 19258 /* CMP_UN_S */ 19259 FGRCCOpnd, FGR32Opnd, FGR32Opnd, 19260 /* CMP_UN_S_MMR6 */ 19261 FGRCCOpnd, FGR32Opnd, FGR32Opnd, 19262 /* COPY_S_B */ 19263 GPR32Opnd, MSA128BOpnd, uimm4_ptr, 19264 /* COPY_S_D */ 19265 GPR64Opnd, MSA128DOpnd, uimm1_ptr, 19266 /* COPY_S_H */ 19267 GPR32Opnd, MSA128HOpnd, uimm3_ptr, 19268 /* COPY_S_W */ 19269 GPR32Opnd, MSA128WOpnd, uimm2_ptr, 19270 /* COPY_U_B */ 19271 GPR32Opnd, MSA128BOpnd, uimm4_ptr, 19272 /* COPY_U_H */ 19273 GPR32Opnd, MSA128HOpnd, uimm3_ptr, 19274 /* COPY_U_W */ 19275 GPR32Opnd, MSA128WOpnd, uimm2_ptr, 19276 /* CRC32B */ 19277 GPR32Opnd, GPR32Opnd, GPR32Opnd, 19278 /* CRC32CB */ 19279 GPR32Opnd, GPR32Opnd, GPR32Opnd, 19280 /* CRC32CD */ 19281 GPR32Opnd, GPR32Opnd, GPR32Opnd, 19282 /* CRC32CH */ 19283 GPR32Opnd, GPR32Opnd, GPR32Opnd, 19284 /* CRC32CW */ 19285 GPR32Opnd, GPR32Opnd, GPR32Opnd, 19286 /* CRC32D */ 19287 GPR32Opnd, GPR32Opnd, GPR32Opnd, 19288 /* CRC32H */ 19289 GPR32Opnd, GPR32Opnd, GPR32Opnd, 19290 /* CRC32W */ 19291 GPR32Opnd, GPR32Opnd, GPR32Opnd, 19292 /* CTC1 */ 19293 CCROpnd, GPR32Opnd, 19294 /* CTC1_MM */ 19295 CCROpnd, GPR32Opnd, 19296 /* CTC2_MM */ 19297 COP2Opnd, GPR32Opnd, 19298 /* CTCMSA */ 19299 MSA128CROpnd, GPR32Opnd, 19300 /* CVT_D32_S */ 19301 AFGR64Opnd, FGR32Opnd, 19302 /* CVT_D32_S_MM */ 19303 AFGR64Opnd, FGR32Opnd, 19304 /* CVT_D32_W */ 19305 AFGR64Opnd, FGR32Opnd, 19306 /* CVT_D32_W_MM */ 19307 AFGR64Opnd, FGR32Opnd, 19308 /* CVT_D64_L */ 19309 FGR64Opnd, FGR64Opnd, 19310 /* CVT_D64_S */ 19311 FGR64Opnd, FGR32Opnd, 19312 /* CVT_D64_S_MM */ 19313 FGR64Opnd, FGR32Opnd, 19314 /* CVT_D64_W */ 19315 FGR64Opnd, FGR32Opnd, 19316 /* CVT_D64_W_MM */ 19317 FGR64Opnd, FGR32Opnd, 19318 /* CVT_D_L_MMR6 */ 19319 FGR64Opnd, FGR64Opnd, 19320 /* CVT_L_D64 */ 19321 FGR64Opnd, FGR64Opnd, 19322 /* CVT_L_D64_MM */ 19323 FGR64Opnd, FGR64Opnd, 19324 /* CVT_L_D_MMR6 */ 19325 FGR64Opnd, FGR64Opnd, 19326 /* CVT_L_S */ 19327 FGR64Opnd, FGR32Opnd, 19328 /* CVT_L_S_MM */ 19329 FGR64Opnd, FGR32Opnd, 19330 /* CVT_L_S_MMR6 */ 19331 FGR64Opnd, FGR32Opnd, 19332 /* CVT_PS_PW64 */ 19333 FGR64Opnd, FGR64Opnd, 19334 /* CVT_PS_S64 */ 19335 FGR64Opnd, FGR32Opnd, FGR32Opnd, 19336 /* CVT_PW_PS64 */ 19337 FGR64Opnd, FGR64Opnd, 19338 /* CVT_S_D32 */ 19339 FGR32Opnd, AFGR64Opnd, 19340 /* CVT_S_D32_MM */ 19341 FGR32Opnd, AFGR64Opnd, 19342 /* CVT_S_D64 */ 19343 FGR32Opnd, FGR64Opnd, 19344 /* CVT_S_D64_MM */ 19345 FGR32Opnd, FGR64Opnd, 19346 /* CVT_S_L */ 19347 FGR32Opnd, FGR64Opnd, 19348 /* CVT_S_L_MMR6 */ 19349 FGR64Opnd, FGR32Opnd, 19350 /* CVT_S_PL64 */ 19351 FGR32Opnd, FGR64Opnd, 19352 /* CVT_S_PU64 */ 19353 FGR32Opnd, FGR64Opnd, 19354 /* CVT_S_W */ 19355 FGR32Opnd, FGR32Opnd, 19356 /* CVT_S_W_MM */ 19357 FGR32Opnd, FGR32Opnd, 19358 /* CVT_S_W_MMR6 */ 19359 FGR32Opnd, FGR32Opnd, 19360 /* CVT_W_D32 */ 19361 FGR32Opnd, AFGR64Opnd, 19362 /* CVT_W_D32_MM */ 19363 FGR32Opnd, AFGR64Opnd, 19364 /* CVT_W_D64 */ 19365 FGR32Opnd, FGR64Opnd, 19366 /* CVT_W_D64_MM */ 19367 FGR32Opnd, FGR64Opnd, 19368 /* CVT_W_S */ 19369 FGR32Opnd, FGR32Opnd, 19370 /* CVT_W_S_MM */ 19371 FGR32Opnd, FGR32Opnd, 19372 /* CVT_W_S_MMR6 */ 19373 FGR32Opnd, FGR32Opnd, 19374 /* C_EQ_D32 */ 19375 FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, 19376 /* C_EQ_D32_MM */ 19377 FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, 19378 /* C_EQ_D64 */ 19379 FCCRegsOpnd, FGR64Opnd, FGR64Opnd, 19380 /* C_EQ_D64_MM */ 19381 FCCRegsOpnd, FGR64Opnd, FGR64Opnd, 19382 /* C_EQ_S */ 19383 FCCRegsOpnd, FGR32Opnd, FGR32Opnd, 19384 /* C_EQ_S_MM */ 19385 FCCRegsOpnd, FGR32Opnd, FGR32Opnd, 19386 /* C_F_D32 */ 19387 FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, 19388 /* C_F_D32_MM */ 19389 FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, 19390 /* C_F_D64 */ 19391 FCCRegsOpnd, FGR64Opnd, FGR64Opnd, 19392 /* C_F_D64_MM */ 19393 FCCRegsOpnd, FGR64Opnd, FGR64Opnd, 19394 /* C_F_S */ 19395 FCCRegsOpnd, FGR32Opnd, FGR32Opnd, 19396 /* C_F_S_MM */ 19397 FCCRegsOpnd, FGR32Opnd, FGR32Opnd, 19398 /* C_LE_D32 */ 19399 FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, 19400 /* C_LE_D32_MM */ 19401 FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, 19402 /* C_LE_D64 */ 19403 FCCRegsOpnd, FGR64Opnd, FGR64Opnd, 19404 /* C_LE_D64_MM */ 19405 FCCRegsOpnd, FGR64Opnd, FGR64Opnd, 19406 /* C_LE_S */ 19407 FCCRegsOpnd, FGR32Opnd, FGR32Opnd, 19408 /* C_LE_S_MM */ 19409 FCCRegsOpnd, FGR32Opnd, FGR32Opnd, 19410 /* C_LT_D32 */ 19411 FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, 19412 /* C_LT_D32_MM */ 19413 FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, 19414 /* C_LT_D64 */ 19415 FCCRegsOpnd, FGR64Opnd, FGR64Opnd, 19416 /* C_LT_D64_MM */ 19417 FCCRegsOpnd, FGR64Opnd, FGR64Opnd, 19418 /* C_LT_S */ 19419 FCCRegsOpnd, FGR32Opnd, FGR32Opnd, 19420 /* C_LT_S_MM */ 19421 FCCRegsOpnd, FGR32Opnd, FGR32Opnd, 19422 /* C_NGE_D32 */ 19423 FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, 19424 /* C_NGE_D32_MM */ 19425 FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, 19426 /* C_NGE_D64 */ 19427 FCCRegsOpnd, FGR64Opnd, FGR64Opnd, 19428 /* C_NGE_D64_MM */ 19429 FCCRegsOpnd, FGR64Opnd, FGR64Opnd, 19430 /* C_NGE_S */ 19431 FCCRegsOpnd, FGR32Opnd, FGR32Opnd, 19432 /* C_NGE_S_MM */ 19433 FCCRegsOpnd, FGR32Opnd, FGR32Opnd, 19434 /* C_NGLE_D32 */ 19435 FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, 19436 /* C_NGLE_D32_MM */ 19437 FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, 19438 /* C_NGLE_D64 */ 19439 FCCRegsOpnd, FGR64Opnd, FGR64Opnd, 19440 /* C_NGLE_D64_MM */ 19441 FCCRegsOpnd, FGR64Opnd, FGR64Opnd, 19442 /* C_NGLE_S */ 19443 FCCRegsOpnd, FGR32Opnd, FGR32Opnd, 19444 /* C_NGLE_S_MM */ 19445 FCCRegsOpnd, FGR32Opnd, FGR32Opnd, 19446 /* C_NGL_D32 */ 19447 FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, 19448 /* C_NGL_D32_MM */ 19449 FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, 19450 /* C_NGL_D64 */ 19451 FCCRegsOpnd, FGR64Opnd, FGR64Opnd, 19452 /* C_NGL_D64_MM */ 19453 FCCRegsOpnd, FGR64Opnd, FGR64Opnd, 19454 /* C_NGL_S */ 19455 FCCRegsOpnd, FGR32Opnd, FGR32Opnd, 19456 /* C_NGL_S_MM */ 19457 FCCRegsOpnd, FGR32Opnd, FGR32Opnd, 19458 /* C_NGT_D32 */ 19459 FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, 19460 /* C_NGT_D32_MM */ 19461 FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, 19462 /* C_NGT_D64 */ 19463 FCCRegsOpnd, FGR64Opnd, FGR64Opnd, 19464 /* C_NGT_D64_MM */ 19465 FCCRegsOpnd, FGR64Opnd, FGR64Opnd, 19466 /* C_NGT_S */ 19467 FCCRegsOpnd, FGR32Opnd, FGR32Opnd, 19468 /* C_NGT_S_MM */ 19469 FCCRegsOpnd, FGR32Opnd, FGR32Opnd, 19470 /* C_OLE_D32 */ 19471 FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, 19472 /* C_OLE_D32_MM */ 19473 FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, 19474 /* C_OLE_D64 */ 19475 FCCRegsOpnd, FGR64Opnd, FGR64Opnd, 19476 /* C_OLE_D64_MM */ 19477 FCCRegsOpnd, FGR64Opnd, FGR64Opnd, 19478 /* C_OLE_S */ 19479 FCCRegsOpnd, FGR32Opnd, FGR32Opnd, 19480 /* C_OLE_S_MM */ 19481 FCCRegsOpnd, FGR32Opnd, FGR32Opnd, 19482 /* C_OLT_D32 */ 19483 FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, 19484 /* C_OLT_D32_MM */ 19485 FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, 19486 /* C_OLT_D64 */ 19487 FCCRegsOpnd, FGR64Opnd, FGR64Opnd, 19488 /* C_OLT_D64_MM */ 19489 FCCRegsOpnd, FGR64Opnd, FGR64Opnd, 19490 /* C_OLT_S */ 19491 FCCRegsOpnd, FGR32Opnd, FGR32Opnd, 19492 /* C_OLT_S_MM */ 19493 FCCRegsOpnd, FGR32Opnd, FGR32Opnd, 19494 /* C_SEQ_D32 */ 19495 FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, 19496 /* C_SEQ_D32_MM */ 19497 FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, 19498 /* C_SEQ_D64 */ 19499 FCCRegsOpnd, FGR64Opnd, FGR64Opnd, 19500 /* C_SEQ_D64_MM */ 19501 FCCRegsOpnd, FGR64Opnd, FGR64Opnd, 19502 /* C_SEQ_S */ 19503 FCCRegsOpnd, FGR32Opnd, FGR32Opnd, 19504 /* C_SEQ_S_MM */ 19505 FCCRegsOpnd, FGR32Opnd, FGR32Opnd, 19506 /* C_SF_D32 */ 19507 FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, 19508 /* C_SF_D32_MM */ 19509 FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, 19510 /* C_SF_D64 */ 19511 FCCRegsOpnd, FGR64Opnd, FGR64Opnd, 19512 /* C_SF_D64_MM */ 19513 FCCRegsOpnd, FGR64Opnd, FGR64Opnd, 19514 /* C_SF_S */ 19515 FCCRegsOpnd, FGR32Opnd, FGR32Opnd, 19516 /* C_SF_S_MM */ 19517 FCCRegsOpnd, FGR32Opnd, FGR32Opnd, 19518 /* C_UEQ_D32 */ 19519 FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, 19520 /* C_UEQ_D32_MM */ 19521 FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, 19522 /* C_UEQ_D64 */ 19523 FCCRegsOpnd, FGR64Opnd, FGR64Opnd, 19524 /* C_UEQ_D64_MM */ 19525 FCCRegsOpnd, FGR64Opnd, FGR64Opnd, 19526 /* C_UEQ_S */ 19527 FCCRegsOpnd, FGR32Opnd, FGR32Opnd, 19528 /* C_UEQ_S_MM */ 19529 FCCRegsOpnd, FGR32Opnd, FGR32Opnd, 19530 /* C_ULE_D32 */ 19531 FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, 19532 /* C_ULE_D32_MM */ 19533 FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, 19534 /* C_ULE_D64 */ 19535 FCCRegsOpnd, FGR64Opnd, FGR64Opnd, 19536 /* C_ULE_D64_MM */ 19537 FCCRegsOpnd, FGR64Opnd, FGR64Opnd, 19538 /* C_ULE_S */ 19539 FCCRegsOpnd, FGR32Opnd, FGR32Opnd, 19540 /* C_ULE_S_MM */ 19541 FCCRegsOpnd, FGR32Opnd, FGR32Opnd, 19542 /* C_ULT_D32 */ 19543 FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, 19544 /* C_ULT_D32_MM */ 19545 FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, 19546 /* C_ULT_D64 */ 19547 FCCRegsOpnd, FGR64Opnd, FGR64Opnd, 19548 /* C_ULT_D64_MM */ 19549 FCCRegsOpnd, FGR64Opnd, FGR64Opnd, 19550 /* C_ULT_S */ 19551 FCCRegsOpnd, FGR32Opnd, FGR32Opnd, 19552 /* C_ULT_S_MM */ 19553 FCCRegsOpnd, FGR32Opnd, FGR32Opnd, 19554 /* C_UN_D32 */ 19555 FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, 19556 /* C_UN_D32_MM */ 19557 FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, 19558 /* C_UN_D64 */ 19559 FCCRegsOpnd, FGR64Opnd, FGR64Opnd, 19560 /* C_UN_D64_MM */ 19561 FCCRegsOpnd, FGR64Opnd, FGR64Opnd, 19562 /* C_UN_S */ 19563 FCCRegsOpnd, FGR32Opnd, FGR32Opnd, 19564 /* C_UN_S_MM */ 19565 FCCRegsOpnd, FGR32Opnd, FGR32Opnd, 19566 /* CmpRxRy16 */ 19567 CPU16Regs, CPU16Regs, 19568 /* CmpiRxImm16 */ 19569 CPU16Regs, simm16, 19570 /* CmpiRxImmX16 */ 19571 CPU16Regs, simm16, 19572 /* DADD */ 19573 GPR64Opnd, GPR64Opnd, GPR64Opnd, 19574 /* DADDi */ 19575 GPR64Opnd, GPR64Opnd, simm16_64, 19576 /* DADDiu */ 19577 GPR64Opnd, GPR64Opnd, simm16_64, 19578 /* DADDu */ 19579 GPR64Opnd, GPR64Opnd, GPR64Opnd, 19580 /* DAHI */ 19581 GPR64Opnd, GPR64Opnd, uimm16_altrelaxed, 19582 /* DALIGN */ 19583 GPR64Opnd, GPR64Opnd, GPR64Opnd, uimm3, 19584 /* DATI */ 19585 GPR64Opnd, GPR64Opnd, uimm16_altrelaxed, 19586 /* DAUI */ 19587 GPR64Opnd, GPR64Opnd, uimm16, 19588 /* DBITSWAP */ 19589 GPR64Opnd, GPR64Opnd, 19590 /* DCLO */ 19591 GPR64Opnd, GPR64Opnd, 19592 /* DCLO_R6 */ 19593 GPR64Opnd, GPR64Opnd, 19594 /* DCLZ */ 19595 GPR64Opnd, GPR64Opnd, 19596 /* DCLZ_R6 */ 19597 GPR64Opnd, GPR64Opnd, 19598 /* DDIV */ 19599 GPR64Opnd, GPR64Opnd, GPR64Opnd, 19600 /* DDIVU */ 19601 GPR64Opnd, GPR64Opnd, GPR64Opnd, 19602 /* DERET */ 19603 /* DERET_MM */ 19604 /* DERET_MMR6 */ 19605 /* DEXT */ 19606 GPR64Opnd, GPR64Opnd, uimm5_report_uimm6, uimm5_plus1_report_uimm6, 19607 /* DEXT64_32 */ 19608 GPR64Opnd, GPR32Opnd, uimm5_report_uimm6, uimm5_plus1, 19609 /* DEXTM */ 19610 GPR64Opnd, GPR64Opnd, uimm5, uimm5_plus33, 19611 /* DEXTU */ 19612 GPR64Opnd, GPR64Opnd, uimm5_plus32, uimm5_plus1, 19613 /* DI */ 19614 GPR32Opnd, 19615 /* DINS */ 19616 GPR64Opnd, GPR64Opnd, uimm6, uimm5_inssize_plus1, GPR64Opnd, 19617 /* DINSM */ 19618 GPR64Opnd, GPR64Opnd, uimm5, uimm_range_2_64, GPR64Opnd, 19619 /* DINSU */ 19620 GPR64Opnd, GPR64Opnd, uimm5_plus32, uimm5_inssize_plus1, GPR64Opnd, 19621 /* DIV */ 19622 GPR32Opnd, GPR32Opnd, GPR32Opnd, 19623 /* DIVU */ 19624 GPR32Opnd, GPR32Opnd, GPR32Opnd, 19625 /* DIVU_MMR6 */ 19626 GPR32Opnd, GPR32Opnd, GPR32Opnd, 19627 /* DIV_MMR6 */ 19628 GPR32Opnd, GPR32Opnd, GPR32Opnd, 19629 /* DIV_S_B */ 19630 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, 19631 /* DIV_S_D */ 19632 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 19633 /* DIV_S_H */ 19634 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, 19635 /* DIV_S_W */ 19636 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 19637 /* DIV_U_B */ 19638 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, 19639 /* DIV_U_D */ 19640 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 19641 /* DIV_U_H */ 19642 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, 19643 /* DIV_U_W */ 19644 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 19645 /* DI_MM */ 19646 GPR32Opnd, 19647 /* DI_MMR6 */ 19648 GPR32Opnd, 19649 /* DLSA */ 19650 GPR64Opnd, GPR64Opnd, GPR64Opnd, uimm2_plus1, 19651 /* DLSA_R6 */ 19652 GPR64Opnd, GPR64Opnd, GPR64Opnd, uimm2_plus1, 19653 /* DMFC0 */ 19654 GPR64Opnd, COP0Opnd, uimm3, 19655 /* DMFC1 */ 19656 GPR64Opnd, FGR64Opnd, 19657 /* DMFC2 */ 19658 GPR64Opnd, COP2Opnd, uimm3, 19659 /* DMFC2_OCTEON */ 19660 GPR64Opnd, uimm16, 19661 /* DMFGC0 */ 19662 GPR64Opnd, COP0Opnd, uimm3, 19663 /* DMOD */ 19664 GPR64Opnd, GPR64Opnd, GPR64Opnd, 19665 /* DMODU */ 19666 GPR64Opnd, GPR64Opnd, GPR64Opnd, 19667 /* DMT */ 19668 GPR32Opnd, 19669 /* DMTC0 */ 19670 COP0Opnd, GPR64Opnd, uimm3, 19671 /* DMTC1 */ 19672 FGR64Opnd, GPR64Opnd, 19673 /* DMTC2 */ 19674 COP2Opnd, GPR64Opnd, uimm3, 19675 /* DMTC2_OCTEON */ 19676 GPR64Opnd, uimm16, 19677 /* DMTGC0 */ 19678 COP0Opnd, GPR64Opnd, uimm3, 19679 /* DMUH */ 19680 GPR64Opnd, GPR64Opnd, GPR64Opnd, 19681 /* DMUHU */ 19682 GPR64Opnd, GPR64Opnd, GPR64Opnd, 19683 /* DMUL */ 19684 GPR64Opnd, GPR64Opnd, GPR64Opnd, 19685 /* DMULT */ 19686 GPR64Opnd, GPR64Opnd, 19687 /* DMULTu */ 19688 GPR64Opnd, GPR64Opnd, 19689 /* DMULU */ 19690 GPR64Opnd, GPR64Opnd, GPR64Opnd, 19691 /* DMUL_R6 */ 19692 GPR64Opnd, GPR64Opnd, GPR64Opnd, 19693 /* DOTP_S_D */ 19694 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd, 19695 /* DOTP_S_H */ 19696 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd, 19697 /* DOTP_S_W */ 19698 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd, 19699 /* DOTP_U_D */ 19700 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd, 19701 /* DOTP_U_H */ 19702 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd, 19703 /* DOTP_U_W */ 19704 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd, 19705 /* DPADD_S_D */ 19706 MSA128DOpnd, MSA128DOpnd, MSA128WOpnd, MSA128WOpnd, 19707 /* DPADD_S_H */ 19708 MSA128HOpnd, MSA128HOpnd, MSA128BOpnd, MSA128BOpnd, 19709 /* DPADD_S_W */ 19710 MSA128WOpnd, MSA128WOpnd, MSA128HOpnd, MSA128HOpnd, 19711 /* DPADD_U_D */ 19712 MSA128DOpnd, MSA128DOpnd, MSA128WOpnd, MSA128WOpnd, 19713 /* DPADD_U_H */ 19714 MSA128HOpnd, MSA128HOpnd, MSA128BOpnd, MSA128BOpnd, 19715 /* DPADD_U_W */ 19716 MSA128WOpnd, MSA128WOpnd, MSA128HOpnd, MSA128HOpnd, 19717 /* DPAQX_SA_W_PH */ 19718 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, 19719 /* DPAQX_SA_W_PH_MMR2 */ 19720 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, 19721 /* DPAQX_S_W_PH */ 19722 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, 19723 /* DPAQX_S_W_PH_MMR2 */ 19724 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, 19725 /* DPAQ_SA_L_W */ 19726 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, 19727 /* DPAQ_SA_L_W_MM */ 19728 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, 19729 /* DPAQ_S_W_PH */ 19730 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, 19731 /* DPAQ_S_W_PH_MM */ 19732 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, 19733 /* DPAU_H_QBL */ 19734 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, 19735 /* DPAU_H_QBL_MM */ 19736 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, 19737 /* DPAU_H_QBR */ 19738 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, 19739 /* DPAU_H_QBR_MM */ 19740 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, 19741 /* DPAX_W_PH */ 19742 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, 19743 /* DPAX_W_PH_MMR2 */ 19744 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, 19745 /* DPA_W_PH */ 19746 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, 19747 /* DPA_W_PH_MMR2 */ 19748 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, 19749 /* DPOP */ 19750 GPR64Opnd, GPR64Opnd, 19751 /* DPSQX_SA_W_PH */ 19752 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, 19753 /* DPSQX_SA_W_PH_MMR2 */ 19754 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, 19755 /* DPSQX_S_W_PH */ 19756 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, 19757 /* DPSQX_S_W_PH_MMR2 */ 19758 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, 19759 /* DPSQ_SA_L_W */ 19760 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, 19761 /* DPSQ_SA_L_W_MM */ 19762 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, 19763 /* DPSQ_S_W_PH */ 19764 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, 19765 /* DPSQ_S_W_PH_MM */ 19766 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, 19767 /* DPSUB_S_D */ 19768 MSA128DOpnd, MSA128DOpnd, MSA128WOpnd, MSA128WOpnd, 19769 /* DPSUB_S_H */ 19770 MSA128HOpnd, MSA128HOpnd, MSA128BOpnd, MSA128BOpnd, 19771 /* DPSUB_S_W */ 19772 MSA128WOpnd, MSA128WOpnd, MSA128HOpnd, MSA128HOpnd, 19773 /* DPSUB_U_D */ 19774 MSA128DOpnd, MSA128DOpnd, MSA128WOpnd, MSA128WOpnd, 19775 /* DPSUB_U_H */ 19776 MSA128HOpnd, MSA128HOpnd, MSA128BOpnd, MSA128BOpnd, 19777 /* DPSUB_U_W */ 19778 MSA128WOpnd, MSA128WOpnd, MSA128HOpnd, MSA128HOpnd, 19779 /* DPSU_H_QBL */ 19780 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, 19781 /* DPSU_H_QBL_MM */ 19782 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, 19783 /* DPSU_H_QBR */ 19784 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, 19785 /* DPSU_H_QBR_MM */ 19786 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, 19787 /* DPSX_W_PH */ 19788 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, 19789 /* DPSX_W_PH_MMR2 */ 19790 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, 19791 /* DPS_W_PH */ 19792 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, 19793 /* DPS_W_PH_MMR2 */ 19794 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, 19795 /* DROTR */ 19796 GPR64Opnd, GPR64Opnd, uimm6, 19797 /* DROTR32 */ 19798 GPR64Opnd, GPR64Opnd, uimm5, 19799 /* DROTRV */ 19800 GPR64Opnd, GPR64Opnd, GPR32Opnd, 19801 /* DSBH */ 19802 GPR64Opnd, GPR64Opnd, 19803 /* DSDIV */ 19804 GPR64Opnd, GPR64Opnd, 19805 /* DSHD */ 19806 GPR64Opnd, GPR64Opnd, 19807 /* DSLL */ 19808 GPR64Opnd, GPR64Opnd, uimm6, 19809 /* DSLL32 */ 19810 GPR64Opnd, GPR64Opnd, uimm5, 19811 /* DSLL64_32 */ 19812 GPR64, GPR32, 19813 /* DSLLV */ 19814 GPR64Opnd, GPR64Opnd, GPR32Opnd, 19815 /* DSRA */ 19816 GPR64Opnd, GPR64Opnd, uimm6, 19817 /* DSRA32 */ 19818 GPR64Opnd, GPR64Opnd, uimm5, 19819 /* DSRAV */ 19820 GPR64Opnd, GPR64Opnd, GPR32Opnd, 19821 /* DSRL */ 19822 GPR64Opnd, GPR64Opnd, uimm6, 19823 /* DSRL32 */ 19824 GPR64Opnd, GPR64Opnd, uimm5, 19825 /* DSRLV */ 19826 GPR64Opnd, GPR64Opnd, GPR32Opnd, 19827 /* DSUB */ 19828 GPR64Opnd, GPR64Opnd, GPR64Opnd, 19829 /* DSUBu */ 19830 GPR64Opnd, GPR64Opnd, GPR64Opnd, 19831 /* DUDIV */ 19832 GPR64Opnd, GPR64Opnd, 19833 /* DVP */ 19834 GPR32Opnd, 19835 /* DVPE */ 19836 GPR32Opnd, 19837 /* DVP_MMR6 */ 19838 GPR32Opnd, 19839 /* DivRxRy16 */ 19840 CPU16Regs, CPU16Regs, 19841 /* DivuRxRy16 */ 19842 CPU16Regs, CPU16Regs, 19843 /* EHB */ 19844 /* EHB_MM */ 19845 /* EHB_MMR6 */ 19846 /* EI */ 19847 GPR32Opnd, 19848 /* EI_MM */ 19849 GPR32Opnd, 19850 /* EI_MMR6 */ 19851 GPR32Opnd, 19852 /* EMT */ 19853 GPR32Opnd, 19854 /* ERET */ 19855 /* ERETNC */ 19856 /* ERETNC_MMR6 */ 19857 /* ERET_MM */ 19858 /* ERET_MMR6 */ 19859 /* EVP */ 19860 GPR32Opnd, 19861 /* EVPE */ 19862 GPR32Opnd, 19863 /* EVP_MMR6 */ 19864 GPR32Opnd, 19865 /* EXT */ 19866 GPR32Opnd, GPR32Opnd, uimm5, uimm5_plus1, 19867 /* EXTP */ 19868 GPR32Opnd, ACC64DSPOpnd, uimm5, 19869 /* EXTPDP */ 19870 GPR32Opnd, ACC64DSPOpnd, uimm5, 19871 /* EXTPDPV */ 19872 GPR32Opnd, ACC64DSPOpnd, GPR32Opnd, 19873 /* EXTPDPV_MM */ 19874 GPR32Opnd, ACC64DSPOpnd, GPR32Opnd, 19875 /* EXTPDP_MM */ 19876 GPR32Opnd, ACC64DSPOpnd, uimm5, 19877 /* EXTPV */ 19878 GPR32Opnd, ACC64DSPOpnd, GPR32Opnd, 19879 /* EXTPV_MM */ 19880 GPR32Opnd, ACC64DSPOpnd, GPR32Opnd, 19881 /* EXTP_MM */ 19882 GPR32Opnd, ACC64DSPOpnd, uimm5, 19883 /* EXTRV_RS_W */ 19884 GPR32Opnd, ACC64DSPOpnd, GPR32Opnd, 19885 /* EXTRV_RS_W_MM */ 19886 GPR32Opnd, ACC64DSPOpnd, GPR32Opnd, 19887 /* EXTRV_R_W */ 19888 GPR32Opnd, ACC64DSPOpnd, GPR32Opnd, 19889 /* EXTRV_R_W_MM */ 19890 GPR32Opnd, ACC64DSPOpnd, GPR32Opnd, 19891 /* EXTRV_S_H */ 19892 GPR32Opnd, ACC64DSPOpnd, GPR32Opnd, 19893 /* EXTRV_S_H_MM */ 19894 GPR32Opnd, ACC64DSPOpnd, GPR32Opnd, 19895 /* EXTRV_W */ 19896 GPR32Opnd, ACC64DSPOpnd, GPR32Opnd, 19897 /* EXTRV_W_MM */ 19898 GPR32Opnd, ACC64DSPOpnd, GPR32Opnd, 19899 /* EXTR_RS_W */ 19900 GPR32Opnd, ACC64DSPOpnd, uimm5, 19901 /* EXTR_RS_W_MM */ 19902 GPR32Opnd, ACC64DSPOpnd, uimm5, 19903 /* EXTR_R_W */ 19904 GPR32Opnd, ACC64DSPOpnd, uimm5, 19905 /* EXTR_R_W_MM */ 19906 GPR32Opnd, ACC64DSPOpnd, uimm5, 19907 /* EXTR_S_H */ 19908 GPR32Opnd, ACC64DSPOpnd, uimm5, 19909 /* EXTR_S_H_MM */ 19910 GPR32Opnd, ACC64DSPOpnd, uimm5, 19911 /* EXTR_W */ 19912 GPR32Opnd, ACC64DSPOpnd, uimm5, 19913 /* EXTR_W_MM */ 19914 GPR32Opnd, ACC64DSPOpnd, uimm5, 19915 /* EXTS */ 19916 GPR64Opnd, GPR64Opnd, uimm5, uimm5, 19917 /* EXTS32 */ 19918 GPR64Opnd, GPR64Opnd, uimm5, uimm5, 19919 /* EXT_MM */ 19920 GPR32Opnd, GPR32Opnd, uimm5, uimm5_plus1, 19921 /* EXT_MMR6 */ 19922 GPR32Opnd, GPR32Opnd, uimm5, uimm5_plus1, 19923 /* FABS_D32 */ 19924 AFGR64Opnd, AFGR64Opnd, 19925 /* FABS_D32_MM */ 19926 AFGR64Opnd, AFGR64Opnd, 19927 /* FABS_D64 */ 19928 FGR64Opnd, FGR64Opnd, 19929 /* FABS_D64_MM */ 19930 FGR64Opnd, FGR64Opnd, 19931 /* FABS_S */ 19932 FGR32Opnd, FGR32Opnd, 19933 /* FABS_S_MM */ 19934 FGR32Opnd, FGR32Opnd, 19935 /* FADD_D */ 19936 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 19937 /* FADD_D32 */ 19938 AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, 19939 /* FADD_D32_MM */ 19940 AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, 19941 /* FADD_D64 */ 19942 FGR64Opnd, FGR64Opnd, FGR64Opnd, 19943 /* FADD_D64_MM */ 19944 FGR64Opnd, FGR64Opnd, FGR64Opnd, 19945 /* FADD_PS64 */ 19946 FGR64Opnd, FGR64Opnd, FGR64Opnd, 19947 /* FADD_S */ 19948 FGR32Opnd, FGR32Opnd, FGR32Opnd, 19949 /* FADD_S_MM */ 19950 FGR32Opnd, FGR32Opnd, FGR32Opnd, 19951 /* FADD_S_MMR6 */ 19952 FGR32Opnd, FGR32Opnd, FGR32Opnd, 19953 /* FADD_W */ 19954 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 19955 /* FCAF_D */ 19956 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 19957 /* FCAF_W */ 19958 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 19959 /* FCEQ_D */ 19960 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 19961 /* FCEQ_W */ 19962 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 19963 /* FCLASS_D */ 19964 MSA128DOpnd, MSA128DOpnd, 19965 /* FCLASS_W */ 19966 MSA128WOpnd, MSA128WOpnd, 19967 /* FCLE_D */ 19968 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 19969 /* FCLE_W */ 19970 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 19971 /* FCLT_D */ 19972 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 19973 /* FCLT_W */ 19974 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 19975 /* FCMP_D32 */ 19976 AFGR64, AFGR64, condcode, 19977 /* FCMP_D32_MM */ 19978 AFGR64, AFGR64, condcode, 19979 /* FCMP_D64 */ 19980 FGR64, FGR64, condcode, 19981 /* FCMP_S32 */ 19982 FGR32, FGR32, condcode, 19983 /* FCMP_S32_MM */ 19984 FGR32, FGR32, condcode, 19985 /* FCNE_D */ 19986 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 19987 /* FCNE_W */ 19988 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 19989 /* FCOR_D */ 19990 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 19991 /* FCOR_W */ 19992 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 19993 /* FCUEQ_D */ 19994 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 19995 /* FCUEQ_W */ 19996 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 19997 /* FCULE_D */ 19998 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 19999 /* FCULE_W */ 20000 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 20001 /* FCULT_D */ 20002 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 20003 /* FCULT_W */ 20004 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 20005 /* FCUNE_D */ 20006 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 20007 /* FCUNE_W */ 20008 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 20009 /* FCUN_D */ 20010 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 20011 /* FCUN_W */ 20012 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 20013 /* FDIV_D */ 20014 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 20015 /* FDIV_D32 */ 20016 AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, 20017 /* FDIV_D32_MM */ 20018 AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, 20019 /* FDIV_D64 */ 20020 FGR64Opnd, FGR64Opnd, FGR64Opnd, 20021 /* FDIV_D64_MM */ 20022 FGR64Opnd, FGR64Opnd, FGR64Opnd, 20023 /* FDIV_S */ 20024 FGR32Opnd, FGR32Opnd, FGR32Opnd, 20025 /* FDIV_S_MM */ 20026 FGR32Opnd, FGR32Opnd, FGR32Opnd, 20027 /* FDIV_S_MMR6 */ 20028 FGR32Opnd, FGR32Opnd, FGR32Opnd, 20029 /* FDIV_W */ 20030 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 20031 /* FEXDO_H */ 20032 MSA128HOpnd, MSA128WOpnd, MSA128WOpnd, 20033 /* FEXDO_W */ 20034 MSA128WOpnd, MSA128DOpnd, MSA128DOpnd, 20035 /* FEXP2_D */ 20036 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 20037 /* FEXP2_W */ 20038 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 20039 /* FEXUPL_D */ 20040 MSA128DOpnd, MSA128WOpnd, 20041 /* FEXUPL_W */ 20042 MSA128WOpnd, MSA128HOpnd, 20043 /* FEXUPR_D */ 20044 MSA128DOpnd, MSA128WOpnd, 20045 /* FEXUPR_W */ 20046 MSA128WOpnd, MSA128HOpnd, 20047 /* FFINT_S_D */ 20048 MSA128DOpnd, MSA128DOpnd, 20049 /* FFINT_S_W */ 20050 MSA128WOpnd, MSA128WOpnd, 20051 /* FFINT_U_D */ 20052 MSA128DOpnd, MSA128DOpnd, 20053 /* FFINT_U_W */ 20054 MSA128WOpnd, MSA128WOpnd, 20055 /* FFQL_D */ 20056 MSA128DOpnd, MSA128WOpnd, 20057 /* FFQL_W */ 20058 MSA128WOpnd, MSA128HOpnd, 20059 /* FFQR_D */ 20060 MSA128DOpnd, MSA128WOpnd, 20061 /* FFQR_W */ 20062 MSA128WOpnd, MSA128HOpnd, 20063 /* FILL_B */ 20064 MSA128BOpnd, GPR32Opnd, 20065 /* FILL_D */ 20066 MSA128DOpnd, GPR64Opnd, 20067 /* FILL_H */ 20068 MSA128HOpnd, GPR32Opnd, 20069 /* FILL_W */ 20070 MSA128WOpnd, GPR32Opnd, 20071 /* FLOG2_D */ 20072 MSA128DOpnd, MSA128DOpnd, 20073 /* FLOG2_W */ 20074 MSA128WOpnd, MSA128WOpnd, 20075 /* FLOOR_L_D64 */ 20076 FGR64Opnd, FGR64Opnd, 20077 /* FLOOR_L_D_MMR6 */ 20078 FGR64Opnd, FGR64Opnd, 20079 /* FLOOR_L_S */ 20080 FGR64Opnd, FGR32Opnd, 20081 /* FLOOR_L_S_MMR6 */ 20082 FGR64Opnd, FGR32Opnd, 20083 /* FLOOR_W_D32 */ 20084 FGR32Opnd, AFGR64Opnd, 20085 /* FLOOR_W_D64 */ 20086 FGR32Opnd, FGR64Opnd, 20087 /* FLOOR_W_D_MMR6 */ 20088 FGR32Opnd, AFGR64Opnd, 20089 /* FLOOR_W_MM */ 20090 FGR32Opnd, AFGR64Opnd, 20091 /* FLOOR_W_S */ 20092 FGR32Opnd, FGR32Opnd, 20093 /* FLOOR_W_S_MM */ 20094 FGR32Opnd, FGR32Opnd, 20095 /* FLOOR_W_S_MMR6 */ 20096 FGR32Opnd, FGR32Opnd, 20097 /* FMADD_D */ 20098 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 20099 /* FMADD_W */ 20100 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 20101 /* FMAX_A_D */ 20102 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 20103 /* FMAX_A_W */ 20104 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 20105 /* FMAX_D */ 20106 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 20107 /* FMAX_W */ 20108 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 20109 /* FMIN_A_D */ 20110 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 20111 /* FMIN_A_W */ 20112 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 20113 /* FMIN_D */ 20114 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 20115 /* FMIN_W */ 20116 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 20117 /* FMOV_D32 */ 20118 AFGR64Opnd, AFGR64Opnd, 20119 /* FMOV_D32_MM */ 20120 AFGR64Opnd, AFGR64Opnd, 20121 /* FMOV_D64 */ 20122 FGR64Opnd, FGR64Opnd, 20123 /* FMOV_D64_MM */ 20124 FGR64Opnd, FGR64Opnd, 20125 /* FMOV_D_MMR6 */ 20126 FGR64Opnd, FGR64Opnd, 20127 /* FMOV_S */ 20128 FGR32Opnd, FGR32Opnd, 20129 /* FMOV_S_MM */ 20130 FGR32Opnd, FGR32Opnd, 20131 /* FMOV_S_MMR6 */ 20132 FGR32Opnd, FGR32Opnd, 20133 /* FMSUB_D */ 20134 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 20135 /* FMSUB_W */ 20136 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 20137 /* FMUL_D */ 20138 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 20139 /* FMUL_D32 */ 20140 AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, 20141 /* FMUL_D32_MM */ 20142 AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, 20143 /* FMUL_D64 */ 20144 FGR64Opnd, FGR64Opnd, FGR64Opnd, 20145 /* FMUL_D64_MM */ 20146 FGR64Opnd, FGR64Opnd, FGR64Opnd, 20147 /* FMUL_PS64 */ 20148 FGR64Opnd, FGR64Opnd, FGR64Opnd, 20149 /* FMUL_S */ 20150 FGR32Opnd, FGR32Opnd, FGR32Opnd, 20151 /* FMUL_S_MM */ 20152 FGR32Opnd, FGR32Opnd, FGR32Opnd, 20153 /* FMUL_S_MMR6 */ 20154 FGR32Opnd, FGR32Opnd, FGR32Opnd, 20155 /* FMUL_W */ 20156 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 20157 /* FNEG_D32 */ 20158 AFGR64Opnd, AFGR64Opnd, 20159 /* FNEG_D32_MM */ 20160 AFGR64Opnd, AFGR64Opnd, 20161 /* FNEG_D64 */ 20162 FGR64Opnd, FGR64Opnd, 20163 /* FNEG_D64_MM */ 20164 FGR64Opnd, FGR64Opnd, 20165 /* FNEG_S */ 20166 FGR32Opnd, FGR32Opnd, 20167 /* FNEG_S_MM */ 20168 FGR32Opnd, FGR32Opnd, 20169 /* FNEG_S_MMR6 */ 20170 FGR32Opnd, FGR32Opnd, 20171 /* FORK */ 20172 GPR32Opnd, GPR32Opnd, GPR32Opnd, 20173 /* FRCP_D */ 20174 MSA128DOpnd, MSA128DOpnd, 20175 /* FRCP_W */ 20176 MSA128WOpnd, MSA128WOpnd, 20177 /* FRINT_D */ 20178 MSA128DOpnd, MSA128DOpnd, 20179 /* FRINT_W */ 20180 MSA128WOpnd, MSA128WOpnd, 20181 /* FRSQRT_D */ 20182 MSA128DOpnd, MSA128DOpnd, 20183 /* FRSQRT_W */ 20184 MSA128WOpnd, MSA128WOpnd, 20185 /* FSAF_D */ 20186 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 20187 /* FSAF_W */ 20188 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 20189 /* FSEQ_D */ 20190 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 20191 /* FSEQ_W */ 20192 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 20193 /* FSLE_D */ 20194 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 20195 /* FSLE_W */ 20196 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 20197 /* FSLT_D */ 20198 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 20199 /* FSLT_W */ 20200 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 20201 /* FSNE_D */ 20202 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 20203 /* FSNE_W */ 20204 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 20205 /* FSOR_D */ 20206 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 20207 /* FSOR_W */ 20208 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 20209 /* FSQRT_D */ 20210 MSA128DOpnd, MSA128DOpnd, 20211 /* FSQRT_D32 */ 20212 AFGR64Opnd, AFGR64Opnd, 20213 /* FSQRT_D32_MM */ 20214 AFGR64Opnd, AFGR64Opnd, 20215 /* FSQRT_D64 */ 20216 FGR64Opnd, FGR64Opnd, 20217 /* FSQRT_D64_MM */ 20218 FGR64Opnd, FGR64Opnd, 20219 /* FSQRT_S */ 20220 FGR32Opnd, FGR32Opnd, 20221 /* FSQRT_S_MM */ 20222 FGR32Opnd, FGR32Opnd, 20223 /* FSQRT_W */ 20224 MSA128WOpnd, MSA128WOpnd, 20225 /* FSUB_D */ 20226 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 20227 /* FSUB_D32 */ 20228 AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, 20229 /* FSUB_D32_MM */ 20230 AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, 20231 /* FSUB_D64 */ 20232 FGR64Opnd, FGR64Opnd, FGR64Opnd, 20233 /* FSUB_D64_MM */ 20234 FGR64Opnd, FGR64Opnd, FGR64Opnd, 20235 /* FSUB_PS64 */ 20236 FGR64Opnd, FGR64Opnd, FGR64Opnd, 20237 /* FSUB_S */ 20238 FGR32Opnd, FGR32Opnd, FGR32Opnd, 20239 /* FSUB_S_MM */ 20240 FGR32Opnd, FGR32Opnd, FGR32Opnd, 20241 /* FSUB_S_MMR6 */ 20242 FGR32Opnd, FGR32Opnd, FGR32Opnd, 20243 /* FSUB_W */ 20244 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 20245 /* FSUEQ_D */ 20246 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 20247 /* FSUEQ_W */ 20248 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 20249 /* FSULE_D */ 20250 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 20251 /* FSULE_W */ 20252 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 20253 /* FSULT_D */ 20254 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 20255 /* FSULT_W */ 20256 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 20257 /* FSUNE_D */ 20258 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 20259 /* FSUNE_W */ 20260 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 20261 /* FSUN_D */ 20262 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 20263 /* FSUN_W */ 20264 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 20265 /* FTINT_S_D */ 20266 MSA128DOpnd, MSA128DOpnd, 20267 /* FTINT_S_W */ 20268 MSA128WOpnd, MSA128WOpnd, 20269 /* FTINT_U_D */ 20270 MSA128DOpnd, MSA128DOpnd, 20271 /* FTINT_U_W */ 20272 MSA128WOpnd, MSA128WOpnd, 20273 /* FTQ_H */ 20274 MSA128HOpnd, MSA128WOpnd, MSA128WOpnd, 20275 /* FTQ_W */ 20276 MSA128WOpnd, MSA128DOpnd, MSA128DOpnd, 20277 /* FTRUNC_S_D */ 20278 MSA128DOpnd, MSA128DOpnd, 20279 /* FTRUNC_S_W */ 20280 MSA128WOpnd, MSA128WOpnd, 20281 /* FTRUNC_U_D */ 20282 MSA128DOpnd, MSA128DOpnd, 20283 /* FTRUNC_U_W */ 20284 MSA128WOpnd, MSA128WOpnd, 20285 /* GINVI */ 20286 GPR32Opnd, 20287 /* GINVI_MMR6 */ 20288 GPR32Opnd, 20289 /* GINVT */ 20290 GPR32Opnd, uimm2, 20291 /* GINVT_MMR6 */ 20292 GPR32Opnd, uimm2, 20293 /* HADD_S_D */ 20294 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd, 20295 /* HADD_S_H */ 20296 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd, 20297 /* HADD_S_W */ 20298 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd, 20299 /* HADD_U_D */ 20300 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd, 20301 /* HADD_U_H */ 20302 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd, 20303 /* HADD_U_W */ 20304 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd, 20305 /* HSUB_S_D */ 20306 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd, 20307 /* HSUB_S_H */ 20308 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd, 20309 /* HSUB_S_W */ 20310 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd, 20311 /* HSUB_U_D */ 20312 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd, 20313 /* HSUB_U_H */ 20314 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd, 20315 /* HSUB_U_W */ 20316 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd, 20317 /* HYPCALL */ 20318 uimm10, 20319 /* HYPCALL_MM */ 20320 uimm10, 20321 /* ILVEV_B */ 20322 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, 20323 /* ILVEV_D */ 20324 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 20325 /* ILVEV_H */ 20326 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, 20327 /* ILVEV_W */ 20328 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 20329 /* ILVL_B */ 20330 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, 20331 /* ILVL_D */ 20332 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 20333 /* ILVL_H */ 20334 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, 20335 /* ILVL_W */ 20336 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 20337 /* ILVOD_B */ 20338 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, 20339 /* ILVOD_D */ 20340 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 20341 /* ILVOD_H */ 20342 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, 20343 /* ILVOD_W */ 20344 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 20345 /* ILVR_B */ 20346 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, 20347 /* ILVR_D */ 20348 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 20349 /* ILVR_H */ 20350 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, 20351 /* ILVR_W */ 20352 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 20353 /* INS */ 20354 GPR32Opnd, GPR32Opnd, uimm5, uimm5_inssize_plus1, GPR32Opnd, 20355 /* INSERT_B */ 20356 MSA128BOpnd, MSA128BOpnd, GPR32Opnd, uimm4, 20357 /* INSERT_D */ 20358 MSA128DOpnd, MSA128DOpnd, GPR64Opnd, uimm1, 20359 /* INSERT_H */ 20360 MSA128HOpnd, MSA128HOpnd, GPR32Opnd, uimm3, 20361 /* INSERT_W */ 20362 MSA128WOpnd, MSA128WOpnd, GPR32Opnd, uimm2, 20363 /* INSV */ 20364 GPR32Opnd, GPR32Opnd, GPR32Opnd, 20365 /* INSVE_B */ 20366 MSA128BOpnd, MSA128BOpnd, uimm4, MSA128BOpnd, uimmz, 20367 /* INSVE_D */ 20368 MSA128DOpnd, MSA128DOpnd, uimm1, MSA128DOpnd, uimmz, 20369 /* INSVE_H */ 20370 MSA128HOpnd, MSA128HOpnd, uimm3, MSA128HOpnd, uimmz, 20371 /* INSVE_W */ 20372 MSA128WOpnd, MSA128WOpnd, uimm2, MSA128WOpnd, uimmz, 20373 /* INSV_MM */ 20374 GPR32Opnd, GPR32Opnd, GPR32Opnd, 20375 /* INS_MM */ 20376 GPR32Opnd, GPR32Opnd, uimm5, uimm5_inssize_plus1, GPR32Opnd, 20377 /* INS_MMR6 */ 20378 GPR32Opnd, GPR32Opnd, uimm5, uimm5_inssize_plus1, GPR32Opnd, 20379 /* J */ 20380 jmptarget, 20381 /* JAL */ 20382 calltarget, 20383 /* JALR */ 20384 GPR32Opnd, GPR32Opnd, 20385 /* JALR16_MM */ 20386 GPR32Opnd, 20387 /* JALR64 */ 20388 GPR64Opnd, GPR64Opnd, 20389 /* JALRC16_MMR6 */ 20390 GPR32Opnd, 20391 /* JALRC_HB_MMR6 */ 20392 GPR32Opnd, GPR32Opnd, 20393 /* JALRC_MMR6 */ 20394 GPR32Opnd, GPR32Opnd, 20395 /* JALRS16_MM */ 20396 GPR32Opnd, 20397 /* JALRS_MM */ 20398 GPR32Opnd, GPR32Opnd, 20399 /* JALR_HB */ 20400 GPR32Opnd, GPR32Opnd, 20401 /* JALR_HB64 */ 20402 GPR64Opnd, GPR64Opnd, 20403 /* JALR_MM */ 20404 GPR32Opnd, GPR32Opnd, 20405 /* JALS_MM */ 20406 calltarget_mm, 20407 /* JALX */ 20408 calltarget, 20409 /* JALX_MM */ 20410 calltarget, 20411 /* JAL_MM */ 20412 calltarget_mm, 20413 /* JIALC */ 20414 GPR32Opnd, calloffset16, 20415 /* JIALC64 */ 20416 GPR64Opnd, calloffset16, 20417 /* JIALC_MMR6 */ 20418 GPR32Opnd, calloffset16, 20419 /* JIC */ 20420 GPR32Opnd, jmpoffset16, 20421 /* JIC64 */ 20422 GPR64Opnd, jmpoffset16, 20423 /* JIC_MMR6 */ 20424 GPR32Opnd, jmpoffset16, 20425 /* JR */ 20426 GPR32Opnd, 20427 /* JR16_MM */ 20428 GPR32Opnd, 20429 /* JR64 */ 20430 GPR64Opnd, 20431 /* JRADDIUSP */ 20432 uimm5_lsl2, 20433 /* JRC16_MM */ 20434 GPR32Opnd, 20435 /* JRC16_MMR6 */ 20436 GPR32Opnd, 20437 /* JRCADDIUSP_MMR6 */ 20438 uimm5_lsl2, 20439 /* JR_HB */ 20440 GPR32Opnd, 20441 /* JR_HB64 */ 20442 GPR64Opnd, 20443 /* JR_HB64_R6 */ 20444 GPR64Opnd, 20445 /* JR_HB_R6 */ 20446 GPR32Opnd, 20447 /* JR_MM */ 20448 GPR32Opnd, 20449 /* J_MM */ 20450 jmptarget_mm, 20451 /* Jal16 */ 20452 uimm26, 20453 /* JalB16 */ 20454 uimm26, 20455 /* JrRa16 */ 20456 /* JrcRa16 */ 20457 /* JrcRx16 */ 20458 CPU16Regs, 20459 /* JumpLinkReg16 */ 20460 CPU16Regs, 20461 /* LB */ 20462 GPR32Opnd, -1, simm16, 20463 /* LB64 */ 20464 GPR64Opnd, -1, simm16, 20465 /* LBE */ 20466 GPR32Opnd, -1, simm9, 20467 /* LBE_MM */ 20468 GPR32Opnd, -1, simm16, 20469 /* LBU16_MM */ 20470 GPRMM16Opnd, -1, simm4, 20471 /* LBUX */ 20472 GPR32Opnd, -1, -1, 20473 /* LBUX_MM */ 20474 GPR32Opnd, -1, -1, 20475 /* LBU_MMR6 */ 20476 GPR32Opnd, -1, simm16, 20477 /* LB_MM */ 20478 GPR32Opnd, -1, simm16, 20479 /* LB_MMR6 */ 20480 GPR32Opnd, -1, simm16, 20481 /* LBu */ 20482 GPR32Opnd, -1, simm16, 20483 /* LBu64 */ 20484 GPR64Opnd, -1, simm16, 20485 /* LBuE */ 20486 GPR32Opnd, -1, simm9, 20487 /* LBuE_MM */ 20488 GPR32Opnd, -1, simm16, 20489 /* LBu_MM */ 20490 GPR32Opnd, -1, simm16, 20491 /* LD */ 20492 GPR64Opnd, -1, simm16, 20493 /* LDC1 */ 20494 AFGR64Opnd, -1, simm16, 20495 /* LDC164 */ 20496 FGR64Opnd, -1, simm16, 20497 /* LDC1_D64_MMR6 */ 20498 FGR64Opnd, -1, simm16, 20499 /* LDC1_MM_D32 */ 20500 AFGR64Opnd, -1, simm16, 20501 /* LDC1_MM_D64 */ 20502 FGR64Opnd, -1, simm16, 20503 /* LDC2 */ 20504 COP2Opnd, -1, simm16, 20505 /* LDC2_MMR6 */ 20506 COP2Opnd, GPR32, simm11, 20507 /* LDC2_R6 */ 20508 COP2Opnd, -1, simm11, 20509 /* LDC3 */ 20510 COP3Opnd, -1, simm16, 20511 /* LDI_B */ 20512 MSA128BOpnd, vsplat_simm10, 20513 /* LDI_D */ 20514 MSA128DOpnd, vsplat_simm10, 20515 /* LDI_H */ 20516 MSA128HOpnd, vsplat_simm10, 20517 /* LDI_W */ 20518 MSA128WOpnd, vsplat_simm10, 20519 /* LDL */ 20520 GPR64Opnd, -1, simm16, GPR64Opnd, 20521 /* LDPC */ 20522 GPR64Opnd, simm18_lsl3, 20523 /* LDR */ 20524 GPR64Opnd, -1, simm16, GPR64Opnd, 20525 /* LDXC1 */ 20526 AFGR64Opnd, -1, -1, 20527 /* LDXC164 */ 20528 FGR64Opnd, -1, -1, 20529 /* LD_B */ 20530 MSA128BOpnd, -1, simm10, 20531 /* LD_D */ 20532 MSA128DOpnd, -1, simm10_lsl3, 20533 /* LD_H */ 20534 MSA128HOpnd, -1, simm10_lsl1, 20535 /* LD_W */ 20536 MSA128WOpnd, -1, simm10_lsl2, 20537 /* LEA_ADDiu */ 20538 GPR32Opnd, -1, simm16, 20539 /* LEA_ADDiu64 */ 20540 GPR64Opnd, -1, simm16, 20541 /* LEA_ADDiu_MM */ 20542 GPR32Opnd, -1, simm16, 20543 /* LH */ 20544 GPR32Opnd, -1, simm16, 20545 /* LH64 */ 20546 GPR64Opnd, -1, simm16, 20547 /* LHE */ 20548 GPR32Opnd, -1, simm9, 20549 /* LHE_MM */ 20550 GPR32Opnd, -1, simm9, 20551 /* LHU16_MM */ 20552 GPRMM16Opnd, -1, simm4, 20553 /* LHX */ 20554 GPR32Opnd, -1, -1, 20555 /* LHX_MM */ 20556 GPR32Opnd, -1, -1, 20557 /* LH_MM */ 20558 GPR32Opnd, -1, simm16, 20559 /* LHu */ 20560 GPR32Opnd, -1, simm16, 20561 /* LHu64 */ 20562 GPR64Opnd, -1, simm16, 20563 /* LHuE */ 20564 GPR32Opnd, -1, simm9, 20565 /* LHuE_MM */ 20566 GPR32Opnd, -1, simm9, 20567 /* LHu_MM */ 20568 GPR32Opnd, -1, simm16, 20569 /* LI16_MM */ 20570 GPRMM16Opnd, li16_imm, 20571 /* LI16_MMR6 */ 20572 GPRMM16Opnd, li16_imm, 20573 /* LL */ 20574 GPR32Opnd, -1, simm16, 20575 /* LL64 */ 20576 GPR32Opnd, -1, simm16, 20577 /* LL64_R6 */ 20578 GPR32Opnd, -1, simm9, 20579 /* LLD */ 20580 GPR64Opnd, -1, simm16, 20581 /* LLD_R6 */ 20582 GPR64Opnd, -1, simm9, 20583 /* LLE */ 20584 GPR32Opnd, -1, simm9, 20585 /* LLE_MM */ 20586 GPR32Opnd, -1, simm9, 20587 /* LL_MM */ 20588 GPR32Opnd, -1, simm12, 20589 /* LL_MMR6 */ 20590 GPR32Opnd, -1, simm9, 20591 /* LL_R6 */ 20592 GPR32Opnd, -1, simm9, 20593 /* LSA */ 20594 GPR32Opnd, GPR32Opnd, GPR32Opnd, uimm2_plus1, 20595 /* LSA_MMR6 */ 20596 GPR32Opnd, GPR32Opnd, GPR32Opnd, uimm2_plus1, 20597 /* LSA_R6 */ 20598 GPR32Opnd, GPR32Opnd, GPR32Opnd, uimm2_plus1, 20599 /* LUI_MMR6 */ 20600 GPR32Opnd, uimm16, 20601 /* LUXC1 */ 20602 AFGR64Opnd, -1, -1, 20603 /* LUXC164 */ 20604 FGR64Opnd, -1, -1, 20605 /* LUXC1_MM */ 20606 FGR64Opnd, -1, -1, 20607 /* LUi */ 20608 GPR32Opnd, uimm16_relaxed, 20609 /* LUi64 */ 20610 GPR64Opnd, uimm16_64_relaxed, 20611 /* LUi_MM */ 20612 GPR32Opnd, uimm16_relaxed, 20613 /* LW */ 20614 GPR32Opnd, -1, simm16, 20615 /* LW16_MM */ 20616 GPRMM16Opnd, -1, simm4, 20617 /* LW64 */ 20618 GPR64Opnd, -1, simm16, 20619 /* LWC1 */ 20620 FGR32Opnd, -1, simm16, 20621 /* LWC1_MM */ 20622 FGR32Opnd, -1, simm16, 20623 /* LWC2 */ 20624 COP2Opnd, -1, simm16, 20625 /* LWC2_MMR6 */ 20626 COP2Opnd, GPR32, simm11, 20627 /* LWC2_R6 */ 20628 COP2Opnd, -1, simm11, 20629 /* LWC3 */ 20630 COP3Opnd, -1, simm16, 20631 /* LWDSP */ 20632 DSPROpnd, -1, simm16, 20633 /* LWDSP_MM */ 20634 DSPROpnd, -1, simm16, 20635 /* LWE */ 20636 GPR32Opnd, -1, simm9, 20637 /* LWE_MM */ 20638 GPR32Opnd, -1, simm9, 20639 /* LWGP_MM */ 20640 GPRMM16Opnd, -1, simm7_lsl2, 20641 /* LWL */ 20642 GPR32Opnd, -1, simm16, GPR32Opnd, 20643 /* LWL64 */ 20644 GPR64Opnd, -1, simm16, GPR64Opnd, 20645 /* LWLE */ 20646 GPR32Opnd, -1, simm9, GPR32Opnd, 20647 /* LWLE_MM */ 20648 GPR32Opnd, -1, simm9, GPR32Opnd, 20649 /* LWL_MM */ 20650 GPR32Opnd, -1, simm12, GPR32Opnd, 20651 /* LWM16_MM */ 20652 reglist16, -1, uimm8, 20653 /* LWM16_MMR6 */ 20654 reglist16, -1, uimm8, 20655 /* LWM32_MM */ 20656 reglist, -1, simm12, 20657 /* LWPC */ 20658 GPR32Opnd, simm19_lsl2, 20659 /* LWPC_MMR6 */ 20660 GPR32Opnd, simm19_lsl2, 20661 /* LWP_MM */ 20662 GPR32Opnd, GPR32Opnd, -1, simm12, 20663 /* LWR */ 20664 GPR32Opnd, -1, simm16, GPR32Opnd, 20665 /* LWR64 */ 20666 GPR64Opnd, -1, simm16, GPR64Opnd, 20667 /* LWRE */ 20668 GPR32Opnd, -1, simm9, GPR32Opnd, 20669 /* LWRE_MM */ 20670 GPR32Opnd, -1, simm9, GPR32Opnd, 20671 /* LWR_MM */ 20672 GPR32Opnd, -1, simm12, GPR32Opnd, 20673 /* LWSP_MM */ 20674 GPR32Opnd, -1, simm5, 20675 /* LWUPC */ 20676 GPR32Opnd, simm19_lsl2, 20677 /* LWU_MM */ 20678 GPR32Opnd, -1, simm12, 20679 /* LWX */ 20680 GPR32Opnd, -1, -1, 20681 /* LWXC1 */ 20682 FGR32Opnd, -1, -1, 20683 /* LWXC1_MM */ 20684 FGR32Opnd, -1, -1, 20685 /* LWXS_MM */ 20686 GPR32Opnd, -1, -1, 20687 /* LWX_MM */ 20688 GPR32Opnd, -1, -1, 20689 /* LW_MM */ 20690 GPR32Opnd, -1, simm16, 20691 /* LW_MMR6 */ 20692 GPR32Opnd, -1, simm16, 20693 /* LWu */ 20694 GPR64Opnd, -1, simm16, 20695 /* LbRxRyOffMemX16 */ 20696 CPU16Regs, CPU16Regs, simm16, 20697 /* LbuRxRyOffMemX16 */ 20698 CPU16Regs, CPU16Regs, simm16, 20699 /* LhRxRyOffMemX16 */ 20700 CPU16Regs, CPU16Regs, simm16, 20701 /* LhuRxRyOffMemX16 */ 20702 CPU16Regs, CPU16Regs, simm16, 20703 /* LiRxImm16 */ 20704 CPU16Regs, simm16, 20705 /* LiRxImmAlignX16 */ 20706 CPU16Regs, simm16, 20707 /* LiRxImmX16 */ 20708 CPU16Regs, simm16, 20709 /* LwRxPcTcp16 */ 20710 CPU16Regs, pcrel16, i32imm, 20711 /* LwRxPcTcpX16 */ 20712 CPU16Regs, pcrel16, i32imm, 20713 /* LwRxRyOffMemX16 */ 20714 CPU16Regs, CPU16Regs, simm16, 20715 /* LwRxSpImmX16 */ 20716 CPU16Regs, CPU16RegsPlusSP, simm16, 20717 /* MADD */ 20718 GPR32Opnd, GPR32Opnd, 20719 /* MADDF_D */ 20720 FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd, 20721 /* MADDF_D_MMR6 */ 20722 FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd, 20723 /* MADDF_S */ 20724 FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd, 20725 /* MADDF_S_MMR6 */ 20726 FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd, 20727 /* MADDR_Q_H */ 20728 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, 20729 /* MADDR_Q_W */ 20730 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 20731 /* MADDU */ 20732 GPR32Opnd, GPR32Opnd, 20733 /* MADDU_DSP */ 20734 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, 20735 /* MADDU_DSP_MM */ 20736 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, 20737 /* MADDU_MM */ 20738 GPR32Opnd, GPR32Opnd, 20739 /* MADDV_B */ 20740 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, 20741 /* MADDV_D */ 20742 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 20743 /* MADDV_H */ 20744 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, 20745 /* MADDV_W */ 20746 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 20747 /* MADD_D32 */ 20748 AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, 20749 /* MADD_D32_MM */ 20750 AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, 20751 /* MADD_D64 */ 20752 FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd, 20753 /* MADD_DSP */ 20754 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, 20755 /* MADD_DSP_MM */ 20756 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, 20757 /* MADD_MM */ 20758 GPR32Opnd, GPR32Opnd, 20759 /* MADD_Q_H */ 20760 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, 20761 /* MADD_Q_W */ 20762 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 20763 /* MADD_S */ 20764 FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd, 20765 /* MADD_S_MM */ 20766 FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd, 20767 /* MAQ_SA_W_PHL */ 20768 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, 20769 /* MAQ_SA_W_PHL_MM */ 20770 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, 20771 /* MAQ_SA_W_PHR */ 20772 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, 20773 /* MAQ_SA_W_PHR_MM */ 20774 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, 20775 /* MAQ_S_W_PHL */ 20776 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, 20777 /* MAQ_S_W_PHL_MM */ 20778 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, 20779 /* MAQ_S_W_PHR */ 20780 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, 20781 /* MAQ_S_W_PHR_MM */ 20782 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, 20783 /* MAXA_D */ 20784 FGR64Opnd, FGR64Opnd, FGR64Opnd, 20785 /* MAXA_D_MMR6 */ 20786 FGR64Opnd, FGR64Opnd, FGR64Opnd, 20787 /* MAXA_S */ 20788 FGR32Opnd, FGR32Opnd, FGR32Opnd, 20789 /* MAXA_S_MMR6 */ 20790 FGR32Opnd, FGR32Opnd, FGR32Opnd, 20791 /* MAXI_S_B */ 20792 MSA128BOpnd, MSA128BOpnd, vsplat_simm5, 20793 /* MAXI_S_D */ 20794 MSA128DOpnd, MSA128DOpnd, vsplat_simm5, 20795 /* MAXI_S_H */ 20796 MSA128HOpnd, MSA128HOpnd, vsplat_simm5, 20797 /* MAXI_S_W */ 20798 MSA128WOpnd, MSA128WOpnd, vsplat_simm5, 20799 /* MAXI_U_B */ 20800 MSA128BOpnd, MSA128BOpnd, vsplat_uimm5, 20801 /* MAXI_U_D */ 20802 MSA128DOpnd, MSA128DOpnd, vsplat_uimm5, 20803 /* MAXI_U_H */ 20804 MSA128HOpnd, MSA128HOpnd, vsplat_uimm5, 20805 /* MAXI_U_W */ 20806 MSA128WOpnd, MSA128WOpnd, vsplat_uimm5, 20807 /* MAX_A_B */ 20808 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, 20809 /* MAX_A_D */ 20810 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 20811 /* MAX_A_H */ 20812 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, 20813 /* MAX_A_W */ 20814 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 20815 /* MAX_D */ 20816 FGR64Opnd, FGR64Opnd, FGR64Opnd, 20817 /* MAX_D_MMR6 */ 20818 FGR64Opnd, FGR64Opnd, FGR64Opnd, 20819 /* MAX_S */ 20820 FGR32Opnd, FGR32Opnd, FGR32Opnd, 20821 /* MAX_S_B */ 20822 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, 20823 /* MAX_S_D */ 20824 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 20825 /* MAX_S_H */ 20826 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, 20827 /* MAX_S_MMR6 */ 20828 FGR32Opnd, FGR32Opnd, FGR32Opnd, 20829 /* MAX_S_W */ 20830 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 20831 /* MAX_U_B */ 20832 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, 20833 /* MAX_U_D */ 20834 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 20835 /* MAX_U_H */ 20836 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, 20837 /* MAX_U_W */ 20838 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 20839 /* MFC0 */ 20840 GPR32Opnd, COP0Opnd, uimm3, 20841 /* MFC0_MMR6 */ 20842 GPR32Opnd, COP0Opnd, uimm3, 20843 /* MFC1 */ 20844 GPR32Opnd, FGR32Opnd, 20845 /* MFC1_D64 */ 20846 GPR32Opnd, FGR64Opnd, 20847 /* MFC1_MM */ 20848 GPR32Opnd, FGR32Opnd, 20849 /* MFC1_MMR6 */ 20850 GPR32Opnd, FGR32Opnd, 20851 /* MFC2 */ 20852 GPR32Opnd, COP2Opnd, uimm3, 20853 /* MFC2_MMR6 */ 20854 GPR32Opnd, COP2Opnd, 20855 /* MFGC0 */ 20856 GPR32Opnd, COP0Opnd, uimm3, 20857 /* MFGC0_MM */ 20858 GPR32Opnd, COP0Opnd, uimm3, 20859 /* MFHC0_MMR6 */ 20860 GPR32Opnd, COP0Opnd, uimm3, 20861 /* MFHC1_D32 */ 20862 GPR32Opnd, AFGR64Opnd, 20863 /* MFHC1_D32_MM */ 20864 GPR32Opnd, AFGR64Opnd, 20865 /* MFHC1_D64 */ 20866 GPR32Opnd, FGR64Opnd, 20867 /* MFHC1_D64_MM */ 20868 GPR32Opnd, FGR64Opnd, 20869 /* MFHC2_MMR6 */ 20870 GPR32Opnd, COP2Opnd, 20871 /* MFHGC0 */ 20872 GPR32Opnd, COP0Opnd, uimm3, 20873 /* MFHGC0_MM */ 20874 GPR32Opnd, COP0Opnd, uimm3, 20875 /* MFHI */ 20876 GPR32Opnd, 20877 /* MFHI16_MM */ 20878 GPR32Opnd, 20879 /* MFHI64 */ 20880 GPR64Opnd, 20881 /* MFHI_DSP */ 20882 GPR32Opnd, ACC64DSPOpnd, 20883 /* MFHI_DSP_MM */ 20884 GPR32Opnd, ACC64DSPOpnd, 20885 /* MFHI_MM */ 20886 GPR32Opnd, 20887 /* MFLO */ 20888 GPR32Opnd, 20889 /* MFLO16_MM */ 20890 GPR32Opnd, 20891 /* MFLO64 */ 20892 GPR64Opnd, 20893 /* MFLO_DSP */ 20894 GPR32Opnd, ACC64DSPOpnd, 20895 /* MFLO_DSP_MM */ 20896 GPR32Opnd, ACC64DSPOpnd, 20897 /* MFLO_MM */ 20898 GPR32Opnd, 20899 /* MFTR */ 20900 GPR32Opnd, GPR32Opnd, uimm1, uimm3, uimm1, 20901 /* MINA_D */ 20902 FGR64Opnd, FGR64Opnd, FGR64Opnd, 20903 /* MINA_D_MMR6 */ 20904 FGR64Opnd, FGR64Opnd, FGR64Opnd, 20905 /* MINA_S */ 20906 FGR32Opnd, FGR32Opnd, FGR32Opnd, 20907 /* MINA_S_MMR6 */ 20908 FGR32Opnd, FGR32Opnd, FGR32Opnd, 20909 /* MINI_S_B */ 20910 MSA128BOpnd, MSA128BOpnd, vsplat_simm5, 20911 /* MINI_S_D */ 20912 MSA128DOpnd, MSA128DOpnd, vsplat_simm5, 20913 /* MINI_S_H */ 20914 MSA128HOpnd, MSA128HOpnd, vsplat_simm5, 20915 /* MINI_S_W */ 20916 MSA128WOpnd, MSA128WOpnd, vsplat_simm5, 20917 /* MINI_U_B */ 20918 MSA128BOpnd, MSA128BOpnd, vsplat_uimm5, 20919 /* MINI_U_D */ 20920 MSA128DOpnd, MSA128DOpnd, vsplat_uimm5, 20921 /* MINI_U_H */ 20922 MSA128HOpnd, MSA128HOpnd, vsplat_uimm5, 20923 /* MINI_U_W */ 20924 MSA128WOpnd, MSA128WOpnd, vsplat_uimm5, 20925 /* MIN_A_B */ 20926 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, 20927 /* MIN_A_D */ 20928 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 20929 /* MIN_A_H */ 20930 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, 20931 /* MIN_A_W */ 20932 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 20933 /* MIN_D */ 20934 FGR64Opnd, FGR64Opnd, FGR64Opnd, 20935 /* MIN_D_MMR6 */ 20936 FGR64Opnd, FGR64Opnd, FGR64Opnd, 20937 /* MIN_S */ 20938 FGR32Opnd, FGR32Opnd, FGR32Opnd, 20939 /* MIN_S_B */ 20940 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, 20941 /* MIN_S_D */ 20942 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 20943 /* MIN_S_H */ 20944 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, 20945 /* MIN_S_MMR6 */ 20946 FGR32Opnd, FGR32Opnd, FGR32Opnd, 20947 /* MIN_S_W */ 20948 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 20949 /* MIN_U_B */ 20950 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, 20951 /* MIN_U_D */ 20952 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 20953 /* MIN_U_H */ 20954 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, 20955 /* MIN_U_W */ 20956 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 20957 /* MOD */ 20958 GPR32Opnd, GPR32Opnd, GPR32Opnd, 20959 /* MODSUB */ 20960 GPR32Opnd, GPR32Opnd, GPR32Opnd, 20961 /* MODSUB_MM */ 20962 GPR32Opnd, GPR32Opnd, GPR32Opnd, 20963 /* MODU */ 20964 GPR32Opnd, GPR32Opnd, GPR32Opnd, 20965 /* MODU_MMR6 */ 20966 GPR32Opnd, GPR32Opnd, GPR32Opnd, 20967 /* MOD_MMR6 */ 20968 GPR32Opnd, GPR32Opnd, GPR32Opnd, 20969 /* MOD_S_B */ 20970 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, 20971 /* MOD_S_D */ 20972 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 20973 /* MOD_S_H */ 20974 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, 20975 /* MOD_S_W */ 20976 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 20977 /* MOD_U_B */ 20978 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, 20979 /* MOD_U_D */ 20980 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 20981 /* MOD_U_H */ 20982 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, 20983 /* MOD_U_W */ 20984 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 20985 /* MOVE16_MM */ 20986 GPR32Opnd, GPR32Opnd, 20987 /* MOVE16_MMR6 */ 20988 GPR32Opnd, GPR32Opnd, 20989 /* MOVEP_MM */ 20990 GPRMM16OpndMovePPairFirst, GPRMM16OpndMovePPairSecond, GPRMM16OpndMoveP, GPRMM16OpndMoveP, 20991 /* MOVEP_MMR6 */ 20992 GPRMM16OpndMovePPairFirst, GPRMM16OpndMovePPairSecond, GPRMM16OpndMoveP, GPRMM16OpndMoveP, 20993 /* MOVE_V */ 20994 MSA128BOpnd, MSA128BOpnd, 20995 /* MOVF_D32 */ 20996 AFGR64Opnd, AFGR64Opnd, FCCRegsOpnd, AFGR64Opnd, 20997 /* MOVF_D32_MM */ 20998 AFGR64Opnd, AFGR64Opnd, FCCRegsOpnd, AFGR64Opnd, 20999 /* MOVF_D64 */ 21000 FGR64Opnd, FGR64Opnd, FCCRegsOpnd, FGR64Opnd, 21001 /* MOVF_I */ 21002 GPR32Opnd, GPR32Opnd, FCCRegsOpnd, GPR32Opnd, 21003 /* MOVF_I64 */ 21004 GPR64Opnd, GPR64Opnd, FCCRegsOpnd, GPR64Opnd, 21005 /* MOVF_I_MM */ 21006 GPR32Opnd, GPR32Opnd, FCCRegsOpnd, GPR32Opnd, 21007 /* MOVF_S */ 21008 FGR32Opnd, FGR32Opnd, FCCRegsOpnd, FGR32Opnd, 21009 /* MOVF_S_MM */ 21010 FGR32Opnd, FGR32Opnd, FCCRegsOpnd, FGR32Opnd, 21011 /* MOVN_I64_D64 */ 21012 FGR64Opnd, FGR64Opnd, GPR64Opnd, FGR64Opnd, 21013 /* MOVN_I64_I */ 21014 GPR32Opnd, GPR32Opnd, GPR64Opnd, GPR32Opnd, 21015 /* MOVN_I64_I64 */ 21016 GPR64Opnd, GPR64Opnd, GPR64Opnd, GPR64Opnd, 21017 /* MOVN_I64_S */ 21018 FGR32Opnd, FGR32Opnd, GPR64Opnd, FGR32Opnd, 21019 /* MOVN_I_D32 */ 21020 AFGR64Opnd, AFGR64Opnd, GPR32Opnd, AFGR64Opnd, 21021 /* MOVN_I_D32_MM */ 21022 AFGR64Opnd, AFGR64Opnd, GPR32Opnd, AFGR64Opnd, 21023 /* MOVN_I_D64 */ 21024 FGR64Opnd, FGR64Opnd, GPR32Opnd, FGR64Opnd, 21025 /* MOVN_I_I */ 21026 GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd, 21027 /* MOVN_I_I64 */ 21028 GPR64Opnd, GPR64Opnd, GPR32Opnd, GPR64Opnd, 21029 /* MOVN_I_MM */ 21030 GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd, 21031 /* MOVN_I_S */ 21032 FGR32Opnd, FGR32Opnd, GPR32Opnd, FGR32Opnd, 21033 /* MOVN_I_S_MM */ 21034 FGR32Opnd, FGR32Opnd, GPR32Opnd, FGR32Opnd, 21035 /* MOVT_D32 */ 21036 AFGR64Opnd, AFGR64Opnd, FCCRegsOpnd, AFGR64Opnd, 21037 /* MOVT_D32_MM */ 21038 AFGR64Opnd, AFGR64Opnd, FCCRegsOpnd, AFGR64Opnd, 21039 /* MOVT_D64 */ 21040 FGR64Opnd, FGR64Opnd, FCCRegsOpnd, FGR64Opnd, 21041 /* MOVT_I */ 21042 GPR32Opnd, GPR32Opnd, FCCRegsOpnd, GPR32Opnd, 21043 /* MOVT_I64 */ 21044 GPR64Opnd, GPR64Opnd, FCCRegsOpnd, GPR64Opnd, 21045 /* MOVT_I_MM */ 21046 GPR32Opnd, GPR32Opnd, FCCRegsOpnd, GPR32Opnd, 21047 /* MOVT_S */ 21048 FGR32Opnd, FGR32Opnd, FCCRegsOpnd, FGR32Opnd, 21049 /* MOVT_S_MM */ 21050 FGR32Opnd, FGR32Opnd, FCCRegsOpnd, FGR32Opnd, 21051 /* MOVZ_I64_D64 */ 21052 FGR64Opnd, FGR64Opnd, GPR64Opnd, FGR64Opnd, 21053 /* MOVZ_I64_I */ 21054 GPR32Opnd, GPR32Opnd, GPR64Opnd, GPR32Opnd, 21055 /* MOVZ_I64_I64 */ 21056 GPR64Opnd, GPR64Opnd, GPR64Opnd, GPR64Opnd, 21057 /* MOVZ_I64_S */ 21058 FGR32Opnd, FGR32Opnd, GPR64Opnd, FGR32Opnd, 21059 /* MOVZ_I_D32 */ 21060 AFGR64Opnd, AFGR64Opnd, GPR32Opnd, AFGR64Opnd, 21061 /* MOVZ_I_D32_MM */ 21062 AFGR64Opnd, AFGR64Opnd, GPR32Opnd, AFGR64Opnd, 21063 /* MOVZ_I_D64 */ 21064 FGR64Opnd, FGR64Opnd, GPR32Opnd, FGR64Opnd, 21065 /* MOVZ_I_I */ 21066 GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd, 21067 /* MOVZ_I_I64 */ 21068 GPR64Opnd, GPR64Opnd, GPR32Opnd, GPR64Opnd, 21069 /* MOVZ_I_MM */ 21070 GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd, 21071 /* MOVZ_I_S */ 21072 FGR32Opnd, FGR32Opnd, GPR32Opnd, FGR32Opnd, 21073 /* MOVZ_I_S_MM */ 21074 FGR32Opnd, FGR32Opnd, GPR32Opnd, FGR32Opnd, 21075 /* MSUB */ 21076 GPR32Opnd, GPR32Opnd, 21077 /* MSUBF_D */ 21078 FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd, 21079 /* MSUBF_D_MMR6 */ 21080 FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd, 21081 /* MSUBF_S */ 21082 FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd, 21083 /* MSUBF_S_MMR6 */ 21084 FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd, 21085 /* MSUBR_Q_H */ 21086 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, 21087 /* MSUBR_Q_W */ 21088 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 21089 /* MSUBU */ 21090 GPR32Opnd, GPR32Opnd, 21091 /* MSUBU_DSP */ 21092 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, 21093 /* MSUBU_DSP_MM */ 21094 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, 21095 /* MSUBU_MM */ 21096 GPR32Opnd, GPR32Opnd, 21097 /* MSUBV_B */ 21098 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, 21099 /* MSUBV_D */ 21100 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 21101 /* MSUBV_H */ 21102 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, 21103 /* MSUBV_W */ 21104 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 21105 /* MSUB_D32 */ 21106 AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, 21107 /* MSUB_D32_MM */ 21108 AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, 21109 /* MSUB_D64 */ 21110 FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd, 21111 /* MSUB_DSP */ 21112 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, 21113 /* MSUB_DSP_MM */ 21114 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, 21115 /* MSUB_MM */ 21116 GPR32Opnd, GPR32Opnd, 21117 /* MSUB_Q_H */ 21118 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, 21119 /* MSUB_Q_W */ 21120 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 21121 /* MSUB_S */ 21122 FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd, 21123 /* MSUB_S_MM */ 21124 FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd, 21125 /* MTC0 */ 21126 COP0Opnd, GPR32Opnd, uimm3, 21127 /* MTC0_MMR6 */ 21128 COP0Opnd, GPR32Opnd, uimm3, 21129 /* MTC1 */ 21130 FGR32Opnd, GPR32Opnd, 21131 /* MTC1_D64 */ 21132 FGR64Opnd, GPR32Opnd, 21133 /* MTC1_D64_MM */ 21134 FGR64Opnd, GPR32Opnd, 21135 /* MTC1_MM */ 21136 FGR32Opnd, GPR32Opnd, 21137 /* MTC1_MMR6 */ 21138 FGR32Opnd, GPR32Opnd, 21139 /* MTC2 */ 21140 COP2Opnd, GPR32Opnd, uimm3, 21141 /* MTC2_MMR6 */ 21142 COP2Opnd, GPR32Opnd, 21143 /* MTGC0 */ 21144 COP0Opnd, GPR32Opnd, uimm3, 21145 /* MTGC0_MM */ 21146 COP0Opnd, GPR32Opnd, uimm3, 21147 /* MTHC0_MMR6 */ 21148 COP0Opnd, GPR32Opnd, uimm3, 21149 /* MTHC1_D32 */ 21150 AFGR64Opnd, AFGR64Opnd, GPR32Opnd, 21151 /* MTHC1_D32_MM */ 21152 AFGR64Opnd, AFGR64Opnd, GPR32Opnd, 21153 /* MTHC1_D64 */ 21154 FGR64Opnd, FGR64Opnd, GPR32Opnd, 21155 /* MTHC1_D64_MM */ 21156 FGR64Opnd, FGR64Opnd, GPR32Opnd, 21157 /* MTHC2_MMR6 */ 21158 COP2Opnd, GPR32Opnd, 21159 /* MTHGC0 */ 21160 COP0Opnd, GPR32Opnd, uimm3, 21161 /* MTHGC0_MM */ 21162 COP0Opnd, GPR32Opnd, uimm3, 21163 /* MTHI */ 21164 GPR32Opnd, 21165 /* MTHI64 */ 21166 GPR64Opnd, 21167 /* MTHI_DSP */ 21168 HI32DSPOpnd, GPR32Opnd, 21169 /* MTHI_DSP_MM */ 21170 HI32DSPOpnd, GPR32Opnd, 21171 /* MTHI_MM */ 21172 GPR32Opnd, 21173 /* MTHLIP */ 21174 ACC64DSPOpnd, GPR32Opnd, ACC64DSPOpnd, 21175 /* MTHLIP_MM */ 21176 ACC64DSPOpnd, GPR32Opnd, ACC64DSPOpnd, 21177 /* MTLO */ 21178 GPR32Opnd, 21179 /* MTLO64 */ 21180 GPR64Opnd, 21181 /* MTLO_DSP */ 21182 LO32DSPOpnd, GPR32Opnd, 21183 /* MTLO_DSP_MM */ 21184 LO32DSPOpnd, GPR32Opnd, 21185 /* MTLO_MM */ 21186 GPR32Opnd, 21187 /* MTM0 */ 21188 GPR64Opnd, 21189 /* MTM1 */ 21190 GPR64Opnd, 21191 /* MTM2 */ 21192 GPR64Opnd, 21193 /* MTP0 */ 21194 GPR64Opnd, 21195 /* MTP1 */ 21196 GPR64Opnd, 21197 /* MTP2 */ 21198 GPR64Opnd, 21199 /* MTTR */ 21200 GPR32Opnd, GPR32Opnd, uimm1, uimm3, uimm1, 21201 /* MUH */ 21202 GPR32Opnd, GPR32Opnd, GPR32Opnd, 21203 /* MUHU */ 21204 GPR32Opnd, GPR32Opnd, GPR32Opnd, 21205 /* MUHU_MMR6 */ 21206 GPR32Opnd, GPR32Opnd, GPR32Opnd, 21207 /* MUH_MMR6 */ 21208 GPR32Opnd, GPR32Opnd, GPR32Opnd, 21209 /* MUL */ 21210 GPR32Opnd, GPR32Opnd, GPR32Opnd, 21211 /* MULEQ_S_W_PHL */ 21212 GPR32Opnd, DSPROpnd, DSPROpnd, 21213 /* MULEQ_S_W_PHL_MM */ 21214 GPR32Opnd, DSPROpnd, DSPROpnd, 21215 /* MULEQ_S_W_PHR */ 21216 GPR32Opnd, DSPROpnd, DSPROpnd, 21217 /* MULEQ_S_W_PHR_MM */ 21218 GPR32Opnd, DSPROpnd, DSPROpnd, 21219 /* MULEU_S_PH_QBL */ 21220 DSPROpnd, DSPROpnd, DSPROpnd, 21221 /* MULEU_S_PH_QBL_MM */ 21222 DSPROpnd, DSPROpnd, DSPROpnd, 21223 /* MULEU_S_PH_QBR */ 21224 DSPROpnd, DSPROpnd, DSPROpnd, 21225 /* MULEU_S_PH_QBR_MM */ 21226 DSPROpnd, DSPROpnd, DSPROpnd, 21227 /* MULQ_RS_PH */ 21228 DSPROpnd, DSPROpnd, DSPROpnd, 21229 /* MULQ_RS_PH_MM */ 21230 DSPROpnd, DSPROpnd, DSPROpnd, 21231 /* MULQ_RS_W */ 21232 GPR32Opnd, GPR32Opnd, GPR32Opnd, 21233 /* MULQ_RS_W_MMR2 */ 21234 GPR32Opnd, GPR32Opnd, GPR32Opnd, 21235 /* MULQ_S_PH */ 21236 DSPROpnd, DSPROpnd, DSPROpnd, 21237 /* MULQ_S_PH_MMR2 */ 21238 DSPROpnd, DSPROpnd, DSPROpnd, 21239 /* MULQ_S_W */ 21240 GPR32Opnd, GPR32Opnd, GPR32Opnd, 21241 /* MULQ_S_W_MMR2 */ 21242 GPR32Opnd, GPR32Opnd, GPR32Opnd, 21243 /* MULR_PS64 */ 21244 FGR64Opnd, FGR64Opnd, FGR64Opnd, 21245 /* MULR_Q_H */ 21246 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, 21247 /* MULR_Q_W */ 21248 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 21249 /* MULSAQ_S_W_PH */ 21250 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, 21251 /* MULSAQ_S_W_PH_MM */ 21252 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, 21253 /* MULSA_W_PH */ 21254 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, 21255 /* MULSA_W_PH_MMR2 */ 21256 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, 21257 /* MULT */ 21258 GPR32Opnd, GPR32Opnd, 21259 /* MULTU_DSP */ 21260 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, 21261 /* MULTU_DSP_MM */ 21262 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, 21263 /* MULT_DSP */ 21264 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, 21265 /* MULT_DSP_MM */ 21266 ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, 21267 /* MULT_MM */ 21268 GPR32Opnd, GPR32Opnd, 21269 /* MULTu */ 21270 GPR32Opnd, GPR32Opnd, 21271 /* MULTu_MM */ 21272 GPR32Opnd, GPR32Opnd, 21273 /* MULU */ 21274 GPR32Opnd, GPR32Opnd, GPR32Opnd, 21275 /* MULU_MMR6 */ 21276 GPR32Opnd, GPR32Opnd, GPR32Opnd, 21277 /* MULV_B */ 21278 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, 21279 /* MULV_D */ 21280 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 21281 /* MULV_H */ 21282 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, 21283 /* MULV_W */ 21284 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 21285 /* MUL_MM */ 21286 GPR32Opnd, GPR32Opnd, GPR32Opnd, 21287 /* MUL_MMR6 */ 21288 GPR32Opnd, GPR32Opnd, GPR32Opnd, 21289 /* MUL_PH */ 21290 DSPROpnd, DSPROpnd, DSPROpnd, 21291 /* MUL_PH_MMR2 */ 21292 DSPROpnd, DSPROpnd, DSPROpnd, 21293 /* MUL_Q_H */ 21294 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, 21295 /* MUL_Q_W */ 21296 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 21297 /* MUL_R6 */ 21298 GPR32Opnd, GPR32Opnd, GPR32Opnd, 21299 /* MUL_S_PH */ 21300 DSPROpnd, DSPROpnd, DSPROpnd, 21301 /* MUL_S_PH_MMR2 */ 21302 DSPROpnd, DSPROpnd, DSPROpnd, 21303 /* Mfhi16 */ 21304 CPU16Regs, 21305 /* Mflo16 */ 21306 CPU16Regs, 21307 /* Move32R16 */ 21308 GPR32, CPU16Regs, 21309 /* MoveR3216 */ 21310 CPU16Regs, GPR32, 21311 /* NLOC_B */ 21312 MSA128BOpnd, MSA128BOpnd, 21313 /* NLOC_D */ 21314 MSA128DOpnd, MSA128DOpnd, 21315 /* NLOC_H */ 21316 MSA128HOpnd, MSA128HOpnd, 21317 /* NLOC_W */ 21318 MSA128WOpnd, MSA128WOpnd, 21319 /* NLZC_B */ 21320 MSA128BOpnd, MSA128BOpnd, 21321 /* NLZC_D */ 21322 MSA128DOpnd, MSA128DOpnd, 21323 /* NLZC_H */ 21324 MSA128HOpnd, MSA128HOpnd, 21325 /* NLZC_W */ 21326 MSA128WOpnd, MSA128WOpnd, 21327 /* NMADD_D32 */ 21328 AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, 21329 /* NMADD_D32_MM */ 21330 AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, 21331 /* NMADD_D64 */ 21332 FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd, 21333 /* NMADD_S */ 21334 FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd, 21335 /* NMADD_S_MM */ 21336 FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd, 21337 /* NMSUB_D32 */ 21338 AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, 21339 /* NMSUB_D32_MM */ 21340 AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, 21341 /* NMSUB_D64 */ 21342 FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd, 21343 /* NMSUB_S */ 21344 FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd, 21345 /* NMSUB_S_MM */ 21346 FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd, 21347 /* NOR */ 21348 GPR32Opnd, GPR32Opnd, GPR32Opnd, 21349 /* NOR64 */ 21350 GPR64Opnd, GPR64Opnd, GPR64Opnd, 21351 /* NORI_B */ 21352 MSA128BOpnd, MSA128BOpnd, vsplat_uimm8, 21353 /* NOR_MM */ 21354 GPR32Opnd, GPR32Opnd, GPR32Opnd, 21355 /* NOR_MMR6 */ 21356 GPR32Opnd, GPR32Opnd, GPR32Opnd, 21357 /* NOR_V */ 21358 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, 21359 /* NOT16_MM */ 21360 GPRMM16Opnd, GPRMM16Opnd, 21361 /* NOT16_MMR6 */ 21362 GPRMM16Opnd, GPRMM16Opnd, 21363 /* NegRxRy16 */ 21364 CPU16Regs, CPU16Regs, 21365 /* NotRxRy16 */ 21366 CPU16Regs, CPU16Regs, 21367 /* OR */ 21368 GPR32Opnd, GPR32Opnd, GPR32Opnd, 21369 /* OR16_MM */ 21370 GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd, 21371 /* OR16_MMR6 */ 21372 GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd, 21373 /* OR64 */ 21374 GPR64Opnd, GPR64Opnd, GPR64Opnd, 21375 /* ORI_B */ 21376 MSA128BOpnd, MSA128BOpnd, vsplat_uimm8, 21377 /* ORI_MMR6 */ 21378 GPR32Opnd, GPR32Opnd, uimm16, 21379 /* OR_MM */ 21380 GPR32Opnd, GPR32Opnd, GPR32Opnd, 21381 /* OR_MMR6 */ 21382 GPR32Opnd, GPR32Opnd, GPR32Opnd, 21383 /* OR_V */ 21384 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, 21385 /* ORi */ 21386 GPR32Opnd, GPR32Opnd, uimm16, 21387 /* ORi64 */ 21388 GPR64Opnd, GPR64Opnd, uimm16_64, 21389 /* ORi_MM */ 21390 GPR32Opnd, GPR32Opnd, uimm16, 21391 /* OrRxRxRy16 */ 21392 CPU16Regs, CPU16Regs, CPU16Regs, 21393 /* PACKRL_PH */ 21394 DSPROpnd, DSPROpnd, DSPROpnd, 21395 /* PACKRL_PH_MM */ 21396 DSPROpnd, DSPROpnd, DSPROpnd, 21397 /* PAUSE */ 21398 /* PAUSE_MM */ 21399 /* PAUSE_MMR6 */ 21400 /* PCKEV_B */ 21401 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, 21402 /* PCKEV_D */ 21403 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 21404 /* PCKEV_H */ 21405 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, 21406 /* PCKEV_W */ 21407 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 21408 /* PCKOD_B */ 21409 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, 21410 /* PCKOD_D */ 21411 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 21412 /* PCKOD_H */ 21413 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, 21414 /* PCKOD_W */ 21415 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 21416 /* PCNT_B */ 21417 MSA128BOpnd, MSA128BOpnd, 21418 /* PCNT_D */ 21419 MSA128DOpnd, MSA128DOpnd, 21420 /* PCNT_H */ 21421 MSA128HOpnd, MSA128HOpnd, 21422 /* PCNT_W */ 21423 MSA128WOpnd, MSA128WOpnd, 21424 /* PICK_PH */ 21425 DSPROpnd, DSPROpnd, DSPROpnd, 21426 /* PICK_PH_MM */ 21427 DSPROpnd, DSPROpnd, DSPROpnd, 21428 /* PICK_QB */ 21429 DSPROpnd, DSPROpnd, DSPROpnd, 21430 /* PICK_QB_MM */ 21431 DSPROpnd, DSPROpnd, DSPROpnd, 21432 /* PLL_PS64 */ 21433 FGR64Opnd, FGR64Opnd, FGR64Opnd, 21434 /* PLU_PS64 */ 21435 FGR64Opnd, FGR64Opnd, FGR64Opnd, 21436 /* POP */ 21437 GPR32Opnd, GPR32Opnd, 21438 /* PRECEQU_PH_QBL */ 21439 DSPROpnd, DSPROpnd, 21440 /* PRECEQU_PH_QBLA */ 21441 DSPROpnd, DSPROpnd, 21442 /* PRECEQU_PH_QBLA_MM */ 21443 DSPROpnd, DSPROpnd, 21444 /* PRECEQU_PH_QBL_MM */ 21445 DSPROpnd, DSPROpnd, 21446 /* PRECEQU_PH_QBR */ 21447 DSPROpnd, DSPROpnd, 21448 /* PRECEQU_PH_QBRA */ 21449 DSPROpnd, DSPROpnd, 21450 /* PRECEQU_PH_QBRA_MM */ 21451 DSPROpnd, DSPROpnd, 21452 /* PRECEQU_PH_QBR_MM */ 21453 DSPROpnd, DSPROpnd, 21454 /* PRECEQ_W_PHL */ 21455 GPR32Opnd, DSPROpnd, 21456 /* PRECEQ_W_PHL_MM */ 21457 GPR32Opnd, DSPROpnd, 21458 /* PRECEQ_W_PHR */ 21459 GPR32Opnd, DSPROpnd, 21460 /* PRECEQ_W_PHR_MM */ 21461 GPR32Opnd, DSPROpnd, 21462 /* PRECEU_PH_QBL */ 21463 DSPROpnd, DSPROpnd, 21464 /* PRECEU_PH_QBLA */ 21465 DSPROpnd, DSPROpnd, 21466 /* PRECEU_PH_QBLA_MM */ 21467 DSPROpnd, DSPROpnd, 21468 /* PRECEU_PH_QBL_MM */ 21469 DSPROpnd, DSPROpnd, 21470 /* PRECEU_PH_QBR */ 21471 DSPROpnd, DSPROpnd, 21472 /* PRECEU_PH_QBRA */ 21473 DSPROpnd, DSPROpnd, 21474 /* PRECEU_PH_QBRA_MM */ 21475 DSPROpnd, DSPROpnd, 21476 /* PRECEU_PH_QBR_MM */ 21477 DSPROpnd, DSPROpnd, 21478 /* PRECRQU_S_QB_PH */ 21479 DSPROpnd, DSPROpnd, DSPROpnd, 21480 /* PRECRQU_S_QB_PH_MM */ 21481 DSPROpnd, DSPROpnd, DSPROpnd, 21482 /* PRECRQ_PH_W */ 21483 DSPROpnd, GPR32Opnd, GPR32Opnd, 21484 /* PRECRQ_PH_W_MM */ 21485 DSPROpnd, GPR32Opnd, GPR32Opnd, 21486 /* PRECRQ_QB_PH */ 21487 DSPROpnd, DSPROpnd, DSPROpnd, 21488 /* PRECRQ_QB_PH_MM */ 21489 DSPROpnd, DSPROpnd, DSPROpnd, 21490 /* PRECRQ_RS_PH_W */ 21491 DSPROpnd, GPR32Opnd, GPR32Opnd, 21492 /* PRECRQ_RS_PH_W_MM */ 21493 DSPROpnd, GPR32Opnd, GPR32Opnd, 21494 /* PRECR_QB_PH */ 21495 DSPROpnd, DSPROpnd, DSPROpnd, 21496 /* PRECR_QB_PH_MMR2 */ 21497 DSPROpnd, DSPROpnd, DSPROpnd, 21498 /* PRECR_SRA_PH_W */ 21499 DSPROpnd, GPR32Opnd, uimm5, GPR32Opnd, 21500 /* PRECR_SRA_PH_W_MMR2 */ 21501 DSPROpnd, GPR32Opnd, uimm5, GPR32Opnd, 21502 /* PRECR_SRA_R_PH_W */ 21503 DSPROpnd, GPR32Opnd, uimm5, GPR32Opnd, 21504 /* PRECR_SRA_R_PH_W_MMR2 */ 21505 DSPROpnd, GPR32Opnd, uimm5, GPR32Opnd, 21506 /* PREF */ 21507 -1, simm16, uimm5, 21508 /* PREFE */ 21509 -1, simm9, uimm5, 21510 /* PREFE_MM */ 21511 -1, simm9, uimm5, 21512 /* PREFX_MM */ 21513 -1, -1, uimm5, 21514 /* PREF_MM */ 21515 -1, simm12, uimm5, 21516 /* PREF_MMR6 */ 21517 -1, simm12, uimm5, 21518 /* PREF_R6 */ 21519 -1, simm9, uimm5, 21520 /* PREPEND */ 21521 GPR32Opnd, GPR32Opnd, uimm5, GPR32Opnd, 21522 /* PREPEND_MMR2 */ 21523 GPR32Opnd, GPR32Opnd, uimm5, GPR32Opnd, 21524 /* PUL_PS64 */ 21525 FGR64Opnd, FGR64Opnd, FGR64Opnd, 21526 /* PUU_PS64 */ 21527 FGR64Opnd, FGR64Opnd, FGR64Opnd, 21528 /* RADDU_W_QB */ 21529 GPR32Opnd, DSPROpnd, 21530 /* RADDU_W_QB_MM */ 21531 GPR32Opnd, DSPROpnd, 21532 /* RDDSP */ 21533 GPR32Opnd, uimm10, 21534 /* RDDSP_MM */ 21535 GPR32Opnd, uimm7, 21536 /* RDHWR */ 21537 GPR32Opnd, HWRegsOpnd, uimm8, 21538 /* RDHWR64 */ 21539 GPR64Opnd, HWRegsOpnd, uimm8, 21540 /* RDHWR_MM */ 21541 GPR32Opnd, HWRegsOpnd, uimm8, 21542 /* RDHWR_MMR6 */ 21543 GPR32Opnd, HWRegsOpnd, uimm3, 21544 /* RDPGPR_MMR6 */ 21545 GPR32Opnd, GPR32Opnd, 21546 /* RECIP_D32 */ 21547 AFGR64Opnd, AFGR64Opnd, 21548 /* RECIP_D32_MM */ 21549 AFGR64Opnd, AFGR64Opnd, 21550 /* RECIP_D64 */ 21551 FGR64Opnd, FGR64Opnd, 21552 /* RECIP_D64_MM */ 21553 FGR64Opnd, FGR64Opnd, 21554 /* RECIP_S */ 21555 FGR32Opnd, FGR32Opnd, 21556 /* RECIP_S_MM */ 21557 FGR32Opnd, FGR32Opnd, 21558 /* REPLV_PH */ 21559 DSPROpnd, GPR32Opnd, 21560 /* REPLV_PH_MM */ 21561 DSPROpnd, GPR32Opnd, 21562 /* REPLV_QB */ 21563 DSPROpnd, GPR32Opnd, 21564 /* REPLV_QB_MM */ 21565 DSPROpnd, GPR32Opnd, 21566 /* REPL_PH */ 21567 DSPROpnd, simm10, 21568 /* REPL_PH_MM */ 21569 DSPROpnd, simm10, 21570 /* REPL_QB */ 21571 DSPROpnd, uimm8, 21572 /* REPL_QB_MM */ 21573 DSPROpnd, uimm8, 21574 /* RINT_D */ 21575 FGR64Opnd, FGR64Opnd, 21576 /* RINT_D_MMR6 */ 21577 FGR64Opnd, FGR64Opnd, 21578 /* RINT_S */ 21579 FGR32Opnd, FGR32Opnd, 21580 /* RINT_S_MMR6 */ 21581 FGR32Opnd, FGR32Opnd, 21582 /* ROTR */ 21583 GPR32Opnd, GPR32Opnd, uimm5, 21584 /* ROTRV */ 21585 GPR32Opnd, GPR32Opnd, GPR32Opnd, 21586 /* ROTRV_MM */ 21587 GPR32Opnd, GPR32Opnd, GPR32Opnd, 21588 /* ROTR_MM */ 21589 GPR32Opnd, GPR32Opnd, uimm5, 21590 /* ROUND_L_D64 */ 21591 FGR64Opnd, FGR64Opnd, 21592 /* ROUND_L_D_MMR6 */ 21593 FGR64Opnd, FGR64Opnd, 21594 /* ROUND_L_S */ 21595 FGR64Opnd, FGR32Opnd, 21596 /* ROUND_L_S_MMR6 */ 21597 FGR64Opnd, FGR32Opnd, 21598 /* ROUND_W_D32 */ 21599 FGR32Opnd, AFGR64Opnd, 21600 /* ROUND_W_D64 */ 21601 FGR32Opnd, FGR64Opnd, 21602 /* ROUND_W_D_MMR6 */ 21603 FGR64Opnd, FGR64Opnd, 21604 /* ROUND_W_MM */ 21605 FGR32Opnd, AFGR64Opnd, 21606 /* ROUND_W_S */ 21607 FGR32Opnd, FGR32Opnd, 21608 /* ROUND_W_S_MM */ 21609 FGR32Opnd, FGR32Opnd, 21610 /* ROUND_W_S_MMR6 */ 21611 FGR32Opnd, FGR32Opnd, 21612 /* RSQRT_D32 */ 21613 AFGR64Opnd, AFGR64Opnd, 21614 /* RSQRT_D32_MM */ 21615 AFGR64Opnd, AFGR64Opnd, 21616 /* RSQRT_D64 */ 21617 FGR64Opnd, FGR64Opnd, 21618 /* RSQRT_D64_MM */ 21619 FGR64Opnd, FGR64Opnd, 21620 /* RSQRT_S */ 21621 FGR32Opnd, FGR32Opnd, 21622 /* RSQRT_S_MM */ 21623 FGR32Opnd, FGR32Opnd, 21624 /* Restore16 */ 21625 /* RestoreX16 */ 21626 /* SAA */ 21627 GPR64Opnd, GPR64Opnd, 21628 /* SAAD */ 21629 GPR64Opnd, GPR64Opnd, 21630 /* SAT_S_B */ 21631 MSA128BOpnd, MSA128BOpnd, uimm3, 21632 /* SAT_S_D */ 21633 MSA128DOpnd, MSA128DOpnd, uimm6, 21634 /* SAT_S_H */ 21635 MSA128HOpnd, MSA128HOpnd, uimm4, 21636 /* SAT_S_W */ 21637 MSA128WOpnd, MSA128WOpnd, uimm5, 21638 /* SAT_U_B */ 21639 MSA128BOpnd, MSA128BOpnd, uimm3, 21640 /* SAT_U_D */ 21641 MSA128DOpnd, MSA128DOpnd, uimm6, 21642 /* SAT_U_H */ 21643 MSA128HOpnd, MSA128HOpnd, uimm4, 21644 /* SAT_U_W */ 21645 MSA128WOpnd, MSA128WOpnd, uimm5, 21646 /* SB */ 21647 GPR32Opnd, -1, simm16, 21648 /* SB16_MM */ 21649 GPRMM16OpndZero, -1, simm4, 21650 /* SB16_MMR6 */ 21651 GPRMM16OpndZero, -1, simm4, 21652 /* SB64 */ 21653 GPR64Opnd, -1, simm16, 21654 /* SBE */ 21655 GPR32Opnd, -1, simm9, 21656 /* SBE_MM */ 21657 GPR32Opnd, -1, simm9, 21658 /* SB_MM */ 21659 GPR32Opnd, -1, simm16, 21660 /* SB_MMR6 */ 21661 GPR32Opnd, -1, simm16, 21662 /* SC */ 21663 GPR32Opnd, GPR32Opnd, -1, simm16, 21664 /* SC64 */ 21665 GPR32Opnd, GPR32Opnd, -1, simm16, 21666 /* SC64_R6 */ 21667 GPR32Opnd, GPR32Opnd, -1, simm9, 21668 /* SCD */ 21669 GPR64Opnd, GPR64Opnd, -1, simm16, 21670 /* SCD_R6 */ 21671 GPR64Opnd, GPR64Opnd, -1, simm9, 21672 /* SCE */ 21673 GPR32Opnd, GPR32Opnd, -1, simm9, 21674 /* SCE_MM */ 21675 GPR32Opnd, GPR32Opnd, -1, simm9, 21676 /* SC_MM */ 21677 GPR32Opnd, GPR32Opnd, -1, simm12, 21678 /* SC_MMR6 */ 21679 GPR32Opnd, GPR32Opnd, -1, simm9, 21680 /* SC_R6 */ 21681 GPR32Opnd, GPR32Opnd, -1, simm9, 21682 /* SD */ 21683 GPR64Opnd, -1, simm16, 21684 /* SDBBP */ 21685 uimm20, 21686 /* SDBBP16_MM */ 21687 uimm4, 21688 /* SDBBP16_MMR6 */ 21689 uimm4, 21690 /* SDBBP_MM */ 21691 uimm10, 21692 /* SDBBP_MMR6 */ 21693 uimm20, 21694 /* SDBBP_R6 */ 21695 uimm20, 21696 /* SDC1 */ 21697 AFGR64Opnd, -1, simm16, 21698 /* SDC164 */ 21699 FGR64Opnd, -1, simm16, 21700 /* SDC1_D64_MMR6 */ 21701 FGR64Opnd, -1, simm16, 21702 /* SDC1_MM_D32 */ 21703 AFGR64Opnd, -1, simm16, 21704 /* SDC1_MM_D64 */ 21705 FGR64Opnd, -1, simm16, 21706 /* SDC2 */ 21707 COP2Opnd, -1, simm16, 21708 /* SDC2_MMR6 */ 21709 COP2Opnd, GPR32, simm11, 21710 /* SDC2_R6 */ 21711 COP2Opnd, -1, simm11, 21712 /* SDC3 */ 21713 COP3Opnd, -1, simm16, 21714 /* SDIV */ 21715 GPR32Opnd, GPR32Opnd, 21716 /* SDIV_MM */ 21717 GPR32Opnd, GPR32Opnd, 21718 /* SDL */ 21719 GPR64Opnd, -1, simm16, 21720 /* SDR */ 21721 GPR64Opnd, -1, simm16, 21722 /* SDXC1 */ 21723 AFGR64Opnd, -1, -1, 21724 /* SDXC164 */ 21725 FGR64Opnd, -1, -1, 21726 /* SEB */ 21727 GPR32Opnd, GPR32Opnd, 21728 /* SEB64 */ 21729 GPR64Opnd, GPR64Opnd, 21730 /* SEB_MM */ 21731 GPR32Opnd, GPR32Opnd, 21732 /* SEH */ 21733 GPR32Opnd, GPR32Opnd, 21734 /* SEH64 */ 21735 GPR64Opnd, GPR64Opnd, 21736 /* SEH_MM */ 21737 GPR32Opnd, GPR32Opnd, 21738 /* SELEQZ */ 21739 GPR32Opnd, GPR32Opnd, GPR32Opnd, 21740 /* SELEQZ64 */ 21741 GPR64Opnd, GPR64Opnd, GPR64Opnd, 21742 /* SELEQZ_D */ 21743 FGR64Opnd, FGR64Opnd, FGR64Opnd, 21744 /* SELEQZ_D_MMR6 */ 21745 FGR64Opnd, FGR64Opnd, FGR64Opnd, 21746 /* SELEQZ_MMR6 */ 21747 GPR32Opnd, GPR32Opnd, GPR32Opnd, 21748 /* SELEQZ_S */ 21749 FGR32Opnd, FGR32Opnd, FGR32Opnd, 21750 /* SELEQZ_S_MMR6 */ 21751 FGR32Opnd, FGR32Opnd, FGR32Opnd, 21752 /* SELNEZ */ 21753 GPR32Opnd, GPR32Opnd, GPR32Opnd, 21754 /* SELNEZ64 */ 21755 GPR64Opnd, GPR64Opnd, GPR64Opnd, 21756 /* SELNEZ_D */ 21757 FGR64Opnd, FGR64Opnd, FGR64Opnd, 21758 /* SELNEZ_D_MMR6 */ 21759 FGR64Opnd, FGR64Opnd, FGR64Opnd, 21760 /* SELNEZ_MMR6 */ 21761 GPR32Opnd, GPR32Opnd, GPR32Opnd, 21762 /* SELNEZ_S */ 21763 FGR32Opnd, FGR32Opnd, FGR32Opnd, 21764 /* SELNEZ_S_MMR6 */ 21765 FGR32Opnd, FGR32Opnd, FGR32Opnd, 21766 /* SEL_D */ 21767 FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd, 21768 /* SEL_D_MMR6 */ 21769 FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd, 21770 /* SEL_S */ 21771 FGR32Opnd, FGRCCOpnd, FGR32Opnd, FGR32Opnd, 21772 /* SEL_S_MMR6 */ 21773 FGR32Opnd, FGRCCOpnd, FGR32Opnd, FGR32Opnd, 21774 /* SEQ */ 21775 GPR64Opnd, GPR64Opnd, GPR64Opnd, 21776 /* SEQi */ 21777 GPR64Opnd, GPR64Opnd, simm10_64, 21778 /* SH */ 21779 GPR32Opnd, -1, simm16, 21780 /* SH16_MM */ 21781 GPRMM16OpndZero, -1, simm4, 21782 /* SH16_MMR6 */ 21783 GPRMM16OpndZero, -1, simm4, 21784 /* SH64 */ 21785 GPR64Opnd, -1, simm16, 21786 /* SHE */ 21787 GPR32Opnd, -1, simm9, 21788 /* SHE_MM */ 21789 GPR32Opnd, -1, simm9, 21790 /* SHF_B */ 21791 MSA128BOpnd, MSA128BOpnd, uimm8, 21792 /* SHF_H */ 21793 MSA128HOpnd, MSA128HOpnd, uimm8, 21794 /* SHF_W */ 21795 MSA128WOpnd, MSA128WOpnd, uimm8, 21796 /* SHILO */ 21797 ACC64DSPOpnd, simm6, ACC64DSPOpnd, 21798 /* SHILOV */ 21799 ACC64DSPOpnd, GPR32Opnd, ACC64DSPOpnd, 21800 /* SHILOV_MM */ 21801 ACC64DSPOpnd, GPR32Opnd, ACC64DSPOpnd, 21802 /* SHILO_MM */ 21803 ACC64DSPOpnd, simm6, ACC64DSPOpnd, 21804 /* SHLLV_PH */ 21805 DSPROpnd, DSPROpnd, GPR32Opnd, 21806 /* SHLLV_PH_MM */ 21807 DSPROpnd, DSPROpnd, GPR32Opnd, 21808 /* SHLLV_QB */ 21809 DSPROpnd, DSPROpnd, GPR32Opnd, 21810 /* SHLLV_QB_MM */ 21811 DSPROpnd, DSPROpnd, GPR32Opnd, 21812 /* SHLLV_S_PH */ 21813 DSPROpnd, DSPROpnd, GPR32Opnd, 21814 /* SHLLV_S_PH_MM */ 21815 DSPROpnd, DSPROpnd, GPR32Opnd, 21816 /* SHLLV_S_W */ 21817 GPR32Opnd, GPR32Opnd, GPR32Opnd, 21818 /* SHLLV_S_W_MM */ 21819 GPR32Opnd, GPR32Opnd, GPR32Opnd, 21820 /* SHLL_PH */ 21821 DSPROpnd, DSPROpnd, uimm4, 21822 /* SHLL_PH_MM */ 21823 DSPROpnd, DSPROpnd, uimm4, 21824 /* SHLL_QB */ 21825 DSPROpnd, DSPROpnd, uimm3, 21826 /* SHLL_QB_MM */ 21827 DSPROpnd, DSPROpnd, uimm3, 21828 /* SHLL_S_PH */ 21829 DSPROpnd, DSPROpnd, uimm4, 21830 /* SHLL_S_PH_MM */ 21831 DSPROpnd, DSPROpnd, uimm4, 21832 /* SHLL_S_W */ 21833 GPR32Opnd, GPR32Opnd, uimm5, 21834 /* SHLL_S_W_MM */ 21835 GPR32Opnd, GPR32Opnd, uimm5, 21836 /* SHRAV_PH */ 21837 DSPROpnd, DSPROpnd, GPR32Opnd, 21838 /* SHRAV_PH_MM */ 21839 DSPROpnd, DSPROpnd, GPR32Opnd, 21840 /* SHRAV_QB */ 21841 DSPROpnd, DSPROpnd, GPR32Opnd, 21842 /* SHRAV_QB_MMR2 */ 21843 DSPROpnd, DSPROpnd, GPR32Opnd, 21844 /* SHRAV_R_PH */ 21845 DSPROpnd, DSPROpnd, GPR32Opnd, 21846 /* SHRAV_R_PH_MM */ 21847 DSPROpnd, DSPROpnd, GPR32Opnd, 21848 /* SHRAV_R_QB */ 21849 DSPROpnd, DSPROpnd, GPR32Opnd, 21850 /* SHRAV_R_QB_MMR2 */ 21851 DSPROpnd, DSPROpnd, GPR32Opnd, 21852 /* SHRAV_R_W */ 21853 GPR32Opnd, GPR32Opnd, GPR32Opnd, 21854 /* SHRAV_R_W_MM */ 21855 GPR32Opnd, GPR32Opnd, GPR32Opnd, 21856 /* SHRA_PH */ 21857 DSPROpnd, DSPROpnd, uimm4, 21858 /* SHRA_PH_MM */ 21859 DSPROpnd, DSPROpnd, uimm4, 21860 /* SHRA_QB */ 21861 DSPROpnd, DSPROpnd, uimm3, 21862 /* SHRA_QB_MMR2 */ 21863 DSPROpnd, DSPROpnd, uimm3, 21864 /* SHRA_R_PH */ 21865 DSPROpnd, DSPROpnd, uimm4, 21866 /* SHRA_R_PH_MM */ 21867 DSPROpnd, DSPROpnd, uimm4, 21868 /* SHRA_R_QB */ 21869 DSPROpnd, DSPROpnd, uimm3, 21870 /* SHRA_R_QB_MMR2 */ 21871 DSPROpnd, DSPROpnd, uimm3, 21872 /* SHRA_R_W */ 21873 GPR32Opnd, GPR32Opnd, uimm5, 21874 /* SHRA_R_W_MM */ 21875 GPR32Opnd, GPR32Opnd, uimm5, 21876 /* SHRLV_PH */ 21877 DSPROpnd, DSPROpnd, GPR32Opnd, 21878 /* SHRLV_PH_MMR2 */ 21879 DSPROpnd, DSPROpnd, GPR32Opnd, 21880 /* SHRLV_QB */ 21881 DSPROpnd, DSPROpnd, GPR32Opnd, 21882 /* SHRLV_QB_MM */ 21883 DSPROpnd, DSPROpnd, GPR32Opnd, 21884 /* SHRL_PH */ 21885 DSPROpnd, DSPROpnd, uimm4, 21886 /* SHRL_PH_MMR2 */ 21887 DSPROpnd, DSPROpnd, uimm4, 21888 /* SHRL_QB */ 21889 DSPROpnd, DSPROpnd, uimm3, 21890 /* SHRL_QB_MM */ 21891 DSPROpnd, DSPROpnd, uimm3, 21892 /* SH_MM */ 21893 GPR32Opnd, -1, simm16, 21894 /* SH_MMR6 */ 21895 GPR32Opnd, -1, simm16, 21896 /* SIGRIE */ 21897 uimm16, 21898 /* SIGRIE_MMR6 */ 21899 uimm16, 21900 /* SLDI_B */ 21901 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, uimm4, 21902 /* SLDI_D */ 21903 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, uimm1, 21904 /* SLDI_H */ 21905 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, uimm3, 21906 /* SLDI_W */ 21907 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, uimm2, 21908 /* SLD_B */ 21909 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, GPR32Opnd, 21910 /* SLD_D */ 21911 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, GPR32Opnd, 21912 /* SLD_H */ 21913 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, GPR32Opnd, 21914 /* SLD_W */ 21915 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, GPR32Opnd, 21916 /* SLL */ 21917 GPR32Opnd, GPR32Opnd, uimm5, 21918 /* SLL16_MM */ 21919 GPRMM16Opnd, GPRMM16Opnd, uimm3_shift, 21920 /* SLL16_MMR6 */ 21921 GPRMM16Opnd, GPRMM16Opnd, uimm3_shift, 21922 /* SLL64_32 */ 21923 GPR64, GPR32, 21924 /* SLL64_64 */ 21925 GPR64, GPR64, 21926 /* SLLI_B */ 21927 MSA128BOpnd, MSA128BOpnd, vsplat_uimm3, 21928 /* SLLI_D */ 21929 MSA128DOpnd, MSA128DOpnd, vsplat_uimm6, 21930 /* SLLI_H */ 21931 MSA128HOpnd, MSA128HOpnd, vsplat_uimm4, 21932 /* SLLI_W */ 21933 MSA128WOpnd, MSA128WOpnd, vsplat_uimm5, 21934 /* SLLV */ 21935 GPR32Opnd, GPR32Opnd, GPR32Opnd, 21936 /* SLLV_MM */ 21937 GPR32Opnd, GPR32Opnd, GPR32Opnd, 21938 /* SLL_B */ 21939 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, 21940 /* SLL_D */ 21941 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 21942 /* SLL_H */ 21943 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, 21944 /* SLL_MM */ 21945 GPR32Opnd, GPR32Opnd, uimm5, 21946 /* SLL_MMR6 */ 21947 GPR32Opnd, GPR32Opnd, uimm5, 21948 /* SLL_W */ 21949 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 21950 /* SLT */ 21951 GPR32Opnd, GPR32Opnd, GPR32Opnd, 21952 /* SLT64 */ 21953 GPR32Opnd, GPR64Opnd, GPR64Opnd, 21954 /* SLT_MM */ 21955 GPR32Opnd, GPR32Opnd, GPR32Opnd, 21956 /* SLTi */ 21957 GPR32Opnd, GPR32Opnd, simm16, 21958 /* SLTi64 */ 21959 GPR32Opnd, GPR64Opnd, simm16_64, 21960 /* SLTi_MM */ 21961 GPR32Opnd, GPR32Opnd, simm16, 21962 /* SLTiu */ 21963 GPR32Opnd, GPR32Opnd, simm16, 21964 /* SLTiu64 */ 21965 GPR32Opnd, GPR64Opnd, simm16_64, 21966 /* SLTiu_MM */ 21967 GPR32Opnd, GPR32Opnd, simm16, 21968 /* SLTu */ 21969 GPR32Opnd, GPR32Opnd, GPR32Opnd, 21970 /* SLTu64 */ 21971 GPR32Opnd, GPR64Opnd, GPR64Opnd, 21972 /* SLTu_MM */ 21973 GPR32Opnd, GPR32Opnd, GPR32Opnd, 21974 /* SNE */ 21975 GPR64Opnd, GPR64Opnd, GPR64Opnd, 21976 /* SNEi */ 21977 GPR64Opnd, GPR64Opnd, simm10_64, 21978 /* SPLATI_B */ 21979 MSA128BOpnd, MSA128BOpnd, vsplat_uimm4, 21980 /* SPLATI_D */ 21981 MSA128DOpnd, MSA128DOpnd, vsplat_uimm1, 21982 /* SPLATI_H */ 21983 MSA128HOpnd, MSA128HOpnd, vsplat_uimm3, 21984 /* SPLATI_W */ 21985 MSA128WOpnd, MSA128WOpnd, vsplat_uimm2, 21986 /* SPLAT_B */ 21987 MSA128BOpnd, MSA128BOpnd, GPR32Opnd, 21988 /* SPLAT_D */ 21989 MSA128DOpnd, MSA128DOpnd, GPR32Opnd, 21990 /* SPLAT_H */ 21991 MSA128HOpnd, MSA128HOpnd, GPR32Opnd, 21992 /* SPLAT_W */ 21993 MSA128WOpnd, MSA128WOpnd, GPR32Opnd, 21994 /* SRA */ 21995 GPR32Opnd, GPR32Opnd, uimm5, 21996 /* SRAI_B */ 21997 MSA128BOpnd, MSA128BOpnd, vsplat_uimm3, 21998 /* SRAI_D */ 21999 MSA128DOpnd, MSA128DOpnd, vsplat_uimm6, 22000 /* SRAI_H */ 22001 MSA128HOpnd, MSA128HOpnd, vsplat_uimm4, 22002 /* SRAI_W */ 22003 MSA128WOpnd, MSA128WOpnd, vsplat_uimm5, 22004 /* SRARI_B */ 22005 MSA128BOpnd, MSA128BOpnd, uimm3, 22006 /* SRARI_D */ 22007 MSA128DOpnd, MSA128DOpnd, uimm6, 22008 /* SRARI_H */ 22009 MSA128HOpnd, MSA128HOpnd, uimm4, 22010 /* SRARI_W */ 22011 MSA128WOpnd, MSA128WOpnd, uimm5, 22012 /* SRAR_B */ 22013 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, 22014 /* SRAR_D */ 22015 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 22016 /* SRAR_H */ 22017 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, 22018 /* SRAR_W */ 22019 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 22020 /* SRAV */ 22021 GPR32Opnd, GPR32Opnd, GPR32Opnd, 22022 /* SRAV_MM */ 22023 GPR32Opnd, GPR32Opnd, GPR32Opnd, 22024 /* SRA_B */ 22025 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, 22026 /* SRA_D */ 22027 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 22028 /* SRA_H */ 22029 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, 22030 /* SRA_MM */ 22031 GPR32Opnd, GPR32Opnd, uimm5, 22032 /* SRA_W */ 22033 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 22034 /* SRL */ 22035 GPR32Opnd, GPR32Opnd, uimm5, 22036 /* SRL16_MM */ 22037 GPRMM16Opnd, GPRMM16Opnd, uimm3_shift, 22038 /* SRL16_MMR6 */ 22039 GPRMM16Opnd, GPRMM16Opnd, uimm3_shift, 22040 /* SRLI_B */ 22041 MSA128BOpnd, MSA128BOpnd, vsplat_uimm3, 22042 /* SRLI_D */ 22043 MSA128DOpnd, MSA128DOpnd, vsplat_uimm6, 22044 /* SRLI_H */ 22045 MSA128HOpnd, MSA128HOpnd, vsplat_uimm4, 22046 /* SRLI_W */ 22047 MSA128WOpnd, MSA128WOpnd, vsplat_uimm5, 22048 /* SRLRI_B */ 22049 MSA128BOpnd, MSA128BOpnd, uimm3, 22050 /* SRLRI_D */ 22051 MSA128DOpnd, MSA128DOpnd, uimm6, 22052 /* SRLRI_H */ 22053 MSA128HOpnd, MSA128HOpnd, uimm4, 22054 /* SRLRI_W */ 22055 MSA128WOpnd, MSA128WOpnd, uimm5, 22056 /* SRLR_B */ 22057 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, 22058 /* SRLR_D */ 22059 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 22060 /* SRLR_H */ 22061 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, 22062 /* SRLR_W */ 22063 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 22064 /* SRLV */ 22065 GPR32Opnd, GPR32Opnd, GPR32Opnd, 22066 /* SRLV_MM */ 22067 GPR32Opnd, GPR32Opnd, GPR32Opnd, 22068 /* SRL_B */ 22069 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, 22070 /* SRL_D */ 22071 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 22072 /* SRL_H */ 22073 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, 22074 /* SRL_MM */ 22075 GPR32Opnd, GPR32Opnd, uimm5, 22076 /* SRL_W */ 22077 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 22078 /* SSNOP */ 22079 /* SSNOP_MM */ 22080 /* SSNOP_MMR6 */ 22081 /* ST_B */ 22082 MSA128BOpnd, -1, simm10, 22083 /* ST_D */ 22084 MSA128DOpnd, -1, simm10_lsl3, 22085 /* ST_H */ 22086 MSA128HOpnd, -1, simm10_lsl1, 22087 /* ST_W */ 22088 MSA128WOpnd, -1, simm10_lsl2, 22089 /* SUB */ 22090 GPR32Opnd, GPR32Opnd, GPR32Opnd, 22091 /* SUBQH_PH */ 22092 DSPROpnd, DSPROpnd, DSPROpnd, 22093 /* SUBQH_PH_MMR2 */ 22094 DSPROpnd, DSPROpnd, DSPROpnd, 22095 /* SUBQH_R_PH */ 22096 DSPROpnd, DSPROpnd, DSPROpnd, 22097 /* SUBQH_R_PH_MMR2 */ 22098 DSPROpnd, DSPROpnd, DSPROpnd, 22099 /* SUBQH_R_W */ 22100 GPR32Opnd, GPR32Opnd, GPR32Opnd, 22101 /* SUBQH_R_W_MMR2 */ 22102 GPR32Opnd, GPR32Opnd, GPR32Opnd, 22103 /* SUBQH_W */ 22104 GPR32Opnd, GPR32Opnd, GPR32Opnd, 22105 /* SUBQH_W_MMR2 */ 22106 GPR32Opnd, GPR32Opnd, GPR32Opnd, 22107 /* SUBQ_PH */ 22108 DSPROpnd, DSPROpnd, DSPROpnd, 22109 /* SUBQ_PH_MM */ 22110 DSPROpnd, DSPROpnd, DSPROpnd, 22111 /* SUBQ_S_PH */ 22112 DSPROpnd, DSPROpnd, DSPROpnd, 22113 /* SUBQ_S_PH_MM */ 22114 DSPROpnd, DSPROpnd, DSPROpnd, 22115 /* SUBQ_S_W */ 22116 GPR32Opnd, GPR32Opnd, GPR32Opnd, 22117 /* SUBQ_S_W_MM */ 22118 GPR32Opnd, GPR32Opnd, GPR32Opnd, 22119 /* SUBSUS_U_B */ 22120 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, 22121 /* SUBSUS_U_D */ 22122 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 22123 /* SUBSUS_U_H */ 22124 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, 22125 /* SUBSUS_U_W */ 22126 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 22127 /* SUBSUU_S_B */ 22128 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, 22129 /* SUBSUU_S_D */ 22130 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 22131 /* SUBSUU_S_H */ 22132 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, 22133 /* SUBSUU_S_W */ 22134 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 22135 /* SUBS_S_B */ 22136 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, 22137 /* SUBS_S_D */ 22138 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 22139 /* SUBS_S_H */ 22140 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, 22141 /* SUBS_S_W */ 22142 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 22143 /* SUBS_U_B */ 22144 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, 22145 /* SUBS_U_D */ 22146 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 22147 /* SUBS_U_H */ 22148 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, 22149 /* SUBS_U_W */ 22150 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 22151 /* SUBU16_MM */ 22152 GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd, 22153 /* SUBU16_MMR6 */ 22154 GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd, 22155 /* SUBUH_QB */ 22156 DSPROpnd, DSPROpnd, DSPROpnd, 22157 /* SUBUH_QB_MMR2 */ 22158 DSPROpnd, DSPROpnd, DSPROpnd, 22159 /* SUBUH_R_QB */ 22160 DSPROpnd, DSPROpnd, DSPROpnd, 22161 /* SUBUH_R_QB_MMR2 */ 22162 DSPROpnd, DSPROpnd, DSPROpnd, 22163 /* SUBU_MMR6 */ 22164 GPR32Opnd, GPR32Opnd, GPR32Opnd, 22165 /* SUBU_PH */ 22166 DSPROpnd, DSPROpnd, DSPROpnd, 22167 /* SUBU_PH_MMR2 */ 22168 DSPROpnd, DSPROpnd, DSPROpnd, 22169 /* SUBU_QB */ 22170 DSPROpnd, DSPROpnd, DSPROpnd, 22171 /* SUBU_QB_MM */ 22172 DSPROpnd, DSPROpnd, DSPROpnd, 22173 /* SUBU_S_PH */ 22174 DSPROpnd, DSPROpnd, DSPROpnd, 22175 /* SUBU_S_PH_MMR2 */ 22176 DSPROpnd, DSPROpnd, DSPROpnd, 22177 /* SUBU_S_QB */ 22178 DSPROpnd, DSPROpnd, DSPROpnd, 22179 /* SUBU_S_QB_MM */ 22180 DSPROpnd, DSPROpnd, DSPROpnd, 22181 /* SUBVI_B */ 22182 MSA128BOpnd, MSA128BOpnd, vsplat_uimm5, 22183 /* SUBVI_D */ 22184 MSA128DOpnd, MSA128DOpnd, vsplat_uimm5, 22185 /* SUBVI_H */ 22186 MSA128HOpnd, MSA128HOpnd, vsplat_uimm5, 22187 /* SUBVI_W */ 22188 MSA128WOpnd, MSA128WOpnd, vsplat_uimm5, 22189 /* SUBV_B */ 22190 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, 22191 /* SUBV_D */ 22192 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 22193 /* SUBV_H */ 22194 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, 22195 /* SUBV_W */ 22196 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 22197 /* SUB_MM */ 22198 GPR32Opnd, GPR32Opnd, GPR32Opnd, 22199 /* SUB_MMR6 */ 22200 GPR32Opnd, GPR32Opnd, GPR32Opnd, 22201 /* SUBu */ 22202 GPR32Opnd, GPR32Opnd, GPR32Opnd, 22203 /* SUBu_MM */ 22204 GPR32Opnd, GPR32Opnd, GPR32Opnd, 22205 /* SUXC1 */ 22206 AFGR64Opnd, -1, -1, 22207 /* SUXC164 */ 22208 FGR64Opnd, -1, -1, 22209 /* SUXC1_MM */ 22210 FGR64Opnd, -1, -1, 22211 /* SW */ 22212 GPR32Opnd, -1, simm16, 22213 /* SW16_MM */ 22214 GPRMM16OpndZero, -1, simm4, 22215 /* SW16_MMR6 */ 22216 GPRMM16OpndZero, -1, simm4, 22217 /* SW64 */ 22218 GPR64Opnd, -1, simm16, 22219 /* SWC1 */ 22220 FGR32Opnd, -1, simm16, 22221 /* SWC1_MM */ 22222 FGR32Opnd, -1, simm16, 22223 /* SWC2 */ 22224 COP2Opnd, -1, simm16, 22225 /* SWC2_MMR6 */ 22226 COP2Opnd, GPR32, simm11, 22227 /* SWC2_R6 */ 22228 COP2Opnd, -1, simm11, 22229 /* SWC3 */ 22230 COP3Opnd, -1, simm16, 22231 /* SWDSP */ 22232 DSPROpnd, -1, simm16, 22233 /* SWDSP_MM */ 22234 DSPROpnd, -1, simm16, 22235 /* SWE */ 22236 GPR32Opnd, -1, simm9, 22237 /* SWE_MM */ 22238 GPR32Opnd, -1, simm9, 22239 /* SWL */ 22240 GPR32Opnd, -1, simm16, 22241 /* SWL64 */ 22242 GPR64Opnd, -1, simm16, 22243 /* SWLE */ 22244 GPR32Opnd, -1, simm9, 22245 /* SWLE_MM */ 22246 GPR32Opnd, -1, simm9, 22247 /* SWL_MM */ 22248 GPR32Opnd, -1, simm12, 22249 /* SWM16_MM */ 22250 reglist16, -1, uimm8, 22251 /* SWM16_MMR6 */ 22252 reglist16, -1, uimm8, 22253 /* SWM32_MM */ 22254 reglist, -1, simm12, 22255 /* SWP_MM */ 22256 GPR32Opnd, GPR32Opnd, -1, simm12, 22257 /* SWR */ 22258 GPR32Opnd, -1, simm16, 22259 /* SWR64 */ 22260 GPR64Opnd, -1, simm16, 22261 /* SWRE */ 22262 GPR32Opnd, -1, simm9, 22263 /* SWRE_MM */ 22264 GPR32Opnd, -1, simm9, 22265 /* SWR_MM */ 22266 GPR32Opnd, -1, simm12, 22267 /* SWSP_MM */ 22268 GPR32Opnd, -1, simm5, 22269 /* SWSP_MMR6 */ 22270 GPR32Opnd, -1, simm5, 22271 /* SWXC1 */ 22272 FGR32Opnd, -1, -1, 22273 /* SWXC1_MM */ 22274 FGR32Opnd, -1, -1, 22275 /* SW_MM */ 22276 GPR32Opnd, -1, simm16, 22277 /* SW_MMR6 */ 22278 GPR32Opnd, -1, simm16, 22279 /* SYNC */ 22280 uimm5, 22281 /* SYNCI */ 22282 -1, simm16, 22283 /* SYNCI_MM */ 22284 -1, simm16, 22285 /* SYNCI_MMR6 */ 22286 -1, simm16, 22287 /* SYNC_MM */ 22288 uimm5, 22289 /* SYNC_MMR6 */ 22290 uimm5, 22291 /* SYSCALL */ 22292 uimm20, 22293 /* SYSCALL_MM */ 22294 uimm10, 22295 /* Save16 */ 22296 /* SaveX16 */ 22297 /* SbRxRyOffMemX16 */ 22298 CPU16Regs, CPU16Regs, simm16, 22299 /* SebRx16 */ 22300 CPU16Regs, CPU16Regs, 22301 /* SehRx16 */ 22302 CPU16Regs, CPU16Regs, 22303 /* ShRxRyOffMemX16 */ 22304 CPU16Regs, CPU16Regs, simm16, 22305 /* SllX16 */ 22306 CPU16Regs, CPU16Regs, uimm5, 22307 /* SllvRxRy16 */ 22308 CPU16Regs, CPU16Regs, CPU16Regs, 22309 /* SltRxRy16 */ 22310 CPU16Regs, CPU16Regs, 22311 /* SltiRxImm16 */ 22312 CPU16Regs, simm16, 22313 /* SltiRxImmX16 */ 22314 CPU16Regs, simm16, 22315 /* SltiuRxImm16 */ 22316 CPU16Regs, simm16, 22317 /* SltiuRxImmX16 */ 22318 CPU16Regs, simm16, 22319 /* SltuRxRy16 */ 22320 CPU16Regs, CPU16Regs, 22321 /* SraX16 */ 22322 CPU16Regs, CPU16Regs, uimm5, 22323 /* SravRxRy16 */ 22324 CPU16Regs, CPU16Regs, CPU16Regs, 22325 /* SrlX16 */ 22326 CPU16Regs, CPU16Regs, uimm5, 22327 /* SrlvRxRy16 */ 22328 CPU16Regs, CPU16Regs, CPU16Regs, 22329 /* SubuRxRyRz16 */ 22330 CPU16Regs, CPU16Regs, CPU16Regs, 22331 /* SwRxRyOffMemX16 */ 22332 CPU16Regs, CPU16Regs, simm16, 22333 /* SwRxSpImmX16 */ 22334 CPU16Regs, CPU16RegsPlusSP, simm16, 22335 /* TEQ */ 22336 GPR32Opnd, GPR32Opnd, uimm10, 22337 /* TEQI */ 22338 GPR32Opnd, simm16, 22339 /* TEQI_MM */ 22340 GPR32Opnd, simm16, 22341 /* TEQ_MM */ 22342 GPR32Opnd, GPR32Opnd, uimm4, 22343 /* TGE */ 22344 GPR32Opnd, GPR32Opnd, uimm10, 22345 /* TGEI */ 22346 GPR32Opnd, simm16, 22347 /* TGEIU */ 22348 GPR32Opnd, simm16, 22349 /* TGEIU_MM */ 22350 GPR32Opnd, simm16, 22351 /* TGEI_MM */ 22352 GPR32Opnd, simm16, 22353 /* TGEU */ 22354 GPR32Opnd, GPR32Opnd, uimm10, 22355 /* TGEU_MM */ 22356 GPR32Opnd, GPR32Opnd, uimm4, 22357 /* TGE_MM */ 22358 GPR32Opnd, GPR32Opnd, uimm4, 22359 /* TLBGINV */ 22360 /* TLBGINVF */ 22361 /* TLBGINVF_MM */ 22362 /* TLBGINV_MM */ 22363 /* TLBGP */ 22364 /* TLBGP_MM */ 22365 /* TLBGR */ 22366 /* TLBGR_MM */ 22367 /* TLBGWI */ 22368 /* TLBGWI_MM */ 22369 /* TLBGWR */ 22370 /* TLBGWR_MM */ 22371 /* TLBINV */ 22372 /* TLBINVF */ 22373 /* TLBINVF_MMR6 */ 22374 /* TLBINV_MMR6 */ 22375 /* TLBP */ 22376 /* TLBP_MM */ 22377 /* TLBR */ 22378 /* TLBR_MM */ 22379 /* TLBWI */ 22380 /* TLBWI_MM */ 22381 /* TLBWR */ 22382 /* TLBWR_MM */ 22383 /* TLT */ 22384 GPR32Opnd, GPR32Opnd, uimm10, 22385 /* TLTI */ 22386 GPR32Opnd, simm16, 22387 /* TLTIU_MM */ 22388 GPR32Opnd, simm16, 22389 /* TLTI_MM */ 22390 GPR32Opnd, simm16, 22391 /* TLTU */ 22392 GPR32Opnd, GPR32Opnd, uimm10, 22393 /* TLTU_MM */ 22394 GPR32Opnd, GPR32Opnd, uimm4, 22395 /* TLT_MM */ 22396 GPR32Opnd, GPR32Opnd, uimm4, 22397 /* TNE */ 22398 GPR32Opnd, GPR32Opnd, uimm10, 22399 /* TNEI */ 22400 GPR32Opnd, simm16, 22401 /* TNEI_MM */ 22402 GPR32Opnd, simm16, 22403 /* TNE_MM */ 22404 GPR32Opnd, GPR32Opnd, uimm4, 22405 /* TRUNC_L_D64 */ 22406 FGR64Opnd, FGR64Opnd, 22407 /* TRUNC_L_D_MMR6 */ 22408 FGR64Opnd, FGR64Opnd, 22409 /* TRUNC_L_S */ 22410 FGR64Opnd, FGR32Opnd, 22411 /* TRUNC_L_S_MMR6 */ 22412 FGR64Opnd, FGR32Opnd, 22413 /* TRUNC_W_D32 */ 22414 FGR32Opnd, AFGR64Opnd, 22415 /* TRUNC_W_D64 */ 22416 FGR32Opnd, FGR64Opnd, 22417 /* TRUNC_W_D_MMR6 */ 22418 FGR32Opnd, FGR64Opnd, 22419 /* TRUNC_W_MM */ 22420 FGR32Opnd, AFGR64Opnd, 22421 /* TRUNC_W_S */ 22422 FGR32Opnd, FGR32Opnd, 22423 /* TRUNC_W_S_MM */ 22424 FGR32Opnd, FGR32Opnd, 22425 /* TRUNC_W_S_MMR6 */ 22426 FGR32Opnd, FGR32Opnd, 22427 /* TTLTIU */ 22428 GPR32Opnd, simm16, 22429 /* UDIV */ 22430 GPR32Opnd, GPR32Opnd, 22431 /* UDIV_MM */ 22432 GPR32Opnd, GPR32Opnd, 22433 /* V3MULU */ 22434 GPR64Opnd, GPR64Opnd, GPR64Opnd, 22435 /* VMM0 */ 22436 GPR64Opnd, GPR64Opnd, GPR64Opnd, 22437 /* VMULU */ 22438 GPR64Opnd, GPR64Opnd, GPR64Opnd, 22439 /* VSHF_B */ 22440 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, 22441 /* VSHF_D */ 22442 MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, 22443 /* VSHF_H */ 22444 MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, 22445 /* VSHF_W */ 22446 MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, 22447 /* WAIT */ 22448 /* WAIT_MM */ 22449 uimm10, 22450 /* WAIT_MMR6 */ 22451 uimm10, 22452 /* WRDSP */ 22453 GPR32Opnd, uimm10, 22454 /* WRDSP_MM */ 22455 GPR32Opnd, uimm7, 22456 /* WRPGPR_MMR6 */ 22457 GPR32Opnd, GPR32Opnd, 22458 /* WSBH */ 22459 GPR32Opnd, GPR32Opnd, 22460 /* WSBH_MM */ 22461 GPR32Opnd, GPR32Opnd, 22462 /* WSBH_MMR6 */ 22463 GPR32Opnd, GPR32Opnd, 22464 /* XOR */ 22465 GPR32Opnd, GPR32Opnd, GPR32Opnd, 22466 /* XOR16_MM */ 22467 GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd, 22468 /* XOR16_MMR6 */ 22469 GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd, 22470 /* XOR64 */ 22471 GPR64Opnd, GPR64Opnd, GPR64Opnd, 22472 /* XORI_B */ 22473 MSA128BOpnd, MSA128BOpnd, vsplat_uimm8, 22474 /* XORI_MMR6 */ 22475 GPR32Opnd, GPR32Opnd, uimm16, 22476 /* XOR_MM */ 22477 GPR32Opnd, GPR32Opnd, GPR32Opnd, 22478 /* XOR_MMR6 */ 22479 GPR32Opnd, GPR32Opnd, GPR32Opnd, 22480 /* XOR_V */ 22481 MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, 22482 /* XORi */ 22483 GPR32Opnd, GPR32Opnd, uimm16, 22484 /* XORi64 */ 22485 GPR64Opnd, GPR64Opnd, uimm16_64, 22486 /* XORi_MM */ 22487 GPR32Opnd, GPR32Opnd, uimm16, 22488 /* XorRxRxRy16 */ 22489 CPU16Regs, CPU16Regs, CPU16Regs, 22490 /* YIELD */ 22491 GPR32Opnd, GPR32Opnd, 22492 }; 22493 return OpcodeOperandTypes[Offsets[Opcode] + OpIdx]; 22494} 22495} // end namespace Mips 22496} // end namespace llvm 22497#endif // GET_INSTRINFO_OPERAND_TYPE 22498 22499#ifdef GET_INSTRINFO_MEM_OPERAND_SIZE 22500#undef GET_INSTRINFO_MEM_OPERAND_SIZE 22501namespace llvm { 22502namespace Mips { 22503LLVM_READONLY 22504static int getMemOperandSize(int OpType) { 22505 switch (OpType) { 22506 default: return 0; 22507 } 22508} 22509} // end namespace Mips 22510} // end namespace llvm 22511#endif // GET_INSTRINFO_MEM_OPERAND_SIZE 22512 22513#ifdef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP 22514#undef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP 22515namespace llvm { 22516namespace Mips { 22517LLVM_READONLY static unsigned 22518getLogicalOperandSize(uint16_t Opcode, uint16_t LogicalOpIdx) { 22519 return LogicalOpIdx; 22520} 22521LLVM_READONLY static inline unsigned 22522getLogicalOperandIdx(uint16_t Opcode, uint16_t LogicalOpIdx) { 22523 auto S = 0U; 22524 for (auto i = 0U; i < LogicalOpIdx; ++i) 22525 S += getLogicalOperandSize(Opcode, i); 22526 return S; 22527} 22528} // end namespace Mips 22529} // end namespace llvm 22530#endif // GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP 22531 22532#ifdef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP 22533#undef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP 22534namespace llvm { 22535namespace Mips { 22536LLVM_READONLY static int 22537getLogicalOperandType(uint16_t Opcode, uint16_t LogicalOpIdx) { 22538 return -1; 22539} 22540} // end namespace Mips 22541} // end namespace llvm 22542#endif // GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP 22543 22544#ifdef GET_INSTRINFO_MC_HELPER_DECLS 22545#undef GET_INSTRINFO_MC_HELPER_DECLS 22546 22547namespace llvm { 22548class MCInst; 22549class FeatureBitset; 22550 22551namespace Mips_MC { 22552 22553void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features); 22554 22555} // end namespace Mips_MC 22556} // end namespace llvm 22557 22558#endif // GET_INSTRINFO_MC_HELPER_DECLS 22559 22560#ifdef GET_INSTRINFO_MC_HELPERS 22561#undef GET_INSTRINFO_MC_HELPERS 22562 22563namespace llvm { 22564namespace Mips_MC { 22565 22566} // end namespace Mips_MC 22567} // end namespace llvm 22568 22569#endif // GET_GENISTRINFO_MC_HELPERS 22570 22571#ifdef ENABLE_INSTR_PREDICATE_VERIFIER 22572#undef ENABLE_INSTR_PREDICATE_VERIFIER 22573#include <sstream> 22574 22575namespace llvm { 22576namespace Mips_MC { 22577 22578// Bits for subtarget features that participate in instruction matching. 22579enum SubtargetFeatureBits : uint8_t { 22580 Feature_HasMips2Bit = 11, 22581 Feature_HasMips3_32Bit = 18, 22582 Feature_HasMips3_32r2Bit = 19, 22583 Feature_HasMips3Bit = 12, 22584 Feature_NotMips3Bit = 47, 22585 Feature_HasMips4_32Bit = 20, 22586 Feature_NotMips4_32Bit = 49, 22587 Feature_HasMips4_32r2Bit = 21, 22588 Feature_HasMips5_32r2Bit = 22, 22589 Feature_HasMips32Bit = 13, 22590 Feature_HasMips32r2Bit = 14, 22591 Feature_HasMips32r5Bit = 15, 22592 Feature_HasMips32r6Bit = 16, 22593 Feature_NotMips32r6Bit = 48, 22594 Feature_IsGP64bitBit = 33, 22595 Feature_IsGP32bitBit = 32, 22596 Feature_IsPTR64bitBit = 37, 22597 Feature_IsPTR32bitBit = 36, 22598 Feature_HasMips64Bit = 23, 22599 Feature_NotMips64Bit = 50, 22600 Feature_HasMips64r2Bit = 24, 22601 Feature_HasMips64r5Bit = 25, 22602 Feature_HasMips64r6Bit = 26, 22603 Feature_NotMips64r6Bit = 51, 22604 Feature_InMips16ModeBit = 30, 22605 Feature_NotInMips16ModeBit = 46, 22606 Feature_HasCnMipsBit = 1, 22607 Feature_NotCnMipsBit = 42, 22608 Feature_HasCnMipsPBit = 2, 22609 Feature_NotCnMipsPBit = 43, 22610 Feature_IsSym32Bit = 39, 22611 Feature_IsSym64Bit = 40, 22612 Feature_HasStdEncBit = 27, 22613 Feature_InMicroMipsBit = 29, 22614 Feature_NotInMicroMipsBit = 45, 22615 Feature_HasEVABit = 6, 22616 Feature_HasMSABit = 8, 22617 Feature_HasMadd4Bit = 10, 22618 Feature_HasMTBit = 9, 22619 Feature_UseIndirectJumpsHazardBit = 52, 22620 Feature_NoIndirectJumpGuardsBit = 41, 22621 Feature_HasCRCBit = 0, 22622 Feature_HasVirtBit = 28, 22623 Feature_HasGINVBit = 7, 22624 Feature_IsFP64bitBit = 31, 22625 Feature_NotFP64bitBit = 44, 22626 Feature_IsSingleFloatBit = 38, 22627 Feature_IsNotSingleFloatBit = 34, 22628 Feature_IsNotSoftFloatBit = 35, 22629 Feature_HasMips3DBit = 17, 22630 Feature_HasDSPBit = 3, 22631 Feature_HasDSPR2Bit = 4, 22632 Feature_HasDSPR3Bit = 5, 22633}; 22634 22635#ifndef NDEBUG 22636static const char *SubtargetFeatureNames[] = { 22637 "Feature_HasCRC", 22638 "Feature_HasCnMips", 22639 "Feature_HasCnMipsP", 22640 "Feature_HasDSP", 22641 "Feature_HasDSPR2", 22642 "Feature_HasDSPR3", 22643 "Feature_HasEVA", 22644 "Feature_HasGINV", 22645 "Feature_HasMSA", 22646 "Feature_HasMT", 22647 "Feature_HasMadd4", 22648 "Feature_HasMips2", 22649 "Feature_HasMips3", 22650 "Feature_HasMips32", 22651 "Feature_HasMips32r2", 22652 "Feature_HasMips32r5", 22653 "Feature_HasMips32r6", 22654 "Feature_HasMips3D", 22655 "Feature_HasMips3_32", 22656 "Feature_HasMips3_32r2", 22657 "Feature_HasMips4_32", 22658 "Feature_HasMips4_32r2", 22659 "Feature_HasMips5_32r2", 22660 "Feature_HasMips64", 22661 "Feature_HasMips64r2", 22662 "Feature_HasMips64r5", 22663 "Feature_HasMips64r6", 22664 "Feature_HasStdEnc", 22665 "Feature_HasVirt", 22666 "Feature_InMicroMips", 22667 "Feature_InMips16Mode", 22668 "Feature_IsFP64bit", 22669 "Feature_IsGP32bit", 22670 "Feature_IsGP64bit", 22671 "Feature_IsNotSingleFloat", 22672 "Feature_IsNotSoftFloat", 22673 "Feature_IsPTR32bit", 22674 "Feature_IsPTR64bit", 22675 "Feature_IsSingleFloat", 22676 "Feature_IsSym32", 22677 "Feature_IsSym64", 22678 "Feature_NoIndirectJumpGuards", 22679 "Feature_NotCnMips", 22680 "Feature_NotCnMipsP", 22681 "Feature_NotFP64bit", 22682 "Feature_NotInMicroMips", 22683 "Feature_NotInMips16Mode", 22684 "Feature_NotMips3", 22685 "Feature_NotMips32r6", 22686 "Feature_NotMips4_32", 22687 "Feature_NotMips64", 22688 "Feature_NotMips64r6", 22689 "Feature_UseIndirectJumpsHazard", 22690 nullptr 22691}; 22692 22693#endif // NDEBUG 22694 22695FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) { 22696 FeatureBitset Features; 22697 if (FB[Mips::FeatureMips2]) 22698 Features.set(Feature_HasMips2Bit); 22699 if (FB[Mips::FeatureMips3_32]) 22700 Features.set(Feature_HasMips3_32Bit); 22701 if (FB[Mips::FeatureMips3_32r2]) 22702 Features.set(Feature_HasMips3_32r2Bit); 22703 if (FB[Mips::FeatureMips3]) 22704 Features.set(Feature_HasMips3Bit); 22705 if (!FB[Mips::FeatureMips3]) 22706 Features.set(Feature_NotMips3Bit); 22707 if (FB[Mips::FeatureMips4_32]) 22708 Features.set(Feature_HasMips4_32Bit); 22709 if (!FB[Mips::FeatureMips4_32]) 22710 Features.set(Feature_NotMips4_32Bit); 22711 if (FB[Mips::FeatureMips4_32r2]) 22712 Features.set(Feature_HasMips4_32r2Bit); 22713 if (FB[Mips::FeatureMips5_32r2]) 22714 Features.set(Feature_HasMips5_32r2Bit); 22715 if (FB[Mips::FeatureMips32]) 22716 Features.set(Feature_HasMips32Bit); 22717 if (FB[Mips::FeatureMips32r2]) 22718 Features.set(Feature_HasMips32r2Bit); 22719 if (FB[Mips::FeatureMips32r5]) 22720 Features.set(Feature_HasMips32r5Bit); 22721 if (FB[Mips::FeatureMips32r6]) 22722 Features.set(Feature_HasMips32r6Bit); 22723 if (!FB[Mips::FeatureMips32r6]) 22724 Features.set(Feature_NotMips32r6Bit); 22725 if (FB[Mips::FeatureGP64Bit]) 22726 Features.set(Feature_IsGP64bitBit); 22727 if (!FB[Mips::FeatureGP64Bit]) 22728 Features.set(Feature_IsGP32bitBit); 22729 if (FB[Mips::FeaturePTR64Bit]) 22730 Features.set(Feature_IsPTR64bitBit); 22731 if (!FB[Mips::FeaturePTR64Bit]) 22732 Features.set(Feature_IsPTR32bitBit); 22733 if (FB[Mips::FeatureMips64]) 22734 Features.set(Feature_HasMips64Bit); 22735 if (!FB[Mips::FeatureMips64]) 22736 Features.set(Feature_NotMips64Bit); 22737 if (FB[Mips::FeatureMips64r2]) 22738 Features.set(Feature_HasMips64r2Bit); 22739 if (FB[Mips::FeatureMips64r5]) 22740 Features.set(Feature_HasMips64r5Bit); 22741 if (FB[Mips::FeatureMips64r6]) 22742 Features.set(Feature_HasMips64r6Bit); 22743 if (!FB[Mips::FeatureMips64r6]) 22744 Features.set(Feature_NotMips64r6Bit); 22745 if (FB[Mips::FeatureMips16]) 22746 Features.set(Feature_InMips16ModeBit); 22747 if (!FB[Mips::FeatureMips16]) 22748 Features.set(Feature_NotInMips16ModeBit); 22749 if (FB[Mips::FeatureCnMips]) 22750 Features.set(Feature_HasCnMipsBit); 22751 if (!FB[Mips::FeatureCnMips]) 22752 Features.set(Feature_NotCnMipsBit); 22753 if (FB[Mips::FeatureCnMipsP]) 22754 Features.set(Feature_HasCnMipsPBit); 22755 if (!FB[Mips::FeatureCnMipsP]) 22756 Features.set(Feature_NotCnMipsPBit); 22757 if (FB[Mips::FeatureSym32]) 22758 Features.set(Feature_IsSym32Bit); 22759 if (!FB[Mips::FeatureSym32]) 22760 Features.set(Feature_IsSym64Bit); 22761 if (!FB[Mips::FeatureMips16]) 22762 Features.set(Feature_HasStdEncBit); 22763 if (FB[Mips::FeatureMicroMips]) 22764 Features.set(Feature_InMicroMipsBit); 22765 if (!FB[Mips::FeatureMicroMips]) 22766 Features.set(Feature_NotInMicroMipsBit); 22767 if (FB[Mips::FeatureEVA]) 22768 Features.set(Feature_HasEVABit); 22769 if (FB[Mips::FeatureMSA]) 22770 Features.set(Feature_HasMSABit); 22771 if (!FB[Mips::FeatureNoMadd4]) 22772 Features.set(Feature_HasMadd4Bit); 22773 if (FB[Mips::FeatureMT]) 22774 Features.set(Feature_HasMTBit); 22775 if (FB[Mips::FeatureUseIndirectJumpsHazard]) 22776 Features.set(Feature_UseIndirectJumpsHazardBit); 22777 if (!FB[Mips::FeatureUseIndirectJumpsHazard]) 22778 Features.set(Feature_NoIndirectJumpGuardsBit); 22779 if (FB[Mips::FeatureCRC]) 22780 Features.set(Feature_HasCRCBit); 22781 if (FB[Mips::FeatureVirt]) 22782 Features.set(Feature_HasVirtBit); 22783 if (FB[Mips::FeatureGINV]) 22784 Features.set(Feature_HasGINVBit); 22785 if (FB[Mips::FeatureFP64Bit]) 22786 Features.set(Feature_IsFP64bitBit); 22787 if (!FB[Mips::FeatureFP64Bit]) 22788 Features.set(Feature_NotFP64bitBit); 22789 if (FB[Mips::FeatureSingleFloat]) 22790 Features.set(Feature_IsSingleFloatBit); 22791 if (!FB[Mips::FeatureSingleFloat]) 22792 Features.set(Feature_IsNotSingleFloatBit); 22793 if (!FB[Mips::FeatureSoftFloat]) 22794 Features.set(Feature_IsNotSoftFloatBit); 22795 if (FB[Mips::FeatureMips3D]) 22796 Features.set(Feature_HasMips3DBit); 22797 if (FB[Mips::FeatureDSP]) 22798 Features.set(Feature_HasDSPBit); 22799 if (FB[Mips::FeatureDSPR2]) 22800 Features.set(Feature_HasDSPR2Bit); 22801 if (FB[Mips::FeatureDSPR3]) 22802 Features.set(Feature_HasDSPR3Bit); 22803 return Features; 22804} 22805 22806#ifndef NDEBUG 22807// Feature bitsets. 22808enum : uint8_t { 22809 CEFBS_None, 22810 CEFBS_HasCnMips, 22811 CEFBS_HasCnMipsP, 22812 CEFBS_HasDSP, 22813 CEFBS_HasDSPR2, 22814 CEFBS_HasMSA, 22815 CEFBS_HasMT, 22816 CEFBS_InMicroMips, 22817 CEFBS_InMips16Mode, 22818 CEFBS_IsGP32bit, 22819 CEFBS_IsGP64bit, 22820 CEFBS_IsNotSoftFloat, 22821 CEFBS_NotCnMips, 22822 CEFBS_NotInMips16Mode, 22823 CEFBS_HasDSP_NotInMicroMips, 22824 CEFBS_HasStdEnc_HasMSA, 22825 CEFBS_HasStdEnc_HasMips32, 22826 CEFBS_HasStdEnc_HasMips32r6, 22827 CEFBS_HasStdEnc_HasMips64, 22828 CEFBS_HasStdEnc_HasMips64r6, 22829 CEFBS_HasStdEnc_IsNotSoftFloat, 22830 CEFBS_HasStdEnc_NotInMicroMips, 22831 CEFBS_HasStdEnc_NotMips3, 22832 CEFBS_HasStdEnc_NotMips4_32, 22833 CEFBS_InMicroMips_HasDSP, 22834 CEFBS_InMicroMips_HasDSPR2, 22835 CEFBS_InMicroMips_HasDSPR3, 22836 CEFBS_InMicroMips_HasEVA, 22837 CEFBS_InMicroMips_HasMips32r6, 22838 CEFBS_InMicroMips_IsNotSoftFloat, 22839 CEFBS_InMicroMips_NotMips32r6, 22840 CEFBS_IsFP64bit_IsNotSoftFloat, 22841 CEFBS_IsGP32bit_NotInMicroMips, 22842 CEFBS_NotFP64bit_IsNotSoftFloat, 22843 CEFBS_NotInMips16Mode_HasDSP, 22844 CEFBS_NotInMips16Mode_IsGP64bit, 22845 CEFBS_NotInMips16Mode_IsNotSoftFloat, 22846 CEFBS_NotInMips16Mode_IsPTR64bit, 22847 CEFBS_HasMips3_NotMips64r6_NotCnMips, 22848 CEFBS_HasMips64_HasCnMips_NotInMicroMips, 22849 CEFBS_HasStdEnc_HasMSA_HasMips64, 22850 CEFBS_HasStdEnc_HasMT_NotInMicroMips, 22851 CEFBS_HasStdEnc_HasMips2_NotInMicroMips, 22852 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, 22853 CEFBS_HasStdEnc_HasMips32_NotInMicroMips, 22854 CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, 22855 CEFBS_HasStdEnc_HasMips32r5_NotInMicroMips, 22856 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, 22857 CEFBS_HasStdEnc_HasMips3_32_NotInMicroMips, 22858 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, 22859 CEFBS_HasStdEnc_HasMips64r5_HasVirt, 22860 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, 22861 CEFBS_HasStdEnc_IsFP64bit_NotMips4_32, 22862 CEFBS_HasStdEnc_IsGP64bit_HasMips3, 22863 CEFBS_HasStdEnc_IsGP64bit_HasMips32r2, 22864 CEFBS_HasStdEnc_IsGP64bit_HasMips32r6, 22865 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, 22866 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, 22867 CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat, 22868 CEFBS_HasStdEnc_NotFP64bit_NotMips4_32, 22869 CEFBS_HasStdEnc_NotInMicroMips_NoIndirectJumpGuards, 22870 CEFBS_HasStdEnc_NotInMips16Mode_NotInMicroMips, 22871 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, 22872 CEFBS_InMicroMips_HasMips32r5_HasVirt, 22873 CEFBS_InMicroMips_HasMips32r6_HasGINV, 22874 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, 22875 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, 22876 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, 22877 CEFBS_InMicroMips_NotMips32r6_HasDSP, 22878 CEFBS_InMicroMips_NotMips32r6_HasEVA, 22879 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, 22880 CEFBS_InMicroMips_NotMips32r6_NotMips64r6, 22881 CEFBS_NotInMips16Mode_IsFP64bit_IsNotSoftFloat, 22882 CEFBS_NotInMips16Mode_IsGP64bit_NotInMicroMips, 22883 CEFBS_NotInMips16Mode_IsPTR64bit_NoIndirectJumpGuards, 22884 CEFBS_NotInMips16Mode_IsPTR64bit_NotInMicroMips, 22885 CEFBS_NotInMips16Mode_IsPTR64bit_UseIndirectJumpsHazard, 22886 CEFBS_NotInMips16Mode_NotFP64bit_IsNotSoftFloat, 22887 CEFBS_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, 22888 CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, 22889 CEFBS_HasStdEnc_HasMips2_NotCnMips_NotInMicroMips, 22890 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, 22891 CEFBS_HasStdEnc_HasMips3_IsNotSoftFloat_NotInMicroMips, 22892 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, 22893 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, 22894 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, 22895 CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6, 22896 CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, 22897 CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, 22898 CEFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips, 22899 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, 22900 CEFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, 22901 CEFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, 22902 CEFBS_HasStdEnc_HasMips64_NotMips64r6_NotInMicroMips, 22903 CEFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips, 22904 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, 22905 CEFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips, 22906 CEFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips, 22907 CEFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips, 22908 CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, 22909 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, 22910 CEFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, 22911 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, 22912 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, 22913 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, 22914 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, 22915 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, 22916 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, 22917 CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, 22918 CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, 22919 CEFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips, 22920 CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, 22921 CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, 22922 CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, 22923 CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, 22924 CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, 22925 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, 22926 CEFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, 22927 CEFBS_HasStdEnc_IsFP64bit_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, 22928 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, 22929 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat, 22930 CEFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips, 22931 CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, 22932 CEFBS_HasStdEnc_NotFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, 22933 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, 22934 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, 22935 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotCnMips_NotInMicroMips, 22936 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, 22937 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, 22938 CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, 22939 CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, 22940 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, 22941 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, 22942 CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, 22943 CEFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, 22944 CEFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, 22945 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, 22946 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, 22947 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, 22948 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, 22949 CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, 22950 CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, 22951 CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, 22952 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, 22953 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, 22954 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, 22955 CEFBS_HasStdEnc_IsFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, 22956 CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, 22957 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, 22958 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, 22959 CEFBS_HasStdEnc_NotFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, 22960 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, 22961 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, 22962 CEFBS_HasStdEnc_IsGP64bit_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, 22963 CEFBS_HasStdEnc_IsPTR64bit_HasMips3_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, 22964 CEFBS_HasStdEnc_IsPTR64bit_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, 22965 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, 22966 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, 22967}; 22968 22969static constexpr FeatureBitset FeatureBitsets[] = { 22970 {}, // CEFBS_None 22971 {Feature_HasCnMipsBit, }, 22972 {Feature_HasCnMipsPBit, }, 22973 {Feature_HasDSPBit, }, 22974 {Feature_HasDSPR2Bit, }, 22975 {Feature_HasMSABit, }, 22976 {Feature_HasMTBit, }, 22977 {Feature_InMicroMipsBit, }, 22978 {Feature_InMips16ModeBit, }, 22979 {Feature_IsGP32bitBit, }, 22980 {Feature_IsGP64bitBit, }, 22981 {Feature_IsNotSoftFloatBit, }, 22982 {Feature_NotCnMipsBit, }, 22983 {Feature_NotInMips16ModeBit, }, 22984 {Feature_HasDSPBit, Feature_NotInMicroMipsBit, }, 22985 {Feature_HasStdEncBit, Feature_HasMSABit, }, 22986 {Feature_HasStdEncBit, Feature_HasMips32Bit, }, 22987 {Feature_HasStdEncBit, Feature_HasMips32r6Bit, }, 22988 {Feature_HasStdEncBit, Feature_HasMips64Bit, }, 22989 {Feature_HasStdEncBit, Feature_HasMips64r6Bit, }, 22990 {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, }, 22991 {Feature_HasStdEncBit, Feature_NotInMicroMipsBit, }, 22992 {Feature_HasStdEncBit, Feature_NotMips3Bit, }, 22993 {Feature_HasStdEncBit, Feature_NotMips4_32Bit, }, 22994 {Feature_InMicroMipsBit, Feature_HasDSPBit, }, 22995 {Feature_InMicroMipsBit, Feature_HasDSPR2Bit, }, 22996 {Feature_InMicroMipsBit, Feature_HasDSPR3Bit, }, 22997 {Feature_InMicroMipsBit, Feature_HasEVABit, }, 22998 {Feature_InMicroMipsBit, Feature_HasMips32r6Bit, }, 22999 {Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, }, 23000 {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, }, 23001 {Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, }, 23002 {Feature_IsGP32bitBit, Feature_NotInMicroMipsBit, }, 23003 {Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, }, 23004 {Feature_NotInMips16ModeBit, Feature_HasDSPBit, }, 23005 {Feature_NotInMips16ModeBit, Feature_IsGP64bitBit, }, 23006 {Feature_NotInMips16ModeBit, Feature_IsNotSoftFloatBit, }, 23007 {Feature_NotInMips16ModeBit, Feature_IsPTR64bitBit, }, 23008 {Feature_HasMips3Bit, Feature_NotMips64r6Bit, Feature_NotCnMipsBit, }, 23009 {Feature_HasMips64Bit, Feature_HasCnMipsBit, Feature_NotInMicroMipsBit, }, 23010 {Feature_HasStdEncBit, Feature_HasMSABit, Feature_HasMips64Bit, }, 23011 {Feature_HasStdEncBit, Feature_HasMTBit, Feature_NotInMicroMipsBit, }, 23012 {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotInMicroMipsBit, }, 23013 {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotInMicroMipsBit, }, 23014 {Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotInMicroMipsBit, }, 23015 {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotInMicroMipsBit, }, 23016 {Feature_HasStdEncBit, Feature_HasMips32r5Bit, Feature_NotInMicroMipsBit, }, 23017 {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_NotInMicroMipsBit, }, 23018 {Feature_HasStdEncBit, Feature_HasMips3_32Bit, Feature_NotInMicroMipsBit, }, 23019 {Feature_HasStdEncBit, Feature_HasMips64r2Bit, Feature_NotInMicroMipsBit, }, 23020 {Feature_HasStdEncBit, Feature_HasMips64r5Bit, Feature_HasVirtBit, }, 23021 {Feature_HasStdEncBit, Feature_HasMips64r6Bit, Feature_NotInMicroMipsBit, }, 23022 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotMips4_32Bit, }, 23023 {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips3Bit, }, 23024 {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips32r2Bit, }, 23025 {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips32r6Bit, }, 23026 {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips64r6Bit, }, 23027 {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 23028 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, }, 23029 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotMips4_32Bit, }, 23030 {Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, }, 23031 {Feature_HasStdEncBit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, }, 23032 {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, 23033 {Feature_InMicroMipsBit, Feature_HasMips32r5Bit, Feature_HasVirtBit, }, 23034 {Feature_InMicroMipsBit, Feature_HasMips32r6Bit, Feature_HasGINVBit, }, 23035 {Feature_InMicroMipsBit, Feature_HasMips32r6Bit, Feature_IsNotSoftFloatBit, }, 23036 {Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, }, 23037 {Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, }, 23038 {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_HasDSPBit, }, 23039 {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_HasEVABit, }, 23040 {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, }, 23041 {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, 23042 {Feature_NotInMips16ModeBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, }, 23043 {Feature_NotInMips16ModeBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, }, 23044 {Feature_NotInMips16ModeBit, Feature_IsPTR64bitBit, Feature_NoIndirectJumpGuardsBit, }, 23045 {Feature_NotInMips16ModeBit, Feature_IsPTR64bitBit, Feature_NotInMicroMipsBit, }, 23046 {Feature_NotInMips16ModeBit, Feature_IsPTR64bitBit, Feature_UseIndirectJumpsHazardBit, }, 23047 {Feature_NotInMips16ModeBit, Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, }, 23048 {Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, }, 23049 {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 23050 {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotCnMipsBit, Feature_NotInMicroMipsBit, }, 23051 {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, 23052 {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 23053 {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, 23054 {Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, 23055 {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_HasEVABit, Feature_NotInMicroMipsBit, }, 23056 {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, 23057 {Feature_HasStdEncBit, Feature_HasMips32r5Bit, Feature_HasVirtBit, Feature_NotInMicroMipsBit, }, 23058 {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_HasCRCBit, Feature_NotInMicroMipsBit, }, 23059 {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_HasGINVBit, Feature_NotInMicroMipsBit, }, 23060 {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 23061 {Feature_HasStdEncBit, Feature_HasMips3_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 23062 {Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 23063 {Feature_HasStdEncBit, Feature_HasMips64Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, 23064 {Feature_HasStdEncBit, Feature_HasMips64r6Bit, Feature_HasCRCBit, Feature_NotInMicroMipsBit, }, 23065 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 23066 {Feature_HasStdEncBit, Feature_IsGP32bitBit, Feature_HasMips32r6Bit, Feature_NotInMicroMipsBit, }, 23067 {Feature_HasStdEncBit, Feature_IsPTR32bitBit, Feature_HasMips32r6Bit, Feature_NotInMicroMipsBit, }, 23068 {Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_HasMips64r6Bit, Feature_NotInMicroMipsBit, }, 23069 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 23070 {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, 23071 {Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_HasMips32r6Bit, Feature_IsNotSoftFloatBit, }, 23072 {Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, }, 23073 {Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, }, 23074 {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, }, 23075 {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, 23076 {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, 23077 {Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, 23078 {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, }, 23079 {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, }, 23080 {Feature_HasStdEncBit, Feature_HasMips3_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, 23081 {Feature_HasStdEncBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, 23082 {Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, }, 23083 {Feature_HasStdEncBit, Feature_HasMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, }, 23084 {Feature_HasStdEncBit, Feature_HasMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, }, 23085 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 23086 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 23087 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips3_32Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 23088 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips3_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 23089 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 23090 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, }, 23091 {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips64Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, 23092 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 23093 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 23094 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 23095 {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 23096 {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotCnMipsBit, Feature_NotInMicroMipsBit, }, 23097 {Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, }, 23098 {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 23099 {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_HasEVABit, Feature_NotInMicroMipsBit, }, 23100 {Feature_HasStdEncBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 23101 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, }, 23102 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 23103 {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, 23104 {Feature_HasStdEncBit, Feature_IsPTR32bitBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, 23105 {Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, 23106 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 23107 {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, }, 23108 {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, }, 23109 {Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, }, 23110 {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, }, 23111 {Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, Feature_NotInMicroMipsBit, }, 23112 {Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_HasMadd4Bit, }, 23113 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMips3DBit, }, 23114 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 23115 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 23116 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips5_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 23117 {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 23118 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 23119 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 23120 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips5_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 23121 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, Feature_NotInMicroMipsBit, }, 23122 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_HasMadd4Bit, }, 23123 {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_IsFP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 23124 {Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, }, 23125 {Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, }, 23126 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, Feature_NotInMicroMipsBit, }, 23127 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_HasMadd4Bit, }, 23128}; 23129#endif // NDEBUG 23130 23131void verifyInstructionPredicates( 23132 unsigned Opcode, const FeatureBitset &Features) { 23133#ifndef NDEBUG 23134 static uint8_t RequiredFeaturesRefs[] = { 23135 CEFBS_None, // PHI = 0 23136 CEFBS_None, // INLINEASM = 1 23137 CEFBS_None, // INLINEASM_BR = 2 23138 CEFBS_None, // CFI_INSTRUCTION = 3 23139 CEFBS_None, // EH_LABEL = 4 23140 CEFBS_None, // GC_LABEL = 5 23141 CEFBS_None, // ANNOTATION_LABEL = 6 23142 CEFBS_None, // KILL = 7 23143 CEFBS_None, // EXTRACT_SUBREG = 8 23144 CEFBS_None, // INSERT_SUBREG = 9 23145 CEFBS_None, // IMPLICIT_DEF = 10 23146 CEFBS_None, // SUBREG_TO_REG = 11 23147 CEFBS_None, // COPY_TO_REGCLASS = 12 23148 CEFBS_None, // DBG_VALUE = 13 23149 CEFBS_None, // DBG_VALUE_LIST = 14 23150 CEFBS_None, // DBG_INSTR_REF = 15 23151 CEFBS_None, // DBG_PHI = 16 23152 CEFBS_None, // DBG_LABEL = 17 23153 CEFBS_None, // REG_SEQUENCE = 18 23154 CEFBS_None, // COPY = 19 23155 CEFBS_None, // BUNDLE = 20 23156 CEFBS_None, // LIFETIME_START = 21 23157 CEFBS_None, // LIFETIME_END = 22 23158 CEFBS_None, // PSEUDO_PROBE = 23 23159 CEFBS_None, // ARITH_FENCE = 24 23160 CEFBS_None, // STACKMAP = 25 23161 CEFBS_None, // FENTRY_CALL = 26 23162 CEFBS_None, // PATCHPOINT = 27 23163 CEFBS_None, // LOAD_STACK_GUARD = 28 23164 CEFBS_None, // PREALLOCATED_SETUP = 29 23165 CEFBS_None, // PREALLOCATED_ARG = 30 23166 CEFBS_None, // STATEPOINT = 31 23167 CEFBS_None, // LOCAL_ESCAPE = 32 23168 CEFBS_None, // FAULTING_OP = 33 23169 CEFBS_None, // PATCHABLE_OP = 34 23170 CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 35 23171 CEFBS_None, // PATCHABLE_RET = 36 23172 CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 37 23173 CEFBS_None, // PATCHABLE_TAIL_CALL = 38 23174 CEFBS_None, // PATCHABLE_EVENT_CALL = 39 23175 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 40 23176 CEFBS_None, // ICALL_BRANCH_FUNNEL = 41 23177 CEFBS_None, // MEMBARRIER = 42 23178 CEFBS_None, // G_ASSERT_SEXT = 43 23179 CEFBS_None, // G_ASSERT_ZEXT = 44 23180 CEFBS_None, // G_ASSERT_ALIGN = 45 23181 CEFBS_None, // G_ADD = 46 23182 CEFBS_None, // G_SUB = 47 23183 CEFBS_None, // G_MUL = 48 23184 CEFBS_None, // G_SDIV = 49 23185 CEFBS_None, // G_UDIV = 50 23186 CEFBS_None, // G_SREM = 51 23187 CEFBS_None, // G_UREM = 52 23188 CEFBS_None, // G_SDIVREM = 53 23189 CEFBS_None, // G_UDIVREM = 54 23190 CEFBS_None, // G_AND = 55 23191 CEFBS_None, // G_OR = 56 23192 CEFBS_None, // G_XOR = 57 23193 CEFBS_None, // G_IMPLICIT_DEF = 58 23194 CEFBS_None, // G_PHI = 59 23195 CEFBS_None, // G_FRAME_INDEX = 60 23196 CEFBS_None, // G_GLOBAL_VALUE = 61 23197 CEFBS_None, // G_EXTRACT = 62 23198 CEFBS_None, // G_UNMERGE_VALUES = 63 23199 CEFBS_None, // G_INSERT = 64 23200 CEFBS_None, // G_MERGE_VALUES = 65 23201 CEFBS_None, // G_BUILD_VECTOR = 66 23202 CEFBS_None, // G_BUILD_VECTOR_TRUNC = 67 23203 CEFBS_None, // G_CONCAT_VECTORS = 68 23204 CEFBS_None, // G_PTRTOINT = 69 23205 CEFBS_None, // G_INTTOPTR = 70 23206 CEFBS_None, // G_BITCAST = 71 23207 CEFBS_None, // G_FREEZE = 72 23208 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND = 73 23209 CEFBS_None, // G_INTRINSIC_TRUNC = 74 23210 CEFBS_None, // G_INTRINSIC_ROUND = 75 23211 CEFBS_None, // G_INTRINSIC_LRINT = 76 23212 CEFBS_None, // G_INTRINSIC_ROUNDEVEN = 77 23213 CEFBS_None, // G_READCYCLECOUNTER = 78 23214 CEFBS_None, // G_LOAD = 79 23215 CEFBS_None, // G_SEXTLOAD = 80 23216 CEFBS_None, // G_ZEXTLOAD = 81 23217 CEFBS_None, // G_INDEXED_LOAD = 82 23218 CEFBS_None, // G_INDEXED_SEXTLOAD = 83 23219 CEFBS_None, // G_INDEXED_ZEXTLOAD = 84 23220 CEFBS_None, // G_STORE = 85 23221 CEFBS_None, // G_INDEXED_STORE = 86 23222 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 87 23223 CEFBS_None, // G_ATOMIC_CMPXCHG = 88 23224 CEFBS_None, // G_ATOMICRMW_XCHG = 89 23225 CEFBS_None, // G_ATOMICRMW_ADD = 90 23226 CEFBS_None, // G_ATOMICRMW_SUB = 91 23227 CEFBS_None, // G_ATOMICRMW_AND = 92 23228 CEFBS_None, // G_ATOMICRMW_NAND = 93 23229 CEFBS_None, // G_ATOMICRMW_OR = 94 23230 CEFBS_None, // G_ATOMICRMW_XOR = 95 23231 CEFBS_None, // G_ATOMICRMW_MAX = 96 23232 CEFBS_None, // G_ATOMICRMW_MIN = 97 23233 CEFBS_None, // G_ATOMICRMW_UMAX = 98 23234 CEFBS_None, // G_ATOMICRMW_UMIN = 99 23235 CEFBS_None, // G_ATOMICRMW_FADD = 100 23236 CEFBS_None, // G_ATOMICRMW_FSUB = 101 23237 CEFBS_None, // G_ATOMICRMW_FMAX = 102 23238 CEFBS_None, // G_ATOMICRMW_FMIN = 103 23239 CEFBS_None, // G_ATOMICRMW_UINC_WRAP = 104 23240 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP = 105 23241 CEFBS_None, // G_FENCE = 106 23242 CEFBS_None, // G_BRCOND = 107 23243 CEFBS_None, // G_BRINDIRECT = 108 23244 CEFBS_None, // G_INVOKE_REGION_START = 109 23245 CEFBS_None, // G_INTRINSIC = 110 23246 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 111 23247 CEFBS_None, // G_ANYEXT = 112 23248 CEFBS_None, // G_TRUNC = 113 23249 CEFBS_None, // G_CONSTANT = 114 23250 CEFBS_None, // G_FCONSTANT = 115 23251 CEFBS_None, // G_VASTART = 116 23252 CEFBS_None, // G_VAARG = 117 23253 CEFBS_None, // G_SEXT = 118 23254 CEFBS_None, // G_SEXT_INREG = 119 23255 CEFBS_None, // G_ZEXT = 120 23256 CEFBS_None, // G_SHL = 121 23257 CEFBS_None, // G_LSHR = 122 23258 CEFBS_None, // G_ASHR = 123 23259 CEFBS_None, // G_FSHL = 124 23260 CEFBS_None, // G_FSHR = 125 23261 CEFBS_None, // G_ROTR = 126 23262 CEFBS_None, // G_ROTL = 127 23263 CEFBS_None, // G_ICMP = 128 23264 CEFBS_None, // G_FCMP = 129 23265 CEFBS_None, // G_SELECT = 130 23266 CEFBS_None, // G_UADDO = 131 23267 CEFBS_None, // G_UADDE = 132 23268 CEFBS_None, // G_USUBO = 133 23269 CEFBS_None, // G_USUBE = 134 23270 CEFBS_None, // G_SADDO = 135 23271 CEFBS_None, // G_SADDE = 136 23272 CEFBS_None, // G_SSUBO = 137 23273 CEFBS_None, // G_SSUBE = 138 23274 CEFBS_None, // G_UMULO = 139 23275 CEFBS_None, // G_SMULO = 140 23276 CEFBS_None, // G_UMULH = 141 23277 CEFBS_None, // G_SMULH = 142 23278 CEFBS_None, // G_UADDSAT = 143 23279 CEFBS_None, // G_SADDSAT = 144 23280 CEFBS_None, // G_USUBSAT = 145 23281 CEFBS_None, // G_SSUBSAT = 146 23282 CEFBS_None, // G_USHLSAT = 147 23283 CEFBS_None, // G_SSHLSAT = 148 23284 CEFBS_None, // G_SMULFIX = 149 23285 CEFBS_None, // G_UMULFIX = 150 23286 CEFBS_None, // G_SMULFIXSAT = 151 23287 CEFBS_None, // G_UMULFIXSAT = 152 23288 CEFBS_None, // G_SDIVFIX = 153 23289 CEFBS_None, // G_UDIVFIX = 154 23290 CEFBS_None, // G_SDIVFIXSAT = 155 23291 CEFBS_None, // G_UDIVFIXSAT = 156 23292 CEFBS_None, // G_FADD = 157 23293 CEFBS_None, // G_FSUB = 158 23294 CEFBS_None, // G_FMUL = 159 23295 CEFBS_None, // G_FMA = 160 23296 CEFBS_None, // G_FMAD = 161 23297 CEFBS_None, // G_FDIV = 162 23298 CEFBS_None, // G_FREM = 163 23299 CEFBS_None, // G_FPOW = 164 23300 CEFBS_None, // G_FPOWI = 165 23301 CEFBS_None, // G_FEXP = 166 23302 CEFBS_None, // G_FEXP2 = 167 23303 CEFBS_None, // G_FLOG = 168 23304 CEFBS_None, // G_FLOG2 = 169 23305 CEFBS_None, // G_FLOG10 = 170 23306 CEFBS_None, // G_FNEG = 171 23307 CEFBS_None, // G_FPEXT = 172 23308 CEFBS_None, // G_FPTRUNC = 173 23309 CEFBS_None, // G_FPTOSI = 174 23310 CEFBS_None, // G_FPTOUI = 175 23311 CEFBS_None, // G_SITOFP = 176 23312 CEFBS_None, // G_UITOFP = 177 23313 CEFBS_None, // G_FABS = 178 23314 CEFBS_None, // G_FCOPYSIGN = 179 23315 CEFBS_None, // G_IS_FPCLASS = 180 23316 CEFBS_None, // G_FCANONICALIZE = 181 23317 CEFBS_None, // G_FMINNUM = 182 23318 CEFBS_None, // G_FMAXNUM = 183 23319 CEFBS_None, // G_FMINNUM_IEEE = 184 23320 CEFBS_None, // G_FMAXNUM_IEEE = 185 23321 CEFBS_None, // G_FMINIMUM = 186 23322 CEFBS_None, // G_FMAXIMUM = 187 23323 CEFBS_None, // G_PTR_ADD = 188 23324 CEFBS_None, // G_PTRMASK = 189 23325 CEFBS_None, // G_SMIN = 190 23326 CEFBS_None, // G_SMAX = 191 23327 CEFBS_None, // G_UMIN = 192 23328 CEFBS_None, // G_UMAX = 193 23329 CEFBS_None, // G_ABS = 194 23330 CEFBS_None, // G_LROUND = 195 23331 CEFBS_None, // G_LLROUND = 196 23332 CEFBS_None, // G_BR = 197 23333 CEFBS_None, // G_BRJT = 198 23334 CEFBS_None, // G_INSERT_VECTOR_ELT = 199 23335 CEFBS_None, // G_EXTRACT_VECTOR_ELT = 200 23336 CEFBS_None, // G_SHUFFLE_VECTOR = 201 23337 CEFBS_None, // G_CTTZ = 202 23338 CEFBS_None, // G_CTTZ_ZERO_UNDEF = 203 23339 CEFBS_None, // G_CTLZ = 204 23340 CEFBS_None, // G_CTLZ_ZERO_UNDEF = 205 23341 CEFBS_None, // G_CTPOP = 206 23342 CEFBS_None, // G_BSWAP = 207 23343 CEFBS_None, // G_BITREVERSE = 208 23344 CEFBS_None, // G_FCEIL = 209 23345 CEFBS_None, // G_FCOS = 210 23346 CEFBS_None, // G_FSIN = 211 23347 CEFBS_None, // G_FSQRT = 212 23348 CEFBS_None, // G_FFLOOR = 213 23349 CEFBS_None, // G_FRINT = 214 23350 CEFBS_None, // G_FNEARBYINT = 215 23351 CEFBS_None, // G_ADDRSPACE_CAST = 216 23352 CEFBS_None, // G_BLOCK_ADDR = 217 23353 CEFBS_None, // G_JUMP_TABLE = 218 23354 CEFBS_None, // G_DYN_STACKALLOC = 219 23355 CEFBS_None, // G_STRICT_FADD = 220 23356 CEFBS_None, // G_STRICT_FSUB = 221 23357 CEFBS_None, // G_STRICT_FMUL = 222 23358 CEFBS_None, // G_STRICT_FDIV = 223 23359 CEFBS_None, // G_STRICT_FREM = 224 23360 CEFBS_None, // G_STRICT_FMA = 225 23361 CEFBS_None, // G_STRICT_FSQRT = 226 23362 CEFBS_None, // G_READ_REGISTER = 227 23363 CEFBS_None, // G_WRITE_REGISTER = 228 23364 CEFBS_None, // G_MEMCPY = 229 23365 CEFBS_None, // G_MEMCPY_INLINE = 230 23366 CEFBS_None, // G_MEMMOVE = 231 23367 CEFBS_None, // G_MEMSET = 232 23368 CEFBS_None, // G_BZERO = 233 23369 CEFBS_None, // G_VECREDUCE_SEQ_FADD = 234 23370 CEFBS_None, // G_VECREDUCE_SEQ_FMUL = 235 23371 CEFBS_None, // G_VECREDUCE_FADD = 236 23372 CEFBS_None, // G_VECREDUCE_FMUL = 237 23373 CEFBS_None, // G_VECREDUCE_FMAX = 238 23374 CEFBS_None, // G_VECREDUCE_FMIN = 239 23375 CEFBS_None, // G_VECREDUCE_ADD = 240 23376 CEFBS_None, // G_VECREDUCE_MUL = 241 23377 CEFBS_None, // G_VECREDUCE_AND = 242 23378 CEFBS_None, // G_VECREDUCE_OR = 243 23379 CEFBS_None, // G_VECREDUCE_XOR = 244 23380 CEFBS_None, // G_VECREDUCE_SMAX = 245 23381 CEFBS_None, // G_VECREDUCE_SMIN = 246 23382 CEFBS_None, // G_VECREDUCE_UMAX = 247 23383 CEFBS_None, // G_VECREDUCE_UMIN = 248 23384 CEFBS_None, // G_SBFX = 249 23385 CEFBS_None, // G_UBFX = 250 23386 CEFBS_None, // ABSMacro = 251 23387 CEFBS_None, // ADJCALLSTACKDOWN = 252 23388 CEFBS_None, // ADJCALLSTACKUP = 253 23389 CEFBS_HasStdEnc_HasMSA, // AND_V_D_PSEUDO = 254 23390 CEFBS_HasStdEnc_HasMSA, // AND_V_H_PSEUDO = 255 23391 CEFBS_HasStdEnc_HasMSA, // AND_V_W_PSEUDO = 256 23392 CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I16 = 257 23393 CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I16_POSTRA = 258 23394 CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I32 = 259 23395 CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I32_POSTRA = 260 23396 CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I64 = 261 23397 CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I64_POSTRA = 262 23398 CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I8 = 263 23399 CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I8_POSTRA = 264 23400 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I16 = 265 23401 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I16_POSTRA = 266 23402 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I32 = 267 23403 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I32_POSTRA = 268 23404 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I64 = 269 23405 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I64_POSTRA = 270 23406 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I8 = 271 23407 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I8_POSTRA = 272 23408 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I16 = 273 23409 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I16_POSTRA = 274 23410 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I32 = 275 23411 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I32_POSTRA = 276 23412 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I64 = 277 23413 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I64_POSTRA = 278 23414 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I8 = 279 23415 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I8_POSTRA = 280 23416 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I16 = 281 23417 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I16_POSTRA = 282 23418 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I32 = 283 23419 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I32_POSTRA = 284 23420 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I64 = 285 23421 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I64_POSTRA = 286 23422 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I8 = 287 23423 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I8_POSTRA = 288 23424 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I16 = 289 23425 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I16_POSTRA = 290 23426 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I32 = 291 23427 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I32_POSTRA = 292 23428 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I64 = 293 23429 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I64_POSTRA = 294 23430 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I8 = 295 23431 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I8_POSTRA = 296 23432 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I16 = 297 23433 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I16_POSTRA = 298 23434 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I32 = 299 23435 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I32_POSTRA = 300 23436 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I64 = 301 23437 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I64_POSTRA = 302 23438 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I8 = 303 23439 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I8_POSTRA = 304 23440 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I16 = 305 23441 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I16_POSTRA = 306 23442 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I32 = 307 23443 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I32_POSTRA = 308 23444 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I64 = 309 23445 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I64_POSTRA = 310 23446 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I8 = 311 23447 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I8_POSTRA = 312 23448 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I16 = 313 23449 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I16_POSTRA = 314 23450 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I32 = 315 23451 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I32_POSTRA = 316 23452 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I64 = 317 23453 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I64_POSTRA = 318 23454 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I8 = 319 23455 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I8_POSTRA = 320 23456 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I16 = 321 23457 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I16_POSTRA = 322 23458 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I32 = 323 23459 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I32_POSTRA = 324 23460 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I64 = 325 23461 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I64_POSTRA = 326 23462 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I8 = 327 23463 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I8_POSTRA = 328 23464 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I16 = 329 23465 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I16_POSTRA = 330 23466 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I32 = 331 23467 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I32_POSTRA = 332 23468 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I64 = 333 23469 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I64_POSTRA = 334 23470 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I8 = 335 23471 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I8_POSTRA = 336 23472 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I16 = 337 23473 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I16_POSTRA = 338 23474 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I32 = 339 23475 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I32_POSTRA = 340 23476 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I64 = 341 23477 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I64_POSTRA = 342 23478 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I8 = 343 23479 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I8_POSTRA = 344 23480 CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I16 = 345 23481 CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I16_POSTRA = 346 23482 CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I32 = 347 23483 CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I32_POSTRA = 348 23484 CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I64 = 349 23485 CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I64_POSTRA = 350 23486 CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I8 = 351 23487 CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I8_POSTRA = 352 23488 CEFBS_HasStdEnc_NotInMicroMips, // B = 353 23489 CEFBS_HasStdEnc_NotInMicroMips, // BAL_BR = 354 23490 CEFBS_InMicroMips_NotMips32r6, // BAL_BR_MM = 355 23491 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BEQLImmMacro = 356 23492 CEFBS_None, // BGE = 357 23493 CEFBS_None, // BGEImmMacro = 358 23494 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGEL = 359 23495 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGELImmMacro = 360 23496 CEFBS_None, // BGEU = 361 23497 CEFBS_None, // BGEUImmMacro = 362 23498 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGEUL = 363 23499 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGEULImmMacro = 364 23500 CEFBS_None, // BGT = 365 23501 CEFBS_None, // BGTImmMacro = 366 23502 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGTL = 367 23503 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGTLImmMacro = 368 23504 CEFBS_None, // BGTU = 369 23505 CEFBS_None, // BGTUImmMacro = 370 23506 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGTUL = 371 23507 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGTULImmMacro = 372 23508 CEFBS_None, // BLE = 373 23509 CEFBS_None, // BLEImmMacro = 374 23510 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLEL = 375 23511 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLELImmMacro = 376 23512 CEFBS_None, // BLEU = 377 23513 CEFBS_None, // BLEUImmMacro = 378 23514 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLEUL = 379 23515 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLEULImmMacro = 380 23516 CEFBS_None, // BLT = 381 23517 CEFBS_None, // BLTImmMacro = 382 23518 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLTL = 383 23519 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLTLImmMacro = 384 23520 CEFBS_None, // BLTU = 385 23521 CEFBS_None, // BLTUImmMacro = 386 23522 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLTUL = 387 23523 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLTULImmMacro = 388 23524 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BNELImmMacro = 389 23525 CEFBS_None, // BPOSGE32_PSEUDO = 390 23526 CEFBS_HasStdEnc_HasMSA, // BSEL_D_PSEUDO = 391 23527 CEFBS_HasStdEnc_HasMSA, // BSEL_FD_PSEUDO = 392 23528 CEFBS_HasStdEnc_HasMSA, // BSEL_FW_PSEUDO = 393 23529 CEFBS_HasStdEnc_HasMSA, // BSEL_H_PSEUDO = 394 23530 CEFBS_HasStdEnc_HasMSA, // BSEL_W_PSEUDO = 395 23531 CEFBS_InMicroMips_NotMips32r6, // B_MM = 396 23532 CEFBS_None, // B_MMR6_Pseudo = 397 23533 CEFBS_InMicroMips, // B_MM_Pseudo = 398 23534 CEFBS_None, // BeqImm = 399 23535 CEFBS_None, // BneImm = 400 23536 CEFBS_InMips16Mode, // BteqzT8CmpX16 = 401 23537 CEFBS_InMips16Mode, // BteqzT8CmpiX16 = 402 23538 CEFBS_InMips16Mode, // BteqzT8SltX16 = 403 23539 CEFBS_InMips16Mode, // BteqzT8SltiX16 = 404 23540 CEFBS_InMips16Mode, // BteqzT8SltiuX16 = 405 23541 CEFBS_InMips16Mode, // BteqzT8SltuX16 = 406 23542 CEFBS_InMips16Mode, // BtnezT8CmpX16 = 407 23543 CEFBS_InMips16Mode, // BtnezT8CmpiX16 = 408 23544 CEFBS_InMips16Mode, // BtnezT8SltX16 = 409 23545 CEFBS_InMips16Mode, // BtnezT8SltiX16 = 410 23546 CEFBS_InMips16Mode, // BtnezT8SltiuX16 = 411 23547 CEFBS_InMips16Mode, // BtnezT8SltuX16 = 412 23548 CEFBS_NotInMips16Mode_NotFP64bit_IsNotSoftFloat, // BuildPairF64 = 413 23549 CEFBS_NotInMips16Mode_IsFP64bit_IsNotSoftFloat, // BuildPairF64_64 = 414 23550 CEFBS_HasMT, // CFTC1 = 415 23551 CEFBS_InMips16Mode, // CONSTPOOL_ENTRY = 416 23552 CEFBS_HasStdEnc_HasMSA, // COPY_FD_PSEUDO = 417 23553 CEFBS_HasStdEnc_HasMSA, // COPY_FW_PSEUDO = 418 23554 CEFBS_HasMT, // CTTC1 = 419 23555 CEFBS_InMips16Mode, // Constant32 = 420 23556 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // DMULImmMacro = 421 23557 CEFBS_HasMips3_NotMips64r6_NotCnMips, // DMULMacro = 422 23558 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // DMULOMacro = 423 23559 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // DMULOUMacro = 424 23560 CEFBS_HasStdEnc_HasMips64, // DROL = 425 23561 CEFBS_HasStdEnc_HasMips64, // DROLImm = 426 23562 CEFBS_HasStdEnc_HasMips64, // DROR = 427 23563 CEFBS_HasStdEnc_HasMips64, // DRORImm = 428 23564 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DSDivIMacro = 429 23565 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DSDivMacro = 430 23566 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DSRemIMacro = 431 23567 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DSRemMacro = 432 23568 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DUDivIMacro = 433 23569 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DUDivMacro = 434 23570 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DURemIMacro = 435 23571 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DURemMacro = 436 23572 CEFBS_NotInMips16Mode, // ERet = 437 23573 CEFBS_NotInMips16Mode_NotFP64bit_IsNotSoftFloat, // ExtractElementF64 = 438 23574 CEFBS_NotInMips16Mode_IsFP64bit_IsNotSoftFloat, // ExtractElementF64_64 = 439 23575 CEFBS_HasStdEnc_HasMSA, // FABS_D = 440 23576 CEFBS_HasStdEnc_HasMSA, // FABS_W = 441 23577 CEFBS_HasStdEnc_HasMSA, // FEXP2_D_1_PSEUDO = 442 23578 CEFBS_HasStdEnc_HasMSA, // FEXP2_W_1_PSEUDO = 443 23579 CEFBS_HasStdEnc_HasMSA, // FILL_FD_PSEUDO = 444 23580 CEFBS_HasStdEnc_HasMSA, // FILL_FW_PSEUDO = 445 23581 CEFBS_InMips16Mode, // GotPrologue16 = 446 23582 CEFBS_HasStdEnc_HasMSA, // INSERT_B_VIDX64_PSEUDO = 447 23583 CEFBS_HasStdEnc_HasMSA, // INSERT_B_VIDX_PSEUDO = 448 23584 CEFBS_HasStdEnc_HasMSA, // INSERT_D_VIDX64_PSEUDO = 449 23585 CEFBS_HasStdEnc_HasMSA, // INSERT_D_VIDX_PSEUDO = 450 23586 CEFBS_HasStdEnc_HasMSA, // INSERT_FD_PSEUDO = 451 23587 CEFBS_HasStdEnc_HasMSA, // INSERT_FD_VIDX64_PSEUDO = 452 23588 CEFBS_HasStdEnc_HasMSA, // INSERT_FD_VIDX_PSEUDO = 453 23589 CEFBS_HasStdEnc_HasMSA, // INSERT_FW_PSEUDO = 454 23590 CEFBS_HasStdEnc_HasMSA, // INSERT_FW_VIDX64_PSEUDO = 455 23591 CEFBS_HasStdEnc_HasMSA, // INSERT_FW_VIDX_PSEUDO = 456 23592 CEFBS_HasStdEnc_HasMSA, // INSERT_H_VIDX64_PSEUDO = 457 23593 CEFBS_HasStdEnc_HasMSA, // INSERT_H_VIDX_PSEUDO = 458 23594 CEFBS_HasStdEnc_HasMSA, // INSERT_W_VIDX64_PSEUDO = 459 23595 CEFBS_HasStdEnc_HasMSA, // INSERT_W_VIDX_PSEUDO = 460 23596 CEFBS_NotInMips16Mode_IsPTR64bit_NoIndirectJumpGuards, // JALR64Pseudo = 461 23597 CEFBS_NotInMips16Mode_IsPTR64bit_UseIndirectJumpsHazard, // JALRHB64Pseudo = 462 23598 CEFBS_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // JALRHBPseudo = 463 23599 CEFBS_HasStdEnc_NotInMicroMips_NoIndirectJumpGuards, // JALRPseudo = 464 23600 CEFBS_InMicroMips_HasMips32r6, // JAL_MMR6 = 465 23601 CEFBS_None, // JalOneReg = 466 23602 CEFBS_None, // JalTwoReg = 467 23603 CEFBS_HasStdEnc_NotMips3, // LDMacro = 468 23604 CEFBS_NotInMips16Mode, // LDR_D = 469 23605 CEFBS_NotInMips16Mode, // LDR_W = 470 23606 CEFBS_HasMSA, // LD_F16 = 471 23607 CEFBS_NotInMips16Mode, // LOAD_ACC128 = 472 23608 CEFBS_NotInMips16Mode, // LOAD_ACC64 = 473 23609 CEFBS_NotInMips16Mode, // LOAD_ACC64DSP = 474 23610 CEFBS_NotInMips16Mode, // LOAD_CCOND_DSP = 475 23611 CEFBS_NotInMips16Mode, // LONG_BRANCH_ADDiu = 476 23612 CEFBS_NotInMips16Mode, // LONG_BRANCH_ADDiu2Op = 477 23613 CEFBS_NotInMips16Mode_IsGP64bit, // LONG_BRANCH_DADDiu = 478 23614 CEFBS_NotInMips16Mode_IsGP64bit, // LONG_BRANCH_DADDiu2Op = 479 23615 CEFBS_NotInMips16Mode, // LONG_BRANCH_LUi = 480 23616 CEFBS_NotInMips16Mode, // LONG_BRANCH_LUi2Op = 481 23617 CEFBS_NotInMips16Mode_IsGP64bit, // LONG_BRANCH_LUi2Op_64 = 482 23618 CEFBS_InMicroMips, // LWM_MM = 483 23619 CEFBS_None, // LoadAddrImm32 = 484 23620 CEFBS_None, // LoadAddrImm64 = 485 23621 CEFBS_None, // LoadAddrReg32 = 486 23622 CEFBS_None, // LoadAddrReg64 = 487 23623 CEFBS_None, // LoadImm32 = 488 23624 CEFBS_None, // LoadImm64 = 489 23625 CEFBS_IsFP64bit_IsNotSoftFloat, // LoadImmDoubleFGR = 490 23626 CEFBS_NotFP64bit_IsNotSoftFloat, // LoadImmDoubleFGR_32 = 491 23627 CEFBS_None, // LoadImmDoubleGPR = 492 23628 CEFBS_IsNotSoftFloat, // LoadImmSingleFGR = 493 23629 CEFBS_None, // LoadImmSingleGPR = 494 23630 CEFBS_InMips16Mode, // LwConstant32 = 495 23631 CEFBS_HasMT, // MFTACX = 496 23632 CEFBS_HasMT, // MFTC0 = 497 23633 CEFBS_HasMT, // MFTC1 = 498 23634 CEFBS_HasMT, // MFTDSP = 499 23635 CEFBS_HasMT, // MFTGPR = 500 23636 CEFBS_HasMT, // MFTHC1 = 501 23637 CEFBS_HasMT, // MFTHI = 502 23638 CEFBS_HasMT, // MFTLO = 503 23639 CEFBS_None, // MIPSeh_return32 = 504 23640 CEFBS_None, // MIPSeh_return64 = 505 23641 CEFBS_HasMSA, // MSA_FP_EXTEND_D_PSEUDO = 506 23642 CEFBS_HasMSA, // MSA_FP_EXTEND_W_PSEUDO = 507 23643 CEFBS_HasMSA, // MSA_FP_ROUND_D_PSEUDO = 508 23644 CEFBS_HasMSA, // MSA_FP_ROUND_W_PSEUDO = 509 23645 CEFBS_HasMT, // MTTACX = 510 23646 CEFBS_HasMT, // MTTC0 = 511 23647 CEFBS_HasMT, // MTTC1 = 512 23648 CEFBS_HasMT, // MTTDSP = 513 23649 CEFBS_HasMT, // MTTGPR = 514 23650 CEFBS_HasMT, // MTTHC1 = 515 23651 CEFBS_HasMT, // MTTHI = 516 23652 CEFBS_HasMT, // MTTLO = 517 23653 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // MULImmMacro = 518 23654 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // MULOMacro = 519 23655 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // MULOUMacro = 520 23656 CEFBS_InMips16Mode, // MultRxRy16 = 521 23657 CEFBS_InMips16Mode, // MultRxRyRz16 = 522 23658 CEFBS_InMips16Mode, // MultuRxRy16 = 523 23659 CEFBS_InMips16Mode, // MultuRxRyRz16 = 524 23660 CEFBS_HasStdEnc_NotInMicroMips, // NOP = 525 23661 CEFBS_IsGP32bit, // NORImm = 526 23662 CEFBS_IsGP64bit, // NORImm64 = 527 23663 CEFBS_HasStdEnc_HasMSA, // NOR_V_D_PSEUDO = 528 23664 CEFBS_HasStdEnc_HasMSA, // NOR_V_H_PSEUDO = 529 23665 CEFBS_HasStdEnc_HasMSA, // NOR_V_W_PSEUDO = 530 23666 CEFBS_HasStdEnc_HasMSA, // OR_V_D_PSEUDO = 531 23667 CEFBS_HasStdEnc_HasMSA, // OR_V_H_PSEUDO = 532 23668 CEFBS_HasStdEnc_HasMSA, // OR_V_W_PSEUDO = 533 23669 CEFBS_HasDSP, // PseudoCMPU_EQ_QB = 534 23670 CEFBS_HasDSP, // PseudoCMPU_LE_QB = 535 23671 CEFBS_HasDSP, // PseudoCMPU_LT_QB = 536 23672 CEFBS_HasDSP, // PseudoCMP_EQ_PH = 537 23673 CEFBS_HasDSP, // PseudoCMP_LE_PH = 538 23674 CEFBS_HasDSP, // PseudoCMP_LT_PH = 539 23675 CEFBS_NotInMips16Mode_IsNotSoftFloat, // PseudoCVT_D32_W = 540 23676 CEFBS_NotInMips16Mode_IsNotSoftFloat, // PseudoCVT_D64_L = 541 23677 CEFBS_NotInMips16Mode_IsNotSoftFloat, // PseudoCVT_D64_W = 542 23678 CEFBS_NotInMips16Mode_IsNotSoftFloat, // PseudoCVT_S_L = 543 23679 CEFBS_NotInMips16Mode_IsNotSoftFloat, // PseudoCVT_S_W = 544 23680 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoDMULT = 545 23681 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoDMULTu = 546 23682 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoDSDIV = 547 23683 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoDUDIV = 548 23684 CEFBS_HasStdEnc_NotMips4_32, // PseudoD_SELECT_I = 549 23685 CEFBS_HasStdEnc_NotMips4_32, // PseudoD_SELECT_I64 = 550 23686 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // PseudoIndirectBranch = 551 23687 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // PseudoIndirectBranch64 = 552 23688 CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // PseudoIndirectBranch64R6 = 553 23689 CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // PseudoIndirectBranchR6 = 554 23690 CEFBS_InMicroMips_NotMips32r6, // PseudoIndirectBranch_MM = 555 23691 CEFBS_InMicroMips_HasMips32r6, // PseudoIndirectBranch_MMR6 = 556 23692 CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // PseudoIndirectHazardBranch = 557 23693 CEFBS_HasStdEnc_IsPTR64bit_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // PseudoIndirectHazardBranch64 = 558 23694 CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // PseudoIndrectHazardBranch64R6 = 559 23695 CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // PseudoIndrectHazardBranchR6 = 560 23696 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, // PseudoMADD = 561 23697 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, // PseudoMADDU = 562 23698 CEFBS_InMicroMips_NotMips32r6, // PseudoMADDU_MM = 563 23699 CEFBS_InMicroMips_NotMips32r6, // PseudoMADD_MM = 564 23700 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMFHI = 565 23701 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoMFHI64 = 566 23702 CEFBS_InMicroMips_NotMips32r6, // PseudoMFHI_MM = 567 23703 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMFLO = 568 23704 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoMFLO64 = 569 23705 CEFBS_InMicroMips_NotMips32r6, // PseudoMFLO_MM = 570 23706 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, // PseudoMSUB = 571 23707 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, // PseudoMSUBU = 572 23708 CEFBS_InMicroMips_NotMips32r6, // PseudoMSUBU_MM = 573 23709 CEFBS_InMicroMips_NotMips32r6, // PseudoMSUB_MM = 574 23710 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMTLOHI = 575 23711 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoMTLOHI64 = 576 23712 CEFBS_NotInMips16Mode_HasDSP, // PseudoMTLOHI_DSP = 577 23713 CEFBS_InMicroMips_NotMips32r6, // PseudoMTLOHI_MM = 578 23714 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMULT = 579 23715 CEFBS_InMicroMips_NotMips32r6, // PseudoMULT_MM = 580 23716 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMULTu = 581 23717 CEFBS_InMicroMips_NotMips32r6, // PseudoMULTu_MM = 582 23718 CEFBS_HasDSP, // PseudoPICK_PH = 583 23719 CEFBS_HasDSP, // PseudoPICK_QB = 584 23720 CEFBS_None, // PseudoReturn = 585 23721 CEFBS_IsGP64bit, // PseudoReturn64 = 586 23722 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // PseudoSDIV = 587 23723 CEFBS_HasStdEnc_NotFP64bit_NotMips4_32, // PseudoSELECTFP_F_D32 = 588 23724 CEFBS_HasStdEnc_IsFP64bit_NotMips4_32, // PseudoSELECTFP_F_D64 = 589 23725 CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_F_I = 590 23726 CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_F_I64 = 591 23727 CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_F_S = 592 23728 CEFBS_HasStdEnc_NotFP64bit_NotMips4_32, // PseudoSELECTFP_T_D32 = 593 23729 CEFBS_HasStdEnc_IsFP64bit_NotMips4_32, // PseudoSELECTFP_T_D64 = 594 23730 CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_T_I = 595 23731 CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_T_I64 = 596 23732 CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_T_S = 597 23733 CEFBS_HasStdEnc_NotFP64bit_NotMips4_32, // PseudoSELECT_D32 = 598 23734 CEFBS_HasStdEnc_IsFP64bit_NotMips4_32, // PseudoSELECT_D64 = 599 23735 CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECT_I = 600 23736 CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECT_I64 = 601 23737 CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECT_S = 602 23738 CEFBS_IsFP64bit_IsNotSoftFloat, // PseudoTRUNC_W_D = 603 23739 CEFBS_NotFP64bit_IsNotSoftFloat, // PseudoTRUNC_W_D32 = 604 23740 CEFBS_None, // PseudoTRUNC_W_S = 605 23741 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // PseudoUDIV = 606 23742 CEFBS_None, // ROL = 607 23743 CEFBS_None, // ROLImm = 608 23744 CEFBS_None, // ROR = 609 23745 CEFBS_None, // RORImm = 610 23746 CEFBS_NotInMips16Mode, // RetRA = 611 23747 CEFBS_InMips16Mode, // RetRA16 = 612 23748 CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat, // SDC1_M1 = 613 23749 CEFBS_InMicroMips_NotMips32r6_NotMips64r6, // SDIV_MM_Pseudo = 614 23750 CEFBS_HasStdEnc_NotMips3, // SDMacro = 615 23751 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // SDivIMacro = 616 23752 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // SDivMacro = 617 23753 CEFBS_NotCnMips, // SEQIMacro = 618 23754 CEFBS_NotCnMips, // SEQMacro = 619 23755 CEFBS_HasStdEnc_NotInMicroMips, // SGE = 620 23756 CEFBS_IsGP32bit_NotInMicroMips, // SGEImm = 621 23757 CEFBS_IsGP64bit, // SGEImm64 = 622 23758 CEFBS_HasStdEnc_NotInMicroMips, // SGEU = 623 23759 CEFBS_IsGP32bit_NotInMicroMips, // SGEUImm = 624 23760 CEFBS_IsGP64bit, // SGEUImm64 = 625 23761 CEFBS_IsGP32bit_NotInMicroMips, // SGTImm = 626 23762 CEFBS_IsGP64bit, // SGTImm64 = 627 23763 CEFBS_IsGP32bit_NotInMicroMips, // SGTUImm = 628 23764 CEFBS_IsGP64bit, // SGTUImm64 = 629 23765 CEFBS_HasStdEnc_NotInMicroMips, // SLE = 630 23766 CEFBS_IsGP32bit_NotInMicroMips, // SLEImm = 631 23767 CEFBS_IsGP64bit, // SLEImm64 = 632 23768 CEFBS_HasStdEnc_NotInMicroMips, // SLEU = 633 23769 CEFBS_IsGP32bit_NotInMicroMips, // SLEUImm = 634 23770 CEFBS_IsGP64bit, // SLEUImm64 = 635 23771 CEFBS_IsGP64bit, // SLTImm64 = 636 23772 CEFBS_IsGP64bit, // SLTUImm64 = 637 23773 CEFBS_NotCnMips, // SNEIMacro = 638 23774 CEFBS_NotCnMips, // SNEMacro = 639 23775 CEFBS_None, // SNZ_B_PSEUDO = 640 23776 CEFBS_None, // SNZ_D_PSEUDO = 641 23777 CEFBS_None, // SNZ_H_PSEUDO = 642 23778 CEFBS_None, // SNZ_V_PSEUDO = 643 23779 CEFBS_None, // SNZ_W_PSEUDO = 644 23780 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // SRemIMacro = 645 23781 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // SRemMacro = 646 23782 CEFBS_NotInMips16Mode, // STORE_ACC128 = 647 23783 CEFBS_NotInMips16Mode, // STORE_ACC64 = 648 23784 CEFBS_NotInMips16Mode, // STORE_ACC64DSP = 649 23785 CEFBS_NotInMips16Mode, // STORE_CCOND_DSP = 650 23786 CEFBS_NotInMips16Mode, // STR_D = 651 23787 CEFBS_NotInMips16Mode, // STR_W = 652 23788 CEFBS_HasMSA, // ST_F16 = 653 23789 CEFBS_InMicroMips, // SWM_MM = 654 23790 CEFBS_None, // SZ_B_PSEUDO = 655 23791 CEFBS_None, // SZ_D_PSEUDO = 656 23792 CEFBS_None, // SZ_H_PSEUDO = 657 23793 CEFBS_None, // SZ_V_PSEUDO = 658 23794 CEFBS_None, // SZ_W_PSEUDO = 659 23795 CEFBS_HasCnMipsP, // SaaAddr = 660 23796 CEFBS_HasCnMipsP, // SaadAddr = 661 23797 CEFBS_InMips16Mode, // SelBeqZ = 662 23798 CEFBS_InMips16Mode, // SelBneZ = 663 23799 CEFBS_InMips16Mode, // SelTBteqZCmp = 664 23800 CEFBS_InMips16Mode, // SelTBteqZCmpi = 665 23801 CEFBS_InMips16Mode, // SelTBteqZSlt = 666 23802 CEFBS_InMips16Mode, // SelTBteqZSlti = 667 23803 CEFBS_InMips16Mode, // SelTBteqZSltiu = 668 23804 CEFBS_InMips16Mode, // SelTBteqZSltu = 669 23805 CEFBS_InMips16Mode, // SelTBtneZCmp = 670 23806 CEFBS_InMips16Mode, // SelTBtneZCmpi = 671 23807 CEFBS_InMips16Mode, // SelTBtneZSlt = 672 23808 CEFBS_InMips16Mode, // SelTBtneZSlti = 673 23809 CEFBS_InMips16Mode, // SelTBtneZSltiu = 674 23810 CEFBS_InMips16Mode, // SelTBtneZSltu = 675 23811 CEFBS_InMips16Mode, // SltCCRxRy16 = 676 23812 CEFBS_InMips16Mode, // SltiCCRxImmX16 = 677 23813 CEFBS_InMips16Mode, // SltiuCCRxImmX16 = 678 23814 CEFBS_InMips16Mode, // SltuCCRxRy16 = 679 23815 CEFBS_InMips16Mode, // SltuRxRyRz16 = 680 23816 CEFBS_HasStdEnc_NotInMips16Mode_NotInMicroMips, // TAILCALL = 681 23817 CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // TAILCALL64R6REG = 682 23818 CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // TAILCALLHB64R6REG = 683 23819 CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // TAILCALLHBR6REG = 684 23820 CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // TAILCALLR6REG = 685 23821 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // TAILCALLREG = 686 23822 CEFBS_HasStdEnc_IsPTR64bit_HasMips3_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // TAILCALLREG64 = 687 23823 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // TAILCALLREGHB = 688 23824 CEFBS_HasStdEnc_IsPTR64bit_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // TAILCALLREGHB64 = 689 23825 CEFBS_InMicroMips_NotMips32r6, // TAILCALLREG_MM = 690 23826 CEFBS_InMicroMips_HasMips32r6, // TAILCALLREG_MMR6 = 691 23827 CEFBS_InMicroMips_NotMips32r6, // TAILCALL_MM = 692 23828 CEFBS_InMicroMips_HasMips32r6, // TAILCALL_MMR6 = 693 23829 CEFBS_HasStdEnc_NotInMicroMips, // TRAP = 694 23830 CEFBS_InMicroMips, // TRAP_MM = 695 23831 CEFBS_InMicroMips_NotMips32r6_NotMips64r6, // UDIV_MM_Pseudo = 696 23832 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // UDivIMacro = 697 23833 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // UDivMacro = 698 23834 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // URemIMacro = 699 23835 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // URemMacro = 700 23836 CEFBS_None, // Ulh = 701 23837 CEFBS_None, // Ulhu = 702 23838 CEFBS_None, // Ulw = 703 23839 CEFBS_None, // Ush = 704 23840 CEFBS_None, // Usw = 705 23841 CEFBS_HasStdEnc_HasMSA, // XOR_V_D_PSEUDO = 706 23842 CEFBS_HasStdEnc_HasMSA, // XOR_V_H_PSEUDO = 707 23843 CEFBS_HasStdEnc_HasMSA, // XOR_V_W_PSEUDO = 708 23844 CEFBS_HasDSP, // ABSQ_S_PH = 709 23845 CEFBS_InMicroMips_HasDSP, // ABSQ_S_PH_MM = 710 23846 CEFBS_HasDSPR2, // ABSQ_S_QB = 711 23847 CEFBS_InMicroMips_HasDSPR2, // ABSQ_S_QB_MMR2 = 712 23848 CEFBS_HasDSP, // ABSQ_S_W = 713 23849 CEFBS_InMicroMips_HasDSP, // ABSQ_S_W_MM = 714 23850 CEFBS_HasStdEnc_NotInMicroMips, // ADD = 715 23851 CEFBS_HasStdEnc_HasMips32r6, // ADDIUPC = 716 23852 CEFBS_InMicroMips_NotMips32r6, // ADDIUPC_MM = 717 23853 CEFBS_InMicroMips_HasMips32r6, // ADDIUPC_MMR6 = 718 23854 CEFBS_InMicroMips, // ADDIUR1SP_MM = 719 23855 CEFBS_InMicroMips, // ADDIUR2_MM = 720 23856 CEFBS_InMicroMips, // ADDIUS5_MM = 721 23857 CEFBS_InMicroMips, // ADDIUSP_MM = 722 23858 CEFBS_InMicroMips_HasMips32r6, // ADDIU_MMR6 = 723 23859 CEFBS_HasDSPR2, // ADDQH_PH = 724 23860 CEFBS_InMicroMips_HasDSPR2, // ADDQH_PH_MMR2 = 725 23861 CEFBS_HasDSPR2, // ADDQH_R_PH = 726 23862 CEFBS_InMicroMips_HasDSPR2, // ADDQH_R_PH_MMR2 = 727 23863 CEFBS_HasDSPR2, // ADDQH_R_W = 728 23864 CEFBS_InMicroMips_HasDSPR2, // ADDQH_R_W_MMR2 = 729 23865 CEFBS_HasDSPR2, // ADDQH_W = 730 23866 CEFBS_InMicroMips_HasDSPR2, // ADDQH_W_MMR2 = 731 23867 CEFBS_HasDSP, // ADDQ_PH = 732 23868 CEFBS_InMicroMips_HasDSP, // ADDQ_PH_MM = 733 23869 CEFBS_HasDSP, // ADDQ_S_PH = 734 23870 CEFBS_InMicroMips_HasDSP, // ADDQ_S_PH_MM = 735 23871 CEFBS_HasDSP, // ADDQ_S_W = 736 23872 CEFBS_InMicroMips_HasDSP, // ADDQ_S_W_MM = 737 23873 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, // ADDR_PS64 = 738 23874 CEFBS_HasDSP, // ADDSC = 739 23875 CEFBS_InMicroMips_HasDSP, // ADDSC_MM = 740 23876 CEFBS_HasStdEnc_HasMSA, // ADDS_A_B = 741 23877 CEFBS_HasStdEnc_HasMSA, // ADDS_A_D = 742 23878 CEFBS_HasStdEnc_HasMSA, // ADDS_A_H = 743 23879 CEFBS_HasStdEnc_HasMSA, // ADDS_A_W = 744 23880 CEFBS_HasStdEnc_HasMSA, // ADDS_S_B = 745 23881 CEFBS_HasStdEnc_HasMSA, // ADDS_S_D = 746 23882 CEFBS_HasStdEnc_HasMSA, // ADDS_S_H = 747 23883 CEFBS_HasStdEnc_HasMSA, // ADDS_S_W = 748 23884 CEFBS_HasStdEnc_HasMSA, // ADDS_U_B = 749 23885 CEFBS_HasStdEnc_HasMSA, // ADDS_U_D = 750 23886 CEFBS_HasStdEnc_HasMSA, // ADDS_U_H = 751 23887 CEFBS_HasStdEnc_HasMSA, // ADDS_U_W = 752 23888 CEFBS_InMicroMips_NotMips32r6, // ADDU16_MM = 753 23889 CEFBS_InMicroMips_HasMips32r6, // ADDU16_MMR6 = 754 23890 CEFBS_HasDSPR2, // ADDUH_QB = 755 23891 CEFBS_InMicroMips_HasDSPR2, // ADDUH_QB_MMR2 = 756 23892 CEFBS_HasDSPR2, // ADDUH_R_QB = 757 23893 CEFBS_InMicroMips_HasDSPR2, // ADDUH_R_QB_MMR2 = 758 23894 CEFBS_InMicroMips_HasMips32r6, // ADDU_MMR6 = 759 23895 CEFBS_HasDSPR2, // ADDU_PH = 760 23896 CEFBS_InMicroMips_HasDSPR2, // ADDU_PH_MMR2 = 761 23897 CEFBS_HasDSP, // ADDU_QB = 762 23898 CEFBS_InMicroMips_HasDSP, // ADDU_QB_MM = 763 23899 CEFBS_HasDSPR2, // ADDU_S_PH = 764 23900 CEFBS_InMicroMips_HasDSPR2, // ADDU_S_PH_MMR2 = 765 23901 CEFBS_HasDSP, // ADDU_S_QB = 766 23902 CEFBS_InMicroMips_HasDSP, // ADDU_S_QB_MM = 767 23903 CEFBS_HasStdEnc_HasMSA, // ADDVI_B = 768 23904 CEFBS_HasStdEnc_HasMSA, // ADDVI_D = 769 23905 CEFBS_HasStdEnc_HasMSA, // ADDVI_H = 770 23906 CEFBS_HasStdEnc_HasMSA, // ADDVI_W = 771 23907 CEFBS_HasStdEnc_HasMSA, // ADDV_B = 772 23908 CEFBS_HasStdEnc_HasMSA, // ADDV_D = 773 23909 CEFBS_HasStdEnc_HasMSA, // ADDV_H = 774 23910 CEFBS_HasStdEnc_HasMSA, // ADDV_W = 775 23911 CEFBS_HasDSP, // ADDWC = 776 23912 CEFBS_InMicroMips_HasDSP, // ADDWC_MM = 777 23913 CEFBS_HasStdEnc_HasMSA, // ADD_A_B = 778 23914 CEFBS_HasStdEnc_HasMSA, // ADD_A_D = 779 23915 CEFBS_HasStdEnc_HasMSA, // ADD_A_H = 780 23916 CEFBS_HasStdEnc_HasMSA, // ADD_A_W = 781 23917 CEFBS_InMicroMips_NotMips32r6, // ADD_MM = 782 23918 CEFBS_InMicroMips_HasMips32r6, // ADD_MMR6 = 783 23919 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // ADDi = 784 23920 CEFBS_InMicroMips_NotMips32r6, // ADDi_MM = 785 23921 CEFBS_HasStdEnc_NotInMicroMips, // ADDiu = 786 23922 CEFBS_InMicroMips_NotMips32r6, // ADDiu_MM = 787 23923 CEFBS_HasStdEnc_NotInMicroMips, // ADDu = 788 23924 CEFBS_InMicroMips_NotMips32r6, // ADDu_MM = 789 23925 CEFBS_HasStdEnc_HasMips32r6, // ALIGN = 790 23926 CEFBS_InMicroMips_HasMips32r6, // ALIGN_MMR6 = 791 23927 CEFBS_HasStdEnc_HasMips32r6, // ALUIPC = 792 23928 CEFBS_InMicroMips_HasMips32r6, // ALUIPC_MMR6 = 793 23929 CEFBS_HasStdEnc_NotInMicroMips, // AND = 794 23930 CEFBS_InMicroMips_NotMips32r6, // AND16_MM = 795 23931 CEFBS_InMicroMips_HasMips32r6, // AND16_MMR6 = 796 23932 CEFBS_NotInMips16Mode_IsGP64bit, // AND64 = 797 23933 CEFBS_InMicroMips_NotMips32r6, // ANDI16_MM = 798 23934 CEFBS_InMicroMips_HasMips32r6, // ANDI16_MMR6 = 799 23935 CEFBS_HasStdEnc_HasMSA, // ANDI_B = 800 23936 CEFBS_InMicroMips_HasMips32r6, // ANDI_MMR6 = 801 23937 CEFBS_InMicroMips_NotMips32r6, // AND_MM = 802 23938 CEFBS_InMicroMips_HasMips32r6, // AND_MMR6 = 803 23939 CEFBS_HasStdEnc_HasMSA, // AND_V = 804 23940 CEFBS_HasStdEnc_NotInMicroMips, // ANDi = 805 23941 CEFBS_NotInMips16Mode_IsGP64bit, // ANDi64 = 806 23942 CEFBS_InMicroMips_NotMips32r6, // ANDi_MM = 807 23943 CEFBS_HasDSPR2, // APPEND = 808 23944 CEFBS_InMicroMips_HasDSPR2, // APPEND_MMR2 = 809 23945 CEFBS_HasStdEnc_HasMSA, // ASUB_S_B = 810 23946 CEFBS_HasStdEnc_HasMSA, // ASUB_S_D = 811 23947 CEFBS_HasStdEnc_HasMSA, // ASUB_S_H = 812 23948 CEFBS_HasStdEnc_HasMSA, // ASUB_S_W = 813 23949 CEFBS_HasStdEnc_HasMSA, // ASUB_U_B = 814 23950 CEFBS_HasStdEnc_HasMSA, // ASUB_U_D = 815 23951 CEFBS_HasStdEnc_HasMSA, // ASUB_U_H = 816 23952 CEFBS_HasStdEnc_HasMSA, // ASUB_U_W = 817 23953 CEFBS_HasStdEnc_HasMips32r6, // AUI = 818 23954 CEFBS_HasStdEnc_HasMips32r6, // AUIPC = 819 23955 CEFBS_InMicroMips_HasMips32r6, // AUIPC_MMR6 = 820 23956 CEFBS_InMicroMips_HasMips32r6, // AUI_MMR6 = 821 23957 CEFBS_HasStdEnc_HasMSA, // AVER_S_B = 822 23958 CEFBS_HasStdEnc_HasMSA, // AVER_S_D = 823 23959 CEFBS_HasStdEnc_HasMSA, // AVER_S_H = 824 23960 CEFBS_HasStdEnc_HasMSA, // AVER_S_W = 825 23961 CEFBS_HasStdEnc_HasMSA, // AVER_U_B = 826 23962 CEFBS_HasStdEnc_HasMSA, // AVER_U_D = 827 23963 CEFBS_HasStdEnc_HasMSA, // AVER_U_H = 828 23964 CEFBS_HasStdEnc_HasMSA, // AVER_U_W = 829 23965 CEFBS_HasStdEnc_HasMSA, // AVE_S_B = 830 23966 CEFBS_HasStdEnc_HasMSA, // AVE_S_D = 831 23967 CEFBS_HasStdEnc_HasMSA, // AVE_S_H = 832 23968 CEFBS_HasStdEnc_HasMSA, // AVE_S_W = 833 23969 CEFBS_HasStdEnc_HasMSA, // AVE_U_B = 834 23970 CEFBS_HasStdEnc_HasMSA, // AVE_U_D = 835 23971 CEFBS_HasStdEnc_HasMSA, // AVE_U_H = 836 23972 CEFBS_HasStdEnc_HasMSA, // AVE_U_W = 837 23973 CEFBS_InMips16Mode, // AddiuRxImmX16 = 838 23974 CEFBS_InMips16Mode, // AddiuRxPcImmX16 = 839 23975 CEFBS_InMips16Mode, // AddiuRxRxImm16 = 840 23976 CEFBS_InMips16Mode, // AddiuRxRxImmX16 = 841 23977 CEFBS_InMips16Mode, // AddiuRxRyOffMemX16 = 842 23978 CEFBS_InMips16Mode, // AddiuSpImm16 = 843 23979 CEFBS_InMips16Mode, // AddiuSpImmX16 = 844 23980 CEFBS_InMips16Mode, // AdduRxRyRz16 = 845 23981 CEFBS_InMips16Mode, // AndRxRxRy16 = 846 23982 CEFBS_InMicroMips, // B16_MM = 847 23983 CEFBS_HasCnMips, // BADDu = 848 23984 CEFBS_HasStdEnc_HasMips32r6, // BAL = 849 23985 CEFBS_HasStdEnc_HasMips32r6, // BALC = 850 23986 CEFBS_InMicroMips_HasMips32r6, // BALC_MMR6 = 851 23987 CEFBS_HasDSPR2, // BALIGN = 852 23988 CEFBS_InMicroMips_HasDSPR2, // BALIGN_MMR2 = 853 23989 CEFBS_HasCnMips, // BBIT0 = 854 23990 CEFBS_HasCnMips, // BBIT032 = 855 23991 CEFBS_HasCnMips, // BBIT1 = 856 23992 CEFBS_HasCnMips, // BBIT132 = 857 23993 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BC = 858 23994 CEFBS_InMicroMips_HasMips32r6, // BC16_MMR6 = 859 23995 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // BC1EQZ = 860 23996 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // BC1EQZC_MMR6 = 861 23997 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // BC1F = 862 23998 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // BC1FL = 863 23999 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // BC1F_MM = 864 24000 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // BC1NEZ = 865 24001 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // BC1NEZC_MMR6 = 866 24002 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // BC1T = 867 24003 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // BC1TL = 868 24004 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // BC1T_MM = 869 24005 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BC2EQZ = 870 24006 CEFBS_InMicroMips_HasMips32r6, // BC2EQZC_MMR6 = 871 24007 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BC2NEZ = 872 24008 CEFBS_InMicroMips_HasMips32r6, // BC2NEZC_MMR6 = 873 24009 CEFBS_HasStdEnc_HasMSA, // BCLRI_B = 874 24010 CEFBS_HasStdEnc_HasMSA, // BCLRI_D = 875 24011 CEFBS_HasStdEnc_HasMSA, // BCLRI_H = 876 24012 CEFBS_HasStdEnc_HasMSA, // BCLRI_W = 877 24013 CEFBS_HasStdEnc_HasMSA, // BCLR_B = 878 24014 CEFBS_HasStdEnc_HasMSA, // BCLR_D = 879 24015 CEFBS_HasStdEnc_HasMSA, // BCLR_H = 880 24016 CEFBS_HasStdEnc_HasMSA, // BCLR_W = 881 24017 CEFBS_InMicroMips_HasMips32r6, // BC_MMR6 = 882 24018 CEFBS_HasStdEnc_NotInMicroMips, // BEQ = 883 24019 CEFBS_NotInMips16Mode_IsGP64bit, // BEQ64 = 884 24020 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BEQC = 885 24021 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BEQC64 = 886 24022 CEFBS_InMicroMips_HasMips32r6, // BEQC_MMR6 = 887 24023 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BEQL = 888 24024 CEFBS_InMicroMips_NotMips32r6, // BEQZ16_MM = 889 24025 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BEQZALC = 890 24026 CEFBS_InMicroMips_HasMips32r6, // BEQZALC_MMR6 = 891 24027 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BEQZC = 892 24028 CEFBS_InMicroMips_HasMips32r6, // BEQZC16_MMR6 = 893 24029 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BEQZC64 = 894 24030 CEFBS_InMicroMips_NotMips32r6, // BEQZC_MM = 895 24031 CEFBS_InMicroMips_HasMips32r6, // BEQZC_MMR6 = 896 24032 CEFBS_InMicroMips_NotMips32r6, // BEQ_MM = 897 24033 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGEC = 898 24034 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BGEC64 = 899 24035 CEFBS_InMicroMips_HasMips32r6, // BGEC_MMR6 = 900 24036 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGEUC = 901 24037 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BGEUC64 = 902 24038 CEFBS_InMicroMips_HasMips32r6, // BGEUC_MMR6 = 903 24039 CEFBS_HasStdEnc_NotInMicroMips, // BGEZ = 904 24040 CEFBS_NotInMips16Mode_IsGP64bit, // BGEZ64 = 905 24041 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // BGEZAL = 906 24042 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGEZALC = 907 24043 CEFBS_InMicroMips_HasMips32r6, // BGEZALC_MMR6 = 908 24044 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BGEZALL = 909 24045 CEFBS_InMicroMips_NotMips32r6, // BGEZALS_MM = 910 24046 CEFBS_InMicroMips_NotMips32r6, // BGEZAL_MM = 911 24047 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGEZC = 912 24048 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BGEZC64 = 913 24049 CEFBS_InMicroMips_HasMips32r6, // BGEZC_MMR6 = 914 24050 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BGEZL = 915 24051 CEFBS_InMicroMips_NotMips32r6, // BGEZ_MM = 916 24052 CEFBS_HasStdEnc_NotInMicroMips, // BGTZ = 917 24053 CEFBS_NotInMips16Mode_IsGP64bit, // BGTZ64 = 918 24054 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGTZALC = 919 24055 CEFBS_InMicroMips_HasMips32r6, // BGTZALC_MMR6 = 920 24056 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGTZC = 921 24057 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BGTZC64 = 922 24058 CEFBS_InMicroMips_HasMips32r6, // BGTZC_MMR6 = 923 24059 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BGTZL = 924 24060 CEFBS_InMicroMips_NotMips32r6, // BGTZ_MM = 925 24061 CEFBS_HasStdEnc_HasMSA, // BINSLI_B = 926 24062 CEFBS_HasStdEnc_HasMSA, // BINSLI_D = 927 24063 CEFBS_HasStdEnc_HasMSA, // BINSLI_H = 928 24064 CEFBS_HasStdEnc_HasMSA, // BINSLI_W = 929 24065 CEFBS_HasStdEnc_HasMSA, // BINSL_B = 930 24066 CEFBS_HasStdEnc_HasMSA, // BINSL_D = 931 24067 CEFBS_HasStdEnc_HasMSA, // BINSL_H = 932 24068 CEFBS_HasStdEnc_HasMSA, // BINSL_W = 933 24069 CEFBS_HasStdEnc_HasMSA, // BINSRI_B = 934 24070 CEFBS_HasStdEnc_HasMSA, // BINSRI_D = 935 24071 CEFBS_HasStdEnc_HasMSA, // BINSRI_H = 936 24072 CEFBS_HasStdEnc_HasMSA, // BINSRI_W = 937 24073 CEFBS_HasStdEnc_HasMSA, // BINSR_B = 938 24074 CEFBS_HasStdEnc_HasMSA, // BINSR_D = 939 24075 CEFBS_HasStdEnc_HasMSA, // BINSR_H = 940 24076 CEFBS_HasStdEnc_HasMSA, // BINSR_W = 941 24077 CEFBS_HasDSP, // BITREV = 942 24078 CEFBS_InMicroMips_HasDSP, // BITREV_MM = 943 24079 CEFBS_HasStdEnc_HasMips32r6, // BITSWAP = 944 24080 CEFBS_InMicroMips_HasMips32r6, // BITSWAP_MMR6 = 945 24081 CEFBS_HasStdEnc_NotInMicroMips, // BLEZ = 946 24082 CEFBS_NotInMips16Mode_IsGP64bit, // BLEZ64 = 947 24083 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLEZALC = 948 24084 CEFBS_InMicroMips_HasMips32r6, // BLEZALC_MMR6 = 949 24085 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLEZC = 950 24086 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BLEZC64 = 951 24087 CEFBS_InMicroMips_HasMips32r6, // BLEZC_MMR6 = 952 24088 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BLEZL = 953 24089 CEFBS_InMicroMips_NotMips32r6, // BLEZ_MM = 954 24090 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLTC = 955 24091 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BLTC64 = 956 24092 CEFBS_InMicroMips_HasMips32r6, // BLTC_MMR6 = 957 24093 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLTUC = 958 24094 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BLTUC64 = 959 24095 CEFBS_InMicroMips_HasMips32r6, // BLTUC_MMR6 = 960 24096 CEFBS_HasStdEnc_NotInMicroMips, // BLTZ = 961 24097 CEFBS_NotInMips16Mode_IsGP64bit, // BLTZ64 = 962 24098 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // BLTZAL = 963 24099 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLTZALC = 964 24100 CEFBS_InMicroMips_HasMips32r6, // BLTZALC_MMR6 = 965 24101 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BLTZALL = 966 24102 CEFBS_InMicroMips_NotMips32r6, // BLTZALS_MM = 967 24103 CEFBS_InMicroMips_NotMips32r6, // BLTZAL_MM = 968 24104 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLTZC = 969 24105 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BLTZC64 = 970 24106 CEFBS_InMicroMips_HasMips32r6, // BLTZC_MMR6 = 971 24107 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BLTZL = 972 24108 CEFBS_InMicroMips_NotMips32r6, // BLTZ_MM = 973 24109 CEFBS_HasStdEnc_HasMSA, // BMNZI_B = 974 24110 CEFBS_HasStdEnc_HasMSA, // BMNZ_V = 975 24111 CEFBS_HasStdEnc_HasMSA, // BMZI_B = 976 24112 CEFBS_HasStdEnc_HasMSA, // BMZ_V = 977 24113 CEFBS_HasStdEnc_NotInMicroMips, // BNE = 978 24114 CEFBS_NotInMips16Mode_IsGP64bit, // BNE64 = 979 24115 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BNEC = 980 24116 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BNEC64 = 981 24117 CEFBS_InMicroMips_HasMips32r6, // BNEC_MMR6 = 982 24118 CEFBS_HasStdEnc_HasMSA, // BNEGI_B = 983 24119 CEFBS_HasStdEnc_HasMSA, // BNEGI_D = 984 24120 CEFBS_HasStdEnc_HasMSA, // BNEGI_H = 985 24121 CEFBS_HasStdEnc_HasMSA, // BNEGI_W = 986 24122 CEFBS_HasStdEnc_HasMSA, // BNEG_B = 987 24123 CEFBS_HasStdEnc_HasMSA, // BNEG_D = 988 24124 CEFBS_HasStdEnc_HasMSA, // BNEG_H = 989 24125 CEFBS_HasStdEnc_HasMSA, // BNEG_W = 990 24126 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BNEL = 991 24127 CEFBS_InMicroMips_NotMips32r6, // BNEZ16_MM = 992 24128 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BNEZALC = 993 24129 CEFBS_InMicroMips_HasMips32r6, // BNEZALC_MMR6 = 994 24130 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BNEZC = 995 24131 CEFBS_InMicroMips_HasMips32r6, // BNEZC16_MMR6 = 996 24132 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BNEZC64 = 997 24133 CEFBS_InMicroMips_NotMips32r6, // BNEZC_MM = 998 24134 CEFBS_InMicroMips_HasMips32r6, // BNEZC_MMR6 = 999 24135 CEFBS_InMicroMips_NotMips32r6, // BNE_MM = 1000 24136 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BNVC = 1001 24137 CEFBS_InMicroMips_HasMips32r6, // BNVC_MMR6 = 1002 24138 CEFBS_HasStdEnc_HasMSA, // BNZ_B = 1003 24139 CEFBS_HasStdEnc_HasMSA, // BNZ_D = 1004 24140 CEFBS_HasStdEnc_HasMSA, // BNZ_H = 1005 24141 CEFBS_HasStdEnc_HasMSA, // BNZ_V = 1006 24142 CEFBS_HasStdEnc_HasMSA, // BNZ_W = 1007 24143 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BOVC = 1008 24144 CEFBS_InMicroMips_HasMips32r6, // BOVC_MMR6 = 1009 24145 CEFBS_HasDSP_NotInMicroMips, // BPOSGE32 = 1010 24146 CEFBS_InMicroMips_HasDSPR3, // BPOSGE32C_MMR3 = 1011 24147 CEFBS_InMicroMips_NotMips32r6_HasDSP, // BPOSGE32_MM = 1012 24148 CEFBS_HasStdEnc_NotInMicroMips, // BREAK = 1013 24149 CEFBS_InMicroMips_NotMips32r6, // BREAK16_MM = 1014 24150 CEFBS_InMicroMips_HasMips32r6, // BREAK16_MMR6 = 1015 24151 CEFBS_InMicroMips, // BREAK_MM = 1016 24152 CEFBS_InMicroMips_HasMips32r6, // BREAK_MMR6 = 1017 24153 CEFBS_HasStdEnc_HasMSA, // BSELI_B = 1018 24154 CEFBS_HasStdEnc_HasMSA, // BSEL_V = 1019 24155 CEFBS_HasStdEnc_HasMSA, // BSETI_B = 1020 24156 CEFBS_HasStdEnc_HasMSA, // BSETI_D = 1021 24157 CEFBS_HasStdEnc_HasMSA, // BSETI_H = 1022 24158 CEFBS_HasStdEnc_HasMSA, // BSETI_W = 1023 24159 CEFBS_HasStdEnc_HasMSA, // BSET_B = 1024 24160 CEFBS_HasStdEnc_HasMSA, // BSET_D = 1025 24161 CEFBS_HasStdEnc_HasMSA, // BSET_H = 1026 24162 CEFBS_HasStdEnc_HasMSA, // BSET_W = 1027 24163 CEFBS_HasStdEnc_HasMSA, // BZ_B = 1028 24164 CEFBS_HasStdEnc_HasMSA, // BZ_D = 1029 24165 CEFBS_HasStdEnc_HasMSA, // BZ_H = 1030 24166 CEFBS_HasStdEnc_HasMSA, // BZ_V = 1031 24167 CEFBS_HasStdEnc_HasMSA, // BZ_W = 1032 24168 CEFBS_InMips16Mode, // BeqzRxImm16 = 1033 24169 CEFBS_InMips16Mode, // BeqzRxImmX16 = 1034 24170 CEFBS_InMips16Mode, // Bimm16 = 1035 24171 CEFBS_InMips16Mode, // BimmX16 = 1036 24172 CEFBS_InMips16Mode, // BnezRxImm16 = 1037 24173 CEFBS_InMips16Mode, // BnezRxImmX16 = 1038 24174 CEFBS_InMips16Mode, // Break16 = 1039 24175 CEFBS_InMips16Mode, // Bteqz16 = 1040 24176 CEFBS_InMips16Mode, // BteqzX16 = 1041 24177 CEFBS_InMips16Mode, // Btnez16 = 1042 24178 CEFBS_InMips16Mode, // BtnezX16 = 1043 24179 CEFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips, // CACHE = 1044 24180 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // CACHEE = 1045 24181 CEFBS_InMicroMips_HasEVA, // CACHEE_MM = 1046 24182 CEFBS_InMicroMips_NotMips32r6, // CACHE_MM = 1047 24183 CEFBS_InMicroMips_HasMips32r6, // CACHE_MMR6 = 1048 24184 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // CACHE_R6 = 1049 24185 CEFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, // CEIL_L_D64 = 1050 24186 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CEIL_L_D_MMR6 = 1051 24187 CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // CEIL_L_S = 1052 24188 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CEIL_L_S_MMR6 = 1053 24189 CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // CEIL_W_D32 = 1054 24190 CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // CEIL_W_D64 = 1055 24191 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CEIL_W_D_MMR6 = 1056 24192 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // CEIL_W_MM = 1057 24193 CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, // CEIL_W_S = 1058 24194 CEFBS_InMicroMips_IsNotSoftFloat, // CEIL_W_S_MM = 1059 24195 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CEIL_W_S_MMR6 = 1060 24196 CEFBS_HasStdEnc_HasMSA, // CEQI_B = 1061 24197 CEFBS_HasStdEnc_HasMSA, // CEQI_D = 1062 24198 CEFBS_HasStdEnc_HasMSA, // CEQI_H = 1063 24199 CEFBS_HasStdEnc_HasMSA, // CEQI_W = 1064 24200 CEFBS_HasStdEnc_HasMSA, // CEQ_B = 1065 24201 CEFBS_HasStdEnc_HasMSA, // CEQ_D = 1066 24202 CEFBS_HasStdEnc_HasMSA, // CEQ_H = 1067 24203 CEFBS_HasStdEnc_HasMSA, // CEQ_W = 1068 24204 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // CFC1 = 1069 24205 CEFBS_InMicroMips_IsNotSoftFloat, // CFC1_MM = 1070 24206 CEFBS_InMicroMips, // CFC2_MM = 1071 24207 CEFBS_HasStdEnc_HasMSA, // CFCMSA = 1072 24208 CEFBS_HasMips64_HasCnMips_NotInMicroMips, // CINS = 1073 24209 CEFBS_HasMips64_HasCnMips_NotInMicroMips, // CINS32 = 1074 24210 CEFBS_HasMips64_HasCnMips_NotInMicroMips, // CINS64_32 = 1075 24211 CEFBS_HasMips64_HasCnMips_NotInMicroMips, // CINS_i32 = 1076 24212 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CLASS_D = 1077 24213 CEFBS_InMicroMips_HasMips32r6, // CLASS_D_MMR6 = 1078 24214 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CLASS_S = 1079 24215 CEFBS_InMicroMips_HasMips32r6, // CLASS_S_MMR6 = 1080 24216 CEFBS_HasStdEnc_HasMSA, // CLEI_S_B = 1081 24217 CEFBS_HasStdEnc_HasMSA, // CLEI_S_D = 1082 24218 CEFBS_HasStdEnc_HasMSA, // CLEI_S_H = 1083 24219 CEFBS_HasStdEnc_HasMSA, // CLEI_S_W = 1084 24220 CEFBS_HasStdEnc_HasMSA, // CLEI_U_B = 1085 24221 CEFBS_HasStdEnc_HasMSA, // CLEI_U_D = 1086 24222 CEFBS_HasStdEnc_HasMSA, // CLEI_U_H = 1087 24223 CEFBS_HasStdEnc_HasMSA, // CLEI_U_W = 1088 24224 CEFBS_HasStdEnc_HasMSA, // CLE_S_B = 1089 24225 CEFBS_HasStdEnc_HasMSA, // CLE_S_D = 1090 24226 CEFBS_HasStdEnc_HasMSA, // CLE_S_H = 1091 24227 CEFBS_HasStdEnc_HasMSA, // CLE_S_W = 1092 24228 CEFBS_HasStdEnc_HasMSA, // CLE_U_B = 1093 24229 CEFBS_HasStdEnc_HasMSA, // CLE_U_D = 1094 24230 CEFBS_HasStdEnc_HasMSA, // CLE_U_H = 1095 24231 CEFBS_HasStdEnc_HasMSA, // CLE_U_W = 1096 24232 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // CLO = 1097 24233 CEFBS_InMicroMips, // CLO_MM = 1098 24234 CEFBS_InMicroMips_HasMips32r6, // CLO_MMR6 = 1099 24235 CEFBS_HasStdEnc_HasMips32r6, // CLO_R6 = 1100 24236 CEFBS_HasStdEnc_HasMSA, // CLTI_S_B = 1101 24237 CEFBS_HasStdEnc_HasMSA, // CLTI_S_D = 1102 24238 CEFBS_HasStdEnc_HasMSA, // CLTI_S_H = 1103 24239 CEFBS_HasStdEnc_HasMSA, // CLTI_S_W = 1104 24240 CEFBS_HasStdEnc_HasMSA, // CLTI_U_B = 1105 24241 CEFBS_HasStdEnc_HasMSA, // CLTI_U_D = 1106 24242 CEFBS_HasStdEnc_HasMSA, // CLTI_U_H = 1107 24243 CEFBS_HasStdEnc_HasMSA, // CLTI_U_W = 1108 24244 CEFBS_HasStdEnc_HasMSA, // CLT_S_B = 1109 24245 CEFBS_HasStdEnc_HasMSA, // CLT_S_D = 1110 24246 CEFBS_HasStdEnc_HasMSA, // CLT_S_H = 1111 24247 CEFBS_HasStdEnc_HasMSA, // CLT_S_W = 1112 24248 CEFBS_HasStdEnc_HasMSA, // CLT_U_B = 1113 24249 CEFBS_HasStdEnc_HasMSA, // CLT_U_D = 1114 24250 CEFBS_HasStdEnc_HasMSA, // CLT_U_H = 1115 24251 CEFBS_HasStdEnc_HasMSA, // CLT_U_W = 1116 24252 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // CLZ = 1117 24253 CEFBS_InMicroMips, // CLZ_MM = 1118 24254 CEFBS_InMicroMips_HasMips32r6, // CLZ_MMR6 = 1119 24255 CEFBS_HasStdEnc_HasMips32r6, // CLZ_R6 = 1120 24256 CEFBS_HasDSPR2, // CMPGDU_EQ_QB = 1121 24257 CEFBS_InMicroMips_HasDSPR2, // CMPGDU_EQ_QB_MMR2 = 1122 24258 CEFBS_HasDSPR2, // CMPGDU_LE_QB = 1123 24259 CEFBS_InMicroMips_HasDSPR2, // CMPGDU_LE_QB_MMR2 = 1124 24260 CEFBS_HasDSPR2, // CMPGDU_LT_QB = 1125 24261 CEFBS_InMicroMips_HasDSPR2, // CMPGDU_LT_QB_MMR2 = 1126 24262 CEFBS_HasDSP, // CMPGU_EQ_QB = 1127 24263 CEFBS_InMicroMips_HasDSP, // CMPGU_EQ_QB_MM = 1128 24264 CEFBS_HasDSP, // CMPGU_LE_QB = 1129 24265 CEFBS_InMicroMips_HasDSP, // CMPGU_LE_QB_MM = 1130 24266 CEFBS_HasDSP, // CMPGU_LT_QB = 1131 24267 CEFBS_InMicroMips_HasDSP, // CMPGU_LT_QB_MM = 1132 24268 CEFBS_HasDSP, // CMPU_EQ_QB = 1133 24269 CEFBS_InMicroMips_HasDSP, // CMPU_EQ_QB_MM = 1134 24270 CEFBS_HasDSP, // CMPU_LE_QB = 1135 24271 CEFBS_InMicroMips_HasDSP, // CMPU_LE_QB_MM = 1136 24272 CEFBS_HasDSP, // CMPU_LT_QB = 1137 24273 CEFBS_InMicroMips_HasDSP, // CMPU_LT_QB_MM = 1138 24274 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_AF_D_MMR6 = 1139 24275 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_AF_S_MMR6 = 1140 24276 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_EQ_D = 1141 24277 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_EQ_D_MMR6 = 1142 24278 CEFBS_HasDSP, // CMP_EQ_PH = 1143 24279 CEFBS_InMicroMips_HasDSP, // CMP_EQ_PH_MM = 1144 24280 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_EQ_S = 1145 24281 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_EQ_S_MMR6 = 1146 24282 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_F_D = 1147 24283 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_F_S = 1148 24284 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_LE_D = 1149 24285 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_LE_D_MMR6 = 1150 24286 CEFBS_HasDSP, // CMP_LE_PH = 1151 24287 CEFBS_InMicroMips_HasDSP, // CMP_LE_PH_MM = 1152 24288 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_LE_S = 1153 24289 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_LE_S_MMR6 = 1154 24290 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_LT_D = 1155 24291 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_LT_D_MMR6 = 1156 24292 CEFBS_HasDSP, // CMP_LT_PH = 1157 24293 CEFBS_InMicroMips_HasDSP, // CMP_LT_PH_MM = 1158 24294 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_LT_S = 1159 24295 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_LT_S_MMR6 = 1160 24296 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SAF_D = 1161 24297 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SAF_D_MMR6 = 1162 24298 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SAF_S = 1163 24299 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SAF_S_MMR6 = 1164 24300 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SEQ_D = 1165 24301 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SEQ_D_MMR6 = 1166 24302 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SEQ_S = 1167 24303 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SEQ_S_MMR6 = 1168 24304 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SLE_D = 1169 24305 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SLE_D_MMR6 = 1170 24306 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SLE_S = 1171 24307 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SLE_S_MMR6 = 1172 24308 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SLT_D = 1173 24309 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SLT_D_MMR6 = 1174 24310 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SLT_S = 1175 24311 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SLT_S_MMR6 = 1176 24312 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SUEQ_D = 1177 24313 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SUEQ_D_MMR6 = 1178 24314 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SUEQ_S = 1179 24315 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SUEQ_S_MMR6 = 1180 24316 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SULE_D = 1181 24317 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SULE_D_MMR6 = 1182 24318 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SULE_S = 1183 24319 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SULE_S_MMR6 = 1184 24320 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SULT_D = 1185 24321 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SULT_D_MMR6 = 1186 24322 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SULT_S = 1187 24323 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SULT_S_MMR6 = 1188 24324 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SUN_D = 1189 24325 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SUN_D_MMR6 = 1190 24326 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SUN_S = 1191 24327 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SUN_S_MMR6 = 1192 24328 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_UEQ_D = 1193 24329 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_UEQ_D_MMR6 = 1194 24330 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_UEQ_S = 1195 24331 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_UEQ_S_MMR6 = 1196 24332 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_ULE_D = 1197 24333 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_ULE_D_MMR6 = 1198 24334 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_ULE_S = 1199 24335 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_ULE_S_MMR6 = 1200 24336 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_ULT_D = 1201 24337 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_ULT_D_MMR6 = 1202 24338 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_ULT_S = 1203 24339 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_ULT_S_MMR6 = 1204 24340 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_UN_D = 1205 24341 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_UN_D_MMR6 = 1206 24342 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_UN_S = 1207 24343 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_UN_S_MMR6 = 1208 24344 CEFBS_HasStdEnc_HasMSA, // COPY_S_B = 1209 24345 CEFBS_HasStdEnc_HasMSA_HasMips64, // COPY_S_D = 1210 24346 CEFBS_HasStdEnc_HasMSA, // COPY_S_H = 1211 24347 CEFBS_HasStdEnc_HasMSA, // COPY_S_W = 1212 24348 CEFBS_HasStdEnc_HasMSA, // COPY_U_B = 1213 24349 CEFBS_HasStdEnc_HasMSA, // COPY_U_H = 1214 24350 CEFBS_HasStdEnc_HasMSA_HasMips64, // COPY_U_W = 1215 24351 CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32B = 1216 24352 CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32CB = 1217 24353 CEFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips, // CRC32CD = 1218 24354 CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32CH = 1219 24355 CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32CW = 1220 24356 CEFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips, // CRC32D = 1221 24357 CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32H = 1222 24358 CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32W = 1223 24359 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // CTC1 = 1224 24360 CEFBS_InMicroMips_IsNotSoftFloat, // CTC1_MM = 1225 24361 CEFBS_InMicroMips, // CTC2_MM = 1226 24362 CEFBS_HasStdEnc_HasMSA, // CTCMSA = 1227 24363 CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_D32_S = 1228 24364 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // CVT_D32_S_MM = 1229 24365 CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_D32_W = 1230 24366 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // CVT_D32_W_MM = 1231 24367 CEFBS_HasStdEnc_IsFP64bit_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, // CVT_D64_L = 1232 24368 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_D64_S = 1233 24369 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_D64_S_MM = 1234 24370 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_D64_W = 1235 24371 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_D64_W_MM = 1236 24372 CEFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, // CVT_D_L_MMR6 = 1237 24373 CEFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, // CVT_L_D64 = 1238 24374 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_L_D64_MM = 1239 24375 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CVT_L_D_MMR6 = 1240 24376 CEFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, // CVT_L_S = 1241 24377 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_L_S_MM = 1242 24378 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CVT_L_S_MMR6 = 1243 24379 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, // CVT_PS_PW64 = 1244 24380 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // CVT_PS_S64 = 1245 24381 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, // CVT_PW_PS64 = 1246 24382 CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_S_D32 = 1247 24383 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // CVT_S_D32_MM = 1248 24384 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_S_D64 = 1249 24385 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_S_D64_MM = 1250 24386 CEFBS_HasStdEnc_IsFP64bit_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, // CVT_S_L = 1251 24387 CEFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, // CVT_S_L_MMR6 = 1252 24388 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // CVT_S_PL64 = 1253 24389 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // CVT_S_PU64 = 1254 24390 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // CVT_S_W = 1255 24391 CEFBS_InMicroMips_IsNotSoftFloat, // CVT_S_W_MM = 1256 24392 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CVT_S_W_MMR6 = 1257 24393 CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_W_D32 = 1258 24394 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // CVT_W_D32_MM = 1259 24395 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_W_D64 = 1260 24396 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_W_D64_MM = 1261 24397 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // CVT_W_S = 1262 24398 CEFBS_InMicroMips_IsNotSoftFloat, // CVT_W_S_MM = 1263 24399 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CVT_W_S_MMR6 = 1264 24400 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_EQ_D32 = 1265 24401 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_EQ_D32_MM = 1266 24402 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_EQ_D64 = 1267 24403 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_EQ_D64_MM = 1268 24404 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_EQ_S = 1269 24405 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_EQ_S_MM = 1270 24406 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_F_D32 = 1271 24407 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_F_D32_MM = 1272 24408 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_F_D64 = 1273 24409 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_F_D64_MM = 1274 24410 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_F_S = 1275 24411 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_F_S_MM = 1276 24412 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LE_D32 = 1277 24413 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_LE_D32_MM = 1278 24414 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LE_D64 = 1279 24415 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_LE_D64_MM = 1280 24416 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LE_S = 1281 24417 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_LE_S_MM = 1282 24418 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LT_D32 = 1283 24419 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_LT_D32_MM = 1284 24420 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LT_D64 = 1285 24421 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_LT_D64_MM = 1286 24422 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LT_S = 1287 24423 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_LT_S_MM = 1288 24424 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGE_D32 = 1289 24425 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGE_D32_MM = 1290 24426 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGE_D64 = 1291 24427 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGE_D64_MM = 1292 24428 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGE_S = 1293 24429 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_NGE_S_MM = 1294 24430 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGLE_D32 = 1295 24431 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGLE_D32_MM = 1296 24432 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGLE_D64 = 1297 24433 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGLE_D64_MM = 1298 24434 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGLE_S = 1299 24435 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_NGLE_S_MM = 1300 24436 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGL_D32 = 1301 24437 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGL_D32_MM = 1302 24438 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGL_D64 = 1303 24439 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGL_D64_MM = 1304 24440 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGL_S = 1305 24441 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_NGL_S_MM = 1306 24442 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGT_D32 = 1307 24443 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGT_D32_MM = 1308 24444 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGT_D64 = 1309 24445 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGT_D64_MM = 1310 24446 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGT_S = 1311 24447 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_NGT_S_MM = 1312 24448 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLE_D32 = 1313 24449 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_OLE_D32_MM = 1314 24450 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLE_D64 = 1315 24451 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_OLE_D64_MM = 1316 24452 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLE_S = 1317 24453 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_OLE_S_MM = 1318 24454 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLT_D32 = 1319 24455 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_OLT_D32_MM = 1320 24456 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLT_D64 = 1321 24457 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_OLT_D64_MM = 1322 24458 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLT_S = 1323 24459 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_OLT_S_MM = 1324 24460 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SEQ_D32 = 1325 24461 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_SEQ_D32_MM = 1326 24462 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SEQ_D64 = 1327 24463 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_SEQ_D64_MM = 1328 24464 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SEQ_S = 1329 24465 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_SEQ_S_MM = 1330 24466 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SF_D32 = 1331 24467 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_SF_D32_MM = 1332 24468 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SF_D64 = 1333 24469 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_SF_D64_MM = 1334 24470 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SF_S = 1335 24471 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_SF_S_MM = 1336 24472 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UEQ_D32 = 1337 24473 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_UEQ_D32_MM = 1338 24474 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UEQ_D64 = 1339 24475 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_UEQ_D64_MM = 1340 24476 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UEQ_S = 1341 24477 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_UEQ_S_MM = 1342 24478 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULE_D32 = 1343 24479 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_ULE_D32_MM = 1344 24480 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULE_D64 = 1345 24481 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_ULE_D64_MM = 1346 24482 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULE_S = 1347 24483 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_ULE_S_MM = 1348 24484 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULT_D32 = 1349 24485 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_ULT_D32_MM = 1350 24486 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULT_D64 = 1351 24487 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_ULT_D64_MM = 1352 24488 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULT_S = 1353 24489 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_ULT_S_MM = 1354 24490 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UN_D32 = 1355 24491 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_UN_D32_MM = 1356 24492 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UN_D64 = 1357 24493 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_UN_D64_MM = 1358 24494 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UN_S = 1359 24495 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_UN_S_MM = 1360 24496 CEFBS_InMips16Mode, // CmpRxRy16 = 1361 24497 CEFBS_InMips16Mode, // CmpiRxImm16 = 1362 24498 CEFBS_InMips16Mode, // CmpiRxImmX16 = 1363 24499 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DADD = 1364 24500 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // DADDi = 1365 24501 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DADDiu = 1366 24502 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DADDu = 1367 24503 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DAHI = 1368 24504 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DALIGN = 1369 24505 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DATI = 1370 24506 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DAUI = 1371 24507 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DBITSWAP = 1372 24508 CEFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips, // DCLO = 1373 24509 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DCLO_R6 = 1374 24510 CEFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips, // DCLZ = 1375 24511 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DCLZ_R6 = 1376 24512 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DDIV = 1377 24513 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DDIVU = 1378 24514 CEFBS_HasStdEnc_HasMips32_NotInMicroMips, // DERET = 1379 24515 CEFBS_InMicroMips, // DERET_MM = 1380 24516 CEFBS_InMicroMips_HasMips32r6, // DERET_MMR6 = 1381 24517 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DEXT = 1382 24518 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DEXT64_32 = 1383 24519 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DEXTM = 1384 24520 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DEXTU = 1385 24521 CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // DI = 1386 24522 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DINS = 1387 24523 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DINSM = 1388 24524 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DINSU = 1389 24525 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // DIV = 1390 24526 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // DIVU = 1391 24527 CEFBS_InMicroMips_HasMips32r6, // DIVU_MMR6 = 1392 24528 CEFBS_InMicroMips_HasMips32r6, // DIV_MMR6 = 1393 24529 CEFBS_HasStdEnc_HasMSA, // DIV_S_B = 1394 24530 CEFBS_HasStdEnc_HasMSA, // DIV_S_D = 1395 24531 CEFBS_HasStdEnc_HasMSA, // DIV_S_H = 1396 24532 CEFBS_HasStdEnc_HasMSA, // DIV_S_W = 1397 24533 CEFBS_HasStdEnc_HasMSA, // DIV_U_B = 1398 24534 CEFBS_HasStdEnc_HasMSA, // DIV_U_D = 1399 24535 CEFBS_HasStdEnc_HasMSA, // DIV_U_H = 1400 24536 CEFBS_HasStdEnc_HasMSA, // DIV_U_W = 1401 24537 CEFBS_InMicroMips, // DI_MM = 1402 24538 CEFBS_InMicroMips_HasMips32r6, // DI_MMR6 = 1403 24539 CEFBS_HasStdEnc_HasMSA_HasMips64, // DLSA = 1404 24540 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DLSA_R6 = 1405 24541 CEFBS_HasStdEnc_IsGP64bit_HasMips3, // DMFC0 = 1406 24542 CEFBS_HasStdEnc_HasMips3_IsNotSoftFloat_NotInMicroMips, // DMFC1 = 1407 24543 CEFBS_HasStdEnc_IsGP64bit_HasMips3, // DMFC2 = 1408 24544 CEFBS_HasCnMips, // DMFC2_OCTEON = 1409 24545 CEFBS_HasStdEnc_HasMips64r5_HasVirt, // DMFGC0 = 1410 24546 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMOD = 1411 24547 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMODU = 1412 24548 CEFBS_HasStdEnc_HasMT_NotInMicroMips, // DMT = 1413 24549 CEFBS_HasStdEnc_IsGP64bit_HasMips3, // DMTC0 = 1414 24550 CEFBS_HasStdEnc_HasMips3_IsNotSoftFloat_NotInMicroMips, // DMTC1 = 1415 24551 CEFBS_HasStdEnc_IsGP64bit_HasMips3, // DMTC2 = 1416 24552 CEFBS_HasCnMips, // DMTC2_OCTEON = 1417 24553 CEFBS_HasStdEnc_HasMips64r5_HasVirt, // DMTGC0 = 1418 24554 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMUH = 1419 24555 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMUHU = 1420 24556 CEFBS_HasCnMips, // DMUL = 1421 24557 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DMULT = 1422 24558 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DMULTu = 1423 24559 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMULU = 1424 24560 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMUL_R6 = 1425 24561 CEFBS_HasStdEnc_HasMSA, // DOTP_S_D = 1426 24562 CEFBS_HasStdEnc_HasMSA, // DOTP_S_H = 1427 24563 CEFBS_HasStdEnc_HasMSA, // DOTP_S_W = 1428 24564 CEFBS_HasStdEnc_HasMSA, // DOTP_U_D = 1429 24565 CEFBS_HasStdEnc_HasMSA, // DOTP_U_H = 1430 24566 CEFBS_HasStdEnc_HasMSA, // DOTP_U_W = 1431 24567 CEFBS_HasStdEnc_HasMSA, // DPADD_S_D = 1432 24568 CEFBS_HasStdEnc_HasMSA, // DPADD_S_H = 1433 24569 CEFBS_HasStdEnc_HasMSA, // DPADD_S_W = 1434 24570 CEFBS_HasStdEnc_HasMSA, // DPADD_U_D = 1435 24571 CEFBS_HasStdEnc_HasMSA, // DPADD_U_H = 1436 24572 CEFBS_HasStdEnc_HasMSA, // DPADD_U_W = 1437 24573 CEFBS_HasDSPR2, // DPAQX_SA_W_PH = 1438 24574 CEFBS_InMicroMips_HasDSPR2, // DPAQX_SA_W_PH_MMR2 = 1439 24575 CEFBS_HasDSPR2, // DPAQX_S_W_PH = 1440 24576 CEFBS_InMicroMips_HasDSPR2, // DPAQX_S_W_PH_MMR2 = 1441 24577 CEFBS_HasDSP, // DPAQ_SA_L_W = 1442 24578 CEFBS_InMicroMips_HasDSP, // DPAQ_SA_L_W_MM = 1443 24579 CEFBS_HasDSP, // DPAQ_S_W_PH = 1444 24580 CEFBS_InMicroMips_HasDSP, // DPAQ_S_W_PH_MM = 1445 24581 CEFBS_HasDSP, // DPAU_H_QBL = 1446 24582 CEFBS_InMicroMips_HasDSP, // DPAU_H_QBL_MM = 1447 24583 CEFBS_HasDSP, // DPAU_H_QBR = 1448 24584 CEFBS_InMicroMips_HasDSP, // DPAU_H_QBR_MM = 1449 24585 CEFBS_HasDSPR2, // DPAX_W_PH = 1450 24586 CEFBS_InMicroMips_HasDSPR2, // DPAX_W_PH_MMR2 = 1451 24587 CEFBS_HasDSPR2, // DPA_W_PH = 1452 24588 CEFBS_InMicroMips_HasDSPR2, // DPA_W_PH_MMR2 = 1453 24589 CEFBS_HasCnMips, // DPOP = 1454 24590 CEFBS_HasDSPR2, // DPSQX_SA_W_PH = 1455 24591 CEFBS_InMicroMips_HasDSPR2, // DPSQX_SA_W_PH_MMR2 = 1456 24592 CEFBS_HasDSPR2, // DPSQX_S_W_PH = 1457 24593 CEFBS_InMicroMips_HasDSPR2, // DPSQX_S_W_PH_MMR2 = 1458 24594 CEFBS_HasDSP, // DPSQ_SA_L_W = 1459 24595 CEFBS_InMicroMips_HasDSP, // DPSQ_SA_L_W_MM = 1460 24596 CEFBS_HasDSP, // DPSQ_S_W_PH = 1461 24597 CEFBS_InMicroMips_HasDSP, // DPSQ_S_W_PH_MM = 1462 24598 CEFBS_HasStdEnc_HasMSA, // DPSUB_S_D = 1463 24599 CEFBS_HasStdEnc_HasMSA, // DPSUB_S_H = 1464 24600 CEFBS_HasStdEnc_HasMSA, // DPSUB_S_W = 1465 24601 CEFBS_HasStdEnc_HasMSA, // DPSUB_U_D = 1466 24602 CEFBS_HasStdEnc_HasMSA, // DPSUB_U_H = 1467 24603 CEFBS_HasStdEnc_HasMSA, // DPSUB_U_W = 1468 24604 CEFBS_HasDSP, // DPSU_H_QBL = 1469 24605 CEFBS_InMicroMips_HasDSP, // DPSU_H_QBL_MM = 1470 24606 CEFBS_HasDSP, // DPSU_H_QBR = 1471 24607 CEFBS_InMicroMips_HasDSP, // DPSU_H_QBR_MM = 1472 24608 CEFBS_HasDSPR2, // DPSX_W_PH = 1473 24609 CEFBS_InMicroMips_HasDSPR2, // DPSX_W_PH_MMR2 = 1474 24610 CEFBS_HasDSPR2, // DPS_W_PH = 1475 24611 CEFBS_InMicroMips_HasDSPR2, // DPS_W_PH_MMR2 = 1476 24612 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DROTR = 1477 24613 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DROTR32 = 1478 24614 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DROTRV = 1479 24615 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DSBH = 1480 24616 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DSDIV = 1481 24617 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DSHD = 1482 24618 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSLL = 1483 24619 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSLL32 = 1484 24620 CEFBS_NotInMips16Mode_IsGP64bit, // DSLL64_32 = 1485 24621 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSLLV = 1486 24622 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRA = 1487 24623 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRA32 = 1488 24624 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRAV = 1489 24625 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRL = 1490 24626 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRL32 = 1491 24627 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRLV = 1492 24628 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSUB = 1493 24629 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSUBu = 1494 24630 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DUDIV = 1495 24631 CEFBS_HasStdEnc_HasMips32r6, // DVP = 1496 24632 CEFBS_HasStdEnc_HasMT_NotInMicroMips, // DVPE = 1497 24633 CEFBS_InMicroMips_HasMips32r6, // DVP_MMR6 = 1498 24634 CEFBS_InMips16Mode, // DivRxRy16 = 1499 24635 CEFBS_InMips16Mode, // DivuRxRy16 = 1500 24636 CEFBS_HasStdEnc_NotInMicroMips, // EHB = 1501 24637 CEFBS_InMicroMips, // EHB_MM = 1502 24638 CEFBS_InMicroMips_HasMips32r6, // EHB_MMR6 = 1503 24639 CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // EI = 1504 24640 CEFBS_InMicroMips, // EI_MM = 1505 24641 CEFBS_InMicroMips_HasMips32r6, // EI_MMR6 = 1506 24642 CEFBS_HasStdEnc_HasMT_NotInMicroMips, // EMT = 1507 24643 CEFBS_HasStdEnc_HasMips3_32_NotInMicroMips, // ERET = 1508 24644 CEFBS_HasStdEnc_HasMips32r5_NotInMicroMips, // ERETNC = 1509 24645 CEFBS_InMicroMips_HasMips32r6, // ERETNC_MMR6 = 1510 24646 CEFBS_InMicroMips, // ERET_MM = 1511 24647 CEFBS_InMicroMips_HasMips32r6, // ERET_MMR6 = 1512 24648 CEFBS_HasStdEnc_HasMips32r6, // EVP = 1513 24649 CEFBS_HasStdEnc_HasMT_NotInMicroMips, // EVPE = 1514 24650 CEFBS_InMicroMips_HasMips32r6, // EVP_MMR6 = 1515 24651 CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // EXT = 1516 24652 CEFBS_HasDSP, // EXTP = 1517 24653 CEFBS_HasDSP, // EXTPDP = 1518 24654 CEFBS_HasDSP, // EXTPDPV = 1519 24655 CEFBS_InMicroMips_HasDSP, // EXTPDPV_MM = 1520 24656 CEFBS_InMicroMips_HasDSP, // EXTPDP_MM = 1521 24657 CEFBS_HasDSP, // EXTPV = 1522 24658 CEFBS_InMicroMips_HasDSP, // EXTPV_MM = 1523 24659 CEFBS_InMicroMips_HasDSP, // EXTP_MM = 1524 24660 CEFBS_HasDSP, // EXTRV_RS_W = 1525 24661 CEFBS_InMicroMips_HasDSP, // EXTRV_RS_W_MM = 1526 24662 CEFBS_HasDSP, // EXTRV_R_W = 1527 24663 CEFBS_InMicroMips_HasDSP, // EXTRV_R_W_MM = 1528 24664 CEFBS_HasDSP, // EXTRV_S_H = 1529 24665 CEFBS_InMicroMips_HasDSP, // EXTRV_S_H_MM = 1530 24666 CEFBS_HasDSP, // EXTRV_W = 1531 24667 CEFBS_InMicroMips_HasDSP, // EXTRV_W_MM = 1532 24668 CEFBS_HasDSP, // EXTR_RS_W = 1533 24669 CEFBS_InMicroMips_HasDSP, // EXTR_RS_W_MM = 1534 24670 CEFBS_HasDSP, // EXTR_R_W = 1535 24671 CEFBS_InMicroMips_HasDSP, // EXTR_R_W_MM = 1536 24672 CEFBS_HasDSP, // EXTR_S_H = 1537 24673 CEFBS_InMicroMips_HasDSP, // EXTR_S_H_MM = 1538 24674 CEFBS_HasDSP, // EXTR_W = 1539 24675 CEFBS_InMicroMips_HasDSP, // EXTR_W_MM = 1540 24676 CEFBS_HasMips64_HasCnMips_NotInMicroMips, // EXTS = 1541 24677 CEFBS_HasMips64_HasCnMips_NotInMicroMips, // EXTS32 = 1542 24678 CEFBS_InMicroMips_NotMips32r6, // EXT_MM = 1543 24679 CEFBS_InMicroMips_HasMips32r6, // EXT_MMR6 = 1544 24680 CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FABS_D32 = 1545 24681 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FABS_D32_MM = 1546 24682 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FABS_D64 = 1547 24683 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FABS_D64_MM = 1548 24684 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FABS_S = 1549 24685 CEFBS_InMicroMips_IsNotSoftFloat, // FABS_S_MM = 1550 24686 CEFBS_HasStdEnc_HasMSA, // FADD_D = 1551 24687 CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FADD_D32 = 1552 24688 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FADD_D32_MM = 1553 24689 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FADD_D64 = 1554 24690 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FADD_D64_MM = 1555 24691 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // FADD_PS64 = 1556 24692 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FADD_S = 1557 24693 CEFBS_InMicroMips_IsNotSoftFloat, // FADD_S_MM = 1558 24694 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FADD_S_MMR6 = 1559 24695 CEFBS_HasStdEnc_HasMSA, // FADD_W = 1560 24696 CEFBS_HasStdEnc_HasMSA, // FCAF_D = 1561 24697 CEFBS_HasStdEnc_HasMSA, // FCAF_W = 1562 24698 CEFBS_HasStdEnc_HasMSA, // FCEQ_D = 1563 24699 CEFBS_HasStdEnc_HasMSA, // FCEQ_W = 1564 24700 CEFBS_HasStdEnc_HasMSA, // FCLASS_D = 1565 24701 CEFBS_HasStdEnc_HasMSA, // FCLASS_W = 1566 24702 CEFBS_HasStdEnc_HasMSA, // FCLE_D = 1567 24703 CEFBS_HasStdEnc_HasMSA, // FCLE_W = 1568 24704 CEFBS_HasStdEnc_HasMSA, // FCLT_D = 1569 24705 CEFBS_HasStdEnc_HasMSA, // FCLT_W = 1570 24706 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // FCMP_D32 = 1571 24707 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // FCMP_D32_MM = 1572 24708 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat, // FCMP_D64 = 1573 24709 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // FCMP_S32 = 1574 24710 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // FCMP_S32_MM = 1575 24711 CEFBS_HasStdEnc_HasMSA, // FCNE_D = 1576 24712 CEFBS_HasStdEnc_HasMSA, // FCNE_W = 1577 24713 CEFBS_HasStdEnc_HasMSA, // FCOR_D = 1578 24714 CEFBS_HasStdEnc_HasMSA, // FCOR_W = 1579 24715 CEFBS_HasStdEnc_HasMSA, // FCUEQ_D = 1580 24716 CEFBS_HasStdEnc_HasMSA, // FCUEQ_W = 1581 24717 CEFBS_HasStdEnc_HasMSA, // FCULE_D = 1582 24718 CEFBS_HasStdEnc_HasMSA, // FCULE_W = 1583 24719 CEFBS_HasStdEnc_HasMSA, // FCULT_D = 1584 24720 CEFBS_HasStdEnc_HasMSA, // FCULT_W = 1585 24721 CEFBS_HasStdEnc_HasMSA, // FCUNE_D = 1586 24722 CEFBS_HasStdEnc_HasMSA, // FCUNE_W = 1587 24723 CEFBS_HasStdEnc_HasMSA, // FCUN_D = 1588 24724 CEFBS_HasStdEnc_HasMSA, // FCUN_W = 1589 24725 CEFBS_HasStdEnc_HasMSA, // FDIV_D = 1590 24726 CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FDIV_D32 = 1591 24727 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FDIV_D32_MM = 1592 24728 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FDIV_D64 = 1593 24729 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FDIV_D64_MM = 1594 24730 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FDIV_S = 1595 24731 CEFBS_InMicroMips_IsNotSoftFloat, // FDIV_S_MM = 1596 24732 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FDIV_S_MMR6 = 1597 24733 CEFBS_HasStdEnc_HasMSA, // FDIV_W = 1598 24734 CEFBS_HasStdEnc_HasMSA, // FEXDO_H = 1599 24735 CEFBS_HasStdEnc_HasMSA, // FEXDO_W = 1600 24736 CEFBS_HasStdEnc_HasMSA, // FEXP2_D = 1601 24737 CEFBS_HasStdEnc_HasMSA, // FEXP2_W = 1602 24738 CEFBS_HasStdEnc_HasMSA, // FEXUPL_D = 1603 24739 CEFBS_HasStdEnc_HasMSA, // FEXUPL_W = 1604 24740 CEFBS_HasStdEnc_HasMSA, // FEXUPR_D = 1605 24741 CEFBS_HasStdEnc_HasMSA, // FEXUPR_W = 1606 24742 CEFBS_HasStdEnc_HasMSA, // FFINT_S_D = 1607 24743 CEFBS_HasStdEnc_HasMSA, // FFINT_S_W = 1608 24744 CEFBS_HasStdEnc_HasMSA, // FFINT_U_D = 1609 24745 CEFBS_HasStdEnc_HasMSA, // FFINT_U_W = 1610 24746 CEFBS_HasStdEnc_HasMSA, // FFQL_D = 1611 24747 CEFBS_HasStdEnc_HasMSA, // FFQL_W = 1612 24748 CEFBS_HasStdEnc_HasMSA, // FFQR_D = 1613 24749 CEFBS_HasStdEnc_HasMSA, // FFQR_W = 1614 24750 CEFBS_HasStdEnc_HasMSA, // FILL_B = 1615 24751 CEFBS_HasStdEnc_HasMSA_HasMips64, // FILL_D = 1616 24752 CEFBS_HasStdEnc_HasMSA, // FILL_H = 1617 24753 CEFBS_HasStdEnc_HasMSA, // FILL_W = 1618 24754 CEFBS_HasStdEnc_HasMSA, // FLOG2_D = 1619 24755 CEFBS_HasStdEnc_HasMSA, // FLOG2_W = 1620 24756 CEFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, // FLOOR_L_D64 = 1621 24757 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FLOOR_L_D_MMR6 = 1622 24758 CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // FLOOR_L_S = 1623 24759 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FLOOR_L_S_MMR6 = 1624 24760 CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // FLOOR_W_D32 = 1625 24761 CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // FLOOR_W_D64 = 1626 24762 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FLOOR_W_D_MMR6 = 1627 24763 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FLOOR_W_MM = 1628 24764 CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, // FLOOR_W_S = 1629 24765 CEFBS_InMicroMips_IsNotSoftFloat, // FLOOR_W_S_MM = 1630 24766 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FLOOR_W_S_MMR6 = 1631 24767 CEFBS_HasStdEnc_HasMSA, // FMADD_D = 1632 24768 CEFBS_HasStdEnc_HasMSA, // FMADD_W = 1633 24769 CEFBS_HasStdEnc_HasMSA, // FMAX_A_D = 1634 24770 CEFBS_HasStdEnc_HasMSA, // FMAX_A_W = 1635 24771 CEFBS_HasStdEnc_HasMSA, // FMAX_D = 1636 24772 CEFBS_HasStdEnc_HasMSA, // FMAX_W = 1637 24773 CEFBS_HasStdEnc_HasMSA, // FMIN_A_D = 1638 24774 CEFBS_HasStdEnc_HasMSA, // FMIN_A_W = 1639 24775 CEFBS_HasStdEnc_HasMSA, // FMIN_D = 1640 24776 CEFBS_HasStdEnc_HasMSA, // FMIN_W = 1641 24777 CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FMOV_D32 = 1642 24778 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FMOV_D32_MM = 1643 24779 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FMOV_D64 = 1644 24780 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FMOV_D64_MM = 1645 24781 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FMOV_D_MMR6 = 1646 24782 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FMOV_S = 1647 24783 CEFBS_InMicroMips_IsNotSoftFloat, // FMOV_S_MM = 1648 24784 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FMOV_S_MMR6 = 1649 24785 CEFBS_HasStdEnc_HasMSA, // FMSUB_D = 1650 24786 CEFBS_HasStdEnc_HasMSA, // FMSUB_W = 1651 24787 CEFBS_HasStdEnc_HasMSA, // FMUL_D = 1652 24788 CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FMUL_D32 = 1653 24789 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FMUL_D32_MM = 1654 24790 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FMUL_D64 = 1655 24791 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FMUL_D64_MM = 1656 24792 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // FMUL_PS64 = 1657 24793 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FMUL_S = 1658 24794 CEFBS_InMicroMips_IsNotSoftFloat, // FMUL_S_MM = 1659 24795 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FMUL_S_MMR6 = 1660 24796 CEFBS_HasStdEnc_HasMSA, // FMUL_W = 1661 24797 CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FNEG_D32 = 1662 24798 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FNEG_D32_MM = 1663 24799 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FNEG_D64 = 1664 24800 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FNEG_D64_MM = 1665 24801 CEFBS_HasStdEnc_IsNotSoftFloat, // FNEG_S = 1666 24802 CEFBS_InMicroMips_IsNotSoftFloat, // FNEG_S_MM = 1667 24803 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FNEG_S_MMR6 = 1668 24804 CEFBS_HasStdEnc_HasMT_NotInMicroMips, // FORK = 1669 24805 CEFBS_HasStdEnc_HasMSA, // FRCP_D = 1670 24806 CEFBS_HasStdEnc_HasMSA, // FRCP_W = 1671 24807 CEFBS_HasStdEnc_HasMSA, // FRINT_D = 1672 24808 CEFBS_HasStdEnc_HasMSA, // FRINT_W = 1673 24809 CEFBS_HasStdEnc_HasMSA, // FRSQRT_D = 1674 24810 CEFBS_HasStdEnc_HasMSA, // FRSQRT_W = 1675 24811 CEFBS_HasStdEnc_HasMSA, // FSAF_D = 1676 24812 CEFBS_HasStdEnc_HasMSA, // FSAF_W = 1677 24813 CEFBS_HasStdEnc_HasMSA, // FSEQ_D = 1678 24814 CEFBS_HasStdEnc_HasMSA, // FSEQ_W = 1679 24815 CEFBS_HasStdEnc_HasMSA, // FSLE_D = 1680 24816 CEFBS_HasStdEnc_HasMSA, // FSLE_W = 1681 24817 CEFBS_HasStdEnc_HasMSA, // FSLT_D = 1682 24818 CEFBS_HasStdEnc_HasMSA, // FSLT_W = 1683 24819 CEFBS_HasStdEnc_HasMSA, // FSNE_D = 1684 24820 CEFBS_HasStdEnc_HasMSA, // FSNE_W = 1685 24821 CEFBS_HasStdEnc_HasMSA, // FSOR_D = 1686 24822 CEFBS_HasStdEnc_HasMSA, // FSOR_W = 1687 24823 CEFBS_HasStdEnc_HasMSA, // FSQRT_D = 1688 24824 CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // FSQRT_D32 = 1689 24825 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FSQRT_D32_MM = 1690 24826 CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // FSQRT_D64 = 1691 24827 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FSQRT_D64_MM = 1692 24828 CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, // FSQRT_S = 1693 24829 CEFBS_InMicroMips_IsNotSoftFloat, // FSQRT_S_MM = 1694 24830 CEFBS_HasStdEnc_HasMSA, // FSQRT_W = 1695 24831 CEFBS_HasStdEnc_HasMSA, // FSUB_D = 1696 24832 CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FSUB_D32 = 1697 24833 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FSUB_D32_MM = 1698 24834 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FSUB_D64 = 1699 24835 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FSUB_D64_MM = 1700 24836 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // FSUB_PS64 = 1701 24837 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FSUB_S = 1702 24838 CEFBS_InMicroMips_IsNotSoftFloat, // FSUB_S_MM = 1703 24839 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FSUB_S_MMR6 = 1704 24840 CEFBS_HasStdEnc_HasMSA, // FSUB_W = 1705 24841 CEFBS_HasStdEnc_HasMSA, // FSUEQ_D = 1706 24842 CEFBS_HasStdEnc_HasMSA, // FSUEQ_W = 1707 24843 CEFBS_HasStdEnc_HasMSA, // FSULE_D = 1708 24844 CEFBS_HasStdEnc_HasMSA, // FSULE_W = 1709 24845 CEFBS_HasStdEnc_HasMSA, // FSULT_D = 1710 24846 CEFBS_HasStdEnc_HasMSA, // FSULT_W = 1711 24847 CEFBS_HasStdEnc_HasMSA, // FSUNE_D = 1712 24848 CEFBS_HasStdEnc_HasMSA, // FSUNE_W = 1713 24849 CEFBS_HasStdEnc_HasMSA, // FSUN_D = 1714 24850 CEFBS_HasStdEnc_HasMSA, // FSUN_W = 1715 24851 CEFBS_HasStdEnc_HasMSA, // FTINT_S_D = 1716 24852 CEFBS_HasStdEnc_HasMSA, // FTINT_S_W = 1717 24853 CEFBS_HasStdEnc_HasMSA, // FTINT_U_D = 1718 24854 CEFBS_HasStdEnc_HasMSA, // FTINT_U_W = 1719 24855 CEFBS_HasStdEnc_HasMSA, // FTQ_H = 1720 24856 CEFBS_HasStdEnc_HasMSA, // FTQ_W = 1721 24857 CEFBS_HasStdEnc_HasMSA, // FTRUNC_S_D = 1722 24858 CEFBS_HasStdEnc_HasMSA, // FTRUNC_S_W = 1723 24859 CEFBS_HasStdEnc_HasMSA, // FTRUNC_U_D = 1724 24860 CEFBS_HasStdEnc_HasMSA, // FTRUNC_U_W = 1725 24861 CEFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips, // GINVI = 1726 24862 CEFBS_InMicroMips_HasMips32r6_HasGINV, // GINVI_MMR6 = 1727 24863 CEFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips, // GINVT = 1728 24864 CEFBS_InMicroMips_HasMips32r6_HasGINV, // GINVT_MMR6 = 1729 24865 CEFBS_HasStdEnc_HasMSA, // HADD_S_D = 1730 24866 CEFBS_HasStdEnc_HasMSA, // HADD_S_H = 1731 24867 CEFBS_HasStdEnc_HasMSA, // HADD_S_W = 1732 24868 CEFBS_HasStdEnc_HasMSA, // HADD_U_D = 1733 24869 CEFBS_HasStdEnc_HasMSA, // HADD_U_H = 1734 24870 CEFBS_HasStdEnc_HasMSA, // HADD_U_W = 1735 24871 CEFBS_HasStdEnc_HasMSA, // HSUB_S_D = 1736 24872 CEFBS_HasStdEnc_HasMSA, // HSUB_S_H = 1737 24873 CEFBS_HasStdEnc_HasMSA, // HSUB_S_W = 1738 24874 CEFBS_HasStdEnc_HasMSA, // HSUB_U_D = 1739 24875 CEFBS_HasStdEnc_HasMSA, // HSUB_U_H = 1740 24876 CEFBS_HasStdEnc_HasMSA, // HSUB_U_W = 1741 24877 CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // HYPCALL = 1742 24878 CEFBS_InMicroMips_HasMips32r5_HasVirt, // HYPCALL_MM = 1743 24879 CEFBS_HasStdEnc_HasMSA, // ILVEV_B = 1744 24880 CEFBS_HasStdEnc_HasMSA, // ILVEV_D = 1745 24881 CEFBS_HasStdEnc_HasMSA, // ILVEV_H = 1746 24882 CEFBS_HasStdEnc_HasMSA, // ILVEV_W = 1747 24883 CEFBS_HasStdEnc_HasMSA, // ILVL_B = 1748 24884 CEFBS_HasStdEnc_HasMSA, // ILVL_D = 1749 24885 CEFBS_HasStdEnc_HasMSA, // ILVL_H = 1750 24886 CEFBS_HasStdEnc_HasMSA, // ILVL_W = 1751 24887 CEFBS_HasStdEnc_HasMSA, // ILVOD_B = 1752 24888 CEFBS_HasStdEnc_HasMSA, // ILVOD_D = 1753 24889 CEFBS_HasStdEnc_HasMSA, // ILVOD_H = 1754 24890 CEFBS_HasStdEnc_HasMSA, // ILVOD_W = 1755 24891 CEFBS_HasStdEnc_HasMSA, // ILVR_B = 1756 24892 CEFBS_HasStdEnc_HasMSA, // ILVR_D = 1757 24893 CEFBS_HasStdEnc_HasMSA, // ILVR_H = 1758 24894 CEFBS_HasStdEnc_HasMSA, // ILVR_W = 1759 24895 CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // INS = 1760 24896 CEFBS_HasStdEnc_HasMSA, // INSERT_B = 1761 24897 CEFBS_HasStdEnc_HasMSA_HasMips64, // INSERT_D = 1762 24898 CEFBS_HasStdEnc_HasMSA, // INSERT_H = 1763 24899 CEFBS_HasStdEnc_HasMSA, // INSERT_W = 1764 24900 CEFBS_HasDSP, // INSV = 1765 24901 CEFBS_HasStdEnc_HasMSA, // INSVE_B = 1766 24902 CEFBS_HasStdEnc_HasMSA, // INSVE_D = 1767 24903 CEFBS_HasStdEnc_HasMSA, // INSVE_H = 1768 24904 CEFBS_HasStdEnc_HasMSA, // INSVE_W = 1769 24905 CEFBS_InMicroMips_HasDSP, // INSV_MM = 1770 24906 CEFBS_InMicroMips_NotMips32r6, // INS_MM = 1771 24907 CEFBS_InMicroMips_HasMips32r6, // INS_MMR6 = 1772 24908 CEFBS_HasStdEnc_NotInMicroMips, // J = 1773 24909 CEFBS_HasStdEnc_NotInMicroMips, // JAL = 1774 24910 CEFBS_HasStdEnc_NotInMicroMips_NoIndirectJumpGuards, // JALR = 1775 24911 CEFBS_InMicroMips_NotMips32r6, // JALR16_MM = 1776 24912 CEFBS_NotInMips16Mode_IsPTR64bit, // JALR64 = 1777 24913 CEFBS_InMicroMips_HasMips32r6, // JALRC16_MMR6 = 1778 24914 CEFBS_InMicroMips_HasMips32r6, // JALRC_HB_MMR6 = 1779 24915 CEFBS_InMicroMips_HasMips32r6, // JALRC_MMR6 = 1780 24916 CEFBS_InMicroMips_NotMips32r6, // JALRS16_MM = 1781 24917 CEFBS_InMicroMips_NotMips32r6, // JALRS_MM = 1782 24918 CEFBS_HasStdEnc_HasMips32, // JALR_HB = 1783 24919 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // JALR_HB64 = 1784 24920 CEFBS_InMicroMips_NotMips32r6, // JALR_MM = 1785 24921 CEFBS_InMicroMips_NotMips32r6, // JALS_MM = 1786 24922 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // JALX = 1787 24923 CEFBS_InMicroMips_NotMips32r6, // JALX_MM = 1788 24924 CEFBS_InMicroMips_NotMips32r6, // JAL_MM = 1789 24925 CEFBS_HasStdEnc_HasMips32r6, // JIALC = 1790 24926 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // JIALC64 = 1791 24927 CEFBS_InMicroMips_HasMips32r6, // JIALC_MMR6 = 1792 24928 CEFBS_HasStdEnc_HasMips32r6, // JIC = 1793 24929 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // JIC64 = 1794 24930 CEFBS_InMicroMips_HasMips32r6, // JIC_MMR6 = 1795 24931 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // JR = 1796 24932 CEFBS_InMicroMips_NotMips32r6, // JR16_MM = 1797 24933 CEFBS_NotInMips16Mode_IsPTR64bit_NotInMicroMips, // JR64 = 1798 24934 CEFBS_InMicroMips_NotMips32r6, // JRADDIUSP = 1799 24935 CEFBS_InMicroMips_NotMips32r6, // JRC16_MM = 1800 24936 CEFBS_InMicroMips_HasMips32r6, // JRC16_MMR6 = 1801 24937 CEFBS_InMicroMips_HasMips32r6, // JRCADDIUSP_MMR6 = 1802 24938 CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6, // JR_HB = 1803 24939 CEFBS_HasStdEnc_HasMips64_NotMips64r6_NotInMicroMips, // JR_HB64 = 1804 24940 CEFBS_HasStdEnc_HasMips32r6, // JR_HB64_R6 = 1805 24941 CEFBS_HasStdEnc_HasMips32r6, // JR_HB_R6 = 1806 24942 CEFBS_InMicroMips_NotMips32r6, // JR_MM = 1807 24943 CEFBS_InMicroMips_NotMips32r6, // J_MM = 1808 24944 CEFBS_InMips16Mode, // Jal16 = 1809 24945 CEFBS_InMips16Mode, // JalB16 = 1810 24946 CEFBS_InMips16Mode, // JrRa16 = 1811 24947 CEFBS_InMips16Mode, // JrcRa16 = 1812 24948 CEFBS_InMips16Mode, // JrcRx16 = 1813 24949 CEFBS_InMips16Mode, // JumpLinkReg16 = 1814 24950 CEFBS_HasStdEnc_NotInMicroMips, // LB = 1815 24951 CEFBS_NotInMips16Mode_IsGP64bit, // LB64 = 1816 24952 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LBE = 1817 24953 CEFBS_InMicroMips_HasEVA, // LBE_MM = 1818 24954 CEFBS_InMicroMips, // LBU16_MM = 1819 24955 CEFBS_HasDSP, // LBUX = 1820 24956 CEFBS_InMicroMips_HasDSP, // LBUX_MM = 1821 24957 CEFBS_InMicroMips_HasMips32r6, // LBU_MMR6 = 1822 24958 CEFBS_InMicroMips, // LB_MM = 1823 24959 CEFBS_InMicroMips_HasMips32r6, // LB_MMR6 = 1824 24960 CEFBS_HasStdEnc_NotInMicroMips, // LBu = 1825 24961 CEFBS_NotInMips16Mode_IsGP64bit, // LBu64 = 1826 24962 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LBuE = 1827 24963 CEFBS_InMicroMips_HasEVA, // LBuE_MM = 1828 24964 CEFBS_InMicroMips, // LBu_MM = 1829 24965 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // LD = 1830 24966 CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // LDC1 = 1831 24967 CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // LDC164 = 1832 24968 CEFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, // LDC1_D64_MMR6 = 1833 24969 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // LDC1_MM_D32 = 1834 24970 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // LDC1_MM_D64 = 1835 24971 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // LDC2 = 1836 24972 CEFBS_InMicroMips_HasMips32r6, // LDC2_MMR6 = 1837 24973 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // LDC2_R6 = 1838 24974 CEFBS_HasStdEnc_HasMips2_NotCnMips_NotInMicroMips, // LDC3 = 1839 24975 CEFBS_HasStdEnc_HasMSA, // LDI_B = 1840 24976 CEFBS_HasStdEnc_HasMSA, // LDI_D = 1841 24977 CEFBS_HasStdEnc_HasMSA, // LDI_H = 1842 24978 CEFBS_HasStdEnc_HasMSA, // LDI_W = 1843 24979 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // LDL = 1844 24980 CEFBS_HasStdEnc_HasMips64r6, // LDPC = 1845 24981 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // LDR = 1846 24982 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // LDXC1 = 1847 24983 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, // LDXC164 = 1848 24984 CEFBS_HasStdEnc_HasMSA, // LD_B = 1849 24985 CEFBS_HasStdEnc_HasMSA, // LD_D = 1850 24986 CEFBS_HasStdEnc_HasMSA, // LD_H = 1851 24987 CEFBS_HasStdEnc_HasMSA, // LD_W = 1852 24988 CEFBS_HasStdEnc_NotInMicroMips, // LEA_ADDiu = 1853 24989 CEFBS_NotInMips16Mode_IsGP64bit_NotInMicroMips, // LEA_ADDiu64 = 1854 24990 CEFBS_InMicroMips, // LEA_ADDiu_MM = 1855 24991 CEFBS_HasStdEnc_NotInMicroMips, // LH = 1856 24992 CEFBS_NotInMips16Mode_IsGP64bit, // LH64 = 1857 24993 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LHE = 1858 24994 CEFBS_InMicroMips_HasEVA, // LHE_MM = 1859 24995 CEFBS_InMicroMips, // LHU16_MM = 1860 24996 CEFBS_HasDSP, // LHX = 1861 24997 CEFBS_InMicroMips_HasDSP, // LHX_MM = 1862 24998 CEFBS_InMicroMips, // LH_MM = 1863 24999 CEFBS_HasStdEnc_NotInMicroMips, // LHu = 1864 25000 CEFBS_NotInMips16Mode_IsGP64bit, // LHu64 = 1865 25001 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LHuE = 1866 25002 CEFBS_InMicroMips_HasEVA, // LHuE_MM = 1867 25003 CEFBS_InMicroMips, // LHu_MM = 1868 25004 CEFBS_InMicroMips_NotMips32r6, // LI16_MM = 1869 25005 CEFBS_InMicroMips_HasMips32r6, // LI16_MMR6 = 1870 25006 CEFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // LL = 1871 25007 CEFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // LL64 = 1872 25008 CEFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips, // LL64_R6 = 1873 25009 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // LLD = 1874 25010 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // LLD_R6 = 1875 25011 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LLE = 1876 25012 CEFBS_InMicroMips_HasEVA, // LLE_MM = 1877 25013 CEFBS_InMicroMips_NotMips32r6, // LL_MM = 1878 25014 CEFBS_InMicroMips_HasMips32r6, // LL_MMR6 = 1879 25015 CEFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips, // LL_R6 = 1880 25016 CEFBS_HasStdEnc_HasMSA, // LSA = 1881 25017 CEFBS_InMicroMips_HasMips32r6, // LSA_MMR6 = 1882 25018 CEFBS_HasStdEnc_HasMips32r6, // LSA_R6 = 1883 25019 CEFBS_InMicroMips_HasMips32r6, // LUI_MMR6 = 1884 25020 CEFBS_HasStdEnc_NotFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // LUXC1 = 1885 25021 CEFBS_HasStdEnc_IsFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // LUXC164 = 1886 25022 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // LUXC1_MM = 1887 25023 CEFBS_HasStdEnc_NotInMicroMips, // LUi = 1888 25024 CEFBS_NotInMips16Mode_IsGP64bit, // LUi64 = 1889 25025 CEFBS_InMicroMips_NotMips32r6, // LUi_MM = 1890 25026 CEFBS_HasStdEnc_NotInMicroMips, // LW = 1891 25027 CEFBS_InMicroMips, // LW16_MM = 1892 25028 CEFBS_NotInMips16Mode_IsGP64bit, // LW64 = 1893 25029 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // LWC1 = 1894 25030 CEFBS_InMicroMips_IsNotSoftFloat, // LWC1_MM = 1895 25031 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // LWC2 = 1896 25032 CEFBS_InMicroMips_HasMips32r6, // LWC2_MMR6 = 1897 25033 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // LWC2_R6 = 1898 25034 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotCnMips_NotInMicroMips, // LWC3 = 1899 25035 CEFBS_NotInMips16Mode_HasDSP, // LWDSP = 1900 25036 CEFBS_InMicroMips_HasDSP, // LWDSP_MM = 1901 25037 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LWE = 1902 25038 CEFBS_InMicroMips_HasEVA, // LWE_MM = 1903 25039 CEFBS_InMicroMips, // LWGP_MM = 1904 25040 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // LWL = 1905 25041 CEFBS_NotInMips16Mode_IsGP64bit, // LWL64 = 1906 25042 CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, // LWLE = 1907 25043 CEFBS_InMicroMips_NotMips32r6_HasEVA, // LWLE_MM = 1908 25044 CEFBS_InMicroMips_NotMips32r6, // LWL_MM = 1909 25045 CEFBS_InMicroMips_NotMips32r6, // LWM16_MM = 1910 25046 CEFBS_InMicroMips_HasMips32r6, // LWM16_MMR6 = 1911 25047 CEFBS_InMicroMips, // LWM32_MM = 1912 25048 CEFBS_HasStdEnc_HasMips32r6, // LWPC = 1913 25049 CEFBS_InMicroMips_HasMips32r6, // LWPC_MMR6 = 1914 25050 CEFBS_InMicroMips, // LWP_MM = 1915 25051 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // LWR = 1916 25052 CEFBS_NotInMips16Mode_IsGP64bit, // LWR64 = 1917 25053 CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, // LWRE = 1918 25054 CEFBS_InMicroMips_NotMips32r6_HasEVA, // LWRE_MM = 1919 25055 CEFBS_InMicroMips_NotMips32r6, // LWR_MM = 1920 25056 CEFBS_InMicroMips, // LWSP_MM = 1921 25057 CEFBS_HasStdEnc_HasMips64r6, // LWUPC = 1922 25058 CEFBS_InMicroMips_NotMips32r6, // LWU_MM = 1923 25059 CEFBS_HasDSP, // LWX = 1924 25060 CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, // LWXC1 = 1925 25061 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // LWXC1_MM = 1926 25062 CEFBS_InMicroMips, // LWXS_MM = 1927 25063 CEFBS_InMicroMips_HasDSP, // LWX_MM = 1928 25064 CEFBS_InMicroMips, // LW_MM = 1929 25065 CEFBS_InMicroMips_HasMips32r6, // LW_MMR6 = 1930 25066 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // LWu = 1931 25067 CEFBS_InMips16Mode, // LbRxRyOffMemX16 = 1932 25068 CEFBS_InMips16Mode, // LbuRxRyOffMemX16 = 1933 25069 CEFBS_InMips16Mode, // LhRxRyOffMemX16 = 1934 25070 CEFBS_InMips16Mode, // LhuRxRyOffMemX16 = 1935 25071 CEFBS_InMips16Mode, // LiRxImm16 = 1936 25072 CEFBS_InMips16Mode, // LiRxImmAlignX16 = 1937 25073 CEFBS_InMips16Mode, // LiRxImmX16 = 1938 25074 CEFBS_InMips16Mode, // LwRxPcTcp16 = 1939 25075 CEFBS_InMips16Mode, // LwRxPcTcpX16 = 1940 25076 CEFBS_InMips16Mode, // LwRxRyOffMemX16 = 1941 25077 CEFBS_InMips16Mode, // LwRxSpImmX16 = 1942 25078 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MADD = 1943 25079 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MADDF_D = 1944 25080 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MADDF_D_MMR6 = 1945 25081 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MADDF_S = 1946 25082 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MADDF_S_MMR6 = 1947 25083 CEFBS_HasStdEnc_HasMSA, // MADDR_Q_H = 1948 25084 CEFBS_HasStdEnc_HasMSA, // MADDR_Q_W = 1949 25085 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MADDU = 1950 25086 CEFBS_HasDSP, // MADDU_DSP = 1951 25087 CEFBS_InMicroMips_HasDSP, // MADDU_DSP_MM = 1952 25088 CEFBS_InMicroMips_NotMips32r6, // MADDU_MM = 1953 25089 CEFBS_HasStdEnc_HasMSA, // MADDV_B = 1954 25090 CEFBS_HasStdEnc_HasMSA, // MADDV_D = 1955 25091 CEFBS_HasStdEnc_HasMSA, // MADDV_H = 1956 25092 CEFBS_HasStdEnc_HasMSA, // MADDV_W = 1957 25093 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MADD_D32 = 1958 25094 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, // MADD_D32_MM = 1959 25095 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MADD_D64 = 1960 25096 CEFBS_HasDSP, // MADD_DSP = 1961 25097 CEFBS_InMicroMips_HasDSP, // MADD_DSP_MM = 1962 25098 CEFBS_InMicroMips_NotMips32r6, // MADD_MM = 1963 25099 CEFBS_HasStdEnc_HasMSA, // MADD_Q_H = 1964 25100 CEFBS_HasStdEnc_HasMSA, // MADD_Q_W = 1965 25101 CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MADD_S = 1966 25102 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, // MADD_S_MM = 1967 25103 CEFBS_HasDSP, // MAQ_SA_W_PHL = 1968 25104 CEFBS_InMicroMips_HasDSP, // MAQ_SA_W_PHL_MM = 1969 25105 CEFBS_HasDSP, // MAQ_SA_W_PHR = 1970 25106 CEFBS_InMicroMips_HasDSP, // MAQ_SA_W_PHR_MM = 1971 25107 CEFBS_HasDSP, // MAQ_S_W_PHL = 1972 25108 CEFBS_InMicroMips_HasDSP, // MAQ_S_W_PHL_MM = 1973 25109 CEFBS_HasDSP, // MAQ_S_W_PHR = 1974 25110 CEFBS_InMicroMips_HasDSP, // MAQ_S_W_PHR_MM = 1975 25111 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MAXA_D = 1976 25112 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MAXA_D_MMR6 = 1977 25113 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MAXA_S = 1978 25114 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MAXA_S_MMR6 = 1979 25115 CEFBS_HasStdEnc_HasMSA, // MAXI_S_B = 1980 25116 CEFBS_HasStdEnc_HasMSA, // MAXI_S_D = 1981 25117 CEFBS_HasStdEnc_HasMSA, // MAXI_S_H = 1982 25118 CEFBS_HasStdEnc_HasMSA, // MAXI_S_W = 1983 25119 CEFBS_HasStdEnc_HasMSA, // MAXI_U_B = 1984 25120 CEFBS_HasStdEnc_HasMSA, // MAXI_U_D = 1985 25121 CEFBS_HasStdEnc_HasMSA, // MAXI_U_H = 1986 25122 CEFBS_HasStdEnc_HasMSA, // MAXI_U_W = 1987 25123 CEFBS_HasStdEnc_HasMSA, // MAX_A_B = 1988 25124 CEFBS_HasStdEnc_HasMSA, // MAX_A_D = 1989 25125 CEFBS_HasStdEnc_HasMSA, // MAX_A_H = 1990 25126 CEFBS_HasStdEnc_HasMSA, // MAX_A_W = 1991 25127 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MAX_D = 1992 25128 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MAX_D_MMR6 = 1993 25129 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MAX_S = 1994 25130 CEFBS_HasStdEnc_HasMSA, // MAX_S_B = 1995 25131 CEFBS_HasStdEnc_HasMSA, // MAX_S_D = 1996 25132 CEFBS_HasStdEnc_HasMSA, // MAX_S_H = 1997 25133 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MAX_S_MMR6 = 1998 25134 CEFBS_HasStdEnc_HasMSA, // MAX_S_W = 1999 25135 CEFBS_HasStdEnc_HasMSA, // MAX_U_B = 2000 25136 CEFBS_HasStdEnc_HasMSA, // MAX_U_D = 2001 25137 CEFBS_HasStdEnc_HasMSA, // MAX_U_H = 2002 25138 CEFBS_HasStdEnc_HasMSA, // MAX_U_W = 2003 25139 CEFBS_HasStdEnc_NotInMicroMips, // MFC0 = 2004 25140 CEFBS_InMicroMips_HasMips32r6, // MFC0_MMR6 = 2005 25141 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // MFC1 = 2006 25142 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // MFC1_D64 = 2007 25143 CEFBS_InMicroMips_IsNotSoftFloat, // MFC1_MM = 2008 25144 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MFC1_MMR6 = 2009 25145 CEFBS_HasStdEnc_NotInMicroMips, // MFC2 = 2010 25146 CEFBS_InMicroMips_HasMips32r6, // MFC2_MMR6 = 2011 25147 CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // MFGC0 = 2012 25148 CEFBS_InMicroMips_HasMips32r5_HasVirt, // MFGC0_MM = 2013 25149 CEFBS_InMicroMips_HasMips32r6, // MFHC0_MMR6 = 2014 25150 CEFBS_HasStdEnc_NotFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, // MFHC1_D32 = 2015 25151 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // MFHC1_D32_MM = 2016 25152 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, // MFHC1_D64 = 2017 25153 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // MFHC1_D64_MM = 2018 25154 CEFBS_InMicroMips_HasMips32r6, // MFHC2_MMR6 = 2019 25155 CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // MFHGC0 = 2020 25156 CEFBS_InMicroMips_HasMips32r5_HasVirt, // MFHGC0_MM = 2021 25157 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MFHI = 2022 25158 CEFBS_InMicroMips_NotMips32r6, // MFHI16_MM = 2023 25159 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // MFHI64 = 2024 25160 CEFBS_HasDSP, // MFHI_DSP = 2025 25161 CEFBS_InMicroMips_HasDSP, // MFHI_DSP_MM = 2026 25162 CEFBS_InMicroMips_NotMips32r6, // MFHI_MM = 2027 25163 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MFLO = 2028 25164 CEFBS_InMicroMips_NotMips32r6, // MFLO16_MM = 2029 25165 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // MFLO64 = 2030 25166 CEFBS_HasDSP, // MFLO_DSP = 2031 25167 CEFBS_InMicroMips_HasDSP, // MFLO_DSP_MM = 2032 25168 CEFBS_InMicroMips_NotMips32r6, // MFLO_MM = 2033 25169 CEFBS_HasStdEnc_HasMT_NotInMicroMips, // MFTR = 2034 25170 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MINA_D = 2035 25171 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MINA_D_MMR6 = 2036 25172 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MINA_S = 2037 25173 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MINA_S_MMR6 = 2038 25174 CEFBS_HasStdEnc_HasMSA, // MINI_S_B = 2039 25175 CEFBS_HasStdEnc_HasMSA, // MINI_S_D = 2040 25176 CEFBS_HasStdEnc_HasMSA, // MINI_S_H = 2041 25177 CEFBS_HasStdEnc_HasMSA, // MINI_S_W = 2042 25178 CEFBS_HasStdEnc_HasMSA, // MINI_U_B = 2043 25179 CEFBS_HasStdEnc_HasMSA, // MINI_U_D = 2044 25180 CEFBS_HasStdEnc_HasMSA, // MINI_U_H = 2045 25181 CEFBS_HasStdEnc_HasMSA, // MINI_U_W = 2046 25182 CEFBS_HasStdEnc_HasMSA, // MIN_A_B = 2047 25183 CEFBS_HasStdEnc_HasMSA, // MIN_A_D = 2048 25184 CEFBS_HasStdEnc_HasMSA, // MIN_A_H = 2049 25185 CEFBS_HasStdEnc_HasMSA, // MIN_A_W = 2050 25186 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MIN_D = 2051 25187 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MIN_D_MMR6 = 2052 25188 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MIN_S = 2053 25189 CEFBS_HasStdEnc_HasMSA, // MIN_S_B = 2054 25190 CEFBS_HasStdEnc_HasMSA, // MIN_S_D = 2055 25191 CEFBS_HasStdEnc_HasMSA, // MIN_S_H = 2056 25192 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MIN_S_MMR6 = 2057 25193 CEFBS_HasStdEnc_HasMSA, // MIN_S_W = 2058 25194 CEFBS_HasStdEnc_HasMSA, // MIN_U_B = 2059 25195 CEFBS_HasStdEnc_HasMSA, // MIN_U_D = 2060 25196 CEFBS_HasStdEnc_HasMSA, // MIN_U_H = 2061 25197 CEFBS_HasStdEnc_HasMSA, // MIN_U_W = 2062 25198 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MOD = 2063 25199 CEFBS_HasDSP, // MODSUB = 2064 25200 CEFBS_InMicroMips_HasDSP, // MODSUB_MM = 2065 25201 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MODU = 2066 25202 CEFBS_InMicroMips_HasMips32r6, // MODU_MMR6 = 2067 25203 CEFBS_InMicroMips_HasMips32r6, // MOD_MMR6 = 2068 25204 CEFBS_HasStdEnc_HasMSA, // MOD_S_B = 2069 25205 CEFBS_HasStdEnc_HasMSA, // MOD_S_D = 2070 25206 CEFBS_HasStdEnc_HasMSA, // MOD_S_H = 2071 25207 CEFBS_HasStdEnc_HasMSA, // MOD_S_W = 2072 25208 CEFBS_HasStdEnc_HasMSA, // MOD_U_B = 2073 25209 CEFBS_HasStdEnc_HasMSA, // MOD_U_D = 2074 25210 CEFBS_HasStdEnc_HasMSA, // MOD_U_H = 2075 25211 CEFBS_HasStdEnc_HasMSA, // MOD_U_W = 2076 25212 CEFBS_InMicroMips_NotMips32r6, // MOVE16_MM = 2077 25213 CEFBS_InMicroMips_HasMips32r6, // MOVE16_MMR6 = 2078 25214 CEFBS_InMicroMips_NotMips32r6, // MOVEP_MM = 2079 25215 CEFBS_InMicroMips_HasMips32r6, // MOVEP_MMR6 = 2080 25216 CEFBS_HasStdEnc_HasMSA, // MOVE_V = 2081 25217 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_D32 = 2082 25218 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // MOVF_D32_MM = 2083 25219 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_D64 = 2084 25220 CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_I = 2085 25221 CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_I64 = 2086 25222 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVF_I_MM = 2087 25223 CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_S = 2088 25224 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVF_S_MM = 2089 25225 CEFBS_HasStdEnc_IsGP64bit_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I64_D64 = 2090 25226 CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVN_I64_I = 2091 25227 CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVN_I64_I64 = 2092 25228 CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I64_S = 2093 25229 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I_D32 = 2094 25230 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // MOVN_I_D32_MM = 2095 25231 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I_D64 = 2096 25232 CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVN_I_I = 2097 25233 CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVN_I_I64 = 2098 25234 CEFBS_InMicroMips_NotMips32r6, // MOVN_I_MM = 2099 25235 CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I_S = 2100 25236 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVN_I_S_MM = 2101 25237 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_D32 = 2102 25238 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // MOVT_D32_MM = 2103 25239 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_D64 = 2104 25240 CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_I = 2105 25241 CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_I64 = 2106 25242 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVT_I_MM = 2107 25243 CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_S = 2108 25244 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVT_S_MM = 2109 25245 CEFBS_HasStdEnc_IsGP64bit_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I64_D64 = 2110 25246 CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVZ_I64_I = 2111 25247 CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVZ_I64_I64 = 2112 25248 CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I64_S = 2113 25249 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I_D32 = 2114 25250 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // MOVZ_I_D32_MM = 2115 25251 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I_D64 = 2116 25252 CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVZ_I_I = 2117 25253 CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVZ_I_I64 = 2118 25254 CEFBS_InMicroMips_NotMips32r6, // MOVZ_I_MM = 2119 25255 CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I_S = 2120 25256 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVZ_I_S_MM = 2121 25257 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MSUB = 2122 25258 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MSUBF_D = 2123 25259 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MSUBF_D_MMR6 = 2124 25260 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MSUBF_S = 2125 25261 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MSUBF_S_MMR6 = 2126 25262 CEFBS_HasStdEnc_HasMSA, // MSUBR_Q_H = 2127 25263 CEFBS_HasStdEnc_HasMSA, // MSUBR_Q_W = 2128 25264 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MSUBU = 2129 25265 CEFBS_HasDSP, // MSUBU_DSP = 2130 25266 CEFBS_InMicroMips_HasDSP, // MSUBU_DSP_MM = 2131 25267 CEFBS_InMicroMips_NotMips32r6, // MSUBU_MM = 2132 25268 CEFBS_HasStdEnc_HasMSA, // MSUBV_B = 2133 25269 CEFBS_HasStdEnc_HasMSA, // MSUBV_D = 2134 25270 CEFBS_HasStdEnc_HasMSA, // MSUBV_H = 2135 25271 CEFBS_HasStdEnc_HasMSA, // MSUBV_W = 2136 25272 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MSUB_D32 = 2137 25273 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, // MSUB_D32_MM = 2138 25274 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MSUB_D64 = 2139 25275 CEFBS_HasDSP, // MSUB_DSP = 2140 25276 CEFBS_InMicroMips_HasDSP, // MSUB_DSP_MM = 2141 25277 CEFBS_InMicroMips_NotMips32r6, // MSUB_MM = 2142 25278 CEFBS_HasStdEnc_HasMSA, // MSUB_Q_H = 2143 25279 CEFBS_HasStdEnc_HasMSA, // MSUB_Q_W = 2144 25280 CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MSUB_S = 2145 25281 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, // MSUB_S_MM = 2146 25282 CEFBS_HasStdEnc_NotInMicroMips, // MTC0 = 2147 25283 CEFBS_InMicroMips_HasMips32r6, // MTC0_MMR6 = 2148 25284 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // MTC1 = 2149 25285 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // MTC1_D64 = 2150 25286 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // MTC1_D64_MM = 2151 25287 CEFBS_InMicroMips_IsNotSoftFloat, // MTC1_MM = 2152 25288 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MTC1_MMR6 = 2153 25289 CEFBS_HasStdEnc_NotInMicroMips, // MTC2 = 2154 25290 CEFBS_InMicroMips_HasMips32r6, // MTC2_MMR6 = 2155 25291 CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // MTGC0 = 2156 25292 CEFBS_InMicroMips_HasMips32r5_HasVirt, // MTGC0_MM = 2157 25293 CEFBS_InMicroMips_HasMips32r6, // MTHC0_MMR6 = 2158 25294 CEFBS_HasStdEnc_NotFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, // MTHC1_D32 = 2159 25295 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // MTHC1_D32_MM = 2160 25296 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, // MTHC1_D64 = 2161 25297 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // MTHC1_D64_MM = 2162 25298 CEFBS_InMicroMips_HasMips32r6, // MTHC2_MMR6 = 2163 25299 CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // MTHGC0 = 2164 25300 CEFBS_InMicroMips_HasMips32r5_HasVirt, // MTHGC0_MM = 2165 25301 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MTHI = 2166 25302 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // MTHI64 = 2167 25303 CEFBS_HasDSP, // MTHI_DSP = 2168 25304 CEFBS_InMicroMips_HasDSP, // MTHI_DSP_MM = 2169 25305 CEFBS_InMicroMips_NotMips32r6, // MTHI_MM = 2170 25306 CEFBS_HasDSP, // MTHLIP = 2171 25307 CEFBS_InMicroMips_HasDSP, // MTHLIP_MM = 2172 25308 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MTLO = 2173 25309 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // MTLO64 = 2174 25310 CEFBS_HasDSP, // MTLO_DSP = 2175 25311 CEFBS_InMicroMips_HasDSP, // MTLO_DSP_MM = 2176 25312 CEFBS_InMicroMips_NotMips32r6, // MTLO_MM = 2177 25313 CEFBS_HasCnMips, // MTM0 = 2178 25314 CEFBS_HasCnMips, // MTM1 = 2179 25315 CEFBS_HasCnMips, // MTM2 = 2180 25316 CEFBS_HasCnMips, // MTP0 = 2181 25317 CEFBS_HasCnMips, // MTP1 = 2182 25318 CEFBS_HasCnMips, // MTP2 = 2183 25319 CEFBS_HasStdEnc_HasMT_NotInMicroMips, // MTTR = 2184 25320 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MUH = 2185 25321 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MUHU = 2186 25322 CEFBS_InMicroMips_HasMips32r6, // MUHU_MMR6 = 2187 25323 CEFBS_InMicroMips_HasMips32r6, // MUH_MMR6 = 2188 25324 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MUL = 2189 25325 CEFBS_HasDSP, // MULEQ_S_W_PHL = 2190 25326 CEFBS_InMicroMips_HasDSP, // MULEQ_S_W_PHL_MM = 2191 25327 CEFBS_HasDSP, // MULEQ_S_W_PHR = 2192 25328 CEFBS_InMicroMips_HasDSP, // MULEQ_S_W_PHR_MM = 2193 25329 CEFBS_HasDSP, // MULEU_S_PH_QBL = 2194 25330 CEFBS_InMicroMips_HasDSP, // MULEU_S_PH_QBL_MM = 2195 25331 CEFBS_HasDSP, // MULEU_S_PH_QBR = 2196 25332 CEFBS_InMicroMips_HasDSP, // MULEU_S_PH_QBR_MM = 2197 25333 CEFBS_HasDSP, // MULQ_RS_PH = 2198 25334 CEFBS_InMicroMips_HasDSP, // MULQ_RS_PH_MM = 2199 25335 CEFBS_HasDSPR2, // MULQ_RS_W = 2200 25336 CEFBS_InMicroMips_HasDSPR2, // MULQ_RS_W_MMR2 = 2201 25337 CEFBS_HasDSPR2, // MULQ_S_PH = 2202 25338 CEFBS_InMicroMips_HasDSPR2, // MULQ_S_PH_MMR2 = 2203 25339 CEFBS_HasDSPR2, // MULQ_S_W = 2204 25340 CEFBS_InMicroMips_HasDSPR2, // MULQ_S_W_MMR2 = 2205 25341 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, // MULR_PS64 = 2206 25342 CEFBS_HasStdEnc_HasMSA, // MULR_Q_H = 2207 25343 CEFBS_HasStdEnc_HasMSA, // MULR_Q_W = 2208 25344 CEFBS_HasDSP, // MULSAQ_S_W_PH = 2209 25345 CEFBS_InMicroMips_HasDSP, // MULSAQ_S_W_PH_MM = 2210 25346 CEFBS_HasDSPR2, // MULSA_W_PH = 2211 25347 CEFBS_InMicroMips_HasDSPR2, // MULSA_W_PH_MMR2 = 2212 25348 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MULT = 2213 25349 CEFBS_HasDSP, // MULTU_DSP = 2214 25350 CEFBS_InMicroMips_HasDSP, // MULTU_DSP_MM = 2215 25351 CEFBS_HasDSP, // MULT_DSP = 2216 25352 CEFBS_InMicroMips_HasDSP, // MULT_DSP_MM = 2217 25353 CEFBS_InMicroMips_NotMips32r6, // MULT_MM = 2218 25354 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MULTu = 2219 25355 CEFBS_InMicroMips_NotMips32r6, // MULTu_MM = 2220 25356 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MULU = 2221 25357 CEFBS_InMicroMips_HasMips32r6, // MULU_MMR6 = 2222 25358 CEFBS_HasStdEnc_HasMSA, // MULV_B = 2223 25359 CEFBS_HasStdEnc_HasMSA, // MULV_D = 2224 25360 CEFBS_HasStdEnc_HasMSA, // MULV_H = 2225 25361 CEFBS_HasStdEnc_HasMSA, // MULV_W = 2226 25362 CEFBS_InMicroMips_NotMips32r6, // MUL_MM = 2227 25363 CEFBS_InMicroMips_HasMips32r6, // MUL_MMR6 = 2228 25364 CEFBS_HasDSPR2, // MUL_PH = 2229 25365 CEFBS_InMicroMips_HasDSPR2, // MUL_PH_MMR2 = 2230 25366 CEFBS_HasStdEnc_HasMSA, // MUL_Q_H = 2231 25367 CEFBS_HasStdEnc_HasMSA, // MUL_Q_W = 2232 25368 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MUL_R6 = 2233 25369 CEFBS_HasDSPR2, // MUL_S_PH = 2234 25370 CEFBS_InMicroMips_HasDSPR2, // MUL_S_PH_MMR2 = 2235 25371 CEFBS_InMips16Mode, // Mfhi16 = 2236 25372 CEFBS_InMips16Mode, // Mflo16 = 2237 25373 CEFBS_InMips16Mode, // Move32R16 = 2238 25374 CEFBS_InMips16Mode, // MoveR3216 = 2239 25375 CEFBS_HasStdEnc_HasMSA, // NLOC_B = 2240 25376 CEFBS_HasStdEnc_HasMSA, // NLOC_D = 2241 25377 CEFBS_HasStdEnc_HasMSA, // NLOC_H = 2242 25378 CEFBS_HasStdEnc_HasMSA, // NLOC_W = 2243 25379 CEFBS_HasStdEnc_HasMSA, // NLZC_B = 2244 25380 CEFBS_HasStdEnc_HasMSA, // NLZC_D = 2245 25381 CEFBS_HasStdEnc_HasMSA, // NLZC_H = 2246 25382 CEFBS_HasStdEnc_HasMSA, // NLZC_W = 2247 25383 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMADD_D32 = 2248 25384 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, // NMADD_D32_MM = 2249 25385 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMADD_D64 = 2250 25386 CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMADD_S = 2251 25387 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, // NMADD_S_MM = 2252 25388 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMSUB_D32 = 2253 25389 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, // NMSUB_D32_MM = 2254 25390 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMSUB_D64 = 2255 25391 CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMSUB_S = 2256 25392 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, // NMSUB_S_MM = 2257 25393 CEFBS_HasStdEnc_NotInMicroMips, // NOR = 2258 25394 CEFBS_NotInMips16Mode_IsGP64bit, // NOR64 = 2259 25395 CEFBS_HasStdEnc_HasMSA, // NORI_B = 2260 25396 CEFBS_InMicroMips_NotMips32r6, // NOR_MM = 2261 25397 CEFBS_InMicroMips_HasMips32r6, // NOR_MMR6 = 2262 25398 CEFBS_HasStdEnc_HasMSA, // NOR_V = 2263 25399 CEFBS_InMicroMips_NotMips32r6, // NOT16_MM = 2264 25400 CEFBS_InMicroMips_HasMips32r6, // NOT16_MMR6 = 2265 25401 CEFBS_InMips16Mode, // NegRxRy16 = 2266 25402 CEFBS_InMips16Mode, // NotRxRy16 = 2267 25403 CEFBS_HasStdEnc_NotInMicroMips, // OR = 2268 25404 CEFBS_InMicroMips_NotMips32r6, // OR16_MM = 2269 25405 CEFBS_InMicroMips_HasMips32r6, // OR16_MMR6 = 2270 25406 CEFBS_NotInMips16Mode_IsGP64bit, // OR64 = 2271 25407 CEFBS_HasStdEnc_HasMSA, // ORI_B = 2272 25408 CEFBS_InMicroMips_HasMips32r6, // ORI_MMR6 = 2273 25409 CEFBS_InMicroMips_NotMips32r6, // OR_MM = 2274 25410 CEFBS_InMicroMips_HasMips32r6, // OR_MMR6 = 2275 25411 CEFBS_HasStdEnc_HasMSA, // OR_V = 2276 25412 CEFBS_HasStdEnc_NotInMicroMips, // ORi = 2277 25413 CEFBS_NotInMips16Mode_IsGP64bit, // ORi64 = 2278 25414 CEFBS_InMicroMips_NotMips32r6, // ORi_MM = 2279 25415 CEFBS_InMips16Mode, // OrRxRxRy16 = 2280 25416 CEFBS_HasDSP, // PACKRL_PH = 2281 25417 CEFBS_InMicroMips_HasDSP, // PACKRL_PH_MM = 2282 25418 CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // PAUSE = 2283 25419 CEFBS_InMicroMips, // PAUSE_MM = 2284 25420 CEFBS_InMicroMips_HasMips32r6, // PAUSE_MMR6 = 2285 25421 CEFBS_HasStdEnc_HasMSA, // PCKEV_B = 2286 25422 CEFBS_HasStdEnc_HasMSA, // PCKEV_D = 2287 25423 CEFBS_HasStdEnc_HasMSA, // PCKEV_H = 2288 25424 CEFBS_HasStdEnc_HasMSA, // PCKEV_W = 2289 25425 CEFBS_HasStdEnc_HasMSA, // PCKOD_B = 2290 25426 CEFBS_HasStdEnc_HasMSA, // PCKOD_D = 2291 25427 CEFBS_HasStdEnc_HasMSA, // PCKOD_H = 2292 25428 CEFBS_HasStdEnc_HasMSA, // PCKOD_W = 2293 25429 CEFBS_HasStdEnc_HasMSA, // PCNT_B = 2294 25430 CEFBS_HasStdEnc_HasMSA, // PCNT_D = 2295 25431 CEFBS_HasStdEnc_HasMSA, // PCNT_H = 2296 25432 CEFBS_HasStdEnc_HasMSA, // PCNT_W = 2297 25433 CEFBS_HasDSP, // PICK_PH = 2298 25434 CEFBS_InMicroMips_HasDSP, // PICK_PH_MM = 2299 25435 CEFBS_HasDSP, // PICK_QB = 2300 25436 CEFBS_InMicroMips_HasDSP, // PICK_QB_MM = 2301 25437 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // PLL_PS64 = 2302 25438 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // PLU_PS64 = 2303 25439 CEFBS_HasCnMips, // POP = 2304 25440 CEFBS_HasDSP, // PRECEQU_PH_QBL = 2305 25441 CEFBS_HasDSP, // PRECEQU_PH_QBLA = 2306 25442 CEFBS_InMicroMips_HasDSP, // PRECEQU_PH_QBLA_MM = 2307 25443 CEFBS_InMicroMips_HasDSP, // PRECEQU_PH_QBL_MM = 2308 25444 CEFBS_HasDSP, // PRECEQU_PH_QBR = 2309 25445 CEFBS_HasDSP, // PRECEQU_PH_QBRA = 2310 25446 CEFBS_InMicroMips_HasDSP, // PRECEQU_PH_QBRA_MM = 2311 25447 CEFBS_InMicroMips_HasDSP, // PRECEQU_PH_QBR_MM = 2312 25448 CEFBS_HasDSP, // PRECEQ_W_PHL = 2313 25449 CEFBS_InMicroMips_HasDSP, // PRECEQ_W_PHL_MM = 2314 25450 CEFBS_HasDSP, // PRECEQ_W_PHR = 2315 25451 CEFBS_InMicroMips_HasDSP, // PRECEQ_W_PHR_MM = 2316 25452 CEFBS_HasDSP, // PRECEU_PH_QBL = 2317 25453 CEFBS_HasDSP, // PRECEU_PH_QBLA = 2318 25454 CEFBS_InMicroMips_HasDSP, // PRECEU_PH_QBLA_MM = 2319 25455 CEFBS_InMicroMips_HasDSP, // PRECEU_PH_QBL_MM = 2320 25456 CEFBS_HasDSP, // PRECEU_PH_QBR = 2321 25457 CEFBS_HasDSP, // PRECEU_PH_QBRA = 2322 25458 CEFBS_InMicroMips_HasDSP, // PRECEU_PH_QBRA_MM = 2323 25459 CEFBS_InMicroMips_HasDSP, // PRECEU_PH_QBR_MM = 2324 25460 CEFBS_HasDSP, // PRECRQU_S_QB_PH = 2325 25461 CEFBS_InMicroMips_HasDSP, // PRECRQU_S_QB_PH_MM = 2326 25462 CEFBS_HasDSP, // PRECRQ_PH_W = 2327 25463 CEFBS_InMicroMips_HasDSP, // PRECRQ_PH_W_MM = 2328 25464 CEFBS_HasDSP, // PRECRQ_QB_PH = 2329 25465 CEFBS_InMicroMips_HasDSP, // PRECRQ_QB_PH_MM = 2330 25466 CEFBS_HasDSP, // PRECRQ_RS_PH_W = 2331 25467 CEFBS_InMicroMips_HasDSP, // PRECRQ_RS_PH_W_MM = 2332 25468 CEFBS_HasDSPR2, // PRECR_QB_PH = 2333 25469 CEFBS_InMicroMips_HasDSPR2, // PRECR_QB_PH_MMR2 = 2334 25470 CEFBS_HasDSPR2, // PRECR_SRA_PH_W = 2335 25471 CEFBS_InMicroMips_HasDSPR2, // PRECR_SRA_PH_W_MMR2 = 2336 25472 CEFBS_HasDSPR2, // PRECR_SRA_R_PH_W = 2337 25473 CEFBS_InMicroMips_HasDSPR2, // PRECR_SRA_R_PH_W_MMR2 = 2338 25474 CEFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips, // PREF = 2339 25475 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // PREFE = 2340 25476 CEFBS_InMicroMips_HasEVA, // PREFE_MM = 2341 25477 CEFBS_InMicroMips_NotMips32r6, // PREFX_MM = 2342 25478 CEFBS_InMicroMips_NotMips32r6, // PREF_MM = 2343 25479 CEFBS_InMicroMips_HasMips32r6, // PREF_MMR6 = 2344 25480 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // PREF_R6 = 2345 25481 CEFBS_HasDSPR2, // PREPEND = 2346 25482 CEFBS_InMicroMips_HasDSPR2, // PREPEND_MMR2 = 2347 25483 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // PUL_PS64 = 2348 25484 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // PUU_PS64 = 2349 25485 CEFBS_HasDSP, // RADDU_W_QB = 2350 25486 CEFBS_InMicroMips_HasDSP, // RADDU_W_QB_MM = 2351 25487 CEFBS_HasDSP, // RDDSP = 2352 25488 CEFBS_InMicroMips_HasDSP, // RDDSP_MM = 2353 25489 CEFBS_HasStdEnc_NotInMicroMips, // RDHWR = 2354 25490 CEFBS_NotInMips16Mode_IsGP64bit, // RDHWR64 = 2355 25491 CEFBS_InMicroMips_NotMips32r6, // RDHWR_MM = 2356 25492 CEFBS_InMicroMips_HasMips32r6, // RDHWR_MMR6 = 2357 25493 CEFBS_InMicroMips_HasMips32r6, // RDPGPR_MMR6 = 2358 25494 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RECIP_D32 = 2359 25495 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // RECIP_D32_MM = 2360 25496 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RECIP_D64 = 2361 25497 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // RECIP_D64_MM = 2362 25498 CEFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RECIP_S = 2363 25499 CEFBS_InMicroMips_IsNotSoftFloat, // RECIP_S_MM = 2364 25500 CEFBS_HasDSP, // REPLV_PH = 2365 25501 CEFBS_InMicroMips_HasDSP, // REPLV_PH_MM = 2366 25502 CEFBS_HasDSP, // REPLV_QB = 2367 25503 CEFBS_InMicroMips_HasDSP, // REPLV_QB_MM = 2368 25504 CEFBS_HasDSP, // REPL_PH = 2369 25505 CEFBS_InMicroMips_HasDSP, // REPL_PH_MM = 2370 25506 CEFBS_HasDSP, // REPL_QB = 2371 25507 CEFBS_InMicroMips_HasDSP, // REPL_QB_MM = 2372 25508 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // RINT_D = 2373 25509 CEFBS_InMicroMips_HasMips32r6, // RINT_D_MMR6 = 2374 25510 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // RINT_S = 2375 25511 CEFBS_InMicroMips_HasMips32r6, // RINT_S_MMR6 = 2376 25512 CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // ROTR = 2377 25513 CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // ROTRV = 2378 25514 CEFBS_InMicroMips, // ROTRV_MM = 2379 25515 CEFBS_InMicroMips, // ROTR_MM = 2380 25516 CEFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, // ROUND_L_D64 = 2381 25517 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // ROUND_L_D_MMR6 = 2382 25518 CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // ROUND_L_S = 2383 25519 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // ROUND_L_S_MMR6 = 2384 25520 CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // ROUND_W_D32 = 2385 25521 CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // ROUND_W_D64 = 2386 25522 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // ROUND_W_D_MMR6 = 2387 25523 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // ROUND_W_MM = 2388 25524 CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, // ROUND_W_S = 2389 25525 CEFBS_InMicroMips_IsNotSoftFloat, // ROUND_W_S_MM = 2390 25526 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // ROUND_W_S_MMR6 = 2391 25527 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RSQRT_D32 = 2392 25528 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // RSQRT_D32_MM = 2393 25529 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RSQRT_D64 = 2394 25530 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // RSQRT_D64_MM = 2395 25531 CEFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RSQRT_S = 2396 25532 CEFBS_InMicroMips_IsNotSoftFloat, // RSQRT_S_MM = 2397 25533 CEFBS_InMips16Mode, // Restore16 = 2398 25534 CEFBS_InMips16Mode, // RestoreX16 = 2399 25535 CEFBS_HasCnMipsP, // SAA = 2400 25536 CEFBS_HasCnMipsP, // SAAD = 2401 25537 CEFBS_HasStdEnc_HasMSA, // SAT_S_B = 2402 25538 CEFBS_HasStdEnc_HasMSA, // SAT_S_D = 2403 25539 CEFBS_HasStdEnc_HasMSA, // SAT_S_H = 2404 25540 CEFBS_HasStdEnc_HasMSA, // SAT_S_W = 2405 25541 CEFBS_HasStdEnc_HasMSA, // SAT_U_B = 2406 25542 CEFBS_HasStdEnc_HasMSA, // SAT_U_D = 2407 25543 CEFBS_HasStdEnc_HasMSA, // SAT_U_H = 2408 25544 CEFBS_HasStdEnc_HasMSA, // SAT_U_W = 2409 25545 CEFBS_HasStdEnc_NotInMicroMips, // SB = 2410 25546 CEFBS_InMicroMips_NotMips32r6, // SB16_MM = 2411 25547 CEFBS_InMicroMips_HasMips32r6, // SB16_MMR6 = 2412 25548 CEFBS_NotInMips16Mode_IsGP64bit, // SB64 = 2413 25549 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // SBE = 2414 25550 CEFBS_InMicroMips_HasEVA, // SBE_MM = 2415 25551 CEFBS_InMicroMips, // SB_MM = 2416 25552 CEFBS_InMicroMips_HasMips32r6, // SB_MMR6 = 2417 25553 CEFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // SC = 2418 25554 CEFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // SC64 = 2419 25555 CEFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips, // SC64_R6 = 2420 25556 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // SCD = 2421 25557 CEFBS_HasStdEnc_HasMips32r6, // SCD_R6 = 2422 25558 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // SCE = 2423 25559 CEFBS_InMicroMips_HasEVA, // SCE_MM = 2424 25560 CEFBS_InMicroMips_NotMips32r6, // SC_MM = 2425 25561 CEFBS_InMicroMips_HasMips32r6, // SC_MMR6 = 2426 25562 CEFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips, // SC_R6 = 2427 25563 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // SD = 2428 25564 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // SDBBP = 2429 25565 CEFBS_InMicroMips_NotMips32r6, // SDBBP16_MM = 2430 25566 CEFBS_InMicroMips_HasMips32r6, // SDBBP16_MMR6 = 2431 25567 CEFBS_InMicroMips, // SDBBP_MM = 2432 25568 CEFBS_InMicroMips_HasMips32r6, // SDBBP_MMR6 = 2433 25569 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // SDBBP_R6 = 2434 25570 CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // SDC1 = 2435 25571 CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // SDC164 = 2436 25572 CEFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, // SDC1_D64_MMR6 = 2437 25573 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // SDC1_MM_D32 = 2438 25574 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // SDC1_MM_D64 = 2439 25575 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // SDC2 = 2440 25576 CEFBS_InMicroMips_HasMips32r6, // SDC2_MMR6 = 2441 25577 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // SDC2_R6 = 2442 25578 CEFBS_HasStdEnc_HasMips2_NotCnMips_NotInMicroMips, // SDC3 = 2443 25579 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // SDIV = 2444 25580 CEFBS_InMicroMips_NotMips32r6, // SDIV_MM = 2445 25581 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // SDL = 2446 25582 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // SDR = 2447 25583 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // SDXC1 = 2448 25584 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, // SDXC164 = 2449 25585 CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // SEB = 2450 25586 CEFBS_HasStdEnc_IsGP64bit_HasMips32r2, // SEB64 = 2451 25587 CEFBS_InMicroMips, // SEB_MM = 2452 25588 CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // SEH = 2453 25589 CEFBS_HasStdEnc_IsGP64bit_HasMips32r2, // SEH64 = 2454 25590 CEFBS_InMicroMips, // SEH_MM = 2455 25591 CEFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips, // SELEQZ = 2456 25592 CEFBS_HasStdEnc_IsGP64bit_HasMips32r6, // SELEQZ64 = 2457 25593 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SELEQZ_D = 2458 25594 CEFBS_InMicroMips_HasMips32r6, // SELEQZ_D_MMR6 = 2459 25595 CEFBS_InMicroMips_HasMips32r6, // SELEQZ_MMR6 = 2460 25596 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SELEQZ_S = 2461 25597 CEFBS_InMicroMips_HasMips32r6, // SELEQZ_S_MMR6 = 2462 25598 CEFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips, // SELNEZ = 2463 25599 CEFBS_HasStdEnc_IsGP64bit_HasMips32r6, // SELNEZ64 = 2464 25600 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SELNEZ_D = 2465 25601 CEFBS_InMicroMips_HasMips32r6, // SELNEZ_D_MMR6 = 2466 25602 CEFBS_InMicroMips_HasMips32r6, // SELNEZ_MMR6 = 2467 25603 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SELNEZ_S = 2468 25604 CEFBS_InMicroMips_HasMips32r6, // SELNEZ_S_MMR6 = 2469 25605 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SEL_D = 2470 25606 CEFBS_InMicroMips_HasMips32r6, // SEL_D_MMR6 = 2471 25607 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SEL_S = 2472 25608 CEFBS_InMicroMips_HasMips32r6, // SEL_S_MMR6 = 2473 25609 CEFBS_HasCnMips, // SEQ = 2474 25610 CEFBS_HasCnMips, // SEQi = 2475 25611 CEFBS_HasStdEnc_NotInMicroMips, // SH = 2476 25612 CEFBS_InMicroMips_NotMips32r6, // SH16_MM = 2477 25613 CEFBS_InMicroMips_HasMips32r6, // SH16_MMR6 = 2478 25614 CEFBS_NotInMips16Mode_IsGP64bit, // SH64 = 2479 25615 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // SHE = 2480 25616 CEFBS_InMicroMips_HasEVA, // SHE_MM = 2481 25617 CEFBS_HasStdEnc_HasMSA, // SHF_B = 2482 25618 CEFBS_HasStdEnc_HasMSA, // SHF_H = 2483 25619 CEFBS_HasStdEnc_HasMSA, // SHF_W = 2484 25620 CEFBS_HasDSP, // SHILO = 2485 25621 CEFBS_HasDSP, // SHILOV = 2486 25622 CEFBS_InMicroMips_HasDSP, // SHILOV_MM = 2487 25623 CEFBS_InMicroMips_HasDSP, // SHILO_MM = 2488 25624 CEFBS_HasDSP, // SHLLV_PH = 2489 25625 CEFBS_InMicroMips_HasDSP, // SHLLV_PH_MM = 2490 25626 CEFBS_HasDSP, // SHLLV_QB = 2491 25627 CEFBS_InMicroMips_HasDSP, // SHLLV_QB_MM = 2492 25628 CEFBS_HasDSP, // SHLLV_S_PH = 2493 25629 CEFBS_InMicroMips_HasDSP, // SHLLV_S_PH_MM = 2494 25630 CEFBS_HasDSP, // SHLLV_S_W = 2495 25631 CEFBS_InMicroMips_HasDSP, // SHLLV_S_W_MM = 2496 25632 CEFBS_HasDSP, // SHLL_PH = 2497 25633 CEFBS_InMicroMips_HasDSP, // SHLL_PH_MM = 2498 25634 CEFBS_HasDSP, // SHLL_QB = 2499 25635 CEFBS_InMicroMips_HasDSP, // SHLL_QB_MM = 2500 25636 CEFBS_HasDSP, // SHLL_S_PH = 2501 25637 CEFBS_InMicroMips_HasDSP, // SHLL_S_PH_MM = 2502 25638 CEFBS_HasDSP, // SHLL_S_W = 2503 25639 CEFBS_InMicroMips_HasDSP, // SHLL_S_W_MM = 2504 25640 CEFBS_HasDSP, // SHRAV_PH = 2505 25641 CEFBS_InMicroMips_HasDSP, // SHRAV_PH_MM = 2506 25642 CEFBS_HasDSPR2, // SHRAV_QB = 2507 25643 CEFBS_InMicroMips_HasDSPR2, // SHRAV_QB_MMR2 = 2508 25644 CEFBS_HasDSP, // SHRAV_R_PH = 2509 25645 CEFBS_InMicroMips_HasDSP, // SHRAV_R_PH_MM = 2510 25646 CEFBS_HasDSPR2, // SHRAV_R_QB = 2511 25647 CEFBS_InMicroMips_HasDSPR2, // SHRAV_R_QB_MMR2 = 2512 25648 CEFBS_HasDSP, // SHRAV_R_W = 2513 25649 CEFBS_InMicroMips_HasDSP, // SHRAV_R_W_MM = 2514 25650 CEFBS_HasDSP, // SHRA_PH = 2515 25651 CEFBS_InMicroMips_HasDSP, // SHRA_PH_MM = 2516 25652 CEFBS_HasDSPR2, // SHRA_QB = 2517 25653 CEFBS_InMicroMips_HasDSPR2, // SHRA_QB_MMR2 = 2518 25654 CEFBS_HasDSP, // SHRA_R_PH = 2519 25655 CEFBS_InMicroMips_HasDSP, // SHRA_R_PH_MM = 2520 25656 CEFBS_HasDSPR2, // SHRA_R_QB = 2521 25657 CEFBS_InMicroMips_HasDSPR2, // SHRA_R_QB_MMR2 = 2522 25658 CEFBS_HasDSP, // SHRA_R_W = 2523 25659 CEFBS_InMicroMips_HasDSP, // SHRA_R_W_MM = 2524 25660 CEFBS_HasDSPR2, // SHRLV_PH = 2525 25661 CEFBS_InMicroMips_HasDSPR2, // SHRLV_PH_MMR2 = 2526 25662 CEFBS_HasDSP, // SHRLV_QB = 2527 25663 CEFBS_InMicroMips_HasDSP, // SHRLV_QB_MM = 2528 25664 CEFBS_HasDSPR2, // SHRL_PH = 2529 25665 CEFBS_InMicroMips_HasDSPR2, // SHRL_PH_MMR2 = 2530 25666 CEFBS_HasDSP, // SHRL_QB = 2531 25667 CEFBS_InMicroMips_HasDSP, // SHRL_QB_MM = 2532 25668 CEFBS_InMicroMips, // SH_MM = 2533 25669 CEFBS_InMicroMips_HasMips32r6, // SH_MMR6 = 2534 25670 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // SIGRIE = 2535 25671 CEFBS_InMicroMips_HasMips32r6, // SIGRIE_MMR6 = 2536 25672 CEFBS_HasStdEnc_HasMSA, // SLDI_B = 2537 25673 CEFBS_HasStdEnc_HasMSA, // SLDI_D = 2538 25674 CEFBS_HasStdEnc_HasMSA, // SLDI_H = 2539 25675 CEFBS_HasStdEnc_HasMSA, // SLDI_W = 2540 25676 CEFBS_HasStdEnc_HasMSA, // SLD_B = 2541 25677 CEFBS_HasStdEnc_HasMSA, // SLD_D = 2542 25678 CEFBS_HasStdEnc_HasMSA, // SLD_H = 2543 25679 CEFBS_HasStdEnc_HasMSA, // SLD_W = 2544 25680 CEFBS_HasStdEnc_NotInMicroMips, // SLL = 2545 25681 CEFBS_InMicroMips_NotMips32r6, // SLL16_MM = 2546 25682 CEFBS_InMicroMips_HasMips32r6, // SLL16_MMR6 = 2547 25683 CEFBS_NotInMips16Mode_IsGP64bit, // SLL64_32 = 2548 25684 CEFBS_NotInMips16Mode_IsGP64bit, // SLL64_64 = 2549 25685 CEFBS_HasStdEnc_HasMSA, // SLLI_B = 2550 25686 CEFBS_HasStdEnc_HasMSA, // SLLI_D = 2551 25687 CEFBS_HasStdEnc_HasMSA, // SLLI_H = 2552 25688 CEFBS_HasStdEnc_HasMSA, // SLLI_W = 2553 25689 CEFBS_HasStdEnc_NotInMicroMips, // SLLV = 2554 25690 CEFBS_InMicroMips, // SLLV_MM = 2555 25691 CEFBS_HasStdEnc_HasMSA, // SLL_B = 2556 25692 CEFBS_HasStdEnc_HasMSA, // SLL_D = 2557 25693 CEFBS_HasStdEnc_HasMSA, // SLL_H = 2558 25694 CEFBS_InMicroMips, // SLL_MM = 2559 25695 CEFBS_InMicroMips_HasMips32r6, // SLL_MMR6 = 2560 25696 CEFBS_HasStdEnc_HasMSA, // SLL_W = 2561 25697 CEFBS_HasStdEnc_NotInMicroMips, // SLT = 2562 25698 CEFBS_NotInMips16Mode_IsGP64bit, // SLT64 = 2563 25699 CEFBS_InMicroMips, // SLT_MM = 2564 25700 CEFBS_HasStdEnc_NotInMicroMips, // SLTi = 2565 25701 CEFBS_NotInMips16Mode_IsGP64bit, // SLTi64 = 2566 25702 CEFBS_InMicroMips, // SLTi_MM = 2567 25703 CEFBS_HasStdEnc_NotInMicroMips, // SLTiu = 2568 25704 CEFBS_NotInMips16Mode_IsGP64bit, // SLTiu64 = 2569 25705 CEFBS_InMicroMips, // SLTiu_MM = 2570 25706 CEFBS_HasStdEnc_NotInMicroMips, // SLTu = 2571 25707 CEFBS_NotInMips16Mode_IsGP64bit, // SLTu64 = 2572 25708 CEFBS_InMicroMips, // SLTu_MM = 2573 25709 CEFBS_HasCnMips, // SNE = 2574 25710 CEFBS_HasCnMips, // SNEi = 2575 25711 CEFBS_HasStdEnc_HasMSA, // SPLATI_B = 2576 25712 CEFBS_HasStdEnc_HasMSA, // SPLATI_D = 2577 25713 CEFBS_HasStdEnc_HasMSA, // SPLATI_H = 2578 25714 CEFBS_HasStdEnc_HasMSA, // SPLATI_W = 2579 25715 CEFBS_HasStdEnc_HasMSA, // SPLAT_B = 2580 25716 CEFBS_HasStdEnc_HasMSA, // SPLAT_D = 2581 25717 CEFBS_HasStdEnc_HasMSA, // SPLAT_H = 2582 25718 CEFBS_HasStdEnc_HasMSA, // SPLAT_W = 2583 25719 CEFBS_HasStdEnc_NotInMicroMips, // SRA = 2584 25720 CEFBS_HasStdEnc_HasMSA, // SRAI_B = 2585 25721 CEFBS_HasStdEnc_HasMSA, // SRAI_D = 2586 25722 CEFBS_HasStdEnc_HasMSA, // SRAI_H = 2587 25723 CEFBS_HasStdEnc_HasMSA, // SRAI_W = 2588 25724 CEFBS_HasStdEnc_HasMSA, // SRARI_B = 2589 25725 CEFBS_HasStdEnc_HasMSA, // SRARI_D = 2590 25726 CEFBS_HasStdEnc_HasMSA, // SRARI_H = 2591 25727 CEFBS_HasStdEnc_HasMSA, // SRARI_W = 2592 25728 CEFBS_HasStdEnc_HasMSA, // SRAR_B = 2593 25729 CEFBS_HasStdEnc_HasMSA, // SRAR_D = 2594 25730 CEFBS_HasStdEnc_HasMSA, // SRAR_H = 2595 25731 CEFBS_HasStdEnc_HasMSA, // SRAR_W = 2596 25732 CEFBS_HasStdEnc_NotInMicroMips, // SRAV = 2597 25733 CEFBS_InMicroMips, // SRAV_MM = 2598 25734 CEFBS_HasStdEnc_HasMSA, // SRA_B = 2599 25735 CEFBS_HasStdEnc_HasMSA, // SRA_D = 2600 25736 CEFBS_HasStdEnc_HasMSA, // SRA_H = 2601 25737 CEFBS_InMicroMips, // SRA_MM = 2602 25738 CEFBS_HasStdEnc_HasMSA, // SRA_W = 2603 25739 CEFBS_HasStdEnc_NotInMicroMips, // SRL = 2604 25740 CEFBS_InMicroMips_NotMips32r6, // SRL16_MM = 2605 25741 CEFBS_InMicroMips_HasMips32r6, // SRL16_MMR6 = 2606 25742 CEFBS_HasStdEnc_HasMSA, // SRLI_B = 2607 25743 CEFBS_HasStdEnc_HasMSA, // SRLI_D = 2608 25744 CEFBS_HasStdEnc_HasMSA, // SRLI_H = 2609 25745 CEFBS_HasStdEnc_HasMSA, // SRLI_W = 2610 25746 CEFBS_HasStdEnc_HasMSA, // SRLRI_B = 2611 25747 CEFBS_HasStdEnc_HasMSA, // SRLRI_D = 2612 25748 CEFBS_HasStdEnc_HasMSA, // SRLRI_H = 2613 25749 CEFBS_HasStdEnc_HasMSA, // SRLRI_W = 2614 25750 CEFBS_HasStdEnc_HasMSA, // SRLR_B = 2615 25751 CEFBS_HasStdEnc_HasMSA, // SRLR_D = 2616 25752 CEFBS_HasStdEnc_HasMSA, // SRLR_H = 2617 25753 CEFBS_HasStdEnc_HasMSA, // SRLR_W = 2618 25754 CEFBS_HasStdEnc_NotInMicroMips, // SRLV = 2619 25755 CEFBS_InMicroMips, // SRLV_MM = 2620 25756 CEFBS_HasStdEnc_HasMSA, // SRL_B = 2621 25757 CEFBS_HasStdEnc_HasMSA, // SRL_D = 2622 25758 CEFBS_HasStdEnc_HasMSA, // SRL_H = 2623 25759 CEFBS_InMicroMips, // SRL_MM = 2624 25760 CEFBS_HasStdEnc_HasMSA, // SRL_W = 2625 25761 CEFBS_HasStdEnc_NotInMicroMips, // SSNOP = 2626 25762 CEFBS_InMicroMips, // SSNOP_MM = 2627 25763 CEFBS_InMicroMips_HasMips32r6, // SSNOP_MMR6 = 2628 25764 CEFBS_HasStdEnc_HasMSA, // ST_B = 2629 25765 CEFBS_HasStdEnc_HasMSA, // ST_D = 2630 25766 CEFBS_HasStdEnc_HasMSA, // ST_H = 2631 25767 CEFBS_HasStdEnc_HasMSA, // ST_W = 2632 25768 CEFBS_HasStdEnc_NotInMicroMips, // SUB = 2633 25769 CEFBS_HasDSPR2, // SUBQH_PH = 2634 25770 CEFBS_InMicroMips_HasDSPR2, // SUBQH_PH_MMR2 = 2635 25771 CEFBS_HasDSPR2, // SUBQH_R_PH = 2636 25772 CEFBS_InMicroMips_HasDSPR2, // SUBQH_R_PH_MMR2 = 2637 25773 CEFBS_HasDSPR2, // SUBQH_R_W = 2638 25774 CEFBS_InMicroMips_HasDSPR2, // SUBQH_R_W_MMR2 = 2639 25775 CEFBS_HasDSPR2, // SUBQH_W = 2640 25776 CEFBS_InMicroMips_HasDSPR2, // SUBQH_W_MMR2 = 2641 25777 CEFBS_HasDSP, // SUBQ_PH = 2642 25778 CEFBS_InMicroMips_HasDSP, // SUBQ_PH_MM = 2643 25779 CEFBS_HasDSP, // SUBQ_S_PH = 2644 25780 CEFBS_InMicroMips_HasDSP, // SUBQ_S_PH_MM = 2645 25781 CEFBS_HasDSP, // SUBQ_S_W = 2646 25782 CEFBS_InMicroMips_HasDSP, // SUBQ_S_W_MM = 2647 25783 CEFBS_HasStdEnc_HasMSA, // SUBSUS_U_B = 2648 25784 CEFBS_HasStdEnc_HasMSA, // SUBSUS_U_D = 2649 25785 CEFBS_HasStdEnc_HasMSA, // SUBSUS_U_H = 2650 25786 CEFBS_HasStdEnc_HasMSA, // SUBSUS_U_W = 2651 25787 CEFBS_HasStdEnc_HasMSA, // SUBSUU_S_B = 2652 25788 CEFBS_HasStdEnc_HasMSA, // SUBSUU_S_D = 2653 25789 CEFBS_HasStdEnc_HasMSA, // SUBSUU_S_H = 2654 25790 CEFBS_HasStdEnc_HasMSA, // SUBSUU_S_W = 2655 25791 CEFBS_HasStdEnc_HasMSA, // SUBS_S_B = 2656 25792 CEFBS_HasStdEnc_HasMSA, // SUBS_S_D = 2657 25793 CEFBS_HasStdEnc_HasMSA, // SUBS_S_H = 2658 25794 CEFBS_HasStdEnc_HasMSA, // SUBS_S_W = 2659 25795 CEFBS_HasStdEnc_HasMSA, // SUBS_U_B = 2660 25796 CEFBS_HasStdEnc_HasMSA, // SUBS_U_D = 2661 25797 CEFBS_HasStdEnc_HasMSA, // SUBS_U_H = 2662 25798 CEFBS_HasStdEnc_HasMSA, // SUBS_U_W = 2663 25799 CEFBS_InMicroMips_NotMips32r6, // SUBU16_MM = 2664 25800 CEFBS_InMicroMips_HasMips32r6, // SUBU16_MMR6 = 2665 25801 CEFBS_HasDSPR2, // SUBUH_QB = 2666 25802 CEFBS_InMicroMips_HasDSPR2, // SUBUH_QB_MMR2 = 2667 25803 CEFBS_HasDSPR2, // SUBUH_R_QB = 2668 25804 CEFBS_InMicroMips_HasDSPR2, // SUBUH_R_QB_MMR2 = 2669 25805 CEFBS_InMicroMips_HasMips32r6, // SUBU_MMR6 = 2670 25806 CEFBS_HasDSPR2, // SUBU_PH = 2671 25807 CEFBS_InMicroMips_HasDSPR2, // SUBU_PH_MMR2 = 2672 25808 CEFBS_HasDSP, // SUBU_QB = 2673 25809 CEFBS_InMicroMips_HasDSP, // SUBU_QB_MM = 2674 25810 CEFBS_HasDSPR2, // SUBU_S_PH = 2675 25811 CEFBS_InMicroMips_HasDSPR2, // SUBU_S_PH_MMR2 = 2676 25812 CEFBS_HasDSP, // SUBU_S_QB = 2677 25813 CEFBS_InMicroMips_HasDSP, // SUBU_S_QB_MM = 2678 25814 CEFBS_HasStdEnc_HasMSA, // SUBVI_B = 2679 25815 CEFBS_HasStdEnc_HasMSA, // SUBVI_D = 2680 25816 CEFBS_HasStdEnc_HasMSA, // SUBVI_H = 2681 25817 CEFBS_HasStdEnc_HasMSA, // SUBVI_W = 2682 25818 CEFBS_HasStdEnc_HasMSA, // SUBV_B = 2683 25819 CEFBS_HasStdEnc_HasMSA, // SUBV_D = 2684 25820 CEFBS_HasStdEnc_HasMSA, // SUBV_H = 2685 25821 CEFBS_HasStdEnc_HasMSA, // SUBV_W = 2686 25822 CEFBS_InMicroMips_NotMips32r6, // SUB_MM = 2687 25823 CEFBS_InMicroMips_HasMips32r6, // SUB_MMR6 = 2688 25824 CEFBS_HasStdEnc_NotInMicroMips, // SUBu = 2689 25825 CEFBS_InMicroMips_NotMips32r6, // SUBu_MM = 2690 25826 CEFBS_HasStdEnc_NotFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // SUXC1 = 2691 25827 CEFBS_HasStdEnc_IsFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // SUXC164 = 2692 25828 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // SUXC1_MM = 2693 25829 CEFBS_HasStdEnc_NotInMicroMips, // SW = 2694 25830 CEFBS_InMicroMips_NotMips32r6, // SW16_MM = 2695 25831 CEFBS_InMicroMips_HasMips32r6, // SW16_MMR6 = 2696 25832 CEFBS_NotInMips16Mode_IsGP64bit, // SW64 = 2697 25833 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // SWC1 = 2698 25834 CEFBS_InMicroMips_IsNotSoftFloat, // SWC1_MM = 2699 25835 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // SWC2 = 2700 25836 CEFBS_InMicroMips_HasMips32r6, // SWC2_MMR6 = 2701 25837 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // SWC2_R6 = 2702 25838 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotCnMips_NotInMicroMips, // SWC3 = 2703 25839 CEFBS_NotInMips16Mode_HasDSP, // SWDSP = 2704 25840 CEFBS_InMicroMips_HasDSP, // SWDSP_MM = 2705 25841 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // SWE = 2706 25842 CEFBS_InMicroMips_HasEVA, // SWE_MM = 2707 25843 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // SWL = 2708 25844 CEFBS_NotInMips16Mode_IsGP64bit, // SWL64 = 2709 25845 CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, // SWLE = 2710 25846 CEFBS_InMicroMips_NotMips32r6_HasEVA, // SWLE_MM = 2711 25847 CEFBS_InMicroMips_NotMips32r6, // SWL_MM = 2712 25848 CEFBS_InMicroMips_NotMips32r6, // SWM16_MM = 2713 25849 CEFBS_InMicroMips_HasMips32r6, // SWM16_MMR6 = 2714 25850 CEFBS_InMicroMips, // SWM32_MM = 2715 25851 CEFBS_InMicroMips, // SWP_MM = 2716 25852 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // SWR = 2717 25853 CEFBS_NotInMips16Mode_IsGP64bit, // SWR64 = 2718 25854 CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, // SWRE = 2719 25855 CEFBS_InMicroMips_NotMips32r6_HasEVA, // SWRE_MM = 2720 25856 CEFBS_InMicroMips_NotMips32r6, // SWR_MM = 2721 25857 CEFBS_InMicroMips_NotMips32r6, // SWSP_MM = 2722 25858 CEFBS_InMicroMips_HasMips32r6, // SWSP_MMR6 = 2723 25859 CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, // SWXC1 = 2724 25860 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // SWXC1_MM = 2725 25861 CEFBS_InMicroMips, // SW_MM = 2726 25862 CEFBS_InMicroMips_HasMips32r6, // SW_MMR6 = 2727 25863 CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // SYNC = 2728 25864 CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // SYNCI = 2729 25865 CEFBS_InMicroMips_NotMips32r6, // SYNCI_MM = 2730 25866 CEFBS_InMicroMips_HasMips32r6, // SYNCI_MMR6 = 2731 25867 CEFBS_InMicroMips, // SYNC_MM = 2732 25868 CEFBS_InMicroMips_HasMips32r6, // SYNC_MMR6 = 2733 25869 CEFBS_HasStdEnc_NotInMicroMips, // SYSCALL = 2734 25870 CEFBS_InMicroMips, // SYSCALL_MM = 2735 25871 CEFBS_InMips16Mode, // Save16 = 2736 25872 CEFBS_InMips16Mode, // SaveX16 = 2737 25873 CEFBS_InMips16Mode, // SbRxRyOffMemX16 = 2738 25874 CEFBS_InMips16Mode, // SebRx16 = 2739 25875 CEFBS_InMips16Mode, // SehRx16 = 2740 25876 CEFBS_InMips16Mode, // ShRxRyOffMemX16 = 2741 25877 CEFBS_InMips16Mode, // SllX16 = 2742 25878 CEFBS_InMips16Mode, // SllvRxRy16 = 2743 25879 CEFBS_InMips16Mode, // SltRxRy16 = 2744 25880 CEFBS_InMips16Mode, // SltiRxImm16 = 2745 25881 CEFBS_InMips16Mode, // SltiRxImmX16 = 2746 25882 CEFBS_InMips16Mode, // SltiuRxImm16 = 2747 25883 CEFBS_InMips16Mode, // SltiuRxImmX16 = 2748 25884 CEFBS_InMips16Mode, // SltuRxRy16 = 2749 25885 CEFBS_InMips16Mode, // SraX16 = 2750 25886 CEFBS_InMips16Mode, // SravRxRy16 = 2751 25887 CEFBS_InMips16Mode, // SrlX16 = 2752 25888 CEFBS_InMips16Mode, // SrlvRxRy16 = 2753 25889 CEFBS_InMips16Mode, // SubuRxRyRz16 = 2754 25890 CEFBS_InMips16Mode, // SwRxRyOffMemX16 = 2755 25891 CEFBS_InMips16Mode, // SwRxSpImmX16 = 2756 25892 CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TEQ = 2757 25893 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TEQI = 2758 25894 CEFBS_InMicroMips_NotMips32r6, // TEQI_MM = 2759 25895 CEFBS_InMicroMips, // TEQ_MM = 2760 25896 CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TGE = 2761 25897 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TGEI = 2762 25898 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TGEIU = 2763 25899 CEFBS_InMicroMips_NotMips32r6, // TGEIU_MM = 2764 25900 CEFBS_InMicroMips_NotMips32r6, // TGEI_MM = 2765 25901 CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TGEU = 2766 25902 CEFBS_InMicroMips, // TGEU_MM = 2767 25903 CEFBS_InMicroMips, // TGE_MM = 2768 25904 CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGINV = 2769 25905 CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGINVF = 2770 25906 CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGINVF_MM = 2771 25907 CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGINV_MM = 2772 25908 CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGP = 2773 25909 CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGP_MM = 2774 25910 CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGR = 2775 25911 CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGR_MM = 2776 25912 CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGWI = 2777 25913 CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGWI_MM = 2778 25914 CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGWR = 2779 25915 CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGWR_MM = 2780 25916 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // TLBINV = 2781 25917 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // TLBINVF = 2782 25918 CEFBS_InMicroMips_HasMips32r6, // TLBINVF_MMR6 = 2783 25919 CEFBS_InMicroMips_HasMips32r6, // TLBINV_MMR6 = 2784 25920 CEFBS_HasStdEnc_NotInMicroMips, // TLBP = 2785 25921 CEFBS_InMicroMips, // TLBP_MM = 2786 25922 CEFBS_HasStdEnc_NotInMicroMips, // TLBR = 2787 25923 CEFBS_InMicroMips, // TLBR_MM = 2788 25924 CEFBS_HasStdEnc_NotInMicroMips, // TLBWI = 2789 25925 CEFBS_InMicroMips, // TLBWI_MM = 2790 25926 CEFBS_HasStdEnc_NotInMicroMips, // TLBWR = 2791 25927 CEFBS_InMicroMips, // TLBWR_MM = 2792 25928 CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TLT = 2793 25929 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TLTI = 2794 25930 CEFBS_InMicroMips_NotMips32r6, // TLTIU_MM = 2795 25931 CEFBS_InMicroMips_NotMips32r6, // TLTI_MM = 2796 25932 CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TLTU = 2797 25933 CEFBS_InMicroMips, // TLTU_MM = 2798 25934 CEFBS_InMicroMips, // TLT_MM = 2799 25935 CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TNE = 2800 25936 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TNEI = 2801 25937 CEFBS_InMicroMips_NotMips32r6, // TNEI_MM = 2802 25938 CEFBS_InMicroMips, // TNE_MM = 2803 25939 CEFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, // TRUNC_L_D64 = 2804 25940 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // TRUNC_L_D_MMR6 = 2805 25941 CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // TRUNC_L_S = 2806 25942 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // TRUNC_L_S_MMR6 = 2807 25943 CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // TRUNC_W_D32 = 2808 25944 CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // TRUNC_W_D64 = 2809 25945 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // TRUNC_W_D_MMR6 = 2810 25946 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // TRUNC_W_MM = 2811 25947 CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, // TRUNC_W_S = 2812 25948 CEFBS_InMicroMips_IsNotSoftFloat, // TRUNC_W_S_MM = 2813 25949 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // TRUNC_W_S_MMR6 = 2814 25950 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TTLTIU = 2815 25951 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // UDIV = 2816 25952 CEFBS_InMicroMips_NotMips32r6, // UDIV_MM = 2817 25953 CEFBS_HasCnMips, // V3MULU = 2818 25954 CEFBS_HasCnMips, // VMM0 = 2819 25955 CEFBS_HasCnMips, // VMULU = 2820 25956 CEFBS_HasStdEnc_HasMSA, // VSHF_B = 2821 25957 CEFBS_HasStdEnc_HasMSA, // VSHF_D = 2822 25958 CEFBS_HasStdEnc_HasMSA, // VSHF_H = 2823 25959 CEFBS_HasStdEnc_HasMSA, // VSHF_W = 2824 25960 CEFBS_HasStdEnc_HasMips3_32_NotInMicroMips, // WAIT = 2825 25961 CEFBS_InMicroMips, // WAIT_MM = 2826 25962 CEFBS_InMicroMips_HasMips32r6, // WAIT_MMR6 = 2827 25963 CEFBS_HasDSP_NotInMicroMips, // WRDSP = 2828 25964 CEFBS_InMicroMips_HasDSP, // WRDSP_MM = 2829 25965 CEFBS_InMicroMips_HasMips32r6, // WRPGPR_MMR6 = 2830 25966 CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // WSBH = 2831 25967 CEFBS_InMicroMips, // WSBH_MM = 2832 25968 CEFBS_InMicroMips_HasMips32r6, // WSBH_MMR6 = 2833 25969 CEFBS_HasStdEnc_NotInMicroMips, // XOR = 2834 25970 CEFBS_InMicroMips_NotMips32r6, // XOR16_MM = 2835 25971 CEFBS_InMicroMips_HasMips32r6, // XOR16_MMR6 = 2836 25972 CEFBS_NotInMips16Mode_IsGP64bit, // XOR64 = 2837 25973 CEFBS_HasStdEnc_HasMSA, // XORI_B = 2838 25974 CEFBS_InMicroMips_HasMips32r6, // XORI_MMR6 = 2839 25975 CEFBS_InMicroMips_NotMips32r6, // XOR_MM = 2840 25976 CEFBS_InMicroMips_HasMips32r6, // XOR_MMR6 = 2841 25977 CEFBS_HasStdEnc_HasMSA, // XOR_V = 2842 25978 CEFBS_HasStdEnc_NotInMicroMips, // XORi = 2843 25979 CEFBS_NotInMips16Mode_IsGP64bit, // XORi64 = 2844 25980 CEFBS_InMicroMips_NotMips32r6, // XORi_MM = 2845 25981 CEFBS_InMips16Mode, // XorRxRxRy16 = 2846 25982 CEFBS_HasStdEnc_HasMT_NotInMicroMips, // YIELD = 2847 25983 }; 25984 25985 assert(Opcode < 2848); 25986 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features); 25987 const FeatureBitset &RequiredFeatures = FeatureBitsets[RequiredFeaturesRefs[Opcode]]; 25988 FeatureBitset MissingFeatures = 25989 (AvailableFeatures & RequiredFeatures) ^ 25990 RequiredFeatures; 25991 if (MissingFeatures.any()) { 25992 std::ostringstream Msg; 25993 Msg << "Attempting to emit " << &MipsInstrNameData[MipsInstrNameIndices[Opcode]] 25994 << " instruction but the "; 25995 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i) 25996 if (MissingFeatures.test(i)) 25997 Msg << SubtargetFeatureNames[i] << " "; 25998 Msg << "predicate(s) are not met"; 25999 report_fatal_error(Msg.str().c_str()); 26000 } 26001#endif // NDEBUG 26002} 26003} // end namespace Mips_MC 26004} // end namespace llvm 26005#endif // ENABLE_INSTR_PREDICATE_VERIFIER 26006 26007#ifdef GET_INSTRMAP_INFO 26008#undef GET_INSTRMAP_INFO 26009namespace llvm { 26010 26011namespace Mips { 26012 26013enum Arch { 26014 Arch_dsp, 26015 Arch_mmdsp, 26016 Arch_mipsr6, 26017 Arch_micromipsr6, 26018 Arch_se, 26019 Arch_micromips 26020}; 26021 26022// Dsp2MicroMips 26023LLVM_READONLY 26024int Dsp2MicroMips(uint16_t Opcode, enum Arch inArch) { 26025static const uint16_t Dsp2MicroMipsTable[][3] = { 26026 { Mips::ABSQ_S_PH, Mips::ABSQ_S_PH, Mips::ABSQ_S_PH_MM }, 26027 { Mips::ABSQ_S_QB, Mips::ABSQ_S_QB, Mips::ABSQ_S_QB_MMR2 }, 26028 { Mips::ABSQ_S_W, Mips::ABSQ_S_W, Mips::ABSQ_S_W_MM }, 26029 { Mips::ADDQH_PH, Mips::ADDQH_PH, Mips::ADDQH_PH_MMR2 }, 26030 { Mips::ADDQH_R_PH, Mips::ADDQH_R_PH, Mips::ADDQH_R_PH_MMR2 }, 26031 { Mips::ADDQH_R_W, Mips::ADDQH_R_W, Mips::ADDQH_R_W_MMR2 }, 26032 { Mips::ADDQH_W, Mips::ADDQH_W, Mips::ADDQH_W_MMR2 }, 26033 { Mips::ADDQ_PH, Mips::ADDQ_PH, Mips::ADDQ_PH_MM }, 26034 { Mips::ADDQ_S_PH, Mips::ADDQ_S_PH, Mips::ADDQ_S_PH_MM }, 26035 { Mips::ADDQ_S_W, Mips::ADDQ_S_W, Mips::ADDQ_S_W_MM }, 26036 { Mips::ADDSC, Mips::ADDSC, Mips::ADDSC_MM }, 26037 { Mips::ADDUH_QB, Mips::ADDUH_QB, Mips::ADDUH_QB_MMR2 }, 26038 { Mips::ADDUH_R_QB, Mips::ADDUH_R_QB, Mips::ADDUH_R_QB_MMR2 }, 26039 { Mips::ADDU_PH, Mips::ADDU_PH, Mips::ADDU_PH_MMR2 }, 26040 { Mips::ADDU_QB, Mips::ADDU_QB, Mips::ADDU_QB_MM }, 26041 { Mips::ADDU_S_PH, Mips::ADDU_S_PH, Mips::ADDU_S_PH_MMR2 }, 26042 { Mips::ADDU_S_QB, Mips::ADDU_S_QB, Mips::ADDU_S_QB_MM }, 26043 { Mips::ADDWC, Mips::ADDWC, Mips::ADDWC_MM }, 26044 { Mips::APPEND, Mips::APPEND, Mips::APPEND_MMR2 }, 26045 { Mips::BALIGN, Mips::BALIGN, Mips::BALIGN_MMR2 }, 26046 { Mips::BITREV, Mips::BITREV, Mips::BITREV_MM }, 26047 { Mips::BPOSGE32, Mips::BPOSGE32, Mips::BPOSGE32_MM }, 26048 { Mips::CMPGDU_EQ_QB, Mips::CMPGDU_EQ_QB, Mips::CMPGDU_EQ_QB_MMR2 }, 26049 { Mips::CMPGDU_LE_QB, Mips::CMPGDU_LE_QB, Mips::CMPGDU_LE_QB_MMR2 }, 26050 { Mips::CMPGDU_LT_QB, Mips::CMPGDU_LT_QB, Mips::CMPGDU_LT_QB_MMR2 }, 26051 { Mips::CMPGU_EQ_QB, Mips::CMPGU_EQ_QB, Mips::CMPGU_EQ_QB_MM }, 26052 { Mips::CMPGU_LE_QB, Mips::CMPGU_LE_QB, Mips::CMPGU_LE_QB_MM }, 26053 { Mips::CMPGU_LT_QB, Mips::CMPGU_LT_QB, Mips::CMPGU_LT_QB_MM }, 26054 { Mips::CMPU_EQ_QB, Mips::CMPU_EQ_QB, Mips::CMPU_EQ_QB_MM }, 26055 { Mips::CMPU_LE_QB, Mips::CMPU_LE_QB, Mips::CMPU_LE_QB_MM }, 26056 { Mips::CMPU_LT_QB, Mips::CMPU_LT_QB, Mips::CMPU_LT_QB_MM }, 26057 { Mips::CMP_EQ_PH, Mips::CMP_EQ_PH, Mips::CMP_EQ_PH_MM }, 26058 { Mips::CMP_LE_PH, Mips::CMP_LE_PH, Mips::CMP_LE_PH_MM }, 26059 { Mips::CMP_LT_PH, Mips::CMP_LT_PH, Mips::CMP_LT_PH_MM }, 26060 { Mips::DPAQX_SA_W_PH, Mips::DPAQX_SA_W_PH, Mips::DPAQX_SA_W_PH_MMR2 }, 26061 { Mips::DPAQX_S_W_PH, Mips::DPAQX_S_W_PH, Mips::DPAQX_S_W_PH_MMR2 }, 26062 { Mips::DPAQ_SA_L_W, Mips::DPAQ_SA_L_W, Mips::DPAQ_SA_L_W_MM }, 26063 { Mips::DPAQ_S_W_PH, Mips::DPAQ_S_W_PH, Mips::DPAQ_S_W_PH_MM }, 26064 { Mips::DPAU_H_QBL, Mips::DPAU_H_QBL, Mips::DPAU_H_QBL_MM }, 26065 { Mips::DPAU_H_QBR, Mips::DPAU_H_QBR, Mips::DPAU_H_QBR_MM }, 26066 { Mips::DPAX_W_PH, Mips::DPAX_W_PH, Mips::DPAX_W_PH_MMR2 }, 26067 { Mips::DPA_W_PH, Mips::DPA_W_PH, Mips::DPA_W_PH_MMR2 }, 26068 { Mips::DPSQX_SA_W_PH, Mips::DPSQX_SA_W_PH, Mips::DPSQX_SA_W_PH_MMR2 }, 26069 { Mips::DPSQX_S_W_PH, Mips::DPSQX_S_W_PH, Mips::DPSQX_S_W_PH_MMR2 }, 26070 { Mips::DPSQ_SA_L_W, Mips::DPSQ_SA_L_W, Mips::DPSQ_SA_L_W_MM }, 26071 { Mips::DPSQ_S_W_PH, Mips::DPSQ_S_W_PH, Mips::DPSQ_S_W_PH_MM }, 26072 { Mips::DPSU_H_QBL, Mips::DPSU_H_QBL, Mips::DPSU_H_QBL_MM }, 26073 { Mips::DPSU_H_QBR, Mips::DPSU_H_QBR, Mips::DPSU_H_QBR_MM }, 26074 { Mips::DPSX_W_PH, Mips::DPSX_W_PH, Mips::DPSX_W_PH_MMR2 }, 26075 { Mips::DPS_W_PH, Mips::DPS_W_PH, Mips::DPS_W_PH_MMR2 }, 26076 { Mips::EXTP, Mips::EXTP, Mips::EXTP_MM }, 26077 { Mips::EXTPDP, Mips::EXTPDP, Mips::EXTPDP_MM }, 26078 { Mips::EXTPDPV, Mips::EXTPDPV, Mips::EXTPDPV_MM }, 26079 { Mips::EXTPV, Mips::EXTPV, Mips::EXTPV_MM }, 26080 { Mips::EXTRV_RS_W, Mips::EXTRV_RS_W, Mips::EXTRV_RS_W_MM }, 26081 { Mips::EXTRV_R_W, Mips::EXTRV_R_W, Mips::EXTRV_R_W_MM }, 26082 { Mips::EXTRV_S_H, Mips::EXTRV_S_H, Mips::EXTRV_S_H_MM }, 26083 { Mips::EXTRV_W, Mips::EXTRV_W, Mips::EXTRV_W_MM }, 26084 { Mips::EXTR_RS_W, Mips::EXTR_RS_W, Mips::EXTR_RS_W_MM }, 26085 { Mips::EXTR_R_W, Mips::EXTR_R_W, Mips::EXTR_R_W_MM }, 26086 { Mips::EXTR_S_H, Mips::EXTR_S_H, Mips::EXTR_S_H_MM }, 26087 { Mips::EXTR_W, Mips::EXTR_W, Mips::EXTR_W_MM }, 26088 { Mips::INSV, Mips::INSV, Mips::INSV_MM }, 26089 { Mips::LBUX, Mips::LBUX, Mips::LBUX_MM }, 26090 { Mips::LHX, Mips::LHX, Mips::LHX_MM }, 26091 { Mips::LWDSP, Mips::LWDSP, Mips::LWDSP_MM }, 26092 { Mips::LWX, Mips::LWX, Mips::LWX_MM }, 26093 { Mips::MADDU_DSP, Mips::MADDU_DSP, Mips::MADDU_DSP_MM }, 26094 { Mips::MADD_DSP, Mips::MADD_DSP, Mips::MADD_DSP_MM }, 26095 { Mips::MAQ_SA_W_PHL, Mips::MAQ_SA_W_PHL, Mips::MAQ_SA_W_PHL_MM }, 26096 { Mips::MAQ_SA_W_PHR, Mips::MAQ_SA_W_PHR, Mips::MAQ_SA_W_PHR_MM }, 26097 { Mips::MAQ_S_W_PHL, Mips::MAQ_S_W_PHL, Mips::MAQ_S_W_PHL_MM }, 26098 { Mips::MAQ_S_W_PHR, Mips::MAQ_S_W_PHR, Mips::MAQ_S_W_PHR_MM }, 26099 { Mips::MFHI_DSP, Mips::MFHI_DSP, Mips::MFHI_DSP_MM }, 26100 { Mips::MFLO_DSP, Mips::MFLO_DSP, Mips::MFLO_DSP_MM }, 26101 { Mips::MODSUB, Mips::MODSUB, Mips::MODSUB_MM }, 26102 { Mips::MSUBU_DSP, Mips::MSUBU_DSP, Mips::MSUBU_DSP_MM }, 26103 { Mips::MSUB_DSP, Mips::MSUB_DSP, Mips::MSUB_DSP_MM }, 26104 { Mips::MTHI_DSP, Mips::MTHI_DSP, Mips::MTHI_DSP_MM }, 26105 { Mips::MTHLIP, Mips::MTHLIP, Mips::MTHLIP_MM }, 26106 { Mips::MTLO_DSP, Mips::MTLO_DSP, Mips::MTLO_DSP_MM }, 26107 { Mips::MULEQ_S_W_PHL, Mips::MULEQ_S_W_PHL, Mips::MULEQ_S_W_PHL_MM }, 26108 { Mips::MULEQ_S_W_PHR, Mips::MULEQ_S_W_PHR, Mips::MULEQ_S_W_PHR_MM }, 26109 { Mips::MULEU_S_PH_QBL, Mips::MULEU_S_PH_QBL, Mips::MULEU_S_PH_QBL_MM }, 26110 { Mips::MULEU_S_PH_QBR, Mips::MULEU_S_PH_QBR, Mips::MULEU_S_PH_QBR_MM }, 26111 { Mips::MULQ_RS_PH, Mips::MULQ_RS_PH, Mips::MULQ_RS_PH_MM }, 26112 { Mips::MULQ_RS_W, Mips::MULQ_RS_W, Mips::MULQ_RS_W_MMR2 }, 26113 { Mips::MULQ_S_PH, Mips::MULQ_S_PH, Mips::MULQ_S_PH_MMR2 }, 26114 { Mips::MULQ_S_W, Mips::MULQ_S_W, Mips::MULQ_S_W_MMR2 }, 26115 { Mips::MULSAQ_S_W_PH, Mips::MULSAQ_S_W_PH, Mips::MULSAQ_S_W_PH_MM }, 26116 { Mips::MULSA_W_PH, Mips::MULSA_W_PH, Mips::MULSA_W_PH_MMR2 }, 26117 { Mips::MULTU_DSP, Mips::MULTU_DSP, Mips::MULTU_DSP_MM }, 26118 { Mips::MULT_DSP, Mips::MULT_DSP, Mips::MULT_DSP_MM }, 26119 { Mips::MUL_PH, Mips::MUL_PH, Mips::MUL_PH_MMR2 }, 26120 { Mips::MUL_S_PH, Mips::MUL_S_PH, Mips::MUL_S_PH_MMR2 }, 26121 { Mips::PACKRL_PH, Mips::PACKRL_PH, Mips::PACKRL_PH_MM }, 26122 { Mips::PICK_PH, Mips::PICK_PH, Mips::PICK_PH_MM }, 26123 { Mips::PICK_QB, Mips::PICK_QB, Mips::PICK_QB_MM }, 26124 { Mips::PRECEQU_PH_QBL, Mips::PRECEQU_PH_QBL, Mips::PRECEQU_PH_QBL_MM }, 26125 { Mips::PRECEQU_PH_QBLA, Mips::PRECEQU_PH_QBLA, Mips::PRECEQU_PH_QBLA_MM }, 26126 { Mips::PRECEQU_PH_QBR, Mips::PRECEQU_PH_QBR, Mips::PRECEQU_PH_QBR_MM }, 26127 { Mips::PRECEQU_PH_QBRA, Mips::PRECEQU_PH_QBRA, Mips::PRECEQU_PH_QBRA_MM }, 26128 { Mips::PRECEQ_W_PHL, Mips::PRECEQ_W_PHL, Mips::PRECEQ_W_PHL_MM }, 26129 { Mips::PRECEQ_W_PHR, Mips::PRECEQ_W_PHR, Mips::PRECEQ_W_PHR_MM }, 26130 { Mips::PRECEU_PH_QBL, Mips::PRECEU_PH_QBL, Mips::PRECEU_PH_QBL_MM }, 26131 { Mips::PRECEU_PH_QBLA, Mips::PRECEU_PH_QBLA, Mips::PRECEU_PH_QBLA_MM }, 26132 { Mips::PRECEU_PH_QBR, Mips::PRECEU_PH_QBR, Mips::PRECEU_PH_QBR_MM }, 26133 { Mips::PRECEU_PH_QBRA, Mips::PRECEU_PH_QBRA, Mips::PRECEU_PH_QBRA_MM }, 26134 { Mips::PRECRQU_S_QB_PH, Mips::PRECRQU_S_QB_PH, Mips::PRECRQU_S_QB_PH_MM }, 26135 { Mips::PRECRQ_PH_W, Mips::PRECRQ_PH_W, Mips::PRECRQ_PH_W_MM }, 26136 { Mips::PRECRQ_QB_PH, Mips::PRECRQ_QB_PH, Mips::PRECRQ_QB_PH_MM }, 26137 { Mips::PRECRQ_RS_PH_W, Mips::PRECRQ_RS_PH_W, Mips::PRECRQ_RS_PH_W_MM }, 26138 { Mips::PRECR_QB_PH, Mips::PRECR_QB_PH, Mips::PRECR_QB_PH_MMR2 }, 26139 { Mips::PRECR_SRA_PH_W, Mips::PRECR_SRA_PH_W, Mips::PRECR_SRA_PH_W_MMR2 }, 26140 { Mips::PRECR_SRA_R_PH_W, Mips::PRECR_SRA_R_PH_W, Mips::PRECR_SRA_R_PH_W_MMR2 }, 26141 { Mips::PREPEND, Mips::PREPEND, Mips::PREPEND_MMR2 }, 26142 { Mips::RADDU_W_QB, Mips::RADDU_W_QB, Mips::RADDU_W_QB_MM }, 26143 { Mips::RDDSP, Mips::RDDSP, Mips::RDDSP_MM }, 26144 { Mips::REPLV_PH, Mips::REPLV_PH, Mips::REPLV_PH_MM }, 26145 { Mips::REPLV_QB, Mips::REPLV_QB, Mips::REPLV_QB_MM }, 26146 { Mips::REPL_PH, Mips::REPL_PH, Mips::REPL_PH_MM }, 26147 { Mips::REPL_QB, Mips::REPL_QB, Mips::REPL_QB_MM }, 26148 { Mips::SHILO, Mips::SHILO, Mips::SHILO_MM }, 26149 { Mips::SHILOV, Mips::SHILOV, Mips::SHILOV_MM }, 26150 { Mips::SHLLV_PH, Mips::SHLLV_PH, Mips::SHLLV_PH_MM }, 26151 { Mips::SHLLV_QB, Mips::SHLLV_QB, Mips::SHLLV_QB_MM }, 26152 { Mips::SHLLV_S_PH, Mips::SHLLV_S_PH, Mips::SHLLV_S_PH_MM }, 26153 { Mips::SHLLV_S_W, Mips::SHLLV_S_W, Mips::SHLLV_S_W_MM }, 26154 { Mips::SHLL_PH, Mips::SHLL_PH, Mips::SHLL_PH_MM }, 26155 { Mips::SHLL_QB, Mips::SHLL_QB, Mips::SHLL_QB_MM }, 26156 { Mips::SHLL_S_PH, Mips::SHLL_S_PH, Mips::SHLL_S_PH_MM }, 26157 { Mips::SHLL_S_W, Mips::SHLL_S_W, Mips::SHLL_S_W_MM }, 26158 { Mips::SHRAV_PH, Mips::SHRAV_PH, Mips::SHRAV_PH_MM }, 26159 { Mips::SHRAV_QB, Mips::SHRAV_QB, Mips::SHRAV_QB_MMR2 }, 26160 { Mips::SHRAV_R_PH, Mips::SHRAV_R_PH, Mips::SHRAV_R_PH_MM }, 26161 { Mips::SHRAV_R_QB, Mips::SHRAV_R_QB, Mips::SHRAV_R_QB_MMR2 }, 26162 { Mips::SHRAV_R_W, Mips::SHRAV_R_W, Mips::SHRAV_R_W_MM }, 26163 { Mips::SHRA_PH, Mips::SHRA_PH, Mips::SHRA_PH_MM }, 26164 { Mips::SHRA_QB, Mips::SHRA_QB, Mips::SHRA_QB_MMR2 }, 26165 { Mips::SHRA_R_PH, Mips::SHRA_R_PH, Mips::SHRA_R_PH_MM }, 26166 { Mips::SHRA_R_QB, Mips::SHRA_R_QB, Mips::SHRA_R_QB_MMR2 }, 26167 { Mips::SHRA_R_W, Mips::SHRA_R_W, Mips::SHRA_R_W_MM }, 26168 { Mips::SHRLV_PH, Mips::SHRLV_PH, Mips::SHRLV_PH_MMR2 }, 26169 { Mips::SHRLV_QB, Mips::SHRLV_QB, Mips::SHRLV_QB_MM }, 26170 { Mips::SHRL_PH, Mips::SHRL_PH, Mips::SHRL_PH_MMR2 }, 26171 { Mips::SHRL_QB, Mips::SHRL_QB, Mips::SHRL_QB_MM }, 26172 { Mips::SUBQH_PH, Mips::SUBQH_PH, Mips::SUBQH_PH_MMR2 }, 26173 { Mips::SUBQH_R_PH, Mips::SUBQH_R_PH, Mips::SUBQH_R_PH_MMR2 }, 26174 { Mips::SUBQH_R_W, Mips::SUBQH_R_W, Mips::SUBQH_R_W_MMR2 }, 26175 { Mips::SUBQH_W, Mips::SUBQH_W, Mips::SUBQH_W_MMR2 }, 26176 { Mips::SUBQ_PH, Mips::SUBQ_PH, Mips::SUBQ_PH_MM }, 26177 { Mips::SUBQ_S_PH, Mips::SUBQ_S_PH, Mips::SUBQ_S_PH_MM }, 26178 { Mips::SUBQ_S_W, Mips::SUBQ_S_W, Mips::SUBQ_S_W_MM }, 26179 { Mips::SUBUH_QB, Mips::SUBUH_QB, Mips::SUBUH_QB_MMR2 }, 26180 { Mips::SUBUH_R_QB, Mips::SUBUH_R_QB, Mips::SUBUH_R_QB_MMR2 }, 26181 { Mips::SUBU_PH, Mips::SUBU_PH, Mips::SUBU_PH_MMR2 }, 26182 { Mips::SUBU_QB, Mips::SUBU_QB, Mips::SUBU_QB_MM }, 26183 { Mips::SUBU_S_PH, Mips::SUBU_S_PH, Mips::SUBU_S_PH_MMR2 }, 26184 { Mips::SUBU_S_QB, Mips::SUBU_S_QB, Mips::SUBU_S_QB_MM }, 26185 { Mips::SWDSP, Mips::SWDSP, Mips::SWDSP_MM }, 26186}; // End of Dsp2MicroMipsTable 26187 26188 unsigned mid; 26189 unsigned start = 0; 26190 unsigned end = 160; 26191 while (start < end) { 26192 mid = start + (end - start) / 2; 26193 if (Opcode == Dsp2MicroMipsTable[mid][0]) { 26194 break; 26195 } 26196 if (Opcode < Dsp2MicroMipsTable[mid][0]) 26197 end = mid; 26198 else 26199 start = mid + 1; 26200 } 26201 if (start == end) 26202 return -1; // Instruction doesn't exist in this table. 26203 26204 if (inArch == Arch_dsp) 26205 return Dsp2MicroMipsTable[mid][1]; 26206 if (inArch == Arch_mmdsp) 26207 return Dsp2MicroMipsTable[mid][2]; 26208 return -1;} 26209 26210// MipsR62MicroMipsR6 26211LLVM_READONLY 26212int MipsR62MicroMipsR6(uint16_t Opcode, enum Arch inArch) { 26213static const uint16_t MipsR62MicroMipsR6Table[][3] = { 26214 { Mips::ADDIUPC, Mips::ADDIUPC, Mips::ADDIUPC_MMR6 }, 26215 { Mips::ALIGN, Mips::ALIGN, Mips::ALIGN_MMR6 }, 26216 { Mips::ALUIPC, Mips::ALUIPC, Mips::ALUIPC_MMR6 }, 26217 { Mips::AUI, Mips::AUI, Mips::AUI_MMR6 }, 26218 { Mips::AUIPC, Mips::AUIPC, Mips::AUIPC_MMR6 }, 26219 { Mips::BALC, Mips::BALC, Mips::BALC_MMR6 }, 26220 { Mips::BC, Mips::BC, Mips::BC_MMR6 }, 26221 { Mips::BEQC, Mips::BEQC, Mips::BEQC_MMR6 }, 26222 { Mips::BEQZALC, Mips::BEQZALC, Mips::BEQZALC_MMR6 }, 26223 { Mips::BEQZC, Mips::BEQZC, Mips::BEQZC_MMR6 }, 26224 { Mips::BGEC, Mips::BGEC, Mips::BGEC_MMR6 }, 26225 { Mips::BGEUC, Mips::BGEUC, Mips::BGEUC_MMR6 }, 26226 { Mips::BGEZALC, Mips::BGEZALC, Mips::BGEZALC_MMR6 }, 26227 { Mips::BGEZC, Mips::BGEZC, Mips::BGEZC_MMR6 }, 26228 { Mips::BGTZALC, Mips::BGTZALC, Mips::BGTZALC_MMR6 }, 26229 { Mips::BGTZC, Mips::BGTZC, Mips::BGTZC_MMR6 }, 26230 { Mips::BITSWAP, Mips::BITSWAP, Mips::BITSWAP_MMR6 }, 26231 { Mips::BLEZALC, Mips::BLEZALC, Mips::BLEZALC_MMR6 }, 26232 { Mips::BLEZC, Mips::BLEZC, Mips::BLEZC_MMR6 }, 26233 { Mips::BLTC, Mips::BLTC, Mips::BLTC_MMR6 }, 26234 { Mips::BLTUC, Mips::BLTUC, Mips::BLTUC_MMR6 }, 26235 { Mips::BLTZALC, Mips::BLTZALC, Mips::BLTZALC_MMR6 }, 26236 { Mips::BLTZC, Mips::BLTZC, Mips::BLTZC_MMR6 }, 26237 { Mips::BNEC, Mips::BNEC, Mips::BNEC_MMR6 }, 26238 { Mips::BNEZALC, Mips::BNEZALC, Mips::BNEZALC_MMR6 }, 26239 { Mips::BNEZC, Mips::BNEZC, Mips::BNEZC_MMR6 }, 26240 { Mips::BNVC, Mips::BNVC, Mips::BNVC_MMR6 }, 26241 { Mips::BOVC, Mips::BOVC, Mips::BOVC_MMR6 }, 26242 { Mips::CACHE_R6, Mips::CACHE_R6, Mips::CACHE_MMR6 }, 26243 { Mips::CLO_R6, Mips::CLO_R6, Mips::CLO_MMR6 }, 26244 { Mips::CLZ_R6, Mips::CLZ_R6, Mips::CLZ_MMR6 }, 26245 { Mips::CMP_EQ_D, Mips::CMP_EQ_D, Mips::CMP_EQ_D_MMR6 }, 26246 { Mips::CMP_EQ_S, Mips::CMP_EQ_S, Mips::CMP_EQ_S_MMR6 }, 26247 { Mips::CMP_F_D, Mips::CMP_F_D, Mips::CMP_AF_D_MMR6 }, 26248 { Mips::CMP_F_S, Mips::CMP_F_S, Mips::CMP_AF_S_MMR6 }, 26249 { Mips::CMP_LE_D, Mips::CMP_LE_D, Mips::CMP_LE_D_MMR6 }, 26250 { Mips::CMP_LE_S, Mips::CMP_LE_S, Mips::CMP_LE_S_MMR6 }, 26251 { Mips::CMP_LT_D, Mips::CMP_LT_D, Mips::CMP_LT_D_MMR6 }, 26252 { Mips::CMP_LT_S, Mips::CMP_LT_S, Mips::CMP_LT_S_MMR6 }, 26253 { Mips::CMP_SAF_D, Mips::CMP_SAF_D, Mips::CMP_SAF_D_MMR6 }, 26254 { Mips::CMP_SAF_S, Mips::CMP_SAF_S, Mips::CMP_SAF_S_MMR6 }, 26255 { Mips::CMP_SEQ_D, Mips::CMP_SEQ_D, Mips::CMP_SEQ_D_MMR6 }, 26256 { Mips::CMP_SEQ_S, Mips::CMP_SEQ_S, Mips::CMP_SEQ_S_MMR6 }, 26257 { Mips::CMP_SLE_D, Mips::CMP_SLE_D, Mips::CMP_SLE_D_MMR6 }, 26258 { Mips::CMP_SLE_S, Mips::CMP_SLE_S, Mips::CMP_SLE_S_MMR6 }, 26259 { Mips::CMP_SLT_D, Mips::CMP_SLT_D, Mips::CMP_SLT_D_MMR6 }, 26260 { Mips::CMP_SLT_S, Mips::CMP_SLT_S, Mips::CMP_SLT_S_MMR6 }, 26261 { Mips::CMP_SUEQ_D, Mips::CMP_SUEQ_D, Mips::CMP_SUEQ_D_MMR6 }, 26262 { Mips::CMP_SUEQ_S, Mips::CMP_SUEQ_S, Mips::CMP_SUEQ_S_MMR6 }, 26263 { Mips::CMP_SULE_D, Mips::CMP_SULE_D, Mips::CMP_SULE_D_MMR6 }, 26264 { Mips::CMP_SULE_S, Mips::CMP_SULE_S, Mips::CMP_SULE_S_MMR6 }, 26265 { Mips::CMP_SULT_D, Mips::CMP_SULT_D, Mips::CMP_SULT_D_MMR6 }, 26266 { Mips::CMP_SULT_S, Mips::CMP_SULT_S, Mips::CMP_SULT_S_MMR6 }, 26267 { Mips::CMP_SUN_D, Mips::CMP_SUN_D, Mips::CMP_SUN_D_MMR6 }, 26268 { Mips::CMP_SUN_S, Mips::CMP_SUN_S, Mips::CMP_SUN_S_MMR6 }, 26269 { Mips::CMP_UEQ_D, Mips::CMP_UEQ_D, Mips::CMP_UEQ_D_MMR6 }, 26270 { Mips::CMP_UEQ_S, Mips::CMP_UEQ_S, Mips::CMP_UEQ_S_MMR6 }, 26271 { Mips::CMP_ULE_D, Mips::CMP_ULE_D, Mips::CMP_ULE_D_MMR6 }, 26272 { Mips::CMP_ULE_S, Mips::CMP_ULE_S, Mips::CMP_ULE_S_MMR6 }, 26273 { Mips::CMP_ULT_D, Mips::CMP_ULT_D, Mips::CMP_ULT_D_MMR6 }, 26274 { Mips::CMP_ULT_S, Mips::CMP_ULT_S, Mips::CMP_ULT_S_MMR6 }, 26275 { Mips::CMP_UN_D, Mips::CMP_UN_D, Mips::CMP_UN_D_MMR6 }, 26276 { Mips::CMP_UN_S, Mips::CMP_UN_S, Mips::CMP_UN_S_MMR6 }, 26277 { Mips::CRC32B, Mips::CRC32B, (uint16_t)-1U }, 26278 { Mips::CRC32CB, Mips::CRC32CB, (uint16_t)-1U }, 26279 { Mips::CRC32CD, Mips::CRC32CD, (uint16_t)-1U }, 26280 { Mips::CRC32CH, Mips::CRC32CH, (uint16_t)-1U }, 26281 { Mips::CRC32CW, Mips::CRC32CW, (uint16_t)-1U }, 26282 { Mips::CRC32D, Mips::CRC32D, (uint16_t)-1U }, 26283 { Mips::CRC32H, Mips::CRC32H, (uint16_t)-1U }, 26284 { Mips::CRC32W, Mips::CRC32W, (uint16_t)-1U }, 26285 { Mips::DIV, Mips::DIV, Mips::DIV_MMR6 }, 26286 { Mips::DIVU, Mips::DIVU, Mips::DIVU_MMR6 }, 26287 { Mips::DVP, Mips::DVP, Mips::DVP_MMR6 }, 26288 { Mips::EVP, Mips::EVP, Mips::EVP_MMR6 }, 26289 { Mips::GINVI, Mips::GINVI, Mips::GINVI_MMR6 }, 26290 { Mips::GINVT, Mips::GINVT, Mips::GINVT_MMR6 }, 26291 { Mips::JIALC, Mips::JIALC, Mips::JIALC_MMR6 }, 26292 { Mips::JIC, Mips::JIC, Mips::JIC_MMR6 }, 26293 { Mips::LSA_R6, Mips::LSA_R6, Mips::LSA_MMR6 }, 26294 { Mips::LWPC, Mips::LWPC, Mips::LWPC_MMR6 }, 26295 { Mips::MOD, Mips::MOD, Mips::MOD_MMR6 }, 26296 { Mips::MODU, Mips::MODU, Mips::MODU_MMR6 }, 26297 { Mips::MUH, Mips::MUH, Mips::MUH_MMR6 }, 26298 { Mips::MUHU, Mips::MUHU, Mips::MUHU_MMR6 }, 26299 { Mips::MULU, Mips::MULU, Mips::MULU_MMR6 }, 26300 { Mips::MUL_R6, Mips::MUL_R6, Mips::MUL_MMR6 }, 26301 { Mips::PREF_R6, Mips::PREF_R6, Mips::PREF_MMR6 }, 26302 { Mips::SELEQZ, Mips::SELEQZ, Mips::SELEQZ_MMR6 }, 26303 { Mips::SELEQZ_D, Mips::SELEQZ_D, Mips::SELEQZ_D_MMR6 }, 26304 { Mips::SELEQZ_S, Mips::SELEQZ_S, Mips::SELEQZ_S_MMR6 }, 26305 { Mips::SELNEZ, Mips::SELNEZ, Mips::SELNEZ_MMR6 }, 26306 { Mips::SELNEZ_D, Mips::SELNEZ_D, Mips::SELNEZ_D_MMR6 }, 26307 { Mips::SELNEZ_S, Mips::SELNEZ_S, Mips::SELNEZ_S_MMR6 }, 26308 { Mips::SEL_D, Mips::SEL_D, Mips::SEL_D_MMR6 }, 26309 { Mips::SEL_S, Mips::SEL_S, Mips::SEL_S_MMR6 }, 26310}; // End of MipsR62MicroMipsR6Table 26311 26312 unsigned mid; 26313 unsigned start = 0; 26314 unsigned end = 96; 26315 while (start < end) { 26316 mid = start + (end - start) / 2; 26317 if (Opcode == MipsR62MicroMipsR6Table[mid][0]) { 26318 break; 26319 } 26320 if (Opcode < MipsR62MicroMipsR6Table[mid][0]) 26321 end = mid; 26322 else 26323 start = mid + 1; 26324 } 26325 if (start == end) 26326 return -1; // Instruction doesn't exist in this table. 26327 26328 if (inArch == Arch_mipsr6) 26329 return MipsR62MicroMipsR6Table[mid][1]; 26330 if (inArch == Arch_micromipsr6) 26331 return MipsR62MicroMipsR6Table[mid][2]; 26332 return -1;} 26333 26334// Std2MicroMips 26335LLVM_READONLY 26336int Std2MicroMips(uint16_t Opcode, enum Arch inArch) { 26337static const uint16_t Std2MicroMipsTable[][3] = { 26338 { Mips::ADD, Mips::ADD, Mips::ADD_MM }, 26339 { Mips::ADDi, Mips::ADDi, Mips::ADDi_MM }, 26340 { Mips::ADDiu, Mips::ADDiu, Mips::ADDiu_MM }, 26341 { Mips::ADDu, Mips::ADDu, Mips::ADDu_MM }, 26342 { Mips::AND, Mips::AND, Mips::AND_MM }, 26343 { Mips::ANDi, Mips::ANDi, Mips::ANDi_MM }, 26344 { Mips::BC1F, Mips::BC1F, Mips::BC1F_MM }, 26345 { Mips::BC1FL, Mips::BC1FL, (uint16_t)-1U }, 26346 { Mips::BC1T, Mips::BC1T, Mips::BC1T_MM }, 26347 { Mips::BC1TL, Mips::BC1TL, (uint16_t)-1U }, 26348 { Mips::BEQ, Mips::BEQ, Mips::BEQ_MM }, 26349 { Mips::BEQL, Mips::BEQL, (uint16_t)-1U }, 26350 { Mips::BGEZ, Mips::BGEZ, Mips::BGEZ_MM }, 26351 { Mips::BGEZAL, Mips::BGEZAL, Mips::BGEZAL_MM }, 26352 { Mips::BGEZALL, Mips::BGEZALL, (uint16_t)-1U }, 26353 { Mips::BGEZL, Mips::BGEZL, (uint16_t)-1U }, 26354 { Mips::BGTZ, Mips::BGTZ, Mips::BGTZ_MM }, 26355 { Mips::BGTZL, Mips::BGTZL, (uint16_t)-1U }, 26356 { Mips::BLEZ, Mips::BLEZ, Mips::BLEZ_MM }, 26357 { Mips::BLEZL, Mips::BLEZL, (uint16_t)-1U }, 26358 { Mips::BLTZ, Mips::BLTZ, Mips::BLTZ_MM }, 26359 { Mips::BLTZAL, Mips::BLTZAL, Mips::BLTZAL_MM }, 26360 { Mips::BLTZALL, Mips::BLTZALL, (uint16_t)-1U }, 26361 { Mips::BLTZL, Mips::BLTZL, (uint16_t)-1U }, 26362 { Mips::BNE, Mips::BNE, Mips::BNE_MM }, 26363 { Mips::BNEL, Mips::BNEL, (uint16_t)-1U }, 26364 { Mips::BREAK, Mips::BREAK, Mips::BREAK_MM }, 26365 { Mips::CACHE, Mips::CACHE, Mips::CACHE_MM }, 26366 { Mips::CACHEE, Mips::CACHEE, Mips::CACHEE_MM }, 26367 { Mips::CEIL_W_D32, Mips::CEIL_W_D32, Mips::CEIL_W_MM }, 26368 { Mips::CEIL_W_S, Mips::CEIL_W_S, Mips::CEIL_W_S_MM }, 26369 { Mips::CFC1, Mips::CFC1, Mips::CFC1_MM }, 26370 { Mips::CLO, Mips::CLO, Mips::CLO_MM }, 26371 { Mips::CLZ, Mips::CLZ, Mips::CLZ_MM }, 26372 { Mips::CTC1, Mips::CTC1, Mips::CTC1_MM }, 26373 { Mips::CVT_D32_S, Mips::CVT_D32_S, Mips::CVT_D32_S_MM }, 26374 { Mips::CVT_D32_W, Mips::CVT_D32_W, Mips::CVT_D32_W_MM }, 26375 { Mips::CVT_L_D64, Mips::CVT_L_D64, Mips::CVT_L_D64_MM }, 26376 { Mips::CVT_L_S, Mips::CVT_L_S, Mips::CVT_L_S_MM }, 26377 { Mips::CVT_S_D32, Mips::CVT_S_D32, Mips::CVT_S_D32_MM }, 26378 { Mips::CVT_S_W, Mips::CVT_S_W, Mips::CVT_S_W_MM }, 26379 { Mips::CVT_W_D32, Mips::CVT_W_D32, Mips::CVT_W_D32_MM }, 26380 { Mips::CVT_W_S, Mips::CVT_W_S, Mips::CVT_W_S_MM }, 26381 { Mips::C_EQ_D32, Mips::C_EQ_D32, Mips::C_EQ_D32_MM }, 26382 { Mips::C_EQ_D64, Mips::C_EQ_D64, Mips::C_EQ_D64_MM }, 26383 { Mips::C_EQ_S, Mips::C_EQ_S, Mips::C_EQ_S_MM }, 26384 { Mips::C_F_D32, Mips::C_F_D32, Mips::C_F_D32_MM }, 26385 { Mips::C_F_D64, Mips::C_F_D64, Mips::C_F_D64_MM }, 26386 { Mips::C_F_S, Mips::C_F_S, Mips::C_F_S_MM }, 26387 { Mips::C_LE_D32, Mips::C_LE_D32, Mips::C_LE_D32_MM }, 26388 { Mips::C_LE_D64, Mips::C_LE_D64, Mips::C_LE_D64_MM }, 26389 { Mips::C_LE_S, Mips::C_LE_S, Mips::C_LE_S_MM }, 26390 { Mips::C_LT_D32, Mips::C_LT_D32, Mips::C_LT_D32_MM }, 26391 { Mips::C_LT_D64, Mips::C_LT_D64, Mips::C_LT_D64_MM }, 26392 { Mips::C_LT_S, Mips::C_LT_S, Mips::C_LT_S_MM }, 26393 { Mips::C_NGE_D32, Mips::C_NGE_D32, Mips::C_NGE_D32_MM }, 26394 { Mips::C_NGE_D64, Mips::C_NGE_D64, Mips::C_NGE_D64_MM }, 26395 { Mips::C_NGE_S, Mips::C_NGE_S, Mips::C_NGE_S_MM }, 26396 { Mips::C_NGLE_D32, Mips::C_NGLE_D32, Mips::C_NGLE_D32_MM }, 26397 { Mips::C_NGLE_D64, Mips::C_NGLE_D64, Mips::C_NGLE_D64_MM }, 26398 { Mips::C_NGLE_S, Mips::C_NGLE_S, Mips::C_NGLE_S_MM }, 26399 { Mips::C_NGL_D32, Mips::C_NGL_D32, Mips::C_NGL_D32_MM }, 26400 { Mips::C_NGL_D64, Mips::C_NGL_D64, Mips::C_NGL_D64_MM }, 26401 { Mips::C_NGL_S, Mips::C_NGL_S, Mips::C_NGL_S_MM }, 26402 { Mips::C_NGT_D32, Mips::C_NGT_D32, Mips::C_NGT_D32_MM }, 26403 { Mips::C_NGT_D64, Mips::C_NGT_D64, Mips::C_NGT_D64_MM }, 26404 { Mips::C_NGT_S, Mips::C_NGT_S, Mips::C_NGT_S_MM }, 26405 { Mips::C_OLE_D32, Mips::C_OLE_D32, Mips::C_OLE_D32_MM }, 26406 { Mips::C_OLE_D64, Mips::C_OLE_D64, Mips::C_OLE_D64_MM }, 26407 { Mips::C_OLE_S, Mips::C_OLE_S, Mips::C_OLE_S_MM }, 26408 { Mips::C_OLT_D32, Mips::C_OLT_D32, Mips::C_OLT_D32_MM }, 26409 { Mips::C_OLT_D64, Mips::C_OLT_D64, Mips::C_OLT_D64_MM }, 26410 { Mips::C_OLT_S, Mips::C_OLT_S, Mips::C_OLT_S_MM }, 26411 { Mips::C_SEQ_D32, Mips::C_SEQ_D32, Mips::C_SEQ_D32_MM }, 26412 { Mips::C_SEQ_D64, Mips::C_SEQ_D64, Mips::C_SEQ_D64_MM }, 26413 { Mips::C_SEQ_S, Mips::C_SEQ_S, Mips::C_SEQ_S_MM }, 26414 { Mips::C_SF_D32, Mips::C_SF_D32, Mips::C_SF_D32_MM }, 26415 { Mips::C_SF_D64, Mips::C_SF_D64, Mips::C_SF_D64_MM }, 26416 { Mips::C_SF_S, Mips::C_SF_S, Mips::C_SF_S_MM }, 26417 { Mips::C_UEQ_D32, Mips::C_UEQ_D32, Mips::C_UEQ_D32_MM }, 26418 { Mips::C_UEQ_D64, Mips::C_UEQ_D64, Mips::C_UEQ_D64_MM }, 26419 { Mips::C_UEQ_S, Mips::C_UEQ_S, Mips::C_UEQ_S_MM }, 26420 { Mips::C_ULE_D32, Mips::C_ULE_D32, Mips::C_ULE_D32_MM }, 26421 { Mips::C_ULE_D64, Mips::C_ULE_D64, Mips::C_ULE_D64_MM }, 26422 { Mips::C_ULE_S, Mips::C_ULE_S, Mips::C_ULE_S_MM }, 26423 { Mips::C_ULT_D32, Mips::C_ULT_D32, Mips::C_ULT_D32_MM }, 26424 { Mips::C_ULT_D64, Mips::C_ULT_D64, Mips::C_ULT_D64_MM }, 26425 { Mips::C_ULT_S, Mips::C_ULT_S, Mips::C_ULT_S_MM }, 26426 { Mips::C_UN_D32, Mips::C_UN_D32, Mips::C_UN_D32_MM }, 26427 { Mips::C_UN_D64, Mips::C_UN_D64, Mips::C_UN_D64_MM }, 26428 { Mips::C_UN_S, Mips::C_UN_S, Mips::C_UN_S_MM }, 26429 { Mips::DERET, Mips::DERET, Mips::DERET_MM }, 26430 { Mips::DI, Mips::DI, Mips::DI_MM }, 26431 { Mips::EHB, Mips::EHB, Mips::EHB_MM }, 26432 { Mips::EI, Mips::EI, Mips::EI_MM }, 26433 { Mips::ERET, Mips::ERET, Mips::ERET_MM }, 26434 { Mips::ERETNC, Mips::ERETNC, (uint16_t)-1U }, 26435 { Mips::EXT, Mips::EXT, Mips::EXT_MM }, 26436 { Mips::FABS_D32, Mips::FABS_D32, Mips::FABS_D32_MM }, 26437 { Mips::FABS_S, Mips::FABS_S, Mips::FABS_S_MM }, 26438 { Mips::FADD_D32, Mips::FADD_D32, Mips::FADD_D32_MM }, 26439 { Mips::FADD_S, Mips::FADD_S, Mips::FADD_S_MM }, 26440 { Mips::FCMP_D32, Mips::FCMP_D32, Mips::FCMP_D32_MM }, 26441 { Mips::FCMP_S32, Mips::FCMP_S32, Mips::FCMP_S32_MM }, 26442 { Mips::FDIV_D32, Mips::FDIV_D32, Mips::FDIV_D32_MM }, 26443 { Mips::FDIV_S, Mips::FDIV_S, Mips::FDIV_S_MM }, 26444 { Mips::FLOOR_W_D32, Mips::FLOOR_W_D32, Mips::FLOOR_W_MM }, 26445 { Mips::FLOOR_W_S, Mips::FLOOR_W_S, Mips::FLOOR_W_S_MM }, 26446 { Mips::FMOV_D32, Mips::FMOV_D32, Mips::FMOV_D32_MM }, 26447 { Mips::FMOV_S, Mips::FMOV_S, Mips::FMOV_S_MM }, 26448 { Mips::FMUL_D32, Mips::FMUL_D32, Mips::FMUL_D32_MM }, 26449 { Mips::FMUL_S, Mips::FMUL_S, Mips::FMUL_S_MM }, 26450 { Mips::FNEG_D32, Mips::FNEG_D32, Mips::FNEG_D32_MM }, 26451 { Mips::FNEG_S, Mips::FNEG_S, Mips::FNEG_S_MM }, 26452 { Mips::FSQRT_D32, Mips::FSQRT_D32, Mips::FSQRT_D32_MM }, 26453 { Mips::FSQRT_S, Mips::FSQRT_S, Mips::FSQRT_S_MM }, 26454 { Mips::FSUB_D32, Mips::FSUB_D32, Mips::FSUB_D32_MM }, 26455 { Mips::FSUB_S, Mips::FSUB_S, Mips::FSUB_S_MM }, 26456 { Mips::HYPCALL, Mips::HYPCALL, Mips::HYPCALL_MM }, 26457 { Mips::INS, Mips::INS, Mips::INS_MM }, 26458 { Mips::J, Mips::J, Mips::J_MM }, 26459 { Mips::JAL, Mips::JAL, Mips::JAL_MM }, 26460 { Mips::JALX, Mips::JALX, Mips::JALX_MM }, 26461 { Mips::JR, Mips::JR, Mips::JR_MM }, 26462 { Mips::LB, Mips::LB, Mips::LB_MM }, 26463 { Mips::LBE, Mips::LBE, Mips::LBE_MM }, 26464 { Mips::LBu, Mips::LBu, Mips::LBu_MM }, 26465 { Mips::LBuE, Mips::LBuE, Mips::LBuE_MM }, 26466 { Mips::LDC1, Mips::LDC1, Mips::LDC1_MM_D32 }, 26467 { Mips::LEA_ADDiu, Mips::LEA_ADDiu, Mips::LEA_ADDiu_MM }, 26468 { Mips::LH, Mips::LH, Mips::LH_MM }, 26469 { Mips::LHE, Mips::LHE, Mips::LHE_MM }, 26470 { Mips::LHu, Mips::LHu, Mips::LHu_MM }, 26471 { Mips::LHuE, Mips::LHuE, Mips::LHuE_MM }, 26472 { Mips::LLE, Mips::LLE, Mips::LLE_MM }, 26473 { Mips::LUXC1, Mips::LUXC1, Mips::LUXC1_MM }, 26474 { Mips::LUi, Mips::LUi, Mips::LUi_MM }, 26475 { Mips::LW, Mips::LW, Mips::LW_MM }, 26476 { Mips::LWC1, Mips::LWC1, Mips::LWC1_MM }, 26477 { Mips::LWE, Mips::LWE, Mips::LWE_MM }, 26478 { Mips::LWL, Mips::LWL, Mips::LWL_MM }, 26479 { Mips::LWLE, Mips::LWLE, Mips::LWLE_MM }, 26480 { Mips::LWR, Mips::LWR, Mips::LWR_MM }, 26481 { Mips::LWRE, Mips::LWRE, Mips::LWRE_MM }, 26482 { Mips::LWXC1, Mips::LWXC1, Mips::LWXC1_MM }, 26483 { Mips::LWu, Mips::LWu, Mips::LWU_MM }, 26484 { Mips::MADD, Mips::MADD, Mips::MADD_MM }, 26485 { Mips::MADDU, Mips::MADDU, Mips::MADDU_MM }, 26486 { Mips::MADD_D32, Mips::MADD_D32, Mips::MADD_D32_MM }, 26487 { Mips::MADD_S, Mips::MADD_S, Mips::MADD_S_MM }, 26488 { Mips::MFC1, Mips::MFC1, Mips::MFC1_MM }, 26489 { Mips::MFGC0, Mips::MFGC0, Mips::MFGC0_MM }, 26490 { Mips::MFHC1_D32, Mips::MFHC1_D32, Mips::MFHC1_D32_MM }, 26491 { Mips::MFHGC0, Mips::MFHGC0, Mips::MFHGC0_MM }, 26492 { Mips::MFHI, Mips::MFHI, Mips::MFHI_MM }, 26493 { Mips::MFLO, Mips::MFLO, Mips::MFLO_MM }, 26494 { Mips::MOVF_D32, Mips::MOVF_D32, Mips::MOVF_D32_MM }, 26495 { Mips::MOVF_I, Mips::MOVF_I, Mips::MOVF_I_MM }, 26496 { Mips::MOVF_S, Mips::MOVF_S, Mips::MOVF_S_MM }, 26497 { Mips::MOVN_I_D32, Mips::MOVN_I_D32, Mips::MOVN_I_D32_MM }, 26498 { Mips::MOVN_I_I, Mips::MOVN_I_I, Mips::MOVN_I_MM }, 26499 { Mips::MOVN_I_S, Mips::MOVN_I_S, Mips::MOVN_I_S_MM }, 26500 { Mips::MOVT_D32, Mips::MOVT_D32, Mips::MOVT_D32_MM }, 26501 { Mips::MOVT_I, Mips::MOVT_I, Mips::MOVT_I_MM }, 26502 { Mips::MOVT_S, Mips::MOVT_S, Mips::MOVT_S_MM }, 26503 { Mips::MOVZ_I_D32, Mips::MOVZ_I_D32, Mips::MOVZ_I_D32_MM }, 26504 { Mips::MOVZ_I_I, Mips::MOVZ_I_I, Mips::MOVZ_I_MM }, 26505 { Mips::MOVZ_I_S, Mips::MOVZ_I_S, Mips::MOVZ_I_S_MM }, 26506 { Mips::MSUB, Mips::MSUB, Mips::MSUB_MM }, 26507 { Mips::MSUBU, Mips::MSUBU, Mips::MSUBU_MM }, 26508 { Mips::MSUB_D32, Mips::MSUB_D32, Mips::MSUB_D32_MM }, 26509 { Mips::MSUB_S, Mips::MSUB_S, Mips::MSUB_S_MM }, 26510 { Mips::MTC1, Mips::MTC1, Mips::MTC1_MM }, 26511 { Mips::MTGC0, Mips::MTGC0, Mips::MTGC0_MM }, 26512 { Mips::MTHC1_D32, Mips::MTHC1_D32, Mips::MTHC1_D32_MM }, 26513 { Mips::MTHGC0, Mips::MTHGC0, Mips::MTHGC0_MM }, 26514 { Mips::MTHI, Mips::MTHI, Mips::MTHI_MM }, 26515 { Mips::MTLO, Mips::MTLO, Mips::MTLO_MM }, 26516 { Mips::MUL, Mips::MUL, Mips::MUL_MM }, 26517 { Mips::MULT, Mips::MULT, Mips::MULT_MM }, 26518 { Mips::MULTu, Mips::MULTu, Mips::MULTu_MM }, 26519 { Mips::NMADD_D32, Mips::NMADD_D32, Mips::NMADD_D32_MM }, 26520 { Mips::NMADD_S, Mips::NMADD_S, Mips::NMADD_S_MM }, 26521 { Mips::NMSUB_D32, Mips::NMSUB_D32, Mips::NMSUB_D32_MM }, 26522 { Mips::NMSUB_S, Mips::NMSUB_S, Mips::NMSUB_S_MM }, 26523 { Mips::NOR, Mips::NOR, Mips::NOR_MM }, 26524 { Mips::OR, Mips::OR, Mips::OR_MM }, 26525 { Mips::ORi, Mips::ORi, Mips::ORi_MM }, 26526 { Mips::PAUSE, Mips::PAUSE, Mips::PAUSE_MM }, 26527 { Mips::PREF, Mips::PREF, Mips::PREF_MM }, 26528 { Mips::PREFE, Mips::PREFE, Mips::PREFE_MM }, 26529 { Mips::RDHWR, Mips::RDHWR, Mips::RDHWR_MM }, 26530 { Mips::RECIP_D32, Mips::RECIP_D32, Mips::RECIP_D32_MM }, 26531 { Mips::RECIP_D64, Mips::RECIP_D64, Mips::RECIP_D64_MM }, 26532 { Mips::RECIP_S, Mips::RECIP_S, Mips::RECIP_S_MM }, 26533 { Mips::ROTR, Mips::ROTR, Mips::ROTR_MM }, 26534 { Mips::ROTRV, Mips::ROTRV, Mips::ROTRV_MM }, 26535 { Mips::ROUND_W_D32, Mips::ROUND_W_D32, Mips::ROUND_W_MM }, 26536 { Mips::ROUND_W_S, Mips::ROUND_W_S, Mips::ROUND_W_S_MM }, 26537 { Mips::RSQRT_D32, Mips::RSQRT_D32, Mips::RSQRT_D32_MM }, 26538 { Mips::RSQRT_D64, Mips::RSQRT_D64, Mips::RSQRT_D64_MM }, 26539 { Mips::RSQRT_S, Mips::RSQRT_S, Mips::RSQRT_S_MM }, 26540 { Mips::SB, Mips::SB, Mips::SB_MM }, 26541 { Mips::SBE, Mips::SBE, Mips::SBE_MM }, 26542 { Mips::SCE, Mips::SCE, Mips::SCE_MM }, 26543 { Mips::SDBBP, Mips::SDBBP, Mips::SDBBP_MM }, 26544 { Mips::SDC1, Mips::SDC1, (uint16_t)-1U }, 26545 { Mips::SDIV, Mips::SDIV, Mips::SDIV_MM }, 26546 { Mips::SEB, Mips::SEB, Mips::SEB_MM }, 26547 { Mips::SEH, Mips::SEH, Mips::SEH_MM }, 26548 { Mips::SH, Mips::SH, Mips::SH_MM }, 26549 { Mips::SHE, Mips::SHE, Mips::SHE_MM }, 26550 { Mips::SLL, Mips::SLL, Mips::SLL_MM }, 26551 { Mips::SLLV, Mips::SLLV, Mips::SLLV_MM }, 26552 { Mips::SLT, Mips::SLT, Mips::SLT_MM }, 26553 { Mips::SLTi, Mips::SLTi, Mips::SLTi_MM }, 26554 { Mips::SLTiu, Mips::SLTiu, Mips::SLTiu_MM }, 26555 { Mips::SLTu, Mips::SLTu, Mips::SLTu_MM }, 26556 { Mips::SRA, Mips::SRA, Mips::SRA_MM }, 26557 { Mips::SRAV, Mips::SRAV, Mips::SRAV_MM }, 26558 { Mips::SRL, Mips::SRL, Mips::SRL_MM }, 26559 { Mips::SRLV, Mips::SRLV, Mips::SRLV_MM }, 26560 { Mips::SSNOP, Mips::SSNOP, Mips::SSNOP_MM }, 26561 { Mips::SUB, Mips::SUB, Mips::SUB_MM }, 26562 { Mips::SUBu, Mips::SUBu, Mips::SUBu_MM }, 26563 { Mips::SUXC1, Mips::SUXC1, Mips::SUXC1_MM }, 26564 { Mips::SW, Mips::SW, Mips::SW_MM }, 26565 { Mips::SWC1, Mips::SWC1, Mips::SWC1_MM }, 26566 { Mips::SWE, Mips::SWE, Mips::SWE_MM }, 26567 { Mips::SWL, Mips::SWL, Mips::SWL_MM }, 26568 { Mips::SWLE, Mips::SWLE, Mips::SWLE_MM }, 26569 { Mips::SWR, Mips::SWR, Mips::SWR_MM }, 26570 { Mips::SWRE, Mips::SWRE, Mips::SWRE_MM }, 26571 { Mips::SWXC1, Mips::SWXC1, Mips::SWXC1_MM }, 26572 { Mips::SYNC, Mips::SYNC, Mips::SYNC_MM }, 26573 { Mips::SYNCI, Mips::SYNCI, Mips::SYNCI_MM }, 26574 { Mips::SYSCALL, Mips::SYSCALL, Mips::SYSCALL_MM }, 26575 { Mips::TEQ, Mips::TEQ, Mips::TEQ_MM }, 26576 { Mips::TEQI, Mips::TEQI, Mips::TEQI_MM }, 26577 { Mips::TGE, Mips::TGE, Mips::TGE_MM }, 26578 { Mips::TGEI, Mips::TGEI, Mips::TGEI_MM }, 26579 { Mips::TGEIU, Mips::TGEIU, Mips::TGEIU_MM }, 26580 { Mips::TGEU, Mips::TGEU, Mips::TGEU_MM }, 26581 { Mips::TLBGINV, Mips::TLBGINV, Mips::TLBGINV_MM }, 26582 { Mips::TLBGINVF, Mips::TLBGINVF, Mips::TLBGINVF_MM }, 26583 { Mips::TLBGP, Mips::TLBGP, Mips::TLBGP_MM }, 26584 { Mips::TLBGR, Mips::TLBGR, Mips::TLBGR_MM }, 26585 { Mips::TLBGWI, Mips::TLBGWI, Mips::TLBGWI_MM }, 26586 { Mips::TLBGWR, Mips::TLBGWR, Mips::TLBGWR_MM }, 26587 { Mips::TLBP, Mips::TLBP, Mips::TLBP_MM }, 26588 { Mips::TLBR, Mips::TLBR, Mips::TLBR_MM }, 26589 { Mips::TLBWI, Mips::TLBWI, Mips::TLBWI_MM }, 26590 { Mips::TLBWR, Mips::TLBWR, Mips::TLBWR_MM }, 26591 { Mips::TLT, Mips::TLT, Mips::TLT_MM }, 26592 { Mips::TLTI, Mips::TLTI, Mips::TLTI_MM }, 26593 { Mips::TLTU, Mips::TLTU, Mips::TLTU_MM }, 26594 { Mips::TNE, Mips::TNE, Mips::TNE_MM }, 26595 { Mips::TNEI, Mips::TNEI, Mips::TNEI_MM }, 26596 { Mips::TRUNC_W_D32, Mips::TRUNC_W_D32, Mips::TRUNC_W_MM }, 26597 { Mips::TRUNC_W_S, Mips::TRUNC_W_S, Mips::TRUNC_W_S_MM }, 26598 { Mips::TTLTIU, Mips::TTLTIU, Mips::TLTIU_MM }, 26599 { Mips::UDIV, Mips::UDIV, Mips::UDIV_MM }, 26600 { Mips::WAIT, Mips::WAIT, Mips::WAIT_MM }, 26601 { Mips::WSBH, Mips::WSBH, Mips::WSBH_MM }, 26602 { Mips::XOR, Mips::XOR, Mips::XOR_MM }, 26603 { Mips::XORi, Mips::XORi, Mips::XORi_MM }, 26604}; // End of Std2MicroMipsTable 26605 26606 unsigned mid; 26607 unsigned start = 0; 26608 unsigned end = 266; 26609 while (start < end) { 26610 mid = start + (end - start) / 2; 26611 if (Opcode == Std2MicroMipsTable[mid][0]) { 26612 break; 26613 } 26614 if (Opcode < Std2MicroMipsTable[mid][0]) 26615 end = mid; 26616 else 26617 start = mid + 1; 26618 } 26619 if (start == end) 26620 return -1; // Instruction doesn't exist in this table. 26621 26622 if (inArch == Arch_se) 26623 return Std2MicroMipsTable[mid][1]; 26624 if (inArch == Arch_micromips) 26625 return Std2MicroMipsTable[mid][2]; 26626 return -1;} 26627 26628// Std2MicroMipsR6 26629LLVM_READONLY 26630int Std2MicroMipsR6(uint16_t Opcode, enum Arch inArch) { 26631static const uint16_t Std2MicroMipsR6Table[][3] = { 26632 { Mips::ADD, Mips::ADD, Mips::ADD_MMR6 }, 26633 { Mips::ADDiu, Mips::ADDiu, Mips::ADDIU_MMR6 }, 26634 { Mips::ADDu, Mips::ADDu, Mips::ADDU_MMR6 }, 26635 { Mips::AND, Mips::AND, Mips::AND_MMR6 }, 26636 { Mips::ANDi, Mips::ANDi, Mips::ANDI_MMR6 }, 26637 { Mips::BREAK, Mips::BREAK, Mips::BREAK_MMR6 }, 26638 { Mips::CEIL_W_D64, Mips::CEIL_W_D64, Mips::CEIL_W_D_MMR6 }, 26639 { Mips::CEIL_W_S, Mips::CEIL_W_S, Mips::CEIL_W_S_MMR6 }, 26640 { Mips::CVT_W_D64, Mips::CVT_W_D64, (uint16_t)-1U }, 26641 { Mips::DI, Mips::DI, Mips::DI_MMR6 }, 26642 { Mips::EI, Mips::EI, Mips::EI_MMR6 }, 26643 { Mips::EXT, Mips::EXT, Mips::EXT_MMR6 }, 26644 { Mips::FABS_D64, Mips::FABS_D64, (uint16_t)-1U }, 26645 { Mips::FLOOR_W_D64, Mips::FLOOR_W_D64, Mips::FLOOR_W_D_MMR6 }, 26646 { Mips::FLOOR_W_S, Mips::FLOOR_W_S, Mips::FLOOR_W_S_MMR6 }, 26647 { Mips::FMOV_D64, Mips::FMOV_D64, Mips::FMOV_D_MMR6 }, 26648 { Mips::FNEG_D64, Mips::FNEG_D64, (uint16_t)-1U }, 26649 { Mips::FSQRT_D64, Mips::FSQRT_D64, (uint16_t)-1U }, 26650 { Mips::FSQRT_S, Mips::FSQRT_S, (uint16_t)-1U }, 26651 { Mips::INS, Mips::INS, Mips::INS_MMR6 }, 26652 { Mips::LDC1, Mips::LDC1, (uint16_t)-1U }, 26653 { Mips::LDC164, Mips::LDC164, Mips::LDC1_D64_MMR6 }, 26654 { Mips::LDC2, Mips::LDC2, Mips::LDC2_MMR6 }, 26655 { Mips::LW, Mips::LW, Mips::LW_MMR6 }, 26656 { Mips::LWC2, Mips::LWC2, Mips::LWC2_MMR6 }, 26657 { Mips::MFC1, Mips::MFC1, Mips::MFC1_MMR6 }, 26658 { Mips::MTC1, Mips::MTC1, Mips::MTC1_MMR6 }, 26659 { Mips::MTHC1_D32, Mips::MTHC1_D32, (uint16_t)-1U }, 26660 { Mips::NOR, Mips::NOR, Mips::NOR_MMR6 }, 26661 { Mips::OR, Mips::OR, Mips::OR_MMR6 }, 26662 { Mips::ORi, Mips::ORi, Mips::ORI_MMR6 }, 26663 { Mips::PAUSE, Mips::PAUSE, Mips::PAUSE_MMR6 }, 26664 { Mips::ROUND_W_D64, Mips::ROUND_W_D64, Mips::ROUND_W_D_MMR6 }, 26665 { Mips::ROUND_W_S, Mips::ROUND_W_S, Mips::ROUND_W_S_MMR6 }, 26666 { Mips::SB, Mips::SB, Mips::SB_MMR6 }, 26667 { Mips::SDC164, Mips::SDC164, Mips::SDC1_D64_MMR6 }, 26668 { Mips::SDC2, Mips::SDC2, Mips::SDC2_MMR6 }, 26669 { Mips::SEB, Mips::SEB, (uint16_t)-1U }, 26670 { Mips::SEH, Mips::SEH, (uint16_t)-1U }, 26671 { Mips::SSNOP, Mips::SSNOP, Mips::SSNOP_MMR6 }, 26672 { Mips::SUB, Mips::SUB, Mips::SUB_MMR6 }, 26673 { Mips::SUBu, Mips::SUBu, Mips::SUBU_MMR6 }, 26674 { Mips::SW, Mips::SW, Mips::SW_MMR6 }, 26675 { Mips::SWC2, Mips::SWC2, Mips::SWC2_MMR6 }, 26676 { Mips::SYNC, Mips::SYNC, Mips::SYNC_MMR6 }, 26677 { Mips::SYNCI, Mips::SYNCI, Mips::SYNCI_MMR6 }, 26678 { Mips::TRUNC_W_D64, Mips::TRUNC_W_D64, Mips::TRUNC_W_D_MMR6 }, 26679 { Mips::TRUNC_W_S, Mips::TRUNC_W_S, Mips::TRUNC_W_S_MMR6 }, 26680 { Mips::WAIT, Mips::WAIT, Mips::WAIT_MMR6 }, 26681 { Mips::XOR, Mips::XOR, Mips::XOR_MMR6 }, 26682 { Mips::XORi, Mips::XORi, Mips::XORI_MMR6 }, 26683}; // End of Std2MicroMipsR6Table 26684 26685 unsigned mid; 26686 unsigned start = 0; 26687 unsigned end = 51; 26688 while (start < end) { 26689 mid = start + (end - start) / 2; 26690 if (Opcode == Std2MicroMipsR6Table[mid][0]) { 26691 break; 26692 } 26693 if (Opcode < Std2MicroMipsR6Table[mid][0]) 26694 end = mid; 26695 else 26696 start = mid + 1; 26697 } 26698 if (start == end) 26699 return -1; // Instruction doesn't exist in this table. 26700 26701 if (inArch == Arch_se) 26702 return Std2MicroMipsR6Table[mid][1]; 26703 if (inArch == Arch_micromipsr6) 26704 return Std2MicroMipsR6Table[mid][2]; 26705 return -1;} 26706 26707} // end namespace Mips 26708} // end namespace llvm 26709#endif // GET_INSTRMAP_INFO 26710 26711