1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2|* *| 3|* Machine Code Emitter *| 4|* *| 5|* Automatically generated file, do not edit! *| 6|* *| 7\*===----------------------------------------------------------------------===*/ 8 9uint64_t MipsMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI, 10 SmallVectorImpl<MCFixup> &Fixups, 11 const MCSubtargetInfo &STI) const { 12 static const uint64_t InstBits[] = { 13 UINT64_C(0), 14 UINT64_C(0), 15 UINT64_C(0), 16 UINT64_C(0), 17 UINT64_C(0), 18 UINT64_C(0), 19 UINT64_C(0), 20 UINT64_C(0), 21 UINT64_C(0), 22 UINT64_C(0), 23 UINT64_C(0), 24 UINT64_C(0), 25 UINT64_C(0), 26 UINT64_C(0), 27 UINT64_C(0), 28 UINT64_C(0), 29 UINT64_C(0), 30 UINT64_C(0), 31 UINT64_C(0), 32 UINT64_C(0), 33 UINT64_C(0), 34 UINT64_C(0), 35 UINT64_C(0), 36 UINT64_C(0), 37 UINT64_C(0), 38 UINT64_C(0), 39 UINT64_C(0), 40 UINT64_C(0), 41 UINT64_C(0), 42 UINT64_C(0), 43 UINT64_C(0), 44 UINT64_C(0), 45 UINT64_C(0), 46 UINT64_C(0), 47 UINT64_C(0), 48 UINT64_C(0), 49 UINT64_C(0), 50 UINT64_C(0), 51 UINT64_C(0), 52 UINT64_C(0), 53 UINT64_C(0), 54 UINT64_C(0), 55 UINT64_C(0), 56 UINT64_C(0), 57 UINT64_C(0), 58 UINT64_C(0), 59 UINT64_C(0), 60 UINT64_C(0), 61 UINT64_C(0), 62 UINT64_C(0), 63 UINT64_C(0), 64 UINT64_C(0), 65 UINT64_C(0), 66 UINT64_C(0), 67 UINT64_C(0), 68 UINT64_C(0), 69 UINT64_C(0), 70 UINT64_C(0), 71 UINT64_C(0), 72 UINT64_C(0), 73 UINT64_C(0), 74 UINT64_C(0), 75 UINT64_C(0), 76 UINT64_C(0), 77 UINT64_C(0), 78 UINT64_C(0), 79 UINT64_C(0), 80 UINT64_C(0), 81 UINT64_C(0), 82 UINT64_C(0), 83 UINT64_C(0), 84 UINT64_C(0), 85 UINT64_C(0), 86 UINT64_C(0), 87 UINT64_C(0), 88 UINT64_C(0), 89 UINT64_C(0), 90 UINT64_C(0), 91 UINT64_C(0), 92 UINT64_C(0), 93 UINT64_C(0), 94 UINT64_C(0), 95 UINT64_C(0), 96 UINT64_C(0), 97 UINT64_C(0), 98 UINT64_C(0), 99 UINT64_C(0), 100 UINT64_C(0), 101 UINT64_C(0), 102 UINT64_C(0), 103 UINT64_C(0), 104 UINT64_C(0), 105 UINT64_C(0), 106 UINT64_C(0), 107 UINT64_C(0), 108 UINT64_C(0), 109 UINT64_C(0), 110 UINT64_C(0), 111 UINT64_C(0), 112 UINT64_C(0), 113 UINT64_C(0), 114 UINT64_C(0), 115 UINT64_C(0), 116 UINT64_C(0), 117 UINT64_C(0), 118 UINT64_C(0), 119 UINT64_C(0), 120 UINT64_C(0), 121 UINT64_C(0), 122 UINT64_C(0), 123 UINT64_C(0), 124 UINT64_C(0), 125 UINT64_C(0), 126 UINT64_C(0), 127 UINT64_C(0), 128 UINT64_C(0), 129 UINT64_C(0), 130 UINT64_C(0), 131 UINT64_C(0), 132 UINT64_C(0), 133 UINT64_C(0), 134 UINT64_C(0), 135 UINT64_C(0), 136 UINT64_C(0), 137 UINT64_C(0), 138 UINT64_C(0), 139 UINT64_C(0), 140 UINT64_C(0), 141 UINT64_C(0), 142 UINT64_C(0), 143 UINT64_C(0), 144 UINT64_C(0), 145 UINT64_C(0), 146 UINT64_C(0), 147 UINT64_C(0), 148 UINT64_C(0), 149 UINT64_C(0), 150 UINT64_C(0), 151 UINT64_C(0), 152 UINT64_C(0), 153 UINT64_C(0), 154 UINT64_C(0), 155 UINT64_C(0), 156 UINT64_C(0), 157 UINT64_C(0), 158 UINT64_C(0), 159 UINT64_C(0), 160 UINT64_C(0), 161 UINT64_C(0), 162 UINT64_C(0), 163 UINT64_C(0), 164 UINT64_C(0), 165 UINT64_C(0), 166 UINT64_C(0), 167 UINT64_C(0), 168 UINT64_C(0), 169 UINT64_C(0), 170 UINT64_C(0), 171 UINT64_C(0), 172 UINT64_C(0), 173 UINT64_C(0), 174 UINT64_C(0), 175 UINT64_C(0), 176 UINT64_C(0), 177 UINT64_C(0), 178 UINT64_C(0), 179 UINT64_C(0), 180 UINT64_C(0), 181 UINT64_C(0), 182 UINT64_C(0), 183 UINT64_C(0), 184 UINT64_C(0), 185 UINT64_C(0), 186 UINT64_C(0), 187 UINT64_C(0), 188 UINT64_C(0), 189 UINT64_C(0), 190 UINT64_C(0), 191 UINT64_C(0), 192 UINT64_C(0), 193 UINT64_C(0), 194 UINT64_C(0), 195 UINT64_C(0), 196 UINT64_C(0), 197 UINT64_C(0), 198 UINT64_C(0), 199 UINT64_C(0), 200 UINT64_C(0), 201 UINT64_C(0), 202 UINT64_C(0), 203 UINT64_C(0), 204 UINT64_C(0), 205 UINT64_C(0), 206 UINT64_C(0), 207 UINT64_C(0), 208 UINT64_C(0), 209 UINT64_C(0), 210 UINT64_C(0), 211 UINT64_C(0), 212 UINT64_C(0), 213 UINT64_C(0), 214 UINT64_C(0), 215 UINT64_C(0), 216 UINT64_C(0), 217 UINT64_C(0), 218 UINT64_C(0), 219 UINT64_C(0), 220 UINT64_C(0), 221 UINT64_C(0), 222 UINT64_C(0), 223 UINT64_C(0), 224 UINT64_C(0), 225 UINT64_C(0), 226 UINT64_C(0), 227 UINT64_C(0), 228 UINT64_C(0), 229 UINT64_C(0), 230 UINT64_C(0), 231 UINT64_C(0), 232 UINT64_C(0), 233 UINT64_C(0), 234 UINT64_C(0), 235 UINT64_C(0), 236 UINT64_C(0), 237 UINT64_C(0), 238 UINT64_C(0), 239 UINT64_C(0), 240 UINT64_C(0), 241 UINT64_C(0), 242 UINT64_C(0), 243 UINT64_C(0), 244 UINT64_C(0), 245 UINT64_C(0), 246 UINT64_C(0), 247 UINT64_C(0), 248 UINT64_C(0), 249 UINT64_C(0), 250 UINT64_C(0), 251 UINT64_C(0), 252 UINT64_C(0), 253 UINT64_C(0), 254 UINT64_C(0), 255 UINT64_C(0), 256 UINT64_C(0), 257 UINT64_C(0), 258 UINT64_C(0), 259 UINT64_C(0), 260 UINT64_C(0), 261 UINT64_C(0), 262 UINT64_C(0), 263 UINT64_C(0), 264 UINT64_C(0), 265 UINT64_C(0), 266 UINT64_C(0), 267 UINT64_C(0), 268 UINT64_C(0), 269 UINT64_C(0), 270 UINT64_C(0), 271 UINT64_C(0), 272 UINT64_C(0), 273 UINT64_C(0), 274 UINT64_C(0), 275 UINT64_C(0), 276 UINT64_C(0), 277 UINT64_C(0), 278 UINT64_C(0), 279 UINT64_C(0), 280 UINT64_C(0), 281 UINT64_C(0), 282 UINT64_C(0), 283 UINT64_C(0), 284 UINT64_C(0), 285 UINT64_C(0), 286 UINT64_C(0), 287 UINT64_C(0), 288 UINT64_C(0), 289 UINT64_C(0), 290 UINT64_C(0), 291 UINT64_C(0), 292 UINT64_C(0), 293 UINT64_C(0), 294 UINT64_C(0), 295 UINT64_C(0), 296 UINT64_C(0), 297 UINT64_C(0), 298 UINT64_C(0), 299 UINT64_C(0), 300 UINT64_C(0), 301 UINT64_C(0), 302 UINT64_C(0), 303 UINT64_C(0), 304 UINT64_C(0), 305 UINT64_C(0), 306 UINT64_C(0), 307 UINT64_C(0), 308 UINT64_C(0), 309 UINT64_C(0), 310 UINT64_C(0), 311 UINT64_C(0), 312 UINT64_C(0), 313 UINT64_C(0), 314 UINT64_C(0), 315 UINT64_C(0), 316 UINT64_C(0), 317 UINT64_C(0), 318 UINT64_C(0), 319 UINT64_C(0), 320 UINT64_C(0), 321 UINT64_C(0), 322 UINT64_C(0), 323 UINT64_C(0), 324 UINT64_C(0), 325 UINT64_C(0), 326 UINT64_C(0), 327 UINT64_C(0), 328 UINT64_C(0), 329 UINT64_C(0), 330 UINT64_C(0), 331 UINT64_C(0), 332 UINT64_C(0), 333 UINT64_C(0), 334 UINT64_C(0), 335 UINT64_C(0), 336 UINT64_C(0), 337 UINT64_C(0), 338 UINT64_C(0), 339 UINT64_C(0), 340 UINT64_C(0), 341 UINT64_C(0), 342 UINT64_C(0), 343 UINT64_C(0), 344 UINT64_C(0), 345 UINT64_C(0), 346 UINT64_C(0), 347 UINT64_C(0), 348 UINT64_C(0), 349 UINT64_C(0), 350 UINT64_C(0), 351 UINT64_C(0), 352 UINT64_C(0), 353 UINT64_C(0), 354 UINT64_C(0), 355 UINT64_C(0), 356 UINT64_C(0), 357 UINT64_C(0), 358 UINT64_C(0), 359 UINT64_C(0), 360 UINT64_C(0), 361 UINT64_C(0), 362 UINT64_C(0), 363 UINT64_C(0), 364 UINT64_C(0), 365 UINT64_C(0), 366 UINT64_C(0), 367 UINT64_C(0), 368 UINT64_C(0), 369 UINT64_C(0), 370 UINT64_C(0), 371 UINT64_C(0), 372 UINT64_C(0), 373 UINT64_C(0), 374 UINT64_C(0), 375 UINT64_C(0), 376 UINT64_C(0), 377 UINT64_C(0), 378 UINT64_C(0), 379 UINT64_C(0), 380 UINT64_C(0), 381 UINT64_C(0), 382 UINT64_C(0), 383 UINT64_C(0), 384 UINT64_C(0), 385 UINT64_C(0), 386 UINT64_C(0), 387 UINT64_C(0), 388 UINT64_C(0), 389 UINT64_C(0), 390 UINT64_C(0), 391 UINT64_C(0), 392 UINT64_C(0), 393 UINT64_C(0), 394 UINT64_C(0), 395 UINT64_C(0), 396 UINT64_C(0), 397 UINT64_C(0), 398 UINT64_C(0), 399 UINT64_C(0), 400 UINT64_C(0), 401 UINT64_C(0), 402 UINT64_C(0), 403 UINT64_C(0), 404 UINT64_C(0), 405 UINT64_C(0), 406 UINT64_C(0), 407 UINT64_C(0), 408 UINT64_C(0), 409 UINT64_C(0), 410 UINT64_C(0), 411 UINT64_C(0), 412 UINT64_C(0), 413 UINT64_C(0), 414 UINT64_C(0), 415 UINT64_C(0), 416 UINT64_C(0), 417 UINT64_C(0), 418 UINT64_C(0), 419 UINT64_C(0), 420 UINT64_C(0), 421 UINT64_C(0), 422 UINT64_C(0), 423 UINT64_C(0), 424 UINT64_C(0), 425 UINT64_C(0), 426 UINT64_C(0), 427 UINT64_C(0), 428 UINT64_C(0), 429 UINT64_C(0), 430 UINT64_C(0), 431 UINT64_C(0), 432 UINT64_C(0), 433 UINT64_C(0), 434 UINT64_C(0), 435 UINT64_C(0), 436 UINT64_C(0), 437 UINT64_C(0), 438 UINT64_C(0), 439 UINT64_C(0), 440 UINT64_C(0), 441 UINT64_C(0), 442 UINT64_C(0), 443 UINT64_C(0), 444 UINT64_C(0), 445 UINT64_C(0), 446 UINT64_C(0), 447 UINT64_C(0), 448 UINT64_C(0), 449 UINT64_C(0), 450 UINT64_C(0), 451 UINT64_C(0), 452 UINT64_C(0), 453 UINT64_C(0), 454 UINT64_C(0), 455 UINT64_C(0), 456 UINT64_C(0), 457 UINT64_C(0), 458 UINT64_C(0), 459 UINT64_C(0), 460 UINT64_C(0), 461 UINT64_C(0), 462 UINT64_C(0), 463 UINT64_C(0), 464 UINT64_C(0), 465 UINT64_C(0), 466 UINT64_C(0), 467 UINT64_C(0), 468 UINT64_C(0), 469 UINT64_C(0), 470 UINT64_C(0), 471 UINT64_C(0), 472 UINT64_C(0), 473 UINT64_C(0), 474 UINT64_C(0), 475 UINT64_C(0), 476 UINT64_C(0), 477 UINT64_C(0), 478 UINT64_C(0), 479 UINT64_C(0), 480 UINT64_C(0), 481 UINT64_C(0), 482 UINT64_C(0), 483 UINT64_C(0), 484 UINT64_C(0), 485 UINT64_C(0), 486 UINT64_C(0), 487 UINT64_C(0), 488 UINT64_C(0), 489 UINT64_C(0), 490 UINT64_C(0), 491 UINT64_C(0), 492 UINT64_C(0), 493 UINT64_C(0), 494 UINT64_C(0), 495 UINT64_C(0), 496 UINT64_C(0), 497 UINT64_C(0), 498 UINT64_C(0), 499 UINT64_C(0), 500 UINT64_C(0), 501 UINT64_C(0), 502 UINT64_C(0), 503 UINT64_C(0), 504 UINT64_C(0), 505 UINT64_C(0), 506 UINT64_C(0), 507 UINT64_C(0), 508 UINT64_C(0), 509 UINT64_C(0), 510 UINT64_C(0), 511 UINT64_C(0), 512 UINT64_C(0), 513 UINT64_C(0), 514 UINT64_C(0), 515 UINT64_C(0), 516 UINT64_C(0), 517 UINT64_C(0), 518 UINT64_C(0), 519 UINT64_C(0), 520 UINT64_C(0), 521 UINT64_C(0), 522 UINT64_C(0), 523 UINT64_C(0), 524 UINT64_C(0), 525 UINT64_C(0), 526 UINT64_C(0), 527 UINT64_C(0), 528 UINT64_C(0), 529 UINT64_C(0), 530 UINT64_C(0), 531 UINT64_C(0), 532 UINT64_C(0), 533 UINT64_C(0), 534 UINT64_C(0), 535 UINT64_C(0), 536 UINT64_C(0), 537 UINT64_C(0), 538 UINT64_C(0), 539 UINT64_C(0), 540 UINT64_C(0), 541 UINT64_C(0), 542 UINT64_C(0), 543 UINT64_C(0), 544 UINT64_C(0), 545 UINT64_C(0), 546 UINT64_C(0), 547 UINT64_C(0), 548 UINT64_C(0), 549 UINT64_C(0), 550 UINT64_C(0), 551 UINT64_C(0), 552 UINT64_C(0), 553 UINT64_C(0), 554 UINT64_C(0), 555 UINT64_C(0), 556 UINT64_C(0), 557 UINT64_C(0), 558 UINT64_C(0), 559 UINT64_C(0), 560 UINT64_C(0), 561 UINT64_C(0), 562 UINT64_C(0), 563 UINT64_C(0), 564 UINT64_C(0), 565 UINT64_C(0), 566 UINT64_C(0), 567 UINT64_C(0), 568 UINT64_C(0), 569 UINT64_C(0), 570 UINT64_C(0), 571 UINT64_C(0), 572 UINT64_C(0), 573 UINT64_C(0), 574 UINT64_C(0), 575 UINT64_C(0), 576 UINT64_C(0), 577 UINT64_C(0), 578 UINT64_C(0), 579 UINT64_C(0), 580 UINT64_C(0), 581 UINT64_C(0), 582 UINT64_C(0), 583 UINT64_C(0), 584 UINT64_C(0), 585 UINT64_C(0), 586 UINT64_C(0), 587 UINT64_C(0), 588 UINT64_C(0), 589 UINT64_C(0), 590 UINT64_C(0), 591 UINT64_C(0), 592 UINT64_C(0), 593 UINT64_C(0), 594 UINT64_C(0), 595 UINT64_C(0), 596 UINT64_C(0), 597 UINT64_C(0), 598 UINT64_C(0), 599 UINT64_C(0), 600 UINT64_C(0), 601 UINT64_C(0), 602 UINT64_C(0), 603 UINT64_C(0), 604 UINT64_C(0), 605 UINT64_C(0), 606 UINT64_C(0), 607 UINT64_C(0), 608 UINT64_C(0), 609 UINT64_C(0), 610 UINT64_C(0), 611 UINT64_C(0), 612 UINT64_C(0), 613 UINT64_C(0), 614 UINT64_C(0), 615 UINT64_C(0), 616 UINT64_C(0), 617 UINT64_C(0), 618 UINT64_C(0), 619 UINT64_C(0), 620 UINT64_C(0), 621 UINT64_C(0), 622 UINT64_C(0), 623 UINT64_C(0), 624 UINT64_C(0), 625 UINT64_C(0), 626 UINT64_C(0), 627 UINT64_C(0), 628 UINT64_C(0), 629 UINT64_C(0), 630 UINT64_C(0), 631 UINT64_C(0), 632 UINT64_C(0), 633 UINT64_C(0), 634 UINT64_C(0), 635 UINT64_C(0), 636 UINT64_C(0), 637 UINT64_C(0), 638 UINT64_C(0), 639 UINT64_C(0), 640 UINT64_C(0), 641 UINT64_C(0), 642 UINT64_C(0), 643 UINT64_C(0), 644 UINT64_C(0), 645 UINT64_C(0), 646 UINT64_C(0), 647 UINT64_C(0), 648 UINT64_C(0), 649 UINT64_C(0), 650 UINT64_C(0), 651 UINT64_C(0), 652 UINT64_C(0), 653 UINT64_C(0), 654 UINT64_C(0), 655 UINT64_C(0), 656 UINT64_C(0), 657 UINT64_C(0), 658 UINT64_C(0), 659 UINT64_C(0), 660 UINT64_C(0), 661 UINT64_C(0), 662 UINT64_C(0), 663 UINT64_C(0), 664 UINT64_C(0), 665 UINT64_C(0), 666 UINT64_C(0), 667 UINT64_C(0), 668 UINT64_C(0), 669 UINT64_C(0), 670 UINT64_C(0), 671 UINT64_C(0), 672 UINT64_C(0), 673 UINT64_C(0), 674 UINT64_C(0), 675 UINT64_C(0), 676 UINT64_C(0), 677 UINT64_C(0), 678 UINT64_C(0), 679 UINT64_C(0), 680 UINT64_C(0), 681 UINT64_C(0), 682 UINT64_C(0), 683 UINT64_C(0), 684 UINT64_C(0), 685 UINT64_C(0), 686 UINT64_C(0), 687 UINT64_C(0), 688 UINT64_C(0), 689 UINT64_C(0), 690 UINT64_C(0), 691 UINT64_C(0), 692 UINT64_C(0), 693 UINT64_C(0), 694 UINT64_C(0), 695 UINT64_C(0), 696 UINT64_C(0), 697 UINT64_C(0), 698 UINT64_C(0), 699 UINT64_C(0), 700 UINT64_C(0), 701 UINT64_C(0), 702 UINT64_C(0), 703 UINT64_C(0), 704 UINT64_C(0), 705 UINT64_C(0), 706 UINT64_C(0), 707 UINT64_C(0), 708 UINT64_C(0), 709 UINT64_C(0), 710 UINT64_C(0), 711 UINT64_C(0), 712 UINT64_C(0), 713 UINT64_C(0), 714 UINT64_C(0), 715 UINT64_C(0), 716 UINT64_C(0), 717 UINT64_C(0), 718 UINT64_C(0), 719 UINT64_C(0), 720 UINT64_C(0), 721 UINT64_C(0), 722 UINT64_C(2080375378), // ABSQ_S_PH 723 UINT64_C(4412), // ABSQ_S_PH_MM 724 UINT64_C(2080374866), // ABSQ_S_QB 725 UINT64_C(316), // ABSQ_S_QB_MMR2 726 UINT64_C(2080375890), // ABSQ_S_W 727 UINT64_C(8508), // ABSQ_S_W_MM 728 UINT64_C(32), // ADD 729 UINT64_C(3959422976), // ADDIUPC 730 UINT64_C(2013265920), // ADDIUPC_MM 731 UINT64_C(2013265920), // ADDIUPC_MMR6 732 UINT64_C(27649), // ADDIUR1SP_MM 733 UINT64_C(27648), // ADDIUR2_MM 734 UINT64_C(19456), // ADDIUS5_MM 735 UINT64_C(19457), // ADDIUSP_MM 736 UINT64_C(805306368), // ADDIU_MMR6 737 UINT64_C(2080375320), // ADDQH_PH 738 UINT64_C(77), // ADDQH_PH_MMR2 739 UINT64_C(2080375448), // ADDQH_R_PH 740 UINT64_C(1101), // ADDQH_R_PH_MMR2 741 UINT64_C(2080375960), // ADDQH_R_W 742 UINT64_C(1165), // ADDQH_R_W_MMR2 743 UINT64_C(2080375832), // ADDQH_W 744 UINT64_C(141), // ADDQH_W_MMR2 745 UINT64_C(2080375440), // ADDQ_PH 746 UINT64_C(13), // ADDQ_PH_MM 747 UINT64_C(2080375696), // ADDQ_S_PH 748 UINT64_C(1037), // ADDQ_S_PH_MM 749 UINT64_C(2080376208), // ADDQ_S_W 750 UINT64_C(773), // ADDQ_S_W_MM 751 UINT64_C(1186988056), // ADDR_PS64 752 UINT64_C(2080375824), // ADDSC 753 UINT64_C(901), // ADDSC_MM 754 UINT64_C(2021654544), // ADDS_A_B 755 UINT64_C(2027946000), // ADDS_A_D 756 UINT64_C(2023751696), // ADDS_A_H 757 UINT64_C(2025848848), // ADDS_A_W 758 UINT64_C(2030043152), // ADDS_S_B 759 UINT64_C(2036334608), // ADDS_S_D 760 UINT64_C(2032140304), // ADDS_S_H 761 UINT64_C(2034237456), // ADDS_S_W 762 UINT64_C(2038431760), // ADDS_U_B 763 UINT64_C(2044723216), // ADDS_U_D 764 UINT64_C(2040528912), // ADDS_U_H 765 UINT64_C(2042626064), // ADDS_U_W 766 UINT64_C(1024), // ADDU16_MM 767 UINT64_C(1024), // ADDU16_MMR6 768 UINT64_C(2080374808), // ADDUH_QB 769 UINT64_C(333), // ADDUH_QB_MMR2 770 UINT64_C(2080374936), // ADDUH_R_QB 771 UINT64_C(1357), // ADDUH_R_QB_MMR2 772 UINT64_C(336), // ADDU_MMR6 773 UINT64_C(2080375312), // ADDU_PH 774 UINT64_C(269), // ADDU_PH_MMR2 775 UINT64_C(2080374800), // ADDU_QB 776 UINT64_C(205), // ADDU_QB_MM 777 UINT64_C(2080375568), // ADDU_S_PH 778 UINT64_C(1293), // ADDU_S_PH_MMR2 779 UINT64_C(2080375056), // ADDU_S_QB 780 UINT64_C(1229), // ADDU_S_QB_MM 781 UINT64_C(2013265926), // ADDVI_B 782 UINT64_C(2019557382), // ADDVI_D 783 UINT64_C(2015363078), // ADDVI_H 784 UINT64_C(2017460230), // ADDVI_W 785 UINT64_C(2013265934), // ADDV_B 786 UINT64_C(2019557390), // ADDV_D 787 UINT64_C(2015363086), // ADDV_H 788 UINT64_C(2017460238), // ADDV_W 789 UINT64_C(2080375888), // ADDWC 790 UINT64_C(965), // ADDWC_MM 791 UINT64_C(2013265936), // ADD_A_B 792 UINT64_C(2019557392), // ADD_A_D 793 UINT64_C(2015363088), // ADD_A_H 794 UINT64_C(2017460240), // ADD_A_W 795 UINT64_C(272), // ADD_MM 796 UINT64_C(272), // ADD_MMR6 797 UINT64_C(536870912), // ADDi 798 UINT64_C(268435456), // ADDi_MM 799 UINT64_C(603979776), // ADDiu 800 UINT64_C(805306368), // ADDiu_MM 801 UINT64_C(33), // ADDu 802 UINT64_C(336), // ADDu_MM 803 UINT64_C(2080375328), // ALIGN 804 UINT64_C(31), // ALIGN_MMR6 805 UINT64_C(3961454592), // ALUIPC 806 UINT64_C(2015297536), // ALUIPC_MMR6 807 UINT64_C(36), // AND 808 UINT64_C(17536), // AND16_MM 809 UINT64_C(17409), // AND16_MMR6 810 UINT64_C(36), // AND64 811 UINT64_C(11264), // ANDI16_MM 812 UINT64_C(11264), // ANDI16_MMR6 813 UINT64_C(2013265920), // ANDI_B 814 UINT64_C(3489660928), // ANDI_MMR6 815 UINT64_C(592), // AND_MM 816 UINT64_C(592), // AND_MMR6 817 UINT64_C(2013265950), // AND_V 818 UINT64_C(805306368), // ANDi 819 UINT64_C(805306368), // ANDi64 820 UINT64_C(3489660928), // ANDi_MM 821 UINT64_C(2080374833), // APPEND 822 UINT64_C(533), // APPEND_MMR2 823 UINT64_C(2046820369), // ASUB_S_B 824 UINT64_C(2053111825), // ASUB_S_D 825 UINT64_C(2048917521), // ASUB_S_H 826 UINT64_C(2051014673), // ASUB_S_W 827 UINT64_C(2055208977), // ASUB_U_B 828 UINT64_C(2061500433), // ASUB_U_D 829 UINT64_C(2057306129), // ASUB_U_H 830 UINT64_C(2059403281), // ASUB_U_W 831 UINT64_C(1006632960), // AUI 832 UINT64_C(3961389056), // AUIPC 833 UINT64_C(2015232000), // AUIPC_MMR6 834 UINT64_C(268435456), // AUI_MMR6 835 UINT64_C(2063597584), // AVER_S_B 836 UINT64_C(2069889040), // AVER_S_D 837 UINT64_C(2065694736), // AVER_S_H 838 UINT64_C(2067791888), // AVER_S_W 839 UINT64_C(2071986192), // AVER_U_B 840 UINT64_C(2078277648), // AVER_U_D 841 UINT64_C(2074083344), // AVER_U_H 842 UINT64_C(2076180496), // AVER_U_W 843 UINT64_C(2046820368), // AVE_S_B 844 UINT64_C(2053111824), // AVE_S_D 845 UINT64_C(2048917520), // AVE_S_H 846 UINT64_C(2051014672), // AVE_S_W 847 UINT64_C(2055208976), // AVE_U_B 848 UINT64_C(2061500432), // AVE_U_D 849 UINT64_C(2057306128), // AVE_U_H 850 UINT64_C(2059403280), // AVE_U_W 851 UINT64_C(4026550272), // AddiuRxImmX16 852 UINT64_C(4026533888), // AddiuRxPcImmX16 853 UINT64_C(18432), // AddiuRxRxImm16 854 UINT64_C(4026550272), // AddiuRxRxImmX16 855 UINT64_C(4026548224), // AddiuRxRyOffMemX16 856 UINT64_C(25344), // AddiuSpImm16 857 UINT64_C(4026544896), // AddiuSpImmX16 858 UINT64_C(57345), // AdduRxRyRz16 859 UINT64_C(59404), // AndRxRxRy16 860 UINT64_C(52224), // B16_MM 861 UINT64_C(1879048232), // BADDu 862 UINT64_C(68222976), // BAL 863 UINT64_C(3892314112), // BALC 864 UINT64_C(3019898880), // BALC_MMR6 865 UINT64_C(2080375857), // BALIGN 866 UINT64_C(2236), // BALIGN_MMR2 867 UINT64_C(3355443200), // BBIT0 868 UINT64_C(3623878656), // BBIT032 869 UINT64_C(3892314112), // BBIT1 870 UINT64_C(4160749568), // BBIT132 871 UINT64_C(3355443200), // BC 872 UINT64_C(52224), // BC16_MMR6 873 UINT64_C(1159725056), // BC1EQZ 874 UINT64_C(1090519040), // BC1EQZC_MMR6 875 UINT64_C(1157627904), // BC1F 876 UINT64_C(1157758976), // BC1FL 877 UINT64_C(1132462080), // BC1F_MM 878 UINT64_C(1168113664), // BC1NEZ 879 UINT64_C(1092616192), // BC1NEZC_MMR6 880 UINT64_C(1157693440), // BC1T 881 UINT64_C(1157824512), // BC1TL 882 UINT64_C(1134559232), // BC1T_MM 883 UINT64_C(1226833920), // BC2EQZ 884 UINT64_C(1094713344), // BC2EQZC_MMR6 885 UINT64_C(1235222528), // BC2NEZ 886 UINT64_C(1096810496), // BC2NEZC_MMR6 887 UINT64_C(2045771785), // BCLRI_B 888 UINT64_C(2038431753), // BCLRI_D 889 UINT64_C(2044723209), // BCLRI_H 890 UINT64_C(2042626057), // BCLRI_W 891 UINT64_C(2038431757), // BCLR_B 892 UINT64_C(2044723213), // BCLR_D 893 UINT64_C(2040528909), // BCLR_H 894 UINT64_C(2042626061), // BCLR_W 895 UINT64_C(2483027968), // BC_MMR6 896 UINT64_C(268435456), // BEQ 897 UINT64_C(268435456), // BEQ64 898 UINT64_C(536870912), // BEQC 899 UINT64_C(536870912), // BEQC64 900 UINT64_C(1946157056), // BEQC_MMR6 901 UINT64_C(1342177280), // BEQL 902 UINT64_C(35840), // BEQZ16_MM 903 UINT64_C(536870912), // BEQZALC 904 UINT64_C(1946157056), // BEQZALC_MMR6 905 UINT64_C(3623878656), // BEQZC 906 UINT64_C(35840), // BEQZC16_MMR6 907 UINT64_C(3623878656), // BEQZC64 908 UINT64_C(1088421888), // BEQZC_MM 909 UINT64_C(2147483648), // BEQZC_MMR6 910 UINT64_C(2483027968), // BEQ_MM 911 UINT64_C(1476395008), // BGEC 912 UINT64_C(1476395008), // BGEC64 913 UINT64_C(4093640704), // BGEC_MMR6 914 UINT64_C(402653184), // BGEUC 915 UINT64_C(402653184), // BGEUC64 916 UINT64_C(3221225472), // BGEUC_MMR6 917 UINT64_C(67174400), // BGEZ 918 UINT64_C(67174400), // BGEZ64 919 UINT64_C(68222976), // BGEZAL 920 UINT64_C(402653184), // BGEZALC 921 UINT64_C(3221225472), // BGEZALC_MMR6 922 UINT64_C(68354048), // BGEZALL 923 UINT64_C(1113587712), // BGEZALS_MM 924 UINT64_C(1080033280), // BGEZAL_MM 925 UINT64_C(1476395008), // BGEZC 926 UINT64_C(1476395008), // BGEZC64 927 UINT64_C(4093640704), // BGEZC_MMR6 928 UINT64_C(67305472), // BGEZL 929 UINT64_C(1077936128), // BGEZ_MM 930 UINT64_C(469762048), // BGTZ 931 UINT64_C(469762048), // BGTZ64 932 UINT64_C(469762048), // BGTZALC 933 UINT64_C(3758096384), // BGTZALC_MMR6 934 UINT64_C(1543503872), // BGTZC 935 UINT64_C(1543503872), // BGTZC64 936 UINT64_C(3556769792), // BGTZC_MMR6 937 UINT64_C(1543503872), // BGTZL 938 UINT64_C(1086324736), // BGTZ_MM 939 UINT64_C(2070937609), // BINSLI_B 940 UINT64_C(2063597577), // BINSLI_D 941 UINT64_C(2069889033), // BINSLI_H 942 UINT64_C(2067791881), // BINSLI_W 943 UINT64_C(2063597581), // BINSL_B 944 UINT64_C(2069889037), // BINSL_D 945 UINT64_C(2065694733), // BINSL_H 946 UINT64_C(2067791885), // BINSL_W 947 UINT64_C(2079326217), // BINSRI_B 948 UINT64_C(2071986185), // BINSRI_D 949 UINT64_C(2078277641), // BINSRI_H 950 UINT64_C(2076180489), // BINSRI_W 951 UINT64_C(2071986189), // BINSR_B 952 UINT64_C(2078277645), // BINSR_D 953 UINT64_C(2074083341), // BINSR_H 954 UINT64_C(2076180493), // BINSR_W 955 UINT64_C(2080376530), // BITREV 956 UINT64_C(12604), // BITREV_MM 957 UINT64_C(2080374816), // BITSWAP 958 UINT64_C(2876), // BITSWAP_MMR6 959 UINT64_C(402653184), // BLEZ 960 UINT64_C(402653184), // BLEZ64 961 UINT64_C(402653184), // BLEZALC 962 UINT64_C(3221225472), // BLEZALC_MMR6 963 UINT64_C(1476395008), // BLEZC 964 UINT64_C(1476395008), // BLEZC64 965 UINT64_C(4093640704), // BLEZC_MMR6 966 UINT64_C(1476395008), // BLEZL 967 UINT64_C(1082130432), // BLEZ_MM 968 UINT64_C(1543503872), // BLTC 969 UINT64_C(1543503872), // BLTC64 970 UINT64_C(3556769792), // BLTC_MMR6 971 UINT64_C(469762048), // BLTUC 972 UINT64_C(469762048), // BLTUC64 973 UINT64_C(3758096384), // BLTUC_MMR6 974 UINT64_C(67108864), // BLTZ 975 UINT64_C(67108864), // BLTZ64 976 UINT64_C(68157440), // BLTZAL 977 UINT64_C(469762048), // BLTZALC 978 UINT64_C(3758096384), // BLTZALC_MMR6 979 UINT64_C(68288512), // BLTZALL 980 UINT64_C(1109393408), // BLTZALS_MM 981 UINT64_C(1075838976), // BLTZAL_MM 982 UINT64_C(1543503872), // BLTZC 983 UINT64_C(1543503872), // BLTZC64 984 UINT64_C(3556769792), // BLTZC_MMR6 985 UINT64_C(67239936), // BLTZL 986 UINT64_C(1073741824), // BLTZ_MM 987 UINT64_C(2013265921), // BMNZI_B 988 UINT64_C(2021654558), // BMNZ_V 989 UINT64_C(2030043137), // BMZI_B 990 UINT64_C(2023751710), // BMZ_V 991 UINT64_C(335544320), // BNE 992 UINT64_C(335544320), // BNE64 993 UINT64_C(1610612736), // BNEC 994 UINT64_C(1610612736), // BNEC64 995 UINT64_C(2080374784), // BNEC_MMR6 996 UINT64_C(2062549001), // BNEGI_B 997 UINT64_C(2055208969), // BNEGI_D 998 UINT64_C(2061500425), // BNEGI_H 999 UINT64_C(2059403273), // BNEGI_W 1000 UINT64_C(2055208973), // BNEG_B 1001 UINT64_C(2061500429), // BNEG_D 1002 UINT64_C(2057306125), // BNEG_H 1003 UINT64_C(2059403277), // BNEG_W 1004 UINT64_C(1409286144), // BNEL 1005 UINT64_C(44032), // BNEZ16_MM 1006 UINT64_C(1610612736), // BNEZALC 1007 UINT64_C(2080374784), // BNEZALC_MMR6 1008 UINT64_C(4160749568), // BNEZC 1009 UINT64_C(44032), // BNEZC16_MMR6 1010 UINT64_C(4160749568), // BNEZC64 1011 UINT64_C(1084227584), // BNEZC_MM 1012 UINT64_C(2684354560), // BNEZC_MMR6 1013 UINT64_C(3019898880), // BNE_MM 1014 UINT64_C(1610612736), // BNVC 1015 UINT64_C(2080374784), // BNVC_MMR6 1016 UINT64_C(1199570944), // BNZ_B 1017 UINT64_C(1205862400), // BNZ_D 1018 UINT64_C(1201668096), // BNZ_H 1019 UINT64_C(1172307968), // BNZ_V 1020 UINT64_C(1203765248), // BNZ_W 1021 UINT64_C(536870912), // BOVC 1022 UINT64_C(1946157056), // BOVC_MMR6 1023 UINT64_C(68943872), // BPOSGE32 1024 UINT64_C(1126170624), // BPOSGE32C_MMR3 1025 UINT64_C(1130364928), // BPOSGE32_MM 1026 UINT64_C(13), // BREAK 1027 UINT64_C(18048), // BREAK16_MM 1028 UINT64_C(17435), // BREAK16_MMR6 1029 UINT64_C(7), // BREAK_MM 1030 UINT64_C(7), // BREAK_MMR6 1031 UINT64_C(2046820353), // BSELI_B 1032 UINT64_C(2025848862), // BSEL_V 1033 UINT64_C(2054160393), // BSETI_B 1034 UINT64_C(2046820361), // BSETI_D 1035 UINT64_C(2053111817), // BSETI_H 1036 UINT64_C(2051014665), // BSETI_W 1037 UINT64_C(2046820365), // BSET_B 1038 UINT64_C(2053111821), // BSET_D 1039 UINT64_C(2048917517), // BSET_H 1040 UINT64_C(2051014669), // BSET_W 1041 UINT64_C(1191182336), // BZ_B 1042 UINT64_C(1197473792), // BZ_D 1043 UINT64_C(1193279488), // BZ_H 1044 UINT64_C(1163919360), // BZ_V 1045 UINT64_C(1195376640), // BZ_W 1046 UINT64_C(8192), // BeqzRxImm16 1047 UINT64_C(4026540032), // BeqzRxImmX16 1048 UINT64_C(4096), // Bimm16 1049 UINT64_C(4026535936), // BimmX16 1050 UINT64_C(10240), // BnezRxImm16 1051 UINT64_C(4026542080), // BnezRxImmX16 1052 UINT64_C(59397), // Break16 1053 UINT64_C(24576), // Bteqz16 1054 UINT64_C(4026544128), // BteqzX16 1055 UINT64_C(24832), // Btnez16 1056 UINT64_C(4026544384), // BtnezX16 1057 UINT64_C(3154116608), // CACHE 1058 UINT64_C(2080374811), // CACHEE 1059 UINT64_C(1610655232), // CACHEE_MM 1060 UINT64_C(536895488), // CACHE_MM 1061 UINT64_C(536895488), // CACHE_MMR6 1062 UINT64_C(2080374821), // CACHE_R6 1063 UINT64_C(1176502282), // CEIL_L_D64 1064 UINT64_C(1409307451), // CEIL_L_D_MMR6 1065 UINT64_C(1174405130), // CEIL_L_S 1066 UINT64_C(1409291067), // CEIL_L_S_MMR6 1067 UINT64_C(1176502286), // CEIL_W_D32 1068 UINT64_C(1176502286), // CEIL_W_D64 1069 UINT64_C(1409309499), // CEIL_W_D_MMR6 1070 UINT64_C(1409309499), // CEIL_W_MM 1071 UINT64_C(1174405134), // CEIL_W_S 1072 UINT64_C(1409293115), // CEIL_W_S_MM 1073 UINT64_C(1409293115), // CEIL_W_S_MMR6 1074 UINT64_C(2013265927), // CEQI_B 1075 UINT64_C(2019557383), // CEQI_D 1076 UINT64_C(2015363079), // CEQI_H 1077 UINT64_C(2017460231), // CEQI_W 1078 UINT64_C(2013265935), // CEQ_B 1079 UINT64_C(2019557391), // CEQ_D 1080 UINT64_C(2015363087), // CEQ_H 1081 UINT64_C(2017460239), // CEQ_W 1082 UINT64_C(1145044992), // CFC1 1083 UINT64_C(1409290299), // CFC1_MM 1084 UINT64_C(52540), // CFC2_MM 1085 UINT64_C(2021523481), // CFCMSA 1086 UINT64_C(1879048242), // CINS 1087 UINT64_C(1879048243), // CINS32 1088 UINT64_C(1879048242), // CINS64_32 1089 UINT64_C(1879048242), // CINS_i32 1090 UINT64_C(1176502299), // CLASS_D 1091 UINT64_C(1409286752), // CLASS_D_MMR6 1092 UINT64_C(1174405147), // CLASS_S 1093 UINT64_C(1409286240), // CLASS_S_MMR6 1094 UINT64_C(2046820359), // CLEI_S_B 1095 UINT64_C(2053111815), // CLEI_S_D 1096 UINT64_C(2048917511), // CLEI_S_H 1097 UINT64_C(2051014663), // CLEI_S_W 1098 UINT64_C(2055208967), // CLEI_U_B 1099 UINT64_C(2061500423), // CLEI_U_D 1100 UINT64_C(2057306119), // CLEI_U_H 1101 UINT64_C(2059403271), // CLEI_U_W 1102 UINT64_C(2046820367), // CLE_S_B 1103 UINT64_C(2053111823), // CLE_S_D 1104 UINT64_C(2048917519), // CLE_S_H 1105 UINT64_C(2051014671), // CLE_S_W 1106 UINT64_C(2055208975), // CLE_U_B 1107 UINT64_C(2061500431), // CLE_U_D 1108 UINT64_C(2057306127), // CLE_U_H 1109 UINT64_C(2059403279), // CLE_U_W 1110 UINT64_C(1879048225), // CLO 1111 UINT64_C(19260), // CLO_MM 1112 UINT64_C(19260), // CLO_MMR6 1113 UINT64_C(81), // CLO_R6 1114 UINT64_C(2030043143), // CLTI_S_B 1115 UINT64_C(2036334599), // CLTI_S_D 1116 UINT64_C(2032140295), // CLTI_S_H 1117 UINT64_C(2034237447), // CLTI_S_W 1118 UINT64_C(2038431751), // CLTI_U_B 1119 UINT64_C(2044723207), // CLTI_U_D 1120 UINT64_C(2040528903), // CLTI_U_H 1121 UINT64_C(2042626055), // CLTI_U_W 1122 UINT64_C(2030043151), // CLT_S_B 1123 UINT64_C(2036334607), // CLT_S_D 1124 UINT64_C(2032140303), // CLT_S_H 1125 UINT64_C(2034237455), // CLT_S_W 1126 UINT64_C(2038431759), // CLT_U_B 1127 UINT64_C(2044723215), // CLT_U_D 1128 UINT64_C(2040528911), // CLT_U_H 1129 UINT64_C(2042626063), // CLT_U_W 1130 UINT64_C(1879048224), // CLZ 1131 UINT64_C(23356), // CLZ_MM 1132 UINT64_C(80), // CLZ_MMR6 1133 UINT64_C(80), // CLZ_R6 1134 UINT64_C(2080376337), // CMPGDU_EQ_QB 1135 UINT64_C(389), // CMPGDU_EQ_QB_MMR2 1136 UINT64_C(2080376465), // CMPGDU_LE_QB 1137 UINT64_C(517), // CMPGDU_LE_QB_MMR2 1138 UINT64_C(2080376401), // CMPGDU_LT_QB 1139 UINT64_C(453), // CMPGDU_LT_QB_MMR2 1140 UINT64_C(2080375057), // CMPGU_EQ_QB 1141 UINT64_C(1476395205), // CMPGU_EQ_QB_MM 1142 UINT64_C(2080375185), // CMPGU_LE_QB 1143 UINT64_C(1476395333), // CMPGU_LE_QB_MM 1144 UINT64_C(2080375121), // CMPGU_LT_QB 1145 UINT64_C(1476395269), // CMPGU_LT_QB_MM 1146 UINT64_C(2080374801), // CMPU_EQ_QB 1147 UINT64_C(581), // CMPU_EQ_QB_MM 1148 UINT64_C(2080374929), // CMPU_LE_QB 1149 UINT64_C(709), // CMPU_LE_QB_MM 1150 UINT64_C(2080374865), // CMPU_LT_QB 1151 UINT64_C(645), // CMPU_LT_QB_MM 1152 UINT64_C(1409286165), // CMP_AF_D_MMR6 1153 UINT64_C(1409286149), // CMP_AF_S_MMR6 1154 UINT64_C(1184890882), // CMP_EQ_D 1155 UINT64_C(1409286293), // CMP_EQ_D_MMR6 1156 UINT64_C(2080375313), // CMP_EQ_PH 1157 UINT64_C(5), // CMP_EQ_PH_MM 1158 UINT64_C(1182793730), // CMP_EQ_S 1159 UINT64_C(1409286277), // CMP_EQ_S_MMR6 1160 UINT64_C(1184890880), // CMP_F_D 1161 UINT64_C(1182793728), // CMP_F_S 1162 UINT64_C(1184890886), // CMP_LE_D 1163 UINT64_C(1409286549), // CMP_LE_D_MMR6 1164 UINT64_C(2080375441), // CMP_LE_PH 1165 UINT64_C(133), // CMP_LE_PH_MM 1166 UINT64_C(1182793734), // CMP_LE_S 1167 UINT64_C(1409286533), // CMP_LE_S_MMR6 1168 UINT64_C(1184890884), // CMP_LT_D 1169 UINT64_C(1409286421), // CMP_LT_D_MMR6 1170 UINT64_C(2080375377), // CMP_LT_PH 1171 UINT64_C(69), // CMP_LT_PH_MM 1172 UINT64_C(1182793732), // CMP_LT_S 1173 UINT64_C(1409286405), // CMP_LT_S_MMR6 1174 UINT64_C(1184890888), // CMP_SAF_D 1175 UINT64_C(1409286677), // CMP_SAF_D_MMR6 1176 UINT64_C(1182793736), // CMP_SAF_S 1177 UINT64_C(1409286661), // CMP_SAF_S_MMR6 1178 UINT64_C(1184890890), // CMP_SEQ_D 1179 UINT64_C(1409286805), // CMP_SEQ_D_MMR6 1180 UINT64_C(1182793738), // CMP_SEQ_S 1181 UINT64_C(1409286789), // CMP_SEQ_S_MMR6 1182 UINT64_C(1184890894), // CMP_SLE_D 1183 UINT64_C(1409287061), // CMP_SLE_D_MMR6 1184 UINT64_C(1182793742), // CMP_SLE_S 1185 UINT64_C(1409287045), // CMP_SLE_S_MMR6 1186 UINT64_C(1184890892), // CMP_SLT_D 1187 UINT64_C(1409286933), // CMP_SLT_D_MMR6 1188 UINT64_C(1182793740), // CMP_SLT_S 1189 UINT64_C(1409286917), // CMP_SLT_S_MMR6 1190 UINT64_C(1184890891), // CMP_SUEQ_D 1191 UINT64_C(1409286869), // CMP_SUEQ_D_MMR6 1192 UINT64_C(1182793739), // CMP_SUEQ_S 1193 UINT64_C(1409286853), // CMP_SUEQ_S_MMR6 1194 UINT64_C(1184890895), // CMP_SULE_D 1195 UINT64_C(1409287125), // CMP_SULE_D_MMR6 1196 UINT64_C(1182793743), // CMP_SULE_S 1197 UINT64_C(1409287109), // CMP_SULE_S_MMR6 1198 UINT64_C(1184890893), // CMP_SULT_D 1199 UINT64_C(1409286997), // CMP_SULT_D_MMR6 1200 UINT64_C(1182793741), // CMP_SULT_S 1201 UINT64_C(1409286981), // CMP_SULT_S_MMR6 1202 UINT64_C(1184890889), // CMP_SUN_D 1203 UINT64_C(1409286741), // CMP_SUN_D_MMR6 1204 UINT64_C(1182793737), // CMP_SUN_S 1205 UINT64_C(1409286725), // CMP_SUN_S_MMR6 1206 UINT64_C(1184890883), // CMP_UEQ_D 1207 UINT64_C(1409286357), // CMP_UEQ_D_MMR6 1208 UINT64_C(1182793731), // CMP_UEQ_S 1209 UINT64_C(1409286341), // CMP_UEQ_S_MMR6 1210 UINT64_C(1184890887), // CMP_ULE_D 1211 UINT64_C(1409286613), // CMP_ULE_D_MMR6 1212 UINT64_C(1182793735), // CMP_ULE_S 1213 UINT64_C(1409286597), // CMP_ULE_S_MMR6 1214 UINT64_C(1184890885), // CMP_ULT_D 1215 UINT64_C(1409286485), // CMP_ULT_D_MMR6 1216 UINT64_C(1182793733), // CMP_ULT_S 1217 UINT64_C(1409286469), // CMP_ULT_S_MMR6 1218 UINT64_C(1184890881), // CMP_UN_D 1219 UINT64_C(1409286229), // CMP_UN_D_MMR6 1220 UINT64_C(1182793729), // CMP_UN_S 1221 UINT64_C(1409286213), // CMP_UN_S_MMR6 1222 UINT64_C(2021654553), // COPY_S_B 1223 UINT64_C(2025324569), // COPY_S_D 1224 UINT64_C(2023751705), // COPY_S_H 1225 UINT64_C(2024800281), // COPY_S_W 1226 UINT64_C(2025848857), // COPY_U_B 1227 UINT64_C(2027946009), // COPY_U_H 1228 UINT64_C(2028994585), // COPY_U_W 1229 UINT64_C(2080374799), // CRC32B 1230 UINT64_C(2080375055), // CRC32CB 1231 UINT64_C(2080375247), // CRC32CD 1232 UINT64_C(2080375119), // CRC32CH 1233 UINT64_C(2080375183), // CRC32CW 1234 UINT64_C(2080374991), // CRC32D 1235 UINT64_C(2080374863), // CRC32H 1236 UINT64_C(2080374927), // CRC32W 1237 UINT64_C(1153433600), // CTC1 1238 UINT64_C(1409292347), // CTC1_MM 1239 UINT64_C(56636), // CTC2_MM 1240 UINT64_C(2017329177), // CTCMSA 1241 UINT64_C(1174405153), // CVT_D32_S 1242 UINT64_C(1409291131), // CVT_D32_S_MM 1243 UINT64_C(1182793761), // CVT_D32_W 1244 UINT64_C(1409299323), // CVT_D32_W_MM 1245 UINT64_C(1184890913), // CVT_D64_L 1246 UINT64_C(1174405153), // CVT_D64_S 1247 UINT64_C(1409291131), // CVT_D64_S_MM 1248 UINT64_C(1182793761), // CVT_D64_W 1249 UINT64_C(1409299323), // CVT_D64_W_MM 1250 UINT64_C(1409307515), // CVT_D_L_MMR6 1251 UINT64_C(1176502309), // CVT_L_D64 1252 UINT64_C(1409302843), // CVT_L_D64_MM 1253 UINT64_C(1409302843), // CVT_L_D_MMR6 1254 UINT64_C(1174405157), // CVT_L_S 1255 UINT64_C(1409286459), // CVT_L_S_MM 1256 UINT64_C(1409286459), // CVT_L_S_MMR6 1257 UINT64_C(1182793766), // CVT_PS_PW64 1258 UINT64_C(1174405158), // CVT_PS_S64 1259 UINT64_C(1186988068), // CVT_PW_PS64 1260 UINT64_C(1176502304), // CVT_S_D32 1261 UINT64_C(1409293179), // CVT_S_D32_MM 1262 UINT64_C(1176502304), // CVT_S_D64 1263 UINT64_C(1409293179), // CVT_S_D64_MM 1264 UINT64_C(1184890912), // CVT_S_L 1265 UINT64_C(1409309563), // CVT_S_L_MMR6 1266 UINT64_C(1186988072), // CVT_S_PL64 1267 UINT64_C(1186988064), // CVT_S_PU64 1268 UINT64_C(1182793760), // CVT_S_W 1269 UINT64_C(1409301371), // CVT_S_W_MM 1270 UINT64_C(1409301371), // CVT_S_W_MMR6 1271 UINT64_C(1176502308), // CVT_W_D32 1272 UINT64_C(1409304891), // CVT_W_D32_MM 1273 UINT64_C(1176502308), // CVT_W_D64 1274 UINT64_C(1409304891), // CVT_W_D64_MM 1275 UINT64_C(1174405156), // CVT_W_S 1276 UINT64_C(1409288507), // CVT_W_S_MM 1277 UINT64_C(1409288507), // CVT_W_S_MMR6 1278 UINT64_C(1176502322), // C_EQ_D32 1279 UINT64_C(1409287356), // C_EQ_D32_MM 1280 UINT64_C(1176502322), // C_EQ_D64 1281 UINT64_C(1409287356), // C_EQ_D64_MM 1282 UINT64_C(1174405170), // C_EQ_S 1283 UINT64_C(1409286332), // C_EQ_S_MM 1284 UINT64_C(1176502320), // C_F_D32 1285 UINT64_C(1409287228), // C_F_D32_MM 1286 UINT64_C(1176502320), // C_F_D64 1287 UINT64_C(1409287228), // C_F_D64_MM 1288 UINT64_C(1174405168), // C_F_S 1289 UINT64_C(1409286204), // C_F_S_MM 1290 UINT64_C(1176502334), // C_LE_D32 1291 UINT64_C(1409288124), // C_LE_D32_MM 1292 UINT64_C(1176502334), // C_LE_D64 1293 UINT64_C(1409288124), // C_LE_D64_MM 1294 UINT64_C(1174405182), // C_LE_S 1295 UINT64_C(1409287100), // C_LE_S_MM 1296 UINT64_C(1176502332), // C_LT_D32 1297 UINT64_C(1409287996), // C_LT_D32_MM 1298 UINT64_C(1176502332), // C_LT_D64 1299 UINT64_C(1409287996), // C_LT_D64_MM 1300 UINT64_C(1174405180), // C_LT_S 1301 UINT64_C(1409286972), // C_LT_S_MM 1302 UINT64_C(1176502333), // C_NGE_D32 1303 UINT64_C(1409288060), // C_NGE_D32_MM 1304 UINT64_C(1176502333), // C_NGE_D64 1305 UINT64_C(1409288060), // C_NGE_D64_MM 1306 UINT64_C(1174405181), // C_NGE_S 1307 UINT64_C(1409287036), // C_NGE_S_MM 1308 UINT64_C(1176502329), // C_NGLE_D32 1309 UINT64_C(1409287804), // C_NGLE_D32_MM 1310 UINT64_C(1176502329), // C_NGLE_D64 1311 UINT64_C(1409287804), // C_NGLE_D64_MM 1312 UINT64_C(1174405177), // C_NGLE_S 1313 UINT64_C(1409286780), // C_NGLE_S_MM 1314 UINT64_C(1176502331), // C_NGL_D32 1315 UINT64_C(1409287932), // C_NGL_D32_MM 1316 UINT64_C(1176502331), // C_NGL_D64 1317 UINT64_C(1409287932), // C_NGL_D64_MM 1318 UINT64_C(1174405179), // C_NGL_S 1319 UINT64_C(1409286908), // C_NGL_S_MM 1320 UINT64_C(1176502335), // C_NGT_D32 1321 UINT64_C(1409288188), // C_NGT_D32_MM 1322 UINT64_C(1176502335), // C_NGT_D64 1323 UINT64_C(1409288188), // C_NGT_D64_MM 1324 UINT64_C(1174405183), // C_NGT_S 1325 UINT64_C(1409287164), // C_NGT_S_MM 1326 UINT64_C(1176502326), // C_OLE_D32 1327 UINT64_C(1409287612), // C_OLE_D32_MM 1328 UINT64_C(1176502326), // C_OLE_D64 1329 UINT64_C(1409287612), // C_OLE_D64_MM 1330 UINT64_C(1174405174), // C_OLE_S 1331 UINT64_C(1409286588), // C_OLE_S_MM 1332 UINT64_C(1176502324), // C_OLT_D32 1333 UINT64_C(1409287484), // C_OLT_D32_MM 1334 UINT64_C(1176502324), // C_OLT_D64 1335 UINT64_C(1409287484), // C_OLT_D64_MM 1336 UINT64_C(1174405172), // C_OLT_S 1337 UINT64_C(1409286460), // C_OLT_S_MM 1338 UINT64_C(1176502330), // C_SEQ_D32 1339 UINT64_C(1409287868), // C_SEQ_D32_MM 1340 UINT64_C(1176502330), // C_SEQ_D64 1341 UINT64_C(1409287868), // C_SEQ_D64_MM 1342 UINT64_C(1174405178), // C_SEQ_S 1343 UINT64_C(1409286844), // C_SEQ_S_MM 1344 UINT64_C(1176502328), // C_SF_D32 1345 UINT64_C(1409287740), // C_SF_D32_MM 1346 UINT64_C(1176502328), // C_SF_D64 1347 UINT64_C(1409287740), // C_SF_D64_MM 1348 UINT64_C(1174405176), // C_SF_S 1349 UINT64_C(1409286716), // C_SF_S_MM 1350 UINT64_C(1176502323), // C_UEQ_D32 1351 UINT64_C(1409287420), // C_UEQ_D32_MM 1352 UINT64_C(1176502323), // C_UEQ_D64 1353 UINT64_C(1409287420), // C_UEQ_D64_MM 1354 UINT64_C(1174405171), // C_UEQ_S 1355 UINT64_C(1409286396), // C_UEQ_S_MM 1356 UINT64_C(1176502327), // C_ULE_D32 1357 UINT64_C(1409287676), // C_ULE_D32_MM 1358 UINT64_C(1176502327), // C_ULE_D64 1359 UINT64_C(1409287676), // C_ULE_D64_MM 1360 UINT64_C(1174405175), // C_ULE_S 1361 UINT64_C(1409286652), // C_ULE_S_MM 1362 UINT64_C(1176502325), // C_ULT_D32 1363 UINT64_C(1409287548), // C_ULT_D32_MM 1364 UINT64_C(1176502325), // C_ULT_D64 1365 UINT64_C(1409287548), // C_ULT_D64_MM 1366 UINT64_C(1174405173), // C_ULT_S 1367 UINT64_C(1409286524), // C_ULT_S_MM 1368 UINT64_C(1176502321), // C_UN_D32 1369 UINT64_C(1409287292), // C_UN_D32_MM 1370 UINT64_C(1176502321), // C_UN_D64 1371 UINT64_C(1409287292), // C_UN_D64_MM 1372 UINT64_C(1174405169), // C_UN_S 1373 UINT64_C(1409286268), // C_UN_S_MM 1374 UINT64_C(59402), // CmpRxRy16 1375 UINT64_C(28672), // CmpiRxImm16 1376 UINT64_C(4026560512), // CmpiRxImmX16 1377 UINT64_C(44), // DADD 1378 UINT64_C(1610612736), // DADDi 1379 UINT64_C(1677721600), // DADDiu 1380 UINT64_C(45), // DADDu 1381 UINT64_C(67502080), // DAHI 1382 UINT64_C(2080375332), // DALIGN 1383 UINT64_C(69074944), // DATI 1384 UINT64_C(1946157056), // DAUI 1385 UINT64_C(2080374820), // DBITSWAP 1386 UINT64_C(1879048229), // DCLO 1387 UINT64_C(83), // DCLO_R6 1388 UINT64_C(1879048228), // DCLZ 1389 UINT64_C(82), // DCLZ_R6 1390 UINT64_C(158), // DDIV 1391 UINT64_C(159), // DDIVU 1392 UINT64_C(1107296287), // DERET 1393 UINT64_C(58236), // DERET_MM 1394 UINT64_C(58236), // DERET_MMR6 1395 UINT64_C(2080374787), // DEXT 1396 UINT64_C(2080374787), // DEXT64_32 1397 UINT64_C(2080374785), // DEXTM 1398 UINT64_C(2080374786), // DEXTU 1399 UINT64_C(1096835072), // DI 1400 UINT64_C(2080374791), // DINS 1401 UINT64_C(2080374789), // DINSM 1402 UINT64_C(2080374790), // DINSU 1403 UINT64_C(154), // DIV 1404 UINT64_C(155), // DIVU 1405 UINT64_C(408), // DIVU_MMR6 1406 UINT64_C(280), // DIV_MMR6 1407 UINT64_C(2046820370), // DIV_S_B 1408 UINT64_C(2053111826), // DIV_S_D 1409 UINT64_C(2048917522), // DIV_S_H 1410 UINT64_C(2051014674), // DIV_S_W 1411 UINT64_C(2055208978), // DIV_U_B 1412 UINT64_C(2061500434), // DIV_U_D 1413 UINT64_C(2057306130), // DIV_U_H 1414 UINT64_C(2059403282), // DIV_U_W 1415 UINT64_C(18300), // DI_MM 1416 UINT64_C(18300), // DI_MMR6 1417 UINT64_C(21), // DLSA 1418 UINT64_C(21), // DLSA_R6 1419 UINT64_C(1075838976), // DMFC0 1420 UINT64_C(1142947840), // DMFC1 1421 UINT64_C(1210056704), // DMFC2 1422 UINT64_C(1210056704), // DMFC2_OCTEON 1423 UINT64_C(1080033536), // DMFGC0 1424 UINT64_C(222), // DMOD 1425 UINT64_C(223), // DMODU 1426 UINT64_C(1096813505), // DMT 1427 UINT64_C(1084227584), // DMTC0 1428 UINT64_C(1151336448), // DMTC1 1429 UINT64_C(1218445312), // DMTC2 1430 UINT64_C(1218445312), // DMTC2_OCTEON 1431 UINT64_C(1080034048), // DMTGC0 1432 UINT64_C(220), // DMUH 1433 UINT64_C(221), // DMUHU 1434 UINT64_C(1879048195), // DMUL 1435 UINT64_C(28), // DMULT 1436 UINT64_C(29), // DMULTu 1437 UINT64_C(157), // DMULU 1438 UINT64_C(156), // DMUL_R6 1439 UINT64_C(2019557395), // DOTP_S_D 1440 UINT64_C(2015363091), // DOTP_S_H 1441 UINT64_C(2017460243), // DOTP_S_W 1442 UINT64_C(2027946003), // DOTP_U_D 1443 UINT64_C(2023751699), // DOTP_U_H 1444 UINT64_C(2025848851), // DOTP_U_W 1445 UINT64_C(2036334611), // DPADD_S_D 1446 UINT64_C(2032140307), // DPADD_S_H 1447 UINT64_C(2034237459), // DPADD_S_W 1448 UINT64_C(2044723219), // DPADD_U_D 1449 UINT64_C(2040528915), // DPADD_U_H 1450 UINT64_C(2042626067), // DPADD_U_W 1451 UINT64_C(2080376496), // DPAQX_SA_W_PH 1452 UINT64_C(12988), // DPAQX_SA_W_PH_MMR2 1453 UINT64_C(2080376368), // DPAQX_S_W_PH 1454 UINT64_C(8892), // DPAQX_S_W_PH_MMR2 1455 UINT64_C(2080375600), // DPAQ_SA_L_W 1456 UINT64_C(4796), // DPAQ_SA_L_W_MM 1457 UINT64_C(2080375088), // DPAQ_S_W_PH 1458 UINT64_C(700), // DPAQ_S_W_PH_MM 1459 UINT64_C(2080375024), // DPAU_H_QBL 1460 UINT64_C(8380), // DPAU_H_QBL_MM 1461 UINT64_C(2080375280), // DPAU_H_QBR 1462 UINT64_C(12476), // DPAU_H_QBR_MM 1463 UINT64_C(2080375344), // DPAX_W_PH 1464 UINT64_C(4284), // DPAX_W_PH_MMR2 1465 UINT64_C(2080374832), // DPA_W_PH 1466 UINT64_C(188), // DPA_W_PH_MMR2 1467 UINT64_C(1879048237), // DPOP 1468 UINT64_C(2080376560), // DPSQX_SA_W_PH 1469 UINT64_C(14012), // DPSQX_SA_W_PH_MMR2 1470 UINT64_C(2080376432), // DPSQX_S_W_PH 1471 UINT64_C(9916), // DPSQX_S_W_PH_MMR2 1472 UINT64_C(2080375664), // DPSQ_SA_L_W 1473 UINT64_C(5820), // DPSQ_SA_L_W_MM 1474 UINT64_C(2080375152), // DPSQ_S_W_PH 1475 UINT64_C(1724), // DPSQ_S_W_PH_MM 1476 UINT64_C(2053111827), // DPSUB_S_D 1477 UINT64_C(2048917523), // DPSUB_S_H 1478 UINT64_C(2051014675), // DPSUB_S_W 1479 UINT64_C(2061500435), // DPSUB_U_D 1480 UINT64_C(2057306131), // DPSUB_U_H 1481 UINT64_C(2059403283), // DPSUB_U_W 1482 UINT64_C(2080375536), // DPSU_H_QBL 1483 UINT64_C(9404), // DPSU_H_QBL_MM 1484 UINT64_C(2080375792), // DPSU_H_QBR 1485 UINT64_C(13500), // DPSU_H_QBR_MM 1486 UINT64_C(2080375408), // DPSX_W_PH 1487 UINT64_C(5308), // DPSX_W_PH_MMR2 1488 UINT64_C(2080374896), // DPS_W_PH 1489 UINT64_C(1212), // DPS_W_PH_MMR2 1490 UINT64_C(2097210), // DROTR 1491 UINT64_C(2097214), // DROTR32 1492 UINT64_C(86), // DROTRV 1493 UINT64_C(2080374948), // DSBH 1494 UINT64_C(30), // DSDIV 1495 UINT64_C(2080375140), // DSHD 1496 UINT64_C(56), // DSLL 1497 UINT64_C(60), // DSLL32 1498 UINT64_C(60), // DSLL64_32 1499 UINT64_C(20), // DSLLV 1500 UINT64_C(59), // DSRA 1501 UINT64_C(63), // DSRA32 1502 UINT64_C(23), // DSRAV 1503 UINT64_C(58), // DSRL 1504 UINT64_C(62), // DSRL32 1505 UINT64_C(22), // DSRLV 1506 UINT64_C(46), // DSUB 1507 UINT64_C(47), // DSUBu 1508 UINT64_C(31), // DUDIV 1509 UINT64_C(1096810532), // DVP 1510 UINT64_C(1096810497), // DVPE 1511 UINT64_C(6524), // DVP_MMR6 1512 UINT64_C(59418), // DivRxRy16 1513 UINT64_C(59419), // DivuRxRy16 1514 UINT64_C(192), // EHB 1515 UINT64_C(6144), // EHB_MM 1516 UINT64_C(6144), // EHB_MMR6 1517 UINT64_C(1096835104), // EI 1518 UINT64_C(22396), // EI_MM 1519 UINT64_C(22396), // EI_MMR6 1520 UINT64_C(1096813537), // EMT 1521 UINT64_C(1107296280), // ERET 1522 UINT64_C(1107296344), // ERETNC 1523 UINT64_C(127868), // ERETNC_MMR6 1524 UINT64_C(62332), // ERET_MM 1525 UINT64_C(62332), // ERET_MMR6 1526 UINT64_C(1096810500), // EVP 1527 UINT64_C(1096810529), // EVPE 1528 UINT64_C(14716), // EVP_MMR6 1529 UINT64_C(2080374784), // EXT 1530 UINT64_C(2080374968), // EXTP 1531 UINT64_C(2080375480), // EXTPDP 1532 UINT64_C(2080375544), // EXTPDPV 1533 UINT64_C(14524), // EXTPDPV_MM 1534 UINT64_C(13948), // EXTPDP_MM 1535 UINT64_C(2080375032), // EXTPV 1536 UINT64_C(10428), // EXTPV_MM 1537 UINT64_C(9852), // EXTP_MM 1538 UINT64_C(2080375288), // EXTRV_RS_W 1539 UINT64_C(11964), // EXTRV_RS_W_MM 1540 UINT64_C(2080375160), // EXTRV_R_W 1541 UINT64_C(7868), // EXTRV_R_W_MM 1542 UINT64_C(2080375800), // EXTRV_S_H 1543 UINT64_C(16060), // EXTRV_S_H_MM 1544 UINT64_C(2080374904), // EXTRV_W 1545 UINT64_C(3772), // EXTRV_W_MM 1546 UINT64_C(2080375224), // EXTR_RS_W 1547 UINT64_C(11900), // EXTR_RS_W_MM 1548 UINT64_C(2080375096), // EXTR_R_W 1549 UINT64_C(7804), // EXTR_R_W_MM 1550 UINT64_C(2080375736), // EXTR_S_H 1551 UINT64_C(15996), // EXTR_S_H_MM 1552 UINT64_C(2080374840), // EXTR_W 1553 UINT64_C(3708), // EXTR_W_MM 1554 UINT64_C(1879048250), // EXTS 1555 UINT64_C(1879048251), // EXTS32 1556 UINT64_C(44), // EXT_MM 1557 UINT64_C(44), // EXT_MMR6 1558 UINT64_C(1176502277), // FABS_D32 1559 UINT64_C(1409295227), // FABS_D32_MM 1560 UINT64_C(1176502277), // FABS_D64 1561 UINT64_C(1409295227), // FABS_D64_MM 1562 UINT64_C(1174405125), // FABS_S 1563 UINT64_C(1409287035), // FABS_S_MM 1564 UINT64_C(2015363099), // FADD_D 1565 UINT64_C(1176502272), // FADD_D32 1566 UINT64_C(1409286448), // FADD_D32_MM 1567 UINT64_C(1176502272), // FADD_D64 1568 UINT64_C(1409286448), // FADD_D64_MM 1569 UINT64_C(1186988032), // FADD_PS64 1570 UINT64_C(1174405120), // FADD_S 1571 UINT64_C(1409286192), // FADD_S_MM 1572 UINT64_C(1409286192), // FADD_S_MMR6 1573 UINT64_C(2013265947), // FADD_W 1574 UINT64_C(2015363098), // FCAF_D 1575 UINT64_C(2013265946), // FCAF_W 1576 UINT64_C(2023751706), // FCEQ_D 1577 UINT64_C(2021654554), // FCEQ_W 1578 UINT64_C(2065760286), // FCLASS_D 1579 UINT64_C(2065694750), // FCLASS_W 1580 UINT64_C(2040528922), // FCLE_D 1581 UINT64_C(2038431770), // FCLE_W 1582 UINT64_C(2032140314), // FCLT_D 1583 UINT64_C(2030043162), // FCLT_W 1584 UINT64_C(1176502320), // FCMP_D32 1585 UINT64_C(1409287228), // FCMP_D32_MM 1586 UINT64_C(1176502320), // FCMP_D64 1587 UINT64_C(1174405168), // FCMP_S32 1588 UINT64_C(1409286204), // FCMP_S32_MM 1589 UINT64_C(2027946012), // FCNE_D 1590 UINT64_C(2025848860), // FCNE_W 1591 UINT64_C(2019557404), // FCOR_D 1592 UINT64_C(2017460252), // FCOR_W 1593 UINT64_C(2027946010), // FCUEQ_D 1594 UINT64_C(2025848858), // FCUEQ_W 1595 UINT64_C(2044723226), // FCULE_D 1596 UINT64_C(2042626074), // FCULE_W 1597 UINT64_C(2036334618), // FCULT_D 1598 UINT64_C(2034237466), // FCULT_W 1599 UINT64_C(2023751708), // FCUNE_D 1600 UINT64_C(2021654556), // FCUNE_W 1601 UINT64_C(2019557402), // FCUN_D 1602 UINT64_C(2017460250), // FCUN_W 1603 UINT64_C(2027946011), // FDIV_D 1604 UINT64_C(1176502275), // FDIV_D32 1605 UINT64_C(1409286640), // FDIV_D32_MM 1606 UINT64_C(1176502275), // FDIV_D64 1607 UINT64_C(1409286640), // FDIV_D64_MM 1608 UINT64_C(1174405123), // FDIV_S 1609 UINT64_C(1409286384), // FDIV_S_MM 1610 UINT64_C(1409286384), // FDIV_S_MMR6 1611 UINT64_C(2025848859), // FDIV_W 1612 UINT64_C(2046820379), // FEXDO_H 1613 UINT64_C(2048917531), // FEXDO_W 1614 UINT64_C(2044723227), // FEXP2_D 1615 UINT64_C(2042626075), // FEXP2_W 1616 UINT64_C(2066808862), // FEXUPL_D 1617 UINT64_C(2066743326), // FEXUPL_W 1618 UINT64_C(2066939934), // FEXUPR_D 1619 UINT64_C(2066874398), // FEXUPR_W 1620 UINT64_C(2067595294), // FFINT_S_D 1621 UINT64_C(2067529758), // FFINT_S_W 1622 UINT64_C(2067726366), // FFINT_U_D 1623 UINT64_C(2067660830), // FFINT_U_W 1624 UINT64_C(2067071006), // FFQL_D 1625 UINT64_C(2067005470), // FFQL_W 1626 UINT64_C(2067202078), // FFQR_D 1627 UINT64_C(2067136542), // FFQR_W 1628 UINT64_C(2063597598), // FILL_B 1629 UINT64_C(2063794206), // FILL_D 1630 UINT64_C(2063663134), // FILL_H 1631 UINT64_C(2063728670), // FILL_W 1632 UINT64_C(2066677790), // FLOG2_D 1633 UINT64_C(2066612254), // FLOG2_W 1634 UINT64_C(1176502283), // FLOOR_L_D64 1635 UINT64_C(1409303355), // FLOOR_L_D_MMR6 1636 UINT64_C(1174405131), // FLOOR_L_S 1637 UINT64_C(1409286971), // FLOOR_L_S_MMR6 1638 UINT64_C(1176502287), // FLOOR_W_D32 1639 UINT64_C(1176502287), // FLOOR_W_D64 1640 UINT64_C(1409305403), // FLOOR_W_D_MMR6 1641 UINT64_C(1409305403), // FLOOR_W_MM 1642 UINT64_C(1174405135), // FLOOR_W_S 1643 UINT64_C(1409289019), // FLOOR_W_S_MM 1644 UINT64_C(1409289019), // FLOOR_W_S_MMR6 1645 UINT64_C(2032140315), // FMADD_D 1646 UINT64_C(2030043163), // FMADD_W 1647 UINT64_C(2078277659), // FMAX_A_D 1648 UINT64_C(2076180507), // FMAX_A_W 1649 UINT64_C(2074083355), // FMAX_D 1650 UINT64_C(2071986203), // FMAX_W 1651 UINT64_C(2069889051), // FMIN_A_D 1652 UINT64_C(2067791899), // FMIN_A_W 1653 UINT64_C(2065694747), // FMIN_D 1654 UINT64_C(2063597595), // FMIN_W 1655 UINT64_C(1176502278), // FMOV_D32 1656 UINT64_C(1409294459), // FMOV_D32_MM 1657 UINT64_C(1176502278), // FMOV_D64 1658 UINT64_C(1409294459), // FMOV_D64_MM 1659 UINT64_C(1409294459), // FMOV_D_MMR6 1660 UINT64_C(1174405126), // FMOV_S 1661 UINT64_C(1409286267), // FMOV_S_MM 1662 UINT64_C(1409286267), // FMOV_S_MMR6 1663 UINT64_C(2036334619), // FMSUB_D 1664 UINT64_C(2034237467), // FMSUB_W 1665 UINT64_C(2023751707), // FMUL_D 1666 UINT64_C(1176502274), // FMUL_D32 1667 UINT64_C(1409286576), // FMUL_D32_MM 1668 UINT64_C(1176502274), // FMUL_D64 1669 UINT64_C(1409286576), // FMUL_D64_MM 1670 UINT64_C(1186988034), // FMUL_PS64 1671 UINT64_C(1174405122), // FMUL_S 1672 UINT64_C(1409286320), // FMUL_S_MM 1673 UINT64_C(1409286320), // FMUL_S_MMR6 1674 UINT64_C(2021654555), // FMUL_W 1675 UINT64_C(1176502279), // FNEG_D32 1676 UINT64_C(1409297275), // FNEG_D32_MM 1677 UINT64_C(1176502279), // FNEG_D64 1678 UINT64_C(1409297275), // FNEG_D64_MM 1679 UINT64_C(1174405127), // FNEG_S 1680 UINT64_C(1409289083), // FNEG_S_MM 1681 UINT64_C(1409289083), // FNEG_S_MMR6 1682 UINT64_C(2080374792), // FORK 1683 UINT64_C(2066415646), // FRCP_D 1684 UINT64_C(2066350110), // FRCP_W 1685 UINT64_C(2066546718), // FRINT_D 1686 UINT64_C(2066481182), // FRINT_W 1687 UINT64_C(2066284574), // FRSQRT_D 1688 UINT64_C(2066219038), // FRSQRT_W 1689 UINT64_C(2048917530), // FSAF_D 1690 UINT64_C(2046820378), // FSAF_W 1691 UINT64_C(2057306138), // FSEQ_D 1692 UINT64_C(2055208986), // FSEQ_W 1693 UINT64_C(2074083354), // FSLE_D 1694 UINT64_C(2071986202), // FSLE_W 1695 UINT64_C(2065694746), // FSLT_D 1696 UINT64_C(2063597594), // FSLT_W 1697 UINT64_C(2061500444), // FSNE_D 1698 UINT64_C(2059403292), // FSNE_W 1699 UINT64_C(2053111836), // FSOR_D 1700 UINT64_C(2051014684), // FSOR_W 1701 UINT64_C(2066153502), // FSQRT_D 1702 UINT64_C(1176502276), // FSQRT_D32 1703 UINT64_C(1409305147), // FSQRT_D32_MM 1704 UINT64_C(1176502276), // FSQRT_D64 1705 UINT64_C(1409305147), // FSQRT_D64_MM 1706 UINT64_C(1174405124), // FSQRT_S 1707 UINT64_C(1409288763), // FSQRT_S_MM 1708 UINT64_C(2066087966), // FSQRT_W 1709 UINT64_C(2019557403), // FSUB_D 1710 UINT64_C(1176502273), // FSUB_D32 1711 UINT64_C(1409286512), // FSUB_D32_MM 1712 UINT64_C(1176502273), // FSUB_D64 1713 UINT64_C(1409286512), // FSUB_D64_MM 1714 UINT64_C(1186988033), // FSUB_PS64 1715 UINT64_C(1174405121), // FSUB_S 1716 UINT64_C(1409286256), // FSUB_S_MM 1717 UINT64_C(1409286256), // FSUB_S_MMR6 1718 UINT64_C(2017460251), // FSUB_W 1719 UINT64_C(2061500442), // FSUEQ_D 1720 UINT64_C(2059403290), // FSUEQ_W 1721 UINT64_C(2078277658), // FSULE_D 1722 UINT64_C(2076180506), // FSULE_W 1723 UINT64_C(2069889050), // FSULT_D 1724 UINT64_C(2067791898), // FSULT_W 1725 UINT64_C(2057306140), // FSUNE_D 1726 UINT64_C(2055208988), // FSUNE_W 1727 UINT64_C(2053111834), // FSUN_D 1728 UINT64_C(2051014682), // FSUN_W 1729 UINT64_C(2067333150), // FTINT_S_D 1730 UINT64_C(2067267614), // FTINT_S_W 1731 UINT64_C(2067464222), // FTINT_U_D 1732 UINT64_C(2067398686), // FTINT_U_W 1733 UINT64_C(2055208987), // FTQ_H 1734 UINT64_C(2057306139), // FTQ_W 1735 UINT64_C(2065891358), // FTRUNC_S_D 1736 UINT64_C(2065825822), // FTRUNC_S_W 1737 UINT64_C(2066022430), // FTRUNC_U_D 1738 UINT64_C(2065956894), // FTRUNC_U_W 1739 UINT64_C(2080374845), // GINVI 1740 UINT64_C(24956), // GINVI_MMR6 1741 UINT64_C(2080374973), // GINVT 1742 UINT64_C(29052), // GINVT_MMR6 1743 UINT64_C(2053111829), // HADD_S_D 1744 UINT64_C(2048917525), // HADD_S_H 1745 UINT64_C(2051014677), // HADD_S_W 1746 UINT64_C(2061500437), // HADD_U_D 1747 UINT64_C(2057306133), // HADD_U_H 1748 UINT64_C(2059403285), // HADD_U_W 1749 UINT64_C(2069889045), // HSUB_S_D 1750 UINT64_C(2065694741), // HSUB_S_H 1751 UINT64_C(2067791893), // HSUB_S_W 1752 UINT64_C(2078277653), // HSUB_U_D 1753 UINT64_C(2074083349), // HSUB_U_H 1754 UINT64_C(2076180501), // HSUB_U_W 1755 UINT64_C(1107296296), // HYPCALL 1756 UINT64_C(50044), // HYPCALL_MM 1757 UINT64_C(2063597588), // ILVEV_B 1758 UINT64_C(2069889044), // ILVEV_D 1759 UINT64_C(2065694740), // ILVEV_H 1760 UINT64_C(2067791892), // ILVEV_W 1761 UINT64_C(2046820372), // ILVL_B 1762 UINT64_C(2053111828), // ILVL_D 1763 UINT64_C(2048917524), // ILVL_H 1764 UINT64_C(2051014676), // ILVL_W 1765 UINT64_C(2071986196), // ILVOD_B 1766 UINT64_C(2078277652), // ILVOD_D 1767 UINT64_C(2074083348), // ILVOD_H 1768 UINT64_C(2076180500), // ILVOD_W 1769 UINT64_C(2055208980), // ILVR_B 1770 UINT64_C(2061500436), // ILVR_D 1771 UINT64_C(2057306132), // ILVR_H 1772 UINT64_C(2059403284), // ILVR_W 1773 UINT64_C(2080374788), // INS 1774 UINT64_C(2030043161), // INSERT_B 1775 UINT64_C(2033713177), // INSERT_D 1776 UINT64_C(2032140313), // INSERT_H 1777 UINT64_C(2033188889), // INSERT_W 1778 UINT64_C(2080374796), // INSV 1779 UINT64_C(2034237465), // INSVE_B 1780 UINT64_C(2037907481), // INSVE_D 1781 UINT64_C(2036334617), // INSVE_H 1782 UINT64_C(2037383193), // INSVE_W 1783 UINT64_C(16700), // INSV_MM 1784 UINT64_C(12), // INS_MM 1785 UINT64_C(12), // INS_MMR6 1786 UINT64_C(134217728), // J 1787 UINT64_C(201326592), // JAL 1788 UINT64_C(9), // JALR 1789 UINT64_C(17856), // JALR16_MM 1790 UINT64_C(9), // JALR64 1791 UINT64_C(17419), // JALRC16_MMR6 1792 UINT64_C(7996), // JALRC_HB_MMR6 1793 UINT64_C(3900), // JALRC_MMR6 1794 UINT64_C(17888), // JALRS16_MM 1795 UINT64_C(20284), // JALRS_MM 1796 UINT64_C(1033), // JALR_HB 1797 UINT64_C(1033), // JALR_HB64 1798 UINT64_C(3900), // JALR_MM 1799 UINT64_C(1946157056), // JALS_MM 1800 UINT64_C(1946157056), // JALX 1801 UINT64_C(4026531840), // JALX_MM 1802 UINT64_C(4093640704), // JAL_MM 1803 UINT64_C(4160749568), // JIALC 1804 UINT64_C(4160749568), // JIALC64 1805 UINT64_C(2147483648), // JIALC_MMR6 1806 UINT64_C(3623878656), // JIC 1807 UINT64_C(3623878656), // JIC64 1808 UINT64_C(2684354560), // JIC_MMR6 1809 UINT64_C(8), // JR 1810 UINT64_C(17792), // JR16_MM 1811 UINT64_C(8), // JR64 1812 UINT64_C(18176), // JRADDIUSP 1813 UINT64_C(17824), // JRC16_MM 1814 UINT64_C(17411), // JRC16_MMR6 1815 UINT64_C(17427), // JRCADDIUSP_MMR6 1816 UINT64_C(1032), // JR_HB 1817 UINT64_C(1032), // JR_HB64 1818 UINT64_C(1033), // JR_HB64_R6 1819 UINT64_C(1033), // JR_HB_R6 1820 UINT64_C(3900), // JR_MM 1821 UINT64_C(3556769792), // J_MM 1822 UINT64_C(402653184), // Jal16 1823 UINT64_C(402653184), // JalB16 1824 UINT64_C(59424), // JrRa16 1825 UINT64_C(59616), // JrcRa16 1826 UINT64_C(59584), // JrcRx16 1827 UINT64_C(59392), // JumpLinkReg16 1828 UINT64_C(2147483648), // LB 1829 UINT64_C(2147483648), // LB64 1830 UINT64_C(2080374828), // LBE 1831 UINT64_C(1610639360), // LBE_MM 1832 UINT64_C(2048), // LBU16_MM 1833 UINT64_C(2080375178), // LBUX 1834 UINT64_C(549), // LBUX_MM 1835 UINT64_C(335544320), // LBU_MMR6 1836 UINT64_C(469762048), // LB_MM 1837 UINT64_C(469762048), // LB_MMR6 1838 UINT64_C(2415919104), // LBu 1839 UINT64_C(2415919104), // LBu64 1840 UINT64_C(2080374824), // LBuE 1841 UINT64_C(1610637312), // LBuE_MM 1842 UINT64_C(335544320), // LBu_MM 1843 UINT64_C(3690987520), // LD 1844 UINT64_C(3556769792), // LDC1 1845 UINT64_C(3556769792), // LDC164 1846 UINT64_C(3154116608), // LDC1_D64_MMR6 1847 UINT64_C(3154116608), // LDC1_MM_D32 1848 UINT64_C(3154116608), // LDC1_MM_D64 1849 UINT64_C(3623878656), // LDC2 1850 UINT64_C(536879104), // LDC2_MMR6 1851 UINT64_C(1237319680), // LDC2_R6 1852 UINT64_C(3690987520), // LDC3 1853 UINT64_C(2063597575), // LDI_B 1854 UINT64_C(2069889031), // LDI_D 1855 UINT64_C(2065694727), // LDI_H 1856 UINT64_C(2067791879), // LDI_W 1857 UINT64_C(1744830464), // LDL 1858 UINT64_C(3960995840), // LDPC 1859 UINT64_C(1811939328), // LDR 1860 UINT64_C(1275068417), // LDXC1 1861 UINT64_C(1275068417), // LDXC164 1862 UINT64_C(2013265952), // LD_B 1863 UINT64_C(2013265955), // LD_D 1864 UINT64_C(2013265953), // LD_H 1865 UINT64_C(2013265954), // LD_W 1866 UINT64_C(603979776), // LEA_ADDiu 1867 UINT64_C(1677721600), // LEA_ADDiu64 1868 UINT64_C(805306368), // LEA_ADDiu_MM 1869 UINT64_C(2214592512), // LH 1870 UINT64_C(2214592512), // LH64 1871 UINT64_C(2080374829), // LHE 1872 UINT64_C(1610639872), // LHE_MM 1873 UINT64_C(10240), // LHU16_MM 1874 UINT64_C(2080375050), // LHX 1875 UINT64_C(357), // LHX_MM 1876 UINT64_C(1006632960), // LH_MM 1877 UINT64_C(2483027968), // LHu 1878 UINT64_C(2483027968), // LHu64 1879 UINT64_C(2080374825), // LHuE 1880 UINT64_C(1610637824), // LHuE_MM 1881 UINT64_C(872415232), // LHu_MM 1882 UINT64_C(60416), // LI16_MM 1883 UINT64_C(60416), // LI16_MMR6 1884 UINT64_C(3221225472), // LL 1885 UINT64_C(3221225472), // LL64 1886 UINT64_C(2080374838), // LL64_R6 1887 UINT64_C(3489660928), // LLD 1888 UINT64_C(2080374839), // LLD_R6 1889 UINT64_C(2080374830), // LLE 1890 UINT64_C(1610640384), // LLE_MM 1891 UINT64_C(1610625024), // LL_MM 1892 UINT64_C(1610625024), // LL_MMR6 1893 UINT64_C(2080374838), // LL_R6 1894 UINT64_C(5), // LSA 1895 UINT64_C(15), // LSA_MMR6 1896 UINT64_C(5), // LSA_R6 1897 UINT64_C(268435456), // LUI_MMR6 1898 UINT64_C(1275068421), // LUXC1 1899 UINT64_C(1275068421), // LUXC164 1900 UINT64_C(1409286472), // LUXC1_MM 1901 UINT64_C(1006632960), // LUi 1902 UINT64_C(1006632960), // LUi64 1903 UINT64_C(1101004800), // LUi_MM 1904 UINT64_C(2348810240), // LW 1905 UINT64_C(26624), // LW16_MM 1906 UINT64_C(2348810240), // LW64 1907 UINT64_C(3288334336), // LWC1 1908 UINT64_C(2617245696), // LWC1_MM 1909 UINT64_C(3355443200), // LWC2 1910 UINT64_C(536870912), // LWC2_MMR6 1911 UINT64_C(1228931072), // LWC2_R6 1912 UINT64_C(3422552064), // LWC3 1913 UINT64_C(2348810240), // LWDSP 1914 UINT64_C(4227858432), // LWDSP_MM 1915 UINT64_C(2080374831), // LWE 1916 UINT64_C(1610640896), // LWE_MM 1917 UINT64_C(25600), // LWGP_MM 1918 UINT64_C(2281701376), // LWL 1919 UINT64_C(2281701376), // LWL64 1920 UINT64_C(2080374809), // LWLE 1921 UINT64_C(1610638336), // LWLE_MM 1922 UINT64_C(1610612736), // LWL_MM 1923 UINT64_C(17664), // LWM16_MM 1924 UINT64_C(17410), // LWM16_MMR6 1925 UINT64_C(536891392), // LWM32_MM 1926 UINT64_C(3959947264), // LWPC 1927 UINT64_C(2013790208), // LWPC_MMR6 1928 UINT64_C(536875008), // LWP_MM 1929 UINT64_C(2550136832), // LWR 1930 UINT64_C(2550136832), // LWR64 1931 UINT64_C(2080374810), // LWRE 1932 UINT64_C(1610638848), // LWRE_MM 1933 UINT64_C(1610616832), // LWR_MM 1934 UINT64_C(18432), // LWSP_MM 1935 UINT64_C(3960471552), // LWUPC 1936 UINT64_C(1610670080), // LWU_MM 1937 UINT64_C(2080374794), // LWX 1938 UINT64_C(1275068416), // LWXC1 1939 UINT64_C(1409286216), // LWXC1_MM 1940 UINT64_C(280), // LWXS_MM 1941 UINT64_C(421), // LWX_MM 1942 UINT64_C(4227858432), // LW_MM 1943 UINT64_C(4227858432), // LW_MMR6 1944 UINT64_C(2617245696), // LWu 1945 UINT64_C(4026570752), // LbRxRyOffMemX16 1946 UINT64_C(4026572800), // LbuRxRyOffMemX16 1947 UINT64_C(4026572800), // LhRxRyOffMemX16 1948 UINT64_C(4026572800), // LhuRxRyOffMemX16 1949 UINT64_C(26624), // LiRxImm16 1950 UINT64_C(4026558464), // LiRxImmAlignX16 1951 UINT64_C(4026558464), // LiRxImmX16 1952 UINT64_C(45056), // LwRxPcTcp16 1953 UINT64_C(4026576896), // LwRxPcTcpX16 1954 UINT64_C(4026570752), // LwRxRyOffMemX16 1955 UINT64_C(4026568704), // LwRxSpImmX16 1956 UINT64_C(1879048192), // MADD 1957 UINT64_C(1176502296), // MADDF_D 1958 UINT64_C(1409287096), // MADDF_D_MMR6 1959 UINT64_C(1174405144), // MADDF_S 1960 UINT64_C(1409286584), // MADDF_S_MMR6 1961 UINT64_C(2067791900), // MADDR_Q_H 1962 UINT64_C(2069889052), // MADDR_Q_W 1963 UINT64_C(1879048193), // MADDU 1964 UINT64_C(1879048193), // MADDU_DSP 1965 UINT64_C(6844), // MADDU_DSP_MM 1966 UINT64_C(56124), // MADDU_MM 1967 UINT64_C(2021654546), // MADDV_B 1968 UINT64_C(2027946002), // MADDV_D 1969 UINT64_C(2023751698), // MADDV_H 1970 UINT64_C(2025848850), // MADDV_W 1971 UINT64_C(1275068449), // MADD_D32 1972 UINT64_C(1409286153), // MADD_D32_MM 1973 UINT64_C(1275068449), // MADD_D64 1974 UINT64_C(1879048192), // MADD_DSP 1975 UINT64_C(2748), // MADD_DSP_MM 1976 UINT64_C(52028), // MADD_MM 1977 UINT64_C(2034237468), // MADD_Q_H 1978 UINT64_C(2036334620), // MADD_Q_W 1979 UINT64_C(1275068448), // MADD_S 1980 UINT64_C(1409286145), // MADD_S_MM 1981 UINT64_C(2080375856), // MAQ_SA_W_PHL 1982 UINT64_C(14972), // MAQ_SA_W_PHL_MM 1983 UINT64_C(2080375984), // MAQ_SA_W_PHR 1984 UINT64_C(10876), // MAQ_SA_W_PHR_MM 1985 UINT64_C(2080376112), // MAQ_S_W_PHL 1986 UINT64_C(6780), // MAQ_S_W_PHL_MM 1987 UINT64_C(2080376240), // MAQ_S_W_PHR 1988 UINT64_C(2684), // MAQ_S_W_PHR_MM 1989 UINT64_C(1176502303), // MAXA_D 1990 UINT64_C(1409286699), // MAXA_D_MMR6 1991 UINT64_C(1174405151), // MAXA_S 1992 UINT64_C(1409286187), // MAXA_S_MMR6 1993 UINT64_C(2030043142), // MAXI_S_B 1994 UINT64_C(2036334598), // MAXI_S_D 1995 UINT64_C(2032140294), // MAXI_S_H 1996 UINT64_C(2034237446), // MAXI_S_W 1997 UINT64_C(2038431750), // MAXI_U_B 1998 UINT64_C(2044723206), // MAXI_U_D 1999 UINT64_C(2040528902), // MAXI_U_H 2000 UINT64_C(2042626054), // MAXI_U_W 2001 UINT64_C(2063597582), // MAX_A_B 2002 UINT64_C(2069889038), // MAX_A_D 2003 UINT64_C(2065694734), // MAX_A_H 2004 UINT64_C(2067791886), // MAX_A_W 2005 UINT64_C(1176502301), // MAX_D 2006 UINT64_C(1409286667), // MAX_D_MMR6 2007 UINT64_C(1174405149), // MAX_S 2008 UINT64_C(2030043150), // MAX_S_B 2009 UINT64_C(2036334606), // MAX_S_D 2010 UINT64_C(2032140302), // MAX_S_H 2011 UINT64_C(1409286155), // MAX_S_MMR6 2012 UINT64_C(2034237454), // MAX_S_W 2013 UINT64_C(2038431758), // MAX_U_B 2014 UINT64_C(2044723214), // MAX_U_D 2015 UINT64_C(2040528910), // MAX_U_H 2016 UINT64_C(2042626062), // MAX_U_W 2017 UINT64_C(1073741824), // MFC0 2018 UINT64_C(252), // MFC0_MMR6 2019 UINT64_C(1140850688), // MFC1 2020 UINT64_C(1140850688), // MFC1_D64 2021 UINT64_C(1409294395), // MFC1_MM 2022 UINT64_C(1409294395), // MFC1_MMR6 2023 UINT64_C(1207959552), // MFC2 2024 UINT64_C(19772), // MFC2_MMR6 2025 UINT64_C(1080033280), // MFGC0 2026 UINT64_C(1276), // MFGC0_MM 2027 UINT64_C(244), // MFHC0_MMR6 2028 UINT64_C(1147142144), // MFHC1_D32 2029 UINT64_C(1409298491), // MFHC1_D32_MM 2030 UINT64_C(1147142144), // MFHC1_D64 2031 UINT64_C(1409298491), // MFHC1_D64_MM 2032 UINT64_C(36156), // MFHC2_MMR6 2033 UINT64_C(1080034304), // MFHGC0 2034 UINT64_C(1268), // MFHGC0_MM 2035 UINT64_C(16), // MFHI 2036 UINT64_C(17920), // MFHI16_MM 2037 UINT64_C(16), // MFHI64 2038 UINT64_C(16), // MFHI_DSP 2039 UINT64_C(124), // MFHI_DSP_MM 2040 UINT64_C(3452), // MFHI_MM 2041 UINT64_C(18), // MFLO 2042 UINT64_C(17984), // MFLO16_MM 2043 UINT64_C(18), // MFLO64 2044 UINT64_C(18), // MFLO_DSP 2045 UINT64_C(4220), // MFLO_DSP_MM 2046 UINT64_C(7548), // MFLO_MM 2047 UINT64_C(1090519040), // MFTR 2048 UINT64_C(1176502302), // MINA_D 2049 UINT64_C(1409286691), // MINA_D_MMR6 2050 UINT64_C(1174405150), // MINA_S 2051 UINT64_C(1409286179), // MINA_S_MMR6 2052 UINT64_C(2046820358), // MINI_S_B 2053 UINT64_C(2053111814), // MINI_S_D 2054 UINT64_C(2048917510), // MINI_S_H 2055 UINT64_C(2051014662), // MINI_S_W 2056 UINT64_C(2055208966), // MINI_U_B 2057 UINT64_C(2061500422), // MINI_U_D 2058 UINT64_C(2057306118), // MINI_U_H 2059 UINT64_C(2059403270), // MINI_U_W 2060 UINT64_C(2071986190), // MIN_A_B 2061 UINT64_C(2078277646), // MIN_A_D 2062 UINT64_C(2074083342), // MIN_A_H 2063 UINT64_C(2076180494), // MIN_A_W 2064 UINT64_C(1176502300), // MIN_D 2065 UINT64_C(1409286659), // MIN_D_MMR6 2066 UINT64_C(1174405148), // MIN_S 2067 UINT64_C(2046820366), // MIN_S_B 2068 UINT64_C(2053111822), // MIN_S_D 2069 UINT64_C(2048917518), // MIN_S_H 2070 UINT64_C(1409286147), // MIN_S_MMR6 2071 UINT64_C(2051014670), // MIN_S_W 2072 UINT64_C(2055208974), // MIN_U_B 2073 UINT64_C(2061500430), // MIN_U_D 2074 UINT64_C(2057306126), // MIN_U_H 2075 UINT64_C(2059403278), // MIN_U_W 2076 UINT64_C(218), // MOD 2077 UINT64_C(2080375952), // MODSUB 2078 UINT64_C(661), // MODSUB_MM 2079 UINT64_C(219), // MODU 2080 UINT64_C(472), // MODU_MMR6 2081 UINT64_C(344), // MOD_MMR6 2082 UINT64_C(2063597586), // MOD_S_B 2083 UINT64_C(2069889042), // MOD_S_D 2084 UINT64_C(2065694738), // MOD_S_H 2085 UINT64_C(2067791890), // MOD_S_W 2086 UINT64_C(2071986194), // MOD_U_B 2087 UINT64_C(2078277650), // MOD_U_D 2088 UINT64_C(2074083346), // MOD_U_H 2089 UINT64_C(2076180498), // MOD_U_W 2090 UINT64_C(3072), // MOVE16_MM 2091 UINT64_C(3072), // MOVE16_MMR6 2092 UINT64_C(33792), // MOVEP_MM 2093 UINT64_C(17412), // MOVEP_MMR6 2094 UINT64_C(2025717785), // MOVE_V 2095 UINT64_C(1176502289), // MOVF_D32 2096 UINT64_C(1409286688), // MOVF_D32_MM 2097 UINT64_C(1176502289), // MOVF_D64 2098 UINT64_C(1), // MOVF_I 2099 UINT64_C(1), // MOVF_I64 2100 UINT64_C(1409286523), // MOVF_I_MM 2101 UINT64_C(1174405137), // MOVF_S 2102 UINT64_C(1409286176), // MOVF_S_MM 2103 UINT64_C(1176502291), // MOVN_I64_D64 2104 UINT64_C(11), // MOVN_I64_I 2105 UINT64_C(11), // MOVN_I64_I64 2106 UINT64_C(1174405139), // MOVN_I64_S 2107 UINT64_C(1176502291), // MOVN_I_D32 2108 UINT64_C(1409286456), // MOVN_I_D32_MM 2109 UINT64_C(1176502291), // MOVN_I_D64 2110 UINT64_C(11), // MOVN_I_I 2111 UINT64_C(11), // MOVN_I_I64 2112 UINT64_C(24), // MOVN_I_MM 2113 UINT64_C(1174405139), // MOVN_I_S 2114 UINT64_C(1409286200), // MOVN_I_S_MM 2115 UINT64_C(1176567825), // MOVT_D32 2116 UINT64_C(1409286752), // MOVT_D32_MM 2117 UINT64_C(1176567825), // MOVT_D64 2118 UINT64_C(65537), // MOVT_I 2119 UINT64_C(65537), // MOVT_I64 2120 UINT64_C(1409288571), // MOVT_I_MM 2121 UINT64_C(1174470673), // MOVT_S 2122 UINT64_C(1409286240), // MOVT_S_MM 2123 UINT64_C(1176502290), // MOVZ_I64_D64 2124 UINT64_C(10), // MOVZ_I64_I 2125 UINT64_C(10), // MOVZ_I64_I64 2126 UINT64_C(1174405138), // MOVZ_I64_S 2127 UINT64_C(1176502290), // MOVZ_I_D32 2128 UINT64_C(1409286520), // MOVZ_I_D32_MM 2129 UINT64_C(1176502290), // MOVZ_I_D64 2130 UINT64_C(10), // MOVZ_I_I 2131 UINT64_C(10), // MOVZ_I_I64 2132 UINT64_C(88), // MOVZ_I_MM 2133 UINT64_C(1174405138), // MOVZ_I_S 2134 UINT64_C(1409286264), // MOVZ_I_S_MM 2135 UINT64_C(1879048196), // MSUB 2136 UINT64_C(1176502297), // MSUBF_D 2137 UINT64_C(1409287160), // MSUBF_D_MMR6 2138 UINT64_C(1174405145), // MSUBF_S 2139 UINT64_C(1409286648), // MSUBF_S_MMR6 2140 UINT64_C(2071986204), // MSUBR_Q_H 2141 UINT64_C(2074083356), // MSUBR_Q_W 2142 UINT64_C(1879048197), // MSUBU 2143 UINT64_C(1879048197), // MSUBU_DSP 2144 UINT64_C(15036), // MSUBU_DSP_MM 2145 UINT64_C(64316), // MSUBU_MM 2146 UINT64_C(2030043154), // MSUBV_B 2147 UINT64_C(2036334610), // MSUBV_D 2148 UINT64_C(2032140306), // MSUBV_H 2149 UINT64_C(2034237458), // MSUBV_W 2150 UINT64_C(1275068457), // MSUB_D32 2151 UINT64_C(1409286185), // MSUB_D32_MM 2152 UINT64_C(1275068457), // MSUB_D64 2153 UINT64_C(1879048196), // MSUB_DSP 2154 UINT64_C(10940), // MSUB_DSP_MM 2155 UINT64_C(60220), // MSUB_MM 2156 UINT64_C(2038431772), // MSUB_Q_H 2157 UINT64_C(2040528924), // MSUB_Q_W 2158 UINT64_C(1275068456), // MSUB_S 2159 UINT64_C(1409286177), // MSUB_S_MM 2160 UINT64_C(1082130432), // MTC0 2161 UINT64_C(764), // MTC0_MMR6 2162 UINT64_C(1149239296), // MTC1 2163 UINT64_C(1149239296), // MTC1_D64 2164 UINT64_C(1409296443), // MTC1_D64_MM 2165 UINT64_C(1409296443), // MTC1_MM 2166 UINT64_C(1409296443), // MTC1_MMR6 2167 UINT64_C(1216348160), // MTC2 2168 UINT64_C(23868), // MTC2_MMR6 2169 UINT64_C(1080033792), // MTGC0 2170 UINT64_C(1788), // MTGC0_MM 2171 UINT64_C(756), // MTHC0_MMR6 2172 UINT64_C(1155530752), // MTHC1_D32 2173 UINT64_C(1409300539), // MTHC1_D32_MM 2174 UINT64_C(1155530752), // MTHC1_D64 2175 UINT64_C(1409300539), // MTHC1_D64_MM 2176 UINT64_C(40252), // MTHC2_MMR6 2177 UINT64_C(1080034816), // MTHGC0 2178 UINT64_C(1780), // MTHGC0_MM 2179 UINT64_C(17), // MTHI 2180 UINT64_C(17), // MTHI64 2181 UINT64_C(17), // MTHI_DSP 2182 UINT64_C(8316), // MTHI_DSP_MM 2183 UINT64_C(11644), // MTHI_MM 2184 UINT64_C(2080376824), // MTHLIP 2185 UINT64_C(636), // MTHLIP_MM 2186 UINT64_C(19), // MTLO 2187 UINT64_C(19), // MTLO64 2188 UINT64_C(19), // MTLO_DSP 2189 UINT64_C(12412), // MTLO_DSP_MM 2190 UINT64_C(15740), // MTLO_MM 2191 UINT64_C(1879048200), // MTM0 2192 UINT64_C(1879048204), // MTM1 2193 UINT64_C(1879048205), // MTM2 2194 UINT64_C(1879048201), // MTP0 2195 UINT64_C(1879048202), // MTP1 2196 UINT64_C(1879048203), // MTP2 2197 UINT64_C(1098907648), // MTTR 2198 UINT64_C(216), // MUH 2199 UINT64_C(217), // MUHU 2200 UINT64_C(216), // MUHU_MMR6 2201 UINT64_C(88), // MUH_MMR6 2202 UINT64_C(1879048194), // MUL 2203 UINT64_C(2080376592), // MULEQ_S_W_PHL 2204 UINT64_C(37), // MULEQ_S_W_PHL_MM 2205 UINT64_C(2080376656), // MULEQ_S_W_PHR 2206 UINT64_C(101), // MULEQ_S_W_PHR_MM 2207 UINT64_C(2080375184), // MULEU_S_PH_QBL 2208 UINT64_C(149), // MULEU_S_PH_QBL_MM 2209 UINT64_C(2080375248), // MULEU_S_PH_QBR 2210 UINT64_C(213), // MULEU_S_PH_QBR_MM 2211 UINT64_C(2080376784), // MULQ_RS_PH 2212 UINT64_C(277), // MULQ_RS_PH_MM 2213 UINT64_C(2080376280), // MULQ_RS_W 2214 UINT64_C(405), // MULQ_RS_W_MMR2 2215 UINT64_C(2080376720), // MULQ_S_PH 2216 UINT64_C(341), // MULQ_S_PH_MMR2 2217 UINT64_C(2080376216), // MULQ_S_W 2218 UINT64_C(469), // MULQ_S_W_MMR2 2219 UINT64_C(1186988058), // MULR_PS64 2220 UINT64_C(2063597596), // MULR_Q_H 2221 UINT64_C(2065694748), // MULR_Q_W 2222 UINT64_C(2080375216), // MULSAQ_S_W_PH 2223 UINT64_C(15548), // MULSAQ_S_W_PH_MM 2224 UINT64_C(2080374960), // MULSA_W_PH 2225 UINT64_C(11452), // MULSA_W_PH_MMR2 2226 UINT64_C(24), // MULT 2227 UINT64_C(25), // MULTU_DSP 2228 UINT64_C(7356), // MULTU_DSP_MM 2229 UINT64_C(24), // MULT_DSP 2230 UINT64_C(3260), // MULT_DSP_MM 2231 UINT64_C(35644), // MULT_MM 2232 UINT64_C(25), // MULTu 2233 UINT64_C(39740), // MULTu_MM 2234 UINT64_C(153), // MULU 2235 UINT64_C(152), // MULU_MMR6 2236 UINT64_C(2013265938), // MULV_B 2237 UINT64_C(2019557394), // MULV_D 2238 UINT64_C(2015363090), // MULV_H 2239 UINT64_C(2017460242), // MULV_W 2240 UINT64_C(528), // MUL_MM 2241 UINT64_C(24), // MUL_MMR6 2242 UINT64_C(2080375576), // MUL_PH 2243 UINT64_C(45), // MUL_PH_MMR2 2244 UINT64_C(2030043164), // MUL_Q_H 2245 UINT64_C(2032140316), // MUL_Q_W 2246 UINT64_C(152), // MUL_R6 2247 UINT64_C(2080375704), // MUL_S_PH 2248 UINT64_C(1069), // MUL_S_PH_MMR2 2249 UINT64_C(59408), // Mfhi16 2250 UINT64_C(59410), // Mflo16 2251 UINT64_C(25856), // Move32R16 2252 UINT64_C(26368), // MoveR3216 2253 UINT64_C(2064121886), // NLOC_B 2254 UINT64_C(2064318494), // NLOC_D 2255 UINT64_C(2064187422), // NLOC_H 2256 UINT64_C(2064252958), // NLOC_W 2257 UINT64_C(2064384030), // NLZC_B 2258 UINT64_C(2064580638), // NLZC_D 2259 UINT64_C(2064449566), // NLZC_H 2260 UINT64_C(2064515102), // NLZC_W 2261 UINT64_C(1275068465), // NMADD_D32 2262 UINT64_C(1409286154), // NMADD_D32_MM 2263 UINT64_C(1275068465), // NMADD_D64 2264 UINT64_C(1275068464), // NMADD_S 2265 UINT64_C(1409286146), // NMADD_S_MM 2266 UINT64_C(1275068473), // NMSUB_D32 2267 UINT64_C(1409286186), // NMSUB_D32_MM 2268 UINT64_C(1275068473), // NMSUB_D64 2269 UINT64_C(1275068472), // NMSUB_S 2270 UINT64_C(1409286178), // NMSUB_S_MM 2271 UINT64_C(39), // NOR 2272 UINT64_C(39), // NOR64 2273 UINT64_C(2046820352), // NORI_B 2274 UINT64_C(720), // NOR_MM 2275 UINT64_C(720), // NOR_MMR6 2276 UINT64_C(2017460254), // NOR_V 2277 UINT64_C(17408), // NOT16_MM 2278 UINT64_C(17408), // NOT16_MMR6 2279 UINT64_C(59421), // NegRxRy16 2280 UINT64_C(59407), // NotRxRy16 2281 UINT64_C(37), // OR 2282 UINT64_C(17600), // OR16_MM 2283 UINT64_C(17417), // OR16_MMR6 2284 UINT64_C(37), // OR64 2285 UINT64_C(2030043136), // ORI_B 2286 UINT64_C(1342177280), // ORI_MMR6 2287 UINT64_C(656), // OR_MM 2288 UINT64_C(656), // OR_MMR6 2289 UINT64_C(2015363102), // OR_V 2290 UINT64_C(872415232), // ORi 2291 UINT64_C(872415232), // ORi64 2292 UINT64_C(1342177280), // ORi_MM 2293 UINT64_C(59405), // OrRxRxRy16 2294 UINT64_C(2080375697), // PACKRL_PH 2295 UINT64_C(429), // PACKRL_PH_MM 2296 UINT64_C(320), // PAUSE 2297 UINT64_C(10240), // PAUSE_MM 2298 UINT64_C(10240), // PAUSE_MMR6 2299 UINT64_C(2030043156), // PCKEV_B 2300 UINT64_C(2036334612), // PCKEV_D 2301 UINT64_C(2032140308), // PCKEV_H 2302 UINT64_C(2034237460), // PCKEV_W 2303 UINT64_C(2038431764), // PCKOD_B 2304 UINT64_C(2044723220), // PCKOD_D 2305 UINT64_C(2040528916), // PCKOD_H 2306 UINT64_C(2042626068), // PCKOD_W 2307 UINT64_C(2063859742), // PCNT_B 2308 UINT64_C(2064056350), // PCNT_D 2309 UINT64_C(2063925278), // PCNT_H 2310 UINT64_C(2063990814), // PCNT_W 2311 UINT64_C(2080375505), // PICK_PH 2312 UINT64_C(557), // PICK_PH_MM 2313 UINT64_C(2080374993), // PICK_QB 2314 UINT64_C(493), // PICK_QB_MM 2315 UINT64_C(1186988076), // PLL_PS64 2316 UINT64_C(1186988077), // PLU_PS64 2317 UINT64_C(1879048236), // POP 2318 UINT64_C(2080375058), // PRECEQU_PH_QBL 2319 UINT64_C(2080375186), // PRECEQU_PH_QBLA 2320 UINT64_C(29500), // PRECEQU_PH_QBLA_MM 2321 UINT64_C(28988), // PRECEQU_PH_QBL_MM 2322 UINT64_C(2080375122), // PRECEQU_PH_QBR 2323 UINT64_C(2080375250), // PRECEQU_PH_QBRA 2324 UINT64_C(37692), // PRECEQU_PH_QBRA_MM 2325 UINT64_C(37180), // PRECEQU_PH_QBR_MM 2326 UINT64_C(2080375570), // PRECEQ_W_PHL 2327 UINT64_C(20796), // PRECEQ_W_PHL_MM 2328 UINT64_C(2080375634), // PRECEQ_W_PHR 2329 UINT64_C(24892), // PRECEQ_W_PHR_MM 2330 UINT64_C(2080376594), // PRECEU_PH_QBL 2331 UINT64_C(2080376722), // PRECEU_PH_QBLA 2332 UINT64_C(45884), // PRECEU_PH_QBLA_MM 2333 UINT64_C(45372), // PRECEU_PH_QBL_MM 2334 UINT64_C(2080376658), // PRECEU_PH_QBR 2335 UINT64_C(2080376786), // PRECEU_PH_QBRA 2336 UINT64_C(54076), // PRECEU_PH_QBRA_MM 2337 UINT64_C(53564), // PRECEU_PH_QBR_MM 2338 UINT64_C(2080375761), // PRECRQU_S_QB_PH 2339 UINT64_C(365), // PRECRQU_S_QB_PH_MM 2340 UINT64_C(2080376081), // PRECRQ_PH_W 2341 UINT64_C(237), // PRECRQ_PH_W_MM 2342 UINT64_C(2080375569), // PRECRQ_QB_PH 2343 UINT64_C(173), // PRECRQ_QB_PH_MM 2344 UINT64_C(2080376145), // PRECRQ_RS_PH_W 2345 UINT64_C(301), // PRECRQ_RS_PH_W_MM 2346 UINT64_C(2080375633), // PRECR_QB_PH 2347 UINT64_C(109), // PRECR_QB_PH_MMR2 2348 UINT64_C(2080376721), // PRECR_SRA_PH_W 2349 UINT64_C(973), // PRECR_SRA_PH_W_MMR2 2350 UINT64_C(2080376785), // PRECR_SRA_R_PH_W 2351 UINT64_C(1997), // PRECR_SRA_R_PH_W_MMR2 2352 UINT64_C(3422552064), // PREF 2353 UINT64_C(2080374819), // PREFE 2354 UINT64_C(1610654720), // PREFE_MM 2355 UINT64_C(1409286560), // PREFX_MM 2356 UINT64_C(1610620928), // PREF_MM 2357 UINT64_C(1610620928), // PREF_MMR6 2358 UINT64_C(2080374837), // PREF_R6 2359 UINT64_C(2080374897), // PREPEND 2360 UINT64_C(597), // PREPEND_MMR2 2361 UINT64_C(1186988078), // PUL_PS64 2362 UINT64_C(1186988079), // PUU_PS64 2363 UINT64_C(2080376080), // RADDU_W_QB 2364 UINT64_C(61756), // RADDU_W_QB_MM 2365 UINT64_C(2080375992), // RDDSP 2366 UINT64_C(1660), // RDDSP_MM 2367 UINT64_C(2080374843), // RDHWR 2368 UINT64_C(2080374843), // RDHWR64 2369 UINT64_C(27452), // RDHWR_MM 2370 UINT64_C(448), // RDHWR_MMR6 2371 UINT64_C(57724), // RDPGPR_MMR6 2372 UINT64_C(1176502293), // RECIP_D32 2373 UINT64_C(1409307195), // RECIP_D32_MM 2374 UINT64_C(1176502293), // RECIP_D64 2375 UINT64_C(1409307195), // RECIP_D64_MM 2376 UINT64_C(1174405141), // RECIP_S 2377 UINT64_C(1409290811), // RECIP_S_MM 2378 UINT64_C(2080375506), // REPLV_PH 2379 UINT64_C(828), // REPLV_PH_MM 2380 UINT64_C(2080374994), // REPLV_QB 2381 UINT64_C(4924), // REPLV_QB_MM 2382 UINT64_C(2080375442), // REPL_PH 2383 UINT64_C(61), // REPL_PH_MM 2384 UINT64_C(2080374930), // REPL_QB 2385 UINT64_C(1532), // REPL_QB_MM 2386 UINT64_C(1176502298), // RINT_D 2387 UINT64_C(1409286688), // RINT_D_MMR6 2388 UINT64_C(1174405146), // RINT_S 2389 UINT64_C(1409286176), // RINT_S_MMR6 2390 UINT64_C(2097154), // ROTR 2391 UINT64_C(70), // ROTRV 2392 UINT64_C(208), // ROTRV_MM 2393 UINT64_C(192), // ROTR_MM 2394 UINT64_C(1176502280), // ROUND_L_D64 2395 UINT64_C(1409315643), // ROUND_L_D_MMR6 2396 UINT64_C(1174405128), // ROUND_L_S 2397 UINT64_C(1409299259), // ROUND_L_S_MMR6 2398 UINT64_C(1176502284), // ROUND_W_D32 2399 UINT64_C(1176502284), // ROUND_W_D64 2400 UINT64_C(1409317691), // ROUND_W_D_MMR6 2401 UINT64_C(1409317691), // ROUND_W_MM 2402 UINT64_C(1174405132), // ROUND_W_S 2403 UINT64_C(1409301307), // ROUND_W_S_MM 2404 UINT64_C(1409301307), // ROUND_W_S_MMR6 2405 UINT64_C(1176502294), // RSQRT_D32 2406 UINT64_C(1409303099), // RSQRT_D32_MM 2407 UINT64_C(1176502294), // RSQRT_D64 2408 UINT64_C(1409303099), // RSQRT_D64_MM 2409 UINT64_C(1174405142), // RSQRT_S 2410 UINT64_C(1409286715), // RSQRT_S_MM 2411 UINT64_C(25728), // Restore16 2412 UINT64_C(25728), // RestoreX16 2413 UINT64_C(1879048216), // SAA 2414 UINT64_C(1879048217), // SAAD 2415 UINT64_C(2020605962), // SAT_S_B 2416 UINT64_C(2013265930), // SAT_S_D 2417 UINT64_C(2019557386), // SAT_S_H 2418 UINT64_C(2017460234), // SAT_S_W 2419 UINT64_C(2028994570), // SAT_U_B 2420 UINT64_C(2021654538), // SAT_U_D 2421 UINT64_C(2027945994), // SAT_U_H 2422 UINT64_C(2025848842), // SAT_U_W 2423 UINT64_C(2684354560), // SB 2424 UINT64_C(34816), // SB16_MM 2425 UINT64_C(34816), // SB16_MMR6 2426 UINT64_C(2684354560), // SB64 2427 UINT64_C(2080374812), // SBE 2428 UINT64_C(1610655744), // SBE_MM 2429 UINT64_C(402653184), // SB_MM 2430 UINT64_C(402653184), // SB_MMR6 2431 UINT64_C(3758096384), // SC 2432 UINT64_C(3758096384), // SC64 2433 UINT64_C(2080374822), // SC64_R6 2434 UINT64_C(4026531840), // SCD 2435 UINT64_C(2080374823), // SCD_R6 2436 UINT64_C(2080374814), // SCE 2437 UINT64_C(1610656768), // SCE_MM 2438 UINT64_C(1610657792), // SC_MM 2439 UINT64_C(1610657792), // SC_MMR6 2440 UINT64_C(2080374822), // SC_R6 2441 UINT64_C(4227858432), // SD 2442 UINT64_C(1879048255), // SDBBP 2443 UINT64_C(18112), // SDBBP16_MM 2444 UINT64_C(17467), // SDBBP16_MMR6 2445 UINT64_C(56188), // SDBBP_MM 2446 UINT64_C(56188), // SDBBP_MMR6 2447 UINT64_C(14), // SDBBP_R6 2448 UINT64_C(4093640704), // SDC1 2449 UINT64_C(4093640704), // SDC164 2450 UINT64_C(3087007744), // SDC1_D64_MMR6 2451 UINT64_C(3087007744), // SDC1_MM_D32 2452 UINT64_C(3087007744), // SDC1_MM_D64 2453 UINT64_C(4160749568), // SDC2 2454 UINT64_C(536911872), // SDC2_MMR6 2455 UINT64_C(1239416832), // SDC2_R6 2456 UINT64_C(4227858432), // SDC3 2457 UINT64_C(26), // SDIV 2458 UINT64_C(43836), // SDIV_MM 2459 UINT64_C(2952790016), // SDL 2460 UINT64_C(3019898880), // SDR 2461 UINT64_C(1275068425), // SDXC1 2462 UINT64_C(1275068425), // SDXC164 2463 UINT64_C(2080375840), // SEB 2464 UINT64_C(2080375840), // SEB64 2465 UINT64_C(11068), // SEB_MM 2466 UINT64_C(2080376352), // SEH 2467 UINT64_C(2080376352), // SEH64 2468 UINT64_C(15164), // SEH_MM 2469 UINT64_C(53), // SELEQZ 2470 UINT64_C(53), // SELEQZ64 2471 UINT64_C(1176502292), // SELEQZ_D 2472 UINT64_C(1409286712), // SELEQZ_D_MMR6 2473 UINT64_C(320), // SELEQZ_MMR6 2474 UINT64_C(1174405140), // SELEQZ_S 2475 UINT64_C(1409286200), // SELEQZ_S_MMR6 2476 UINT64_C(55), // SELNEZ 2477 UINT64_C(55), // SELNEZ64 2478 UINT64_C(1176502295), // SELNEZ_D 2479 UINT64_C(1409286776), // SELNEZ_D_MMR6 2480 UINT64_C(384), // SELNEZ_MMR6 2481 UINT64_C(1174405143), // SELNEZ_S 2482 UINT64_C(1409286264), // SELNEZ_S_MMR6 2483 UINT64_C(1176502288), // SEL_D 2484 UINT64_C(1409286840), // SEL_D_MMR6 2485 UINT64_C(1174405136), // SEL_S 2486 UINT64_C(1409286328), // SEL_S_MMR6 2487 UINT64_C(1879048234), // SEQ 2488 UINT64_C(1879048238), // SEQi 2489 UINT64_C(2751463424), // SH 2490 UINT64_C(43008), // SH16_MM 2491 UINT64_C(43008), // SH16_MMR6 2492 UINT64_C(2751463424), // SH64 2493 UINT64_C(2080374813), // SHE 2494 UINT64_C(1610656256), // SHE_MM 2495 UINT64_C(2013265922), // SHF_B 2496 UINT64_C(2030043138), // SHF_H 2497 UINT64_C(2046820354), // SHF_W 2498 UINT64_C(2080376504), // SHILO 2499 UINT64_C(2080376568), // SHILOV 2500 UINT64_C(4732), // SHILOV_MM 2501 UINT64_C(29), // SHILO_MM 2502 UINT64_C(2080375443), // SHLLV_PH 2503 UINT64_C(14), // SHLLV_PH_MM 2504 UINT64_C(2080374931), // SHLLV_QB 2505 UINT64_C(917), // SHLLV_QB_MM 2506 UINT64_C(2080375699), // SHLLV_S_PH 2507 UINT64_C(1038), // SHLLV_S_PH_MM 2508 UINT64_C(2080376211), // SHLLV_S_W 2509 UINT64_C(981), // SHLLV_S_W_MM 2510 UINT64_C(2080375315), // SHLL_PH 2511 UINT64_C(949), // SHLL_PH_MM 2512 UINT64_C(2080374803), // SHLL_QB 2513 UINT64_C(2172), // SHLL_QB_MM 2514 UINT64_C(2080375571), // SHLL_S_PH 2515 UINT64_C(2997), // SHLL_S_PH_MM 2516 UINT64_C(2080376083), // SHLL_S_W 2517 UINT64_C(1013), // SHLL_S_W_MM 2518 UINT64_C(2080375507), // SHRAV_PH 2519 UINT64_C(397), // SHRAV_PH_MM 2520 UINT64_C(2080375187), // SHRAV_QB 2521 UINT64_C(461), // SHRAV_QB_MMR2 2522 UINT64_C(2080375763), // SHRAV_R_PH 2523 UINT64_C(1421), // SHRAV_R_PH_MM 2524 UINT64_C(2080375251), // SHRAV_R_QB 2525 UINT64_C(1485), // SHRAV_R_QB_MMR2 2526 UINT64_C(2080376275), // SHRAV_R_W 2527 UINT64_C(725), // SHRAV_R_W_MM 2528 UINT64_C(2080375379), // SHRA_PH 2529 UINT64_C(821), // SHRA_PH_MM 2530 UINT64_C(2080375059), // SHRA_QB 2531 UINT64_C(508), // SHRA_QB_MMR2 2532 UINT64_C(2080375635), // SHRA_R_PH 2533 UINT64_C(1845), // SHRA_R_PH_MM 2534 UINT64_C(2080375123), // SHRA_R_QB 2535 UINT64_C(4604), // SHRA_R_QB_MMR2 2536 UINT64_C(2080376147), // SHRA_R_W 2537 UINT64_C(757), // SHRA_R_W_MM 2538 UINT64_C(2080376531), // SHRLV_PH 2539 UINT64_C(789), // SHRLV_PH_MMR2 2540 UINT64_C(2080374995), // SHRLV_QB 2541 UINT64_C(853), // SHRLV_QB_MM 2542 UINT64_C(2080376403), // SHRL_PH 2543 UINT64_C(1020), // SHRL_PH_MMR2 2544 UINT64_C(2080374867), // SHRL_QB 2545 UINT64_C(6268), // SHRL_QB_MM 2546 UINT64_C(939524096), // SH_MM 2547 UINT64_C(939524096), // SH_MMR6 2548 UINT64_C(68616192), // SIGRIE 2549 UINT64_C(63), // SIGRIE_MMR6 2550 UINT64_C(2013265945), // SLDI_B 2551 UINT64_C(2016935961), // SLDI_D 2552 UINT64_C(2015363097), // SLDI_H 2553 UINT64_C(2016411673), // SLDI_W 2554 UINT64_C(2013265940), // SLD_B 2555 UINT64_C(2019557396), // SLD_D 2556 UINT64_C(2015363092), // SLD_H 2557 UINT64_C(2017460244), // SLD_W 2558 UINT64_C(0), // SLL 2559 UINT64_C(9216), // SLL16_MM 2560 UINT64_C(9216), // SLL16_MMR6 2561 UINT64_C(0), // SLL64_32 2562 UINT64_C(0), // SLL64_64 2563 UINT64_C(2020605961), // SLLI_B 2564 UINT64_C(2013265929), // SLLI_D 2565 UINT64_C(2019557385), // SLLI_H 2566 UINT64_C(2017460233), // SLLI_W 2567 UINT64_C(4), // SLLV 2568 UINT64_C(16), // SLLV_MM 2569 UINT64_C(2013265933), // SLL_B 2570 UINT64_C(2019557389), // SLL_D 2571 UINT64_C(2015363085), // SLL_H 2572 UINT64_C(0), // SLL_MM 2573 UINT64_C(0), // SLL_MMR6 2574 UINT64_C(2017460237), // SLL_W 2575 UINT64_C(42), // SLT 2576 UINT64_C(42), // SLT64 2577 UINT64_C(848), // SLT_MM 2578 UINT64_C(671088640), // SLTi 2579 UINT64_C(671088640), // SLTi64 2580 UINT64_C(2415919104), // SLTi_MM 2581 UINT64_C(738197504), // SLTiu 2582 UINT64_C(738197504), // SLTiu64 2583 UINT64_C(2952790016), // SLTiu_MM 2584 UINT64_C(43), // SLTu 2585 UINT64_C(43), // SLTu64 2586 UINT64_C(912), // SLTu_MM 2587 UINT64_C(1879048235), // SNE 2588 UINT64_C(1879048239), // SNEi 2589 UINT64_C(2017460249), // SPLATI_B 2590 UINT64_C(2021130265), // SPLATI_D 2591 UINT64_C(2019557401), // SPLATI_H 2592 UINT64_C(2020605977), // SPLATI_W 2593 UINT64_C(2021654548), // SPLAT_B 2594 UINT64_C(2027946004), // SPLAT_D 2595 UINT64_C(2023751700), // SPLAT_H 2596 UINT64_C(2025848852), // SPLAT_W 2597 UINT64_C(3), // SRA 2598 UINT64_C(2028994569), // SRAI_B 2599 UINT64_C(2021654537), // SRAI_D 2600 UINT64_C(2027945993), // SRAI_H 2601 UINT64_C(2025848841), // SRAI_W 2602 UINT64_C(2037383178), // SRARI_B 2603 UINT64_C(2030043146), // SRARI_D 2604 UINT64_C(2036334602), // SRARI_H 2605 UINT64_C(2034237450), // SRARI_W 2606 UINT64_C(2021654549), // SRAR_B 2607 UINT64_C(2027946005), // SRAR_D 2608 UINT64_C(2023751701), // SRAR_H 2609 UINT64_C(2025848853), // SRAR_W 2610 UINT64_C(7), // SRAV 2611 UINT64_C(144), // SRAV_MM 2612 UINT64_C(2021654541), // SRA_B 2613 UINT64_C(2027945997), // SRA_D 2614 UINT64_C(2023751693), // SRA_H 2615 UINT64_C(128), // SRA_MM 2616 UINT64_C(2025848845), // SRA_W 2617 UINT64_C(2), // SRL 2618 UINT64_C(9217), // SRL16_MM 2619 UINT64_C(9217), // SRL16_MMR6 2620 UINT64_C(2037383177), // SRLI_B 2621 UINT64_C(2030043145), // SRLI_D 2622 UINT64_C(2036334601), // SRLI_H 2623 UINT64_C(2034237449), // SRLI_W 2624 UINT64_C(2045771786), // SRLRI_B 2625 UINT64_C(2038431754), // SRLRI_D 2626 UINT64_C(2044723210), // SRLRI_H 2627 UINT64_C(2042626058), // SRLRI_W 2628 UINT64_C(2030043157), // SRLR_B 2629 UINT64_C(2036334613), // SRLR_D 2630 UINT64_C(2032140309), // SRLR_H 2631 UINT64_C(2034237461), // SRLR_W 2632 UINT64_C(6), // SRLV 2633 UINT64_C(80), // SRLV_MM 2634 UINT64_C(2030043149), // SRL_B 2635 UINT64_C(2036334605), // SRL_D 2636 UINT64_C(2032140301), // SRL_H 2637 UINT64_C(64), // SRL_MM 2638 UINT64_C(2034237453), // SRL_W 2639 UINT64_C(64), // SSNOP 2640 UINT64_C(2048), // SSNOP_MM 2641 UINT64_C(2048), // SSNOP_MMR6 2642 UINT64_C(2013265956), // ST_B 2643 UINT64_C(2013265959), // ST_D 2644 UINT64_C(2013265957), // ST_H 2645 UINT64_C(2013265958), // ST_W 2646 UINT64_C(34), // SUB 2647 UINT64_C(2080375384), // SUBQH_PH 2648 UINT64_C(589), // SUBQH_PH_MMR2 2649 UINT64_C(2080375512), // SUBQH_R_PH 2650 UINT64_C(1613), // SUBQH_R_PH_MMR2 2651 UINT64_C(2080376024), // SUBQH_R_W 2652 UINT64_C(1677), // SUBQH_R_W_MMR2 2653 UINT64_C(2080375896), // SUBQH_W 2654 UINT64_C(653), // SUBQH_W_MMR2 2655 UINT64_C(2080375504), // SUBQ_PH 2656 UINT64_C(525), // SUBQ_PH_MM 2657 UINT64_C(2080375760), // SUBQ_S_PH 2658 UINT64_C(1549), // SUBQ_S_PH_MM 2659 UINT64_C(2080376272), // SUBQ_S_W 2660 UINT64_C(837), // SUBQ_S_W_MM 2661 UINT64_C(2030043153), // SUBSUS_U_B 2662 UINT64_C(2036334609), // SUBSUS_U_D 2663 UINT64_C(2032140305), // SUBSUS_U_H 2664 UINT64_C(2034237457), // SUBSUS_U_W 2665 UINT64_C(2038431761), // SUBSUU_S_B 2666 UINT64_C(2044723217), // SUBSUU_S_D 2667 UINT64_C(2040528913), // SUBSUU_S_H 2668 UINT64_C(2042626065), // SUBSUU_S_W 2669 UINT64_C(2013265937), // SUBS_S_B 2670 UINT64_C(2019557393), // SUBS_S_D 2671 UINT64_C(2015363089), // SUBS_S_H 2672 UINT64_C(2017460241), // SUBS_S_W 2673 UINT64_C(2021654545), // SUBS_U_B 2674 UINT64_C(2027946001), // SUBS_U_D 2675 UINT64_C(2023751697), // SUBS_U_H 2676 UINT64_C(2025848849), // SUBS_U_W 2677 UINT64_C(1025), // SUBU16_MM 2678 UINT64_C(1025), // SUBU16_MMR6 2679 UINT64_C(2080374872), // SUBUH_QB 2680 UINT64_C(845), // SUBUH_QB_MMR2 2681 UINT64_C(2080375000), // SUBUH_R_QB 2682 UINT64_C(1869), // SUBUH_R_QB_MMR2 2683 UINT64_C(464), // SUBU_MMR6 2684 UINT64_C(2080375376), // SUBU_PH 2685 UINT64_C(781), // SUBU_PH_MMR2 2686 UINT64_C(2080374864), // SUBU_QB 2687 UINT64_C(717), // SUBU_QB_MM 2688 UINT64_C(2080375632), // SUBU_S_PH 2689 UINT64_C(1805), // SUBU_S_PH_MMR2 2690 UINT64_C(2080375120), // SUBU_S_QB 2691 UINT64_C(1741), // SUBU_S_QB_MM 2692 UINT64_C(2021654534), // SUBVI_B 2693 UINT64_C(2027945990), // SUBVI_D 2694 UINT64_C(2023751686), // SUBVI_H 2695 UINT64_C(2025848838), // SUBVI_W 2696 UINT64_C(2021654542), // SUBV_B 2697 UINT64_C(2027945998), // SUBV_D 2698 UINT64_C(2023751694), // SUBV_H 2699 UINT64_C(2025848846), // SUBV_W 2700 UINT64_C(400), // SUB_MM 2701 UINT64_C(400), // SUB_MMR6 2702 UINT64_C(35), // SUBu 2703 UINT64_C(464), // SUBu_MM 2704 UINT64_C(1275068429), // SUXC1 2705 UINT64_C(1275068429), // SUXC164 2706 UINT64_C(1409286536), // SUXC1_MM 2707 UINT64_C(2885681152), // SW 2708 UINT64_C(59392), // SW16_MM 2709 UINT64_C(59392), // SW16_MMR6 2710 UINT64_C(2885681152), // SW64 2711 UINT64_C(3825205248), // SWC1 2712 UINT64_C(2550136832), // SWC1_MM 2713 UINT64_C(3892314112), // SWC2 2714 UINT64_C(536903680), // SWC2_MMR6 2715 UINT64_C(1231028224), // SWC2_R6 2716 UINT64_C(3959422976), // SWC3 2717 UINT64_C(2885681152), // SWDSP 2718 UINT64_C(4160749568), // SWDSP_MM 2719 UINT64_C(2080374815), // SWE 2720 UINT64_C(1610657280), // SWE_MM 2721 UINT64_C(2818572288), // SWL 2722 UINT64_C(2818572288), // SWL64 2723 UINT64_C(2080374817), // SWLE 2724 UINT64_C(1610653696), // SWLE_MM 2725 UINT64_C(1610645504), // SWL_MM 2726 UINT64_C(17728), // SWM16_MM 2727 UINT64_C(17418), // SWM16_MMR6 2728 UINT64_C(536924160), // SWM32_MM 2729 UINT64_C(536907776), // SWP_MM 2730 UINT64_C(3087007744), // SWR 2731 UINT64_C(3087007744), // SWR64 2732 UINT64_C(2080374818), // SWRE 2733 UINT64_C(1610654208), // SWRE_MM 2734 UINT64_C(1610649600), // SWR_MM 2735 UINT64_C(51200), // SWSP_MM 2736 UINT64_C(51200), // SWSP_MMR6 2737 UINT64_C(1275068424), // SWXC1 2738 UINT64_C(1409286280), // SWXC1_MM 2739 UINT64_C(4160749568), // SW_MM 2740 UINT64_C(4160749568), // SW_MMR6 2741 UINT64_C(15), // SYNC 2742 UINT64_C(69140480), // SYNCI 2743 UINT64_C(1107296256), // SYNCI_MM 2744 UINT64_C(1098907648), // SYNCI_MMR6 2745 UINT64_C(27516), // SYNC_MM 2746 UINT64_C(27516), // SYNC_MMR6 2747 UINT64_C(12), // SYSCALL 2748 UINT64_C(35708), // SYSCALL_MM 2749 UINT64_C(25728), // Save16 2750 UINT64_C(25728), // SaveX16 2751 UINT64_C(4026580992), // SbRxRyOffMemX16 2752 UINT64_C(59537), // SebRx16 2753 UINT64_C(59569), // SehRx16 2754 UINT64_C(4026583040), // ShRxRyOffMemX16 2755 UINT64_C(4026544128), // SllX16 2756 UINT64_C(59396), // SllvRxRy16 2757 UINT64_C(59394), // SltRxRy16 2758 UINT64_C(20480), // SltiRxImm16 2759 UINT64_C(4026552320), // SltiRxImmX16 2760 UINT64_C(22528), // SltiuRxImm16 2761 UINT64_C(4026554368), // SltiuRxImmX16 2762 UINT64_C(59395), // SltuRxRy16 2763 UINT64_C(4026544131), // SraX16 2764 UINT64_C(59399), // SravRxRy16 2765 UINT64_C(4026544130), // SrlX16 2766 UINT64_C(59398), // SrlvRxRy16 2767 UINT64_C(57347), // SubuRxRyRz16 2768 UINT64_C(4026587136), // SwRxRyOffMemX16 2769 UINT64_C(4026585088), // SwRxSpImmX16 2770 UINT64_C(52), // TEQ 2771 UINT64_C(67895296), // TEQI 2772 UINT64_C(1103101952), // TEQI_MM 2773 UINT64_C(60), // TEQ_MM 2774 UINT64_C(48), // TGE 2775 UINT64_C(67633152), // TGEI 2776 UINT64_C(67698688), // TGEIU 2777 UINT64_C(1096810496), // TGEIU_MM 2778 UINT64_C(1092616192), // TGEI_MM 2779 UINT64_C(49), // TGEU 2780 UINT64_C(1084), // TGEU_MM 2781 UINT64_C(572), // TGE_MM 2782 UINT64_C(1107296267), // TLBGINV 2783 UINT64_C(1107296268), // TLBGINVF 2784 UINT64_C(20860), // TLBGINVF_MM 2785 UINT64_C(16764), // TLBGINV_MM 2786 UINT64_C(1107296272), // TLBGP 2787 UINT64_C(380), // TLBGP_MM 2788 UINT64_C(1107296265), // TLBGR 2789 UINT64_C(4476), // TLBGR_MM 2790 UINT64_C(1107296266), // TLBGWI 2791 UINT64_C(8572), // TLBGWI_MM 2792 UINT64_C(1107296270), // TLBGWR 2793 UINT64_C(12668), // TLBGWR_MM 2794 UINT64_C(1107296259), // TLBINV 2795 UINT64_C(1107296260), // TLBINVF 2796 UINT64_C(21372), // TLBINVF_MMR6 2797 UINT64_C(17276), // TLBINV_MMR6 2798 UINT64_C(1107296264), // TLBP 2799 UINT64_C(892), // TLBP_MM 2800 UINT64_C(1107296257), // TLBR 2801 UINT64_C(4988), // TLBR_MM 2802 UINT64_C(1107296258), // TLBWI 2803 UINT64_C(9084), // TLBWI_MM 2804 UINT64_C(1107296262), // TLBWR 2805 UINT64_C(13180), // TLBWR_MM 2806 UINT64_C(50), // TLT 2807 UINT64_C(67764224), // TLTI 2808 UINT64_C(1094713344), // TLTIU_MM 2809 UINT64_C(1090519040), // TLTI_MM 2810 UINT64_C(51), // TLTU 2811 UINT64_C(2620), // TLTU_MM 2812 UINT64_C(2108), // TLT_MM 2813 UINT64_C(54), // TNE 2814 UINT64_C(68026368), // TNEI 2815 UINT64_C(1098907648), // TNEI_MM 2816 UINT64_C(3132), // TNE_MM 2817 UINT64_C(1176502281), // TRUNC_L_D64 2818 UINT64_C(1409311547), // TRUNC_L_D_MMR6 2819 UINT64_C(1174405129), // TRUNC_L_S 2820 UINT64_C(1409295163), // TRUNC_L_S_MMR6 2821 UINT64_C(1176502285), // TRUNC_W_D32 2822 UINT64_C(1176502285), // TRUNC_W_D64 2823 UINT64_C(1409313595), // TRUNC_W_D_MMR6 2824 UINT64_C(1409313595), // TRUNC_W_MM 2825 UINT64_C(1174405133), // TRUNC_W_S 2826 UINT64_C(1409297211), // TRUNC_W_S_MM 2827 UINT64_C(1409297211), // TRUNC_W_S_MMR6 2828 UINT64_C(67829760), // TTLTIU 2829 UINT64_C(27), // UDIV 2830 UINT64_C(47932), // UDIV_MM 2831 UINT64_C(1879048209), // V3MULU 2832 UINT64_C(1879048208), // VMM0 2833 UINT64_C(1879048207), // VMULU 2834 UINT64_C(2013265941), // VSHF_B 2835 UINT64_C(2019557397), // VSHF_D 2836 UINT64_C(2015363093), // VSHF_H 2837 UINT64_C(2017460245), // VSHF_W 2838 UINT64_C(1107296288), // WAIT 2839 UINT64_C(37756), // WAIT_MM 2840 UINT64_C(37756), // WAIT_MMR6 2841 UINT64_C(2080376056), // WRDSP 2842 UINT64_C(5756), // WRDSP_MM 2843 UINT64_C(61820), // WRPGPR_MMR6 2844 UINT64_C(2080374944), // WSBH 2845 UINT64_C(31548), // WSBH_MM 2846 UINT64_C(31548), // WSBH_MMR6 2847 UINT64_C(38), // XOR 2848 UINT64_C(17472), // XOR16_MM 2849 UINT64_C(17416), // XOR16_MMR6 2850 UINT64_C(38), // XOR64 2851 UINT64_C(2063597568), // XORI_B 2852 UINT64_C(1879048192), // XORI_MMR6 2853 UINT64_C(784), // XOR_MM 2854 UINT64_C(784), // XOR_MMR6 2855 UINT64_C(2019557406), // XOR_V 2856 UINT64_C(939524096), // XORi 2857 UINT64_C(939524096), // XORi64 2858 UINT64_C(1879048192), // XORi_MM 2859 UINT64_C(59406), // XorRxRxRy16 2860 UINT64_C(2080374793), // YIELD 2861 UINT64_C(0) 2862 }; 2863 const unsigned opcode = MI.getOpcode(); 2864 uint64_t Value = InstBits[opcode]; 2865 uint64_t op = 0; 2866 (void)op; // suppress warning 2867 switch (opcode) { 2868 case Mips::Break16: 2869 case Mips::DERET: 2870 case Mips::DERET_MM: 2871 case Mips::DERET_MMR6: 2872 case Mips::EHB: 2873 case Mips::EHB_MM: 2874 case Mips::EHB_MMR6: 2875 case Mips::ERET: 2876 case Mips::ERETNC: 2877 case Mips::ERETNC_MMR6: 2878 case Mips::ERET_MM: 2879 case Mips::ERET_MMR6: 2880 case Mips::JrRa16: 2881 case Mips::JrcRa16: 2882 case Mips::JrcRx16: 2883 case Mips::PAUSE: 2884 case Mips::PAUSE_MM: 2885 case Mips::PAUSE_MMR6: 2886 case Mips::Restore16: 2887 case Mips::RestoreX16: 2888 case Mips::SSNOP: 2889 case Mips::SSNOP_MM: 2890 case Mips::SSNOP_MMR6: 2891 case Mips::Save16: 2892 case Mips::SaveX16: 2893 case Mips::TLBGINV: 2894 case Mips::TLBGINVF: 2895 case Mips::TLBGINVF_MM: 2896 case Mips::TLBGINV_MM: 2897 case Mips::TLBGP: 2898 case Mips::TLBGP_MM: 2899 case Mips::TLBGR: 2900 case Mips::TLBGR_MM: 2901 case Mips::TLBGWI: 2902 case Mips::TLBGWI_MM: 2903 case Mips::TLBGWR: 2904 case Mips::TLBGWR_MM: 2905 case Mips::TLBINV: 2906 case Mips::TLBINVF: 2907 case Mips::TLBINVF_MMR6: 2908 case Mips::TLBINV_MMR6: 2909 case Mips::TLBP: 2910 case Mips::TLBP_MM: 2911 case Mips::TLBR: 2912 case Mips::TLBR_MM: 2913 case Mips::TLBWI: 2914 case Mips::TLBWI_MM: 2915 case Mips::TLBWR: 2916 case Mips::TLBWR_MM: 2917 case Mips::WAIT: { 2918 break; 2919 } 2920 case Mips::MTHLIP: 2921 case Mips::SHILOV: { 2922 // op: ac 2923 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 2924 op &= UINT64_C(3); 2925 op <<= 11; 2926 Value |= op; 2927 // op: rs 2928 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 2929 op &= UINT64_C(31); 2930 op <<= 21; 2931 Value |= op; 2932 break; 2933 } 2934 case Mips::DPAQX_SA_W_PH: 2935 case Mips::DPAQX_S_W_PH: 2936 case Mips::DPAQ_SA_L_W: 2937 case Mips::DPAQ_S_W_PH: 2938 case Mips::DPAU_H_QBL: 2939 case Mips::DPAU_H_QBR: 2940 case Mips::DPAX_W_PH: 2941 case Mips::DPA_W_PH: 2942 case Mips::DPSQX_SA_W_PH: 2943 case Mips::DPSQX_S_W_PH: 2944 case Mips::DPSQ_SA_L_W: 2945 case Mips::DPSQ_S_W_PH: 2946 case Mips::DPSU_H_QBL: 2947 case Mips::DPSU_H_QBR: 2948 case Mips::DPSX_W_PH: 2949 case Mips::DPS_W_PH: 2950 case Mips::MADDU_DSP: 2951 case Mips::MADD_DSP: 2952 case Mips::MAQ_SA_W_PHL: 2953 case Mips::MAQ_SA_W_PHR: 2954 case Mips::MAQ_S_W_PHL: 2955 case Mips::MAQ_S_W_PHR: 2956 case Mips::MSUBU_DSP: 2957 case Mips::MSUB_DSP: 2958 case Mips::MULSAQ_S_W_PH: 2959 case Mips::MULSA_W_PH: 2960 case Mips::MULTU_DSP: 2961 case Mips::MULT_DSP: { 2962 // op: ac 2963 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 2964 op &= UINT64_C(3); 2965 op <<= 11; 2966 Value |= op; 2967 // op: rs 2968 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 2969 op &= UINT64_C(31); 2970 op <<= 21; 2971 Value |= op; 2972 // op: rt 2973 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 2974 op &= UINT64_C(31); 2975 op <<= 16; 2976 Value |= op; 2977 break; 2978 } 2979 case Mips::SHILO: { 2980 // op: ac 2981 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 2982 op &= UINT64_C(3); 2983 op <<= 11; 2984 Value |= op; 2985 // op: shift 2986 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 2987 op &= UINT64_C(63); 2988 op <<= 20; 2989 Value |= op; 2990 break; 2991 } 2992 case Mips::CACHEE: 2993 case Mips::CACHE_R6: 2994 case Mips::PREFE: 2995 case Mips::PREF_R6: { 2996 // op: addr 2997 op = getMemEncoding(MI, 0, Fixups, STI); 2998 Value |= (op & UINT64_C(2031616)) << 5; 2999 Value |= (op & UINT64_C(511)) << 7; 3000 // op: hint 3001 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3002 op &= UINT64_C(31); 3003 op <<= 16; 3004 Value |= op; 3005 break; 3006 } 3007 case Mips::SYNCI: { 3008 // op: addr 3009 op = getMemEncoding(MI, 0, Fixups, STI); 3010 Value |= (op & UINT64_C(2031616)) << 5; 3011 Value |= (op & UINT64_C(65535)); 3012 break; 3013 } 3014 case Mips::CACHE: 3015 case Mips::PREF: { 3016 // op: addr 3017 op = getMemEncoding(MI, 0, Fixups, STI); 3018 Value |= (op & UINT64_C(2031616)) << 5; 3019 Value |= (op & UINT64_C(65535)); 3020 // op: hint 3021 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3022 op &= UINT64_C(31); 3023 op <<= 16; 3024 Value |= op; 3025 break; 3026 } 3027 case Mips::LD_B: 3028 case Mips::ST_B: { 3029 // op: addr 3030 op = getMemEncoding(MI, 1, Fixups, STI); 3031 Value |= (op & UINT64_C(1023)) << 16; 3032 Value |= (op & UINT64_C(2031616)) >> 5; 3033 // op: wd 3034 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3035 op &= UINT64_C(31); 3036 op <<= 6; 3037 Value |= op; 3038 break; 3039 } 3040 case Mips::LBE: 3041 case Mips::LBuE: 3042 case Mips::LHE: 3043 case Mips::LHuE: 3044 case Mips::LLE: 3045 case Mips::LWE: 3046 case Mips::LWLE: 3047 case Mips::LWRE: 3048 case Mips::SBE: 3049 case Mips::SHE: 3050 case Mips::SWE: 3051 case Mips::SWLE: 3052 case Mips::SWRE: { 3053 // op: addr 3054 op = getMemEncoding(MI, 1, Fixups, STI); 3055 Value |= (op & UINT64_C(2031616)) << 5; 3056 Value |= (op & UINT64_C(511)) << 7; 3057 // op: rt 3058 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3059 op &= UINT64_C(31); 3060 op <<= 16; 3061 Value |= op; 3062 break; 3063 } 3064 case Mips::SCE: { 3065 // op: addr 3066 op = getMemEncoding(MI, 2, Fixups, STI); 3067 Value |= (op & UINT64_C(2031616)) << 5; 3068 Value |= (op & UINT64_C(511)) << 7; 3069 // op: rt 3070 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3071 op &= UINT64_C(31); 3072 op <<= 16; 3073 Value |= op; 3074 break; 3075 } 3076 case Mips::LD_H: 3077 case Mips::ST_H: { 3078 // op: addr 3079 op = getMemEncoding<1>(MI, 1, Fixups, STI); 3080 Value |= (op & UINT64_C(1023)) << 16; 3081 Value |= (op & UINT64_C(2031616)) >> 5; 3082 // op: wd 3083 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3084 op &= UINT64_C(31); 3085 op <<= 6; 3086 Value |= op; 3087 break; 3088 } 3089 case Mips::LD_W: 3090 case Mips::ST_W: { 3091 // op: addr 3092 op = getMemEncoding<2>(MI, 1, Fixups, STI); 3093 Value |= (op & UINT64_C(1023)) << 16; 3094 Value |= (op & UINT64_C(2031616)) >> 5; 3095 // op: wd 3096 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3097 op &= UINT64_C(31); 3098 op <<= 6; 3099 Value |= op; 3100 break; 3101 } 3102 case Mips::LD_D: 3103 case Mips::ST_D: { 3104 // op: addr 3105 op = getMemEncoding<3>(MI, 1, Fixups, STI); 3106 Value |= (op & UINT64_C(1023)) << 16; 3107 Value |= (op & UINT64_C(2031616)) >> 5; 3108 // op: wd 3109 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3110 op &= UINT64_C(31); 3111 op <<= 6; 3112 Value |= op; 3113 break; 3114 } 3115 case Mips::CACHE_MM: 3116 case Mips::CACHE_MMR6: 3117 case Mips::PREF_MM: 3118 case Mips::PREF_MMR6: { 3119 // op: addr 3120 op = getMemEncodingMMImm12(MI, 0, Fixups, STI); 3121 Value |= (op & UINT64_C(2031616)); 3122 Value |= (op & UINT64_C(4095)); 3123 // op: hint 3124 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3125 op &= UINT64_C(31); 3126 op <<= 21; 3127 Value |= op; 3128 break; 3129 } 3130 case Mips::SYNCI_MM: 3131 case Mips::SYNCI_MMR6: { 3132 // op: addr 3133 op = getMemEncodingMMImm16(MI, 0, Fixups, STI); 3134 op &= UINT64_C(2097151); 3135 Value |= op; 3136 break; 3137 } 3138 case Mips::LBU_MMR6: 3139 case Mips::LB_MMR6: { 3140 // op: addr 3141 op = getMemEncodingMMImm16(MI, 1, Fixups, STI); 3142 op &= UINT64_C(2097151); 3143 Value |= op; 3144 // op: rt 3145 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3146 op &= UINT64_C(31); 3147 op <<= 21; 3148 Value |= op; 3149 break; 3150 } 3151 case Mips::CACHEE_MM: 3152 case Mips::PREFE_MM: { 3153 // op: addr 3154 op = getMemEncodingMMImm9(MI, 0, Fixups, STI); 3155 Value |= (op & UINT64_C(2031616)); 3156 Value |= (op & UINT64_C(511)); 3157 // op: hint 3158 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3159 op &= UINT64_C(31); 3160 op <<= 21; 3161 Value |= op; 3162 break; 3163 } 3164 case Mips::HYPCALL: { 3165 // op: code_ 3166 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3167 op &= UINT64_C(1023); 3168 op <<= 11; 3169 Value |= op; 3170 break; 3171 } 3172 case Mips::HYPCALL_MM: 3173 case Mips::SDBBP_MM: 3174 case Mips::SDBBP_MMR6: 3175 case Mips::SYSCALL_MM: 3176 case Mips::WAIT_MM: 3177 case Mips::WAIT_MMR6: { 3178 // op: code_ 3179 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3180 op &= UINT64_C(1023); 3181 op <<= 16; 3182 Value |= op; 3183 break; 3184 } 3185 case Mips::SDBBP: 3186 case Mips::SDBBP_R6: 3187 case Mips::SYSCALL: { 3188 // op: code_ 3189 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3190 op &= UINT64_C(1048575); 3191 op <<= 6; 3192 Value |= op; 3193 break; 3194 } 3195 case Mips::BREAK16_MM: 3196 case Mips::SDBBP16_MM: { 3197 // op: code_ 3198 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3199 op &= UINT64_C(15); 3200 Value |= op; 3201 break; 3202 } 3203 case Mips::BREAK16_MMR6: 3204 case Mips::SDBBP16_MMR6: { 3205 // op: code_ 3206 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3207 op &= UINT64_C(15); 3208 op <<= 6; 3209 Value |= op; 3210 break; 3211 } 3212 case Mips::SIGRIE: { 3213 // op: code_ 3214 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3215 op &= UINT64_C(65535); 3216 Value |= op; 3217 break; 3218 } 3219 case Mips::SIGRIE_MMR6: { 3220 // op: code_ 3221 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3222 op &= UINT64_C(65535); 3223 op <<= 6; 3224 Value |= op; 3225 break; 3226 } 3227 case Mips::BREAK: 3228 case Mips::BREAK_MM: 3229 case Mips::BREAK_MMR6: { 3230 // op: code_1 3231 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3232 op &= UINT64_C(1023); 3233 op <<= 16; 3234 Value |= op; 3235 // op: code_2 3236 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3237 op &= UINT64_C(1023); 3238 op <<= 6; 3239 Value |= op; 3240 break; 3241 } 3242 case Mips::BC2EQZ: 3243 case Mips::BC2NEZ: { 3244 // op: ct 3245 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3246 op &= UINT64_C(31); 3247 op <<= 16; 3248 Value |= op; 3249 // op: offset 3250 op = getBranchTargetOpValue(MI, 1, Fixups, STI); 3251 op &= UINT64_C(65535); 3252 Value |= op; 3253 break; 3254 } 3255 case Mips::BC1F: 3256 case Mips::BC1FL: 3257 case Mips::BC1T: 3258 case Mips::BC1TL: { 3259 // op: fcc 3260 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3261 op &= UINT64_C(7); 3262 op <<= 18; 3263 Value |= op; 3264 // op: offset 3265 op = getBranchTargetOpValue(MI, 1, Fixups, STI); 3266 op &= UINT64_C(65535); 3267 Value |= op; 3268 break; 3269 } 3270 case Mips::BC1F_MM: 3271 case Mips::BC1T_MM: { 3272 // op: fcc 3273 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3274 op &= UINT64_C(7); 3275 op <<= 18; 3276 Value |= op; 3277 // op: offset 3278 op = getBranchTargetOpValueMM(MI, 1, Fixups, STI); 3279 op &= UINT64_C(65535); 3280 Value |= op; 3281 break; 3282 } 3283 case Mips::LUXC1_MM: 3284 case Mips::LWXC1_MM: { 3285 // op: fd 3286 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3287 op &= UINT64_C(31); 3288 op <<= 11; 3289 Value |= op; 3290 // op: base 3291 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3292 op &= UINT64_C(31); 3293 op <<= 16; 3294 Value |= op; 3295 // op: index 3296 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3297 op &= UINT64_C(31); 3298 op <<= 21; 3299 Value |= op; 3300 break; 3301 } 3302 case Mips::MOVN_I_D32_MM: 3303 case Mips::MOVN_I_S_MM: 3304 case Mips::MOVZ_I_D32_MM: 3305 case Mips::MOVZ_I_S_MM: { 3306 // op: fd 3307 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3308 op &= UINT64_C(31); 3309 op <<= 11; 3310 Value |= op; 3311 // op: fs 3312 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3313 op &= UINT64_C(31); 3314 op <<= 16; 3315 Value |= op; 3316 // op: rt 3317 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3318 op &= UINT64_C(31); 3319 op <<= 21; 3320 Value |= op; 3321 break; 3322 } 3323 case Mips::CEIL_W_MM: 3324 case Mips::CEIL_W_S_MM: 3325 case Mips::CVT_D32_S_MM: 3326 case Mips::CVT_D32_W_MM: 3327 case Mips::CVT_D64_S_MM: 3328 case Mips::CVT_D64_W_MM: 3329 case Mips::CVT_L_D64_MM: 3330 case Mips::CVT_L_S_MM: 3331 case Mips::CVT_S_D32_MM: 3332 case Mips::CVT_S_D64_MM: 3333 case Mips::CVT_S_W_MM: 3334 case Mips::CVT_W_D32_MM: 3335 case Mips::CVT_W_D64_MM: 3336 case Mips::CVT_W_S_MM: 3337 case Mips::FABS_D32_MM: 3338 case Mips::FABS_D64_MM: 3339 case Mips::FABS_S_MM: 3340 case Mips::FLOOR_W_MM: 3341 case Mips::FLOOR_W_S_MM: 3342 case Mips::FMOV_D32_MM: 3343 case Mips::FMOV_D64_MM: 3344 case Mips::FMOV_S_MM: 3345 case Mips::FNEG_D32_MM: 3346 case Mips::FNEG_D64_MM: 3347 case Mips::FNEG_S_MM: 3348 case Mips::FSQRT_D32_MM: 3349 case Mips::FSQRT_D64_MM: 3350 case Mips::FSQRT_S_MM: 3351 case Mips::RECIP_D32_MM: 3352 case Mips::RECIP_D64_MM: 3353 case Mips::RECIP_S_MM: 3354 case Mips::ROUND_W_MM: 3355 case Mips::ROUND_W_S_MM: 3356 case Mips::RSQRT_D32_MM: 3357 case Mips::RSQRT_D64_MM: 3358 case Mips::RSQRT_S_MM: 3359 case Mips::TRUNC_W_MM: 3360 case Mips::TRUNC_W_S_MM: { 3361 // op: fd 3362 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3363 op &= UINT64_C(31); 3364 op <<= 21; 3365 Value |= op; 3366 // op: fs 3367 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3368 op &= UINT64_C(31); 3369 op <<= 16; 3370 Value |= op; 3371 break; 3372 } 3373 case Mips::MOVF_D32_MM: 3374 case Mips::MOVF_S_MM: 3375 case Mips::MOVT_D32_MM: 3376 case Mips::MOVT_S_MM: { 3377 // op: fd 3378 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3379 op &= UINT64_C(31); 3380 op <<= 21; 3381 Value |= op; 3382 // op: fs 3383 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3384 op &= UINT64_C(31); 3385 op <<= 16; 3386 Value |= op; 3387 // op: fcc 3388 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3389 op &= UINT64_C(7); 3390 op <<= 13; 3391 Value |= op; 3392 break; 3393 } 3394 case Mips::LDXC1: 3395 case Mips::LDXC164: 3396 case Mips::LUXC1: 3397 case Mips::LUXC164: 3398 case Mips::LWXC1: { 3399 // op: fd 3400 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3401 op &= UINT64_C(31); 3402 op <<= 6; 3403 Value |= op; 3404 // op: base 3405 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3406 op &= UINT64_C(31); 3407 op <<= 21; 3408 Value |= op; 3409 // op: index 3410 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3411 op &= UINT64_C(31); 3412 op <<= 16; 3413 Value |= op; 3414 break; 3415 } 3416 case Mips::MADD_D32: 3417 case Mips::MADD_D64: 3418 case Mips::MADD_S: 3419 case Mips::MSUB_D32: 3420 case Mips::MSUB_D64: 3421 case Mips::MSUB_S: 3422 case Mips::NMADD_D32: 3423 case Mips::NMADD_D64: 3424 case Mips::NMADD_S: 3425 case Mips::NMSUB_D32: 3426 case Mips::NMSUB_D64: 3427 case Mips::NMSUB_S: { 3428 // op: fd 3429 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3430 op &= UINT64_C(31); 3431 op <<= 6; 3432 Value |= op; 3433 // op: fr 3434 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3435 op &= UINT64_C(31); 3436 op <<= 21; 3437 Value |= op; 3438 // op: fs 3439 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3440 op &= UINT64_C(31); 3441 op <<= 11; 3442 Value |= op; 3443 // op: ft 3444 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 3445 op &= UINT64_C(31); 3446 op <<= 16; 3447 Value |= op; 3448 break; 3449 } 3450 case Mips::CEIL_L_D64: 3451 case Mips::CEIL_L_S: 3452 case Mips::CEIL_W_D32: 3453 case Mips::CEIL_W_D64: 3454 case Mips::CEIL_W_S: 3455 case Mips::CVT_D32_S: 3456 case Mips::CVT_D32_W: 3457 case Mips::CVT_D64_L: 3458 case Mips::CVT_D64_S: 3459 case Mips::CVT_D64_W: 3460 case Mips::CVT_L_D64: 3461 case Mips::CVT_L_S: 3462 case Mips::CVT_PS_PW64: 3463 case Mips::CVT_PW_PS64: 3464 case Mips::CVT_S_D32: 3465 case Mips::CVT_S_D64: 3466 case Mips::CVT_S_L: 3467 case Mips::CVT_S_PL64: 3468 case Mips::CVT_S_PU64: 3469 case Mips::CVT_S_W: 3470 case Mips::CVT_W_D32: 3471 case Mips::CVT_W_D64: 3472 case Mips::CVT_W_S: 3473 case Mips::FABS_D32: 3474 case Mips::FABS_D64: 3475 case Mips::FABS_S: 3476 case Mips::FLOOR_L_D64: 3477 case Mips::FLOOR_L_S: 3478 case Mips::FLOOR_W_D32: 3479 case Mips::FLOOR_W_D64: 3480 case Mips::FLOOR_W_S: 3481 case Mips::FMOV_D32: 3482 case Mips::FMOV_D64: 3483 case Mips::FMOV_S: 3484 case Mips::FNEG_D32: 3485 case Mips::FNEG_D64: 3486 case Mips::FNEG_S: 3487 case Mips::FSQRT_D32: 3488 case Mips::FSQRT_D64: 3489 case Mips::FSQRT_S: 3490 case Mips::RECIP_D32: 3491 case Mips::RECIP_D64: 3492 case Mips::RECIP_S: 3493 case Mips::ROUND_L_D64: 3494 case Mips::ROUND_L_S: 3495 case Mips::ROUND_W_D32: 3496 case Mips::ROUND_W_D64: 3497 case Mips::ROUND_W_S: 3498 case Mips::RSQRT_D32: 3499 case Mips::RSQRT_D64: 3500 case Mips::RSQRT_S: 3501 case Mips::TRUNC_L_D64: 3502 case Mips::TRUNC_L_S: 3503 case Mips::TRUNC_W_D32: 3504 case Mips::TRUNC_W_D64: 3505 case Mips::TRUNC_W_S: { 3506 // op: fd 3507 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3508 op &= UINT64_C(31); 3509 op <<= 6; 3510 Value |= op; 3511 // op: fs 3512 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3513 op &= UINT64_C(31); 3514 op <<= 11; 3515 Value |= op; 3516 break; 3517 } 3518 case Mips::MOVF_D32: 3519 case Mips::MOVF_D64: 3520 case Mips::MOVF_S: 3521 case Mips::MOVT_D32: 3522 case Mips::MOVT_D64: 3523 case Mips::MOVT_S: { 3524 // op: fd 3525 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3526 op &= UINT64_C(31); 3527 op <<= 6; 3528 Value |= op; 3529 // op: fs 3530 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3531 op &= UINT64_C(31); 3532 op <<= 11; 3533 Value |= op; 3534 // op: fcc 3535 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3536 op &= UINT64_C(7); 3537 op <<= 18; 3538 Value |= op; 3539 break; 3540 } 3541 case Mips::ADDR_PS64: 3542 case Mips::CMP_EQ_D: 3543 case Mips::CMP_EQ_S: 3544 case Mips::CMP_F_D: 3545 case Mips::CMP_F_S: 3546 case Mips::CMP_LE_D: 3547 case Mips::CMP_LE_S: 3548 case Mips::CMP_LT_D: 3549 case Mips::CMP_LT_S: 3550 case Mips::CMP_SAF_D: 3551 case Mips::CMP_SAF_S: 3552 case Mips::CMP_SEQ_D: 3553 case Mips::CMP_SEQ_S: 3554 case Mips::CMP_SLE_D: 3555 case Mips::CMP_SLE_S: 3556 case Mips::CMP_SLT_D: 3557 case Mips::CMP_SLT_S: 3558 case Mips::CMP_SUEQ_D: 3559 case Mips::CMP_SUEQ_S: 3560 case Mips::CMP_SULE_D: 3561 case Mips::CMP_SULE_S: 3562 case Mips::CMP_SULT_D: 3563 case Mips::CMP_SULT_S: 3564 case Mips::CMP_SUN_D: 3565 case Mips::CMP_SUN_S: 3566 case Mips::CMP_UEQ_D: 3567 case Mips::CMP_UEQ_S: 3568 case Mips::CMP_ULE_D: 3569 case Mips::CMP_ULE_S: 3570 case Mips::CMP_ULT_D: 3571 case Mips::CMP_ULT_S: 3572 case Mips::CMP_UN_D: 3573 case Mips::CMP_UN_S: 3574 case Mips::CVT_PS_S64: 3575 case Mips::FADD_D32: 3576 case Mips::FADD_D64: 3577 case Mips::FADD_PS64: 3578 case Mips::FADD_S: 3579 case Mips::FDIV_D32: 3580 case Mips::FDIV_D64: 3581 case Mips::FDIV_S: 3582 case Mips::FMUL_D32: 3583 case Mips::FMUL_D64: 3584 case Mips::FMUL_PS64: 3585 case Mips::FMUL_S: 3586 case Mips::FSUB_D32: 3587 case Mips::FSUB_D64: 3588 case Mips::FSUB_PS64: 3589 case Mips::FSUB_S: 3590 case Mips::MULR_PS64: 3591 case Mips::PLL_PS64: 3592 case Mips::PLU_PS64: 3593 case Mips::PUL_PS64: 3594 case Mips::PUU_PS64: { 3595 // op: fd 3596 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3597 op &= UINT64_C(31); 3598 op <<= 6; 3599 Value |= op; 3600 // op: fs 3601 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3602 op &= UINT64_C(31); 3603 op <<= 11; 3604 Value |= op; 3605 // op: ft 3606 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3607 op &= UINT64_C(31); 3608 op <<= 16; 3609 Value |= op; 3610 break; 3611 } 3612 case Mips::MOVN_I64_D64: 3613 case Mips::MOVN_I64_S: 3614 case Mips::MOVN_I_D32: 3615 case Mips::MOVN_I_D64: 3616 case Mips::MOVN_I_S: 3617 case Mips::MOVZ_I64_D64: 3618 case Mips::MOVZ_I64_S: 3619 case Mips::MOVZ_I_D32: 3620 case Mips::MOVZ_I_D64: 3621 case Mips::MOVZ_I_S: { 3622 // op: fd 3623 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3624 op &= UINT64_C(31); 3625 op <<= 6; 3626 Value |= op; 3627 // op: fs 3628 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3629 op &= UINT64_C(31); 3630 op <<= 11; 3631 Value |= op; 3632 // op: rt 3633 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3634 op &= UINT64_C(31); 3635 op <<= 16; 3636 Value |= op; 3637 break; 3638 } 3639 case Mips::SUXC1_MM: 3640 case Mips::SWXC1_MM: { 3641 // op: fs 3642 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3643 op &= UINT64_C(31); 3644 op <<= 11; 3645 Value |= op; 3646 // op: base 3647 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3648 op &= UINT64_C(31); 3649 op <<= 16; 3650 Value |= op; 3651 // op: index 3652 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3653 op &= UINT64_C(31); 3654 op <<= 21; 3655 Value |= op; 3656 break; 3657 } 3658 case Mips::SDXC1: 3659 case Mips::SDXC164: 3660 case Mips::SUXC1: 3661 case Mips::SUXC164: 3662 case Mips::SWXC1: { 3663 // op: fs 3664 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3665 op &= UINT64_C(31); 3666 op <<= 11; 3667 Value |= op; 3668 // op: base 3669 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3670 op &= UINT64_C(31); 3671 op <<= 21; 3672 Value |= op; 3673 // op: index 3674 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3675 op &= UINT64_C(31); 3676 op <<= 16; 3677 Value |= op; 3678 break; 3679 } 3680 case Mips::FCMP_D32: 3681 case Mips::FCMP_D64: 3682 case Mips::FCMP_S32: { 3683 // op: fs 3684 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3685 op &= UINT64_C(31); 3686 op <<= 11; 3687 Value |= op; 3688 // op: ft 3689 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3690 op &= UINT64_C(31); 3691 op <<= 16; 3692 Value |= op; 3693 // op: cond 3694 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3695 op &= UINT64_C(15); 3696 Value |= op; 3697 break; 3698 } 3699 case Mips::FCMP_D32_MM: 3700 case Mips::FCMP_S32_MM: { 3701 // op: fs 3702 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3703 op &= UINT64_C(31); 3704 op <<= 16; 3705 Value |= op; 3706 // op: ft 3707 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3708 op &= UINT64_C(31); 3709 op <<= 21; 3710 Value |= op; 3711 // op: cond 3712 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3713 op &= UINT64_C(15); 3714 op <<= 6; 3715 Value |= op; 3716 break; 3717 } 3718 case Mips::CLASS_D: 3719 case Mips::CLASS_S: 3720 case Mips::RINT_D: 3721 case Mips::RINT_S: { 3722 // op: fs 3723 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3724 op &= UINT64_C(31); 3725 op <<= 11; 3726 Value |= op; 3727 // op: fd 3728 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3729 op &= UINT64_C(31); 3730 op <<= 6; 3731 Value |= op; 3732 break; 3733 } 3734 case Mips::C_EQ_D32: 3735 case Mips::C_EQ_D64: 3736 case Mips::C_EQ_S: 3737 case Mips::C_F_D32: 3738 case Mips::C_F_D64: 3739 case Mips::C_F_S: 3740 case Mips::C_LE_D32: 3741 case Mips::C_LE_D64: 3742 case Mips::C_LE_S: 3743 case Mips::C_LT_D32: 3744 case Mips::C_LT_D64: 3745 case Mips::C_LT_S: 3746 case Mips::C_NGE_D32: 3747 case Mips::C_NGE_D64: 3748 case Mips::C_NGE_S: 3749 case Mips::C_NGLE_D32: 3750 case Mips::C_NGLE_D64: 3751 case Mips::C_NGLE_S: 3752 case Mips::C_NGL_D32: 3753 case Mips::C_NGL_D64: 3754 case Mips::C_NGL_S: 3755 case Mips::C_NGT_D32: 3756 case Mips::C_NGT_D64: 3757 case Mips::C_NGT_S: 3758 case Mips::C_OLE_D32: 3759 case Mips::C_OLE_D64: 3760 case Mips::C_OLE_S: 3761 case Mips::C_OLT_D32: 3762 case Mips::C_OLT_D64: 3763 case Mips::C_OLT_S: 3764 case Mips::C_SEQ_D32: 3765 case Mips::C_SEQ_D64: 3766 case Mips::C_SEQ_S: 3767 case Mips::C_SF_D32: 3768 case Mips::C_SF_D64: 3769 case Mips::C_SF_S: 3770 case Mips::C_UEQ_D32: 3771 case Mips::C_UEQ_D64: 3772 case Mips::C_UEQ_S: 3773 case Mips::C_ULE_D32: 3774 case Mips::C_ULE_D64: 3775 case Mips::C_ULE_S: 3776 case Mips::C_ULT_D32: 3777 case Mips::C_ULT_D64: 3778 case Mips::C_ULT_S: 3779 case Mips::C_UN_D32: 3780 case Mips::C_UN_D64: 3781 case Mips::C_UN_S: { 3782 // op: fs 3783 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3784 op &= UINT64_C(31); 3785 op <<= 11; 3786 Value |= op; 3787 // op: ft 3788 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3789 op &= UINT64_C(31); 3790 op <<= 16; 3791 Value |= op; 3792 // op: fcc 3793 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3794 op &= UINT64_C(7); 3795 op <<= 8; 3796 Value |= op; 3797 break; 3798 } 3799 case Mips::C_EQ_D32_MM: 3800 case Mips::C_EQ_D64_MM: 3801 case Mips::C_EQ_S_MM: 3802 case Mips::C_F_D32_MM: 3803 case Mips::C_F_D64_MM: 3804 case Mips::C_F_S_MM: 3805 case Mips::C_LE_D32_MM: 3806 case Mips::C_LE_D64_MM: 3807 case Mips::C_LE_S_MM: 3808 case Mips::C_LT_D32_MM: 3809 case Mips::C_LT_D64_MM: 3810 case Mips::C_LT_S_MM: 3811 case Mips::C_NGE_D32_MM: 3812 case Mips::C_NGE_D64_MM: 3813 case Mips::C_NGE_S_MM: 3814 case Mips::C_NGLE_D32_MM: 3815 case Mips::C_NGLE_D64_MM: 3816 case Mips::C_NGLE_S_MM: 3817 case Mips::C_NGL_D32_MM: 3818 case Mips::C_NGL_D64_MM: 3819 case Mips::C_NGL_S_MM: 3820 case Mips::C_NGT_D32_MM: 3821 case Mips::C_NGT_D64_MM: 3822 case Mips::C_NGT_S_MM: 3823 case Mips::C_OLE_D32_MM: 3824 case Mips::C_OLE_D64_MM: 3825 case Mips::C_OLE_S_MM: 3826 case Mips::C_OLT_D32_MM: 3827 case Mips::C_OLT_D64_MM: 3828 case Mips::C_OLT_S_MM: 3829 case Mips::C_SEQ_D32_MM: 3830 case Mips::C_SEQ_D64_MM: 3831 case Mips::C_SEQ_S_MM: 3832 case Mips::C_SF_D32_MM: 3833 case Mips::C_SF_D64_MM: 3834 case Mips::C_SF_S_MM: 3835 case Mips::C_UEQ_D32_MM: 3836 case Mips::C_UEQ_D64_MM: 3837 case Mips::C_UEQ_S_MM: 3838 case Mips::C_ULE_D32_MM: 3839 case Mips::C_ULE_D64_MM: 3840 case Mips::C_ULE_S_MM: 3841 case Mips::C_ULT_D32_MM: 3842 case Mips::C_ULT_D64_MM: 3843 case Mips::C_ULT_S_MM: 3844 case Mips::C_UN_D32_MM: 3845 case Mips::C_UN_D64_MM: 3846 case Mips::C_UN_S_MM: { 3847 // op: fs 3848 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3849 op &= UINT64_C(31); 3850 op <<= 16; 3851 Value |= op; 3852 // op: ft 3853 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3854 op &= UINT64_C(31); 3855 op <<= 21; 3856 Value |= op; 3857 // op: fcc 3858 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3859 op &= UINT64_C(7); 3860 op <<= 13; 3861 Value |= op; 3862 break; 3863 } 3864 case Mips::CLASS_D_MMR6: 3865 case Mips::CLASS_S_MMR6: 3866 case Mips::RINT_D_MMR6: 3867 case Mips::RINT_S_MMR6: { 3868 // op: fs 3869 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3870 op &= UINT64_C(31); 3871 op <<= 21; 3872 Value |= op; 3873 // op: fd 3874 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3875 op &= UINT64_C(31); 3876 op <<= 16; 3877 Value |= op; 3878 break; 3879 } 3880 case Mips::BC1EQZ: 3881 case Mips::BC1NEZ: { 3882 // op: ft 3883 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3884 op &= UINT64_C(31); 3885 op <<= 16; 3886 Value |= op; 3887 // op: offset 3888 op = getBranchTargetOpValue(MI, 1, Fixups, STI); 3889 op &= UINT64_C(65535); 3890 Value |= op; 3891 break; 3892 } 3893 case Mips::LDC1_D64_MMR6: 3894 case Mips::SDC1_D64_MMR6: { 3895 // op: ft 3896 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3897 op &= UINT64_C(31); 3898 op <<= 21; 3899 Value |= op; 3900 // op: addr 3901 op = getMemEncodingMMImm16(MI, 1, Fixups, STI); 3902 op &= UINT64_C(2097151); 3903 Value |= op; 3904 break; 3905 } 3906 case Mips::CEIL_L_D_MMR6: 3907 case Mips::CEIL_L_S_MMR6: 3908 case Mips::CEIL_W_D_MMR6: 3909 case Mips::CEIL_W_S_MMR6: 3910 case Mips::CVT_D_L_MMR6: 3911 case Mips::CVT_L_D_MMR6: 3912 case Mips::CVT_L_S_MMR6: 3913 case Mips::CVT_S_L_MMR6: 3914 case Mips::CVT_S_W_MMR6: 3915 case Mips::CVT_W_S_MMR6: 3916 case Mips::FLOOR_L_D_MMR6: 3917 case Mips::FLOOR_L_S_MMR6: 3918 case Mips::FLOOR_W_D_MMR6: 3919 case Mips::FLOOR_W_S_MMR6: 3920 case Mips::FMOV_D_MMR6: 3921 case Mips::FMOV_S_MMR6: 3922 case Mips::FNEG_S_MMR6: 3923 case Mips::ROUND_L_D_MMR6: 3924 case Mips::ROUND_L_S_MMR6: 3925 case Mips::ROUND_W_D_MMR6: 3926 case Mips::ROUND_W_S_MMR6: 3927 case Mips::TRUNC_L_D_MMR6: 3928 case Mips::TRUNC_L_S_MMR6: 3929 case Mips::TRUNC_W_D_MMR6: 3930 case Mips::TRUNC_W_S_MMR6: { 3931 // op: ft 3932 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3933 op &= UINT64_C(31); 3934 op <<= 21; 3935 Value |= op; 3936 // op: fs 3937 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3938 op &= UINT64_C(31); 3939 op <<= 16; 3940 Value |= op; 3941 break; 3942 } 3943 case Mips::FADD_S_MMR6: 3944 case Mips::FDIV_S_MMR6: 3945 case Mips::FMUL_S_MMR6: 3946 case Mips::FSUB_S_MMR6: { 3947 // op: ft 3948 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3949 op &= UINT64_C(31); 3950 op <<= 21; 3951 Value |= op; 3952 // op: fs 3953 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3954 op &= UINT64_C(31); 3955 op <<= 16; 3956 Value |= op; 3957 // op: fd 3958 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3959 op &= UINT64_C(31); 3960 op <<= 11; 3961 Value |= op; 3962 break; 3963 } 3964 case Mips::MAXA_D: 3965 case Mips::MAXA_S: 3966 case Mips::MAX_D: 3967 case Mips::MAX_S: 3968 case Mips::MINA_D: 3969 case Mips::MINA_S: 3970 case Mips::MIN_D: 3971 case Mips::MIN_S: 3972 case Mips::SELEQZ_D: 3973 case Mips::SELEQZ_S: 3974 case Mips::SELNEZ_D: 3975 case Mips::SELNEZ_S: { 3976 // op: ft 3977 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3978 op &= UINT64_C(31); 3979 op <<= 16; 3980 Value |= op; 3981 // op: fs 3982 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3983 op &= UINT64_C(31); 3984 op <<= 11; 3985 Value |= op; 3986 // op: fd 3987 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3988 op &= UINT64_C(31); 3989 op <<= 6; 3990 Value |= op; 3991 break; 3992 } 3993 case Mips::CMP_AF_D_MMR6: 3994 case Mips::CMP_AF_S_MMR6: 3995 case Mips::CMP_EQ_D_MMR6: 3996 case Mips::CMP_EQ_S_MMR6: 3997 case Mips::CMP_LE_D_MMR6: 3998 case Mips::CMP_LE_S_MMR6: 3999 case Mips::CMP_LT_D_MMR6: 4000 case Mips::CMP_LT_S_MMR6: 4001 case Mips::CMP_SAF_D_MMR6: 4002 case Mips::CMP_SAF_S_MMR6: 4003 case Mips::CMP_SEQ_D_MMR6: 4004 case Mips::CMP_SEQ_S_MMR6: 4005 case Mips::CMP_SLE_D_MMR6: 4006 case Mips::CMP_SLE_S_MMR6: 4007 case Mips::CMP_SLT_D_MMR6: 4008 case Mips::CMP_SLT_S_MMR6: 4009 case Mips::CMP_SUEQ_D_MMR6: 4010 case Mips::CMP_SUEQ_S_MMR6: 4011 case Mips::CMP_SULE_D_MMR6: 4012 case Mips::CMP_SULE_S_MMR6: 4013 case Mips::CMP_SULT_D_MMR6: 4014 case Mips::CMP_SULT_S_MMR6: 4015 case Mips::CMP_SUN_D_MMR6: 4016 case Mips::CMP_SUN_S_MMR6: 4017 case Mips::CMP_UEQ_D_MMR6: 4018 case Mips::CMP_UEQ_S_MMR6: 4019 case Mips::CMP_ULE_D_MMR6: 4020 case Mips::CMP_ULE_S_MMR6: 4021 case Mips::CMP_ULT_D_MMR6: 4022 case Mips::CMP_ULT_S_MMR6: 4023 case Mips::CMP_UN_D_MMR6: 4024 case Mips::CMP_UN_S_MMR6: 4025 case Mips::FADD_D32_MM: 4026 case Mips::FADD_D64_MM: 4027 case Mips::FADD_S_MM: 4028 case Mips::FDIV_D32_MM: 4029 case Mips::FDIV_D64_MM: 4030 case Mips::FDIV_S_MM: 4031 case Mips::FMUL_D32_MM: 4032 case Mips::FMUL_D64_MM: 4033 case Mips::FMUL_S_MM: 4034 case Mips::FSUB_D32_MM: 4035 case Mips::FSUB_D64_MM: 4036 case Mips::FSUB_S_MM: 4037 case Mips::MAXA_D_MMR6: 4038 case Mips::MAXA_S_MMR6: 4039 case Mips::MAX_D_MMR6: 4040 case Mips::MAX_S_MMR6: 4041 case Mips::MINA_D_MMR6: 4042 case Mips::MINA_S_MMR6: 4043 case Mips::MIN_D_MMR6: 4044 case Mips::MIN_S_MMR6: 4045 case Mips::SELEQZ_D_MMR6: 4046 case Mips::SELEQZ_S_MMR6: 4047 case Mips::SELNEZ_D_MMR6: 4048 case Mips::SELNEZ_S_MMR6: { 4049 // op: ft 4050 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4051 op &= UINT64_C(31); 4052 op <<= 21; 4053 Value |= op; 4054 // op: fs 4055 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4056 op &= UINT64_C(31); 4057 op <<= 16; 4058 Value |= op; 4059 // op: fd 4060 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4061 op &= UINT64_C(31); 4062 op <<= 11; 4063 Value |= op; 4064 break; 4065 } 4066 case Mips::MADDF_D: 4067 case Mips::MADDF_S: 4068 case Mips::MSUBF_D: 4069 case Mips::MSUBF_S: 4070 case Mips::SEL_D: 4071 case Mips::SEL_S: { 4072 // op: ft 4073 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4074 op &= UINT64_C(31); 4075 op <<= 16; 4076 Value |= op; 4077 // op: fs 4078 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4079 op &= UINT64_C(31); 4080 op <<= 11; 4081 Value |= op; 4082 // op: fd 4083 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4084 op &= UINT64_C(31); 4085 op <<= 6; 4086 Value |= op; 4087 break; 4088 } 4089 case Mips::MADDF_D_MMR6: 4090 case Mips::MADDF_S_MMR6: 4091 case Mips::MSUBF_D_MMR6: 4092 case Mips::MSUBF_S_MMR6: 4093 case Mips::SEL_D_MMR6: 4094 case Mips::SEL_S_MMR6: { 4095 // op: ft 4096 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4097 op &= UINT64_C(31); 4098 op <<= 21; 4099 Value |= op; 4100 // op: fs 4101 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4102 op &= UINT64_C(31); 4103 op <<= 16; 4104 Value |= op; 4105 // op: fd 4106 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4107 op &= UINT64_C(31); 4108 op <<= 11; 4109 Value |= op; 4110 break; 4111 } 4112 case Mips::MADD_D32_MM: 4113 case Mips::MADD_S_MM: 4114 case Mips::MSUB_D32_MM: 4115 case Mips::MSUB_S_MM: 4116 case Mips::NMADD_D32_MM: 4117 case Mips::NMADD_S_MM: 4118 case Mips::NMSUB_D32_MM: 4119 case Mips::NMSUB_S_MM: { 4120 // op: ft 4121 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4122 op &= UINT64_C(31); 4123 op <<= 21; 4124 Value |= op; 4125 // op: fs 4126 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4127 op &= UINT64_C(31); 4128 op <<= 16; 4129 Value |= op; 4130 // op: fd 4131 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4132 op &= UINT64_C(31); 4133 op <<= 11; 4134 Value |= op; 4135 // op: fr 4136 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4137 op &= UINT64_C(31); 4138 op <<= 6; 4139 Value |= op; 4140 break; 4141 } 4142 case Mips::ADDVI_B: 4143 case Mips::ADDVI_D: 4144 case Mips::ADDVI_H: 4145 case Mips::ADDVI_W: 4146 case Mips::CEQI_B: 4147 case Mips::CEQI_D: 4148 case Mips::CEQI_H: 4149 case Mips::CEQI_W: 4150 case Mips::CLEI_S_B: 4151 case Mips::CLEI_S_D: 4152 case Mips::CLEI_S_H: 4153 case Mips::CLEI_S_W: 4154 case Mips::CLEI_U_B: 4155 case Mips::CLEI_U_D: 4156 case Mips::CLEI_U_H: 4157 case Mips::CLEI_U_W: 4158 case Mips::CLTI_S_B: 4159 case Mips::CLTI_S_D: 4160 case Mips::CLTI_S_H: 4161 case Mips::CLTI_S_W: 4162 case Mips::CLTI_U_B: 4163 case Mips::CLTI_U_D: 4164 case Mips::CLTI_U_H: 4165 case Mips::CLTI_U_W: 4166 case Mips::MAXI_S_B: 4167 case Mips::MAXI_S_D: 4168 case Mips::MAXI_S_H: 4169 case Mips::MAXI_S_W: 4170 case Mips::MAXI_U_B: 4171 case Mips::MAXI_U_D: 4172 case Mips::MAXI_U_H: 4173 case Mips::MAXI_U_W: 4174 case Mips::MINI_S_B: 4175 case Mips::MINI_S_D: 4176 case Mips::MINI_S_H: 4177 case Mips::MINI_S_W: 4178 case Mips::MINI_U_B: 4179 case Mips::MINI_U_D: 4180 case Mips::MINI_U_H: 4181 case Mips::MINI_U_W: 4182 case Mips::SUBVI_B: 4183 case Mips::SUBVI_D: 4184 case Mips::SUBVI_H: 4185 case Mips::SUBVI_W: { 4186 // op: imm 4187 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4188 op &= UINT64_C(31); 4189 op <<= 16; 4190 Value |= op; 4191 // op: ws 4192 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4193 op &= UINT64_C(31); 4194 op <<= 11; 4195 Value |= op; 4196 // op: wd 4197 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4198 op &= UINT64_C(31); 4199 op <<= 6; 4200 Value |= op; 4201 break; 4202 } 4203 case Mips::ADDIUSP_MM: { 4204 // op: imm 4205 op = getSImm9AddiuspValue(MI, 0, Fixups, STI); 4206 op &= UINT64_C(511); 4207 op <<= 1; 4208 Value |= op; 4209 break; 4210 } 4211 case Mips::JRADDIUSP: { 4212 // op: imm 4213 op = getUImm5Lsl2Encoding(MI, 0, Fixups, STI); 4214 op &= UINT64_C(31); 4215 Value |= op; 4216 break; 4217 } 4218 case Mips::JRCADDIUSP_MMR6: { 4219 // op: imm 4220 op = getUImm5Lsl2Encoding(MI, 0, Fixups, STI); 4221 op &= UINT64_C(31); 4222 op <<= 5; 4223 Value |= op; 4224 break; 4225 } 4226 case Mips::Bimm16: { 4227 // op: imm11 4228 op = getBranchTargetOpValue(MI, 0, Fixups, STI); 4229 op &= UINT64_C(2047); 4230 Value |= op; 4231 break; 4232 } 4233 case Mips::AddiuRxRyOffMemX16: { 4234 // op: imm15 4235 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4236 Value |= (op & UINT64_C(2032)) << 16; 4237 Value |= (op & UINT64_C(30720)) << 5; 4238 Value |= (op & UINT64_C(15)); 4239 // op: rx 4240 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4241 op &= UINT64_C(7); 4242 op <<= 8; 4243 Value |= op; 4244 // op: ry 4245 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4246 op &= UINT64_C(7); 4247 op <<= 5; 4248 Value |= op; 4249 break; 4250 } 4251 case Mips::BimmX16: { 4252 // op: imm16 4253 op = getBranchTargetOpValue(MI, 0, Fixups, STI); 4254 Value |= (op & UINT64_C(2016)) << 16; 4255 Value |= (op & UINT64_C(63488)) << 5; 4256 Value |= (op & UINT64_C(31)); 4257 break; 4258 } 4259 case Mips::BeqzRxImmX16: 4260 case Mips::BnezRxImmX16: { 4261 // op: imm16 4262 op = getBranchTargetOpValue(MI, 1, Fixups, STI); 4263 Value |= (op & UINT64_C(2016)) << 16; 4264 Value |= (op & UINT64_C(63488)) << 5; 4265 Value |= (op & UINT64_C(31)); 4266 // op: rx 4267 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4268 op &= UINT64_C(7); 4269 op <<= 8; 4270 Value |= op; 4271 break; 4272 } 4273 case Mips::AddiuSpImmX16: 4274 case Mips::BteqzX16: 4275 case Mips::BtnezX16: { 4276 // op: imm16 4277 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4278 Value |= (op & UINT64_C(2016)) << 16; 4279 Value |= (op & UINT64_C(63488)) << 5; 4280 Value |= (op & UINT64_C(31)); 4281 break; 4282 } 4283 case Mips::AddiuRxImmX16: 4284 case Mips::AddiuRxPcImmX16: 4285 case Mips::CmpiRxImmX16: 4286 case Mips::LiRxImmAlignX16: 4287 case Mips::LiRxImmX16: 4288 case Mips::LwRxPcTcpX16: 4289 case Mips::SltiRxImmX16: 4290 case Mips::SltiuRxImmX16: { 4291 // op: imm16 4292 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4293 Value |= (op & UINT64_C(2016)) << 16; 4294 Value |= (op & UINT64_C(63488)) << 5; 4295 Value |= (op & UINT64_C(31)); 4296 // op: rx 4297 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4298 op &= UINT64_C(7); 4299 op <<= 8; 4300 Value |= op; 4301 break; 4302 } 4303 case Mips::AddiuRxRxImmX16: { 4304 // op: imm16 4305 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4306 Value |= (op & UINT64_C(2016)) << 16; 4307 Value |= (op & UINT64_C(63488)) << 5; 4308 Value |= (op & UINT64_C(31)); 4309 // op: rx 4310 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4311 op &= UINT64_C(7); 4312 op <<= 8; 4313 Value |= op; 4314 break; 4315 } 4316 case Mips::LbRxRyOffMemX16: 4317 case Mips::LbuRxRyOffMemX16: 4318 case Mips::LhRxRyOffMemX16: 4319 case Mips::LhuRxRyOffMemX16: 4320 case Mips::LwRxRyOffMemX16: 4321 case Mips::LwRxSpImmX16: 4322 case Mips::SbRxRyOffMemX16: 4323 case Mips::ShRxRyOffMemX16: 4324 case Mips::SwRxRyOffMemX16: 4325 case Mips::SwRxSpImmX16: { 4326 // op: imm16 4327 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4328 Value |= (op & UINT64_C(2016)) << 16; 4329 Value |= (op & UINT64_C(63488)) << 5; 4330 Value |= (op & UINT64_C(31)); 4331 // op: rx 4332 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4333 op &= UINT64_C(7); 4334 op <<= 8; 4335 Value |= op; 4336 // op: ry 4337 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4338 op &= UINT64_C(7); 4339 op <<= 5; 4340 Value |= op; 4341 break; 4342 } 4343 case Mips::Jal16: 4344 case Mips::JalB16: { 4345 // op: imm26 4346 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4347 Value |= (op & UINT64_C(2031616)) << 5; 4348 Value |= (op & UINT64_C(65011712)) >> 5; 4349 Value |= (op & UINT64_C(65535)); 4350 break; 4351 } 4352 case Mips::AddiuSpImm16: 4353 case Mips::Bteqz16: 4354 case Mips::Btnez16: { 4355 // op: imm8 4356 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4357 op &= UINT64_C(255); 4358 Value |= op; 4359 break; 4360 } 4361 case Mips::PREFX_MM: { 4362 // op: index 4363 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4364 op &= UINT64_C(31); 4365 op <<= 21; 4366 Value |= op; 4367 // op: base 4368 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4369 op &= UINT64_C(31); 4370 op <<= 16; 4371 Value |= op; 4372 // op: hint 4373 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4374 op &= UINT64_C(31); 4375 op <<= 11; 4376 Value |= op; 4377 break; 4378 } 4379 case Mips::LBUX_MM: 4380 case Mips::LHX_MM: 4381 case Mips::LWX_MM: { 4382 // op: index 4383 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4384 op &= UINT64_C(31); 4385 op <<= 21; 4386 Value |= op; 4387 // op: base 4388 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4389 op &= UINT64_C(31); 4390 op <<= 16; 4391 Value |= op; 4392 // op: rd 4393 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4394 op &= UINT64_C(31); 4395 op <<= 11; 4396 Value |= op; 4397 break; 4398 } 4399 case Mips::COPY_S_D: { 4400 // op: n 4401 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4402 op &= UINT64_C(1); 4403 op <<= 16; 4404 Value |= op; 4405 // op: ws 4406 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4407 op &= UINT64_C(31); 4408 op <<= 11; 4409 Value |= op; 4410 // op: rd 4411 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4412 op &= UINT64_C(31); 4413 op <<= 6; 4414 Value |= op; 4415 break; 4416 } 4417 case Mips::SPLATI_D: { 4418 // op: n 4419 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4420 op &= UINT64_C(1); 4421 op <<= 16; 4422 Value |= op; 4423 // op: ws 4424 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4425 op &= UINT64_C(31); 4426 op <<= 11; 4427 Value |= op; 4428 // op: wd 4429 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4430 op &= UINT64_C(31); 4431 op <<= 6; 4432 Value |= op; 4433 break; 4434 } 4435 case Mips::INSVE_D: { 4436 // op: n 4437 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4438 op &= UINT64_C(1); 4439 op <<= 16; 4440 Value |= op; 4441 // op: ws 4442 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4443 op &= UINT64_C(31); 4444 op <<= 11; 4445 Value |= op; 4446 // op: wd 4447 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4448 op &= UINT64_C(31); 4449 op <<= 6; 4450 Value |= op; 4451 break; 4452 } 4453 case Mips::COPY_S_B: 4454 case Mips::COPY_U_B: { 4455 // op: n 4456 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4457 op &= UINT64_C(15); 4458 op <<= 16; 4459 Value |= op; 4460 // op: ws 4461 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4462 op &= UINT64_C(31); 4463 op <<= 11; 4464 Value |= op; 4465 // op: rd 4466 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4467 op &= UINT64_C(31); 4468 op <<= 6; 4469 Value |= op; 4470 break; 4471 } 4472 case Mips::SPLATI_B: { 4473 // op: n 4474 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4475 op &= UINT64_C(15); 4476 op <<= 16; 4477 Value |= op; 4478 // op: ws 4479 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4480 op &= UINT64_C(31); 4481 op <<= 11; 4482 Value |= op; 4483 // op: wd 4484 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4485 op &= UINT64_C(31); 4486 op <<= 6; 4487 Value |= op; 4488 break; 4489 } 4490 case Mips::INSVE_B: { 4491 // op: n 4492 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4493 op &= UINT64_C(15); 4494 op <<= 16; 4495 Value |= op; 4496 // op: ws 4497 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4498 op &= UINT64_C(31); 4499 op <<= 11; 4500 Value |= op; 4501 // op: wd 4502 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4503 op &= UINT64_C(31); 4504 op <<= 6; 4505 Value |= op; 4506 break; 4507 } 4508 case Mips::COPY_S_W: 4509 case Mips::COPY_U_W: { 4510 // op: n 4511 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4512 op &= UINT64_C(3); 4513 op <<= 16; 4514 Value |= op; 4515 // op: ws 4516 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4517 op &= UINT64_C(31); 4518 op <<= 11; 4519 Value |= op; 4520 // op: rd 4521 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4522 op &= UINT64_C(31); 4523 op <<= 6; 4524 Value |= op; 4525 break; 4526 } 4527 case Mips::SPLATI_W: { 4528 // op: n 4529 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4530 op &= UINT64_C(3); 4531 op <<= 16; 4532 Value |= op; 4533 // op: ws 4534 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4535 op &= UINT64_C(31); 4536 op <<= 11; 4537 Value |= op; 4538 // op: wd 4539 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4540 op &= UINT64_C(31); 4541 op <<= 6; 4542 Value |= op; 4543 break; 4544 } 4545 case Mips::INSVE_W: { 4546 // op: n 4547 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4548 op &= UINT64_C(3); 4549 op <<= 16; 4550 Value |= op; 4551 // op: ws 4552 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4553 op &= UINT64_C(31); 4554 op <<= 11; 4555 Value |= op; 4556 // op: wd 4557 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4558 op &= UINT64_C(31); 4559 op <<= 6; 4560 Value |= op; 4561 break; 4562 } 4563 case Mips::COPY_S_H: 4564 case Mips::COPY_U_H: { 4565 // op: n 4566 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4567 op &= UINT64_C(7); 4568 op <<= 16; 4569 Value |= op; 4570 // op: ws 4571 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4572 op &= UINT64_C(31); 4573 op <<= 11; 4574 Value |= op; 4575 // op: rd 4576 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4577 op &= UINT64_C(31); 4578 op <<= 6; 4579 Value |= op; 4580 break; 4581 } 4582 case Mips::SPLATI_H: { 4583 // op: n 4584 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4585 op &= UINT64_C(7); 4586 op <<= 16; 4587 Value |= op; 4588 // op: ws 4589 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4590 op &= UINT64_C(31); 4591 op <<= 11; 4592 Value |= op; 4593 // op: wd 4594 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4595 op &= UINT64_C(31); 4596 op <<= 6; 4597 Value |= op; 4598 break; 4599 } 4600 case Mips::INSVE_H: { 4601 // op: n 4602 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4603 op &= UINT64_C(7); 4604 op <<= 16; 4605 Value |= op; 4606 // op: ws 4607 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4608 op &= UINT64_C(31); 4609 op <<= 11; 4610 Value |= op; 4611 // op: wd 4612 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4613 op &= UINT64_C(31); 4614 op <<= 6; 4615 Value |= op; 4616 break; 4617 } 4618 case Mips::INSERT_D: { 4619 // op: n 4620 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4621 op &= UINT64_C(1); 4622 op <<= 16; 4623 Value |= op; 4624 // op: rs 4625 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4626 op &= UINT64_C(31); 4627 op <<= 11; 4628 Value |= op; 4629 // op: wd 4630 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4631 op &= UINT64_C(31); 4632 op <<= 6; 4633 Value |= op; 4634 break; 4635 } 4636 case Mips::SLDI_D: { 4637 // op: n 4638 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4639 op &= UINT64_C(1); 4640 op <<= 16; 4641 Value |= op; 4642 // op: ws 4643 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4644 op &= UINT64_C(31); 4645 op <<= 11; 4646 Value |= op; 4647 // op: wd 4648 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4649 op &= UINT64_C(31); 4650 op <<= 6; 4651 Value |= op; 4652 break; 4653 } 4654 case Mips::INSERT_B: { 4655 // op: n 4656 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4657 op &= UINT64_C(15); 4658 op <<= 16; 4659 Value |= op; 4660 // op: rs 4661 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4662 op &= UINT64_C(31); 4663 op <<= 11; 4664 Value |= op; 4665 // op: wd 4666 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4667 op &= UINT64_C(31); 4668 op <<= 6; 4669 Value |= op; 4670 break; 4671 } 4672 case Mips::SLDI_B: { 4673 // op: n 4674 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4675 op &= UINT64_C(15); 4676 op <<= 16; 4677 Value |= op; 4678 // op: ws 4679 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4680 op &= UINT64_C(31); 4681 op <<= 11; 4682 Value |= op; 4683 // op: wd 4684 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4685 op &= UINT64_C(31); 4686 op <<= 6; 4687 Value |= op; 4688 break; 4689 } 4690 case Mips::INSERT_W: { 4691 // op: n 4692 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4693 op &= UINT64_C(3); 4694 op <<= 16; 4695 Value |= op; 4696 // op: rs 4697 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4698 op &= UINT64_C(31); 4699 op <<= 11; 4700 Value |= op; 4701 // op: wd 4702 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4703 op &= UINT64_C(31); 4704 op <<= 6; 4705 Value |= op; 4706 break; 4707 } 4708 case Mips::SLDI_W: { 4709 // op: n 4710 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4711 op &= UINT64_C(3); 4712 op <<= 16; 4713 Value |= op; 4714 // op: ws 4715 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4716 op &= UINT64_C(31); 4717 op <<= 11; 4718 Value |= op; 4719 // op: wd 4720 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4721 op &= UINT64_C(31); 4722 op <<= 6; 4723 Value |= op; 4724 break; 4725 } 4726 case Mips::INSERT_H: { 4727 // op: n 4728 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4729 op &= UINT64_C(7); 4730 op <<= 16; 4731 Value |= op; 4732 // op: rs 4733 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4734 op &= UINT64_C(31); 4735 op <<= 11; 4736 Value |= op; 4737 // op: wd 4738 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4739 op &= UINT64_C(31); 4740 op <<= 6; 4741 Value |= op; 4742 break; 4743 } 4744 case Mips::SLDI_H: { 4745 // op: n 4746 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4747 op &= UINT64_C(7); 4748 op <<= 16; 4749 Value |= op; 4750 // op: ws 4751 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4752 op &= UINT64_C(31); 4753 op <<= 11; 4754 Value |= op; 4755 // op: wd 4756 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4757 op &= UINT64_C(31); 4758 op <<= 6; 4759 Value |= op; 4760 break; 4761 } 4762 case Mips::BALC: 4763 case Mips::BC: { 4764 // op: offset 4765 op = getBranchTarget26OpValue(MI, 0, Fixups, STI); 4766 op &= UINT64_C(67108863); 4767 Value |= op; 4768 break; 4769 } 4770 case Mips::BALC_MMR6: 4771 case Mips::BC_MMR6: { 4772 // op: offset 4773 op = getBranchTarget26OpValueMM(MI, 0, Fixups, STI); 4774 op &= UINT64_C(67108863); 4775 Value |= op; 4776 break; 4777 } 4778 case Mips::BAL: 4779 case Mips::BPOSGE32: { 4780 // op: offset 4781 op = getBranchTargetOpValue(MI, 0, Fixups, STI); 4782 op &= UINT64_C(65535); 4783 Value |= op; 4784 break; 4785 } 4786 case Mips::BNZ_B: 4787 case Mips::BNZ_D: 4788 case Mips::BNZ_H: 4789 case Mips::BNZ_V: 4790 case Mips::BNZ_W: 4791 case Mips::BZ_B: 4792 case Mips::BZ_D: 4793 case Mips::BZ_H: 4794 case Mips::BZ_V: 4795 case Mips::BZ_W: { 4796 // op: offset 4797 op = getBranchTargetOpValue(MI, 1, Fixups, STI); 4798 op &= UINT64_C(65535); 4799 Value |= op; 4800 // op: wt 4801 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4802 op &= UINT64_C(31); 4803 op <<= 16; 4804 Value |= op; 4805 break; 4806 } 4807 case Mips::BPOSGE32C_MMR3: { 4808 // op: offset 4809 op = getBranchTargetOpValue1SImm16(MI, 0, Fixups, STI); 4810 op &= UINT64_C(65535); 4811 Value |= op; 4812 break; 4813 } 4814 case Mips::BPOSGE32_MM: { 4815 // op: offset 4816 op = getBranchTargetOpValueMM(MI, 0, Fixups, STI); 4817 op &= UINT64_C(65535); 4818 Value |= op; 4819 break; 4820 } 4821 case Mips::B16_MM: 4822 case Mips::BC16_MMR6: { 4823 // op: offset 4824 op = getBranchTargetOpValueMMPC10(MI, 0, Fixups, STI); 4825 op &= UINT64_C(1023); 4826 Value |= op; 4827 break; 4828 } 4829 case Mips::Move32R16: { 4830 // op: r32 4831 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4832 Value |= (op & UINT64_C(7)) << 5; 4833 Value |= (op & UINT64_C(24)); 4834 // op: rz 4835 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4836 op &= UINT64_C(7); 4837 Value |= op; 4838 break; 4839 } 4840 case Mips::CLO: 4841 case Mips::CLZ: 4842 case Mips::DCLO: 4843 case Mips::DCLZ: { 4844 // op: rd 4845 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4846 Value |= (op & UINT64_C(31)) << 16; 4847 Value |= (op & UINT64_C(31)) << 11; 4848 // op: rs 4849 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4850 op &= UINT64_C(31); 4851 op <<= 21; 4852 Value |= op; 4853 break; 4854 } 4855 case Mips::MFHI16_MM: 4856 case Mips::MFLO16_MM: { 4857 // op: rd 4858 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4859 op &= UINT64_C(31); 4860 Value |= op; 4861 break; 4862 } 4863 case Mips::MFHI: 4864 case Mips::MFHI64: 4865 case Mips::MFLO: 4866 case Mips::MFLO64: { 4867 // op: rd 4868 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4869 op &= UINT64_C(31); 4870 op <<= 11; 4871 Value |= op; 4872 break; 4873 } 4874 case Mips::MFHI_DSP: 4875 case Mips::MFLO_DSP: { 4876 // op: rd 4877 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4878 op &= UINT64_C(31); 4879 op <<= 11; 4880 Value |= op; 4881 // op: ac 4882 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4883 op &= UINT64_C(3); 4884 op <<= 21; 4885 Value |= op; 4886 break; 4887 } 4888 case Mips::LWXS_MM: { 4889 // op: rd 4890 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4891 op &= UINT64_C(31); 4892 op <<= 11; 4893 Value |= op; 4894 // op: base 4895 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4896 op &= UINT64_C(31); 4897 op <<= 16; 4898 Value |= op; 4899 // op: index 4900 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4901 op &= UINT64_C(31); 4902 op <<= 21; 4903 Value |= op; 4904 break; 4905 } 4906 case Mips::LBUX: 4907 case Mips::LHX: 4908 case Mips::LWX: { 4909 // op: rd 4910 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4911 op &= UINT64_C(31); 4912 op <<= 11; 4913 Value |= op; 4914 // op: base 4915 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4916 op &= UINT64_C(31); 4917 op <<= 21; 4918 Value |= op; 4919 // op: index 4920 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4921 op &= UINT64_C(31); 4922 op <<= 16; 4923 Value |= op; 4924 break; 4925 } 4926 case Mips::REPL_PH: 4927 case Mips::REPL_PH_MM: 4928 case Mips::REPL_QB: { 4929 // op: rd 4930 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4931 op &= UINT64_C(31); 4932 op <<= 11; 4933 Value |= op; 4934 // op: imm 4935 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4936 op &= UINT64_C(1023); 4937 op <<= 16; 4938 Value |= op; 4939 break; 4940 } 4941 case Mips::RDDSP: { 4942 // op: rd 4943 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4944 op &= UINT64_C(31); 4945 op <<= 11; 4946 Value |= op; 4947 // op: mask 4948 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4949 op &= UINT64_C(1023); 4950 op <<= 16; 4951 Value |= op; 4952 break; 4953 } 4954 case Mips::ADDQH_PH_MMR2: 4955 case Mips::ADDQH_R_PH_MMR2: 4956 case Mips::ADDQH_R_W_MMR2: 4957 case Mips::ADDQH_W_MMR2: 4958 case Mips::ADDQ_PH_MM: 4959 case Mips::ADDQ_S_PH_MM: 4960 case Mips::ADDQ_S_W_MM: 4961 case Mips::ADDSC_MM: 4962 case Mips::ADDUH_QB_MMR2: 4963 case Mips::ADDUH_R_QB_MMR2: 4964 case Mips::ADDU_PH_MMR2: 4965 case Mips::ADDU_QB_MM: 4966 case Mips::ADDU_S_PH_MMR2: 4967 case Mips::ADDU_S_QB_MM: 4968 case Mips::ADDWC_MM: 4969 case Mips::CMPGDU_EQ_QB_MMR2: 4970 case Mips::CMPGDU_LE_QB_MMR2: 4971 case Mips::CMPGDU_LT_QB_MMR2: 4972 case Mips::MODSUB_MM: 4973 case Mips::MULEQ_S_W_PHL_MM: 4974 case Mips::MULEQ_S_W_PHR_MM: 4975 case Mips::MULEU_S_PH_QBL_MM: 4976 case Mips::MULEU_S_PH_QBR_MM: 4977 case Mips::MULQ_RS_PH_MM: 4978 case Mips::MULQ_RS_W_MMR2: 4979 case Mips::MULQ_S_PH_MMR2: 4980 case Mips::MULQ_S_W_MMR2: 4981 case Mips::MUL_PH_MMR2: 4982 case Mips::MUL_S_PH_MMR2: 4983 case Mips::PACKRL_PH_MM: 4984 case Mips::PICK_PH_MM: 4985 case Mips::PICK_QB_MM: 4986 case Mips::PRECRQU_S_QB_PH_MM: 4987 case Mips::PRECRQ_PH_W_MM: 4988 case Mips::PRECRQ_QB_PH_MM: 4989 case Mips::PRECRQ_RS_PH_W_MM: 4990 case Mips::PRECR_QB_PH_MMR2: 4991 case Mips::SELEQZ_MMR6: 4992 case Mips::SELNEZ_MMR6: 4993 case Mips::SUBQH_PH_MMR2: 4994 case Mips::SUBQH_R_PH_MMR2: 4995 case Mips::SUBQH_R_W_MMR2: 4996 case Mips::SUBQH_W_MMR2: 4997 case Mips::SUBQ_PH_MM: 4998 case Mips::SUBQ_S_PH_MM: 4999 case Mips::SUBQ_S_W_MM: 5000 case Mips::SUBUH_QB_MMR2: 5001 case Mips::SUBUH_R_QB_MMR2: 5002 case Mips::SUBU_PH_MMR2: 5003 case Mips::SUBU_QB_MM: 5004 case Mips::SUBU_S_PH_MMR2: 5005 case Mips::SUBU_S_QB_MM: { 5006 // op: rd 5007 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5008 op &= UINT64_C(31); 5009 op <<= 11; 5010 Value |= op; 5011 // op: rs 5012 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5013 op &= UINT64_C(31); 5014 op <<= 16; 5015 Value |= op; 5016 // op: rt 5017 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5018 op &= UINT64_C(31); 5019 op <<= 21; 5020 Value |= op; 5021 break; 5022 } 5023 case Mips::LSA_MMR6: { 5024 // op: rd 5025 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5026 op &= UINT64_C(31); 5027 op <<= 11; 5028 Value |= op; 5029 // op: rs 5030 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5031 op &= UINT64_C(31); 5032 op <<= 16; 5033 Value |= op; 5034 // op: rt 5035 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5036 op &= UINT64_C(31); 5037 op <<= 21; 5038 Value |= op; 5039 // op: imm2 5040 op = getUImmWithOffsetEncoding<2, 1>(MI, 3, Fixups, STI); 5041 op &= UINT64_C(3); 5042 op <<= 9; 5043 Value |= op; 5044 break; 5045 } 5046 case Mips::CLO_R6: 5047 case Mips::CLZ_R6: 5048 case Mips::DCLO_R6: 5049 case Mips::DCLZ_R6: 5050 case Mips::DPOP: 5051 case Mips::JALR: 5052 case Mips::JALR64: 5053 case Mips::JALR_HB: 5054 case Mips::JALR_HB64: 5055 case Mips::POP: 5056 case Mips::RADDU_W_QB: { 5057 // op: rd 5058 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5059 op &= UINT64_C(31); 5060 op <<= 11; 5061 Value |= op; 5062 // op: rs 5063 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5064 op &= UINT64_C(31); 5065 op <<= 21; 5066 Value |= op; 5067 break; 5068 } 5069 case Mips::MOVF_I: 5070 case Mips::MOVF_I64: 5071 case Mips::MOVT_I: 5072 case Mips::MOVT_I64: { 5073 // op: rd 5074 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5075 op &= UINT64_C(31); 5076 op <<= 11; 5077 Value |= op; 5078 // op: rs 5079 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5080 op &= UINT64_C(31); 5081 op <<= 21; 5082 Value |= op; 5083 // op: fcc 5084 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5085 op &= UINT64_C(7); 5086 op <<= 18; 5087 Value |= op; 5088 break; 5089 } 5090 case Mips::ADD: 5091 case Mips::ADDQH_PH: 5092 case Mips::ADDQH_R_PH: 5093 case Mips::ADDQH_R_W: 5094 case Mips::ADDQH_W: 5095 case Mips::ADDQ_PH: 5096 case Mips::ADDQ_S_PH: 5097 case Mips::ADDQ_S_W: 5098 case Mips::ADDSC: 5099 case Mips::ADDUH_QB: 5100 case Mips::ADDUH_R_QB: 5101 case Mips::ADDU_PH: 5102 case Mips::ADDU_QB: 5103 case Mips::ADDU_S_PH: 5104 case Mips::ADDU_S_QB: 5105 case Mips::ADDWC: 5106 case Mips::ADDu: 5107 case Mips::AND: 5108 case Mips::AND64: 5109 case Mips::BADDu: 5110 case Mips::DADD: 5111 case Mips::DADDu: 5112 case Mips::DDIV: 5113 case Mips::DDIVU: 5114 case Mips::DIV: 5115 case Mips::DIVU: 5116 case Mips::DMOD: 5117 case Mips::DMODU: 5118 case Mips::DMUH: 5119 case Mips::DMUHU: 5120 case Mips::DMUL: 5121 case Mips::DMULU: 5122 case Mips::DMUL_R6: 5123 case Mips::DSUB: 5124 case Mips::DSUBu: 5125 case Mips::MOD: 5126 case Mips::MODSUB: 5127 case Mips::MODU: 5128 case Mips::MOVN_I64_I: 5129 case Mips::MOVN_I64_I64: 5130 case Mips::MOVN_I_I: 5131 case Mips::MOVN_I_I64: 5132 case Mips::MOVZ_I64_I: 5133 case Mips::MOVZ_I64_I64: 5134 case Mips::MOVZ_I_I: 5135 case Mips::MOVZ_I_I64: 5136 case Mips::MUH: 5137 case Mips::MUHU: 5138 case Mips::MUL: 5139 case Mips::MULEQ_S_W_PHL: 5140 case Mips::MULEQ_S_W_PHR: 5141 case Mips::MULEU_S_PH_QBL: 5142 case Mips::MULEU_S_PH_QBR: 5143 case Mips::MULQ_RS_PH: 5144 case Mips::MULQ_RS_W: 5145 case Mips::MULQ_S_PH: 5146 case Mips::MULQ_S_W: 5147 case Mips::MULU: 5148 case Mips::MUL_PH: 5149 case Mips::MUL_R6: 5150 case Mips::MUL_S_PH: 5151 case Mips::NOR: 5152 case Mips::NOR64: 5153 case Mips::OR: 5154 case Mips::OR64: 5155 case Mips::SELEQZ: 5156 case Mips::SELEQZ64: 5157 case Mips::SELNEZ: 5158 case Mips::SELNEZ64: 5159 case Mips::SEQ: 5160 case Mips::SLT: 5161 case Mips::SLT64: 5162 case Mips::SLTu: 5163 case Mips::SLTu64: 5164 case Mips::SNE: 5165 case Mips::SUB: 5166 case Mips::SUBQH_PH: 5167 case Mips::SUBQH_R_PH: 5168 case Mips::SUBQH_R_W: 5169 case Mips::SUBQH_W: 5170 case Mips::SUBQ_PH: 5171 case Mips::SUBQ_S_PH: 5172 case Mips::SUBQ_S_W: 5173 case Mips::SUBUH_QB: 5174 case Mips::SUBUH_R_QB: 5175 case Mips::SUBU_PH: 5176 case Mips::SUBU_QB: 5177 case Mips::SUBU_S_PH: 5178 case Mips::SUBU_S_QB: 5179 case Mips::SUBu: 5180 case Mips::V3MULU: 5181 case Mips::VMM0: 5182 case Mips::VMULU: 5183 case Mips::XOR: 5184 case Mips::XOR64: { 5185 // op: rd 5186 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5187 op &= UINT64_C(31); 5188 op <<= 11; 5189 Value |= op; 5190 // op: rs 5191 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5192 op &= UINT64_C(31); 5193 op <<= 21; 5194 Value |= op; 5195 // op: rt 5196 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5197 op &= UINT64_C(31); 5198 op <<= 16; 5199 Value |= op; 5200 break; 5201 } 5202 case Mips::ALIGN: { 5203 // op: rd 5204 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5205 op &= UINT64_C(31); 5206 op <<= 11; 5207 Value |= op; 5208 // op: rs 5209 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5210 op &= UINT64_C(31); 5211 op <<= 21; 5212 Value |= op; 5213 // op: rt 5214 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5215 op &= UINT64_C(31); 5216 op <<= 16; 5217 Value |= op; 5218 // op: bp 5219 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 5220 op &= UINT64_C(3); 5221 op <<= 6; 5222 Value |= op; 5223 break; 5224 } 5225 case Mips::ALIGN_MMR6: { 5226 // op: rd 5227 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5228 op &= UINT64_C(31); 5229 op <<= 11; 5230 Value |= op; 5231 // op: rs 5232 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5233 op &= UINT64_C(31); 5234 op <<= 21; 5235 Value |= op; 5236 // op: rt 5237 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5238 op &= UINT64_C(31); 5239 op <<= 16; 5240 Value |= op; 5241 // op: bp 5242 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 5243 op &= UINT64_C(3); 5244 op <<= 9; 5245 Value |= op; 5246 break; 5247 } 5248 case Mips::DALIGN: { 5249 // op: rd 5250 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5251 op &= UINT64_C(31); 5252 op <<= 11; 5253 Value |= op; 5254 // op: rs 5255 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5256 op &= UINT64_C(31); 5257 op <<= 21; 5258 Value |= op; 5259 // op: rt 5260 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5261 op &= UINT64_C(31); 5262 op <<= 16; 5263 Value |= op; 5264 // op: bp 5265 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 5266 op &= UINT64_C(7); 5267 op <<= 6; 5268 Value |= op; 5269 break; 5270 } 5271 case Mips::DLSA_R6: 5272 case Mips::LSA_R6: { 5273 // op: rd 5274 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5275 op &= UINT64_C(31); 5276 op <<= 11; 5277 Value |= op; 5278 // op: rs 5279 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5280 op &= UINT64_C(31); 5281 op <<= 21; 5282 Value |= op; 5283 // op: rt 5284 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5285 op &= UINT64_C(31); 5286 op <<= 16; 5287 Value |= op; 5288 // op: imm2 5289 op = getUImmWithOffsetEncoding<2, 1>(MI, 3, Fixups, STI); 5290 op &= UINT64_C(3); 5291 op <<= 6; 5292 Value |= op; 5293 break; 5294 } 5295 case Mips::SHLLV_PH_MM: 5296 case Mips::SHLLV_QB_MM: 5297 case Mips::SHLLV_S_PH_MM: 5298 case Mips::SHLLV_S_W_MM: 5299 case Mips::SHRAV_PH_MM: 5300 case Mips::SHRAV_QB_MMR2: 5301 case Mips::SHRAV_R_PH_MM: 5302 case Mips::SHRAV_R_QB_MMR2: 5303 case Mips::SHRAV_R_W_MM: 5304 case Mips::SHRLV_PH_MMR2: 5305 case Mips::SHRLV_QB_MM: { 5306 // op: rd 5307 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5308 op &= UINT64_C(31); 5309 op <<= 11; 5310 Value |= op; 5311 // op: rs 5312 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5313 op &= UINT64_C(31); 5314 op <<= 16; 5315 Value |= op; 5316 // op: rt 5317 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5318 op &= UINT64_C(31); 5319 op <<= 21; 5320 Value |= op; 5321 break; 5322 } 5323 case Mips::ABSQ_S_PH: 5324 case Mips::ABSQ_S_QB: 5325 case Mips::ABSQ_S_W: 5326 case Mips::BITREV: 5327 case Mips::BITSWAP: 5328 case Mips::DBITSWAP: 5329 case Mips::DSBH: 5330 case Mips::DSHD: 5331 case Mips::DSLL64_32: 5332 case Mips::PRECEQU_PH_QBL: 5333 case Mips::PRECEQU_PH_QBLA: 5334 case Mips::PRECEQU_PH_QBR: 5335 case Mips::PRECEQU_PH_QBRA: 5336 case Mips::PRECEQ_W_PHL: 5337 case Mips::PRECEQ_W_PHR: 5338 case Mips::PRECEU_PH_QBL: 5339 case Mips::PRECEU_PH_QBLA: 5340 case Mips::PRECEU_PH_QBR: 5341 case Mips::PRECEU_PH_QBRA: 5342 case Mips::REPLV_PH: 5343 case Mips::REPLV_QB: 5344 case Mips::SEB: 5345 case Mips::SEB64: 5346 case Mips::SEH: 5347 case Mips::SEH64: 5348 case Mips::SLL64_32: 5349 case Mips::SLL64_64: 5350 case Mips::WSBH: { 5351 // op: rd 5352 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5353 op &= UINT64_C(31); 5354 op <<= 11; 5355 Value |= op; 5356 // op: rt 5357 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5358 op &= UINT64_C(31); 5359 op <<= 16; 5360 Value |= op; 5361 break; 5362 } 5363 case Mips::DROTRV: 5364 case Mips::DSLLV: 5365 case Mips::DSRAV: 5366 case Mips::DSRLV: 5367 case Mips::ROTRV: 5368 case Mips::SLLV: 5369 case Mips::SRAV: 5370 case Mips::SRLV: { 5371 // op: rd 5372 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5373 op &= UINT64_C(31); 5374 op <<= 11; 5375 Value |= op; 5376 // op: rt 5377 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5378 op &= UINT64_C(31); 5379 op <<= 16; 5380 Value |= op; 5381 // op: rs 5382 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5383 op &= UINT64_C(31); 5384 op <<= 21; 5385 Value |= op; 5386 break; 5387 } 5388 case Mips::SHLLV_PH: 5389 case Mips::SHLLV_QB: 5390 case Mips::SHLLV_S_PH: 5391 case Mips::SHLLV_S_W: 5392 case Mips::SHLL_PH: 5393 case Mips::SHLL_QB: 5394 case Mips::SHLL_S_PH: 5395 case Mips::SHLL_S_W: 5396 case Mips::SHRAV_PH: 5397 case Mips::SHRAV_QB: 5398 case Mips::SHRAV_R_PH: 5399 case Mips::SHRAV_R_QB: 5400 case Mips::SHRAV_R_W: 5401 case Mips::SHRA_PH: 5402 case Mips::SHRA_QB: 5403 case Mips::SHRA_R_PH: 5404 case Mips::SHRA_R_QB: 5405 case Mips::SHRA_R_W: 5406 case Mips::SHRLV_PH: 5407 case Mips::SHRLV_QB: 5408 case Mips::SHRL_PH: 5409 case Mips::SHRL_QB: { 5410 // op: rd 5411 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5412 op &= UINT64_C(31); 5413 op <<= 11; 5414 Value |= op; 5415 // op: rt 5416 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5417 op &= UINT64_C(31); 5418 op <<= 16; 5419 Value |= op; 5420 // op: rs_sa 5421 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5422 op &= UINT64_C(31); 5423 op <<= 21; 5424 Value |= op; 5425 break; 5426 } 5427 case Mips::DROTR: 5428 case Mips::DROTR32: 5429 case Mips::DSLL: 5430 case Mips::DSLL32: 5431 case Mips::DSRA: 5432 case Mips::DSRA32: 5433 case Mips::DSRL: 5434 case Mips::DSRL32: 5435 case Mips::ROTR: 5436 case Mips::SLL: 5437 case Mips::SRA: 5438 case Mips::SRL: { 5439 // op: rd 5440 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5441 op &= UINT64_C(31); 5442 op <<= 11; 5443 Value |= op; 5444 // op: rt 5445 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5446 op &= UINT64_C(31); 5447 op <<= 16; 5448 Value |= op; 5449 // op: shamt 5450 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5451 op &= UINT64_C(31); 5452 op <<= 6; 5453 Value |= op; 5454 break; 5455 } 5456 case Mips::ROTRV_MM: 5457 case Mips::SLLV_MM: 5458 case Mips::SRAV_MM: 5459 case Mips::SRLV_MM: { 5460 // op: rd 5461 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5462 op &= UINT64_C(31); 5463 op <<= 11; 5464 Value |= op; 5465 // op: rt 5466 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5467 op &= UINT64_C(31); 5468 op <<= 21; 5469 Value |= op; 5470 // op: rs 5471 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5472 op &= UINT64_C(31); 5473 op <<= 16; 5474 Value |= op; 5475 break; 5476 } 5477 case Mips::ADDU_MMR6: 5478 case Mips::ADD_MMR6: 5479 case Mips::AND_MMR6: 5480 case Mips::DIVU_MMR6: 5481 case Mips::DIV_MMR6: 5482 case Mips::MODU_MMR6: 5483 case Mips::MOD_MMR6: 5484 case Mips::MUHU_MMR6: 5485 case Mips::MUH_MMR6: 5486 case Mips::MULU_MMR6: 5487 case Mips::MUL_MMR6: 5488 case Mips::NOR_MMR6: 5489 case Mips::OR_MMR6: 5490 case Mips::SUBU_MMR6: 5491 case Mips::SUB_MMR6: 5492 case Mips::XOR_MMR6: { 5493 // op: rd 5494 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5495 op &= UINT64_C(31); 5496 op <<= 11; 5497 Value |= op; 5498 // op: rt 5499 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5500 op &= UINT64_C(31); 5501 op <<= 21; 5502 Value |= op; 5503 // op: rs 5504 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5505 op &= UINT64_C(31); 5506 op <<= 16; 5507 Value |= op; 5508 break; 5509 } 5510 case Mips::MFHI_MM: 5511 case Mips::MFLO_MM: { 5512 // op: rd 5513 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5514 op &= UINT64_C(31); 5515 op <<= 16; 5516 Value |= op; 5517 break; 5518 } 5519 case Mips::BITSWAP_MMR6: { 5520 // op: rd 5521 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5522 op &= UINT64_C(31); 5523 op <<= 16; 5524 Value |= op; 5525 // op: rt 5526 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5527 op &= UINT64_C(31); 5528 op <<= 21; 5529 Value |= op; 5530 break; 5531 } 5532 case Mips::CLO_MM: 5533 case Mips::CLZ_MM: { 5534 // op: rd 5535 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5536 op &= UINT64_C(31); 5537 op <<= 21; 5538 Value |= op; 5539 // op: rs 5540 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5541 op &= UINT64_C(31); 5542 op <<= 16; 5543 Value |= op; 5544 break; 5545 } 5546 case Mips::MOVF_I_MM: 5547 case Mips::MOVT_I_MM: { 5548 // op: rd 5549 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5550 op &= UINT64_C(31); 5551 op <<= 21; 5552 Value |= op; 5553 // op: rs 5554 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5555 op &= UINT64_C(31); 5556 op <<= 16; 5557 Value |= op; 5558 // op: fcc 5559 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5560 op &= UINT64_C(7); 5561 op <<= 13; 5562 Value |= op; 5563 break; 5564 } 5565 case Mips::SEB_MM: 5566 case Mips::SEH_MM: 5567 case Mips::WSBH_MM: { 5568 // op: rd 5569 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5570 op &= UINT64_C(31); 5571 op <<= 21; 5572 Value |= op; 5573 // op: rt 5574 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5575 op &= UINT64_C(31); 5576 op <<= 16; 5577 Value |= op; 5578 break; 5579 } 5580 case Mips::ROTR_MM: 5581 case Mips::SLL_MM: 5582 case Mips::SLL_MMR6: 5583 case Mips::SRA_MM: 5584 case Mips::SRL_MM: { 5585 // op: rd 5586 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5587 op &= UINT64_C(31); 5588 op <<= 21; 5589 Value |= op; 5590 // op: rt 5591 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5592 op &= UINT64_C(31); 5593 op <<= 16; 5594 Value |= op; 5595 // op: shamt 5596 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5597 op &= UINT64_C(31); 5598 op <<= 11; 5599 Value |= op; 5600 break; 5601 } 5602 case Mips::CFCMSA: { 5603 // op: rd 5604 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5605 op &= UINT64_C(31); 5606 op <<= 6; 5607 Value |= op; 5608 // op: cs 5609 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5610 op &= UINT64_C(31); 5611 op <<= 11; 5612 Value |= op; 5613 break; 5614 } 5615 case Mips::LI16_MM: 5616 case Mips::LI16_MMR6: { 5617 // op: rd 5618 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5619 op &= UINT64_C(7); 5620 op <<= 7; 5621 Value |= op; 5622 // op: imm 5623 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5624 op &= UINT64_C(127); 5625 Value |= op; 5626 break; 5627 } 5628 case Mips::ADDIUR1SP_MM: { 5629 // op: rd 5630 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5631 op &= UINT64_C(7); 5632 op <<= 7; 5633 Value |= op; 5634 // op: imm 5635 op = getUImm6Lsl2Encoding(MI, 1, Fixups, STI); 5636 op &= UINT64_C(63); 5637 op <<= 1; 5638 Value |= op; 5639 break; 5640 } 5641 case Mips::ADDIUR2_MM: { 5642 // op: rd 5643 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5644 op &= UINT64_C(7); 5645 op <<= 7; 5646 Value |= op; 5647 // op: rs 5648 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5649 op &= UINT64_C(7); 5650 op <<= 4; 5651 Value |= op; 5652 // op: imm 5653 op = getSImm3Lsa2Value(MI, 2, Fixups, STI); 5654 op &= UINT64_C(7); 5655 op <<= 1; 5656 Value |= op; 5657 break; 5658 } 5659 case Mips::ANDI16_MM: 5660 case Mips::ANDI16_MMR6: { 5661 // op: rd 5662 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5663 op &= UINT64_C(7); 5664 op <<= 7; 5665 Value |= op; 5666 // op: rs 5667 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5668 op &= UINT64_C(7); 5669 op <<= 4; 5670 Value |= op; 5671 // op: imm 5672 op = getUImm4AndValue(MI, 2, Fixups, STI); 5673 op &= UINT64_C(15); 5674 Value |= op; 5675 break; 5676 } 5677 case Mips::SLL16_MM: 5678 case Mips::SLL16_MMR6: 5679 case Mips::SRL16_MM: 5680 case Mips::SRL16_MMR6: { 5681 // op: rd 5682 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5683 op &= UINT64_C(7); 5684 op <<= 7; 5685 Value |= op; 5686 // op: rt 5687 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5688 op &= UINT64_C(7); 5689 op <<= 4; 5690 Value |= op; 5691 // op: shamt 5692 op = getUImm3Mod8Encoding(MI, 2, Fixups, STI); 5693 op &= UINT64_C(7); 5694 op <<= 1; 5695 Value |= op; 5696 break; 5697 } 5698 case Mips::ADDU16_MM: 5699 case Mips::SUBU16_MM: { 5700 // op: rd 5701 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5702 op &= UINT64_C(7); 5703 op <<= 7; 5704 Value |= op; 5705 // op: rt 5706 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5707 op &= UINT64_C(7); 5708 op <<= 4; 5709 Value |= op; 5710 // op: rs 5711 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5712 op &= UINT64_C(7); 5713 op <<= 1; 5714 Value |= op; 5715 break; 5716 } 5717 case Mips::ADDIUS5_MM: { 5718 // op: rd 5719 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5720 op &= UINT64_C(31); 5721 op <<= 5; 5722 Value |= op; 5723 // op: imm 5724 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5725 op &= UINT64_C(15); 5726 op <<= 1; 5727 Value |= op; 5728 break; 5729 } 5730 case Mips::JALR16_MM: 5731 case Mips::JALRS16_MM: 5732 case Mips::JR16_MM: 5733 case Mips::JRC16_MM: { 5734 // op: rs 5735 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5736 op &= UINT64_C(31); 5737 Value |= op; 5738 break; 5739 } 5740 case Mips::DVP_MMR6: 5741 case Mips::EVP_MMR6: 5742 case Mips::GINVI_MMR6: 5743 case Mips::JR_MM: 5744 case Mips::MTHI_MM: 5745 case Mips::MTLO_MM: { 5746 // op: rs 5747 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5748 op &= UINT64_C(31); 5749 op <<= 16; 5750 Value |= op; 5751 break; 5752 } 5753 case Mips::MFHI_DSP_MM: 5754 case Mips::MFLO_DSP_MM: { 5755 // op: rs 5756 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5757 op &= UINT64_C(31); 5758 op <<= 16; 5759 Value |= op; 5760 // op: ac 5761 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5762 op &= UINT64_C(3); 5763 op <<= 14; 5764 Value |= op; 5765 break; 5766 } 5767 case Mips::TEQI_MM: 5768 case Mips::TGEIU_MM: 5769 case Mips::TGEI_MM: 5770 case Mips::TLTIU_MM: 5771 case Mips::TLTI_MM: 5772 case Mips::TNEI_MM: { 5773 // op: rs 5774 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5775 op &= UINT64_C(31); 5776 op <<= 16; 5777 Value |= op; 5778 // op: imm16 5779 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5780 op &= UINT64_C(65535); 5781 Value |= op; 5782 break; 5783 } 5784 case Mips::BEQZC_MM: 5785 case Mips::BGEZALS_MM: 5786 case Mips::BGEZAL_MM: 5787 case Mips::BGEZ_MM: 5788 case Mips::BGTZ_MM: 5789 case Mips::BLEZ_MM: 5790 case Mips::BLTZALS_MM: 5791 case Mips::BLTZAL_MM: 5792 case Mips::BLTZ_MM: 5793 case Mips::BNEZC_MM: { 5794 // op: rs 5795 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5796 op &= UINT64_C(31); 5797 op <<= 16; 5798 Value |= op; 5799 // op: offset 5800 op = getBranchTargetOpValueMM(MI, 1, Fixups, STI); 5801 op &= UINT64_C(65535); 5802 Value |= op; 5803 break; 5804 } 5805 case Mips::MADDU_MM: 5806 case Mips::MADD_MM: 5807 case Mips::MSUBU_MM: 5808 case Mips::MSUB_MM: 5809 case Mips::MULT_MM: 5810 case Mips::MULTu_MM: 5811 case Mips::SDIV_MM: 5812 case Mips::UDIV_MM: { 5813 // op: rs 5814 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5815 op &= UINT64_C(31); 5816 op <<= 16; 5817 Value |= op; 5818 // op: rt 5819 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5820 op &= UINT64_C(31); 5821 op <<= 21; 5822 Value |= op; 5823 break; 5824 } 5825 case Mips::TEQ_MM: 5826 case Mips::TGEU_MM: 5827 case Mips::TGE_MM: 5828 case Mips::TLTU_MM: 5829 case Mips::TLT_MM: 5830 case Mips::TNE_MM: { 5831 // op: rs 5832 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5833 op &= UINT64_C(31); 5834 op <<= 16; 5835 Value |= op; 5836 // op: rt 5837 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5838 op &= UINT64_C(31); 5839 op <<= 21; 5840 Value |= op; 5841 // op: code_ 5842 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5843 op &= UINT64_C(15); 5844 op <<= 12; 5845 Value |= op; 5846 break; 5847 } 5848 case Mips::BEQ_MM: 5849 case Mips::BNE_MM: { 5850 // op: rs 5851 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5852 op &= UINT64_C(31); 5853 op <<= 16; 5854 Value |= op; 5855 // op: rt 5856 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5857 op &= UINT64_C(31); 5858 op <<= 21; 5859 Value |= op; 5860 // op: offset 5861 op = getBranchTargetOpValueMM(MI, 2, Fixups, STI); 5862 op &= UINT64_C(65535); 5863 Value |= op; 5864 break; 5865 } 5866 case Mips::GINVT_MMR6: { 5867 // op: rs 5868 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5869 op &= UINT64_C(31); 5870 op <<= 16; 5871 Value |= op; 5872 // op: type 5873 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5874 op &= UINT64_C(3); 5875 op <<= 9; 5876 Value |= op; 5877 break; 5878 } 5879 case Mips::GINVI: 5880 case Mips::JR: 5881 case Mips::JR64: 5882 case Mips::JR_HB: 5883 case Mips::JR_HB64: 5884 case Mips::JR_HB64_R6: 5885 case Mips::JR_HB_R6: 5886 case Mips::MTHI: 5887 case Mips::MTHI64: 5888 case Mips::MTLO: 5889 case Mips::MTLO64: 5890 case Mips::MTM0: 5891 case Mips::MTM1: 5892 case Mips::MTM2: 5893 case Mips::MTP0: 5894 case Mips::MTP1: 5895 case Mips::MTP2: { 5896 // op: rs 5897 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5898 op &= UINT64_C(31); 5899 op <<= 21; 5900 Value |= op; 5901 break; 5902 } 5903 case Mips::ALUIPC: 5904 case Mips::AUIPC: { 5905 // op: rs 5906 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5907 op &= UINT64_C(31); 5908 op <<= 21; 5909 Value |= op; 5910 // op: imm 5911 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5912 op &= UINT64_C(65535); 5913 Value |= op; 5914 break; 5915 } 5916 case Mips::DAHI: 5917 case Mips::DATI: { 5918 // op: rs 5919 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5920 op &= UINT64_C(31); 5921 op <<= 21; 5922 Value |= op; 5923 // op: imm 5924 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5925 op &= UINT64_C(65535); 5926 Value |= op; 5927 break; 5928 } 5929 case Mips::LDPC: { 5930 // op: rs 5931 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5932 op &= UINT64_C(31); 5933 op <<= 21; 5934 Value |= op; 5935 // op: imm 5936 op = getSimm18Lsl3Encoding(MI, 1, Fixups, STI); 5937 op &= UINT64_C(262143); 5938 Value |= op; 5939 break; 5940 } 5941 case Mips::ADDIUPC: 5942 case Mips::LWPC: 5943 case Mips::LWUPC: { 5944 // op: rs 5945 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5946 op &= UINT64_C(31); 5947 op <<= 21; 5948 Value |= op; 5949 // op: imm 5950 op = getSimm19Lsl2Encoding(MI, 1, Fixups, STI); 5951 op &= UINT64_C(524287); 5952 Value |= op; 5953 break; 5954 } 5955 case Mips::TEQI: 5956 case Mips::TGEI: 5957 case Mips::TGEIU: 5958 case Mips::TLTI: 5959 case Mips::TNEI: 5960 case Mips::TTLTIU: { 5961 // op: rs 5962 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5963 op &= UINT64_C(31); 5964 op <<= 21; 5965 Value |= op; 5966 // op: imm16 5967 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5968 op &= UINT64_C(65535); 5969 Value |= op; 5970 break; 5971 } 5972 case Mips::WRDSP: { 5973 // op: rs 5974 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5975 op &= UINT64_C(31); 5976 op <<= 21; 5977 Value |= op; 5978 // op: mask 5979 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5980 op &= UINT64_C(1023); 5981 op <<= 11; 5982 Value |= op; 5983 break; 5984 } 5985 case Mips::BEQZC: 5986 case Mips::BEQZC64: 5987 case Mips::BNEZC: 5988 case Mips::BNEZC64: { 5989 // op: rs 5990 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5991 op &= UINT64_C(31); 5992 op <<= 21; 5993 Value |= op; 5994 // op: offset 5995 op = getBranchTarget21OpValue(MI, 1, Fixups, STI); 5996 op &= UINT64_C(2097151); 5997 Value |= op; 5998 break; 5999 } 6000 case Mips::BEQZC_MMR6: 6001 case Mips::BNEZC_MMR6: { 6002 // op: rs 6003 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6004 op &= UINT64_C(31); 6005 op <<= 21; 6006 Value |= op; 6007 // op: offset 6008 op = getBranchTarget21OpValueMM(MI, 1, Fixups, STI); 6009 op &= UINT64_C(2097151); 6010 Value |= op; 6011 break; 6012 } 6013 case Mips::BGEZ: 6014 case Mips::BGEZ64: 6015 case Mips::BGEZAL: 6016 case Mips::BGEZALL: 6017 case Mips::BGEZL: 6018 case Mips::BGTZ: 6019 case Mips::BGTZ64: 6020 case Mips::BGTZL: 6021 case Mips::BLEZ: 6022 case Mips::BLEZ64: 6023 case Mips::BLEZL: 6024 case Mips::BLTZ: 6025 case Mips::BLTZ64: 6026 case Mips::BLTZAL: 6027 case Mips::BLTZALL: 6028 case Mips::BLTZL: { 6029 // op: rs 6030 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6031 op &= UINT64_C(31); 6032 op <<= 21; 6033 Value |= op; 6034 // op: offset 6035 op = getBranchTargetOpValue(MI, 1, Fixups, STI); 6036 op &= UINT64_C(65535); 6037 Value |= op; 6038 break; 6039 } 6040 case Mips::BBIT0: 6041 case Mips::BBIT032: 6042 case Mips::BBIT1: 6043 case Mips::BBIT132: { 6044 // op: rs 6045 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6046 op &= UINT64_C(31); 6047 op <<= 21; 6048 Value |= op; 6049 // op: p 6050 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6051 op &= UINT64_C(31); 6052 op <<= 16; 6053 Value |= op; 6054 // op: offset 6055 op = getBranchTargetOpValue(MI, 2, Fixups, STI); 6056 op &= UINT64_C(65535); 6057 Value |= op; 6058 break; 6059 } 6060 case Mips::CMPU_EQ_QB: 6061 case Mips::CMPU_LE_QB: 6062 case Mips::CMPU_LT_QB: 6063 case Mips::CMP_EQ_PH: 6064 case Mips::CMP_LE_PH: 6065 case Mips::CMP_LT_PH: 6066 case Mips::DMULT: 6067 case Mips::DMULTu: 6068 case Mips::DSDIV: 6069 case Mips::DUDIV: 6070 case Mips::MADD: 6071 case Mips::MADDU: 6072 case Mips::MSUB: 6073 case Mips::MSUBU: 6074 case Mips::MULT: 6075 case Mips::MULTu: 6076 case Mips::SDIV: 6077 case Mips::UDIV: { 6078 // op: rs 6079 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6080 op &= UINT64_C(31); 6081 op <<= 21; 6082 Value |= op; 6083 // op: rt 6084 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6085 op &= UINT64_C(31); 6086 op <<= 16; 6087 Value |= op; 6088 break; 6089 } 6090 case Mips::TEQ: 6091 case Mips::TGE: 6092 case Mips::TGEU: 6093 case Mips::TLT: 6094 case Mips::TLTU: 6095 case Mips::TNE: { 6096 // op: rs 6097 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6098 op &= UINT64_C(31); 6099 op <<= 21; 6100 Value |= op; 6101 // op: rt 6102 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6103 op &= UINT64_C(31); 6104 op <<= 16; 6105 Value |= op; 6106 // op: code_ 6107 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6108 op &= UINT64_C(1023); 6109 op <<= 6; 6110 Value |= op; 6111 break; 6112 } 6113 case Mips::BEQ: 6114 case Mips::BEQ64: 6115 case Mips::BEQC: 6116 case Mips::BEQC64: 6117 case Mips::BEQL: 6118 case Mips::BGEC: 6119 case Mips::BGEC64: 6120 case Mips::BGEUC: 6121 case Mips::BGEUC64: 6122 case Mips::BLTC: 6123 case Mips::BLTC64: 6124 case Mips::BLTUC: 6125 case Mips::BLTUC64: 6126 case Mips::BNE: 6127 case Mips::BNE64: 6128 case Mips::BNEC: 6129 case Mips::BNEC64: 6130 case Mips::BNEL: 6131 case Mips::BNVC: 6132 case Mips::BOVC: { 6133 // op: rs 6134 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6135 op &= UINT64_C(31); 6136 op <<= 21; 6137 Value |= op; 6138 // op: rt 6139 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6140 op &= UINT64_C(31); 6141 op <<= 16; 6142 Value |= op; 6143 // op: offset 6144 op = getBranchTargetOpValue(MI, 2, Fixups, STI); 6145 op &= UINT64_C(65535); 6146 Value |= op; 6147 break; 6148 } 6149 case Mips::FORK: { 6150 // op: rs 6151 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6152 op &= UINT64_C(31); 6153 op <<= 21; 6154 Value |= op; 6155 // op: rt 6156 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6157 op &= UINT64_C(31); 6158 op <<= 16; 6159 Value |= op; 6160 // op: rd 6161 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6162 op &= UINT64_C(31); 6163 op <<= 11; 6164 Value |= op; 6165 break; 6166 } 6167 case Mips::GINVT: { 6168 // op: rs 6169 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6170 op &= UINT64_C(31); 6171 op <<= 21; 6172 Value |= op; 6173 // op: type_ 6174 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6175 op &= UINT64_C(3); 6176 op <<= 8; 6177 Value |= op; 6178 break; 6179 } 6180 case Mips::JALRC16_MMR6: 6181 case Mips::JRC16_MMR6: { 6182 // op: rs 6183 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6184 op &= UINT64_C(31); 6185 op <<= 5; 6186 Value |= op; 6187 break; 6188 } 6189 case Mips::ADDIUPC_MM: { 6190 // op: rs 6191 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6192 op &= UINT64_C(7); 6193 op <<= 23; 6194 Value |= op; 6195 // op: imm 6196 op = getSimm23Lsl2Encoding(MI, 1, Fixups, STI); 6197 op &= UINT64_C(8388607); 6198 Value |= op; 6199 break; 6200 } 6201 case Mips::BEQZ16_MM: 6202 case Mips::BEQZC16_MMR6: 6203 case Mips::BNEZ16_MM: 6204 case Mips::BNEZC16_MMR6: { 6205 // op: rs 6206 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6207 op &= UINT64_C(7); 6208 op <<= 7; 6209 Value |= op; 6210 // op: offset 6211 op = getBranchTarget7OpValueMM(MI, 1, Fixups, STI); 6212 op &= UINT64_C(127); 6213 Value |= op; 6214 break; 6215 } 6216 case Mips::MOVE16_MM: 6217 case Mips::MOVE16_MMR6: { 6218 // op: rs 6219 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6220 op &= UINT64_C(31); 6221 Value |= op; 6222 // op: rd 6223 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6224 op &= UINT64_C(31); 6225 op <<= 5; 6226 Value |= op; 6227 break; 6228 } 6229 case Mips::CTCMSA: { 6230 // op: rs 6231 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6232 op &= UINT64_C(31); 6233 op <<= 11; 6234 Value |= op; 6235 // op: cd 6236 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6237 op &= UINT64_C(31); 6238 op <<= 6; 6239 Value |= op; 6240 break; 6241 } 6242 case Mips::FILL_B: 6243 case Mips::FILL_D: 6244 case Mips::FILL_H: 6245 case Mips::FILL_W: { 6246 // op: rs 6247 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6248 op &= UINT64_C(31); 6249 op <<= 11; 6250 Value |= op; 6251 // op: wd 6252 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6253 op &= UINT64_C(31); 6254 op <<= 6; 6255 Value |= op; 6256 break; 6257 } 6258 case Mips::MTHI_DSP_MM: 6259 case Mips::MTHLIP_MM: 6260 case Mips::MTLO_DSP_MM: 6261 case Mips::SHILOV_MM: { 6262 // op: rs 6263 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6264 op &= UINT64_C(31); 6265 op <<= 16; 6266 Value |= op; 6267 // op: ac 6268 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6269 op &= UINT64_C(3); 6270 op <<= 14; 6271 Value |= op; 6272 break; 6273 } 6274 case Mips::JALRS_MM: 6275 case Mips::JALR_MM: { 6276 // op: rs 6277 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6278 op &= UINT64_C(31); 6279 op <<= 16; 6280 Value |= op; 6281 // op: rd 6282 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6283 op &= UINT64_C(31); 6284 op <<= 21; 6285 Value |= op; 6286 break; 6287 } 6288 case Mips::CLO_MMR6: { 6289 // op: rs 6290 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6291 op &= UINT64_C(31); 6292 op <<= 16; 6293 Value |= op; 6294 // op: rt 6295 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6296 op &= UINT64_C(31); 6297 op <<= 21; 6298 Value |= op; 6299 break; 6300 } 6301 case Mips::AUI_MMR6: { 6302 // op: rs 6303 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6304 op &= UINT64_C(31); 6305 op <<= 16; 6306 Value |= op; 6307 // op: rt 6308 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6309 op &= UINT64_C(31); 6310 op <<= 21; 6311 Value |= op; 6312 // op: imm 6313 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6314 op &= UINT64_C(65535); 6315 Value |= op; 6316 break; 6317 } 6318 case Mips::ADDi_MM: 6319 case Mips::ADDiu_MM: 6320 case Mips::ANDi_MM: 6321 case Mips::ORi_MM: 6322 case Mips::XORi_MM: { 6323 // op: rs 6324 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6325 op &= UINT64_C(31); 6326 op <<= 16; 6327 Value |= op; 6328 // op: rt 6329 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6330 op &= UINT64_C(31); 6331 op <<= 21; 6332 Value |= op; 6333 // op: imm16 6334 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6335 op &= UINT64_C(65535); 6336 Value |= op; 6337 break; 6338 } 6339 case Mips::MTHI_DSP: 6340 case Mips::MTLO_DSP: { 6341 // op: rs 6342 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6343 op &= UINT64_C(31); 6344 op <<= 21; 6345 Value |= op; 6346 // op: ac 6347 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6348 op &= UINT64_C(3); 6349 op <<= 11; 6350 Value |= op; 6351 break; 6352 } 6353 case Mips::YIELD: { 6354 // op: rs 6355 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6356 op &= UINT64_C(31); 6357 op <<= 21; 6358 Value |= op; 6359 // op: rd 6360 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6361 op &= UINT64_C(31); 6362 op <<= 11; 6363 Value |= op; 6364 break; 6365 } 6366 case Mips::CLZ_MMR6: { 6367 // op: rs 6368 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6369 op &= UINT64_C(31); 6370 op <<= 21; 6371 Value |= op; 6372 // op: rt 6373 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6374 op &= UINT64_C(31); 6375 op <<= 11; 6376 Value |= op; 6377 break; 6378 } 6379 case Mips::AUI: 6380 case Mips::DAUI: { 6381 // op: rs 6382 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6383 op &= UINT64_C(31); 6384 op <<= 21; 6385 Value |= op; 6386 // op: rt 6387 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6388 op &= UINT64_C(31); 6389 op <<= 16; 6390 Value |= op; 6391 // op: imm 6392 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6393 op &= UINT64_C(65535); 6394 Value |= op; 6395 break; 6396 } 6397 case Mips::SEQi: 6398 case Mips::SNEi: { 6399 // op: rs 6400 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6401 op &= UINT64_C(31); 6402 op <<= 21; 6403 Value |= op; 6404 // op: rt 6405 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6406 op &= UINT64_C(31); 6407 op <<= 16; 6408 Value |= op; 6409 // op: imm10 6410 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6411 op &= UINT64_C(1023); 6412 op <<= 6; 6413 Value |= op; 6414 break; 6415 } 6416 case Mips::ADDi: 6417 case Mips::ADDiu: 6418 case Mips::ANDi: 6419 case Mips::ANDi64: 6420 case Mips::DADDi: 6421 case Mips::DADDiu: 6422 case Mips::ORi: 6423 case Mips::ORi64: 6424 case Mips::XORi: 6425 case Mips::XORi64: { 6426 // op: rs 6427 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6428 op &= UINT64_C(31); 6429 op <<= 21; 6430 Value |= op; 6431 // op: rt 6432 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6433 op &= UINT64_C(31); 6434 op <<= 16; 6435 Value |= op; 6436 // op: imm16 6437 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6438 op &= UINT64_C(65535); 6439 Value |= op; 6440 break; 6441 } 6442 case Mips::PRECR_SRA_PH_W: 6443 case Mips::PRECR_SRA_R_PH_W: { 6444 // op: rs 6445 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6446 op &= UINT64_C(31); 6447 op <<= 21; 6448 Value |= op; 6449 // op: rt 6450 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6451 op &= UINT64_C(31); 6452 op <<= 16; 6453 Value |= op; 6454 // op: sa 6455 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6456 op &= UINT64_C(31); 6457 op <<= 11; 6458 Value |= op; 6459 break; 6460 } 6461 case Mips::CRC32B: 6462 case Mips::CRC32CB: 6463 case Mips::CRC32CD: 6464 case Mips::CRC32CH: 6465 case Mips::CRC32CW: 6466 case Mips::CRC32D: 6467 case Mips::CRC32H: 6468 case Mips::CRC32W: { 6469 // op: rs 6470 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6471 op &= UINT64_C(31); 6472 op <<= 21; 6473 Value |= op; 6474 // op: rt 6475 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6476 op &= UINT64_C(31); 6477 op <<= 16; 6478 Value |= op; 6479 break; 6480 } 6481 case Mips::CMPGDU_EQ_QB: 6482 case Mips::CMPGDU_LE_QB: 6483 case Mips::CMPGDU_LT_QB: 6484 case Mips::CMPGU_EQ_QB: 6485 case Mips::CMPGU_LE_QB: 6486 case Mips::CMPGU_LT_QB: 6487 case Mips::PACKRL_PH: 6488 case Mips::PICK_PH: 6489 case Mips::PICK_QB: 6490 case Mips::PRECRQU_S_QB_PH: 6491 case Mips::PRECRQ_PH_W: 6492 case Mips::PRECRQ_QB_PH: 6493 case Mips::PRECRQ_RS_PH_W: 6494 case Mips::PRECR_QB_PH: { 6495 // op: rs 6496 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6497 op &= UINT64_C(31); 6498 op <<= 21; 6499 Value |= op; 6500 // op: rt 6501 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6502 op &= UINT64_C(31); 6503 op <<= 16; 6504 Value |= op; 6505 // op: rd 6506 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6507 op &= UINT64_C(31); 6508 op <<= 11; 6509 Value |= op; 6510 break; 6511 } 6512 case Mips::DLSA: 6513 case Mips::LSA: { 6514 // op: rs 6515 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6516 op &= UINT64_C(31); 6517 op <<= 21; 6518 Value |= op; 6519 // op: rt 6520 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6521 op &= UINT64_C(31); 6522 op <<= 16; 6523 Value |= op; 6524 // op: rd 6525 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6526 op &= UINT64_C(31); 6527 op <<= 11; 6528 Value |= op; 6529 // op: sa 6530 op = getUImmWithOffsetEncoding<2, 1>(MI, 3, Fixups, STI); 6531 op &= UINT64_C(3); 6532 op <<= 6; 6533 Value |= op; 6534 break; 6535 } 6536 case Mips::ADDU16_MMR6: 6537 case Mips::SUBU16_MMR6: { 6538 // op: rs 6539 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6540 op &= UINT64_C(7); 6541 op <<= 7; 6542 Value |= op; 6543 // op: rt 6544 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6545 op &= UINT64_C(7); 6546 op <<= 4; 6547 Value |= op; 6548 // op: rd 6549 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6550 op &= UINT64_C(7); 6551 op <<= 1; 6552 Value |= op; 6553 break; 6554 } 6555 case Mips::BGEZALC: 6556 case Mips::BGEZC: 6557 case Mips::BGEZC64: 6558 case Mips::BLTZALC: 6559 case Mips::BLTZC: 6560 case Mips::BLTZC64: { 6561 // op: rt 6562 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6563 Value |= (op & UINT64_C(31)) << 21; 6564 Value |= (op & UINT64_C(31)) << 16; 6565 // op: offset 6566 op = getBranchTargetOpValue(MI, 1, Fixups, STI); 6567 op &= UINT64_C(65535); 6568 Value |= op; 6569 break; 6570 } 6571 case Mips::BGEZC_MMR6: 6572 case Mips::BLTZC_MMR6: { 6573 // op: rt 6574 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6575 Value |= (op & UINT64_C(31)) << 21; 6576 Value |= (op & UINT64_C(31)) << 16; 6577 // op: offset 6578 op = getBranchTargetOpValueLsl2MMR6(MI, 1, Fixups, STI); 6579 op &= UINT64_C(65535); 6580 Value |= op; 6581 break; 6582 } 6583 case Mips::BGEZALC_MMR6: 6584 case Mips::BLTZALC_MMR6: { 6585 // op: rt 6586 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6587 Value |= (op & UINT64_C(31)) << 21; 6588 Value |= (op & UINT64_C(31)) << 16; 6589 // op: offset 6590 op = getBranchTargetOpValueMM(MI, 1, Fixups, STI); 6591 op &= UINT64_C(65535); 6592 Value |= op; 6593 break; 6594 } 6595 case Mips::DI: 6596 case Mips::DI_MM: 6597 case Mips::DI_MMR6: 6598 case Mips::DMT: 6599 case Mips::DVP: 6600 case Mips::DVPE: 6601 case Mips::EI: 6602 case Mips::EI_MM: 6603 case Mips::EI_MMR6: 6604 case Mips::EMT: 6605 case Mips::EVP: 6606 case Mips::EVPE: { 6607 // op: rt 6608 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6609 op &= UINT64_C(31); 6610 op <<= 16; 6611 Value |= op; 6612 break; 6613 } 6614 case Mips::EXTP: 6615 case Mips::EXTPDP: 6616 case Mips::EXTPDPV: 6617 case Mips::EXTPV: 6618 case Mips::EXTRV_RS_W: 6619 case Mips::EXTRV_R_W: 6620 case Mips::EXTRV_S_H: 6621 case Mips::EXTRV_W: 6622 case Mips::EXTR_RS_W: 6623 case Mips::EXTR_R_W: 6624 case Mips::EXTR_S_H: 6625 case Mips::EXTR_W: { 6626 // op: rt 6627 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6628 op &= UINT64_C(31); 6629 op <<= 16; 6630 Value |= op; 6631 // op: ac 6632 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6633 op &= UINT64_C(3); 6634 op <<= 11; 6635 Value |= op; 6636 // op: shift_rs 6637 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6638 op &= UINT64_C(31); 6639 op <<= 21; 6640 Value |= op; 6641 break; 6642 } 6643 case Mips::LL64_R6: 6644 case Mips::LLD_R6: 6645 case Mips::LL_R6: { 6646 // op: rt 6647 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6648 op &= UINT64_C(31); 6649 op <<= 16; 6650 Value |= op; 6651 // op: addr 6652 op = getMemEncoding(MI, 1, Fixups, STI); 6653 Value |= (op & UINT64_C(2031616)) << 5; 6654 Value |= (op & UINT64_C(511)) << 7; 6655 break; 6656 } 6657 case Mips::LB: 6658 case Mips::LB64: 6659 case Mips::LBu: 6660 case Mips::LBu64: 6661 case Mips::LD: 6662 case Mips::LDC1: 6663 case Mips::LDC164: 6664 case Mips::LDC2: 6665 case Mips::LDC3: 6666 case Mips::LDL: 6667 case Mips::LDR: 6668 case Mips::LEA_ADDiu: 6669 case Mips::LEA_ADDiu64: 6670 case Mips::LH: 6671 case Mips::LH64: 6672 case Mips::LHu: 6673 case Mips::LHu64: 6674 case Mips::LL: 6675 case Mips::LL64: 6676 case Mips::LLD: 6677 case Mips::LW: 6678 case Mips::LW64: 6679 case Mips::LWC1: 6680 case Mips::LWC2: 6681 case Mips::LWC3: 6682 case Mips::LWDSP: 6683 case Mips::LWL: 6684 case Mips::LWL64: 6685 case Mips::LWR: 6686 case Mips::LWR64: 6687 case Mips::LWu: 6688 case Mips::SB: 6689 case Mips::SB64: 6690 case Mips::SD: 6691 case Mips::SDC1: 6692 case Mips::SDC164: 6693 case Mips::SDC2: 6694 case Mips::SDC3: 6695 case Mips::SDL: 6696 case Mips::SDR: 6697 case Mips::SH: 6698 case Mips::SH64: 6699 case Mips::SW: 6700 case Mips::SW64: 6701 case Mips::SWC1: 6702 case Mips::SWC2: 6703 case Mips::SWC3: 6704 case Mips::SWDSP: 6705 case Mips::SWL: 6706 case Mips::SWL64: 6707 case Mips::SWR: 6708 case Mips::SWR64: { 6709 // op: rt 6710 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6711 op &= UINT64_C(31); 6712 op <<= 16; 6713 Value |= op; 6714 // op: addr 6715 op = getMemEncoding(MI, 1, Fixups, STI); 6716 Value |= (op & UINT64_C(2031616)) << 5; 6717 Value |= (op & UINT64_C(65535)); 6718 break; 6719 } 6720 case Mips::LDC2_R6: 6721 case Mips::LWC2_R6: 6722 case Mips::SDC2_R6: 6723 case Mips::SWC2_R6: { 6724 // op: rt 6725 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6726 op &= UINT64_C(31); 6727 op <<= 16; 6728 Value |= op; 6729 // op: addr 6730 op = getMemEncoding(MI, 1, Fixups, STI); 6731 Value |= (op & UINT64_C(2031616)) >> 5; 6732 Value |= (op & UINT64_C(2047)); 6733 break; 6734 } 6735 case Mips::CFC1: 6736 case Mips::DMFC1: 6737 case Mips::MFC1: 6738 case Mips::MFC1_D64: 6739 case Mips::MFHC1_D32: 6740 case Mips::MFHC1_D64: { 6741 // op: rt 6742 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6743 op &= UINT64_C(31); 6744 op <<= 16; 6745 Value |= op; 6746 // op: fs 6747 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6748 op &= UINT64_C(31); 6749 op <<= 11; 6750 Value |= op; 6751 break; 6752 } 6753 case Mips::DMFC2_OCTEON: 6754 case Mips::DMTC2_OCTEON: 6755 case Mips::LUi: 6756 case Mips::LUi64: 6757 case Mips::LUi_MM: { 6758 // op: rt 6759 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6760 op &= UINT64_C(31); 6761 op <<= 16; 6762 Value |= op; 6763 // op: imm16 6764 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6765 op &= UINT64_C(65535); 6766 Value |= op; 6767 break; 6768 } 6769 case Mips::BEQZALC: 6770 case Mips::BGTZALC: 6771 case Mips::BGTZC: 6772 case Mips::BGTZC64: 6773 case Mips::BLEZALC: 6774 case Mips::BLEZC: 6775 case Mips::BLEZC64: 6776 case Mips::BNEZALC: { 6777 // op: rt 6778 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6779 op &= UINT64_C(31); 6780 op <<= 16; 6781 Value |= op; 6782 // op: offset 6783 op = getBranchTargetOpValue(MI, 1, Fixups, STI); 6784 op &= UINT64_C(65535); 6785 Value |= op; 6786 break; 6787 } 6788 case Mips::BC1EQZC_MMR6: 6789 case Mips::BC1NEZC_MMR6: 6790 case Mips::BC2EQZC_MMR6: 6791 case Mips::BC2NEZC_MMR6: { 6792 // op: rt 6793 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6794 op &= UINT64_C(31); 6795 op <<= 16; 6796 Value |= op; 6797 // op: offset 6798 op = getBranchTargetOpValueMM(MI, 1, Fixups, STI); 6799 op &= UINT64_C(65535); 6800 Value |= op; 6801 break; 6802 } 6803 case Mips::JIALC: 6804 case Mips::JIALC64: 6805 case Mips::JIALC_MMR6: 6806 case Mips::JIC: 6807 case Mips::JIC64: 6808 case Mips::JIC_MMR6: { 6809 // op: rt 6810 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6811 op &= UINT64_C(31); 6812 op <<= 16; 6813 Value |= op; 6814 // op: offset 6815 op = getJumpOffset16OpValue(MI, 1, Fixups, STI); 6816 op &= UINT64_C(65535); 6817 Value |= op; 6818 break; 6819 } 6820 case Mips::DMFC0: 6821 case Mips::DMFC2: 6822 case Mips::DMFGC0: 6823 case Mips::MFC0: 6824 case Mips::MFC2: 6825 case Mips::MFGC0: 6826 case Mips::MFHGC0: { 6827 // op: rt 6828 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6829 op &= UINT64_C(31); 6830 op <<= 16; 6831 Value |= op; 6832 // op: rd 6833 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6834 op &= UINT64_C(31); 6835 op <<= 11; 6836 Value |= op; 6837 // op: sel 6838 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6839 op &= UINT64_C(7); 6840 Value |= op; 6841 break; 6842 } 6843 case Mips::RDHWR: 6844 case Mips::RDHWR64: { 6845 // op: rt 6846 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6847 op &= UINT64_C(31); 6848 op <<= 16; 6849 Value |= op; 6850 // op: rd 6851 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6852 op &= UINT64_C(31); 6853 op <<= 11; 6854 Value |= op; 6855 // op: sel 6856 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6857 op &= UINT64_C(7); 6858 op <<= 6; 6859 Value |= op; 6860 break; 6861 } 6862 case Mips::SAA: 6863 case Mips::SAAD: { 6864 // op: rt 6865 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6866 op &= UINT64_C(31); 6867 op <<= 16; 6868 Value |= op; 6869 // op: rs 6870 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6871 op &= UINT64_C(31); 6872 op <<= 21; 6873 Value |= op; 6874 break; 6875 } 6876 case Mips::SLTi: 6877 case Mips::SLTi64: 6878 case Mips::SLTiu: 6879 case Mips::SLTiu64: { 6880 // op: rt 6881 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6882 op &= UINT64_C(31); 6883 op <<= 16; 6884 Value |= op; 6885 // op: rs 6886 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6887 op &= UINT64_C(31); 6888 op <<= 21; 6889 Value |= op; 6890 // op: imm16 6891 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6892 op &= UINT64_C(65535); 6893 Value |= op; 6894 break; 6895 } 6896 case Mips::CINS: 6897 case Mips::CINS32: 6898 case Mips::CINS64_32: 6899 case Mips::CINS_i32: 6900 case Mips::EXTS: 6901 case Mips::EXTS32: { 6902 // op: rt 6903 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6904 op &= UINT64_C(31); 6905 op <<= 16; 6906 Value |= op; 6907 // op: rs 6908 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6909 op &= UINT64_C(31); 6910 op <<= 21; 6911 Value |= op; 6912 // op: pos 6913 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6914 op &= UINT64_C(31); 6915 op <<= 6; 6916 Value |= op; 6917 // op: lenm1 6918 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6919 op &= UINT64_C(31); 6920 op <<= 11; 6921 Value |= op; 6922 break; 6923 } 6924 case Mips::DINS: 6925 case Mips::DINSM: 6926 case Mips::DINSU: 6927 case Mips::INS: { 6928 // op: rt 6929 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6930 op &= UINT64_C(31); 6931 op <<= 16; 6932 Value |= op; 6933 // op: rs 6934 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6935 op &= UINT64_C(31); 6936 op <<= 21; 6937 Value |= op; 6938 // op: pos 6939 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6940 op &= UINT64_C(31); 6941 op <<= 6; 6942 Value |= op; 6943 // op: size 6944 op = getSizeInsEncoding(MI, 3, Fixups, STI); 6945 op &= UINT64_C(31); 6946 op <<= 11; 6947 Value |= op; 6948 break; 6949 } 6950 case Mips::DEXT: 6951 case Mips::DEXT64_32: 6952 case Mips::DEXTM: 6953 case Mips::DEXTU: 6954 case Mips::EXT: { 6955 // op: rt 6956 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6957 op &= UINT64_C(31); 6958 op <<= 16; 6959 Value |= op; 6960 // op: rs 6961 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6962 op &= UINT64_C(31); 6963 op <<= 21; 6964 Value |= op; 6965 // op: pos 6966 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6967 op &= UINT64_C(31); 6968 op <<= 6; 6969 Value |= op; 6970 // op: size 6971 op = getUImmWithOffsetEncoding<5, 1>(MI, 3, Fixups, STI); 6972 op &= UINT64_C(31); 6973 op <<= 11; 6974 Value |= op; 6975 break; 6976 } 6977 case Mips::APPEND: 6978 case Mips::BALIGN: 6979 case Mips::PREPEND: { 6980 // op: rt 6981 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6982 op &= UINT64_C(31); 6983 op <<= 16; 6984 Value |= op; 6985 // op: rs 6986 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6987 op &= UINT64_C(31); 6988 op <<= 21; 6989 Value |= op; 6990 // op: sa 6991 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6992 op &= UINT64_C(31); 6993 op <<= 11; 6994 Value |= op; 6995 break; 6996 } 6997 case Mips::INSV: { 6998 // op: rt 6999 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7000 op &= UINT64_C(31); 7001 op <<= 16; 7002 Value |= op; 7003 // op: rs 7004 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7005 op &= UINT64_C(31); 7006 op <<= 21; 7007 Value |= op; 7008 break; 7009 } 7010 case Mips::LWU_MM: { 7011 // op: rt 7012 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7013 op &= UINT64_C(31); 7014 op <<= 21; 7015 Value |= op; 7016 // op: addr 7017 op = getMemEncoding(MI, 1, Fixups, STI); 7018 Value |= (op & UINT64_C(2031616)); 7019 Value |= (op & UINT64_C(4095)); 7020 break; 7021 } 7022 case Mips::LBE_MM: 7023 case Mips::LBuE_MM: 7024 case Mips::LHE_MM: 7025 case Mips::LHuE_MM: 7026 case Mips::LLE_MM: 7027 case Mips::LWE_MM: 7028 case Mips::SBE_MM: 7029 case Mips::SHE_MM: 7030 case Mips::SWE_MM: { 7031 // op: rt 7032 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7033 op &= UINT64_C(31); 7034 op <<= 21; 7035 Value |= op; 7036 // op: addr 7037 op = getMemEncoding(MI, 1, Fixups, STI); 7038 Value |= (op & UINT64_C(2031616)); 7039 Value |= (op & UINT64_C(511)); 7040 break; 7041 } 7042 case Mips::LEA_ADDiu_MM: 7043 case Mips::LH_MM: 7044 case Mips::LHu_MM: 7045 case Mips::LWDSP_MM: 7046 case Mips::LW_MM: 7047 case Mips::LW_MMR6: 7048 case Mips::SB_MM: 7049 case Mips::SB_MMR6: 7050 case Mips::SH_MM: 7051 case Mips::SH_MMR6: 7052 case Mips::SWDSP_MM: 7053 case Mips::SW_MM: 7054 case Mips::SW_MMR6: { 7055 // op: rt 7056 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7057 op &= UINT64_C(31); 7058 op <<= 21; 7059 Value |= op; 7060 // op: addr 7061 op = getMemEncoding(MI, 1, Fixups, STI); 7062 op &= UINT64_C(2097151); 7063 Value |= op; 7064 break; 7065 } 7066 case Mips::LWP_MM: 7067 case Mips::SWP_MM: { 7068 // op: rt 7069 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7070 op &= UINT64_C(31); 7071 op <<= 21; 7072 Value |= op; 7073 // op: addr 7074 op = getMemEncoding(MI, 2, Fixups, STI); 7075 Value |= (op & UINT64_C(2031616)); 7076 Value |= (op & UINT64_C(4095)); 7077 break; 7078 } 7079 case Mips::LDC2_MMR6: 7080 case Mips::LWC2_MMR6: 7081 case Mips::SDC2_MMR6: 7082 case Mips::SWC2_MMR6: { 7083 // op: rt 7084 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7085 op &= UINT64_C(31); 7086 op <<= 21; 7087 Value |= op; 7088 // op: addr 7089 op = getMemEncodingMMImm11(MI, 1, Fixups, STI); 7090 Value |= (op & UINT64_C(2031616)); 7091 Value |= (op & UINT64_C(2047)); 7092 break; 7093 } 7094 case Mips::LL_MM: 7095 case Mips::LWL_MM: 7096 case Mips::LWR_MM: 7097 case Mips::SWL_MM: 7098 case Mips::SWR_MM: { 7099 // op: rt 7100 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7101 op &= UINT64_C(31); 7102 op <<= 21; 7103 Value |= op; 7104 // op: addr 7105 op = getMemEncodingMMImm12(MI, 1, Fixups, STI); 7106 Value |= (op & UINT64_C(2031616)); 7107 Value |= (op & UINT64_C(4095)); 7108 break; 7109 } 7110 case Mips::LB_MM: 7111 case Mips::LBu_MM: 7112 case Mips::LDC1_MM_D32: 7113 case Mips::LDC1_MM_D64: 7114 case Mips::LWC1_MM: 7115 case Mips::SDC1_MM_D32: 7116 case Mips::SDC1_MM_D64: 7117 case Mips::SWC1_MM: { 7118 // op: rt 7119 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7120 op &= UINT64_C(31); 7121 op <<= 21; 7122 Value |= op; 7123 // op: addr 7124 op = getMemEncodingMMImm16(MI, 1, Fixups, STI); 7125 op &= UINT64_C(2097151); 7126 Value |= op; 7127 break; 7128 } 7129 case Mips::LL_MMR6: 7130 case Mips::LWLE_MM: 7131 case Mips::LWRE_MM: 7132 case Mips::SWLE_MM: 7133 case Mips::SWRE_MM: { 7134 // op: rt 7135 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7136 op &= UINT64_C(31); 7137 op <<= 21; 7138 Value |= op; 7139 // op: addr 7140 op = getMemEncodingMMImm9(MI, 1, Fixups, STI); 7141 Value |= (op & UINT64_C(2031616)); 7142 Value |= (op & UINT64_C(511)); 7143 break; 7144 } 7145 case Mips::CFC1_MM: 7146 case Mips::MFC1_MM: 7147 case Mips::MFC1_MMR6: 7148 case Mips::MFHC1_D32_MM: 7149 case Mips::MFHC1_D64_MM: { 7150 // op: rt 7151 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7152 op &= UINT64_C(31); 7153 op <<= 21; 7154 Value |= op; 7155 // op: fs 7156 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7157 op &= UINT64_C(31); 7158 op <<= 16; 7159 Value |= op; 7160 break; 7161 } 7162 case Mips::REPL_QB_MM: { 7163 // op: rt 7164 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7165 op &= UINT64_C(31); 7166 op <<= 21; 7167 Value |= op; 7168 // op: imm 7169 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7170 op &= UINT64_C(255); 7171 op <<= 13; 7172 Value |= op; 7173 break; 7174 } 7175 case Mips::ALUIPC_MMR6: 7176 case Mips::AUIPC_MMR6: { 7177 // op: rt 7178 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7179 op &= UINT64_C(31); 7180 op <<= 21; 7181 Value |= op; 7182 // op: imm 7183 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7184 op &= UINT64_C(65535); 7185 Value |= op; 7186 break; 7187 } 7188 case Mips::EXTPDP_MM: 7189 case Mips::EXTP_MM: 7190 case Mips::EXTR_RS_W_MM: 7191 case Mips::EXTR_R_W_MM: 7192 case Mips::EXTR_S_H_MM: 7193 case Mips::EXTR_W_MM: { 7194 // op: rt 7195 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7196 op &= UINT64_C(31); 7197 op <<= 21; 7198 Value |= op; 7199 // op: imm 7200 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7201 op &= UINT64_C(31); 7202 op <<= 16; 7203 Value |= op; 7204 // op: ac 7205 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7206 op &= UINT64_C(3); 7207 op <<= 14; 7208 Value |= op; 7209 break; 7210 } 7211 case Mips::ADDIUPC_MMR6: 7212 case Mips::LWPC_MMR6: { 7213 // op: rt 7214 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7215 op &= UINT64_C(31); 7216 op <<= 21; 7217 Value |= op; 7218 // op: imm 7219 op = getSimm19Lsl2Encoding(MI, 1, Fixups, STI); 7220 op &= UINT64_C(524287); 7221 Value |= op; 7222 break; 7223 } 7224 case Mips::LUI_MMR6: { 7225 // op: rt 7226 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7227 op &= UINT64_C(31); 7228 op <<= 21; 7229 Value |= op; 7230 // op: imm16 7231 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7232 op &= UINT64_C(65535); 7233 Value |= op; 7234 break; 7235 } 7236 case Mips::CFC2_MM: 7237 case Mips::MFC2_MMR6: 7238 case Mips::MFHC2_MMR6: { 7239 // op: rt 7240 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7241 op &= UINT64_C(31); 7242 op <<= 21; 7243 Value |= op; 7244 // op: impl 7245 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7246 op &= UINT64_C(31); 7247 op <<= 16; 7248 Value |= op; 7249 break; 7250 } 7251 case Mips::RDDSP_MM: 7252 case Mips::WRDSP_MM: { 7253 // op: rt 7254 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7255 op &= UINT64_C(31); 7256 op <<= 21; 7257 Value |= op; 7258 // op: mask 7259 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7260 op &= UINT64_C(127); 7261 op <<= 14; 7262 Value |= op; 7263 break; 7264 } 7265 case Mips::BGTZC_MMR6: 7266 case Mips::BLEZC_MMR6: { 7267 // op: rt 7268 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7269 op &= UINT64_C(31); 7270 op <<= 21; 7271 Value |= op; 7272 // op: offset 7273 op = getBranchTargetOpValueLsl2MMR6(MI, 1, Fixups, STI); 7274 op &= UINT64_C(65535); 7275 Value |= op; 7276 break; 7277 } 7278 case Mips::BEQZALC_MMR6: 7279 case Mips::BGTZALC_MMR6: 7280 case Mips::BLEZALC_MMR6: 7281 case Mips::BNEZALC_MMR6: { 7282 // op: rt 7283 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7284 op &= UINT64_C(31); 7285 op <<= 21; 7286 Value |= op; 7287 // op: offset 7288 op = getBranchTargetOpValueMM(MI, 1, Fixups, STI); 7289 op &= UINT64_C(65535); 7290 Value |= op; 7291 break; 7292 } 7293 case Mips::RDHWR_MM: 7294 case Mips::RDPGPR_MMR6: { 7295 // op: rt 7296 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7297 op &= UINT64_C(31); 7298 op <<= 21; 7299 Value |= op; 7300 // op: rd 7301 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7302 op &= UINT64_C(31); 7303 op <<= 16; 7304 Value |= op; 7305 break; 7306 } 7307 case Mips::ABSQ_S_PH_MM: 7308 case Mips::ABSQ_S_QB_MMR2: 7309 case Mips::ABSQ_S_W_MM: 7310 case Mips::BITREV_MM: 7311 case Mips::JALRC_HB_MMR6: 7312 case Mips::JALRC_MMR6: 7313 case Mips::PRECEQU_PH_QBLA_MM: 7314 case Mips::PRECEQU_PH_QBL_MM: 7315 case Mips::PRECEQU_PH_QBRA_MM: 7316 case Mips::PRECEQU_PH_QBR_MM: 7317 case Mips::PRECEQ_W_PHL_MM: 7318 case Mips::PRECEQ_W_PHR_MM: 7319 case Mips::PRECEU_PH_QBLA_MM: 7320 case Mips::PRECEU_PH_QBL_MM: 7321 case Mips::PRECEU_PH_QBRA_MM: 7322 case Mips::PRECEU_PH_QBR_MM: 7323 case Mips::RADDU_W_QB_MM: 7324 case Mips::REPLV_PH_MM: 7325 case Mips::REPLV_QB_MM: 7326 case Mips::WRPGPR_MMR6: 7327 case Mips::WSBH_MMR6: { 7328 // op: rt 7329 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7330 op &= UINT64_C(31); 7331 op <<= 21; 7332 Value |= op; 7333 // op: rs 7334 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7335 op &= UINT64_C(31); 7336 op <<= 16; 7337 Value |= op; 7338 break; 7339 } 7340 case Mips::BALIGN_MMR2: { 7341 // op: rt 7342 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7343 op &= UINT64_C(31); 7344 op <<= 21; 7345 Value |= op; 7346 // op: rs 7347 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7348 op &= UINT64_C(31); 7349 op <<= 16; 7350 Value |= op; 7351 // op: bp 7352 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7353 op &= UINT64_C(3); 7354 op <<= 14; 7355 Value |= op; 7356 break; 7357 } 7358 case Mips::ADDIU_MMR6: 7359 case Mips::ANDI_MMR6: 7360 case Mips::ORI_MMR6: 7361 case Mips::SLTi_MM: 7362 case Mips::SLTiu_MM: 7363 case Mips::XORI_MMR6: { 7364 // op: rt 7365 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7366 op &= UINT64_C(31); 7367 op <<= 21; 7368 Value |= op; 7369 // op: rs 7370 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7371 op &= UINT64_C(31); 7372 op <<= 16; 7373 Value |= op; 7374 // op: imm16 7375 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7376 op &= UINT64_C(65535); 7377 Value |= op; 7378 break; 7379 } 7380 case Mips::BNVC_MMR6: 7381 case Mips::BOVC_MMR6: { 7382 // op: rt 7383 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7384 op &= UINT64_C(31); 7385 op <<= 21; 7386 Value |= op; 7387 // op: rs 7388 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7389 op &= UINT64_C(31); 7390 op <<= 16; 7391 Value |= op; 7392 // op: offset 7393 op = getBranchTargetOpValueMMR6(MI, 2, Fixups, STI); 7394 op &= UINT64_C(65535); 7395 Value |= op; 7396 break; 7397 } 7398 case Mips::INS_MM: { 7399 // op: rt 7400 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7401 op &= UINT64_C(31); 7402 op <<= 21; 7403 Value |= op; 7404 // op: rs 7405 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7406 op &= UINT64_C(31); 7407 op <<= 16; 7408 Value |= op; 7409 // op: pos 7410 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7411 op &= UINT64_C(31); 7412 op <<= 6; 7413 Value |= op; 7414 // op: size 7415 op = getSizeInsEncoding(MI, 3, Fixups, STI); 7416 op &= UINT64_C(31); 7417 op <<= 11; 7418 Value |= op; 7419 break; 7420 } 7421 case Mips::EXT_MM: { 7422 // op: rt 7423 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7424 op &= UINT64_C(31); 7425 op <<= 21; 7426 Value |= op; 7427 // op: rs 7428 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7429 op &= UINT64_C(31); 7430 op <<= 16; 7431 Value |= op; 7432 // op: pos 7433 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7434 op &= UINT64_C(31); 7435 op <<= 6; 7436 Value |= op; 7437 // op: size 7438 op = getUImmWithOffsetEncoding<5, 1>(MI, 3, Fixups, STI); 7439 op &= UINT64_C(31); 7440 op <<= 11; 7441 Value |= op; 7442 break; 7443 } 7444 case Mips::SHLL_PH_MM: 7445 case Mips::SHLL_S_PH_MM: 7446 case Mips::SHRA_PH_MM: 7447 case Mips::SHRA_R_PH_MM: 7448 case Mips::SHRL_PH_MMR2: { 7449 // op: rt 7450 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7451 op &= UINT64_C(31); 7452 op <<= 21; 7453 Value |= op; 7454 // op: rs 7455 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7456 op &= UINT64_C(31); 7457 op <<= 16; 7458 Value |= op; 7459 // op: sa 7460 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7461 op &= UINT64_C(15); 7462 op <<= 12; 7463 Value |= op; 7464 break; 7465 } 7466 case Mips::APPEND_MMR2: 7467 case Mips::PRECR_SRA_PH_W_MMR2: 7468 case Mips::PRECR_SRA_R_PH_W_MMR2: 7469 case Mips::PREPEND_MMR2: 7470 case Mips::SHLL_S_W_MM: 7471 case Mips::SHRA_R_W_MM: { 7472 // op: rt 7473 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7474 op &= UINT64_C(31); 7475 op <<= 21; 7476 Value |= op; 7477 // op: rs 7478 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7479 op &= UINT64_C(31); 7480 op <<= 16; 7481 Value |= op; 7482 // op: sa 7483 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7484 op &= UINT64_C(31); 7485 op <<= 11; 7486 Value |= op; 7487 break; 7488 } 7489 case Mips::SHLL_QB_MM: 7490 case Mips::SHRA_QB_MMR2: 7491 case Mips::SHRA_R_QB_MMR2: 7492 case Mips::SHRL_QB_MM: { 7493 // op: rt 7494 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7495 op &= UINT64_C(31); 7496 op <<= 21; 7497 Value |= op; 7498 // op: rs 7499 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7500 op &= UINT64_C(31); 7501 op <<= 16; 7502 Value |= op; 7503 // op: sa 7504 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7505 op &= UINT64_C(7); 7506 op <<= 13; 7507 Value |= op; 7508 break; 7509 } 7510 case Mips::MFC0_MMR6: 7511 case Mips::MFGC0_MM: 7512 case Mips::MFHC0_MMR6: 7513 case Mips::MFHGC0_MM: 7514 case Mips::RDHWR_MMR6: { 7515 // op: rt 7516 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7517 op &= UINT64_C(31); 7518 op <<= 21; 7519 Value |= op; 7520 // op: rs 7521 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7522 op &= UINT64_C(31); 7523 op <<= 16; 7524 Value |= op; 7525 // op: sel 7526 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7527 op &= UINT64_C(7); 7528 op <<= 11; 7529 Value |= op; 7530 break; 7531 } 7532 case Mips::INS_MMR6: { 7533 // op: rt 7534 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7535 op &= UINT64_C(31); 7536 op <<= 21; 7537 Value |= op; 7538 // op: rs 7539 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7540 op &= UINT64_C(31); 7541 op <<= 16; 7542 Value |= op; 7543 // op: size 7544 op = getSizeInsEncoding(MI, 3, Fixups, STI); 7545 op &= UINT64_C(31); 7546 op <<= 11; 7547 Value |= op; 7548 // op: pos 7549 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7550 op &= UINT64_C(31); 7551 op <<= 6; 7552 Value |= op; 7553 break; 7554 } 7555 case Mips::EXT_MMR6: { 7556 // op: rt 7557 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7558 op &= UINT64_C(31); 7559 op <<= 21; 7560 Value |= op; 7561 // op: rs 7562 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7563 op &= UINT64_C(31); 7564 op <<= 16; 7565 Value |= op; 7566 // op: size 7567 op = getUImmWithOffsetEncoding<5, 1>(MI, 3, Fixups, STI); 7568 op &= UINT64_C(31); 7569 op <<= 11; 7570 Value |= op; 7571 // op: pos 7572 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7573 op &= UINT64_C(31); 7574 op <<= 6; 7575 Value |= op; 7576 break; 7577 } 7578 case Mips::INSV_MM: { 7579 // op: rt 7580 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7581 op &= UINT64_C(31); 7582 op <<= 21; 7583 Value |= op; 7584 // op: rs 7585 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7586 op &= UINT64_C(31); 7587 op <<= 16; 7588 Value |= op; 7589 break; 7590 } 7591 case Mips::EXTPDPV_MM: 7592 case Mips::EXTPV_MM: 7593 case Mips::EXTRV_RS_W_MM: 7594 case Mips::EXTRV_R_W_MM: 7595 case Mips::EXTRV_S_H_MM: 7596 case Mips::EXTRV_W_MM: { 7597 // op: rt 7598 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7599 op &= UINT64_C(31); 7600 op <<= 21; 7601 Value |= op; 7602 // op: rs 7603 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7604 op &= UINT64_C(31); 7605 op <<= 16; 7606 Value |= op; 7607 // op: ac 7608 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7609 op &= UINT64_C(3); 7610 op <<= 14; 7611 Value |= op; 7612 break; 7613 } 7614 case Mips::LWSP_MM: 7615 case Mips::SWSP_MM: 7616 case Mips::SWSP_MMR6: { 7617 // op: rt 7618 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7619 op &= UINT64_C(31); 7620 op <<= 5; 7621 Value |= op; 7622 // op: offset 7623 op = getMemEncodingMMSPImm5Lsl2(MI, 1, Fixups, STI); 7624 op &= UINT64_C(31); 7625 Value |= op; 7626 break; 7627 } 7628 case Mips::NOT16_MM: { 7629 // op: rt 7630 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7631 op &= UINT64_C(7); 7632 op <<= 3; 7633 Value |= op; 7634 // op: rs 7635 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7636 op &= UINT64_C(7); 7637 Value |= op; 7638 break; 7639 } 7640 case Mips::LBU16_MM: 7641 case Mips::SB16_MM: 7642 case Mips::SB16_MMR6: { 7643 // op: rt 7644 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7645 op &= UINT64_C(7); 7646 op <<= 7; 7647 Value |= op; 7648 // op: addr 7649 op = getMemEncodingMMImm4(MI, 1, Fixups, STI); 7650 op &= UINT64_C(127); 7651 Value |= op; 7652 break; 7653 } 7654 case Mips::LHU16_MM: 7655 case Mips::SH16_MM: 7656 case Mips::SH16_MMR6: { 7657 // op: rt 7658 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7659 op &= UINT64_C(7); 7660 op <<= 7; 7661 Value |= op; 7662 // op: addr 7663 op = getMemEncodingMMImm4Lsl1(MI, 1, Fixups, STI); 7664 op &= UINT64_C(127); 7665 Value |= op; 7666 break; 7667 } 7668 case Mips::LW16_MM: 7669 case Mips::SW16_MM: 7670 case Mips::SW16_MMR6: { 7671 // op: rt 7672 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7673 op &= UINT64_C(7); 7674 op <<= 7; 7675 Value |= op; 7676 // op: addr 7677 op = getMemEncodingMMImm4Lsl2(MI, 1, Fixups, STI); 7678 op &= UINT64_C(127); 7679 Value |= op; 7680 break; 7681 } 7682 case Mips::LWGP_MM: { 7683 // op: rt 7684 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7685 op &= UINT64_C(7); 7686 op <<= 7; 7687 Value |= op; 7688 // op: offset 7689 op = getMemEncodingMMGPImm7Lsl2(MI, 1, Fixups, STI); 7690 op &= UINT64_C(127); 7691 Value |= op; 7692 break; 7693 } 7694 case Mips::NOT16_MMR6: { 7695 // op: rt 7696 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7697 op &= UINT64_C(7); 7698 op <<= 7; 7699 Value |= op; 7700 // op: rs 7701 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7702 op &= UINT64_C(7); 7703 op <<= 4; 7704 Value |= op; 7705 break; 7706 } 7707 case Mips::SC64_R6: 7708 case Mips::SCD_R6: 7709 case Mips::SC_R6: { 7710 // op: rt 7711 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7712 op &= UINT64_C(31); 7713 op <<= 16; 7714 Value |= op; 7715 // op: addr 7716 op = getMemEncoding(MI, 2, Fixups, STI); 7717 Value |= (op & UINT64_C(2031616)) << 5; 7718 Value |= (op & UINT64_C(511)) << 7; 7719 break; 7720 } 7721 case Mips::SC: 7722 case Mips::SC64: 7723 case Mips::SCD: { 7724 // op: rt 7725 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7726 op &= UINT64_C(31); 7727 op <<= 16; 7728 Value |= op; 7729 // op: addr 7730 op = getMemEncoding(MI, 2, Fixups, STI); 7731 Value |= (op & UINT64_C(2031616)) << 5; 7732 Value |= (op & UINT64_C(65535)); 7733 break; 7734 } 7735 case Mips::CTC1: 7736 case Mips::DMTC1: 7737 case Mips::MTC1: 7738 case Mips::MTC1_D64: { 7739 // op: rt 7740 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7741 op &= UINT64_C(31); 7742 op <<= 16; 7743 Value |= op; 7744 // op: fs 7745 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7746 op &= UINT64_C(31); 7747 op <<= 11; 7748 Value |= op; 7749 break; 7750 } 7751 case Mips::DMTC0: 7752 case Mips::DMTC2: 7753 case Mips::DMTGC0: 7754 case Mips::MTC0: 7755 case Mips::MTC2: 7756 case Mips::MTGC0: 7757 case Mips::MTHGC0: { 7758 // op: rt 7759 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7760 op &= UINT64_C(31); 7761 op <<= 16; 7762 Value |= op; 7763 // op: rd 7764 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7765 op &= UINT64_C(31); 7766 op <<= 11; 7767 Value |= op; 7768 // op: sel 7769 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7770 op &= UINT64_C(7); 7771 Value |= op; 7772 break; 7773 } 7774 case Mips::MFTR: 7775 case Mips::MTTR: { 7776 // op: rt 7777 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7778 op &= UINT64_C(31); 7779 op <<= 16; 7780 Value |= op; 7781 // op: rd 7782 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7783 op &= UINT64_C(31); 7784 op <<= 11; 7785 Value |= op; 7786 // op: u 7787 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7788 op &= UINT64_C(1); 7789 op <<= 5; 7790 Value |= op; 7791 // op: h 7792 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7793 op &= UINT64_C(1); 7794 op <<= 4; 7795 Value |= op; 7796 // op: sel 7797 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 7798 op &= UINT64_C(7); 7799 Value |= op; 7800 break; 7801 } 7802 case Mips::SCE_MM: { 7803 // op: rt 7804 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7805 op &= UINT64_C(31); 7806 op <<= 21; 7807 Value |= op; 7808 // op: addr 7809 op = getMemEncoding(MI, 2, Fixups, STI); 7810 Value |= (op & UINT64_C(2031616)); 7811 Value |= (op & UINT64_C(511)); 7812 break; 7813 } 7814 case Mips::SC_MM: { 7815 // op: rt 7816 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7817 op &= UINT64_C(31); 7818 op <<= 21; 7819 Value |= op; 7820 // op: addr 7821 op = getMemEncodingMMImm12(MI, 2, Fixups, STI); 7822 Value |= (op & UINT64_C(2031616)); 7823 Value |= (op & UINT64_C(4095)); 7824 break; 7825 } 7826 case Mips::SC_MMR6: { 7827 // op: rt 7828 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7829 op &= UINT64_C(31); 7830 op <<= 21; 7831 Value |= op; 7832 // op: addr 7833 op = getMemEncodingMMImm9(MI, 2, Fixups, STI); 7834 Value |= (op & UINT64_C(2031616)); 7835 Value |= (op & UINT64_C(511)); 7836 break; 7837 } 7838 case Mips::CTC1_MM: 7839 case Mips::MTC1_D64_MM: 7840 case Mips::MTC1_MM: 7841 case Mips::MTC1_MMR6: { 7842 // op: rt 7843 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7844 op &= UINT64_C(31); 7845 op <<= 21; 7846 Value |= op; 7847 // op: fs 7848 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7849 op &= UINT64_C(31); 7850 op <<= 16; 7851 Value |= op; 7852 break; 7853 } 7854 case Mips::CTC2_MM: 7855 case Mips::MTC2_MMR6: 7856 case Mips::MTHC2_MMR6: { 7857 // op: rt 7858 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7859 op &= UINT64_C(31); 7860 op <<= 21; 7861 Value |= op; 7862 // op: impl 7863 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7864 op &= UINT64_C(31); 7865 op <<= 16; 7866 Value |= op; 7867 break; 7868 } 7869 case Mips::CMPU_EQ_QB_MM: 7870 case Mips::CMPU_LE_QB_MM: 7871 case Mips::CMPU_LT_QB_MM: 7872 case Mips::CMP_EQ_PH_MM: 7873 case Mips::CMP_LE_PH_MM: 7874 case Mips::CMP_LT_PH_MM: { 7875 // op: rt 7876 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7877 op &= UINT64_C(31); 7878 op <<= 21; 7879 Value |= op; 7880 // op: rs 7881 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7882 op &= UINT64_C(31); 7883 op <<= 16; 7884 Value |= op; 7885 break; 7886 } 7887 case Mips::BEQC_MMR6: 7888 case Mips::BGEC_MMR6: 7889 case Mips::BGEUC_MMR6: 7890 case Mips::BLTC_MMR6: 7891 case Mips::BLTUC_MMR6: 7892 case Mips::BNEC_MMR6: { 7893 // op: rt 7894 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7895 op &= UINT64_C(31); 7896 op <<= 21; 7897 Value |= op; 7898 // op: rs 7899 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7900 op &= UINT64_C(31); 7901 op <<= 16; 7902 Value |= op; 7903 // op: offset 7904 op = getBranchTargetOpValueLsl2MMR6(MI, 2, Fixups, STI); 7905 op &= UINT64_C(65535); 7906 Value |= op; 7907 break; 7908 } 7909 case Mips::MTC0_MMR6: 7910 case Mips::MTGC0_MM: 7911 case Mips::MTHC0_MMR6: 7912 case Mips::MTHGC0_MM: { 7913 // op: rt 7914 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7915 op &= UINT64_C(31); 7916 op <<= 21; 7917 Value |= op; 7918 // op: rs 7919 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7920 op &= UINT64_C(31); 7921 op <<= 16; 7922 Value |= op; 7923 // op: sel 7924 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7925 op &= UINT64_C(7); 7926 op <<= 11; 7927 Value |= op; 7928 break; 7929 } 7930 case Mips::MTHC1_D32: 7931 case Mips::MTHC1_D64: { 7932 // op: rt 7933 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7934 op &= UINT64_C(31); 7935 op <<= 16; 7936 Value |= op; 7937 // op: fs 7938 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7939 op &= UINT64_C(31); 7940 op <<= 11; 7941 Value |= op; 7942 break; 7943 } 7944 case Mips::SPLAT_B: 7945 case Mips::SPLAT_D: 7946 case Mips::SPLAT_H: 7947 case Mips::SPLAT_W: { 7948 // op: rt 7949 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7950 op &= UINT64_C(31); 7951 op <<= 16; 7952 Value |= op; 7953 // op: ws 7954 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7955 op &= UINT64_C(31); 7956 op <<= 11; 7957 Value |= op; 7958 // op: wd 7959 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7960 op &= UINT64_C(31); 7961 op <<= 6; 7962 Value |= op; 7963 break; 7964 } 7965 case Mips::MTHC1_D32_MM: 7966 case Mips::MTHC1_D64_MM: { 7967 // op: rt 7968 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7969 op &= UINT64_C(31); 7970 op <<= 21; 7971 Value |= op; 7972 // op: fs 7973 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7974 op &= UINT64_C(31); 7975 op <<= 16; 7976 Value |= op; 7977 break; 7978 } 7979 case Mips::DPAQX_SA_W_PH_MMR2: 7980 case Mips::DPAQX_S_W_PH_MMR2: 7981 case Mips::DPAQ_SA_L_W_MM: 7982 case Mips::DPAQ_S_W_PH_MM: 7983 case Mips::DPAU_H_QBL_MM: 7984 case Mips::DPAU_H_QBR_MM: 7985 case Mips::DPAX_W_PH_MMR2: 7986 case Mips::DPA_W_PH_MMR2: 7987 case Mips::DPSQX_SA_W_PH_MMR2: 7988 case Mips::DPSQX_S_W_PH_MMR2: 7989 case Mips::DPSQ_SA_L_W_MM: 7990 case Mips::DPSQ_S_W_PH_MM: 7991 case Mips::DPSU_H_QBL_MM: 7992 case Mips::DPSU_H_QBR_MM: 7993 case Mips::DPSX_W_PH_MMR2: 7994 case Mips::DPS_W_PH_MMR2: 7995 case Mips::MADDU_DSP_MM: 7996 case Mips::MADD_DSP_MM: 7997 case Mips::MAQ_SA_W_PHL_MM: 7998 case Mips::MAQ_SA_W_PHR_MM: 7999 case Mips::MAQ_S_W_PHL_MM: 8000 case Mips::MAQ_S_W_PHR_MM: 8001 case Mips::MSUBU_DSP_MM: 8002 case Mips::MSUB_DSP_MM: 8003 case Mips::MULSAQ_S_W_PH_MM: 8004 case Mips::MULSA_W_PH_MMR2: 8005 case Mips::MULTU_DSP_MM: 8006 case Mips::MULT_DSP_MM: { 8007 // op: rt 8008 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8009 op &= UINT64_C(31); 8010 op <<= 21; 8011 Value |= op; 8012 // op: rs 8013 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8014 op &= UINT64_C(31); 8015 op <<= 16; 8016 Value |= op; 8017 // op: ac 8018 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8019 op &= UINT64_C(3); 8020 op <<= 14; 8021 Value |= op; 8022 break; 8023 } 8024 case Mips::ADD_MM: 8025 case Mips::ADDu_MM: 8026 case Mips::AND_MM: 8027 case Mips::CMPGU_EQ_QB_MM: 8028 case Mips::CMPGU_LE_QB_MM: 8029 case Mips::CMPGU_LT_QB_MM: 8030 case Mips::MOVN_I_MM: 8031 case Mips::MOVZ_I_MM: 8032 case Mips::MUL_MM: 8033 case Mips::NOR_MM: 8034 case Mips::OR_MM: 8035 case Mips::SLT_MM: 8036 case Mips::SLTu_MM: 8037 case Mips::SUB_MM: 8038 case Mips::SUBu_MM: 8039 case Mips::XOR_MM: { 8040 // op: rt 8041 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8042 op &= UINT64_C(31); 8043 op <<= 21; 8044 Value |= op; 8045 // op: rs 8046 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8047 op &= UINT64_C(31); 8048 op <<= 16; 8049 Value |= op; 8050 // op: rd 8051 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8052 op &= UINT64_C(31); 8053 op <<= 11; 8054 Value |= op; 8055 break; 8056 } 8057 case Mips::AND16_MM: 8058 case Mips::OR16_MM: 8059 case Mips::XOR16_MM: { 8060 // op: rt 8061 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8062 op &= UINT64_C(7); 8063 op <<= 3; 8064 Value |= op; 8065 // op: rs 8066 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8067 op &= UINT64_C(7); 8068 Value |= op; 8069 break; 8070 } 8071 case Mips::AND16_MMR6: 8072 case Mips::OR16_MMR6: 8073 case Mips::XOR16_MMR6: { 8074 // op: rt 8075 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8076 op &= UINT64_C(7); 8077 op <<= 7; 8078 Value |= op; 8079 // op: rs 8080 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8081 op &= UINT64_C(7); 8082 op <<= 4; 8083 Value |= op; 8084 break; 8085 } 8086 case Mips::SLD_B: 8087 case Mips::SLD_D: 8088 case Mips::SLD_H: 8089 case Mips::SLD_W: { 8090 // op: rt 8091 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 8092 op &= UINT64_C(31); 8093 op <<= 16; 8094 Value |= op; 8095 // op: ws 8096 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8097 op &= UINT64_C(31); 8098 op <<= 11; 8099 Value |= op; 8100 // op: wd 8101 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8102 op &= UINT64_C(31); 8103 op <<= 6; 8104 Value |= op; 8105 break; 8106 } 8107 case Mips::MOVEP_MMR6: { 8108 // op: rt 8109 op = getMovePRegSingleOpValue(MI, 3, Fixups, STI); 8110 op &= UINT64_C(7); 8111 op <<= 4; 8112 Value |= op; 8113 // op: rs 8114 op = getMovePRegSingleOpValue(MI, 2, Fixups, STI); 8115 Value |= (op & UINT64_C(4)) << 1; 8116 Value |= (op & UINT64_C(3)); 8117 break; 8118 } 8119 case Mips::MOVEP_MM: { 8120 // op: rt 8121 op = getMovePRegSingleOpValue(MI, 3, Fixups, STI); 8122 op &= UINT64_C(7); 8123 op <<= 4; 8124 Value |= op; 8125 // op: rs 8126 op = getMovePRegSingleOpValue(MI, 2, Fixups, STI); 8127 op &= UINT64_C(7); 8128 op <<= 1; 8129 Value |= op; 8130 break; 8131 } 8132 case Mips::LWM32_MM: 8133 case Mips::SWM32_MM: { 8134 // op: rt 8135 op = getRegisterListOpValue(MI, 0, Fixups, STI); 8136 op &= UINT64_C(31); 8137 op <<= 21; 8138 Value |= op; 8139 // op: addr 8140 op = getMemEncodingMMImm12(MI, 1, Fixups, STI); 8141 Value |= (op & UINT64_C(2031616)); 8142 Value |= (op & UINT64_C(4095)); 8143 break; 8144 } 8145 case Mips::LWM16_MM: 8146 case Mips::SWM16_MM: { 8147 // op: rt 8148 op = getRegisterListOpValue16(MI, 0, Fixups, STI); 8149 op &= UINT64_C(3); 8150 op <<= 4; 8151 Value |= op; 8152 // op: addr 8153 op = getMemEncodingMMImm4sp(MI, 1, Fixups, STI); 8154 op &= UINT64_C(15); 8155 Value |= op; 8156 break; 8157 } 8158 case Mips::LWM16_MMR6: 8159 case Mips::SWM16_MMR6: { 8160 // op: rt 8161 op = getRegisterListOpValue16(MI, 0, Fixups, STI); 8162 op &= UINT64_C(3); 8163 op <<= 8; 8164 Value |= op; 8165 // op: addr 8166 op = getMemEncodingMMImm4sp(MI, 1, Fixups, STI); 8167 op &= UINT64_C(15); 8168 op <<= 4; 8169 Value |= op; 8170 break; 8171 } 8172 case Mips::JumpLinkReg16: 8173 case Mips::Mfhi16: 8174 case Mips::Mflo16: 8175 case Mips::SebRx16: 8176 case Mips::SehRx16: { 8177 // op: rx 8178 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8179 op &= UINT64_C(7); 8180 op <<= 8; 8181 Value |= op; 8182 break; 8183 } 8184 case Mips::BeqzRxImm16: 8185 case Mips::BnezRxImm16: { 8186 // op: rx 8187 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8188 op &= UINT64_C(7); 8189 op <<= 8; 8190 Value |= op; 8191 // op: imm8 8192 op = getBranchTargetOpValue(MI, 1, Fixups, STI); 8193 op &= UINT64_C(255); 8194 Value |= op; 8195 break; 8196 } 8197 case Mips::CmpiRxImm16: 8198 case Mips::LiRxImm16: 8199 case Mips::LwRxPcTcp16: 8200 case Mips::SltiRxImm16: 8201 case Mips::SltiuRxImm16: { 8202 // op: rx 8203 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8204 op &= UINT64_C(7); 8205 op <<= 8; 8206 Value |= op; 8207 // op: imm8 8208 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8209 op &= UINT64_C(255); 8210 Value |= op; 8211 break; 8212 } 8213 case Mips::AddiuRxRxImm16: { 8214 // op: rx 8215 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8216 op &= UINT64_C(7); 8217 op <<= 8; 8218 Value |= op; 8219 // op: imm8 8220 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8221 op &= UINT64_C(255); 8222 Value |= op; 8223 break; 8224 } 8225 case Mips::CmpRxRy16: 8226 case Mips::DivRxRy16: 8227 case Mips::DivuRxRy16: 8228 case Mips::NegRxRy16: 8229 case Mips::NotRxRy16: 8230 case Mips::SltRxRy16: 8231 case Mips::SltuRxRy16: { 8232 // op: rx 8233 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8234 op &= UINT64_C(7); 8235 op <<= 8; 8236 Value |= op; 8237 // op: ry 8238 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8239 op &= UINT64_C(7); 8240 op <<= 5; 8241 Value |= op; 8242 break; 8243 } 8244 case Mips::AndRxRxRy16: 8245 case Mips::OrRxRxRy16: 8246 case Mips::SllvRxRy16: 8247 case Mips::SravRxRy16: 8248 case Mips::SrlvRxRy16: 8249 case Mips::XorRxRxRy16: { 8250 // op: rx 8251 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8252 op &= UINT64_C(7); 8253 op <<= 8; 8254 Value |= op; 8255 // op: ry 8256 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8257 op &= UINT64_C(7); 8258 op <<= 5; 8259 Value |= op; 8260 break; 8261 } 8262 case Mips::AdduRxRyRz16: 8263 case Mips::SubuRxRyRz16: { 8264 // op: rx 8265 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8266 op &= UINT64_C(7); 8267 op <<= 8; 8268 Value |= op; 8269 // op: ry 8270 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8271 op &= UINT64_C(7); 8272 op <<= 5; 8273 Value |= op; 8274 // op: rz 8275 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8276 op &= UINT64_C(7); 8277 op <<= 2; 8278 Value |= op; 8279 break; 8280 } 8281 case Mips::MoveR3216: { 8282 // op: ry 8283 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8284 op &= UINT64_C(15); 8285 op <<= 4; 8286 Value |= op; 8287 // op: r32 8288 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8289 op &= UINT64_C(15); 8290 Value |= op; 8291 break; 8292 } 8293 case Mips::LDI_B: 8294 case Mips::LDI_D: 8295 case Mips::LDI_H: 8296 case Mips::LDI_W: { 8297 // op: s10 8298 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8299 op &= UINT64_C(1023); 8300 op <<= 11; 8301 Value |= op; 8302 // op: wd 8303 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8304 op &= UINT64_C(31); 8305 op <<= 6; 8306 Value |= op; 8307 break; 8308 } 8309 case Mips::SllX16: 8310 case Mips::SraX16: 8311 case Mips::SrlX16: { 8312 // op: sa6 8313 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8314 Value |= (op & UINT64_C(31)) << 22; 8315 Value |= (op & UINT64_C(32)) << 16; 8316 // op: rx 8317 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8318 op &= UINT64_C(7); 8319 op <<= 8; 8320 Value |= op; 8321 // op: ry 8322 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8323 op &= UINT64_C(7); 8324 op <<= 5; 8325 Value |= op; 8326 break; 8327 } 8328 case Mips::SHILO_MM: { 8329 // op: shift 8330 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8331 op &= UINT64_C(63); 8332 op <<= 16; 8333 Value |= op; 8334 // op: ac 8335 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8336 op &= UINT64_C(3); 8337 op <<= 14; 8338 Value |= op; 8339 break; 8340 } 8341 case Mips::SYNC_MM: 8342 case Mips::SYNC_MMR6: { 8343 // op: stype 8344 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8345 op &= UINT64_C(31); 8346 op <<= 16; 8347 Value |= op; 8348 break; 8349 } 8350 case Mips::SYNC: { 8351 // op: stype 8352 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8353 op &= UINT64_C(31); 8354 op <<= 6; 8355 Value |= op; 8356 break; 8357 } 8358 case Mips::J: 8359 case Mips::JAL: 8360 case Mips::JALX: 8361 case Mips::JALX_MM: { 8362 // op: target 8363 op = getJumpTargetOpValue(MI, 0, Fixups, STI); 8364 op &= UINT64_C(67108863); 8365 Value |= op; 8366 break; 8367 } 8368 case Mips::JALS_MM: 8369 case Mips::JAL_MM: 8370 case Mips::J_MM: { 8371 // op: target 8372 op = getJumpTargetOpValueMM(MI, 0, Fixups, STI); 8373 op &= UINT64_C(67108863); 8374 Value |= op; 8375 break; 8376 } 8377 case Mips::ANDI_B: 8378 case Mips::NORI_B: 8379 case Mips::ORI_B: 8380 case Mips::SHF_B: 8381 case Mips::SHF_H: 8382 case Mips::SHF_W: 8383 case Mips::XORI_B: { 8384 // op: u8 8385 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8386 op &= UINT64_C(255); 8387 op <<= 16; 8388 Value |= op; 8389 // op: ws 8390 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8391 op &= UINT64_C(31); 8392 op <<= 11; 8393 Value |= op; 8394 // op: wd 8395 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8396 op &= UINT64_C(31); 8397 op <<= 6; 8398 Value |= op; 8399 break; 8400 } 8401 case Mips::BMNZI_B: 8402 case Mips::BMZI_B: 8403 case Mips::BSELI_B: { 8404 // op: u8 8405 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 8406 op &= UINT64_C(255); 8407 op <<= 16; 8408 Value |= op; 8409 // op: ws 8410 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8411 op &= UINT64_C(31); 8412 op <<= 11; 8413 Value |= op; 8414 // op: wd 8415 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8416 op &= UINT64_C(31); 8417 op <<= 6; 8418 Value |= op; 8419 break; 8420 } 8421 case Mips::FCLASS_D: 8422 case Mips::FCLASS_W: 8423 case Mips::FEXUPL_D: 8424 case Mips::FEXUPL_W: 8425 case Mips::FEXUPR_D: 8426 case Mips::FEXUPR_W: 8427 case Mips::FFINT_S_D: 8428 case Mips::FFINT_S_W: 8429 case Mips::FFINT_U_D: 8430 case Mips::FFINT_U_W: 8431 case Mips::FFQL_D: 8432 case Mips::FFQL_W: 8433 case Mips::FFQR_D: 8434 case Mips::FFQR_W: 8435 case Mips::FLOG2_D: 8436 case Mips::FLOG2_W: 8437 case Mips::FRCP_D: 8438 case Mips::FRCP_W: 8439 case Mips::FRINT_D: 8440 case Mips::FRINT_W: 8441 case Mips::FRSQRT_D: 8442 case Mips::FRSQRT_W: 8443 case Mips::FSQRT_D: 8444 case Mips::FSQRT_W: 8445 case Mips::FTINT_S_D: 8446 case Mips::FTINT_S_W: 8447 case Mips::FTINT_U_D: 8448 case Mips::FTINT_U_W: 8449 case Mips::FTRUNC_S_D: 8450 case Mips::FTRUNC_S_W: 8451 case Mips::FTRUNC_U_D: 8452 case Mips::FTRUNC_U_W: 8453 case Mips::MOVE_V: 8454 case Mips::NLOC_B: 8455 case Mips::NLOC_D: 8456 case Mips::NLOC_H: 8457 case Mips::NLOC_W: 8458 case Mips::NLZC_B: 8459 case Mips::NLZC_D: 8460 case Mips::NLZC_H: 8461 case Mips::NLZC_W: 8462 case Mips::PCNT_B: 8463 case Mips::PCNT_D: 8464 case Mips::PCNT_H: 8465 case Mips::PCNT_W: { 8466 // op: ws 8467 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8468 op &= UINT64_C(31); 8469 op <<= 11; 8470 Value |= op; 8471 // op: wd 8472 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8473 op &= UINT64_C(31); 8474 op <<= 6; 8475 Value |= op; 8476 break; 8477 } 8478 case Mips::BCLRI_H: 8479 case Mips::BNEGI_H: 8480 case Mips::BSETI_H: 8481 case Mips::SAT_S_H: 8482 case Mips::SAT_U_H: 8483 case Mips::SLLI_H: 8484 case Mips::SRAI_H: 8485 case Mips::SRARI_H: 8486 case Mips::SRLI_H: 8487 case Mips::SRLRI_H: { 8488 // op: ws 8489 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8490 op &= UINT64_C(31); 8491 op <<= 11; 8492 Value |= op; 8493 // op: wd 8494 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8495 op &= UINT64_C(31); 8496 op <<= 6; 8497 Value |= op; 8498 // op: m 8499 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8500 op &= UINT64_C(15); 8501 op <<= 16; 8502 Value |= op; 8503 break; 8504 } 8505 case Mips::BCLRI_W: 8506 case Mips::BNEGI_W: 8507 case Mips::BSETI_W: 8508 case Mips::SAT_S_W: 8509 case Mips::SAT_U_W: 8510 case Mips::SLLI_W: 8511 case Mips::SRAI_W: 8512 case Mips::SRARI_W: 8513 case Mips::SRLI_W: 8514 case Mips::SRLRI_W: { 8515 // op: ws 8516 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8517 op &= UINT64_C(31); 8518 op <<= 11; 8519 Value |= op; 8520 // op: wd 8521 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8522 op &= UINT64_C(31); 8523 op <<= 6; 8524 Value |= op; 8525 // op: m 8526 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8527 op &= UINT64_C(31); 8528 op <<= 16; 8529 Value |= op; 8530 break; 8531 } 8532 case Mips::BCLRI_D: 8533 case Mips::BNEGI_D: 8534 case Mips::BSETI_D: 8535 case Mips::SAT_S_D: 8536 case Mips::SAT_U_D: 8537 case Mips::SLLI_D: 8538 case Mips::SRAI_D: 8539 case Mips::SRARI_D: 8540 case Mips::SRLI_D: 8541 case Mips::SRLRI_D: { 8542 // op: ws 8543 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8544 op &= UINT64_C(31); 8545 op <<= 11; 8546 Value |= op; 8547 // op: wd 8548 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8549 op &= UINT64_C(31); 8550 op <<= 6; 8551 Value |= op; 8552 // op: m 8553 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8554 op &= UINT64_C(63); 8555 op <<= 16; 8556 Value |= op; 8557 break; 8558 } 8559 case Mips::BCLRI_B: 8560 case Mips::BNEGI_B: 8561 case Mips::BSETI_B: 8562 case Mips::SAT_S_B: 8563 case Mips::SAT_U_B: 8564 case Mips::SLLI_B: 8565 case Mips::SRAI_B: 8566 case Mips::SRARI_B: 8567 case Mips::SRLI_B: 8568 case Mips::SRLRI_B: { 8569 // op: ws 8570 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8571 op &= UINT64_C(31); 8572 op <<= 11; 8573 Value |= op; 8574 // op: wd 8575 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8576 op &= UINT64_C(31); 8577 op <<= 6; 8578 Value |= op; 8579 // op: m 8580 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8581 op &= UINT64_C(7); 8582 op <<= 16; 8583 Value |= op; 8584 break; 8585 } 8586 case Mips::BINSLI_H: 8587 case Mips::BINSRI_H: { 8588 // op: ws 8589 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8590 op &= UINT64_C(31); 8591 op <<= 11; 8592 Value |= op; 8593 // op: wd 8594 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8595 op &= UINT64_C(31); 8596 op <<= 6; 8597 Value |= op; 8598 // op: m 8599 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 8600 op &= UINT64_C(15); 8601 op <<= 16; 8602 Value |= op; 8603 break; 8604 } 8605 case Mips::BINSLI_W: 8606 case Mips::BINSRI_W: { 8607 // op: ws 8608 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8609 op &= UINT64_C(31); 8610 op <<= 11; 8611 Value |= op; 8612 // op: wd 8613 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8614 op &= UINT64_C(31); 8615 op <<= 6; 8616 Value |= op; 8617 // op: m 8618 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 8619 op &= UINT64_C(31); 8620 op <<= 16; 8621 Value |= op; 8622 break; 8623 } 8624 case Mips::BINSLI_D: 8625 case Mips::BINSRI_D: { 8626 // op: ws 8627 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8628 op &= UINT64_C(31); 8629 op <<= 11; 8630 Value |= op; 8631 // op: wd 8632 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8633 op &= UINT64_C(31); 8634 op <<= 6; 8635 Value |= op; 8636 // op: m 8637 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 8638 op &= UINT64_C(63); 8639 op <<= 16; 8640 Value |= op; 8641 break; 8642 } 8643 case Mips::BINSLI_B: 8644 case Mips::BINSRI_B: { 8645 // op: ws 8646 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8647 op &= UINT64_C(31); 8648 op <<= 11; 8649 Value |= op; 8650 // op: wd 8651 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8652 op &= UINT64_C(31); 8653 op <<= 6; 8654 Value |= op; 8655 // op: m 8656 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 8657 op &= UINT64_C(7); 8658 op <<= 16; 8659 Value |= op; 8660 break; 8661 } 8662 case Mips::ADDS_A_B: 8663 case Mips::ADDS_A_D: 8664 case Mips::ADDS_A_H: 8665 case Mips::ADDS_A_W: 8666 case Mips::ADDS_S_B: 8667 case Mips::ADDS_S_D: 8668 case Mips::ADDS_S_H: 8669 case Mips::ADDS_S_W: 8670 case Mips::ADDS_U_B: 8671 case Mips::ADDS_U_D: 8672 case Mips::ADDS_U_H: 8673 case Mips::ADDS_U_W: 8674 case Mips::ADDV_B: 8675 case Mips::ADDV_D: 8676 case Mips::ADDV_H: 8677 case Mips::ADDV_W: 8678 case Mips::ADD_A_B: 8679 case Mips::ADD_A_D: 8680 case Mips::ADD_A_H: 8681 case Mips::ADD_A_W: 8682 case Mips::AND_V: 8683 case Mips::ASUB_S_B: 8684 case Mips::ASUB_S_D: 8685 case Mips::ASUB_S_H: 8686 case Mips::ASUB_S_W: 8687 case Mips::ASUB_U_B: 8688 case Mips::ASUB_U_D: 8689 case Mips::ASUB_U_H: 8690 case Mips::ASUB_U_W: 8691 case Mips::AVER_S_B: 8692 case Mips::AVER_S_D: 8693 case Mips::AVER_S_H: 8694 case Mips::AVER_S_W: 8695 case Mips::AVER_U_B: 8696 case Mips::AVER_U_D: 8697 case Mips::AVER_U_H: 8698 case Mips::AVER_U_W: 8699 case Mips::AVE_S_B: 8700 case Mips::AVE_S_D: 8701 case Mips::AVE_S_H: 8702 case Mips::AVE_S_W: 8703 case Mips::AVE_U_B: 8704 case Mips::AVE_U_D: 8705 case Mips::AVE_U_H: 8706 case Mips::AVE_U_W: 8707 case Mips::BCLR_B: 8708 case Mips::BCLR_D: 8709 case Mips::BCLR_H: 8710 case Mips::BCLR_W: 8711 case Mips::BNEG_B: 8712 case Mips::BNEG_D: 8713 case Mips::BNEG_H: 8714 case Mips::BNEG_W: 8715 case Mips::BSET_B: 8716 case Mips::BSET_D: 8717 case Mips::BSET_H: 8718 case Mips::BSET_W: 8719 case Mips::CEQ_B: 8720 case Mips::CEQ_D: 8721 case Mips::CEQ_H: 8722 case Mips::CEQ_W: 8723 case Mips::CLE_S_B: 8724 case Mips::CLE_S_D: 8725 case Mips::CLE_S_H: 8726 case Mips::CLE_S_W: 8727 case Mips::CLE_U_B: 8728 case Mips::CLE_U_D: 8729 case Mips::CLE_U_H: 8730 case Mips::CLE_U_W: 8731 case Mips::CLT_S_B: 8732 case Mips::CLT_S_D: 8733 case Mips::CLT_S_H: 8734 case Mips::CLT_S_W: 8735 case Mips::CLT_U_B: 8736 case Mips::CLT_U_D: 8737 case Mips::CLT_U_H: 8738 case Mips::CLT_U_W: 8739 case Mips::DIV_S_B: 8740 case Mips::DIV_S_D: 8741 case Mips::DIV_S_H: 8742 case Mips::DIV_S_W: 8743 case Mips::DIV_U_B: 8744 case Mips::DIV_U_D: 8745 case Mips::DIV_U_H: 8746 case Mips::DIV_U_W: 8747 case Mips::DOTP_S_D: 8748 case Mips::DOTP_S_H: 8749 case Mips::DOTP_S_W: 8750 case Mips::DOTP_U_D: 8751 case Mips::DOTP_U_H: 8752 case Mips::DOTP_U_W: 8753 case Mips::FADD_D: 8754 case Mips::FADD_W: 8755 case Mips::FCAF_D: 8756 case Mips::FCAF_W: 8757 case Mips::FCEQ_D: 8758 case Mips::FCEQ_W: 8759 case Mips::FCLE_D: 8760 case Mips::FCLE_W: 8761 case Mips::FCLT_D: 8762 case Mips::FCLT_W: 8763 case Mips::FCNE_D: 8764 case Mips::FCNE_W: 8765 case Mips::FCOR_D: 8766 case Mips::FCOR_W: 8767 case Mips::FCUEQ_D: 8768 case Mips::FCUEQ_W: 8769 case Mips::FCULE_D: 8770 case Mips::FCULE_W: 8771 case Mips::FCULT_D: 8772 case Mips::FCULT_W: 8773 case Mips::FCUNE_D: 8774 case Mips::FCUNE_W: 8775 case Mips::FCUN_D: 8776 case Mips::FCUN_W: 8777 case Mips::FDIV_D: 8778 case Mips::FDIV_W: 8779 case Mips::FEXDO_H: 8780 case Mips::FEXDO_W: 8781 case Mips::FEXP2_D: 8782 case Mips::FEXP2_W: 8783 case Mips::FMAX_A_D: 8784 case Mips::FMAX_A_W: 8785 case Mips::FMAX_D: 8786 case Mips::FMAX_W: 8787 case Mips::FMIN_A_D: 8788 case Mips::FMIN_A_W: 8789 case Mips::FMIN_D: 8790 case Mips::FMIN_W: 8791 case Mips::FMUL_D: 8792 case Mips::FMUL_W: 8793 case Mips::FSAF_D: 8794 case Mips::FSAF_W: 8795 case Mips::FSEQ_D: 8796 case Mips::FSEQ_W: 8797 case Mips::FSLE_D: 8798 case Mips::FSLE_W: 8799 case Mips::FSLT_D: 8800 case Mips::FSLT_W: 8801 case Mips::FSNE_D: 8802 case Mips::FSNE_W: 8803 case Mips::FSOR_D: 8804 case Mips::FSOR_W: 8805 case Mips::FSUB_D: 8806 case Mips::FSUB_W: 8807 case Mips::FSUEQ_D: 8808 case Mips::FSUEQ_W: 8809 case Mips::FSULE_D: 8810 case Mips::FSULE_W: 8811 case Mips::FSULT_D: 8812 case Mips::FSULT_W: 8813 case Mips::FSUNE_D: 8814 case Mips::FSUNE_W: 8815 case Mips::FSUN_D: 8816 case Mips::FSUN_W: 8817 case Mips::FTQ_H: 8818 case Mips::FTQ_W: 8819 case Mips::HADD_S_D: 8820 case Mips::HADD_S_H: 8821 case Mips::HADD_S_W: 8822 case Mips::HADD_U_D: 8823 case Mips::HADD_U_H: 8824 case Mips::HADD_U_W: 8825 case Mips::HSUB_S_D: 8826 case Mips::HSUB_S_H: 8827 case Mips::HSUB_S_W: 8828 case Mips::HSUB_U_D: 8829 case Mips::HSUB_U_H: 8830 case Mips::HSUB_U_W: 8831 case Mips::ILVEV_B: 8832 case Mips::ILVEV_D: 8833 case Mips::ILVEV_H: 8834 case Mips::ILVEV_W: 8835 case Mips::ILVL_B: 8836 case Mips::ILVL_D: 8837 case Mips::ILVL_H: 8838 case Mips::ILVL_W: 8839 case Mips::ILVOD_B: 8840 case Mips::ILVOD_D: 8841 case Mips::ILVOD_H: 8842 case Mips::ILVOD_W: 8843 case Mips::ILVR_B: 8844 case Mips::ILVR_D: 8845 case Mips::ILVR_H: 8846 case Mips::ILVR_W: 8847 case Mips::MAX_A_B: 8848 case Mips::MAX_A_D: 8849 case Mips::MAX_A_H: 8850 case Mips::MAX_A_W: 8851 case Mips::MAX_S_B: 8852 case Mips::MAX_S_D: 8853 case Mips::MAX_S_H: 8854 case Mips::MAX_S_W: 8855 case Mips::MAX_U_B: 8856 case Mips::MAX_U_D: 8857 case Mips::MAX_U_H: 8858 case Mips::MAX_U_W: 8859 case Mips::MIN_A_B: 8860 case Mips::MIN_A_D: 8861 case Mips::MIN_A_H: 8862 case Mips::MIN_A_W: 8863 case Mips::MIN_S_B: 8864 case Mips::MIN_S_D: 8865 case Mips::MIN_S_H: 8866 case Mips::MIN_S_W: 8867 case Mips::MIN_U_B: 8868 case Mips::MIN_U_D: 8869 case Mips::MIN_U_H: 8870 case Mips::MIN_U_W: 8871 case Mips::MOD_S_B: 8872 case Mips::MOD_S_D: 8873 case Mips::MOD_S_H: 8874 case Mips::MOD_S_W: 8875 case Mips::MOD_U_B: 8876 case Mips::MOD_U_D: 8877 case Mips::MOD_U_H: 8878 case Mips::MOD_U_W: 8879 case Mips::MULR_Q_H: 8880 case Mips::MULR_Q_W: 8881 case Mips::MULV_B: 8882 case Mips::MULV_D: 8883 case Mips::MULV_H: 8884 case Mips::MULV_W: 8885 case Mips::MUL_Q_H: 8886 case Mips::MUL_Q_W: 8887 case Mips::NOR_V: 8888 case Mips::OR_V: 8889 case Mips::PCKEV_B: 8890 case Mips::PCKEV_D: 8891 case Mips::PCKEV_H: 8892 case Mips::PCKEV_W: 8893 case Mips::PCKOD_B: 8894 case Mips::PCKOD_D: 8895 case Mips::PCKOD_H: 8896 case Mips::PCKOD_W: 8897 case Mips::SLL_B: 8898 case Mips::SLL_D: 8899 case Mips::SLL_H: 8900 case Mips::SLL_W: 8901 case Mips::SRAR_B: 8902 case Mips::SRAR_D: 8903 case Mips::SRAR_H: 8904 case Mips::SRAR_W: 8905 case Mips::SRA_B: 8906 case Mips::SRA_D: 8907 case Mips::SRA_H: 8908 case Mips::SRA_W: 8909 case Mips::SRLR_B: 8910 case Mips::SRLR_D: 8911 case Mips::SRLR_H: 8912 case Mips::SRLR_W: 8913 case Mips::SRL_B: 8914 case Mips::SRL_D: 8915 case Mips::SRL_H: 8916 case Mips::SRL_W: 8917 case Mips::SUBSUS_U_B: 8918 case Mips::SUBSUS_U_D: 8919 case Mips::SUBSUS_U_H: 8920 case Mips::SUBSUS_U_W: 8921 case Mips::SUBSUU_S_B: 8922 case Mips::SUBSUU_S_D: 8923 case Mips::SUBSUU_S_H: 8924 case Mips::SUBSUU_S_W: 8925 case Mips::SUBS_S_B: 8926 case Mips::SUBS_S_D: 8927 case Mips::SUBS_S_H: 8928 case Mips::SUBS_S_W: 8929 case Mips::SUBS_U_B: 8930 case Mips::SUBS_U_D: 8931 case Mips::SUBS_U_H: 8932 case Mips::SUBS_U_W: 8933 case Mips::SUBV_B: 8934 case Mips::SUBV_D: 8935 case Mips::SUBV_H: 8936 case Mips::SUBV_W: 8937 case Mips::XOR_V: { 8938 // op: wt 8939 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8940 op &= UINT64_C(31); 8941 op <<= 16; 8942 Value |= op; 8943 // op: ws 8944 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8945 op &= UINT64_C(31); 8946 op <<= 11; 8947 Value |= op; 8948 // op: wd 8949 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8950 op &= UINT64_C(31); 8951 op <<= 6; 8952 Value |= op; 8953 break; 8954 } 8955 case Mips::BINSL_B: 8956 case Mips::BINSL_D: 8957 case Mips::BINSL_H: 8958 case Mips::BINSL_W: 8959 case Mips::BINSR_B: 8960 case Mips::BINSR_D: 8961 case Mips::BINSR_H: 8962 case Mips::BINSR_W: 8963 case Mips::BMNZ_V: 8964 case Mips::BMZ_V: 8965 case Mips::BSEL_V: 8966 case Mips::DPADD_S_D: 8967 case Mips::DPADD_S_H: 8968 case Mips::DPADD_S_W: 8969 case Mips::DPADD_U_D: 8970 case Mips::DPADD_U_H: 8971 case Mips::DPADD_U_W: 8972 case Mips::DPSUB_S_D: 8973 case Mips::DPSUB_S_H: 8974 case Mips::DPSUB_S_W: 8975 case Mips::DPSUB_U_D: 8976 case Mips::DPSUB_U_H: 8977 case Mips::DPSUB_U_W: 8978 case Mips::FMADD_D: 8979 case Mips::FMADD_W: 8980 case Mips::FMSUB_D: 8981 case Mips::FMSUB_W: 8982 case Mips::MADDR_Q_H: 8983 case Mips::MADDR_Q_W: 8984 case Mips::MADDV_B: 8985 case Mips::MADDV_D: 8986 case Mips::MADDV_H: 8987 case Mips::MADDV_W: 8988 case Mips::MADD_Q_H: 8989 case Mips::MADD_Q_W: 8990 case Mips::MSUBR_Q_H: 8991 case Mips::MSUBR_Q_W: 8992 case Mips::MSUBV_B: 8993 case Mips::MSUBV_D: 8994 case Mips::MSUBV_H: 8995 case Mips::MSUBV_W: 8996 case Mips::MSUB_Q_H: 8997 case Mips::MSUB_Q_W: 8998 case Mips::VSHF_B: 8999 case Mips::VSHF_D: 9000 case Mips::VSHF_H: 9001 case Mips::VSHF_W: { 9002 // op: wt 9003 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9004 op &= UINT64_C(31); 9005 op <<= 16; 9006 Value |= op; 9007 // op: ws 9008 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9009 op &= UINT64_C(31); 9010 op <<= 11; 9011 Value |= op; 9012 // op: wd 9013 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9014 op &= UINT64_C(31); 9015 op <<= 6; 9016 Value |= op; 9017 break; 9018 } 9019 default: 9020 std::string msg; 9021 raw_string_ostream Msg(msg); 9022 Msg << "Not supported instr: " << MI; 9023 report_fatal_error(Msg.str().c_str()); 9024 } 9025 return Value; 9026} 9027 9028