1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2|* *| 3|* Pseudo-instruction MC lowering Source Fragment *| 4|* *| 5|* Automatically generated file, do not edit! *| 6|* *| 7\*===----------------------------------------------------------------------===*/ 8 9bool MipsAsmPrinter:: 10emitPseudoExpansionLowering(MCStreamer &OutStreamer, 11 const MachineInstr *MI) { 12 switch (MI->getOpcode()) { 13 default: return false; 14 case Mips::AND_V_D_PSEUDO: { 15 MCInst TmpInst; 16 MCOperand MCOp; 17 TmpInst.setOpcode(Mips::AND_V); 18 // Operand: wd 19 lowerOperand(MI->getOperand(0), MCOp); 20 TmpInst.addOperand(MCOp); 21 // Operand: ws 22 lowerOperand(MI->getOperand(1), MCOp); 23 TmpInst.addOperand(MCOp); 24 // Operand: wt 25 lowerOperand(MI->getOperand(2), MCOp); 26 TmpInst.addOperand(MCOp); 27 EmitToStreamer(OutStreamer, TmpInst); 28 break; 29 } 30 case Mips::AND_V_H_PSEUDO: { 31 MCInst TmpInst; 32 MCOperand MCOp; 33 TmpInst.setOpcode(Mips::AND_V); 34 // Operand: wd 35 lowerOperand(MI->getOperand(0), MCOp); 36 TmpInst.addOperand(MCOp); 37 // Operand: ws 38 lowerOperand(MI->getOperand(1), MCOp); 39 TmpInst.addOperand(MCOp); 40 // Operand: wt 41 lowerOperand(MI->getOperand(2), MCOp); 42 TmpInst.addOperand(MCOp); 43 EmitToStreamer(OutStreamer, TmpInst); 44 break; 45 } 46 case Mips::AND_V_W_PSEUDO: { 47 MCInst TmpInst; 48 MCOperand MCOp; 49 TmpInst.setOpcode(Mips::AND_V); 50 // Operand: wd 51 lowerOperand(MI->getOperand(0), MCOp); 52 TmpInst.addOperand(MCOp); 53 // Operand: ws 54 lowerOperand(MI->getOperand(1), MCOp); 55 TmpInst.addOperand(MCOp); 56 // Operand: wt 57 lowerOperand(MI->getOperand(2), MCOp); 58 TmpInst.addOperand(MCOp); 59 EmitToStreamer(OutStreamer, TmpInst); 60 break; 61 } 62 case Mips::B: { 63 MCInst TmpInst; 64 MCOperand MCOp; 65 TmpInst.setOpcode(Mips::BEQ); 66 // Operand: rs 67 TmpInst.addOperand(MCOperand::createReg(Mips::ZERO)); 68 // Operand: rt 69 TmpInst.addOperand(MCOperand::createReg(Mips::ZERO)); 70 // Operand: offset 71 lowerOperand(MI->getOperand(0), MCOp); 72 TmpInst.addOperand(MCOp); 73 EmitToStreamer(OutStreamer, TmpInst); 74 break; 75 } 76 case Mips::BAL_BR: { 77 MCInst TmpInst; 78 MCOperand MCOp; 79 TmpInst.setOpcode(Mips::BGEZAL); 80 // Operand: rs 81 TmpInst.addOperand(MCOperand::createReg(Mips::ZERO)); 82 // Operand: offset 83 lowerOperand(MI->getOperand(0), MCOp); 84 TmpInst.addOperand(MCOp); 85 EmitToStreamer(OutStreamer, TmpInst); 86 break; 87 } 88 case Mips::BAL_BR_MM: { 89 MCInst TmpInst; 90 MCOperand MCOp; 91 TmpInst.setOpcode(Mips::BGEZAL_MM); 92 // Operand: rs 93 TmpInst.addOperand(MCOperand::createReg(Mips::ZERO)); 94 // Operand: offset 95 lowerOperand(MI->getOperand(0), MCOp); 96 TmpInst.addOperand(MCOp); 97 EmitToStreamer(OutStreamer, TmpInst); 98 break; 99 } 100 case Mips::BSEL_D_PSEUDO: { 101 MCInst TmpInst; 102 MCOperand MCOp; 103 TmpInst.setOpcode(Mips::BSEL_V); 104 // Operand: wd 105 lowerOperand(MI->getOperand(0), MCOp); 106 TmpInst.addOperand(MCOp); 107 // Operand: wd_in 108 lowerOperand(MI->getOperand(1), MCOp); 109 TmpInst.addOperand(MCOp); 110 // Operand: ws 111 lowerOperand(MI->getOperand(2), MCOp); 112 TmpInst.addOperand(MCOp); 113 // Operand: wt 114 lowerOperand(MI->getOperand(3), MCOp); 115 TmpInst.addOperand(MCOp); 116 EmitToStreamer(OutStreamer, TmpInst); 117 break; 118 } 119 case Mips::BSEL_FD_PSEUDO: { 120 MCInst TmpInst; 121 MCOperand MCOp; 122 TmpInst.setOpcode(Mips::BSEL_V); 123 // Operand: wd 124 lowerOperand(MI->getOperand(0), MCOp); 125 TmpInst.addOperand(MCOp); 126 // Operand: wd_in 127 lowerOperand(MI->getOperand(1), MCOp); 128 TmpInst.addOperand(MCOp); 129 // Operand: ws 130 lowerOperand(MI->getOperand(2), MCOp); 131 TmpInst.addOperand(MCOp); 132 // Operand: wt 133 lowerOperand(MI->getOperand(3), MCOp); 134 TmpInst.addOperand(MCOp); 135 EmitToStreamer(OutStreamer, TmpInst); 136 break; 137 } 138 case Mips::BSEL_FW_PSEUDO: { 139 MCInst TmpInst; 140 MCOperand MCOp; 141 TmpInst.setOpcode(Mips::BSEL_V); 142 // Operand: wd 143 lowerOperand(MI->getOperand(0), MCOp); 144 TmpInst.addOperand(MCOp); 145 // Operand: wd_in 146 lowerOperand(MI->getOperand(1), MCOp); 147 TmpInst.addOperand(MCOp); 148 // Operand: ws 149 lowerOperand(MI->getOperand(2), MCOp); 150 TmpInst.addOperand(MCOp); 151 // Operand: wt 152 lowerOperand(MI->getOperand(3), MCOp); 153 TmpInst.addOperand(MCOp); 154 EmitToStreamer(OutStreamer, TmpInst); 155 break; 156 } 157 case Mips::BSEL_H_PSEUDO: { 158 MCInst TmpInst; 159 MCOperand MCOp; 160 TmpInst.setOpcode(Mips::BSEL_V); 161 // Operand: wd 162 lowerOperand(MI->getOperand(0), MCOp); 163 TmpInst.addOperand(MCOp); 164 // Operand: wd_in 165 lowerOperand(MI->getOperand(1), MCOp); 166 TmpInst.addOperand(MCOp); 167 // Operand: ws 168 lowerOperand(MI->getOperand(2), MCOp); 169 TmpInst.addOperand(MCOp); 170 // Operand: wt 171 lowerOperand(MI->getOperand(3), MCOp); 172 TmpInst.addOperand(MCOp); 173 EmitToStreamer(OutStreamer, TmpInst); 174 break; 175 } 176 case Mips::BSEL_W_PSEUDO: { 177 MCInst TmpInst; 178 MCOperand MCOp; 179 TmpInst.setOpcode(Mips::BSEL_V); 180 // Operand: wd 181 lowerOperand(MI->getOperand(0), MCOp); 182 TmpInst.addOperand(MCOp); 183 // Operand: wd_in 184 lowerOperand(MI->getOperand(1), MCOp); 185 TmpInst.addOperand(MCOp); 186 // Operand: ws 187 lowerOperand(MI->getOperand(2), MCOp); 188 TmpInst.addOperand(MCOp); 189 // Operand: wt 190 lowerOperand(MI->getOperand(3), MCOp); 191 TmpInst.addOperand(MCOp); 192 EmitToStreamer(OutStreamer, TmpInst); 193 break; 194 } 195 case Mips::B_MM: { 196 MCInst TmpInst; 197 MCOperand MCOp; 198 TmpInst.setOpcode(Mips::BEQ_MM); 199 // Operand: rs 200 TmpInst.addOperand(MCOperand::createReg(Mips::ZERO)); 201 // Operand: rt 202 TmpInst.addOperand(MCOperand::createReg(Mips::ZERO)); 203 // Operand: offset 204 lowerOperand(MI->getOperand(0), MCOp); 205 TmpInst.addOperand(MCOp); 206 EmitToStreamer(OutStreamer, TmpInst); 207 break; 208 } 209 case Mips::FABS_D: { 210 MCInst TmpInst; 211 MCOperand MCOp; 212 TmpInst.setOpcode(Mips::FMAX_A_D); 213 // Operand: wd 214 lowerOperand(MI->getOperand(0), MCOp); 215 TmpInst.addOperand(MCOp); 216 // Operand: ws 217 lowerOperand(MI->getOperand(1), MCOp); 218 TmpInst.addOperand(MCOp); 219 // Operand: wt 220 lowerOperand(MI->getOperand(1), MCOp); 221 TmpInst.addOperand(MCOp); 222 EmitToStreamer(OutStreamer, TmpInst); 223 break; 224 } 225 case Mips::FABS_W: { 226 MCInst TmpInst; 227 MCOperand MCOp; 228 TmpInst.setOpcode(Mips::FMAX_A_W); 229 // Operand: wd 230 lowerOperand(MI->getOperand(0), MCOp); 231 TmpInst.addOperand(MCOp); 232 // Operand: ws 233 lowerOperand(MI->getOperand(1), MCOp); 234 TmpInst.addOperand(MCOp); 235 // Operand: wt 236 lowerOperand(MI->getOperand(1), MCOp); 237 TmpInst.addOperand(MCOp); 238 EmitToStreamer(OutStreamer, TmpInst); 239 break; 240 } 241 case Mips::JALR64Pseudo: { 242 MCInst TmpInst; 243 MCOperand MCOp; 244 TmpInst.setOpcode(Mips::JALR); 245 // Operand: rd 246 TmpInst.addOperand(MCOperand::createReg(Mips::RA)); 247 // Operand: rs 248 lowerOperand(MI->getOperand(0), MCOp); 249 TmpInst.addOperand(MCOp); 250 EmitToStreamer(OutStreamer, TmpInst); 251 break; 252 } 253 case Mips::JALRHB64Pseudo: { 254 MCInst TmpInst; 255 MCOperand MCOp; 256 TmpInst.setOpcode(Mips::JALR_HB64); 257 // Operand: rd 258 TmpInst.addOperand(MCOperand::createReg(Mips::RA_64)); 259 // Operand: rs 260 lowerOperand(MI->getOperand(0), MCOp); 261 TmpInst.addOperand(MCOp); 262 EmitToStreamer(OutStreamer, TmpInst); 263 break; 264 } 265 case Mips::JALRHBPseudo: { 266 MCInst TmpInst; 267 MCOperand MCOp; 268 TmpInst.setOpcode(Mips::JALR_HB); 269 // Operand: rd 270 TmpInst.addOperand(MCOperand::createReg(Mips::RA)); 271 // Operand: rs 272 lowerOperand(MI->getOperand(0), MCOp); 273 TmpInst.addOperand(MCOp); 274 EmitToStreamer(OutStreamer, TmpInst); 275 break; 276 } 277 case Mips::JALRPseudo: { 278 MCInst TmpInst; 279 MCOperand MCOp; 280 TmpInst.setOpcode(Mips::JALR); 281 // Operand: rd 282 TmpInst.addOperand(MCOperand::createReg(Mips::RA)); 283 // Operand: rs 284 lowerOperand(MI->getOperand(0), MCOp); 285 TmpInst.addOperand(MCOp); 286 EmitToStreamer(OutStreamer, TmpInst); 287 break; 288 } 289 case Mips::JAL_MMR6: { 290 MCInst TmpInst; 291 MCOperand MCOp; 292 TmpInst.setOpcode(Mips::BALC_MMR6); 293 // Operand: offset 294 lowerOperand(MI->getOperand(0), MCOp); 295 TmpInst.addOperand(MCOp); 296 EmitToStreamer(OutStreamer, TmpInst); 297 break; 298 } 299 case Mips::NOP: { 300 MCInst TmpInst; 301 MCOperand MCOp; 302 TmpInst.setOpcode(Mips::SLL); 303 // Operand: rd 304 TmpInst.addOperand(MCOperand::createReg(Mips::ZERO)); 305 // Operand: rt 306 TmpInst.addOperand(MCOperand::createReg(Mips::ZERO)); 307 // Operand: shamt 308 TmpInst.addOperand(MCOperand::createImm(0)); 309 EmitToStreamer(OutStreamer, TmpInst); 310 break; 311 } 312 case Mips::NOR_V_D_PSEUDO: { 313 MCInst TmpInst; 314 MCOperand MCOp; 315 TmpInst.setOpcode(Mips::NOR_V); 316 // Operand: wd 317 lowerOperand(MI->getOperand(0), MCOp); 318 TmpInst.addOperand(MCOp); 319 // Operand: ws 320 lowerOperand(MI->getOperand(1), MCOp); 321 TmpInst.addOperand(MCOp); 322 // Operand: wt 323 lowerOperand(MI->getOperand(2), MCOp); 324 TmpInst.addOperand(MCOp); 325 EmitToStreamer(OutStreamer, TmpInst); 326 break; 327 } 328 case Mips::NOR_V_H_PSEUDO: { 329 MCInst TmpInst; 330 MCOperand MCOp; 331 TmpInst.setOpcode(Mips::NOR_V); 332 // Operand: wd 333 lowerOperand(MI->getOperand(0), MCOp); 334 TmpInst.addOperand(MCOp); 335 // Operand: ws 336 lowerOperand(MI->getOperand(1), MCOp); 337 TmpInst.addOperand(MCOp); 338 // Operand: wt 339 lowerOperand(MI->getOperand(2), MCOp); 340 TmpInst.addOperand(MCOp); 341 EmitToStreamer(OutStreamer, TmpInst); 342 break; 343 } 344 case Mips::NOR_V_W_PSEUDO: { 345 MCInst TmpInst; 346 MCOperand MCOp; 347 TmpInst.setOpcode(Mips::NOR_V); 348 // Operand: wd 349 lowerOperand(MI->getOperand(0), MCOp); 350 TmpInst.addOperand(MCOp); 351 // Operand: ws 352 lowerOperand(MI->getOperand(1), MCOp); 353 TmpInst.addOperand(MCOp); 354 // Operand: wt 355 lowerOperand(MI->getOperand(2), MCOp); 356 TmpInst.addOperand(MCOp); 357 EmitToStreamer(OutStreamer, TmpInst); 358 break; 359 } 360 case Mips::OR_V_D_PSEUDO: { 361 MCInst TmpInst; 362 MCOperand MCOp; 363 TmpInst.setOpcode(Mips::OR_V); 364 // Operand: wd 365 lowerOperand(MI->getOperand(0), MCOp); 366 TmpInst.addOperand(MCOp); 367 // Operand: ws 368 lowerOperand(MI->getOperand(1), MCOp); 369 TmpInst.addOperand(MCOp); 370 // Operand: wt 371 lowerOperand(MI->getOperand(2), MCOp); 372 TmpInst.addOperand(MCOp); 373 EmitToStreamer(OutStreamer, TmpInst); 374 break; 375 } 376 case Mips::OR_V_H_PSEUDO: { 377 MCInst TmpInst; 378 MCOperand MCOp; 379 TmpInst.setOpcode(Mips::OR_V); 380 // Operand: wd 381 lowerOperand(MI->getOperand(0), MCOp); 382 TmpInst.addOperand(MCOp); 383 // Operand: ws 384 lowerOperand(MI->getOperand(1), MCOp); 385 TmpInst.addOperand(MCOp); 386 // Operand: wt 387 lowerOperand(MI->getOperand(2), MCOp); 388 TmpInst.addOperand(MCOp); 389 EmitToStreamer(OutStreamer, TmpInst); 390 break; 391 } 392 case Mips::OR_V_W_PSEUDO: { 393 MCInst TmpInst; 394 MCOperand MCOp; 395 TmpInst.setOpcode(Mips::OR_V); 396 // Operand: wd 397 lowerOperand(MI->getOperand(0), MCOp); 398 TmpInst.addOperand(MCOp); 399 // Operand: ws 400 lowerOperand(MI->getOperand(1), MCOp); 401 TmpInst.addOperand(MCOp); 402 // Operand: wt 403 lowerOperand(MI->getOperand(2), MCOp); 404 TmpInst.addOperand(MCOp); 405 EmitToStreamer(OutStreamer, TmpInst); 406 break; 407 } 408 case Mips::PseudoCMPU_EQ_QB: { 409 MCInst TmpInst; 410 MCOperand MCOp; 411 TmpInst.setOpcode(Mips::CMPU_EQ_QB); 412 // Operand: rs 413 lowerOperand(MI->getOperand(1), MCOp); 414 TmpInst.addOperand(MCOp); 415 // Operand: rt 416 lowerOperand(MI->getOperand(2), MCOp); 417 TmpInst.addOperand(MCOp); 418 EmitToStreamer(OutStreamer, TmpInst); 419 break; 420 } 421 case Mips::PseudoCMPU_LE_QB: { 422 MCInst TmpInst; 423 MCOperand MCOp; 424 TmpInst.setOpcode(Mips::CMPU_LE_QB); 425 // Operand: rs 426 lowerOperand(MI->getOperand(1), MCOp); 427 TmpInst.addOperand(MCOp); 428 // Operand: rt 429 lowerOperand(MI->getOperand(2), MCOp); 430 TmpInst.addOperand(MCOp); 431 EmitToStreamer(OutStreamer, TmpInst); 432 break; 433 } 434 case Mips::PseudoCMPU_LT_QB: { 435 MCInst TmpInst; 436 MCOperand MCOp; 437 TmpInst.setOpcode(Mips::CMPU_LT_QB); 438 // Operand: rs 439 lowerOperand(MI->getOperand(1), MCOp); 440 TmpInst.addOperand(MCOp); 441 // Operand: rt 442 lowerOperand(MI->getOperand(2), MCOp); 443 TmpInst.addOperand(MCOp); 444 EmitToStreamer(OutStreamer, TmpInst); 445 break; 446 } 447 case Mips::PseudoCMP_EQ_PH: { 448 MCInst TmpInst; 449 MCOperand MCOp; 450 TmpInst.setOpcode(Mips::CMP_EQ_PH); 451 // Operand: rs 452 lowerOperand(MI->getOperand(1), MCOp); 453 TmpInst.addOperand(MCOp); 454 // Operand: rt 455 lowerOperand(MI->getOperand(2), MCOp); 456 TmpInst.addOperand(MCOp); 457 EmitToStreamer(OutStreamer, TmpInst); 458 break; 459 } 460 case Mips::PseudoCMP_LE_PH: { 461 MCInst TmpInst; 462 MCOperand MCOp; 463 TmpInst.setOpcode(Mips::CMP_LE_PH); 464 // Operand: rs 465 lowerOperand(MI->getOperand(1), MCOp); 466 TmpInst.addOperand(MCOp); 467 // Operand: rt 468 lowerOperand(MI->getOperand(2), MCOp); 469 TmpInst.addOperand(MCOp); 470 EmitToStreamer(OutStreamer, TmpInst); 471 break; 472 } 473 case Mips::PseudoCMP_LT_PH: { 474 MCInst TmpInst; 475 MCOperand MCOp; 476 TmpInst.setOpcode(Mips::CMP_LT_PH); 477 // Operand: rs 478 lowerOperand(MI->getOperand(1), MCOp); 479 TmpInst.addOperand(MCOp); 480 // Operand: rt 481 lowerOperand(MI->getOperand(2), MCOp); 482 TmpInst.addOperand(MCOp); 483 EmitToStreamer(OutStreamer, TmpInst); 484 break; 485 } 486 case Mips::PseudoDMULT: { 487 MCInst TmpInst; 488 MCOperand MCOp; 489 TmpInst.setOpcode(Mips::DMULT); 490 // Operand: rs 491 lowerOperand(MI->getOperand(1), MCOp); 492 TmpInst.addOperand(MCOp); 493 // Operand: rt 494 lowerOperand(MI->getOperand(2), MCOp); 495 TmpInst.addOperand(MCOp); 496 EmitToStreamer(OutStreamer, TmpInst); 497 break; 498 } 499 case Mips::PseudoDMULTu: { 500 MCInst TmpInst; 501 MCOperand MCOp; 502 TmpInst.setOpcode(Mips::DMULTu); 503 // Operand: rs 504 lowerOperand(MI->getOperand(1), MCOp); 505 TmpInst.addOperand(MCOp); 506 // Operand: rt 507 lowerOperand(MI->getOperand(2), MCOp); 508 TmpInst.addOperand(MCOp); 509 EmitToStreamer(OutStreamer, TmpInst); 510 break; 511 } 512 case Mips::PseudoDSDIV: { 513 MCInst TmpInst; 514 MCOperand MCOp; 515 TmpInst.setOpcode(Mips::DSDIV); 516 // Operand: rs 517 lowerOperand(MI->getOperand(1), MCOp); 518 TmpInst.addOperand(MCOp); 519 // Operand: rt 520 lowerOperand(MI->getOperand(2), MCOp); 521 TmpInst.addOperand(MCOp); 522 EmitToStreamer(OutStreamer, TmpInst); 523 break; 524 } 525 case Mips::PseudoDUDIV: { 526 MCInst TmpInst; 527 MCOperand MCOp; 528 TmpInst.setOpcode(Mips::DUDIV); 529 // Operand: rs 530 lowerOperand(MI->getOperand(1), MCOp); 531 TmpInst.addOperand(MCOp); 532 // Operand: rt 533 lowerOperand(MI->getOperand(2), MCOp); 534 TmpInst.addOperand(MCOp); 535 EmitToStreamer(OutStreamer, TmpInst); 536 break; 537 } 538 case Mips::PseudoIndirectBranch: { 539 MCInst TmpInst; 540 MCOperand MCOp; 541 TmpInst.setOpcode(Mips::JR); 542 // Operand: rs 543 lowerOperand(MI->getOperand(0), MCOp); 544 TmpInst.addOperand(MCOp); 545 EmitToStreamer(OutStreamer, TmpInst); 546 break; 547 } 548 case Mips::PseudoIndirectBranch64: { 549 MCInst TmpInst; 550 MCOperand MCOp; 551 TmpInst.setOpcode(Mips::JR64); 552 // Operand: rs 553 lowerOperand(MI->getOperand(0), MCOp); 554 TmpInst.addOperand(MCOp); 555 EmitToStreamer(OutStreamer, TmpInst); 556 break; 557 } 558 case Mips::PseudoIndirectBranch64R6: { 559 MCInst TmpInst; 560 MCOperand MCOp; 561 TmpInst.setOpcode(Mips::JALR64); 562 // Operand: rd 563 TmpInst.addOperand(MCOperand::createReg(Mips::ZERO_64)); 564 // Operand: rs 565 lowerOperand(MI->getOperand(0), MCOp); 566 TmpInst.addOperand(MCOp); 567 EmitToStreamer(OutStreamer, TmpInst); 568 break; 569 } 570 case Mips::PseudoIndirectBranchR6: { 571 MCInst TmpInst; 572 MCOperand MCOp; 573 TmpInst.setOpcode(Mips::JALR); 574 // Operand: rd 575 TmpInst.addOperand(MCOperand::createReg(Mips::ZERO)); 576 // Operand: rs 577 lowerOperand(MI->getOperand(0), MCOp); 578 TmpInst.addOperand(MCOp); 579 EmitToStreamer(OutStreamer, TmpInst); 580 break; 581 } 582 case Mips::PseudoIndirectBranch_MM: { 583 MCInst TmpInst; 584 MCOperand MCOp; 585 TmpInst.setOpcode(Mips::JR_MM); 586 // Operand: rs 587 lowerOperand(MI->getOperand(0), MCOp); 588 TmpInst.addOperand(MCOp); 589 EmitToStreamer(OutStreamer, TmpInst); 590 break; 591 } 592 case Mips::PseudoIndirectBranch_MMR6: { 593 MCInst TmpInst; 594 MCOperand MCOp; 595 TmpInst.setOpcode(Mips::JRC16_MMR6); 596 // Operand: rs 597 lowerOperand(MI->getOperand(0), MCOp); 598 TmpInst.addOperand(MCOp); 599 EmitToStreamer(OutStreamer, TmpInst); 600 break; 601 } 602 case Mips::PseudoIndirectHazardBranch: { 603 MCInst TmpInst; 604 MCOperand MCOp; 605 TmpInst.setOpcode(Mips::JR_HB); 606 // Operand: rs 607 lowerOperand(MI->getOperand(0), MCOp); 608 TmpInst.addOperand(MCOp); 609 EmitToStreamer(OutStreamer, TmpInst); 610 break; 611 } 612 case Mips::PseudoIndirectHazardBranch64: { 613 MCInst TmpInst; 614 MCOperand MCOp; 615 TmpInst.setOpcode(Mips::JR_HB64); 616 // Operand: rs 617 lowerOperand(MI->getOperand(0), MCOp); 618 TmpInst.addOperand(MCOp); 619 EmitToStreamer(OutStreamer, TmpInst); 620 break; 621 } 622 case Mips::PseudoIndrectHazardBranch64R6: { 623 MCInst TmpInst; 624 MCOperand MCOp; 625 TmpInst.setOpcode(Mips::JR_HB64_R6); 626 // Operand: rs 627 lowerOperand(MI->getOperand(0), MCOp); 628 TmpInst.addOperand(MCOp); 629 EmitToStreamer(OutStreamer, TmpInst); 630 break; 631 } 632 case Mips::PseudoIndrectHazardBranchR6: { 633 MCInst TmpInst; 634 MCOperand MCOp; 635 TmpInst.setOpcode(Mips::JR_HB_R6); 636 // Operand: rs 637 lowerOperand(MI->getOperand(0), MCOp); 638 TmpInst.addOperand(MCOp); 639 EmitToStreamer(OutStreamer, TmpInst); 640 break; 641 } 642 case Mips::PseudoMADD: { 643 MCInst TmpInst; 644 MCOperand MCOp; 645 TmpInst.setOpcode(Mips::MADD); 646 // Operand: rs 647 lowerOperand(MI->getOperand(1), MCOp); 648 TmpInst.addOperand(MCOp); 649 // Operand: rt 650 lowerOperand(MI->getOperand(2), MCOp); 651 TmpInst.addOperand(MCOp); 652 EmitToStreamer(OutStreamer, TmpInst); 653 break; 654 } 655 case Mips::PseudoMADDU: { 656 MCInst TmpInst; 657 MCOperand MCOp; 658 TmpInst.setOpcode(Mips::MADDU); 659 // Operand: rs 660 lowerOperand(MI->getOperand(1), MCOp); 661 TmpInst.addOperand(MCOp); 662 // Operand: rt 663 lowerOperand(MI->getOperand(2), MCOp); 664 TmpInst.addOperand(MCOp); 665 EmitToStreamer(OutStreamer, TmpInst); 666 break; 667 } 668 case Mips::PseudoMADDU_MM: { 669 MCInst TmpInst; 670 MCOperand MCOp; 671 TmpInst.setOpcode(Mips::MADDU); 672 // Operand: rs 673 lowerOperand(MI->getOperand(1), MCOp); 674 TmpInst.addOperand(MCOp); 675 // Operand: rt 676 lowerOperand(MI->getOperand(2), MCOp); 677 TmpInst.addOperand(MCOp); 678 EmitToStreamer(OutStreamer, TmpInst); 679 break; 680 } 681 case Mips::PseudoMADD_MM: { 682 MCInst TmpInst; 683 MCOperand MCOp; 684 TmpInst.setOpcode(Mips::MADD); 685 // Operand: rs 686 lowerOperand(MI->getOperand(1), MCOp); 687 TmpInst.addOperand(MCOp); 688 // Operand: rt 689 lowerOperand(MI->getOperand(2), MCOp); 690 TmpInst.addOperand(MCOp); 691 EmitToStreamer(OutStreamer, TmpInst); 692 break; 693 } 694 case Mips::PseudoMSUB: { 695 MCInst TmpInst; 696 MCOperand MCOp; 697 TmpInst.setOpcode(Mips::MSUB); 698 // Operand: rs 699 lowerOperand(MI->getOperand(1), MCOp); 700 TmpInst.addOperand(MCOp); 701 // Operand: rt 702 lowerOperand(MI->getOperand(2), MCOp); 703 TmpInst.addOperand(MCOp); 704 EmitToStreamer(OutStreamer, TmpInst); 705 break; 706 } 707 case Mips::PseudoMSUBU: { 708 MCInst TmpInst; 709 MCOperand MCOp; 710 TmpInst.setOpcode(Mips::MSUBU); 711 // Operand: rs 712 lowerOperand(MI->getOperand(1), MCOp); 713 TmpInst.addOperand(MCOp); 714 // Operand: rt 715 lowerOperand(MI->getOperand(2), MCOp); 716 TmpInst.addOperand(MCOp); 717 EmitToStreamer(OutStreamer, TmpInst); 718 break; 719 } 720 case Mips::PseudoMSUBU_MM: { 721 MCInst TmpInst; 722 MCOperand MCOp; 723 TmpInst.setOpcode(Mips::MSUBU); 724 // Operand: rs 725 lowerOperand(MI->getOperand(1), MCOp); 726 TmpInst.addOperand(MCOp); 727 // Operand: rt 728 lowerOperand(MI->getOperand(2), MCOp); 729 TmpInst.addOperand(MCOp); 730 EmitToStreamer(OutStreamer, TmpInst); 731 break; 732 } 733 case Mips::PseudoMSUB_MM: { 734 MCInst TmpInst; 735 MCOperand MCOp; 736 TmpInst.setOpcode(Mips::MSUB); 737 // Operand: rs 738 lowerOperand(MI->getOperand(1), MCOp); 739 TmpInst.addOperand(MCOp); 740 // Operand: rt 741 lowerOperand(MI->getOperand(2), MCOp); 742 TmpInst.addOperand(MCOp); 743 EmitToStreamer(OutStreamer, TmpInst); 744 break; 745 } 746 case Mips::PseudoMULT: { 747 MCInst TmpInst; 748 MCOperand MCOp; 749 TmpInst.setOpcode(Mips::MULT); 750 // Operand: rs 751 lowerOperand(MI->getOperand(1), MCOp); 752 TmpInst.addOperand(MCOp); 753 // Operand: rt 754 lowerOperand(MI->getOperand(2), MCOp); 755 TmpInst.addOperand(MCOp); 756 EmitToStreamer(OutStreamer, TmpInst); 757 break; 758 } 759 case Mips::PseudoMULT_MM: { 760 MCInst TmpInst; 761 MCOperand MCOp; 762 TmpInst.setOpcode(Mips::MULT); 763 // Operand: rs 764 lowerOperand(MI->getOperand(1), MCOp); 765 TmpInst.addOperand(MCOp); 766 // Operand: rt 767 lowerOperand(MI->getOperand(2), MCOp); 768 TmpInst.addOperand(MCOp); 769 EmitToStreamer(OutStreamer, TmpInst); 770 break; 771 } 772 case Mips::PseudoMULTu: { 773 MCInst TmpInst; 774 MCOperand MCOp; 775 TmpInst.setOpcode(Mips::MULTu); 776 // Operand: rs 777 lowerOperand(MI->getOperand(1), MCOp); 778 TmpInst.addOperand(MCOp); 779 // Operand: rt 780 lowerOperand(MI->getOperand(2), MCOp); 781 TmpInst.addOperand(MCOp); 782 EmitToStreamer(OutStreamer, TmpInst); 783 break; 784 } 785 case Mips::PseudoMULTu_MM: { 786 MCInst TmpInst; 787 MCOperand MCOp; 788 TmpInst.setOpcode(Mips::MULTu); 789 // Operand: rs 790 lowerOperand(MI->getOperand(1), MCOp); 791 TmpInst.addOperand(MCOp); 792 // Operand: rt 793 lowerOperand(MI->getOperand(2), MCOp); 794 TmpInst.addOperand(MCOp); 795 EmitToStreamer(OutStreamer, TmpInst); 796 break; 797 } 798 case Mips::PseudoPICK_PH: { 799 MCInst TmpInst; 800 MCOperand MCOp; 801 TmpInst.setOpcode(Mips::PICK_PH); 802 // Operand: rd 803 lowerOperand(MI->getOperand(0), MCOp); 804 TmpInst.addOperand(MCOp); 805 // Operand: rs 806 lowerOperand(MI->getOperand(2), MCOp); 807 TmpInst.addOperand(MCOp); 808 // Operand: rt 809 lowerOperand(MI->getOperand(3), MCOp); 810 TmpInst.addOperand(MCOp); 811 EmitToStreamer(OutStreamer, TmpInst); 812 break; 813 } 814 case Mips::PseudoPICK_QB: { 815 MCInst TmpInst; 816 MCOperand MCOp; 817 TmpInst.setOpcode(Mips::PICK_QB); 818 // Operand: rd 819 lowerOperand(MI->getOperand(0), MCOp); 820 TmpInst.addOperand(MCOp); 821 // Operand: rs 822 lowerOperand(MI->getOperand(2), MCOp); 823 TmpInst.addOperand(MCOp); 824 // Operand: rt 825 lowerOperand(MI->getOperand(3), MCOp); 826 TmpInst.addOperand(MCOp); 827 EmitToStreamer(OutStreamer, TmpInst); 828 break; 829 } 830 case Mips::PseudoSDIV: { 831 MCInst TmpInst; 832 MCOperand MCOp; 833 TmpInst.setOpcode(Mips::SDIV); 834 // Operand: rs 835 lowerOperand(MI->getOperand(1), MCOp); 836 TmpInst.addOperand(MCOp); 837 // Operand: rt 838 lowerOperand(MI->getOperand(2), MCOp); 839 TmpInst.addOperand(MCOp); 840 EmitToStreamer(OutStreamer, TmpInst); 841 break; 842 } 843 case Mips::PseudoUDIV: { 844 MCInst TmpInst; 845 MCOperand MCOp; 846 TmpInst.setOpcode(Mips::UDIV); 847 // Operand: rs 848 lowerOperand(MI->getOperand(1), MCOp); 849 TmpInst.addOperand(MCOp); 850 // Operand: rt 851 lowerOperand(MI->getOperand(2), MCOp); 852 TmpInst.addOperand(MCOp); 853 EmitToStreamer(OutStreamer, TmpInst); 854 break; 855 } 856 case Mips::SDIV_MM_Pseudo: { 857 MCInst TmpInst; 858 MCOperand MCOp; 859 TmpInst.setOpcode(Mips::SDIV_MM); 860 // Operand: rs 861 lowerOperand(MI->getOperand(1), MCOp); 862 TmpInst.addOperand(MCOp); 863 // Operand: rt 864 lowerOperand(MI->getOperand(2), MCOp); 865 TmpInst.addOperand(MCOp); 866 EmitToStreamer(OutStreamer, TmpInst); 867 break; 868 } 869 case Mips::TAILCALL: { 870 MCInst TmpInst; 871 MCOperand MCOp; 872 TmpInst.setOpcode(Mips::J); 873 // Operand: target 874 lowerOperand(MI->getOperand(0), MCOp); 875 TmpInst.addOperand(MCOp); 876 EmitToStreamer(OutStreamer, TmpInst); 877 break; 878 } 879 case Mips::TAILCALL64R6REG: { 880 MCInst TmpInst; 881 MCOperand MCOp; 882 TmpInst.setOpcode(Mips::JALR64); 883 // Operand: rd 884 TmpInst.addOperand(MCOperand::createReg(Mips::ZERO_64)); 885 // Operand: rs 886 lowerOperand(MI->getOperand(0), MCOp); 887 TmpInst.addOperand(MCOp); 888 EmitToStreamer(OutStreamer, TmpInst); 889 break; 890 } 891 case Mips::TAILCALLHB64R6REG: { 892 MCInst TmpInst; 893 MCOperand MCOp; 894 TmpInst.setOpcode(Mips::JR_HB64_R6); 895 // Operand: rs 896 lowerOperand(MI->getOperand(0), MCOp); 897 TmpInst.addOperand(MCOp); 898 EmitToStreamer(OutStreamer, TmpInst); 899 break; 900 } 901 case Mips::TAILCALLHBR6REG: { 902 MCInst TmpInst; 903 MCOperand MCOp; 904 TmpInst.setOpcode(Mips::JR_HB_R6); 905 // Operand: rs 906 lowerOperand(MI->getOperand(0), MCOp); 907 TmpInst.addOperand(MCOp); 908 EmitToStreamer(OutStreamer, TmpInst); 909 break; 910 } 911 case Mips::TAILCALLR6REG: { 912 MCInst TmpInst; 913 MCOperand MCOp; 914 TmpInst.setOpcode(Mips::JALR); 915 // Operand: rd 916 TmpInst.addOperand(MCOperand::createReg(Mips::ZERO)); 917 // Operand: rs 918 lowerOperand(MI->getOperand(0), MCOp); 919 TmpInst.addOperand(MCOp); 920 EmitToStreamer(OutStreamer, TmpInst); 921 break; 922 } 923 case Mips::TAILCALLREG: { 924 MCInst TmpInst; 925 MCOperand MCOp; 926 TmpInst.setOpcode(Mips::JR); 927 // Operand: rs 928 lowerOperand(MI->getOperand(0), MCOp); 929 TmpInst.addOperand(MCOp); 930 EmitToStreamer(OutStreamer, TmpInst); 931 break; 932 } 933 case Mips::TAILCALLREG64: { 934 MCInst TmpInst; 935 MCOperand MCOp; 936 TmpInst.setOpcode(Mips::JR64); 937 // Operand: rs 938 lowerOperand(MI->getOperand(0), MCOp); 939 TmpInst.addOperand(MCOp); 940 EmitToStreamer(OutStreamer, TmpInst); 941 break; 942 } 943 case Mips::TAILCALLREGHB: { 944 MCInst TmpInst; 945 MCOperand MCOp; 946 TmpInst.setOpcode(Mips::JR_HB); 947 // Operand: rs 948 lowerOperand(MI->getOperand(0), MCOp); 949 TmpInst.addOperand(MCOp); 950 EmitToStreamer(OutStreamer, TmpInst); 951 break; 952 } 953 case Mips::TAILCALLREGHB64: { 954 MCInst TmpInst; 955 MCOperand MCOp; 956 TmpInst.setOpcode(Mips::JR_HB64); 957 // Operand: rs 958 lowerOperand(MI->getOperand(0), MCOp); 959 TmpInst.addOperand(MCOp); 960 EmitToStreamer(OutStreamer, TmpInst); 961 break; 962 } 963 case Mips::TAILCALLREG_MM: { 964 MCInst TmpInst; 965 MCOperand MCOp; 966 TmpInst.setOpcode(Mips::JRC16_MM); 967 // Operand: rs 968 lowerOperand(MI->getOperand(0), MCOp); 969 TmpInst.addOperand(MCOp); 970 EmitToStreamer(OutStreamer, TmpInst); 971 break; 972 } 973 case Mips::TAILCALLREG_MMR6: { 974 MCInst TmpInst; 975 MCOperand MCOp; 976 TmpInst.setOpcode(Mips::JRC16_MM); 977 // Operand: rs 978 lowerOperand(MI->getOperand(0), MCOp); 979 TmpInst.addOperand(MCOp); 980 EmitToStreamer(OutStreamer, TmpInst); 981 break; 982 } 983 case Mips::TAILCALL_MM: { 984 MCInst TmpInst; 985 MCOperand MCOp; 986 TmpInst.setOpcode(Mips::J_MM); 987 // Operand: target 988 lowerOperand(MI->getOperand(0), MCOp); 989 TmpInst.addOperand(MCOp); 990 EmitToStreamer(OutStreamer, TmpInst); 991 break; 992 } 993 case Mips::TAILCALL_MMR6: { 994 MCInst TmpInst; 995 MCOperand MCOp; 996 TmpInst.setOpcode(Mips::BC_MMR6); 997 // Operand: offset 998 lowerOperand(MI->getOperand(0), MCOp); 999 TmpInst.addOperand(MCOp); 1000 EmitToStreamer(OutStreamer, TmpInst); 1001 break; 1002 } 1003 case Mips::TRAP: { 1004 MCInst TmpInst; 1005 MCOperand MCOp; 1006 TmpInst.setOpcode(Mips::BREAK); 1007 // Operand: code_1 1008 TmpInst.addOperand(MCOperand::createImm(0)); 1009 // Operand: code_2 1010 TmpInst.addOperand(MCOperand::createImm(0)); 1011 EmitToStreamer(OutStreamer, TmpInst); 1012 break; 1013 } 1014 case Mips::TRAP_MM: { 1015 MCInst TmpInst; 1016 MCOperand MCOp; 1017 TmpInst.setOpcode(Mips::BREAK_MM); 1018 // Operand: code_1 1019 TmpInst.addOperand(MCOperand::createImm(0)); 1020 // Operand: code_2 1021 TmpInst.addOperand(MCOperand::createImm(0)); 1022 EmitToStreamer(OutStreamer, TmpInst); 1023 break; 1024 } 1025 case Mips::UDIV_MM_Pseudo: { 1026 MCInst TmpInst; 1027 MCOperand MCOp; 1028 TmpInst.setOpcode(Mips::UDIV_MM); 1029 // Operand: rs 1030 lowerOperand(MI->getOperand(1), MCOp); 1031 TmpInst.addOperand(MCOp); 1032 // Operand: rt 1033 lowerOperand(MI->getOperand(2), MCOp); 1034 TmpInst.addOperand(MCOp); 1035 EmitToStreamer(OutStreamer, TmpInst); 1036 break; 1037 } 1038 case Mips::XOR_V_D_PSEUDO: { 1039 MCInst TmpInst; 1040 MCOperand MCOp; 1041 TmpInst.setOpcode(Mips::XOR_V); 1042 // Operand: wd 1043 lowerOperand(MI->getOperand(0), MCOp); 1044 TmpInst.addOperand(MCOp); 1045 // Operand: ws 1046 lowerOperand(MI->getOperand(1), MCOp); 1047 TmpInst.addOperand(MCOp); 1048 // Operand: wt 1049 lowerOperand(MI->getOperand(2), MCOp); 1050 TmpInst.addOperand(MCOp); 1051 EmitToStreamer(OutStreamer, TmpInst); 1052 break; 1053 } 1054 case Mips::XOR_V_H_PSEUDO: { 1055 MCInst TmpInst; 1056 MCOperand MCOp; 1057 TmpInst.setOpcode(Mips::XOR_V); 1058 // Operand: wd 1059 lowerOperand(MI->getOperand(0), MCOp); 1060 TmpInst.addOperand(MCOp); 1061 // Operand: ws 1062 lowerOperand(MI->getOperand(1), MCOp); 1063 TmpInst.addOperand(MCOp); 1064 // Operand: wt 1065 lowerOperand(MI->getOperand(2), MCOp); 1066 TmpInst.addOperand(MCOp); 1067 EmitToStreamer(OutStreamer, TmpInst); 1068 break; 1069 } 1070 case Mips::XOR_V_W_PSEUDO: { 1071 MCInst TmpInst; 1072 MCOperand MCOp; 1073 TmpInst.setOpcode(Mips::XOR_V); 1074 // Operand: wd 1075 lowerOperand(MI->getOperand(0), MCOp); 1076 TmpInst.addOperand(MCOp); 1077 // Operand: ws 1078 lowerOperand(MI->getOperand(1), MCOp); 1079 TmpInst.addOperand(MCOp); 1080 // Operand: wt 1081 lowerOperand(MI->getOperand(2), MCOp); 1082 TmpInst.addOperand(MCOp); 1083 EmitToStreamer(OutStreamer, TmpInst); 1084 break; 1085 } 1086 } 1087 return true; 1088} 1089 1090