1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2|* *| 3|* Register Bank Source Fragments *| 4|* *| 5|* Automatically generated file, do not edit! *| 6|* *| 7\*===----------------------------------------------------------------------===*/ 8 9#ifdef GET_REGBANK_DECLARATIONS 10#undef GET_REGBANK_DECLARATIONS 11namespace llvm { 12namespace Mips { 13enum : unsigned { 14 InvalidRegBankID = ~0u, 15 FPRBRegBankID = 0, 16 GPRBRegBankID = 1, 17 NumRegisterBanks, 18}; 19} // end namespace Mips 20} // end namespace llvm 21#endif // GET_REGBANK_DECLARATIONS 22 23#ifdef GET_TARGET_REGBANK_CLASS 24#undef GET_TARGET_REGBANK_CLASS 25private: 26 static RegisterBank *RegBanks[]; 27 28protected: 29 MipsGenRegisterBankInfo(); 30 31#endif // GET_TARGET_REGBANK_CLASS 32 33#ifdef GET_TARGET_REGBANK_IMPL 34#undef GET_TARGET_REGBANK_IMPL 35namespace llvm { 36namespace Mips { 37const uint32_t FPRBRegBankCoverageData[] = { 38 // 0-31 39 (1u << (Mips::FGR32RegClassID - 0)) | 40 (1u << (Mips::FGRCCRegClassID - 0)) | 41 0, 42 // 32-63 43 (1u << (Mips::FGR64RegClassID - 32)) | 44 (1u << (Mips::AFGR64RegClassID - 32)) | 45 0, 46 // 64-95 47 (1u << (Mips::MSA128DRegClassID - 64)) | 48 (1u << (Mips::MSA128BRegClassID - 64)) | 49 (1u << (Mips::MSA128HRegClassID - 64)) | 50 (1u << (Mips::MSA128WRegClassID - 64)) | 51 (1u << (Mips::MSA128WEvensRegClassID - 64)) | 52 0, 53}; 54const uint32_t GPRBRegBankCoverageData[] = { 55 // 0-31 56 (1u << (Mips::GPR32RegClassID - 0)) | 57 (1u << (Mips::GPR32NONZERORegClassID - 0)) | 58 (1u << (Mips::CPU16RegsPlusSPRegClassID - 0)) | 59 (1u << (Mips::CPU16RegsRegClassID - 0)) | 60 (1u << (Mips::GPRMM16RegClassID - 0)) | 61 (1u << (Mips::CPU16Regs_and_GPRMM16ZeroRegClassID - 0)) | 62 (1u << (Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClassID - 0)) | 63 (1u << (Mips::GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID - 0)) | 64 (1u << (Mips::GPRMM16MovePPairFirstRegClassID - 0)) | 65 (1u << (Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID - 0)) | 66 (1u << (Mips::CPU16Regs_and_GPRMM16MovePRegClassID - 0)) | 67 (1u << (Mips::CPUSPRegRegClassID - 0)) | 68 (1u << (Mips::GPR32NONZERO_and_GPRMM16MovePRegClassID - 0)) | 69 (1u << (Mips::GPRMM16MovePPairSecondRegClassID - 0)) | 70 (1u << (Mips::CPURARegRegClassID - 0)) | 71 (1u << (Mips::GPRMM16MovePRegClassID - 0)) | 72 (1u << (Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClassID - 0)) | 73 (1u << (Mips::GPRMM16ZeroRegClassID - 0)) | 74 0, 75 // 32-63 76 (1u << (Mips::SP32RegClassID - 32)) | 77 (1u << (Mips::GP32RegClassID - 32)) | 78 (1u << (Mips::GPR32ZERORegClassID - 32)) | 79 0, 80 // 64-95 81 0, 82}; 83 84RegisterBank FPRBRegBank(/* ID */ Mips::FPRBRegBankID, /* Name */ "FPRB", /* Size */ 128, /* CoveredRegClasses */ FPRBRegBankCoverageData, /* NumRegClasses */ 70); 85RegisterBank GPRBRegBank(/* ID */ Mips::GPRBRegBankID, /* Name */ "GPRB", /* Size */ 32, /* CoveredRegClasses */ GPRBRegBankCoverageData, /* NumRegClasses */ 70); 86} // end namespace Mips 87 88RegisterBank *MipsGenRegisterBankInfo::RegBanks[] = { 89 &Mips::FPRBRegBank, 90 &Mips::GPRBRegBank, 91}; 92 93MipsGenRegisterBankInfo::MipsGenRegisterBankInfo() 94 : RegisterBankInfo(RegBanks, Mips::NumRegisterBanks) { 95 // Assert that RegBank indices match their ID's 96#ifndef NDEBUG 97 for (auto RB : enumerate(RegBanks)) 98 assert(RB.index() == RB.value()->getID() && "Index != ID"); 99#endif // NDEBUG 100} 101} // end namespace llvm 102#endif // GET_TARGET_REGBANK_IMPL 103