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1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|*                                                                            *|
3|* Target Register Enum Values                                                *|
4|*                                                                            *|
5|* Automatically generated file, do not edit!                                 *|
6|*                                                                            *|
7\*===----------------------------------------------------------------------===*/
8
9
10#ifdef GET_REGINFO_ENUM
11#undef GET_REGINFO_ENUM
12
13namespace llvm {
14
15class MCRegisterClass;
16extern const MCRegisterClass MipsMCRegisterClasses[];
17
18namespace Mips {
19enum {
20  NoRegister,
21  AT = 1,
22  DSPCCond = 2,
23  DSPCarry = 3,
24  DSPEFI = 4,
25  DSPOutFlag = 5,
26  DSPPos = 6,
27  DSPSCount = 7,
28  FP = 8,
29  GP = 9,
30  MSAAccess = 10,
31  MSACSR = 11,
32  MSAIR = 12,
33  MSAMap = 13,
34  MSAModify = 14,
35  MSARequest = 15,
36  MSASave = 16,
37  MSAUnmap = 17,
38  PC = 18,
39  RA = 19,
40  SP = 20,
41  ZERO = 21,
42  A0 = 22,
43  A1 = 23,
44  A2 = 24,
45  A3 = 25,
46  AC0 = 26,
47  AC1 = 27,
48  AC2 = 28,
49  AC3 = 29,
50  AT_64 = 30,
51  COP00 = 31,
52  COP01 = 32,
53  COP02 = 33,
54  COP03 = 34,
55  COP04 = 35,
56  COP05 = 36,
57  COP06 = 37,
58  COP07 = 38,
59  COP08 = 39,
60  COP09 = 40,
61  COP20 = 41,
62  COP21 = 42,
63  COP22 = 43,
64  COP23 = 44,
65  COP24 = 45,
66  COP25 = 46,
67  COP26 = 47,
68  COP27 = 48,
69  COP28 = 49,
70  COP29 = 50,
71  COP30 = 51,
72  COP31 = 52,
73  COP32 = 53,
74  COP33 = 54,
75  COP34 = 55,
76  COP35 = 56,
77  COP36 = 57,
78  COP37 = 58,
79  COP38 = 59,
80  COP39 = 60,
81  COP010 = 61,
82  COP011 = 62,
83  COP012 = 63,
84  COP013 = 64,
85  COP014 = 65,
86  COP015 = 66,
87  COP016 = 67,
88  COP017 = 68,
89  COP018 = 69,
90  COP019 = 70,
91  COP020 = 71,
92  COP021 = 72,
93  COP022 = 73,
94  COP023 = 74,
95  COP024 = 75,
96  COP025 = 76,
97  COP026 = 77,
98  COP027 = 78,
99  COP028 = 79,
100  COP029 = 80,
101  COP030 = 81,
102  COP031 = 82,
103  COP210 = 83,
104  COP211 = 84,
105  COP212 = 85,
106  COP213 = 86,
107  COP214 = 87,
108  COP215 = 88,
109  COP216 = 89,
110  COP217 = 90,
111  COP218 = 91,
112  COP219 = 92,
113  COP220 = 93,
114  COP221 = 94,
115  COP222 = 95,
116  COP223 = 96,
117  COP224 = 97,
118  COP225 = 98,
119  COP226 = 99,
120  COP227 = 100,
121  COP228 = 101,
122  COP229 = 102,
123  COP230 = 103,
124  COP231 = 104,
125  COP310 = 105,
126  COP311 = 106,
127  COP312 = 107,
128  COP313 = 108,
129  COP314 = 109,
130  COP315 = 110,
131  COP316 = 111,
132  COP317 = 112,
133  COP318 = 113,
134  COP319 = 114,
135  COP320 = 115,
136  COP321 = 116,
137  COP322 = 117,
138  COP323 = 118,
139  COP324 = 119,
140  COP325 = 120,
141  COP326 = 121,
142  COP327 = 122,
143  COP328 = 123,
144  COP329 = 124,
145  COP330 = 125,
146  COP331 = 126,
147  D0 = 127,
148  D1 = 128,
149  D2 = 129,
150  D3 = 130,
151  D4 = 131,
152  D5 = 132,
153  D6 = 133,
154  D7 = 134,
155  D8 = 135,
156  D9 = 136,
157  D10 = 137,
158  D11 = 138,
159  D12 = 139,
160  D13 = 140,
161  D14 = 141,
162  D15 = 142,
163  DSPOutFlag20 = 143,
164  DSPOutFlag21 = 144,
165  DSPOutFlag22 = 145,
166  DSPOutFlag23 = 146,
167  F0 = 147,
168  F1 = 148,
169  F2 = 149,
170  F3 = 150,
171  F4 = 151,
172  F5 = 152,
173  F6 = 153,
174  F7 = 154,
175  F8 = 155,
176  F9 = 156,
177  F10 = 157,
178  F11 = 158,
179  F12 = 159,
180  F13 = 160,
181  F14 = 161,
182  F15 = 162,
183  F16 = 163,
184  F17 = 164,
185  F18 = 165,
186  F19 = 166,
187  F20 = 167,
188  F21 = 168,
189  F22 = 169,
190  F23 = 170,
191  F24 = 171,
192  F25 = 172,
193  F26 = 173,
194  F27 = 174,
195  F28 = 175,
196  F29 = 176,
197  F30 = 177,
198  F31 = 178,
199  FCC0 = 179,
200  FCC1 = 180,
201  FCC2 = 181,
202  FCC3 = 182,
203  FCC4 = 183,
204  FCC5 = 184,
205  FCC6 = 185,
206  FCC7 = 186,
207  FCR0 = 187,
208  FCR1 = 188,
209  FCR2 = 189,
210  FCR3 = 190,
211  FCR4 = 191,
212  FCR5 = 192,
213  FCR6 = 193,
214  FCR7 = 194,
215  FCR8 = 195,
216  FCR9 = 196,
217  FCR10 = 197,
218  FCR11 = 198,
219  FCR12 = 199,
220  FCR13 = 200,
221  FCR14 = 201,
222  FCR15 = 202,
223  FCR16 = 203,
224  FCR17 = 204,
225  FCR18 = 205,
226  FCR19 = 206,
227  FCR20 = 207,
228  FCR21 = 208,
229  FCR22 = 209,
230  FCR23 = 210,
231  FCR24 = 211,
232  FCR25 = 212,
233  FCR26 = 213,
234  FCR27 = 214,
235  FCR28 = 215,
236  FCR29 = 216,
237  FCR30 = 217,
238  FCR31 = 218,
239  FP_64 = 219,
240  F_HI0 = 220,
241  F_HI1 = 221,
242  F_HI2 = 222,
243  F_HI3 = 223,
244  F_HI4 = 224,
245  F_HI5 = 225,
246  F_HI6 = 226,
247  F_HI7 = 227,
248  F_HI8 = 228,
249  F_HI9 = 229,
250  F_HI10 = 230,
251  F_HI11 = 231,
252  F_HI12 = 232,
253  F_HI13 = 233,
254  F_HI14 = 234,
255  F_HI15 = 235,
256  F_HI16 = 236,
257  F_HI17 = 237,
258  F_HI18 = 238,
259  F_HI19 = 239,
260  F_HI20 = 240,
261  F_HI21 = 241,
262  F_HI22 = 242,
263  F_HI23 = 243,
264  F_HI24 = 244,
265  F_HI25 = 245,
266  F_HI26 = 246,
267  F_HI27 = 247,
268  F_HI28 = 248,
269  F_HI29 = 249,
270  F_HI30 = 250,
271  F_HI31 = 251,
272  GP_64 = 252,
273  HI0 = 253,
274  HI1 = 254,
275  HI2 = 255,
276  HI3 = 256,
277  HWR0 = 257,
278  HWR1 = 258,
279  HWR2 = 259,
280  HWR3 = 260,
281  HWR4 = 261,
282  HWR5 = 262,
283  HWR6 = 263,
284  HWR7 = 264,
285  HWR8 = 265,
286  HWR9 = 266,
287  HWR10 = 267,
288  HWR11 = 268,
289  HWR12 = 269,
290  HWR13 = 270,
291  HWR14 = 271,
292  HWR15 = 272,
293  HWR16 = 273,
294  HWR17 = 274,
295  HWR18 = 275,
296  HWR19 = 276,
297  HWR20 = 277,
298  HWR21 = 278,
299  HWR22 = 279,
300  HWR23 = 280,
301  HWR24 = 281,
302  HWR25 = 282,
303  HWR26 = 283,
304  HWR27 = 284,
305  HWR28 = 285,
306  HWR29 = 286,
307  HWR30 = 287,
308  HWR31 = 288,
309  K0 = 289,
310  K1 = 290,
311  LO0 = 291,
312  LO1 = 292,
313  LO2 = 293,
314  LO3 = 294,
315  MPL0 = 295,
316  MPL1 = 296,
317  MPL2 = 297,
318  MSA8 = 298,
319  MSA9 = 299,
320  MSA10 = 300,
321  MSA11 = 301,
322  MSA12 = 302,
323  MSA13 = 303,
324  MSA14 = 304,
325  MSA15 = 305,
326  MSA16 = 306,
327  MSA17 = 307,
328  MSA18 = 308,
329  MSA19 = 309,
330  MSA20 = 310,
331  MSA21 = 311,
332  MSA22 = 312,
333  MSA23 = 313,
334  MSA24 = 314,
335  MSA25 = 315,
336  MSA26 = 316,
337  MSA27 = 317,
338  MSA28 = 318,
339  MSA29 = 319,
340  MSA30 = 320,
341  MSA31 = 321,
342  P0 = 322,
343  P1 = 323,
344  P2 = 324,
345  RA_64 = 325,
346  S0 = 326,
347  S1 = 327,
348  S2 = 328,
349  S3 = 329,
350  S4 = 330,
351  S5 = 331,
352  S6 = 332,
353  S7 = 333,
354  SP_64 = 334,
355  T0 = 335,
356  T1 = 336,
357  T2 = 337,
358  T3 = 338,
359  T4 = 339,
360  T5 = 340,
361  T6 = 341,
362  T7 = 342,
363  T8 = 343,
364  T9 = 344,
365  V0 = 345,
366  V1 = 346,
367  W0 = 347,
368  W1 = 348,
369  W2 = 349,
370  W3 = 350,
371  W4 = 351,
372  W5 = 352,
373  W6 = 353,
374  W7 = 354,
375  W8 = 355,
376  W9 = 356,
377  W10 = 357,
378  W11 = 358,
379  W12 = 359,
380  W13 = 360,
381  W14 = 361,
382  W15 = 362,
383  W16 = 363,
384  W17 = 364,
385  W18 = 365,
386  W19 = 366,
387  W20 = 367,
388  W21 = 368,
389  W22 = 369,
390  W23 = 370,
391  W24 = 371,
392  W25 = 372,
393  W26 = 373,
394  W27 = 374,
395  W28 = 375,
396  W29 = 376,
397  W30 = 377,
398  W31 = 378,
399  ZERO_64 = 379,
400  A0_64 = 380,
401  A1_64 = 381,
402  A2_64 = 382,
403  A3_64 = 383,
404  AC0_64 = 384,
405  D0_64 = 385,
406  D1_64 = 386,
407  D2_64 = 387,
408  D3_64 = 388,
409  D4_64 = 389,
410  D5_64 = 390,
411  D6_64 = 391,
412  D7_64 = 392,
413  D8_64 = 393,
414  D9_64 = 394,
415  D10_64 = 395,
416  D11_64 = 396,
417  D12_64 = 397,
418  D13_64 = 398,
419  D14_64 = 399,
420  D15_64 = 400,
421  D16_64 = 401,
422  D17_64 = 402,
423  D18_64 = 403,
424  D19_64 = 404,
425  D20_64 = 405,
426  D21_64 = 406,
427  D22_64 = 407,
428  D23_64 = 408,
429  D24_64 = 409,
430  D25_64 = 410,
431  D26_64 = 411,
432  D27_64 = 412,
433  D28_64 = 413,
434  D29_64 = 414,
435  D30_64 = 415,
436  D31_64 = 416,
437  DSPOutFlag16_19 = 417,
438  HI0_64 = 418,
439  K0_64 = 419,
440  K1_64 = 420,
441  LO0_64 = 421,
442  S0_64 = 422,
443  S1_64 = 423,
444  S2_64 = 424,
445  S3_64 = 425,
446  S4_64 = 426,
447  S5_64 = 427,
448  S6_64 = 428,
449  S7_64 = 429,
450  T0_64 = 430,
451  T1_64 = 431,
452  T2_64 = 432,
453  T3_64 = 433,
454  T4_64 = 434,
455  T5_64 = 435,
456  T6_64 = 436,
457  T7_64 = 437,
458  T8_64 = 438,
459  T9_64 = 439,
460  V0_64 = 440,
461  V1_64 = 441,
462  NUM_TARGET_REGS // 442
463};
464} // end namespace Mips
465
466// Register classes
467
468namespace Mips {
469enum {
470  MSA128F16RegClassID = 0,
471  CCRRegClassID = 1,
472  COP0RegClassID = 2,
473  COP2RegClassID = 3,
474  COP3RegClassID = 4,
475  DSPRRegClassID = 5,
476  FGR32RegClassID = 6,
477  FGRCCRegClassID = 7,
478  GPR32RegClassID = 8,
479  HWRegsRegClassID = 9,
480  MSACtrlRegClassID = 10,
481  GPR32NONZERORegClassID = 11,
482  CPU16RegsPlusSPRegClassID = 12,
483  CPU16RegsRegClassID = 13,
484  FCCRegClassID = 14,
485  GPRMM16RegClassID = 15,
486  GPRMM16MovePRegClassID = 16,
487  GPRMM16ZeroRegClassID = 17,
488  CPU16Regs_and_GPRMM16ZeroRegClassID = 18,
489  GPR32NONZERO_and_GPRMM16MovePRegClassID = 19,
490  GPRMM16MovePPairSecondRegClassID = 20,
491  CPU16Regs_and_GPRMM16MovePRegClassID = 21,
492  GPRMM16MoveP_and_GPRMM16ZeroRegClassID = 22,
493  HI32DSPRegClassID = 23,
494  LO32DSPRegClassID = 24,
495  CPU16Regs_and_GPRMM16MovePPairSecondRegClassID = 25,
496  GPRMM16MovePPairFirstRegClassID = 26,
497  GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID = 27,
498  GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID = 28,
499  CPURARegRegClassID = 29,
500  CPUSPRegRegClassID = 30,
501  DSPCCRegClassID = 31,
502  GP32RegClassID = 32,
503  GPR32ZERORegClassID = 33,
504  HI32RegClassID = 34,
505  LO32RegClassID = 35,
506  SP32RegClassID = 36,
507  FGR64RegClassID = 37,
508  GPR64RegClassID = 38,
509  GPR64_with_sub_32_in_GPR32NONZERORegClassID = 39,
510  AFGR64RegClassID = 40,
511  GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID = 41,
512  GPR64_with_sub_32_in_CPU16RegsRegClassID = 42,
513  GPR64_with_sub_32_in_GPRMM16MovePRegClassID = 43,
514  GPR64_with_sub_32_in_GPRMM16ZeroRegClassID = 44,
515  GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID = 45,
516  GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID = 46,
517  GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClassID = 47,
518  ACC64DSPRegClassID = 48,
519  GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID = 49,
520  GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID = 50,
521  GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClassID = 51,
522  GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClassID = 52,
523  GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID = 53,
524  OCTEON_MPLRegClassID = 54,
525  OCTEON_PRegClassID = 55,
526  GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID = 56,
527  ACC64RegClassID = 57,
528  GP64RegClassID = 58,
529  GPR64_with_sub_32_in_CPURARegRegClassID = 59,
530  GPR64_with_sub_32_in_GPR32ZERORegClassID = 60,
531  HI64RegClassID = 61,
532  LO64RegClassID = 62,
533  SP64RegClassID = 63,
534  MSA128BRegClassID = 64,
535  MSA128DRegClassID = 65,
536  MSA128HRegClassID = 66,
537  MSA128WRegClassID = 67,
538  MSA128WEvensRegClassID = 68,
539  ACC128RegClassID = 69,
540
541};
542} // end namespace Mips
543
544
545// Subregister indices
546
547namespace Mips {
548enum : uint16_t {
549  NoSubRegister,
550  sub_32,	// 1
551  sub_64,	// 2
552  sub_dsp16_19,	// 3
553  sub_dsp20,	// 4
554  sub_dsp21,	// 5
555  sub_dsp22,	// 6
556  sub_dsp23,	// 7
557  sub_hi,	// 8
558  sub_lo,	// 9
559  sub_hi_then_sub_32,	// 10
560  sub_32_sub_hi_then_sub_32,	// 11
561  NUM_TARGET_SUBREGS
562};
563} // end namespace Mips
564
565// Register pressure sets enum.
566namespace Mips {
567enum RegisterPressureSets {
568  DSPCC = 0,
569  GPR32ZERO = 1,
570  GPR64_with_sub_32_in_CPURAReg = 2,
571  HI32 = 3,
572  GPRMM16MovePPairFirst = 4,
573  CPU16Regs_and_GPRMM16MoveP = 5,
574  HI32DSP = 6,
575  LO32DSP = 7,
576  GPRMM16MovePPairSecond = 8,
577  GPRMM16MoveP = 9,
578  ACC64DSP = 10,
579  CPU16Regs = 11,
580  GPRMM16Zero_with_GPRMM16MovePPairSecond = 12,
581  CPU16Regs_with_GPRMM16MovePPairSecond = 13,
582  CPU16Regs_with_GPRMM16MoveP = 14,
583  DSPR = 15,
584  FGR32 = 16,
585  MSA128WEvens = 17,
586  FGR32_with_MSA128WEvens = 18,
587  MSA128F16 = 19,
588};
589} // end namespace Mips
590
591} // end namespace llvm
592
593#endif // GET_REGINFO_ENUM
594
595/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
596|*                                                                            *|
597|* MC Register Information                                                    *|
598|*                                                                            *|
599|* Automatically generated file, do not edit!                                 *|
600|*                                                                            *|
601\*===----------------------------------------------------------------------===*/
602
603
604#ifdef GET_REGINFO_MC_DESC
605#undef GET_REGINFO_MC_DESC
606
607namespace llvm {
608
609extern const MCPhysReg MipsRegDiffLists[] = {
610  /* 0 */ 0, 0,
611  /* 2 */ 4, 1, 1, 1, 1, 0,
612  /* 8 */ 412, 65262, 1, 1, 1, 0,
613  /* 14 */ 20, 1, 0,
614  /* 17 */ 21, 1, 0,
615  /* 20 */ 22, 1, 0,
616  /* 23 */ 23, 1, 0,
617  /* 26 */ 24, 1, 0,
618  /* 29 */ 25, 1, 0,
619  /* 32 */ 26, 1, 0,
620  /* 35 */ 27, 1, 0,
621  /* 38 */ 28, 1, 0,
622  /* 41 */ 29, 1, 0,
623  /* 44 */ 30, 1, 0,
624  /* 47 */ 31, 1, 0,
625  /* 50 */ 32, 1, 0,
626  /* 53 */ 33, 1, 0,
627  /* 56 */ 34, 1, 0,
628  /* 59 */ 35, 1, 0,
629  /* 62 */ 65415, 1, 0,
630  /* 65 */ 65513, 1, 0,
631  /* 68 */ 3, 0,
632  /* 70 */ 4, 0,
633  /* 72 */ 6, 0,
634  /* 74 */ 11, 0,
635  /* 76 */ 12, 0,
636  /* 78 */ 22, 0,
637  /* 80 */ 23, 0,
638  /* 82 */ 29, 0,
639  /* 84 */ 30, 0,
640  /* 86 */ 65284, 72, 0,
641  /* 89 */ 65322, 72, 0,
642  /* 92 */ 38, 65298, 73, 0,
643  /* 96 */ 95, 0,
644  /* 98 */ 96, 0,
645  /* 100 */ 130, 0,
646  /* 102 */ 211, 0,
647  /* 104 */ 243, 0,
648  /* 106 */ 306, 0,
649  /* 108 */ 314, 0,
650  /* 110 */ 358, 0,
651  /* 112 */ 64983, 0,
652  /* 114 */ 65060, 0,
653  /* 116 */ 65124, 0,
654  /* 118 */ 65178, 0,
655  /* 120 */ 65181, 0,
656  /* 122 */ 65222, 0,
657  /* 124 */ 65230, 0,
658  /* 126 */ 65271, 0,
659  /* 128 */ 65293, 0,
660  /* 130 */ 37, 65406, 127, 65371, 65309, 0,
661  /* 136 */ 65325, 0,
662  /* 138 */ 65371, 0,
663  /* 140 */ 65386, 0,
664  /* 142 */ 65395, 0,
665  /* 144 */ 65396, 0,
666  /* 146 */ 65397, 0,
667  /* 148 */ 65398, 0,
668  /* 150 */ 65406, 0,
669  /* 152 */ 65415, 0,
670  /* 154 */ 65440, 0,
671  /* 156 */ 65441, 0,
672  /* 158 */ 165, 65498, 0,
673  /* 161 */ 65516, 258, 65498, 0,
674  /* 165 */ 65515, 259, 65498, 0,
675  /* 169 */ 65514, 260, 65498, 0,
676  /* 173 */ 65513, 261, 65498, 0,
677  /* 177 */ 65512, 262, 65498, 0,
678  /* 181 */ 65511, 263, 65498, 0,
679  /* 185 */ 65510, 264, 65498, 0,
680  /* 189 */ 65509, 265, 65498, 0,
681  /* 193 */ 65508, 266, 65498, 0,
682  /* 197 */ 65507, 267, 65498, 0,
683  /* 201 */ 65506, 268, 65498, 0,
684  /* 205 */ 65505, 269, 65498, 0,
685  /* 209 */ 65504, 270, 65498, 0,
686  /* 213 */ 65503, 271, 65498, 0,
687  /* 217 */ 65502, 272, 65498, 0,
688  /* 221 */ 65501, 273, 65498, 0,
689  /* 225 */ 65500, 274, 65498, 0,
690  /* 229 */ 65271, 395, 65499, 0,
691  /* 233 */ 65309, 392, 65502, 0,
692  /* 237 */ 65507, 0,
693  /* 239 */ 65510, 0,
694  /* 241 */ 65511, 0,
695  /* 243 */ 65512, 0,
696  /* 245 */ 65516, 0,
697  /* 247 */ 65521, 0,
698  /* 249 */ 65522, 0,
699  /* 251 */ 65535, 0,
700};
701
702extern const LaneBitmask MipsLaneMaskLists[] = {
703  /* 0 */ LaneBitmask(0x0000000000000000), LaneBitmask::getAll(),
704  /* 2 */ LaneBitmask(0x0000000000000001), LaneBitmask::getAll(),
705  /* 4 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask::getAll(),
706  /* 10 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000040), LaneBitmask::getAll(),
707};
708
709extern const uint16_t MipsSubRegIdxLists[] = {
710  /* 0 */ 1, 0,
711  /* 2 */ 3, 4, 5, 6, 7, 0,
712  /* 8 */ 2, 9, 8, 0,
713  /* 12 */ 9, 1, 8, 10, 11, 0,
714};
715
716extern const MCRegisterInfo::SubRegCoveredBits MipsSubRegIdxRanges[] = {
717  { 65535, 65535 },
718  { 0, 32 },	// sub_32
719  { 0, 64 },	// sub_64
720  { 16, 4 },	// sub_dsp16_19
721  { 20, 1 },	// sub_dsp20
722  { 21, 1 },	// sub_dsp21
723  { 22, 1 },	// sub_dsp22
724  { 23, 1 },	// sub_dsp23
725  { 32, 32 },	// sub_hi
726  { 0, 32 },	// sub_lo
727  { 32, 32 },	// sub_hi_then_sub_32
728  { 0, 64 },	// sub_32_sub_hi_then_sub_32
729};
730
731extern const char MipsRegStrings[] = {
732  /* 0 */ 'C', 'O', 'P', '0', '0', 0,
733  /* 6 */ 'C', 'O', 'P', '0', '1', '0', 0,
734  /* 13 */ 'C', 'O', 'P', '2', '1', '0', 0,
735  /* 20 */ 'C', 'O', 'P', '3', '1', '0', 0,
736  /* 27 */ 'M', 'S', 'A', '1', '0', 0,
737  /* 33 */ 'D', '1', '0', 0,
738  /* 37 */ 'F', '1', '0', 0,
739  /* 41 */ 'F', '_', 'H', 'I', '1', '0', 0,
740  /* 48 */ 'F', 'C', 'R', '1', '0', 0,
741  /* 54 */ 'H', 'W', 'R', '1', '0', 0,
742  /* 60 */ 'W', '1', '0', 0,
743  /* 64 */ 'C', 'O', 'P', '0', '2', '0', 0,
744  /* 71 */ 'C', 'O', 'P', '2', '2', '0', 0,
745  /* 78 */ 'C', 'O', 'P', '3', '2', '0', 0,
746  /* 85 */ 'M', 'S', 'A', '2', '0', 0,
747  /* 91 */ 'F', '2', '0', 0,
748  /* 95 */ 'F', '_', 'H', 'I', '2', '0', 0,
749  /* 102 */ 'C', 'O', 'P', '2', '0', 0,
750  /* 108 */ 'F', 'C', 'R', '2', '0', 0,
751  /* 114 */ 'H', 'W', 'R', '2', '0', 0,
752  /* 120 */ 'W', '2', '0', 0,
753  /* 124 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '0', 0,
754  /* 137 */ 'C', 'O', 'P', '0', '3', '0', 0,
755  /* 144 */ 'C', 'O', 'P', '2', '3', '0', 0,
756  /* 151 */ 'C', 'O', 'P', '3', '3', '0', 0,
757  /* 158 */ 'M', 'S', 'A', '3', '0', 0,
758  /* 164 */ 'F', '3', '0', 0,
759  /* 168 */ 'F', '_', 'H', 'I', '3', '0', 0,
760  /* 175 */ 'C', 'O', 'P', '3', '0', 0,
761  /* 181 */ 'F', 'C', 'R', '3', '0', 0,
762  /* 187 */ 'H', 'W', 'R', '3', '0', 0,
763  /* 193 */ 'W', '3', '0', 0,
764  /* 197 */ 'A', '0', 0,
765  /* 200 */ 'A', 'C', '0', 0,
766  /* 204 */ 'F', 'C', 'C', '0', 0,
767  /* 209 */ 'D', '0', 0,
768  /* 212 */ 'F', '0', 0,
769  /* 215 */ 'F', '_', 'H', 'I', '0', 0,
770  /* 221 */ 'K', '0', 0,
771  /* 224 */ 'M', 'P', 'L', '0', 0,
772  /* 229 */ 'L', 'O', '0', 0,
773  /* 233 */ 'P', '0', 0,
774  /* 236 */ 'F', 'C', 'R', '0', 0,
775  /* 241 */ 'H', 'W', 'R', '0', 0,
776  /* 246 */ 'S', '0', 0,
777  /* 249 */ 'T', '0', 0,
778  /* 252 */ 'V', '0', 0,
779  /* 255 */ 'W', '0', 0,
780  /* 258 */ 'C', 'O', 'P', '0', '1', 0,
781  /* 264 */ 'C', 'O', 'P', '0', '1', '1', 0,
782  /* 271 */ 'C', 'O', 'P', '2', '1', '1', 0,
783  /* 278 */ 'C', 'O', 'P', '3', '1', '1', 0,
784  /* 285 */ 'M', 'S', 'A', '1', '1', 0,
785  /* 291 */ 'D', '1', '1', 0,
786  /* 295 */ 'F', '1', '1', 0,
787  /* 299 */ 'F', '_', 'H', 'I', '1', '1', 0,
788  /* 306 */ 'F', 'C', 'R', '1', '1', 0,
789  /* 312 */ 'H', 'W', 'R', '1', '1', 0,
790  /* 318 */ 'W', '1', '1', 0,
791  /* 322 */ 'C', 'O', 'P', '0', '2', '1', 0,
792  /* 329 */ 'C', 'O', 'P', '2', '2', '1', 0,
793  /* 336 */ 'C', 'O', 'P', '3', '2', '1', 0,
794  /* 343 */ 'M', 'S', 'A', '2', '1', 0,
795  /* 349 */ 'F', '2', '1', 0,
796  /* 353 */ 'F', '_', 'H', 'I', '2', '1', 0,
797  /* 360 */ 'C', 'O', 'P', '2', '1', 0,
798  /* 366 */ 'F', 'C', 'R', '2', '1', 0,
799  /* 372 */ 'H', 'W', 'R', '2', '1', 0,
800  /* 378 */ 'W', '2', '1', 0,
801  /* 382 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '1', 0,
802  /* 395 */ 'C', 'O', 'P', '0', '3', '1', 0,
803  /* 402 */ 'C', 'O', 'P', '2', '3', '1', 0,
804  /* 409 */ 'C', 'O', 'P', '3', '3', '1', 0,
805  /* 416 */ 'M', 'S', 'A', '3', '1', 0,
806  /* 422 */ 'F', '3', '1', 0,
807  /* 426 */ 'F', '_', 'H', 'I', '3', '1', 0,
808  /* 433 */ 'C', 'O', 'P', '3', '1', 0,
809  /* 439 */ 'F', 'C', 'R', '3', '1', 0,
810  /* 445 */ 'H', 'W', 'R', '3', '1', 0,
811  /* 451 */ 'W', '3', '1', 0,
812  /* 455 */ 'A', '1', 0,
813  /* 458 */ 'A', 'C', '1', 0,
814  /* 462 */ 'F', 'C', 'C', '1', 0,
815  /* 467 */ 'D', '1', 0,
816  /* 470 */ 'F', '1', 0,
817  /* 473 */ 'F', '_', 'H', 'I', '1', 0,
818  /* 479 */ 'K', '1', 0,
819  /* 482 */ 'M', 'P', 'L', '1', 0,
820  /* 487 */ 'L', 'O', '1', 0,
821  /* 491 */ 'P', '1', 0,
822  /* 494 */ 'F', 'C', 'R', '1', 0,
823  /* 499 */ 'H', 'W', 'R', '1', 0,
824  /* 504 */ 'S', '1', 0,
825  /* 507 */ 'T', '1', 0,
826  /* 510 */ 'V', '1', 0,
827  /* 513 */ 'W', '1', 0,
828  /* 516 */ 'C', 'O', 'P', '0', '2', 0,
829  /* 522 */ 'C', 'O', 'P', '0', '1', '2', 0,
830  /* 529 */ 'C', 'O', 'P', '2', '1', '2', 0,
831  /* 536 */ 'C', 'O', 'P', '3', '1', '2', 0,
832  /* 543 */ 'M', 'S', 'A', '1', '2', 0,
833  /* 549 */ 'D', '1', '2', 0,
834  /* 553 */ 'F', '1', '2', 0,
835  /* 557 */ 'F', '_', 'H', 'I', '1', '2', 0,
836  /* 564 */ 'F', 'C', 'R', '1', '2', 0,
837  /* 570 */ 'H', 'W', 'R', '1', '2', 0,
838  /* 576 */ 'W', '1', '2', 0,
839  /* 580 */ 'C', 'O', 'P', '0', '2', '2', 0,
840  /* 587 */ 'C', 'O', 'P', '2', '2', '2', 0,
841  /* 594 */ 'C', 'O', 'P', '3', '2', '2', 0,
842  /* 601 */ 'M', 'S', 'A', '2', '2', 0,
843  /* 607 */ 'F', '2', '2', 0,
844  /* 611 */ 'F', '_', 'H', 'I', '2', '2', 0,
845  /* 618 */ 'C', 'O', 'P', '2', '2', 0,
846  /* 624 */ 'F', 'C', 'R', '2', '2', 0,
847  /* 630 */ 'H', 'W', 'R', '2', '2', 0,
848  /* 636 */ 'W', '2', '2', 0,
849  /* 640 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '2', 0,
850  /* 653 */ 'C', 'O', 'P', '3', '2', 0,
851  /* 659 */ 'A', '2', 0,
852  /* 662 */ 'A', 'C', '2', 0,
853  /* 666 */ 'F', 'C', 'C', '2', 0,
854  /* 671 */ 'D', '2', 0,
855  /* 674 */ 'F', '2', 0,
856  /* 677 */ 'F', '_', 'H', 'I', '2', 0,
857  /* 683 */ 'M', 'P', 'L', '2', 0,
858  /* 688 */ 'L', 'O', '2', 0,
859  /* 692 */ 'P', '2', 0,
860  /* 695 */ 'F', 'C', 'R', '2', 0,
861  /* 700 */ 'H', 'W', 'R', '2', 0,
862  /* 705 */ 'S', '2', 0,
863  /* 708 */ 'T', '2', 0,
864  /* 711 */ 'W', '2', 0,
865  /* 714 */ 'C', 'O', 'P', '0', '3', 0,
866  /* 720 */ 'C', 'O', 'P', '0', '1', '3', 0,
867  /* 727 */ 'C', 'O', 'P', '2', '1', '3', 0,
868  /* 734 */ 'C', 'O', 'P', '3', '1', '3', 0,
869  /* 741 */ 'M', 'S', 'A', '1', '3', 0,
870  /* 747 */ 'D', '1', '3', 0,
871  /* 751 */ 'F', '1', '3', 0,
872  /* 755 */ 'F', '_', 'H', 'I', '1', '3', 0,
873  /* 762 */ 'F', 'C', 'R', '1', '3', 0,
874  /* 768 */ 'H', 'W', 'R', '1', '3', 0,
875  /* 774 */ 'W', '1', '3', 0,
876  /* 778 */ 'C', 'O', 'P', '0', '2', '3', 0,
877  /* 785 */ 'C', 'O', 'P', '2', '2', '3', 0,
878  /* 792 */ 'C', 'O', 'P', '3', '2', '3', 0,
879  /* 799 */ 'M', 'S', 'A', '2', '3', 0,
880  /* 805 */ 'F', '2', '3', 0,
881  /* 809 */ 'F', '_', 'H', 'I', '2', '3', 0,
882  /* 816 */ 'C', 'O', 'P', '2', '3', 0,
883  /* 822 */ 'F', 'C', 'R', '2', '3', 0,
884  /* 828 */ 'H', 'W', 'R', '2', '3', 0,
885  /* 834 */ 'W', '2', '3', 0,
886  /* 838 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '3', 0,
887  /* 851 */ 'C', 'O', 'P', '3', '3', 0,
888  /* 857 */ 'A', '3', 0,
889  /* 860 */ 'A', 'C', '3', 0,
890  /* 864 */ 'F', 'C', 'C', '3', 0,
891  /* 869 */ 'D', '3', 0,
892  /* 872 */ 'F', '3', 0,
893  /* 875 */ 'F', '_', 'H', 'I', '3', 0,
894  /* 881 */ 'L', 'O', '3', 0,
895  /* 885 */ 'F', 'C', 'R', '3', 0,
896  /* 890 */ 'H', 'W', 'R', '3', 0,
897  /* 895 */ 'S', '3', 0,
898  /* 898 */ 'T', '3', 0,
899  /* 901 */ 'W', '3', 0,
900  /* 904 */ 'C', 'O', 'P', '0', '4', 0,
901  /* 910 */ 'C', 'O', 'P', '0', '1', '4', 0,
902  /* 917 */ 'C', 'O', 'P', '2', '1', '4', 0,
903  /* 924 */ 'C', 'O', 'P', '3', '1', '4', 0,
904  /* 931 */ 'M', 'S', 'A', '1', '4', 0,
905  /* 937 */ 'D', '1', '4', 0,
906  /* 941 */ 'F', '1', '4', 0,
907  /* 945 */ 'F', '_', 'H', 'I', '1', '4', 0,
908  /* 952 */ 'F', 'C', 'R', '1', '4', 0,
909  /* 958 */ 'H', 'W', 'R', '1', '4', 0,
910  /* 964 */ 'W', '1', '4', 0,
911  /* 968 */ 'C', 'O', 'P', '0', '2', '4', 0,
912  /* 975 */ 'C', 'O', 'P', '2', '2', '4', 0,
913  /* 982 */ 'C', 'O', 'P', '3', '2', '4', 0,
914  /* 989 */ 'M', 'S', 'A', '2', '4', 0,
915  /* 995 */ 'F', '2', '4', 0,
916  /* 999 */ 'F', '_', 'H', 'I', '2', '4', 0,
917  /* 1006 */ 'C', 'O', 'P', '2', '4', 0,
918  /* 1012 */ 'F', 'C', 'R', '2', '4', 0,
919  /* 1018 */ 'H', 'W', 'R', '2', '4', 0,
920  /* 1024 */ 'W', '2', '4', 0,
921  /* 1028 */ 'C', 'O', 'P', '3', '4', 0,
922  /* 1034 */ 'D', '1', '0', '_', '6', '4', 0,
923  /* 1041 */ 'D', '2', '0', '_', '6', '4', 0,
924  /* 1048 */ 'D', '3', '0', '_', '6', '4', 0,
925  /* 1055 */ 'A', '0', '_', '6', '4', 0,
926  /* 1061 */ 'A', 'C', '0', '_', '6', '4', 0,
927  /* 1068 */ 'D', '0', '_', '6', '4', 0,
928  /* 1074 */ 'H', 'I', '0', '_', '6', '4', 0,
929  /* 1081 */ 'K', '0', '_', '6', '4', 0,
930  /* 1087 */ 'L', 'O', '0', '_', '6', '4', 0,
931  /* 1094 */ 'S', '0', '_', '6', '4', 0,
932  /* 1100 */ 'T', '0', '_', '6', '4', 0,
933  /* 1106 */ 'V', '0', '_', '6', '4', 0,
934  /* 1112 */ 'D', '1', '1', '_', '6', '4', 0,
935  /* 1119 */ 'D', '2', '1', '_', '6', '4', 0,
936  /* 1126 */ 'D', '3', '1', '_', '6', '4', 0,
937  /* 1133 */ 'A', '1', '_', '6', '4', 0,
938  /* 1139 */ 'D', '1', '_', '6', '4', 0,
939  /* 1145 */ 'K', '1', '_', '6', '4', 0,
940  /* 1151 */ 'S', '1', '_', '6', '4', 0,
941  /* 1157 */ 'T', '1', '_', '6', '4', 0,
942  /* 1163 */ 'V', '1', '_', '6', '4', 0,
943  /* 1169 */ 'D', '1', '2', '_', '6', '4', 0,
944  /* 1176 */ 'D', '2', '2', '_', '6', '4', 0,
945  /* 1183 */ 'A', '2', '_', '6', '4', 0,
946  /* 1189 */ 'D', '2', '_', '6', '4', 0,
947  /* 1195 */ 'S', '2', '_', '6', '4', 0,
948  /* 1201 */ 'T', '2', '_', '6', '4', 0,
949  /* 1207 */ 'D', '1', '3', '_', '6', '4', 0,
950  /* 1214 */ 'D', '2', '3', '_', '6', '4', 0,
951  /* 1221 */ 'A', '3', '_', '6', '4', 0,
952  /* 1227 */ 'D', '3', '_', '6', '4', 0,
953  /* 1233 */ 'S', '3', '_', '6', '4', 0,
954  /* 1239 */ 'T', '3', '_', '6', '4', 0,
955  /* 1245 */ 'D', '1', '4', '_', '6', '4', 0,
956  /* 1252 */ 'D', '2', '4', '_', '6', '4', 0,
957  /* 1259 */ 'D', '4', '_', '6', '4', 0,
958  /* 1265 */ 'S', '4', '_', '6', '4', 0,
959  /* 1271 */ 'T', '4', '_', '6', '4', 0,
960  /* 1277 */ 'D', '1', '5', '_', '6', '4', 0,
961  /* 1284 */ 'D', '2', '5', '_', '6', '4', 0,
962  /* 1291 */ 'D', '5', '_', '6', '4', 0,
963  /* 1297 */ 'S', '5', '_', '6', '4', 0,
964  /* 1303 */ 'T', '5', '_', '6', '4', 0,
965  /* 1309 */ 'D', '1', '6', '_', '6', '4', 0,
966  /* 1316 */ 'D', '2', '6', '_', '6', '4', 0,
967  /* 1323 */ 'D', '6', '_', '6', '4', 0,
968  /* 1329 */ 'S', '6', '_', '6', '4', 0,
969  /* 1335 */ 'T', '6', '_', '6', '4', 0,
970  /* 1341 */ 'D', '1', '7', '_', '6', '4', 0,
971  /* 1348 */ 'D', '2', '7', '_', '6', '4', 0,
972  /* 1355 */ 'D', '7', '_', '6', '4', 0,
973  /* 1361 */ 'S', '7', '_', '6', '4', 0,
974  /* 1367 */ 'T', '7', '_', '6', '4', 0,
975  /* 1373 */ 'D', '1', '8', '_', '6', '4', 0,
976  /* 1380 */ 'D', '2', '8', '_', '6', '4', 0,
977  /* 1387 */ 'D', '8', '_', '6', '4', 0,
978  /* 1393 */ 'T', '8', '_', '6', '4', 0,
979  /* 1399 */ 'D', '1', '9', '_', '6', '4', 0,
980  /* 1406 */ 'D', '2', '9', '_', '6', '4', 0,
981  /* 1413 */ 'D', '9', '_', '6', '4', 0,
982  /* 1419 */ 'T', '9', '_', '6', '4', 0,
983  /* 1425 */ 'R', 'A', '_', '6', '4', 0,
984  /* 1431 */ 'Z', 'E', 'R', 'O', '_', '6', '4', 0,
985  /* 1439 */ 'F', 'P', '_', '6', '4', 0,
986  /* 1445 */ 'G', 'P', '_', '6', '4', 0,
987  /* 1451 */ 'S', 'P', '_', '6', '4', 0,
988  /* 1457 */ 'A', 'T', '_', '6', '4', 0,
989  /* 1463 */ 'F', 'C', 'C', '4', 0,
990  /* 1468 */ 'D', '4', 0,
991  /* 1471 */ 'F', '4', 0,
992  /* 1474 */ 'F', '_', 'H', 'I', '4', 0,
993  /* 1480 */ 'F', 'C', 'R', '4', 0,
994  /* 1485 */ 'H', 'W', 'R', '4', 0,
995  /* 1490 */ 'S', '4', 0,
996  /* 1493 */ 'T', '4', 0,
997  /* 1496 */ 'W', '4', 0,
998  /* 1499 */ 'C', 'O', 'P', '0', '5', 0,
999  /* 1505 */ 'C', 'O', 'P', '0', '1', '5', 0,
1000  /* 1512 */ 'C', 'O', 'P', '2', '1', '5', 0,
1001  /* 1519 */ 'C', 'O', 'P', '3', '1', '5', 0,
1002  /* 1526 */ 'M', 'S', 'A', '1', '5', 0,
1003  /* 1532 */ 'D', '1', '5', 0,
1004  /* 1536 */ 'F', '1', '5', 0,
1005  /* 1540 */ 'F', '_', 'H', 'I', '1', '5', 0,
1006  /* 1547 */ 'F', 'C', 'R', '1', '5', 0,
1007  /* 1553 */ 'H', 'W', 'R', '1', '5', 0,
1008  /* 1559 */ 'W', '1', '5', 0,
1009  /* 1563 */ 'C', 'O', 'P', '0', '2', '5', 0,
1010  /* 1570 */ 'C', 'O', 'P', '2', '2', '5', 0,
1011  /* 1577 */ 'C', 'O', 'P', '3', '2', '5', 0,
1012  /* 1584 */ 'M', 'S', 'A', '2', '5', 0,
1013  /* 1590 */ 'F', '2', '5', 0,
1014  /* 1594 */ 'F', '_', 'H', 'I', '2', '5', 0,
1015  /* 1601 */ 'C', 'O', 'P', '2', '5', 0,
1016  /* 1607 */ 'F', 'C', 'R', '2', '5', 0,
1017  /* 1613 */ 'H', 'W', 'R', '2', '5', 0,
1018  /* 1619 */ 'W', '2', '5', 0,
1019  /* 1623 */ 'C', 'O', 'P', '3', '5', 0,
1020  /* 1629 */ 'F', 'C', 'C', '5', 0,
1021  /* 1634 */ 'D', '5', 0,
1022  /* 1637 */ 'F', '5', 0,
1023  /* 1640 */ 'F', '_', 'H', 'I', '5', 0,
1024  /* 1646 */ 'F', 'C', 'R', '5', 0,
1025  /* 1651 */ 'H', 'W', 'R', '5', 0,
1026  /* 1656 */ 'S', '5', 0,
1027  /* 1659 */ 'T', '5', 0,
1028  /* 1662 */ 'W', '5', 0,
1029  /* 1665 */ 'C', 'O', 'P', '0', '6', 0,
1030  /* 1671 */ 'C', 'O', 'P', '0', '1', '6', 0,
1031  /* 1678 */ 'C', 'O', 'P', '2', '1', '6', 0,
1032  /* 1685 */ 'C', 'O', 'P', '3', '1', '6', 0,
1033  /* 1692 */ 'M', 'S', 'A', '1', '6', 0,
1034  /* 1698 */ 'F', '1', '6', 0,
1035  /* 1702 */ 'F', '_', 'H', 'I', '1', '6', 0,
1036  /* 1709 */ 'F', 'C', 'R', '1', '6', 0,
1037  /* 1715 */ 'H', 'W', 'R', '1', '6', 0,
1038  /* 1721 */ 'W', '1', '6', 0,
1039  /* 1725 */ 'C', 'O', 'P', '0', '2', '6', 0,
1040  /* 1732 */ 'C', 'O', 'P', '2', '2', '6', 0,
1041  /* 1739 */ 'C', 'O', 'P', '3', '2', '6', 0,
1042  /* 1746 */ 'M', 'S', 'A', '2', '6', 0,
1043  /* 1752 */ 'F', '2', '6', 0,
1044  /* 1756 */ 'F', '_', 'H', 'I', '2', '6', 0,
1045  /* 1763 */ 'C', 'O', 'P', '2', '6', 0,
1046  /* 1769 */ 'F', 'C', 'R', '2', '6', 0,
1047  /* 1775 */ 'H', 'W', 'R', '2', '6', 0,
1048  /* 1781 */ 'W', '2', '6', 0,
1049  /* 1785 */ 'C', 'O', 'P', '3', '6', 0,
1050  /* 1791 */ 'F', 'C', 'C', '6', 0,
1051  /* 1796 */ 'D', '6', 0,
1052  /* 1799 */ 'F', '6', 0,
1053  /* 1802 */ 'F', '_', 'H', 'I', '6', 0,
1054  /* 1808 */ 'F', 'C', 'R', '6', 0,
1055  /* 1813 */ 'H', 'W', 'R', '6', 0,
1056  /* 1818 */ 'S', '6', 0,
1057  /* 1821 */ 'T', '6', 0,
1058  /* 1824 */ 'W', '6', 0,
1059  /* 1827 */ 'C', 'O', 'P', '0', '7', 0,
1060  /* 1833 */ 'C', 'O', 'P', '0', '1', '7', 0,
1061  /* 1840 */ 'C', 'O', 'P', '2', '1', '7', 0,
1062  /* 1847 */ 'C', 'O', 'P', '3', '1', '7', 0,
1063  /* 1854 */ 'M', 'S', 'A', '1', '7', 0,
1064  /* 1860 */ 'F', '1', '7', 0,
1065  /* 1864 */ 'F', '_', 'H', 'I', '1', '7', 0,
1066  /* 1871 */ 'F', 'C', 'R', '1', '7', 0,
1067  /* 1877 */ 'H', 'W', 'R', '1', '7', 0,
1068  /* 1883 */ 'W', '1', '7', 0,
1069  /* 1887 */ 'C', 'O', 'P', '0', '2', '7', 0,
1070  /* 1894 */ 'C', 'O', 'P', '2', '2', '7', 0,
1071  /* 1901 */ 'C', 'O', 'P', '3', '2', '7', 0,
1072  /* 1908 */ 'M', 'S', 'A', '2', '7', 0,
1073  /* 1914 */ 'F', '2', '7', 0,
1074  /* 1918 */ 'F', '_', 'H', 'I', '2', '7', 0,
1075  /* 1925 */ 'C', 'O', 'P', '2', '7', 0,
1076  /* 1931 */ 'F', 'C', 'R', '2', '7', 0,
1077  /* 1937 */ 'H', 'W', 'R', '2', '7', 0,
1078  /* 1943 */ 'W', '2', '7', 0,
1079  /* 1947 */ 'C', 'O', 'P', '3', '7', 0,
1080  /* 1953 */ 'F', 'C', 'C', '7', 0,
1081  /* 1958 */ 'D', '7', 0,
1082  /* 1961 */ 'F', '7', 0,
1083  /* 1964 */ 'F', '_', 'H', 'I', '7', 0,
1084  /* 1970 */ 'F', 'C', 'R', '7', 0,
1085  /* 1975 */ 'H', 'W', 'R', '7', 0,
1086  /* 1980 */ 'S', '7', 0,
1087  /* 1983 */ 'T', '7', 0,
1088  /* 1986 */ 'W', '7', 0,
1089  /* 1989 */ 'C', 'O', 'P', '0', '8', 0,
1090  /* 1995 */ 'C', 'O', 'P', '0', '1', '8', 0,
1091  /* 2002 */ 'C', 'O', 'P', '2', '1', '8', 0,
1092  /* 2009 */ 'C', 'O', 'P', '3', '1', '8', 0,
1093  /* 2016 */ 'M', 'S', 'A', '1', '8', 0,
1094  /* 2022 */ 'F', '1', '8', 0,
1095  /* 2026 */ 'F', '_', 'H', 'I', '1', '8', 0,
1096  /* 2033 */ 'F', 'C', 'R', '1', '8', 0,
1097  /* 2039 */ 'H', 'W', 'R', '1', '8', 0,
1098  /* 2045 */ 'W', '1', '8', 0,
1099  /* 2049 */ 'C', 'O', 'P', '0', '2', '8', 0,
1100  /* 2056 */ 'C', 'O', 'P', '2', '2', '8', 0,
1101  /* 2063 */ 'C', 'O', 'P', '3', '2', '8', 0,
1102  /* 2070 */ 'M', 'S', 'A', '2', '8', 0,
1103  /* 2076 */ 'F', '2', '8', 0,
1104  /* 2080 */ 'F', '_', 'H', 'I', '2', '8', 0,
1105  /* 2087 */ 'C', 'O', 'P', '2', '8', 0,
1106  /* 2093 */ 'F', 'C', 'R', '2', '8', 0,
1107  /* 2099 */ 'H', 'W', 'R', '2', '8', 0,
1108  /* 2105 */ 'W', '2', '8', 0,
1109  /* 2109 */ 'C', 'O', 'P', '3', '8', 0,
1110  /* 2115 */ 'M', 'S', 'A', '8', 0,
1111  /* 2120 */ 'D', '8', 0,
1112  /* 2123 */ 'F', '8', 0,
1113  /* 2126 */ 'F', '_', 'H', 'I', '8', 0,
1114  /* 2132 */ 'F', 'C', 'R', '8', 0,
1115  /* 2137 */ 'H', 'W', 'R', '8', 0,
1116  /* 2142 */ 'T', '8', 0,
1117  /* 2145 */ 'W', '8', 0,
1118  /* 2148 */ 'C', 'O', 'P', '0', '9', 0,
1119  /* 2154 */ 'C', 'O', 'P', '0', '1', '9', 0,
1120  /* 2161 */ 'C', 'O', 'P', '2', '1', '9', 0,
1121  /* 2168 */ 'C', 'O', 'P', '3', '1', '9', 0,
1122  /* 2175 */ 'M', 'S', 'A', '1', '9', 0,
1123  /* 2181 */ 'F', '1', '9', 0,
1124  /* 2185 */ 'F', '_', 'H', 'I', '1', '9', 0,
1125  /* 2192 */ 'F', 'C', 'R', '1', '9', 0,
1126  /* 2198 */ 'H', 'W', 'R', '1', '9', 0,
1127  /* 2204 */ 'W', '1', '9', 0,
1128  /* 2208 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '1', '6', '_', '1', '9', 0,
1129  /* 2224 */ 'C', 'O', 'P', '0', '2', '9', 0,
1130  /* 2231 */ 'C', 'O', 'P', '2', '2', '9', 0,
1131  /* 2238 */ 'C', 'O', 'P', '3', '2', '9', 0,
1132  /* 2245 */ 'M', 'S', 'A', '2', '9', 0,
1133  /* 2251 */ 'F', '2', '9', 0,
1134  /* 2255 */ 'F', '_', 'H', 'I', '2', '9', 0,
1135  /* 2262 */ 'C', 'O', 'P', '2', '9', 0,
1136  /* 2268 */ 'F', 'C', 'R', '2', '9', 0,
1137  /* 2274 */ 'H', 'W', 'R', '2', '9', 0,
1138  /* 2280 */ 'W', '2', '9', 0,
1139  /* 2284 */ 'C', 'O', 'P', '3', '9', 0,
1140  /* 2290 */ 'M', 'S', 'A', '9', 0,
1141  /* 2295 */ 'D', '9', 0,
1142  /* 2298 */ 'F', '9', 0,
1143  /* 2301 */ 'F', '_', 'H', 'I', '9', 0,
1144  /* 2307 */ 'F', 'C', 'R', '9', 0,
1145  /* 2312 */ 'H', 'W', 'R', '9', 0,
1146  /* 2317 */ 'T', '9', 0,
1147  /* 2320 */ 'W', '9', 0,
1148  /* 2323 */ 'R', 'A', 0,
1149  /* 2326 */ 'P', 'C', 0,
1150  /* 2329 */ 'D', 'S', 'P', 'E', 'F', 'I', 0,
1151  /* 2336 */ 'Z', 'E', 'R', 'O', 0,
1152  /* 2341 */ 'F', 'P', 0,
1153  /* 2344 */ 'G', 'P', 0,
1154  /* 2347 */ 'S', 'P', 0,
1155  /* 2350 */ 'M', 'S', 'A', 'I', 'R', 0,
1156  /* 2356 */ 'M', 'S', 'A', 'C', 'S', 'R', 0,
1157  /* 2363 */ 'A', 'T', 0,
1158  /* 2366 */ 'D', 'S', 'P', 'C', 'C', 'o', 'n', 'd', 0,
1159  /* 2375 */ 'M', 'S', 'A', 'S', 'a', 'v', 'e', 0,
1160  /* 2383 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', 0,
1161  /* 2394 */ 'M', 'S', 'A', 'M', 'a', 'p', 0,
1162  /* 2401 */ 'M', 'S', 'A', 'U', 'n', 'm', 'a', 'p', 0,
1163  /* 2410 */ 'D', 'S', 'P', 'P', 'o', 's', 0,
1164  /* 2417 */ 'M', 'S', 'A', 'A', 'c', 'c', 'e', 's', 's', 0,
1165  /* 2427 */ 'D', 'S', 'P', 'S', 'C', 'o', 'u', 'n', 't', 0,
1166  /* 2437 */ 'M', 'S', 'A', 'R', 'e', 'q', 'u', 'e', 's', 't', 0,
1167  /* 2448 */ 'M', 'S', 'A', 'M', 'o', 'd', 'i', 'f', 'y', 0,
1168  /* 2458 */ 'D', 'S', 'P', 'C', 'a', 'r', 'r', 'y', 0,
1169  0
1170};
1171
1172extern const MCRegisterDesc MipsRegDesc[] = { // Descriptors
1173  { 5, 0, 0, 0, 0, 0 },
1174  { 2363, 1, 82, 1, 4017, 0 },
1175  { 2366, 1, 1, 1, 4017, 0 },
1176  { 2458, 1, 1, 1, 4017, 0 },
1177  { 2329, 1, 1, 1, 4017, 0 },
1178  { 2383, 8, 1, 2, 32, 4 },
1179  { 2410, 1, 1, 1, 1089, 0 },
1180  { 2427, 1, 1, 1, 1089, 0 },
1181  { 2341, 1, 102, 1, 1089, 0 },
1182  { 2344, 1, 104, 1, 1089, 0 },
1183  { 2417, 1, 1, 1, 1089, 0 },
1184  { 2356, 1, 1, 1, 1089, 0 },
1185  { 2350, 1, 1, 1, 1089, 0 },
1186  { 2394, 1, 1, 1, 1089, 0 },
1187  { 2448, 1, 1, 1, 1089, 0 },
1188  { 2437, 1, 1, 1, 1089, 0 },
1189  { 2375, 1, 1, 1, 1089, 0 },
1190  { 2401, 1, 1, 1, 1089, 0 },
1191  { 2326, 1, 1, 1, 1089, 0 },
1192  { 2323, 1, 106, 1, 1089, 0 },
1193  { 2347, 1, 108, 1, 1089, 0 },
1194  { 2336, 1, 110, 1, 1089, 0 },
1195  { 197, 1, 110, 1, 1089, 0 },
1196  { 455, 1, 110, 1, 1089, 0 },
1197  { 659, 1, 110, 1, 1089, 0 },
1198  { 857, 1, 110, 1, 1089, 0 },
1199  { 200, 190, 110, 9, 1042, 10 },
1200  { 458, 190, 1, 9, 1042, 10 },
1201  { 662, 190, 1, 9, 1042, 10 },
1202  { 860, 190, 1, 9, 1042, 10 },
1203  { 1457, 237, 1, 0, 0, 2 },
1204  { 0, 1, 1, 1, 1153, 0 },
1205  { 258, 1, 1, 1, 1153, 0 },
1206  { 516, 1, 1, 1, 1153, 0 },
1207  { 714, 1, 1, 1, 1153, 0 },
1208  { 904, 1, 1, 1, 1153, 0 },
1209  { 1499, 1, 1, 1, 1153, 0 },
1210  { 1665, 1, 1, 1, 1153, 0 },
1211  { 1827, 1, 1, 1, 1153, 0 },
1212  { 1989, 1, 1, 1, 1153, 0 },
1213  { 2148, 1, 1, 1, 1153, 0 },
1214  { 102, 1, 1, 1, 1153, 0 },
1215  { 360, 1, 1, 1, 1153, 0 },
1216  { 618, 1, 1, 1, 1153, 0 },
1217  { 816, 1, 1, 1, 1153, 0 },
1218  { 1006, 1, 1, 1, 1153, 0 },
1219  { 1601, 1, 1, 1, 1153, 0 },
1220  { 1763, 1, 1, 1, 1153, 0 },
1221  { 1925, 1, 1, 1, 1153, 0 },
1222  { 2087, 1, 1, 1, 1153, 0 },
1223  { 2262, 1, 1, 1, 1153, 0 },
1224  { 175, 1, 1, 1, 1153, 0 },
1225  { 433, 1, 1, 1, 1153, 0 },
1226  { 653, 1, 1, 1, 1153, 0 },
1227  { 851, 1, 1, 1, 1153, 0 },
1228  { 1028, 1, 1, 1, 1153, 0 },
1229  { 1623, 1, 1, 1, 1153, 0 },
1230  { 1785, 1, 1, 1, 1153, 0 },
1231  { 1947, 1, 1, 1, 1153, 0 },
1232  { 2109, 1, 1, 1, 1153, 0 },
1233  { 2284, 1, 1, 1, 1153, 0 },
1234  { 6, 1, 1, 1, 1153, 0 },
1235  { 264, 1, 1, 1, 1153, 0 },
1236  { 522, 1, 1, 1, 1153, 0 },
1237  { 720, 1, 1, 1, 1153, 0 },
1238  { 910, 1, 1, 1, 1153, 0 },
1239  { 1505, 1, 1, 1, 1153, 0 },
1240  { 1671, 1, 1, 1, 1153, 0 },
1241  { 1833, 1, 1, 1, 1153, 0 },
1242  { 1995, 1, 1, 1, 1153, 0 },
1243  { 2154, 1, 1, 1, 1153, 0 },
1244  { 64, 1, 1, 1, 1153, 0 },
1245  { 322, 1, 1, 1, 1153, 0 },
1246  { 580, 1, 1, 1, 1153, 0 },
1247  { 778, 1, 1, 1, 1153, 0 },
1248  { 968, 1, 1, 1, 1153, 0 },
1249  { 1563, 1, 1, 1, 1153, 0 },
1250  { 1725, 1, 1, 1, 1153, 0 },
1251  { 1887, 1, 1, 1, 1153, 0 },
1252  { 2049, 1, 1, 1, 1153, 0 },
1253  { 2224, 1, 1, 1, 1153, 0 },
1254  { 137, 1, 1, 1, 1153, 0 },
1255  { 395, 1, 1, 1, 1153, 0 },
1256  { 13, 1, 1, 1, 1153, 0 },
1257  { 271, 1, 1, 1, 1153, 0 },
1258  { 529, 1, 1, 1, 1153, 0 },
1259  { 727, 1, 1, 1, 1153, 0 },
1260  { 917, 1, 1, 1, 1153, 0 },
1261  { 1512, 1, 1, 1, 1153, 0 },
1262  { 1678, 1, 1, 1, 1153, 0 },
1263  { 1840, 1, 1, 1, 1153, 0 },
1264  { 2002, 1, 1, 1, 1153, 0 },
1265  { 2161, 1, 1, 1, 1153, 0 },
1266  { 71, 1, 1, 1, 1153, 0 },
1267  { 329, 1, 1, 1, 1153, 0 },
1268  { 587, 1, 1, 1, 1153, 0 },
1269  { 785, 1, 1, 1, 1153, 0 },
1270  { 975, 1, 1, 1, 1153, 0 },
1271  { 1570, 1, 1, 1, 1153, 0 },
1272  { 1732, 1, 1, 1, 1153, 0 },
1273  { 1894, 1, 1, 1, 1153, 0 },
1274  { 2056, 1, 1, 1, 1153, 0 },
1275  { 2231, 1, 1, 1, 1153, 0 },
1276  { 144, 1, 1, 1, 1153, 0 },
1277  { 402, 1, 1, 1, 1153, 0 },
1278  { 20, 1, 1, 1, 1153, 0 },
1279  { 278, 1, 1, 1, 1153, 0 },
1280  { 536, 1, 1, 1, 1153, 0 },
1281  { 734, 1, 1, 1, 1153, 0 },
1282  { 924, 1, 1, 1, 1153, 0 },
1283  { 1519, 1, 1, 1, 1153, 0 },
1284  { 1685, 1, 1, 1, 1153, 0 },
1285  { 1847, 1, 1, 1, 1153, 0 },
1286  { 2009, 1, 1, 1, 1153, 0 },
1287  { 2168, 1, 1, 1, 1153, 0 },
1288  { 78, 1, 1, 1, 1153, 0 },
1289  { 336, 1, 1, 1, 1153, 0 },
1290  { 594, 1, 1, 1, 1153, 0 },
1291  { 792, 1, 1, 1, 1153, 0 },
1292  { 982, 1, 1, 1, 1153, 0 },
1293  { 1577, 1, 1, 1, 1153, 0 },
1294  { 1739, 1, 1, 1, 1153, 0 },
1295  { 1901, 1, 1, 1, 1153, 0 },
1296  { 2063, 1, 1, 1, 1153, 0 },
1297  { 2238, 1, 1, 1, 1153, 0 },
1298  { 151, 1, 1, 1, 1153, 0 },
1299  { 409, 1, 1, 1, 1153, 0 },
1300  { 209, 14, 1, 9, 994, 10 },
1301  { 467, 17, 1, 9, 994, 10 },
1302  { 671, 20, 1, 9, 994, 10 },
1303  { 869, 23, 1, 9, 994, 10 },
1304  { 1468, 26, 1, 9, 994, 10 },
1305  { 1634, 29, 1, 9, 994, 10 },
1306  { 1796, 32, 1, 9, 994, 10 },
1307  { 1958, 35, 1, 9, 994, 10 },
1308  { 2120, 38, 1, 9, 994, 10 },
1309  { 2295, 41, 1, 9, 994, 10 },
1310  { 33, 44, 1, 9, 994, 10 },
1311  { 291, 47, 1, 9, 994, 10 },
1312  { 549, 50, 1, 9, 994, 10 },
1313  { 747, 53, 1, 9, 994, 10 },
1314  { 937, 56, 1, 9, 994, 10 },
1315  { 1532, 59, 1, 9, 994, 10 },
1316  { 124, 1, 148, 1, 2369, 0 },
1317  { 382, 1, 146, 1, 2369, 0 },
1318  { 640, 1, 144, 1, 2369, 0 },
1319  { 838, 1, 142, 1, 2369, 0 },
1320  { 212, 1, 161, 1, 3985, 0 },
1321  { 470, 1, 165, 1, 3985, 0 },
1322  { 674, 1, 165, 1, 3985, 0 },
1323  { 872, 1, 169, 1, 3985, 0 },
1324  { 1471, 1, 169, 1, 3985, 0 },
1325  { 1637, 1, 173, 1, 3985, 0 },
1326  { 1799, 1, 173, 1, 3985, 0 },
1327  { 1961, 1, 177, 1, 3985, 0 },
1328  { 2123, 1, 177, 1, 3985, 0 },
1329  { 2298, 1, 181, 1, 3985, 0 },
1330  { 37, 1, 181, 1, 3985, 0 },
1331  { 295, 1, 185, 1, 3985, 0 },
1332  { 553, 1, 185, 1, 3985, 0 },
1333  { 751, 1, 189, 1, 3985, 0 },
1334  { 941, 1, 189, 1, 3985, 0 },
1335  { 1536, 1, 193, 1, 3985, 0 },
1336  { 1698, 1, 193, 1, 3985, 0 },
1337  { 1860, 1, 197, 1, 3985, 0 },
1338  { 2022, 1, 197, 1, 3985, 0 },
1339  { 2181, 1, 201, 1, 3985, 0 },
1340  { 91, 1, 201, 1, 3985, 0 },
1341  { 349, 1, 205, 1, 3985, 0 },
1342  { 607, 1, 205, 1, 3985, 0 },
1343  { 805, 1, 209, 1, 3985, 0 },
1344  { 995, 1, 209, 1, 3985, 0 },
1345  { 1590, 1, 213, 1, 3985, 0 },
1346  { 1752, 1, 213, 1, 3985, 0 },
1347  { 1914, 1, 217, 1, 3985, 0 },
1348  { 2076, 1, 217, 1, 3985, 0 },
1349  { 2251, 1, 221, 1, 3985, 0 },
1350  { 164, 1, 221, 1, 3985, 0 },
1351  { 422, 1, 225, 1, 3985, 0 },
1352  { 204, 1, 1, 1, 3985, 0 },
1353  { 462, 1, 1, 1, 3985, 0 },
1354  { 666, 1, 1, 1, 3985, 0 },
1355  { 864, 1, 1, 1, 3985, 0 },
1356  { 1463, 1, 1, 1, 3985, 0 },
1357  { 1629, 1, 1, 1, 3985, 0 },
1358  { 1791, 1, 1, 1, 3985, 0 },
1359  { 1953, 1, 1, 1, 3985, 0 },
1360  { 236, 1, 1, 1, 3985, 0 },
1361  { 494, 1, 1, 1, 3985, 0 },
1362  { 695, 1, 1, 1, 3985, 0 },
1363  { 885, 1, 1, 1, 3985, 0 },
1364  { 1480, 1, 1, 1, 3985, 0 },
1365  { 1646, 1, 1, 1, 3985, 0 },
1366  { 1808, 1, 1, 1, 3985, 0 },
1367  { 1970, 1, 1, 1, 3985, 0 },
1368  { 2132, 1, 1, 1, 3985, 0 },
1369  { 2307, 1, 1, 1, 3985, 0 },
1370  { 48, 1, 1, 1, 3985, 0 },
1371  { 306, 1, 1, 1, 3985, 0 },
1372  { 564, 1, 1, 1, 3985, 0 },
1373  { 762, 1, 1, 1, 3985, 0 },
1374  { 952, 1, 1, 1, 3985, 0 },
1375  { 1547, 1, 1, 1, 3985, 0 },
1376  { 1709, 1, 1, 1, 3985, 0 },
1377  { 1871, 1, 1, 1, 3985, 0 },
1378  { 2033, 1, 1, 1, 3985, 0 },
1379  { 2192, 1, 1, 1, 3985, 0 },
1380  { 108, 1, 1, 1, 3985, 0 },
1381  { 366, 1, 1, 1, 3985, 0 },
1382  { 624, 1, 1, 1, 3985, 0 },
1383  { 822, 1, 1, 1, 3985, 0 },
1384  { 1012, 1, 1, 1, 3985, 0 },
1385  { 1607, 1, 1, 1, 3985, 0 },
1386  { 1769, 1, 1, 1, 3985, 0 },
1387  { 1931, 1, 1, 1, 3985, 0 },
1388  { 2093, 1, 1, 1, 3985, 0 },
1389  { 2268, 1, 1, 1, 3985, 0 },
1390  { 181, 1, 1, 1, 3985, 0 },
1391  { 439, 1, 1, 1, 3985, 0 },
1392  { 1439, 136, 1, 0, 1184, 2 },
1393  { 215, 1, 158, 1, 3953, 0 },
1394  { 473, 1, 158, 1, 3953, 0 },
1395  { 677, 1, 158, 1, 3953, 0 },
1396  { 875, 1, 158, 1, 3953, 0 },
1397  { 1474, 1, 158, 1, 3953, 0 },
1398  { 1640, 1, 158, 1, 3953, 0 },
1399  { 1802, 1, 158, 1, 3953, 0 },
1400  { 1964, 1, 158, 1, 3953, 0 },
1401  { 2126, 1, 158, 1, 3953, 0 },
1402  { 2301, 1, 158, 1, 3953, 0 },
1403  { 41, 1, 158, 1, 3953, 0 },
1404  { 299, 1, 158, 1, 3953, 0 },
1405  { 557, 1, 158, 1, 3953, 0 },
1406  { 755, 1, 158, 1, 3953, 0 },
1407  { 945, 1, 158, 1, 3953, 0 },
1408  { 1540, 1, 158, 1, 3953, 0 },
1409  { 1702, 1, 158, 1, 3953, 0 },
1410  { 1864, 1, 158, 1, 3953, 0 },
1411  { 2026, 1, 158, 1, 3953, 0 },
1412  { 2185, 1, 158, 1, 3953, 0 },
1413  { 95, 1, 158, 1, 3953, 0 },
1414  { 353, 1, 158, 1, 3953, 0 },
1415  { 611, 1, 158, 1, 3953, 0 },
1416  { 809, 1, 158, 1, 3953, 0 },
1417  { 999, 1, 158, 1, 3953, 0 },
1418  { 1594, 1, 158, 1, 3953, 0 },
1419  { 1756, 1, 158, 1, 3953, 0 },
1420  { 1918, 1, 158, 1, 3953, 0 },
1421  { 2080, 1, 158, 1, 3953, 0 },
1422  { 2255, 1, 158, 1, 3953, 0 },
1423  { 168, 1, 158, 1, 3953, 0 },
1424  { 426, 1, 158, 1, 3953, 0 },
1425  { 1445, 128, 1, 0, 1216, 2 },
1426  { 217, 1, 233, 1, 1826, 0 },
1427  { 475, 1, 134, 1, 1826, 0 },
1428  { 679, 1, 134, 1, 1826, 0 },
1429  { 877, 1, 134, 1, 1826, 0 },
1430  { 241, 1, 1, 1, 3921, 0 },
1431  { 499, 1, 1, 1, 3921, 0 },
1432  { 700, 1, 1, 1, 3921, 0 },
1433  { 890, 1, 1, 1, 3921, 0 },
1434  { 1485, 1, 1, 1, 3921, 0 },
1435  { 1651, 1, 1, 1, 3921, 0 },
1436  { 1813, 1, 1, 1, 3921, 0 },
1437  { 1975, 1, 1, 1, 3921, 0 },
1438  { 2137, 1, 1, 1, 3921, 0 },
1439  { 2312, 1, 1, 1, 3921, 0 },
1440  { 54, 1, 1, 1, 3921, 0 },
1441  { 312, 1, 1, 1, 3921, 0 },
1442  { 570, 1, 1, 1, 3921, 0 },
1443  { 768, 1, 1, 1, 3921, 0 },
1444  { 958, 1, 1, 1, 3921, 0 },
1445  { 1553, 1, 1, 1, 3921, 0 },
1446  { 1715, 1, 1, 1, 3921, 0 },
1447  { 1877, 1, 1, 1, 3921, 0 },
1448  { 2039, 1, 1, 1, 3921, 0 },
1449  { 2198, 1, 1, 1, 3921, 0 },
1450  { 114, 1, 1, 1, 3921, 0 },
1451  { 372, 1, 1, 1, 3921, 0 },
1452  { 630, 1, 1, 1, 3921, 0 },
1453  { 828, 1, 1, 1, 3921, 0 },
1454  { 1018, 1, 1, 1, 3921, 0 },
1455  { 1613, 1, 1, 1, 3921, 0 },
1456  { 1775, 1, 1, 1, 3921, 0 },
1457  { 1937, 1, 1, 1, 3921, 0 },
1458  { 2099, 1, 1, 1, 3921, 0 },
1459  { 2274, 1, 1, 1, 3921, 0 },
1460  { 187, 1, 1, 1, 3921, 0 },
1461  { 445, 1, 1, 1, 3921, 0 },
1462  { 221, 1, 100, 1, 3921, 0 },
1463  { 479, 1, 100, 1, 3921, 0 },
1464  { 229, 1, 229, 1, 1794, 0 },
1465  { 487, 1, 126, 1, 1794, 0 },
1466  { 688, 1, 126, 1, 1794, 0 },
1467  { 881, 1, 126, 1, 1794, 0 },
1468  { 224, 1, 1, 1, 3889, 0 },
1469  { 482, 1, 1, 1, 3889, 0 },
1470  { 683, 1, 1, 1, 3889, 0 },
1471  { 2115, 1, 1, 1, 3889, 0 },
1472  { 2290, 1, 1, 1, 3889, 0 },
1473  { 27, 1, 1, 1, 3889, 0 },
1474  { 285, 1, 1, 1, 3889, 0 },
1475  { 543, 1, 1, 1, 3889, 0 },
1476  { 741, 1, 1, 1, 3889, 0 },
1477  { 931, 1, 1, 1, 3889, 0 },
1478  { 1526, 1, 1, 1, 3889, 0 },
1479  { 1692, 1, 1, 1, 3889, 0 },
1480  { 1854, 1, 1, 1, 3889, 0 },
1481  { 2016, 1, 1, 1, 3889, 0 },
1482  { 2175, 1, 1, 1, 3889, 0 },
1483  { 85, 1, 1, 1, 3889, 0 },
1484  { 343, 1, 1, 1, 3889, 0 },
1485  { 601, 1, 1, 1, 3889, 0 },
1486  { 799, 1, 1, 1, 3889, 0 },
1487  { 989, 1, 1, 1, 3889, 0 },
1488  { 1584, 1, 1, 1, 3889, 0 },
1489  { 1746, 1, 1, 1, 3889, 0 },
1490  { 1908, 1, 1, 1, 3889, 0 },
1491  { 2070, 1, 1, 1, 3889, 0 },
1492  { 2245, 1, 1, 1, 3889, 0 },
1493  { 158, 1, 1, 1, 3889, 0 },
1494  { 416, 1, 1, 1, 3889, 0 },
1495  { 233, 1, 1, 1, 3889, 0 },
1496  { 491, 1, 1, 1, 3889, 0 },
1497  { 692, 1, 1, 1, 3889, 0 },
1498  { 1425, 124, 1, 0, 1248, 2 },
1499  { 246, 1, 98, 1, 3857, 0 },
1500  { 504, 1, 98, 1, 3857, 0 },
1501  { 705, 1, 98, 1, 3857, 0 },
1502  { 895, 1, 98, 1, 3857, 0 },
1503  { 1490, 1, 98, 1, 3857, 0 },
1504  { 1656, 1, 98, 1, 3857, 0 },
1505  { 1818, 1, 98, 1, 3857, 0 },
1506  { 1980, 1, 98, 1, 3857, 0 },
1507  { 1451, 122, 1, 0, 1280, 2 },
1508  { 249, 1, 96, 1, 3825, 0 },
1509  { 507, 1, 96, 1, 3825, 0 },
1510  { 708, 1, 96, 1, 3825, 0 },
1511  { 898, 1, 96, 1, 3825, 0 },
1512  { 1493, 1, 96, 1, 3825, 0 },
1513  { 1659, 1, 96, 1, 3825, 0 },
1514  { 1821, 1, 96, 1, 3825, 0 },
1515  { 1983, 1, 96, 1, 3825, 0 },
1516  { 2142, 1, 96, 1, 3825, 0 },
1517  { 2317, 1, 96, 1, 3825, 0 },
1518  { 252, 1, 96, 1, 3825, 0 },
1519  { 510, 1, 96, 1, 3825, 0 },
1520  { 255, 92, 1, 8, 1425, 10 },
1521  { 513, 92, 1, 8, 1425, 10 },
1522  { 711, 92, 1, 8, 1425, 10 },
1523  { 901, 92, 1, 8, 1425, 10 },
1524  { 1496, 92, 1, 8, 1425, 10 },
1525  { 1662, 92, 1, 8, 1425, 10 },
1526  { 1824, 92, 1, 8, 1425, 10 },
1527  { 1986, 92, 1, 8, 1425, 10 },
1528  { 2145, 92, 1, 8, 1425, 10 },
1529  { 2320, 92, 1, 8, 1425, 10 },
1530  { 60, 92, 1, 8, 1425, 10 },
1531  { 318, 92, 1, 8, 1425, 10 },
1532  { 576, 92, 1, 8, 1425, 10 },
1533  { 774, 92, 1, 8, 1425, 10 },
1534  { 964, 92, 1, 8, 1425, 10 },
1535  { 1559, 92, 1, 8, 1425, 10 },
1536  { 1721, 92, 1, 8, 1425, 10 },
1537  { 1883, 92, 1, 8, 1425, 10 },
1538  { 2045, 92, 1, 8, 1425, 10 },
1539  { 2204, 92, 1, 8, 1425, 10 },
1540  { 120, 92, 1, 8, 1425, 10 },
1541  { 378, 92, 1, 8, 1425, 10 },
1542  { 636, 92, 1, 8, 1425, 10 },
1543  { 834, 92, 1, 8, 1425, 10 },
1544  { 1024, 92, 1, 8, 1425, 10 },
1545  { 1619, 92, 1, 8, 1425, 10 },
1546  { 1781, 92, 1, 8, 1425, 10 },
1547  { 1943, 92, 1, 8, 1425, 10 },
1548  { 2105, 92, 1, 8, 1425, 10 },
1549  { 2280, 92, 1, 8, 1425, 10 },
1550  { 193, 92, 1, 8, 1425, 10 },
1551  { 451, 92, 1, 8, 1425, 10 },
1552  { 1431, 118, 1, 0, 1921, 2 },
1553  { 1055, 118, 1, 0, 1921, 2 },
1554  { 1133, 118, 1, 0, 1921, 2 },
1555  { 1183, 118, 1, 0, 1921, 2 },
1556  { 1221, 118, 1, 0, 1921, 2 },
1557  { 1061, 130, 1, 12, 656, 10 },
1558  { 1068, 93, 159, 9, 1377, 10 },
1559  { 1139, 93, 159, 9, 1377, 10 },
1560  { 1189, 93, 159, 9, 1377, 10 },
1561  { 1227, 93, 159, 9, 1377, 10 },
1562  { 1259, 93, 159, 9, 1377, 10 },
1563  { 1291, 93, 159, 9, 1377, 10 },
1564  { 1323, 93, 159, 9, 1377, 10 },
1565  { 1355, 93, 159, 9, 1377, 10 },
1566  { 1387, 93, 159, 9, 1377, 10 },
1567  { 1413, 93, 159, 9, 1377, 10 },
1568  { 1034, 93, 159, 9, 1377, 10 },
1569  { 1112, 93, 159, 9, 1377, 10 },
1570  { 1169, 93, 159, 9, 1377, 10 },
1571  { 1207, 93, 159, 9, 1377, 10 },
1572  { 1245, 93, 159, 9, 1377, 10 },
1573  { 1277, 93, 159, 9, 1377, 10 },
1574  { 1309, 93, 159, 9, 1377, 10 },
1575  { 1341, 93, 159, 9, 1377, 10 },
1576  { 1373, 93, 159, 9, 1377, 10 },
1577  { 1399, 93, 159, 9, 1377, 10 },
1578  { 1041, 93, 159, 9, 1377, 10 },
1579  { 1119, 93, 159, 9, 1377, 10 },
1580  { 1176, 93, 159, 9, 1377, 10 },
1581  { 1214, 93, 159, 9, 1377, 10 },
1582  { 1252, 93, 159, 9, 1377, 10 },
1583  { 1284, 93, 159, 9, 1377, 10 },
1584  { 1316, 93, 159, 9, 1377, 10 },
1585  { 1348, 93, 159, 9, 1377, 10 },
1586  { 1380, 93, 159, 9, 1377, 10 },
1587  { 1406, 93, 159, 9, 1377, 10 },
1588  { 1048, 93, 159, 9, 1377, 10 },
1589  { 1126, 93, 159, 9, 1377, 10 },
1590  { 2208, 1, 116, 1, 1120, 0 },
1591  { 1074, 138, 235, 0, 1344, 2 },
1592  { 1081, 150, 1, 0, 2241, 2 },
1593  { 1145, 150, 1, 0, 2241, 2 },
1594  { 1087, 150, 231, 0, 1312, 2 },
1595  { 1094, 154, 1, 0, 2433, 2 },
1596  { 1151, 154, 1, 0, 2433, 2 },
1597  { 1195, 154, 1, 0, 2433, 2 },
1598  { 1233, 154, 1, 0, 2433, 2 },
1599  { 1265, 154, 1, 0, 2433, 2 },
1600  { 1297, 154, 1, 0, 2433, 2 },
1601  { 1329, 154, 1, 0, 2433, 2 },
1602  { 1361, 154, 1, 0, 2433, 2 },
1603  { 1100, 156, 1, 0, 2433, 2 },
1604  { 1157, 156, 1, 0, 2433, 2 },
1605  { 1201, 156, 1, 0, 2433, 2 },
1606  { 1239, 156, 1, 0, 2433, 2 },
1607  { 1271, 156, 1, 0, 2433, 2 },
1608  { 1303, 156, 1, 0, 2433, 2 },
1609  { 1335, 156, 1, 0, 2433, 2 },
1610  { 1367, 156, 1, 0, 2433, 2 },
1611  { 1393, 156, 1, 0, 2433, 2 },
1612  { 1419, 156, 1, 0, 2433, 2 },
1613  { 1106, 156, 1, 0, 2433, 2 },
1614  { 1163, 156, 1, 0, 2433, 2 },
1615};
1616
1617extern const MCPhysReg MipsRegUnitRoots[][2] = {
1618  { Mips::AT },
1619  { Mips::DSPCCond },
1620  { Mips::DSPCarry },
1621  { Mips::DSPEFI },
1622  { Mips::DSPOutFlag16_19 },
1623  { Mips::DSPOutFlag20 },
1624  { Mips::DSPOutFlag21 },
1625  { Mips::DSPOutFlag22 },
1626  { Mips::DSPOutFlag23 },
1627  { Mips::DSPPos },
1628  { Mips::DSPSCount },
1629  { Mips::FP },
1630  { Mips::GP },
1631  { Mips::MSAAccess },
1632  { Mips::MSACSR },
1633  { Mips::MSAIR },
1634  { Mips::MSAMap },
1635  { Mips::MSAModify },
1636  { Mips::MSARequest },
1637  { Mips::MSASave },
1638  { Mips::MSAUnmap },
1639  { Mips::PC },
1640  { Mips::RA },
1641  { Mips::SP },
1642  { Mips::ZERO },
1643  { Mips::A0 },
1644  { Mips::A1 },
1645  { Mips::A2 },
1646  { Mips::A3 },
1647  { Mips::LO0 },
1648  { Mips::HI0 },
1649  { Mips::LO1 },
1650  { Mips::HI1 },
1651  { Mips::LO2 },
1652  { Mips::HI2 },
1653  { Mips::LO3 },
1654  { Mips::HI3 },
1655  { Mips::COP00 },
1656  { Mips::COP01 },
1657  { Mips::COP02 },
1658  { Mips::COP03 },
1659  { Mips::COP04 },
1660  { Mips::COP05 },
1661  { Mips::COP06 },
1662  { Mips::COP07 },
1663  { Mips::COP08 },
1664  { Mips::COP09 },
1665  { Mips::COP20 },
1666  { Mips::COP21 },
1667  { Mips::COP22 },
1668  { Mips::COP23 },
1669  { Mips::COP24 },
1670  { Mips::COP25 },
1671  { Mips::COP26 },
1672  { Mips::COP27 },
1673  { Mips::COP28 },
1674  { Mips::COP29 },
1675  { Mips::COP30 },
1676  { Mips::COP31 },
1677  { Mips::COP32 },
1678  { Mips::COP33 },
1679  { Mips::COP34 },
1680  { Mips::COP35 },
1681  { Mips::COP36 },
1682  { Mips::COP37 },
1683  { Mips::COP38 },
1684  { Mips::COP39 },
1685  { Mips::COP010 },
1686  { Mips::COP011 },
1687  { Mips::COP012 },
1688  { Mips::COP013 },
1689  { Mips::COP014 },
1690  { Mips::COP015 },
1691  { Mips::COP016 },
1692  { Mips::COP017 },
1693  { Mips::COP018 },
1694  { Mips::COP019 },
1695  { Mips::COP020 },
1696  { Mips::COP021 },
1697  { Mips::COP022 },
1698  { Mips::COP023 },
1699  { Mips::COP024 },
1700  { Mips::COP025 },
1701  { Mips::COP026 },
1702  { Mips::COP027 },
1703  { Mips::COP028 },
1704  { Mips::COP029 },
1705  { Mips::COP030 },
1706  { Mips::COP031 },
1707  { Mips::COP210 },
1708  { Mips::COP211 },
1709  { Mips::COP212 },
1710  { Mips::COP213 },
1711  { Mips::COP214 },
1712  { Mips::COP215 },
1713  { Mips::COP216 },
1714  { Mips::COP217 },
1715  { Mips::COP218 },
1716  { Mips::COP219 },
1717  { Mips::COP220 },
1718  { Mips::COP221 },
1719  { Mips::COP222 },
1720  { Mips::COP223 },
1721  { Mips::COP224 },
1722  { Mips::COP225 },
1723  { Mips::COP226 },
1724  { Mips::COP227 },
1725  { Mips::COP228 },
1726  { Mips::COP229 },
1727  { Mips::COP230 },
1728  { Mips::COP231 },
1729  { Mips::COP310 },
1730  { Mips::COP311 },
1731  { Mips::COP312 },
1732  { Mips::COP313 },
1733  { Mips::COP314 },
1734  { Mips::COP315 },
1735  { Mips::COP316 },
1736  { Mips::COP317 },
1737  { Mips::COP318 },
1738  { Mips::COP319 },
1739  { Mips::COP320 },
1740  { Mips::COP321 },
1741  { Mips::COP322 },
1742  { Mips::COP323 },
1743  { Mips::COP324 },
1744  { Mips::COP325 },
1745  { Mips::COP326 },
1746  { Mips::COP327 },
1747  { Mips::COP328 },
1748  { Mips::COP329 },
1749  { Mips::COP330 },
1750  { Mips::COP331 },
1751  { Mips::F0 },
1752  { Mips::F1 },
1753  { Mips::F2 },
1754  { Mips::F3 },
1755  { Mips::F4 },
1756  { Mips::F5 },
1757  { Mips::F6 },
1758  { Mips::F7 },
1759  { Mips::F8 },
1760  { Mips::F9 },
1761  { Mips::F10 },
1762  { Mips::F11 },
1763  { Mips::F12 },
1764  { Mips::F13 },
1765  { Mips::F14 },
1766  { Mips::F15 },
1767  { Mips::F16 },
1768  { Mips::F17 },
1769  { Mips::F18 },
1770  { Mips::F19 },
1771  { Mips::F20 },
1772  { Mips::F21 },
1773  { Mips::F22 },
1774  { Mips::F23 },
1775  { Mips::F24 },
1776  { Mips::F25 },
1777  { Mips::F26 },
1778  { Mips::F27 },
1779  { Mips::F28 },
1780  { Mips::F29 },
1781  { Mips::F30 },
1782  { Mips::F31 },
1783  { Mips::FCC0 },
1784  { Mips::FCC1 },
1785  { Mips::FCC2 },
1786  { Mips::FCC3 },
1787  { Mips::FCC4 },
1788  { Mips::FCC5 },
1789  { Mips::FCC6 },
1790  { Mips::FCC7 },
1791  { Mips::FCR0 },
1792  { Mips::FCR1 },
1793  { Mips::FCR2 },
1794  { Mips::FCR3 },
1795  { Mips::FCR4 },
1796  { Mips::FCR5 },
1797  { Mips::FCR6 },
1798  { Mips::FCR7 },
1799  { Mips::FCR8 },
1800  { Mips::FCR9 },
1801  { Mips::FCR10 },
1802  { Mips::FCR11 },
1803  { Mips::FCR12 },
1804  { Mips::FCR13 },
1805  { Mips::FCR14 },
1806  { Mips::FCR15 },
1807  { Mips::FCR16 },
1808  { Mips::FCR17 },
1809  { Mips::FCR18 },
1810  { Mips::FCR19 },
1811  { Mips::FCR20 },
1812  { Mips::FCR21 },
1813  { Mips::FCR22 },
1814  { Mips::FCR23 },
1815  { Mips::FCR24 },
1816  { Mips::FCR25 },
1817  { Mips::FCR26 },
1818  { Mips::FCR27 },
1819  { Mips::FCR28 },
1820  { Mips::FCR29 },
1821  { Mips::FCR30 },
1822  { Mips::FCR31 },
1823  { Mips::F_HI0 },
1824  { Mips::F_HI1 },
1825  { Mips::F_HI2 },
1826  { Mips::F_HI3 },
1827  { Mips::F_HI4 },
1828  { Mips::F_HI5 },
1829  { Mips::F_HI6 },
1830  { Mips::F_HI7 },
1831  { Mips::F_HI8 },
1832  { Mips::F_HI9 },
1833  { Mips::F_HI10 },
1834  { Mips::F_HI11 },
1835  { Mips::F_HI12 },
1836  { Mips::F_HI13 },
1837  { Mips::F_HI14 },
1838  { Mips::F_HI15 },
1839  { Mips::F_HI16 },
1840  { Mips::F_HI17 },
1841  { Mips::F_HI18 },
1842  { Mips::F_HI19 },
1843  { Mips::F_HI20 },
1844  { Mips::F_HI21 },
1845  { Mips::F_HI22 },
1846  { Mips::F_HI23 },
1847  { Mips::F_HI24 },
1848  { Mips::F_HI25 },
1849  { Mips::F_HI26 },
1850  { Mips::F_HI27 },
1851  { Mips::F_HI28 },
1852  { Mips::F_HI29 },
1853  { Mips::F_HI30 },
1854  { Mips::F_HI31 },
1855  { Mips::HWR0 },
1856  { Mips::HWR1 },
1857  { Mips::HWR2 },
1858  { Mips::HWR3 },
1859  { Mips::HWR4 },
1860  { Mips::HWR5 },
1861  { Mips::HWR6 },
1862  { Mips::HWR7 },
1863  { Mips::HWR8 },
1864  { Mips::HWR9 },
1865  { Mips::HWR10 },
1866  { Mips::HWR11 },
1867  { Mips::HWR12 },
1868  { Mips::HWR13 },
1869  { Mips::HWR14 },
1870  { Mips::HWR15 },
1871  { Mips::HWR16 },
1872  { Mips::HWR17 },
1873  { Mips::HWR18 },
1874  { Mips::HWR19 },
1875  { Mips::HWR20 },
1876  { Mips::HWR21 },
1877  { Mips::HWR22 },
1878  { Mips::HWR23 },
1879  { Mips::HWR24 },
1880  { Mips::HWR25 },
1881  { Mips::HWR26 },
1882  { Mips::HWR27 },
1883  { Mips::HWR28 },
1884  { Mips::HWR29 },
1885  { Mips::HWR30 },
1886  { Mips::HWR31 },
1887  { Mips::K0 },
1888  { Mips::K1 },
1889  { Mips::MPL0 },
1890  { Mips::MPL1 },
1891  { Mips::MPL2 },
1892  { Mips::MSA8 },
1893  { Mips::MSA9 },
1894  { Mips::MSA10 },
1895  { Mips::MSA11 },
1896  { Mips::MSA12 },
1897  { Mips::MSA13 },
1898  { Mips::MSA14 },
1899  { Mips::MSA15 },
1900  { Mips::MSA16 },
1901  { Mips::MSA17 },
1902  { Mips::MSA18 },
1903  { Mips::MSA19 },
1904  { Mips::MSA20 },
1905  { Mips::MSA21 },
1906  { Mips::MSA22 },
1907  { Mips::MSA23 },
1908  { Mips::MSA24 },
1909  { Mips::MSA25 },
1910  { Mips::MSA26 },
1911  { Mips::MSA27 },
1912  { Mips::MSA28 },
1913  { Mips::MSA29 },
1914  { Mips::MSA30 },
1915  { Mips::MSA31 },
1916  { Mips::P0 },
1917  { Mips::P1 },
1918  { Mips::P2 },
1919  { Mips::S0 },
1920  { Mips::S1 },
1921  { Mips::S2 },
1922  { Mips::S3 },
1923  { Mips::S4 },
1924  { Mips::S5 },
1925  { Mips::S6 },
1926  { Mips::S7 },
1927  { Mips::T0 },
1928  { Mips::T1 },
1929  { Mips::T2 },
1930  { Mips::T3 },
1931  { Mips::T4 },
1932  { Mips::T5 },
1933  { Mips::T6 },
1934  { Mips::T7 },
1935  { Mips::T8 },
1936  { Mips::T9 },
1937  { Mips::V0 },
1938  { Mips::V1 },
1939};
1940
1941namespace {     // Register classes...
1942  // MSA128F16 Register Class...
1943  const MCPhysReg MSA128F16[] = {
1944    Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31,
1945  };
1946
1947  // MSA128F16 Bit set.
1948  const uint8_t MSA128F16Bits[] = {
1949    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
1950  };
1951
1952  // CCR Register Class...
1953  const MCPhysReg CCR[] = {
1954    Mips::FCR0, Mips::FCR1, Mips::FCR2, Mips::FCR3, Mips::FCR4, Mips::FCR5, Mips::FCR6, Mips::FCR7, Mips::FCR8, Mips::FCR9, Mips::FCR10, Mips::FCR11, Mips::FCR12, Mips::FCR13, Mips::FCR14, Mips::FCR15, Mips::FCR16, Mips::FCR17, Mips::FCR18, Mips::FCR19, Mips::FCR20, Mips::FCR21, Mips::FCR22, Mips::FCR23, Mips::FCR24, Mips::FCR25, Mips::FCR26, Mips::FCR27, Mips::FCR28, Mips::FCR29, Mips::FCR30, Mips::FCR31,
1955  };
1956
1957  // CCR Bit set.
1958  const uint8_t CCRBits[] = {
1959    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
1960  };
1961
1962  // COP0 Register Class...
1963  const MCPhysReg COP0[] = {
1964    Mips::COP00, Mips::COP01, Mips::COP02, Mips::COP03, Mips::COP04, Mips::COP05, Mips::COP06, Mips::COP07, Mips::COP08, Mips::COP09, Mips::COP010, Mips::COP011, Mips::COP012, Mips::COP013, Mips::COP014, Mips::COP015, Mips::COP016, Mips::COP017, Mips::COP018, Mips::COP019, Mips::COP020, Mips::COP021, Mips::COP022, Mips::COP023, Mips::COP024, Mips::COP025, Mips::COP026, Mips::COP027, Mips::COP028, Mips::COP029, Mips::COP030, Mips::COP031,
1965  };
1966
1967  // COP0 Bit set.
1968  const uint8_t COP0Bits[] = {
1969    0x00, 0x00, 0x00, 0x80, 0xff, 0x01, 0x00, 0xe0, 0xff, 0xff, 0x07,
1970  };
1971
1972  // COP2 Register Class...
1973  const MCPhysReg COP2[] = {
1974    Mips::COP20, Mips::COP21, Mips::COP22, Mips::COP23, Mips::COP24, Mips::COP25, Mips::COP26, Mips::COP27, Mips::COP28, Mips::COP29, Mips::COP210, Mips::COP211, Mips::COP212, Mips::COP213, Mips::COP214, Mips::COP215, Mips::COP216, Mips::COP217, Mips::COP218, Mips::COP219, Mips::COP220, Mips::COP221, Mips::COP222, Mips::COP223, Mips::COP224, Mips::COP225, Mips::COP226, Mips::COP227, Mips::COP228, Mips::COP229, Mips::COP230, Mips::COP231,
1975  };
1976
1977  // COP2 Bit set.
1978  const uint8_t COP2Bits[] = {
1979    0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x07, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0x01,
1980  };
1981
1982  // COP3 Register Class...
1983  const MCPhysReg COP3[] = {
1984    Mips::COP30, Mips::COP31, Mips::COP32, Mips::COP33, Mips::COP34, Mips::COP35, Mips::COP36, Mips::COP37, Mips::COP38, Mips::COP39, Mips::COP310, Mips::COP311, Mips::COP312, Mips::COP313, Mips::COP314, Mips::COP315, Mips::COP316, Mips::COP317, Mips::COP318, Mips::COP319, Mips::COP320, Mips::COP321, Mips::COP322, Mips::COP323, Mips::COP324, Mips::COP325, Mips::COP326, Mips::COP327, Mips::COP328, Mips::COP329, Mips::COP330, Mips::COP331,
1985  };
1986
1987  // COP3 Bit set.
1988  const uint8_t COP3Bits[] = {
1989    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x7f,
1990  };
1991
1992  // DSPR Register Class...
1993  const MCPhysReg DSPR[] = {
1994    Mips::ZERO, Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7, Mips::T8, Mips::T9, Mips::K0, Mips::K1, Mips::GP, Mips::SP, Mips::FP, Mips::RA,
1995  };
1996
1997  // DSPR Bit set.
1998  const uint8_t DSPRBits[] = {
1999    0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0xc0, 0xbf, 0xff, 0x07,
2000  };
2001
2002  // FGR32 Register Class...
2003  const MCPhysReg FGR32[] = {
2004    Mips::F0, Mips::F1, Mips::F2, Mips::F3, Mips::F4, Mips::F5, Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11, Mips::F12, Mips::F13, Mips::F14, Mips::F15, Mips::F16, Mips::F17, Mips::F18, Mips::F19, Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24, Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29, Mips::F30, Mips::F31,
2005  };
2006
2007  // FGR32 Bit set.
2008  const uint8_t FGR32Bits[] = {
2009    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
2010  };
2011
2012  // FGRCC Register Class...
2013  const MCPhysReg FGRCC[] = {
2014    Mips::F0, Mips::F1, Mips::F2, Mips::F3, Mips::F4, Mips::F5, Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11, Mips::F12, Mips::F13, Mips::F14, Mips::F15, Mips::F16, Mips::F17, Mips::F18, Mips::F19, Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24, Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29, Mips::F30, Mips::F31,
2015  };
2016
2017  // FGRCC Bit set.
2018  const uint8_t FGRCCBits[] = {
2019    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
2020  };
2021
2022  // GPR32 Register Class...
2023  const MCPhysReg GPR32[] = {
2024    Mips::ZERO, Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7, Mips::T8, Mips::T9, Mips::K0, Mips::K1, Mips::GP, Mips::SP, Mips::FP, Mips::RA,
2025  };
2026
2027  // GPR32 Bit set.
2028  const uint8_t GPR32Bits[] = {
2029    0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0xc0, 0xbf, 0xff, 0x07,
2030  };
2031
2032  // HWRegs Register Class...
2033  const MCPhysReg HWRegs[] = {
2034    Mips::HWR0, Mips::HWR1, Mips::HWR2, Mips::HWR3, Mips::HWR4, Mips::HWR5, Mips::HWR6, Mips::HWR7, Mips::HWR8, Mips::HWR9, Mips::HWR10, Mips::HWR11, Mips::HWR12, Mips::HWR13, Mips::HWR14, Mips::HWR15, Mips::HWR16, Mips::HWR17, Mips::HWR18, Mips::HWR19, Mips::HWR20, Mips::HWR21, Mips::HWR22, Mips::HWR23, Mips::HWR24, Mips::HWR25, Mips::HWR26, Mips::HWR27, Mips::HWR28, Mips::HWR29, Mips::HWR30, Mips::HWR31,
2035  };
2036
2037  // HWRegs Bit set.
2038  const uint8_t HWRegsBits[] = {
2039    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
2040  };
2041
2042  // MSACtrl Register Class...
2043  const MCPhysReg MSACtrl[] = {
2044    Mips::MSAIR, Mips::MSACSR, Mips::MSAAccess, Mips::MSASave, Mips::MSAModify, Mips::MSARequest, Mips::MSAMap, Mips::MSAUnmap, Mips::MSA8, Mips::MSA9, Mips::MSA10, Mips::MSA11, Mips::MSA12, Mips::MSA13, Mips::MSA14, Mips::MSA15, Mips::MSA16, Mips::MSA17, Mips::MSA18, Mips::MSA19, Mips::MSA20, Mips::MSA21, Mips::MSA22, Mips::MSA23, Mips::MSA24, Mips::MSA25, Mips::MSA26, Mips::MSA27, Mips::MSA28, Mips::MSA29, Mips::MSA30, Mips::MSA31,
2045  };
2046
2047  // MSACtrl Bit set.
2048  const uint8_t MSACtrlBits[] = {
2049    0x00, 0xfc, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0x03,
2050  };
2051
2052  // GPR32NONZERO Register Class...
2053  const MCPhysReg GPR32NONZERO[] = {
2054    Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7, Mips::T8, Mips::T9, Mips::K0, Mips::K1, Mips::GP, Mips::SP, Mips::FP, Mips::RA,
2055  };
2056
2057  // GPR32NONZERO Bit set.
2058  const uint8_t GPR32NONZEROBits[] = {
2059    0x02, 0x03, 0xd8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0xc0, 0xbf, 0xff, 0x07,
2060  };
2061
2062  // CPU16RegsPlusSP Register Class...
2063  const MCPhysReg CPU16RegsPlusSP[] = {
2064    Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::S0, Mips::S1, Mips::SP,
2065  };
2066
2067  // CPU16RegsPlusSP Bit set.
2068  const uint8_t CPU16RegsPlusSPBits[] = {
2069    0x00, 0x00, 0xd0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06,
2070  };
2071
2072  // CPU16Regs Register Class...
2073  const MCPhysReg CPU16Regs[] = {
2074    Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::S0, Mips::S1,
2075  };
2076
2077  // CPU16Regs Bit set.
2078  const uint8_t CPU16RegsBits[] = {
2079    0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06,
2080  };
2081
2082  // FCC Register Class...
2083  const MCPhysReg FCC[] = {
2084    Mips::FCC0, Mips::FCC1, Mips::FCC2, Mips::FCC3, Mips::FCC4, Mips::FCC5, Mips::FCC6, Mips::FCC7,
2085  };
2086
2087  // FCC Bit set.
2088  const uint8_t FCCBits[] = {
2089    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,
2090  };
2091
2092  // GPRMM16 Register Class...
2093  const MCPhysReg GPRMM16[] = {
2094    Mips::S0, Mips::S1, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3,
2095  };
2096
2097  // GPRMM16 Bit set.
2098  const uint8_t GPRMM16Bits[] = {
2099    0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06,
2100  };
2101
2102  // GPRMM16MoveP Register Class...
2103  const MCPhysReg GPRMM16MoveP[] = {
2104    Mips::ZERO, Mips::S1, Mips::V0, Mips::V1, Mips::S0, Mips::S2, Mips::S3, Mips::S4,
2105  };
2106
2107  // GPRMM16MoveP Bit set.
2108  const uint8_t GPRMM16MovePBits[] = {
2109    0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x06,
2110  };
2111
2112  // GPRMM16Zero Register Class...
2113  const MCPhysReg GPRMM16Zero[] = {
2114    Mips::ZERO, Mips::S1, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3,
2115  };
2116
2117  // GPRMM16Zero Bit set.
2118  const uint8_t GPRMM16ZeroBits[] = {
2119    0x00, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06,
2120  };
2121
2122  // CPU16Regs_and_GPRMM16Zero Register Class...
2123  const MCPhysReg CPU16Regs_and_GPRMM16Zero[] = {
2124    Mips::S1, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3,
2125  };
2126
2127  // CPU16Regs_and_GPRMM16Zero Bit set.
2128  const uint8_t CPU16Regs_and_GPRMM16ZeroBits[] = {
2129    0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06,
2130  };
2131
2132  // GPR32NONZERO_and_GPRMM16MoveP Register Class...
2133  const MCPhysReg GPR32NONZERO_and_GPRMM16MoveP[] = {
2134    Mips::S1, Mips::V0, Mips::V1, Mips::S0, Mips::S2, Mips::S3, Mips::S4,
2135  };
2136
2137  // GPR32NONZERO_and_GPRMM16MoveP Bit set.
2138  const uint8_t GPR32NONZERO_and_GPRMM16MovePBits[] = {
2139    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x06,
2140  };
2141
2142  // GPRMM16MovePPairSecond Register Class...
2143  const MCPhysReg GPRMM16MovePPairSecond[] = {
2144    Mips::A1, Mips::A2, Mips::A3, Mips::S5, Mips::S6,
2145  };
2146
2147  // GPRMM16MovePPairSecond Bit set.
2148  const uint8_t GPRMM16MovePPairSecondBits[] = {
2149    0x00, 0x00, 0x80, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18,
2150  };
2151
2152  // CPU16Regs_and_GPRMM16MoveP Register Class...
2153  const MCPhysReg CPU16Regs_and_GPRMM16MoveP[] = {
2154    Mips::S1, Mips::V0, Mips::V1, Mips::S0,
2155  };
2156
2157  // CPU16Regs_and_GPRMM16MoveP Bit set.
2158  const uint8_t CPU16Regs_and_GPRMM16MovePBits[] = {
2159    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06,
2160  };
2161
2162  // GPRMM16MoveP_and_GPRMM16Zero Register Class...
2163  const MCPhysReg GPRMM16MoveP_and_GPRMM16Zero[] = {
2164    Mips::ZERO, Mips::S1, Mips::V0, Mips::V1,
2165  };
2166
2167  // GPRMM16MoveP_and_GPRMM16Zero Bit set.
2168  const uint8_t GPRMM16MoveP_and_GPRMM16ZeroBits[] = {
2169    0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06,
2170  };
2171
2172  // HI32DSP Register Class...
2173  const MCPhysReg HI32DSP[] = {
2174    Mips::HI0, Mips::HI1, Mips::HI2, Mips::HI3,
2175  };
2176
2177  // HI32DSP Bit set.
2178  const uint8_t HI32DSPBits[] = {
2179    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01,
2180  };
2181
2182  // LO32DSP Register Class...
2183  const MCPhysReg LO32DSP[] = {
2184    Mips::LO0, Mips::LO1, Mips::LO2, Mips::LO3,
2185  };
2186
2187  // LO32DSP Bit set.
2188  const uint8_t LO32DSPBits[] = {
2189    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78,
2190  };
2191
2192  // CPU16Regs_and_GPRMM16MovePPairSecond Register Class...
2193  const MCPhysReg CPU16Regs_and_GPRMM16MovePPairSecond[] = {
2194    Mips::A1, Mips::A2, Mips::A3,
2195  };
2196
2197  // CPU16Regs_and_GPRMM16MovePPairSecond Bit set.
2198  const uint8_t CPU16Regs_and_GPRMM16MovePPairSecondBits[] = {
2199    0x00, 0x00, 0x80, 0x03,
2200  };
2201
2202  // GPRMM16MovePPairFirst Register Class...
2203  const MCPhysReg GPRMM16MovePPairFirst[] = {
2204    Mips::A0, Mips::A1, Mips::A2,
2205  };
2206
2207  // GPRMM16MovePPairFirst Bit set.
2208  const uint8_t GPRMM16MovePPairFirstBits[] = {
2209    0x00, 0x00, 0xc0, 0x01,
2210  };
2211
2212  // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Register Class...
2213  const MCPhysReg GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero[] = {
2214    Mips::S1, Mips::V0, Mips::V1,
2215  };
2216
2217  // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Bit set.
2218  const uint8_t GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits[] = {
2219    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06,
2220  };
2221
2222  // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond Register Class...
2223  const MCPhysReg GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond[] = {
2224    Mips::A1, Mips::A2,
2225  };
2226
2227  // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond Bit set.
2228  const uint8_t GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits[] = {
2229    0x00, 0x00, 0x80, 0x01,
2230  };
2231
2232  // CPURAReg Register Class...
2233  const MCPhysReg CPURAReg[] = {
2234    Mips::RA,
2235  };
2236
2237  // CPURAReg Bit set.
2238  const uint8_t CPURARegBits[] = {
2239    0x00, 0x00, 0x08,
2240  };
2241
2242  // CPUSPReg Register Class...
2243  const MCPhysReg CPUSPReg[] = {
2244    Mips::SP,
2245  };
2246
2247  // CPUSPReg Bit set.
2248  const uint8_t CPUSPRegBits[] = {
2249    0x00, 0x00, 0x10,
2250  };
2251
2252  // DSPCC Register Class...
2253  const MCPhysReg DSPCC[] = {
2254    Mips::DSPCCond,
2255  };
2256
2257  // DSPCC Bit set.
2258  const uint8_t DSPCCBits[] = {
2259    0x04,
2260  };
2261
2262  // GP32 Register Class...
2263  const MCPhysReg GP32[] = {
2264    Mips::GP,
2265  };
2266
2267  // GP32 Bit set.
2268  const uint8_t GP32Bits[] = {
2269    0x00, 0x02,
2270  };
2271
2272  // GPR32ZERO Register Class...
2273  const MCPhysReg GPR32ZERO[] = {
2274    Mips::ZERO,
2275  };
2276
2277  // GPR32ZERO Bit set.
2278  const uint8_t GPR32ZEROBits[] = {
2279    0x00, 0x00, 0x20,
2280  };
2281
2282  // HI32 Register Class...
2283  const MCPhysReg HI32[] = {
2284    Mips::HI0,
2285  };
2286
2287  // HI32 Bit set.
2288  const uint8_t HI32Bits[] = {
2289    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
2290  };
2291
2292  // LO32 Register Class...
2293  const MCPhysReg LO32[] = {
2294    Mips::LO0,
2295  };
2296
2297  // LO32 Bit set.
2298  const uint8_t LO32Bits[] = {
2299    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
2300  };
2301
2302  // SP32 Register Class...
2303  const MCPhysReg SP32[] = {
2304    Mips::SP,
2305  };
2306
2307  // SP32 Bit set.
2308  const uint8_t SP32Bits[] = {
2309    0x00, 0x00, 0x10,
2310  };
2311
2312  // FGR64 Register Class...
2313  const MCPhysReg FGR64[] = {
2314    Mips::D0_64, Mips::D1_64, Mips::D2_64, Mips::D3_64, Mips::D4_64, Mips::D5_64, Mips::D6_64, Mips::D7_64, Mips::D8_64, Mips::D9_64, Mips::D10_64, Mips::D11_64, Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64, Mips::D20_64, Mips::D21_64, Mips::D22_64, Mips::D23_64, Mips::D24_64, Mips::D25_64, Mips::D26_64, Mips::D27_64, Mips::D28_64, Mips::D29_64, Mips::D30_64, Mips::D31_64,
2315  };
2316
2317  // FGR64 Bit set.
2318  const uint8_t FGR64Bits[] = {
2319    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
2320  };
2321
2322  // GPR64 Register Class...
2323  const MCPhysReg GPR64[] = {
2324    Mips::ZERO_64, Mips::AT_64, Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64, Mips::T4_64, Mips::T5_64, Mips::T6_64, Mips::T7_64, Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64, Mips::S4_64, Mips::S5_64, Mips::S6_64, Mips::S7_64, Mips::T8_64, Mips::T9_64, Mips::K0_64, Mips::K1_64, Mips::GP_64, Mips::SP_64, Mips::FP_64, Mips::RA_64,
2325  };
2326
2327  // GPR64 Bit set.
2328  const uint8_t GPR64Bits[] = {
2329    0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x00, 0xd8, 0xff, 0xff, 0x03,
2330  };
2331
2332  // GPR64_with_sub_32_in_GPR32NONZERO Register Class...
2333  const MCPhysReg GPR64_with_sub_32_in_GPR32NONZERO[] = {
2334    Mips::AT_64, Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64, Mips::T4_64, Mips::T5_64, Mips::T6_64, Mips::T7_64, Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64, Mips::S4_64, Mips::S5_64, Mips::S6_64, Mips::S7_64, Mips::T8_64, Mips::T9_64, Mips::K0_64, Mips::K1_64, Mips::GP_64, Mips::SP_64, Mips::FP_64, Mips::RA_64,
2335  };
2336
2337  // GPR64_with_sub_32_in_GPR32NONZERO Bit set.
2338  const uint8_t GPR64_with_sub_32_in_GPR32NONZEROBits[] = {
2339    0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xd8, 0xff, 0xff, 0x03,
2340  };
2341
2342  // AFGR64 Register Class...
2343  const MCPhysReg AFGR64[] = {
2344    Mips::D0, Mips::D1, Mips::D2, Mips::D3, Mips::D4, Mips::D5, Mips::D6, Mips::D7, Mips::D8, Mips::D9, Mips::D10, Mips::D11, Mips::D12, Mips::D13, Mips::D14, Mips::D15,
2345  };
2346
2347  // AFGR64 Bit set.
2348  const uint8_t AFGR64Bits[] = {
2349    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
2350  };
2351
2352  // GPR64_with_sub_32_in_CPU16RegsPlusSP Register Class...
2353  const MCPhysReg GPR64_with_sub_32_in_CPU16RegsPlusSP[] = {
2354    Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S0_64, Mips::S1_64, Mips::SP_64,
2355  };
2356
2357  // GPR64_with_sub_32_in_CPU16RegsPlusSP Bit set.
2358  const uint8_t GPR64_with_sub_32_in_CPU16RegsPlusSPBits[] = {
2359    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03,
2360  };
2361
2362  // GPR64_with_sub_32_in_CPU16Regs Register Class...
2363  const MCPhysReg GPR64_with_sub_32_in_CPU16Regs[] = {
2364    Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S0_64, Mips::S1_64,
2365  };
2366
2367  // GPR64_with_sub_32_in_CPU16Regs Bit set.
2368  const uint8_t GPR64_with_sub_32_in_CPU16RegsBits[] = {
2369    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03,
2370  };
2371
2372  // GPR64_with_sub_32_in_GPRMM16MoveP Register Class...
2373  const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP[] = {
2374    Mips::ZERO_64, Mips::V0_64, Mips::V1_64, Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64, Mips::S4_64,
2375  };
2376
2377  // GPR64_with_sub_32_in_GPRMM16MoveP Bit set.
2378  const uint8_t GPR64_with_sub_32_in_GPRMM16MovePBits[] = {
2379    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x03,
2380  };
2381
2382  // GPR64_with_sub_32_in_GPRMM16Zero Register Class...
2383  const MCPhysReg GPR64_with_sub_32_in_GPRMM16Zero[] = {
2384    Mips::ZERO_64, Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S1_64,
2385  };
2386
2387  // GPR64_with_sub_32_in_GPRMM16Zero Bit set.
2388  const uint8_t GPR64_with_sub_32_in_GPRMM16ZeroBits[] = {
2389    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03,
2390  };
2391
2392  // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero Register Class...
2393  const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero[] = {
2394    Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S1_64,
2395  };
2396
2397  // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero Bit set.
2398  const uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits[] = {
2399    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03,
2400  };
2401
2402  // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP Register Class...
2403  const MCPhysReg GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP[] = {
2404    Mips::V0_64, Mips::V1_64, Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64, Mips::S4_64,
2405  };
2406
2407  // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP Bit set.
2408  const uint8_t GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePBits[] = {
2409    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x03,
2410  };
2411
2412  // GPR64_with_sub_32_in_GPRMM16MovePPairSecond Register Class...
2413  const MCPhysReg GPR64_with_sub_32_in_GPRMM16MovePPairSecond[] = {
2414    Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S5_64, Mips::S6_64,
2415  };
2416
2417  // GPR64_with_sub_32_in_GPRMM16MovePPairSecond Bit set.
2418  const uint8_t GPR64_with_sub_32_in_GPRMM16MovePPairSecondBits[] = {
2419    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18,
2420  };
2421
2422  // ACC64DSP Register Class...
2423  const MCPhysReg ACC64DSP[] = {
2424    Mips::AC0, Mips::AC1, Mips::AC2, Mips::AC3,
2425  };
2426
2427  // ACC64DSP Bit set.
2428  const uint8_t ACC64DSPBits[] = {
2429    0x00, 0x00, 0x00, 0x3c,
2430  };
2431
2432  // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP Register Class...
2433  const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP[] = {
2434    Mips::V0_64, Mips::V1_64, Mips::S0_64, Mips::S1_64,
2435  };
2436
2437  // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP Bit set.
2438  const uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits[] = {
2439    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03,
2440  };
2441
2442  // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero Register Class...
2443  const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero[] = {
2444    Mips::ZERO_64, Mips::V0_64, Mips::V1_64, Mips::S1_64,
2445  };
2446
2447  // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero Bit set.
2448  const uint8_t GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits[] = {
2449    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03,
2450  };
2451
2452  // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond Register Class...
2453  const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond[] = {
2454    Mips::A1_64, Mips::A2_64, Mips::A3_64,
2455  };
2456
2457  // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond Bit set.
2458  const uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondBits[] = {
2459    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0,
2460  };
2461
2462  // GPR64_with_sub_32_in_GPRMM16MovePPairFirst Register Class...
2463  const MCPhysReg GPR64_with_sub_32_in_GPRMM16MovePPairFirst[] = {
2464    Mips::A0_64, Mips::A1_64, Mips::A2_64,
2465  };
2466
2467  // GPR64_with_sub_32_in_GPRMM16MovePPairFirst Bit set.
2468  const uint8_t GPR64_with_sub_32_in_GPRMM16MovePPairFirstBits[] = {
2469    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70,
2470  };
2471
2472  // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Register Class...
2473  const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero[] = {
2474    Mips::V0_64, Mips::V1_64, Mips::S1_64,
2475  };
2476
2477  // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Bit set.
2478  const uint8_t GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits[] = {
2479    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03,
2480  };
2481
2482  // OCTEON_MPL Register Class...
2483  const MCPhysReg OCTEON_MPL[] = {
2484    Mips::MPL0, Mips::MPL1, Mips::MPL2,
2485  };
2486
2487  // OCTEON_MPL Bit set.
2488  const uint8_t OCTEON_MPLBits[] = {
2489    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x03,
2490  };
2491
2492  // OCTEON_P Register Class...
2493  const MCPhysReg OCTEON_P[] = {
2494    Mips::P0, Mips::P1, Mips::P2,
2495  };
2496
2497  // OCTEON_P Bit set.
2498  const uint8_t OCTEON_PBits[] = {
2499    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c,
2500  };
2501
2502  // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond Register Class...
2503  const MCPhysReg GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond[] = {
2504    Mips::A1_64, Mips::A2_64,
2505  };
2506
2507  // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond Bit set.
2508  const uint8_t GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits[] = {
2509    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60,
2510  };
2511
2512  // ACC64 Register Class...
2513  const MCPhysReg ACC64[] = {
2514    Mips::AC0,
2515  };
2516
2517  // ACC64 Bit set.
2518  const uint8_t ACC64Bits[] = {
2519    0x00, 0x00, 0x00, 0x04,
2520  };
2521
2522  // GP64 Register Class...
2523  const MCPhysReg GP64[] = {
2524    Mips::GP_64,
2525  };
2526
2527  // GP64 Bit set.
2528  const uint8_t GP64Bits[] = {
2529    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
2530  };
2531
2532  // GPR64_with_sub_32_in_CPURAReg Register Class...
2533  const MCPhysReg GPR64_with_sub_32_in_CPURAReg[] = {
2534    Mips::RA_64,
2535  };
2536
2537  // GPR64_with_sub_32_in_CPURAReg Bit set.
2538  const uint8_t GPR64_with_sub_32_in_CPURARegBits[] = {
2539    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
2540  };
2541
2542  // GPR64_with_sub_32_in_GPR32ZERO Register Class...
2543  const MCPhysReg GPR64_with_sub_32_in_GPR32ZERO[] = {
2544    Mips::ZERO_64,
2545  };
2546
2547  // GPR64_with_sub_32_in_GPR32ZERO Bit set.
2548  const uint8_t GPR64_with_sub_32_in_GPR32ZEROBits[] = {
2549    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
2550  };
2551
2552  // HI64 Register Class...
2553  const MCPhysReg HI64[] = {
2554    Mips::HI0_64,
2555  };
2556
2557  // HI64 Bit set.
2558  const uint8_t HI64Bits[] = {
2559    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,
2560  };
2561
2562  // LO64 Register Class...
2563  const MCPhysReg LO64[] = {
2564    Mips::LO0_64,
2565  };
2566
2567  // LO64 Bit set.
2568  const uint8_t LO64Bits[] = {
2569    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
2570  };
2571
2572  // SP64 Register Class...
2573  const MCPhysReg SP64[] = {
2574    Mips::SP_64,
2575  };
2576
2577  // SP64 Bit set.
2578  const uint8_t SP64Bits[] = {
2579    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
2580  };
2581
2582  // MSA128B Register Class...
2583  const MCPhysReg MSA128B[] = {
2584    Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31,
2585  };
2586
2587  // MSA128B Bit set.
2588  const uint8_t MSA128BBits[] = {
2589    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
2590  };
2591
2592  // MSA128D Register Class...
2593  const MCPhysReg MSA128D[] = {
2594    Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31,
2595  };
2596
2597  // MSA128D Bit set.
2598  const uint8_t MSA128DBits[] = {
2599    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
2600  };
2601
2602  // MSA128H Register Class...
2603  const MCPhysReg MSA128H[] = {
2604    Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31,
2605  };
2606
2607  // MSA128H Bit set.
2608  const uint8_t MSA128HBits[] = {
2609    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
2610  };
2611
2612  // MSA128W Register Class...
2613  const MCPhysReg MSA128W[] = {
2614    Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31,
2615  };
2616
2617  // MSA128W Bit set.
2618  const uint8_t MSA128WBits[] = {
2619    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
2620  };
2621
2622  // MSA128WEvens Register Class...
2623  const MCPhysReg MSA128WEvens[] = {
2624    Mips::W0, Mips::W2, Mips::W4, Mips::W6, Mips::W8, Mips::W10, Mips::W12, Mips::W14, Mips::W16, Mips::W18, Mips::W20, Mips::W22, Mips::W24, Mips::W26, Mips::W28, Mips::W30,
2625  };
2626
2627  // MSA128WEvens Bit set.
2628  const uint8_t MSA128WEvensBits[] = {
2629    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa8, 0xaa, 0xaa, 0xaa, 0x02,
2630  };
2631
2632  // ACC128 Register Class...
2633  const MCPhysReg ACC128[] = {
2634    Mips::AC0_64,
2635  };
2636
2637  // ACC128 Bit set.
2638  const uint8_t ACC128Bits[] = {
2639    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
2640  };
2641
2642} // end anonymous namespace
2643
2644extern const char MipsRegClassStrings[] = {
2645  /* 0 */ 'C', 'O', 'P', '0', 0,
2646  /* 5 */ 'H', 'I', '3', '2', 0,
2647  /* 10 */ 'L', 'O', '3', '2', 0,
2648  /* 15 */ 'G', 'P', '3', '2', 0,
2649  /* 20 */ 'S', 'P', '3', '2', 0,
2650  /* 25 */ 'F', 'G', 'R', '3', '2', 0,
2651  /* 31 */ 'G', 'P', 'R', '3', '2', 0,
2652  /* 37 */ 'C', 'O', 'P', '2', 0,
2653  /* 42 */ 'C', 'O', 'P', '3', 0,
2654  /* 47 */ 'A', 'C', 'C', '6', '4', 0,
2655  /* 53 */ 'H', 'I', '6', '4', 0,
2656  /* 58 */ 'L', 'O', '6', '4', 0,
2657  /* 63 */ 'G', 'P', '6', '4', 0,
2658  /* 68 */ 'S', 'P', '6', '4', 0,
2659  /* 73 */ 'A', 'F', 'G', 'R', '6', '4', 0,
2660  /* 80 */ 'G', 'P', 'R', '6', '4', 0,
2661  /* 86 */ 'M', 'S', 'A', '1', '2', '8', 'F', '1', '6', 0,
2662  /* 96 */ 'G', 'P', 'R', 'M', 'M', '1', '6', 0,
2663  /* 104 */ 'A', 'C', 'C', '1', '2', '8', 0,
2664  /* 111 */ 'M', 'S', 'A', '1', '2', '8', 'B', 0,
2665  /* 119 */ 'F', 'C', 'C', 0,
2666  /* 123 */ 'D', 'S', 'P', 'C', 'C', 0,
2667  /* 129 */ 'F', 'G', 'R', 'C', 'C', 0,
2668  /* 135 */ 'M', 'S', 'A', '1', '2', '8', 'D', 0,
2669  /* 143 */ 'M', 'S', 'A', '1', '2', '8', 'H', 0,
2670  /* 151 */ 'O', 'C', 'T', 'E', 'O', 'N', '_', 'M', 'P', 'L', 0,
2671  /* 162 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'Z', 'E', 'R', 'O', 0,
2672  /* 193 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'N', 'O', 'N', 'Z', 'E', 'R', 'O', 0,
2673  /* 227 */ 'H', 'I', '3', '2', 'D', 'S', 'P', 0,
2674  /* 235 */ 'L', 'O', '3', '2', 'D', 'S', 'P', 0,
2675  /* 243 */ 'A', 'C', 'C', '6', '4', 'D', 'S', 'P', 0,
2676  /* 252 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'C', 'P', 'U', '1', '6', 'R', 'e', 'g', 's', 'P', 'l', 'u', 's', 'S', 'P', 0,
2677  /* 289 */ 'O', 'C', 'T', 'E', 'O', 'N', '_', 'P', 0,
2678  /* 298 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'N', 'O', 'N', 'Z', 'E', 'R', 'O', '_', 'a', 'n', 'd', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'M', 'o', 'v', 'e', 'P', 0,
2679  /* 349 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'C', 'P', 'U', '1', '6', 'R', 'e', 'g', 's', '_', 'a', 'n', 'd', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'M', 'o', 'v', 'e', 'P', 0,
2680  /* 397 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'M', 'o', 'v', 'e', 'P', 0,
2681  /* 431 */ 'C', 'C', 'R', 0,
2682  /* 435 */ 'D', 'S', 'P', 'R', 0,
2683  /* 440 */ 'M', 'S', 'A', '1', '2', '8', 'W', 0,
2684  /* 448 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'C', 'P', 'U', '1', '6', 'R', 'e', 'g', 's', '_', 'a', 'n', 'd', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'M', 'o', 'v', 'e', 'P', 'P', 'a', 'i', 'r', 'S', 'e', 'c', 'o', 'n', 'd', 0,
2685  /* 506 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'M', 'o', 'v', 'e', 'P', 'P', 'a', 'i', 'r', 'F', 'i', 'r', 's', 't', '_', 'a', 'n', 'd', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'M', 'o', 'v', 'e', 'P', 'P', 'a', 'i', 'r', 'S', 'e', 'c', 'o', 'n', 'd', 0,
2686  /* 576 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'M', 'o', 'v', 'e', 'P', 'P', 'a', 'i', 'r', 'S', 'e', 'c', 'o', 'n', 'd', 0,
2687  /* 620 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'C', 'P', 'U', 'R', 'A', 'R', 'e', 'g', 0,
2688  /* 650 */ 'C', 'P', 'U', 'S', 'P', 'R', 'e', 'g', 0,
2689  /* 659 */ 'M', 'S', 'A', 'C', 't', 'r', 'l', 0,
2690  /* 667 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'M', 'o', 'v', 'e', 'P', '_', 'a', 'n', 'd', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'Z', 'e', 'r', 'o', 0,
2691  /* 717 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'M', 'o', 'v', 'e', 'P', '_', 'a', 'n', 'd', '_', 'C', 'P', 'U', '1', '6', 'R', 'e', 'g', 's', '_', 'a', 'n', 'd', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'Z', 'e', 'r', 'o', 0,
2692  /* 781 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'C', 'P', 'U', '1', '6', 'R', 'e', 'g', 's', '_', 'a', 'n', 'd', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'Z', 'e', 'r', 'o', 0,
2693  /* 828 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'Z', 'e', 'r', 'o', 0,
2694  /* 861 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'C', 'P', 'U', '1', '6', 'R', 'e', 'g', 's', 0,
2695  /* 892 */ 'H', 'W', 'R', 'e', 'g', 's', 0,
2696  /* 899 */ 'M', 'S', 'A', '1', '2', '8', 'W', 'E', 'v', 'e', 'n', 's', 0,
2697  /* 912 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'M', 'o', 'v', 'e', 'P', 'P', 'a', 'i', 'r', 'F', 'i', 'r', 's', 't', 0,
2698  0
2699};
2700
2701extern const MCRegisterClass MipsMCRegisterClasses[] = {
2702  { MSA128F16, MSA128F16Bits, 86, 32, sizeof(MSA128F16Bits), Mips::MSA128F16RegClassID, 16, 1, true },
2703  { CCR, CCRBits, 431, 32, sizeof(CCRBits), Mips::CCRRegClassID, 32, 1, false },
2704  { COP0, COP0Bits, 0, 32, sizeof(COP0Bits), Mips::COP0RegClassID, 32, 1, false },
2705  { COP2, COP2Bits, 37, 32, sizeof(COP2Bits), Mips::COP2RegClassID, 32, 1, false },
2706  { COP3, COP3Bits, 42, 32, sizeof(COP3Bits), Mips::COP3RegClassID, 32, 1, false },
2707  { DSPR, DSPRBits, 435, 32, sizeof(DSPRBits), Mips::DSPRRegClassID, 32, 1, true },
2708  { FGR32, FGR32Bits, 25, 32, sizeof(FGR32Bits), Mips::FGR32RegClassID, 32, 1, true },
2709  { FGRCC, FGRCCBits, 129, 32, sizeof(FGRCCBits), Mips::FGRCCRegClassID, 32, 1, true },
2710  { GPR32, GPR32Bits, 31, 32, sizeof(GPR32Bits), Mips::GPR32RegClassID, 32, 1, true },
2711  { HWRegs, HWRegsBits, 892, 32, sizeof(HWRegsBits), Mips::HWRegsRegClassID, 32, 1, false },
2712  { MSACtrl, MSACtrlBits, 659, 32, sizeof(MSACtrlBits), Mips::MSACtrlRegClassID, 32, 1, false },
2713  { GPR32NONZERO, GPR32NONZEROBits, 214, 31, sizeof(GPR32NONZEROBits), Mips::GPR32NONZERORegClassID, 32, 1, true },
2714  { CPU16RegsPlusSP, CPU16RegsPlusSPBits, 273, 9, sizeof(CPU16RegsPlusSPBits), Mips::CPU16RegsPlusSPRegClassID, 32, 1, true },
2715  { CPU16Regs, CPU16RegsBits, 882, 8, sizeof(CPU16RegsBits), Mips::CPU16RegsRegClassID, 32, 1, true },
2716  { FCC, FCCBits, 119, 8, sizeof(FCCBits), Mips::FCCRegClassID, 32, 1, false },
2717  { GPRMM16, GPRMM16Bits, 96, 8, sizeof(GPRMM16Bits), Mips::GPRMM16RegClassID, 32, 1, true },
2718  { GPRMM16MoveP, GPRMM16MovePBits, 336, 8, sizeof(GPRMM16MovePBits), Mips::GPRMM16MovePRegClassID, 32, 1, true },
2719  { GPRMM16Zero, GPRMM16ZeroBits, 705, 8, sizeof(GPRMM16ZeroBits), Mips::GPRMM16ZeroRegClassID, 32, 1, true },
2720  { CPU16Regs_and_GPRMM16Zero, CPU16Regs_and_GPRMM16ZeroBits, 755, 7, sizeof(CPU16Regs_and_GPRMM16ZeroBits), Mips::CPU16Regs_and_GPRMM16ZeroRegClassID, 32, 1, true },
2721  { GPR32NONZERO_and_GPRMM16MoveP, GPR32NONZERO_and_GPRMM16MovePBits, 319, 7, sizeof(GPR32NONZERO_and_GPRMM16MovePBits), Mips::GPR32NONZERO_and_GPRMM16MovePRegClassID, 32, 1, true },
2722  { GPRMM16MovePPairSecond, GPRMM16MovePPairSecondBits, 483, 5, sizeof(GPRMM16MovePPairSecondBits), Mips::GPRMM16MovePPairSecondRegClassID, 32, 1, true },
2723  { CPU16Regs_and_GPRMM16MoveP, CPU16Regs_and_GPRMM16MovePBits, 370, 4, sizeof(CPU16Regs_and_GPRMM16MovePBits), Mips::CPU16Regs_and_GPRMM16MovePRegClassID, 32, 1, true },
2724  { GPRMM16MoveP_and_GPRMM16Zero, GPRMM16MoveP_and_GPRMM16ZeroBits, 688, 4, sizeof(GPRMM16MoveP_and_GPRMM16ZeroBits), Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClassID, 32, 1, true },
2725  { HI32DSP, HI32DSPBits, 227, 4, sizeof(HI32DSPBits), Mips::HI32DSPRegClassID, 32, 1, true },
2726  { LO32DSP, LO32DSPBits, 235, 4, sizeof(LO32DSPBits), Mips::LO32DSPRegClassID, 32, 1, true },
2727  { CPU16Regs_and_GPRMM16MovePPairSecond, CPU16Regs_and_GPRMM16MovePPairSecondBits, 469, 3, sizeof(CPU16Regs_and_GPRMM16MovePPairSecondBits), Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClassID, 32, 1, true },
2728  { GPRMM16MovePPairFirst, GPRMM16MovePPairFirstBits, 933, 3, sizeof(GPRMM16MovePPairFirstBits), Mips::GPRMM16MovePPairFirstRegClassID, 32, 1, true },
2729  { GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero, GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits, 738, 3, sizeof(GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits), Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID, 32, 1, true },
2730  { GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond, GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits, 527, 2, sizeof(GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits), Mips::GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID, 32, 1, true },
2731  { CPURAReg, CPURARegBits, 641, 1, sizeof(CPURARegBits), Mips::CPURARegRegClassID, 32, 1, false },
2732  { CPUSPReg, CPUSPRegBits, 650, 1, sizeof(CPUSPRegBits), Mips::CPUSPRegRegClassID, 32, 1, false },
2733  { DSPCC, DSPCCBits, 123, 1, sizeof(DSPCCBits), Mips::DSPCCRegClassID, 32, 1, true },
2734  { GP32, GP32Bits, 15, 1, sizeof(GP32Bits), Mips::GP32RegClassID, 32, 1, false },
2735  { GPR32ZERO, GPR32ZEROBits, 183, 1, sizeof(GPR32ZEROBits), Mips::GPR32ZERORegClassID, 32, 1, true },
2736  { HI32, HI32Bits, 5, 1, sizeof(HI32Bits), Mips::HI32RegClassID, 32, 1, true },
2737  { LO32, LO32Bits, 10, 1, sizeof(LO32Bits), Mips::LO32RegClassID, 32, 1, true },
2738  { SP32, SP32Bits, 20, 1, sizeof(SP32Bits), Mips::SP32RegClassID, 32, 1, false },
2739  { FGR64, FGR64Bits, 74, 32, sizeof(FGR64Bits), Mips::FGR64RegClassID, 64, 1, true },
2740  { GPR64, GPR64Bits, 80, 32, sizeof(GPR64Bits), Mips::GPR64RegClassID, 64, 1, true },
2741  { GPR64_with_sub_32_in_GPR32NONZERO, GPR64_with_sub_32_in_GPR32NONZEROBits, 193, 31, sizeof(GPR64_with_sub_32_in_GPR32NONZEROBits), Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID, 64, 1, true },
2742  { AFGR64, AFGR64Bits, 73, 16, sizeof(AFGR64Bits), Mips::AFGR64RegClassID, 64, 1, true },
2743  { GPR64_with_sub_32_in_CPU16RegsPlusSP, GPR64_with_sub_32_in_CPU16RegsPlusSPBits, 252, 9, sizeof(GPR64_with_sub_32_in_CPU16RegsPlusSPBits), Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID, 64, 1, true },
2744  { GPR64_with_sub_32_in_CPU16Regs, GPR64_with_sub_32_in_CPU16RegsBits, 861, 8, sizeof(GPR64_with_sub_32_in_CPU16RegsBits), Mips::GPR64_with_sub_32_in_CPU16RegsRegClassID, 64, 1, true },
2745  { GPR64_with_sub_32_in_GPRMM16MoveP, GPR64_with_sub_32_in_GPRMM16MovePBits, 397, 8, sizeof(GPR64_with_sub_32_in_GPRMM16MovePBits), Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClassID, 64, 1, true },
2746  { GPR64_with_sub_32_in_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16ZeroBits, 828, 8, sizeof(GPR64_with_sub_32_in_GPRMM16ZeroBits), Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClassID, 64, 1, true },
2747  { GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits, 781, 7, sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits), Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID, 64, 1, true },
2748  { GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP, GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePBits, 298, 7, sizeof(GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePBits), Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID, 64, 1, true },
2749  { GPR64_with_sub_32_in_GPRMM16MovePPairSecond, GPR64_with_sub_32_in_GPRMM16MovePPairSecondBits, 576, 5, sizeof(GPR64_with_sub_32_in_GPRMM16MovePPairSecondBits), Mips::GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClassID, 64, 1, true },
2750  { ACC64DSP, ACC64DSPBits, 243, 4, sizeof(ACC64DSPBits), Mips::ACC64DSPRegClassID, 64, 1, true },
2751  { GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits, 349, 4, sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits), Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID, 64, 1, true },
2752  { GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits, 667, 4, sizeof(GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits), Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID, 64, 1, true },
2753  { GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondBits, 448, 3, sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondBits), Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClassID, 64, 1, true },
2754  { GPR64_with_sub_32_in_GPRMM16MovePPairFirst, GPR64_with_sub_32_in_GPRMM16MovePPairFirstBits, 912, 3, sizeof(GPR64_with_sub_32_in_GPRMM16MovePPairFirstBits), Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClassID, 64, 1, true },
2755  { GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits, 717, 3, sizeof(GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits), Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID, 64, 1, true },
2756  { OCTEON_MPL, OCTEON_MPLBits, 151, 3, sizeof(OCTEON_MPLBits), Mips::OCTEON_MPLRegClassID, 64, 1, false },
2757  { OCTEON_P, OCTEON_PBits, 289, 3, sizeof(OCTEON_PBits), Mips::OCTEON_PRegClassID, 64, 1, false },
2758  { GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond, GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits, 506, 2, sizeof(GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits), Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID, 64, 1, true },
2759  { ACC64, ACC64Bits, 47, 1, sizeof(ACC64Bits), Mips::ACC64RegClassID, 64, 1, true },
2760  { GP64, GP64Bits, 63, 1, sizeof(GP64Bits), Mips::GP64RegClassID, 64, 1, false },
2761  { GPR64_with_sub_32_in_CPURAReg, GPR64_with_sub_32_in_CPURARegBits, 620, 1, sizeof(GPR64_with_sub_32_in_CPURARegBits), Mips::GPR64_with_sub_32_in_CPURARegRegClassID, 64, 1, true },
2762  { GPR64_with_sub_32_in_GPR32ZERO, GPR64_with_sub_32_in_GPR32ZEROBits, 162, 1, sizeof(GPR64_with_sub_32_in_GPR32ZEROBits), Mips::GPR64_with_sub_32_in_GPR32ZERORegClassID, 64, 1, true },
2763  { HI64, HI64Bits, 53, 1, sizeof(HI64Bits), Mips::HI64RegClassID, 64, 1, true },
2764  { LO64, LO64Bits, 58, 1, sizeof(LO64Bits), Mips::LO64RegClassID, 64, 1, true },
2765  { SP64, SP64Bits, 68, 1, sizeof(SP64Bits), Mips::SP64RegClassID, 64, 1, false },
2766  { MSA128B, MSA128BBits, 111, 32, sizeof(MSA128BBits), Mips::MSA128BRegClassID, 128, 1, true },
2767  { MSA128D, MSA128DBits, 135, 32, sizeof(MSA128DBits), Mips::MSA128DRegClassID, 128, 1, true },
2768  { MSA128H, MSA128HBits, 143, 32, sizeof(MSA128HBits), Mips::MSA128HRegClassID, 128, 1, true },
2769  { MSA128W, MSA128WBits, 440, 32, sizeof(MSA128WBits), Mips::MSA128WRegClassID, 128, 1, true },
2770  { MSA128WEvens, MSA128WEvensBits, 899, 16, sizeof(MSA128WEvensBits), Mips::MSA128WEvensRegClassID, 128, 1, true },
2771  { ACC128, ACC128Bits, 104, 1, sizeof(ACC128Bits), Mips::ACC128RegClassID, 128, 1, true },
2772};
2773
2774// Mips Dwarf<->LLVM register mappings.
2775extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0Dwarf2L[] = {
2776  { 0U, Mips::ZERO_64 },
2777  { 1U, Mips::AT_64 },
2778  { 2U, Mips::V0_64 },
2779  { 3U, Mips::V1_64 },
2780  { 4U, Mips::A0_64 },
2781  { 5U, Mips::A1_64 },
2782  { 6U, Mips::A2_64 },
2783  { 7U, Mips::A3_64 },
2784  { 8U, Mips::T0_64 },
2785  { 9U, Mips::T1_64 },
2786  { 10U, Mips::T2_64 },
2787  { 11U, Mips::T3_64 },
2788  { 12U, Mips::T4_64 },
2789  { 13U, Mips::T5_64 },
2790  { 14U, Mips::T6_64 },
2791  { 15U, Mips::T7_64 },
2792  { 16U, Mips::S0_64 },
2793  { 17U, Mips::S1_64 },
2794  { 18U, Mips::S2_64 },
2795  { 19U, Mips::S3_64 },
2796  { 20U, Mips::S4_64 },
2797  { 21U, Mips::S5_64 },
2798  { 22U, Mips::S6_64 },
2799  { 23U, Mips::S7_64 },
2800  { 24U, Mips::T8_64 },
2801  { 25U, Mips::T9_64 },
2802  { 26U, Mips::K0_64 },
2803  { 27U, Mips::K1_64 },
2804  { 28U, Mips::GP_64 },
2805  { 29U, Mips::SP_64 },
2806  { 30U, Mips::FP_64 },
2807  { 31U, Mips::RA_64 },
2808  { 32U, Mips::D0_64 },
2809  { 33U, Mips::D1_64 },
2810  { 34U, Mips::D2_64 },
2811  { 35U, Mips::D3_64 },
2812  { 36U, Mips::D4_64 },
2813  { 37U, Mips::D5_64 },
2814  { 38U, Mips::D6_64 },
2815  { 39U, Mips::D7_64 },
2816  { 40U, Mips::D8_64 },
2817  { 41U, Mips::D9_64 },
2818  { 42U, Mips::D10_64 },
2819  { 43U, Mips::D11_64 },
2820  { 44U, Mips::D12_64 },
2821  { 45U, Mips::D13_64 },
2822  { 46U, Mips::D14_64 },
2823  { 47U, Mips::D15_64 },
2824  { 48U, Mips::D16_64 },
2825  { 49U, Mips::D17_64 },
2826  { 50U, Mips::D18_64 },
2827  { 51U, Mips::D19_64 },
2828  { 52U, Mips::D20_64 },
2829  { 53U, Mips::D21_64 },
2830  { 54U, Mips::D22_64 },
2831  { 55U, Mips::D23_64 },
2832  { 56U, Mips::D24_64 },
2833  { 57U, Mips::D25_64 },
2834  { 58U, Mips::D26_64 },
2835  { 59U, Mips::D27_64 },
2836  { 60U, Mips::D28_64 },
2837  { 61U, Mips::D29_64 },
2838  { 62U, Mips::D30_64 },
2839  { 63U, Mips::D31_64 },
2840  { 64U, Mips::HI0 },
2841  { 65U, Mips::LO0 },
2842  { 176U, Mips::HI1 },
2843  { 177U, Mips::LO1 },
2844  { 178U, Mips::HI2 },
2845  { 179U, Mips::LO2 },
2846  { 180U, Mips::HI3 },
2847  { 181U, Mips::LO3 },
2848};
2849extern const unsigned MipsDwarfFlavour0Dwarf2LSize = std::size(MipsDwarfFlavour0Dwarf2L);
2850
2851extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0Dwarf2L[] = {
2852  { 0U, Mips::ZERO_64 },
2853  { 1U, Mips::AT_64 },
2854  { 2U, Mips::V0_64 },
2855  { 3U, Mips::V1_64 },
2856  { 4U, Mips::A0_64 },
2857  { 5U, Mips::A1_64 },
2858  { 6U, Mips::A2_64 },
2859  { 7U, Mips::A3_64 },
2860  { 8U, Mips::T0_64 },
2861  { 9U, Mips::T1_64 },
2862  { 10U, Mips::T2_64 },
2863  { 11U, Mips::T3_64 },
2864  { 12U, Mips::T4_64 },
2865  { 13U, Mips::T5_64 },
2866  { 14U, Mips::T6_64 },
2867  { 15U, Mips::T7_64 },
2868  { 16U, Mips::S0_64 },
2869  { 17U, Mips::S1_64 },
2870  { 18U, Mips::S2_64 },
2871  { 19U, Mips::S3_64 },
2872  { 20U, Mips::S4_64 },
2873  { 21U, Mips::S5_64 },
2874  { 22U, Mips::S6_64 },
2875  { 23U, Mips::S7_64 },
2876  { 24U, Mips::T8_64 },
2877  { 25U, Mips::T9_64 },
2878  { 26U, Mips::K0_64 },
2879  { 27U, Mips::K1_64 },
2880  { 28U, Mips::GP_64 },
2881  { 29U, Mips::SP_64 },
2882  { 30U, Mips::FP_64 },
2883  { 31U, Mips::RA_64 },
2884  { 32U, Mips::D0_64 },
2885  { 33U, Mips::D1_64 },
2886  { 34U, Mips::D2_64 },
2887  { 35U, Mips::D3_64 },
2888  { 36U, Mips::D4_64 },
2889  { 37U, Mips::D5_64 },
2890  { 38U, Mips::D6_64 },
2891  { 39U, Mips::D7_64 },
2892  { 40U, Mips::D8_64 },
2893  { 41U, Mips::D9_64 },
2894  { 42U, Mips::D10_64 },
2895  { 43U, Mips::D11_64 },
2896  { 44U, Mips::D12_64 },
2897  { 45U, Mips::D13_64 },
2898  { 46U, Mips::D14_64 },
2899  { 47U, Mips::D15_64 },
2900  { 48U, Mips::D16_64 },
2901  { 49U, Mips::D17_64 },
2902  { 50U, Mips::D18_64 },
2903  { 51U, Mips::D19_64 },
2904  { 52U, Mips::D20_64 },
2905  { 53U, Mips::D21_64 },
2906  { 54U, Mips::D22_64 },
2907  { 55U, Mips::D23_64 },
2908  { 56U, Mips::D24_64 },
2909  { 57U, Mips::D25_64 },
2910  { 58U, Mips::D26_64 },
2911  { 59U, Mips::D27_64 },
2912  { 60U, Mips::D28_64 },
2913  { 61U, Mips::D29_64 },
2914  { 62U, Mips::D30_64 },
2915  { 63U, Mips::D31_64 },
2916  { 64U, Mips::HI0 },
2917  { 65U, Mips::LO0 },
2918  { 176U, Mips::HI1 },
2919  { 177U, Mips::LO1 },
2920  { 178U, Mips::HI2 },
2921  { 179U, Mips::LO2 },
2922  { 180U, Mips::HI3 },
2923  { 181U, Mips::LO3 },
2924};
2925extern const unsigned MipsEHFlavour0Dwarf2LSize = std::size(MipsEHFlavour0Dwarf2L);
2926
2927extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0L2Dwarf[] = {
2928  { Mips::AT, 1U },
2929  { Mips::FP, 30U },
2930  { Mips::GP, 28U },
2931  { Mips::RA, 31U },
2932  { Mips::SP, 29U },
2933  { Mips::ZERO, 0U },
2934  { Mips::A0, 4U },
2935  { Mips::A1, 5U },
2936  { Mips::A2, 6U },
2937  { Mips::A3, 7U },
2938  { Mips::AT_64, 1U },
2939  { Mips::F0, 32U },
2940  { Mips::F1, 33U },
2941  { Mips::F2, 34U },
2942  { Mips::F3, 35U },
2943  { Mips::F4, 36U },
2944  { Mips::F5, 37U },
2945  { Mips::F6, 38U },
2946  { Mips::F7, 39U },
2947  { Mips::F8, 40U },
2948  { Mips::F9, 41U },
2949  { Mips::F10, 42U },
2950  { Mips::F11, 43U },
2951  { Mips::F12, 44U },
2952  { Mips::F13, 45U },
2953  { Mips::F14, 46U },
2954  { Mips::F15, 47U },
2955  { Mips::F16, 48U },
2956  { Mips::F17, 49U },
2957  { Mips::F18, 50U },
2958  { Mips::F19, 51U },
2959  { Mips::F20, 52U },
2960  { Mips::F21, 53U },
2961  { Mips::F22, 54U },
2962  { Mips::F23, 55U },
2963  { Mips::F24, 56U },
2964  { Mips::F25, 57U },
2965  { Mips::F26, 58U },
2966  { Mips::F27, 59U },
2967  { Mips::F28, 60U },
2968  { Mips::F29, 61U },
2969  { Mips::F30, 62U },
2970  { Mips::F31, 63U },
2971  { Mips::FP_64, 30U },
2972  { Mips::F_HI0, 32U },
2973  { Mips::F_HI1, 33U },
2974  { Mips::F_HI2, 34U },
2975  { Mips::F_HI3, 35U },
2976  { Mips::F_HI4, 36U },
2977  { Mips::F_HI5, 37U },
2978  { Mips::F_HI6, 38U },
2979  { Mips::F_HI7, 39U },
2980  { Mips::F_HI8, 40U },
2981  { Mips::F_HI9, 41U },
2982  { Mips::F_HI10, 42U },
2983  { Mips::F_HI11, 43U },
2984  { Mips::F_HI12, 44U },
2985  { Mips::F_HI13, 45U },
2986  { Mips::F_HI14, 46U },
2987  { Mips::F_HI15, 47U },
2988  { Mips::F_HI16, 48U },
2989  { Mips::F_HI17, 49U },
2990  { Mips::F_HI18, 50U },
2991  { Mips::F_HI19, 51U },
2992  { Mips::F_HI20, 52U },
2993  { Mips::F_HI21, 53U },
2994  { Mips::F_HI22, 54U },
2995  { Mips::F_HI23, 55U },
2996  { Mips::F_HI24, 56U },
2997  { Mips::F_HI25, 57U },
2998  { Mips::F_HI26, 58U },
2999  { Mips::F_HI27, 59U },
3000  { Mips::F_HI28, 60U },
3001  { Mips::F_HI29, 61U },
3002  { Mips::F_HI30, 62U },
3003  { Mips::F_HI31, 63U },
3004  { Mips::GP_64, 28U },
3005  { Mips::HI0, 64U },
3006  { Mips::HI1, 176U },
3007  { Mips::HI2, 178U },
3008  { Mips::HI3, 180U },
3009  { Mips::K0, 26U },
3010  { Mips::K1, 27U },
3011  { Mips::LO0, 65U },
3012  { Mips::LO1, 177U },
3013  { Mips::LO2, 179U },
3014  { Mips::LO3, 181U },
3015  { Mips::RA_64, 31U },
3016  { Mips::S0, 16U },
3017  { Mips::S1, 17U },
3018  { Mips::S2, 18U },
3019  { Mips::S3, 19U },
3020  { Mips::S4, 20U },
3021  { Mips::S5, 21U },
3022  { Mips::S6, 22U },
3023  { Mips::S7, 23U },
3024  { Mips::SP_64, 29U },
3025  { Mips::T0, 8U },
3026  { Mips::T1, 9U },
3027  { Mips::T2, 10U },
3028  { Mips::T3, 11U },
3029  { Mips::T4, 12U },
3030  { Mips::T5, 13U },
3031  { Mips::T6, 14U },
3032  { Mips::T7, 15U },
3033  { Mips::T8, 24U },
3034  { Mips::T9, 25U },
3035  { Mips::V0, 2U },
3036  { Mips::V1, 3U },
3037  { Mips::W0, 32U },
3038  { Mips::W1, 33U },
3039  { Mips::W2, 34U },
3040  { Mips::W3, 35U },
3041  { Mips::W4, 36U },
3042  { Mips::W5, 37U },
3043  { Mips::W6, 38U },
3044  { Mips::W7, 39U },
3045  { Mips::W8, 40U },
3046  { Mips::W9, 41U },
3047  { Mips::W10, 42U },
3048  { Mips::W11, 43U },
3049  { Mips::W12, 44U },
3050  { Mips::W13, 45U },
3051  { Mips::W14, 46U },
3052  { Mips::W15, 47U },
3053  { Mips::W16, 48U },
3054  { Mips::W17, 49U },
3055  { Mips::W18, 50U },
3056  { Mips::W19, 51U },
3057  { Mips::W20, 52U },
3058  { Mips::W21, 53U },
3059  { Mips::W22, 54U },
3060  { Mips::W23, 55U },
3061  { Mips::W24, 56U },
3062  { Mips::W25, 57U },
3063  { Mips::W26, 58U },
3064  { Mips::W27, 59U },
3065  { Mips::W28, 60U },
3066  { Mips::W29, 61U },
3067  { Mips::W30, 62U },
3068  { Mips::W31, 63U },
3069  { Mips::ZERO_64, 0U },
3070  { Mips::A0_64, 4U },
3071  { Mips::A1_64, 5U },
3072  { Mips::A2_64, 6U },
3073  { Mips::A3_64, 7U },
3074  { Mips::D0_64, 32U },
3075  { Mips::D1_64, 33U },
3076  { Mips::D2_64, 34U },
3077  { Mips::D3_64, 35U },
3078  { Mips::D4_64, 36U },
3079  { Mips::D5_64, 37U },
3080  { Mips::D6_64, 38U },
3081  { Mips::D7_64, 39U },
3082  { Mips::D8_64, 40U },
3083  { Mips::D9_64, 41U },
3084  { Mips::D10_64, 42U },
3085  { Mips::D11_64, 43U },
3086  { Mips::D12_64, 44U },
3087  { Mips::D13_64, 45U },
3088  { Mips::D14_64, 46U },
3089  { Mips::D15_64, 47U },
3090  { Mips::D16_64, 48U },
3091  { Mips::D17_64, 49U },
3092  { Mips::D18_64, 50U },
3093  { Mips::D19_64, 51U },
3094  { Mips::D20_64, 52U },
3095  { Mips::D21_64, 53U },
3096  { Mips::D22_64, 54U },
3097  { Mips::D23_64, 55U },
3098  { Mips::D24_64, 56U },
3099  { Mips::D25_64, 57U },
3100  { Mips::D26_64, 58U },
3101  { Mips::D27_64, 59U },
3102  { Mips::D28_64, 60U },
3103  { Mips::D29_64, 61U },
3104  { Mips::D30_64, 62U },
3105  { Mips::D31_64, 63U },
3106  { Mips::K0_64, 26U },
3107  { Mips::K1_64, 27U },
3108  { Mips::S0_64, 16U },
3109  { Mips::S1_64, 17U },
3110  { Mips::S2_64, 18U },
3111  { Mips::S3_64, 19U },
3112  { Mips::S4_64, 20U },
3113  { Mips::S5_64, 21U },
3114  { Mips::S6_64, 22U },
3115  { Mips::S7_64, 23U },
3116  { Mips::T0_64, 8U },
3117  { Mips::T1_64, 9U },
3118  { Mips::T2_64, 10U },
3119  { Mips::T3_64, 11U },
3120  { Mips::T4_64, 12U },
3121  { Mips::T5_64, 13U },
3122  { Mips::T6_64, 14U },
3123  { Mips::T7_64, 15U },
3124  { Mips::T8_64, 24U },
3125  { Mips::T9_64, 25U },
3126  { Mips::V0_64, 2U },
3127  { Mips::V1_64, 3U },
3128};
3129extern const unsigned MipsDwarfFlavour0L2DwarfSize = std::size(MipsDwarfFlavour0L2Dwarf);
3130
3131extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0L2Dwarf[] = {
3132  { Mips::AT, 1U },
3133  { Mips::FP, 30U },
3134  { Mips::GP, 28U },
3135  { Mips::RA, 31U },
3136  { Mips::SP, 29U },
3137  { Mips::ZERO, 0U },
3138  { Mips::A0, 4U },
3139  { Mips::A1, 5U },
3140  { Mips::A2, 6U },
3141  { Mips::A3, 7U },
3142  { Mips::AT_64, 1U },
3143  { Mips::F0, 32U },
3144  { Mips::F1, 33U },
3145  { Mips::F2, 34U },
3146  { Mips::F3, 35U },
3147  { Mips::F4, 36U },
3148  { Mips::F5, 37U },
3149  { Mips::F6, 38U },
3150  { Mips::F7, 39U },
3151  { Mips::F8, 40U },
3152  { Mips::F9, 41U },
3153  { Mips::F10, 42U },
3154  { Mips::F11, 43U },
3155  { Mips::F12, 44U },
3156  { Mips::F13, 45U },
3157  { Mips::F14, 46U },
3158  { Mips::F15, 47U },
3159  { Mips::F16, 48U },
3160  { Mips::F17, 49U },
3161  { Mips::F18, 50U },
3162  { Mips::F19, 51U },
3163  { Mips::F20, 52U },
3164  { Mips::F21, 53U },
3165  { Mips::F22, 54U },
3166  { Mips::F23, 55U },
3167  { Mips::F24, 56U },
3168  { Mips::F25, 57U },
3169  { Mips::F26, 58U },
3170  { Mips::F27, 59U },
3171  { Mips::F28, 60U },
3172  { Mips::F29, 61U },
3173  { Mips::F30, 62U },
3174  { Mips::F31, 63U },
3175  { Mips::FP_64, 30U },
3176  { Mips::F_HI0, 32U },
3177  { Mips::F_HI1, 33U },
3178  { Mips::F_HI2, 34U },
3179  { Mips::F_HI3, 35U },
3180  { Mips::F_HI4, 36U },
3181  { Mips::F_HI5, 37U },
3182  { Mips::F_HI6, 38U },
3183  { Mips::F_HI7, 39U },
3184  { Mips::F_HI8, 40U },
3185  { Mips::F_HI9, 41U },
3186  { Mips::F_HI10, 42U },
3187  { Mips::F_HI11, 43U },
3188  { Mips::F_HI12, 44U },
3189  { Mips::F_HI13, 45U },
3190  { Mips::F_HI14, 46U },
3191  { Mips::F_HI15, 47U },
3192  { Mips::F_HI16, 48U },
3193  { Mips::F_HI17, 49U },
3194  { Mips::F_HI18, 50U },
3195  { Mips::F_HI19, 51U },
3196  { Mips::F_HI20, 52U },
3197  { Mips::F_HI21, 53U },
3198  { Mips::F_HI22, 54U },
3199  { Mips::F_HI23, 55U },
3200  { Mips::F_HI24, 56U },
3201  { Mips::F_HI25, 57U },
3202  { Mips::F_HI26, 58U },
3203  { Mips::F_HI27, 59U },
3204  { Mips::F_HI28, 60U },
3205  { Mips::F_HI29, 61U },
3206  { Mips::F_HI30, 62U },
3207  { Mips::F_HI31, 63U },
3208  { Mips::GP_64, 28U },
3209  { Mips::HI0, 64U },
3210  { Mips::HI1, 176U },
3211  { Mips::HI2, 178U },
3212  { Mips::HI3, 180U },
3213  { Mips::K0, 26U },
3214  { Mips::K1, 27U },
3215  { Mips::LO0, 65U },
3216  { Mips::LO1, 177U },
3217  { Mips::LO2, 179U },
3218  { Mips::LO3, 181U },
3219  { Mips::RA_64, 31U },
3220  { Mips::S0, 16U },
3221  { Mips::S1, 17U },
3222  { Mips::S2, 18U },
3223  { Mips::S3, 19U },
3224  { Mips::S4, 20U },
3225  { Mips::S5, 21U },
3226  { Mips::S6, 22U },
3227  { Mips::S7, 23U },
3228  { Mips::SP_64, 29U },
3229  { Mips::T0, 8U },
3230  { Mips::T1, 9U },
3231  { Mips::T2, 10U },
3232  { Mips::T3, 11U },
3233  { Mips::T4, 12U },
3234  { Mips::T5, 13U },
3235  { Mips::T6, 14U },
3236  { Mips::T7, 15U },
3237  { Mips::T8, 24U },
3238  { Mips::T9, 25U },
3239  { Mips::V0, 2U },
3240  { Mips::V1, 3U },
3241  { Mips::W0, 32U },
3242  { Mips::W1, 33U },
3243  { Mips::W2, 34U },
3244  { Mips::W3, 35U },
3245  { Mips::W4, 36U },
3246  { Mips::W5, 37U },
3247  { Mips::W6, 38U },
3248  { Mips::W7, 39U },
3249  { Mips::W8, 40U },
3250  { Mips::W9, 41U },
3251  { Mips::W10, 42U },
3252  { Mips::W11, 43U },
3253  { Mips::W12, 44U },
3254  { Mips::W13, 45U },
3255  { Mips::W14, 46U },
3256  { Mips::W15, 47U },
3257  { Mips::W16, 48U },
3258  { Mips::W17, 49U },
3259  { Mips::W18, 50U },
3260  { Mips::W19, 51U },
3261  { Mips::W20, 52U },
3262  { Mips::W21, 53U },
3263  { Mips::W22, 54U },
3264  { Mips::W23, 55U },
3265  { Mips::W24, 56U },
3266  { Mips::W25, 57U },
3267  { Mips::W26, 58U },
3268  { Mips::W27, 59U },
3269  { Mips::W28, 60U },
3270  { Mips::W29, 61U },
3271  { Mips::W30, 62U },
3272  { Mips::W31, 63U },
3273  { Mips::ZERO_64, 0U },
3274  { Mips::A0_64, 4U },
3275  { Mips::A1_64, 5U },
3276  { Mips::A2_64, 6U },
3277  { Mips::A3_64, 7U },
3278  { Mips::D0_64, 32U },
3279  { Mips::D1_64, 33U },
3280  { Mips::D2_64, 34U },
3281  { Mips::D3_64, 35U },
3282  { Mips::D4_64, 36U },
3283  { Mips::D5_64, 37U },
3284  { Mips::D6_64, 38U },
3285  { Mips::D7_64, 39U },
3286  { Mips::D8_64, 40U },
3287  { Mips::D9_64, 41U },
3288  { Mips::D10_64, 42U },
3289  { Mips::D11_64, 43U },
3290  { Mips::D12_64, 44U },
3291  { Mips::D13_64, 45U },
3292  { Mips::D14_64, 46U },
3293  { Mips::D15_64, 47U },
3294  { Mips::D16_64, 48U },
3295  { Mips::D17_64, 49U },
3296  { Mips::D18_64, 50U },
3297  { Mips::D19_64, 51U },
3298  { Mips::D20_64, 52U },
3299  { Mips::D21_64, 53U },
3300  { Mips::D22_64, 54U },
3301  { Mips::D23_64, 55U },
3302  { Mips::D24_64, 56U },
3303  { Mips::D25_64, 57U },
3304  { Mips::D26_64, 58U },
3305  { Mips::D27_64, 59U },
3306  { Mips::D28_64, 60U },
3307  { Mips::D29_64, 61U },
3308  { Mips::D30_64, 62U },
3309  { Mips::D31_64, 63U },
3310  { Mips::K0_64, 26U },
3311  { Mips::K1_64, 27U },
3312  { Mips::S0_64, 16U },
3313  { Mips::S1_64, 17U },
3314  { Mips::S2_64, 18U },
3315  { Mips::S3_64, 19U },
3316  { Mips::S4_64, 20U },
3317  { Mips::S5_64, 21U },
3318  { Mips::S6_64, 22U },
3319  { Mips::S7_64, 23U },
3320  { Mips::T0_64, 8U },
3321  { Mips::T1_64, 9U },
3322  { Mips::T2_64, 10U },
3323  { Mips::T3_64, 11U },
3324  { Mips::T4_64, 12U },
3325  { Mips::T5_64, 13U },
3326  { Mips::T6_64, 14U },
3327  { Mips::T7_64, 15U },
3328  { Mips::T8_64, 24U },
3329  { Mips::T9_64, 25U },
3330  { Mips::V0_64, 2U },
3331  { Mips::V1_64, 3U },
3332};
3333extern const unsigned MipsEHFlavour0L2DwarfSize = std::size(MipsEHFlavour0L2Dwarf);
3334
3335extern const uint16_t MipsRegEncodingTable[] = {
3336  0,
3337  1,
3338  0,
3339  0,
3340  0,
3341  0,
3342  0,
3343  0,
3344  30,
3345  28,
3346  2,
3347  1,
3348  0,
3349  6,
3350  4,
3351  5,
3352  3,
3353  7,
3354  0,
3355  31,
3356  29,
3357  0,
3358  4,
3359  5,
3360  6,
3361  7,
3362  0,
3363  1,
3364  2,
3365  3,
3366  1,
3367  0,
3368  1,
3369  2,
3370  3,
3371  4,
3372  5,
3373  6,
3374  7,
3375  8,
3376  9,
3377  0,
3378  1,
3379  2,
3380  3,
3381  4,
3382  5,
3383  6,
3384  7,
3385  8,
3386  9,
3387  0,
3388  1,
3389  2,
3390  3,
3391  4,
3392  5,
3393  6,
3394  7,
3395  8,
3396  9,
3397  10,
3398  11,
3399  12,
3400  13,
3401  14,
3402  15,
3403  16,
3404  17,
3405  18,
3406  19,
3407  20,
3408  21,
3409  22,
3410  23,
3411  24,
3412  25,
3413  26,
3414  27,
3415  28,
3416  29,
3417  30,
3418  31,
3419  10,
3420  11,
3421  12,
3422  13,
3423  14,
3424  15,
3425  16,
3426  17,
3427  18,
3428  19,
3429  20,
3430  21,
3431  22,
3432  23,
3433  24,
3434  25,
3435  26,
3436  27,
3437  28,
3438  29,
3439  30,
3440  31,
3441  10,
3442  11,
3443  12,
3444  13,
3445  14,
3446  15,
3447  16,
3448  17,
3449  18,
3450  19,
3451  20,
3452  21,
3453  22,
3454  23,
3455  24,
3456  25,
3457  26,
3458  27,
3459  28,
3460  29,
3461  30,
3462  31,
3463  0,
3464  2,
3465  4,
3466  6,
3467  8,
3468  10,
3469  12,
3470  14,
3471  16,
3472  18,
3473  20,
3474  22,
3475  24,
3476  26,
3477  28,
3478  30,
3479  0,
3480  0,
3481  0,
3482  0,
3483  0,
3484  1,
3485  2,
3486  3,
3487  4,
3488  5,
3489  6,
3490  7,
3491  8,
3492  9,
3493  10,
3494  11,
3495  12,
3496  13,
3497  14,
3498  15,
3499  16,
3500  17,
3501  18,
3502  19,
3503  20,
3504  21,
3505  22,
3506  23,
3507  24,
3508  25,
3509  26,
3510  27,
3511  28,
3512  29,
3513  30,
3514  31,
3515  0,
3516  1,
3517  2,
3518  3,
3519  4,
3520  5,
3521  6,
3522  7,
3523  0,
3524  1,
3525  2,
3526  3,
3527  4,
3528  5,
3529  6,
3530  7,
3531  8,
3532  9,
3533  10,
3534  11,
3535  12,
3536  13,
3537  14,
3538  15,
3539  16,
3540  17,
3541  18,
3542  19,
3543  20,
3544  21,
3545  22,
3546  23,
3547  24,
3548  25,
3549  26,
3550  27,
3551  28,
3552  29,
3553  30,
3554  31,
3555  30,
3556  0,
3557  1,
3558  2,
3559  3,
3560  4,
3561  5,
3562  6,
3563  7,
3564  8,
3565  9,
3566  10,
3567  11,
3568  12,
3569  13,
3570  14,
3571  15,
3572  16,
3573  17,
3574  18,
3575  19,
3576  20,
3577  21,
3578  22,
3579  23,
3580  24,
3581  25,
3582  26,
3583  27,
3584  28,
3585  29,
3586  30,
3587  31,
3588  28,
3589  0,
3590  1,
3591  2,
3592  3,
3593  0,
3594  1,
3595  2,
3596  3,
3597  4,
3598  5,
3599  6,
3600  7,
3601  8,
3602  9,
3603  10,
3604  11,
3605  12,
3606  13,
3607  14,
3608  15,
3609  16,
3610  17,
3611  18,
3612  19,
3613  20,
3614  21,
3615  22,
3616  23,
3617  24,
3618  25,
3619  26,
3620  27,
3621  28,
3622  29,
3623  30,
3624  31,
3625  26,
3626  27,
3627  0,
3628  1,
3629  2,
3630  3,
3631  0,
3632  1,
3633  2,
3634  8,
3635  9,
3636  10,
3637  11,
3638  12,
3639  13,
3640  14,
3641  15,
3642  16,
3643  17,
3644  18,
3645  19,
3646  20,
3647  21,
3648  22,
3649  23,
3650  24,
3651  25,
3652  26,
3653  27,
3654  28,
3655  29,
3656  30,
3657  31,
3658  0,
3659  1,
3660  2,
3661  31,
3662  16,
3663  17,
3664  18,
3665  19,
3666  20,
3667  21,
3668  22,
3669  23,
3670  29,
3671  8,
3672  9,
3673  10,
3674  11,
3675  12,
3676  13,
3677  14,
3678  15,
3679  24,
3680  25,
3681  2,
3682  3,
3683  0,
3684  1,
3685  2,
3686  3,
3687  4,
3688  5,
3689  6,
3690  7,
3691  8,
3692  9,
3693  10,
3694  11,
3695  12,
3696  13,
3697  14,
3698  15,
3699  16,
3700  17,
3701  18,
3702  19,
3703  20,
3704  21,
3705  22,
3706  23,
3707  24,
3708  25,
3709  26,
3710  27,
3711  28,
3712  29,
3713  30,
3714  31,
3715  0,
3716  4,
3717  5,
3718  6,
3719  7,
3720  0,
3721  0,
3722  1,
3723  2,
3724  3,
3725  4,
3726  5,
3727  6,
3728  7,
3729  8,
3730  9,
3731  10,
3732  11,
3733  12,
3734  13,
3735  14,
3736  15,
3737  16,
3738  17,
3739  18,
3740  19,
3741  20,
3742  21,
3743  22,
3744  23,
3745  24,
3746  25,
3747  26,
3748  27,
3749  28,
3750  29,
3751  30,
3752  31,
3753  0,
3754  0,
3755  26,
3756  27,
3757  0,
3758  16,
3759  17,
3760  18,
3761  19,
3762  20,
3763  21,
3764  22,
3765  23,
3766  8,
3767  9,
3768  10,
3769  11,
3770  12,
3771  13,
3772  14,
3773  15,
3774  24,
3775  25,
3776  2,
3777  3,
3778};
3779static inline void InitMipsMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
3780  RI->InitMCRegisterInfo(MipsRegDesc, 442, RA, PC, MipsMCRegisterClasses, 70, MipsRegUnitRoots, 321, MipsRegDiffLists, MipsLaneMaskLists, MipsRegStrings, MipsRegClassStrings, MipsSubRegIdxLists, 12,
3781MipsSubRegIdxRanges, MipsRegEncodingTable);
3782
3783  switch (DwarfFlavour) {
3784  default:
3785    llvm_unreachable("Unknown DWARF flavour");
3786  case 0:
3787    RI->mapDwarfRegsToLLVMRegs(MipsDwarfFlavour0Dwarf2L, MipsDwarfFlavour0Dwarf2LSize, false);
3788    break;
3789  }
3790  switch (EHFlavour) {
3791  default:
3792    llvm_unreachable("Unknown DWARF flavour");
3793  case 0:
3794    RI->mapDwarfRegsToLLVMRegs(MipsEHFlavour0Dwarf2L, MipsEHFlavour0Dwarf2LSize, true);
3795    break;
3796  }
3797  switch (DwarfFlavour) {
3798  default:
3799    llvm_unreachable("Unknown DWARF flavour");
3800  case 0:
3801    RI->mapLLVMRegsToDwarfRegs(MipsDwarfFlavour0L2Dwarf, MipsDwarfFlavour0L2DwarfSize, false);
3802    break;
3803  }
3804  switch (EHFlavour) {
3805  default:
3806    llvm_unreachable("Unknown DWARF flavour");
3807  case 0:
3808    RI->mapLLVMRegsToDwarfRegs(MipsEHFlavour0L2Dwarf, MipsEHFlavour0L2DwarfSize, true);
3809    break;
3810  }
3811}
3812
3813} // end namespace llvm
3814
3815#endif // GET_REGINFO_MC_DESC
3816
3817/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
3818|*                                                                            *|
3819|* Register Information Header Fragment                                       *|
3820|*                                                                            *|
3821|* Automatically generated file, do not edit!                                 *|
3822|*                                                                            *|
3823\*===----------------------------------------------------------------------===*/
3824
3825
3826#ifdef GET_REGINFO_HEADER
3827#undef GET_REGINFO_HEADER
3828
3829#include "llvm/CodeGen/TargetRegisterInfo.h"
3830
3831namespace llvm {
3832
3833class MipsFrameLowering;
3834
3835struct MipsGenRegisterInfo : public TargetRegisterInfo {
3836  explicit MipsGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
3837      unsigned PC = 0, unsigned HwMode = 0);
3838  unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
3839  LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
3840  LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
3841  const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass *, unsigned) const override;
3842  const TargetRegisterClass *getSubRegisterClass(const TargetRegisterClass *, unsigned) const override;
3843  const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
3844  unsigned getRegUnitWeight(unsigned RegUnit) const override;
3845  unsigned getNumRegPressureSets() const override;
3846  const char *getRegPressureSetName(unsigned Idx) const override;
3847  unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
3848  const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
3849  const int *getRegUnitPressureSets(unsigned RegUnit) const override;
3850  ArrayRef<const char *> getRegMaskNames() const override;
3851  ArrayRef<const uint32_t *> getRegMasks() const override;
3852  bool isGeneralPurposeRegister(const MachineFunction &, MCRegister) const override;
3853  bool isFixedRegister(const MachineFunction &, MCRegister) const override;
3854  bool isArgumentRegister(const MachineFunction &, MCRegister) const override;
3855  bool isConstantPhysReg(MCRegister PhysReg) const override final;
3856  /// Devirtualized TargetFrameLowering.
3857  static const MipsFrameLowering *getFrameLowering(
3858      const MachineFunction &MF);
3859};
3860
3861namespace Mips { // Register classes
3862  extern const TargetRegisterClass MSA128F16RegClass;
3863  extern const TargetRegisterClass CCRRegClass;
3864  extern const TargetRegisterClass COP0RegClass;
3865  extern const TargetRegisterClass COP2RegClass;
3866  extern const TargetRegisterClass COP3RegClass;
3867  extern const TargetRegisterClass DSPRRegClass;
3868  extern const TargetRegisterClass FGR32RegClass;
3869  extern const TargetRegisterClass FGRCCRegClass;
3870  extern const TargetRegisterClass GPR32RegClass;
3871  extern const TargetRegisterClass HWRegsRegClass;
3872  extern const TargetRegisterClass MSACtrlRegClass;
3873  extern const TargetRegisterClass GPR32NONZERORegClass;
3874  extern const TargetRegisterClass CPU16RegsPlusSPRegClass;
3875  extern const TargetRegisterClass CPU16RegsRegClass;
3876  extern const TargetRegisterClass FCCRegClass;
3877  extern const TargetRegisterClass GPRMM16RegClass;
3878  extern const TargetRegisterClass GPRMM16MovePRegClass;
3879  extern const TargetRegisterClass GPRMM16ZeroRegClass;
3880  extern const TargetRegisterClass CPU16Regs_and_GPRMM16ZeroRegClass;
3881  extern const TargetRegisterClass GPR32NONZERO_and_GPRMM16MovePRegClass;
3882  extern const TargetRegisterClass GPRMM16MovePPairSecondRegClass;
3883  extern const TargetRegisterClass CPU16Regs_and_GPRMM16MovePRegClass;
3884  extern const TargetRegisterClass GPRMM16MoveP_and_GPRMM16ZeroRegClass;
3885  extern const TargetRegisterClass HI32DSPRegClass;
3886  extern const TargetRegisterClass LO32DSPRegClass;
3887  extern const TargetRegisterClass CPU16Regs_and_GPRMM16MovePPairSecondRegClass;
3888  extern const TargetRegisterClass GPRMM16MovePPairFirstRegClass;
3889  extern const TargetRegisterClass GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass;
3890  extern const TargetRegisterClass GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass;
3891  extern const TargetRegisterClass CPURARegRegClass;
3892  extern const TargetRegisterClass CPUSPRegRegClass;
3893  extern const TargetRegisterClass DSPCCRegClass;
3894  extern const TargetRegisterClass GP32RegClass;
3895  extern const TargetRegisterClass GPR32ZERORegClass;
3896  extern const TargetRegisterClass HI32RegClass;
3897  extern const TargetRegisterClass LO32RegClass;
3898  extern const TargetRegisterClass SP32RegClass;
3899  extern const TargetRegisterClass FGR64RegClass;
3900  extern const TargetRegisterClass GPR64RegClass;
3901  extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERORegClass;
3902  extern const TargetRegisterClass AFGR64RegClass;
3903  extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass;
3904  extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsRegClass;
3905  extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePRegClass;
3906  extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16ZeroRegClass;
3907  extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass;
3908  extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass;
3909  extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClass;
3910  extern const TargetRegisterClass ACC64DSPRegClass;
3911  extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClass;
3912  extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass;
3913  extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClass;
3914  extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClass;
3915  extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass;
3916  extern const TargetRegisterClass OCTEON_MPLRegClass;
3917  extern const TargetRegisterClass OCTEON_PRegClass;
3918  extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass;
3919  extern const TargetRegisterClass ACC64RegClass;
3920  extern const TargetRegisterClass GP64RegClass;
3921  extern const TargetRegisterClass GPR64_with_sub_32_in_CPURARegRegClass;
3922  extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32ZERORegClass;
3923  extern const TargetRegisterClass HI64RegClass;
3924  extern const TargetRegisterClass LO64RegClass;
3925  extern const TargetRegisterClass SP64RegClass;
3926  extern const TargetRegisterClass MSA128BRegClass;
3927  extern const TargetRegisterClass MSA128DRegClass;
3928  extern const TargetRegisterClass MSA128HRegClass;
3929  extern const TargetRegisterClass MSA128WRegClass;
3930  extern const TargetRegisterClass MSA128WEvensRegClass;
3931  extern const TargetRegisterClass ACC128RegClass;
3932} // end namespace Mips
3933
3934} // end namespace llvm
3935
3936#endif // GET_REGINFO_HEADER
3937
3938/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
3939|*                                                                            *|
3940|* Target Register and Register Classes Information                           *|
3941|*                                                                            *|
3942|* Automatically generated file, do not edit!                                 *|
3943|*                                                                            *|
3944\*===----------------------------------------------------------------------===*/
3945
3946
3947#ifdef GET_REGINFO_TARGET_DESC
3948#undef GET_REGINFO_TARGET_DESC
3949
3950namespace llvm {
3951
3952extern const MCRegisterClass MipsMCRegisterClasses[];
3953
3954static const MVT::SimpleValueType VTLists[] = {
3955  /* 0 */ MVT::i32, MVT::Other,
3956  /* 2 */ MVT::i64, MVT::Other,
3957  /* 4 */ MVT::f16, MVT::Other,
3958  /* 6 */ MVT::f32, MVT::Other,
3959  /* 8 */ MVT::f64, MVT::Other,
3960  /* 10 */ MVT::v16i8, MVT::Other,
3961  /* 12 */ MVT::v4i8, MVT::v2i16, MVT::Other,
3962  /* 15 */ MVT::v8i16, MVT::v8f16, MVT::Other,
3963  /* 18 */ MVT::v4i32, MVT::v4f32, MVT::Other,
3964  /* 21 */ MVT::v2i64, MVT::v2f64, MVT::Other,
3965  /* 24 */ MVT::Untyped, MVT::Other,
3966};
3967
3968static const char *SubRegIndexNameTable[] = { "sub_32", "sub_64", "sub_dsp16_19", "sub_dsp20", "sub_dsp21", "sub_dsp22", "sub_dsp23", "sub_hi", "sub_lo", "sub_hi_then_sub_32", "sub_32_sub_hi_then_sub_32", "" };
3969
3970
3971static const LaneBitmask SubRegIndexLaneMaskTable[] = {
3972  LaneBitmask::getAll(),
3973  LaneBitmask(0x0000000000000001), // sub_32
3974  LaneBitmask(0x0000000000000041), // sub_64
3975  LaneBitmask(0x0000000000000002), // sub_dsp16_19
3976  LaneBitmask(0x0000000000000004), // sub_dsp20
3977  LaneBitmask(0x0000000000000008), // sub_dsp21
3978  LaneBitmask(0x0000000000000010), // sub_dsp22
3979  LaneBitmask(0x0000000000000020), // sub_dsp23
3980  LaneBitmask(0x0000000000000040), // sub_hi
3981  LaneBitmask(0x0000000000000001), // sub_lo
3982  LaneBitmask(0x0000000000000040), // sub_hi_then_sub_32
3983  LaneBitmask(0x0000000000000041), // sub_32_sub_hi_then_sub_32
3984 };
3985
3986
3987
3988static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
3989  // Mode = 0 (Default)
3990  { 16, 16, 128, VTLists+4 },    // MSA128F16
3991  { 32, 32, 32, VTLists+0 },    // CCR
3992  { 32, 32, 32, VTLists+0 },    // COP0
3993  { 32, 32, 32, VTLists+0 },    // COP2
3994  { 32, 32, 32, VTLists+0 },    // COP3
3995  { 32, 32, 32, VTLists+12 },    // DSPR
3996  { 32, 32, 32, VTLists+6 },    // FGR32
3997  { 32, 32, 32, VTLists+0 },    // FGRCC
3998  { 32, 32, 32, VTLists+0 },    // GPR32
3999  { 32, 32, 32, VTLists+0 },    // HWRegs
4000  { 32, 32, 32, VTLists+0 },    // MSACtrl
4001  { 32, 32, 32, VTLists+0 },    // GPR32NONZERO
4002  { 32, 32, 32, VTLists+0 },    // CPU16RegsPlusSP
4003  { 32, 32, 32, VTLists+0 },    // CPU16Regs
4004  { 32, 32, 32, VTLists+0 },    // FCC
4005  { 32, 32, 32, VTLists+0 },    // GPRMM16
4006  { 32, 32, 32, VTLists+0 },    // GPRMM16MoveP
4007  { 32, 32, 32, VTLists+0 },    // GPRMM16Zero
4008  { 32, 32, 32, VTLists+0 },    // CPU16Regs_and_GPRMM16Zero
4009  { 32, 32, 32, VTLists+0 },    // GPR32NONZERO_and_GPRMM16MoveP
4010  { 32, 32, 32, VTLists+0 },    // GPRMM16MovePPairSecond
4011  { 32, 32, 32, VTLists+0 },    // CPU16Regs_and_GPRMM16MoveP
4012  { 32, 32, 32, VTLists+0 },    // GPRMM16MoveP_and_GPRMM16Zero
4013  { 32, 32, 32, VTLists+0 },    // HI32DSP
4014  { 32, 32, 32, VTLists+0 },    // LO32DSP
4015  { 32, 32, 32, VTLists+0 },    // CPU16Regs_and_GPRMM16MovePPairSecond
4016  { 32, 32, 32, VTLists+0 },    // GPRMM16MovePPairFirst
4017  { 32, 32, 32, VTLists+0 },    // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
4018  { 32, 32, 32, VTLists+0 },    // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
4019  { 32, 32, 32, VTLists+0 },    // CPURAReg
4020  { 32, 32, 32, VTLists+0 },    // CPUSPReg
4021  { 32, 32, 32, VTLists+12 },    // DSPCC
4022  { 32, 32, 32, VTLists+0 },    // GP32
4023  { 32, 32, 32, VTLists+0 },    // GPR32ZERO
4024  { 32, 32, 32, VTLists+0 },    // HI32
4025  { 32, 32, 32, VTLists+0 },    // LO32
4026  { 32, 32, 32, VTLists+0 },    // SP32
4027  { 64, 64, 64, VTLists+8 },    // FGR64
4028  { 64, 64, 64, VTLists+2 },    // GPR64
4029  { 64, 64, 64, VTLists+2 },    // GPR64_with_sub_32_in_GPR32NONZERO
4030  { 64, 64, 64, VTLists+8 },    // AFGR64
4031  { 64, 64, 64, VTLists+2 },    // GPR64_with_sub_32_in_CPU16RegsPlusSP
4032  { 64, 64, 64, VTLists+2 },    // GPR64_with_sub_32_in_CPU16Regs
4033  { 64, 64, 64, VTLists+2 },    // GPR64_with_sub_32_in_GPRMM16MoveP
4034  { 64, 64, 64, VTLists+2 },    // GPR64_with_sub_32_in_GPRMM16Zero
4035  { 64, 64, 64, VTLists+2 },    // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
4036  { 64, 64, 64, VTLists+2 },    // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
4037  { 64, 64, 64, VTLists+2 },    // GPR64_with_sub_32_in_GPRMM16MovePPairSecond
4038  { 64, 64, 64, VTLists+24 },    // ACC64DSP
4039  { 64, 64, 64, VTLists+2 },    // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
4040  { 64, 64, 64, VTLists+2 },    // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
4041  { 64, 64, 64, VTLists+2 },    // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond
4042  { 64, 64, 64, VTLists+2 },    // GPR64_with_sub_32_in_GPRMM16MovePPairFirst
4043  { 64, 64, 64, VTLists+2 },    // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
4044  { 64, 64, 64, VTLists+2 },    // OCTEON_MPL
4045  { 64, 64, 64, VTLists+2 },    // OCTEON_P
4046  { 64, 64, 64, VTLists+2 },    // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
4047  { 64, 64, 64, VTLists+24 },    // ACC64
4048  { 64, 64, 64, VTLists+2 },    // GP64
4049  { 64, 64, 64, VTLists+2 },    // GPR64_with_sub_32_in_CPURAReg
4050  { 64, 64, 64, VTLists+2 },    // GPR64_with_sub_32_in_GPR32ZERO
4051  { 64, 64, 64, VTLists+2 },    // HI64
4052  { 64, 64, 64, VTLists+2 },    // LO64
4053  { 64, 64, 64, VTLists+2 },    // SP64
4054  { 128, 128, 128, VTLists+10 },    // MSA128B
4055  { 128, 128, 128, VTLists+21 },    // MSA128D
4056  { 128, 128, 128, VTLists+15 },    // MSA128H
4057  { 128, 128, 128, VTLists+18 },    // MSA128W
4058  { 128, 128, 128, VTLists+18 },    // MSA128WEvens
4059  { 128, 128, 128, VTLists+24 },    // ACC128
4060};
4061
4062static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
4063
4064static const uint32_t MSA128F16SubClassMask[] = {
4065  0x00000001, 0x00000000, 0x0000001f,
4066};
4067
4068static const uint32_t CCRSubClassMask[] = {
4069  0x00000002, 0x00000000, 0x00000000,
4070};
4071
4072static const uint32_t COP0SubClassMask[] = {
4073  0x00000004, 0x00000000, 0x00000000,
4074};
4075
4076static const uint32_t COP2SubClassMask[] = {
4077  0x00000008, 0x00000000, 0x00000000,
4078};
4079
4080static const uint32_t COP3SubClassMask[] = {
4081  0x00000010, 0x00000000, 0x00000000,
4082};
4083
4084static const uint32_t DSPRSubClassMask[] = {
4085  0x7e7fb920, 0x00000013, 0x00000000,
4086  0x00000000, 0x9d3efec0, 0x00000000, // sub_32
4087};
4088
4089static const uint32_t FGR32SubClassMask[] = {
4090  0x000000c0, 0x00000000, 0x00000000,
4091  0x00000000, 0x00000100, 0x00000000, // sub_hi
4092  0x00000001, 0x00000120, 0x0000001f, // sub_lo
4093};
4094
4095static const uint32_t FGRCCSubClassMask[] = {
4096  0x000000c0, 0x00000000, 0x00000000,
4097  0x00000000, 0x00000100, 0x00000000, // sub_hi
4098  0x00000001, 0x00000120, 0x0000001f, // sub_lo
4099};
4100
4101static const uint32_t GPR32SubClassMask[] = {
4102  0x7e7fb900, 0x00000013, 0x00000000,
4103  0x00000000, 0x9d3efec0, 0x00000000, // sub_32
4104};
4105
4106static const uint32_t HWRegsSubClassMask[] = {
4107  0x00000200, 0x00000000, 0x00000000,
4108};
4109
4110static const uint32_t MSACtrlSubClassMask[] = {
4111  0x00000400, 0x00000000, 0x00000000,
4112};
4113
4114static const uint32_t GPR32NONZEROSubClassMask[] = {
4115  0x7e3cb800, 0x00000011, 0x00000000,
4116  0x00000000, 0x8d3ae680, 0x00000000, // sub_32
4117};
4118
4119static const uint32_t CPU16RegsPlusSPSubClassMask[] = {
4120  0x5e24b000, 0x00000010, 0x00000000,
4121  0x00000000, 0x813a2600, 0x00000000, // sub_32
4122};
4123
4124static const uint32_t CPU16RegsSubClassMask[] = {
4125  0x1e24a000, 0x00000000, 0x00000000,
4126  0x00000000, 0x013a2400, 0x00000000, // sub_32
4127};
4128
4129static const uint32_t FCCSubClassMask[] = {
4130  0x00004000, 0x00000000, 0x00000000,
4131};
4132
4133static const uint32_t GPRMM16SubClassMask[] = {
4134  0x1e248000, 0x00000000, 0x00000000,
4135  0x00000000, 0x013a2400, 0x00000000, // sub_32
4136};
4137
4138static const uint32_t GPRMM16MovePSubClassMask[] = {
4139  0x08690000, 0x00000002, 0x00000000,
4140  0x00000000, 0x10264800, 0x00000000, // sub_32
4141};
4142
4143static const uint32_t GPRMM16ZeroSubClassMask[] = {
4144  0x1e460000, 0x00000002, 0x00000000,
4145  0x00000000, 0x113c3000, 0x00000000, // sub_32
4146};
4147
4148static const uint32_t CPU16Regs_and_GPRMM16ZeroSubClassMask[] = {
4149  0x1e040000, 0x00000000, 0x00000000,
4150  0x00000000, 0x01382000, 0x00000000, // sub_32
4151};
4152
4153static const uint32_t GPR32NONZERO_and_GPRMM16MovePSubClassMask[] = {
4154  0x08280000, 0x00000000, 0x00000000,
4155  0x00000000, 0x00224000, 0x00000000, // sub_32
4156};
4157
4158static const uint32_t GPRMM16MovePPairSecondSubClassMask[] = {
4159  0x12100000, 0x00000000, 0x00000000,
4160  0x00000000, 0x01088000, 0x00000000, // sub_32
4161};
4162
4163static const uint32_t CPU16Regs_and_GPRMM16MovePSubClassMask[] = {
4164  0x08200000, 0x00000000, 0x00000000,
4165  0x00000000, 0x00220000, 0x00000000, // sub_32
4166};
4167
4168static const uint32_t GPRMM16MoveP_and_GPRMM16ZeroSubClassMask[] = {
4169  0x08400000, 0x00000002, 0x00000000,
4170  0x00000000, 0x10240000, 0x00000000, // sub_32
4171};
4172
4173static const uint32_t HI32DSPSubClassMask[] = {
4174  0x00800000, 0x00000004, 0x00000000,
4175  0x00000000, 0x20000000, 0x00000000, // sub_32
4176  0x00000000, 0x02010000, 0x00000000, // sub_hi
4177  0x00000000, 0x00000000, 0x00000020, // sub_hi_then_sub_32
4178};
4179
4180static const uint32_t LO32DSPSubClassMask[] = {
4181  0x01000000, 0x00000008, 0x00000000,
4182  0x00000000, 0x40000000, 0x00000020, // sub_32
4183  0x00000000, 0x02010000, 0x00000000, // sub_lo
4184};
4185
4186static const uint32_t CPU16Regs_and_GPRMM16MovePPairSecondSubClassMask[] = {
4187  0x12000000, 0x00000000, 0x00000000,
4188  0x00000000, 0x01080000, 0x00000000, // sub_32
4189};
4190
4191static const uint32_t GPRMM16MovePPairFirstSubClassMask[] = {
4192  0x14000000, 0x00000000, 0x00000000,
4193  0x00000000, 0x01100000, 0x00000000, // sub_32
4194};
4195
4196static const uint32_t GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask[] = {
4197  0x08000000, 0x00000000, 0x00000000,
4198  0x00000000, 0x00200000, 0x00000000, // sub_32
4199};
4200
4201static const uint32_t GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSubClassMask[] = {
4202  0x10000000, 0x00000000, 0x00000000,
4203  0x00000000, 0x01000000, 0x00000000, // sub_32
4204};
4205
4206static const uint32_t CPURARegSubClassMask[] = {
4207  0x20000000, 0x00000000, 0x00000000,
4208  0x00000000, 0x08000000, 0x00000000, // sub_32
4209};
4210
4211static const uint32_t CPUSPRegSubClassMask[] = {
4212  0x40000000, 0x00000010, 0x00000000,
4213  0x00000000, 0x80000000, 0x00000000, // sub_32
4214};
4215
4216static const uint32_t DSPCCSubClassMask[] = {
4217  0x80000000, 0x00000000, 0x00000000,
4218};
4219
4220static const uint32_t GP32SubClassMask[] = {
4221  0x00000000, 0x00000001, 0x00000000,
4222  0x00000000, 0x04000000, 0x00000000, // sub_32
4223};
4224
4225static const uint32_t GPR32ZEROSubClassMask[] = {
4226  0x00000000, 0x00000002, 0x00000000,
4227  0x00000000, 0x10000000, 0x00000000, // sub_32
4228};
4229
4230static const uint32_t HI32SubClassMask[] = {
4231  0x00000000, 0x00000004, 0x00000000,
4232  0x00000000, 0x20000000, 0x00000000, // sub_32
4233  0x00000000, 0x02000000, 0x00000000, // sub_hi
4234  0x00000000, 0x00000000, 0x00000020, // sub_hi_then_sub_32
4235};
4236
4237static const uint32_t LO32SubClassMask[] = {
4238  0x00000000, 0x00000008, 0x00000000,
4239  0x00000000, 0x40000000, 0x00000020, // sub_32
4240  0x00000000, 0x02000000, 0x00000000, // sub_lo
4241};
4242
4243static const uint32_t SP32SubClassMask[] = {
4244  0x00000000, 0x00000010, 0x00000000,
4245  0x00000000, 0x80000000, 0x00000000, // sub_32
4246};
4247
4248static const uint32_t FGR64SubClassMask[] = {
4249  0x00000000, 0x00000020, 0x00000000,
4250  0x00000001, 0x00000000, 0x0000001f, // sub_64
4251};
4252
4253static const uint32_t GPR64SubClassMask[] = {
4254  0x00000000, 0x9d3efec0, 0x00000000,
4255};
4256
4257static const uint32_t GPR64_with_sub_32_in_GPR32NONZEROSubClassMask[] = {
4258  0x00000000, 0x8d3ae680, 0x00000000,
4259};
4260
4261static const uint32_t AFGR64SubClassMask[] = {
4262  0x00000000, 0x00000100, 0x00000000,
4263};
4264
4265static const uint32_t GPR64_with_sub_32_in_CPU16RegsPlusSPSubClassMask[] = {
4266  0x00000000, 0x813a2600, 0x00000000,
4267};
4268
4269static const uint32_t GPR64_with_sub_32_in_CPU16RegsSubClassMask[] = {
4270  0x00000000, 0x013a2400, 0x00000000,
4271};
4272
4273static const uint32_t GPR64_with_sub_32_in_GPRMM16MovePSubClassMask[] = {
4274  0x00000000, 0x10264800, 0x00000000,
4275};
4276
4277static const uint32_t GPR64_with_sub_32_in_GPRMM16ZeroSubClassMask[] = {
4278  0x00000000, 0x113c3000, 0x00000000,
4279};
4280
4281static const uint32_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSubClassMask[] = {
4282  0x00000000, 0x01382000, 0x00000000,
4283};
4284
4285static const uint32_t GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSubClassMask[] = {
4286  0x00000000, 0x00224000, 0x00000000,
4287};
4288
4289static const uint32_t GPR64_with_sub_32_in_GPRMM16MovePPairSecondSubClassMask[] = {
4290  0x00000000, 0x01088000, 0x00000000,
4291};
4292
4293static const uint32_t ACC64DSPSubClassMask[] = {
4294  0x00000000, 0x02010000, 0x00000000,
4295  0x00000000, 0x00000000, 0x00000020, // sub_32_sub_hi_then_sub_32
4296};
4297
4298static const uint32_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSubClassMask[] = {
4299  0x00000000, 0x00220000, 0x00000000,
4300};
4301
4302static const uint32_t GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSubClassMask[] = {
4303  0x00000000, 0x10240000, 0x00000000,
4304};
4305
4306static const uint32_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondSubClassMask[] = {
4307  0x00000000, 0x01080000, 0x00000000,
4308};
4309
4310static const uint32_t GPR64_with_sub_32_in_GPRMM16MovePPairFirstSubClassMask[] = {
4311  0x00000000, 0x01100000, 0x00000000,
4312};
4313
4314static const uint32_t GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask[] = {
4315  0x00000000, 0x00200000, 0x00000000,
4316};
4317
4318static const uint32_t OCTEON_MPLSubClassMask[] = {
4319  0x00000000, 0x00400000, 0x00000000,
4320};
4321
4322static const uint32_t OCTEON_PSubClassMask[] = {
4323  0x00000000, 0x00800000, 0x00000000,
4324};
4325
4326static const uint32_t GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSubClassMask[] = {
4327  0x00000000, 0x01000000, 0x00000000,
4328};
4329
4330static const uint32_t ACC64SubClassMask[] = {
4331  0x00000000, 0x02000000, 0x00000000,
4332  0x00000000, 0x00000000, 0x00000020, // sub_32_sub_hi_then_sub_32
4333};
4334
4335static const uint32_t GP64SubClassMask[] = {
4336  0x00000000, 0x04000000, 0x00000000,
4337};
4338
4339static const uint32_t GPR64_with_sub_32_in_CPURARegSubClassMask[] = {
4340  0x00000000, 0x08000000, 0x00000000,
4341};
4342
4343static const uint32_t GPR64_with_sub_32_in_GPR32ZEROSubClassMask[] = {
4344  0x00000000, 0x10000000, 0x00000000,
4345};
4346
4347static const uint32_t HI64SubClassMask[] = {
4348  0x00000000, 0x20000000, 0x00000000,
4349  0x00000000, 0x00000000, 0x00000020, // sub_hi
4350};
4351
4352static const uint32_t LO64SubClassMask[] = {
4353  0x00000000, 0x40000000, 0x00000000,
4354  0x00000000, 0x00000000, 0x00000020, // sub_lo
4355};
4356
4357static const uint32_t SP64SubClassMask[] = {
4358  0x00000000, 0x80000000, 0x00000000,
4359};
4360
4361static const uint32_t MSA128BSubClassMask[] = {
4362  0x00000000, 0x00000000, 0x0000001f,
4363};
4364
4365static const uint32_t MSA128DSubClassMask[] = {
4366  0x00000000, 0x00000000, 0x0000001f,
4367};
4368
4369static const uint32_t MSA128HSubClassMask[] = {
4370  0x00000000, 0x00000000, 0x0000001f,
4371};
4372
4373static const uint32_t MSA128WSubClassMask[] = {
4374  0x00000000, 0x00000000, 0x0000001f,
4375};
4376
4377static const uint32_t MSA128WEvensSubClassMask[] = {
4378  0x00000000, 0x00000000, 0x00000010,
4379};
4380
4381static const uint32_t ACC128SubClassMask[] = {
4382  0x00000000, 0x00000000, 0x00000020,
4383};
4384
4385static const uint16_t SuperRegIdxSeqs[] = {
4386  /* 0 */ 1, 0,
4387  /* 2 */ 2, 0,
4388  /* 4 */ 8, 0,
4389  /* 6 */ 1, 9, 0,
4390  /* 9 */ 8, 9, 0,
4391  /* 12 */ 1, 8, 10, 0,
4392  /* 16 */ 11, 0,
4393};
4394
4395static const TargetRegisterClass *const FGR32Superclasses[] = {
4396  &Mips::FGRCCRegClass,
4397  nullptr
4398};
4399
4400static const TargetRegisterClass *const FGRCCSuperclasses[] = {
4401  &Mips::FGR32RegClass,
4402  nullptr
4403};
4404
4405static const TargetRegisterClass *const GPR32Superclasses[] = {
4406  &Mips::DSPRRegClass,
4407  nullptr
4408};
4409
4410static const TargetRegisterClass *const GPR32NONZEROSuperclasses[] = {
4411  &Mips::DSPRRegClass,
4412  &Mips::GPR32RegClass,
4413  nullptr
4414};
4415
4416static const TargetRegisterClass *const CPU16RegsPlusSPSuperclasses[] = {
4417  &Mips::DSPRRegClass,
4418  &Mips::GPR32RegClass,
4419  &Mips::GPR32NONZERORegClass,
4420  nullptr
4421};
4422
4423static const TargetRegisterClass *const CPU16RegsSuperclasses[] = {
4424  &Mips::DSPRRegClass,
4425  &Mips::GPR32RegClass,
4426  &Mips::GPR32NONZERORegClass,
4427  &Mips::CPU16RegsPlusSPRegClass,
4428  nullptr
4429};
4430
4431static const TargetRegisterClass *const GPRMM16Superclasses[] = {
4432  &Mips::DSPRRegClass,
4433  &Mips::GPR32RegClass,
4434  &Mips::GPR32NONZERORegClass,
4435  &Mips::CPU16RegsPlusSPRegClass,
4436  &Mips::CPU16RegsRegClass,
4437  nullptr
4438};
4439
4440static const TargetRegisterClass *const GPRMM16MovePSuperclasses[] = {
4441  &Mips::DSPRRegClass,
4442  &Mips::GPR32RegClass,
4443  nullptr
4444};
4445
4446static const TargetRegisterClass *const GPRMM16ZeroSuperclasses[] = {
4447  &Mips::DSPRRegClass,
4448  &Mips::GPR32RegClass,
4449  nullptr
4450};
4451
4452static const TargetRegisterClass *const CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {
4453  &Mips::DSPRRegClass,
4454  &Mips::GPR32RegClass,
4455  &Mips::GPR32NONZERORegClass,
4456  &Mips::CPU16RegsPlusSPRegClass,
4457  &Mips::CPU16RegsRegClass,
4458  &Mips::GPRMM16RegClass,
4459  &Mips::GPRMM16ZeroRegClass,
4460  nullptr
4461};
4462
4463static const TargetRegisterClass *const GPR32NONZERO_and_GPRMM16MovePSuperclasses[] = {
4464  &Mips::DSPRRegClass,
4465  &Mips::GPR32RegClass,
4466  &Mips::GPR32NONZERORegClass,
4467  &Mips::GPRMM16MovePRegClass,
4468  nullptr
4469};
4470
4471static const TargetRegisterClass *const GPRMM16MovePPairSecondSuperclasses[] = {
4472  &Mips::DSPRRegClass,
4473  &Mips::GPR32RegClass,
4474  &Mips::GPR32NONZERORegClass,
4475  nullptr
4476};
4477
4478static const TargetRegisterClass *const CPU16Regs_and_GPRMM16MovePSuperclasses[] = {
4479  &Mips::DSPRRegClass,
4480  &Mips::GPR32RegClass,
4481  &Mips::GPR32NONZERORegClass,
4482  &Mips::CPU16RegsPlusSPRegClass,
4483  &Mips::CPU16RegsRegClass,
4484  &Mips::GPRMM16RegClass,
4485  &Mips::GPRMM16MovePRegClass,
4486  &Mips::GPR32NONZERO_and_GPRMM16MovePRegClass,
4487  nullptr
4488};
4489
4490static const TargetRegisterClass *const GPRMM16MoveP_and_GPRMM16ZeroSuperclasses[] = {
4491  &Mips::DSPRRegClass,
4492  &Mips::GPR32RegClass,
4493  &Mips::GPRMM16MovePRegClass,
4494  &Mips::GPRMM16ZeroRegClass,
4495  nullptr
4496};
4497
4498static const TargetRegisterClass *const CPU16Regs_and_GPRMM16MovePPairSecondSuperclasses[] = {
4499  &Mips::DSPRRegClass,
4500  &Mips::GPR32RegClass,
4501  &Mips::GPR32NONZERORegClass,
4502  &Mips::CPU16RegsPlusSPRegClass,
4503  &Mips::CPU16RegsRegClass,
4504  &Mips::GPRMM16RegClass,
4505  &Mips::GPRMM16ZeroRegClass,
4506  &Mips::CPU16Regs_and_GPRMM16ZeroRegClass,
4507  &Mips::GPRMM16MovePPairSecondRegClass,
4508  nullptr
4509};
4510
4511static const TargetRegisterClass *const GPRMM16MovePPairFirstSuperclasses[] = {
4512  &Mips::DSPRRegClass,
4513  &Mips::GPR32RegClass,
4514  &Mips::GPR32NONZERORegClass,
4515  &Mips::CPU16RegsPlusSPRegClass,
4516  &Mips::CPU16RegsRegClass,
4517  &Mips::GPRMM16RegClass,
4518  &Mips::GPRMM16ZeroRegClass,
4519  &Mips::CPU16Regs_and_GPRMM16ZeroRegClass,
4520  nullptr
4521};
4522
4523static const TargetRegisterClass *const GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {
4524  &Mips::DSPRRegClass,
4525  &Mips::GPR32RegClass,
4526  &Mips::GPR32NONZERORegClass,
4527  &Mips::CPU16RegsPlusSPRegClass,
4528  &Mips::CPU16RegsRegClass,
4529  &Mips::GPRMM16RegClass,
4530  &Mips::GPRMM16MovePRegClass,
4531  &Mips::GPRMM16ZeroRegClass,
4532  &Mips::CPU16Regs_and_GPRMM16ZeroRegClass,
4533  &Mips::GPR32NONZERO_and_GPRMM16MovePRegClass,
4534  &Mips::CPU16Regs_and_GPRMM16MovePRegClass,
4535  &Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClass,
4536  nullptr
4537};
4538
4539static const TargetRegisterClass *const GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSuperclasses[] = {
4540  &Mips::DSPRRegClass,
4541  &Mips::GPR32RegClass,
4542  &Mips::GPR32NONZERORegClass,
4543  &Mips::CPU16RegsPlusSPRegClass,
4544  &Mips::CPU16RegsRegClass,
4545  &Mips::GPRMM16RegClass,
4546  &Mips::GPRMM16ZeroRegClass,
4547  &Mips::CPU16Regs_and_GPRMM16ZeroRegClass,
4548  &Mips::GPRMM16MovePPairSecondRegClass,
4549  &Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClass,
4550  &Mips::GPRMM16MovePPairFirstRegClass,
4551  nullptr
4552};
4553
4554static const TargetRegisterClass *const CPURARegSuperclasses[] = {
4555  &Mips::DSPRRegClass,
4556  &Mips::GPR32RegClass,
4557  &Mips::GPR32NONZERORegClass,
4558  nullptr
4559};
4560
4561static const TargetRegisterClass *const CPUSPRegSuperclasses[] = {
4562  &Mips::DSPRRegClass,
4563  &Mips::GPR32RegClass,
4564  &Mips::GPR32NONZERORegClass,
4565  &Mips::CPU16RegsPlusSPRegClass,
4566  nullptr
4567};
4568
4569static const TargetRegisterClass *const GP32Superclasses[] = {
4570  &Mips::DSPRRegClass,
4571  &Mips::GPR32RegClass,
4572  &Mips::GPR32NONZERORegClass,
4573  nullptr
4574};
4575
4576static const TargetRegisterClass *const GPR32ZEROSuperclasses[] = {
4577  &Mips::DSPRRegClass,
4578  &Mips::GPR32RegClass,
4579  &Mips::GPRMM16MovePRegClass,
4580  &Mips::GPRMM16ZeroRegClass,
4581  &Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClass,
4582  nullptr
4583};
4584
4585static const TargetRegisterClass *const HI32Superclasses[] = {
4586  &Mips::HI32DSPRegClass,
4587  nullptr
4588};
4589
4590static const TargetRegisterClass *const LO32Superclasses[] = {
4591  &Mips::LO32DSPRegClass,
4592  nullptr
4593};
4594
4595static const TargetRegisterClass *const SP32Superclasses[] = {
4596  &Mips::DSPRRegClass,
4597  &Mips::GPR32RegClass,
4598  &Mips::GPR32NONZERORegClass,
4599  &Mips::CPU16RegsPlusSPRegClass,
4600  &Mips::CPUSPRegRegClass,
4601  nullptr
4602};
4603
4604static const TargetRegisterClass *const GPR64_with_sub_32_in_GPR32NONZEROSuperclasses[] = {
4605  &Mips::GPR64RegClass,
4606  nullptr
4607};
4608
4609static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16RegsPlusSPSuperclasses[] = {
4610  &Mips::GPR64RegClass,
4611  &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4612  nullptr
4613};
4614
4615static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16RegsSuperclasses[] = {
4616  &Mips::GPR64RegClass,
4617  &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4618  &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
4619  nullptr
4620};
4621
4622static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MovePSuperclasses[] = {
4623  &Mips::GPR64RegClass,
4624  nullptr
4625};
4626
4627static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16ZeroSuperclasses[] = {
4628  &Mips::GPR64RegClass,
4629  nullptr
4630};
4631
4632static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {
4633  &Mips::GPR64RegClass,
4634  &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4635  &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
4636  &Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,
4637  &Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,
4638  nullptr
4639};
4640
4641static const TargetRegisterClass *const GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSuperclasses[] = {
4642  &Mips::GPR64RegClass,
4643  &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4644  &Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,
4645  nullptr
4646};
4647
4648static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MovePPairSecondSuperclasses[] = {
4649  &Mips::GPR64RegClass,
4650  &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4651  nullptr
4652};
4653
4654static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSuperclasses[] = {
4655  &Mips::GPR64RegClass,
4656  &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4657  &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
4658  &Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,
4659  &Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,
4660  &Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass,
4661  nullptr
4662};
4663
4664static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSuperclasses[] = {
4665  &Mips::GPR64RegClass,
4666  &Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,
4667  &Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,
4668  nullptr
4669};
4670
4671static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondSuperclasses[] = {
4672  &Mips::GPR64RegClass,
4673  &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4674  &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
4675  &Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,
4676  &Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,
4677  &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass,
4678  &Mips::GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClass,
4679  nullptr
4680};
4681
4682static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MovePPairFirstSuperclasses[] = {
4683  &Mips::GPR64RegClass,
4684  &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4685  &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
4686  &Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,
4687  &Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,
4688  &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass,
4689  nullptr
4690};
4691
4692static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {
4693  &Mips::GPR64RegClass,
4694  &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4695  &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
4696  &Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,
4697  &Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,
4698  &Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,
4699  &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass,
4700  &Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass,
4701  &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClass,
4702  &Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass,
4703  nullptr
4704};
4705
4706static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSuperclasses[] = {
4707  &Mips::GPR64RegClass,
4708  &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4709  &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
4710  &Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,
4711  &Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,
4712  &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass,
4713  &Mips::GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClass,
4714  &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClass,
4715  &Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClass,
4716  nullptr
4717};
4718
4719static const TargetRegisterClass *const ACC64Superclasses[] = {
4720  &Mips::ACC64DSPRegClass,
4721  nullptr
4722};
4723
4724static const TargetRegisterClass *const GP64Superclasses[] = {
4725  &Mips::GPR64RegClass,
4726  &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4727  nullptr
4728};
4729
4730static const TargetRegisterClass *const GPR64_with_sub_32_in_CPURARegSuperclasses[] = {
4731  &Mips::GPR64RegClass,
4732  &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4733  nullptr
4734};
4735
4736static const TargetRegisterClass *const GPR64_with_sub_32_in_GPR32ZEROSuperclasses[] = {
4737  &Mips::GPR64RegClass,
4738  &Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,
4739  &Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,
4740  &Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass,
4741  nullptr
4742};
4743
4744static const TargetRegisterClass *const SP64Superclasses[] = {
4745  &Mips::GPR64RegClass,
4746  &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4747  &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
4748  nullptr
4749};
4750
4751static const TargetRegisterClass *const MSA128BSuperclasses[] = {
4752  &Mips::MSA128F16RegClass,
4753  &Mips::MSA128DRegClass,
4754  &Mips::MSA128HRegClass,
4755  &Mips::MSA128WRegClass,
4756  nullptr
4757};
4758
4759static const TargetRegisterClass *const MSA128DSuperclasses[] = {
4760  &Mips::MSA128F16RegClass,
4761  &Mips::MSA128BRegClass,
4762  &Mips::MSA128HRegClass,
4763  &Mips::MSA128WRegClass,
4764  nullptr
4765};
4766
4767static const TargetRegisterClass *const MSA128HSuperclasses[] = {
4768  &Mips::MSA128F16RegClass,
4769  &Mips::MSA128BRegClass,
4770  &Mips::MSA128DRegClass,
4771  &Mips::MSA128WRegClass,
4772  nullptr
4773};
4774
4775static const TargetRegisterClass *const MSA128WSuperclasses[] = {
4776  &Mips::MSA128F16RegClass,
4777  &Mips::MSA128BRegClass,
4778  &Mips::MSA128DRegClass,
4779  &Mips::MSA128HRegClass,
4780  nullptr
4781};
4782
4783static const TargetRegisterClass *const MSA128WEvensSuperclasses[] = {
4784  &Mips::MSA128F16RegClass,
4785  &Mips::MSA128BRegClass,
4786  &Mips::MSA128DRegClass,
4787  &Mips::MSA128HRegClass,
4788  &Mips::MSA128WRegClass,
4789  nullptr
4790};
4791
4792
4793static inline unsigned FGR32AltOrderSelect(const MachineFunction &MF) {
4794    const auto & S = MF.getSubtarget<MipsSubtarget>();
4795    return S.isABI_O32() && !S.useOddSPReg();
4796  }
4797
4798static ArrayRef<MCPhysReg> FGR32GetRawAllocationOrder(const MachineFunction &MF) {
4799  static const MCPhysReg AltOrder1[] = { Mips::F0, Mips::F2, Mips::F4, Mips::F6, Mips::F8, Mips::F10, Mips::F12, Mips::F14, Mips::F16, Mips::F18, Mips::F20, Mips::F22, Mips::F24, Mips::F26, Mips::F28, Mips::F30 };
4800  const MCRegisterClass &MCR = MipsMCRegisterClasses[Mips::FGR32RegClassID];
4801  const ArrayRef<MCPhysReg> Order[] = {
4802    ArrayRef(MCR.begin(), MCR.getNumRegs()),
4803    ArrayRef(AltOrder1)
4804  };
4805  const unsigned Select = FGR32AltOrderSelect(MF);
4806  assert(Select < 2);
4807  return Order[Select];
4808}
4809
4810static inline unsigned FGR64AltOrderSelect(const MachineFunction &MF) {
4811    const auto & S = MF.getSubtarget<MipsSubtarget>();
4812    return S.isABI_O32() && !S.useOddSPReg();
4813  }
4814
4815static ArrayRef<MCPhysReg> FGR64GetRawAllocationOrder(const MachineFunction &MF) {
4816  static const MCPhysReg AltOrder1[] = { Mips::D0_64, Mips::D2_64, Mips::D4_64, Mips::D6_64, Mips::D8_64, Mips::D10_64, Mips::D12_64, Mips::D14_64, Mips::D16_64, Mips::D18_64, Mips::D20_64, Mips::D22_64, Mips::D24_64, Mips::D26_64, Mips::D28_64, Mips::D30_64 };
4817  const MCRegisterClass &MCR = MipsMCRegisterClasses[Mips::FGR64RegClassID];
4818  const ArrayRef<MCPhysReg> Order[] = {
4819    ArrayRef(MCR.begin(), MCR.getNumRegs()),
4820    ArrayRef(AltOrder1)
4821  };
4822  const unsigned Select = FGR64AltOrderSelect(MF);
4823  assert(Select < 2);
4824  return Order[Select];
4825}
4826
4827namespace Mips {   // Register class instances
4828  extern const TargetRegisterClass MSA128F16RegClass = {
4829    &MipsMCRegisterClasses[MSA128F16RegClassID],
4830    MSA128F16SubClassMask,
4831    SuperRegIdxSeqs + 1,
4832    LaneBitmask(0x0000000000000041),
4833    0,
4834    false,
4835    0x00, /* TSFlags */
4836    true, /* HasDisjunctSubRegs */
4837    false, /* CoveredBySubRegs */
4838    NullRegClasses,
4839    nullptr
4840  };
4841
4842  extern const TargetRegisterClass CCRRegClass = {
4843    &MipsMCRegisterClasses[CCRRegClassID],
4844    CCRSubClassMask,
4845    SuperRegIdxSeqs + 1,
4846    LaneBitmask(0x0000000000000001),
4847    0,
4848    false,
4849    0x00, /* TSFlags */
4850    false, /* HasDisjunctSubRegs */
4851    false, /* CoveredBySubRegs */
4852    NullRegClasses,
4853    nullptr
4854  };
4855
4856  extern const TargetRegisterClass COP0RegClass = {
4857    &MipsMCRegisterClasses[COP0RegClassID],
4858    COP0SubClassMask,
4859    SuperRegIdxSeqs + 1,
4860    LaneBitmask(0x0000000000000001),
4861    0,
4862    false,
4863    0x00, /* TSFlags */
4864    false, /* HasDisjunctSubRegs */
4865    false, /* CoveredBySubRegs */
4866    NullRegClasses,
4867    nullptr
4868  };
4869
4870  extern const TargetRegisterClass COP2RegClass = {
4871    &MipsMCRegisterClasses[COP2RegClassID],
4872    COP2SubClassMask,
4873    SuperRegIdxSeqs + 1,
4874    LaneBitmask(0x0000000000000001),
4875    0,
4876    false,
4877    0x00, /* TSFlags */
4878    false, /* HasDisjunctSubRegs */
4879    false, /* CoveredBySubRegs */
4880    NullRegClasses,
4881    nullptr
4882  };
4883
4884  extern const TargetRegisterClass COP3RegClass = {
4885    &MipsMCRegisterClasses[COP3RegClassID],
4886    COP3SubClassMask,
4887    SuperRegIdxSeqs + 1,
4888    LaneBitmask(0x0000000000000001),
4889    0,
4890    false,
4891    0x00, /* TSFlags */
4892    false, /* HasDisjunctSubRegs */
4893    false, /* CoveredBySubRegs */
4894    NullRegClasses,
4895    nullptr
4896  };
4897
4898  extern const TargetRegisterClass DSPRRegClass = {
4899    &MipsMCRegisterClasses[DSPRRegClassID],
4900    DSPRSubClassMask,
4901    SuperRegIdxSeqs + 0,
4902    LaneBitmask(0x0000000000000001),
4903    0,
4904    false,
4905    0x00, /* TSFlags */
4906    false, /* HasDisjunctSubRegs */
4907    false, /* CoveredBySubRegs */
4908    NullRegClasses,
4909    nullptr
4910  };
4911
4912  extern const TargetRegisterClass FGR32RegClass = {
4913    &MipsMCRegisterClasses[FGR32RegClassID],
4914    FGR32SubClassMask,
4915    SuperRegIdxSeqs + 9,
4916    LaneBitmask(0x0000000000000001),
4917    0,
4918    false,
4919    0x00, /* TSFlags */
4920    false, /* HasDisjunctSubRegs */
4921    false, /* CoveredBySubRegs */
4922    FGR32Superclasses,
4923    FGR32GetRawAllocationOrder
4924  };
4925
4926  extern const TargetRegisterClass FGRCCRegClass = {
4927    &MipsMCRegisterClasses[FGRCCRegClassID],
4928    FGRCCSubClassMask,
4929    SuperRegIdxSeqs + 9,
4930    LaneBitmask(0x0000000000000001),
4931    0,
4932    false,
4933    0x00, /* TSFlags */
4934    false, /* HasDisjunctSubRegs */
4935    false, /* CoveredBySubRegs */
4936    FGRCCSuperclasses,
4937    nullptr
4938  };
4939
4940  extern const TargetRegisterClass GPR32RegClass = {
4941    &MipsMCRegisterClasses[GPR32RegClassID],
4942    GPR32SubClassMask,
4943    SuperRegIdxSeqs + 0,
4944    LaneBitmask(0x0000000000000001),
4945    0,
4946    false,
4947    0x00, /* TSFlags */
4948    false, /* HasDisjunctSubRegs */
4949    false, /* CoveredBySubRegs */
4950    GPR32Superclasses,
4951    nullptr
4952  };
4953
4954  extern const TargetRegisterClass HWRegsRegClass = {
4955    &MipsMCRegisterClasses[HWRegsRegClassID],
4956    HWRegsSubClassMask,
4957    SuperRegIdxSeqs + 1,
4958    LaneBitmask(0x0000000000000001),
4959    0,
4960    false,
4961    0x00, /* TSFlags */
4962    false, /* HasDisjunctSubRegs */
4963    false, /* CoveredBySubRegs */
4964    NullRegClasses,
4965    nullptr
4966  };
4967
4968  extern const TargetRegisterClass MSACtrlRegClass = {
4969    &MipsMCRegisterClasses[MSACtrlRegClassID],
4970    MSACtrlSubClassMask,
4971    SuperRegIdxSeqs + 1,
4972    LaneBitmask(0x0000000000000001),
4973    0,
4974    false,
4975    0x00, /* TSFlags */
4976    false, /* HasDisjunctSubRegs */
4977    false, /* CoveredBySubRegs */
4978    NullRegClasses,
4979    nullptr
4980  };
4981
4982  extern const TargetRegisterClass GPR32NONZERORegClass = {
4983    &MipsMCRegisterClasses[GPR32NONZERORegClassID],
4984    GPR32NONZEROSubClassMask,
4985    SuperRegIdxSeqs + 0,
4986    LaneBitmask(0x0000000000000001),
4987    0,
4988    false,
4989    0x00, /* TSFlags */
4990    false, /* HasDisjunctSubRegs */
4991    false, /* CoveredBySubRegs */
4992    GPR32NONZEROSuperclasses,
4993    nullptr
4994  };
4995
4996  extern const TargetRegisterClass CPU16RegsPlusSPRegClass = {
4997    &MipsMCRegisterClasses[CPU16RegsPlusSPRegClassID],
4998    CPU16RegsPlusSPSubClassMask,
4999    SuperRegIdxSeqs + 0,
5000    LaneBitmask(0x0000000000000001),
5001    0,
5002    false,
5003    0x00, /* TSFlags */
5004    false, /* HasDisjunctSubRegs */
5005    false, /* CoveredBySubRegs */
5006    CPU16RegsPlusSPSuperclasses,
5007    nullptr
5008  };
5009
5010  extern const TargetRegisterClass CPU16RegsRegClass = {
5011    &MipsMCRegisterClasses[CPU16RegsRegClassID],
5012    CPU16RegsSubClassMask,
5013    SuperRegIdxSeqs + 0,
5014    LaneBitmask(0x0000000000000001),
5015    0,
5016    false,
5017    0x00, /* TSFlags */
5018    false, /* HasDisjunctSubRegs */
5019    false, /* CoveredBySubRegs */
5020    CPU16RegsSuperclasses,
5021    nullptr
5022  };
5023
5024  extern const TargetRegisterClass FCCRegClass = {
5025    &MipsMCRegisterClasses[FCCRegClassID],
5026    FCCSubClassMask,
5027    SuperRegIdxSeqs + 1,
5028    LaneBitmask(0x0000000000000001),
5029    0,
5030    false,
5031    0x00, /* TSFlags */
5032    false, /* HasDisjunctSubRegs */
5033    false, /* CoveredBySubRegs */
5034    NullRegClasses,
5035    nullptr
5036  };
5037
5038  extern const TargetRegisterClass GPRMM16RegClass = {
5039    &MipsMCRegisterClasses[GPRMM16RegClassID],
5040    GPRMM16SubClassMask,
5041    SuperRegIdxSeqs + 0,
5042    LaneBitmask(0x0000000000000001),
5043    0,
5044    false,
5045    0x00, /* TSFlags */
5046    false, /* HasDisjunctSubRegs */
5047    false, /* CoveredBySubRegs */
5048    GPRMM16Superclasses,
5049    nullptr
5050  };
5051
5052  extern const TargetRegisterClass GPRMM16MovePRegClass = {
5053    &MipsMCRegisterClasses[GPRMM16MovePRegClassID],
5054    GPRMM16MovePSubClassMask,
5055    SuperRegIdxSeqs + 0,
5056    LaneBitmask(0x0000000000000001),
5057    0,
5058    false,
5059    0x00, /* TSFlags */
5060    false, /* HasDisjunctSubRegs */
5061    false, /* CoveredBySubRegs */
5062    GPRMM16MovePSuperclasses,
5063    nullptr
5064  };
5065
5066  extern const TargetRegisterClass GPRMM16ZeroRegClass = {
5067    &MipsMCRegisterClasses[GPRMM16ZeroRegClassID],
5068    GPRMM16ZeroSubClassMask,
5069    SuperRegIdxSeqs + 0,
5070    LaneBitmask(0x0000000000000001),
5071    0,
5072    false,
5073    0x00, /* TSFlags */
5074    false, /* HasDisjunctSubRegs */
5075    false, /* CoveredBySubRegs */
5076    GPRMM16ZeroSuperclasses,
5077    nullptr
5078  };
5079
5080  extern const TargetRegisterClass CPU16Regs_and_GPRMM16ZeroRegClass = {
5081    &MipsMCRegisterClasses[CPU16Regs_and_GPRMM16ZeroRegClassID],
5082    CPU16Regs_and_GPRMM16ZeroSubClassMask,
5083    SuperRegIdxSeqs + 0,
5084    LaneBitmask(0x0000000000000001),
5085    0,
5086    false,
5087    0x00, /* TSFlags */
5088    false, /* HasDisjunctSubRegs */
5089    false, /* CoveredBySubRegs */
5090    CPU16Regs_and_GPRMM16ZeroSuperclasses,
5091    nullptr
5092  };
5093
5094  extern const TargetRegisterClass GPR32NONZERO_and_GPRMM16MovePRegClass = {
5095    &MipsMCRegisterClasses[GPR32NONZERO_and_GPRMM16MovePRegClassID],
5096    GPR32NONZERO_and_GPRMM16MovePSubClassMask,
5097    SuperRegIdxSeqs + 0,
5098    LaneBitmask(0x0000000000000001),
5099    0,
5100    false,
5101    0x00, /* TSFlags */
5102    false, /* HasDisjunctSubRegs */
5103    false, /* CoveredBySubRegs */
5104    GPR32NONZERO_and_GPRMM16MovePSuperclasses,
5105    nullptr
5106  };
5107
5108  extern const TargetRegisterClass GPRMM16MovePPairSecondRegClass = {
5109    &MipsMCRegisterClasses[GPRMM16MovePPairSecondRegClassID],
5110    GPRMM16MovePPairSecondSubClassMask,
5111    SuperRegIdxSeqs + 0,
5112    LaneBitmask(0x0000000000000001),
5113    0,
5114    false,
5115    0x00, /* TSFlags */
5116    false, /* HasDisjunctSubRegs */
5117    false, /* CoveredBySubRegs */
5118    GPRMM16MovePPairSecondSuperclasses,
5119    nullptr
5120  };
5121
5122  extern const TargetRegisterClass CPU16Regs_and_GPRMM16MovePRegClass = {
5123    &MipsMCRegisterClasses[CPU16Regs_and_GPRMM16MovePRegClassID],
5124    CPU16Regs_and_GPRMM16MovePSubClassMask,
5125    SuperRegIdxSeqs + 0,
5126    LaneBitmask(0x0000000000000001),
5127    0,
5128    false,
5129    0x00, /* TSFlags */
5130    false, /* HasDisjunctSubRegs */
5131    false, /* CoveredBySubRegs */
5132    CPU16Regs_and_GPRMM16MovePSuperclasses,
5133    nullptr
5134  };
5135
5136  extern const TargetRegisterClass GPRMM16MoveP_and_GPRMM16ZeroRegClass = {
5137    &MipsMCRegisterClasses[GPRMM16MoveP_and_GPRMM16ZeroRegClassID],
5138    GPRMM16MoveP_and_GPRMM16ZeroSubClassMask,
5139    SuperRegIdxSeqs + 0,
5140    LaneBitmask(0x0000000000000001),
5141    0,
5142    false,
5143    0x00, /* TSFlags */
5144    false, /* HasDisjunctSubRegs */
5145    false, /* CoveredBySubRegs */
5146    GPRMM16MoveP_and_GPRMM16ZeroSuperclasses,
5147    nullptr
5148  };
5149
5150  extern const TargetRegisterClass HI32DSPRegClass = {
5151    &MipsMCRegisterClasses[HI32DSPRegClassID],
5152    HI32DSPSubClassMask,
5153    SuperRegIdxSeqs + 12,
5154    LaneBitmask(0x0000000000000001),
5155    0,
5156    false,
5157    0x00, /* TSFlags */
5158    false, /* HasDisjunctSubRegs */
5159    false, /* CoveredBySubRegs */
5160    NullRegClasses,
5161    nullptr
5162  };
5163
5164  extern const TargetRegisterClass LO32DSPRegClass = {
5165    &MipsMCRegisterClasses[LO32DSPRegClassID],
5166    LO32DSPSubClassMask,
5167    SuperRegIdxSeqs + 6,
5168    LaneBitmask(0x0000000000000001),
5169    0,
5170    false,
5171    0x00, /* TSFlags */
5172    false, /* HasDisjunctSubRegs */
5173    false, /* CoveredBySubRegs */
5174    NullRegClasses,
5175    nullptr
5176  };
5177
5178  extern const TargetRegisterClass CPU16Regs_and_GPRMM16MovePPairSecondRegClass = {
5179    &MipsMCRegisterClasses[CPU16Regs_and_GPRMM16MovePPairSecondRegClassID],
5180    CPU16Regs_and_GPRMM16MovePPairSecondSubClassMask,
5181    SuperRegIdxSeqs + 0,
5182    LaneBitmask(0x0000000000000001),
5183    0,
5184    false,
5185    0x00, /* TSFlags */
5186    false, /* HasDisjunctSubRegs */
5187    false, /* CoveredBySubRegs */
5188    CPU16Regs_and_GPRMM16MovePPairSecondSuperclasses,
5189    nullptr
5190  };
5191
5192  extern const TargetRegisterClass GPRMM16MovePPairFirstRegClass = {
5193    &MipsMCRegisterClasses[GPRMM16MovePPairFirstRegClassID],
5194    GPRMM16MovePPairFirstSubClassMask,
5195    SuperRegIdxSeqs + 0,
5196    LaneBitmask(0x0000000000000001),
5197    0,
5198    false,
5199    0x00, /* TSFlags */
5200    false, /* HasDisjunctSubRegs */
5201    false, /* CoveredBySubRegs */
5202    GPRMM16MovePPairFirstSuperclasses,
5203    nullptr
5204  };
5205
5206  extern const TargetRegisterClass GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass = {
5207    &MipsMCRegisterClasses[GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID],
5208    GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask,
5209    SuperRegIdxSeqs + 0,
5210    LaneBitmask(0x0000000000000001),
5211    0,
5212    false,
5213    0x00, /* TSFlags */
5214    false, /* HasDisjunctSubRegs */
5215    false, /* CoveredBySubRegs */
5216    GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses,
5217    nullptr
5218  };
5219
5220  extern const TargetRegisterClass GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass = {
5221    &MipsMCRegisterClasses[GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID],
5222    GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSubClassMask,
5223    SuperRegIdxSeqs + 0,
5224    LaneBitmask(0x0000000000000001),
5225    0,
5226    false,
5227    0x00, /* TSFlags */
5228    false, /* HasDisjunctSubRegs */
5229    false, /* CoveredBySubRegs */
5230    GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSuperclasses,
5231    nullptr
5232  };
5233
5234  extern const TargetRegisterClass CPURARegRegClass = {
5235    &MipsMCRegisterClasses[CPURARegRegClassID],
5236    CPURARegSubClassMask,
5237    SuperRegIdxSeqs + 0,
5238    LaneBitmask(0x0000000000000001),
5239    0,
5240    false,
5241    0x00, /* TSFlags */
5242    false, /* HasDisjunctSubRegs */
5243    false, /* CoveredBySubRegs */
5244    CPURARegSuperclasses,
5245    nullptr
5246  };
5247
5248  extern const TargetRegisterClass CPUSPRegRegClass = {
5249    &MipsMCRegisterClasses[CPUSPRegRegClassID],
5250    CPUSPRegSubClassMask,
5251    SuperRegIdxSeqs + 0,
5252    LaneBitmask(0x0000000000000001),
5253    0,
5254    false,
5255    0x00, /* TSFlags */
5256    false, /* HasDisjunctSubRegs */
5257    false, /* CoveredBySubRegs */
5258    CPUSPRegSuperclasses,
5259    nullptr
5260  };
5261
5262  extern const TargetRegisterClass DSPCCRegClass = {
5263    &MipsMCRegisterClasses[DSPCCRegClassID],
5264    DSPCCSubClassMask,
5265    SuperRegIdxSeqs + 1,
5266    LaneBitmask(0x0000000000000001),
5267    0,
5268    false,
5269    0x00, /* TSFlags */
5270    false, /* HasDisjunctSubRegs */
5271    false, /* CoveredBySubRegs */
5272    NullRegClasses,
5273    nullptr
5274  };
5275
5276  extern const TargetRegisterClass GP32RegClass = {
5277    &MipsMCRegisterClasses[GP32RegClassID],
5278    GP32SubClassMask,
5279    SuperRegIdxSeqs + 0,
5280    LaneBitmask(0x0000000000000001),
5281    0,
5282    false,
5283    0x00, /* TSFlags */
5284    false, /* HasDisjunctSubRegs */
5285    false, /* CoveredBySubRegs */
5286    GP32Superclasses,
5287    nullptr
5288  };
5289
5290  extern const TargetRegisterClass GPR32ZERORegClass = {
5291    &MipsMCRegisterClasses[GPR32ZERORegClassID],
5292    GPR32ZEROSubClassMask,
5293    SuperRegIdxSeqs + 0,
5294    LaneBitmask(0x0000000000000001),
5295    0,
5296    false,
5297    0x00, /* TSFlags */
5298    false, /* HasDisjunctSubRegs */
5299    false, /* CoveredBySubRegs */
5300    GPR32ZEROSuperclasses,
5301    nullptr
5302  };
5303
5304  extern const TargetRegisterClass HI32RegClass = {
5305    &MipsMCRegisterClasses[HI32RegClassID],
5306    HI32SubClassMask,
5307    SuperRegIdxSeqs + 12,
5308    LaneBitmask(0x0000000000000001),
5309    0,
5310    false,
5311    0x00, /* TSFlags */
5312    false, /* HasDisjunctSubRegs */
5313    false, /* CoveredBySubRegs */
5314    HI32Superclasses,
5315    nullptr
5316  };
5317
5318  extern const TargetRegisterClass LO32RegClass = {
5319    &MipsMCRegisterClasses[LO32RegClassID],
5320    LO32SubClassMask,
5321    SuperRegIdxSeqs + 6,
5322    LaneBitmask(0x0000000000000001),
5323    0,
5324    false,
5325    0x00, /* TSFlags */
5326    false, /* HasDisjunctSubRegs */
5327    false, /* CoveredBySubRegs */
5328    LO32Superclasses,
5329    nullptr
5330  };
5331
5332  extern const TargetRegisterClass SP32RegClass = {
5333    &MipsMCRegisterClasses[SP32RegClassID],
5334    SP32SubClassMask,
5335    SuperRegIdxSeqs + 0,
5336    LaneBitmask(0x0000000000000001),
5337    0,
5338    false,
5339    0x00, /* TSFlags */
5340    false, /* HasDisjunctSubRegs */
5341    false, /* CoveredBySubRegs */
5342    SP32Superclasses,
5343    nullptr
5344  };
5345
5346  extern const TargetRegisterClass FGR64RegClass = {
5347    &MipsMCRegisterClasses[FGR64RegClassID],
5348    FGR64SubClassMask,
5349    SuperRegIdxSeqs + 2,
5350    LaneBitmask(0x0000000000000041),
5351    0,
5352    false,
5353    0x00, /* TSFlags */
5354    true, /* HasDisjunctSubRegs */
5355    true, /* CoveredBySubRegs */
5356    NullRegClasses,
5357    FGR64GetRawAllocationOrder
5358  };
5359
5360  extern const TargetRegisterClass GPR64RegClass = {
5361    &MipsMCRegisterClasses[GPR64RegClassID],
5362    GPR64SubClassMask,
5363    SuperRegIdxSeqs + 1,
5364    LaneBitmask(0x0000000000000001),
5365    0,
5366    false,
5367    0x00, /* TSFlags */
5368    false, /* HasDisjunctSubRegs */
5369    false, /* CoveredBySubRegs */
5370    NullRegClasses,
5371    nullptr
5372  };
5373
5374  extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERORegClass = {
5375    &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPR32NONZERORegClassID],
5376    GPR64_with_sub_32_in_GPR32NONZEROSubClassMask,
5377    SuperRegIdxSeqs + 1,
5378    LaneBitmask(0x0000000000000001),
5379    0,
5380    false,
5381    0x00, /* TSFlags */
5382    false, /* HasDisjunctSubRegs */
5383    false, /* CoveredBySubRegs */
5384    GPR64_with_sub_32_in_GPR32NONZEROSuperclasses,
5385    nullptr
5386  };
5387
5388  extern const TargetRegisterClass AFGR64RegClass = {
5389    &MipsMCRegisterClasses[AFGR64RegClassID],
5390    AFGR64SubClassMask,
5391    SuperRegIdxSeqs + 1,
5392    LaneBitmask(0x0000000000000041),
5393    0,
5394    false,
5395    0x00, /* TSFlags */
5396    true, /* HasDisjunctSubRegs */
5397    true, /* CoveredBySubRegs */
5398    NullRegClasses,
5399    nullptr
5400  };
5401
5402  extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass = {
5403    &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID],
5404    GPR64_with_sub_32_in_CPU16RegsPlusSPSubClassMask,
5405    SuperRegIdxSeqs + 1,
5406    LaneBitmask(0x0000000000000001),
5407    0,
5408    false,
5409    0x00, /* TSFlags */
5410    false, /* HasDisjunctSubRegs */
5411    false, /* CoveredBySubRegs */
5412    GPR64_with_sub_32_in_CPU16RegsPlusSPSuperclasses,
5413    nullptr
5414  };
5415
5416  extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsRegClass = {
5417    &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16RegsRegClassID],
5418    GPR64_with_sub_32_in_CPU16RegsSubClassMask,
5419    SuperRegIdxSeqs + 1,
5420    LaneBitmask(0x0000000000000001),
5421    0,
5422    false,
5423    0x00, /* TSFlags */
5424    false, /* HasDisjunctSubRegs */
5425    false, /* CoveredBySubRegs */
5426    GPR64_with_sub_32_in_CPU16RegsSuperclasses,
5427    nullptr
5428  };
5429
5430  extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePRegClass = {
5431    &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MovePRegClassID],
5432    GPR64_with_sub_32_in_GPRMM16MovePSubClassMask,
5433    SuperRegIdxSeqs + 1,
5434    LaneBitmask(0x0000000000000001),
5435    0,
5436    false,
5437    0x00, /* TSFlags */
5438    false, /* HasDisjunctSubRegs */
5439    false, /* CoveredBySubRegs */
5440    GPR64_with_sub_32_in_GPRMM16MovePSuperclasses,
5441    nullptr
5442  };
5443
5444  extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16ZeroRegClass = {
5445    &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16ZeroRegClassID],
5446    GPR64_with_sub_32_in_GPRMM16ZeroSubClassMask,
5447    SuperRegIdxSeqs + 1,
5448    LaneBitmask(0x0000000000000001),
5449    0,
5450    false,
5451    0x00, /* TSFlags */
5452    false, /* HasDisjunctSubRegs */
5453    false, /* CoveredBySubRegs */
5454    GPR64_with_sub_32_in_GPRMM16ZeroSuperclasses,
5455    nullptr
5456  };
5457
5458  extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass = {
5459    &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID],
5460    GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSubClassMask,
5461    SuperRegIdxSeqs + 1,
5462    LaneBitmask(0x0000000000000001),
5463    0,
5464    false,
5465    0x00, /* TSFlags */
5466    false, /* HasDisjunctSubRegs */
5467    false, /* CoveredBySubRegs */
5468    GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSuperclasses,
5469    nullptr
5470  };
5471
5472  extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass = {
5473    &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID],
5474    GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSubClassMask,
5475    SuperRegIdxSeqs + 1,
5476    LaneBitmask(0x0000000000000001),
5477    0,
5478    false,
5479    0x00, /* TSFlags */
5480    false, /* HasDisjunctSubRegs */
5481    false, /* CoveredBySubRegs */
5482    GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSuperclasses,
5483    nullptr
5484  };
5485
5486  extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClass = {
5487    &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClassID],
5488    GPR64_with_sub_32_in_GPRMM16MovePPairSecondSubClassMask,
5489    SuperRegIdxSeqs + 1,
5490    LaneBitmask(0x0000000000000001),
5491    0,
5492    false,
5493    0x00, /* TSFlags */
5494    false, /* HasDisjunctSubRegs */
5495    false, /* CoveredBySubRegs */
5496    GPR64_with_sub_32_in_GPRMM16MovePPairSecondSuperclasses,
5497    nullptr
5498  };
5499
5500  extern const TargetRegisterClass ACC64DSPRegClass = {
5501    &MipsMCRegisterClasses[ACC64DSPRegClassID],
5502    ACC64DSPSubClassMask,
5503    SuperRegIdxSeqs + 16,
5504    LaneBitmask(0x0000000000000041),
5505    0,
5506    false,
5507    0x00, /* TSFlags */
5508    true, /* HasDisjunctSubRegs */
5509    true, /* CoveredBySubRegs */
5510    NullRegClasses,
5511    nullptr
5512  };
5513
5514  extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClass = {
5515    &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID],
5516    GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSubClassMask,
5517    SuperRegIdxSeqs + 1,
5518    LaneBitmask(0x0000000000000001),
5519    0,
5520    false,
5521    0x00, /* TSFlags */
5522    false, /* HasDisjunctSubRegs */
5523    false, /* CoveredBySubRegs */
5524    GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSuperclasses,
5525    nullptr
5526  };
5527
5528  extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass = {
5529    &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID],
5530    GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSubClassMask,
5531    SuperRegIdxSeqs + 1,
5532    LaneBitmask(0x0000000000000001),
5533    0,
5534    false,
5535    0x00, /* TSFlags */
5536    false, /* HasDisjunctSubRegs */
5537    false, /* CoveredBySubRegs */
5538    GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSuperclasses,
5539    nullptr
5540  };
5541
5542  extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClass = {
5543    &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClassID],
5544    GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondSubClassMask,
5545    SuperRegIdxSeqs + 1,
5546    LaneBitmask(0x0000000000000001),
5547    0,
5548    false,
5549    0x00, /* TSFlags */
5550    false, /* HasDisjunctSubRegs */
5551    false, /* CoveredBySubRegs */
5552    GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondSuperclasses,
5553    nullptr
5554  };
5555
5556  extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClass = {
5557    &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClassID],
5558    GPR64_with_sub_32_in_GPRMM16MovePPairFirstSubClassMask,
5559    SuperRegIdxSeqs + 1,
5560    LaneBitmask(0x0000000000000001),
5561    0,
5562    false,
5563    0x00, /* TSFlags */
5564    false, /* HasDisjunctSubRegs */
5565    false, /* CoveredBySubRegs */
5566    GPR64_with_sub_32_in_GPRMM16MovePPairFirstSuperclasses,
5567    nullptr
5568  };
5569
5570  extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass = {
5571    &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID],
5572    GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask,
5573    SuperRegIdxSeqs + 1,
5574    LaneBitmask(0x0000000000000001),
5575    0,
5576    false,
5577    0x00, /* TSFlags */
5578    false, /* HasDisjunctSubRegs */
5579    false, /* CoveredBySubRegs */
5580    GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses,
5581    nullptr
5582  };
5583
5584  extern const TargetRegisterClass OCTEON_MPLRegClass = {
5585    &MipsMCRegisterClasses[OCTEON_MPLRegClassID],
5586    OCTEON_MPLSubClassMask,
5587    SuperRegIdxSeqs + 1,
5588    LaneBitmask(0x0000000000000001),
5589    0,
5590    false,
5591    0x00, /* TSFlags */
5592    false, /* HasDisjunctSubRegs */
5593    false, /* CoveredBySubRegs */
5594    NullRegClasses,
5595    nullptr
5596  };
5597
5598  extern const TargetRegisterClass OCTEON_PRegClass = {
5599    &MipsMCRegisterClasses[OCTEON_PRegClassID],
5600    OCTEON_PSubClassMask,
5601    SuperRegIdxSeqs + 1,
5602    LaneBitmask(0x0000000000000001),
5603    0,
5604    false,
5605    0x00, /* TSFlags */
5606    false, /* HasDisjunctSubRegs */
5607    false, /* CoveredBySubRegs */
5608    NullRegClasses,
5609    nullptr
5610  };
5611
5612  extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass = {
5613    &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID],
5614    GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSubClassMask,
5615    SuperRegIdxSeqs + 1,
5616    LaneBitmask(0x0000000000000001),
5617    0,
5618    false,
5619    0x00, /* TSFlags */
5620    false, /* HasDisjunctSubRegs */
5621    false, /* CoveredBySubRegs */
5622    GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSuperclasses,
5623    nullptr
5624  };
5625
5626  extern const TargetRegisterClass ACC64RegClass = {
5627    &MipsMCRegisterClasses[ACC64RegClassID],
5628    ACC64SubClassMask,
5629    SuperRegIdxSeqs + 16,
5630    LaneBitmask(0x0000000000000041),
5631    0,
5632    false,
5633    0x00, /* TSFlags */
5634    true, /* HasDisjunctSubRegs */
5635    true, /* CoveredBySubRegs */
5636    ACC64Superclasses,
5637    nullptr
5638  };
5639
5640  extern const TargetRegisterClass GP64RegClass = {
5641    &MipsMCRegisterClasses[GP64RegClassID],
5642    GP64SubClassMask,
5643    SuperRegIdxSeqs + 1,
5644    LaneBitmask(0x0000000000000001),
5645    0,
5646    false,
5647    0x00, /* TSFlags */
5648    false, /* HasDisjunctSubRegs */
5649    false, /* CoveredBySubRegs */
5650    GP64Superclasses,
5651    nullptr
5652  };
5653
5654  extern const TargetRegisterClass GPR64_with_sub_32_in_CPURARegRegClass = {
5655    &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPURARegRegClassID],
5656    GPR64_with_sub_32_in_CPURARegSubClassMask,
5657    SuperRegIdxSeqs + 1,
5658    LaneBitmask(0x0000000000000001),
5659    0,
5660    false,
5661    0x00, /* TSFlags */
5662    false, /* HasDisjunctSubRegs */
5663    false, /* CoveredBySubRegs */
5664    GPR64_with_sub_32_in_CPURARegSuperclasses,
5665    nullptr
5666  };
5667
5668  extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32ZERORegClass = {
5669    &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPR32ZERORegClassID],
5670    GPR64_with_sub_32_in_GPR32ZEROSubClassMask,
5671    SuperRegIdxSeqs + 1,
5672    LaneBitmask(0x0000000000000001),
5673    0,
5674    false,
5675    0x00, /* TSFlags */
5676    false, /* HasDisjunctSubRegs */
5677    false, /* CoveredBySubRegs */
5678    GPR64_with_sub_32_in_GPR32ZEROSuperclasses,
5679    nullptr
5680  };
5681
5682  extern const TargetRegisterClass HI64RegClass = {
5683    &MipsMCRegisterClasses[HI64RegClassID],
5684    HI64SubClassMask,
5685    SuperRegIdxSeqs + 4,
5686    LaneBitmask(0x0000000000000001),
5687    0,
5688    false,
5689    0x00, /* TSFlags */
5690    false, /* HasDisjunctSubRegs */
5691    false, /* CoveredBySubRegs */
5692    NullRegClasses,
5693    nullptr
5694  };
5695
5696  extern const TargetRegisterClass LO64RegClass = {
5697    &MipsMCRegisterClasses[LO64RegClassID],
5698    LO64SubClassMask,
5699    SuperRegIdxSeqs + 7,
5700    LaneBitmask(0x0000000000000001),
5701    0,
5702    false,
5703    0x00, /* TSFlags */
5704    false, /* HasDisjunctSubRegs */
5705    false, /* CoveredBySubRegs */
5706    NullRegClasses,
5707    nullptr
5708  };
5709
5710  extern const TargetRegisterClass SP64RegClass = {
5711    &MipsMCRegisterClasses[SP64RegClassID],
5712    SP64SubClassMask,
5713    SuperRegIdxSeqs + 1,
5714    LaneBitmask(0x0000000000000001),
5715    0,
5716    false,
5717    0x00, /* TSFlags */
5718    false, /* HasDisjunctSubRegs */
5719    false, /* CoveredBySubRegs */
5720    SP64Superclasses,
5721    nullptr
5722  };
5723
5724  extern const TargetRegisterClass MSA128BRegClass = {
5725    &MipsMCRegisterClasses[MSA128BRegClassID],
5726    MSA128BSubClassMask,
5727    SuperRegIdxSeqs + 1,
5728    LaneBitmask(0x0000000000000041),
5729    0,
5730    false,
5731    0x00, /* TSFlags */
5732    true, /* HasDisjunctSubRegs */
5733    false, /* CoveredBySubRegs */
5734    MSA128BSuperclasses,
5735    nullptr
5736  };
5737
5738  extern const TargetRegisterClass MSA128DRegClass = {
5739    &MipsMCRegisterClasses[MSA128DRegClassID],
5740    MSA128DSubClassMask,
5741    SuperRegIdxSeqs + 1,
5742    LaneBitmask(0x0000000000000041),
5743    0,
5744    false,
5745    0x00, /* TSFlags */
5746    true, /* HasDisjunctSubRegs */
5747    false, /* CoveredBySubRegs */
5748    MSA128DSuperclasses,
5749    nullptr
5750  };
5751
5752  extern const TargetRegisterClass MSA128HRegClass = {
5753    &MipsMCRegisterClasses[MSA128HRegClassID],
5754    MSA128HSubClassMask,
5755    SuperRegIdxSeqs + 1,
5756    LaneBitmask(0x0000000000000041),
5757    0,
5758    false,
5759    0x00, /* TSFlags */
5760    true, /* HasDisjunctSubRegs */
5761    false, /* CoveredBySubRegs */
5762    MSA128HSuperclasses,
5763    nullptr
5764  };
5765
5766  extern const TargetRegisterClass MSA128WRegClass = {
5767    &MipsMCRegisterClasses[MSA128WRegClassID],
5768    MSA128WSubClassMask,
5769    SuperRegIdxSeqs + 1,
5770    LaneBitmask(0x0000000000000041),
5771    0,
5772    false,
5773    0x00, /* TSFlags */
5774    true, /* HasDisjunctSubRegs */
5775    false, /* CoveredBySubRegs */
5776    MSA128WSuperclasses,
5777    nullptr
5778  };
5779
5780  extern const TargetRegisterClass MSA128WEvensRegClass = {
5781    &MipsMCRegisterClasses[MSA128WEvensRegClassID],
5782    MSA128WEvensSubClassMask,
5783    SuperRegIdxSeqs + 1,
5784    LaneBitmask(0x0000000000000041),
5785    0,
5786    false,
5787    0x00, /* TSFlags */
5788    true, /* HasDisjunctSubRegs */
5789    false, /* CoveredBySubRegs */
5790    MSA128WEvensSuperclasses,
5791    nullptr
5792  };
5793
5794  extern const TargetRegisterClass ACC128RegClass = {
5795    &MipsMCRegisterClasses[ACC128RegClassID],
5796    ACC128SubClassMask,
5797    SuperRegIdxSeqs + 1,
5798    LaneBitmask(0x0000000000000041),
5799    0,
5800    false,
5801    0x00, /* TSFlags */
5802    true, /* HasDisjunctSubRegs */
5803    true, /* CoveredBySubRegs */
5804    NullRegClasses,
5805    nullptr
5806  };
5807
5808} // end namespace Mips
5809
5810namespace {
5811  const TargetRegisterClass *const RegisterClasses[] = {
5812    &Mips::MSA128F16RegClass,
5813    &Mips::CCRRegClass,
5814    &Mips::COP0RegClass,
5815    &Mips::COP2RegClass,
5816    &Mips::COP3RegClass,
5817    &Mips::DSPRRegClass,
5818    &Mips::FGR32RegClass,
5819    &Mips::FGRCCRegClass,
5820    &Mips::GPR32RegClass,
5821    &Mips::HWRegsRegClass,
5822    &Mips::MSACtrlRegClass,
5823    &Mips::GPR32NONZERORegClass,
5824    &Mips::CPU16RegsPlusSPRegClass,
5825    &Mips::CPU16RegsRegClass,
5826    &Mips::FCCRegClass,
5827    &Mips::GPRMM16RegClass,
5828    &Mips::GPRMM16MovePRegClass,
5829    &Mips::GPRMM16ZeroRegClass,
5830    &Mips::CPU16Regs_and_GPRMM16ZeroRegClass,
5831    &Mips::GPR32NONZERO_and_GPRMM16MovePRegClass,
5832    &Mips::GPRMM16MovePPairSecondRegClass,
5833    &Mips::CPU16Regs_and_GPRMM16MovePRegClass,
5834    &Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClass,
5835    &Mips::HI32DSPRegClass,
5836    &Mips::LO32DSPRegClass,
5837    &Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClass,
5838    &Mips::GPRMM16MovePPairFirstRegClass,
5839    &Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass,
5840    &Mips::GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass,
5841    &Mips::CPURARegRegClass,
5842    &Mips::CPUSPRegRegClass,
5843    &Mips::DSPCCRegClass,
5844    &Mips::GP32RegClass,
5845    &Mips::GPR32ZERORegClass,
5846    &Mips::HI32RegClass,
5847    &Mips::LO32RegClass,
5848    &Mips::SP32RegClass,
5849    &Mips::FGR64RegClass,
5850    &Mips::GPR64RegClass,
5851    &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
5852    &Mips::AFGR64RegClass,
5853    &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
5854    &Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,
5855    &Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,
5856    &Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,
5857    &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass,
5858    &Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass,
5859    &Mips::GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClass,
5860    &Mips::ACC64DSPRegClass,
5861    &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClass,
5862    &Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass,
5863    &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClass,
5864    &Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClass,
5865    &Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass,
5866    &Mips::OCTEON_MPLRegClass,
5867    &Mips::OCTEON_PRegClass,
5868    &Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass,
5869    &Mips::ACC64RegClass,
5870    &Mips::GP64RegClass,
5871    &Mips::GPR64_with_sub_32_in_CPURARegRegClass,
5872    &Mips::GPR64_with_sub_32_in_GPR32ZERORegClass,
5873    &Mips::HI64RegClass,
5874    &Mips::LO64RegClass,
5875    &Mips::SP64RegClass,
5876    &Mips::MSA128BRegClass,
5877    &Mips::MSA128DRegClass,
5878    &Mips::MSA128HRegClass,
5879    &Mips::MSA128WRegClass,
5880    &Mips::MSA128WEvensRegClass,
5881    &Mips::ACC128RegClass,
5882  };
5883} // end anonymous namespace
5884
5885static const uint8_t CostPerUseTable[] = {
58860, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
5887
5888
5889static const bool InAllocatableClassTable[] = {
5890false, true, true, false, false, false, false, false, true, true, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
5891
5892
5893static const TargetRegisterInfoDesc MipsRegInfoDesc = { // Extra Descriptors
5894CostPerUseTable, 1, InAllocatableClassTable};
5895
5896unsigned MipsGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
5897  static const uint8_t RowMap[11] = {
5898    0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1,
5899  };
5900  static const uint8_t Rows[2][11] = {
5901    { Mips::sub_hi_then_sub_32, 0, 0, 0, 0, 0, 0, Mips::sub_hi, Mips::sub_lo, 0, 0, },
5902    { Mips::sub_32, 0, 0, 0, 0, 0, 0, Mips::sub_hi_then_sub_32, Mips::sub_32, 0, 0, },
5903  };
5904
5905  --IdxA; assert(IdxA < 11); (void) IdxA;
5906  --IdxB; assert(IdxB < 11);
5907  return Rows[RowMap[IdxA]][IdxB];
5908}
5909
5910  struct MaskRolOp {
5911    LaneBitmask Mask;
5912    uint8_t  RotateLeft;
5913  };
5914  static const MaskRolOp LaneMaskComposeSequences[] = {
5915    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  0 }, { LaneBitmask::getNone(), 0 },   // Sequence 0
5916    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  1 }, { LaneBitmask::getNone(), 0 },   // Sequence 2
5917    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  2 }, { LaneBitmask::getNone(), 0 },   // Sequence 4
5918    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  3 }, { LaneBitmask::getNone(), 0 },   // Sequence 6
5919    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  4 }, { LaneBitmask::getNone(), 0 },   // Sequence 8
5920    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  5 }, { LaneBitmask::getNone(), 0 },   // Sequence 10
5921    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  6 }, { LaneBitmask::getNone(), 0 }  // Sequence 12
5922  };
5923  static const uint8_t CompositeSequences[] = {
5924    0, // to sub_32
5925    0, // to sub_64
5926    2, // to sub_dsp16_19
5927    4, // to sub_dsp20
5928    6, // to sub_dsp21
5929    8, // to sub_dsp22
5930    10, // to sub_dsp23
5931    12, // to sub_hi
5932    0, // to sub_lo
5933    12, // to sub_hi_then_sub_32
5934    0 // to sub_32_sub_hi_then_sub_32
5935  };
5936
5937LaneBitmask MipsGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
5938  --IdxA; assert(IdxA < 11 && "Subregister index out of bounds");
5939  LaneBitmask Result;
5940  for (const MaskRolOp *Ops =
5941       &LaneMaskComposeSequences[CompositeSequences[IdxA]];
5942       Ops->Mask.any(); ++Ops) {
5943    LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
5944    if (unsigned S = Ops->RotateLeft)
5945      Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
5946    else
5947      Result |= LaneBitmask(M);
5948  }
5949  return Result;
5950}
5951
5952LaneBitmask MipsGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA,  LaneBitmask LaneMask) const {
5953  LaneMask &= getSubRegIndexLaneMask(IdxA);
5954  --IdxA; assert(IdxA < 11 && "Subregister index out of bounds");
5955  LaneBitmask Result;
5956  for (const MaskRolOp *Ops =
5957       &LaneMaskComposeSequences[CompositeSequences[IdxA]];
5958       Ops->Mask.any(); ++Ops) {
5959    LaneBitmask::Type M = LaneMask.getAsInteger();
5960    if (unsigned S = Ops->RotateLeft)
5961      Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
5962    else
5963      Result |= LaneBitmask(M);
5964  }
5965  return Result;
5966}
5967
5968const TargetRegisterClass *MipsGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
5969  static const uint8_t Table[70][11] = {
5970    {	// MSA128F16
5971      0,	// sub_32
5972      1,	// sub_64 -> MSA128F16
5973      0,	// sub_dsp16_19
5974      0,	// sub_dsp20
5975      0,	// sub_dsp21
5976      0,	// sub_dsp22
5977      0,	// sub_dsp23
5978      1,	// sub_hi -> MSA128F16
5979      1,	// sub_lo -> MSA128F16
5980      0,	// sub_hi_then_sub_32
5981      0,	// sub_32_sub_hi_then_sub_32
5982    },
5983    {	// CCR
5984      0,	// sub_32
5985      0,	// sub_64
5986      0,	// sub_dsp16_19
5987      0,	// sub_dsp20
5988      0,	// sub_dsp21
5989      0,	// sub_dsp22
5990      0,	// sub_dsp23
5991      0,	// sub_hi
5992      0,	// sub_lo
5993      0,	// sub_hi_then_sub_32
5994      0,	// sub_32_sub_hi_then_sub_32
5995    },
5996    {	// COP0
5997      0,	// sub_32
5998      0,	// sub_64
5999      0,	// sub_dsp16_19
6000      0,	// sub_dsp20
6001      0,	// sub_dsp21
6002      0,	// sub_dsp22
6003      0,	// sub_dsp23
6004      0,	// sub_hi
6005      0,	// sub_lo
6006      0,	// sub_hi_then_sub_32
6007      0,	// sub_32_sub_hi_then_sub_32
6008    },
6009    {	// COP2
6010      0,	// sub_32
6011      0,	// sub_64
6012      0,	// sub_dsp16_19
6013      0,	// sub_dsp20
6014      0,	// sub_dsp21
6015      0,	// sub_dsp22
6016      0,	// sub_dsp23
6017      0,	// sub_hi
6018      0,	// sub_lo
6019      0,	// sub_hi_then_sub_32
6020      0,	// sub_32_sub_hi_then_sub_32
6021    },
6022    {	// COP3
6023      0,	// sub_32
6024      0,	// sub_64
6025      0,	// sub_dsp16_19
6026      0,	// sub_dsp20
6027      0,	// sub_dsp21
6028      0,	// sub_dsp22
6029      0,	// sub_dsp23
6030      0,	// sub_hi
6031      0,	// sub_lo
6032      0,	// sub_hi_then_sub_32
6033      0,	// sub_32_sub_hi_then_sub_32
6034    },
6035    {	// DSPR
6036      0,	// sub_32
6037      0,	// sub_64
6038      0,	// sub_dsp16_19
6039      0,	// sub_dsp20
6040      0,	// sub_dsp21
6041      0,	// sub_dsp22
6042      0,	// sub_dsp23
6043      0,	// sub_hi
6044      0,	// sub_lo
6045      0,	// sub_hi_then_sub_32
6046      0,	// sub_32_sub_hi_then_sub_32
6047    },
6048    {	// FGR32
6049      0,	// sub_32
6050      0,	// sub_64
6051      0,	// sub_dsp16_19
6052      0,	// sub_dsp20
6053      0,	// sub_dsp21
6054      0,	// sub_dsp22
6055      0,	// sub_dsp23
6056      0,	// sub_hi
6057      0,	// sub_lo
6058      0,	// sub_hi_then_sub_32
6059      0,	// sub_32_sub_hi_then_sub_32
6060    },
6061    {	// FGRCC
6062      0,	// sub_32
6063      0,	// sub_64
6064      0,	// sub_dsp16_19
6065      0,	// sub_dsp20
6066      0,	// sub_dsp21
6067      0,	// sub_dsp22
6068      0,	// sub_dsp23
6069      0,	// sub_hi
6070      0,	// sub_lo
6071      0,	// sub_hi_then_sub_32
6072      0,	// sub_32_sub_hi_then_sub_32
6073    },
6074    {	// GPR32
6075      0,	// sub_32
6076      0,	// sub_64
6077      0,	// sub_dsp16_19
6078      0,	// sub_dsp20
6079      0,	// sub_dsp21
6080      0,	// sub_dsp22
6081      0,	// sub_dsp23
6082      0,	// sub_hi
6083      0,	// sub_lo
6084      0,	// sub_hi_then_sub_32
6085      0,	// sub_32_sub_hi_then_sub_32
6086    },
6087    {	// HWRegs
6088      0,	// sub_32
6089      0,	// sub_64
6090      0,	// sub_dsp16_19
6091      0,	// sub_dsp20
6092      0,	// sub_dsp21
6093      0,	// sub_dsp22
6094      0,	// sub_dsp23
6095      0,	// sub_hi
6096      0,	// sub_lo
6097      0,	// sub_hi_then_sub_32
6098      0,	// sub_32_sub_hi_then_sub_32
6099    },
6100    {	// MSACtrl
6101      0,	// sub_32
6102      0,	// sub_64
6103      0,	// sub_dsp16_19
6104      0,	// sub_dsp20
6105      0,	// sub_dsp21
6106      0,	// sub_dsp22
6107      0,	// sub_dsp23
6108      0,	// sub_hi
6109      0,	// sub_lo
6110      0,	// sub_hi_then_sub_32
6111      0,	// sub_32_sub_hi_then_sub_32
6112    },
6113    {	// GPR32NONZERO
6114      0,	// sub_32
6115      0,	// sub_64
6116      0,	// sub_dsp16_19
6117      0,	// sub_dsp20
6118      0,	// sub_dsp21
6119      0,	// sub_dsp22
6120      0,	// sub_dsp23
6121      0,	// sub_hi
6122      0,	// sub_lo
6123      0,	// sub_hi_then_sub_32
6124      0,	// sub_32_sub_hi_then_sub_32
6125    },
6126    {	// CPU16RegsPlusSP
6127      0,	// sub_32
6128      0,	// sub_64
6129      0,	// sub_dsp16_19
6130      0,	// sub_dsp20
6131      0,	// sub_dsp21
6132      0,	// sub_dsp22
6133      0,	// sub_dsp23
6134      0,	// sub_hi
6135      0,	// sub_lo
6136      0,	// sub_hi_then_sub_32
6137      0,	// sub_32_sub_hi_then_sub_32
6138    },
6139    {	// CPU16Regs
6140      0,	// sub_32
6141      0,	// sub_64
6142      0,	// sub_dsp16_19
6143      0,	// sub_dsp20
6144      0,	// sub_dsp21
6145      0,	// sub_dsp22
6146      0,	// sub_dsp23
6147      0,	// sub_hi
6148      0,	// sub_lo
6149      0,	// sub_hi_then_sub_32
6150      0,	// sub_32_sub_hi_then_sub_32
6151    },
6152    {	// FCC
6153      0,	// sub_32
6154      0,	// sub_64
6155      0,	// sub_dsp16_19
6156      0,	// sub_dsp20
6157      0,	// sub_dsp21
6158      0,	// sub_dsp22
6159      0,	// sub_dsp23
6160      0,	// sub_hi
6161      0,	// sub_lo
6162      0,	// sub_hi_then_sub_32
6163      0,	// sub_32_sub_hi_then_sub_32
6164    },
6165    {	// GPRMM16
6166      0,	// sub_32
6167      0,	// sub_64
6168      0,	// sub_dsp16_19
6169      0,	// sub_dsp20
6170      0,	// sub_dsp21
6171      0,	// sub_dsp22
6172      0,	// sub_dsp23
6173      0,	// sub_hi
6174      0,	// sub_lo
6175      0,	// sub_hi_then_sub_32
6176      0,	// sub_32_sub_hi_then_sub_32
6177    },
6178    {	// GPRMM16MoveP
6179      0,	// sub_32
6180      0,	// sub_64
6181      0,	// sub_dsp16_19
6182      0,	// sub_dsp20
6183      0,	// sub_dsp21
6184      0,	// sub_dsp22
6185      0,	// sub_dsp23
6186      0,	// sub_hi
6187      0,	// sub_lo
6188      0,	// sub_hi_then_sub_32
6189      0,	// sub_32_sub_hi_then_sub_32
6190    },
6191    {	// GPRMM16Zero
6192      0,	// sub_32
6193      0,	// sub_64
6194      0,	// sub_dsp16_19
6195      0,	// sub_dsp20
6196      0,	// sub_dsp21
6197      0,	// sub_dsp22
6198      0,	// sub_dsp23
6199      0,	// sub_hi
6200      0,	// sub_lo
6201      0,	// sub_hi_then_sub_32
6202      0,	// sub_32_sub_hi_then_sub_32
6203    },
6204    {	// CPU16Regs_and_GPRMM16Zero
6205      0,	// sub_32
6206      0,	// sub_64
6207      0,	// sub_dsp16_19
6208      0,	// sub_dsp20
6209      0,	// sub_dsp21
6210      0,	// sub_dsp22
6211      0,	// sub_dsp23
6212      0,	// sub_hi
6213      0,	// sub_lo
6214      0,	// sub_hi_then_sub_32
6215      0,	// sub_32_sub_hi_then_sub_32
6216    },
6217    {	// GPR32NONZERO_and_GPRMM16MoveP
6218      0,	// sub_32
6219      0,	// sub_64
6220      0,	// sub_dsp16_19
6221      0,	// sub_dsp20
6222      0,	// sub_dsp21
6223      0,	// sub_dsp22
6224      0,	// sub_dsp23
6225      0,	// sub_hi
6226      0,	// sub_lo
6227      0,	// sub_hi_then_sub_32
6228      0,	// sub_32_sub_hi_then_sub_32
6229    },
6230    {	// GPRMM16MovePPairSecond
6231      0,	// sub_32
6232      0,	// sub_64
6233      0,	// sub_dsp16_19
6234      0,	// sub_dsp20
6235      0,	// sub_dsp21
6236      0,	// sub_dsp22
6237      0,	// sub_dsp23
6238      0,	// sub_hi
6239      0,	// sub_lo
6240      0,	// sub_hi_then_sub_32
6241      0,	// sub_32_sub_hi_then_sub_32
6242    },
6243    {	// CPU16Regs_and_GPRMM16MoveP
6244      0,	// sub_32
6245      0,	// sub_64
6246      0,	// sub_dsp16_19
6247      0,	// sub_dsp20
6248      0,	// sub_dsp21
6249      0,	// sub_dsp22
6250      0,	// sub_dsp23
6251      0,	// sub_hi
6252      0,	// sub_lo
6253      0,	// sub_hi_then_sub_32
6254      0,	// sub_32_sub_hi_then_sub_32
6255    },
6256    {	// GPRMM16MoveP_and_GPRMM16Zero
6257      0,	// sub_32
6258      0,	// sub_64
6259      0,	// sub_dsp16_19
6260      0,	// sub_dsp20
6261      0,	// sub_dsp21
6262      0,	// sub_dsp22
6263      0,	// sub_dsp23
6264      0,	// sub_hi
6265      0,	// sub_lo
6266      0,	// sub_hi_then_sub_32
6267      0,	// sub_32_sub_hi_then_sub_32
6268    },
6269    {	// HI32DSP
6270      0,	// sub_32
6271      0,	// sub_64
6272      0,	// sub_dsp16_19
6273      0,	// sub_dsp20
6274      0,	// sub_dsp21
6275      0,	// sub_dsp22
6276      0,	// sub_dsp23
6277      0,	// sub_hi
6278      0,	// sub_lo
6279      0,	// sub_hi_then_sub_32
6280      0,	// sub_32_sub_hi_then_sub_32
6281    },
6282    {	// LO32DSP
6283      0,	// sub_32
6284      0,	// sub_64
6285      0,	// sub_dsp16_19
6286      0,	// sub_dsp20
6287      0,	// sub_dsp21
6288      0,	// sub_dsp22
6289      0,	// sub_dsp23
6290      0,	// sub_hi
6291      0,	// sub_lo
6292      0,	// sub_hi_then_sub_32
6293      0,	// sub_32_sub_hi_then_sub_32
6294    },
6295    {	// CPU16Regs_and_GPRMM16MovePPairSecond
6296      0,	// sub_32
6297      0,	// sub_64
6298      0,	// sub_dsp16_19
6299      0,	// sub_dsp20
6300      0,	// sub_dsp21
6301      0,	// sub_dsp22
6302      0,	// sub_dsp23
6303      0,	// sub_hi
6304      0,	// sub_lo
6305      0,	// sub_hi_then_sub_32
6306      0,	// sub_32_sub_hi_then_sub_32
6307    },
6308    {	// GPRMM16MovePPairFirst
6309      0,	// sub_32
6310      0,	// sub_64
6311      0,	// sub_dsp16_19
6312      0,	// sub_dsp20
6313      0,	// sub_dsp21
6314      0,	// sub_dsp22
6315      0,	// sub_dsp23
6316      0,	// sub_hi
6317      0,	// sub_lo
6318      0,	// sub_hi_then_sub_32
6319      0,	// sub_32_sub_hi_then_sub_32
6320    },
6321    {	// GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
6322      0,	// sub_32
6323      0,	// sub_64
6324      0,	// sub_dsp16_19
6325      0,	// sub_dsp20
6326      0,	// sub_dsp21
6327      0,	// sub_dsp22
6328      0,	// sub_dsp23
6329      0,	// sub_hi
6330      0,	// sub_lo
6331      0,	// sub_hi_then_sub_32
6332      0,	// sub_32_sub_hi_then_sub_32
6333    },
6334    {	// GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
6335      0,	// sub_32
6336      0,	// sub_64
6337      0,	// sub_dsp16_19
6338      0,	// sub_dsp20
6339      0,	// sub_dsp21
6340      0,	// sub_dsp22
6341      0,	// sub_dsp23
6342      0,	// sub_hi
6343      0,	// sub_lo
6344      0,	// sub_hi_then_sub_32
6345      0,	// sub_32_sub_hi_then_sub_32
6346    },
6347    {	// CPURAReg
6348      0,	// sub_32
6349      0,	// sub_64
6350      0,	// sub_dsp16_19
6351      0,	// sub_dsp20
6352      0,	// sub_dsp21
6353      0,	// sub_dsp22
6354      0,	// sub_dsp23
6355      0,	// sub_hi
6356      0,	// sub_lo
6357      0,	// sub_hi_then_sub_32
6358      0,	// sub_32_sub_hi_then_sub_32
6359    },
6360    {	// CPUSPReg
6361      0,	// sub_32
6362      0,	// sub_64
6363      0,	// sub_dsp16_19
6364      0,	// sub_dsp20
6365      0,	// sub_dsp21
6366      0,	// sub_dsp22
6367      0,	// sub_dsp23
6368      0,	// sub_hi
6369      0,	// sub_lo
6370      0,	// sub_hi_then_sub_32
6371      0,	// sub_32_sub_hi_then_sub_32
6372    },
6373    {	// DSPCC
6374      0,	// sub_32
6375      0,	// sub_64
6376      0,	// sub_dsp16_19
6377      0,	// sub_dsp20
6378      0,	// sub_dsp21
6379      0,	// sub_dsp22
6380      0,	// sub_dsp23
6381      0,	// sub_hi
6382      0,	// sub_lo
6383      0,	// sub_hi_then_sub_32
6384      0,	// sub_32_sub_hi_then_sub_32
6385    },
6386    {	// GP32
6387      0,	// sub_32
6388      0,	// sub_64
6389      0,	// sub_dsp16_19
6390      0,	// sub_dsp20
6391      0,	// sub_dsp21
6392      0,	// sub_dsp22
6393      0,	// sub_dsp23
6394      0,	// sub_hi
6395      0,	// sub_lo
6396      0,	// sub_hi_then_sub_32
6397      0,	// sub_32_sub_hi_then_sub_32
6398    },
6399    {	// GPR32ZERO
6400      0,	// sub_32
6401      0,	// sub_64
6402      0,	// sub_dsp16_19
6403      0,	// sub_dsp20
6404      0,	// sub_dsp21
6405      0,	// sub_dsp22
6406      0,	// sub_dsp23
6407      0,	// sub_hi
6408      0,	// sub_lo
6409      0,	// sub_hi_then_sub_32
6410      0,	// sub_32_sub_hi_then_sub_32
6411    },
6412    {	// HI32
6413      0,	// sub_32
6414      0,	// sub_64
6415      0,	// sub_dsp16_19
6416      0,	// sub_dsp20
6417      0,	// sub_dsp21
6418      0,	// sub_dsp22
6419      0,	// sub_dsp23
6420      0,	// sub_hi
6421      0,	// sub_lo
6422      0,	// sub_hi_then_sub_32
6423      0,	// sub_32_sub_hi_then_sub_32
6424    },
6425    {	// LO32
6426      0,	// sub_32
6427      0,	// sub_64
6428      0,	// sub_dsp16_19
6429      0,	// sub_dsp20
6430      0,	// sub_dsp21
6431      0,	// sub_dsp22
6432      0,	// sub_dsp23
6433      0,	// sub_hi
6434      0,	// sub_lo
6435      0,	// sub_hi_then_sub_32
6436      0,	// sub_32_sub_hi_then_sub_32
6437    },
6438    {	// SP32
6439      0,	// sub_32
6440      0,	// sub_64
6441      0,	// sub_dsp16_19
6442      0,	// sub_dsp20
6443      0,	// sub_dsp21
6444      0,	// sub_dsp22
6445      0,	// sub_dsp23
6446      0,	// sub_hi
6447      0,	// sub_lo
6448      0,	// sub_hi_then_sub_32
6449      0,	// sub_32_sub_hi_then_sub_32
6450    },
6451    {	// FGR64
6452      0,	// sub_32
6453      0,	// sub_64
6454      0,	// sub_dsp16_19
6455      0,	// sub_dsp20
6456      0,	// sub_dsp21
6457      0,	// sub_dsp22
6458      0,	// sub_dsp23
6459      38,	// sub_hi -> FGR64
6460      38,	// sub_lo -> FGR64
6461      0,	// sub_hi_then_sub_32
6462      0,	// sub_32_sub_hi_then_sub_32
6463    },
6464    {	// GPR64
6465      39,	// sub_32 -> GPR64
6466      0,	// sub_64
6467      0,	// sub_dsp16_19
6468      0,	// sub_dsp20
6469      0,	// sub_dsp21
6470      0,	// sub_dsp22
6471      0,	// sub_dsp23
6472      0,	// sub_hi
6473      0,	// sub_lo
6474      0,	// sub_hi_then_sub_32
6475      0,	// sub_32_sub_hi_then_sub_32
6476    },
6477    {	// GPR64_with_sub_32_in_GPR32NONZERO
6478      40,	// sub_32 -> GPR64_with_sub_32_in_GPR32NONZERO
6479      0,	// sub_64
6480      0,	// sub_dsp16_19
6481      0,	// sub_dsp20
6482      0,	// sub_dsp21
6483      0,	// sub_dsp22
6484      0,	// sub_dsp23
6485      0,	// sub_hi
6486      0,	// sub_lo
6487      0,	// sub_hi_then_sub_32
6488      0,	// sub_32_sub_hi_then_sub_32
6489    },
6490    {	// AFGR64
6491      0,	// sub_32
6492      0,	// sub_64
6493      0,	// sub_dsp16_19
6494      0,	// sub_dsp20
6495      0,	// sub_dsp21
6496      0,	// sub_dsp22
6497      0,	// sub_dsp23
6498      41,	// sub_hi -> AFGR64
6499      41,	// sub_lo -> AFGR64
6500      0,	// sub_hi_then_sub_32
6501      0,	// sub_32_sub_hi_then_sub_32
6502    },
6503    {	// GPR64_with_sub_32_in_CPU16RegsPlusSP
6504      42,	// sub_32 -> GPR64_with_sub_32_in_CPU16RegsPlusSP
6505      0,	// sub_64
6506      0,	// sub_dsp16_19
6507      0,	// sub_dsp20
6508      0,	// sub_dsp21
6509      0,	// sub_dsp22
6510      0,	// sub_dsp23
6511      0,	// sub_hi
6512      0,	// sub_lo
6513      0,	// sub_hi_then_sub_32
6514      0,	// sub_32_sub_hi_then_sub_32
6515    },
6516    {	// GPR64_with_sub_32_in_CPU16Regs
6517      43,	// sub_32 -> GPR64_with_sub_32_in_CPU16Regs
6518      0,	// sub_64
6519      0,	// sub_dsp16_19
6520      0,	// sub_dsp20
6521      0,	// sub_dsp21
6522      0,	// sub_dsp22
6523      0,	// sub_dsp23
6524      0,	// sub_hi
6525      0,	// sub_lo
6526      0,	// sub_hi_then_sub_32
6527      0,	// sub_32_sub_hi_then_sub_32
6528    },
6529    {	// GPR64_with_sub_32_in_GPRMM16MoveP
6530      44,	// sub_32 -> GPR64_with_sub_32_in_GPRMM16MoveP
6531      0,	// sub_64
6532      0,	// sub_dsp16_19
6533      0,	// sub_dsp20
6534      0,	// sub_dsp21
6535      0,	// sub_dsp22
6536      0,	// sub_dsp23
6537      0,	// sub_hi
6538      0,	// sub_lo
6539      0,	// sub_hi_then_sub_32
6540      0,	// sub_32_sub_hi_then_sub_32
6541    },
6542    {	// GPR64_with_sub_32_in_GPRMM16Zero
6543      45,	// sub_32 -> GPR64_with_sub_32_in_GPRMM16Zero
6544      0,	// sub_64
6545      0,	// sub_dsp16_19
6546      0,	// sub_dsp20
6547      0,	// sub_dsp21
6548      0,	// sub_dsp22
6549      0,	// sub_dsp23
6550      0,	// sub_hi
6551      0,	// sub_lo
6552      0,	// sub_hi_then_sub_32
6553      0,	// sub_32_sub_hi_then_sub_32
6554    },
6555    {	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
6556      46,	// sub_32 -> GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
6557      0,	// sub_64
6558      0,	// sub_dsp16_19
6559      0,	// sub_dsp20
6560      0,	// sub_dsp21
6561      0,	// sub_dsp22
6562      0,	// sub_dsp23
6563      0,	// sub_hi
6564      0,	// sub_lo
6565      0,	// sub_hi_then_sub_32
6566      0,	// sub_32_sub_hi_then_sub_32
6567    },
6568    {	// GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
6569      47,	// sub_32 -> GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
6570      0,	// sub_64
6571      0,	// sub_dsp16_19
6572      0,	// sub_dsp20
6573      0,	// sub_dsp21
6574      0,	// sub_dsp22
6575      0,	// sub_dsp23
6576      0,	// sub_hi
6577      0,	// sub_lo
6578      0,	// sub_hi_then_sub_32
6579      0,	// sub_32_sub_hi_then_sub_32
6580    },
6581    {	// GPR64_with_sub_32_in_GPRMM16MovePPairSecond
6582      48,	// sub_32 -> GPR64_with_sub_32_in_GPRMM16MovePPairSecond
6583      0,	// sub_64
6584      0,	// sub_dsp16_19
6585      0,	// sub_dsp20
6586      0,	// sub_dsp21
6587      0,	// sub_dsp22
6588      0,	// sub_dsp23
6589      0,	// sub_hi
6590      0,	// sub_lo
6591      0,	// sub_hi_then_sub_32
6592      0,	// sub_32_sub_hi_then_sub_32
6593    },
6594    {	// ACC64DSP
6595      0,	// sub_32
6596      0,	// sub_64
6597      0,	// sub_dsp16_19
6598      0,	// sub_dsp20
6599      0,	// sub_dsp21
6600      0,	// sub_dsp22
6601      0,	// sub_dsp23
6602      49,	// sub_hi -> ACC64DSP
6603      49,	// sub_lo -> ACC64DSP
6604      0,	// sub_hi_then_sub_32
6605      0,	// sub_32_sub_hi_then_sub_32
6606    },
6607    {	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
6608      50,	// sub_32 -> GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
6609      0,	// sub_64
6610      0,	// sub_dsp16_19
6611      0,	// sub_dsp20
6612      0,	// sub_dsp21
6613      0,	// sub_dsp22
6614      0,	// sub_dsp23
6615      0,	// sub_hi
6616      0,	// sub_lo
6617      0,	// sub_hi_then_sub_32
6618      0,	// sub_32_sub_hi_then_sub_32
6619    },
6620    {	// GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
6621      51,	// sub_32 -> GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
6622      0,	// sub_64
6623      0,	// sub_dsp16_19
6624      0,	// sub_dsp20
6625      0,	// sub_dsp21
6626      0,	// sub_dsp22
6627      0,	// sub_dsp23
6628      0,	// sub_hi
6629      0,	// sub_lo
6630      0,	// sub_hi_then_sub_32
6631      0,	// sub_32_sub_hi_then_sub_32
6632    },
6633    {	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond
6634      52,	// sub_32 -> GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond
6635      0,	// sub_64
6636      0,	// sub_dsp16_19
6637      0,	// sub_dsp20
6638      0,	// sub_dsp21
6639      0,	// sub_dsp22
6640      0,	// sub_dsp23
6641      0,	// sub_hi
6642      0,	// sub_lo
6643      0,	// sub_hi_then_sub_32
6644      0,	// sub_32_sub_hi_then_sub_32
6645    },
6646    {	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst
6647      53,	// sub_32 -> GPR64_with_sub_32_in_GPRMM16MovePPairFirst
6648      0,	// sub_64
6649      0,	// sub_dsp16_19
6650      0,	// sub_dsp20
6651      0,	// sub_dsp21
6652      0,	// sub_dsp22
6653      0,	// sub_dsp23
6654      0,	// sub_hi
6655      0,	// sub_lo
6656      0,	// sub_hi_then_sub_32
6657      0,	// sub_32_sub_hi_then_sub_32
6658    },
6659    {	// GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
6660      54,	// sub_32 -> GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
6661      0,	// sub_64
6662      0,	// sub_dsp16_19
6663      0,	// sub_dsp20
6664      0,	// sub_dsp21
6665      0,	// sub_dsp22
6666      0,	// sub_dsp23
6667      0,	// sub_hi
6668      0,	// sub_lo
6669      0,	// sub_hi_then_sub_32
6670      0,	// sub_32_sub_hi_then_sub_32
6671    },
6672    {	// OCTEON_MPL
6673      0,	// sub_32
6674      0,	// sub_64
6675      0,	// sub_dsp16_19
6676      0,	// sub_dsp20
6677      0,	// sub_dsp21
6678      0,	// sub_dsp22
6679      0,	// sub_dsp23
6680      0,	// sub_hi
6681      0,	// sub_lo
6682      0,	// sub_hi_then_sub_32
6683      0,	// sub_32_sub_hi_then_sub_32
6684    },
6685    {	// OCTEON_P
6686      0,	// sub_32
6687      0,	// sub_64
6688      0,	// sub_dsp16_19
6689      0,	// sub_dsp20
6690      0,	// sub_dsp21
6691      0,	// sub_dsp22
6692      0,	// sub_dsp23
6693      0,	// sub_hi
6694      0,	// sub_lo
6695      0,	// sub_hi_then_sub_32
6696      0,	// sub_32_sub_hi_then_sub_32
6697    },
6698    {	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
6699      57,	// sub_32 -> GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
6700      0,	// sub_64
6701      0,	// sub_dsp16_19
6702      0,	// sub_dsp20
6703      0,	// sub_dsp21
6704      0,	// sub_dsp22
6705      0,	// sub_dsp23
6706      0,	// sub_hi
6707      0,	// sub_lo
6708      0,	// sub_hi_then_sub_32
6709      0,	// sub_32_sub_hi_then_sub_32
6710    },
6711    {	// ACC64
6712      0,	// sub_32
6713      0,	// sub_64
6714      0,	// sub_dsp16_19
6715      0,	// sub_dsp20
6716      0,	// sub_dsp21
6717      0,	// sub_dsp22
6718      0,	// sub_dsp23
6719      58,	// sub_hi -> ACC64
6720      58,	// sub_lo -> ACC64
6721      0,	// sub_hi_then_sub_32
6722      0,	// sub_32_sub_hi_then_sub_32
6723    },
6724    {	// GP64
6725      59,	// sub_32 -> GP64
6726      0,	// sub_64
6727      0,	// sub_dsp16_19
6728      0,	// sub_dsp20
6729      0,	// sub_dsp21
6730      0,	// sub_dsp22
6731      0,	// sub_dsp23
6732      0,	// sub_hi
6733      0,	// sub_lo
6734      0,	// sub_hi_then_sub_32
6735      0,	// sub_32_sub_hi_then_sub_32
6736    },
6737    {	// GPR64_with_sub_32_in_CPURAReg
6738      60,	// sub_32 -> GPR64_with_sub_32_in_CPURAReg
6739      0,	// sub_64
6740      0,	// sub_dsp16_19
6741      0,	// sub_dsp20
6742      0,	// sub_dsp21
6743      0,	// sub_dsp22
6744      0,	// sub_dsp23
6745      0,	// sub_hi
6746      0,	// sub_lo
6747      0,	// sub_hi_then_sub_32
6748      0,	// sub_32_sub_hi_then_sub_32
6749    },
6750    {	// GPR64_with_sub_32_in_GPR32ZERO
6751      61,	// sub_32 -> GPR64_with_sub_32_in_GPR32ZERO
6752      0,	// sub_64
6753      0,	// sub_dsp16_19
6754      0,	// sub_dsp20
6755      0,	// sub_dsp21
6756      0,	// sub_dsp22
6757      0,	// sub_dsp23
6758      0,	// sub_hi
6759      0,	// sub_lo
6760      0,	// sub_hi_then_sub_32
6761      0,	// sub_32_sub_hi_then_sub_32
6762    },
6763    {	// HI64
6764      62,	// sub_32 -> HI64
6765      0,	// sub_64
6766      0,	// sub_dsp16_19
6767      0,	// sub_dsp20
6768      0,	// sub_dsp21
6769      0,	// sub_dsp22
6770      0,	// sub_dsp23
6771      0,	// sub_hi
6772      0,	// sub_lo
6773      0,	// sub_hi_then_sub_32
6774      0,	// sub_32_sub_hi_then_sub_32
6775    },
6776    {	// LO64
6777      63,	// sub_32 -> LO64
6778      0,	// sub_64
6779      0,	// sub_dsp16_19
6780      0,	// sub_dsp20
6781      0,	// sub_dsp21
6782      0,	// sub_dsp22
6783      0,	// sub_dsp23
6784      0,	// sub_hi
6785      0,	// sub_lo
6786      0,	// sub_hi_then_sub_32
6787      0,	// sub_32_sub_hi_then_sub_32
6788    },
6789    {	// SP64
6790      64,	// sub_32 -> SP64
6791      0,	// sub_64
6792      0,	// sub_dsp16_19
6793      0,	// sub_dsp20
6794      0,	// sub_dsp21
6795      0,	// sub_dsp22
6796      0,	// sub_dsp23
6797      0,	// sub_hi
6798      0,	// sub_lo
6799      0,	// sub_hi_then_sub_32
6800      0,	// sub_32_sub_hi_then_sub_32
6801    },
6802    {	// MSA128B
6803      0,	// sub_32
6804      65,	// sub_64 -> MSA128B
6805      0,	// sub_dsp16_19
6806      0,	// sub_dsp20
6807      0,	// sub_dsp21
6808      0,	// sub_dsp22
6809      0,	// sub_dsp23
6810      65,	// sub_hi -> MSA128B
6811      65,	// sub_lo -> MSA128B
6812      0,	// sub_hi_then_sub_32
6813      0,	// sub_32_sub_hi_then_sub_32
6814    },
6815    {	// MSA128D
6816      0,	// sub_32
6817      66,	// sub_64 -> MSA128D
6818      0,	// sub_dsp16_19
6819      0,	// sub_dsp20
6820      0,	// sub_dsp21
6821      0,	// sub_dsp22
6822      0,	// sub_dsp23
6823      66,	// sub_hi -> MSA128D
6824      66,	// sub_lo -> MSA128D
6825      0,	// sub_hi_then_sub_32
6826      0,	// sub_32_sub_hi_then_sub_32
6827    },
6828    {	// MSA128H
6829      0,	// sub_32
6830      67,	// sub_64 -> MSA128H
6831      0,	// sub_dsp16_19
6832      0,	// sub_dsp20
6833      0,	// sub_dsp21
6834      0,	// sub_dsp22
6835      0,	// sub_dsp23
6836      67,	// sub_hi -> MSA128H
6837      67,	// sub_lo -> MSA128H
6838      0,	// sub_hi_then_sub_32
6839      0,	// sub_32_sub_hi_then_sub_32
6840    },
6841    {	// MSA128W
6842      0,	// sub_32
6843      68,	// sub_64 -> MSA128W
6844      0,	// sub_dsp16_19
6845      0,	// sub_dsp20
6846      0,	// sub_dsp21
6847      0,	// sub_dsp22
6848      0,	// sub_dsp23
6849      68,	// sub_hi -> MSA128W
6850      68,	// sub_lo -> MSA128W
6851      0,	// sub_hi_then_sub_32
6852      0,	// sub_32_sub_hi_then_sub_32
6853    },
6854    {	// MSA128WEvens
6855      0,	// sub_32
6856      69,	// sub_64 -> MSA128WEvens
6857      0,	// sub_dsp16_19
6858      0,	// sub_dsp20
6859      0,	// sub_dsp21
6860      0,	// sub_dsp22
6861      0,	// sub_dsp23
6862      69,	// sub_hi -> MSA128WEvens
6863      69,	// sub_lo -> MSA128WEvens
6864      0,	// sub_hi_then_sub_32
6865      0,	// sub_32_sub_hi_then_sub_32
6866    },
6867    {	// ACC128
6868      70,	// sub_32 -> ACC128
6869      0,	// sub_64
6870      0,	// sub_dsp16_19
6871      0,	// sub_dsp20
6872      0,	// sub_dsp21
6873      0,	// sub_dsp22
6874      0,	// sub_dsp23
6875      70,	// sub_hi -> ACC128
6876      70,	// sub_lo -> ACC128
6877      70,	// sub_hi_then_sub_32 -> ACC128
6878      70,	// sub_32_sub_hi_then_sub_32 -> ACC128
6879    },
6880  };
6881  assert(RC && "Missing regclass");
6882  if (!Idx) return RC;
6883  --Idx;
6884  assert(Idx < 11 && "Bad subreg");
6885  unsigned TV = Table[RC->getID()][Idx];
6886  return TV ? getRegClass(TV - 1) : nullptr;
6887}
6888
6889const TargetRegisterClass *MipsGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
6890  static const uint8_t Table[70][11] = {
6891    {	// MSA128F16
6892      0,	// MSA128F16:sub_32
6893      38,	// MSA128F16:sub_64 -> FGR64
6894      0,	// MSA128F16:sub_dsp16_19
6895      0,	// MSA128F16:sub_dsp20
6896      0,	// MSA128F16:sub_dsp21
6897      0,	// MSA128F16:sub_dsp22
6898      0,	// MSA128F16:sub_dsp23
6899      0,	// MSA128F16:sub_hi
6900      7,	// MSA128F16:sub_lo -> FGR32
6901      0,	// MSA128F16:sub_hi_then_sub_32
6902      0,	// MSA128F16:sub_32_sub_hi_then_sub_32
6903    },
6904    {	// CCR
6905      0,	// CCR:sub_32
6906      0,	// CCR:sub_64
6907      0,	// CCR:sub_dsp16_19
6908      0,	// CCR:sub_dsp20
6909      0,	// CCR:sub_dsp21
6910      0,	// CCR:sub_dsp22
6911      0,	// CCR:sub_dsp23
6912      0,	// CCR:sub_hi
6913      0,	// CCR:sub_lo
6914      0,	// CCR:sub_hi_then_sub_32
6915      0,	// CCR:sub_32_sub_hi_then_sub_32
6916    },
6917    {	// COP0
6918      0,	// COP0:sub_32
6919      0,	// COP0:sub_64
6920      0,	// COP0:sub_dsp16_19
6921      0,	// COP0:sub_dsp20
6922      0,	// COP0:sub_dsp21
6923      0,	// COP0:sub_dsp22
6924      0,	// COP0:sub_dsp23
6925      0,	// COP0:sub_hi
6926      0,	// COP0:sub_lo
6927      0,	// COP0:sub_hi_then_sub_32
6928      0,	// COP0:sub_32_sub_hi_then_sub_32
6929    },
6930    {	// COP2
6931      0,	// COP2:sub_32
6932      0,	// COP2:sub_64
6933      0,	// COP2:sub_dsp16_19
6934      0,	// COP2:sub_dsp20
6935      0,	// COP2:sub_dsp21
6936      0,	// COP2:sub_dsp22
6937      0,	// COP2:sub_dsp23
6938      0,	// COP2:sub_hi
6939      0,	// COP2:sub_lo
6940      0,	// COP2:sub_hi_then_sub_32
6941      0,	// COP2:sub_32_sub_hi_then_sub_32
6942    },
6943    {	// COP3
6944      0,	// COP3:sub_32
6945      0,	// COP3:sub_64
6946      0,	// COP3:sub_dsp16_19
6947      0,	// COP3:sub_dsp20
6948      0,	// COP3:sub_dsp21
6949      0,	// COP3:sub_dsp22
6950      0,	// COP3:sub_dsp23
6951      0,	// COP3:sub_hi
6952      0,	// COP3:sub_lo
6953      0,	// COP3:sub_hi_then_sub_32
6954      0,	// COP3:sub_32_sub_hi_then_sub_32
6955    },
6956    {	// DSPR
6957      0,	// DSPR:sub_32
6958      0,	// DSPR:sub_64
6959      0,	// DSPR:sub_dsp16_19
6960      0,	// DSPR:sub_dsp20
6961      0,	// DSPR:sub_dsp21
6962      0,	// DSPR:sub_dsp22
6963      0,	// DSPR:sub_dsp23
6964      0,	// DSPR:sub_hi
6965      0,	// DSPR:sub_lo
6966      0,	// DSPR:sub_hi_then_sub_32
6967      0,	// DSPR:sub_32_sub_hi_then_sub_32
6968    },
6969    {	// FGR32
6970      0,	// FGR32:sub_32
6971      0,	// FGR32:sub_64
6972      0,	// FGR32:sub_dsp16_19
6973      0,	// FGR32:sub_dsp20
6974      0,	// FGR32:sub_dsp21
6975      0,	// FGR32:sub_dsp22
6976      0,	// FGR32:sub_dsp23
6977      0,	// FGR32:sub_hi
6978      0,	// FGR32:sub_lo
6979      0,	// FGR32:sub_hi_then_sub_32
6980      0,	// FGR32:sub_32_sub_hi_then_sub_32
6981    },
6982    {	// FGRCC
6983      0,	// FGRCC:sub_32
6984      0,	// FGRCC:sub_64
6985      0,	// FGRCC:sub_dsp16_19
6986      0,	// FGRCC:sub_dsp20
6987      0,	// FGRCC:sub_dsp21
6988      0,	// FGRCC:sub_dsp22
6989      0,	// FGRCC:sub_dsp23
6990      0,	// FGRCC:sub_hi
6991      0,	// FGRCC:sub_lo
6992      0,	// FGRCC:sub_hi_then_sub_32
6993      0,	// FGRCC:sub_32_sub_hi_then_sub_32
6994    },
6995    {	// GPR32
6996      0,	// GPR32:sub_32
6997      0,	// GPR32:sub_64
6998      0,	// GPR32:sub_dsp16_19
6999      0,	// GPR32:sub_dsp20
7000      0,	// GPR32:sub_dsp21
7001      0,	// GPR32:sub_dsp22
7002      0,	// GPR32:sub_dsp23
7003      0,	// GPR32:sub_hi
7004      0,	// GPR32:sub_lo
7005      0,	// GPR32:sub_hi_then_sub_32
7006      0,	// GPR32:sub_32_sub_hi_then_sub_32
7007    },
7008    {	// HWRegs
7009      0,	// HWRegs:sub_32
7010      0,	// HWRegs:sub_64
7011      0,	// HWRegs:sub_dsp16_19
7012      0,	// HWRegs:sub_dsp20
7013      0,	// HWRegs:sub_dsp21
7014      0,	// HWRegs:sub_dsp22
7015      0,	// HWRegs:sub_dsp23
7016      0,	// HWRegs:sub_hi
7017      0,	// HWRegs:sub_lo
7018      0,	// HWRegs:sub_hi_then_sub_32
7019      0,	// HWRegs:sub_32_sub_hi_then_sub_32
7020    },
7021    {	// MSACtrl
7022      0,	// MSACtrl:sub_32
7023      0,	// MSACtrl:sub_64
7024      0,	// MSACtrl:sub_dsp16_19
7025      0,	// MSACtrl:sub_dsp20
7026      0,	// MSACtrl:sub_dsp21
7027      0,	// MSACtrl:sub_dsp22
7028      0,	// MSACtrl:sub_dsp23
7029      0,	// MSACtrl:sub_hi
7030      0,	// MSACtrl:sub_lo
7031      0,	// MSACtrl:sub_hi_then_sub_32
7032      0,	// MSACtrl:sub_32_sub_hi_then_sub_32
7033    },
7034    {	// GPR32NONZERO
7035      0,	// GPR32NONZERO:sub_32
7036      0,	// GPR32NONZERO:sub_64
7037      0,	// GPR32NONZERO:sub_dsp16_19
7038      0,	// GPR32NONZERO:sub_dsp20
7039      0,	// GPR32NONZERO:sub_dsp21
7040      0,	// GPR32NONZERO:sub_dsp22
7041      0,	// GPR32NONZERO:sub_dsp23
7042      0,	// GPR32NONZERO:sub_hi
7043      0,	// GPR32NONZERO:sub_lo
7044      0,	// GPR32NONZERO:sub_hi_then_sub_32
7045      0,	// GPR32NONZERO:sub_32_sub_hi_then_sub_32
7046    },
7047    {	// CPU16RegsPlusSP
7048      0,	// CPU16RegsPlusSP:sub_32
7049      0,	// CPU16RegsPlusSP:sub_64
7050      0,	// CPU16RegsPlusSP:sub_dsp16_19
7051      0,	// CPU16RegsPlusSP:sub_dsp20
7052      0,	// CPU16RegsPlusSP:sub_dsp21
7053      0,	// CPU16RegsPlusSP:sub_dsp22
7054      0,	// CPU16RegsPlusSP:sub_dsp23
7055      0,	// CPU16RegsPlusSP:sub_hi
7056      0,	// CPU16RegsPlusSP:sub_lo
7057      0,	// CPU16RegsPlusSP:sub_hi_then_sub_32
7058      0,	// CPU16RegsPlusSP:sub_32_sub_hi_then_sub_32
7059    },
7060    {	// CPU16Regs
7061      0,	// CPU16Regs:sub_32
7062      0,	// CPU16Regs:sub_64
7063      0,	// CPU16Regs:sub_dsp16_19
7064      0,	// CPU16Regs:sub_dsp20
7065      0,	// CPU16Regs:sub_dsp21
7066      0,	// CPU16Regs:sub_dsp22
7067      0,	// CPU16Regs:sub_dsp23
7068      0,	// CPU16Regs:sub_hi
7069      0,	// CPU16Regs:sub_lo
7070      0,	// CPU16Regs:sub_hi_then_sub_32
7071      0,	// CPU16Regs:sub_32_sub_hi_then_sub_32
7072    },
7073    {	// FCC
7074      0,	// FCC:sub_32
7075      0,	// FCC:sub_64
7076      0,	// FCC:sub_dsp16_19
7077      0,	// FCC:sub_dsp20
7078      0,	// FCC:sub_dsp21
7079      0,	// FCC:sub_dsp22
7080      0,	// FCC:sub_dsp23
7081      0,	// FCC:sub_hi
7082      0,	// FCC:sub_lo
7083      0,	// FCC:sub_hi_then_sub_32
7084      0,	// FCC:sub_32_sub_hi_then_sub_32
7085    },
7086    {	// GPRMM16
7087      0,	// GPRMM16:sub_32
7088      0,	// GPRMM16:sub_64
7089      0,	// GPRMM16:sub_dsp16_19
7090      0,	// GPRMM16:sub_dsp20
7091      0,	// GPRMM16:sub_dsp21
7092      0,	// GPRMM16:sub_dsp22
7093      0,	// GPRMM16:sub_dsp23
7094      0,	// GPRMM16:sub_hi
7095      0,	// GPRMM16:sub_lo
7096      0,	// GPRMM16:sub_hi_then_sub_32
7097      0,	// GPRMM16:sub_32_sub_hi_then_sub_32
7098    },
7099    {	// GPRMM16MoveP
7100      0,	// GPRMM16MoveP:sub_32
7101      0,	// GPRMM16MoveP:sub_64
7102      0,	// GPRMM16MoveP:sub_dsp16_19
7103      0,	// GPRMM16MoveP:sub_dsp20
7104      0,	// GPRMM16MoveP:sub_dsp21
7105      0,	// GPRMM16MoveP:sub_dsp22
7106      0,	// GPRMM16MoveP:sub_dsp23
7107      0,	// GPRMM16MoveP:sub_hi
7108      0,	// GPRMM16MoveP:sub_lo
7109      0,	// GPRMM16MoveP:sub_hi_then_sub_32
7110      0,	// GPRMM16MoveP:sub_32_sub_hi_then_sub_32
7111    },
7112    {	// GPRMM16Zero
7113      0,	// GPRMM16Zero:sub_32
7114      0,	// GPRMM16Zero:sub_64
7115      0,	// GPRMM16Zero:sub_dsp16_19
7116      0,	// GPRMM16Zero:sub_dsp20
7117      0,	// GPRMM16Zero:sub_dsp21
7118      0,	// GPRMM16Zero:sub_dsp22
7119      0,	// GPRMM16Zero:sub_dsp23
7120      0,	// GPRMM16Zero:sub_hi
7121      0,	// GPRMM16Zero:sub_lo
7122      0,	// GPRMM16Zero:sub_hi_then_sub_32
7123      0,	// GPRMM16Zero:sub_32_sub_hi_then_sub_32
7124    },
7125    {	// CPU16Regs_and_GPRMM16Zero
7126      0,	// CPU16Regs_and_GPRMM16Zero:sub_32
7127      0,	// CPU16Regs_and_GPRMM16Zero:sub_64
7128      0,	// CPU16Regs_and_GPRMM16Zero:sub_dsp16_19
7129      0,	// CPU16Regs_and_GPRMM16Zero:sub_dsp20
7130      0,	// CPU16Regs_and_GPRMM16Zero:sub_dsp21
7131      0,	// CPU16Regs_and_GPRMM16Zero:sub_dsp22
7132      0,	// CPU16Regs_and_GPRMM16Zero:sub_dsp23
7133      0,	// CPU16Regs_and_GPRMM16Zero:sub_hi
7134      0,	// CPU16Regs_and_GPRMM16Zero:sub_lo
7135      0,	// CPU16Regs_and_GPRMM16Zero:sub_hi_then_sub_32
7136      0,	// CPU16Regs_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32
7137    },
7138    {	// GPR32NONZERO_and_GPRMM16MoveP
7139      0,	// GPR32NONZERO_and_GPRMM16MoveP:sub_32
7140      0,	// GPR32NONZERO_and_GPRMM16MoveP:sub_64
7141      0,	// GPR32NONZERO_and_GPRMM16MoveP:sub_dsp16_19
7142      0,	// GPR32NONZERO_and_GPRMM16MoveP:sub_dsp20
7143      0,	// GPR32NONZERO_and_GPRMM16MoveP:sub_dsp21
7144      0,	// GPR32NONZERO_and_GPRMM16MoveP:sub_dsp22
7145      0,	// GPR32NONZERO_and_GPRMM16MoveP:sub_dsp23
7146      0,	// GPR32NONZERO_and_GPRMM16MoveP:sub_hi
7147      0,	// GPR32NONZERO_and_GPRMM16MoveP:sub_lo
7148      0,	// GPR32NONZERO_and_GPRMM16MoveP:sub_hi_then_sub_32
7149      0,	// GPR32NONZERO_and_GPRMM16MoveP:sub_32_sub_hi_then_sub_32
7150    },
7151    {	// GPRMM16MovePPairSecond
7152      0,	// GPRMM16MovePPairSecond:sub_32
7153      0,	// GPRMM16MovePPairSecond:sub_64
7154      0,	// GPRMM16MovePPairSecond:sub_dsp16_19
7155      0,	// GPRMM16MovePPairSecond:sub_dsp20
7156      0,	// GPRMM16MovePPairSecond:sub_dsp21
7157      0,	// GPRMM16MovePPairSecond:sub_dsp22
7158      0,	// GPRMM16MovePPairSecond:sub_dsp23
7159      0,	// GPRMM16MovePPairSecond:sub_hi
7160      0,	// GPRMM16MovePPairSecond:sub_lo
7161      0,	// GPRMM16MovePPairSecond:sub_hi_then_sub_32
7162      0,	// GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32
7163    },
7164    {	// CPU16Regs_and_GPRMM16MoveP
7165      0,	// CPU16Regs_and_GPRMM16MoveP:sub_32
7166      0,	// CPU16Regs_and_GPRMM16MoveP:sub_64
7167      0,	// CPU16Regs_and_GPRMM16MoveP:sub_dsp16_19
7168      0,	// CPU16Regs_and_GPRMM16MoveP:sub_dsp20
7169      0,	// CPU16Regs_and_GPRMM16MoveP:sub_dsp21
7170      0,	// CPU16Regs_and_GPRMM16MoveP:sub_dsp22
7171      0,	// CPU16Regs_and_GPRMM16MoveP:sub_dsp23
7172      0,	// CPU16Regs_and_GPRMM16MoveP:sub_hi
7173      0,	// CPU16Regs_and_GPRMM16MoveP:sub_lo
7174      0,	// CPU16Regs_and_GPRMM16MoveP:sub_hi_then_sub_32
7175      0,	// CPU16Regs_and_GPRMM16MoveP:sub_32_sub_hi_then_sub_32
7176    },
7177    {	// GPRMM16MoveP_and_GPRMM16Zero
7178      0,	// GPRMM16MoveP_and_GPRMM16Zero:sub_32
7179      0,	// GPRMM16MoveP_and_GPRMM16Zero:sub_64
7180      0,	// GPRMM16MoveP_and_GPRMM16Zero:sub_dsp16_19
7181      0,	// GPRMM16MoveP_and_GPRMM16Zero:sub_dsp20
7182      0,	// GPRMM16MoveP_and_GPRMM16Zero:sub_dsp21
7183      0,	// GPRMM16MoveP_and_GPRMM16Zero:sub_dsp22
7184      0,	// GPRMM16MoveP_and_GPRMM16Zero:sub_dsp23
7185      0,	// GPRMM16MoveP_and_GPRMM16Zero:sub_hi
7186      0,	// GPRMM16MoveP_and_GPRMM16Zero:sub_lo
7187      0,	// GPRMM16MoveP_and_GPRMM16Zero:sub_hi_then_sub_32
7188      0,	// GPRMM16MoveP_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32
7189    },
7190    {	// HI32DSP
7191      0,	// HI32DSP:sub_32
7192      0,	// HI32DSP:sub_64
7193      0,	// HI32DSP:sub_dsp16_19
7194      0,	// HI32DSP:sub_dsp20
7195      0,	// HI32DSP:sub_dsp21
7196      0,	// HI32DSP:sub_dsp22
7197      0,	// HI32DSP:sub_dsp23
7198      0,	// HI32DSP:sub_hi
7199      0,	// HI32DSP:sub_lo
7200      0,	// HI32DSP:sub_hi_then_sub_32
7201      0,	// HI32DSP:sub_32_sub_hi_then_sub_32
7202    },
7203    {	// LO32DSP
7204      0,	// LO32DSP:sub_32
7205      0,	// LO32DSP:sub_64
7206      0,	// LO32DSP:sub_dsp16_19
7207      0,	// LO32DSP:sub_dsp20
7208      0,	// LO32DSP:sub_dsp21
7209      0,	// LO32DSP:sub_dsp22
7210      0,	// LO32DSP:sub_dsp23
7211      0,	// LO32DSP:sub_hi
7212      0,	// LO32DSP:sub_lo
7213      0,	// LO32DSP:sub_hi_then_sub_32
7214      0,	// LO32DSP:sub_32_sub_hi_then_sub_32
7215    },
7216    {	// CPU16Regs_and_GPRMM16MovePPairSecond
7217      0,	// CPU16Regs_and_GPRMM16MovePPairSecond:sub_32
7218      0,	// CPU16Regs_and_GPRMM16MovePPairSecond:sub_64
7219      0,	// CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp16_19
7220      0,	// CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp20
7221      0,	// CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp21
7222      0,	// CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp22
7223      0,	// CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp23
7224      0,	// CPU16Regs_and_GPRMM16MovePPairSecond:sub_hi
7225      0,	// CPU16Regs_and_GPRMM16MovePPairSecond:sub_lo
7226      0,	// CPU16Regs_and_GPRMM16MovePPairSecond:sub_hi_then_sub_32
7227      0,	// CPU16Regs_and_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32
7228    },
7229    {	// GPRMM16MovePPairFirst
7230      0,	// GPRMM16MovePPairFirst:sub_32
7231      0,	// GPRMM16MovePPairFirst:sub_64
7232      0,	// GPRMM16MovePPairFirst:sub_dsp16_19
7233      0,	// GPRMM16MovePPairFirst:sub_dsp20
7234      0,	// GPRMM16MovePPairFirst:sub_dsp21
7235      0,	// GPRMM16MovePPairFirst:sub_dsp22
7236      0,	// GPRMM16MovePPairFirst:sub_dsp23
7237      0,	// GPRMM16MovePPairFirst:sub_hi
7238      0,	// GPRMM16MovePPairFirst:sub_lo
7239      0,	// GPRMM16MovePPairFirst:sub_hi_then_sub_32
7240      0,	// GPRMM16MovePPairFirst:sub_32_sub_hi_then_sub_32
7241    },
7242    {	// GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
7243      0,	// GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_32
7244      0,	// GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_64
7245      0,	// GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp16_19
7246      0,	// GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp20
7247      0,	// GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp21
7248      0,	// GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp22
7249      0,	// GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp23
7250      0,	// GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_hi
7251      0,	// GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_lo
7252      0,	// GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_hi_then_sub_32
7253      0,	// GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32
7254    },
7255    {	// GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
7256      0,	// GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_32
7257      0,	// GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_64
7258      0,	// GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp16_19
7259      0,	// GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp20
7260      0,	// GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp21
7261      0,	// GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp22
7262      0,	// GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp23
7263      0,	// GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_hi
7264      0,	// GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_lo
7265      0,	// GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_hi_then_sub_32
7266      0,	// GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32
7267    },
7268    {	// CPURAReg
7269      0,	// CPURAReg:sub_32
7270      0,	// CPURAReg:sub_64
7271      0,	// CPURAReg:sub_dsp16_19
7272      0,	// CPURAReg:sub_dsp20
7273      0,	// CPURAReg:sub_dsp21
7274      0,	// CPURAReg:sub_dsp22
7275      0,	// CPURAReg:sub_dsp23
7276      0,	// CPURAReg:sub_hi
7277      0,	// CPURAReg:sub_lo
7278      0,	// CPURAReg:sub_hi_then_sub_32
7279      0,	// CPURAReg:sub_32_sub_hi_then_sub_32
7280    },
7281    {	// CPUSPReg
7282      0,	// CPUSPReg:sub_32
7283      0,	// CPUSPReg:sub_64
7284      0,	// CPUSPReg:sub_dsp16_19
7285      0,	// CPUSPReg:sub_dsp20
7286      0,	// CPUSPReg:sub_dsp21
7287      0,	// CPUSPReg:sub_dsp22
7288      0,	// CPUSPReg:sub_dsp23
7289      0,	// CPUSPReg:sub_hi
7290      0,	// CPUSPReg:sub_lo
7291      0,	// CPUSPReg:sub_hi_then_sub_32
7292      0,	// CPUSPReg:sub_32_sub_hi_then_sub_32
7293    },
7294    {	// DSPCC
7295      0,	// DSPCC:sub_32
7296      0,	// DSPCC:sub_64
7297      0,	// DSPCC:sub_dsp16_19
7298      0,	// DSPCC:sub_dsp20
7299      0,	// DSPCC:sub_dsp21
7300      0,	// DSPCC:sub_dsp22
7301      0,	// DSPCC:sub_dsp23
7302      0,	// DSPCC:sub_hi
7303      0,	// DSPCC:sub_lo
7304      0,	// DSPCC:sub_hi_then_sub_32
7305      0,	// DSPCC:sub_32_sub_hi_then_sub_32
7306    },
7307    {	// GP32
7308      0,	// GP32:sub_32
7309      0,	// GP32:sub_64
7310      0,	// GP32:sub_dsp16_19
7311      0,	// GP32:sub_dsp20
7312      0,	// GP32:sub_dsp21
7313      0,	// GP32:sub_dsp22
7314      0,	// GP32:sub_dsp23
7315      0,	// GP32:sub_hi
7316      0,	// GP32:sub_lo
7317      0,	// GP32:sub_hi_then_sub_32
7318      0,	// GP32:sub_32_sub_hi_then_sub_32
7319    },
7320    {	// GPR32ZERO
7321      0,	// GPR32ZERO:sub_32
7322      0,	// GPR32ZERO:sub_64
7323      0,	// GPR32ZERO:sub_dsp16_19
7324      0,	// GPR32ZERO:sub_dsp20
7325      0,	// GPR32ZERO:sub_dsp21
7326      0,	// GPR32ZERO:sub_dsp22
7327      0,	// GPR32ZERO:sub_dsp23
7328      0,	// GPR32ZERO:sub_hi
7329      0,	// GPR32ZERO:sub_lo
7330      0,	// GPR32ZERO:sub_hi_then_sub_32
7331      0,	// GPR32ZERO:sub_32_sub_hi_then_sub_32
7332    },
7333    {	// HI32
7334      0,	// HI32:sub_32
7335      0,	// HI32:sub_64
7336      0,	// HI32:sub_dsp16_19
7337      0,	// HI32:sub_dsp20
7338      0,	// HI32:sub_dsp21
7339      0,	// HI32:sub_dsp22
7340      0,	// HI32:sub_dsp23
7341      0,	// HI32:sub_hi
7342      0,	// HI32:sub_lo
7343      0,	// HI32:sub_hi_then_sub_32
7344      0,	// HI32:sub_32_sub_hi_then_sub_32
7345    },
7346    {	// LO32
7347      0,	// LO32:sub_32
7348      0,	// LO32:sub_64
7349      0,	// LO32:sub_dsp16_19
7350      0,	// LO32:sub_dsp20
7351      0,	// LO32:sub_dsp21
7352      0,	// LO32:sub_dsp22
7353      0,	// LO32:sub_dsp23
7354      0,	// LO32:sub_hi
7355      0,	// LO32:sub_lo
7356      0,	// LO32:sub_hi_then_sub_32
7357      0,	// LO32:sub_32_sub_hi_then_sub_32
7358    },
7359    {	// SP32
7360      0,	// SP32:sub_32
7361      0,	// SP32:sub_64
7362      0,	// SP32:sub_dsp16_19
7363      0,	// SP32:sub_dsp20
7364      0,	// SP32:sub_dsp21
7365      0,	// SP32:sub_dsp22
7366      0,	// SP32:sub_dsp23
7367      0,	// SP32:sub_hi
7368      0,	// SP32:sub_lo
7369      0,	// SP32:sub_hi_then_sub_32
7370      0,	// SP32:sub_32_sub_hi_then_sub_32
7371    },
7372    {	// FGR64
7373      0,	// FGR64:sub_32
7374      0,	// FGR64:sub_64
7375      0,	// FGR64:sub_dsp16_19
7376      0,	// FGR64:sub_dsp20
7377      0,	// FGR64:sub_dsp21
7378      0,	// FGR64:sub_dsp22
7379      0,	// FGR64:sub_dsp23
7380      0,	// FGR64:sub_hi
7381      7,	// FGR64:sub_lo -> FGR32
7382      0,	// FGR64:sub_hi_then_sub_32
7383      0,	// FGR64:sub_32_sub_hi_then_sub_32
7384    },
7385    {	// GPR64
7386      6,	// GPR64:sub_32 -> DSPR
7387      0,	// GPR64:sub_64
7388      0,	// GPR64:sub_dsp16_19
7389      0,	// GPR64:sub_dsp20
7390      0,	// GPR64:sub_dsp21
7391      0,	// GPR64:sub_dsp22
7392      0,	// GPR64:sub_dsp23
7393      0,	// GPR64:sub_hi
7394      0,	// GPR64:sub_lo
7395      0,	// GPR64:sub_hi_then_sub_32
7396      0,	// GPR64:sub_32_sub_hi_then_sub_32
7397    },
7398    {	// GPR64_with_sub_32_in_GPR32NONZERO
7399      12,	// GPR64_with_sub_32_in_GPR32NONZERO:sub_32 -> GPR32NONZERO
7400      0,	// GPR64_with_sub_32_in_GPR32NONZERO:sub_64
7401      0,	// GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp16_19
7402      0,	// GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp20
7403      0,	// GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp21
7404      0,	// GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp22
7405      0,	// GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp23
7406      0,	// GPR64_with_sub_32_in_GPR32NONZERO:sub_hi
7407      0,	// GPR64_with_sub_32_in_GPR32NONZERO:sub_lo
7408      0,	// GPR64_with_sub_32_in_GPR32NONZERO:sub_hi_then_sub_32
7409      0,	// GPR64_with_sub_32_in_GPR32NONZERO:sub_32_sub_hi_then_sub_32
7410    },
7411    {	// AFGR64
7412      0,	// AFGR64:sub_32
7413      0,	// AFGR64:sub_64
7414      0,	// AFGR64:sub_dsp16_19
7415      0,	// AFGR64:sub_dsp20
7416      0,	// AFGR64:sub_dsp21
7417      0,	// AFGR64:sub_dsp22
7418      0,	// AFGR64:sub_dsp23
7419      8,	// AFGR64:sub_hi -> FGRCC
7420      8,	// AFGR64:sub_lo -> FGRCC
7421      0,	// AFGR64:sub_hi_then_sub_32
7422      0,	// AFGR64:sub_32_sub_hi_then_sub_32
7423    },
7424    {	// GPR64_with_sub_32_in_CPU16RegsPlusSP
7425      13,	// GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_32 -> CPU16RegsPlusSP
7426      0,	// GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_64
7427      0,	// GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp16_19
7428      0,	// GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp20
7429      0,	// GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp21
7430      0,	// GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp22
7431      0,	// GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp23
7432      0,	// GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_hi
7433      0,	// GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_lo
7434      0,	// GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_hi_then_sub_32
7435      0,	// GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_32_sub_hi_then_sub_32
7436    },
7437    {	// GPR64_with_sub_32_in_CPU16Regs
7438      14,	// GPR64_with_sub_32_in_CPU16Regs:sub_32 -> CPU16Regs
7439      0,	// GPR64_with_sub_32_in_CPU16Regs:sub_64
7440      0,	// GPR64_with_sub_32_in_CPU16Regs:sub_dsp16_19
7441      0,	// GPR64_with_sub_32_in_CPU16Regs:sub_dsp20
7442      0,	// GPR64_with_sub_32_in_CPU16Regs:sub_dsp21
7443      0,	// GPR64_with_sub_32_in_CPU16Regs:sub_dsp22
7444      0,	// GPR64_with_sub_32_in_CPU16Regs:sub_dsp23
7445      0,	// GPR64_with_sub_32_in_CPU16Regs:sub_hi
7446      0,	// GPR64_with_sub_32_in_CPU16Regs:sub_lo
7447      0,	// GPR64_with_sub_32_in_CPU16Regs:sub_hi_then_sub_32
7448      0,	// GPR64_with_sub_32_in_CPU16Regs:sub_32_sub_hi_then_sub_32
7449    },
7450    {	// GPR64_with_sub_32_in_GPRMM16MoveP
7451      17,	// GPR64_with_sub_32_in_GPRMM16MoveP:sub_32 -> GPRMM16MoveP
7452      0,	// GPR64_with_sub_32_in_GPRMM16MoveP:sub_64
7453      0,	// GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp16_19
7454      0,	// GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp20
7455      0,	// GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp21
7456      0,	// GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp22
7457      0,	// GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp23
7458      0,	// GPR64_with_sub_32_in_GPRMM16MoveP:sub_hi
7459      0,	// GPR64_with_sub_32_in_GPRMM16MoveP:sub_lo
7460      0,	// GPR64_with_sub_32_in_GPRMM16MoveP:sub_hi_then_sub_32
7461      0,	// GPR64_with_sub_32_in_GPRMM16MoveP:sub_32_sub_hi_then_sub_32
7462    },
7463    {	// GPR64_with_sub_32_in_GPRMM16Zero
7464      18,	// GPR64_with_sub_32_in_GPRMM16Zero:sub_32 -> GPRMM16Zero
7465      0,	// GPR64_with_sub_32_in_GPRMM16Zero:sub_64
7466      0,	// GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp16_19
7467      0,	// GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp20
7468      0,	// GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp21
7469      0,	// GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp22
7470      0,	// GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp23
7471      0,	// GPR64_with_sub_32_in_GPRMM16Zero:sub_hi
7472      0,	// GPR64_with_sub_32_in_GPRMM16Zero:sub_lo
7473      0,	// GPR64_with_sub_32_in_GPRMM16Zero:sub_hi_then_sub_32
7474      0,	// GPR64_with_sub_32_in_GPRMM16Zero:sub_32_sub_hi_then_sub_32
7475    },
7476    {	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
7477      19,	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_32 -> CPU16Regs_and_GPRMM16Zero
7478      0,	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_64
7479      0,	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp16_19
7480      0,	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp20
7481      0,	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp21
7482      0,	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp22
7483      0,	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp23
7484      0,	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_hi
7485      0,	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_lo
7486      0,	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_hi_then_sub_32
7487      0,	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32
7488    },
7489    {	// GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
7490      20,	// GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_32 -> GPR32NONZERO_and_GPRMM16MoveP
7491      0,	// GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_64
7492      0,	// GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp16_19
7493      0,	// GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp20
7494      0,	// GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp21
7495      0,	// GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp22
7496      0,	// GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp23
7497      0,	// GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_hi
7498      0,	// GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_lo
7499      0,	// GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_hi_then_sub_32
7500      0,	// GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_32_sub_hi_then_sub_32
7501    },
7502    {	// GPR64_with_sub_32_in_GPRMM16MovePPairSecond
7503      21,	// GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_32 -> GPRMM16MovePPairSecond
7504      0,	// GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_64
7505      0,	// GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp16_19
7506      0,	// GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp20
7507      0,	// GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp21
7508      0,	// GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp22
7509      0,	// GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp23
7510      0,	// GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_hi
7511      0,	// GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_lo
7512      0,	// GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_hi_then_sub_32
7513      0,	// GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32
7514    },
7515    {	// ACC64DSP
7516      0,	// ACC64DSP:sub_32
7517      0,	// ACC64DSP:sub_64
7518      0,	// ACC64DSP:sub_dsp16_19
7519      0,	// ACC64DSP:sub_dsp20
7520      0,	// ACC64DSP:sub_dsp21
7521      0,	// ACC64DSP:sub_dsp22
7522      0,	// ACC64DSP:sub_dsp23
7523      24,	// ACC64DSP:sub_hi -> HI32DSP
7524      25,	// ACC64DSP:sub_lo -> LO32DSP
7525      0,	// ACC64DSP:sub_hi_then_sub_32
7526      0,	// ACC64DSP:sub_32_sub_hi_then_sub_32
7527    },
7528    {	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
7529      22,	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_32 -> CPU16Regs_and_GPRMM16MoveP
7530      0,	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_64
7531      0,	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp16_19
7532      0,	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp20
7533      0,	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp21
7534      0,	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp22
7535      0,	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp23
7536      0,	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_hi
7537      0,	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_lo
7538      0,	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_hi_then_sub_32
7539      0,	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_32_sub_hi_then_sub_32
7540    },
7541    {	// GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
7542      23,	// GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_32 -> GPRMM16MoveP_and_GPRMM16Zero
7543      0,	// GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_64
7544      0,	// GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp16_19
7545      0,	// GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp20
7546      0,	// GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp21
7547      0,	// GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp22
7548      0,	// GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp23
7549      0,	// GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_hi
7550      0,	// GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_lo
7551      0,	// GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_hi_then_sub_32
7552      0,	// GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32
7553    },
7554    {	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond
7555      26,	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_32 -> CPU16Regs_and_GPRMM16MovePPairSecond
7556      0,	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_64
7557      0,	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp16_19
7558      0,	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp20
7559      0,	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp21
7560      0,	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp22
7561      0,	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp23
7562      0,	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_hi
7563      0,	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_lo
7564      0,	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_hi_then_sub_32
7565      0,	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32
7566    },
7567    {	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst
7568      27,	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_32 -> GPRMM16MovePPairFirst
7569      0,	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_64
7570      0,	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp16_19
7571      0,	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp20
7572      0,	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp21
7573      0,	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp22
7574      0,	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp23
7575      0,	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_hi
7576      0,	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_lo
7577      0,	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_hi_then_sub_32
7578      0,	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_32_sub_hi_then_sub_32
7579    },
7580    {	// GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
7581      28,	// GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_32 -> GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
7582      0,	// GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_64
7583      0,	// GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp16_19
7584      0,	// GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp20
7585      0,	// GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp21
7586      0,	// GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp22
7587      0,	// GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp23
7588      0,	// GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_hi
7589      0,	// GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_lo
7590      0,	// GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_hi_then_sub_32
7591      0,	// GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32
7592    },
7593    {	// OCTEON_MPL
7594      0,	// OCTEON_MPL:sub_32
7595      0,	// OCTEON_MPL:sub_64
7596      0,	// OCTEON_MPL:sub_dsp16_19
7597      0,	// OCTEON_MPL:sub_dsp20
7598      0,	// OCTEON_MPL:sub_dsp21
7599      0,	// OCTEON_MPL:sub_dsp22
7600      0,	// OCTEON_MPL:sub_dsp23
7601      0,	// OCTEON_MPL:sub_hi
7602      0,	// OCTEON_MPL:sub_lo
7603      0,	// OCTEON_MPL:sub_hi_then_sub_32
7604      0,	// OCTEON_MPL:sub_32_sub_hi_then_sub_32
7605    },
7606    {	// OCTEON_P
7607      0,	// OCTEON_P:sub_32
7608      0,	// OCTEON_P:sub_64
7609      0,	// OCTEON_P:sub_dsp16_19
7610      0,	// OCTEON_P:sub_dsp20
7611      0,	// OCTEON_P:sub_dsp21
7612      0,	// OCTEON_P:sub_dsp22
7613      0,	// OCTEON_P:sub_dsp23
7614      0,	// OCTEON_P:sub_hi
7615      0,	// OCTEON_P:sub_lo
7616      0,	// OCTEON_P:sub_hi_then_sub_32
7617      0,	// OCTEON_P:sub_32_sub_hi_then_sub_32
7618    },
7619    {	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
7620      29,	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_32 -> GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
7621      0,	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_64
7622      0,	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp16_19
7623      0,	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp20
7624      0,	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp21
7625      0,	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp22
7626      0,	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp23
7627      0,	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_hi
7628      0,	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_lo
7629      0,	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_hi_then_sub_32
7630      0,	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32
7631    },
7632    {	// ACC64
7633      0,	// ACC64:sub_32
7634      0,	// ACC64:sub_64
7635      0,	// ACC64:sub_dsp16_19
7636      0,	// ACC64:sub_dsp20
7637      0,	// ACC64:sub_dsp21
7638      0,	// ACC64:sub_dsp22
7639      0,	// ACC64:sub_dsp23
7640      35,	// ACC64:sub_hi -> HI32
7641      36,	// ACC64:sub_lo -> LO32
7642      0,	// ACC64:sub_hi_then_sub_32
7643      0,	// ACC64:sub_32_sub_hi_then_sub_32
7644    },
7645    {	// GP64
7646      33,	// GP64:sub_32 -> GP32
7647      0,	// GP64:sub_64
7648      0,	// GP64:sub_dsp16_19
7649      0,	// GP64:sub_dsp20
7650      0,	// GP64:sub_dsp21
7651      0,	// GP64:sub_dsp22
7652      0,	// GP64:sub_dsp23
7653      0,	// GP64:sub_hi
7654      0,	// GP64:sub_lo
7655      0,	// GP64:sub_hi_then_sub_32
7656      0,	// GP64:sub_32_sub_hi_then_sub_32
7657    },
7658    {	// GPR64_with_sub_32_in_CPURAReg
7659      30,	// GPR64_with_sub_32_in_CPURAReg:sub_32 -> CPURAReg
7660      0,	// GPR64_with_sub_32_in_CPURAReg:sub_64
7661      0,	// GPR64_with_sub_32_in_CPURAReg:sub_dsp16_19
7662      0,	// GPR64_with_sub_32_in_CPURAReg:sub_dsp20
7663      0,	// GPR64_with_sub_32_in_CPURAReg:sub_dsp21
7664      0,	// GPR64_with_sub_32_in_CPURAReg:sub_dsp22
7665      0,	// GPR64_with_sub_32_in_CPURAReg:sub_dsp23
7666      0,	// GPR64_with_sub_32_in_CPURAReg:sub_hi
7667      0,	// GPR64_with_sub_32_in_CPURAReg:sub_lo
7668      0,	// GPR64_with_sub_32_in_CPURAReg:sub_hi_then_sub_32
7669      0,	// GPR64_with_sub_32_in_CPURAReg:sub_32_sub_hi_then_sub_32
7670    },
7671    {	// GPR64_with_sub_32_in_GPR32ZERO
7672      34,	// GPR64_with_sub_32_in_GPR32ZERO:sub_32 -> GPR32ZERO
7673      0,	// GPR64_with_sub_32_in_GPR32ZERO:sub_64
7674      0,	// GPR64_with_sub_32_in_GPR32ZERO:sub_dsp16_19
7675      0,	// GPR64_with_sub_32_in_GPR32ZERO:sub_dsp20
7676      0,	// GPR64_with_sub_32_in_GPR32ZERO:sub_dsp21
7677      0,	// GPR64_with_sub_32_in_GPR32ZERO:sub_dsp22
7678      0,	// GPR64_with_sub_32_in_GPR32ZERO:sub_dsp23
7679      0,	// GPR64_with_sub_32_in_GPR32ZERO:sub_hi
7680      0,	// GPR64_with_sub_32_in_GPR32ZERO:sub_lo
7681      0,	// GPR64_with_sub_32_in_GPR32ZERO:sub_hi_then_sub_32
7682      0,	// GPR64_with_sub_32_in_GPR32ZERO:sub_32_sub_hi_then_sub_32
7683    },
7684    {	// HI64
7685      35,	// HI64:sub_32 -> HI32
7686      0,	// HI64:sub_64
7687      0,	// HI64:sub_dsp16_19
7688      0,	// HI64:sub_dsp20
7689      0,	// HI64:sub_dsp21
7690      0,	// HI64:sub_dsp22
7691      0,	// HI64:sub_dsp23
7692      0,	// HI64:sub_hi
7693      0,	// HI64:sub_lo
7694      0,	// HI64:sub_hi_then_sub_32
7695      0,	// HI64:sub_32_sub_hi_then_sub_32
7696    },
7697    {	// LO64
7698      36,	// LO64:sub_32 -> LO32
7699      0,	// LO64:sub_64
7700      0,	// LO64:sub_dsp16_19
7701      0,	// LO64:sub_dsp20
7702      0,	// LO64:sub_dsp21
7703      0,	// LO64:sub_dsp22
7704      0,	// LO64:sub_dsp23
7705      0,	// LO64:sub_hi
7706      0,	// LO64:sub_lo
7707      0,	// LO64:sub_hi_then_sub_32
7708      0,	// LO64:sub_32_sub_hi_then_sub_32
7709    },
7710    {	// SP64
7711      31,	// SP64:sub_32 -> CPUSPReg
7712      0,	// SP64:sub_64
7713      0,	// SP64:sub_dsp16_19
7714      0,	// SP64:sub_dsp20
7715      0,	// SP64:sub_dsp21
7716      0,	// SP64:sub_dsp22
7717      0,	// SP64:sub_dsp23
7718      0,	// SP64:sub_hi
7719      0,	// SP64:sub_lo
7720      0,	// SP64:sub_hi_then_sub_32
7721      0,	// SP64:sub_32_sub_hi_then_sub_32
7722    },
7723    {	// MSA128B
7724      0,	// MSA128B:sub_32
7725      38,	// MSA128B:sub_64 -> FGR64
7726      0,	// MSA128B:sub_dsp16_19
7727      0,	// MSA128B:sub_dsp20
7728      0,	// MSA128B:sub_dsp21
7729      0,	// MSA128B:sub_dsp22
7730      0,	// MSA128B:sub_dsp23
7731      0,	// MSA128B:sub_hi
7732      7,	// MSA128B:sub_lo -> FGR32
7733      0,	// MSA128B:sub_hi_then_sub_32
7734      0,	// MSA128B:sub_32_sub_hi_then_sub_32
7735    },
7736    {	// MSA128D
7737      0,	// MSA128D:sub_32
7738      38,	// MSA128D:sub_64 -> FGR64
7739      0,	// MSA128D:sub_dsp16_19
7740      0,	// MSA128D:sub_dsp20
7741      0,	// MSA128D:sub_dsp21
7742      0,	// MSA128D:sub_dsp22
7743      0,	// MSA128D:sub_dsp23
7744      0,	// MSA128D:sub_hi
7745      7,	// MSA128D:sub_lo -> FGR32
7746      0,	// MSA128D:sub_hi_then_sub_32
7747      0,	// MSA128D:sub_32_sub_hi_then_sub_32
7748    },
7749    {	// MSA128H
7750      0,	// MSA128H:sub_32
7751      38,	// MSA128H:sub_64 -> FGR64
7752      0,	// MSA128H:sub_dsp16_19
7753      0,	// MSA128H:sub_dsp20
7754      0,	// MSA128H:sub_dsp21
7755      0,	// MSA128H:sub_dsp22
7756      0,	// MSA128H:sub_dsp23
7757      0,	// MSA128H:sub_hi
7758      7,	// MSA128H:sub_lo -> FGR32
7759      0,	// MSA128H:sub_hi_then_sub_32
7760      0,	// MSA128H:sub_32_sub_hi_then_sub_32
7761    },
7762    {	// MSA128W
7763      0,	// MSA128W:sub_32
7764      38,	// MSA128W:sub_64 -> FGR64
7765      0,	// MSA128W:sub_dsp16_19
7766      0,	// MSA128W:sub_dsp20
7767      0,	// MSA128W:sub_dsp21
7768      0,	// MSA128W:sub_dsp22
7769      0,	// MSA128W:sub_dsp23
7770      0,	// MSA128W:sub_hi
7771      7,	// MSA128W:sub_lo -> FGR32
7772      0,	// MSA128W:sub_hi_then_sub_32
7773      0,	// MSA128W:sub_32_sub_hi_then_sub_32
7774    },
7775    {	// MSA128WEvens
7776      0,	// MSA128WEvens:sub_32
7777      38,	// MSA128WEvens:sub_64 -> FGR64
7778      0,	// MSA128WEvens:sub_dsp16_19
7779      0,	// MSA128WEvens:sub_dsp20
7780      0,	// MSA128WEvens:sub_dsp21
7781      0,	// MSA128WEvens:sub_dsp22
7782      0,	// MSA128WEvens:sub_dsp23
7783      0,	// MSA128WEvens:sub_hi
7784      8,	// MSA128WEvens:sub_lo -> FGRCC
7785      0,	// MSA128WEvens:sub_hi_then_sub_32
7786      0,	// MSA128WEvens:sub_32_sub_hi_then_sub_32
7787    },
7788    {	// ACC128
7789      36,	// ACC128:sub_32 -> LO32
7790      0,	// ACC128:sub_64
7791      0,	// ACC128:sub_dsp16_19
7792      0,	// ACC128:sub_dsp20
7793      0,	// ACC128:sub_dsp21
7794      0,	// ACC128:sub_dsp22
7795      0,	// ACC128:sub_dsp23
7796      62,	// ACC128:sub_hi -> HI64
7797      63,	// ACC128:sub_lo -> LO64
7798      35,	// ACC128:sub_hi_then_sub_32 -> HI32
7799      58,	// ACC128:sub_32_sub_hi_then_sub_32 -> ACC64
7800    },
7801  };
7802  assert(RC && "Missing regclass");
7803  if (!Idx) return RC;
7804  --Idx;
7805  assert(Idx < 11 && "Bad subreg");
7806  unsigned TV = Table[RC->getID()][Idx];
7807  return TV ? getRegClass(TV - 1) : nullptr;
7808}
7809
7810/// Get the weight in units of pressure for this register class.
7811const RegClassWeight &MipsGenRegisterInfo::
7812getRegClassWeight(const TargetRegisterClass *RC) const {
7813  static const RegClassWeight RCWeightTable[] = {
7814    {2, 64},  	// MSA128F16
7815    {0, 0},  	// CCR
7816    {0, 0},  	// COP0
7817    {0, 0},  	// COP2
7818    {0, 0},  	// COP3
7819    {1, 32},  	// DSPR
7820    {1, 32},  	// FGR32
7821    {1, 32},  	// FGRCC
7822    {1, 32},  	// GPR32
7823    {0, 0},  	// HWRegs
7824    {0, 0},  	// MSACtrl
7825    {1, 31},  	// GPR32NONZERO
7826    {1, 9},  	// CPU16RegsPlusSP
7827    {1, 8},  	// CPU16Regs
7828    {0, 0},  	// FCC
7829    {1, 8},  	// GPRMM16
7830    {1, 8},  	// GPRMM16MoveP
7831    {1, 8},  	// GPRMM16Zero
7832    {1, 7},  	// CPU16Regs_and_GPRMM16Zero
7833    {1, 7},  	// GPR32NONZERO_and_GPRMM16MoveP
7834    {1, 5},  	// GPRMM16MovePPairSecond
7835    {1, 4},  	// CPU16Regs_and_GPRMM16MoveP
7836    {1, 4},  	// GPRMM16MoveP_and_GPRMM16Zero
7837    {1, 4},  	// HI32DSP
7838    {1, 4},  	// LO32DSP
7839    {1, 3},  	// CPU16Regs_and_GPRMM16MovePPairSecond
7840    {1, 3},  	// GPRMM16MovePPairFirst
7841    {1, 3},  	// GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
7842    {1, 2},  	// GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
7843    {1, 1},  	// CPURAReg
7844    {1, 1},  	// CPUSPReg
7845    {1, 1},  	// DSPCC
7846    {1, 1},  	// GP32
7847    {1, 1},  	// GPR32ZERO
7848    {1, 1},  	// HI32
7849    {1, 1},  	// LO32
7850    {1, 1},  	// SP32
7851    {2, 64},  	// FGR64
7852    {1, 32},  	// GPR64
7853    {1, 31},  	// GPR64_with_sub_32_in_GPR32NONZERO
7854    {2, 32},  	// AFGR64
7855    {1, 9},  	// GPR64_with_sub_32_in_CPU16RegsPlusSP
7856    {1, 8},  	// GPR64_with_sub_32_in_CPU16Regs
7857    {1, 8},  	// GPR64_with_sub_32_in_GPRMM16MoveP
7858    {1, 8},  	// GPR64_with_sub_32_in_GPRMM16Zero
7859    {1, 7},  	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
7860    {1, 7},  	// GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
7861    {1, 5},  	// GPR64_with_sub_32_in_GPRMM16MovePPairSecond
7862    {2, 8},  	// ACC64DSP
7863    {1, 4},  	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
7864    {1, 4},  	// GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
7865    {1, 3},  	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond
7866    {1, 3},  	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst
7867    {1, 3},  	// GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
7868    {0, 0},  	// OCTEON_MPL
7869    {0, 0},  	// OCTEON_P
7870    {1, 2},  	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
7871    {2, 2},  	// ACC64
7872    {1, 1},  	// GP64
7873    {1, 1},  	// GPR64_with_sub_32_in_CPURAReg
7874    {1, 1},  	// GPR64_with_sub_32_in_GPR32ZERO
7875    {1, 1},  	// HI64
7876    {1, 1},  	// LO64
7877    {1, 1},  	// SP64
7878    {2, 64},  	// MSA128B
7879    {2, 64},  	// MSA128D
7880    {2, 64},  	// MSA128H
7881    {2, 64},  	// MSA128W
7882    {2, 32},  	// MSA128WEvens
7883    {2, 2},  	// ACC128
7884  };
7885  return RCWeightTable[RC->getID()];
7886}
7887
7888/// Get the weight in units of pressure for this register unit.
7889unsigned MipsGenRegisterInfo::
7890getRegUnitWeight(unsigned RegUnit) const {
7891  assert(RegUnit < 321 && "invalid register unit");
7892  // All register units have unit weight.
7893  return 1;
7894}
7895
7896
7897// Get the number of dimensions of register pressure.
7898unsigned MipsGenRegisterInfo::getNumRegPressureSets() const {
7899  return 20;
7900}
7901
7902// Get the name of this register unit pressure set.
7903const char *MipsGenRegisterInfo::
7904getRegPressureSetName(unsigned Idx) const {
7905  static const char *PressureNameTable[] = {
7906    "DSPCC",
7907    "GPR32ZERO",
7908    "GPR64_with_sub_32_in_CPURAReg",
7909    "HI32",
7910    "GPRMM16MovePPairFirst",
7911    "CPU16Regs_and_GPRMM16MoveP",
7912    "HI32DSP",
7913    "LO32DSP",
7914    "GPRMM16MovePPairSecond",
7915    "GPRMM16MoveP",
7916    "ACC64DSP",
7917    "CPU16Regs",
7918    "GPRMM16Zero_with_GPRMM16MovePPairSecond",
7919    "CPU16Regs_with_GPRMM16MovePPairSecond",
7920    "CPU16Regs_with_GPRMM16MoveP",
7921    "DSPR",
7922    "FGR32",
7923    "MSA128WEvens",
7924    "FGR32_with_MSA128WEvens",
7925    "MSA128F16",
7926  };
7927  return PressureNameTable[Idx];
7928}
7929
7930// Get the register unit pressure limit for this dimension.
7931// This limit must be adjusted dynamically for reserved registers.
7932unsigned MipsGenRegisterInfo::
7933getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
7934  static const uint8_t PressureLimitTable[] = {
7935    1,  	// 0: DSPCC
7936    1,  	// 1: GPR32ZERO
7937    1,  	// 2: GPR64_with_sub_32_in_CPURAReg
7938    2,  	// 3: HI32
7939    3,  	// 4: GPRMM16MovePPairFirst
7940    5,  	// 5: CPU16Regs_and_GPRMM16MoveP
7941    5,  	// 6: HI32DSP
7942    5,  	// 7: LO32DSP
7943    6,  	// 8: GPRMM16MovePPairSecond
7944    8,  	// 9: GPRMM16MoveP
7945    8,  	// 10: ACC64DSP
7946    10,  	// 11: CPU16Regs
7947    10,  	// 12: GPRMM16Zero_with_GPRMM16MovePPairSecond
7948    11,  	// 13: CPU16Regs_with_GPRMM16MovePPairSecond
7949    13,  	// 14: CPU16Regs_with_GPRMM16MoveP
7950    32,  	// 15: DSPR
7951    32,  	// 16: FGR32
7952    32,  	// 17: MSA128WEvens
7953    48,  	// 18: FGR32_with_MSA128WEvens
7954    64,  	// 19: MSA128F16
7955  };
7956  return PressureLimitTable[Idx];
7957}
7958
7959/// Table of pressure sets per register class or unit.
7960static const int RCSetsTable[] = {
7961  /* 0 */ 0, -1,
7962  /* 2 */ 6, 10, -1,
7963  /* 5 */ 3, 6, 7, 10, -1,
7964  /* 10 */ 2, 15, -1,
7965  /* 13 */ 8, 12, 13, 15, -1,
7966  /* 18 */ 9, 14, 15, -1,
7967  /* 22 */ 1, 5, 9, 11, 12, 14, 15, -1,
7968  /* 30 */ 5, 9, 11, 13, 14, 15, -1,
7969  /* 37 */ 4, 8, 11, 12, 13, 14, 15, -1,
7970  /* 45 */ 5, 9, 11, 12, 13, 14, 15, -1,
7971  /* 53 */ 16, 18, 19, -1,
7972  /* 57 */ 16, 17, 18, 19, -1,
7973};
7974
7975/// Get the dimensions of register pressure impacted by this register class.
7976/// Returns a -1 terminated array of pressure set IDs
7977const int *MipsGenRegisterInfo::
7978getRegClassPressureSets(const TargetRegisterClass *RC) const {
7979  static const uint8_t RCSetStartTable[] = {
7980    55,1,1,1,1,11,53,53,11,1,1,11,32,32,1,32,18,25,39,18,13,30,23,2,7,38,37,45,37,1,1,0,1,22,5,5,1,55,11,11,53,32,32,18,25,39,18,13,3,30,23,38,37,45,1,1,37,5,1,10,22,5,5,1,55,55,55,55,58,5,};
7981  return &RCSetsTable[RCSetStartTable[RC->getID()]];
7982}
7983
7984/// Get the dimensions of register pressure impacted by this register unit.
7985/// Returns a -1 terminated array of pressure set IDs
7986const int *MipsGenRegisterInfo::
7987getRegUnitPressureSets(unsigned RegUnit) const {
7988  assert(RegUnit < 321 && "invalid register unit");
7989  static const uint8_t RUSetStartTable[] = {
7990    11,0,1,1,1,1,1,1,1,1,1,11,11,1,1,1,1,1,1,1,1,1,10,32,22,37,37,37,38,5,5,7,2,7,2,7,2,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,11,11,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,30,45,18,18,18,13,13,11,11,11,11,11,11,11,11,11,11,11,45,45,};
7991  return &RCSetsTable[RUSetStartTable[RegUnit]];
7992}
7993
7994extern const MCRegisterDesc MipsRegDesc[];
7995extern const MCPhysReg MipsRegDiffLists[];
7996extern const LaneBitmask MipsLaneMaskLists[];
7997extern const char MipsRegStrings[];
7998extern const char MipsRegClassStrings[];
7999extern const MCPhysReg MipsRegUnitRoots[][2];
8000extern const uint16_t MipsSubRegIdxLists[];
8001extern const MCRegisterInfo::SubRegCoveredBits MipsSubRegIdxRanges[];
8002extern const uint16_t MipsRegEncodingTable[];
8003// Mips Dwarf<->LLVM register mappings.
8004extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0Dwarf2L[];
8005extern const unsigned MipsDwarfFlavour0Dwarf2LSize;
8006
8007extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0Dwarf2L[];
8008extern const unsigned MipsEHFlavour0Dwarf2LSize;
8009
8010extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0L2Dwarf[];
8011extern const unsigned MipsDwarfFlavour0L2DwarfSize;
8012
8013extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0L2Dwarf[];
8014extern const unsigned MipsEHFlavour0L2DwarfSize;
8015
8016MipsGenRegisterInfo::
8017MipsGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
8018      unsigned PC, unsigned HwMode)
8019  : TargetRegisterInfo(&MipsRegInfoDesc, RegisterClasses, RegisterClasses+70,
8020             SubRegIndexNameTable, SubRegIndexLaneMaskTable,
8021             LaneBitmask(0xFFFFFFFFFFFFFF80), RegClassInfos, HwMode) {
8022  InitMCRegisterInfo(MipsRegDesc, 442, RA, PC,
8023                     MipsMCRegisterClasses, 70,
8024                     MipsRegUnitRoots,
8025                     321,
8026                     MipsRegDiffLists,
8027                     MipsLaneMaskLists,
8028                     MipsRegStrings,
8029                     MipsRegClassStrings,
8030                     MipsSubRegIdxLists,
8031                     12,
8032                     MipsSubRegIdxRanges,
8033                     MipsRegEncodingTable);
8034
8035  switch (DwarfFlavour) {
8036  default:
8037    llvm_unreachable("Unknown DWARF flavour");
8038  case 0:
8039    mapDwarfRegsToLLVMRegs(MipsDwarfFlavour0Dwarf2L, MipsDwarfFlavour0Dwarf2LSize, false);
8040    break;
8041  }
8042  switch (EHFlavour) {
8043  default:
8044    llvm_unreachable("Unknown DWARF flavour");
8045  case 0:
8046    mapDwarfRegsToLLVMRegs(MipsEHFlavour0Dwarf2L, MipsEHFlavour0Dwarf2LSize, true);
8047    break;
8048  }
8049  switch (DwarfFlavour) {
8050  default:
8051    llvm_unreachable("Unknown DWARF flavour");
8052  case 0:
8053    mapLLVMRegsToDwarfRegs(MipsDwarfFlavour0L2Dwarf, MipsDwarfFlavour0L2DwarfSize, false);
8054    break;
8055  }
8056  switch (EHFlavour) {
8057  default:
8058    llvm_unreachable("Unknown DWARF flavour");
8059  case 0:
8060    mapLLVMRegsToDwarfRegs(MipsEHFlavour0L2Dwarf, MipsEHFlavour0L2DwarfSize, true);
8061    break;
8062  }
8063}
8064
8065static const MCPhysReg CSR_Interrupt_32_SaveList[] = { Mips::A3, Mips::A2, Mips::A1, Mips::A0, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, Mips::V1, Mips::V0, Mips::T9, Mips::T8, Mips::T7, Mips::T6, Mips::T5, Mips::T4, Mips::T3, Mips::T2, Mips::T1, Mips::T0, Mips::RA, Mips::FP, Mips::GP, Mips::AT, Mips::LO0, Mips::HI0, 0 };
8066static const uint32_t CSR_Interrupt_32_RegMask[] = { 0x07e80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x20000000, 0x00000000, 0x00000008, 0x07ffbfc0, 0x08000000, 0x00000000, 0x00000000, };
8067static const MCPhysReg CSR_Interrupt_32R6_SaveList[] = { Mips::A3, Mips::A2, Mips::A1, Mips::A0, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, Mips::V1, Mips::V0, Mips::T9, Mips::T8, Mips::T7, Mips::T6, Mips::T5, Mips::T4, Mips::T3, Mips::T2, Mips::T1, Mips::T0, Mips::RA, Mips::FP, Mips::GP, Mips::AT, 0 };
8068static const uint32_t CSR_Interrupt_32R6_RegMask[] = { 0x03e80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x07ffbfc0, 0x08000000, 0x00000000, 0x00000000, };
8069static const MCPhysReg CSR_Interrupt_64_SaveList[] = { Mips::A3_64, Mips::A2_64, Mips::A1_64, Mips::A0_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, Mips::T9_64, Mips::T8_64, Mips::T7_64, Mips::T6_64, Mips::T5_64, Mips::T4_64, Mips::T3_64, Mips::T2_64, Mips::T1_64, Mips::T0_64, Mips::V1_64, Mips::V0_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::AT_64, Mips::LO0_64, Mips::HI0_64, 0 };
8070static const uint32_t CSR_Interrupt_64_RegMask[] = { 0x47e80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x30000000, 0x00000000, 0x00000008, 0x07ffbfe0, 0xf8000000, 0x00000001, 0x03ffffe4, };
8071static const MCPhysReg CSR_Interrupt_64R6_SaveList[] = { Mips::A3_64, Mips::A2_64, Mips::A1_64, Mips::A0_64, Mips::V1_64, Mips::V0_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, Mips::T9_64, Mips::T8_64, Mips::T7_64, Mips::T6_64, Mips::T5_64, Mips::T4_64, Mips::T3_64, Mips::T2_64, Mips::T1_64, Mips::T0_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::AT_64, 0 };
8072static const uint32_t CSR_Interrupt_64R6_RegMask[] = { 0x43e80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x10000000, 0x00000000, 0x00000000, 0x07ffbfe0, 0xf8000000, 0x00000000, 0x03ffffc0, };
8073static const MCPhysReg CSR_Mips16RetHelper_SaveList[] = { Mips::V0, Mips::V1, Mips::FP, Mips::A3, Mips::A2, Mips::A1, Mips::A0, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10, 0 };
8074static const uint32_t CSR_Mips16RetHelper_RegMask[] = { 0x03e00100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x06003fc0, 0x08000000, 0x00000000, 0x00000000, };
8075static const MCPhysReg CSR_N32_SaveList[] = { Mips::D20_64, Mips::D22_64, Mips::D24_64, Mips::D26_64, Mips::D28_64, Mips::D30_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, 0 };
8076static const uint32_t CSR_N32_RegMask[] = { 0x00280300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0002aa80, 0x08000000, 0x15550000, 0x00000000, 0x00000000, 0x00003fe0, 0x08000000, 0xaaa00000, 0x00003fc0, };
8077static const MCPhysReg CSR_N64_SaveList[] = { Mips::D31_64, Mips::D30_64, Mips::D29_64, Mips::D28_64, Mips::D27_64, Mips::D26_64, Mips::D25_64, Mips::D24_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, 0 };
8078static const uint32_t CSR_N64_RegMask[] = { 0x00280300, 0x00000000, 0x00000000, 0x00000000, 0x00007800, 0x0007f800, 0x08000000, 0x1ff00000, 0x00000000, 0x00000000, 0x00003fe0, 0x08000000, 0xfe000000, 0x00003fc1, };
8079static const MCPhysReg CSR_O32_SaveList[] = { Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 };
8080static const uint32_t CSR_O32_RegMask[] = { 0x00280100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00003fc0, 0x08000000, 0x00000000, 0x00000000, };
8081static const MCPhysReg CSR_O32_FP64_SaveList[] = { Mips::D30_64, Mips::D28_64, Mips::D26_64, Mips::D24_64, Mips::D22_64, Mips::D20_64, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 };
8082static const uint32_t CSR_O32_FP64_RegMask[] = { 0x00280100, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0002aa80, 0x00000000, 0x05550000, 0x00000000, 0x00000000, 0x00003fc0, 0x08000000, 0xaaa00000, 0x00000000, };
8083static const MCPhysReg CSR_O32_FPXX_SaveList[] = { Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 };
8084static const uint32_t CSR_O32_FPXX_RegMask[] = { 0x00280100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00003fc0, 0x08000000, 0x00000000, 0x00000000, };
8085static const MCPhysReg CSR_SingleFloatOnly_SaveList[] = { Mips::F31, Mips::F30, Mips::F29, Mips::F28, Mips::F27, Mips::F26, Mips::F25, Mips::F24, Mips::F23, Mips::F22, Mips::F21, Mips::F20, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 };
8086static const uint32_t CSR_SingleFloatOnly_RegMask[] = { 0x00280100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00003fc0, 0x08000000, 0x00000000, 0x00000000, };
8087
8088
8089ArrayRef<const uint32_t *> MipsGenRegisterInfo::getRegMasks() const {
8090  static const uint32_t *const Masks[] = {
8091    CSR_Interrupt_32_RegMask,
8092    CSR_Interrupt_32R6_RegMask,
8093    CSR_Interrupt_64_RegMask,
8094    CSR_Interrupt_64R6_RegMask,
8095    CSR_Mips16RetHelper_RegMask,
8096    CSR_N32_RegMask,
8097    CSR_N64_RegMask,
8098    CSR_O32_RegMask,
8099    CSR_O32_FP64_RegMask,
8100    CSR_O32_FPXX_RegMask,
8101    CSR_SingleFloatOnly_RegMask,
8102  };
8103  return ArrayRef(Masks);
8104}
8105
8106bool MipsGenRegisterInfo::
8107isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
8108  return
8109      false;
8110}
8111
8112bool MipsGenRegisterInfo::
8113isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
8114  return
8115      false;
8116}
8117
8118bool MipsGenRegisterInfo::
8119isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
8120  return
8121      false;
8122}
8123
8124bool MipsGenRegisterInfo::
8125isConstantPhysReg(MCRegister PhysReg) const {
8126  return
8127      PhysReg == Mips::ZERO ||
8128      PhysReg == Mips::ZERO_64 ||
8129      false;
8130}
8131
8132ArrayRef<const char *> MipsGenRegisterInfo::getRegMaskNames() const {
8133  static const char *Names[] = {
8134    "CSR_Interrupt_32",
8135    "CSR_Interrupt_32R6",
8136    "CSR_Interrupt_64",
8137    "CSR_Interrupt_64R6",
8138    "CSR_Mips16RetHelper",
8139    "CSR_N32",
8140    "CSR_N64",
8141    "CSR_O32",
8142    "CSR_O32_FP64",
8143    "CSR_O32_FPXX",
8144    "CSR_SingleFloatOnly",
8145  };
8146  return ArrayRef(Names);
8147}
8148
8149const MipsFrameLowering *
8150MipsGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
8151  return static_cast<const MipsFrameLowering *>(
8152      MF.getSubtarget().getFrameLowering());
8153}
8154
8155} // end namespace llvm
8156
8157#endif // GET_REGINFO_TARGET_DESC
8158
8159