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1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|*                                                                            *|
3|* Calling Convention Implementation Fragment                                 *|
4|*                                                                            *|
5|* Automatically generated file, do not edit!                                 *|
6|*                                                                            *|
7\*===----------------------------------------------------------------------===*/
8
9#ifndef GET_CC_REGISTER_LISTS
10
11bool llvm::CC_PPC32_SVR4(unsigned ValNo, MVT ValVT,
12                         MVT LocVT, CCValAssign::LocInfo LocInfo,
13                         ISD::ArgFlagsTy ArgFlags, CCState &State);
14bool llvm::CC_PPC32_SVR4_ByVal(unsigned ValNo, MVT ValVT,
15                               MVT LocVT, CCValAssign::LocInfo LocInfo,
16                               ISD::ArgFlagsTy ArgFlags, CCState &State);
17static bool CC_PPC32_SVR4_Common(unsigned ValNo, MVT ValVT,
18                                 MVT LocVT, CCValAssign::LocInfo LocInfo,
19                                 ISD::ArgFlagsTy ArgFlags, CCState &State);
20bool llvm::CC_PPC32_SVR4_VarArg(unsigned ValNo, MVT ValVT,
21                                MVT LocVT, CCValAssign::LocInfo LocInfo,
22                                ISD::ArgFlagsTy ArgFlags, CCState &State);
23static bool CC_PPC64_AnyReg(unsigned ValNo, MVT ValVT,
24                            MVT LocVT, CCValAssign::LocInfo LocInfo,
25                            ISD::ArgFlagsTy ArgFlags, CCState &State);
26bool llvm::CC_PPC64_ELF_FIS(unsigned ValNo, MVT ValVT,
27                            MVT LocVT, CCValAssign::LocInfo LocInfo,
28                            ISD::ArgFlagsTy ArgFlags, CCState &State);
29bool llvm::RetCC_PPC(unsigned ValNo, MVT ValVT,
30                     MVT LocVT, CCValAssign::LocInfo LocInfo,
31                     ISD::ArgFlagsTy ArgFlags, CCState &State);
32static bool RetCC_PPC64_AnyReg(unsigned ValNo, MVT ValVT,
33                               MVT LocVT, CCValAssign::LocInfo LocInfo,
34                               ISD::ArgFlagsTy ArgFlags, CCState &State);
35bool llvm::RetCC_PPC64_ELF_FIS(unsigned ValNo, MVT ValVT,
36                               MVT LocVT, CCValAssign::LocInfo LocInfo,
37                               ISD::ArgFlagsTy ArgFlags, CCState &State);
38bool llvm::RetCC_PPC_Cold(unsigned ValNo, MVT ValVT,
39                          MVT LocVT, CCValAssign::LocInfo LocInfo,
40                          ISD::ArgFlagsTy ArgFlags, CCState &State);
41
42
43bool llvm::CC_PPC32_SVR4(unsigned ValNo, MVT ValVT,
44                         MVT LocVT, CCValAssign::LocInfo LocInfo,
45                         ISD::ArgFlagsTy ArgFlags, CCState &State) {
46
47  if (LocVT == MVT::v16i8 ||
48      LocVT == MVT::v8i16 ||
49      LocVT == MVT::v4i32 ||
50      LocVT == MVT::v2i64 ||
51      LocVT == MVT::v1i128 ||
52      LocVT == MVT::v4f32 ||
53      LocVT == MVT::v2f64) {
54    if (static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).hasAltivec()) {
55      static const MCPhysReg RegList1[] = {
56        PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
57      };
58      if (unsigned Reg = State.AllocateReg(RegList1)) {
59        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
60        return false;
61      }
62    }
63  }
64
65  if (LocVT == MVT::f128) {
66    if (static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).hasAltivec()) {
67      static const MCPhysReg RegList2[] = {
68        PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
69      };
70      if (unsigned Reg = State.AllocateReg(RegList2)) {
71        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
72        return false;
73      }
74    }
75  }
76
77  if (!CC_PPC32_SVR4_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
78    return false;
79
80  return true; // CC didn't match.
81}
82
83
84bool llvm::CC_PPC32_SVR4_ByVal(unsigned ValNo, MVT ValVT,
85                               MVT LocVT, CCValAssign::LocInfo LocInfo,
86                               ISD::ArgFlagsTy ArgFlags, CCState &State) {
87
88  if (ArgFlags.isByVal()) {
89    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, Align(4), ArgFlags);
90    return false;
91  }
92
93  if (CC_PPC32_SVR4_Custom_Dummy(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
94    return false;
95
96  return true; // CC didn't match.
97}
98
99
100static bool CC_PPC32_SVR4_Common(unsigned ValNo, MVT ValVT,
101                                 MVT LocVT, CCValAssign::LocInfo LocInfo,
102                                 ISD::ArgFlagsTy ArgFlags, CCState &State) {
103
104  if (LocVT == MVT::i1) {
105    LocVT = MVT::i32;
106    if (ArgFlags.isSExt())
107      LocInfo = CCValAssign::SExt;
108    else if (ArgFlags.isZExt())
109      LocInfo = CCValAssign::ZExt;
110    else
111      LocInfo = CCValAssign::AExt;
112  }
113
114  if (LocVT == MVT::i32) {
115    if (ArgFlags.isSplit()) {
116      if (static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).useSoftFloat()) {
117        if (!static_cast<PPCCCState *>(&State)->WasOriginalArgPPCF128(ValNo)) {
118          if (CC_PPC32_SVR4_Custom_AlignArgRegs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
119            return false;
120        }
121      }
122    }
123  }
124
125  if (LocVT == MVT::i32) {
126    if (ArgFlags.isSplit()) {
127      if (!static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).useSoftFloat()) {
128        if (CC_PPC32_SVR4_Custom_AlignArgRegs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
129          return false;
130      }
131    }
132  }
133
134  if (LocVT == MVT::f64) {
135    if (static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).hasSPE()) {
136      if (CC_PPC32_SVR4_Custom_AlignArgRegs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
137        return false;
138    }
139  }
140
141  if (ArgFlags.isSplit()) {
142    if (static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).useSoftFloat()) {
143      if (static_cast<PPCCCState *>(&State)->WasOriginalArgPPCF128(ValNo)) {
144        if (CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
145          return false;
146      }
147    }
148  }
149
150  if (ArgFlags.isNest()) {
151    if (unsigned Reg = State.AllocateReg(PPC::R11)) {
152      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
153      return false;
154    }
155  }
156
157  if (LocVT == MVT::i32) {
158    static const MCPhysReg RegList1[] = {
159      PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10
160    };
161    if (unsigned Reg = State.AllocateReg(RegList1)) {
162      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
163      return false;
164    }
165  }
166
167  if (LocVT == MVT::f64) {
168    if (ArgFlags.isSplit()) {
169      if (CC_PPC32_SVR4_Custom_AlignFPArgRegs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
170        return false;
171    }
172  }
173
174  if (LocVT == MVT::f32 ||
175      LocVT == MVT::f64) {
176    if (!static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).hasSPE()) {
177      static const MCPhysReg RegList2[] = {
178        PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8
179      };
180      if (unsigned Reg = State.AllocateReg(RegList2)) {
181        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
182        return false;
183      }
184    }
185  }
186
187  if (LocVT == MVT::f64) {
188    if (static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).hasSPE()) {
189      if (CC_PPC32_SPE_CustomSplitFP64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
190        return false;
191    }
192  }
193
194  if (LocVT == MVT::f32) {
195    if (static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).hasSPE()) {
196      static const MCPhysReg RegList3[] = {
197        PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10
198      };
199      if (unsigned Reg = State.AllocateReg(RegList3)) {
200        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
201        return false;
202      }
203    }
204  }
205
206  if (LocVT == MVT::i32) {
207    if (ArgFlags.isSplit()) {
208      unsigned Offset4 = State.AllocateStack(4, Align(8));
209      State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset4, LocVT, LocInfo));
210      return false;
211    }
212  }
213
214  if (LocVT == MVT::i32) {
215    unsigned Offset5 = State.AllocateStack(4, Align(4));
216    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset5, LocVT, LocInfo));
217    return false;
218  }
219
220  if (LocVT == MVT::f32) {
221    unsigned Offset6 = State.AllocateStack(4, Align(4));
222    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo));
223    return false;
224  }
225
226  if (LocVT == MVT::f64) {
227    unsigned Offset7 = State.AllocateStack(8, Align(8));
228    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset7, LocVT, LocInfo));
229    return false;
230  }
231
232  if (LocVT == MVT::v16i8 ||
233      LocVT == MVT::v8i16 ||
234      LocVT == MVT::v4i32 ||
235      LocVT == MVT::v4f32 ||
236      LocVT == MVT::v2f64 ||
237      LocVT == MVT::v2i64) {
238    unsigned Offset8 = State.AllocateStack(16, Align(16));
239    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset8, LocVT, LocInfo));
240    return false;
241  }
242
243  if (LocVT == MVT::f128) {
244    if (static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).hasAltivec()) {
245      unsigned Offset9 = State.AllocateStack(16, Align(16));
246      State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset9, LocVT, LocInfo));
247      return false;
248    }
249  }
250
251  return true; // CC didn't match.
252}
253
254
255bool llvm::CC_PPC32_SVR4_VarArg(unsigned ValNo, MVT ValVT,
256                                MVT LocVT, CCValAssign::LocInfo LocInfo,
257                                ISD::ArgFlagsTy ArgFlags, CCState &State) {
258
259  if (!CC_PPC32_SVR4_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
260    return false;
261
262  return true; // CC didn't match.
263}
264
265
266static bool CC_PPC64_AnyReg(unsigned ValNo, MVT ValVT,
267                            MVT LocVT, CCValAssign::LocInfo LocInfo,
268                            ISD::ArgFlagsTy ArgFlags, CCState &State) {
269
270  if (CC_PPC_AnyReg_Error(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
271    return false;
272
273  return true; // CC didn't match.
274}
275
276
277bool llvm::CC_PPC64_ELF_FIS(unsigned ValNo, MVT ValVT,
278                            MVT LocVT, CCValAssign::LocInfo LocInfo,
279                            ISD::ArgFlagsTy ArgFlags, CCState &State) {
280
281  if (State.getCallingConv() == CallingConv::AnyReg) {
282    if (!CC_PPC64_AnyReg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
283      return false;
284  }
285
286  if (LocVT == MVT::i1) {
287    LocVT = MVT::i64;
288    if (ArgFlags.isSExt())
289      LocInfo = CCValAssign::SExt;
290    else if (ArgFlags.isZExt())
291      LocInfo = CCValAssign::ZExt;
292    else
293      LocInfo = CCValAssign::AExt;
294  }
295
296  if (LocVT == MVT::i8) {
297    LocVT = MVT::i64;
298    if (ArgFlags.isSExt())
299      LocInfo = CCValAssign::SExt;
300    else if (ArgFlags.isZExt())
301      LocInfo = CCValAssign::ZExt;
302    else
303      LocInfo = CCValAssign::AExt;
304  }
305
306  if (LocVT == MVT::i16) {
307    LocVT = MVT::i64;
308    if (ArgFlags.isSExt())
309      LocInfo = CCValAssign::SExt;
310    else if (ArgFlags.isZExt())
311      LocInfo = CCValAssign::ZExt;
312    else
313      LocInfo = CCValAssign::AExt;
314  }
315
316  if (LocVT == MVT::i32) {
317    LocVT = MVT::i64;
318    if (ArgFlags.isSExt())
319      LocInfo = CCValAssign::SExt;
320    else if (ArgFlags.isZExt())
321      LocInfo = CCValAssign::ZExt;
322    else
323      LocInfo = CCValAssign::AExt;
324  }
325
326  if (LocVT == MVT::i64) {
327    static const MCPhysReg RegList1[] = {
328      PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10
329    };
330    if (unsigned Reg = State.AllocateReg(RegList1)) {
331      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
332      return false;
333    }
334  }
335
336  if (LocVT == MVT::f32 ||
337      LocVT == MVT::f64) {
338    static const MCPhysReg RegList2[] = {
339      PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8
340    };
341    if (unsigned Reg = State.AllocateReg(RegList2)) {
342      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
343      return false;
344    }
345  }
346
347  return true; // CC didn't match.
348}
349
350
351bool llvm::RetCC_PPC(unsigned ValNo, MVT ValVT,
352                     MVT LocVT, CCValAssign::LocInfo LocInfo,
353                     ISD::ArgFlagsTy ArgFlags, CCState &State) {
354
355  if (State.getCallingConv() == CallingConv::AnyReg) {
356    if (!RetCC_PPC64_AnyReg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
357      return false;
358  }
359
360  if (LocVT == MVT::i32 ||
361      LocVT == MVT::i1) {
362    if (static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).isPPC64()) {
363      LocVT = MVT::i64;
364      if (ArgFlags.isSExt())
365        LocInfo = CCValAssign::SExt;
366      else if (ArgFlags.isZExt())
367        LocInfo = CCValAssign::ZExt;
368      else
369        LocInfo = CCValAssign::AExt;
370    }
371  }
372
373  if (LocVT == MVT::i1) {
374    if (!static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).isPPC64()) {
375      LocVT = MVT::i32;
376      if (ArgFlags.isSExt())
377        LocInfo = CCValAssign::SExt;
378      else if (ArgFlags.isZExt())
379        LocInfo = CCValAssign::ZExt;
380      else
381        LocInfo = CCValAssign::AExt;
382    }
383  }
384
385  if (LocVT == MVT::i32) {
386    static const MCPhysReg RegList1[] = {
387      PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10
388    };
389    if (unsigned Reg = State.AllocateReg(RegList1)) {
390      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
391      return false;
392    }
393  }
394
395  if (LocVT == MVT::i64) {
396    static const MCPhysReg RegList2[] = {
397      PPC::X3, PPC::X4, PPC::X5, PPC::X6
398    };
399    if (unsigned Reg = State.AllocateReg(RegList2)) {
400      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
401      return false;
402    }
403  }
404
405  if (LocVT == MVT::i128) {
406    static const MCPhysReg RegList3[] = {
407      PPC::X3, PPC::X4, PPC::X5, PPC::X6
408    };
409    if (unsigned Reg = State.AllocateReg(RegList3)) {
410      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
411      return false;
412    }
413  }
414
415  if (!static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).hasSPE()) {
416    if (LocVT == MVT::f32) {
417      static const MCPhysReg RegList4[] = {
418        PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8
419      };
420      if (unsigned Reg = State.AllocateReg(RegList4)) {
421        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
422        return false;
423      }
424    }
425  }
426
427  if (!static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).hasSPE()) {
428    if (LocVT == MVT::f64) {
429      static const MCPhysReg RegList5[] = {
430        PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8
431      };
432      if (unsigned Reg = State.AllocateReg(RegList5)) {
433        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
434        return false;
435      }
436    }
437  }
438
439  if (static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).hasSPE()) {
440    if (LocVT == MVT::f32) {
441      static const MCPhysReg RegList6[] = {
442        PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10
443      };
444      if (unsigned Reg = State.AllocateReg(RegList6)) {
445        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
446        return false;
447      }
448    }
449  }
450
451  if (static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).hasSPE()) {
452    if (LocVT == MVT::f64) {
453      if (CC_PPC32_SPE_RetF64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
454        return false;
455    }
456  }
457
458  if (LocVT == MVT::f128) {
459    if (static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).hasAltivec()) {
460      static const MCPhysReg RegList7[] = {
461        PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9
462      };
463      if (unsigned Reg = State.AllocateReg(RegList7)) {
464        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
465        return false;
466      }
467    }
468  }
469
470  if (LocVT == MVT::v16i8 ||
471      LocVT == MVT::v8i16 ||
472      LocVT == MVT::v4i32 ||
473      LocVT == MVT::v2i64 ||
474      LocVT == MVT::v1i128 ||
475      LocVT == MVT::v4f32 ||
476      LocVT == MVT::v2f64) {
477    if (static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).hasAltivec()) {
478      static const MCPhysReg RegList8[] = {
479        PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9
480      };
481      if (unsigned Reg = State.AllocateReg(RegList8)) {
482        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
483        return false;
484      }
485    }
486  }
487
488  return true; // CC didn't match.
489}
490
491
492static bool RetCC_PPC64_AnyReg(unsigned ValNo, MVT ValVT,
493                               MVT LocVT, CCValAssign::LocInfo LocInfo,
494                               ISD::ArgFlagsTy ArgFlags, CCState &State) {
495
496  if (CC_PPC_AnyReg_Error(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
497    return false;
498
499  return true; // CC didn't match.
500}
501
502
503bool llvm::RetCC_PPC64_ELF_FIS(unsigned ValNo, MVT ValVT,
504                               MVT LocVT, CCValAssign::LocInfo LocInfo,
505                               ISD::ArgFlagsTy ArgFlags, CCState &State) {
506
507  if (State.getCallingConv() == CallingConv::AnyReg) {
508    if (!RetCC_PPC64_AnyReg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
509      return false;
510  }
511
512  if (LocVT == MVT::i1) {
513    LocVT = MVT::i64;
514    if (ArgFlags.isSExt())
515      LocInfo = CCValAssign::SExt;
516    else if (ArgFlags.isZExt())
517      LocInfo = CCValAssign::ZExt;
518    else
519      LocInfo = CCValAssign::AExt;
520  }
521
522  if (LocVT == MVT::i8) {
523    LocVT = MVT::i64;
524    if (ArgFlags.isSExt())
525      LocInfo = CCValAssign::SExt;
526    else if (ArgFlags.isZExt())
527      LocInfo = CCValAssign::ZExt;
528    else
529      LocInfo = CCValAssign::AExt;
530  }
531
532  if (LocVT == MVT::i16) {
533    LocVT = MVT::i64;
534    if (ArgFlags.isSExt())
535      LocInfo = CCValAssign::SExt;
536    else if (ArgFlags.isZExt())
537      LocInfo = CCValAssign::ZExt;
538    else
539      LocInfo = CCValAssign::AExt;
540  }
541
542  if (LocVT == MVT::i32) {
543    LocVT = MVT::i64;
544    if (ArgFlags.isSExt())
545      LocInfo = CCValAssign::SExt;
546    else if (ArgFlags.isZExt())
547      LocInfo = CCValAssign::ZExt;
548    else
549      LocInfo = CCValAssign::AExt;
550  }
551
552  if (LocVT == MVT::i64) {
553    static const MCPhysReg RegList1[] = {
554      PPC::X3, PPC::X4, PPC::X5, PPC::X6
555    };
556    if (unsigned Reg = State.AllocateReg(RegList1)) {
557      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
558      return false;
559    }
560  }
561
562  if (LocVT == MVT::i128) {
563    static const MCPhysReg RegList2[] = {
564      PPC::X3, PPC::X4, PPC::X5, PPC::X6
565    };
566    if (unsigned Reg = State.AllocateReg(RegList2)) {
567      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
568      return false;
569    }
570  }
571
572  if (LocVT == MVT::f32) {
573    static const MCPhysReg RegList3[] = {
574      PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8
575    };
576    if (unsigned Reg = State.AllocateReg(RegList3)) {
577      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
578      return false;
579    }
580  }
581
582  if (LocVT == MVT::f64) {
583    static const MCPhysReg RegList4[] = {
584      PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8
585    };
586    if (unsigned Reg = State.AllocateReg(RegList4)) {
587      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
588      return false;
589    }
590  }
591
592  if (LocVT == MVT::f128) {
593    if (static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).hasAltivec()) {
594      static const MCPhysReg RegList5[] = {
595        PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9
596      };
597      if (unsigned Reg = State.AllocateReg(RegList5)) {
598        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
599        return false;
600      }
601    }
602  }
603
604  if (LocVT == MVT::v16i8 ||
605      LocVT == MVT::v8i16 ||
606      LocVT == MVT::v4i32 ||
607      LocVT == MVT::v2i64 ||
608      LocVT == MVT::v1i128 ||
609      LocVT == MVT::v4f32 ||
610      LocVT == MVT::v2f64) {
611    if (static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).hasAltivec()) {
612      static const MCPhysReg RegList6[] = {
613        PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9
614      };
615      if (unsigned Reg = State.AllocateReg(RegList6)) {
616        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
617        return false;
618      }
619    }
620  }
621
622  return true; // CC didn't match.
623}
624
625
626bool llvm::RetCC_PPC_Cold(unsigned ValNo, MVT ValVT,
627                          MVT LocVT, CCValAssign::LocInfo LocInfo,
628                          ISD::ArgFlagsTy ArgFlags, CCState &State) {
629
630  if (LocVT == MVT::i32 ||
631      LocVT == MVT::i1) {
632    if (static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).isPPC64()) {
633      LocVT = MVT::i64;
634      if (ArgFlags.isSExt())
635        LocInfo = CCValAssign::SExt;
636      else if (ArgFlags.isZExt())
637        LocInfo = CCValAssign::ZExt;
638      else
639        LocInfo = CCValAssign::AExt;
640    }
641  }
642
643  if (LocVT == MVT::i1) {
644    if (!static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).isPPC64()) {
645      LocVT = MVT::i32;
646      if (ArgFlags.isSExt())
647        LocInfo = CCValAssign::SExt;
648      else if (ArgFlags.isZExt())
649        LocInfo = CCValAssign::ZExt;
650      else
651        LocInfo = CCValAssign::AExt;
652    }
653  }
654
655  if (LocVT == MVT::i32) {
656    if (unsigned Reg = State.AllocateReg(PPC::R3)) {
657      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
658      return false;
659    }
660  }
661
662  if (LocVT == MVT::i64) {
663    if (unsigned Reg = State.AllocateReg(PPC::X3)) {
664      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
665      return false;
666    }
667  }
668
669  if (LocVT == MVT::i128) {
670    if (unsigned Reg = State.AllocateReg(PPC::X3)) {
671      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
672      return false;
673    }
674  }
675
676  if (LocVT == MVT::f32) {
677    if (unsigned Reg = State.AllocateReg(PPC::F1)) {
678      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
679      return false;
680    }
681  }
682
683  if (LocVT == MVT::f64) {
684    if (unsigned Reg = State.AllocateReg(PPC::F1)) {
685      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
686      return false;
687    }
688  }
689
690  if (LocVT == MVT::f128) {
691    if (static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).hasAltivec()) {
692      if (unsigned Reg = State.AllocateReg(PPC::V2)) {
693        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
694        return false;
695      }
696    }
697  }
698
699  if (LocVT == MVT::v16i8 ||
700      LocVT == MVT::v8i16 ||
701      LocVT == MVT::v4i32 ||
702      LocVT == MVT::v2i64 ||
703      LocVT == MVT::v1i128 ||
704      LocVT == MVT::v4f32 ||
705      LocVT == MVT::v2f64) {
706    if (static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).hasAltivec()) {
707      if (unsigned Reg = State.AllocateReg(PPC::V2)) {
708        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
709        return false;
710      }
711    }
712  }
713
714  return true; // CC didn't match.
715}
716
717#else
718
719const MCRegister CC_PPC32_SVR4_ArgRegs[] = { PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9 };
720const MCRegister CC_PPC32_SVR4_ByVal_ArgRegs[] = { 0 };
721const MCRegister CC_PPC32_SVR4_Common_ArgRegs[] = { PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::R10, PPC::R11, PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9 };
722const MCRegister CC_PPC32_SVR4_VarArg_ArgRegs[] = { 0 };
723const MCRegister CC_PPC64_AnyReg_ArgRegs[] = { 0 };
724const MCRegister CC_PPC64_ELF_FIS_ArgRegs[] = { PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::X10, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9 };
725const MCRegister RetCC_PPC_ArgRegs[] = { PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::R10, PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::X3, PPC::X4, PPC::X5, PPC::X6 };
726const MCRegister RetCC_PPC64_AnyReg_ArgRegs[] = { 0 };
727const MCRegister RetCC_PPC64_ELF_FIS_ArgRegs[] = { PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::X3, PPC::X4, PPC::X5, PPC::X6 };
728const MCRegister RetCC_PPC_Cold_ArgRegs[] = { PPC::F1, PPC::R3, PPC::V2, PPC::X3 };
729
730#endif // CC_REGISTER_LIST
731