1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2|* *| 3|* "Fast" Instruction Selector for the PPC target *| 4|* *| 5|* Automatically generated file, do not edit! *| 6|* *| 7\*===----------------------------------------------------------------------===*/ 8 9 10// FastEmit Immediate Predicate functions. 11static bool Predicate_imm32SExt16(int64_t Imm) { 12 13 // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit 14 // sign extended field. Used by instructions like 'addi'. 15 return (int32_t)Imm == (short)Imm; 16 17} 18static bool Predicate_imm64SExt16(int64_t Imm) { 19 20 // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit 21 // sign extended field. Used by instructions like 'addi'. 22 return (int64_t)Imm == (short)Imm; 23 24} 25static bool Predicate_immSExt5NonZero(int64_t Imm) { 26 return Imm && isInt<5>(Imm); 27} 28static bool Predicate_i32immNonAllOneNonZero(int64_t Imm) { 29 return Imm && (Imm != -1); 30} 31 32 33// FastEmit functions for ISD::READCYCLECOUNTER. 34 35unsigned fastEmit_ISD_READCYCLECOUNTER_MVT_i64_(MVT RetVT) { 36 if (RetVT.SimpleTy != MVT::i64) 37 return 0; 38 return fastEmitInst_(PPC::MFTB8, &PPC::G8RCRegClass); 39} 40 41unsigned fastEmit_ISD_READCYCLECOUNTER_(MVT VT, MVT RetVT) { 42 switch (VT.SimpleTy) { 43 case MVT::i64: return fastEmit_ISD_READCYCLECOUNTER_MVT_i64_(RetVT); 44 default: return 0; 45 } 46} 47 48// FastEmit functions for PPCISD::MFFS. 49 50unsigned fastEmit_PPCISD_MFFS_MVT_f64_(MVT RetVT) { 51 if (RetVT.SimpleTy != MVT::f64) 52 return 0; 53 if ((Subtarget->hasFPU())) { 54 return fastEmitInst_(PPC::MFFS, &PPC::F8RCRegClass); 55 } 56 return 0; 57} 58 59unsigned fastEmit_PPCISD_MFFS_(MVT VT, MVT RetVT) { 60 switch (VT.SimpleTy) { 61 case MVT::f64: return fastEmit_PPCISD_MFFS_MVT_f64_(RetVT); 62 default: return 0; 63 } 64} 65 66// FastEmit functions for PPCISD::PPC32_GOT. 67 68unsigned fastEmit_PPCISD_PPC32_GOT_MVT_i32_(MVT RetVT) { 69 if (RetVT.SimpleTy != MVT::i32) 70 return 0; 71 return fastEmitInst_(PPC::PPC32GOT, &PPC::GPRCRegClass); 72} 73 74unsigned fastEmit_PPCISD_PPC32_GOT_(MVT VT, MVT RetVT) { 75 switch (VT.SimpleTy) { 76 case MVT::i32: return fastEmit_PPCISD_PPC32_GOT_MVT_i32_(RetVT); 77 default: return 0; 78 } 79} 80 81// Top-level FastEmit function. 82 83unsigned fastEmit_(MVT VT, MVT RetVT, unsigned Opcode) override { 84 switch (Opcode) { 85 case ISD::READCYCLECOUNTER: return fastEmit_ISD_READCYCLECOUNTER_(VT, RetVT); 86 case PPCISD::MFFS: return fastEmit_PPCISD_MFFS_(VT, RetVT); 87 case PPCISD::PPC32_GOT: return fastEmit_PPCISD_PPC32_GOT_(VT, RetVT); 88 default: return 0; 89 } 90} 91 92// FastEmit functions for ISD::ANY_EXTEND. 93 94unsigned fastEmit_ISD_ANY_EXTEND_MVT_i1_MVT_i32_r(unsigned Op0) { 95 if ((Subtarget->isISA3_1())) { 96 return fastEmitInst_r(PPC::SETBC, &PPC::GPRCRegClass, Op0); 97 } 98 return 0; 99} 100 101unsigned fastEmit_ISD_ANY_EXTEND_MVT_i1_MVT_i64_r(unsigned Op0) { 102 if ((Subtarget->isISA3_1())) { 103 return fastEmitInst_r(PPC::SETBC8, &PPC::G8RCRegClass, Op0); 104 } 105 return 0; 106} 107 108unsigned fastEmit_ISD_ANY_EXTEND_MVT_i1_r(MVT RetVT, unsigned Op0) { 109switch (RetVT.SimpleTy) { 110 case MVT::i32: return fastEmit_ISD_ANY_EXTEND_MVT_i1_MVT_i32_r(Op0); 111 case MVT::i64: return fastEmit_ISD_ANY_EXTEND_MVT_i1_MVT_i64_r(Op0); 112 default: return 0; 113} 114} 115 116unsigned fastEmit_ISD_ANY_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0) { 117 switch (VT.SimpleTy) { 118 case MVT::i1: return fastEmit_ISD_ANY_EXTEND_MVT_i1_r(RetVT, Op0); 119 default: return 0; 120 } 121} 122 123// FastEmit functions for ISD::BITCAST. 124 125unsigned fastEmit_ISD_BITCAST_MVT_i64_r(MVT RetVT, unsigned Op0) { 126 if (RetVT.SimpleTy != MVT::f64) 127 return 0; 128 if ((Subtarget->hasDirectMove()) && (Subtarget->hasVSX())) { 129 return fastEmitInst_r(PPC::MTVSRD, &PPC::VSFRCRegClass, Op0); 130 } 131 return 0; 132} 133 134unsigned fastEmit_ISD_BITCAST_MVT_f64_r(MVT RetVT, unsigned Op0) { 135 if (RetVT.SimpleTy != MVT::i64) 136 return 0; 137 if ((Subtarget->hasDirectMove()) && (Subtarget->hasVSX())) { 138 return fastEmitInst_r(PPC::MFVSRD, &PPC::G8RCRegClass, Op0); 139 } 140 return 0; 141} 142 143unsigned fastEmit_ISD_BITCAST_r(MVT VT, MVT RetVT, unsigned Op0) { 144 switch (VT.SimpleTy) { 145 case MVT::i64: return fastEmit_ISD_BITCAST_MVT_i64_r(RetVT, Op0); 146 case MVT::f64: return fastEmit_ISD_BITCAST_MVT_f64_r(RetVT, Op0); 147 default: return 0; 148 } 149} 150 151// FastEmit functions for ISD::BSWAP. 152 153unsigned fastEmit_ISD_BSWAP_MVT_i32_r(MVT RetVT, unsigned Op0) { 154 if (RetVT.SimpleTy != MVT::i32) 155 return 0; 156 if ((Subtarget->isISA3_1())) { 157 return fastEmitInst_r(PPC::BRW, &PPC::GPRCRegClass, Op0); 158 } 159 return 0; 160} 161 162unsigned fastEmit_ISD_BSWAP_MVT_i64_r(MVT RetVT, unsigned Op0) { 163 if (RetVT.SimpleTy != MVT::i64) 164 return 0; 165 if ((Subtarget->isISA3_1())) { 166 return fastEmitInst_r(PPC::BRD, &PPC::G8RCRegClass, Op0); 167 } 168 return 0; 169} 170 171unsigned fastEmit_ISD_BSWAP_MVT_v4i32_r(MVT RetVT, unsigned Op0) { 172 if (RetVT.SimpleTy != MVT::v4i32) 173 return 0; 174 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) { 175 return fastEmitInst_r(PPC::XXBRW, &PPC::VSRCRegClass, Op0); 176 } 177 return 0; 178} 179 180unsigned fastEmit_ISD_BSWAP_MVT_v2i64_r(MVT RetVT, unsigned Op0) { 181 if (RetVT.SimpleTy != MVT::v2i64) 182 return 0; 183 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) { 184 return fastEmitInst_r(PPC::XXBRD, &PPC::VSRCRegClass, Op0); 185 } 186 return 0; 187} 188 189unsigned fastEmit_ISD_BSWAP_r(MVT VT, MVT RetVT, unsigned Op0) { 190 switch (VT.SimpleTy) { 191 case MVT::i32: return fastEmit_ISD_BSWAP_MVT_i32_r(RetVT, Op0); 192 case MVT::i64: return fastEmit_ISD_BSWAP_MVT_i64_r(RetVT, Op0); 193 case MVT::v4i32: return fastEmit_ISD_BSWAP_MVT_v4i32_r(RetVT, Op0); 194 case MVT::v2i64: return fastEmit_ISD_BSWAP_MVT_v2i64_r(RetVT, Op0); 195 default: return 0; 196 } 197} 198 199// FastEmit functions for ISD::CTLZ. 200 201unsigned fastEmit_ISD_CTLZ_MVT_i32_r(MVT RetVT, unsigned Op0) { 202 if (RetVT.SimpleTy != MVT::i32) 203 return 0; 204 return fastEmitInst_r(PPC::CNTLZW, &PPC::GPRCRegClass, Op0); 205} 206 207unsigned fastEmit_ISD_CTLZ_MVT_i64_r(MVT RetVT, unsigned Op0) { 208 if (RetVT.SimpleTy != MVT::i64) 209 return 0; 210 return fastEmitInst_r(PPC::CNTLZD, &PPC::G8RCRegClass, Op0); 211} 212 213unsigned fastEmit_ISD_CTLZ_MVT_v16i8_r(MVT RetVT, unsigned Op0) { 214 if (RetVT.SimpleTy != MVT::v16i8) 215 return 0; 216 if ((Subtarget->hasP8Altivec())) { 217 return fastEmitInst_r(PPC::VCLZB, &PPC::VRRCRegClass, Op0); 218 } 219 return 0; 220} 221 222unsigned fastEmit_ISD_CTLZ_MVT_v8i16_r(MVT RetVT, unsigned Op0) { 223 if (RetVT.SimpleTy != MVT::v8i16) 224 return 0; 225 if ((Subtarget->hasP8Altivec())) { 226 return fastEmitInst_r(PPC::VCLZH, &PPC::VRRCRegClass, Op0); 227 } 228 return 0; 229} 230 231unsigned fastEmit_ISD_CTLZ_MVT_v4i32_r(MVT RetVT, unsigned Op0) { 232 if (RetVT.SimpleTy != MVT::v4i32) 233 return 0; 234 if ((Subtarget->hasP8Altivec())) { 235 return fastEmitInst_r(PPC::VCLZW, &PPC::VRRCRegClass, Op0); 236 } 237 return 0; 238} 239 240unsigned fastEmit_ISD_CTLZ_MVT_v2i64_r(MVT RetVT, unsigned Op0) { 241 if (RetVT.SimpleTy != MVT::v2i64) 242 return 0; 243 if ((Subtarget->hasP8Altivec())) { 244 return fastEmitInst_r(PPC::VCLZD, &PPC::VRRCRegClass, Op0); 245 } 246 return 0; 247} 248 249unsigned fastEmit_ISD_CTLZ_r(MVT VT, MVT RetVT, unsigned Op0) { 250 switch (VT.SimpleTy) { 251 case MVT::i32: return fastEmit_ISD_CTLZ_MVT_i32_r(RetVT, Op0); 252 case MVT::i64: return fastEmit_ISD_CTLZ_MVT_i64_r(RetVT, Op0); 253 case MVT::v16i8: return fastEmit_ISD_CTLZ_MVT_v16i8_r(RetVT, Op0); 254 case MVT::v8i16: return fastEmit_ISD_CTLZ_MVT_v8i16_r(RetVT, Op0); 255 case MVT::v4i32: return fastEmit_ISD_CTLZ_MVT_v4i32_r(RetVT, Op0); 256 case MVT::v2i64: return fastEmit_ISD_CTLZ_MVT_v2i64_r(RetVT, Op0); 257 default: return 0; 258 } 259} 260 261// FastEmit functions for ISD::CTPOP. 262 263unsigned fastEmit_ISD_CTPOP_MVT_i32_r(MVT RetVT, unsigned Op0) { 264 if (RetVT.SimpleTy != MVT::i32) 265 return 0; 266 return fastEmitInst_r(PPC::POPCNTW, &PPC::GPRCRegClass, Op0); 267} 268 269unsigned fastEmit_ISD_CTPOP_MVT_i64_r(MVT RetVT, unsigned Op0) { 270 if (RetVT.SimpleTy != MVT::i64) 271 return 0; 272 return fastEmitInst_r(PPC::POPCNTD, &PPC::G8RCRegClass, Op0); 273} 274 275unsigned fastEmit_ISD_CTPOP_MVT_v16i8_r(MVT RetVT, unsigned Op0) { 276 if (RetVT.SimpleTy != MVT::v16i8) 277 return 0; 278 if ((Subtarget->hasP8Altivec())) { 279 return fastEmitInst_r(PPC::VPOPCNTB, &PPC::VRRCRegClass, Op0); 280 } 281 return 0; 282} 283 284unsigned fastEmit_ISD_CTPOP_MVT_v8i16_r(MVT RetVT, unsigned Op0) { 285 if (RetVT.SimpleTy != MVT::v8i16) 286 return 0; 287 if ((Subtarget->hasP8Altivec())) { 288 return fastEmitInst_r(PPC::VPOPCNTH, &PPC::VRRCRegClass, Op0); 289 } 290 return 0; 291} 292 293unsigned fastEmit_ISD_CTPOP_MVT_v4i32_r(MVT RetVT, unsigned Op0) { 294 if (RetVT.SimpleTy != MVT::v4i32) 295 return 0; 296 if ((Subtarget->hasP8Altivec())) { 297 return fastEmitInst_r(PPC::VPOPCNTW, &PPC::VRRCRegClass, Op0); 298 } 299 return 0; 300} 301 302unsigned fastEmit_ISD_CTPOP_MVT_v2i64_r(MVT RetVT, unsigned Op0) { 303 if (RetVT.SimpleTy != MVT::v2i64) 304 return 0; 305 if ((Subtarget->hasP8Altivec())) { 306 return fastEmitInst_r(PPC::VPOPCNTD, &PPC::VRRCRegClass, Op0); 307 } 308 return 0; 309} 310 311unsigned fastEmit_ISD_CTPOP_r(MVT VT, MVT RetVT, unsigned Op0) { 312 switch (VT.SimpleTy) { 313 case MVT::i32: return fastEmit_ISD_CTPOP_MVT_i32_r(RetVT, Op0); 314 case MVT::i64: return fastEmit_ISD_CTPOP_MVT_i64_r(RetVT, Op0); 315 case MVT::v16i8: return fastEmit_ISD_CTPOP_MVT_v16i8_r(RetVT, Op0); 316 case MVT::v8i16: return fastEmit_ISD_CTPOP_MVT_v8i16_r(RetVT, Op0); 317 case MVT::v4i32: return fastEmit_ISD_CTPOP_MVT_v4i32_r(RetVT, Op0); 318 case MVT::v2i64: return fastEmit_ISD_CTPOP_MVT_v2i64_r(RetVT, Op0); 319 default: return 0; 320 } 321} 322 323// FastEmit functions for ISD::CTTZ. 324 325unsigned fastEmit_ISD_CTTZ_MVT_i32_r(MVT RetVT, unsigned Op0) { 326 if (RetVT.SimpleTy != MVT::i32) 327 return 0; 328 if ((Subtarget->isISA3_0())) { 329 return fastEmitInst_r(PPC::CNTTZW, &PPC::GPRCRegClass, Op0); 330 } 331 return 0; 332} 333 334unsigned fastEmit_ISD_CTTZ_MVT_i64_r(MVT RetVT, unsigned Op0) { 335 if (RetVT.SimpleTy != MVT::i64) 336 return 0; 337 if ((Subtarget->isISA3_0())) { 338 return fastEmitInst_r(PPC::CNTTZD, &PPC::G8RCRegClass, Op0); 339 } 340 return 0; 341} 342 343unsigned fastEmit_ISD_CTTZ_MVT_v16i8_r(MVT RetVT, unsigned Op0) { 344 if (RetVT.SimpleTy != MVT::v16i8) 345 return 0; 346 if ((Subtarget->hasP9Altivec())) { 347 return fastEmitInst_r(PPC::VCTZB, &PPC::VRRCRegClass, Op0); 348 } 349 return 0; 350} 351 352unsigned fastEmit_ISD_CTTZ_MVT_v8i16_r(MVT RetVT, unsigned Op0) { 353 if (RetVT.SimpleTy != MVT::v8i16) 354 return 0; 355 if ((Subtarget->hasP9Altivec())) { 356 return fastEmitInst_r(PPC::VCTZH, &PPC::VRRCRegClass, Op0); 357 } 358 return 0; 359} 360 361unsigned fastEmit_ISD_CTTZ_MVT_v4i32_r(MVT RetVT, unsigned Op0) { 362 if (RetVT.SimpleTy != MVT::v4i32) 363 return 0; 364 if ((Subtarget->hasP9Altivec())) { 365 return fastEmitInst_r(PPC::VCTZW, &PPC::VRRCRegClass, Op0); 366 } 367 return 0; 368} 369 370unsigned fastEmit_ISD_CTTZ_MVT_v2i64_r(MVT RetVT, unsigned Op0) { 371 if (RetVT.SimpleTy != MVT::v2i64) 372 return 0; 373 if ((Subtarget->hasP9Altivec())) { 374 return fastEmitInst_r(PPC::VCTZD, &PPC::VRRCRegClass, Op0); 375 } 376 return 0; 377} 378 379unsigned fastEmit_ISD_CTTZ_r(MVT VT, MVT RetVT, unsigned Op0) { 380 switch (VT.SimpleTy) { 381 case MVT::i32: return fastEmit_ISD_CTTZ_MVT_i32_r(RetVT, Op0); 382 case MVT::i64: return fastEmit_ISD_CTTZ_MVT_i64_r(RetVT, Op0); 383 case MVT::v16i8: return fastEmit_ISD_CTTZ_MVT_v16i8_r(RetVT, Op0); 384 case MVT::v8i16: return fastEmit_ISD_CTTZ_MVT_v8i16_r(RetVT, Op0); 385 case MVT::v4i32: return fastEmit_ISD_CTTZ_MVT_v4i32_r(RetVT, Op0); 386 case MVT::v2i64: return fastEmit_ISD_CTTZ_MVT_v2i64_r(RetVT, Op0); 387 default: return 0; 388 } 389} 390 391// FastEmit functions for ISD::FABS. 392 393unsigned fastEmit_ISD_FABS_MVT_f32_r(MVT RetVT, unsigned Op0) { 394 if (RetVT.SimpleTy != MVT::f32) 395 return 0; 396 if ((Subtarget->hasSPE())) { 397 return fastEmitInst_r(PPC::EFSABS, &PPC::GPRCRegClass, Op0); 398 } 399 if ((Subtarget->hasFPU())) { 400 return fastEmitInst_r(PPC::FABSS, &PPC::F4RCRegClass, Op0); 401 } 402 return 0; 403} 404 405unsigned fastEmit_ISD_FABS_MVT_f64_r(MVT RetVT, unsigned Op0) { 406 if (RetVT.SimpleTy != MVT::f64) 407 return 0; 408 if ((Subtarget->hasVSX())) { 409 return fastEmitInst_r(PPC::XSABSDP, &PPC::VSFRCRegClass, Op0); 410 } 411 if ((Subtarget->hasSPE())) { 412 return fastEmitInst_r(PPC::EFDABS, &PPC::SPERCRegClass, Op0); 413 } 414 if ((Subtarget->hasFPU())) { 415 return fastEmitInst_r(PPC::FABSD, &PPC::F8RCRegClass, Op0); 416 } 417 return 0; 418} 419 420unsigned fastEmit_ISD_FABS_MVT_f128_r(MVT RetVT, unsigned Op0) { 421 if (RetVT.SimpleTy != MVT::f128) 422 return 0; 423 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) { 424 return fastEmitInst_r(PPC::XSABSQP, &PPC::VRRCRegClass, Op0); 425 } 426 return 0; 427} 428 429unsigned fastEmit_ISD_FABS_MVT_v4f32_r(MVT RetVT, unsigned Op0) { 430 if (RetVT.SimpleTy != MVT::v4f32) 431 return 0; 432 if ((Subtarget->hasVSX())) { 433 return fastEmitInst_r(PPC::XVABSSP, &PPC::VSRCRegClass, Op0); 434 } 435 return 0; 436} 437 438unsigned fastEmit_ISD_FABS_MVT_v2f64_r(MVT RetVT, unsigned Op0) { 439 if (RetVT.SimpleTy != MVT::v2f64) 440 return 0; 441 if ((Subtarget->hasVSX())) { 442 return fastEmitInst_r(PPC::XVABSDP, &PPC::VSRCRegClass, Op0); 443 } 444 return 0; 445} 446 447unsigned fastEmit_ISD_FABS_r(MVT VT, MVT RetVT, unsigned Op0) { 448 switch (VT.SimpleTy) { 449 case MVT::f32: return fastEmit_ISD_FABS_MVT_f32_r(RetVT, Op0); 450 case MVT::f64: return fastEmit_ISD_FABS_MVT_f64_r(RetVT, Op0); 451 case MVT::f128: return fastEmit_ISD_FABS_MVT_f128_r(RetVT, Op0); 452 case MVT::v4f32: return fastEmit_ISD_FABS_MVT_v4f32_r(RetVT, Op0); 453 case MVT::v2f64: return fastEmit_ISD_FABS_MVT_v2f64_r(RetVT, Op0); 454 default: return 0; 455 } 456} 457 458// FastEmit functions for ISD::FCEIL. 459 460unsigned fastEmit_ISD_FCEIL_MVT_f32_r(MVT RetVT, unsigned Op0) { 461 if (RetVT.SimpleTy != MVT::f32) 462 return 0; 463 if ((Subtarget->hasFPU())) { 464 return fastEmitInst_r(PPC::FRIPS, &PPC::F4RCRegClass, Op0); 465 } 466 return 0; 467} 468 469unsigned fastEmit_ISD_FCEIL_MVT_f64_r(MVT RetVT, unsigned Op0) { 470 if (RetVT.SimpleTy != MVT::f64) 471 return 0; 472 if ((Subtarget->hasVSX())) { 473 return fastEmitInst_r(PPC::XSRDPIP, &PPC::VSFRCRegClass, Op0); 474 } 475 if ((Subtarget->hasFPU())) { 476 return fastEmitInst_r(PPC::FRIPD, &PPC::F8RCRegClass, Op0); 477 } 478 return 0; 479} 480 481unsigned fastEmit_ISD_FCEIL_MVT_v4f32_r(MVT RetVT, unsigned Op0) { 482 if (RetVT.SimpleTy != MVT::v4f32) 483 return 0; 484 if ((Subtarget->hasVSX())) { 485 return fastEmitInst_r(PPC::XVRSPIP, &PPC::VSRCRegClass, Op0); 486 } 487 if ((Subtarget->hasAltivec())) { 488 return fastEmitInst_r(PPC::VRFIP, &PPC::VRRCRegClass, Op0); 489 } 490 return 0; 491} 492 493unsigned fastEmit_ISD_FCEIL_MVT_v2f64_r(MVT RetVT, unsigned Op0) { 494 if (RetVT.SimpleTy != MVT::v2f64) 495 return 0; 496 if ((Subtarget->hasVSX())) { 497 return fastEmitInst_r(PPC::XVRDPIP, &PPC::VSRCRegClass, Op0); 498 } 499 return 0; 500} 501 502unsigned fastEmit_ISD_FCEIL_r(MVT VT, MVT RetVT, unsigned Op0) { 503 switch (VT.SimpleTy) { 504 case MVT::f32: return fastEmit_ISD_FCEIL_MVT_f32_r(RetVT, Op0); 505 case MVT::f64: return fastEmit_ISD_FCEIL_MVT_f64_r(RetVT, Op0); 506 case MVT::v4f32: return fastEmit_ISD_FCEIL_MVT_v4f32_r(RetVT, Op0); 507 case MVT::v2f64: return fastEmit_ISD_FCEIL_MVT_v2f64_r(RetVT, Op0); 508 default: return 0; 509 } 510} 511 512// FastEmit functions for ISD::FFLOOR. 513 514unsigned fastEmit_ISD_FFLOOR_MVT_f32_r(MVT RetVT, unsigned Op0) { 515 if (RetVT.SimpleTy != MVT::f32) 516 return 0; 517 if ((Subtarget->hasFPU())) { 518 return fastEmitInst_r(PPC::FRIMS, &PPC::F4RCRegClass, Op0); 519 } 520 return 0; 521} 522 523unsigned fastEmit_ISD_FFLOOR_MVT_f64_r(MVT RetVT, unsigned Op0) { 524 if (RetVT.SimpleTy != MVT::f64) 525 return 0; 526 if ((Subtarget->hasVSX())) { 527 return fastEmitInst_r(PPC::XSRDPIM, &PPC::VSFRCRegClass, Op0); 528 } 529 if ((Subtarget->hasFPU())) { 530 return fastEmitInst_r(PPC::FRIMD, &PPC::F8RCRegClass, Op0); 531 } 532 return 0; 533} 534 535unsigned fastEmit_ISD_FFLOOR_MVT_v4f32_r(MVT RetVT, unsigned Op0) { 536 if (RetVT.SimpleTy != MVT::v4f32) 537 return 0; 538 if ((Subtarget->hasVSX())) { 539 return fastEmitInst_r(PPC::XVRSPIM, &PPC::VSRCRegClass, Op0); 540 } 541 if ((Subtarget->hasAltivec())) { 542 return fastEmitInst_r(PPC::VRFIM, &PPC::VRRCRegClass, Op0); 543 } 544 return 0; 545} 546 547unsigned fastEmit_ISD_FFLOOR_MVT_v2f64_r(MVT RetVT, unsigned Op0) { 548 if (RetVT.SimpleTy != MVT::v2f64) 549 return 0; 550 if ((Subtarget->hasVSX())) { 551 return fastEmitInst_r(PPC::XVRDPIM, &PPC::VSRCRegClass, Op0); 552 } 553 return 0; 554} 555 556unsigned fastEmit_ISD_FFLOOR_r(MVT VT, MVT RetVT, unsigned Op0) { 557 switch (VT.SimpleTy) { 558 case MVT::f32: return fastEmit_ISD_FFLOOR_MVT_f32_r(RetVT, Op0); 559 case MVT::f64: return fastEmit_ISD_FFLOOR_MVT_f64_r(RetVT, Op0); 560 case MVT::v4f32: return fastEmit_ISD_FFLOOR_MVT_v4f32_r(RetVT, Op0); 561 case MVT::v2f64: return fastEmit_ISD_FFLOOR_MVT_v2f64_r(RetVT, Op0); 562 default: return 0; 563 } 564} 565 566// FastEmit functions for ISD::FNEARBYINT. 567 568unsigned fastEmit_ISD_FNEARBYINT_MVT_f64_r(MVT RetVT, unsigned Op0) { 569 if (RetVT.SimpleTy != MVT::f64) 570 return 0; 571 if ((Subtarget->hasVSX())) { 572 return fastEmitInst_r(PPC::XSRDPIC, &PPC::VSFRCRegClass, Op0); 573 } 574 return 0; 575} 576 577unsigned fastEmit_ISD_FNEARBYINT_MVT_v4f32_r(MVT RetVT, unsigned Op0) { 578 if (RetVT.SimpleTy != MVT::v4f32) 579 return 0; 580 if ((Subtarget->hasVSX())) { 581 return fastEmitInst_r(PPC::XVRSPIC, &PPC::VSRCRegClass, Op0); 582 } 583 if ((Subtarget->hasAltivec())) { 584 return fastEmitInst_r(PPC::VRFIN, &PPC::VRRCRegClass, Op0); 585 } 586 return 0; 587} 588 589unsigned fastEmit_ISD_FNEARBYINT_MVT_v2f64_r(MVT RetVT, unsigned Op0) { 590 if (RetVT.SimpleTy != MVT::v2f64) 591 return 0; 592 if ((Subtarget->hasVSX())) { 593 return fastEmitInst_r(PPC::XVRDPIC, &PPC::VSRCRegClass, Op0); 594 } 595 return 0; 596} 597 598unsigned fastEmit_ISD_FNEARBYINT_r(MVT VT, MVT RetVT, unsigned Op0) { 599 switch (VT.SimpleTy) { 600 case MVT::f64: return fastEmit_ISD_FNEARBYINT_MVT_f64_r(RetVT, Op0); 601 case MVT::v4f32: return fastEmit_ISD_FNEARBYINT_MVT_v4f32_r(RetVT, Op0); 602 case MVT::v2f64: return fastEmit_ISD_FNEARBYINT_MVT_v2f64_r(RetVT, Op0); 603 default: return 0; 604 } 605} 606 607// FastEmit functions for ISD::FNEG. 608 609unsigned fastEmit_ISD_FNEG_MVT_f32_r(MVT RetVT, unsigned Op0) { 610 if (RetVT.SimpleTy != MVT::f32) 611 return 0; 612 if ((Subtarget->hasSPE())) { 613 return fastEmitInst_r(PPC::EFSNEG, &PPC::GPRCRegClass, Op0); 614 } 615 if ((Subtarget->hasFPU())) { 616 return fastEmitInst_r(PPC::FNEGS, &PPC::F4RCRegClass, Op0); 617 } 618 return 0; 619} 620 621unsigned fastEmit_ISD_FNEG_MVT_f64_r(MVT RetVT, unsigned Op0) { 622 if (RetVT.SimpleTy != MVT::f64) 623 return 0; 624 if ((Subtarget->hasVSX())) { 625 return fastEmitInst_r(PPC::XSNEGDP, &PPC::VSFRCRegClass, Op0); 626 } 627 if ((Subtarget->hasSPE())) { 628 return fastEmitInst_r(PPC::EFDNEG, &PPC::SPERCRegClass, Op0); 629 } 630 if ((Subtarget->hasFPU())) { 631 return fastEmitInst_r(PPC::FNEGD, &PPC::F8RCRegClass, Op0); 632 } 633 return 0; 634} 635 636unsigned fastEmit_ISD_FNEG_MVT_f128_r(MVT RetVT, unsigned Op0) { 637 if (RetVT.SimpleTy != MVT::f128) 638 return 0; 639 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) { 640 return fastEmitInst_r(PPC::XSNEGQP, &PPC::VRRCRegClass, Op0); 641 } 642 return 0; 643} 644 645unsigned fastEmit_ISD_FNEG_MVT_v4f32_r(MVT RetVT, unsigned Op0) { 646 if (RetVT.SimpleTy != MVT::v4f32) 647 return 0; 648 if ((Subtarget->hasVSX())) { 649 return fastEmitInst_r(PPC::XVNEGSP, &PPC::VSRCRegClass, Op0); 650 } 651 return 0; 652} 653 654unsigned fastEmit_ISD_FNEG_MVT_v2f64_r(MVT RetVT, unsigned Op0) { 655 if (RetVT.SimpleTy != MVT::v2f64) 656 return 0; 657 if ((Subtarget->hasVSX())) { 658 return fastEmitInst_r(PPC::XVNEGDP, &PPC::VSRCRegClass, Op0); 659 } 660 return 0; 661} 662 663unsigned fastEmit_ISD_FNEG_r(MVT VT, MVT RetVT, unsigned Op0) { 664 switch (VT.SimpleTy) { 665 case MVT::f32: return fastEmit_ISD_FNEG_MVT_f32_r(RetVT, Op0); 666 case MVT::f64: return fastEmit_ISD_FNEG_MVT_f64_r(RetVT, Op0); 667 case MVT::f128: return fastEmit_ISD_FNEG_MVT_f128_r(RetVT, Op0); 668 case MVT::v4f32: return fastEmit_ISD_FNEG_MVT_v4f32_r(RetVT, Op0); 669 case MVT::v2f64: return fastEmit_ISD_FNEG_MVT_v2f64_r(RetVT, Op0); 670 default: return 0; 671 } 672} 673 674// FastEmit functions for ISD::FP_EXTEND. 675 676unsigned fastEmit_ISD_FP_EXTEND_MVT_f32_r(MVT RetVT, unsigned Op0) { 677 if (RetVT.SimpleTy != MVT::f64) 678 return 0; 679 if ((Subtarget->hasSPE())) { 680 return fastEmitInst_r(PPC::EFDCFS, &PPC::SPERCRegClass, Op0); 681 } 682 return 0; 683} 684 685unsigned fastEmit_ISD_FP_EXTEND_MVT_f64_r(MVT RetVT, unsigned Op0) { 686 if (RetVT.SimpleTy != MVT::f128) 687 return 0; 688 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) { 689 return fastEmitInst_r(PPC::XSCVDPQP, &PPC::VRRCRegClass, Op0); 690 } 691 return 0; 692} 693 694unsigned fastEmit_ISD_FP_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0) { 695 switch (VT.SimpleTy) { 696 case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f32_r(RetVT, Op0); 697 case MVT::f64: return fastEmit_ISD_FP_EXTEND_MVT_f64_r(RetVT, Op0); 698 default: return 0; 699 } 700} 701 702// FastEmit functions for ISD::FP_ROUND. 703 704unsigned fastEmit_ISD_FP_ROUND_MVT_f64_r(MVT RetVT, unsigned Op0) { 705 if (RetVT.SimpleTy != MVT::f32) 706 return 0; 707 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) { 708 return fastEmitInst_r(PPC::XSRSP, &PPC::VSSRCRegClass, Op0); 709 } 710 if ((Subtarget->hasSPE())) { 711 return fastEmitInst_r(PPC::EFSCFD, &PPC::GPRCRegClass, Op0); 712 } 713 if ((Subtarget->hasFPU())) { 714 return fastEmitInst_r(PPC::FRSP, &PPC::F4RCRegClass, Op0); 715 } 716 return 0; 717} 718 719unsigned fastEmit_ISD_FP_ROUND_MVT_f128_r(MVT RetVT, unsigned Op0) { 720 if (RetVT.SimpleTy != MVT::f64) 721 return 0; 722 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) { 723 return fastEmitInst_r(PPC::XSCVQPDP, &PPC::VFRCRegClass, Op0); 724 } 725 return 0; 726} 727 728unsigned fastEmit_ISD_FP_ROUND_r(MVT VT, MVT RetVT, unsigned Op0) { 729 switch (VT.SimpleTy) { 730 case MVT::f64: return fastEmit_ISD_FP_ROUND_MVT_f64_r(RetVT, Op0); 731 case MVT::f128: return fastEmit_ISD_FP_ROUND_MVT_f128_r(RetVT, Op0); 732 default: return 0; 733 } 734} 735 736// FastEmit functions for ISD::FP_TO_SINT. 737 738unsigned fastEmit_ISD_FP_TO_SINT_MVT_f32_r(MVT RetVT, unsigned Op0) { 739 if (RetVT.SimpleTy != MVT::i32) 740 return 0; 741 if ((Subtarget->hasSPE())) { 742 return fastEmitInst_r(PPC::EFSCTSIZ, &PPC::GPRCRegClass, Op0); 743 } 744 return 0; 745} 746 747unsigned fastEmit_ISD_FP_TO_SINT_MVT_f64_r(MVT RetVT, unsigned Op0) { 748 if (RetVT.SimpleTy != MVT::i32) 749 return 0; 750 if ((Subtarget->hasSPE())) { 751 return fastEmitInst_r(PPC::EFDCTSIZ, &PPC::GPRCRegClass, Op0); 752 } 753 return 0; 754} 755 756unsigned fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(MVT RetVT, unsigned Op0) { 757 if (RetVT.SimpleTy != MVT::v4i32) 758 return 0; 759 if ((Subtarget->hasVSX())) { 760 return fastEmitInst_r(PPC::XVCVSPSXWS, &PPC::VSRCRegClass, Op0); 761 } 762 if ((Subtarget->hasAltivec())) { 763 return fastEmitInst_r(PPC::VCTSXS_0, &PPC::VRRCRegClass, Op0); 764 } 765 return 0; 766} 767 768unsigned fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(MVT RetVT, unsigned Op0) { 769 if (RetVT.SimpleTy != MVT::v2i64) 770 return 0; 771 if ((Subtarget->hasVSX())) { 772 return fastEmitInst_r(PPC::XVCVDPSXDS, &PPC::VSRCRegClass, Op0); 773 } 774 return 0; 775} 776 777unsigned fastEmit_ISD_FP_TO_SINT_r(MVT VT, MVT RetVT, unsigned Op0) { 778 switch (VT.SimpleTy) { 779 case MVT::f32: return fastEmit_ISD_FP_TO_SINT_MVT_f32_r(RetVT, Op0); 780 case MVT::f64: return fastEmit_ISD_FP_TO_SINT_MVT_f64_r(RetVT, Op0); 781 case MVT::v4f32: return fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(RetVT, Op0); 782 case MVT::v2f64: return fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(RetVT, Op0); 783 default: return 0; 784 } 785} 786 787// FastEmit functions for ISD::FP_TO_UINT. 788 789unsigned fastEmit_ISD_FP_TO_UINT_MVT_f32_r(MVT RetVT, unsigned Op0) { 790 if (RetVT.SimpleTy != MVT::i32) 791 return 0; 792 if ((Subtarget->hasSPE())) { 793 return fastEmitInst_r(PPC::EFSCTUIZ, &PPC::GPRCRegClass, Op0); 794 } 795 return 0; 796} 797 798unsigned fastEmit_ISD_FP_TO_UINT_MVT_f64_r(MVT RetVT, unsigned Op0) { 799 if (RetVT.SimpleTy != MVT::i32) 800 return 0; 801 if ((Subtarget->hasSPE())) { 802 return fastEmitInst_r(PPC::EFDCTUIZ, &PPC::GPRCRegClass, Op0); 803 } 804 return 0; 805} 806 807unsigned fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(MVT RetVT, unsigned Op0) { 808 if (RetVT.SimpleTy != MVT::v4i32) 809 return 0; 810 if ((Subtarget->hasVSX())) { 811 return fastEmitInst_r(PPC::XVCVSPUXWS, &PPC::VSRCRegClass, Op0); 812 } 813 if ((Subtarget->hasAltivec())) { 814 return fastEmitInst_r(PPC::VCTUXS_0, &PPC::VRRCRegClass, Op0); 815 } 816 return 0; 817} 818 819unsigned fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(MVT RetVT, unsigned Op0) { 820 if (RetVT.SimpleTy != MVT::v2i64) 821 return 0; 822 if ((Subtarget->hasVSX())) { 823 return fastEmitInst_r(PPC::XVCVDPUXDS, &PPC::VSRCRegClass, Op0); 824 } 825 return 0; 826} 827 828unsigned fastEmit_ISD_FP_TO_UINT_r(MVT VT, MVT RetVT, unsigned Op0) { 829 switch (VT.SimpleTy) { 830 case MVT::f32: return fastEmit_ISD_FP_TO_UINT_MVT_f32_r(RetVT, Op0); 831 case MVT::f64: return fastEmit_ISD_FP_TO_UINT_MVT_f64_r(RetVT, Op0); 832 case MVT::v4f32: return fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(RetVT, Op0); 833 case MVT::v2f64: return fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(RetVT, Op0); 834 default: return 0; 835 } 836} 837 838// FastEmit functions for ISD::FRINT. 839 840unsigned fastEmit_ISD_FRINT_MVT_f64_r(MVT RetVT, unsigned Op0) { 841 if (RetVT.SimpleTy != MVT::f64) 842 return 0; 843 if ((Subtarget->hasVSX())) { 844 return fastEmitInst_r(PPC::XSRDPIC, &PPC::VSFRCRegClass, Op0); 845 } 846 return 0; 847} 848 849unsigned fastEmit_ISD_FRINT_MVT_v4f32_r(MVT RetVT, unsigned Op0) { 850 if (RetVT.SimpleTy != MVT::v4f32) 851 return 0; 852 if ((Subtarget->hasVSX())) { 853 return fastEmitInst_r(PPC::XVRSPIC, &PPC::VSRCRegClass, Op0); 854 } 855 return 0; 856} 857 858unsigned fastEmit_ISD_FRINT_MVT_v2f64_r(MVT RetVT, unsigned Op0) { 859 if (RetVT.SimpleTy != MVT::v2f64) 860 return 0; 861 if ((Subtarget->hasVSX())) { 862 return fastEmitInst_r(PPC::XVRDPIC, &PPC::VSRCRegClass, Op0); 863 } 864 return 0; 865} 866 867unsigned fastEmit_ISD_FRINT_r(MVT VT, MVT RetVT, unsigned Op0) { 868 switch (VT.SimpleTy) { 869 case MVT::f64: return fastEmit_ISD_FRINT_MVT_f64_r(RetVT, Op0); 870 case MVT::v4f32: return fastEmit_ISD_FRINT_MVT_v4f32_r(RetVT, Op0); 871 case MVT::v2f64: return fastEmit_ISD_FRINT_MVT_v2f64_r(RetVT, Op0); 872 default: return 0; 873 } 874} 875 876// FastEmit functions for ISD::FROUND. 877 878unsigned fastEmit_ISD_FROUND_MVT_f32_r(MVT RetVT, unsigned Op0) { 879 if (RetVT.SimpleTy != MVT::f32) 880 return 0; 881 if ((Subtarget->hasFPU())) { 882 return fastEmitInst_r(PPC::FRINS, &PPC::F4RCRegClass, Op0); 883 } 884 return 0; 885} 886 887unsigned fastEmit_ISD_FROUND_MVT_f64_r(MVT RetVT, unsigned Op0) { 888 if (RetVT.SimpleTy != MVT::f64) 889 return 0; 890 if ((Subtarget->hasVSX())) { 891 return fastEmitInst_r(PPC::XSRDPI, &PPC::VSFRCRegClass, Op0); 892 } 893 if ((Subtarget->hasFPU())) { 894 return fastEmitInst_r(PPC::FRIND, &PPC::F8RCRegClass, Op0); 895 } 896 return 0; 897} 898 899unsigned fastEmit_ISD_FROUND_MVT_v4f32_r(MVT RetVT, unsigned Op0) { 900 if (RetVT.SimpleTy != MVT::v4f32) 901 return 0; 902 if ((Subtarget->hasVSX())) { 903 return fastEmitInst_r(PPC::XVRSPI, &PPC::VSRCRegClass, Op0); 904 } 905 return 0; 906} 907 908unsigned fastEmit_ISD_FROUND_MVT_v2f64_r(MVT RetVT, unsigned Op0) { 909 if (RetVT.SimpleTy != MVT::v2f64) 910 return 0; 911 if ((Subtarget->hasVSX())) { 912 return fastEmitInst_r(PPC::XVRDPI, &PPC::VSRCRegClass, Op0); 913 } 914 return 0; 915} 916 917unsigned fastEmit_ISD_FROUND_r(MVT VT, MVT RetVT, unsigned Op0) { 918 switch (VT.SimpleTy) { 919 case MVT::f32: return fastEmit_ISD_FROUND_MVT_f32_r(RetVT, Op0); 920 case MVT::f64: return fastEmit_ISD_FROUND_MVT_f64_r(RetVT, Op0); 921 case MVT::v4f32: return fastEmit_ISD_FROUND_MVT_v4f32_r(RetVT, Op0); 922 case MVT::v2f64: return fastEmit_ISD_FROUND_MVT_v2f64_r(RetVT, Op0); 923 default: return 0; 924 } 925} 926 927// FastEmit functions for ISD::FSQRT. 928 929unsigned fastEmit_ISD_FSQRT_MVT_f32_r(MVT RetVT, unsigned Op0) { 930 if (RetVT.SimpleTy != MVT::f32) 931 return 0; 932 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) { 933 return fastEmitInst_r(PPC::XSSQRTSP, &PPC::VSSRCRegClass, Op0); 934 } 935 if ((Subtarget->hasFPU())) { 936 return fastEmitInst_r(PPC::FSQRTS, &PPC::F4RCRegClass, Op0); 937 } 938 return 0; 939} 940 941unsigned fastEmit_ISD_FSQRT_MVT_f64_r(MVT RetVT, unsigned Op0) { 942 if (RetVT.SimpleTy != MVT::f64) 943 return 0; 944 if ((Subtarget->hasVSX())) { 945 return fastEmitInst_r(PPC::XSSQRTDP, &PPC::VSFRCRegClass, Op0); 946 } 947 if ((Subtarget->hasFPU())) { 948 return fastEmitInst_r(PPC::FSQRT, &PPC::F8RCRegClass, Op0); 949 } 950 return 0; 951} 952 953unsigned fastEmit_ISD_FSQRT_MVT_f128_r(MVT RetVT, unsigned Op0) { 954 if (RetVT.SimpleTy != MVT::f128) 955 return 0; 956 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) { 957 return fastEmitInst_r(PPC::XSSQRTQP, &PPC::VRRCRegClass, Op0); 958 } 959 return 0; 960} 961 962unsigned fastEmit_ISD_FSQRT_MVT_v4f32_r(MVT RetVT, unsigned Op0) { 963 if (RetVT.SimpleTy != MVT::v4f32) 964 return 0; 965 if ((Subtarget->hasVSX())) { 966 return fastEmitInst_r(PPC::XVSQRTSP, &PPC::VSRCRegClass, Op0); 967 } 968 return 0; 969} 970 971unsigned fastEmit_ISD_FSQRT_MVT_v2f64_r(MVT RetVT, unsigned Op0) { 972 if (RetVT.SimpleTy != MVT::v2f64) 973 return 0; 974 if ((Subtarget->hasVSX())) { 975 return fastEmitInst_r(PPC::XVSQRTDP, &PPC::VSRCRegClass, Op0); 976 } 977 return 0; 978} 979 980unsigned fastEmit_ISD_FSQRT_r(MVT VT, MVT RetVT, unsigned Op0) { 981 switch (VT.SimpleTy) { 982 case MVT::f32: return fastEmit_ISD_FSQRT_MVT_f32_r(RetVT, Op0); 983 case MVT::f64: return fastEmit_ISD_FSQRT_MVT_f64_r(RetVT, Op0); 984 case MVT::f128: return fastEmit_ISD_FSQRT_MVT_f128_r(RetVT, Op0); 985 case MVT::v4f32: return fastEmit_ISD_FSQRT_MVT_v4f32_r(RetVT, Op0); 986 case MVT::v2f64: return fastEmit_ISD_FSQRT_MVT_v2f64_r(RetVT, Op0); 987 default: return 0; 988 } 989} 990 991// FastEmit functions for ISD::FTRUNC. 992 993unsigned fastEmit_ISD_FTRUNC_MVT_f32_r(MVT RetVT, unsigned Op0) { 994 if (RetVT.SimpleTy != MVT::f32) 995 return 0; 996 if ((Subtarget->hasFPU())) { 997 return fastEmitInst_r(PPC::FRIZS, &PPC::F4RCRegClass, Op0); 998 } 999 return 0; 1000} 1001 1002unsigned fastEmit_ISD_FTRUNC_MVT_f64_r(MVT RetVT, unsigned Op0) { 1003 if (RetVT.SimpleTy != MVT::f64) 1004 return 0; 1005 if ((Subtarget->hasVSX())) { 1006 return fastEmitInst_r(PPC::XSRDPIZ, &PPC::VSFRCRegClass, Op0); 1007 } 1008 if ((Subtarget->hasFPU())) { 1009 return fastEmitInst_r(PPC::FRIZD, &PPC::F8RCRegClass, Op0); 1010 } 1011 return 0; 1012} 1013 1014unsigned fastEmit_ISD_FTRUNC_MVT_v4f32_r(MVT RetVT, unsigned Op0) { 1015 if (RetVT.SimpleTy != MVT::v4f32) 1016 return 0; 1017 if ((Subtarget->hasVSX())) { 1018 return fastEmitInst_r(PPC::XVRSPIZ, &PPC::VSRCRegClass, Op0); 1019 } 1020 if ((Subtarget->hasAltivec())) { 1021 return fastEmitInst_r(PPC::VRFIZ, &PPC::VRRCRegClass, Op0); 1022 } 1023 return 0; 1024} 1025 1026unsigned fastEmit_ISD_FTRUNC_MVT_v2f64_r(MVT RetVT, unsigned Op0) { 1027 if (RetVT.SimpleTy != MVT::v2f64) 1028 return 0; 1029 if ((Subtarget->hasVSX())) { 1030 return fastEmitInst_r(PPC::XVRDPIZ, &PPC::VSRCRegClass, Op0); 1031 } 1032 return 0; 1033} 1034 1035unsigned fastEmit_ISD_FTRUNC_r(MVT VT, MVT RetVT, unsigned Op0) { 1036 switch (VT.SimpleTy) { 1037 case MVT::f32: return fastEmit_ISD_FTRUNC_MVT_f32_r(RetVT, Op0); 1038 case MVT::f64: return fastEmit_ISD_FTRUNC_MVT_f64_r(RetVT, Op0); 1039 case MVT::v4f32: return fastEmit_ISD_FTRUNC_MVT_v4f32_r(RetVT, Op0); 1040 case MVT::v2f64: return fastEmit_ISD_FTRUNC_MVT_v2f64_r(RetVT, Op0); 1041 default: return 0; 1042 } 1043} 1044 1045// FastEmit functions for ISD::SCALAR_TO_VECTOR. 1046 1047unsigned fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_r(MVT RetVT, unsigned Op0) { 1048 if (RetVT.SimpleTy != MVT::v4i32) 1049 return 0; 1050 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) { 1051 return fastEmitInst_r(PPC::MTVSRWS, &PPC::VSRCRegClass, Op0); 1052 } 1053 return 0; 1054} 1055 1056unsigned fastEmit_ISD_SCALAR_TO_VECTOR_MVT_f32_r(MVT RetVT, unsigned Op0) { 1057 if (RetVT.SimpleTy != MVT::v4f32) 1058 return 0; 1059 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX()) && (!Subtarget->isLittleEndian())) { 1060 return fastEmitInst_r(PPC::XSCVDPSPN, &PPC::VSRCRegClass, Op0); 1061 } 1062 return 0; 1063} 1064 1065unsigned fastEmit_ISD_SCALAR_TO_VECTOR_r(MVT VT, MVT RetVT, unsigned Op0) { 1066 switch (VT.SimpleTy) { 1067 case MVT::i32: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_r(RetVT, Op0); 1068 case MVT::f32: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_f32_r(RetVT, Op0); 1069 default: return 0; 1070 } 1071} 1072 1073// FastEmit functions for ISD::SIGN_EXTEND. 1074 1075unsigned fastEmit_ISD_SIGN_EXTEND_MVT_i1_MVT_i32_r(unsigned Op0) { 1076 if ((Subtarget->isISA3_1())) { 1077 return fastEmitInst_r(PPC::SETNBC, &PPC::GPRCRegClass, Op0); 1078 } 1079 return 0; 1080} 1081 1082unsigned fastEmit_ISD_SIGN_EXTEND_MVT_i1_MVT_i64_r(unsigned Op0) { 1083 if ((Subtarget->isISA3_1())) { 1084 return fastEmitInst_r(PPC::SETNBC8, &PPC::G8RCRegClass, Op0); 1085 } 1086 return 0; 1087} 1088 1089unsigned fastEmit_ISD_SIGN_EXTEND_MVT_i1_r(MVT RetVT, unsigned Op0) { 1090switch (RetVT.SimpleTy) { 1091 case MVT::i32: return fastEmit_ISD_SIGN_EXTEND_MVT_i1_MVT_i32_r(Op0); 1092 case MVT::i64: return fastEmit_ISD_SIGN_EXTEND_MVT_i1_MVT_i64_r(Op0); 1093 default: return 0; 1094} 1095} 1096 1097unsigned fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(MVT RetVT, unsigned Op0) { 1098 if (RetVT.SimpleTy != MVT::i64) 1099 return 0; 1100 return fastEmitInst_r(PPC::EXTSW_32_64, &PPC::G8RCRegClass, Op0); 1101} 1102 1103unsigned fastEmit_ISD_SIGN_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0) { 1104 switch (VT.SimpleTy) { 1105 case MVT::i1: return fastEmit_ISD_SIGN_EXTEND_MVT_i1_r(RetVT, Op0); 1106 case MVT::i32: return fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(RetVT, Op0); 1107 default: return 0; 1108 } 1109} 1110 1111// FastEmit functions for ISD::SINT_TO_FP. 1112 1113unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(unsigned Op0) { 1114 if ((Subtarget->hasSPE())) { 1115 return fastEmitInst_r(PPC::EFSCFSI, &PPC::GPRCRegClass, Op0); 1116 } 1117 return 0; 1118} 1119 1120unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(unsigned Op0) { 1121 if ((Subtarget->hasSPE())) { 1122 return fastEmitInst_r(PPC::EFDCFSI, &PPC::SPERCRegClass, Op0); 1123 } 1124 return 0; 1125} 1126 1127unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_r(MVT RetVT, unsigned Op0) { 1128switch (RetVT.SimpleTy) { 1129 case MVT::f32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(Op0); 1130 case MVT::f64: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(Op0); 1131 default: return 0; 1132} 1133} 1134 1135unsigned fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0) { 1136 if (RetVT.SimpleTy != MVT::v4f32) 1137 return 0; 1138 if ((Subtarget->hasVSX())) { 1139 return fastEmitInst_r(PPC::XVCVSXWSP, &PPC::VSRCRegClass, Op0); 1140 } 1141 if ((Subtarget->hasAltivec())) { 1142 return fastEmitInst_r(PPC::VCFSX_0, &PPC::VRRCRegClass, Op0); 1143 } 1144 return 0; 1145} 1146 1147unsigned fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(MVT RetVT, unsigned Op0) { 1148 if (RetVT.SimpleTy != MVT::v2f64) 1149 return 0; 1150 if ((Subtarget->hasVSX())) { 1151 return fastEmitInst_r(PPC::XVCVSXDDP, &PPC::VSRCRegClass, Op0); 1152 } 1153 return 0; 1154} 1155 1156unsigned fastEmit_ISD_SINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0) { 1157 switch (VT.SimpleTy) { 1158 case MVT::i32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_r(RetVT, Op0); 1159 case MVT::v4i32: return fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(RetVT, Op0); 1160 case MVT::v2i64: return fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(RetVT, Op0); 1161 default: return 0; 1162 } 1163} 1164 1165// FastEmit functions for ISD::STRICT_FCEIL. 1166 1167unsigned fastEmit_ISD_STRICT_FCEIL_MVT_f32_r(MVT RetVT, unsigned Op0) { 1168 if (RetVT.SimpleTy != MVT::f32) 1169 return 0; 1170 if ((Subtarget->hasFPU())) { 1171 return fastEmitInst_r(PPC::FRIPS, &PPC::F4RCRegClass, Op0); 1172 } 1173 return 0; 1174} 1175 1176unsigned fastEmit_ISD_STRICT_FCEIL_MVT_f64_r(MVT RetVT, unsigned Op0) { 1177 if (RetVT.SimpleTy != MVT::f64) 1178 return 0; 1179 if ((Subtarget->hasVSX())) { 1180 return fastEmitInst_r(PPC::XSRDPIP, &PPC::VSFRCRegClass, Op0); 1181 } 1182 if ((Subtarget->hasFPU())) { 1183 return fastEmitInst_r(PPC::FRIPD, &PPC::F8RCRegClass, Op0); 1184 } 1185 return 0; 1186} 1187 1188unsigned fastEmit_ISD_STRICT_FCEIL_MVT_v4f32_r(MVT RetVT, unsigned Op0) { 1189 if (RetVT.SimpleTy != MVT::v4f32) 1190 return 0; 1191 if ((Subtarget->hasVSX())) { 1192 return fastEmitInst_r(PPC::XVRSPIP, &PPC::VSRCRegClass, Op0); 1193 } 1194 return 0; 1195} 1196 1197unsigned fastEmit_ISD_STRICT_FCEIL_MVT_v2f64_r(MVT RetVT, unsigned Op0) { 1198 if (RetVT.SimpleTy != MVT::v2f64) 1199 return 0; 1200 if ((Subtarget->hasVSX())) { 1201 return fastEmitInst_r(PPC::XVRDPIP, &PPC::VSRCRegClass, Op0); 1202 } 1203 return 0; 1204} 1205 1206unsigned fastEmit_ISD_STRICT_FCEIL_r(MVT VT, MVT RetVT, unsigned Op0) { 1207 switch (VT.SimpleTy) { 1208 case MVT::f32: return fastEmit_ISD_STRICT_FCEIL_MVT_f32_r(RetVT, Op0); 1209 case MVT::f64: return fastEmit_ISD_STRICT_FCEIL_MVT_f64_r(RetVT, Op0); 1210 case MVT::v4f32: return fastEmit_ISD_STRICT_FCEIL_MVT_v4f32_r(RetVT, Op0); 1211 case MVT::v2f64: return fastEmit_ISD_STRICT_FCEIL_MVT_v2f64_r(RetVT, Op0); 1212 default: return 0; 1213 } 1214} 1215 1216// FastEmit functions for ISD::STRICT_FFLOOR. 1217 1218unsigned fastEmit_ISD_STRICT_FFLOOR_MVT_f32_r(MVT RetVT, unsigned Op0) { 1219 if (RetVT.SimpleTy != MVT::f32) 1220 return 0; 1221 if ((Subtarget->hasFPU())) { 1222 return fastEmitInst_r(PPC::FRIMS, &PPC::F4RCRegClass, Op0); 1223 } 1224 return 0; 1225} 1226 1227unsigned fastEmit_ISD_STRICT_FFLOOR_MVT_f64_r(MVT RetVT, unsigned Op0) { 1228 if (RetVT.SimpleTy != MVT::f64) 1229 return 0; 1230 if ((Subtarget->hasVSX())) { 1231 return fastEmitInst_r(PPC::XSRDPIM, &PPC::VSFRCRegClass, Op0); 1232 } 1233 if ((Subtarget->hasFPU())) { 1234 return fastEmitInst_r(PPC::FRIMD, &PPC::F8RCRegClass, Op0); 1235 } 1236 return 0; 1237} 1238 1239unsigned fastEmit_ISD_STRICT_FFLOOR_MVT_v4f32_r(MVT RetVT, unsigned Op0) { 1240 if (RetVT.SimpleTy != MVT::v4f32) 1241 return 0; 1242 if ((Subtarget->hasVSX())) { 1243 return fastEmitInst_r(PPC::XVRSPIM, &PPC::VSRCRegClass, Op0); 1244 } 1245 return 0; 1246} 1247 1248unsigned fastEmit_ISD_STRICT_FFLOOR_MVT_v2f64_r(MVT RetVT, unsigned Op0) { 1249 if (RetVT.SimpleTy != MVT::v2f64) 1250 return 0; 1251 if ((Subtarget->hasVSX())) { 1252 return fastEmitInst_r(PPC::XVRDPIM, &PPC::VSRCRegClass, Op0); 1253 } 1254 return 0; 1255} 1256 1257unsigned fastEmit_ISD_STRICT_FFLOOR_r(MVT VT, MVT RetVT, unsigned Op0) { 1258 switch (VT.SimpleTy) { 1259 case MVT::f32: return fastEmit_ISD_STRICT_FFLOOR_MVT_f32_r(RetVT, Op0); 1260 case MVT::f64: return fastEmit_ISD_STRICT_FFLOOR_MVT_f64_r(RetVT, Op0); 1261 case MVT::v4f32: return fastEmit_ISD_STRICT_FFLOOR_MVT_v4f32_r(RetVT, Op0); 1262 case MVT::v2f64: return fastEmit_ISD_STRICT_FFLOOR_MVT_v2f64_r(RetVT, Op0); 1263 default: return 0; 1264 } 1265} 1266 1267// FastEmit functions for ISD::STRICT_FP_EXTEND. 1268 1269unsigned fastEmit_ISD_STRICT_FP_EXTEND_MVT_f32_r(MVT RetVT, unsigned Op0) { 1270 if (RetVT.SimpleTy != MVT::f64) 1271 return 0; 1272 if ((Subtarget->hasSPE())) { 1273 return fastEmitInst_r(PPC::EFDCFS, &PPC::SPERCRegClass, Op0); 1274 } 1275 return 0; 1276} 1277 1278unsigned fastEmit_ISD_STRICT_FP_EXTEND_MVT_f64_r(MVT RetVT, unsigned Op0) { 1279 if (RetVT.SimpleTy != MVT::f128) 1280 return 0; 1281 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) { 1282 return fastEmitInst_r(PPC::XSCVDPQP, &PPC::VRRCRegClass, Op0); 1283 } 1284 return 0; 1285} 1286 1287unsigned fastEmit_ISD_STRICT_FP_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0) { 1288 switch (VT.SimpleTy) { 1289 case MVT::f32: return fastEmit_ISD_STRICT_FP_EXTEND_MVT_f32_r(RetVT, Op0); 1290 case MVT::f64: return fastEmit_ISD_STRICT_FP_EXTEND_MVT_f64_r(RetVT, Op0); 1291 default: return 0; 1292 } 1293} 1294 1295// FastEmit functions for ISD::STRICT_FP_ROUND. 1296 1297unsigned fastEmit_ISD_STRICT_FP_ROUND_MVT_f64_r(MVT RetVT, unsigned Op0) { 1298 if (RetVT.SimpleTy != MVT::f32) 1299 return 0; 1300 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) { 1301 return fastEmitInst_r(PPC::XSRSP, &PPC::VSSRCRegClass, Op0); 1302 } 1303 if ((Subtarget->hasSPE())) { 1304 return fastEmitInst_r(PPC::EFSCFD, &PPC::GPRCRegClass, Op0); 1305 } 1306 if ((Subtarget->hasFPU())) { 1307 return fastEmitInst_r(PPC::FRSP, &PPC::F4RCRegClass, Op0); 1308 } 1309 return 0; 1310} 1311 1312unsigned fastEmit_ISD_STRICT_FP_ROUND_MVT_f128_r(MVT RetVT, unsigned Op0) { 1313 if (RetVT.SimpleTy != MVT::f64) 1314 return 0; 1315 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) { 1316 return fastEmitInst_r(PPC::XSCVQPDP, &PPC::VFRCRegClass, Op0); 1317 } 1318 return 0; 1319} 1320 1321unsigned fastEmit_ISD_STRICT_FP_ROUND_r(MVT VT, MVT RetVT, unsigned Op0) { 1322 switch (VT.SimpleTy) { 1323 case MVT::f64: return fastEmit_ISD_STRICT_FP_ROUND_MVT_f64_r(RetVT, Op0); 1324 case MVT::f128: return fastEmit_ISD_STRICT_FP_ROUND_MVT_f128_r(RetVT, Op0); 1325 default: return 0; 1326 } 1327} 1328 1329// FastEmit functions for ISD::STRICT_FP_TO_SINT. 1330 1331unsigned fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f32_r(MVT RetVT, unsigned Op0) { 1332 if (RetVT.SimpleTy != MVT::i32) 1333 return 0; 1334 if ((Subtarget->hasSPE())) { 1335 return fastEmitInst_r(PPC::EFSCTSIZ, &PPC::GPRCRegClass, Op0); 1336 } 1337 return 0; 1338} 1339 1340unsigned fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f64_r(MVT RetVT, unsigned Op0) { 1341 if (RetVT.SimpleTy != MVT::i32) 1342 return 0; 1343 if ((Subtarget->hasSPE())) { 1344 return fastEmitInst_r(PPC::EFDCTSIZ, &PPC::GPRCRegClass, Op0); 1345 } 1346 return 0; 1347} 1348 1349unsigned fastEmit_ISD_STRICT_FP_TO_SINT_MVT_v4f32_r(MVT RetVT, unsigned Op0) { 1350 if (RetVT.SimpleTy != MVT::v4i32) 1351 return 0; 1352 if ((Subtarget->hasVSX())) { 1353 return fastEmitInst_r(PPC::XVCVSPSXWS, &PPC::VSRCRegClass, Op0); 1354 } 1355 return 0; 1356} 1357 1358unsigned fastEmit_ISD_STRICT_FP_TO_SINT_MVT_v2f64_r(MVT RetVT, unsigned Op0) { 1359 if (RetVT.SimpleTy != MVT::v2i64) 1360 return 0; 1361 if ((Subtarget->hasVSX())) { 1362 return fastEmitInst_r(PPC::XVCVDPSXDS, &PPC::VSRCRegClass, Op0); 1363 } 1364 return 0; 1365} 1366 1367unsigned fastEmit_ISD_STRICT_FP_TO_SINT_r(MVT VT, MVT RetVT, unsigned Op0) { 1368 switch (VT.SimpleTy) { 1369 case MVT::f32: return fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f32_r(RetVT, Op0); 1370 case MVT::f64: return fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f64_r(RetVT, Op0); 1371 case MVT::v4f32: return fastEmit_ISD_STRICT_FP_TO_SINT_MVT_v4f32_r(RetVT, Op0); 1372 case MVT::v2f64: return fastEmit_ISD_STRICT_FP_TO_SINT_MVT_v2f64_r(RetVT, Op0); 1373 default: return 0; 1374 } 1375} 1376 1377// FastEmit functions for ISD::STRICT_FP_TO_UINT. 1378 1379unsigned fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f32_r(MVT RetVT, unsigned Op0) { 1380 if (RetVT.SimpleTy != MVT::i32) 1381 return 0; 1382 if ((Subtarget->hasSPE())) { 1383 return fastEmitInst_r(PPC::EFSCTUIZ, &PPC::GPRCRegClass, Op0); 1384 } 1385 return 0; 1386} 1387 1388unsigned fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f64_r(MVT RetVT, unsigned Op0) { 1389 if (RetVT.SimpleTy != MVT::i32) 1390 return 0; 1391 if ((Subtarget->hasSPE())) { 1392 return fastEmitInst_r(PPC::EFDCTUIZ, &PPC::GPRCRegClass, Op0); 1393 } 1394 return 0; 1395} 1396 1397unsigned fastEmit_ISD_STRICT_FP_TO_UINT_MVT_v4f32_r(MVT RetVT, unsigned Op0) { 1398 if (RetVT.SimpleTy != MVT::v4i32) 1399 return 0; 1400 if ((Subtarget->hasVSX())) { 1401 return fastEmitInst_r(PPC::XVCVSPUXWS, &PPC::VSRCRegClass, Op0); 1402 } 1403 return 0; 1404} 1405 1406unsigned fastEmit_ISD_STRICT_FP_TO_UINT_MVT_v2f64_r(MVT RetVT, unsigned Op0) { 1407 if (RetVT.SimpleTy != MVT::v2i64) 1408 return 0; 1409 if ((Subtarget->hasVSX())) { 1410 return fastEmitInst_r(PPC::XVCVDPUXDS, &PPC::VSRCRegClass, Op0); 1411 } 1412 return 0; 1413} 1414 1415unsigned fastEmit_ISD_STRICT_FP_TO_UINT_r(MVT VT, MVT RetVT, unsigned Op0) { 1416 switch (VT.SimpleTy) { 1417 case MVT::f32: return fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f32_r(RetVT, Op0); 1418 case MVT::f64: return fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f64_r(RetVT, Op0); 1419 case MVT::v4f32: return fastEmit_ISD_STRICT_FP_TO_UINT_MVT_v4f32_r(RetVT, Op0); 1420 case MVT::v2f64: return fastEmit_ISD_STRICT_FP_TO_UINT_MVT_v2f64_r(RetVT, Op0); 1421 default: return 0; 1422 } 1423} 1424 1425// FastEmit functions for ISD::STRICT_FRINT. 1426 1427unsigned fastEmit_ISD_STRICT_FRINT_MVT_f64_r(MVT RetVT, unsigned Op0) { 1428 if (RetVT.SimpleTy != MVT::f64) 1429 return 0; 1430 if ((Subtarget->hasVSX())) { 1431 return fastEmitInst_r(PPC::XSRDPIC, &PPC::VSFRCRegClass, Op0); 1432 } 1433 return 0; 1434} 1435 1436unsigned fastEmit_ISD_STRICT_FRINT_MVT_v4f32_r(MVT RetVT, unsigned Op0) { 1437 if (RetVT.SimpleTy != MVT::v4f32) 1438 return 0; 1439 if ((Subtarget->hasVSX())) { 1440 return fastEmitInst_r(PPC::XVRSPIC, &PPC::VSRCRegClass, Op0); 1441 } 1442 return 0; 1443} 1444 1445unsigned fastEmit_ISD_STRICT_FRINT_MVT_v2f64_r(MVT RetVT, unsigned Op0) { 1446 if (RetVT.SimpleTy != MVT::v2f64) 1447 return 0; 1448 if ((Subtarget->hasVSX())) { 1449 return fastEmitInst_r(PPC::XVRDPIC, &PPC::VSRCRegClass, Op0); 1450 } 1451 return 0; 1452} 1453 1454unsigned fastEmit_ISD_STRICT_FRINT_r(MVT VT, MVT RetVT, unsigned Op0) { 1455 switch (VT.SimpleTy) { 1456 case MVT::f64: return fastEmit_ISD_STRICT_FRINT_MVT_f64_r(RetVT, Op0); 1457 case MVT::v4f32: return fastEmit_ISD_STRICT_FRINT_MVT_v4f32_r(RetVT, Op0); 1458 case MVT::v2f64: return fastEmit_ISD_STRICT_FRINT_MVT_v2f64_r(RetVT, Op0); 1459 default: return 0; 1460 } 1461} 1462 1463// FastEmit functions for ISD::STRICT_FROUND. 1464 1465unsigned fastEmit_ISD_STRICT_FROUND_MVT_f32_r(MVT RetVT, unsigned Op0) { 1466 if (RetVT.SimpleTy != MVT::f32) 1467 return 0; 1468 if ((Subtarget->hasFPU())) { 1469 return fastEmitInst_r(PPC::FRINS, &PPC::F4RCRegClass, Op0); 1470 } 1471 return 0; 1472} 1473 1474unsigned fastEmit_ISD_STRICT_FROUND_MVT_f64_r(MVT RetVT, unsigned Op0) { 1475 if (RetVT.SimpleTy != MVT::f64) 1476 return 0; 1477 if ((Subtarget->hasVSX())) { 1478 return fastEmitInst_r(PPC::XSRDPI, &PPC::VSFRCRegClass, Op0); 1479 } 1480 if ((Subtarget->hasFPU())) { 1481 return fastEmitInst_r(PPC::FRIND, &PPC::F8RCRegClass, Op0); 1482 } 1483 return 0; 1484} 1485 1486unsigned fastEmit_ISD_STRICT_FROUND_MVT_v4f32_r(MVT RetVT, unsigned Op0) { 1487 if (RetVT.SimpleTy != MVT::v4f32) 1488 return 0; 1489 if ((Subtarget->hasVSX())) { 1490 return fastEmitInst_r(PPC::XVRSPI, &PPC::VSRCRegClass, Op0); 1491 } 1492 return 0; 1493} 1494 1495unsigned fastEmit_ISD_STRICT_FROUND_MVT_v2f64_r(MVT RetVT, unsigned Op0) { 1496 if (RetVT.SimpleTy != MVT::v2f64) 1497 return 0; 1498 if ((Subtarget->hasVSX())) { 1499 return fastEmitInst_r(PPC::XVRDPI, &PPC::VSRCRegClass, Op0); 1500 } 1501 return 0; 1502} 1503 1504unsigned fastEmit_ISD_STRICT_FROUND_r(MVT VT, MVT RetVT, unsigned Op0) { 1505 switch (VT.SimpleTy) { 1506 case MVT::f32: return fastEmit_ISD_STRICT_FROUND_MVT_f32_r(RetVT, Op0); 1507 case MVT::f64: return fastEmit_ISD_STRICT_FROUND_MVT_f64_r(RetVT, Op0); 1508 case MVT::v4f32: return fastEmit_ISD_STRICT_FROUND_MVT_v4f32_r(RetVT, Op0); 1509 case MVT::v2f64: return fastEmit_ISD_STRICT_FROUND_MVT_v2f64_r(RetVT, Op0); 1510 default: return 0; 1511 } 1512} 1513 1514// FastEmit functions for ISD::STRICT_FSQRT. 1515 1516unsigned fastEmit_ISD_STRICT_FSQRT_MVT_f32_r(MVT RetVT, unsigned Op0) { 1517 if (RetVT.SimpleTy != MVT::f32) 1518 return 0; 1519 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) { 1520 return fastEmitInst_r(PPC::XSSQRTSP, &PPC::VSSRCRegClass, Op0); 1521 } 1522 if ((Subtarget->hasFPU())) { 1523 return fastEmitInst_r(PPC::FSQRTS, &PPC::F4RCRegClass, Op0); 1524 } 1525 return 0; 1526} 1527 1528unsigned fastEmit_ISD_STRICT_FSQRT_MVT_f64_r(MVT RetVT, unsigned Op0) { 1529 if (RetVT.SimpleTy != MVT::f64) 1530 return 0; 1531 if ((Subtarget->hasVSX())) { 1532 return fastEmitInst_r(PPC::XSSQRTDP, &PPC::VSFRCRegClass, Op0); 1533 } 1534 if ((Subtarget->hasFPU())) { 1535 return fastEmitInst_r(PPC::FSQRT, &PPC::F8RCRegClass, Op0); 1536 } 1537 return 0; 1538} 1539 1540unsigned fastEmit_ISD_STRICT_FSQRT_MVT_f128_r(MVT RetVT, unsigned Op0) { 1541 if (RetVT.SimpleTy != MVT::f128) 1542 return 0; 1543 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) { 1544 return fastEmitInst_r(PPC::XSSQRTQP, &PPC::VRRCRegClass, Op0); 1545 } 1546 return 0; 1547} 1548 1549unsigned fastEmit_ISD_STRICT_FSQRT_MVT_v4f32_r(MVT RetVT, unsigned Op0) { 1550 if (RetVT.SimpleTy != MVT::v4f32) 1551 return 0; 1552 if ((Subtarget->hasVSX())) { 1553 return fastEmitInst_r(PPC::XVSQRTSP, &PPC::VSRCRegClass, Op0); 1554 } 1555 return 0; 1556} 1557 1558unsigned fastEmit_ISD_STRICT_FSQRT_MVT_v2f64_r(MVT RetVT, unsigned Op0) { 1559 if (RetVT.SimpleTy != MVT::v2f64) 1560 return 0; 1561 if ((Subtarget->hasVSX())) { 1562 return fastEmitInst_r(PPC::XVSQRTDP, &PPC::VSRCRegClass, Op0); 1563 } 1564 return 0; 1565} 1566 1567unsigned fastEmit_ISD_STRICT_FSQRT_r(MVT VT, MVT RetVT, unsigned Op0) { 1568 switch (VT.SimpleTy) { 1569 case MVT::f32: return fastEmit_ISD_STRICT_FSQRT_MVT_f32_r(RetVT, Op0); 1570 case MVT::f64: return fastEmit_ISD_STRICT_FSQRT_MVT_f64_r(RetVT, Op0); 1571 case MVT::f128: return fastEmit_ISD_STRICT_FSQRT_MVT_f128_r(RetVT, Op0); 1572 case MVT::v4f32: return fastEmit_ISD_STRICT_FSQRT_MVT_v4f32_r(RetVT, Op0); 1573 case MVT::v2f64: return fastEmit_ISD_STRICT_FSQRT_MVT_v2f64_r(RetVT, Op0); 1574 default: return 0; 1575 } 1576} 1577 1578// FastEmit functions for ISD::STRICT_FTRUNC. 1579 1580unsigned fastEmit_ISD_STRICT_FTRUNC_MVT_f32_r(MVT RetVT, unsigned Op0) { 1581 if (RetVT.SimpleTy != MVT::f32) 1582 return 0; 1583 if ((Subtarget->hasFPU())) { 1584 return fastEmitInst_r(PPC::FRIZS, &PPC::F4RCRegClass, Op0); 1585 } 1586 return 0; 1587} 1588 1589unsigned fastEmit_ISD_STRICT_FTRUNC_MVT_f64_r(MVT RetVT, unsigned Op0) { 1590 if (RetVT.SimpleTy != MVT::f64) 1591 return 0; 1592 if ((Subtarget->hasVSX())) { 1593 return fastEmitInst_r(PPC::XSRDPIZ, &PPC::VSFRCRegClass, Op0); 1594 } 1595 if ((Subtarget->hasFPU())) { 1596 return fastEmitInst_r(PPC::FRIZD, &PPC::F8RCRegClass, Op0); 1597 } 1598 return 0; 1599} 1600 1601unsigned fastEmit_ISD_STRICT_FTRUNC_MVT_v4f32_r(MVT RetVT, unsigned Op0) { 1602 if (RetVT.SimpleTy != MVT::v4f32) 1603 return 0; 1604 if ((Subtarget->hasVSX())) { 1605 return fastEmitInst_r(PPC::XVRSPIZ, &PPC::VSRCRegClass, Op0); 1606 } 1607 return 0; 1608} 1609 1610unsigned fastEmit_ISD_STRICT_FTRUNC_MVT_v2f64_r(MVT RetVT, unsigned Op0) { 1611 if (RetVT.SimpleTy != MVT::v2f64) 1612 return 0; 1613 if ((Subtarget->hasVSX())) { 1614 return fastEmitInst_r(PPC::XVRDPIZ, &PPC::VSRCRegClass, Op0); 1615 } 1616 return 0; 1617} 1618 1619unsigned fastEmit_ISD_STRICT_FTRUNC_r(MVT VT, MVT RetVT, unsigned Op0) { 1620 switch (VT.SimpleTy) { 1621 case MVT::f32: return fastEmit_ISD_STRICT_FTRUNC_MVT_f32_r(RetVT, Op0); 1622 case MVT::f64: return fastEmit_ISD_STRICT_FTRUNC_MVT_f64_r(RetVT, Op0); 1623 case MVT::v4f32: return fastEmit_ISD_STRICT_FTRUNC_MVT_v4f32_r(RetVT, Op0); 1624 case MVT::v2f64: return fastEmit_ISD_STRICT_FTRUNC_MVT_v2f64_r(RetVT, Op0); 1625 default: return 0; 1626 } 1627} 1628 1629// FastEmit functions for ISD::STRICT_SINT_TO_FP. 1630 1631unsigned fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_MVT_f32_r(unsigned Op0) { 1632 if ((Subtarget->hasSPE())) { 1633 return fastEmitInst_r(PPC::EFSCFSI, &PPC::GPRCRegClass, Op0); 1634 } 1635 return 0; 1636} 1637 1638unsigned fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_MVT_f64_r(unsigned Op0) { 1639 if ((Subtarget->hasSPE())) { 1640 return fastEmitInst_r(PPC::EFDCFSI, &PPC::SPERCRegClass, Op0); 1641 } 1642 return 0; 1643} 1644 1645unsigned fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_r(MVT RetVT, unsigned Op0) { 1646switch (RetVT.SimpleTy) { 1647 case MVT::f32: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_MVT_f32_r(Op0); 1648 case MVT::f64: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_MVT_f64_r(Op0); 1649 default: return 0; 1650} 1651} 1652 1653unsigned fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0) { 1654 if (RetVT.SimpleTy != MVT::v4f32) 1655 return 0; 1656 if ((Subtarget->hasVSX())) { 1657 return fastEmitInst_r(PPC::XVCVSXWSP, &PPC::VSRCRegClass, Op0); 1658 } 1659 return 0; 1660} 1661 1662unsigned fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v2i64_r(MVT RetVT, unsigned Op0) { 1663 if (RetVT.SimpleTy != MVT::v2f64) 1664 return 0; 1665 if ((Subtarget->hasVSX())) { 1666 return fastEmitInst_r(PPC::XVCVSXDDP, &PPC::VSRCRegClass, Op0); 1667 } 1668 return 0; 1669} 1670 1671unsigned fastEmit_ISD_STRICT_SINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0) { 1672 switch (VT.SimpleTy) { 1673 case MVT::i32: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_r(RetVT, Op0); 1674 case MVT::v4i32: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v4i32_r(RetVT, Op0); 1675 case MVT::v2i64: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v2i64_r(RetVT, Op0); 1676 default: return 0; 1677 } 1678} 1679 1680// FastEmit functions for ISD::STRICT_UINT_TO_FP. 1681 1682unsigned fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i32_MVT_f32_r(unsigned Op0) { 1683 if ((Subtarget->hasSPE())) { 1684 return fastEmitInst_r(PPC::EFSCFUI, &PPC::GPRCRegClass, Op0); 1685 } 1686 return 0; 1687} 1688 1689unsigned fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i32_MVT_f64_r(unsigned Op0) { 1690 if ((Subtarget->hasSPE())) { 1691 return fastEmitInst_r(PPC::EFDCFUI, &PPC::SPERCRegClass, Op0); 1692 } 1693 return 0; 1694} 1695 1696unsigned fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i32_r(MVT RetVT, unsigned Op0) { 1697switch (RetVT.SimpleTy) { 1698 case MVT::f32: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i32_MVT_f32_r(Op0); 1699 case MVT::f64: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i32_MVT_f64_r(Op0); 1700 default: return 0; 1701} 1702} 1703 1704unsigned fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0) { 1705 if (RetVT.SimpleTy != MVT::v4f32) 1706 return 0; 1707 if ((Subtarget->hasVSX())) { 1708 return fastEmitInst_r(PPC::XVCVUXWSP, &PPC::VSRCRegClass, Op0); 1709 } 1710 return 0; 1711} 1712 1713unsigned fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v2i64_r(MVT RetVT, unsigned Op0) { 1714 if (RetVT.SimpleTy != MVT::v2f64) 1715 return 0; 1716 if ((Subtarget->hasVSX())) { 1717 return fastEmitInst_r(PPC::XVCVUXDDP, &PPC::VSRCRegClass, Op0); 1718 } 1719 return 0; 1720} 1721 1722unsigned fastEmit_ISD_STRICT_UINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0) { 1723 switch (VT.SimpleTy) { 1724 case MVT::i32: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i32_r(RetVT, Op0); 1725 case MVT::v4i32: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v4i32_r(RetVT, Op0); 1726 case MVT::v2i64: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v2i64_r(RetVT, Op0); 1727 default: return 0; 1728 } 1729} 1730 1731// FastEmit functions for ISD::TRUNCATE. 1732 1733unsigned fastEmit_ISD_TRUNCATE_MVT_i32_r(MVT RetVT, unsigned Op0) { 1734 if (RetVT.SimpleTy != MVT::i1) 1735 return 0; 1736 return fastEmitInst_r(PPC::ANDI_rec_1_GT_BIT, &PPC::CRBITRCRegClass, Op0); 1737} 1738 1739unsigned fastEmit_ISD_TRUNCATE_MVT_i64_r(MVT RetVT, unsigned Op0) { 1740 if (RetVT.SimpleTy != MVT::i1) 1741 return 0; 1742 return fastEmitInst_r(PPC::ANDI_rec_1_GT_BIT8, &PPC::CRBITRCRegClass, Op0); 1743} 1744 1745unsigned fastEmit_ISD_TRUNCATE_r(MVT VT, MVT RetVT, unsigned Op0) { 1746 switch (VT.SimpleTy) { 1747 case MVT::i32: return fastEmit_ISD_TRUNCATE_MVT_i32_r(RetVT, Op0); 1748 case MVT::i64: return fastEmit_ISD_TRUNCATE_MVT_i64_r(RetVT, Op0); 1749 default: return 0; 1750 } 1751} 1752 1753// FastEmit functions for ISD::UINT_TO_FP. 1754 1755unsigned fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f32_r(unsigned Op0) { 1756 if ((Subtarget->hasSPE())) { 1757 return fastEmitInst_r(PPC::EFSCFUI, &PPC::GPRCRegClass, Op0); 1758 } 1759 return 0; 1760} 1761 1762unsigned fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f64_r(unsigned Op0) { 1763 if ((Subtarget->hasSPE())) { 1764 return fastEmitInst_r(PPC::EFDCFUI, &PPC::SPERCRegClass, Op0); 1765 } 1766 return 0; 1767} 1768 1769unsigned fastEmit_ISD_UINT_TO_FP_MVT_i32_r(MVT RetVT, unsigned Op0) { 1770switch (RetVT.SimpleTy) { 1771 case MVT::f32: return fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f32_r(Op0); 1772 case MVT::f64: return fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f64_r(Op0); 1773 default: return 0; 1774} 1775} 1776 1777unsigned fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0) { 1778 if (RetVT.SimpleTy != MVT::v4f32) 1779 return 0; 1780 if ((Subtarget->hasVSX())) { 1781 return fastEmitInst_r(PPC::XVCVUXWSP, &PPC::VSRCRegClass, Op0); 1782 } 1783 if ((Subtarget->hasAltivec())) { 1784 return fastEmitInst_r(PPC::VCFUX_0, &PPC::VRRCRegClass, Op0); 1785 } 1786 return 0; 1787} 1788 1789unsigned fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(MVT RetVT, unsigned Op0) { 1790 if (RetVT.SimpleTy != MVT::v2f64) 1791 return 0; 1792 if ((Subtarget->hasVSX())) { 1793 return fastEmitInst_r(PPC::XVCVUXDDP, &PPC::VSRCRegClass, Op0); 1794 } 1795 return 0; 1796} 1797 1798unsigned fastEmit_ISD_UINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0) { 1799 switch (VT.SimpleTy) { 1800 case MVT::i32: return fastEmit_ISD_UINT_TO_FP_MVT_i32_r(RetVT, Op0); 1801 case MVT::v4i32: return fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(RetVT, Op0); 1802 case MVT::v2i64: return fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(RetVT, Op0); 1803 default: return 0; 1804 } 1805} 1806 1807// FastEmit functions for ISD::ZERO_EXTEND. 1808 1809unsigned fastEmit_ISD_ZERO_EXTEND_MVT_i1_MVT_i32_r(unsigned Op0) { 1810 if ((Subtarget->isISA3_1())) { 1811 return fastEmitInst_r(PPC::SETBC, &PPC::GPRCRegClass, Op0); 1812 } 1813 return 0; 1814} 1815 1816unsigned fastEmit_ISD_ZERO_EXTEND_MVT_i1_MVT_i64_r(unsigned Op0) { 1817 if ((Subtarget->isISA3_1())) { 1818 return fastEmitInst_r(PPC::SETBC8, &PPC::G8RCRegClass, Op0); 1819 } 1820 return 0; 1821} 1822 1823unsigned fastEmit_ISD_ZERO_EXTEND_MVT_i1_r(MVT RetVT, unsigned Op0) { 1824switch (RetVT.SimpleTy) { 1825 case MVT::i32: return fastEmit_ISD_ZERO_EXTEND_MVT_i1_MVT_i32_r(Op0); 1826 case MVT::i64: return fastEmit_ISD_ZERO_EXTEND_MVT_i1_MVT_i64_r(Op0); 1827 default: return 0; 1828} 1829} 1830 1831unsigned fastEmit_ISD_ZERO_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0) { 1832 switch (VT.SimpleTy) { 1833 case MVT::i1: return fastEmit_ISD_ZERO_EXTEND_MVT_i1_r(RetVT, Op0); 1834 default: return 0; 1835 } 1836} 1837 1838// FastEmit functions for PPCISD::FCFID. 1839 1840unsigned fastEmit_PPCISD_FCFID_MVT_f64_r(MVT RetVT, unsigned Op0) { 1841 if (RetVT.SimpleTy != MVT::f64) 1842 return 0; 1843 if ((Subtarget->hasVSX())) { 1844 return fastEmitInst_r(PPC::XSCVSXDDP, &PPC::VSFRCRegClass, Op0); 1845 } 1846 return fastEmitInst_r(PPC::FCFID, &PPC::F8RCRegClass, Op0); 1847} 1848 1849unsigned fastEmit_PPCISD_FCFID_r(MVT VT, MVT RetVT, unsigned Op0) { 1850 switch (VT.SimpleTy) { 1851 case MVT::f64: return fastEmit_PPCISD_FCFID_MVT_f64_r(RetVT, Op0); 1852 default: return 0; 1853 } 1854} 1855 1856// FastEmit functions for PPCISD::FCFIDS. 1857 1858unsigned fastEmit_PPCISD_FCFIDS_MVT_f64_r(MVT RetVT, unsigned Op0) { 1859 if (RetVT.SimpleTy != MVT::f32) 1860 return 0; 1861 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) { 1862 return fastEmitInst_r(PPC::XSCVSXDSP, &PPC::VSSRCRegClass, Op0); 1863 } 1864 return fastEmitInst_r(PPC::FCFIDS, &PPC::F4RCRegClass, Op0); 1865} 1866 1867unsigned fastEmit_PPCISD_FCFIDS_r(MVT VT, MVT RetVT, unsigned Op0) { 1868 switch (VT.SimpleTy) { 1869 case MVT::f64: return fastEmit_PPCISD_FCFIDS_MVT_f64_r(RetVT, Op0); 1870 default: return 0; 1871 } 1872} 1873 1874// FastEmit functions for PPCISD::FCFIDU. 1875 1876unsigned fastEmit_PPCISD_FCFIDU_MVT_f64_r(MVT RetVT, unsigned Op0) { 1877 if (RetVT.SimpleTy != MVT::f64) 1878 return 0; 1879 if ((Subtarget->hasVSX())) { 1880 return fastEmitInst_r(PPC::XSCVUXDDP, &PPC::VSFRCRegClass, Op0); 1881 } 1882 return fastEmitInst_r(PPC::FCFIDU, &PPC::F8RCRegClass, Op0); 1883} 1884 1885unsigned fastEmit_PPCISD_FCFIDU_r(MVT VT, MVT RetVT, unsigned Op0) { 1886 switch (VT.SimpleTy) { 1887 case MVT::f64: return fastEmit_PPCISD_FCFIDU_MVT_f64_r(RetVT, Op0); 1888 default: return 0; 1889 } 1890} 1891 1892// FastEmit functions for PPCISD::FCFIDUS. 1893 1894unsigned fastEmit_PPCISD_FCFIDUS_MVT_f64_r(MVT RetVT, unsigned Op0) { 1895 if (RetVT.SimpleTy != MVT::f32) 1896 return 0; 1897 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) { 1898 return fastEmitInst_r(PPC::XSCVUXDSP, &PPC::VSSRCRegClass, Op0); 1899 } 1900 return fastEmitInst_r(PPC::FCFIDUS, &PPC::F4RCRegClass, Op0); 1901} 1902 1903unsigned fastEmit_PPCISD_FCFIDUS_r(MVT VT, MVT RetVT, unsigned Op0) { 1904 switch (VT.SimpleTy) { 1905 case MVT::f64: return fastEmit_PPCISD_FCFIDUS_MVT_f64_r(RetVT, Op0); 1906 default: return 0; 1907 } 1908} 1909 1910// FastEmit functions for PPCISD::FCTIDUZ. 1911 1912unsigned fastEmit_PPCISD_FCTIDUZ_MVT_f32_r(MVT RetVT, unsigned Op0) { 1913 if (RetVT.SimpleTy != MVT::f32) 1914 return 0; 1915 if ((Subtarget->hasVSX())) { 1916 return fastEmitInst_r(PPC::XSCVDPUXDSs, &PPC::VSSRCRegClass, Op0); 1917 } 1918 return 0; 1919} 1920 1921unsigned fastEmit_PPCISD_FCTIDUZ_MVT_f64_r(MVT RetVT, unsigned Op0) { 1922 if (RetVT.SimpleTy != MVT::f64) 1923 return 0; 1924 if ((Subtarget->hasVSX())) { 1925 return fastEmitInst_r(PPC::XSCVDPUXDS, &PPC::VSFRCRegClass, Op0); 1926 } 1927 return fastEmitInst_r(PPC::FCTIDUZ, &PPC::F8RCRegClass, Op0); 1928} 1929 1930unsigned fastEmit_PPCISD_FCTIDUZ_r(MVT VT, MVT RetVT, unsigned Op0) { 1931 switch (VT.SimpleTy) { 1932 case MVT::f32: return fastEmit_PPCISD_FCTIDUZ_MVT_f32_r(RetVT, Op0); 1933 case MVT::f64: return fastEmit_PPCISD_FCTIDUZ_MVT_f64_r(RetVT, Op0); 1934 default: return 0; 1935 } 1936} 1937 1938// FastEmit functions for PPCISD::FCTIDZ. 1939 1940unsigned fastEmit_PPCISD_FCTIDZ_MVT_f32_r(MVT RetVT, unsigned Op0) { 1941 if (RetVT.SimpleTy != MVT::f32) 1942 return 0; 1943 if ((Subtarget->hasVSX())) { 1944 return fastEmitInst_r(PPC::XSCVDPSXDSs, &PPC::VSSRCRegClass, Op0); 1945 } 1946 return 0; 1947} 1948 1949unsigned fastEmit_PPCISD_FCTIDZ_MVT_f64_r(MVT RetVT, unsigned Op0) { 1950 if (RetVT.SimpleTy != MVT::f64) 1951 return 0; 1952 if ((Subtarget->hasVSX())) { 1953 return fastEmitInst_r(PPC::XSCVDPSXDS, &PPC::VSFRCRegClass, Op0); 1954 } 1955 return fastEmitInst_r(PPC::FCTIDZ, &PPC::F8RCRegClass, Op0); 1956} 1957 1958unsigned fastEmit_PPCISD_FCTIDZ_r(MVT VT, MVT RetVT, unsigned Op0) { 1959 switch (VT.SimpleTy) { 1960 case MVT::f32: return fastEmit_PPCISD_FCTIDZ_MVT_f32_r(RetVT, Op0); 1961 case MVT::f64: return fastEmit_PPCISD_FCTIDZ_MVT_f64_r(RetVT, Op0); 1962 default: return 0; 1963 } 1964} 1965 1966// FastEmit functions for PPCISD::FCTIWUZ. 1967 1968unsigned fastEmit_PPCISD_FCTIWUZ_MVT_f32_r(MVT RetVT, unsigned Op0) { 1969 if (RetVT.SimpleTy != MVT::f32) 1970 return 0; 1971 if ((Subtarget->hasVSX())) { 1972 return fastEmitInst_r(PPC::XSCVDPUXWSs, &PPC::VSSRCRegClass, Op0); 1973 } 1974 return 0; 1975} 1976 1977unsigned fastEmit_PPCISD_FCTIWUZ_MVT_f64_r(MVT RetVT, unsigned Op0) { 1978 if (RetVT.SimpleTy != MVT::f64) 1979 return 0; 1980 if ((Subtarget->hasVSX())) { 1981 return fastEmitInst_r(PPC::XSCVDPUXWS, &PPC::VSFRCRegClass, Op0); 1982 } 1983 return fastEmitInst_r(PPC::FCTIWUZ, &PPC::F8RCRegClass, Op0); 1984} 1985 1986unsigned fastEmit_PPCISD_FCTIWUZ_r(MVT VT, MVT RetVT, unsigned Op0) { 1987 switch (VT.SimpleTy) { 1988 case MVT::f32: return fastEmit_PPCISD_FCTIWUZ_MVT_f32_r(RetVT, Op0); 1989 case MVT::f64: return fastEmit_PPCISD_FCTIWUZ_MVT_f64_r(RetVT, Op0); 1990 default: return 0; 1991 } 1992} 1993 1994// FastEmit functions for PPCISD::FCTIWZ. 1995 1996unsigned fastEmit_PPCISD_FCTIWZ_MVT_f32_r(MVT RetVT, unsigned Op0) { 1997 if (RetVT.SimpleTy != MVT::f32) 1998 return 0; 1999 if ((Subtarget->hasVSX())) { 2000 return fastEmitInst_r(PPC::XSCVDPSXWSs, &PPC::VSSRCRegClass, Op0); 2001 } 2002 return 0; 2003} 2004 2005unsigned fastEmit_PPCISD_FCTIWZ_MVT_f64_r(MVT RetVT, unsigned Op0) { 2006 if (RetVT.SimpleTy != MVT::f64) 2007 return 0; 2008 if ((Subtarget->hasVSX())) { 2009 return fastEmitInst_r(PPC::XSCVDPSXWS, &PPC::VSFRCRegClass, Op0); 2010 } 2011 if ((Subtarget->hasFPU())) { 2012 return fastEmitInst_r(PPC::FCTIWZ, &PPC::F8RCRegClass, Op0); 2013 } 2014 return 0; 2015} 2016 2017unsigned fastEmit_PPCISD_FCTIWZ_r(MVT VT, MVT RetVT, unsigned Op0) { 2018 switch (VT.SimpleTy) { 2019 case MVT::f32: return fastEmit_PPCISD_FCTIWZ_MVT_f32_r(RetVT, Op0); 2020 case MVT::f64: return fastEmit_PPCISD_FCTIWZ_MVT_f64_r(RetVT, Op0); 2021 default: return 0; 2022 } 2023} 2024 2025// FastEmit functions for PPCISD::FRE. 2026 2027unsigned fastEmit_PPCISD_FRE_MVT_f32_r(MVT RetVT, unsigned Op0) { 2028 if (RetVT.SimpleTy != MVT::f32) 2029 return 0; 2030 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) { 2031 return fastEmitInst_r(PPC::XSRESP, &PPC::VSSRCRegClass, Op0); 2032 } 2033 if ((Subtarget->hasFPU())) { 2034 return fastEmitInst_r(PPC::FRES, &PPC::F4RCRegClass, Op0); 2035 } 2036 return 0; 2037} 2038 2039unsigned fastEmit_PPCISD_FRE_MVT_f64_r(MVT RetVT, unsigned Op0) { 2040 if (RetVT.SimpleTy != MVT::f64) 2041 return 0; 2042 if ((Subtarget->hasVSX())) { 2043 return fastEmitInst_r(PPC::XSREDP, &PPC::VSFRCRegClass, Op0); 2044 } 2045 if ((Subtarget->hasFPU())) { 2046 return fastEmitInst_r(PPC::FRE, &PPC::F8RCRegClass, Op0); 2047 } 2048 return 0; 2049} 2050 2051unsigned fastEmit_PPCISD_FRE_MVT_v4f32_r(MVT RetVT, unsigned Op0) { 2052 if (RetVT.SimpleTy != MVT::v4f32) 2053 return 0; 2054 if ((Subtarget->hasVSX())) { 2055 return fastEmitInst_r(PPC::XVRESP, &PPC::VSRCRegClass, Op0); 2056 } 2057 if ((Subtarget->hasAltivec())) { 2058 return fastEmitInst_r(PPC::VREFP, &PPC::VRRCRegClass, Op0); 2059 } 2060 return 0; 2061} 2062 2063unsigned fastEmit_PPCISD_FRE_MVT_v2f64_r(MVT RetVT, unsigned Op0) { 2064 if (RetVT.SimpleTy != MVT::v2f64) 2065 return 0; 2066 if ((Subtarget->hasVSX())) { 2067 return fastEmitInst_r(PPC::XVREDP, &PPC::VSRCRegClass, Op0); 2068 } 2069 return 0; 2070} 2071 2072unsigned fastEmit_PPCISD_FRE_r(MVT VT, MVT RetVT, unsigned Op0) { 2073 switch (VT.SimpleTy) { 2074 case MVT::f32: return fastEmit_PPCISD_FRE_MVT_f32_r(RetVT, Op0); 2075 case MVT::f64: return fastEmit_PPCISD_FRE_MVT_f64_r(RetVT, Op0); 2076 case MVT::v4f32: return fastEmit_PPCISD_FRE_MVT_v4f32_r(RetVT, Op0); 2077 case MVT::v2f64: return fastEmit_PPCISD_FRE_MVT_v2f64_r(RetVT, Op0); 2078 default: return 0; 2079 } 2080} 2081 2082// FastEmit functions for PPCISD::FRSQRTE. 2083 2084unsigned fastEmit_PPCISD_FRSQRTE_MVT_f32_r(MVT RetVT, unsigned Op0) { 2085 if (RetVT.SimpleTy != MVT::f32) 2086 return 0; 2087 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) { 2088 return fastEmitInst_r(PPC::XSRSQRTESP, &PPC::VSSRCRegClass, Op0); 2089 } 2090 if ((Subtarget->hasFPU())) { 2091 return fastEmitInst_r(PPC::FRSQRTES, &PPC::F4RCRegClass, Op0); 2092 } 2093 return 0; 2094} 2095 2096unsigned fastEmit_PPCISD_FRSQRTE_MVT_f64_r(MVT RetVT, unsigned Op0) { 2097 if (RetVT.SimpleTy != MVT::f64) 2098 return 0; 2099 if ((Subtarget->hasVSX())) { 2100 return fastEmitInst_r(PPC::XSRSQRTEDP, &PPC::VSFRCRegClass, Op0); 2101 } 2102 if ((Subtarget->hasFPU())) { 2103 return fastEmitInst_r(PPC::FRSQRTE, &PPC::F8RCRegClass, Op0); 2104 } 2105 return 0; 2106} 2107 2108unsigned fastEmit_PPCISD_FRSQRTE_MVT_v4f32_r(MVT RetVT, unsigned Op0) { 2109 if (RetVT.SimpleTy != MVT::v4f32) 2110 return 0; 2111 if ((Subtarget->hasVSX())) { 2112 return fastEmitInst_r(PPC::XVRSQRTESP, &PPC::VSRCRegClass, Op0); 2113 } 2114 if ((Subtarget->hasAltivec())) { 2115 return fastEmitInst_r(PPC::VRSQRTEFP, &PPC::VRRCRegClass, Op0); 2116 } 2117 return 0; 2118} 2119 2120unsigned fastEmit_PPCISD_FRSQRTE_MVT_v2f64_r(MVT RetVT, unsigned Op0) { 2121 if (RetVT.SimpleTy != MVT::v2f64) 2122 return 0; 2123 if ((Subtarget->hasVSX())) { 2124 return fastEmitInst_r(PPC::XVRSQRTEDP, &PPC::VSRCRegClass, Op0); 2125 } 2126 return 0; 2127} 2128 2129unsigned fastEmit_PPCISD_FRSQRTE_r(MVT VT, MVT RetVT, unsigned Op0) { 2130 switch (VT.SimpleTy) { 2131 case MVT::f32: return fastEmit_PPCISD_FRSQRTE_MVT_f32_r(RetVT, Op0); 2132 case MVT::f64: return fastEmit_PPCISD_FRSQRTE_MVT_f64_r(RetVT, Op0); 2133 case MVT::v4f32: return fastEmit_PPCISD_FRSQRTE_MVT_v4f32_r(RetVT, Op0); 2134 case MVT::v2f64: return fastEmit_PPCISD_FRSQRTE_MVT_v2f64_r(RetVT, Op0); 2135 default: return 0; 2136 } 2137} 2138 2139// FastEmit functions for PPCISD::FSQRT. 2140 2141unsigned fastEmit_PPCISD_FSQRT_MVT_f64_r(MVT RetVT, unsigned Op0) { 2142 if (RetVT.SimpleTy != MVT::f64) 2143 return 0; 2144 if ((Subtarget->hasVSX())) { 2145 return fastEmitInst_r(PPC::XSSQRTDP, &PPC::VSFRCRegClass, Op0); 2146 } 2147 return fastEmitInst_r(PPC::FSQRT, &PPC::F8RCRegClass, Op0); 2148} 2149 2150unsigned fastEmit_PPCISD_FSQRT_MVT_v4f32_r(MVT RetVT, unsigned Op0) { 2151 if (RetVT.SimpleTy != MVT::v4f32) 2152 return 0; 2153 if ((Subtarget->hasVSX())) { 2154 return fastEmitInst_r(PPC::XVSQRTSP, &PPC::VSRCRegClass, Op0); 2155 } 2156 return 0; 2157} 2158 2159unsigned fastEmit_PPCISD_FSQRT_MVT_v2f64_r(MVT RetVT, unsigned Op0) { 2160 if (RetVT.SimpleTy != MVT::v2f64) 2161 return 0; 2162 if ((Subtarget->hasVSX())) { 2163 return fastEmitInst_r(PPC::XVSQRTDP, &PPC::VSRCRegClass, Op0); 2164 } 2165 return 0; 2166} 2167 2168unsigned fastEmit_PPCISD_FSQRT_r(MVT VT, MVT RetVT, unsigned Op0) { 2169 switch (VT.SimpleTy) { 2170 case MVT::f64: return fastEmit_PPCISD_FSQRT_MVT_f64_r(RetVT, Op0); 2171 case MVT::v4f32: return fastEmit_PPCISD_FSQRT_MVT_v4f32_r(RetVT, Op0); 2172 case MVT::v2f64: return fastEmit_PPCISD_FSQRT_MVT_v2f64_r(RetVT, Op0); 2173 default: return 0; 2174 } 2175} 2176 2177// FastEmit functions for PPCISD::FTSQRT. 2178 2179unsigned fastEmit_PPCISD_FTSQRT_MVT_f64_r(MVT RetVT, unsigned Op0) { 2180 if (RetVT.SimpleTy != MVT::i32) 2181 return 0; 2182 if ((Subtarget->hasVSX())) { 2183 return fastEmitInst_r(PPC::XSTSQRTDP, &PPC::CRRCRegClass, Op0); 2184 } 2185 if ((Subtarget->hasFPU())) { 2186 return fastEmitInst_r(PPC::FTSQRT, &PPC::CRRCRegClass, Op0); 2187 } 2188 return 0; 2189} 2190 2191unsigned fastEmit_PPCISD_FTSQRT_MVT_v4f32_r(MVT RetVT, unsigned Op0) { 2192 if (RetVT.SimpleTy != MVT::i32) 2193 return 0; 2194 if ((Subtarget->hasVSX())) { 2195 return fastEmitInst_r(PPC::XVTSQRTSP, &PPC::CRRCRegClass, Op0); 2196 } 2197 return 0; 2198} 2199 2200unsigned fastEmit_PPCISD_FTSQRT_MVT_v2f64_r(MVT RetVT, unsigned Op0) { 2201 if (RetVT.SimpleTy != MVT::i32) 2202 return 0; 2203 if ((Subtarget->hasVSX())) { 2204 return fastEmitInst_r(PPC::XVTSQRTDP, &PPC::CRRCRegClass, Op0); 2205 } 2206 return 0; 2207} 2208 2209unsigned fastEmit_PPCISD_FTSQRT_r(MVT VT, MVT RetVT, unsigned Op0) { 2210 switch (VT.SimpleTy) { 2211 case MVT::f64: return fastEmit_PPCISD_FTSQRT_MVT_f64_r(RetVT, Op0); 2212 case MVT::v4f32: return fastEmit_PPCISD_FTSQRT_MVT_v4f32_r(RetVT, Op0); 2213 case MVT::v2f64: return fastEmit_PPCISD_FTSQRT_MVT_v2f64_r(RetVT, Op0); 2214 default: return 0; 2215 } 2216} 2217 2218// FastEmit functions for PPCISD::MFVSR. 2219 2220unsigned fastEmit_PPCISD_MFVSR_MVT_f64_MVT_i32_r(unsigned Op0) { 2221 if ((Subtarget->hasDirectMove()) && (Subtarget->hasVSX())) { 2222 return fastEmitInst_r(PPC::MFVSRWZ, &PPC::GPRCRegClass, Op0); 2223 } 2224 return 0; 2225} 2226 2227unsigned fastEmit_PPCISD_MFVSR_MVT_f64_MVT_i64_r(unsigned Op0) { 2228 if ((Subtarget->hasDirectMove()) && (Subtarget->hasVSX())) { 2229 return fastEmitInst_r(PPC::MFVSRD, &PPC::G8RCRegClass, Op0); 2230 } 2231 return 0; 2232} 2233 2234unsigned fastEmit_PPCISD_MFVSR_MVT_f64_r(MVT RetVT, unsigned Op0) { 2235switch (RetVT.SimpleTy) { 2236 case MVT::i32: return fastEmit_PPCISD_MFVSR_MVT_f64_MVT_i32_r(Op0); 2237 case MVT::i64: return fastEmit_PPCISD_MFVSR_MVT_f64_MVT_i64_r(Op0); 2238 default: return 0; 2239} 2240} 2241 2242unsigned fastEmit_PPCISD_MFVSR_r(MVT VT, MVT RetVT, unsigned Op0) { 2243 switch (VT.SimpleTy) { 2244 case MVT::f64: return fastEmit_PPCISD_MFVSR_MVT_f64_r(RetVT, Op0); 2245 default: return 0; 2246 } 2247} 2248 2249// FastEmit functions for PPCISD::MTCTR. 2250 2251unsigned fastEmit_PPCISD_MTCTR_MVT_i32_r(MVT RetVT, unsigned Op0) { 2252 if (RetVT.SimpleTy != MVT::isVoid) 2253 return 0; 2254 return fastEmitInst_r(PPC::MTCTR, &PPC::GPRCRegClass, Op0); 2255} 2256 2257unsigned fastEmit_PPCISD_MTCTR_MVT_i64_r(MVT RetVT, unsigned Op0) { 2258 if (RetVT.SimpleTy != MVT::isVoid) 2259 return 0; 2260 return fastEmitInst_r(PPC::MTCTR8, &PPC::G8RCRegClass, Op0); 2261} 2262 2263unsigned fastEmit_PPCISD_MTCTR_r(MVT VT, MVT RetVT, unsigned Op0) { 2264 switch (VT.SimpleTy) { 2265 case MVT::i32: return fastEmit_PPCISD_MTCTR_MVT_i32_r(RetVT, Op0); 2266 case MVT::i64: return fastEmit_PPCISD_MTCTR_MVT_i64_r(RetVT, Op0); 2267 default: return 0; 2268 } 2269} 2270 2271// FastEmit functions for PPCISD::MTVSRA. 2272 2273unsigned fastEmit_PPCISD_MTVSRA_MVT_i32_r(MVT RetVT, unsigned Op0) { 2274 if (RetVT.SimpleTy != MVT::f64) 2275 return 0; 2276 if ((Subtarget->hasDirectMove()) && (Subtarget->hasVSX())) { 2277 return fastEmitInst_r(PPC::MTVSRWA, &PPC::VSFRCRegClass, Op0); 2278 } 2279 return 0; 2280} 2281 2282unsigned fastEmit_PPCISD_MTVSRA_MVT_i64_r(MVT RetVT, unsigned Op0) { 2283 if (RetVT.SimpleTy != MVT::f64) 2284 return 0; 2285 if ((Subtarget->hasDirectMove()) && (Subtarget->hasVSX())) { 2286 return fastEmitInst_r(PPC::MTVSRD, &PPC::VSFRCRegClass, Op0); 2287 } 2288 return 0; 2289} 2290 2291unsigned fastEmit_PPCISD_MTVSRA_r(MVT VT, MVT RetVT, unsigned Op0) { 2292 switch (VT.SimpleTy) { 2293 case MVT::i32: return fastEmit_PPCISD_MTVSRA_MVT_i32_r(RetVT, Op0); 2294 case MVT::i64: return fastEmit_PPCISD_MTVSRA_MVT_i64_r(RetVT, Op0); 2295 default: return 0; 2296 } 2297} 2298 2299// FastEmit functions for PPCISD::MTVSRZ. 2300 2301unsigned fastEmit_PPCISD_MTVSRZ_MVT_i32_r(MVT RetVT, unsigned Op0) { 2302 if (RetVT.SimpleTy != MVT::f64) 2303 return 0; 2304 if ((Subtarget->hasDirectMove()) && (Subtarget->hasVSX())) { 2305 return fastEmitInst_r(PPC::MTVSRWZ, &PPC::VSFRCRegClass, Op0); 2306 } 2307 return 0; 2308} 2309 2310unsigned fastEmit_PPCISD_MTVSRZ_r(MVT VT, MVT RetVT, unsigned Op0) { 2311 switch (VT.SimpleTy) { 2312 case MVT::i32: return fastEmit_PPCISD_MTVSRZ_MVT_i32_r(RetVT, Op0); 2313 default: return 0; 2314 } 2315} 2316 2317// FastEmit functions for PPCISD::SCALAR_TO_VECTOR_PERMUTED. 2318 2319unsigned fastEmit_PPCISD_SCALAR_TO_VECTOR_PERMUTED_MVT_f32_r(MVT RetVT, unsigned Op0) { 2320 if (RetVT.SimpleTy != MVT::v4f32) 2321 return 0; 2322 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX()) && (Subtarget->isLittleEndian())) { 2323 return fastEmitInst_r(PPC::XSCVDPSPN, &PPC::VSRCRegClass, Op0); 2324 } 2325 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX()) && (!Subtarget->isLittleEndian())) { 2326 return fastEmitInst_r(PPC::XSCVDPSPN, &PPC::VSRCRegClass, Op0); 2327 } 2328 return 0; 2329} 2330 2331unsigned fastEmit_PPCISD_SCALAR_TO_VECTOR_PERMUTED_r(MVT VT, MVT RetVT, unsigned Op0) { 2332 switch (VT.SimpleTy) { 2333 case MVT::f32: return fastEmit_PPCISD_SCALAR_TO_VECTOR_PERMUTED_MVT_f32_r(RetVT, Op0); 2334 default: return 0; 2335 } 2336} 2337 2338// FastEmit functions for PPCISD::STRICT_FCFID. 2339 2340unsigned fastEmit_PPCISD_STRICT_FCFID_MVT_f64_r(MVT RetVT, unsigned Op0) { 2341 if (RetVT.SimpleTy != MVT::f64) 2342 return 0; 2343 if ((Subtarget->hasVSX())) { 2344 return fastEmitInst_r(PPC::XSCVSXDDP, &PPC::VSFRCRegClass, Op0); 2345 } 2346 return fastEmitInst_r(PPC::FCFID, &PPC::F8RCRegClass, Op0); 2347} 2348 2349unsigned fastEmit_PPCISD_STRICT_FCFID_r(MVT VT, MVT RetVT, unsigned Op0) { 2350 switch (VT.SimpleTy) { 2351 case MVT::f64: return fastEmit_PPCISD_STRICT_FCFID_MVT_f64_r(RetVT, Op0); 2352 default: return 0; 2353 } 2354} 2355 2356// FastEmit functions for PPCISD::STRICT_FCFIDS. 2357 2358unsigned fastEmit_PPCISD_STRICT_FCFIDS_MVT_f64_r(MVT RetVT, unsigned Op0) { 2359 if (RetVT.SimpleTy != MVT::f32) 2360 return 0; 2361 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) { 2362 return fastEmitInst_r(PPC::XSCVSXDSP, &PPC::VSSRCRegClass, Op0); 2363 } 2364 return fastEmitInst_r(PPC::FCFIDS, &PPC::F4RCRegClass, Op0); 2365} 2366 2367unsigned fastEmit_PPCISD_STRICT_FCFIDS_r(MVT VT, MVT RetVT, unsigned Op0) { 2368 switch (VT.SimpleTy) { 2369 case MVT::f64: return fastEmit_PPCISD_STRICT_FCFIDS_MVT_f64_r(RetVT, Op0); 2370 default: return 0; 2371 } 2372} 2373 2374// FastEmit functions for PPCISD::STRICT_FCFIDU. 2375 2376unsigned fastEmit_PPCISD_STRICT_FCFIDU_MVT_f64_r(MVT RetVT, unsigned Op0) { 2377 if (RetVT.SimpleTy != MVT::f64) 2378 return 0; 2379 if ((Subtarget->hasVSX())) { 2380 return fastEmitInst_r(PPC::XSCVUXDDP, &PPC::VSFRCRegClass, Op0); 2381 } 2382 return fastEmitInst_r(PPC::FCFIDU, &PPC::F8RCRegClass, Op0); 2383} 2384 2385unsigned fastEmit_PPCISD_STRICT_FCFIDU_r(MVT VT, MVT RetVT, unsigned Op0) { 2386 switch (VT.SimpleTy) { 2387 case MVT::f64: return fastEmit_PPCISD_STRICT_FCFIDU_MVT_f64_r(RetVT, Op0); 2388 default: return 0; 2389 } 2390} 2391 2392// FastEmit functions for PPCISD::STRICT_FCFIDUS. 2393 2394unsigned fastEmit_PPCISD_STRICT_FCFIDUS_MVT_f64_r(MVT RetVT, unsigned Op0) { 2395 if (RetVT.SimpleTy != MVT::f32) 2396 return 0; 2397 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) { 2398 return fastEmitInst_r(PPC::XSCVUXDSP, &PPC::VSSRCRegClass, Op0); 2399 } 2400 return fastEmitInst_r(PPC::FCFIDUS, &PPC::F4RCRegClass, Op0); 2401} 2402 2403unsigned fastEmit_PPCISD_STRICT_FCFIDUS_r(MVT VT, MVT RetVT, unsigned Op0) { 2404 switch (VT.SimpleTy) { 2405 case MVT::f64: return fastEmit_PPCISD_STRICT_FCFIDUS_MVT_f64_r(RetVT, Op0); 2406 default: return 0; 2407 } 2408} 2409 2410// FastEmit functions for PPCISD::STRICT_FCTIDUZ. 2411 2412unsigned fastEmit_PPCISD_STRICT_FCTIDUZ_MVT_f32_r(MVT RetVT, unsigned Op0) { 2413 if (RetVT.SimpleTy != MVT::f32) 2414 return 0; 2415 if ((Subtarget->hasVSX())) { 2416 return fastEmitInst_r(PPC::XSCVDPUXDSs, &PPC::VSSRCRegClass, Op0); 2417 } 2418 return 0; 2419} 2420 2421unsigned fastEmit_PPCISD_STRICT_FCTIDUZ_MVT_f64_r(MVT RetVT, unsigned Op0) { 2422 if (RetVT.SimpleTy != MVT::f64) 2423 return 0; 2424 if ((Subtarget->hasVSX())) { 2425 return fastEmitInst_r(PPC::XSCVDPUXDS, &PPC::VSFRCRegClass, Op0); 2426 } 2427 return fastEmitInst_r(PPC::FCTIDUZ, &PPC::F8RCRegClass, Op0); 2428} 2429 2430unsigned fastEmit_PPCISD_STRICT_FCTIDUZ_r(MVT VT, MVT RetVT, unsigned Op0) { 2431 switch (VT.SimpleTy) { 2432 case MVT::f32: return fastEmit_PPCISD_STRICT_FCTIDUZ_MVT_f32_r(RetVT, Op0); 2433 case MVT::f64: return fastEmit_PPCISD_STRICT_FCTIDUZ_MVT_f64_r(RetVT, Op0); 2434 default: return 0; 2435 } 2436} 2437 2438// FastEmit functions for PPCISD::STRICT_FCTIDZ. 2439 2440unsigned fastEmit_PPCISD_STRICT_FCTIDZ_MVT_f32_r(MVT RetVT, unsigned Op0) { 2441 if (RetVT.SimpleTy != MVT::f32) 2442 return 0; 2443 if ((Subtarget->hasVSX())) { 2444 return fastEmitInst_r(PPC::XSCVDPSXDSs, &PPC::VSSRCRegClass, Op0); 2445 } 2446 return 0; 2447} 2448 2449unsigned fastEmit_PPCISD_STRICT_FCTIDZ_MVT_f64_r(MVT RetVT, unsigned Op0) { 2450 if (RetVT.SimpleTy != MVT::f64) 2451 return 0; 2452 if ((Subtarget->hasVSX())) { 2453 return fastEmitInst_r(PPC::XSCVDPSXDS, &PPC::VSFRCRegClass, Op0); 2454 } 2455 return fastEmitInst_r(PPC::FCTIDZ, &PPC::F8RCRegClass, Op0); 2456} 2457 2458unsigned fastEmit_PPCISD_STRICT_FCTIDZ_r(MVT VT, MVT RetVT, unsigned Op0) { 2459 switch (VT.SimpleTy) { 2460 case MVT::f32: return fastEmit_PPCISD_STRICT_FCTIDZ_MVT_f32_r(RetVT, Op0); 2461 case MVT::f64: return fastEmit_PPCISD_STRICT_FCTIDZ_MVT_f64_r(RetVT, Op0); 2462 default: return 0; 2463 } 2464} 2465 2466// FastEmit functions for PPCISD::STRICT_FCTIWUZ. 2467 2468unsigned fastEmit_PPCISD_STRICT_FCTIWUZ_MVT_f32_r(MVT RetVT, unsigned Op0) { 2469 if (RetVT.SimpleTy != MVT::f32) 2470 return 0; 2471 if ((Subtarget->hasVSX())) { 2472 return fastEmitInst_r(PPC::XSCVDPUXWSs, &PPC::VSSRCRegClass, Op0); 2473 } 2474 return 0; 2475} 2476 2477unsigned fastEmit_PPCISD_STRICT_FCTIWUZ_MVT_f64_r(MVT RetVT, unsigned Op0) { 2478 if (RetVT.SimpleTy != MVT::f64) 2479 return 0; 2480 if ((Subtarget->hasVSX())) { 2481 return fastEmitInst_r(PPC::XSCVDPUXWS, &PPC::VSFRCRegClass, Op0); 2482 } 2483 return fastEmitInst_r(PPC::FCTIWUZ, &PPC::F8RCRegClass, Op0); 2484} 2485 2486unsigned fastEmit_PPCISD_STRICT_FCTIWUZ_r(MVT VT, MVT RetVT, unsigned Op0) { 2487 switch (VT.SimpleTy) { 2488 case MVT::f32: return fastEmit_PPCISD_STRICT_FCTIWUZ_MVT_f32_r(RetVT, Op0); 2489 case MVT::f64: return fastEmit_PPCISD_STRICT_FCTIWUZ_MVT_f64_r(RetVT, Op0); 2490 default: return 0; 2491 } 2492} 2493 2494// FastEmit functions for PPCISD::STRICT_FCTIWZ. 2495 2496unsigned fastEmit_PPCISD_STRICT_FCTIWZ_MVT_f32_r(MVT RetVT, unsigned Op0) { 2497 if (RetVT.SimpleTy != MVT::f32) 2498 return 0; 2499 if ((Subtarget->hasVSX())) { 2500 return fastEmitInst_r(PPC::XSCVDPSXWSs, &PPC::VSSRCRegClass, Op0); 2501 } 2502 return 0; 2503} 2504 2505unsigned fastEmit_PPCISD_STRICT_FCTIWZ_MVT_f64_r(MVT RetVT, unsigned Op0) { 2506 if (RetVT.SimpleTy != MVT::f64) 2507 return 0; 2508 if ((Subtarget->hasVSX())) { 2509 return fastEmitInst_r(PPC::XSCVDPSXWS, &PPC::VSFRCRegClass, Op0); 2510 } 2511 if ((Subtarget->hasFPU())) { 2512 return fastEmitInst_r(PPC::FCTIWZ, &PPC::F8RCRegClass, Op0); 2513 } 2514 return 0; 2515} 2516 2517unsigned fastEmit_PPCISD_STRICT_FCTIWZ_r(MVT VT, MVT RetVT, unsigned Op0) { 2518 switch (VT.SimpleTy) { 2519 case MVT::f32: return fastEmit_PPCISD_STRICT_FCTIWZ_MVT_f32_r(RetVT, Op0); 2520 case MVT::f64: return fastEmit_PPCISD_STRICT_FCTIWZ_MVT_f64_r(RetVT, Op0); 2521 default: return 0; 2522 } 2523} 2524 2525// FastEmit functions for PPCISD::XXMFACC. 2526 2527unsigned fastEmit_PPCISD_XXMFACC_MVT_v512i1_r(MVT RetVT, unsigned Op0) { 2528 if (RetVT.SimpleTy != MVT::v512i1) 2529 return 0; 2530 if ((!Subtarget->isISAFuture()) && (Subtarget->hasMMA())) { 2531 return fastEmitInst_r(PPC::XXMFACC, &PPC::ACCRCRegClass, Op0); 2532 } 2533 return 0; 2534} 2535 2536unsigned fastEmit_PPCISD_XXMFACC_r(MVT VT, MVT RetVT, unsigned Op0) { 2537 switch (VT.SimpleTy) { 2538 case MVT::v512i1: return fastEmit_PPCISD_XXMFACC_MVT_v512i1_r(RetVT, Op0); 2539 default: return 0; 2540 } 2541} 2542 2543// FastEmit functions for PPCISD::XXSPLTI_SP_TO_DP. 2544 2545unsigned fastEmit_PPCISD_XXSPLTI_SP_TO_DP_MVT_i32_r(MVT RetVT, unsigned Op0) { 2546 if (RetVT.SimpleTy != MVT::v2f64) 2547 return 0; 2548 if ((Subtarget->hasPrefixInstrs())) { 2549 return fastEmitInst_r(PPC::XXSPLTIDP, &PPC::VSRCRegClass, Op0); 2550 } 2551 return 0; 2552} 2553 2554unsigned fastEmit_PPCISD_XXSPLTI_SP_TO_DP_r(MVT VT, MVT RetVT, unsigned Op0) { 2555 switch (VT.SimpleTy) { 2556 case MVT::i32: return fastEmit_PPCISD_XXSPLTI_SP_TO_DP_MVT_i32_r(RetVT, Op0); 2557 default: return 0; 2558 } 2559} 2560 2561// Top-level FastEmit function. 2562 2563unsigned fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0) override { 2564 switch (Opcode) { 2565 case ISD::ANY_EXTEND: return fastEmit_ISD_ANY_EXTEND_r(VT, RetVT, Op0); 2566 case ISD::BITCAST: return fastEmit_ISD_BITCAST_r(VT, RetVT, Op0); 2567 case ISD::BSWAP: return fastEmit_ISD_BSWAP_r(VT, RetVT, Op0); 2568 case ISD::CTLZ: return fastEmit_ISD_CTLZ_r(VT, RetVT, Op0); 2569 case ISD::CTPOP: return fastEmit_ISD_CTPOP_r(VT, RetVT, Op0); 2570 case ISD::CTTZ: return fastEmit_ISD_CTTZ_r(VT, RetVT, Op0); 2571 case ISD::FABS: return fastEmit_ISD_FABS_r(VT, RetVT, Op0); 2572 case ISD::FCEIL: return fastEmit_ISD_FCEIL_r(VT, RetVT, Op0); 2573 case ISD::FFLOOR: return fastEmit_ISD_FFLOOR_r(VT, RetVT, Op0); 2574 case ISD::FNEARBYINT: return fastEmit_ISD_FNEARBYINT_r(VT, RetVT, Op0); 2575 case ISD::FNEG: return fastEmit_ISD_FNEG_r(VT, RetVT, Op0); 2576 case ISD::FP_EXTEND: return fastEmit_ISD_FP_EXTEND_r(VT, RetVT, Op0); 2577 case ISD::FP_ROUND: return fastEmit_ISD_FP_ROUND_r(VT, RetVT, Op0); 2578 case ISD::FP_TO_SINT: return fastEmit_ISD_FP_TO_SINT_r(VT, RetVT, Op0); 2579 case ISD::FP_TO_UINT: return fastEmit_ISD_FP_TO_UINT_r(VT, RetVT, Op0); 2580 case ISD::FRINT: return fastEmit_ISD_FRINT_r(VT, RetVT, Op0); 2581 case ISD::FROUND: return fastEmit_ISD_FROUND_r(VT, RetVT, Op0); 2582 case ISD::FSQRT: return fastEmit_ISD_FSQRT_r(VT, RetVT, Op0); 2583 case ISD::FTRUNC: return fastEmit_ISD_FTRUNC_r(VT, RetVT, Op0); 2584 case ISD::SCALAR_TO_VECTOR: return fastEmit_ISD_SCALAR_TO_VECTOR_r(VT, RetVT, Op0); 2585 case ISD::SIGN_EXTEND: return fastEmit_ISD_SIGN_EXTEND_r(VT, RetVT, Op0); 2586 case ISD::SINT_TO_FP: return fastEmit_ISD_SINT_TO_FP_r(VT, RetVT, Op0); 2587 case ISD::STRICT_FCEIL: return fastEmit_ISD_STRICT_FCEIL_r(VT, RetVT, Op0); 2588 case ISD::STRICT_FFLOOR: return fastEmit_ISD_STRICT_FFLOOR_r(VT, RetVT, Op0); 2589 case ISD::STRICT_FP_EXTEND: return fastEmit_ISD_STRICT_FP_EXTEND_r(VT, RetVT, Op0); 2590 case ISD::STRICT_FP_ROUND: return fastEmit_ISD_STRICT_FP_ROUND_r(VT, RetVT, Op0); 2591 case ISD::STRICT_FP_TO_SINT: return fastEmit_ISD_STRICT_FP_TO_SINT_r(VT, RetVT, Op0); 2592 case ISD::STRICT_FP_TO_UINT: return fastEmit_ISD_STRICT_FP_TO_UINT_r(VT, RetVT, Op0); 2593 case ISD::STRICT_FRINT: return fastEmit_ISD_STRICT_FRINT_r(VT, RetVT, Op0); 2594 case ISD::STRICT_FROUND: return fastEmit_ISD_STRICT_FROUND_r(VT, RetVT, Op0); 2595 case ISD::STRICT_FSQRT: return fastEmit_ISD_STRICT_FSQRT_r(VT, RetVT, Op0); 2596 case ISD::STRICT_FTRUNC: return fastEmit_ISD_STRICT_FTRUNC_r(VT, RetVT, Op0); 2597 case ISD::STRICT_SINT_TO_FP: return fastEmit_ISD_STRICT_SINT_TO_FP_r(VT, RetVT, Op0); 2598 case ISD::STRICT_UINT_TO_FP: return fastEmit_ISD_STRICT_UINT_TO_FP_r(VT, RetVT, Op0); 2599 case ISD::TRUNCATE: return fastEmit_ISD_TRUNCATE_r(VT, RetVT, Op0); 2600 case ISD::UINT_TO_FP: return fastEmit_ISD_UINT_TO_FP_r(VT, RetVT, Op0); 2601 case ISD::ZERO_EXTEND: return fastEmit_ISD_ZERO_EXTEND_r(VT, RetVT, Op0); 2602 case PPCISD::FCFID: return fastEmit_PPCISD_FCFID_r(VT, RetVT, Op0); 2603 case PPCISD::FCFIDS: return fastEmit_PPCISD_FCFIDS_r(VT, RetVT, Op0); 2604 case PPCISD::FCFIDU: return fastEmit_PPCISD_FCFIDU_r(VT, RetVT, Op0); 2605 case PPCISD::FCFIDUS: return fastEmit_PPCISD_FCFIDUS_r(VT, RetVT, Op0); 2606 case PPCISD::FCTIDUZ: return fastEmit_PPCISD_FCTIDUZ_r(VT, RetVT, Op0); 2607 case PPCISD::FCTIDZ: return fastEmit_PPCISD_FCTIDZ_r(VT, RetVT, Op0); 2608 case PPCISD::FCTIWUZ: return fastEmit_PPCISD_FCTIWUZ_r(VT, RetVT, Op0); 2609 case PPCISD::FCTIWZ: return fastEmit_PPCISD_FCTIWZ_r(VT, RetVT, Op0); 2610 case PPCISD::FRE: return fastEmit_PPCISD_FRE_r(VT, RetVT, Op0); 2611 case PPCISD::FRSQRTE: return fastEmit_PPCISD_FRSQRTE_r(VT, RetVT, Op0); 2612 case PPCISD::FSQRT: return fastEmit_PPCISD_FSQRT_r(VT, RetVT, Op0); 2613 case PPCISD::FTSQRT: return fastEmit_PPCISD_FTSQRT_r(VT, RetVT, Op0); 2614 case PPCISD::MFVSR: return fastEmit_PPCISD_MFVSR_r(VT, RetVT, Op0); 2615 case PPCISD::MTCTR: return fastEmit_PPCISD_MTCTR_r(VT, RetVT, Op0); 2616 case PPCISD::MTVSRA: return fastEmit_PPCISD_MTVSRA_r(VT, RetVT, Op0); 2617 case PPCISD::MTVSRZ: return fastEmit_PPCISD_MTVSRZ_r(VT, RetVT, Op0); 2618 case PPCISD::SCALAR_TO_VECTOR_PERMUTED: return fastEmit_PPCISD_SCALAR_TO_VECTOR_PERMUTED_r(VT, RetVT, Op0); 2619 case PPCISD::STRICT_FCFID: return fastEmit_PPCISD_STRICT_FCFID_r(VT, RetVT, Op0); 2620 case PPCISD::STRICT_FCFIDS: return fastEmit_PPCISD_STRICT_FCFIDS_r(VT, RetVT, Op0); 2621 case PPCISD::STRICT_FCFIDU: return fastEmit_PPCISD_STRICT_FCFIDU_r(VT, RetVT, Op0); 2622 case PPCISD::STRICT_FCFIDUS: return fastEmit_PPCISD_STRICT_FCFIDUS_r(VT, RetVT, Op0); 2623 case PPCISD::STRICT_FCTIDUZ: return fastEmit_PPCISD_STRICT_FCTIDUZ_r(VT, RetVT, Op0); 2624 case PPCISD::STRICT_FCTIDZ: return fastEmit_PPCISD_STRICT_FCTIDZ_r(VT, RetVT, Op0); 2625 case PPCISD::STRICT_FCTIWUZ: return fastEmit_PPCISD_STRICT_FCTIWUZ_r(VT, RetVT, Op0); 2626 case PPCISD::STRICT_FCTIWZ: return fastEmit_PPCISD_STRICT_FCTIWZ_r(VT, RetVT, Op0); 2627 case PPCISD::XXMFACC: return fastEmit_PPCISD_XXMFACC_r(VT, RetVT, Op0); 2628 case PPCISD::XXSPLTI_SP_TO_DP: return fastEmit_PPCISD_XXSPLTI_SP_TO_DP_r(VT, RetVT, Op0); 2629 default: return 0; 2630 } 2631} 2632 2633// FastEmit functions for ISD::ADD. 2634 2635unsigned fastEmit_ISD_ADD_MVT_i1_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 2636 if (RetVT.SimpleTy != MVT::i1) 2637 return 0; 2638 return fastEmitInst_rr(PPC::CRXOR, &PPC::CRBITRCRegClass, Op0, Op1); 2639} 2640 2641unsigned fastEmit_ISD_ADD_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 2642 if (RetVT.SimpleTy != MVT::i32) 2643 return 0; 2644 return fastEmitInst_rr(PPC::ADD4, &PPC::GPRCRegClass, Op0, Op1); 2645} 2646 2647unsigned fastEmit_ISD_ADD_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 2648 if (RetVT.SimpleTy != MVT::i64) 2649 return 0; 2650 return fastEmitInst_rr(PPC::ADD8, &PPC::G8RCRegClass, Op0, Op1); 2651} 2652 2653unsigned fastEmit_ISD_ADD_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 2654 if (RetVT.SimpleTy != MVT::v16i8) 2655 return 0; 2656 if ((Subtarget->hasAltivec())) { 2657 return fastEmitInst_rr(PPC::VADDUBM, &PPC::VRRCRegClass, Op0, Op1); 2658 } 2659 return 0; 2660} 2661 2662unsigned fastEmit_ISD_ADD_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 2663 if (RetVT.SimpleTy != MVT::v8i16) 2664 return 0; 2665 if ((Subtarget->hasAltivec())) { 2666 return fastEmitInst_rr(PPC::VADDUHM, &PPC::VRRCRegClass, Op0, Op1); 2667 } 2668 return 0; 2669} 2670 2671unsigned fastEmit_ISD_ADD_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 2672 if (RetVT.SimpleTy != MVT::v4i32) 2673 return 0; 2674 if ((Subtarget->hasAltivec())) { 2675 return fastEmitInst_rr(PPC::VADDUWM, &PPC::VRRCRegClass, Op0, Op1); 2676 } 2677 return 0; 2678} 2679 2680unsigned fastEmit_ISD_ADD_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 2681 if (RetVT.SimpleTy != MVT::v2i64) 2682 return 0; 2683 if ((Subtarget->hasP8Altivec())) { 2684 return fastEmitInst_rr(PPC::VADDUDM, &PPC::VRRCRegClass, Op0, Op1); 2685 } 2686 return 0; 2687} 2688 2689unsigned fastEmit_ISD_ADD_MVT_v1i128_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 2690 if (RetVT.SimpleTy != MVT::v1i128) 2691 return 0; 2692 if ((Subtarget->hasP8Altivec())) { 2693 return fastEmitInst_rr(PPC::VADDUQM, &PPC::VRRCRegClass, Op0, Op1); 2694 } 2695 return 0; 2696} 2697 2698unsigned fastEmit_ISD_ADD_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { 2699 switch (VT.SimpleTy) { 2700 case MVT::i1: return fastEmit_ISD_ADD_MVT_i1_rr(RetVT, Op0, Op1); 2701 case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_rr(RetVT, Op0, Op1); 2702 case MVT::i64: return fastEmit_ISD_ADD_MVT_i64_rr(RetVT, Op0, Op1); 2703 case MVT::v16i8: return fastEmit_ISD_ADD_MVT_v16i8_rr(RetVT, Op0, Op1); 2704 case MVT::v8i16: return fastEmit_ISD_ADD_MVT_v8i16_rr(RetVT, Op0, Op1); 2705 case MVT::v4i32: return fastEmit_ISD_ADD_MVT_v4i32_rr(RetVT, Op0, Op1); 2706 case MVT::v2i64: return fastEmit_ISD_ADD_MVT_v2i64_rr(RetVT, Op0, Op1); 2707 case MVT::v1i128: return fastEmit_ISD_ADD_MVT_v1i128_rr(RetVT, Op0, Op1); 2708 default: return 0; 2709 } 2710} 2711 2712// FastEmit functions for ISD::ADDC. 2713 2714unsigned fastEmit_ISD_ADDC_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 2715 if (RetVT.SimpleTy != MVT::i32) 2716 return 0; 2717 return fastEmitInst_rr(PPC::ADDC, &PPC::GPRCRegClass, Op0, Op1); 2718} 2719 2720unsigned fastEmit_ISD_ADDC_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 2721 if (RetVT.SimpleTy != MVT::i64) 2722 return 0; 2723 return fastEmitInst_rr(PPC::ADDC8, &PPC::G8RCRegClass, Op0, Op1); 2724} 2725 2726unsigned fastEmit_ISD_ADDC_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { 2727 switch (VT.SimpleTy) { 2728 case MVT::i32: return fastEmit_ISD_ADDC_MVT_i32_rr(RetVT, Op0, Op1); 2729 case MVT::i64: return fastEmit_ISD_ADDC_MVT_i64_rr(RetVT, Op0, Op1); 2730 default: return 0; 2731 } 2732} 2733 2734// FastEmit functions for ISD::ADDE. 2735 2736unsigned fastEmit_ISD_ADDE_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 2737 if (RetVT.SimpleTy != MVT::i32) 2738 return 0; 2739 return fastEmitInst_rr(PPC::ADDE, &PPC::GPRCRegClass, Op0, Op1); 2740} 2741 2742unsigned fastEmit_ISD_ADDE_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 2743 if (RetVT.SimpleTy != MVT::i64) 2744 return 0; 2745 return fastEmitInst_rr(PPC::ADDE8, &PPC::G8RCRegClass, Op0, Op1); 2746} 2747 2748unsigned fastEmit_ISD_ADDE_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { 2749 switch (VT.SimpleTy) { 2750 case MVT::i32: return fastEmit_ISD_ADDE_MVT_i32_rr(RetVT, Op0, Op1); 2751 case MVT::i64: return fastEmit_ISD_ADDE_MVT_i64_rr(RetVT, Op0, Op1); 2752 default: return 0; 2753 } 2754} 2755 2756// FastEmit functions for ISD::AND. 2757 2758unsigned fastEmit_ISD_AND_MVT_i1_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 2759 if (RetVT.SimpleTy != MVT::i1) 2760 return 0; 2761 return fastEmitInst_rr(PPC::CRAND, &PPC::CRBITRCRegClass, Op0, Op1); 2762} 2763 2764unsigned fastEmit_ISD_AND_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 2765 if (RetVT.SimpleTy != MVT::i32) 2766 return 0; 2767 return fastEmitInst_rr(PPC::AND, &PPC::GPRCRegClass, Op0, Op1); 2768} 2769 2770unsigned fastEmit_ISD_AND_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 2771 if (RetVT.SimpleTy != MVT::i64) 2772 return 0; 2773 return fastEmitInst_rr(PPC::AND8, &PPC::G8RCRegClass, Op0, Op1); 2774} 2775 2776unsigned fastEmit_ISD_AND_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 2777 if (RetVT.SimpleTy != MVT::v4i32) 2778 return 0; 2779 if ((Subtarget->hasVSX())) { 2780 return fastEmitInst_rr(PPC::XXLAND, &PPC::VSRCRegClass, Op0, Op1); 2781 } 2782 if ((Subtarget->hasAltivec())) { 2783 return fastEmitInst_rr(PPC::VAND, &PPC::VRRCRegClass, Op0, Op1); 2784 } 2785 return 0; 2786} 2787 2788unsigned fastEmit_ISD_AND_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { 2789 switch (VT.SimpleTy) { 2790 case MVT::i1: return fastEmit_ISD_AND_MVT_i1_rr(RetVT, Op0, Op1); 2791 case MVT::i32: return fastEmit_ISD_AND_MVT_i32_rr(RetVT, Op0, Op1); 2792 case MVT::i64: return fastEmit_ISD_AND_MVT_i64_rr(RetVT, Op0, Op1); 2793 case MVT::v4i32: return fastEmit_ISD_AND_MVT_v4i32_rr(RetVT, Op0, Op1); 2794 default: return 0; 2795 } 2796} 2797 2798// FastEmit functions for ISD::BUILD_VECTOR. 2799 2800unsigned fastEmit_ISD_BUILD_VECTOR_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 2801 if (RetVT.SimpleTy != MVT::v2i64) 2802 return 0; 2803 if ((Subtarget->hasDirectMove()) && (Subtarget->hasVSX()) && (!Subtarget->isLittleEndian()) && (Subtarget->isISA3_0()) && (Subtarget->isPPC64())) { 2804 return fastEmitInst_rr(PPC::MTVSRDD, &PPC::VSRCRegClass, Op0, Op1); 2805 } 2806 return 0; 2807} 2808 2809unsigned fastEmit_ISD_BUILD_VECTOR_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { 2810 switch (VT.SimpleTy) { 2811 case MVT::i64: return fastEmit_ISD_BUILD_VECTOR_MVT_i64_rr(RetVT, Op0, Op1); 2812 default: return 0; 2813 } 2814} 2815 2816// FastEmit functions for ISD::FADD. 2817 2818unsigned fastEmit_ISD_FADD_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 2819 if (RetVT.SimpleTy != MVT::f32) 2820 return 0; 2821 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) { 2822 return fastEmitInst_rr(PPC::XSADDSP, &PPC::VSSRCRegClass, Op0, Op1); 2823 } 2824 if ((Subtarget->hasSPE())) { 2825 return fastEmitInst_rr(PPC::EFSADD, &PPC::GPRCRegClass, Op0, Op1); 2826 } 2827 if ((Subtarget->hasFPU())) { 2828 return fastEmitInst_rr(PPC::FADDS, &PPC::F4RCRegClass, Op0, Op1); 2829 } 2830 return 0; 2831} 2832 2833unsigned fastEmit_ISD_FADD_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 2834 if (RetVT.SimpleTy != MVT::f64) 2835 return 0; 2836 if ((Subtarget->hasVSX())) { 2837 return fastEmitInst_rr(PPC::XSADDDP, &PPC::VSFRCRegClass, Op0, Op1); 2838 } 2839 if ((Subtarget->hasSPE())) { 2840 return fastEmitInst_rr(PPC::EFDADD, &PPC::SPERCRegClass, Op0, Op1); 2841 } 2842 if ((Subtarget->hasFPU())) { 2843 return fastEmitInst_rr(PPC::FADD, &PPC::F8RCRegClass, Op0, Op1); 2844 } 2845 return 0; 2846} 2847 2848unsigned fastEmit_ISD_FADD_MVT_f128_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 2849 if (RetVT.SimpleTy != MVT::f128) 2850 return 0; 2851 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) { 2852 return fastEmitInst_rr(PPC::XSADDQP, &PPC::VRRCRegClass, Op0, Op1); 2853 } 2854 return 0; 2855} 2856 2857unsigned fastEmit_ISD_FADD_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 2858 if (RetVT.SimpleTy != MVT::v4f32) 2859 return 0; 2860 if ((Subtarget->hasVSX())) { 2861 return fastEmitInst_rr(PPC::XVADDSP, &PPC::VSRCRegClass, Op0, Op1); 2862 } 2863 if ((Subtarget->hasAltivec())) { 2864 return fastEmitInst_rr(PPC::VADDFP, &PPC::VRRCRegClass, Op0, Op1); 2865 } 2866 return 0; 2867} 2868 2869unsigned fastEmit_ISD_FADD_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 2870 if (RetVT.SimpleTy != MVT::v2f64) 2871 return 0; 2872 if ((Subtarget->hasVSX())) { 2873 return fastEmitInst_rr(PPC::XVADDDP, &PPC::VSRCRegClass, Op0, Op1); 2874 } 2875 return 0; 2876} 2877 2878unsigned fastEmit_ISD_FADD_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { 2879 switch (VT.SimpleTy) { 2880 case MVT::f32: return fastEmit_ISD_FADD_MVT_f32_rr(RetVT, Op0, Op1); 2881 case MVT::f64: return fastEmit_ISD_FADD_MVT_f64_rr(RetVT, Op0, Op1); 2882 case MVT::f128: return fastEmit_ISD_FADD_MVT_f128_rr(RetVT, Op0, Op1); 2883 case MVT::v4f32: return fastEmit_ISD_FADD_MVT_v4f32_rr(RetVT, Op0, Op1); 2884 case MVT::v2f64: return fastEmit_ISD_FADD_MVT_v2f64_rr(RetVT, Op0, Op1); 2885 default: return 0; 2886 } 2887} 2888 2889// FastEmit functions for ISD::FDIV. 2890 2891unsigned fastEmit_ISD_FDIV_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 2892 if (RetVT.SimpleTy != MVT::f32) 2893 return 0; 2894 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) { 2895 return fastEmitInst_rr(PPC::XSDIVSP, &PPC::VSSRCRegClass, Op0, Op1); 2896 } 2897 if ((Subtarget->hasSPE())) { 2898 return fastEmitInst_rr(PPC::EFSDIV, &PPC::GPRCRegClass, Op0, Op1); 2899 } 2900 if ((Subtarget->hasFPU())) { 2901 return fastEmitInst_rr(PPC::FDIVS, &PPC::F4RCRegClass, Op0, Op1); 2902 } 2903 return 0; 2904} 2905 2906unsigned fastEmit_ISD_FDIV_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 2907 if (RetVT.SimpleTy != MVT::f64) 2908 return 0; 2909 if ((Subtarget->hasVSX())) { 2910 return fastEmitInst_rr(PPC::XSDIVDP, &PPC::VSFRCRegClass, Op0, Op1); 2911 } 2912 if ((Subtarget->hasSPE())) { 2913 return fastEmitInst_rr(PPC::EFDDIV, &PPC::SPERCRegClass, Op0, Op1); 2914 } 2915 if ((Subtarget->hasFPU())) { 2916 return fastEmitInst_rr(PPC::FDIV, &PPC::F8RCRegClass, Op0, Op1); 2917 } 2918 return 0; 2919} 2920 2921unsigned fastEmit_ISD_FDIV_MVT_f128_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 2922 if (RetVT.SimpleTy != MVT::f128) 2923 return 0; 2924 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) { 2925 return fastEmitInst_rr(PPC::XSDIVQP, &PPC::VRRCRegClass, Op0, Op1); 2926 } 2927 return 0; 2928} 2929 2930unsigned fastEmit_ISD_FDIV_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 2931 if (RetVT.SimpleTy != MVT::v4f32) 2932 return 0; 2933 if ((Subtarget->hasVSX())) { 2934 return fastEmitInst_rr(PPC::XVDIVSP, &PPC::VSRCRegClass, Op0, Op1); 2935 } 2936 return 0; 2937} 2938 2939unsigned fastEmit_ISD_FDIV_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 2940 if (RetVT.SimpleTy != MVT::v2f64) 2941 return 0; 2942 if ((Subtarget->hasVSX())) { 2943 return fastEmitInst_rr(PPC::XVDIVDP, &PPC::VSRCRegClass, Op0, Op1); 2944 } 2945 return 0; 2946} 2947 2948unsigned fastEmit_ISD_FDIV_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { 2949 switch (VT.SimpleTy) { 2950 case MVT::f32: return fastEmit_ISD_FDIV_MVT_f32_rr(RetVT, Op0, Op1); 2951 case MVT::f64: return fastEmit_ISD_FDIV_MVT_f64_rr(RetVT, Op0, Op1); 2952 case MVT::f128: return fastEmit_ISD_FDIV_MVT_f128_rr(RetVT, Op0, Op1); 2953 case MVT::v4f32: return fastEmit_ISD_FDIV_MVT_v4f32_rr(RetVT, Op0, Op1); 2954 case MVT::v2f64: return fastEmit_ISD_FDIV_MVT_v2f64_rr(RetVT, Op0, Op1); 2955 default: return 0; 2956 } 2957} 2958 2959// FastEmit functions for ISD::FMAXNUM. 2960 2961unsigned fastEmit_ISD_FMAXNUM_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 2962 if (RetVT.SimpleTy != MVT::v4f32) 2963 return 0; 2964 if ((Subtarget->hasVSX())) { 2965 return fastEmitInst_rr(PPC::XVMAXSP, &PPC::VSRCRegClass, Op0, Op1); 2966 } 2967 return 0; 2968} 2969 2970unsigned fastEmit_ISD_FMAXNUM_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 2971 if (RetVT.SimpleTy != MVT::v2f64) 2972 return 0; 2973 if ((Subtarget->hasVSX())) { 2974 return fastEmitInst_rr(PPC::XVMAXDP, &PPC::VSRCRegClass, Op0, Op1); 2975 } 2976 return 0; 2977} 2978 2979unsigned fastEmit_ISD_FMAXNUM_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { 2980 switch (VT.SimpleTy) { 2981 case MVT::v4f32: return fastEmit_ISD_FMAXNUM_MVT_v4f32_rr(RetVT, Op0, Op1); 2982 case MVT::v2f64: return fastEmit_ISD_FMAXNUM_MVT_v2f64_rr(RetVT, Op0, Op1); 2983 default: return 0; 2984 } 2985} 2986 2987// FastEmit functions for ISD::FMAXNUM_IEEE. 2988 2989unsigned fastEmit_ISD_FMAXNUM_IEEE_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 2990 if (RetVT.SimpleTy != MVT::f64) 2991 return 0; 2992 if ((Subtarget->hasVSX())) { 2993 return fastEmitInst_rr(PPC::XSMAXDP, &PPC::VSFRCRegClass, Op0, Op1); 2994 } 2995 return 0; 2996} 2997 2998unsigned fastEmit_ISD_FMAXNUM_IEEE_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { 2999 switch (VT.SimpleTy) { 3000 case MVT::f64: return fastEmit_ISD_FMAXNUM_IEEE_MVT_f64_rr(RetVT, Op0, Op1); 3001 default: return 0; 3002 } 3003} 3004 3005// FastEmit functions for ISD::FMINNUM. 3006 3007unsigned fastEmit_ISD_FMINNUM_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3008 if (RetVT.SimpleTy != MVT::v4f32) 3009 return 0; 3010 if ((Subtarget->hasVSX())) { 3011 return fastEmitInst_rr(PPC::XVMINSP, &PPC::VSRCRegClass, Op0, Op1); 3012 } 3013 return 0; 3014} 3015 3016unsigned fastEmit_ISD_FMINNUM_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3017 if (RetVT.SimpleTy != MVT::v2f64) 3018 return 0; 3019 if ((Subtarget->hasVSX())) { 3020 return fastEmitInst_rr(PPC::XVMINDP, &PPC::VSRCRegClass, Op0, Op1); 3021 } 3022 return 0; 3023} 3024 3025unsigned fastEmit_ISD_FMINNUM_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { 3026 switch (VT.SimpleTy) { 3027 case MVT::v4f32: return fastEmit_ISD_FMINNUM_MVT_v4f32_rr(RetVT, Op0, Op1); 3028 case MVT::v2f64: return fastEmit_ISD_FMINNUM_MVT_v2f64_rr(RetVT, Op0, Op1); 3029 default: return 0; 3030 } 3031} 3032 3033// FastEmit functions for ISD::FMINNUM_IEEE. 3034 3035unsigned fastEmit_ISD_FMINNUM_IEEE_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3036 if (RetVT.SimpleTy != MVT::f64) 3037 return 0; 3038 if ((Subtarget->hasVSX())) { 3039 return fastEmitInst_rr(PPC::XSMINDP, &PPC::VSFRCRegClass, Op0, Op1); 3040 } 3041 return 0; 3042} 3043 3044unsigned fastEmit_ISD_FMINNUM_IEEE_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { 3045 switch (VT.SimpleTy) { 3046 case MVT::f64: return fastEmit_ISD_FMINNUM_IEEE_MVT_f64_rr(RetVT, Op0, Op1); 3047 default: return 0; 3048 } 3049} 3050 3051// FastEmit functions for ISD::FMUL. 3052 3053unsigned fastEmit_ISD_FMUL_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3054 if (RetVT.SimpleTy != MVT::f32) 3055 return 0; 3056 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) { 3057 return fastEmitInst_rr(PPC::XSMULSP, &PPC::VSSRCRegClass, Op0, Op1); 3058 } 3059 if ((Subtarget->hasSPE())) { 3060 return fastEmitInst_rr(PPC::EFSMUL, &PPC::GPRCRegClass, Op0, Op1); 3061 } 3062 if ((Subtarget->hasFPU())) { 3063 return fastEmitInst_rr(PPC::FMULS, &PPC::F4RCRegClass, Op0, Op1); 3064 } 3065 return 0; 3066} 3067 3068unsigned fastEmit_ISD_FMUL_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3069 if (RetVT.SimpleTy != MVT::f64) 3070 return 0; 3071 if ((Subtarget->hasVSX())) { 3072 return fastEmitInst_rr(PPC::XSMULDP, &PPC::VSFRCRegClass, Op0, Op1); 3073 } 3074 if ((Subtarget->hasSPE())) { 3075 return fastEmitInst_rr(PPC::EFDMUL, &PPC::SPERCRegClass, Op0, Op1); 3076 } 3077 if ((Subtarget->hasFPU())) { 3078 return fastEmitInst_rr(PPC::FMUL, &PPC::F8RCRegClass, Op0, Op1); 3079 } 3080 return 0; 3081} 3082 3083unsigned fastEmit_ISD_FMUL_MVT_f128_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3084 if (RetVT.SimpleTy != MVT::f128) 3085 return 0; 3086 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) { 3087 return fastEmitInst_rr(PPC::XSMULQP, &PPC::VRRCRegClass, Op0, Op1); 3088 } 3089 return 0; 3090} 3091 3092unsigned fastEmit_ISD_FMUL_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3093 if (RetVT.SimpleTy != MVT::v4f32) 3094 return 0; 3095 if ((Subtarget->hasVSX())) { 3096 return fastEmitInst_rr(PPC::XVMULSP, &PPC::VSRCRegClass, Op0, Op1); 3097 } 3098 return 0; 3099} 3100 3101unsigned fastEmit_ISD_FMUL_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3102 if (RetVT.SimpleTy != MVT::v2f64) 3103 return 0; 3104 if ((Subtarget->hasVSX())) { 3105 return fastEmitInst_rr(PPC::XVMULDP, &PPC::VSRCRegClass, Op0, Op1); 3106 } 3107 return 0; 3108} 3109 3110unsigned fastEmit_ISD_FMUL_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { 3111 switch (VT.SimpleTy) { 3112 case MVT::f32: return fastEmit_ISD_FMUL_MVT_f32_rr(RetVT, Op0, Op1); 3113 case MVT::f64: return fastEmit_ISD_FMUL_MVT_f64_rr(RetVT, Op0, Op1); 3114 case MVT::f128: return fastEmit_ISD_FMUL_MVT_f128_rr(RetVT, Op0, Op1); 3115 case MVT::v4f32: return fastEmit_ISD_FMUL_MVT_v4f32_rr(RetVT, Op0, Op1); 3116 case MVT::v2f64: return fastEmit_ISD_FMUL_MVT_v2f64_rr(RetVT, Op0, Op1); 3117 default: return 0; 3118 } 3119} 3120 3121// FastEmit functions for ISD::FSUB. 3122 3123unsigned fastEmit_ISD_FSUB_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3124 if (RetVT.SimpleTy != MVT::f32) 3125 return 0; 3126 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) { 3127 return fastEmitInst_rr(PPC::XSSUBSP, &PPC::VSSRCRegClass, Op0, Op1); 3128 } 3129 if ((Subtarget->hasSPE())) { 3130 return fastEmitInst_rr(PPC::EFSSUB, &PPC::GPRCRegClass, Op0, Op1); 3131 } 3132 if ((Subtarget->hasFPU())) { 3133 return fastEmitInst_rr(PPC::FSUBS, &PPC::F4RCRegClass, Op0, Op1); 3134 } 3135 return 0; 3136} 3137 3138unsigned fastEmit_ISD_FSUB_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3139 if (RetVT.SimpleTy != MVT::f64) 3140 return 0; 3141 if ((Subtarget->hasVSX())) { 3142 return fastEmitInst_rr(PPC::XSSUBDP, &PPC::VSFRCRegClass, Op0, Op1); 3143 } 3144 if ((Subtarget->hasSPE())) { 3145 return fastEmitInst_rr(PPC::EFDSUB, &PPC::SPERCRegClass, Op0, Op1); 3146 } 3147 if ((Subtarget->hasFPU())) { 3148 return fastEmitInst_rr(PPC::FSUB, &PPC::F8RCRegClass, Op0, Op1); 3149 } 3150 return 0; 3151} 3152 3153unsigned fastEmit_ISD_FSUB_MVT_f128_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3154 if (RetVT.SimpleTy != MVT::f128) 3155 return 0; 3156 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) { 3157 return fastEmitInst_rr(PPC::XSSUBQP, &PPC::VRRCRegClass, Op0, Op1); 3158 } 3159 return 0; 3160} 3161 3162unsigned fastEmit_ISD_FSUB_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3163 if (RetVT.SimpleTy != MVT::v4f32) 3164 return 0; 3165 if ((Subtarget->hasVSX())) { 3166 return fastEmitInst_rr(PPC::XVSUBSP, &PPC::VSRCRegClass, Op0, Op1); 3167 } 3168 if ((Subtarget->hasAltivec())) { 3169 return fastEmitInst_rr(PPC::VSUBFP, &PPC::VRRCRegClass, Op0, Op1); 3170 } 3171 return 0; 3172} 3173 3174unsigned fastEmit_ISD_FSUB_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3175 if (RetVT.SimpleTy != MVT::v2f64) 3176 return 0; 3177 if ((Subtarget->hasVSX())) { 3178 return fastEmitInst_rr(PPC::XVSUBDP, &PPC::VSRCRegClass, Op0, Op1); 3179 } 3180 return 0; 3181} 3182 3183unsigned fastEmit_ISD_FSUB_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { 3184 switch (VT.SimpleTy) { 3185 case MVT::f32: return fastEmit_ISD_FSUB_MVT_f32_rr(RetVT, Op0, Op1); 3186 case MVT::f64: return fastEmit_ISD_FSUB_MVT_f64_rr(RetVT, Op0, Op1); 3187 case MVT::f128: return fastEmit_ISD_FSUB_MVT_f128_rr(RetVT, Op0, Op1); 3188 case MVT::v4f32: return fastEmit_ISD_FSUB_MVT_v4f32_rr(RetVT, Op0, Op1); 3189 case MVT::v2f64: return fastEmit_ISD_FSUB_MVT_v2f64_rr(RetVT, Op0, Op1); 3190 default: return 0; 3191 } 3192} 3193 3194// FastEmit functions for ISD::MUL. 3195 3196unsigned fastEmit_ISD_MUL_MVT_i1_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3197 if (RetVT.SimpleTy != MVT::i1) 3198 return 0; 3199 return fastEmitInst_rr(PPC::CRAND, &PPC::CRBITRCRegClass, Op0, Op1); 3200} 3201 3202unsigned fastEmit_ISD_MUL_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3203 if (RetVT.SimpleTy != MVT::i32) 3204 return 0; 3205 return fastEmitInst_rr(PPC::MULLW, &PPC::GPRCRegClass, Op0, Op1); 3206} 3207 3208unsigned fastEmit_ISD_MUL_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3209 if (RetVT.SimpleTy != MVT::i64) 3210 return 0; 3211 return fastEmitInst_rr(PPC::MULLD, &PPC::G8RCRegClass, Op0, Op1); 3212} 3213 3214unsigned fastEmit_ISD_MUL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3215 if (RetVT.SimpleTy != MVT::v4i32) 3216 return 0; 3217 if ((Subtarget->hasP8Altivec())) { 3218 return fastEmitInst_rr(PPC::VMULUWM, &PPC::VRRCRegClass, Op0, Op1); 3219 } 3220 return 0; 3221} 3222 3223unsigned fastEmit_ISD_MUL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3224 if (RetVT.SimpleTy != MVT::v2i64) 3225 return 0; 3226 if ((Subtarget->isISA3_1())) { 3227 return fastEmitInst_rr(PPC::VMULLD, &PPC::VRRCRegClass, Op0, Op1); 3228 } 3229 return 0; 3230} 3231 3232unsigned fastEmit_ISD_MUL_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { 3233 switch (VT.SimpleTy) { 3234 case MVT::i1: return fastEmit_ISD_MUL_MVT_i1_rr(RetVT, Op0, Op1); 3235 case MVT::i32: return fastEmit_ISD_MUL_MVT_i32_rr(RetVT, Op0, Op1); 3236 case MVT::i64: return fastEmit_ISD_MUL_MVT_i64_rr(RetVT, Op0, Op1); 3237 case MVT::v4i32: return fastEmit_ISD_MUL_MVT_v4i32_rr(RetVT, Op0, Op1); 3238 case MVT::v2i64: return fastEmit_ISD_MUL_MVT_v2i64_rr(RetVT, Op0, Op1); 3239 default: return 0; 3240 } 3241} 3242 3243// FastEmit functions for ISD::MULHS. 3244 3245unsigned fastEmit_ISD_MULHS_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3246 if (RetVT.SimpleTy != MVT::i32) 3247 return 0; 3248 return fastEmitInst_rr(PPC::MULHW, &PPC::GPRCRegClass, Op0, Op1); 3249} 3250 3251unsigned fastEmit_ISD_MULHS_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3252 if (RetVT.SimpleTy != MVT::i64) 3253 return 0; 3254 return fastEmitInst_rr(PPC::MULHD, &PPC::G8RCRegClass, Op0, Op1); 3255} 3256 3257unsigned fastEmit_ISD_MULHS_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3258 if (RetVT.SimpleTy != MVT::v4i32) 3259 return 0; 3260 if ((Subtarget->isISA3_1())) { 3261 return fastEmitInst_rr(PPC::VMULHSW, &PPC::VRRCRegClass, Op0, Op1); 3262 } 3263 return 0; 3264} 3265 3266unsigned fastEmit_ISD_MULHS_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3267 if (RetVT.SimpleTy != MVT::v2i64) 3268 return 0; 3269 if ((Subtarget->isISA3_1())) { 3270 return fastEmitInst_rr(PPC::VMULHSD, &PPC::VRRCRegClass, Op0, Op1); 3271 } 3272 return 0; 3273} 3274 3275unsigned fastEmit_ISD_MULHS_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { 3276 switch (VT.SimpleTy) { 3277 case MVT::i32: return fastEmit_ISD_MULHS_MVT_i32_rr(RetVT, Op0, Op1); 3278 case MVT::i64: return fastEmit_ISD_MULHS_MVT_i64_rr(RetVT, Op0, Op1); 3279 case MVT::v4i32: return fastEmit_ISD_MULHS_MVT_v4i32_rr(RetVT, Op0, Op1); 3280 case MVT::v2i64: return fastEmit_ISD_MULHS_MVT_v2i64_rr(RetVT, Op0, Op1); 3281 default: return 0; 3282 } 3283} 3284 3285// FastEmit functions for ISD::MULHU. 3286 3287unsigned fastEmit_ISD_MULHU_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3288 if (RetVT.SimpleTy != MVT::i32) 3289 return 0; 3290 return fastEmitInst_rr(PPC::MULHWU, &PPC::GPRCRegClass, Op0, Op1); 3291} 3292 3293unsigned fastEmit_ISD_MULHU_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3294 if (RetVT.SimpleTy != MVT::i64) 3295 return 0; 3296 return fastEmitInst_rr(PPC::MULHDU, &PPC::G8RCRegClass, Op0, Op1); 3297} 3298 3299unsigned fastEmit_ISD_MULHU_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3300 if (RetVT.SimpleTy != MVT::v4i32) 3301 return 0; 3302 if ((Subtarget->isISA3_1())) { 3303 return fastEmitInst_rr(PPC::VMULHUW, &PPC::VRRCRegClass, Op0, Op1); 3304 } 3305 return 0; 3306} 3307 3308unsigned fastEmit_ISD_MULHU_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3309 if (RetVT.SimpleTy != MVT::v2i64) 3310 return 0; 3311 if ((Subtarget->isISA3_1())) { 3312 return fastEmitInst_rr(PPC::VMULHUD, &PPC::VRRCRegClass, Op0, Op1); 3313 } 3314 return 0; 3315} 3316 3317unsigned fastEmit_ISD_MULHU_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { 3318 switch (VT.SimpleTy) { 3319 case MVT::i32: return fastEmit_ISD_MULHU_MVT_i32_rr(RetVT, Op0, Op1); 3320 case MVT::i64: return fastEmit_ISD_MULHU_MVT_i64_rr(RetVT, Op0, Op1); 3321 case MVT::v4i32: return fastEmit_ISD_MULHU_MVT_v4i32_rr(RetVT, Op0, Op1); 3322 case MVT::v2i64: return fastEmit_ISD_MULHU_MVT_v2i64_rr(RetVT, Op0, Op1); 3323 default: return 0; 3324 } 3325} 3326 3327// FastEmit functions for ISD::OR. 3328 3329unsigned fastEmit_ISD_OR_MVT_i1_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3330 if (RetVT.SimpleTy != MVT::i1) 3331 return 0; 3332 return fastEmitInst_rr(PPC::CROR, &PPC::CRBITRCRegClass, Op0, Op1); 3333} 3334 3335unsigned fastEmit_ISD_OR_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3336 if (RetVT.SimpleTy != MVT::i32) 3337 return 0; 3338 return fastEmitInst_rr(PPC::OR, &PPC::GPRCRegClass, Op0, Op1); 3339} 3340 3341unsigned fastEmit_ISD_OR_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3342 if (RetVT.SimpleTy != MVT::i64) 3343 return 0; 3344 return fastEmitInst_rr(PPC::OR8, &PPC::G8RCRegClass, Op0, Op1); 3345} 3346 3347unsigned fastEmit_ISD_OR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3348 if (RetVT.SimpleTy != MVT::v4i32) 3349 return 0; 3350 if ((Subtarget->hasVSX())) { 3351 return fastEmitInst_rr(PPC::XXLOR, &PPC::VSRCRegClass, Op0, Op1); 3352 } 3353 if ((Subtarget->hasAltivec())) { 3354 return fastEmitInst_rr(PPC::VOR, &PPC::VRRCRegClass, Op0, Op1); 3355 } 3356 return 0; 3357} 3358 3359unsigned fastEmit_ISD_OR_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { 3360 switch (VT.SimpleTy) { 3361 case MVT::i1: return fastEmit_ISD_OR_MVT_i1_rr(RetVT, Op0, Op1); 3362 case MVT::i32: return fastEmit_ISD_OR_MVT_i32_rr(RetVT, Op0, Op1); 3363 case MVT::i64: return fastEmit_ISD_OR_MVT_i64_rr(RetVT, Op0, Op1); 3364 case MVT::v4i32: return fastEmit_ISD_OR_MVT_v4i32_rr(RetVT, Op0, Op1); 3365 default: return 0; 3366 } 3367} 3368 3369// FastEmit functions for ISD::ROTL. 3370 3371unsigned fastEmit_ISD_ROTL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3372 if (RetVT.SimpleTy != MVT::v16i8) 3373 return 0; 3374 if ((Subtarget->hasAltivec())) { 3375 return fastEmitInst_rr(PPC::VRLB, &PPC::VRRCRegClass, Op0, Op1); 3376 } 3377 return 0; 3378} 3379 3380unsigned fastEmit_ISD_ROTL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3381 if (RetVT.SimpleTy != MVT::v8i16) 3382 return 0; 3383 if ((Subtarget->hasAltivec())) { 3384 return fastEmitInst_rr(PPC::VRLH, &PPC::VRRCRegClass, Op0, Op1); 3385 } 3386 return 0; 3387} 3388 3389unsigned fastEmit_ISD_ROTL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3390 if (RetVT.SimpleTy != MVT::v4i32) 3391 return 0; 3392 if ((Subtarget->hasAltivec())) { 3393 return fastEmitInst_rr(PPC::VRLW, &PPC::VRRCRegClass, Op0, Op1); 3394 } 3395 return 0; 3396} 3397 3398unsigned fastEmit_ISD_ROTL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3399 if (RetVT.SimpleTy != MVT::v2i64) 3400 return 0; 3401 if ((Subtarget->hasP8Altivec())) { 3402 return fastEmitInst_rr(PPC::VRLD, &PPC::VRRCRegClass, Op0, Op1); 3403 } 3404 return 0; 3405} 3406 3407unsigned fastEmit_ISD_ROTL_MVT_v1i128_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3408 if (RetVT.SimpleTy != MVT::v1i128) 3409 return 0; 3410 if ((Subtarget->isISA3_1())) { 3411 return fastEmitInst_rr(PPC::VRLQ, &PPC::VRRCRegClass, Op0, Op1); 3412 } 3413 return 0; 3414} 3415 3416unsigned fastEmit_ISD_ROTL_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { 3417 switch (VT.SimpleTy) { 3418 case MVT::v16i8: return fastEmit_ISD_ROTL_MVT_v16i8_rr(RetVT, Op0, Op1); 3419 case MVT::v8i16: return fastEmit_ISD_ROTL_MVT_v8i16_rr(RetVT, Op0, Op1); 3420 case MVT::v4i32: return fastEmit_ISD_ROTL_MVT_v4i32_rr(RetVT, Op0, Op1); 3421 case MVT::v2i64: return fastEmit_ISD_ROTL_MVT_v2i64_rr(RetVT, Op0, Op1); 3422 case MVT::v1i128: return fastEmit_ISD_ROTL_MVT_v1i128_rr(RetVT, Op0, Op1); 3423 default: return 0; 3424 } 3425} 3426 3427// FastEmit functions for ISD::SADDSAT. 3428 3429unsigned fastEmit_ISD_SADDSAT_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3430 if (RetVT.SimpleTy != MVT::v16i8) 3431 return 0; 3432 if ((Subtarget->hasAltivec())) { 3433 return fastEmitInst_rr(PPC::VADDSBS, &PPC::VRRCRegClass, Op0, Op1); 3434 } 3435 return 0; 3436} 3437 3438unsigned fastEmit_ISD_SADDSAT_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3439 if (RetVT.SimpleTy != MVT::v8i16) 3440 return 0; 3441 if ((Subtarget->hasAltivec())) { 3442 return fastEmitInst_rr(PPC::VADDSHS, &PPC::VRRCRegClass, Op0, Op1); 3443 } 3444 return 0; 3445} 3446 3447unsigned fastEmit_ISD_SADDSAT_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3448 if (RetVT.SimpleTy != MVT::v4i32) 3449 return 0; 3450 if ((Subtarget->hasAltivec())) { 3451 return fastEmitInst_rr(PPC::VADDSWS, &PPC::VRRCRegClass, Op0, Op1); 3452 } 3453 return 0; 3454} 3455 3456unsigned fastEmit_ISD_SADDSAT_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { 3457 switch (VT.SimpleTy) { 3458 case MVT::v16i8: return fastEmit_ISD_SADDSAT_MVT_v16i8_rr(RetVT, Op0, Op1); 3459 case MVT::v8i16: return fastEmit_ISD_SADDSAT_MVT_v8i16_rr(RetVT, Op0, Op1); 3460 case MVT::v4i32: return fastEmit_ISD_SADDSAT_MVT_v4i32_rr(RetVT, Op0, Op1); 3461 default: return 0; 3462 } 3463} 3464 3465// FastEmit functions for ISD::SDIV. 3466 3467unsigned fastEmit_ISD_SDIV_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3468 if (RetVT.SimpleTy != MVT::i32) 3469 return 0; 3470 return fastEmitInst_rr(PPC::DIVW, &PPC::GPRCRegClass, Op0, Op1); 3471} 3472 3473unsigned fastEmit_ISD_SDIV_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3474 if (RetVT.SimpleTy != MVT::i64) 3475 return 0; 3476 return fastEmitInst_rr(PPC::DIVD, &PPC::G8RCRegClass, Op0, Op1); 3477} 3478 3479unsigned fastEmit_ISD_SDIV_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3480 if (RetVT.SimpleTy != MVT::v4i32) 3481 return 0; 3482 if ((Subtarget->isISA3_1())) { 3483 return fastEmitInst_rr(PPC::VDIVSW, &PPC::VRRCRegClass, Op0, Op1); 3484 } 3485 return 0; 3486} 3487 3488unsigned fastEmit_ISD_SDIV_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3489 if (RetVT.SimpleTy != MVT::v2i64) 3490 return 0; 3491 if ((Subtarget->isISA3_1())) { 3492 return fastEmitInst_rr(PPC::VDIVSD, &PPC::VRRCRegClass, Op0, Op1); 3493 } 3494 return 0; 3495} 3496 3497unsigned fastEmit_ISD_SDIV_MVT_v1i128_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3498 if (RetVT.SimpleTy != MVT::v1i128) 3499 return 0; 3500 if ((Subtarget->isISA3_1())) { 3501 return fastEmitInst_rr(PPC::VDIVSQ, &PPC::VRRCRegClass, Op0, Op1); 3502 } 3503 return 0; 3504} 3505 3506unsigned fastEmit_ISD_SDIV_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { 3507 switch (VT.SimpleTy) { 3508 case MVT::i32: return fastEmit_ISD_SDIV_MVT_i32_rr(RetVT, Op0, Op1); 3509 case MVT::i64: return fastEmit_ISD_SDIV_MVT_i64_rr(RetVT, Op0, Op1); 3510 case MVT::v4i32: return fastEmit_ISD_SDIV_MVT_v4i32_rr(RetVT, Op0, Op1); 3511 case MVT::v2i64: return fastEmit_ISD_SDIV_MVT_v2i64_rr(RetVT, Op0, Op1); 3512 case MVT::v1i128: return fastEmit_ISD_SDIV_MVT_v1i128_rr(RetVT, Op0, Op1); 3513 default: return 0; 3514 } 3515} 3516 3517// FastEmit functions for ISD::SHL. 3518 3519unsigned fastEmit_ISD_SHL_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3520 if (RetVT.SimpleTy != MVT::i32) 3521 return 0; 3522 return fastEmitInst_rr(PPC::SLW, &PPC::GPRCRegClass, Op0, Op1); 3523} 3524 3525unsigned fastEmit_ISD_SHL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3526 if (RetVT.SimpleTy != MVT::v16i8) 3527 return 0; 3528 if ((Subtarget->hasAltivec())) { 3529 return fastEmitInst_rr(PPC::VSLB, &PPC::VRRCRegClass, Op0, Op1); 3530 } 3531 return 0; 3532} 3533 3534unsigned fastEmit_ISD_SHL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3535 if (RetVT.SimpleTy != MVT::v8i16) 3536 return 0; 3537 if ((Subtarget->hasAltivec())) { 3538 return fastEmitInst_rr(PPC::VSLH, &PPC::VRRCRegClass, Op0, Op1); 3539 } 3540 return 0; 3541} 3542 3543unsigned fastEmit_ISD_SHL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3544 if (RetVT.SimpleTy != MVT::v4i32) 3545 return 0; 3546 if ((Subtarget->hasAltivec())) { 3547 return fastEmitInst_rr(PPC::VSLW, &PPC::VRRCRegClass, Op0, Op1); 3548 } 3549 return 0; 3550} 3551 3552unsigned fastEmit_ISD_SHL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3553 if (RetVT.SimpleTy != MVT::v2i64) 3554 return 0; 3555 if ((Subtarget->hasP8Altivec())) { 3556 return fastEmitInst_rr(PPC::VSLD, &PPC::VRRCRegClass, Op0, Op1); 3557 } 3558 return 0; 3559} 3560 3561unsigned fastEmit_ISD_SHL_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { 3562 switch (VT.SimpleTy) { 3563 case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_rr(RetVT, Op0, Op1); 3564 case MVT::v16i8: return fastEmit_ISD_SHL_MVT_v16i8_rr(RetVT, Op0, Op1); 3565 case MVT::v8i16: return fastEmit_ISD_SHL_MVT_v8i16_rr(RetVT, Op0, Op1); 3566 case MVT::v4i32: return fastEmit_ISD_SHL_MVT_v4i32_rr(RetVT, Op0, Op1); 3567 case MVT::v2i64: return fastEmit_ISD_SHL_MVT_v2i64_rr(RetVT, Op0, Op1); 3568 default: return 0; 3569 } 3570} 3571 3572// FastEmit functions for ISD::SMAX. 3573 3574unsigned fastEmit_ISD_SMAX_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3575 if (RetVT.SimpleTy != MVT::v16i8) 3576 return 0; 3577 if ((Subtarget->hasAltivec())) { 3578 return fastEmitInst_rr(PPC::VMAXSB, &PPC::VRRCRegClass, Op0, Op1); 3579 } 3580 return 0; 3581} 3582 3583unsigned fastEmit_ISD_SMAX_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3584 if (RetVT.SimpleTy != MVT::v8i16) 3585 return 0; 3586 if ((Subtarget->hasAltivec())) { 3587 return fastEmitInst_rr(PPC::VMAXSH, &PPC::VRRCRegClass, Op0, Op1); 3588 } 3589 return 0; 3590} 3591 3592unsigned fastEmit_ISD_SMAX_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3593 if (RetVT.SimpleTy != MVT::v4i32) 3594 return 0; 3595 if ((Subtarget->hasAltivec())) { 3596 return fastEmitInst_rr(PPC::VMAXSW, &PPC::VRRCRegClass, Op0, Op1); 3597 } 3598 return 0; 3599} 3600 3601unsigned fastEmit_ISD_SMAX_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { 3602 switch (VT.SimpleTy) { 3603 case MVT::v16i8: return fastEmit_ISD_SMAX_MVT_v16i8_rr(RetVT, Op0, Op1); 3604 case MVT::v8i16: return fastEmit_ISD_SMAX_MVT_v8i16_rr(RetVT, Op0, Op1); 3605 case MVT::v4i32: return fastEmit_ISD_SMAX_MVT_v4i32_rr(RetVT, Op0, Op1); 3606 default: return 0; 3607 } 3608} 3609 3610// FastEmit functions for ISD::SMIN. 3611 3612unsigned fastEmit_ISD_SMIN_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3613 if (RetVT.SimpleTy != MVT::v16i8) 3614 return 0; 3615 if ((Subtarget->hasAltivec())) { 3616 return fastEmitInst_rr(PPC::VMINSB, &PPC::VRRCRegClass, Op0, Op1); 3617 } 3618 return 0; 3619} 3620 3621unsigned fastEmit_ISD_SMIN_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3622 if (RetVT.SimpleTy != MVT::v8i16) 3623 return 0; 3624 if ((Subtarget->hasAltivec())) { 3625 return fastEmitInst_rr(PPC::VMINSH, &PPC::VRRCRegClass, Op0, Op1); 3626 } 3627 return 0; 3628} 3629 3630unsigned fastEmit_ISD_SMIN_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3631 if (RetVT.SimpleTy != MVT::v4i32) 3632 return 0; 3633 if ((Subtarget->hasAltivec())) { 3634 return fastEmitInst_rr(PPC::VMINSW, &PPC::VRRCRegClass, Op0, Op1); 3635 } 3636 return 0; 3637} 3638 3639unsigned fastEmit_ISD_SMIN_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { 3640 switch (VT.SimpleTy) { 3641 case MVT::v16i8: return fastEmit_ISD_SMIN_MVT_v16i8_rr(RetVT, Op0, Op1); 3642 case MVT::v8i16: return fastEmit_ISD_SMIN_MVT_v8i16_rr(RetVT, Op0, Op1); 3643 case MVT::v4i32: return fastEmit_ISD_SMIN_MVT_v4i32_rr(RetVT, Op0, Op1); 3644 default: return 0; 3645 } 3646} 3647 3648// FastEmit functions for ISD::SRA. 3649 3650unsigned fastEmit_ISD_SRA_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3651 if (RetVT.SimpleTy != MVT::i32) 3652 return 0; 3653 return fastEmitInst_rr(PPC::SRAW, &PPC::GPRCRegClass, Op0, Op1); 3654} 3655 3656unsigned fastEmit_ISD_SRA_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3657 if (RetVT.SimpleTy != MVT::v16i8) 3658 return 0; 3659 if ((Subtarget->hasAltivec())) { 3660 return fastEmitInst_rr(PPC::VSRAB, &PPC::VRRCRegClass, Op0, Op1); 3661 } 3662 return 0; 3663} 3664 3665unsigned fastEmit_ISD_SRA_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3666 if (RetVT.SimpleTy != MVT::v8i16) 3667 return 0; 3668 if ((Subtarget->hasAltivec())) { 3669 return fastEmitInst_rr(PPC::VSRAH, &PPC::VRRCRegClass, Op0, Op1); 3670 } 3671 return 0; 3672} 3673 3674unsigned fastEmit_ISD_SRA_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3675 if (RetVT.SimpleTy != MVT::v4i32) 3676 return 0; 3677 if ((Subtarget->hasAltivec())) { 3678 return fastEmitInst_rr(PPC::VSRAW, &PPC::VRRCRegClass, Op0, Op1); 3679 } 3680 return 0; 3681} 3682 3683unsigned fastEmit_ISD_SRA_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3684 if (RetVT.SimpleTy != MVT::v2i64) 3685 return 0; 3686 if ((Subtarget->hasP8Altivec())) { 3687 return fastEmitInst_rr(PPC::VSRAD, &PPC::VRRCRegClass, Op0, Op1); 3688 } 3689 return 0; 3690} 3691 3692unsigned fastEmit_ISD_SRA_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { 3693 switch (VT.SimpleTy) { 3694 case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_rr(RetVT, Op0, Op1); 3695 case MVT::v16i8: return fastEmit_ISD_SRA_MVT_v16i8_rr(RetVT, Op0, Op1); 3696 case MVT::v8i16: return fastEmit_ISD_SRA_MVT_v8i16_rr(RetVT, Op0, Op1); 3697 case MVT::v4i32: return fastEmit_ISD_SRA_MVT_v4i32_rr(RetVT, Op0, Op1); 3698 case MVT::v2i64: return fastEmit_ISD_SRA_MVT_v2i64_rr(RetVT, Op0, Op1); 3699 default: return 0; 3700 } 3701} 3702 3703// FastEmit functions for ISD::SREM. 3704 3705unsigned fastEmit_ISD_SREM_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3706 if (RetVT.SimpleTy != MVT::i32) 3707 return 0; 3708 if ((Subtarget->isISA3_0())) { 3709 return fastEmitInst_rr(PPC::MODSW, &PPC::GPRCRegClass, Op0, Op1); 3710 } 3711 return 0; 3712} 3713 3714unsigned fastEmit_ISD_SREM_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3715 if (RetVT.SimpleTy != MVT::i64) 3716 return 0; 3717 if ((Subtarget->isISA3_0())) { 3718 return fastEmitInst_rr(PPC::MODSD, &PPC::G8RCRegClass, Op0, Op1); 3719 } 3720 return 0; 3721} 3722 3723unsigned fastEmit_ISD_SREM_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3724 if (RetVT.SimpleTy != MVT::v4i32) 3725 return 0; 3726 if ((Subtarget->isISA3_1())) { 3727 return fastEmitInst_rr(PPC::VMODSW, &PPC::VRRCRegClass, Op0, Op1); 3728 } 3729 return 0; 3730} 3731 3732unsigned fastEmit_ISD_SREM_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3733 if (RetVT.SimpleTy != MVT::v2i64) 3734 return 0; 3735 if ((Subtarget->isISA3_1())) { 3736 return fastEmitInst_rr(PPC::VMODSD, &PPC::VRRCRegClass, Op0, Op1); 3737 } 3738 return 0; 3739} 3740 3741unsigned fastEmit_ISD_SREM_MVT_v1i128_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3742 if (RetVT.SimpleTy != MVT::v1i128) 3743 return 0; 3744 if ((Subtarget->isISA3_1())) { 3745 return fastEmitInst_rr(PPC::VMODSQ, &PPC::VRRCRegClass, Op0, Op1); 3746 } 3747 return 0; 3748} 3749 3750unsigned fastEmit_ISD_SREM_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { 3751 switch (VT.SimpleTy) { 3752 case MVT::i32: return fastEmit_ISD_SREM_MVT_i32_rr(RetVT, Op0, Op1); 3753 case MVT::i64: return fastEmit_ISD_SREM_MVT_i64_rr(RetVT, Op0, Op1); 3754 case MVT::v4i32: return fastEmit_ISD_SREM_MVT_v4i32_rr(RetVT, Op0, Op1); 3755 case MVT::v2i64: return fastEmit_ISD_SREM_MVT_v2i64_rr(RetVT, Op0, Op1); 3756 case MVT::v1i128: return fastEmit_ISD_SREM_MVT_v1i128_rr(RetVT, Op0, Op1); 3757 default: return 0; 3758 } 3759} 3760 3761// FastEmit functions for ISD::SRL. 3762 3763unsigned fastEmit_ISD_SRL_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3764 if (RetVT.SimpleTy != MVT::i32) 3765 return 0; 3766 return fastEmitInst_rr(PPC::SRW, &PPC::GPRCRegClass, Op0, Op1); 3767} 3768 3769unsigned fastEmit_ISD_SRL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3770 if (RetVT.SimpleTy != MVT::v16i8) 3771 return 0; 3772 if ((Subtarget->hasAltivec())) { 3773 return fastEmitInst_rr(PPC::VSRB, &PPC::VRRCRegClass, Op0, Op1); 3774 } 3775 return 0; 3776} 3777 3778unsigned fastEmit_ISD_SRL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3779 if (RetVT.SimpleTy != MVT::v8i16) 3780 return 0; 3781 if ((Subtarget->hasAltivec())) { 3782 return fastEmitInst_rr(PPC::VSRH, &PPC::VRRCRegClass, Op0, Op1); 3783 } 3784 return 0; 3785} 3786 3787unsigned fastEmit_ISD_SRL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3788 if (RetVT.SimpleTy != MVT::v4i32) 3789 return 0; 3790 if ((Subtarget->hasAltivec())) { 3791 return fastEmitInst_rr(PPC::VSRW, &PPC::VRRCRegClass, Op0, Op1); 3792 } 3793 return 0; 3794} 3795 3796unsigned fastEmit_ISD_SRL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3797 if (RetVT.SimpleTy != MVT::v2i64) 3798 return 0; 3799 if ((Subtarget->hasP8Altivec())) { 3800 return fastEmitInst_rr(PPC::VSRD, &PPC::VRRCRegClass, Op0, Op1); 3801 } 3802 return 0; 3803} 3804 3805unsigned fastEmit_ISD_SRL_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { 3806 switch (VT.SimpleTy) { 3807 case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_rr(RetVT, Op0, Op1); 3808 case MVT::v16i8: return fastEmit_ISD_SRL_MVT_v16i8_rr(RetVT, Op0, Op1); 3809 case MVT::v8i16: return fastEmit_ISD_SRL_MVT_v8i16_rr(RetVT, Op0, Op1); 3810 case MVT::v4i32: return fastEmit_ISD_SRL_MVT_v4i32_rr(RetVT, Op0, Op1); 3811 case MVT::v2i64: return fastEmit_ISD_SRL_MVT_v2i64_rr(RetVT, Op0, Op1); 3812 default: return 0; 3813 } 3814} 3815 3816// FastEmit functions for ISD::SSUBSAT. 3817 3818unsigned fastEmit_ISD_SSUBSAT_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3819 if (RetVT.SimpleTy != MVT::v16i8) 3820 return 0; 3821 if ((Subtarget->hasAltivec())) { 3822 return fastEmitInst_rr(PPC::VSUBSBS, &PPC::VRRCRegClass, Op0, Op1); 3823 } 3824 return 0; 3825} 3826 3827unsigned fastEmit_ISD_SSUBSAT_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3828 if (RetVT.SimpleTy != MVT::v8i16) 3829 return 0; 3830 if ((Subtarget->hasAltivec())) { 3831 return fastEmitInst_rr(PPC::VSUBSHS, &PPC::VRRCRegClass, Op0, Op1); 3832 } 3833 return 0; 3834} 3835 3836unsigned fastEmit_ISD_SSUBSAT_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3837 if (RetVT.SimpleTy != MVT::v4i32) 3838 return 0; 3839 if ((Subtarget->hasAltivec())) { 3840 return fastEmitInst_rr(PPC::VSUBSWS, &PPC::VRRCRegClass, Op0, Op1); 3841 } 3842 return 0; 3843} 3844 3845unsigned fastEmit_ISD_SSUBSAT_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { 3846 switch (VT.SimpleTy) { 3847 case MVT::v16i8: return fastEmit_ISD_SSUBSAT_MVT_v16i8_rr(RetVT, Op0, Op1); 3848 case MVT::v8i16: return fastEmit_ISD_SSUBSAT_MVT_v8i16_rr(RetVT, Op0, Op1); 3849 case MVT::v4i32: return fastEmit_ISD_SSUBSAT_MVT_v4i32_rr(RetVT, Op0, Op1); 3850 default: return 0; 3851 } 3852} 3853 3854// FastEmit functions for ISD::STRICT_FADD. 3855 3856unsigned fastEmit_ISD_STRICT_FADD_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3857 if (RetVT.SimpleTy != MVT::f32) 3858 return 0; 3859 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) { 3860 return fastEmitInst_rr(PPC::XSADDSP, &PPC::VSSRCRegClass, Op0, Op1); 3861 } 3862 if ((Subtarget->hasSPE())) { 3863 return fastEmitInst_rr(PPC::EFSADD, &PPC::GPRCRegClass, Op0, Op1); 3864 } 3865 if ((Subtarget->hasFPU())) { 3866 return fastEmitInst_rr(PPC::FADDS, &PPC::F4RCRegClass, Op0, Op1); 3867 } 3868 return 0; 3869} 3870 3871unsigned fastEmit_ISD_STRICT_FADD_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3872 if (RetVT.SimpleTy != MVT::f64) 3873 return 0; 3874 if ((Subtarget->hasVSX())) { 3875 return fastEmitInst_rr(PPC::XSADDDP, &PPC::VSFRCRegClass, Op0, Op1); 3876 } 3877 if ((Subtarget->hasSPE())) { 3878 return fastEmitInst_rr(PPC::EFDADD, &PPC::SPERCRegClass, Op0, Op1); 3879 } 3880 if ((Subtarget->hasFPU())) { 3881 return fastEmitInst_rr(PPC::FADD, &PPC::F8RCRegClass, Op0, Op1); 3882 } 3883 return 0; 3884} 3885 3886unsigned fastEmit_ISD_STRICT_FADD_MVT_f128_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3887 if (RetVT.SimpleTy != MVT::f128) 3888 return 0; 3889 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) { 3890 return fastEmitInst_rr(PPC::XSADDQP, &PPC::VRRCRegClass, Op0, Op1); 3891 } 3892 return 0; 3893} 3894 3895unsigned fastEmit_ISD_STRICT_FADD_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3896 if (RetVT.SimpleTy != MVT::v4f32) 3897 return 0; 3898 if ((Subtarget->hasVSX())) { 3899 return fastEmitInst_rr(PPC::XVADDSP, &PPC::VSRCRegClass, Op0, Op1); 3900 } 3901 return 0; 3902} 3903 3904unsigned fastEmit_ISD_STRICT_FADD_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3905 if (RetVT.SimpleTy != MVT::v2f64) 3906 return 0; 3907 if ((Subtarget->hasVSX())) { 3908 return fastEmitInst_rr(PPC::XVADDDP, &PPC::VSRCRegClass, Op0, Op1); 3909 } 3910 return 0; 3911} 3912 3913unsigned fastEmit_ISD_STRICT_FADD_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { 3914 switch (VT.SimpleTy) { 3915 case MVT::f32: return fastEmit_ISD_STRICT_FADD_MVT_f32_rr(RetVT, Op0, Op1); 3916 case MVT::f64: return fastEmit_ISD_STRICT_FADD_MVT_f64_rr(RetVT, Op0, Op1); 3917 case MVT::f128: return fastEmit_ISD_STRICT_FADD_MVT_f128_rr(RetVT, Op0, Op1); 3918 case MVT::v4f32: return fastEmit_ISD_STRICT_FADD_MVT_v4f32_rr(RetVT, Op0, Op1); 3919 case MVT::v2f64: return fastEmit_ISD_STRICT_FADD_MVT_v2f64_rr(RetVT, Op0, Op1); 3920 default: return 0; 3921 } 3922} 3923 3924// FastEmit functions for ISD::STRICT_FDIV. 3925 3926unsigned fastEmit_ISD_STRICT_FDIV_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3927 if (RetVT.SimpleTy != MVT::f32) 3928 return 0; 3929 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) { 3930 return fastEmitInst_rr(PPC::XSDIVSP, &PPC::VSSRCRegClass, Op0, Op1); 3931 } 3932 if ((Subtarget->hasSPE())) { 3933 return fastEmitInst_rr(PPC::EFSDIV, &PPC::GPRCRegClass, Op0, Op1); 3934 } 3935 if ((Subtarget->hasFPU())) { 3936 return fastEmitInst_rr(PPC::FDIVS, &PPC::F4RCRegClass, Op0, Op1); 3937 } 3938 return 0; 3939} 3940 3941unsigned fastEmit_ISD_STRICT_FDIV_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3942 if (RetVT.SimpleTy != MVT::f64) 3943 return 0; 3944 if ((Subtarget->hasVSX())) { 3945 return fastEmitInst_rr(PPC::XSDIVDP, &PPC::VSFRCRegClass, Op0, Op1); 3946 } 3947 if ((Subtarget->hasSPE())) { 3948 return fastEmitInst_rr(PPC::EFDDIV, &PPC::SPERCRegClass, Op0, Op1); 3949 } 3950 if ((Subtarget->hasFPU())) { 3951 return fastEmitInst_rr(PPC::FDIV, &PPC::F8RCRegClass, Op0, Op1); 3952 } 3953 return 0; 3954} 3955 3956unsigned fastEmit_ISD_STRICT_FDIV_MVT_f128_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3957 if (RetVT.SimpleTy != MVT::f128) 3958 return 0; 3959 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) { 3960 return fastEmitInst_rr(PPC::XSDIVQP, &PPC::VRRCRegClass, Op0, Op1); 3961 } 3962 return 0; 3963} 3964 3965unsigned fastEmit_ISD_STRICT_FDIV_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3966 if (RetVT.SimpleTy != MVT::v4f32) 3967 return 0; 3968 if ((Subtarget->hasVSX())) { 3969 return fastEmitInst_rr(PPC::XVDIVSP, &PPC::VSRCRegClass, Op0, Op1); 3970 } 3971 return 0; 3972} 3973 3974unsigned fastEmit_ISD_STRICT_FDIV_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3975 if (RetVT.SimpleTy != MVT::v2f64) 3976 return 0; 3977 if ((Subtarget->hasVSX())) { 3978 return fastEmitInst_rr(PPC::XVDIVDP, &PPC::VSRCRegClass, Op0, Op1); 3979 } 3980 return 0; 3981} 3982 3983unsigned fastEmit_ISD_STRICT_FDIV_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { 3984 switch (VT.SimpleTy) { 3985 case MVT::f32: return fastEmit_ISD_STRICT_FDIV_MVT_f32_rr(RetVT, Op0, Op1); 3986 case MVT::f64: return fastEmit_ISD_STRICT_FDIV_MVT_f64_rr(RetVT, Op0, Op1); 3987 case MVT::f128: return fastEmit_ISD_STRICT_FDIV_MVT_f128_rr(RetVT, Op0, Op1); 3988 case MVT::v4f32: return fastEmit_ISD_STRICT_FDIV_MVT_v4f32_rr(RetVT, Op0, Op1); 3989 case MVT::v2f64: return fastEmit_ISD_STRICT_FDIV_MVT_v2f64_rr(RetVT, Op0, Op1); 3990 default: return 0; 3991 } 3992} 3993 3994// FastEmit functions for ISD::STRICT_FMAXNUM. 3995 3996unsigned fastEmit_ISD_STRICT_FMAXNUM_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 3997 if (RetVT.SimpleTy != MVT::v4f32) 3998 return 0; 3999 if ((Subtarget->hasVSX())) { 4000 return fastEmitInst_rr(PPC::XVMAXSP, &PPC::VSRCRegClass, Op0, Op1); 4001 } 4002 return 0; 4003} 4004 4005unsigned fastEmit_ISD_STRICT_FMAXNUM_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4006 if (RetVT.SimpleTy != MVT::v2f64) 4007 return 0; 4008 if ((Subtarget->hasVSX())) { 4009 return fastEmitInst_rr(PPC::XVMAXDP, &PPC::VSRCRegClass, Op0, Op1); 4010 } 4011 return 0; 4012} 4013 4014unsigned fastEmit_ISD_STRICT_FMAXNUM_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { 4015 switch (VT.SimpleTy) { 4016 case MVT::v4f32: return fastEmit_ISD_STRICT_FMAXNUM_MVT_v4f32_rr(RetVT, Op0, Op1); 4017 case MVT::v2f64: return fastEmit_ISD_STRICT_FMAXNUM_MVT_v2f64_rr(RetVT, Op0, Op1); 4018 default: return 0; 4019 } 4020} 4021 4022// FastEmit functions for ISD::STRICT_FMINNUM. 4023 4024unsigned fastEmit_ISD_STRICT_FMINNUM_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4025 if (RetVT.SimpleTy != MVT::v4f32) 4026 return 0; 4027 if ((Subtarget->hasVSX())) { 4028 return fastEmitInst_rr(PPC::XVMINSP, &PPC::VSRCRegClass, Op0, Op1); 4029 } 4030 return 0; 4031} 4032 4033unsigned fastEmit_ISD_STRICT_FMINNUM_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4034 if (RetVT.SimpleTy != MVT::v2f64) 4035 return 0; 4036 if ((Subtarget->hasVSX())) { 4037 return fastEmitInst_rr(PPC::XVMINDP, &PPC::VSRCRegClass, Op0, Op1); 4038 } 4039 return 0; 4040} 4041 4042unsigned fastEmit_ISD_STRICT_FMINNUM_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { 4043 switch (VT.SimpleTy) { 4044 case MVT::v4f32: return fastEmit_ISD_STRICT_FMINNUM_MVT_v4f32_rr(RetVT, Op0, Op1); 4045 case MVT::v2f64: return fastEmit_ISD_STRICT_FMINNUM_MVT_v2f64_rr(RetVT, Op0, Op1); 4046 default: return 0; 4047 } 4048} 4049 4050// FastEmit functions for ISD::STRICT_FMUL. 4051 4052unsigned fastEmit_ISD_STRICT_FMUL_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4053 if (RetVT.SimpleTy != MVT::f32) 4054 return 0; 4055 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) { 4056 return fastEmitInst_rr(PPC::XSMULSP, &PPC::VSSRCRegClass, Op0, Op1); 4057 } 4058 if ((Subtarget->hasSPE())) { 4059 return fastEmitInst_rr(PPC::EFSMUL, &PPC::GPRCRegClass, Op0, Op1); 4060 } 4061 if ((Subtarget->hasFPU())) { 4062 return fastEmitInst_rr(PPC::FMULS, &PPC::F4RCRegClass, Op0, Op1); 4063 } 4064 return 0; 4065} 4066 4067unsigned fastEmit_ISD_STRICT_FMUL_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4068 if (RetVT.SimpleTy != MVT::f64) 4069 return 0; 4070 if ((Subtarget->hasVSX())) { 4071 return fastEmitInst_rr(PPC::XSMULDP, &PPC::VSFRCRegClass, Op0, Op1); 4072 } 4073 if ((Subtarget->hasSPE())) { 4074 return fastEmitInst_rr(PPC::EFDMUL, &PPC::SPERCRegClass, Op0, Op1); 4075 } 4076 if ((Subtarget->hasFPU())) { 4077 return fastEmitInst_rr(PPC::FMUL, &PPC::F8RCRegClass, Op0, Op1); 4078 } 4079 return 0; 4080} 4081 4082unsigned fastEmit_ISD_STRICT_FMUL_MVT_f128_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4083 if (RetVT.SimpleTy != MVT::f128) 4084 return 0; 4085 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) { 4086 return fastEmitInst_rr(PPC::XSMULQP, &PPC::VRRCRegClass, Op0, Op1); 4087 } 4088 return 0; 4089} 4090 4091unsigned fastEmit_ISD_STRICT_FMUL_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4092 if (RetVT.SimpleTy != MVT::v4f32) 4093 return 0; 4094 if ((Subtarget->hasVSX())) { 4095 return fastEmitInst_rr(PPC::XVMULSP, &PPC::VSRCRegClass, Op0, Op1); 4096 } 4097 return 0; 4098} 4099 4100unsigned fastEmit_ISD_STRICT_FMUL_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4101 if (RetVT.SimpleTy != MVT::v2f64) 4102 return 0; 4103 if ((Subtarget->hasVSX())) { 4104 return fastEmitInst_rr(PPC::XVMULDP, &PPC::VSRCRegClass, Op0, Op1); 4105 } 4106 return 0; 4107} 4108 4109unsigned fastEmit_ISD_STRICT_FMUL_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { 4110 switch (VT.SimpleTy) { 4111 case MVT::f32: return fastEmit_ISD_STRICT_FMUL_MVT_f32_rr(RetVT, Op0, Op1); 4112 case MVT::f64: return fastEmit_ISD_STRICT_FMUL_MVT_f64_rr(RetVT, Op0, Op1); 4113 case MVT::f128: return fastEmit_ISD_STRICT_FMUL_MVT_f128_rr(RetVT, Op0, Op1); 4114 case MVT::v4f32: return fastEmit_ISD_STRICT_FMUL_MVT_v4f32_rr(RetVT, Op0, Op1); 4115 case MVT::v2f64: return fastEmit_ISD_STRICT_FMUL_MVT_v2f64_rr(RetVT, Op0, Op1); 4116 default: return 0; 4117 } 4118} 4119 4120// FastEmit functions for ISD::STRICT_FSUB. 4121 4122unsigned fastEmit_ISD_STRICT_FSUB_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4123 if (RetVT.SimpleTy != MVT::f32) 4124 return 0; 4125 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) { 4126 return fastEmitInst_rr(PPC::XSSUBSP, &PPC::VSSRCRegClass, Op0, Op1); 4127 } 4128 if ((Subtarget->hasSPE())) { 4129 return fastEmitInst_rr(PPC::EFSSUB, &PPC::GPRCRegClass, Op0, Op1); 4130 } 4131 if ((Subtarget->hasFPU())) { 4132 return fastEmitInst_rr(PPC::FSUBS, &PPC::F4RCRegClass, Op0, Op1); 4133 } 4134 return 0; 4135} 4136 4137unsigned fastEmit_ISD_STRICT_FSUB_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4138 if (RetVT.SimpleTy != MVT::f64) 4139 return 0; 4140 if ((Subtarget->hasVSX())) { 4141 return fastEmitInst_rr(PPC::XSSUBDP, &PPC::VSFRCRegClass, Op0, Op1); 4142 } 4143 if ((Subtarget->hasSPE())) { 4144 return fastEmitInst_rr(PPC::EFDSUB, &PPC::SPERCRegClass, Op0, Op1); 4145 } 4146 if ((Subtarget->hasFPU())) { 4147 return fastEmitInst_rr(PPC::FSUB, &PPC::F8RCRegClass, Op0, Op1); 4148 } 4149 return 0; 4150} 4151 4152unsigned fastEmit_ISD_STRICT_FSUB_MVT_f128_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4153 if (RetVT.SimpleTy != MVT::f128) 4154 return 0; 4155 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) { 4156 return fastEmitInst_rr(PPC::XSSUBQP, &PPC::VRRCRegClass, Op0, Op1); 4157 } 4158 return 0; 4159} 4160 4161unsigned fastEmit_ISD_STRICT_FSUB_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4162 if (RetVT.SimpleTy != MVT::v4f32) 4163 return 0; 4164 if ((Subtarget->hasVSX())) { 4165 return fastEmitInst_rr(PPC::XVSUBSP, &PPC::VSRCRegClass, Op0, Op1); 4166 } 4167 return 0; 4168} 4169 4170unsigned fastEmit_ISD_STRICT_FSUB_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4171 if (RetVT.SimpleTy != MVT::v2f64) 4172 return 0; 4173 if ((Subtarget->hasVSX())) { 4174 return fastEmitInst_rr(PPC::XVSUBDP, &PPC::VSRCRegClass, Op0, Op1); 4175 } 4176 return 0; 4177} 4178 4179unsigned fastEmit_ISD_STRICT_FSUB_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { 4180 switch (VT.SimpleTy) { 4181 case MVT::f32: return fastEmit_ISD_STRICT_FSUB_MVT_f32_rr(RetVT, Op0, Op1); 4182 case MVT::f64: return fastEmit_ISD_STRICT_FSUB_MVT_f64_rr(RetVT, Op0, Op1); 4183 case MVT::f128: return fastEmit_ISD_STRICT_FSUB_MVT_f128_rr(RetVT, Op0, Op1); 4184 case MVT::v4f32: return fastEmit_ISD_STRICT_FSUB_MVT_v4f32_rr(RetVT, Op0, Op1); 4185 case MVT::v2f64: return fastEmit_ISD_STRICT_FSUB_MVT_v2f64_rr(RetVT, Op0, Op1); 4186 default: return 0; 4187 } 4188} 4189 4190// FastEmit functions for ISD::SUB. 4191 4192unsigned fastEmit_ISD_SUB_MVT_i1_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4193 if (RetVT.SimpleTy != MVT::i1) 4194 return 0; 4195 return fastEmitInst_rr(PPC::CRXOR, &PPC::CRBITRCRegClass, Op0, Op1); 4196} 4197 4198unsigned fastEmit_ISD_SUB_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4199 if (RetVT.SimpleTy != MVT::v16i8) 4200 return 0; 4201 if ((Subtarget->hasAltivec())) { 4202 return fastEmitInst_rr(PPC::VSUBUBM, &PPC::VRRCRegClass, Op0, Op1); 4203 } 4204 return 0; 4205} 4206 4207unsigned fastEmit_ISD_SUB_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4208 if (RetVT.SimpleTy != MVT::v8i16) 4209 return 0; 4210 if ((Subtarget->hasAltivec())) { 4211 return fastEmitInst_rr(PPC::VSUBUHM, &PPC::VRRCRegClass, Op0, Op1); 4212 } 4213 return 0; 4214} 4215 4216unsigned fastEmit_ISD_SUB_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4217 if (RetVT.SimpleTy != MVT::v4i32) 4218 return 0; 4219 if ((Subtarget->hasAltivec())) { 4220 return fastEmitInst_rr(PPC::VSUBUWM, &PPC::VRRCRegClass, Op0, Op1); 4221 } 4222 return 0; 4223} 4224 4225unsigned fastEmit_ISD_SUB_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4226 if (RetVT.SimpleTy != MVT::v2i64) 4227 return 0; 4228 if ((Subtarget->hasP8Altivec())) { 4229 return fastEmitInst_rr(PPC::VSUBUDM, &PPC::VRRCRegClass, Op0, Op1); 4230 } 4231 return 0; 4232} 4233 4234unsigned fastEmit_ISD_SUB_MVT_v1i128_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4235 if (RetVT.SimpleTy != MVT::v1i128) 4236 return 0; 4237 if ((Subtarget->hasP8Altivec())) { 4238 return fastEmitInst_rr(PPC::VSUBUQM, &PPC::VRRCRegClass, Op0, Op1); 4239 } 4240 return 0; 4241} 4242 4243unsigned fastEmit_ISD_SUB_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { 4244 switch (VT.SimpleTy) { 4245 case MVT::i1: return fastEmit_ISD_SUB_MVT_i1_rr(RetVT, Op0, Op1); 4246 case MVT::v16i8: return fastEmit_ISD_SUB_MVT_v16i8_rr(RetVT, Op0, Op1); 4247 case MVT::v8i16: return fastEmit_ISD_SUB_MVT_v8i16_rr(RetVT, Op0, Op1); 4248 case MVT::v4i32: return fastEmit_ISD_SUB_MVT_v4i32_rr(RetVT, Op0, Op1); 4249 case MVT::v2i64: return fastEmit_ISD_SUB_MVT_v2i64_rr(RetVT, Op0, Op1); 4250 case MVT::v1i128: return fastEmit_ISD_SUB_MVT_v1i128_rr(RetVT, Op0, Op1); 4251 default: return 0; 4252 } 4253} 4254 4255// FastEmit functions for ISD::UADDSAT. 4256 4257unsigned fastEmit_ISD_UADDSAT_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4258 if (RetVT.SimpleTy != MVT::v16i8) 4259 return 0; 4260 if ((Subtarget->hasAltivec())) { 4261 return fastEmitInst_rr(PPC::VADDUBS, &PPC::VRRCRegClass, Op0, Op1); 4262 } 4263 return 0; 4264} 4265 4266unsigned fastEmit_ISD_UADDSAT_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4267 if (RetVT.SimpleTy != MVT::v8i16) 4268 return 0; 4269 if ((Subtarget->hasAltivec())) { 4270 return fastEmitInst_rr(PPC::VADDUHS, &PPC::VRRCRegClass, Op0, Op1); 4271 } 4272 return 0; 4273} 4274 4275unsigned fastEmit_ISD_UADDSAT_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4276 if (RetVT.SimpleTy != MVT::v4i32) 4277 return 0; 4278 if ((Subtarget->hasAltivec())) { 4279 return fastEmitInst_rr(PPC::VADDUWS, &PPC::VRRCRegClass, Op0, Op1); 4280 } 4281 return 0; 4282} 4283 4284unsigned fastEmit_ISD_UADDSAT_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { 4285 switch (VT.SimpleTy) { 4286 case MVT::v16i8: return fastEmit_ISD_UADDSAT_MVT_v16i8_rr(RetVT, Op0, Op1); 4287 case MVT::v8i16: return fastEmit_ISD_UADDSAT_MVT_v8i16_rr(RetVT, Op0, Op1); 4288 case MVT::v4i32: return fastEmit_ISD_UADDSAT_MVT_v4i32_rr(RetVT, Op0, Op1); 4289 default: return 0; 4290 } 4291} 4292 4293// FastEmit functions for ISD::UDIV. 4294 4295unsigned fastEmit_ISD_UDIV_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4296 if (RetVT.SimpleTy != MVT::i32) 4297 return 0; 4298 return fastEmitInst_rr(PPC::DIVWU, &PPC::GPRCRegClass, Op0, Op1); 4299} 4300 4301unsigned fastEmit_ISD_UDIV_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4302 if (RetVT.SimpleTy != MVT::i64) 4303 return 0; 4304 return fastEmitInst_rr(PPC::DIVDU, &PPC::G8RCRegClass, Op0, Op1); 4305} 4306 4307unsigned fastEmit_ISD_UDIV_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4308 if (RetVT.SimpleTy != MVT::v4i32) 4309 return 0; 4310 if ((Subtarget->isISA3_1())) { 4311 return fastEmitInst_rr(PPC::VDIVUW, &PPC::VRRCRegClass, Op0, Op1); 4312 } 4313 return 0; 4314} 4315 4316unsigned fastEmit_ISD_UDIV_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4317 if (RetVT.SimpleTy != MVT::v2i64) 4318 return 0; 4319 if ((Subtarget->isISA3_1())) { 4320 return fastEmitInst_rr(PPC::VDIVUD, &PPC::VRRCRegClass, Op0, Op1); 4321 } 4322 return 0; 4323} 4324 4325unsigned fastEmit_ISD_UDIV_MVT_v1i128_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4326 if (RetVT.SimpleTy != MVT::v1i128) 4327 return 0; 4328 if ((Subtarget->isISA3_1())) { 4329 return fastEmitInst_rr(PPC::VDIVUQ, &PPC::VRRCRegClass, Op0, Op1); 4330 } 4331 return 0; 4332} 4333 4334unsigned fastEmit_ISD_UDIV_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { 4335 switch (VT.SimpleTy) { 4336 case MVT::i32: return fastEmit_ISD_UDIV_MVT_i32_rr(RetVT, Op0, Op1); 4337 case MVT::i64: return fastEmit_ISD_UDIV_MVT_i64_rr(RetVT, Op0, Op1); 4338 case MVT::v4i32: return fastEmit_ISD_UDIV_MVT_v4i32_rr(RetVT, Op0, Op1); 4339 case MVT::v2i64: return fastEmit_ISD_UDIV_MVT_v2i64_rr(RetVT, Op0, Op1); 4340 case MVT::v1i128: return fastEmit_ISD_UDIV_MVT_v1i128_rr(RetVT, Op0, Op1); 4341 default: return 0; 4342 } 4343} 4344 4345// FastEmit functions for ISD::UMAX. 4346 4347unsigned fastEmit_ISD_UMAX_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4348 if (RetVT.SimpleTy != MVT::v16i8) 4349 return 0; 4350 if ((Subtarget->hasAltivec())) { 4351 return fastEmitInst_rr(PPC::VMAXUB, &PPC::VRRCRegClass, Op0, Op1); 4352 } 4353 return 0; 4354} 4355 4356unsigned fastEmit_ISD_UMAX_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4357 if (RetVT.SimpleTy != MVT::v8i16) 4358 return 0; 4359 if ((Subtarget->hasAltivec())) { 4360 return fastEmitInst_rr(PPC::VMAXUH, &PPC::VRRCRegClass, Op0, Op1); 4361 } 4362 return 0; 4363} 4364 4365unsigned fastEmit_ISD_UMAX_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4366 if (RetVT.SimpleTy != MVT::v4i32) 4367 return 0; 4368 if ((Subtarget->hasAltivec())) { 4369 return fastEmitInst_rr(PPC::VMAXUW, &PPC::VRRCRegClass, Op0, Op1); 4370 } 4371 return 0; 4372} 4373 4374unsigned fastEmit_ISD_UMAX_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { 4375 switch (VT.SimpleTy) { 4376 case MVT::v16i8: return fastEmit_ISD_UMAX_MVT_v16i8_rr(RetVT, Op0, Op1); 4377 case MVT::v8i16: return fastEmit_ISD_UMAX_MVT_v8i16_rr(RetVT, Op0, Op1); 4378 case MVT::v4i32: return fastEmit_ISD_UMAX_MVT_v4i32_rr(RetVT, Op0, Op1); 4379 default: return 0; 4380 } 4381} 4382 4383// FastEmit functions for ISD::UMIN. 4384 4385unsigned fastEmit_ISD_UMIN_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4386 if (RetVT.SimpleTy != MVT::v16i8) 4387 return 0; 4388 if ((Subtarget->hasAltivec())) { 4389 return fastEmitInst_rr(PPC::VMINUB, &PPC::VRRCRegClass, Op0, Op1); 4390 } 4391 return 0; 4392} 4393 4394unsigned fastEmit_ISD_UMIN_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4395 if (RetVT.SimpleTy != MVT::v8i16) 4396 return 0; 4397 if ((Subtarget->hasAltivec())) { 4398 return fastEmitInst_rr(PPC::VMINUH, &PPC::VRRCRegClass, Op0, Op1); 4399 } 4400 return 0; 4401} 4402 4403unsigned fastEmit_ISD_UMIN_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4404 if (RetVT.SimpleTy != MVT::v4i32) 4405 return 0; 4406 if ((Subtarget->hasAltivec())) { 4407 return fastEmitInst_rr(PPC::VMINUW, &PPC::VRRCRegClass, Op0, Op1); 4408 } 4409 return 0; 4410} 4411 4412unsigned fastEmit_ISD_UMIN_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { 4413 switch (VT.SimpleTy) { 4414 case MVT::v16i8: return fastEmit_ISD_UMIN_MVT_v16i8_rr(RetVT, Op0, Op1); 4415 case MVT::v8i16: return fastEmit_ISD_UMIN_MVT_v8i16_rr(RetVT, Op0, Op1); 4416 case MVT::v4i32: return fastEmit_ISD_UMIN_MVT_v4i32_rr(RetVT, Op0, Op1); 4417 default: return 0; 4418 } 4419} 4420 4421// FastEmit functions for ISD::UREM. 4422 4423unsigned fastEmit_ISD_UREM_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4424 if (RetVT.SimpleTy != MVT::i32) 4425 return 0; 4426 if ((Subtarget->isISA3_0())) { 4427 return fastEmitInst_rr(PPC::MODUW, &PPC::GPRCRegClass, Op0, Op1); 4428 } 4429 return 0; 4430} 4431 4432unsigned fastEmit_ISD_UREM_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4433 if (RetVT.SimpleTy != MVT::i64) 4434 return 0; 4435 if ((Subtarget->isISA3_0())) { 4436 return fastEmitInst_rr(PPC::MODUD, &PPC::G8RCRegClass, Op0, Op1); 4437 } 4438 return 0; 4439} 4440 4441unsigned fastEmit_ISD_UREM_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4442 if (RetVT.SimpleTy != MVT::v4i32) 4443 return 0; 4444 if ((Subtarget->isISA3_1())) { 4445 return fastEmitInst_rr(PPC::VMODUW, &PPC::VRRCRegClass, Op0, Op1); 4446 } 4447 return 0; 4448} 4449 4450unsigned fastEmit_ISD_UREM_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4451 if (RetVT.SimpleTy != MVT::v2i64) 4452 return 0; 4453 if ((Subtarget->isISA3_1())) { 4454 return fastEmitInst_rr(PPC::VMODUD, &PPC::VRRCRegClass, Op0, Op1); 4455 } 4456 return 0; 4457} 4458 4459unsigned fastEmit_ISD_UREM_MVT_v1i128_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4460 if (RetVT.SimpleTy != MVT::v1i128) 4461 return 0; 4462 if ((Subtarget->isISA3_1())) { 4463 return fastEmitInst_rr(PPC::VMODUQ, &PPC::VRRCRegClass, Op0, Op1); 4464 } 4465 return 0; 4466} 4467 4468unsigned fastEmit_ISD_UREM_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { 4469 switch (VT.SimpleTy) { 4470 case MVT::i32: return fastEmit_ISD_UREM_MVT_i32_rr(RetVT, Op0, Op1); 4471 case MVT::i64: return fastEmit_ISD_UREM_MVT_i64_rr(RetVT, Op0, Op1); 4472 case MVT::v4i32: return fastEmit_ISD_UREM_MVT_v4i32_rr(RetVT, Op0, Op1); 4473 case MVT::v2i64: return fastEmit_ISD_UREM_MVT_v2i64_rr(RetVT, Op0, Op1); 4474 case MVT::v1i128: return fastEmit_ISD_UREM_MVT_v1i128_rr(RetVT, Op0, Op1); 4475 default: return 0; 4476 } 4477} 4478 4479// FastEmit functions for ISD::USUBSAT. 4480 4481unsigned fastEmit_ISD_USUBSAT_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4482 if (RetVT.SimpleTy != MVT::v16i8) 4483 return 0; 4484 if ((Subtarget->hasAltivec())) { 4485 return fastEmitInst_rr(PPC::VSUBUBS, &PPC::VRRCRegClass, Op0, Op1); 4486 } 4487 return 0; 4488} 4489 4490unsigned fastEmit_ISD_USUBSAT_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4491 if (RetVT.SimpleTy != MVT::v8i16) 4492 return 0; 4493 if ((Subtarget->hasAltivec())) { 4494 return fastEmitInst_rr(PPC::VSUBUHS, &PPC::VRRCRegClass, Op0, Op1); 4495 } 4496 return 0; 4497} 4498 4499unsigned fastEmit_ISD_USUBSAT_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4500 if (RetVT.SimpleTy != MVT::v4i32) 4501 return 0; 4502 if ((Subtarget->hasAltivec())) { 4503 return fastEmitInst_rr(PPC::VSUBUWS, &PPC::VRRCRegClass, Op0, Op1); 4504 } 4505 return 0; 4506} 4507 4508unsigned fastEmit_ISD_USUBSAT_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { 4509 switch (VT.SimpleTy) { 4510 case MVT::v16i8: return fastEmit_ISD_USUBSAT_MVT_v16i8_rr(RetVT, Op0, Op1); 4511 case MVT::v8i16: return fastEmit_ISD_USUBSAT_MVT_v8i16_rr(RetVT, Op0, Op1); 4512 case MVT::v4i32: return fastEmit_ISD_USUBSAT_MVT_v4i32_rr(RetVT, Op0, Op1); 4513 default: return 0; 4514 } 4515} 4516 4517// FastEmit functions for ISD::XOR. 4518 4519unsigned fastEmit_ISD_XOR_MVT_i1_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4520 if (RetVT.SimpleTy != MVT::i1) 4521 return 0; 4522 return fastEmitInst_rr(PPC::CRXOR, &PPC::CRBITRCRegClass, Op0, Op1); 4523} 4524 4525unsigned fastEmit_ISD_XOR_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4526 if (RetVT.SimpleTy != MVT::i32) 4527 return 0; 4528 return fastEmitInst_rr(PPC::XOR, &PPC::GPRCRegClass, Op0, Op1); 4529} 4530 4531unsigned fastEmit_ISD_XOR_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4532 if (RetVT.SimpleTy != MVT::i64) 4533 return 0; 4534 return fastEmitInst_rr(PPC::XOR8, &PPC::G8RCRegClass, Op0, Op1); 4535} 4536 4537unsigned fastEmit_ISD_XOR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4538 if (RetVT.SimpleTy != MVT::v4i32) 4539 return 0; 4540 if ((Subtarget->hasVSX())) { 4541 return fastEmitInst_rr(PPC::XXLXOR, &PPC::VSRCRegClass, Op0, Op1); 4542 } 4543 if ((Subtarget->hasAltivec())) { 4544 return fastEmitInst_rr(PPC::VXOR, &PPC::VRRCRegClass, Op0, Op1); 4545 } 4546 return 0; 4547} 4548 4549unsigned fastEmit_ISD_XOR_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { 4550 switch (VT.SimpleTy) { 4551 case MVT::i1: return fastEmit_ISD_XOR_MVT_i1_rr(RetVT, Op0, Op1); 4552 case MVT::i32: return fastEmit_ISD_XOR_MVT_i32_rr(RetVT, Op0, Op1); 4553 case MVT::i64: return fastEmit_ISD_XOR_MVT_i64_rr(RetVT, Op0, Op1); 4554 case MVT::v4i32: return fastEmit_ISD_XOR_MVT_v4i32_rr(RetVT, Op0, Op1); 4555 default: return 0; 4556 } 4557} 4558 4559// FastEmit functions for PPCISD::CMPB. 4560 4561unsigned fastEmit_PPCISD_CMPB_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4562 if (RetVT.SimpleTy != MVT::i32) 4563 return 0; 4564 return fastEmitInst_rr(PPC::CMPB, &PPC::GPRCRegClass, Op0, Op1); 4565} 4566 4567unsigned fastEmit_PPCISD_CMPB_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4568 if (RetVT.SimpleTy != MVT::i64) 4569 return 0; 4570 return fastEmitInst_rr(PPC::CMPB8, &PPC::G8RCRegClass, Op0, Op1); 4571} 4572 4573unsigned fastEmit_PPCISD_CMPB_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { 4574 switch (VT.SimpleTy) { 4575 case MVT::i32: return fastEmit_PPCISD_CMPB_MVT_i32_rr(RetVT, Op0, Op1); 4576 case MVT::i64: return fastEmit_PPCISD_CMPB_MVT_i64_rr(RetVT, Op0, Op1); 4577 default: return 0; 4578 } 4579} 4580 4581// FastEmit functions for PPCISD::FADDRTZ. 4582 4583unsigned fastEmit_PPCISD_FADDRTZ_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4584 if (RetVT.SimpleTy != MVT::f64) 4585 return 0; 4586 if ((Subtarget->hasFPU())) { 4587 return fastEmitInst_rr(PPC::FADDrtz, &PPC::F8RCRegClass, Op0, Op1); 4588 } 4589 return 0; 4590} 4591 4592unsigned fastEmit_PPCISD_FADDRTZ_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { 4593 switch (VT.SimpleTy) { 4594 case MVT::f64: return fastEmit_PPCISD_FADDRTZ_MVT_f64_rr(RetVT, Op0, Op1); 4595 default: return 0; 4596 } 4597} 4598 4599// FastEmit functions for PPCISD::GET_TLS_ADDR. 4600 4601unsigned fastEmit_PPCISD_GET_TLS_ADDR_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4602 if (RetVT.SimpleTy != MVT::i32) 4603 return 0; 4604 return fastEmitInst_rr(PPC::GETtlsADDR32AIX, &PPC::GPRCRegClass, Op0, Op1); 4605} 4606 4607unsigned fastEmit_PPCISD_GET_TLS_ADDR_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4608 if (RetVT.SimpleTy != MVT::i64) 4609 return 0; 4610 return fastEmitInst_rr(PPC::GETtlsADDR64AIX, &PPC::G8RCRegClass, Op0, Op1); 4611} 4612 4613unsigned fastEmit_PPCISD_GET_TLS_ADDR_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { 4614 switch (VT.SimpleTy) { 4615 case MVT::i32: return fastEmit_PPCISD_GET_TLS_ADDR_MVT_i32_rr(RetVT, Op0, Op1); 4616 case MVT::i64: return fastEmit_PPCISD_GET_TLS_ADDR_MVT_i64_rr(RetVT, Op0, Op1); 4617 default: return 0; 4618 } 4619} 4620 4621// FastEmit functions for PPCISD::SHL. 4622 4623unsigned fastEmit_PPCISD_SHL_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4624 if (RetVT.SimpleTy != MVT::i32) 4625 return 0; 4626 return fastEmitInst_rr(PPC::SLW, &PPC::GPRCRegClass, Op0, Op1); 4627} 4628 4629unsigned fastEmit_PPCISD_SHL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4630 if (RetVT.SimpleTy != MVT::v16i8) 4631 return 0; 4632 if ((Subtarget->hasAltivec())) { 4633 return fastEmitInst_rr(PPC::VSLB, &PPC::VRRCRegClass, Op0, Op1); 4634 } 4635 return 0; 4636} 4637 4638unsigned fastEmit_PPCISD_SHL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4639 if (RetVT.SimpleTy != MVT::v8i16) 4640 return 0; 4641 if ((Subtarget->hasAltivec())) { 4642 return fastEmitInst_rr(PPC::VSLH, &PPC::VRRCRegClass, Op0, Op1); 4643 } 4644 return 0; 4645} 4646 4647unsigned fastEmit_PPCISD_SHL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4648 if (RetVT.SimpleTy != MVT::v4i32) 4649 return 0; 4650 if ((Subtarget->hasAltivec())) { 4651 return fastEmitInst_rr(PPC::VSLW, &PPC::VRRCRegClass, Op0, Op1); 4652 } 4653 return 0; 4654} 4655 4656unsigned fastEmit_PPCISD_SHL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4657 if (RetVT.SimpleTy != MVT::v2i64) 4658 return 0; 4659 if ((Subtarget->hasP8Altivec())) { 4660 return fastEmitInst_rr(PPC::VSLD, &PPC::VRRCRegClass, Op0, Op1); 4661 } 4662 return 0; 4663} 4664 4665unsigned fastEmit_PPCISD_SHL_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { 4666 switch (VT.SimpleTy) { 4667 case MVT::i32: return fastEmit_PPCISD_SHL_MVT_i32_rr(RetVT, Op0, Op1); 4668 case MVT::v16i8: return fastEmit_PPCISD_SHL_MVT_v16i8_rr(RetVT, Op0, Op1); 4669 case MVT::v8i16: return fastEmit_PPCISD_SHL_MVT_v8i16_rr(RetVT, Op0, Op1); 4670 case MVT::v4i32: return fastEmit_PPCISD_SHL_MVT_v4i32_rr(RetVT, Op0, Op1); 4671 case MVT::v2i64: return fastEmit_PPCISD_SHL_MVT_v2i64_rr(RetVT, Op0, Op1); 4672 default: return 0; 4673 } 4674} 4675 4676// FastEmit functions for PPCISD::SRA. 4677 4678unsigned fastEmit_PPCISD_SRA_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4679 if (RetVT.SimpleTy != MVT::i32) 4680 return 0; 4681 return fastEmitInst_rr(PPC::SRAW, &PPC::GPRCRegClass, Op0, Op1); 4682} 4683 4684unsigned fastEmit_PPCISD_SRA_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4685 if (RetVT.SimpleTy != MVT::v16i8) 4686 return 0; 4687 if ((Subtarget->hasAltivec())) { 4688 return fastEmitInst_rr(PPC::VSRAB, &PPC::VRRCRegClass, Op0, Op1); 4689 } 4690 return 0; 4691} 4692 4693unsigned fastEmit_PPCISD_SRA_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4694 if (RetVT.SimpleTy != MVT::v8i16) 4695 return 0; 4696 if ((Subtarget->hasAltivec())) { 4697 return fastEmitInst_rr(PPC::VSRAH, &PPC::VRRCRegClass, Op0, Op1); 4698 } 4699 return 0; 4700} 4701 4702unsigned fastEmit_PPCISD_SRA_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4703 if (RetVT.SimpleTy != MVT::v4i32) 4704 return 0; 4705 if ((Subtarget->hasAltivec())) { 4706 return fastEmitInst_rr(PPC::VSRAW, &PPC::VRRCRegClass, Op0, Op1); 4707 } 4708 return 0; 4709} 4710 4711unsigned fastEmit_PPCISD_SRA_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4712 if (RetVT.SimpleTy != MVT::v2i64) 4713 return 0; 4714 if ((Subtarget->hasP8Altivec())) { 4715 return fastEmitInst_rr(PPC::VSRAD, &PPC::VRRCRegClass, Op0, Op1); 4716 } 4717 return 0; 4718} 4719 4720unsigned fastEmit_PPCISD_SRA_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { 4721 switch (VT.SimpleTy) { 4722 case MVT::i32: return fastEmit_PPCISD_SRA_MVT_i32_rr(RetVT, Op0, Op1); 4723 case MVT::v16i8: return fastEmit_PPCISD_SRA_MVT_v16i8_rr(RetVT, Op0, Op1); 4724 case MVT::v8i16: return fastEmit_PPCISD_SRA_MVT_v8i16_rr(RetVT, Op0, Op1); 4725 case MVT::v4i32: return fastEmit_PPCISD_SRA_MVT_v4i32_rr(RetVT, Op0, Op1); 4726 case MVT::v2i64: return fastEmit_PPCISD_SRA_MVT_v2i64_rr(RetVT, Op0, Op1); 4727 default: return 0; 4728 } 4729} 4730 4731// FastEmit functions for PPCISD::SRL. 4732 4733unsigned fastEmit_PPCISD_SRL_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4734 if (RetVT.SimpleTy != MVT::i32) 4735 return 0; 4736 return fastEmitInst_rr(PPC::SRW, &PPC::GPRCRegClass, Op0, Op1); 4737} 4738 4739unsigned fastEmit_PPCISD_SRL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4740 if (RetVT.SimpleTy != MVT::v16i8) 4741 return 0; 4742 if ((Subtarget->hasAltivec())) { 4743 return fastEmitInst_rr(PPC::VSRB, &PPC::VRRCRegClass, Op0, Op1); 4744 } 4745 return 0; 4746} 4747 4748unsigned fastEmit_PPCISD_SRL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4749 if (RetVT.SimpleTy != MVT::v8i16) 4750 return 0; 4751 if ((Subtarget->hasAltivec())) { 4752 return fastEmitInst_rr(PPC::VSRH, &PPC::VRRCRegClass, Op0, Op1); 4753 } 4754 return 0; 4755} 4756 4757unsigned fastEmit_PPCISD_SRL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4758 if (RetVT.SimpleTy != MVT::v4i32) 4759 return 0; 4760 if ((Subtarget->hasAltivec())) { 4761 return fastEmitInst_rr(PPC::VSRW, &PPC::VRRCRegClass, Op0, Op1); 4762 } 4763 return 0; 4764} 4765 4766unsigned fastEmit_PPCISD_SRL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4767 if (RetVT.SimpleTy != MVT::v2i64) 4768 return 0; 4769 if ((Subtarget->hasP8Altivec())) { 4770 return fastEmitInst_rr(PPC::VSRD, &PPC::VRRCRegClass, Op0, Op1); 4771 } 4772 return 0; 4773} 4774 4775unsigned fastEmit_PPCISD_SRL_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { 4776 switch (VT.SimpleTy) { 4777 case MVT::i32: return fastEmit_PPCISD_SRL_MVT_i32_rr(RetVT, Op0, Op1); 4778 case MVT::v16i8: return fastEmit_PPCISD_SRL_MVT_v16i8_rr(RetVT, Op0, Op1); 4779 case MVT::v8i16: return fastEmit_PPCISD_SRL_MVT_v8i16_rr(RetVT, Op0, Op1); 4780 case MVT::v4i32: return fastEmit_PPCISD_SRL_MVT_v4i32_rr(RetVT, Op0, Op1); 4781 case MVT::v2i64: return fastEmit_PPCISD_SRL_MVT_v2i64_rr(RetVT, Op0, Op1); 4782 default: return 0; 4783 } 4784} 4785 4786// FastEmit functions for PPCISD::STRICT_FADDRTZ. 4787 4788unsigned fastEmit_PPCISD_STRICT_FADDRTZ_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4789 if (RetVT.SimpleTy != MVT::f64) 4790 return 0; 4791 if ((Subtarget->hasFPU())) { 4792 return fastEmitInst_rr(PPC::FADDrtz, &PPC::F8RCRegClass, Op0, Op1); 4793 } 4794 return 0; 4795} 4796 4797unsigned fastEmit_PPCISD_STRICT_FADDRTZ_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { 4798 switch (VT.SimpleTy) { 4799 case MVT::f64: return fastEmit_PPCISD_STRICT_FADDRTZ_MVT_f64_rr(RetVT, Op0, Op1); 4800 default: return 0; 4801 } 4802} 4803 4804// FastEmit functions for PPCISD::TLSGD_AIX. 4805 4806unsigned fastEmit_PPCISD_TLSGD_AIX_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4807 if (RetVT.SimpleTy != MVT::i32) 4808 return 0; 4809 return fastEmitInst_rr(PPC::TLSGDAIX, &PPC::GPRCRegClass, Op0, Op1); 4810} 4811 4812unsigned fastEmit_PPCISD_TLSGD_AIX_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4813 if (RetVT.SimpleTy != MVT::i64) 4814 return 0; 4815 return fastEmitInst_rr(PPC::TLSGDAIX8, &PPC::G8RCRegClass, Op0, Op1); 4816} 4817 4818unsigned fastEmit_PPCISD_TLSGD_AIX_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { 4819 switch (VT.SimpleTy) { 4820 case MVT::i32: return fastEmit_PPCISD_TLSGD_AIX_MVT_i32_rr(RetVT, Op0, Op1); 4821 case MVT::i64: return fastEmit_PPCISD_TLSGD_AIX_MVT_i64_rr(RetVT, Op0, Op1); 4822 default: return 0; 4823 } 4824} 4825 4826// FastEmit functions for PPCISD::XSMAXC. 4827 4828unsigned fastEmit_PPCISD_XSMAXC_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4829 if (RetVT.SimpleTy != MVT::f64) 4830 return 0; 4831 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) { 4832 return fastEmitInst_rr(PPC::XSMAXCDP, &PPC::VSFRCRegClass, Op0, Op1); 4833 } 4834 return 0; 4835} 4836 4837unsigned fastEmit_PPCISD_XSMAXC_MVT_f128_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4838 if (RetVT.SimpleTy != MVT::f128) 4839 return 0; 4840 if ((Subtarget->hasVSX()) && (Subtarget->isISA3_1())) { 4841 return fastEmitInst_rr(PPC::XSMAXCQP, &PPC::VRRCRegClass, Op0, Op1); 4842 } 4843 return 0; 4844} 4845 4846unsigned fastEmit_PPCISD_XSMAXC_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { 4847 switch (VT.SimpleTy) { 4848 case MVT::f64: return fastEmit_PPCISD_XSMAXC_MVT_f64_rr(RetVT, Op0, Op1); 4849 case MVT::f128: return fastEmit_PPCISD_XSMAXC_MVT_f128_rr(RetVT, Op0, Op1); 4850 default: return 0; 4851 } 4852} 4853 4854// FastEmit functions for PPCISD::XSMINC. 4855 4856unsigned fastEmit_PPCISD_XSMINC_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4857 if (RetVT.SimpleTy != MVT::f64) 4858 return 0; 4859 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) { 4860 return fastEmitInst_rr(PPC::XSMINCDP, &PPC::VSFRCRegClass, Op0, Op1); 4861 } 4862 return 0; 4863} 4864 4865unsigned fastEmit_PPCISD_XSMINC_MVT_f128_rr(MVT RetVT, unsigned Op0, unsigned Op1) { 4866 if (RetVT.SimpleTy != MVT::f128) 4867 return 0; 4868 if ((Subtarget->hasVSX()) && (Subtarget->isISA3_1())) { 4869 return fastEmitInst_rr(PPC::XSMINCQP, &PPC::VRRCRegClass, Op0, Op1); 4870 } 4871 return 0; 4872} 4873 4874unsigned fastEmit_PPCISD_XSMINC_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { 4875 switch (VT.SimpleTy) { 4876 case MVT::f64: return fastEmit_PPCISD_XSMINC_MVT_f64_rr(RetVT, Op0, Op1); 4877 case MVT::f128: return fastEmit_PPCISD_XSMINC_MVT_f128_rr(RetVT, Op0, Op1); 4878 default: return 0; 4879 } 4880} 4881 4882// Top-level FastEmit function. 4883 4884unsigned fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, unsigned Op1) override { 4885 switch (Opcode) { 4886 case ISD::ADD: return fastEmit_ISD_ADD_rr(VT, RetVT, Op0, Op1); 4887 case ISD::ADDC: return fastEmit_ISD_ADDC_rr(VT, RetVT, Op0, Op1); 4888 case ISD::ADDE: return fastEmit_ISD_ADDE_rr(VT, RetVT, Op0, Op1); 4889 case ISD::AND: return fastEmit_ISD_AND_rr(VT, RetVT, Op0, Op1); 4890 case ISD::BUILD_VECTOR: return fastEmit_ISD_BUILD_VECTOR_rr(VT, RetVT, Op0, Op1); 4891 case ISD::FADD: return fastEmit_ISD_FADD_rr(VT, RetVT, Op0, Op1); 4892 case ISD::FDIV: return fastEmit_ISD_FDIV_rr(VT, RetVT, Op0, Op1); 4893 case ISD::FMAXNUM: return fastEmit_ISD_FMAXNUM_rr(VT, RetVT, Op0, Op1); 4894 case ISD::FMAXNUM_IEEE: return fastEmit_ISD_FMAXNUM_IEEE_rr(VT, RetVT, Op0, Op1); 4895 case ISD::FMINNUM: return fastEmit_ISD_FMINNUM_rr(VT, RetVT, Op0, Op1); 4896 case ISD::FMINNUM_IEEE: return fastEmit_ISD_FMINNUM_IEEE_rr(VT, RetVT, Op0, Op1); 4897 case ISD::FMUL: return fastEmit_ISD_FMUL_rr(VT, RetVT, Op0, Op1); 4898 case ISD::FSUB: return fastEmit_ISD_FSUB_rr(VT, RetVT, Op0, Op1); 4899 case ISD::MUL: return fastEmit_ISD_MUL_rr(VT, RetVT, Op0, Op1); 4900 case ISD::MULHS: return fastEmit_ISD_MULHS_rr(VT, RetVT, Op0, Op1); 4901 case ISD::MULHU: return fastEmit_ISD_MULHU_rr(VT, RetVT, Op0, Op1); 4902 case ISD::OR: return fastEmit_ISD_OR_rr(VT, RetVT, Op0, Op1); 4903 case ISD::ROTL: return fastEmit_ISD_ROTL_rr(VT, RetVT, Op0, Op1); 4904 case ISD::SADDSAT: return fastEmit_ISD_SADDSAT_rr(VT, RetVT, Op0, Op1); 4905 case ISD::SDIV: return fastEmit_ISD_SDIV_rr(VT, RetVT, Op0, Op1); 4906 case ISD::SHL: return fastEmit_ISD_SHL_rr(VT, RetVT, Op0, Op1); 4907 case ISD::SMAX: return fastEmit_ISD_SMAX_rr(VT, RetVT, Op0, Op1); 4908 case ISD::SMIN: return fastEmit_ISD_SMIN_rr(VT, RetVT, Op0, Op1); 4909 case ISD::SRA: return fastEmit_ISD_SRA_rr(VT, RetVT, Op0, Op1); 4910 case ISD::SREM: return fastEmit_ISD_SREM_rr(VT, RetVT, Op0, Op1); 4911 case ISD::SRL: return fastEmit_ISD_SRL_rr(VT, RetVT, Op0, Op1); 4912 case ISD::SSUBSAT: return fastEmit_ISD_SSUBSAT_rr(VT, RetVT, Op0, Op1); 4913 case ISD::STRICT_FADD: return fastEmit_ISD_STRICT_FADD_rr(VT, RetVT, Op0, Op1); 4914 case ISD::STRICT_FDIV: return fastEmit_ISD_STRICT_FDIV_rr(VT, RetVT, Op0, Op1); 4915 case ISD::STRICT_FMAXNUM: return fastEmit_ISD_STRICT_FMAXNUM_rr(VT, RetVT, Op0, Op1); 4916 case ISD::STRICT_FMINNUM: return fastEmit_ISD_STRICT_FMINNUM_rr(VT, RetVT, Op0, Op1); 4917 case ISD::STRICT_FMUL: return fastEmit_ISD_STRICT_FMUL_rr(VT, RetVT, Op0, Op1); 4918 case ISD::STRICT_FSUB: return fastEmit_ISD_STRICT_FSUB_rr(VT, RetVT, Op0, Op1); 4919 case ISD::SUB: return fastEmit_ISD_SUB_rr(VT, RetVT, Op0, Op1); 4920 case ISD::UADDSAT: return fastEmit_ISD_UADDSAT_rr(VT, RetVT, Op0, Op1); 4921 case ISD::UDIV: return fastEmit_ISD_UDIV_rr(VT, RetVT, Op0, Op1); 4922 case ISD::UMAX: return fastEmit_ISD_UMAX_rr(VT, RetVT, Op0, Op1); 4923 case ISD::UMIN: return fastEmit_ISD_UMIN_rr(VT, RetVT, Op0, Op1); 4924 case ISD::UREM: return fastEmit_ISD_UREM_rr(VT, RetVT, Op0, Op1); 4925 case ISD::USUBSAT: return fastEmit_ISD_USUBSAT_rr(VT, RetVT, Op0, Op1); 4926 case ISD::XOR: return fastEmit_ISD_XOR_rr(VT, RetVT, Op0, Op1); 4927 case PPCISD::CMPB: return fastEmit_PPCISD_CMPB_rr(VT, RetVT, Op0, Op1); 4928 case PPCISD::FADDRTZ: return fastEmit_PPCISD_FADDRTZ_rr(VT, RetVT, Op0, Op1); 4929 case PPCISD::GET_TLS_ADDR: return fastEmit_PPCISD_GET_TLS_ADDR_rr(VT, RetVT, Op0, Op1); 4930 case PPCISD::SHL: return fastEmit_PPCISD_SHL_rr(VT, RetVT, Op0, Op1); 4931 case PPCISD::SRA: return fastEmit_PPCISD_SRA_rr(VT, RetVT, Op0, Op1); 4932 case PPCISD::SRL: return fastEmit_PPCISD_SRL_rr(VT, RetVT, Op0, Op1); 4933 case PPCISD::STRICT_FADDRTZ: return fastEmit_PPCISD_STRICT_FADDRTZ_rr(VT, RetVT, Op0, Op1); 4934 case PPCISD::TLSGD_AIX: return fastEmit_PPCISD_TLSGD_AIX_rr(VT, RetVT, Op0, Op1); 4935 case PPCISD::XSMAXC: return fastEmit_PPCISD_XSMAXC_rr(VT, RetVT, Op0, Op1); 4936 case PPCISD::XSMINC: return fastEmit_PPCISD_XSMINC_rr(VT, RetVT, Op0, Op1); 4937 default: return 0; 4938 } 4939} 4940 4941// FastEmit functions for ISD::SRA. 4942 4943unsigned fastEmit_ISD_SRA_MVT_i32_ri(MVT RetVT, unsigned Op0, uint64_t imm1) { 4944 if (RetVT.SimpleTy != MVT::i32) 4945 return 0; 4946 return fastEmitInst_ri(PPC::SRAWI, &PPC::GPRCRegClass, Op0, imm1); 4947} 4948 4949unsigned fastEmit_ISD_SRA_MVT_i64_ri(MVT RetVT, unsigned Op0, uint64_t imm1) { 4950 if (RetVT.SimpleTy != MVT::i64) 4951 return 0; 4952 return fastEmitInst_ri(PPC::SRADI, &PPC::G8RCRegClass, Op0, imm1); 4953} 4954 4955unsigned fastEmit_ISD_SRA_ri(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { 4956 switch (VT.SimpleTy) { 4957 case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_ri(RetVT, Op0, imm1); 4958 case MVT::i64: return fastEmit_ISD_SRA_MVT_i64_ri(RetVT, Op0, imm1); 4959 default: return 0; 4960 } 4961} 4962 4963// FastEmit functions for PPCISD::EXTSWSLI. 4964 4965unsigned fastEmit_PPCISD_EXTSWSLI_MVT_i32_ri(MVT RetVT, unsigned Op0, uint64_t imm1) { 4966 if (RetVT.SimpleTy != MVT::i64) 4967 return 0; 4968 if ((Subtarget->isISA3_0())) { 4969 return fastEmitInst_ri(PPC::EXTSWSLI_32_64, &PPC::G8RCRegClass, Op0, imm1); 4970 } 4971 return 0; 4972} 4973 4974unsigned fastEmit_PPCISD_EXTSWSLI_ri(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { 4975 switch (VT.SimpleTy) { 4976 case MVT::i32: return fastEmit_PPCISD_EXTSWSLI_MVT_i32_ri(RetVT, Op0, imm1); 4977 default: return 0; 4978 } 4979} 4980 4981// FastEmit functions for PPCISD::TC_RETURN. 4982 4983unsigned fastEmit_PPCISD_TC_RETURN_MVT_i32_ri(MVT RetVT, unsigned Op0, uint64_t imm1) { 4984 if (RetVT.SimpleTy != MVT::isVoid) 4985 return 0; 4986 return fastEmitInst_ri(PPC::TCRETURNri, &PPC::CTRRCRegClass, Op0, imm1); 4987} 4988 4989unsigned fastEmit_PPCISD_TC_RETURN_MVT_i64_ri(MVT RetVT, unsigned Op0, uint64_t imm1) { 4990 if (RetVT.SimpleTy != MVT::isVoid) 4991 return 0; 4992 return fastEmitInst_ri(PPC::TCRETURNri8, &PPC::CTRRC8RegClass, Op0, imm1); 4993} 4994 4995unsigned fastEmit_PPCISD_TC_RETURN_ri(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { 4996 switch (VT.SimpleTy) { 4997 case MVT::i32: return fastEmit_PPCISD_TC_RETURN_MVT_i32_ri(RetVT, Op0, imm1); 4998 case MVT::i64: return fastEmit_PPCISD_TC_RETURN_MVT_i64_ri(RetVT, Op0, imm1); 4999 default: return 0; 5000 } 5001} 5002 5003// Top-level FastEmit function. 5004 5005unsigned fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, uint64_t imm1) override { 5006 if (VT == MVT::i32 && Predicate_imm32SExt16(imm1)) 5007 if (unsigned Reg = fastEmit_ri_Predicate_imm32SExt16(VT, RetVT, Opcode, Op0, imm1)) 5008 return Reg; 5009 5010 if (VT == MVT::i64 && Predicate_imm64SExt16(imm1)) 5011 if (unsigned Reg = fastEmit_ri_Predicate_imm64SExt16(VT, RetVT, Opcode, Op0, imm1)) 5012 return Reg; 5013 5014 switch (Opcode) { 5015 case ISD::SRA: return fastEmit_ISD_SRA_ri(VT, RetVT, Op0, imm1); 5016 case PPCISD::EXTSWSLI: return fastEmit_PPCISD_EXTSWSLI_ri(VT, RetVT, Op0, imm1); 5017 case PPCISD::TC_RETURN: return fastEmit_PPCISD_TC_RETURN_ri(VT, RetVT, Op0, imm1); 5018 default: return 0; 5019 } 5020} 5021 5022// FastEmit functions for ISD::ADD. 5023 5024unsigned fastEmit_ISD_ADD_MVT_i32_ri_Predicate_imm32SExt16(MVT RetVT, unsigned Op0, uint64_t imm1) { 5025 if (RetVT.SimpleTy != MVT::i32) 5026 return 0; 5027 return fastEmitInst_ri(PPC::ADDI, &PPC::GPRCRegClass, Op0, imm1); 5028} 5029 5030unsigned fastEmit_ISD_ADD_ri_Predicate_imm32SExt16(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { 5031 switch (VT.SimpleTy) { 5032 case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_imm32SExt16(RetVT, Op0, imm1); 5033 default: return 0; 5034 } 5035} 5036 5037// FastEmit functions for ISD::ADDC. 5038 5039unsigned fastEmit_ISD_ADDC_MVT_i32_ri_Predicate_imm32SExt16(MVT RetVT, unsigned Op0, uint64_t imm1) { 5040 if (RetVT.SimpleTy != MVT::i32) 5041 return 0; 5042 return fastEmitInst_ri(PPC::ADDIC, &PPC::GPRCRegClass, Op0, imm1); 5043} 5044 5045unsigned fastEmit_ISD_ADDC_ri_Predicate_imm32SExt16(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { 5046 switch (VT.SimpleTy) { 5047 case MVT::i32: return fastEmit_ISD_ADDC_MVT_i32_ri_Predicate_imm32SExt16(RetVT, Op0, imm1); 5048 default: return 0; 5049 } 5050} 5051 5052// FastEmit functions for ISD::MUL. 5053 5054unsigned fastEmit_ISD_MUL_MVT_i32_ri_Predicate_imm32SExt16(MVT RetVT, unsigned Op0, uint64_t imm1) { 5055 if (RetVT.SimpleTy != MVT::i32) 5056 return 0; 5057 return fastEmitInst_ri(PPC::MULLI, &PPC::GPRCRegClass, Op0, imm1); 5058} 5059 5060unsigned fastEmit_ISD_MUL_ri_Predicate_imm32SExt16(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { 5061 switch (VT.SimpleTy) { 5062 case MVT::i32: return fastEmit_ISD_MUL_MVT_i32_ri_Predicate_imm32SExt16(RetVT, Op0, imm1); 5063 default: return 0; 5064 } 5065} 5066 5067// FastEmit functions for PPCISD::XXSPLT. 5068 5069unsigned fastEmit_PPCISD_XXSPLT_MVT_v4i32_ri_Predicate_imm32SExt16(MVT RetVT, unsigned Op0, uint64_t imm1) { 5070 if (RetVT.SimpleTy != MVT::v4i32) 5071 return 0; 5072 if ((Subtarget->hasVSX())) { 5073 return fastEmitInst_ri(PPC::XXSPLTW, &PPC::VSRCRegClass, Op0, imm1); 5074 } 5075 return 0; 5076} 5077 5078unsigned fastEmit_PPCISD_XXSPLT_ri_Predicate_imm32SExt16(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { 5079 switch (VT.SimpleTy) { 5080 case MVT::v4i32: return fastEmit_PPCISD_XXSPLT_MVT_v4i32_ri_Predicate_imm32SExt16(RetVT, Op0, imm1); 5081 default: return 0; 5082 } 5083} 5084 5085// Top-level FastEmit function. 5086 5087unsigned fastEmit_ri_Predicate_imm32SExt16(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, uint64_t imm1) { 5088 switch (Opcode) { 5089 case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_imm32SExt16(VT, RetVT, Op0, imm1); 5090 case ISD::ADDC: return fastEmit_ISD_ADDC_ri_Predicate_imm32SExt16(VT, RetVT, Op0, imm1); 5091 case ISD::MUL: return fastEmit_ISD_MUL_ri_Predicate_imm32SExt16(VT, RetVT, Op0, imm1); 5092 case PPCISD::XXSPLT: return fastEmit_PPCISD_XXSPLT_ri_Predicate_imm32SExt16(VT, RetVT, Op0, imm1); 5093 default: return 0; 5094 } 5095} 5096 5097// FastEmit functions for ISD::ADD. 5098 5099unsigned fastEmit_ISD_ADD_MVT_i64_ri_Predicate_imm64SExt16(MVT RetVT, unsigned Op0, uint64_t imm1) { 5100 if (RetVT.SimpleTy != MVT::i64) 5101 return 0; 5102 return fastEmitInst_ri(PPC::ADDI8, &PPC::G8RCRegClass, Op0, imm1); 5103} 5104 5105unsigned fastEmit_ISD_ADD_ri_Predicate_imm64SExt16(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { 5106 switch (VT.SimpleTy) { 5107 case MVT::i64: return fastEmit_ISD_ADD_MVT_i64_ri_Predicate_imm64SExt16(RetVT, Op0, imm1); 5108 default: return 0; 5109 } 5110} 5111 5112// FastEmit functions for ISD::ADDC. 5113 5114unsigned fastEmit_ISD_ADDC_MVT_i64_ri_Predicate_imm64SExt16(MVT RetVT, unsigned Op0, uint64_t imm1) { 5115 if (RetVT.SimpleTy != MVT::i64) 5116 return 0; 5117 return fastEmitInst_ri(PPC::ADDIC8, &PPC::G8RCRegClass, Op0, imm1); 5118} 5119 5120unsigned fastEmit_ISD_ADDC_ri_Predicate_imm64SExt16(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { 5121 switch (VT.SimpleTy) { 5122 case MVT::i64: return fastEmit_ISD_ADDC_MVT_i64_ri_Predicate_imm64SExt16(RetVT, Op0, imm1); 5123 default: return 0; 5124 } 5125} 5126 5127// FastEmit functions for ISD::MUL. 5128 5129unsigned fastEmit_ISD_MUL_MVT_i64_ri_Predicate_imm64SExt16(MVT RetVT, unsigned Op0, uint64_t imm1) { 5130 if (RetVT.SimpleTy != MVT::i64) 5131 return 0; 5132 return fastEmitInst_ri(PPC::MULLI8, &PPC::G8RCRegClass, Op0, imm1); 5133} 5134 5135unsigned fastEmit_ISD_MUL_ri_Predicate_imm64SExt16(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { 5136 switch (VT.SimpleTy) { 5137 case MVT::i64: return fastEmit_ISD_MUL_MVT_i64_ri_Predicate_imm64SExt16(RetVT, Op0, imm1); 5138 default: return 0; 5139 } 5140} 5141 5142// Top-level FastEmit function. 5143 5144unsigned fastEmit_ri_Predicate_imm64SExt16(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, uint64_t imm1) { 5145 switch (Opcode) { 5146 case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_imm64SExt16(VT, RetVT, Op0, imm1); 5147 case ISD::ADDC: return fastEmit_ISD_ADDC_ri_Predicate_imm64SExt16(VT, RetVT, Op0, imm1); 5148 case ISD::MUL: return fastEmit_ISD_MUL_ri_Predicate_imm64SExt16(VT, RetVT, Op0, imm1); 5149 default: return 0; 5150 } 5151} 5152 5153