1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2|* *| 3|* Register Bank Source Fragments *| 4|* *| 5|* Automatically generated file, do not edit! *| 6|* *| 7\*===----------------------------------------------------------------------===*/ 8 9#ifdef GET_REGBANK_DECLARATIONS 10#undef GET_REGBANK_DECLARATIONS 11namespace llvm { 12namespace PPC { 13enum : unsigned { 14 InvalidRegBankID = ~0u, 15 CRRegBankID = 0, 16 FPRRegBankID = 1, 17 GPRRegBankID = 2, 18 NumRegisterBanks, 19}; 20} // end namespace PPC 21} // end namespace llvm 22#endif // GET_REGBANK_DECLARATIONS 23 24#ifdef GET_TARGET_REGBANK_CLASS 25#undef GET_TARGET_REGBANK_CLASS 26private: 27 static RegisterBank *RegBanks[]; 28 29protected: 30 PPCGenRegisterBankInfo(); 31 32#endif // GET_TARGET_REGBANK_CLASS 33 34#ifdef GET_TARGET_REGBANK_IMPL 35#undef GET_TARGET_REGBANK_IMPL 36namespace llvm { 37namespace PPC { 38const uint32_t CRRegBankCoverageData[] = { 39 // 0-31 40 (1u << (PPC::CRRCRegClassID - 0)) | 41 (1u << (PPC::CRBITRCRegClassID - 0)) | 42 0, 43 // 32-63 44 0, 45}; 46const uint32_t FPRRegBankCoverageData[] = { 47 // 0-31 48 (1u << (PPC::VSSRCRegClassID - 0)) | 49 (1u << (PPC::F4RCRegClassID - 0)) | 50 (1u << (PPC::F8RCRegClassID - 0)) | 51 (1u << (PPC::SPILLTOVSRRC_and_F4RCRegClassID - 0)) | 52 (1u << (PPC::VSFRCRegClassID - 0)) | 53 (1u << (PPC::SPILLTOVSRRC_and_VSFRCRegClassID - 0)) | 54 (1u << (PPC::SPILLTOVSRRC_and_VFRCRegClassID - 0)) | 55 (1u << (PPC::VFRCRegClassID - 0)) | 56 0, 57 // 32-63 58 0, 59}; 60const uint32_t GPRRegBankCoverageData[] = { 61 // 0-31 62 (1u << (PPC::G8RCRegClassID - 0)) | 63 (1u << (PPC::GPRCRegClassID - 0)) | 64 (1u << (PPC::G8RC_and_G8RC_NOX0RegClassID - 0)) | 65 (1u << (PPC::GPRC_NOR0RegClassID - 0)) | 66 (1u << (PPC::GPRC_and_GPRC_NOR0RegClassID - 0)) | 67 (1u << (PPC::G8RC_NOX0RegClassID - 0)) | 68 0, 69 // 32-63 70 0, 71}; 72 73RegisterBank CRRegBank(/* ID */ PPC::CRRegBankID, /* Name */ "CR", /* Size */ 32, /* CoveredRegClasses */ CRRegBankCoverageData, /* NumRegClasses */ 51); 74RegisterBank FPRRegBank(/* ID */ PPC::FPRRegBankID, /* Name */ "FPR", /* Size */ 64, /* CoveredRegClasses */ FPRRegBankCoverageData, /* NumRegClasses */ 51); 75RegisterBank GPRRegBank(/* ID */ PPC::GPRRegBankID, /* Name */ "GPR", /* Size */ 64, /* CoveredRegClasses */ GPRRegBankCoverageData, /* NumRegClasses */ 51); 76} // end namespace PPC 77 78RegisterBank *PPCGenRegisterBankInfo::RegBanks[] = { 79 &PPC::CRRegBank, 80 &PPC::FPRRegBank, 81 &PPC::GPRRegBank, 82}; 83 84PPCGenRegisterBankInfo::PPCGenRegisterBankInfo() 85 : RegisterBankInfo(RegBanks, PPC::NumRegisterBanks) { 86 // Assert that RegBank indices match their ID's 87#ifndef NDEBUG 88 for (auto RB : enumerate(RegBanks)) 89 assert(RB.index() == RB.value()->getID() && "Index != ID"); 90#endif // NDEBUG 91} 92} // end namespace llvm 93#endif // GET_TARGET_REGBANK_IMPL 94