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1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|*                                                                            *|
3|* Target Register Enum Values                                                *|
4|*                                                                            *|
5|* Automatically generated file, do not edit!                                 *|
6|*                                                                            *|
7\*===----------------------------------------------------------------------===*/
8
9
10#ifdef GET_REGINFO_ENUM
11#undef GET_REGINFO_ENUM
12
13namespace llvm {
14
15class MCRegisterClass;
16extern const MCRegisterClass PPCMCRegisterClasses[];
17
18namespace PPC {
19enum {
20  NoRegister,
21  BP = 1,
22  CARRY = 2,
23  CTR = 3,
24  FP = 4,
25  LR = 5,
26  RM = 6,
27  SPEFSCR = 7,
28  VRSAVE = 8,
29  XER = 9,
30  ZERO = 10,
31  ACC0 = 11,
32  ACC1 = 12,
33  ACC2 = 13,
34  ACC3 = 14,
35  ACC4 = 15,
36  ACC5 = 16,
37  ACC6 = 17,
38  ACC7 = 18,
39  BP8 = 19,
40  CR0 = 20,
41  CR1 = 21,
42  CR2 = 22,
43  CR3 = 23,
44  CR4 = 24,
45  CR5 = 25,
46  CR6 = 26,
47  CR7 = 27,
48  CTR8 = 28,
49  DMR0 = 29,
50  DMR1 = 30,
51  DMR2 = 31,
52  DMR3 = 32,
53  DMR4 = 33,
54  DMR5 = 34,
55  DMR6 = 35,
56  DMR7 = 36,
57  DMRROW0 = 37,
58  DMRROW1 = 38,
59  DMRROW2 = 39,
60  DMRROW3 = 40,
61  DMRROW4 = 41,
62  DMRROW5 = 42,
63  DMRROW6 = 43,
64  DMRROW7 = 44,
65  DMRROW8 = 45,
66  DMRROW9 = 46,
67  DMRROW10 = 47,
68  DMRROW11 = 48,
69  DMRROW12 = 49,
70  DMRROW13 = 50,
71  DMRROW14 = 51,
72  DMRROW15 = 52,
73  DMRROW16 = 53,
74  DMRROW17 = 54,
75  DMRROW18 = 55,
76  DMRROW19 = 56,
77  DMRROW20 = 57,
78  DMRROW21 = 58,
79  DMRROW22 = 59,
80  DMRROW23 = 60,
81  DMRROW24 = 61,
82  DMRROW25 = 62,
83  DMRROW26 = 63,
84  DMRROW27 = 64,
85  DMRROW28 = 65,
86  DMRROW29 = 66,
87  DMRROW30 = 67,
88  DMRROW31 = 68,
89  DMRROW32 = 69,
90  DMRROW33 = 70,
91  DMRROW34 = 71,
92  DMRROW35 = 72,
93  DMRROW36 = 73,
94  DMRROW37 = 74,
95  DMRROW38 = 75,
96  DMRROW39 = 76,
97  DMRROW40 = 77,
98  DMRROW41 = 78,
99  DMRROW42 = 79,
100  DMRROW43 = 80,
101  DMRROW44 = 81,
102  DMRROW45 = 82,
103  DMRROW46 = 83,
104  DMRROW47 = 84,
105  DMRROW48 = 85,
106  DMRROW49 = 86,
107  DMRROW50 = 87,
108  DMRROW51 = 88,
109  DMRROW52 = 89,
110  DMRROW53 = 90,
111  DMRROW54 = 91,
112  DMRROW55 = 92,
113  DMRROW56 = 93,
114  DMRROW57 = 94,
115  DMRROW58 = 95,
116  DMRROW59 = 96,
117  DMRROW60 = 97,
118  DMRROW61 = 98,
119  DMRROW62 = 99,
120  DMRROW63 = 100,
121  DMRROWp0 = 101,
122  DMRROWp1 = 102,
123  DMRROWp2 = 103,
124  DMRROWp3 = 104,
125  DMRROWp4 = 105,
126  DMRROWp5 = 106,
127  DMRROWp6 = 107,
128  DMRROWp7 = 108,
129  DMRROWp8 = 109,
130  DMRROWp9 = 110,
131  DMRROWp10 = 111,
132  DMRROWp11 = 112,
133  DMRROWp12 = 113,
134  DMRROWp13 = 114,
135  DMRROWp14 = 115,
136  DMRROWp15 = 116,
137  DMRROWp16 = 117,
138  DMRROWp17 = 118,
139  DMRROWp18 = 119,
140  DMRROWp19 = 120,
141  DMRROWp20 = 121,
142  DMRROWp21 = 122,
143  DMRROWp22 = 123,
144  DMRROWp23 = 124,
145  DMRROWp24 = 125,
146  DMRROWp25 = 126,
147  DMRROWp26 = 127,
148  DMRROWp27 = 128,
149  DMRROWp28 = 129,
150  DMRROWp29 = 130,
151  DMRROWp30 = 131,
152  DMRROWp31 = 132,
153  DMRp0 = 133,
154  DMRp1 = 134,
155  DMRp2 = 135,
156  DMRp3 = 136,
157  F0 = 137,
158  F1 = 138,
159  F2 = 139,
160  F3 = 140,
161  F4 = 141,
162  F5 = 142,
163  F6 = 143,
164  F7 = 144,
165  F8 = 145,
166  F9 = 146,
167  F10 = 147,
168  F11 = 148,
169  F12 = 149,
170  F13 = 150,
171  F14 = 151,
172  F15 = 152,
173  F16 = 153,
174  F17 = 154,
175  F18 = 155,
176  F19 = 156,
177  F20 = 157,
178  F21 = 158,
179  F22 = 159,
180  F23 = 160,
181  F24 = 161,
182  F25 = 162,
183  F26 = 163,
184  F27 = 164,
185  F28 = 165,
186  F29 = 166,
187  F30 = 167,
188  F31 = 168,
189  FP8 = 169,
190  LR8 = 170,
191  R0 = 171,
192  R1 = 172,
193  R2 = 173,
194  R3 = 174,
195  R4 = 175,
196  R5 = 176,
197  R6 = 177,
198  R7 = 178,
199  R8 = 179,
200  R9 = 180,
201  R10 = 181,
202  R11 = 182,
203  R12 = 183,
204  R13 = 184,
205  R14 = 185,
206  R15 = 186,
207  R16 = 187,
208  R17 = 188,
209  R18 = 189,
210  R19 = 190,
211  R20 = 191,
212  R21 = 192,
213  R22 = 193,
214  R23 = 194,
215  R24 = 195,
216  R25 = 196,
217  R26 = 197,
218  R27 = 198,
219  R28 = 199,
220  R29 = 200,
221  R30 = 201,
222  R31 = 202,
223  S0 = 203,
224  S1 = 204,
225  S2 = 205,
226  S3 = 206,
227  S4 = 207,
228  S5 = 208,
229  S6 = 209,
230  S7 = 210,
231  S8 = 211,
232  S9 = 212,
233  S10 = 213,
234  S11 = 214,
235  S12 = 215,
236  S13 = 216,
237  S14 = 217,
238  S15 = 218,
239  S16 = 219,
240  S17 = 220,
241  S18 = 221,
242  S19 = 222,
243  S20 = 223,
244  S21 = 224,
245  S22 = 225,
246  S23 = 226,
247  S24 = 227,
248  S25 = 228,
249  S26 = 229,
250  S27 = 230,
251  S28 = 231,
252  S29 = 232,
253  S30 = 233,
254  S31 = 234,
255  UACC0 = 235,
256  UACC1 = 236,
257  UACC2 = 237,
258  UACC3 = 238,
259  UACC4 = 239,
260  UACC5 = 240,
261  UACC6 = 241,
262  UACC7 = 242,
263  V0 = 243,
264  V1 = 244,
265  V2 = 245,
266  V3 = 246,
267  V4 = 247,
268  V5 = 248,
269  V6 = 249,
270  V7 = 250,
271  V8 = 251,
272  V9 = 252,
273  V10 = 253,
274  V11 = 254,
275  V12 = 255,
276  V13 = 256,
277  V14 = 257,
278  V15 = 258,
279  V16 = 259,
280  V17 = 260,
281  V18 = 261,
282  V19 = 262,
283  V20 = 263,
284  V21 = 264,
285  V22 = 265,
286  V23 = 266,
287  V24 = 267,
288  V25 = 268,
289  V26 = 269,
290  V27 = 270,
291  V28 = 271,
292  V29 = 272,
293  V30 = 273,
294  V31 = 274,
295  VF0 = 275,
296  VF1 = 276,
297  VF2 = 277,
298  VF3 = 278,
299  VF4 = 279,
300  VF5 = 280,
301  VF6 = 281,
302  VF7 = 282,
303  VF8 = 283,
304  VF9 = 284,
305  VF10 = 285,
306  VF11 = 286,
307  VF12 = 287,
308  VF13 = 288,
309  VF14 = 289,
310  VF15 = 290,
311  VF16 = 291,
312  VF17 = 292,
313  VF18 = 293,
314  VF19 = 294,
315  VF20 = 295,
316  VF21 = 296,
317  VF22 = 297,
318  VF23 = 298,
319  VF24 = 299,
320  VF25 = 300,
321  VF26 = 301,
322  VF27 = 302,
323  VF28 = 303,
324  VF29 = 304,
325  VF30 = 305,
326  VF31 = 306,
327  VSL0 = 307,
328  VSL1 = 308,
329  VSL2 = 309,
330  VSL3 = 310,
331  VSL4 = 311,
332  VSL5 = 312,
333  VSL6 = 313,
334  VSL7 = 314,
335  VSL8 = 315,
336  VSL9 = 316,
337  VSL10 = 317,
338  VSL11 = 318,
339  VSL12 = 319,
340  VSL13 = 320,
341  VSL14 = 321,
342  VSL15 = 322,
343  VSL16 = 323,
344  VSL17 = 324,
345  VSL18 = 325,
346  VSL19 = 326,
347  VSL20 = 327,
348  VSL21 = 328,
349  VSL22 = 329,
350  VSL23 = 330,
351  VSL24 = 331,
352  VSL25 = 332,
353  VSL26 = 333,
354  VSL27 = 334,
355  VSL28 = 335,
356  VSL29 = 336,
357  VSL30 = 337,
358  VSL31 = 338,
359  VSRp0 = 339,
360  VSRp1 = 340,
361  VSRp2 = 341,
362  VSRp3 = 342,
363  VSRp4 = 343,
364  VSRp5 = 344,
365  VSRp6 = 345,
366  VSRp7 = 346,
367  VSRp8 = 347,
368  VSRp9 = 348,
369  VSRp10 = 349,
370  VSRp11 = 350,
371  VSRp12 = 351,
372  VSRp13 = 352,
373  VSRp14 = 353,
374  VSRp15 = 354,
375  VSRp16 = 355,
376  VSRp17 = 356,
377  VSRp18 = 357,
378  VSRp19 = 358,
379  VSRp20 = 359,
380  VSRp21 = 360,
381  VSRp22 = 361,
382  VSRp23 = 362,
383  VSRp24 = 363,
384  VSRp25 = 364,
385  VSRp26 = 365,
386  VSRp27 = 366,
387  VSRp28 = 367,
388  VSRp29 = 368,
389  VSRp30 = 369,
390  VSRp31 = 370,
391  VSX32 = 371,
392  VSX33 = 372,
393  VSX34 = 373,
394  VSX35 = 374,
395  VSX36 = 375,
396  VSX37 = 376,
397  VSX38 = 377,
398  VSX39 = 378,
399  VSX40 = 379,
400  VSX41 = 380,
401  VSX42 = 381,
402  VSX43 = 382,
403  VSX44 = 383,
404  VSX45 = 384,
405  VSX46 = 385,
406  VSX47 = 386,
407  VSX48 = 387,
408  VSX49 = 388,
409  VSX50 = 389,
410  VSX51 = 390,
411  VSX52 = 391,
412  VSX53 = 392,
413  VSX54 = 393,
414  VSX55 = 394,
415  VSX56 = 395,
416  VSX57 = 396,
417  VSX58 = 397,
418  VSX59 = 398,
419  VSX60 = 399,
420  VSX61 = 400,
421  VSX62 = 401,
422  VSX63 = 402,
423  WACC0 = 403,
424  WACC1 = 404,
425  WACC2 = 405,
426  WACC3 = 406,
427  WACC4 = 407,
428  WACC5 = 408,
429  WACC6 = 409,
430  WACC7 = 410,
431  WACC_HI0 = 411,
432  WACC_HI1 = 412,
433  WACC_HI2 = 413,
434  WACC_HI3 = 414,
435  WACC_HI4 = 415,
436  WACC_HI5 = 416,
437  WACC_HI6 = 417,
438  WACC_HI7 = 418,
439  X0 = 419,
440  X1 = 420,
441  X2 = 421,
442  X3 = 422,
443  X4 = 423,
444  X5 = 424,
445  X6 = 425,
446  X7 = 426,
447  X8 = 427,
448  X9 = 428,
449  X10 = 429,
450  X11 = 430,
451  X12 = 431,
452  X13 = 432,
453  X14 = 433,
454  X15 = 434,
455  X16 = 435,
456  X17 = 436,
457  X18 = 437,
458  X19 = 438,
459  X20 = 439,
460  X21 = 440,
461  X22 = 441,
462  X23 = 442,
463  X24 = 443,
464  X25 = 444,
465  X26 = 445,
466  X27 = 446,
467  X28 = 447,
468  X29 = 448,
469  X30 = 449,
470  X31 = 450,
471  ZERO8 = 451,
472  CR0EQ = 452,
473  CR1EQ = 453,
474  CR2EQ = 454,
475  CR3EQ = 455,
476  CR4EQ = 456,
477  CR5EQ = 457,
478  CR6EQ = 458,
479  CR7EQ = 459,
480  CR0GT = 460,
481  CR1GT = 461,
482  CR2GT = 462,
483  CR3GT = 463,
484  CR4GT = 464,
485  CR5GT = 465,
486  CR6GT = 466,
487  CR7GT = 467,
488  CR0LT = 468,
489  CR1LT = 469,
490  CR2LT = 470,
491  CR3LT = 471,
492  CR4LT = 472,
493  CR5LT = 473,
494  CR6LT = 474,
495  CR7LT = 475,
496  CR0UN = 476,
497  CR1UN = 477,
498  CR2UN = 478,
499  CR3UN = 479,
500  CR4UN = 480,
501  CR5UN = 481,
502  CR6UN = 482,
503  CR7UN = 483,
504  G8p0 = 484,
505  G8p1 = 485,
506  G8p2 = 486,
507  G8p3 = 487,
508  G8p4 = 488,
509  G8p5 = 489,
510  G8p6 = 490,
511  G8p7 = 491,
512  G8p8 = 492,
513  G8p9 = 493,
514  G8p10 = 494,
515  G8p11 = 495,
516  G8p12 = 496,
517  G8p13 = 497,
518  G8p14 = 498,
519  G8p15 = 499,
520  NUM_TARGET_REGS // 500
521};
522} // end namespace PPC
523
524// Register classes
525
526namespace PPC {
527enum {
528  VSSRCRegClassID = 0,
529  GPRCRegClassID = 1,
530  GPRC_NOR0RegClassID = 2,
531  GPRC_and_GPRC_NOR0RegClassID = 3,
532  CRBITRCRegClassID = 4,
533  F4RCRegClassID = 5,
534  CRRCRegClassID = 6,
535  CARRYRCRegClassID = 7,
536  CTRRCRegClassID = 8,
537  LRRCRegClassID = 9,
538  VRSAVERCRegClassID = 10,
539  SPILLTOVSRRCRegClassID = 11,
540  VSFRCRegClassID = 12,
541  G8RCRegClassID = 13,
542  G8RC_NOX0RegClassID = 14,
543  SPILLTOVSRRC_and_VSFRCRegClassID = 15,
544  G8RC_and_G8RC_NOX0RegClassID = 16,
545  F8RCRegClassID = 17,
546  SPERCRegClassID = 18,
547  VFRCRegClassID = 19,
548  SPERC_with_sub_32_in_GPRC_NOR0RegClassID = 20,
549  SPILLTOVSRRC_and_VFRCRegClassID = 21,
550  SPILLTOVSRRC_and_F4RCRegClassID = 22,
551  CTRRC8RegClassID = 23,
552  LR8RCRegClassID = 24,
553  DMRROWRCRegClassID = 25,
554  VSRCRegClassID = 26,
555  VSRC_with_sub_64_in_SPILLTOVSRRCRegClassID = 27,
556  VRRCRegClassID = 28,
557  VSLRCRegClassID = 29,
558  VRRC_with_sub_64_in_SPILLTOVSRRCRegClassID = 30,
559  G8pRCRegClassID = 31,
560  G8pRC_with_sub_32_in_GPRC_NOR0RegClassID = 32,
561  VSLRC_with_sub_64_in_SPILLTOVSRRCRegClassID = 33,
562  DMRROWpRCRegClassID = 34,
563  VSRpRCRegClassID = 35,
564  VSRpRC_with_sub_64_in_SPILLTOVSRRCRegClassID = 36,
565  VSRpRC_with_sub_64_in_F4RCRegClassID = 37,
566  VSRpRC_with_sub_64_in_VFRCRegClassID = 38,
567  VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCRegClassID = 39,
568  VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCRegClassID = 40,
569  ACCRCRegClassID = 41,
570  UACCRCRegClassID = 42,
571  WACCRCRegClassID = 43,
572  WACC_HIRCRegClassID = 44,
573  ACCRC_with_sub_64_in_SPILLTOVSRRCRegClassID = 45,
574  UACCRC_with_sub_64_in_SPILLTOVSRRCRegClassID = 46,
575  ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCRegClassID = 47,
576  UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCRegClassID = 48,
577  DMRRCRegClassID = 49,
578  DMRpRCRegClassID = 50,
579
580};
581} // end namespace PPC
582
583
584// Subregister indices
585
586namespace PPC {
587enum : uint16_t {
588  NoSubRegister,
589  sub_32,	// 1
590  sub_64,	// 2
591  sub_dmr0,	// 3
592  sub_dmr1,	// 4
593  sub_dmrrow0,	// 5
594  sub_dmrrow1,	// 6
595  sub_dmrrowp0,	// 7
596  sub_dmrrowp1,	// 8
597  sub_eq,	// 9
598  sub_gp8_x0,	// 10
599  sub_gp8_x1,	// 11
600  sub_gt,	// 12
601  sub_lt,	// 13
602  sub_pair0,	// 14
603  sub_pair1,	// 15
604  sub_un,	// 16
605  sub_vsx0,	// 17
606  sub_vsx1,	// 18
607  sub_wacc_hi,	// 19
608  sub_wacc_lo,	// 20
609  sub_vsx1_then_sub_64,	// 21
610  sub_pair1_then_sub_64,	// 22
611  sub_pair1_then_sub_vsx0,	// 23
612  sub_pair1_then_sub_vsx1,	// 24
613  sub_pair1_then_sub_vsx1_then_sub_64,	// 25
614  sub_dmrrowp1_then_sub_dmrrow0,	// 26
615  sub_dmrrowp1_then_sub_dmrrow1,	// 27
616  sub_wacc_hi_then_sub_dmrrow0,	// 28
617  sub_wacc_hi_then_sub_dmrrow1,	// 29
618  sub_wacc_hi_then_sub_dmrrowp0,	// 30
619  sub_wacc_hi_then_sub_dmrrowp1,	// 31
620  sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0,	// 32
621  sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1,	// 33
622  sub_dmr1_then_sub_dmrrow0,	// 34
623  sub_dmr1_then_sub_dmrrow1,	// 35
624  sub_dmr1_then_sub_dmrrowp0,	// 36
625  sub_dmr1_then_sub_dmrrowp1,	// 37
626  sub_dmr1_then_sub_wacc_hi,	// 38
627  sub_dmr1_then_sub_wacc_lo,	// 39
628  sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0,	// 40
629  sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1,	// 41
630  sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0,	// 42
631  sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1,	// 43
632  sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0,	// 44
633  sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1,	// 45
634  sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0,	// 46
635  sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1,	// 47
636  sub_gp8_x1_then_sub_32,	// 48
637  NUM_TARGET_SUBREGS
638};
639} // end namespace PPC
640
641// Register pressure sets enum.
642namespace PPC {
643enum RegisterPressureSets {
644  CARRYRC = 0,
645  VRSAVERC = 1,
646  SPILLTOVSRRC_and_F4RC = 2,
647  SPILLTOVSRRC_and_VFRC = 3,
648  CRBITRC = 4,
649  F4RC = 5,
650  VFRC = 6,
651  WACCRC = 7,
652  WACC_HIRC = 8,
653  GPRC = 9,
654  SPILLTOVSRRC_and_VSFRC = 10,
655  SPILLTOVSRRC_and_VSFRC_with_VFRC = 11,
656  F4RC_with_SPILLTOVSRRC_and_VSFRC = 12,
657  VSSRC = 13,
658  DMRROWRC = 14,
659  SPILLTOVSRRC = 15,
660  SPILLTOVSRRC_with_SPILLTOVSRRC_and_F4RC = 16,
661  SPILLTOVSRRC_with_VFRC = 17,
662  F4RC_with_SPILLTOVSRRC = 18,
663  VSSRC_with_SPILLTOVSRRC = 19,
664};
665} // end namespace PPC
666
667} // end namespace llvm
668
669#endif // GET_REGINFO_ENUM
670
671/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
672|*                                                                            *|
673|* MC Register Information                                                    *|
674|*                                                                            *|
675|* Automatically generated file, do not edit!                                 *|
676|*                                                                            *|
677\*===----------------------------------------------------------------------===*/
678
679
680#ifdef GET_REGINFO_MC_DESC
681#undef GET_REGINFO_MC_DESC
682
683namespace llvm {
684
685extern const MCPhysReg PPCRegDiffLists[] = {
686  /* 0 */ 0, 0,
687  /* 2 */ 74, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
688  /* 19 */ 90, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
689  /* 36 */ 106, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
690  /* 53 */ 122, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
691  /* 70 */ 65378, 1, 1, 1, 1, 1, 1, 1, 0,
692  /* 79 */ 62326, 1, 1, 1, 0,
693  /* 84 */ 62386, 1, 1, 1, 0,
694  /* 89 */ 64605, 1, 1, 1, 0,
695  /* 94 */ 65497, 1, 1, 1, 0,
696  /* 99 */ 65501, 1, 1, 1, 0,
697  /* 104 */ 64707, 1, 0,
698  /* 107 */ 64867, 1, 0,
699  /* 110 */ 64997, 1, 0,
700  /* 113 */ 65408, 1, 0,
701  /* 116 */ 65472, 1, 0,
702  /* 119 */ 65234, 65472, 1, 64, 65473, 1, 0,
703  /* 126 */ 65474, 1, 0,
704  /* 129 */ 374, 65234, 65472, 1, 64, 65473, 1, 371, 65228, 65474, 1, 62, 65475, 1, 0,
705  /* 144 */ 65476, 1, 0,
706  /* 147 */ 65237, 65476, 1, 60, 65477, 1, 0,
707  /* 154 */ 65478, 1, 0,
708  /* 157 */ 65432, 374, 65234, 65472, 1, 64, 65473, 1, 371, 65228, 65474, 1, 62, 65475, 1, 65522, 374, 65237, 65476, 1, 60, 65477, 1, 364, 65231, 65478, 1, 58, 65479, 1, 0,
709  /* 188 */ 65480, 1, 0,
710  /* 191 */ 65240, 65480, 1, 56, 65481, 1, 0,
711  /* 198 */ 65482, 1, 0,
712  /* 201 */ 374, 65240, 65480, 1, 56, 65481, 1, 357, 65234, 65482, 1, 54, 65483, 1, 0,
713  /* 216 */ 65484, 1, 0,
714  /* 219 */ 65243, 65484, 1, 52, 65485, 1, 0,
715  /* 226 */ 65486, 1, 0,
716  /* 229 */ 65433, 374, 65240, 65480, 1, 56, 65481, 1, 357, 65234, 65482, 1, 54, 65483, 1, 65508, 374, 65243, 65484, 1, 52, 65485, 1, 350, 65237, 65486, 1, 50, 65487, 1, 0,
717  /* 260 */ 65488, 1, 0,
718  /* 263 */ 65246, 65488, 1, 48, 65489, 1, 0,
719  /* 270 */ 65490, 1, 0,
720  /* 273 */ 374, 65246, 65488, 1, 48, 65489, 1, 343, 65240, 65490, 1, 46, 65491, 1, 0,
721  /* 288 */ 65492, 1, 0,
722  /* 291 */ 65249, 65492, 1, 44, 65493, 1, 0,
723  /* 298 */ 65494, 1, 0,
724  /* 301 */ 65434, 374, 65246, 65488, 1, 48, 65489, 1, 343, 65240, 65490, 1, 46, 65491, 1, 65494, 374, 65249, 65492, 1, 44, 65493, 1, 336, 65243, 65494, 1, 42, 65495, 1, 0,
725  /* 332 */ 65496, 1, 0,
726  /* 335 */ 65252, 65496, 1, 40, 65497, 1, 0,
727  /* 342 */ 65498, 1, 0,
728  /* 345 */ 374, 65252, 65496, 1, 40, 65497, 1, 329, 65246, 65498, 1, 38, 65499, 1, 0,
729  /* 360 */ 65500, 1, 0,
730  /* 363 */ 65255, 65500, 1, 36, 65501, 1, 0,
731  /* 370 */ 65502, 1, 0,
732  /* 373 */ 65435, 374, 65252, 65496, 1, 40, 65497, 1, 329, 65246, 65498, 1, 38, 65499, 1, 65480, 374, 65255, 65500, 1, 36, 65501, 1, 322, 65249, 65502, 1, 34, 65503, 1, 0,
733  /* 404 */ 3, 0,
734  /* 406 */ 8, 0,
735  /* 408 */ 18, 0,
736  /* 410 */ 448, 65528, 65528, 24, 0,
737  /* 415 */ 65424, 32, 65505, 32, 0,
738  /* 420 */ 65425, 32, 65505, 32, 0,
739  /* 425 */ 65426, 32, 65505, 32, 0,
740  /* 430 */ 65427, 32, 65505, 32, 0,
741  /* 435 */ 65428, 32, 65505, 32, 0,
742  /* 440 */ 65429, 32, 65505, 32, 0,
743  /* 445 */ 65430, 32, 65505, 32, 0,
744  /* 450 */ 65431, 32, 65505, 32, 0,
745  /* 455 */ 65432, 32, 65505, 32, 0,
746  /* 460 */ 65433, 32, 65505, 32, 0,
747  /* 465 */ 65434, 32, 65505, 32, 0,
748  /* 470 */ 65435, 32, 65505, 32, 0,
749  /* 475 */ 65436, 32, 65505, 32, 0,
750  /* 480 */ 65437, 32, 65505, 32, 0,
751  /* 485 */ 65438, 32, 65505, 32, 0,
752  /* 490 */ 65439, 32, 65505, 32, 0,
753  /* 495 */ 37, 0,
754  /* 497 */ 32, 216, 49, 0,
755  /* 501 */ 32, 216, 50, 0,
756  /* 505 */ 32, 216, 51, 0,
757  /* 509 */ 32, 216, 52, 0,
758  /* 513 */ 32, 216, 53, 0,
759  /* 517 */ 32, 216, 54, 0,
760  /* 521 */ 32, 216, 55, 0,
761  /* 525 */ 32, 216, 56, 0,
762  /* 529 */ 32, 216, 57, 0,
763  /* 533 */ 32, 216, 58, 0,
764  /* 537 */ 32, 216, 59, 0,
765  /* 541 */ 32, 216, 60, 0,
766  /* 545 */ 32, 216, 61, 0,
767  /* 549 */ 32, 216, 62, 0,
768  /* 553 */ 32, 216, 63, 0,
769  /* 557 */ 32, 216, 64, 0,
770  /* 561 */ 32, 216, 65, 0,
771  /* 565 */ 73, 0,
772  /* 567 */ 65504, 96, 0,
773  /* 570 */ 65504, 97, 0,
774  /* 573 */ 65504, 98, 0,
775  /* 576 */ 65504, 99, 0,
776  /* 579 */ 32, 286, 65154, 100, 0,
777  /* 584 */ 33, 286, 65154, 100, 0,
778  /* 589 */ 33, 287, 65154, 100, 0,
779  /* 594 */ 34, 287, 65154, 100, 0,
780  /* 599 */ 34, 280, 65162, 100, 0,
781  /* 604 */ 35, 280, 65162, 100, 0,
782  /* 609 */ 35, 281, 65162, 100, 0,
783  /* 614 */ 36, 281, 65162, 100, 0,
784  /* 619 */ 65504, 100, 0,
785  /* 622 */ 36, 289, 65154, 101, 0,
786  /* 627 */ 37, 289, 65154, 101, 0,
787  /* 632 */ 37, 290, 65154, 101, 0,
788  /* 637 */ 38, 290, 65154, 101, 0,
789  /* 642 */ 40, 292, 65154, 101, 0,
790  /* 647 */ 41, 292, 65154, 101, 0,
791  /* 652 */ 41, 293, 65154, 101, 0,
792  /* 657 */ 42, 293, 65154, 101, 0,
793  /* 662 */ 38, 283, 65162, 101, 0,
794  /* 667 */ 39, 283, 65162, 101, 0,
795  /* 672 */ 39, 284, 65162, 101, 0,
796  /* 677 */ 40, 284, 65162, 101, 0,
797  /* 682 */ 42, 286, 65162, 101, 0,
798  /* 687 */ 43, 286, 65162, 101, 0,
799  /* 692 */ 43, 287, 65162, 101, 0,
800  /* 697 */ 44, 287, 65162, 101, 0,
801  /* 702 */ 65504, 101, 0,
802  /* 705 */ 44, 295, 65154, 102, 0,
803  /* 710 */ 45, 295, 65154, 102, 0,
804  /* 715 */ 45, 296, 65154, 102, 0,
805  /* 720 */ 46, 296, 65154, 102, 0,
806  /* 725 */ 48, 298, 65154, 102, 0,
807  /* 730 */ 49, 298, 65154, 102, 0,
808  /* 735 */ 49, 299, 65154, 102, 0,
809  /* 740 */ 50, 299, 65154, 102, 0,
810  /* 745 */ 46, 289, 65162, 102, 0,
811  /* 750 */ 47, 289, 65162, 102, 0,
812  /* 755 */ 47, 290, 65162, 102, 0,
813  /* 760 */ 48, 290, 65162, 102, 0,
814  /* 765 */ 50, 292, 65162, 102, 0,
815  /* 770 */ 51, 292, 65162, 102, 0,
816  /* 775 */ 51, 293, 65162, 102, 0,
817  /* 780 */ 52, 293, 65162, 102, 0,
818  /* 785 */ 65504, 102, 0,
819  /* 788 */ 52, 301, 65154, 103, 0,
820  /* 793 */ 53, 301, 65154, 103, 0,
821  /* 798 */ 53, 302, 65154, 103, 0,
822  /* 803 */ 54, 302, 65154, 103, 0,
823  /* 808 */ 56, 304, 65154, 103, 0,
824  /* 813 */ 57, 304, 65154, 103, 0,
825  /* 818 */ 57, 305, 65154, 103, 0,
826  /* 823 */ 58, 305, 65154, 103, 0,
827  /* 828 */ 54, 295, 65162, 103, 0,
828  /* 833 */ 55, 295, 65162, 103, 0,
829  /* 838 */ 55, 296, 65162, 103, 0,
830  /* 843 */ 56, 296, 65162, 103, 0,
831  /* 848 */ 58, 298, 65162, 103, 0,
832  /* 853 */ 59, 298, 65162, 103, 0,
833  /* 858 */ 59, 299, 65162, 103, 0,
834  /* 863 */ 60, 299, 65162, 103, 0,
835  /* 868 */ 65504, 103, 0,
836  /* 871 */ 60, 307, 65154, 104, 0,
837  /* 876 */ 61, 307, 65154, 104, 0,
838  /* 881 */ 61, 308, 65154, 104, 0,
839  /* 886 */ 62, 308, 65154, 104, 0,
840  /* 891 */ 62, 301, 65162, 104, 0,
841  /* 896 */ 63, 301, 65162, 104, 0,
842  /* 901 */ 63, 302, 65162, 104, 0,
843  /* 906 */ 64, 302, 65162, 104, 0,
844  /* 911 */ 65504, 104, 0,
845  /* 914 */ 65504, 105, 0,
846  /* 917 */ 65504, 106, 0,
847  /* 920 */ 65504, 107, 0,
848  /* 923 */ 65504, 108, 0,
849  /* 926 */ 65504, 109, 0,
850  /* 929 */ 65504, 110, 0,
851  /* 932 */ 65504, 111, 0,
852  /* 935 */ 65504, 112, 0,
853  /* 938 */ 165, 0,
854  /* 940 */ 170, 16, 65200, 224, 0,
855  /* 945 */ 170, 17, 65200, 224, 0,
856  /* 950 */ 170, 17, 65201, 224, 0,
857  /* 955 */ 170, 18, 65201, 224, 0,
858  /* 960 */ 170, 19, 65201, 224, 0,
859  /* 965 */ 170, 19, 65202, 224, 0,
860  /* 970 */ 170, 20, 65202, 224, 0,
861  /* 975 */ 170, 21, 65202, 224, 0,
862  /* 980 */ 170, 21, 65203, 224, 0,
863  /* 985 */ 170, 22, 65203, 224, 0,
864  /* 990 */ 170, 23, 65203, 224, 0,
865  /* 995 */ 170, 23, 65204, 224, 0,
866  /* 1000 */ 170, 24, 65204, 224, 0,
867  /* 1005 */ 170, 25, 65204, 224, 0,
868  /* 1010 */ 170, 25, 65205, 224, 0,
869  /* 1015 */ 170, 26, 65205, 224, 0,
870  /* 1020 */ 170, 27, 65205, 224, 0,
871  /* 1025 */ 170, 27, 65206, 224, 0,
872  /* 1030 */ 170, 28, 65206, 224, 0,
873  /* 1035 */ 170, 29, 65206, 224, 0,
874  /* 1040 */ 170, 29, 65207, 224, 0,
875  /* 1045 */ 170, 30, 65207, 224, 0,
876  /* 1050 */ 170, 31, 65207, 224, 0,
877  /* 1055 */ 170, 31, 65208, 224, 0,
878  /* 1060 */ 170, 32, 65208, 224, 0,
879  /* 1065 */ 441, 0,
880  /* 1067 */ 63676, 0,
881  /* 1069 */ 63705, 0,
882  /* 1071 */ 63738, 0,
883  /* 1073 */ 63771, 0,
884  /* 1075 */ 65080, 0,
885  /* 1077 */ 65088, 0,
886  /* 1079 */ 65095, 0,
887  /* 1081 */ 65096, 0,
888  /* 1083 */ 65104, 0,
889  /* 1085 */ 65238, 0,
890  /* 1087 */ 65256, 0,
891  /* 1089 */ 65471, 65288, 249, 65288, 0,
892  /* 1094 */ 65472, 65288, 249, 65288, 0,
893  /* 1099 */ 65473, 65288, 249, 65288, 0,
894  /* 1104 */ 65474, 65288, 249, 65288, 0,
895  /* 1109 */ 65475, 65288, 249, 65288, 0,
896  /* 1114 */ 65476, 65288, 249, 65288, 0,
897  /* 1119 */ 65477, 65288, 249, 65288, 0,
898  /* 1124 */ 65478, 65288, 249, 65288, 0,
899  /* 1129 */ 65479, 65288, 249, 65288, 0,
900  /* 1134 */ 65480, 65288, 249, 65288, 0,
901  /* 1139 */ 65481, 65288, 249, 65288, 0,
902  /* 1144 */ 65482, 65288, 249, 65288, 0,
903  /* 1149 */ 65483, 65288, 249, 65288, 0,
904  /* 1154 */ 65484, 65288, 249, 65288, 0,
905  /* 1159 */ 65485, 65288, 249, 65288, 0,
906  /* 1164 */ 65486, 65288, 249, 65288, 0,
907  /* 1169 */ 65504, 65366, 171, 65366, 0,
908  /* 1174 */ 104, 65504, 65366, 171, 65366, 202, 65505, 65366, 171, 65366, 0,
909  /* 1185 */ 328, 65504, 65366, 171, 65366, 202, 65505, 65366, 171, 65366, 0,
910  /* 1196 */ 65506, 65366, 171, 65366, 0,
911  /* 1201 */ 105, 65506, 65366, 171, 65366, 200, 65507, 65366, 171, 65366, 0,
912  /* 1212 */ 329, 65506, 65366, 171, 65366, 200, 65507, 65366, 171, 65366, 0,
913  /* 1223 */ 65508, 65366, 171, 65366, 0,
914  /* 1228 */ 106, 65508, 65366, 171, 65366, 198, 65509, 65366, 171, 65366, 0,
915  /* 1239 */ 330, 65508, 65366, 171, 65366, 198, 65509, 65366, 171, 65366, 0,
916  /* 1250 */ 65510, 65366, 171, 65366, 0,
917  /* 1255 */ 107, 65510, 65366, 171, 65366, 196, 65511, 65366, 171, 65366, 0,
918  /* 1266 */ 331, 65510, 65366, 171, 65366, 196, 65511, 65366, 171, 65366, 0,
919  /* 1277 */ 65512, 65366, 171, 65366, 0,
920  /* 1282 */ 108, 65512, 65366, 171, 65366, 194, 65513, 65366, 171, 65366, 0,
921  /* 1293 */ 332, 65512, 65366, 171, 65366, 194, 65513, 65366, 171, 65366, 0,
922  /* 1304 */ 65514, 65366, 171, 65366, 0,
923  /* 1309 */ 109, 65514, 65366, 171, 65366, 192, 65515, 65366, 171, 65366, 0,
924  /* 1320 */ 333, 65514, 65366, 171, 65366, 192, 65515, 65366, 171, 65366, 0,
925  /* 1331 */ 65516, 65366, 171, 65366, 0,
926  /* 1336 */ 110, 65516, 65366, 171, 65366, 190, 65517, 65366, 171, 65366, 0,
927  /* 1347 */ 334, 65516, 65366, 171, 65366, 190, 65517, 65366, 171, 65366, 0,
928  /* 1358 */ 65518, 65366, 171, 65366, 0,
929  /* 1363 */ 111, 65518, 65366, 171, 65366, 188, 65519, 65366, 171, 65366, 0,
930  /* 1374 */ 335, 65518, 65366, 171, 65366, 188, 65519, 65366, 171, 65366, 0,
931  /* 1385 */ 65368, 0,
932  /* 1387 */ 65371, 0,
933  /* 1389 */ 65408, 0,
934  /* 1391 */ 65432, 0,
935  /* 1393 */ 65464, 0,
936  /* 1395 */ 65472, 0,
937  /* 1397 */ 65474, 0,
938  /* 1399 */ 65504, 0,
939  /* 1401 */ 65518, 0,
940  /* 1403 */ 65535, 0,
941};
942
943extern const LaneBitmask PPCLaneMaskLists[] = {
944  /* 0 */ LaneBitmask(0x0000000000000000), LaneBitmask::getAll(),
945  /* 2 */ LaneBitmask(0x0000000000000001), LaneBitmask::getAll(),
946  /* 4 */ LaneBitmask(0x0000000000000002), LaneBitmask::getAll(),
947  /* 6 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask::getAll(),
948  /* 9 */ LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000080), LaneBitmask::getAll(),
949  /* 14 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000100), LaneBitmask::getAll(),
950  /* 17 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000100), LaneBitmask(0x0000000000000200), LaneBitmask(0x0000000000000400), LaneBitmask::getAll(),
951  /* 22 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000800), LaneBitmask(0x0000000000001000), LaneBitmask::getAll(),
952  /* 27 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000800), LaneBitmask(0x0000000000001000), LaneBitmask(0x0000000000002000), LaneBitmask(0x0000000000004000), LaneBitmask(0x0000000000008000), LaneBitmask(0x0000000000010000), LaneBitmask::getAll(),
953  /* 36 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000800), LaneBitmask(0x0000000000001000), LaneBitmask(0x0000000000002000), LaneBitmask(0x0000000000004000), LaneBitmask(0x0000000000008000), LaneBitmask(0x0000000000010000), LaneBitmask(0x0000000000020000), LaneBitmask(0x0000000000040000), LaneBitmask(0x0000000000080000), LaneBitmask(0x0000000000100000), LaneBitmask(0x0000000000200000), LaneBitmask(0x0000000000400000), LaneBitmask(0x0000000000800000), LaneBitmask(0x0000000001000000), LaneBitmask::getAll(),
954  /* 53 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000002000000), LaneBitmask::getAll(),
955};
956
957extern const uint16_t PPCSubRegIdxLists[] = {
958  /* 0 */ 1, 0,
959  /* 2 */ 2, 0,
960  /* 4 */ 5, 6, 0,
961  /* 7 */ 13, 12, 9, 16, 0,
962  /* 12 */ 17, 2, 18, 21, 0,
963  /* 17 */ 14, 17, 2, 18, 21, 15, 23, 22, 24, 25, 0,
964  /* 28 */ 7, 5, 6, 8, 26, 27, 0,
965  /* 35 */ 20, 7, 5, 6, 8, 26, 27, 19, 30, 28, 29, 31, 32, 33, 0,
966  /* 50 */ 3, 20, 7, 5, 6, 8, 26, 27, 19, 30, 28, 29, 31, 32, 33, 4, 39, 36, 34, 35, 37, 40, 41, 38, 44, 42, 43, 45, 46, 47, 0,
967  /* 81 */ 10, 1, 11, 48, 0,
968};
969
970extern const MCRegisterInfo::SubRegCoveredBits PPCSubRegIdxRanges[] = {
971  { 65535, 65535 },
972  { 0, 32 },	// sub_32
973  { 0, 64 },	// sub_64
974  { 0, 1024 },	// sub_dmr0
975  { 1024, 1024 },	// sub_dmr1
976  { 0, 128 },	// sub_dmrrow0
977  { 128, 128 },	// sub_dmrrow1
978  { 0, 256 },	// sub_dmrrowp0
979  { 256, 256 },	// sub_dmrrowp1
980  { 2, 1 },	// sub_eq
981  { 0, 64 },	// sub_gp8_x0
982  { 64, 64 },	// sub_gp8_x1
983  { 1, 1 },	// sub_gt
984  { 0, 1 },	// sub_lt
985  { 0, 256 },	// sub_pair0
986  { 256, 256 },	// sub_pair1
987  { 3, 1 },	// sub_un
988  { 0, 128 },	// sub_vsx0
989  { 128, 128 },	// sub_vsx1
990  { 512, 512 },	// sub_wacc_hi
991  { 0, 512 },	// sub_wacc_lo
992  { 128, 64 },	// sub_vsx1_then_sub_64
993  { 256, 64 },	// sub_pair1_then_sub_64
994  { 256, 128 },	// sub_pair1_then_sub_vsx0
995  { 384, 128 },	// sub_pair1_then_sub_vsx1
996  { 384, 64 },	// sub_pair1_then_sub_vsx1_then_sub_64
997  { 256, 128 },	// sub_dmrrowp1_then_sub_dmrrow0
998  { 384, 128 },	// sub_dmrrowp1_then_sub_dmrrow1
999  { 512, 128 },	// sub_wacc_hi_then_sub_dmrrow0
1000  { 640, 128 },	// sub_wacc_hi_then_sub_dmrrow1
1001  { 512, 256 },	// sub_wacc_hi_then_sub_dmrrowp0
1002  { 768, 256 },	// sub_wacc_hi_then_sub_dmrrowp1
1003  { 768, 128 },	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
1004  { 896, 128 },	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
1005  { 1024, 128 },	// sub_dmr1_then_sub_dmrrow0
1006  { 1152, 128 },	// sub_dmr1_then_sub_dmrrow1
1007  { 1024, 256 },	// sub_dmr1_then_sub_dmrrowp0
1008  { 1280, 256 },	// sub_dmr1_then_sub_dmrrowp1
1009  { 1536, 512 },	// sub_dmr1_then_sub_wacc_hi
1010  { 1024, 512 },	// sub_dmr1_then_sub_wacc_lo
1011  { 1280, 128 },	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
1012  { 1408, 128 },	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
1013  { 1536, 128 },	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
1014  { 1664, 128 },	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
1015  { 1536, 256 },	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
1016  { 1792, 256 },	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
1017  { 1792, 128 },	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
1018  { 1920, 128 },	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
1019  { 64, 32 },	// sub_gp8_x1_then_sub_32
1020};
1021
1022
1023#ifdef __GNUC__
1024#pragma GCC diagnostic push
1025#pragma GCC diagnostic ignored "-Woverlength-strings"
1026#endif
1027extern const char PPCRegStrings[] = {
1028  /* 0 */ "VF10\0"
1029  /* 5 */ "VSL10\0"
1030  /* 11 */ "R10\0"
1031  /* 15 */ "S10\0"
1032  /* 19 */ "V10\0"
1033  /* 23 */ "DMRROW10\0"
1034  /* 32 */ "X10\0"
1035  /* 36 */ "G8p10\0"
1036  /* 42 */ "VSRp10\0"
1037  /* 49 */ "DMRROWp10\0"
1038  /* 59 */ "VF20\0"
1039  /* 64 */ "VSL20\0"
1040  /* 70 */ "R20\0"
1041  /* 74 */ "S20\0"
1042  /* 78 */ "V20\0"
1043  /* 82 */ "DMRROW20\0"
1044  /* 91 */ "X20\0"
1045  /* 95 */ "VSRp20\0"
1046  /* 102 */ "DMRROWp20\0"
1047  /* 112 */ "VF30\0"
1048  /* 117 */ "VSL30\0"
1049  /* 123 */ "R30\0"
1050  /* 127 */ "S30\0"
1051  /* 131 */ "V30\0"
1052  /* 135 */ "DMRROW30\0"
1053  /* 144 */ "X30\0"
1054  /* 148 */ "VSRp30\0"
1055  /* 155 */ "DMRROWp30\0"
1056  /* 165 */ "DMRROW40\0"
1057  /* 174 */ "VSX40\0"
1058  /* 180 */ "DMRROW50\0"
1059  /* 189 */ "VSX50\0"
1060  /* 195 */ "DMRROW60\0"
1061  /* 204 */ "VSX60\0"
1062  /* 210 */ "UACC0\0"
1063  /* 216 */ "WACC0\0"
1064  /* 222 */ "VF0\0"
1065  /* 226 */ "WACC_HI0\0"
1066  /* 235 */ "VSL0\0"
1067  /* 240 */ "CR0\0"
1068  /* 244 */ "DMR0\0"
1069  /* 249 */ "S0\0"
1070  /* 252 */ "V0\0"
1071  /* 255 */ "DMRROW0\0"
1072  /* 263 */ "X0\0"
1073  /* 266 */ "G8p0\0"
1074  /* 271 */ "DMRp0\0"
1075  /* 277 */ "VSRp0\0"
1076  /* 283 */ "DMRROWp0\0"
1077  /* 292 */ "VF11\0"
1078  /* 297 */ "VSL11\0"
1079  /* 303 */ "R11\0"
1080  /* 307 */ "S11\0"
1081  /* 311 */ "V11\0"
1082  /* 315 */ "DMRROW11\0"
1083  /* 324 */ "X11\0"
1084  /* 328 */ "G8p11\0"
1085  /* 334 */ "VSRp11\0"
1086  /* 341 */ "DMRROWp11\0"
1087  /* 351 */ "VF21\0"
1088  /* 356 */ "VSL21\0"
1089  /* 362 */ "R21\0"
1090  /* 366 */ "S21\0"
1091  /* 370 */ "V21\0"
1092  /* 374 */ "DMRROW21\0"
1093  /* 383 */ "X21\0"
1094  /* 387 */ "VSRp21\0"
1095  /* 394 */ "DMRROWp21\0"
1096  /* 404 */ "VF31\0"
1097  /* 409 */ "VSL31\0"
1098  /* 415 */ "R31\0"
1099  /* 419 */ "S31\0"
1100  /* 423 */ "V31\0"
1101  /* 427 */ "DMRROW31\0"
1102  /* 436 */ "X31\0"
1103  /* 440 */ "VSRp31\0"
1104  /* 447 */ "DMRROWp31\0"
1105  /* 457 */ "DMRROW41\0"
1106  /* 466 */ "VSX41\0"
1107  /* 472 */ "DMRROW51\0"
1108  /* 481 */ "VSX51\0"
1109  /* 487 */ "DMRROW61\0"
1110  /* 496 */ "VSX61\0"
1111  /* 502 */ "UACC1\0"
1112  /* 508 */ "WACC1\0"
1113  /* 514 */ "VF1\0"
1114  /* 518 */ "WACC_HI1\0"
1115  /* 527 */ "VSL1\0"
1116  /* 532 */ "CR1\0"
1117  /* 536 */ "DMR1\0"
1118  /* 541 */ "S1\0"
1119  /* 544 */ "V1\0"
1120  /* 547 */ "DMRROW1\0"
1121  /* 555 */ "X1\0"
1122  /* 558 */ "G8p1\0"
1123  /* 563 */ "DMRp1\0"
1124  /* 569 */ "VSRp1\0"
1125  /* 575 */ "DMRROWp1\0"
1126  /* 584 */ "VF12\0"
1127  /* 589 */ "VSL12\0"
1128  /* 595 */ "R12\0"
1129  /* 599 */ "S12\0"
1130  /* 603 */ "V12\0"
1131  /* 607 */ "DMRROW12\0"
1132  /* 616 */ "X12\0"
1133  /* 620 */ "G8p12\0"
1134  /* 626 */ "VSRp12\0"
1135  /* 633 */ "DMRROWp12\0"
1136  /* 643 */ "VF22\0"
1137  /* 648 */ "VSL22\0"
1138  /* 654 */ "R22\0"
1139  /* 658 */ "S22\0"
1140  /* 662 */ "V22\0"
1141  /* 666 */ "DMRROW22\0"
1142  /* 675 */ "X22\0"
1143  /* 679 */ "VSRp22\0"
1144  /* 686 */ "DMRROWp22\0"
1145  /* 696 */ "DMRROW32\0"
1146  /* 705 */ "VSX32\0"
1147  /* 711 */ "DMRROW42\0"
1148  /* 720 */ "VSX42\0"
1149  /* 726 */ "DMRROW52\0"
1150  /* 735 */ "VSX52\0"
1151  /* 741 */ "DMRROW62\0"
1152  /* 750 */ "VSX62\0"
1153  /* 756 */ "UACC2\0"
1154  /* 762 */ "WACC2\0"
1155  /* 768 */ "VF2\0"
1156  /* 772 */ "WACC_HI2\0"
1157  /* 781 */ "VSL2\0"
1158  /* 786 */ "CR2\0"
1159  /* 790 */ "DMR2\0"
1160  /* 795 */ "S2\0"
1161  /* 798 */ "V2\0"
1162  /* 801 */ "DMRROW2\0"
1163  /* 809 */ "X2\0"
1164  /* 812 */ "G8p2\0"
1165  /* 817 */ "DMRp2\0"
1166  /* 823 */ "VSRp2\0"
1167  /* 829 */ "DMRROWp2\0"
1168  /* 838 */ "VF13\0"
1169  /* 843 */ "VSL13\0"
1170  /* 849 */ "R13\0"
1171  /* 853 */ "S13\0"
1172  /* 857 */ "V13\0"
1173  /* 861 */ "DMRROW13\0"
1174  /* 870 */ "X13\0"
1175  /* 874 */ "G8p13\0"
1176  /* 880 */ "VSRp13\0"
1177  /* 887 */ "DMRROWp13\0"
1178  /* 897 */ "VF23\0"
1179  /* 902 */ "VSL23\0"
1180  /* 908 */ "R23\0"
1181  /* 912 */ "S23\0"
1182  /* 916 */ "V23\0"
1183  /* 920 */ "DMRROW23\0"
1184  /* 929 */ "X23\0"
1185  /* 933 */ "VSRp23\0"
1186  /* 940 */ "DMRROWp23\0"
1187  /* 950 */ "DMRROW33\0"
1188  /* 959 */ "VSX33\0"
1189  /* 965 */ "DMRROW43\0"
1190  /* 974 */ "VSX43\0"
1191  /* 980 */ "DMRROW53\0"
1192  /* 989 */ "VSX53\0"
1193  /* 995 */ "DMRROW63\0"
1194  /* 1004 */ "VSX63\0"
1195  /* 1010 */ "UACC3\0"
1196  /* 1016 */ "WACC3\0"
1197  /* 1022 */ "VF3\0"
1198  /* 1026 */ "WACC_HI3\0"
1199  /* 1035 */ "VSL3\0"
1200  /* 1040 */ "CR3\0"
1201  /* 1044 */ "DMR3\0"
1202  /* 1049 */ "S3\0"
1203  /* 1052 */ "V3\0"
1204  /* 1055 */ "DMRROW3\0"
1205  /* 1063 */ "X3\0"
1206  /* 1066 */ "G8p3\0"
1207  /* 1071 */ "DMRp3\0"
1208  /* 1077 */ "VSRp3\0"
1209  /* 1083 */ "DMRROWp3\0"
1210  /* 1092 */ "VF14\0"
1211  /* 1097 */ "VSL14\0"
1212  /* 1103 */ "R14\0"
1213  /* 1107 */ "S14\0"
1214  /* 1111 */ "V14\0"
1215  /* 1115 */ "DMRROW14\0"
1216  /* 1124 */ "X14\0"
1217  /* 1128 */ "G8p14\0"
1218  /* 1134 */ "VSRp14\0"
1219  /* 1141 */ "DMRROWp14\0"
1220  /* 1151 */ "VF24\0"
1221  /* 1156 */ "VSL24\0"
1222  /* 1162 */ "R24\0"
1223  /* 1166 */ "S24\0"
1224  /* 1170 */ "V24\0"
1225  /* 1174 */ "DMRROW24\0"
1226  /* 1183 */ "X24\0"
1227  /* 1187 */ "VSRp24\0"
1228  /* 1194 */ "DMRROWp24\0"
1229  /* 1204 */ "DMRROW34\0"
1230  /* 1213 */ "VSX34\0"
1231  /* 1219 */ "DMRROW44\0"
1232  /* 1228 */ "VSX44\0"
1233  /* 1234 */ "DMRROW54\0"
1234  /* 1243 */ "VSX54\0"
1235  /* 1249 */ "UACC4\0"
1236  /* 1255 */ "WACC4\0"
1237  /* 1261 */ "VF4\0"
1238  /* 1265 */ "WACC_HI4\0"
1239  /* 1274 */ "VSL4\0"
1240  /* 1279 */ "CR4\0"
1241  /* 1283 */ "DMR4\0"
1242  /* 1288 */ "S4\0"
1243  /* 1291 */ "V4\0"
1244  /* 1294 */ "DMRROW4\0"
1245  /* 1302 */ "X4\0"
1246  /* 1305 */ "G8p4\0"
1247  /* 1310 */ "VSRp4\0"
1248  /* 1316 */ "DMRROWp4\0"
1249  /* 1325 */ "VF15\0"
1250  /* 1330 */ "VSL15\0"
1251  /* 1336 */ "R15\0"
1252  /* 1340 */ "S15\0"
1253  /* 1344 */ "V15\0"
1254  /* 1348 */ "DMRROW15\0"
1255  /* 1357 */ "X15\0"
1256  /* 1361 */ "G8p15\0"
1257  /* 1367 */ "VSRp15\0"
1258  /* 1374 */ "DMRROWp15\0"
1259  /* 1384 */ "VF25\0"
1260  /* 1389 */ "VSL25\0"
1261  /* 1395 */ "R25\0"
1262  /* 1399 */ "S25\0"
1263  /* 1403 */ "V25\0"
1264  /* 1407 */ "DMRROW25\0"
1265  /* 1416 */ "X25\0"
1266  /* 1420 */ "VSRp25\0"
1267  /* 1427 */ "DMRROWp25\0"
1268  /* 1437 */ "DMRROW35\0"
1269  /* 1446 */ "VSX35\0"
1270  /* 1452 */ "DMRROW45\0"
1271  /* 1461 */ "VSX45\0"
1272  /* 1467 */ "DMRROW55\0"
1273  /* 1476 */ "VSX55\0"
1274  /* 1482 */ "UACC5\0"
1275  /* 1488 */ "WACC5\0"
1276  /* 1494 */ "VF5\0"
1277  /* 1498 */ "WACC_HI5\0"
1278  /* 1507 */ "VSL5\0"
1279  /* 1512 */ "CR5\0"
1280  /* 1516 */ "DMR5\0"
1281  /* 1521 */ "S5\0"
1282  /* 1524 */ "V5\0"
1283  /* 1527 */ "DMRROW5\0"
1284  /* 1535 */ "X5\0"
1285  /* 1538 */ "G8p5\0"
1286  /* 1543 */ "VSRp5\0"
1287  /* 1549 */ "DMRROWp5\0"
1288  /* 1558 */ "VF16\0"
1289  /* 1563 */ "VSL16\0"
1290  /* 1569 */ "R16\0"
1291  /* 1573 */ "S16\0"
1292  /* 1577 */ "V16\0"
1293  /* 1581 */ "DMRROW16\0"
1294  /* 1590 */ "X16\0"
1295  /* 1594 */ "VSRp16\0"
1296  /* 1601 */ "DMRROWp16\0"
1297  /* 1611 */ "VF26\0"
1298  /* 1616 */ "VSL26\0"
1299  /* 1622 */ "R26\0"
1300  /* 1626 */ "S26\0"
1301  /* 1630 */ "V26\0"
1302  /* 1634 */ "DMRROW26\0"
1303  /* 1643 */ "X26\0"
1304  /* 1647 */ "VSRp26\0"
1305  /* 1654 */ "DMRROWp26\0"
1306  /* 1664 */ "DMRROW36\0"
1307  /* 1673 */ "VSX36\0"
1308  /* 1679 */ "DMRROW46\0"
1309  /* 1688 */ "VSX46\0"
1310  /* 1694 */ "DMRROW56\0"
1311  /* 1703 */ "VSX56\0"
1312  /* 1709 */ "UACC6\0"
1313  /* 1715 */ "WACC6\0"
1314  /* 1721 */ "VF6\0"
1315  /* 1725 */ "WACC_HI6\0"
1316  /* 1734 */ "VSL6\0"
1317  /* 1739 */ "CR6\0"
1318  /* 1743 */ "DMR6\0"
1319  /* 1748 */ "S6\0"
1320  /* 1751 */ "V6\0"
1321  /* 1754 */ "DMRROW6\0"
1322  /* 1762 */ "X6\0"
1323  /* 1765 */ "G8p6\0"
1324  /* 1770 */ "VSRp6\0"
1325  /* 1776 */ "DMRROWp6\0"
1326  /* 1785 */ "VF17\0"
1327  /* 1790 */ "VSL17\0"
1328  /* 1796 */ "R17\0"
1329  /* 1800 */ "S17\0"
1330  /* 1804 */ "V17\0"
1331  /* 1808 */ "DMRROW17\0"
1332  /* 1817 */ "X17\0"
1333  /* 1821 */ "VSRp17\0"
1334  /* 1828 */ "DMRROWp17\0"
1335  /* 1838 */ "VF27\0"
1336  /* 1843 */ "VSL27\0"
1337  /* 1849 */ "R27\0"
1338  /* 1853 */ "S27\0"
1339  /* 1857 */ "V27\0"
1340  /* 1861 */ "DMRROW27\0"
1341  /* 1870 */ "X27\0"
1342  /* 1874 */ "VSRp27\0"
1343  /* 1881 */ "DMRROWp27\0"
1344  /* 1891 */ "DMRROW37\0"
1345  /* 1900 */ "VSX37\0"
1346  /* 1906 */ "DMRROW47\0"
1347  /* 1915 */ "VSX47\0"
1348  /* 1921 */ "DMRROW57\0"
1349  /* 1930 */ "VSX57\0"
1350  /* 1936 */ "UACC7\0"
1351  /* 1942 */ "WACC7\0"
1352  /* 1948 */ "VF7\0"
1353  /* 1952 */ "WACC_HI7\0"
1354  /* 1961 */ "VSL7\0"
1355  /* 1966 */ "CR7\0"
1356  /* 1970 */ "DMR7\0"
1357  /* 1975 */ "S7\0"
1358  /* 1978 */ "V7\0"
1359  /* 1981 */ "DMRROW7\0"
1360  /* 1989 */ "X7\0"
1361  /* 1992 */ "G8p7\0"
1362  /* 1997 */ "VSRp7\0"
1363  /* 2003 */ "DMRROWp7\0"
1364  /* 2012 */ "VF18\0"
1365  /* 2017 */ "VSL18\0"
1366  /* 2023 */ "R18\0"
1367  /* 2027 */ "S18\0"
1368  /* 2031 */ "V18\0"
1369  /* 2035 */ "DMRROW18\0"
1370  /* 2044 */ "X18\0"
1371  /* 2048 */ "VSRp18\0"
1372  /* 2055 */ "DMRROWp18\0"
1373  /* 2065 */ "VF28\0"
1374  /* 2070 */ "VSL28\0"
1375  /* 2076 */ "R28\0"
1376  /* 2080 */ "S28\0"
1377  /* 2084 */ "V28\0"
1378  /* 2088 */ "DMRROW28\0"
1379  /* 2097 */ "X28\0"
1380  /* 2101 */ "VSRp28\0"
1381  /* 2108 */ "DMRROWp28\0"
1382  /* 2118 */ "DMRROW38\0"
1383  /* 2127 */ "VSX38\0"
1384  /* 2133 */ "DMRROW48\0"
1385  /* 2142 */ "VSX48\0"
1386  /* 2148 */ "DMRROW58\0"
1387  /* 2157 */ "VSX58\0"
1388  /* 2163 */ "VF8\0"
1389  /* 2167 */ "VSL8\0"
1390  /* 2172 */ "ZERO8\0"
1391  /* 2178 */ "BP8\0"
1392  /* 2182 */ "FP8\0"
1393  /* 2186 */ "LR8\0"
1394  /* 2190 */ "CTR8\0"
1395  /* 2195 */ "S8\0"
1396  /* 2198 */ "V8\0"
1397  /* 2201 */ "DMRROW8\0"
1398  /* 2209 */ "X8\0"
1399  /* 2212 */ "G8p8\0"
1400  /* 2217 */ "VSRp8\0"
1401  /* 2223 */ "DMRROWp8\0"
1402  /* 2232 */ "VF19\0"
1403  /* 2237 */ "VSL19\0"
1404  /* 2243 */ "R19\0"
1405  /* 2247 */ "S19\0"
1406  /* 2251 */ "V19\0"
1407  /* 2255 */ "DMRROW19\0"
1408  /* 2264 */ "X19\0"
1409  /* 2268 */ "VSRp19\0"
1410  /* 2275 */ "DMRROWp19\0"
1411  /* 2285 */ "VF29\0"
1412  /* 2290 */ "VSL29\0"
1413  /* 2296 */ "R29\0"
1414  /* 2300 */ "S29\0"
1415  /* 2304 */ "V29\0"
1416  /* 2308 */ "DMRROW29\0"
1417  /* 2317 */ "X29\0"
1418  /* 2321 */ "VSRp29\0"
1419  /* 2328 */ "DMRROWp29\0"
1420  /* 2338 */ "DMRROW39\0"
1421  /* 2347 */ "VSX39\0"
1422  /* 2353 */ "DMRROW49\0"
1423  /* 2362 */ "VSX49\0"
1424  /* 2368 */ "DMRROW59\0"
1425  /* 2377 */ "VSX59\0"
1426  /* 2383 */ "VF9\0"
1427  /* 2387 */ "VSL9\0"
1428  /* 2392 */ "R9\0"
1429  /* 2395 */ "S9\0"
1430  /* 2398 */ "V9\0"
1431  /* 2401 */ "DMRROW9\0"
1432  /* 2409 */ "X9\0"
1433  /* 2412 */ "G8p9\0"
1434  /* 2417 */ "VSRp9\0"
1435  /* 2423 */ "DMRROWp9\0"
1436  /* 2432 */ "VRSAVE\0"
1437  /* 2439 */ "RM\0"
1438  /* 2442 */ "CR0UN\0"
1439  /* 2448 */ "CR1UN\0"
1440  /* 2454 */ "CR2UN\0"
1441  /* 2460 */ "CR3UN\0"
1442  /* 2466 */ "CR4UN\0"
1443  /* 2472 */ "CR5UN\0"
1444  /* 2478 */ "CR6UN\0"
1445  /* 2484 */ "CR7UN\0"
1446  /* 2490 */ "ZERO\0"
1447  /* 2495 */ "BP\0"
1448  /* 2498 */ "FP\0"
1449  /* 2501 */ "CR0EQ\0"
1450  /* 2507 */ "CR1EQ\0"
1451  /* 2513 */ "CR2EQ\0"
1452  /* 2519 */ "CR3EQ\0"
1453  /* 2525 */ "CR4EQ\0"
1454  /* 2531 */ "CR5EQ\0"
1455  /* 2537 */ "CR6EQ\0"
1456  /* 2543 */ "CR7EQ\0"
1457  /* 2549 */ "SPEFSCR\0"
1458  /* 2557 */ "XER\0"
1459  /* 2561 */ "LR\0"
1460  /* 2564 */ "CTR\0"
1461  /* 2568 */ "CR0GT\0"
1462  /* 2574 */ "CR1GT\0"
1463  /* 2580 */ "CR2GT\0"
1464  /* 2586 */ "CR3GT\0"
1465  /* 2592 */ "CR4GT\0"
1466  /* 2598 */ "CR5GT\0"
1467  /* 2604 */ "CR6GT\0"
1468  /* 2610 */ "CR7GT\0"
1469  /* 2616 */ "CR0LT\0"
1470  /* 2622 */ "CR1LT\0"
1471  /* 2628 */ "CR2LT\0"
1472  /* 2634 */ "CR3LT\0"
1473  /* 2640 */ "CR4LT\0"
1474  /* 2646 */ "CR5LT\0"
1475  /* 2652 */ "CR6LT\0"
1476  /* 2658 */ "CR7LT\0"
1477  /* 2664 */ "CARRY\0"
1478};
1479#ifdef __GNUC__
1480#pragma GCC diagnostic pop
1481#endif
1482
1483extern const MCRegisterDesc PPCRegDesc[] = { // Descriptors
1484  { 4, 0, 0, 0, 0, 0 },
1485  { 2495, 1, 408, 1, 22449, 0 },
1486  { 2664, 1, 1, 1, 22449, 0 },
1487  { 2564, 1, 1, 1, 22449, 0 },
1488  { 2498, 1, 938, 1, 22449, 0 },
1489  { 2561, 1, 1, 1, 22449, 0 },
1490  { 2439, 1, 1, 1, 22449, 0 },
1491  { 2549, 1, 1, 1, 22449, 0 },
1492  { 2432, 1, 1, 1, 22449, 0 },
1493  { 2557, 1, 1, 1, 22359, 0 },
1494  { 2490, 1, 1065, 1, 22359, 0 },
1495  { 211, 1185, 1, 17, 1588, 17 },
1496  { 503, 1212, 1, 17, 1588, 17 },
1497  { 757, 1239, 1, 17, 1588, 17 },
1498  { 1011, 1266, 1, 17, 1588, 17 },
1499  { 1250, 1293, 1, 17, 1588, 17 },
1500  { 1483, 1320, 1, 17, 1588, 17 },
1501  { 1710, 1347, 1, 17, 1588, 17 },
1502  { 1937, 1374, 1, 17, 1588, 17 },
1503  { 2178, 1401, 1, 0, 0, 2 },
1504  { 240, 410, 1, 7, 1508, 9 },
1505  { 532, 410, 1, 7, 1508, 9 },
1506  { 786, 410, 1, 7, 1508, 9 },
1507  { 1040, 410, 1, 7, 1508, 9 },
1508  { 1279, 410, 1, 7, 1508, 9 },
1509  { 1512, 410, 1, 7, 1508, 9 },
1510  { 1739, 410, 1, 7, 1508, 9 },
1511  { 1966, 410, 1, 7, 1508, 9 },
1512  { 2190, 1, 1, 1, 9040, 0 },
1513  { 244, 129, 874, 35, 1128, 27 },
1514  { 536, 173, 791, 35, 1128, 27 },
1515  { 790, 201, 791, 35, 1128, 27 },
1516  { 1044, 245, 708, 35, 1128, 27 },
1517  { 1283, 273, 708, 35, 1128, 27 },
1518  { 1516, 317, 625, 35, 1128, 27 },
1519  { 1743, 345, 625, 35, 1128, 27 },
1520  { 1970, 389, 582, 35, 1128, 27 },
1521  { 255, 1, 906, 1, 7921, 0 },
1522  { 547, 1, 901, 1, 7921, 0 },
1523  { 801, 1, 896, 1, 7921, 0 },
1524  { 1055, 1, 891, 1, 7921, 0 },
1525  { 1294, 1, 886, 1, 7921, 0 },
1526  { 1527, 1, 881, 1, 7921, 0 },
1527  { 1754, 1, 876, 1, 7921, 0 },
1528  { 1981, 1, 871, 1, 7921, 0 },
1529  { 2201, 1, 863, 1, 7921, 0 },
1530  { 2401, 1, 858, 1, 7921, 0 },
1531  { 23, 1, 853, 1, 7921, 0 },
1532  { 315, 1, 848, 1, 7921, 0 },
1533  { 607, 1, 823, 1, 7921, 0 },
1534  { 861, 1, 818, 1, 7921, 0 },
1535  { 1115, 1, 813, 1, 7921, 0 },
1536  { 1348, 1, 808, 1, 7921, 0 },
1537  { 1581, 1, 843, 1, 7921, 0 },
1538  { 1808, 1, 838, 1, 7921, 0 },
1539  { 2035, 1, 833, 1, 7921, 0 },
1540  { 2255, 1, 828, 1, 7921, 0 },
1541  { 82, 1, 803, 1, 7921, 0 },
1542  { 374, 1, 798, 1, 7921, 0 },
1543  { 666, 1, 793, 1, 7921, 0 },
1544  { 920, 1, 788, 1, 7921, 0 },
1545  { 1174, 1, 780, 1, 7921, 0 },
1546  { 1407, 1, 775, 1, 7921, 0 },
1547  { 1634, 1, 770, 1, 7921, 0 },
1548  { 1861, 1, 765, 1, 7921, 0 },
1549  { 2088, 1, 740, 1, 7921, 0 },
1550  { 2308, 1, 735, 1, 7921, 0 },
1551  { 135, 1, 730, 1, 7921, 0 },
1552  { 427, 1, 725, 1, 7921, 0 },
1553  { 696, 1, 760, 1, 7921, 0 },
1554  { 950, 1, 755, 1, 7921, 0 },
1555  { 1204, 1, 750, 1, 7921, 0 },
1556  { 1437, 1, 745, 1, 7921, 0 },
1557  { 1664, 1, 720, 1, 7921, 0 },
1558  { 1891, 1, 715, 1, 7921, 0 },
1559  { 2118, 1, 710, 1, 7921, 0 },
1560  { 2338, 1, 705, 1, 7921, 0 },
1561  { 165, 1, 697, 1, 7921, 0 },
1562  { 457, 1, 692, 1, 7921, 0 },
1563  { 711, 1, 687, 1, 7921, 0 },
1564  { 965, 1, 682, 1, 7921, 0 },
1565  { 1219, 1, 657, 1, 7921, 0 },
1566  { 1452, 1, 652, 1, 7921, 0 },
1567  { 1679, 1, 647, 1, 7921, 0 },
1568  { 1906, 1, 642, 1, 7921, 0 },
1569  { 2133, 1, 677, 1, 7921, 0 },
1570  { 2353, 1, 672, 1, 7921, 0 },
1571  { 180, 1, 667, 1, 7921, 0 },
1572  { 472, 1, 662, 1, 7921, 0 },
1573  { 726, 1, 637, 1, 7921, 0 },
1574  { 980, 1, 632, 1, 7921, 0 },
1575  { 1234, 1, 627, 1, 7921, 0 },
1576  { 1467, 1, 622, 1, 7921, 0 },
1577  { 1694, 1, 614, 1, 7921, 0 },
1578  { 1921, 1, 609, 1, 7921, 0 },
1579  { 2148, 1, 604, 1, 7921, 0 },
1580  { 2368, 1, 599, 1, 7921, 0 },
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1616  { 447, 401, 580, 4, 1810, 6 },
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1618  { 563, 229, 1, 50, 304, 36 },
1619  { 817, 301, 1, 50, 576, 36 },
1620  { 1071, 373, 1, 50, 848, 36 },
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1622  { 515, 1, 1055, 1, 22225, 0 },
1623  { 769, 1, 1050, 1, 22225, 0 },
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1630  { 2384, 1, 1025, 1, 22225, 0 },
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1634  { 839, 1, 1010, 1, 22225, 0 },
1635  { 1093, 1, 1005, 1, 22225, 0 },
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1650  { 2286, 1, 950, 1, 22225, 0 },
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1652  { 405, 1, 940, 1, 22225, 0 },
1653  { 2182, 1387, 1, 0, 6464, 2 },
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1656  { 533, 1, 557, 1, 22385, 0 },
1657  { 787, 1, 557, 1, 22385, 0 },
1658  { 1041, 1, 553, 1, 22385, 0 },
1659  { 1280, 1, 553, 1, 22385, 0 },
1660  { 1513, 1, 549, 1, 22385, 0 },
1661  { 1740, 1, 549, 1, 22385, 0 },
1662  { 1967, 1, 545, 1, 22385, 0 },
1663  { 2187, 1, 545, 1, 22385, 0 },
1664  { 2392, 1, 541, 1, 22385, 0 },
1665  { 11, 1, 541, 1, 22385, 0 },
1666  { 303, 1, 537, 1, 22385, 0 },
1667  { 595, 1, 537, 1, 22385, 0 },
1668  { 849, 1, 533, 1, 22385, 0 },
1669  { 1103, 1, 533, 1, 22385, 0 },
1670  { 1336, 1, 529, 1, 22385, 0 },
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1673  { 2023, 1, 525, 1, 22385, 0 },
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1677  { 654, 1, 517, 1, 22385, 0 },
1678  { 908, 1, 513, 1, 22385, 0 },
1679  { 1162, 1, 513, 1, 22385, 0 },
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1681  { 1622, 1, 509, 1, 22385, 0 },
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1688  { 541, 1399, 1, 0, 22321, 2 },
1689  { 795, 1399, 1, 0, 22321, 2 },
1690  { 1049, 1399, 1, 0, 22321, 2 },
1691  { 1288, 1399, 1, 0, 22321, 2 },
1692  { 1521, 1399, 1, 0, 22321, 2 },
1693  { 1748, 1399, 1, 0, 22321, 2 },
1694  { 1975, 1399, 1, 0, 22321, 2 },
1695  { 2195, 1399, 1, 0, 22321, 2 },
1696  { 2395, 1399, 1, 0, 22321, 2 },
1697  { 15, 1399, 1, 0, 22321, 2 },
1698  { 307, 1399, 1, 0, 22321, 2 },
1699  { 599, 1399, 1, 0, 22321, 2 },
1700  { 853, 1399, 1, 0, 22321, 2 },
1701  { 1107, 1399, 1, 0, 22321, 2 },
1702  { 1340, 1399, 1, 0, 22321, 2 },
1703  { 1573, 1399, 1, 0, 22321, 2 },
1704  { 1800, 1399, 1, 0, 22321, 2 },
1705  { 2027, 1399, 1, 0, 22321, 2 },
1706  { 2247, 1399, 1, 0, 22321, 2 },
1707  { 74, 1399, 1, 0, 22321, 2 },
1708  { 366, 1399, 1, 0, 22321, 2 },
1709  { 658, 1399, 1, 0, 22321, 2 },
1710  { 912, 1399, 1, 0, 22321, 2 },
1711  { 1166, 1399, 1, 0, 22321, 2 },
1712  { 1399, 1399, 1, 0, 22321, 2 },
1713  { 1626, 1399, 1, 0, 22321, 2 },
1714  { 1853, 1399, 1, 0, 22321, 2 },
1715  { 2080, 1399, 1, 0, 22321, 2 },
1716  { 2300, 1399, 1, 0, 22321, 2 },
1717  { 127, 1399, 1, 0, 22321, 2 },
1718  { 419, 1399, 1, 0, 22321, 2 },
1719  { 210, 1174, 1, 17, 1428, 17 },
1720  { 502, 1201, 1, 17, 1428, 17 },
1721  { 756, 1228, 1, 17, 1428, 17 },
1722  { 1010, 1255, 1, 17, 1428, 17 },
1723  { 1249, 1282, 1, 17, 1428, 17 },
1724  { 1482, 1309, 1, 17, 1428, 17 },
1725  { 1709, 1336, 1, 17, 1428, 17 },
1726  { 1936, 1363, 1, 17, 1428, 17 },
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1728  { 544, 418, 933, 2, 22289, 4 },
1729  { 798, 418, 933, 2, 22289, 4 },
1730  { 1052, 418, 930, 2, 22289, 4 },
1731  { 1291, 418, 930, 2, 22289, 4 },
1732  { 1524, 418, 927, 2, 22289, 4 },
1733  { 1751, 418, 927, 2, 22289, 4 },
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1735  { 2198, 418, 924, 2, 22289, 4 },
1736  { 2398, 418, 921, 2, 22289, 4 },
1737  { 19, 418, 921, 2, 22289, 4 },
1738  { 311, 418, 918, 2, 22289, 4 },
1739  { 603, 418, 918, 2, 22289, 4 },
1740  { 857, 418, 915, 2, 22289, 4 },
1741  { 1111, 418, 915, 2, 22289, 4 },
1742  { 1344, 418, 874, 2, 22289, 4 },
1743  { 1577, 418, 874, 2, 22289, 4 },
1744  { 1804, 418, 791, 2, 22289, 4 },
1745  { 2031, 418, 791, 2, 22289, 4 },
1746  { 2251, 418, 708, 2, 22289, 4 },
1747  { 78, 418, 708, 2, 22289, 4 },
1748  { 370, 418, 625, 2, 22289, 4 },
1749  { 662, 418, 625, 2, 22289, 4 },
1750  { 916, 418, 582, 2, 22289, 4 },
1751  { 1170, 418, 582, 2, 22289, 4 },
1752  { 1403, 418, 577, 2, 22289, 4 },
1753  { 1630, 418, 577, 2, 22289, 4 },
1754  { 1857, 418, 574, 2, 22289, 4 },
1755  { 2084, 418, 574, 2, 22289, 4 },
1756  { 2304, 418, 571, 2, 22289, 4 },
1757  { 131, 418, 571, 2, 22289, 4 },
1758  { 423, 418, 568, 2, 22289, 4 },
1759  { 222, 1, 935, 1, 22257, 0 },
1760  { 514, 1, 932, 1, 22257, 0 },
1761  { 768, 1, 932, 1, 22257, 0 },
1762  { 1022, 1, 929, 1, 22257, 0 },
1763  { 1261, 1, 929, 1, 22257, 0 },
1764  { 1494, 1, 926, 1, 22257, 0 },
1765  { 1721, 1, 926, 1, 22257, 0 },
1766  { 1948, 1, 923, 1, 22257, 0 },
1767  { 2163, 1, 923, 1, 22257, 0 },
1768  { 2383, 1, 920, 1, 22257, 0 },
1769  { 0, 1, 920, 1, 22257, 0 },
1770  { 292, 1, 917, 1, 22257, 0 },
1771  { 584, 1, 917, 1, 22257, 0 },
1772  { 838, 1, 914, 1, 22257, 0 },
1773  { 1092, 1, 914, 1, 22257, 0 },
1774  { 1325, 1, 911, 1, 22257, 0 },
1775  { 1558, 1, 911, 1, 22257, 0 },
1776  { 1785, 1, 868, 1, 22257, 0 },
1777  { 2012, 1, 868, 1, 22257, 0 },
1778  { 2232, 1, 785, 1, 22257, 0 },
1779  { 59, 1, 785, 1, 22257, 0 },
1780  { 351, 1, 702, 1, 22257, 0 },
1781  { 643, 1, 702, 1, 22257, 0 },
1782  { 897, 1, 619, 1, 22257, 0 },
1783  { 1151, 1, 619, 1, 22257, 0 },
1784  { 1384, 1, 576, 1, 22257, 0 },
1785  { 1611, 1, 576, 1, 22257, 0 },
1786  { 1838, 1, 573, 1, 22257, 0 },
1787  { 2065, 1, 573, 1, 22257, 0 },
1788  { 2285, 1, 570, 1, 22257, 0 },
1789  { 112, 1, 570, 1, 22257, 0 },
1790  { 404, 1, 567, 1, 22257, 0 },
1791  { 235, 1172, 1061, 2, 17361, 4 },
1792  { 527, 1172, 1056, 2, 17361, 4 },
1793  { 781, 1172, 1051, 2, 17361, 4 },
1794  { 1035, 1172, 1046, 2, 17361, 4 },
1795  { 1274, 1172, 1046, 2, 17361, 4 },
1796  { 1507, 1172, 1041, 2, 17361, 4 },
1797  { 1734, 1172, 1036, 2, 17361, 4 },
1798  { 1961, 1172, 1031, 2, 17361, 4 },
1799  { 2167, 1172, 1031, 2, 17361, 4 },
1800  { 2387, 1172, 1026, 2, 17361, 4 },
1801  { 5, 1172, 1021, 2, 17361, 4 },
1802  { 297, 1172, 1016, 2, 17361, 4 },
1803  { 589, 1172, 1016, 2, 17361, 4 },
1804  { 843, 1172, 1011, 2, 17361, 4 },
1805  { 1097, 1172, 1006, 2, 17361, 4 },
1806  { 1330, 1172, 1001, 2, 17361, 4 },
1807  { 1563, 1172, 1001, 2, 17361, 4 },
1808  { 1790, 1172, 996, 2, 17361, 4 },
1809  { 2017, 1172, 991, 2, 17361, 4 },
1810  { 2237, 1172, 986, 2, 17361, 4 },
1811  { 64, 1172, 986, 2, 17361, 4 },
1812  { 356, 1172, 981, 2, 17361, 4 },
1813  { 648, 1172, 976, 2, 17361, 4 },
1814  { 902, 1172, 971, 2, 17361, 4 },
1815  { 1156, 1172, 971, 2, 17361, 4 },
1816  { 1389, 1172, 966, 2, 17361, 4 },
1817  { 1616, 1172, 961, 2, 17361, 4 },
1818  { 1843, 1172, 956, 2, 17361, 4 },
1819  { 2070, 1172, 956, 2, 17361, 4 },
1820  { 2290, 1172, 951, 2, 17361, 4 },
1821  { 117, 1172, 946, 2, 17361, 4 },
1822  { 409, 1172, 941, 2, 17361, 4 },
1823  { 277, 1169, 1057, 12, 1714, 14 },
1824  { 569, 1180, 1042, 12, 1714, 14 },
1825  { 823, 1196, 1042, 12, 1714, 14 },
1826  { 1077, 1207, 1027, 12, 1714, 14 },
1827  { 1310, 1223, 1027, 12, 1714, 14 },
1828  { 1543, 1234, 1012, 12, 1714, 14 },
1829  { 1770, 1250, 1012, 12, 1714, 14 },
1830  { 1997, 1261, 997, 12, 1714, 14 },
1831  { 2217, 1277, 997, 12, 1714, 14 },
1832  { 2417, 1288, 982, 12, 1714, 14 },
1833  { 42, 1304, 982, 12, 1714, 14 },
1834  { 334, 1315, 967, 12, 1714, 14 },
1835  { 626, 1331, 967, 12, 1714, 14 },
1836  { 880, 1342, 952, 12, 1714, 14 },
1837  { 1134, 1358, 952, 12, 1714, 14 },
1838  { 1367, 1369, 942, 12, 1714, 14 },
1839  { 1594, 415, 1, 12, 1762, 14 },
1840  { 1821, 420, 1, 12, 1762, 14 },
1841  { 2048, 425, 1, 12, 1762, 14 },
1842  { 2268, 430, 1, 12, 1762, 14 },
1843  { 95, 435, 1, 12, 1762, 14 },
1844  { 387, 440, 1, 12, 1762, 14 },
1845  { 679, 445, 1, 12, 1762, 14 },
1846  { 933, 450, 1, 12, 1762, 14 },
1847  { 1187, 455, 1, 12, 1762, 14 },
1848  { 1420, 460, 1, 12, 1762, 14 },
1849  { 1647, 465, 1, 12, 1762, 14 },
1850  { 1874, 470, 1, 12, 1762, 14 },
1851  { 2101, 475, 1, 12, 1762, 14 },
1852  { 2321, 480, 1, 12, 1762, 14 },
1853  { 148, 485, 1, 12, 1762, 14 },
1854  { 440, 490, 1, 12, 1762, 14 },
1855  { 705, 1, 1, 1, 22161, 0 },
1856  { 959, 1, 1, 1, 22161, 0 },
1857  { 1213, 1, 1, 1, 22161, 0 },
1858  { 1446, 1, 1, 1, 22161, 0 },
1859  { 1673, 1, 1, 1, 22161, 0 },
1860  { 1900, 1, 1, 1, 22161, 0 },
1861  { 2127, 1, 1, 1, 22161, 0 },
1862  { 2347, 1, 1, 1, 22161, 0 },
1863  { 174, 1, 1, 1, 22161, 0 },
1864  { 466, 1, 1, 1, 22161, 0 },
1865  { 720, 1, 1, 1, 22161, 0 },
1866  { 974, 1, 1, 1, 22161, 0 },
1867  { 1228, 1, 1, 1, 22161, 0 },
1868  { 1461, 1, 1, 1, 22161, 0 },
1869  { 1688, 1, 1, 1, 22161, 0 },
1870  { 1915, 1, 1, 1, 22161, 0 },
1871  { 2142, 1, 1, 1, 22161, 0 },
1872  { 2362, 1, 1, 1, 22161, 0 },
1873  { 189, 1, 1, 1, 22161, 0 },
1874  { 481, 1, 1, 1, 22161, 0 },
1875  { 735, 1, 1, 1, 22161, 0 },
1876  { 989, 1, 1, 1, 22161, 0 },
1877  { 1243, 1, 1, 1, 22161, 0 },
1878  { 1476, 1, 1, 1, 22161, 0 },
1879  { 1703, 1, 1, 1, 22161, 0 },
1880  { 1930, 1, 1, 1, 22161, 0 },
1881  { 2157, 1, 1, 1, 22161, 0 },
1882  { 2377, 1, 1, 1, 22161, 0 },
1883  { 204, 1, 1, 1, 22161, 0 },
1884  { 496, 1, 1, 1, 22161, 0 },
1885  { 750, 1, 1, 1, 22161, 0 },
1886  { 1004, 1, 1, 1, 22161, 0 },
1887  { 216, 119, 893, 28, 1352, 22 },
1888  { 508, 147, 830, 28, 1352, 22 },
1889  { 762, 191, 830, 28, 1352, 22 },
1890  { 1016, 219, 747, 28, 1352, 22 },
1891  { 1255, 263, 747, 28, 1352, 22 },
1892  { 1488, 291, 664, 28, 1352, 22 },
1893  { 1715, 335, 664, 28, 1352, 22 },
1894  { 1942, 363, 601, 28, 1352, 22 },
1895  { 226, 137, 873, 28, 1272, 22 },
1896  { 518, 181, 790, 28, 1272, 22 },
1897  { 772, 209, 790, 28, 1272, 22 },
1898  { 1026, 253, 707, 28, 1272, 22 },
1899  { 1265, 281, 707, 28, 1272, 22 },
1900  { 1498, 325, 624, 28, 1272, 22 },
1901  { 1725, 353, 624, 28, 1272, 22 },
1902  { 1952, 397, 581, 28, 1272, 22 },
1903  { 263, 1092, 563, 0, 17393, 2 },
1904  { 555, 1092, 559, 0, 17393, 2 },
1905  { 809, 1092, 559, 0, 17393, 2 },
1906  { 1063, 1092, 555, 0, 17393, 2 },
1907  { 1302, 1092, 555, 0, 17393, 2 },
1908  { 1535, 1092, 551, 0, 17393, 2 },
1909  { 1762, 1092, 551, 0, 17393, 2 },
1910  { 1989, 1092, 547, 0, 17393, 2 },
1911  { 2209, 1092, 547, 0, 17393, 2 },
1912  { 2409, 1092, 543, 0, 17393, 2 },
1913  { 32, 1092, 543, 0, 17393, 2 },
1914  { 324, 1092, 539, 0, 17393, 2 },
1915  { 616, 1092, 539, 0, 17393, 2 },
1916  { 870, 1092, 535, 0, 17393, 2 },
1917  { 1124, 1092, 535, 0, 17393, 2 },
1918  { 1357, 1092, 531, 0, 17393, 2 },
1919  { 1590, 1092, 531, 0, 17393, 2 },
1920  { 1817, 1092, 527, 0, 17393, 2 },
1921  { 2044, 1092, 527, 0, 17393, 2 },
1922  { 2264, 1092, 523, 0, 17393, 2 },
1923  { 91, 1092, 523, 0, 17393, 2 },
1924  { 383, 1092, 519, 0, 17393, 2 },
1925  { 675, 1092, 519, 0, 17393, 2 },
1926  { 929, 1092, 515, 0, 17393, 2 },
1927  { 1183, 1092, 515, 0, 17393, 2 },
1928  { 1416, 1092, 511, 0, 17393, 2 },
1929  { 1643, 1092, 511, 0, 17393, 2 },
1930  { 1870, 1092, 507, 0, 17393, 2 },
1931  { 2097, 1092, 507, 0, 17393, 2 },
1932  { 2317, 1092, 503, 0, 17393, 2 },
1933  { 144, 1092, 503, 0, 17393, 2 },
1934  { 436, 1092, 499, 0, 17393, 2 },
1935  { 2172, 1079, 1, 0, 6496, 2 },
1936  { 2501, 1, 1083, 1, 17172, 0 },
1937  { 2507, 1, 1083, 1, 17172, 0 },
1938  { 2513, 1, 1083, 1, 17172, 0 },
1939  { 2519, 1, 1083, 1, 17172, 0 },
1940  { 2525, 1, 1083, 1, 17172, 0 },
1941  { 2531, 1, 1083, 1, 17172, 0 },
1942  { 2537, 1, 1083, 1, 17172, 0 },
1943  { 2543, 1, 1083, 1, 17172, 0 },
1944  { 2568, 1, 1081, 1, 17140, 0 },
1945  { 2574, 1, 1081, 1, 17140, 0 },
1946  { 2580, 1, 1081, 1, 17140, 0 },
1947  { 2586, 1, 1081, 1, 17140, 0 },
1948  { 2592, 1, 1081, 1, 17140, 0 },
1949  { 2598, 1, 1081, 1, 17140, 0 },
1950  { 2604, 1, 1081, 1, 17140, 0 },
1951  { 2610, 1, 1081, 1, 17140, 0 },
1952  { 2616, 1, 1077, 1, 17108, 0 },
1953  { 2622, 1, 1077, 1, 17108, 0 },
1954  { 2628, 1, 1077, 1, 17108, 0 },
1955  { 2634, 1, 1077, 1, 17108, 0 },
1956  { 2640, 1, 1077, 1, 17108, 0 },
1957  { 2646, 1, 1077, 1, 17108, 0 },
1958  { 2652, 1, 1077, 1, 17108, 0 },
1959  { 2658, 1, 1077, 1, 17108, 0 },
1960  { 2442, 1, 1075, 1, 17076, 0 },
1961  { 2448, 1, 1075, 1, 17076, 0 },
1962  { 2454, 1, 1075, 1, 17076, 0 },
1963  { 2460, 1, 1075, 1, 17076, 0 },
1964  { 2466, 1, 1075, 1, 17076, 0 },
1965  { 2472, 1, 1075, 1, 17076, 0 },
1966  { 2478, 1, 1075, 1, 17076, 0 },
1967  { 2484, 1, 1075, 1, 17076, 0 },
1968  { 266, 1089, 1, 81, 1666, 53 },
1969  { 558, 1094, 1, 81, 1666, 53 },
1970  { 812, 1099, 1, 81, 1666, 53 },
1971  { 1066, 1104, 1, 81, 1666, 53 },
1972  { 1305, 1109, 1, 81, 1666, 53 },
1973  { 1538, 1114, 1, 81, 1666, 53 },
1974  { 1765, 1119, 1, 81, 1666, 53 },
1975  { 1992, 1124, 1, 81, 1666, 53 },
1976  { 2212, 1129, 1, 81, 1666, 53 },
1977  { 2412, 1134, 1, 81, 1666, 53 },
1978  { 36, 1139, 1, 81, 1666, 53 },
1979  { 328, 1144, 1, 81, 1666, 53 },
1980  { 620, 1149, 1, 81, 1666, 53 },
1981  { 874, 1154, 1, 81, 1666, 53 },
1982  { 1128, 1159, 1, 81, 1666, 53 },
1983  { 1361, 1164, 1, 81, 1666, 53 },
1984};
1985
1986extern const MCPhysReg PPCRegUnitRoots[][2] = {
1987  { PPC::BP },
1988  { PPC::CARRY, PPC::XER },
1989  { PPC::CTR },
1990  { PPC::FP },
1991  { PPC::LR },
1992  { PPC::RM },
1993  { PPC::SPEFSCR },
1994  { PPC::VRSAVE },
1995  { PPC::ZERO },
1996  { PPC::F0 },
1997  { PPC::F1 },
1998  { PPC::F2 },
1999  { PPC::F3 },
2000  { PPC::F4 },
2001  { PPC::F5 },
2002  { PPC::F6 },
2003  { PPC::F7 },
2004  { PPC::F8 },
2005  { PPC::F9 },
2006  { PPC::F10 },
2007  { PPC::F11 },
2008  { PPC::F12 },
2009  { PPC::F13 },
2010  { PPC::F14 },
2011  { PPC::F15 },
2012  { PPC::F16 },
2013  { PPC::F17 },
2014  { PPC::F18 },
2015  { PPC::F19 },
2016  { PPC::F20 },
2017  { PPC::F21 },
2018  { PPC::F22 },
2019  { PPC::F23 },
2020  { PPC::F24 },
2021  { PPC::F25 },
2022  { PPC::F26 },
2023  { PPC::F27 },
2024  { PPC::F28 },
2025  { PPC::F29 },
2026  { PPC::F30 },
2027  { PPC::F31 },
2028  { PPC::CR0LT },
2029  { PPC::CR0GT },
2030  { PPC::CR0EQ },
2031  { PPC::CR0UN },
2032  { PPC::CR1LT },
2033  { PPC::CR1GT },
2034  { PPC::CR1EQ },
2035  { PPC::CR1UN },
2036  { PPC::CR2LT },
2037  { PPC::CR2GT },
2038  { PPC::CR2EQ },
2039  { PPC::CR2UN },
2040  { PPC::CR3LT },
2041  { PPC::CR3GT },
2042  { PPC::CR3EQ },
2043  { PPC::CR3UN },
2044  { PPC::CR4LT },
2045  { PPC::CR4GT },
2046  { PPC::CR4EQ },
2047  { PPC::CR4UN },
2048  { PPC::CR5LT },
2049  { PPC::CR5GT },
2050  { PPC::CR5EQ },
2051  { PPC::CR5UN },
2052  { PPC::CR6LT },
2053  { PPC::CR6GT },
2054  { PPC::CR6EQ },
2055  { PPC::CR6UN },
2056  { PPC::CR7LT },
2057  { PPC::CR7GT },
2058  { PPC::CR7EQ },
2059  { PPC::CR7UN },
2060  { PPC::CTR8 },
2061  { PPC::DMRROW0 },
2062  { PPC::DMRROW1 },
2063  { PPC::DMRROW2 },
2064  { PPC::DMRROW3 },
2065  { PPC::DMRROW4 },
2066  { PPC::DMRROW5 },
2067  { PPC::DMRROW6 },
2068  { PPC::DMRROW7 },
2069  { PPC::DMRROW8 },
2070  { PPC::DMRROW9 },
2071  { PPC::DMRROW10 },
2072  { PPC::DMRROW11 },
2073  { PPC::DMRROW12 },
2074  { PPC::DMRROW13 },
2075  { PPC::DMRROW14 },
2076  { PPC::DMRROW15 },
2077  { PPC::DMRROW16 },
2078  { PPC::DMRROW17 },
2079  { PPC::DMRROW18 },
2080  { PPC::DMRROW19 },
2081  { PPC::DMRROW20 },
2082  { PPC::DMRROW21 },
2083  { PPC::DMRROW22 },
2084  { PPC::DMRROW23 },
2085  { PPC::DMRROW24 },
2086  { PPC::DMRROW25 },
2087  { PPC::DMRROW26 },
2088  { PPC::DMRROW27 },
2089  { PPC::DMRROW28 },
2090  { PPC::DMRROW29 },
2091  { PPC::DMRROW30 },
2092  { PPC::DMRROW31 },
2093  { PPC::DMRROW32 },
2094  { PPC::DMRROW33 },
2095  { PPC::DMRROW34 },
2096  { PPC::DMRROW35 },
2097  { PPC::DMRROW36 },
2098  { PPC::DMRROW37 },
2099  { PPC::DMRROW38 },
2100  { PPC::DMRROW39 },
2101  { PPC::DMRROW40 },
2102  { PPC::DMRROW41 },
2103  { PPC::DMRROW42 },
2104  { PPC::DMRROW43 },
2105  { PPC::DMRROW44 },
2106  { PPC::DMRROW45 },
2107  { PPC::DMRROW46 },
2108  { PPC::DMRROW47 },
2109  { PPC::DMRROW48 },
2110  { PPC::DMRROW49 },
2111  { PPC::DMRROW50 },
2112  { PPC::DMRROW51 },
2113  { PPC::DMRROW52 },
2114  { PPC::DMRROW53 },
2115  { PPC::DMRROW54 },
2116  { PPC::DMRROW55 },
2117  { PPC::DMRROW56 },
2118  { PPC::DMRROW57 },
2119  { PPC::DMRROW58 },
2120  { PPC::DMRROW59 },
2121  { PPC::DMRROW60 },
2122  { PPC::DMRROW61 },
2123  { PPC::DMRROW62 },
2124  { PPC::DMRROW63 },
2125  { PPC::LR8 },
2126  { PPC::R0 },
2127  { PPC::R1 },
2128  { PPC::R2 },
2129  { PPC::R3 },
2130  { PPC::R4 },
2131  { PPC::R5 },
2132  { PPC::R6 },
2133  { PPC::R7 },
2134  { PPC::R8 },
2135  { PPC::R9 },
2136  { PPC::R10 },
2137  { PPC::R11 },
2138  { PPC::R12 },
2139  { PPC::R13 },
2140  { PPC::R14 },
2141  { PPC::R15 },
2142  { PPC::R16 },
2143  { PPC::R17 },
2144  { PPC::R18 },
2145  { PPC::R19 },
2146  { PPC::R20 },
2147  { PPC::R21 },
2148  { PPC::R22 },
2149  { PPC::R23 },
2150  { PPC::R24 },
2151  { PPC::R25 },
2152  { PPC::R26 },
2153  { PPC::R27 },
2154  { PPC::R28 },
2155  { PPC::R29 },
2156  { PPC::R30 },
2157  { PPC::R31 },
2158  { PPC::VF0 },
2159  { PPC::VF1 },
2160  { PPC::VF2 },
2161  { PPC::VF3 },
2162  { PPC::VF4 },
2163  { PPC::VF5 },
2164  { PPC::VF6 },
2165  { PPC::VF7 },
2166  { PPC::VF8 },
2167  { PPC::VF9 },
2168  { PPC::VF10 },
2169  { PPC::VF11 },
2170  { PPC::VF12 },
2171  { PPC::VF13 },
2172  { PPC::VF14 },
2173  { PPC::VF15 },
2174  { PPC::VF16 },
2175  { PPC::VF17 },
2176  { PPC::VF18 },
2177  { PPC::VF19 },
2178  { PPC::VF20 },
2179  { PPC::VF21 },
2180  { PPC::VF22 },
2181  { PPC::VF23 },
2182  { PPC::VF24 },
2183  { PPC::VF25 },
2184  { PPC::VF26 },
2185  { PPC::VF27 },
2186  { PPC::VF28 },
2187  { PPC::VF29 },
2188  { PPC::VF30 },
2189  { PPC::VF31 },
2190  { PPC::VSX32 },
2191  { PPC::VSX33 },
2192  { PPC::VSX34 },
2193  { PPC::VSX35 },
2194  { PPC::VSX36 },
2195  { PPC::VSX37 },
2196  { PPC::VSX38 },
2197  { PPC::VSX39 },
2198  { PPC::VSX40 },
2199  { PPC::VSX41 },
2200  { PPC::VSX42 },
2201  { PPC::VSX43 },
2202  { PPC::VSX44 },
2203  { PPC::VSX45 },
2204  { PPC::VSX46 },
2205  { PPC::VSX47 },
2206  { PPC::VSX48 },
2207  { PPC::VSX49 },
2208  { PPC::VSX50 },
2209  { PPC::VSX51 },
2210  { PPC::VSX52 },
2211  { PPC::VSX53 },
2212  { PPC::VSX54 },
2213  { PPC::VSX55 },
2214  { PPC::VSX56 },
2215  { PPC::VSX57 },
2216  { PPC::VSX58 },
2217  { PPC::VSX59 },
2218  { PPC::VSX60 },
2219  { PPC::VSX61 },
2220  { PPC::VSX62 },
2221  { PPC::VSX63 },
2222};
2223
2224namespace {     // Register classes...
2225  // VSSRC Register Class...
2226  const MCPhysReg VSSRC[] = {
2227    PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F31, PPC::F30, PPC::F29, PPC::F28, PPC::F27, PPC::F26, PPC::F25, PPC::F24, PPC::F23, PPC::F22, PPC::F21, PPC::F20, PPC::F19, PPC::F18, PPC::F17, PPC::F16, PPC::F15, PPC::F14, PPC::VF2, PPC::VF3, PPC::VF4, PPC::VF5, PPC::VF0, PPC::VF1, PPC::VF6, PPC::VF7, PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11, PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15, PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19, PPC::VF31, PPC::VF30, PPC::VF29, PPC::VF28, PPC::VF27, PPC::VF26, PPC::VF25, PPC::VF24, PPC::VF23, PPC::VF22, PPC::VF21, PPC::VF20,
2228  };
2229
2230  // VSSRC Bit set.
2231  const uint8_t VSSRCBits[] = {
2232    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
2233  };
2234
2235  // GPRC Register Class...
2236  const MCPhysReg GPRC[] = {
2237    PPC::R2, PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::R30, PPC::R29, PPC::R28, PPC::R27, PPC::R26, PPC::R25, PPC::R24, PPC::R23, PPC::R22, PPC::R21, PPC::R20, PPC::R19, PPC::R18, PPC::R17, PPC::R16, PPC::R15, PPC::R14, PPC::R13, PPC::R31, PPC::R0, PPC::R1, PPC::FP, PPC::BP,
2238  };
2239
2240  // GPRC Bit set.
2241  const uint8_t GPRCBits[] = {
2242    0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
2243  };
2244
2245  // GPRC_NOR0 Register Class...
2246  const MCPhysReg GPRC_NOR0[] = {
2247    PPC::R2, PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::R30, PPC::R29, PPC::R28, PPC::R27, PPC::R26, PPC::R25, PPC::R24, PPC::R23, PPC::R22, PPC::R21, PPC::R20, PPC::R19, PPC::R18, PPC::R17, PPC::R16, PPC::R15, PPC::R14, PPC::R13, PPC::R31, PPC::R1, PPC::FP, PPC::BP, PPC::ZERO,
2248  };
2249
2250  // GPRC_NOR0 Bit set.
2251  const uint8_t GPRC_NOR0Bits[] = {
2252    0x12, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x07,
2253  };
2254
2255  // GPRC_and_GPRC_NOR0 Register Class...
2256  const MCPhysReg GPRC_and_GPRC_NOR0[] = {
2257    PPC::R2, PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::R30, PPC::R29, PPC::R28, PPC::R27, PPC::R26, PPC::R25, PPC::R24, PPC::R23, PPC::R22, PPC::R21, PPC::R20, PPC::R19, PPC::R18, PPC::R17, PPC::R16, PPC::R15, PPC::R14, PPC::R13, PPC::R31, PPC::R1, PPC::FP, PPC::BP,
2258  };
2259
2260  // GPRC_and_GPRC_NOR0 Bit set.
2261  const uint8_t GPRC_and_GPRC_NOR0Bits[] = {
2262    0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x07,
2263  };
2264
2265  // CRBITRC Register Class...
2266  const MCPhysReg CRBITRC[] = {
2267    PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN, PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN, PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN, PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN, PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN,
2268  };
2269
2270  // CRBITRC Bit set.
2271  const uint8_t CRBITRCBits[] = {
2272    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f,
2273  };
2274
2275  // F4RC Register Class...
2276  const MCPhysReg F4RC[] = {
2277    PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F31, PPC::F30, PPC::F29, PPC::F28, PPC::F27, PPC::F26, PPC::F25, PPC::F24, PPC::F23, PPC::F22, PPC::F21, PPC::F20, PPC::F19, PPC::F18, PPC::F17, PPC::F16, PPC::F15, PPC::F14,
2278  };
2279
2280  // F4RC Bit set.
2281  const uint8_t F4RCBits[] = {
2282    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
2283  };
2284
2285  // CRRC Register Class...
2286  const MCPhysReg CRRC[] = {
2287    PPC::CR0, PPC::CR1, PPC::CR5, PPC::CR6, PPC::CR7, PPC::CR2, PPC::CR3, PPC::CR4,
2288  };
2289
2290  // CRRC Bit set.
2291  const uint8_t CRRCBits[] = {
2292    0x00, 0x00, 0xf0, 0x0f,
2293  };
2294
2295  // CARRYRC Register Class...
2296  const MCPhysReg CARRYRC[] = {
2297    PPC::CARRY, PPC::XER,
2298  };
2299
2300  // CARRYRC Bit set.
2301  const uint8_t CARRYRCBits[] = {
2302    0x04, 0x02,
2303  };
2304
2305  // CTRRC Register Class...
2306  const MCPhysReg CTRRC[] = {
2307    PPC::CTR,
2308  };
2309
2310  // CTRRC Bit set.
2311  const uint8_t CTRRCBits[] = {
2312    0x08,
2313  };
2314
2315  // LRRC Register Class...
2316  const MCPhysReg LRRC[] = {
2317    PPC::LR,
2318  };
2319
2320  // LRRC Bit set.
2321  const uint8_t LRRCBits[] = {
2322    0x20,
2323  };
2324
2325  // VRSAVERC Register Class...
2326  const MCPhysReg VRSAVERC[] = {
2327    PPC::VRSAVE,
2328  };
2329
2330  // VRSAVERC Bit set.
2331  const uint8_t VRSAVERCBits[] = {
2332    0x00, 0x01,
2333  };
2334
2335  // SPILLTOVSRRC Register Class...
2336  const MCPhysReg SPILLTOVSRRC[] = {
2337    PPC::X2, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::X30, PPC::X29, PPC::X28, PPC::X27, PPC::X26, PPC::X25, PPC::X24, PPC::X23, PPC::X22, PPC::X21, PPC::X20, PPC::X19, PPC::X18, PPC::X17, PPC::X16, PPC::X15, PPC::X14, PPC::X31, PPC::X13, PPC::X0, PPC::X1, PPC::FP8, PPC::BP8, PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::VF2, PPC::VF3, PPC::VF4, PPC::VF5, PPC::VF0, PPC::VF1, PPC::VF6, PPC::VF7, PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11, PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15, PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
2338  };
2339
2340  // SPILLTOVSRRC Bit set.
2341  const uint8_t SPILLTOVSRRCBits[] = {
2342    0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x7f, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
2343  };
2344
2345  // VSFRC Register Class...
2346  const MCPhysReg VSFRC[] = {
2347    PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F31, PPC::F30, PPC::F29, PPC::F28, PPC::F27, PPC::F26, PPC::F25, PPC::F24, PPC::F23, PPC::F22, PPC::F21, PPC::F20, PPC::F19, PPC::F18, PPC::F17, PPC::F16, PPC::F15, PPC::F14, PPC::VF2, PPC::VF3, PPC::VF4, PPC::VF5, PPC::VF0, PPC::VF1, PPC::VF6, PPC::VF7, PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11, PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15, PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19, PPC::VF31, PPC::VF30, PPC::VF29, PPC::VF28, PPC::VF27, PPC::VF26, PPC::VF25, PPC::VF24, PPC::VF23, PPC::VF22, PPC::VF21, PPC::VF20,
2348  };
2349
2350  // VSFRC Bit set.
2351  const uint8_t VSFRCBits[] = {
2352    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
2353  };
2354
2355  // G8RC Register Class...
2356  const MCPhysReg G8RC[] = {
2357    PPC::X2, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::X30, PPC::X29, PPC::X28, PPC::X27, PPC::X26, PPC::X25, PPC::X24, PPC::X23, PPC::X22, PPC::X21, PPC::X20, PPC::X19, PPC::X18, PPC::X17, PPC::X16, PPC::X15, PPC::X14, PPC::X31, PPC::X13, PPC::X0, PPC::X1, PPC::FP8, PPC::BP8,
2358  };
2359
2360  // G8RC Bit set.
2361  const uint8_t G8RCBits[] = {
2362    0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
2363  };
2364
2365  // G8RC_NOX0 Register Class...
2366  const MCPhysReg G8RC_NOX0[] = {
2367    PPC::X2, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::X30, PPC::X29, PPC::X28, PPC::X27, PPC::X26, PPC::X25, PPC::X24, PPC::X23, PPC::X22, PPC::X21, PPC::X20, PPC::X19, PPC::X18, PPC::X17, PPC::X16, PPC::X15, PPC::X14, PPC::X31, PPC::X13, PPC::X1, PPC::FP8, PPC::BP8, PPC::ZERO8,
2368  };
2369
2370  // G8RC_NOX0 Bit set.
2371  const uint8_t G8RC_NOX0Bits[] = {
2372    0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f,
2373  };
2374
2375  // SPILLTOVSRRC_and_VSFRC Register Class...
2376  const MCPhysReg SPILLTOVSRRC_and_VSFRC[] = {
2377    PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::VF2, PPC::VF3, PPC::VF4, PPC::VF5, PPC::VF0, PPC::VF1, PPC::VF6, PPC::VF7, PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11, PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15, PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
2378  };
2379
2380  // SPILLTOVSRRC_and_VSFRC Bit set.
2381  const uint8_t SPILLTOVSRRC_and_VSFRCBits[] = {
2382    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x7f,
2383  };
2384
2385  // G8RC_and_G8RC_NOX0 Register Class...
2386  const MCPhysReg G8RC_and_G8RC_NOX0[] = {
2387    PPC::X2, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::X30, PPC::X29, PPC::X28, PPC::X27, PPC::X26, PPC::X25, PPC::X24, PPC::X23, PPC::X22, PPC::X21, PPC::X20, PPC::X19, PPC::X18, PPC::X17, PPC::X16, PPC::X15, PPC::X14, PPC::X31, PPC::X13, PPC::X1, PPC::FP8, PPC::BP8,
2388  };
2389
2390  // G8RC_and_G8RC_NOX0 Bit set.
2391  const uint8_t G8RC_and_G8RC_NOX0Bits[] = {
2392    0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x07,
2393  };
2394
2395  // F8RC Register Class...
2396  const MCPhysReg F8RC[] = {
2397    PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F31, PPC::F30, PPC::F29, PPC::F28, PPC::F27, PPC::F26, PPC::F25, PPC::F24, PPC::F23, PPC::F22, PPC::F21, PPC::F20, PPC::F19, PPC::F18, PPC::F17, PPC::F16, PPC::F15, PPC::F14,
2398  };
2399
2400  // F8RC Bit set.
2401  const uint8_t F8RCBits[] = {
2402    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
2403  };
2404
2405  // SPERC Register Class...
2406  const MCPhysReg SPERC[] = {
2407    PPC::S2, PPC::S3, PPC::S4, PPC::S5, PPC::S6, PPC::S7, PPC::S8, PPC::S9, PPC::S10, PPC::S11, PPC::S12, PPC::S30, PPC::S29, PPC::S28, PPC::S27, PPC::S26, PPC::S25, PPC::S24, PPC::S23, PPC::S22, PPC::S21, PPC::S20, PPC::S19, PPC::S18, PPC::S17, PPC::S16, PPC::S15, PPC::S14, PPC::S13, PPC::S31, PPC::S0, PPC::S1,
2408  };
2409
2410  // SPERC Bit set.
2411  const uint8_t SPERCBits[] = {
2412    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
2413  };
2414
2415  // VFRC Register Class...
2416  const MCPhysReg VFRC[] = {
2417    PPC::VF2, PPC::VF3, PPC::VF4, PPC::VF5, PPC::VF0, PPC::VF1, PPC::VF6, PPC::VF7, PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11, PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15, PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19, PPC::VF31, PPC::VF30, PPC::VF29, PPC::VF28, PPC::VF27, PPC::VF26, PPC::VF25, PPC::VF24, PPC::VF23, PPC::VF22, PPC::VF21, PPC::VF20,
2418  };
2419
2420  // VFRC Bit set.
2421  const uint8_t VFRCBits[] = {
2422    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
2423  };
2424
2425  // SPERC_with_sub_32_in_GPRC_NOR0 Register Class...
2426  const MCPhysReg SPERC_with_sub_32_in_GPRC_NOR0[] = {
2427    PPC::S2, PPC::S3, PPC::S4, PPC::S5, PPC::S6, PPC::S7, PPC::S8, PPC::S9, PPC::S10, PPC::S11, PPC::S12, PPC::S30, PPC::S29, PPC::S28, PPC::S27, PPC::S26, PPC::S25, PPC::S24, PPC::S23, PPC::S22, PPC::S21, PPC::S20, PPC::S19, PPC::S18, PPC::S17, PPC::S16, PPC::S15, PPC::S14, PPC::S13, PPC::S31, PPC::S1,
2428  };
2429
2430  // SPERC_with_sub_32_in_GPRC_NOR0 Bit set.
2431  const uint8_t SPERC_with_sub_32_in_GPRC_NOR0Bits[] = {
2432    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x07,
2433  };
2434
2435  // SPILLTOVSRRC_and_VFRC Register Class...
2436  const MCPhysReg SPILLTOVSRRC_and_VFRC[] = {
2437    PPC::VF2, PPC::VF3, PPC::VF4, PPC::VF5, PPC::VF0, PPC::VF1, PPC::VF6, PPC::VF7, PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11, PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15, PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
2438  };
2439
2440  // SPILLTOVSRRC_and_VFRC Bit set.
2441  const uint8_t SPILLTOVSRRC_and_VFRCBits[] = {
2442    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x7f,
2443  };
2444
2445  // SPILLTOVSRRC_and_F4RC Register Class...
2446  const MCPhysReg SPILLTOVSRRC_and_F4RC[] = {
2447    PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13,
2448  };
2449
2450  // SPILLTOVSRRC_and_F4RC Bit set.
2451  const uint8_t SPILLTOVSRRC_and_F4RCBits[] = {
2452    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x7f,
2453  };
2454
2455  // CTRRC8 Register Class...
2456  const MCPhysReg CTRRC8[] = {
2457    PPC::CTR8,
2458  };
2459
2460  // CTRRC8 Bit set.
2461  const uint8_t CTRRC8Bits[] = {
2462    0x00, 0x00, 0x00, 0x10,
2463  };
2464
2465  // LR8RC Register Class...
2466  const MCPhysReg LR8RC[] = {
2467    PPC::LR8,
2468  };
2469
2470  // LR8RC Bit set.
2471  const uint8_t LR8RCBits[] = {
2472    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,
2473  };
2474
2475  // DMRROWRC Register Class...
2476  const MCPhysReg DMRROWRC[] = {
2477    PPC::DMRROW0, PPC::DMRROW1, PPC::DMRROW2, PPC::DMRROW3, PPC::DMRROW4, PPC::DMRROW5, PPC::DMRROW6, PPC::DMRROW7, PPC::DMRROW8, PPC::DMRROW9, PPC::DMRROW10, PPC::DMRROW11, PPC::DMRROW12, PPC::DMRROW13, PPC::DMRROW14, PPC::DMRROW15, PPC::DMRROW16, PPC::DMRROW17, PPC::DMRROW18, PPC::DMRROW19, PPC::DMRROW20, PPC::DMRROW21, PPC::DMRROW22, PPC::DMRROW23, PPC::DMRROW24, PPC::DMRROW25, PPC::DMRROW26, PPC::DMRROW27, PPC::DMRROW28, PPC::DMRROW29, PPC::DMRROW30, PPC::DMRROW31, PPC::DMRROW32, PPC::DMRROW33, PPC::DMRROW34, PPC::DMRROW35, PPC::DMRROW36, PPC::DMRROW37, PPC::DMRROW38, PPC::DMRROW39, PPC::DMRROW40, PPC::DMRROW41, PPC::DMRROW42, PPC::DMRROW43, PPC::DMRROW44, PPC::DMRROW45, PPC::DMRROW46, PPC::DMRROW47, PPC::DMRROW48, PPC::DMRROW49, PPC::DMRROW50, PPC::DMRROW51, PPC::DMRROW52, PPC::DMRROW53, PPC::DMRROW54, PPC::DMRROW55, PPC::DMRROW56, PPC::DMRROW57, PPC::DMRROW58, PPC::DMRROW59, PPC::DMRROW60, PPC::DMRROW61, PPC::DMRROW62, PPC::DMRROW63,
2478  };
2479
2480  // DMRROWRC Bit set.
2481  const uint8_t DMRROWRCBits[] = {
2482    0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x1f,
2483  };
2484
2485  // VSRC Register Class...
2486  const MCPhysReg VSRC[] = {
2487    PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3, PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7, PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11, PPC::VSL12, PPC::VSL13, PPC::VSL31, PPC::VSL30, PPC::VSL29, PPC::VSL28, PPC::VSL27, PPC::VSL26, PPC::VSL25, PPC::VSL24, PPC::VSL23, PPC::VSL22, PPC::VSL21, PPC::VSL20, PPC::VSL19, PPC::VSL18, PPC::VSL17, PPC::VSL16, PPC::VSL15, PPC::VSL14, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V0, PPC::V1, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V31, PPC::V30, PPC::V29, PPC::V28, PPC::V27, PPC::V26, PPC::V25, PPC::V24, PPC::V23, PPC::V22, PPC::V21, PPC::V20,
2488  };
2489
2490  // VSRC Bit set.
2491  const uint8_t VSRCBits[] = {
2492    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
2493  };
2494
2495  // VSRC_with_sub_64_in_SPILLTOVSRRC Register Class...
2496  const MCPhysReg VSRC_with_sub_64_in_SPILLTOVSRRC[] = {
2497    PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3, PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7, PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11, PPC::VSL12, PPC::VSL13, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V0, PPC::V1, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19,
2498  };
2499
2500  // VSRC_with_sub_64_in_SPILLTOVSRRC Bit set.
2501  const uint8_t VSRC_with_sub_64_in_SPILLTOVSRRCBits[] = {
2502    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x01,
2503  };
2504
2505  // VRRC Register Class...
2506  const MCPhysReg VRRC[] = {
2507    PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V0, PPC::V1, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V31, PPC::V30, PPC::V29, PPC::V28, PPC::V27, PPC::V26, PPC::V25, PPC::V24, PPC::V23, PPC::V22, PPC::V21, PPC::V20,
2508  };
2509
2510  // VRRC Bit set.
2511  const uint8_t VRRCBits[] = {
2512    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
2513  };
2514
2515  // VSLRC Register Class...
2516  const MCPhysReg VSLRC[] = {
2517    PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3, PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7, PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11, PPC::VSL12, PPC::VSL13, PPC::VSL31, PPC::VSL30, PPC::VSL29, PPC::VSL28, PPC::VSL27, PPC::VSL26, PPC::VSL25, PPC::VSL24, PPC::VSL23, PPC::VSL22, PPC::VSL21, PPC::VSL20, PPC::VSL19, PPC::VSL18, PPC::VSL17, PPC::VSL16, PPC::VSL15, PPC::VSL14,
2518  };
2519
2520  // VSLRC Bit set.
2521  const uint8_t VSLRCBits[] = {
2522    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
2523  };
2524
2525  // VRRC_with_sub_64_in_SPILLTOVSRRC Register Class...
2526  const MCPhysReg VRRC_with_sub_64_in_SPILLTOVSRRC[] = {
2527    PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V0, PPC::V1, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19,
2528  };
2529
2530  // VRRC_with_sub_64_in_SPILLTOVSRRC Bit set.
2531  const uint8_t VRRC_with_sub_64_in_SPILLTOVSRRCBits[] = {
2532    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x7f,
2533  };
2534
2535  // G8pRC Register Class...
2536  const MCPhysReg G8pRC[] = {
2537    PPC::G8p1, PPC::G8p2, PPC::G8p3, PPC::G8p4, PPC::G8p5, PPC::G8p14, PPC::G8p13, PPC::G8p12, PPC::G8p11, PPC::G8p10, PPC::G8p9, PPC::G8p8, PPC::G8p7, PPC::G8p15, PPC::G8p6, PPC::G8p0,
2538  };
2539
2540  // G8pRC Bit set.
2541  const uint8_t G8pRCBits[] = {
2542    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f,
2543  };
2544
2545  // G8pRC_with_sub_32_in_GPRC_NOR0 Register Class...
2546  const MCPhysReg G8pRC_with_sub_32_in_GPRC_NOR0[] = {
2547    PPC::G8p1, PPC::G8p2, PPC::G8p3, PPC::G8p4, PPC::G8p5, PPC::G8p14, PPC::G8p13, PPC::G8p12, PPC::G8p11, PPC::G8p10, PPC::G8p9, PPC::G8p8, PPC::G8p7, PPC::G8p15, PPC::G8p6,
2548  };
2549
2550  // G8pRC_with_sub_32_in_GPRC_NOR0 Bit set.
2551  const uint8_t G8pRC_with_sub_32_in_GPRC_NOR0Bits[] = {
2552    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f,
2553  };
2554
2555  // VSLRC_with_sub_64_in_SPILLTOVSRRC Register Class...
2556  const MCPhysReg VSLRC_with_sub_64_in_SPILLTOVSRRC[] = {
2557    PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3, PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7, PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11, PPC::VSL12, PPC::VSL13,
2558  };
2559
2560  // VSLRC_with_sub_64_in_SPILLTOVSRRC Bit set.
2561  const uint8_t VSLRC_with_sub_64_in_SPILLTOVSRRCBits[] = {
2562    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x01,
2563  };
2564
2565  // DMRROWpRC Register Class...
2566  const MCPhysReg DMRROWpRC[] = {
2567    PPC::DMRROWp0, PPC::DMRROWp1, PPC::DMRROWp2, PPC::DMRROWp3, PPC::DMRROWp4, PPC::DMRROWp5, PPC::DMRROWp6, PPC::DMRROWp7, PPC::DMRROWp8, PPC::DMRROWp9, PPC::DMRROWp10, PPC::DMRROWp11, PPC::DMRROWp12, PPC::DMRROWp13, PPC::DMRROWp14, PPC::DMRROWp15, PPC::DMRROWp16, PPC::DMRROWp17, PPC::DMRROWp18, PPC::DMRROWp19, PPC::DMRROWp20, PPC::DMRROWp21, PPC::DMRROWp22, PPC::DMRROWp23, PPC::DMRROWp24, PPC::DMRROWp25, PPC::DMRROWp26, PPC::DMRROWp27, PPC::DMRROWp28, PPC::DMRROWp29, PPC::DMRROWp30, PPC::DMRROWp31,
2568  };
2569
2570  // DMRROWpRC Bit set.
2571  const uint8_t DMRROWpRCBits[] = {
2572    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f,
2573  };
2574
2575  // VSRpRC Register Class...
2576  const MCPhysReg VSRpRC[] = {
2577    PPC::VSRp17, PPC::VSRp18, PPC::VSRp16, PPC::VSRp19, PPC::VSRp20, PPC::VSRp21, PPC::VSRp22, PPC::VSRp23, PPC::VSRp24, PPC::VSRp25, PPC::VSRp31, PPC::VSRp30, PPC::VSRp29, PPC::VSRp28, PPC::VSRp27, PPC::VSRp26, PPC::VSRp0, PPC::VSRp1, PPC::VSRp2, PPC::VSRp3, PPC::VSRp4, PPC::VSRp5, PPC::VSRp6, PPC::VSRp15, PPC::VSRp14, PPC::VSRp13, PPC::VSRp12, PPC::VSRp11, PPC::VSRp10, PPC::VSRp9, PPC::VSRp8, PPC::VSRp7,
2578  };
2579
2580  // VSRpRC Bit set.
2581  const uint8_t VSRpRCBits[] = {
2582    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
2583  };
2584
2585  // VSRpRC_with_sub_64_in_SPILLTOVSRRC Register Class...
2586  const MCPhysReg VSRpRC_with_sub_64_in_SPILLTOVSRRC[] = {
2587    PPC::VSRp17, PPC::VSRp18, PPC::VSRp16, PPC::VSRp19, PPC::VSRp20, PPC::VSRp21, PPC::VSRp22, PPC::VSRp23, PPC::VSRp24, PPC::VSRp25, PPC::VSRp0, PPC::VSRp1, PPC::VSRp2, PPC::VSRp3, PPC::VSRp4, PPC::VSRp5, PPC::VSRp6,
2588  };
2589
2590  // VSRpRC_with_sub_64_in_SPILLTOVSRRC Bit set.
2591  const uint8_t VSRpRC_with_sub_64_in_SPILLTOVSRRCBits[] = {
2592    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03, 0xf8, 0x1f,
2593  };
2594
2595  // VSRpRC_with_sub_64_in_F4RC Register Class...
2596  const MCPhysReg VSRpRC_with_sub_64_in_F4RC[] = {
2597    PPC::VSRp0, PPC::VSRp1, PPC::VSRp2, PPC::VSRp3, PPC::VSRp4, PPC::VSRp5, PPC::VSRp6, PPC::VSRp15, PPC::VSRp14, PPC::VSRp13, PPC::VSRp12, PPC::VSRp11, PPC::VSRp10, PPC::VSRp9, PPC::VSRp8, PPC::VSRp7,
2598  };
2599
2600  // VSRpRC_with_sub_64_in_F4RC Bit set.
2601  const uint8_t VSRpRC_with_sub_64_in_F4RCBits[] = {
2602    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07,
2603  };
2604
2605  // VSRpRC_with_sub_64_in_VFRC Register Class...
2606  const MCPhysReg VSRpRC_with_sub_64_in_VFRC[] = {
2607    PPC::VSRp17, PPC::VSRp18, PPC::VSRp16, PPC::VSRp19, PPC::VSRp20, PPC::VSRp21, PPC::VSRp22, PPC::VSRp23, PPC::VSRp24, PPC::VSRp25, PPC::VSRp31, PPC::VSRp30, PPC::VSRp29, PPC::VSRp28, PPC::VSRp27, PPC::VSRp26,
2608  };
2609
2610  // VSRpRC_with_sub_64_in_VFRC Bit set.
2611  const uint8_t VSRpRC_with_sub_64_in_VFRCBits[] = {
2612    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07,
2613  };
2614
2615  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC Register Class...
2616  const MCPhysReg VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC[] = {
2617    PPC::VSRp17, PPC::VSRp18, PPC::VSRp16, PPC::VSRp19, PPC::VSRp20, PPC::VSRp21, PPC::VSRp22, PPC::VSRp23, PPC::VSRp24, PPC::VSRp25,
2618  };
2619
2620  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC Bit set.
2621  const uint8_t VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCBits[] = {
2622    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x1f,
2623  };
2624
2625  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC Register Class...
2626  const MCPhysReg VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC[] = {
2627    PPC::VSRp0, PPC::VSRp1, PPC::VSRp2, PPC::VSRp3, PPC::VSRp4, PPC::VSRp5, PPC::VSRp6,
2628  };
2629
2630  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC Bit set.
2631  const uint8_t VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCBits[] = {
2632    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03,
2633  };
2634
2635  // ACCRC Register Class...
2636  const MCPhysReg ACCRC[] = {
2637    PPC::ACC0, PPC::ACC1, PPC::ACC2, PPC::ACC3, PPC::ACC4, PPC::ACC5, PPC::ACC6, PPC::ACC7,
2638  };
2639
2640  // ACCRC Bit set.
2641  const uint8_t ACCRCBits[] = {
2642    0x00, 0xf8, 0x07,
2643  };
2644
2645  // UACCRC Register Class...
2646  const MCPhysReg UACCRC[] = {
2647    PPC::UACC0, PPC::UACC1, PPC::UACC2, PPC::UACC3, PPC::UACC4, PPC::UACC5, PPC::UACC6, PPC::UACC7,
2648  };
2649
2650  // UACCRC Bit set.
2651  const uint8_t UACCRCBits[] = {
2652    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,
2653  };
2654
2655  // WACCRC Register Class...
2656  const MCPhysReg WACCRC[] = {
2657    PPC::WACC0, PPC::WACC1, PPC::WACC2, PPC::WACC3, PPC::WACC4, PPC::WACC5, PPC::WACC6, PPC::WACC7,
2658  };
2659
2660  // WACCRC Bit set.
2661  const uint8_t WACCRCBits[] = {
2662    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,
2663  };
2664
2665  // WACC_HIRC Register Class...
2666  const MCPhysReg WACC_HIRC[] = {
2667    PPC::WACC_HI0, PPC::WACC_HI1, PPC::WACC_HI2, PPC::WACC_HI3, PPC::WACC_HI4, PPC::WACC_HI5, PPC::WACC_HI6, PPC::WACC_HI7,
2668  };
2669
2670  // WACC_HIRC Bit set.
2671  const uint8_t WACC_HIRCBits[] = {
2672    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,
2673  };
2674
2675  // ACCRC_with_sub_64_in_SPILLTOVSRRC Register Class...
2676  const MCPhysReg ACCRC_with_sub_64_in_SPILLTOVSRRC[] = {
2677    PPC::ACC0, PPC::ACC1, PPC::ACC2, PPC::ACC3,
2678  };
2679
2680  // ACCRC_with_sub_64_in_SPILLTOVSRRC Bit set.
2681  const uint8_t ACCRC_with_sub_64_in_SPILLTOVSRRCBits[] = {
2682    0x00, 0x78,
2683  };
2684
2685  // UACCRC_with_sub_64_in_SPILLTOVSRRC Register Class...
2686  const MCPhysReg UACCRC_with_sub_64_in_SPILLTOVSRRC[] = {
2687    PPC::UACC0, PPC::UACC1, PPC::UACC2, PPC::UACC3,
2688  };
2689
2690  // UACCRC_with_sub_64_in_SPILLTOVSRRC Bit set.
2691  const uint8_t UACCRC_with_sub_64_in_SPILLTOVSRRCBits[] = {
2692    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78,
2693  };
2694
2695  // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC Register Class...
2696  const MCPhysReg ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC[] = {
2697    PPC::ACC0, PPC::ACC1, PPC::ACC2,
2698  };
2699
2700  // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC Bit set.
2701  const uint8_t ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCBits[] = {
2702    0x00, 0x38,
2703  };
2704
2705  // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC Register Class...
2706  const MCPhysReg UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC[] = {
2707    PPC::UACC0, PPC::UACC1, PPC::UACC2,
2708  };
2709
2710  // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC Bit set.
2711  const uint8_t UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCBits[] = {
2712    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38,
2713  };
2714
2715  // DMRRC Register Class...
2716  const MCPhysReg DMRRC[] = {
2717    PPC::DMR0, PPC::DMR1, PPC::DMR2, PPC::DMR3, PPC::DMR4, PPC::DMR5, PPC::DMR6, PPC::DMR7,
2718  };
2719
2720  // DMRRC Bit set.
2721  const uint8_t DMRRCBits[] = {
2722    0x00, 0x00, 0x00, 0xe0, 0x1f,
2723  };
2724
2725  // DMRpRC Register Class...
2726  const MCPhysReg DMRpRC[] = {
2727    PPC::DMRp0, PPC::DMRp1, PPC::DMRp2, PPC::DMRp3,
2728  };
2729
2730  // DMRpRC Bit set.
2731  const uint8_t DMRpRCBits[] = {
2732    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01,
2733  };
2734
2735} // end anonymous namespace
2736
2737
2738#ifdef __GNUC__
2739#pragma GCC diagnostic push
2740#pragma GCC diagnostic ignored "-Woverlength-strings"
2741#endif
2742extern const char PPCRegClassStrings[] = {
2743  /* 0 */ "GPRC_and_GPRC_NOR0\0"
2744  /* 19 */ "SPERC_with_sub_32_in_GPRC_NOR0\0"
2745  /* 50 */ "G8pRC_with_sub_32_in_GPRC_NOR0\0"
2746  /* 81 */ "G8RC_and_G8RC_NOX0\0"
2747  /* 100 */ "CTRRC8\0"
2748  /* 107 */ "VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC\0"
2749  /* 151 */ "VSRpRC_with_sub_64_in_F4RC\0"
2750  /* 178 */ "F8RC\0"
2751  /* 183 */ "G8RC\0"
2752  /* 188 */ "LR8RC\0"
2753  /* 194 */ "UACCRC\0"
2754  /* 201 */ "WACCRC\0"
2755  /* 208 */ "SPERC\0"
2756  /* 214 */ "VRSAVERC\0"
2757  /* 223 */ "SPILLTOVSRRC_and_VSFRC\0"
2758  /* 246 */ "VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC\0"
2759  /* 290 */ "VSRpRC_with_sub_64_in_VFRC\0"
2760  /* 317 */ "WACC_HIRC\0"
2761  /* 327 */ "VSLRC\0"
2762  /* 333 */ "GPRC\0"
2763  /* 338 */ "CRRC\0"
2764  /* 343 */ "LRRC\0"
2765  /* 348 */ "DMRRC\0"
2766  /* 354 */ "UACCRC_with_sub_64_in_SPILLTOVSRRC\0"
2767  /* 389 */ "VSLRC_with_sub_64_in_SPILLTOVSRRC\0"
2768  /* 423 */ "VRRC_with_sub_64_in_SPILLTOVSRRC\0"
2769  /* 456 */ "VSRC_with_sub_64_in_SPILLTOVSRRC\0"
2770  /* 489 */ "VSRpRC_with_sub_64_in_SPILLTOVSRRC\0"
2771  /* 524 */ "UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC\0"
2772  /* 574 */ "CTRRC\0"
2773  /* 580 */ "VRRC\0"
2774  /* 585 */ "VSSRC\0"
2775  /* 591 */ "VSRC\0"
2776  /* 596 */ "CRBITRC\0"
2777  /* 604 */ "DMRROWRC\0"
2778  /* 613 */ "CARRYRC\0"
2779  /* 621 */ "G8pRC\0"
2780  /* 627 */ "DMRpRC\0"
2781  /* 634 */ "VSRpRC\0"
2782  /* 641 */ "DMRROWpRC\0"
2783};
2784#ifdef __GNUC__
2785#pragma GCC diagnostic pop
2786#endif
2787
2788extern const MCRegisterClass PPCMCRegisterClasses[] = {
2789  { VSSRC, VSSRCBits, 585, 64, sizeof(VSSRCBits), PPC::VSSRCRegClassID, 32, 1, true },
2790  { GPRC, GPRCBits, 333, 34, sizeof(GPRCBits), PPC::GPRCRegClassID, 32, 1, true },
2791  { GPRC_NOR0, GPRC_NOR0Bits, 9, 34, sizeof(GPRC_NOR0Bits), PPC::GPRC_NOR0RegClassID, 32, 1, true },
2792  { GPRC_and_GPRC_NOR0, GPRC_and_GPRC_NOR0Bits, 0, 33, sizeof(GPRC_and_GPRC_NOR0Bits), PPC::GPRC_and_GPRC_NOR0RegClassID, 32, 1, true },
2793  { CRBITRC, CRBITRCBits, 596, 32, sizeof(CRBITRCBits), PPC::CRBITRCRegClassID, 32, 1, true },
2794  { F4RC, F4RCBits, 146, 32, sizeof(F4RCBits), PPC::F4RCRegClassID, 32, 1, true },
2795  { CRRC, CRRCBits, 338, 8, sizeof(CRRCBits), PPC::CRRCRegClassID, 32, 1, true },
2796  { CARRYRC, CARRYRCBits, 613, 2, sizeof(CARRYRCBits), PPC::CARRYRCRegClassID, 32, -1, true },
2797  { CTRRC, CTRRCBits, 574, 1, sizeof(CTRRCBits), PPC::CTRRCRegClassID, 32, 1, false },
2798  { LRRC, LRRCBits, 343, 1, sizeof(LRRCBits), PPC::LRRCRegClassID, 32, 1, false },
2799  { VRSAVERC, VRSAVERCBits, 214, 1, sizeof(VRSAVERCBits), PPC::VRSAVERCRegClassID, 32, 1, true },
2800  { SPILLTOVSRRC, SPILLTOVSRRCBits, 376, 68, sizeof(SPILLTOVSRRCBits), PPC::SPILLTOVSRRCRegClassID, 64, 1, true },
2801  { VSFRC, VSFRCBits, 240, 64, sizeof(VSFRCBits), PPC::VSFRCRegClassID, 64, 1, true },
2802  { G8RC, G8RCBits, 183, 34, sizeof(G8RCBits), PPC::G8RCRegClassID, 64, 1, true },
2803  { G8RC_NOX0, G8RC_NOX0Bits, 90, 34, sizeof(G8RC_NOX0Bits), PPC::G8RC_NOX0RegClassID, 64, 1, true },
2804  { SPILLTOVSRRC_and_VSFRC, SPILLTOVSRRC_and_VSFRCBits, 223, 34, sizeof(SPILLTOVSRRC_and_VSFRCBits), PPC::SPILLTOVSRRC_and_VSFRCRegClassID, 64, 1, true },
2805  { G8RC_and_G8RC_NOX0, G8RC_and_G8RC_NOX0Bits, 81, 33, sizeof(G8RC_and_G8RC_NOX0Bits), PPC::G8RC_and_G8RC_NOX0RegClassID, 64, 1, true },
2806  { F8RC, F8RCBits, 178, 32, sizeof(F8RCBits), PPC::F8RCRegClassID, 64, 1, true },
2807  { SPERC, SPERCBits, 208, 32, sizeof(SPERCBits), PPC::SPERCRegClassID, 64, 1, true },
2808  { VFRC, VFRCBits, 285, 32, sizeof(VFRCBits), PPC::VFRCRegClassID, 64, 1, true },
2809  { SPERC_with_sub_32_in_GPRC_NOR0, SPERC_with_sub_32_in_GPRC_NOR0Bits, 19, 31, sizeof(SPERC_with_sub_32_in_GPRC_NOR0Bits), PPC::SPERC_with_sub_32_in_GPRC_NOR0RegClassID, 64, 1, true },
2810  { SPILLTOVSRRC_and_VFRC, SPILLTOVSRRC_and_VFRCBits, 268, 20, sizeof(SPILLTOVSRRC_and_VFRCBits), PPC::SPILLTOVSRRC_and_VFRCRegClassID, 64, 1, true },
2811  { SPILLTOVSRRC_and_F4RC, SPILLTOVSRRC_and_F4RCBits, 129, 14, sizeof(SPILLTOVSRRC_and_F4RCBits), PPC::SPILLTOVSRRC_and_F4RCRegClassID, 64, 1, true },
2812  { CTRRC8, CTRRC8Bits, 100, 1, sizeof(CTRRC8Bits), PPC::CTRRC8RegClassID, 64, 1, false },
2813  { LR8RC, LR8RCBits, 188, 1, sizeof(LR8RCBits), PPC::LR8RCRegClassID, 64, 1, false },
2814  { DMRROWRC, DMRROWRCBits, 604, 64, sizeof(DMRROWRCBits), PPC::DMRROWRCRegClassID, 128, 1, true },
2815  { VSRC, VSRCBits, 591, 64, sizeof(VSRCBits), PPC::VSRCRegClassID, 128, 1, true },
2816  { VSRC_with_sub_64_in_SPILLTOVSRRC, VSRC_with_sub_64_in_SPILLTOVSRRCBits, 456, 34, sizeof(VSRC_with_sub_64_in_SPILLTOVSRRCBits), PPC::VSRC_with_sub_64_in_SPILLTOVSRRCRegClassID, 128, 1, true },
2817  { VRRC, VRRCBits, 580, 32, sizeof(VRRCBits), PPC::VRRCRegClassID, 128, 1, true },
2818  { VSLRC, VSLRCBits, 327, 32, sizeof(VSLRCBits), PPC::VSLRCRegClassID, 128, 1, true },
2819  { VRRC_with_sub_64_in_SPILLTOVSRRC, VRRC_with_sub_64_in_SPILLTOVSRRCBits, 423, 20, sizeof(VRRC_with_sub_64_in_SPILLTOVSRRCBits), PPC::VRRC_with_sub_64_in_SPILLTOVSRRCRegClassID, 128, 1, true },
2820  { G8pRC, G8pRCBits, 621, 16, sizeof(G8pRCBits), PPC::G8pRCRegClassID, 128, 1, true },
2821  { G8pRC_with_sub_32_in_GPRC_NOR0, G8pRC_with_sub_32_in_GPRC_NOR0Bits, 50, 15, sizeof(G8pRC_with_sub_32_in_GPRC_NOR0Bits), PPC::G8pRC_with_sub_32_in_GPRC_NOR0RegClassID, 128, 1, true },
2822  { VSLRC_with_sub_64_in_SPILLTOVSRRC, VSLRC_with_sub_64_in_SPILLTOVSRRCBits, 389, 14, sizeof(VSLRC_with_sub_64_in_SPILLTOVSRRCBits), PPC::VSLRC_with_sub_64_in_SPILLTOVSRRCRegClassID, 128, 1, true },
2823  { DMRROWpRC, DMRROWpRCBits, 641, 32, sizeof(DMRROWpRCBits), PPC::DMRROWpRCRegClassID, 256, 1, true },
2824  { VSRpRC, VSRpRCBits, 634, 32, sizeof(VSRpRCBits), PPC::VSRpRCRegClassID, 256, 1, true },
2825  { VSRpRC_with_sub_64_in_SPILLTOVSRRC, VSRpRC_with_sub_64_in_SPILLTOVSRRCBits, 489, 17, sizeof(VSRpRC_with_sub_64_in_SPILLTOVSRRCBits), PPC::VSRpRC_with_sub_64_in_SPILLTOVSRRCRegClassID, 256, 1, true },
2826  { VSRpRC_with_sub_64_in_F4RC, VSRpRC_with_sub_64_in_F4RCBits, 151, 16, sizeof(VSRpRC_with_sub_64_in_F4RCBits), PPC::VSRpRC_with_sub_64_in_F4RCRegClassID, 256, 1, true },
2827  { VSRpRC_with_sub_64_in_VFRC, VSRpRC_with_sub_64_in_VFRCBits, 290, 16, sizeof(VSRpRC_with_sub_64_in_VFRCBits), PPC::VSRpRC_with_sub_64_in_VFRCRegClassID, 256, 1, true },
2828  { VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC, VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCBits, 246, 10, sizeof(VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCBits), PPC::VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCRegClassID, 256, 1, true },
2829  { VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC, VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCBits, 107, 7, sizeof(VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCBits), PPC::VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCRegClassID, 256, 1, true },
2830  { ACCRC, ACCRCBits, 195, 8, sizeof(ACCRCBits), PPC::ACCRCRegClassID, 512, 1, true },
2831  { UACCRC, UACCRCBits, 194, 8, sizeof(UACCRCBits), PPC::UACCRCRegClassID, 512, 1, true },
2832  { WACCRC, WACCRCBits, 201, 8, sizeof(WACCRCBits), PPC::WACCRCRegClassID, 512, 1, true },
2833  { WACC_HIRC, WACC_HIRCBits, 317, 8, sizeof(WACC_HIRCBits), PPC::WACC_HIRCRegClassID, 512, 1, true },
2834  { ACCRC_with_sub_64_in_SPILLTOVSRRC, ACCRC_with_sub_64_in_SPILLTOVSRRCBits, 355, 4, sizeof(ACCRC_with_sub_64_in_SPILLTOVSRRCBits), PPC::ACCRC_with_sub_64_in_SPILLTOVSRRCRegClassID, 512, 1, true },
2835  { UACCRC_with_sub_64_in_SPILLTOVSRRC, UACCRC_with_sub_64_in_SPILLTOVSRRCBits, 354, 4, sizeof(UACCRC_with_sub_64_in_SPILLTOVSRRCBits), PPC::UACCRC_with_sub_64_in_SPILLTOVSRRCRegClassID, 512, 1, true },
2836  { ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC, ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCBits, 525, 3, sizeof(ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCBits), PPC::ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCRegClassID, 512, 1, true },
2837  { UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC, UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCBits, 524, 3, sizeof(UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCBits), PPC::UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCRegClassID, 512, 1, true },
2838  { DMRRC, DMRRCBits, 348, 8, sizeof(DMRRCBits), PPC::DMRRCRegClassID, 1024, 1, true },
2839  { DMRpRC, DMRpRCBits, 627, 4, sizeof(DMRpRCBits), PPC::DMRpRCRegClassID, 2048, 1, true },
2840};
2841
2842// PPC Dwarf<->LLVM register mappings.
2843extern const MCRegisterInfo::DwarfLLVMRegPair PPCDwarfFlavour0Dwarf2L[] = {
2844  { 0U, PPC::X0 },
2845  { 1U, PPC::X1 },
2846  { 2U, PPC::X2 },
2847  { 3U, PPC::X3 },
2848  { 4U, PPC::X4 },
2849  { 5U, PPC::X5 },
2850  { 6U, PPC::X6 },
2851  { 7U, PPC::X7 },
2852  { 8U, PPC::X8 },
2853  { 9U, PPC::X9 },
2854  { 10U, PPC::X10 },
2855  { 11U, PPC::X11 },
2856  { 12U, PPC::X12 },
2857  { 13U, PPC::X13 },
2858  { 14U, PPC::X14 },
2859  { 15U, PPC::X15 },
2860  { 16U, PPC::X16 },
2861  { 17U, PPC::X17 },
2862  { 18U, PPC::X18 },
2863  { 19U, PPC::X19 },
2864  { 20U, PPC::X20 },
2865  { 21U, PPC::X21 },
2866  { 22U, PPC::X22 },
2867  { 23U, PPC::X23 },
2868  { 24U, PPC::X24 },
2869  { 25U, PPC::X25 },
2870  { 26U, PPC::X26 },
2871  { 27U, PPC::X27 },
2872  { 28U, PPC::X28 },
2873  { 29U, PPC::X29 },
2874  { 30U, PPC::X30 },
2875  { 31U, PPC::X31 },
2876  { 32U, PPC::F0 },
2877  { 33U, PPC::F1 },
2878  { 34U, PPC::F2 },
2879  { 35U, PPC::F3 },
2880  { 36U, PPC::F4 },
2881  { 37U, PPC::F5 },
2882  { 38U, PPC::F6 },
2883  { 39U, PPC::F7 },
2884  { 40U, PPC::F8 },
2885  { 41U, PPC::F9 },
2886  { 42U, PPC::F10 },
2887  { 43U, PPC::F11 },
2888  { 44U, PPC::F12 },
2889  { 45U, PPC::F13 },
2890  { 46U, PPC::F14 },
2891  { 47U, PPC::F15 },
2892  { 48U, PPC::F16 },
2893  { 49U, PPC::F17 },
2894  { 50U, PPC::F18 },
2895  { 51U, PPC::F19 },
2896  { 52U, PPC::F20 },
2897  { 53U, PPC::F21 },
2898  { 54U, PPC::F22 },
2899  { 55U, PPC::F23 },
2900  { 56U, PPC::F24 },
2901  { 57U, PPC::F25 },
2902  { 58U, PPC::F26 },
2903  { 59U, PPC::F27 },
2904  { 60U, PPC::F28 },
2905  { 61U, PPC::F29 },
2906  { 62U, PPC::F30 },
2907  { 63U, PPC::F31 },
2908  { 65U, PPC::LR8 },
2909  { 66U, PPC::CTR8 },
2910  { 68U, PPC::CR0 },
2911  { 69U, PPC::CR1 },
2912  { 70U, PPC::CR2 },
2913  { 71U, PPC::CR3 },
2914  { 72U, PPC::CR4 },
2915  { 73U, PPC::CR5 },
2916  { 74U, PPC::CR6 },
2917  { 75U, PPC::CR7 },
2918  { 76U, PPC::XER },
2919  { 77U, PPC::VF0 },
2920  { 78U, PPC::VF1 },
2921  { 79U, PPC::VF2 },
2922  { 80U, PPC::VF3 },
2923  { 81U, PPC::VF4 },
2924  { 82U, PPC::VF5 },
2925  { 83U, PPC::VF6 },
2926  { 84U, PPC::VF7 },
2927  { 85U, PPC::VF8 },
2928  { 86U, PPC::VF9 },
2929  { 87U, PPC::VF10 },
2930  { 88U, PPC::VF11 },
2931  { 89U, PPC::VF12 },
2932  { 90U, PPC::VF13 },
2933  { 91U, PPC::VF14 },
2934  { 92U, PPC::VF15 },
2935  { 93U, PPC::VF16 },
2936  { 94U, PPC::VF17 },
2937  { 95U, PPC::VF18 },
2938  { 96U, PPC::VF19 },
2939  { 97U, PPC::VF20 },
2940  { 98U, PPC::VF21 },
2941  { 99U, PPC::VF22 },
2942  { 100U, PPC::VF23 },
2943  { 101U, PPC::VF24 },
2944  { 102U, PPC::VF25 },
2945  { 103U, PPC::VF26 },
2946  { 104U, PPC::VF27 },
2947  { 105U, PPC::VF28 },
2948  { 106U, PPC::VF29 },
2949  { 107U, PPC::VF30 },
2950  { 108U, PPC::VF31 },
2951  { 109U, PPC::VRSAVE },
2952  { 612U, PPC::SPEFSCR },
2953  { 1200U, PPC::S0 },
2954  { 1201U, PPC::S1 },
2955  { 1202U, PPC::S2 },
2956  { 1203U, PPC::S3 },
2957  { 1204U, PPC::S4 },
2958  { 1205U, PPC::S5 },
2959  { 1206U, PPC::S6 },
2960  { 1207U, PPC::S7 },
2961  { 1208U, PPC::S8 },
2962  { 1209U, PPC::S9 },
2963  { 1210U, PPC::S10 },
2964  { 1211U, PPC::S11 },
2965  { 1212U, PPC::S12 },
2966  { 1213U, PPC::S13 },
2967  { 1214U, PPC::S14 },
2968  { 1215U, PPC::S15 },
2969  { 1216U, PPC::S16 },
2970  { 1217U, PPC::S17 },
2971  { 1218U, PPC::S18 },
2972  { 1219U, PPC::S19 },
2973  { 1220U, PPC::S20 },
2974  { 1221U, PPC::S21 },
2975  { 1222U, PPC::S22 },
2976  { 1223U, PPC::S23 },
2977  { 1224U, PPC::S24 },
2978  { 1225U, PPC::S25 },
2979  { 1226U, PPC::S26 },
2980  { 1227U, PPC::S27 },
2981  { 1228U, PPC::S28 },
2982  { 1229U, PPC::S29 },
2983  { 1230U, PPC::S30 },
2984  { 1231U, PPC::S31 },
2985};
2986extern const unsigned PPCDwarfFlavour0Dwarf2LSize = std::size(PPCDwarfFlavour0Dwarf2L);
2987
2988extern const MCRegisterInfo::DwarfLLVMRegPair PPCDwarfFlavour1Dwarf2L[] = {
2989  { 0U, PPC::R0 },
2990  { 1U, PPC::R1 },
2991  { 2U, PPC::R2 },
2992  { 3U, PPC::R3 },
2993  { 4U, PPC::R4 },
2994  { 5U, PPC::R5 },
2995  { 6U, PPC::R6 },
2996  { 7U, PPC::R7 },
2997  { 8U, PPC::R8 },
2998  { 9U, PPC::R9 },
2999  { 10U, PPC::R10 },
3000  { 11U, PPC::R11 },
3001  { 12U, PPC::R12 },
3002  { 13U, PPC::R13 },
3003  { 14U, PPC::R14 },
3004  { 15U, PPC::R15 },
3005  { 16U, PPC::R16 },
3006  { 17U, PPC::R17 },
3007  { 18U, PPC::R18 },
3008  { 19U, PPC::R19 },
3009  { 20U, PPC::R20 },
3010  { 21U, PPC::R21 },
3011  { 22U, PPC::R22 },
3012  { 23U, PPC::R23 },
3013  { 24U, PPC::R24 },
3014  { 25U, PPC::R25 },
3015  { 26U, PPC::R26 },
3016  { 27U, PPC::R27 },
3017  { 28U, PPC::R28 },
3018  { 29U, PPC::R29 },
3019  { 30U, PPC::R30 },
3020  { 31U, PPC::R31 },
3021  { 32U, PPC::F0 },
3022  { 33U, PPC::F1 },
3023  { 34U, PPC::F2 },
3024  { 35U, PPC::F3 },
3025  { 36U, PPC::F4 },
3026  { 37U, PPC::F5 },
3027  { 38U, PPC::F6 },
3028  { 39U, PPC::F7 },
3029  { 40U, PPC::F8 },
3030  { 41U, PPC::F9 },
3031  { 42U, PPC::F10 },
3032  { 43U, PPC::F11 },
3033  { 44U, PPC::F12 },
3034  { 45U, PPC::F13 },
3035  { 46U, PPC::F14 },
3036  { 47U, PPC::F15 },
3037  { 48U, PPC::F16 },
3038  { 49U, PPC::F17 },
3039  { 50U, PPC::F18 },
3040  { 51U, PPC::F19 },
3041  { 52U, PPC::F20 },
3042  { 53U, PPC::F21 },
3043  { 54U, PPC::F22 },
3044  { 55U, PPC::F23 },
3045  { 56U, PPC::F24 },
3046  { 57U, PPC::F25 },
3047  { 58U, PPC::F26 },
3048  { 59U, PPC::F27 },
3049  { 60U, PPC::F28 },
3050  { 61U, PPC::F29 },
3051  { 62U, PPC::F30 },
3052  { 63U, PPC::F31 },
3053  { 65U, PPC::LR },
3054  { 66U, PPC::CTR },
3055  { 68U, PPC::CR0 },
3056  { 69U, PPC::CR1 },
3057  { 70U, PPC::CR2 },
3058  { 71U, PPC::CR3 },
3059  { 72U, PPC::CR4 },
3060  { 73U, PPC::CR5 },
3061  { 74U, PPC::CR6 },
3062  { 75U, PPC::CR7 },
3063  { 77U, PPC::VF0 },
3064  { 78U, PPC::VF1 },
3065  { 79U, PPC::VF2 },
3066  { 80U, PPC::VF3 },
3067  { 81U, PPC::VF4 },
3068  { 82U, PPC::VF5 },
3069  { 83U, PPC::VF6 },
3070  { 84U, PPC::VF7 },
3071  { 85U, PPC::VF8 },
3072  { 86U, PPC::VF9 },
3073  { 87U, PPC::VF10 },
3074  { 88U, PPC::VF11 },
3075  { 89U, PPC::VF12 },
3076  { 90U, PPC::VF13 },
3077  { 91U, PPC::VF14 },
3078  { 92U, PPC::VF15 },
3079  { 93U, PPC::VF16 },
3080  { 94U, PPC::VF17 },
3081  { 95U, PPC::VF18 },
3082  { 96U, PPC::VF19 },
3083  { 97U, PPC::VF20 },
3084  { 98U, PPC::VF21 },
3085  { 99U, PPC::VF22 },
3086  { 100U, PPC::VF23 },
3087  { 101U, PPC::VF24 },
3088  { 102U, PPC::VF25 },
3089  { 103U, PPC::VF26 },
3090  { 104U, PPC::VF27 },
3091  { 105U, PPC::VF28 },
3092  { 106U, PPC::VF29 },
3093  { 107U, PPC::VF30 },
3094  { 108U, PPC::VF31 },
3095  { 112U, PPC::SPEFSCR },
3096  { 1200U, PPC::S0 },
3097  { 1201U, PPC::S1 },
3098  { 1202U, PPC::S2 },
3099  { 1203U, PPC::S3 },
3100  { 1204U, PPC::S4 },
3101  { 1205U, PPC::S5 },
3102  { 1206U, PPC::S6 },
3103  { 1207U, PPC::S7 },
3104  { 1208U, PPC::S8 },
3105  { 1209U, PPC::S9 },
3106  { 1210U, PPC::S10 },
3107  { 1211U, PPC::S11 },
3108  { 1212U, PPC::S12 },
3109  { 1213U, PPC::S13 },
3110  { 1214U, PPC::S14 },
3111  { 1215U, PPC::S15 },
3112  { 1216U, PPC::S16 },
3113  { 1217U, PPC::S17 },
3114  { 1218U, PPC::S18 },
3115  { 1219U, PPC::S19 },
3116  { 1220U, PPC::S20 },
3117  { 1221U, PPC::S21 },
3118  { 1222U, PPC::S22 },
3119  { 1223U, PPC::S23 },
3120  { 1224U, PPC::S24 },
3121  { 1225U, PPC::S25 },
3122  { 1226U, PPC::S26 },
3123  { 1227U, PPC::S27 },
3124  { 1228U, PPC::S28 },
3125  { 1229U, PPC::S29 },
3126  { 1230U, PPC::S30 },
3127  { 1231U, PPC::S31 },
3128};
3129extern const unsigned PPCDwarfFlavour1Dwarf2LSize = std::size(PPCDwarfFlavour1Dwarf2L);
3130
3131extern const MCRegisterInfo::DwarfLLVMRegPair PPCEHFlavour0Dwarf2L[] = {
3132  { 0U, PPC::X0 },
3133  { 1U, PPC::X1 },
3134  { 2U, PPC::X2 },
3135  { 3U, PPC::X3 },
3136  { 4U, PPC::X4 },
3137  { 5U, PPC::X5 },
3138  { 6U, PPC::X6 },
3139  { 7U, PPC::X7 },
3140  { 8U, PPC::X8 },
3141  { 9U, PPC::X9 },
3142  { 10U, PPC::X10 },
3143  { 11U, PPC::X11 },
3144  { 12U, PPC::X12 },
3145  { 13U, PPC::X13 },
3146  { 14U, PPC::X14 },
3147  { 15U, PPC::X15 },
3148  { 16U, PPC::X16 },
3149  { 17U, PPC::X17 },
3150  { 18U, PPC::X18 },
3151  { 19U, PPC::X19 },
3152  { 20U, PPC::X20 },
3153  { 21U, PPC::X21 },
3154  { 22U, PPC::X22 },
3155  { 23U, PPC::X23 },
3156  { 24U, PPC::X24 },
3157  { 25U, PPC::X25 },
3158  { 26U, PPC::X26 },
3159  { 27U, PPC::X27 },
3160  { 28U, PPC::X28 },
3161  { 29U, PPC::X29 },
3162  { 30U, PPC::X30 },
3163  { 31U, PPC::X31 },
3164  { 32U, PPC::F0 },
3165  { 33U, PPC::F1 },
3166  { 34U, PPC::F2 },
3167  { 35U, PPC::F3 },
3168  { 36U, PPC::F4 },
3169  { 37U, PPC::F5 },
3170  { 38U, PPC::F6 },
3171  { 39U, PPC::F7 },
3172  { 40U, PPC::F8 },
3173  { 41U, PPC::F9 },
3174  { 42U, PPC::F10 },
3175  { 43U, PPC::F11 },
3176  { 44U, PPC::F12 },
3177  { 45U, PPC::F13 },
3178  { 46U, PPC::F14 },
3179  { 47U, PPC::F15 },
3180  { 48U, PPC::F16 },
3181  { 49U, PPC::F17 },
3182  { 50U, PPC::F18 },
3183  { 51U, PPC::F19 },
3184  { 52U, PPC::F20 },
3185  { 53U, PPC::F21 },
3186  { 54U, PPC::F22 },
3187  { 55U, PPC::F23 },
3188  { 56U, PPC::F24 },
3189  { 57U, PPC::F25 },
3190  { 58U, PPC::F26 },
3191  { 59U, PPC::F27 },
3192  { 60U, PPC::F28 },
3193  { 61U, PPC::F29 },
3194  { 62U, PPC::F30 },
3195  { 63U, PPC::F31 },
3196  { 65U, PPC::LR8 },
3197  { 66U, PPC::CTR8 },
3198  { 68U, PPC::CR0 },
3199  { 69U, PPC::CR1 },
3200  { 70U, PPC::CR2 },
3201  { 71U, PPC::CR3 },
3202  { 72U, PPC::CR4 },
3203  { 73U, PPC::CR5 },
3204  { 74U, PPC::CR6 },
3205  { 75U, PPC::CR7 },
3206  { 76U, PPC::XER },
3207  { 77U, PPC::VF0 },
3208  { 78U, PPC::VF1 },
3209  { 79U, PPC::VF2 },
3210  { 80U, PPC::VF3 },
3211  { 81U, PPC::VF4 },
3212  { 82U, PPC::VF5 },
3213  { 83U, PPC::VF6 },
3214  { 84U, PPC::VF7 },
3215  { 85U, PPC::VF8 },
3216  { 86U, PPC::VF9 },
3217  { 87U, PPC::VF10 },
3218  { 88U, PPC::VF11 },
3219  { 89U, PPC::VF12 },
3220  { 90U, PPC::VF13 },
3221  { 91U, PPC::VF14 },
3222  { 92U, PPC::VF15 },
3223  { 93U, PPC::VF16 },
3224  { 94U, PPC::VF17 },
3225  { 95U, PPC::VF18 },
3226  { 96U, PPC::VF19 },
3227  { 97U, PPC::VF20 },
3228  { 98U, PPC::VF21 },
3229  { 99U, PPC::VF22 },
3230  { 100U, PPC::VF23 },
3231  { 101U, PPC::VF24 },
3232  { 102U, PPC::VF25 },
3233  { 103U, PPC::VF26 },
3234  { 104U, PPC::VF27 },
3235  { 105U, PPC::VF28 },
3236  { 106U, PPC::VF29 },
3237  { 107U, PPC::VF30 },
3238  { 108U, PPC::VF31 },
3239  { 109U, PPC::VRSAVE },
3240  { 612U, PPC::SPEFSCR },
3241  { 1200U, PPC::S0 },
3242  { 1201U, PPC::S1 },
3243  { 1202U, PPC::S2 },
3244  { 1203U, PPC::S3 },
3245  { 1204U, PPC::S4 },
3246  { 1205U, PPC::S5 },
3247  { 1206U, PPC::S6 },
3248  { 1207U, PPC::S7 },
3249  { 1208U, PPC::S8 },
3250  { 1209U, PPC::S9 },
3251  { 1210U, PPC::S10 },
3252  { 1211U, PPC::S11 },
3253  { 1212U, PPC::S12 },
3254  { 1213U, PPC::S13 },
3255  { 1214U, PPC::S14 },
3256  { 1215U, PPC::S15 },
3257  { 1216U, PPC::S16 },
3258  { 1217U, PPC::S17 },
3259  { 1218U, PPC::S18 },
3260  { 1219U, PPC::S19 },
3261  { 1220U, PPC::S20 },
3262  { 1221U, PPC::S21 },
3263  { 1222U, PPC::S22 },
3264  { 1223U, PPC::S23 },
3265  { 1224U, PPC::S24 },
3266  { 1225U, PPC::S25 },
3267  { 1226U, PPC::S26 },
3268  { 1227U, PPC::S27 },
3269  { 1228U, PPC::S28 },
3270  { 1229U, PPC::S29 },
3271  { 1230U, PPC::S30 },
3272  { 1231U, PPC::S31 },
3273};
3274extern const unsigned PPCEHFlavour0Dwarf2LSize = std::size(PPCEHFlavour0Dwarf2L);
3275
3276extern const MCRegisterInfo::DwarfLLVMRegPair PPCEHFlavour1Dwarf2L[] = {
3277  { 0U, PPC::R0 },
3278  { 1U, PPC::R1 },
3279  { 2U, PPC::R2 },
3280  { 3U, PPC::R3 },
3281  { 4U, PPC::R4 },
3282  { 5U, PPC::R5 },
3283  { 6U, PPC::R6 },
3284  { 7U, PPC::R7 },
3285  { 8U, PPC::R8 },
3286  { 9U, PPC::R9 },
3287  { 10U, PPC::R10 },
3288  { 11U, PPC::R11 },
3289  { 12U, PPC::R12 },
3290  { 13U, PPC::R13 },
3291  { 14U, PPC::R14 },
3292  { 15U, PPC::R15 },
3293  { 16U, PPC::R16 },
3294  { 17U, PPC::R17 },
3295  { 18U, PPC::R18 },
3296  { 19U, PPC::R19 },
3297  { 20U, PPC::R20 },
3298  { 21U, PPC::R21 },
3299  { 22U, PPC::R22 },
3300  { 23U, PPC::R23 },
3301  { 24U, PPC::R24 },
3302  { 25U, PPC::R25 },
3303  { 26U, PPC::R26 },
3304  { 27U, PPC::R27 },
3305  { 28U, PPC::R28 },
3306  { 29U, PPC::R29 },
3307  { 30U, PPC::R30 },
3308  { 31U, PPC::R31 },
3309  { 32U, PPC::F0 },
3310  { 33U, PPC::F1 },
3311  { 34U, PPC::F2 },
3312  { 35U, PPC::F3 },
3313  { 36U, PPC::F4 },
3314  { 37U, PPC::F5 },
3315  { 38U, PPC::F6 },
3316  { 39U, PPC::F7 },
3317  { 40U, PPC::F8 },
3318  { 41U, PPC::F9 },
3319  { 42U, PPC::F10 },
3320  { 43U, PPC::F11 },
3321  { 44U, PPC::F12 },
3322  { 45U, PPC::F13 },
3323  { 46U, PPC::F14 },
3324  { 47U, PPC::F15 },
3325  { 48U, PPC::F16 },
3326  { 49U, PPC::F17 },
3327  { 50U, PPC::F18 },
3328  { 51U, PPC::F19 },
3329  { 52U, PPC::F20 },
3330  { 53U, PPC::F21 },
3331  { 54U, PPC::F22 },
3332  { 55U, PPC::F23 },
3333  { 56U, PPC::F24 },
3334  { 57U, PPC::F25 },
3335  { 58U, PPC::F26 },
3336  { 59U, PPC::F27 },
3337  { 60U, PPC::F28 },
3338  { 61U, PPC::F29 },
3339  { 62U, PPC::F30 },
3340  { 63U, PPC::F31 },
3341  { 65U, PPC::LR },
3342  { 66U, PPC::CTR },
3343  { 68U, PPC::CR0 },
3344  { 69U, PPC::CR1 },
3345  { 70U, PPC::CR2 },
3346  { 71U, PPC::CR3 },
3347  { 72U, PPC::CR4 },
3348  { 73U, PPC::CR5 },
3349  { 74U, PPC::CR6 },
3350  { 75U, PPC::CR7 },
3351  { 77U, PPC::VF0 },
3352  { 78U, PPC::VF1 },
3353  { 79U, PPC::VF2 },
3354  { 80U, PPC::VF3 },
3355  { 81U, PPC::VF4 },
3356  { 82U, PPC::VF5 },
3357  { 83U, PPC::VF6 },
3358  { 84U, PPC::VF7 },
3359  { 85U, PPC::VF8 },
3360  { 86U, PPC::VF9 },
3361  { 87U, PPC::VF10 },
3362  { 88U, PPC::VF11 },
3363  { 89U, PPC::VF12 },
3364  { 90U, PPC::VF13 },
3365  { 91U, PPC::VF14 },
3366  { 92U, PPC::VF15 },
3367  { 93U, PPC::VF16 },
3368  { 94U, PPC::VF17 },
3369  { 95U, PPC::VF18 },
3370  { 96U, PPC::VF19 },
3371  { 97U, PPC::VF20 },
3372  { 98U, PPC::VF21 },
3373  { 99U, PPC::VF22 },
3374  { 100U, PPC::VF23 },
3375  { 101U, PPC::VF24 },
3376  { 102U, PPC::VF25 },
3377  { 103U, PPC::VF26 },
3378  { 104U, PPC::VF27 },
3379  { 105U, PPC::VF28 },
3380  { 106U, PPC::VF29 },
3381  { 107U, PPC::VF30 },
3382  { 108U, PPC::VF31 },
3383  { 112U, PPC::SPEFSCR },
3384  { 1200U, PPC::S0 },
3385  { 1201U, PPC::S1 },
3386  { 1202U, PPC::S2 },
3387  { 1203U, PPC::S3 },
3388  { 1204U, PPC::S4 },
3389  { 1205U, PPC::S5 },
3390  { 1206U, PPC::S6 },
3391  { 1207U, PPC::S7 },
3392  { 1208U, PPC::S8 },
3393  { 1209U, PPC::S9 },
3394  { 1210U, PPC::S10 },
3395  { 1211U, PPC::S11 },
3396  { 1212U, PPC::S12 },
3397  { 1213U, PPC::S13 },
3398  { 1214U, PPC::S14 },
3399  { 1215U, PPC::S15 },
3400  { 1216U, PPC::S16 },
3401  { 1217U, PPC::S17 },
3402  { 1218U, PPC::S18 },
3403  { 1219U, PPC::S19 },
3404  { 1220U, PPC::S20 },
3405  { 1221U, PPC::S21 },
3406  { 1222U, PPC::S22 },
3407  { 1223U, PPC::S23 },
3408  { 1224U, PPC::S24 },
3409  { 1225U, PPC::S25 },
3410  { 1226U, PPC::S26 },
3411  { 1227U, PPC::S27 },
3412  { 1228U, PPC::S28 },
3413  { 1229U, PPC::S29 },
3414  { 1230U, PPC::S30 },
3415  { 1231U, PPC::S31 },
3416};
3417extern const unsigned PPCEHFlavour1Dwarf2LSize = std::size(PPCEHFlavour1Dwarf2L);
3418
3419extern const MCRegisterInfo::DwarfLLVMRegPair PPCDwarfFlavour0L2Dwarf[] = {
3420  { PPC::CARRY, 76U },
3421  { PPC::CTR, -2U },
3422  { PPC::LR, -2U },
3423  { PPC::SPEFSCR, 612U },
3424  { PPC::VRSAVE, 109U },
3425  { PPC::XER, 76U },
3426  { PPC::ZERO, -2U },
3427  { PPC::CR0, 68U },
3428  { PPC::CR1, 69U },
3429  { PPC::CR2, 70U },
3430  { PPC::CR3, 71U },
3431  { PPC::CR4, 72U },
3432  { PPC::CR5, 73U },
3433  { PPC::CR6, 74U },
3434  { PPC::CR7, 75U },
3435  { PPC::CTR8, 66U },
3436  { PPC::F0, 32U },
3437  { PPC::F1, 33U },
3438  { PPC::F2, 34U },
3439  { PPC::F3, 35U },
3440  { PPC::F4, 36U },
3441  { PPC::F5, 37U },
3442  { PPC::F6, 38U },
3443  { PPC::F7, 39U },
3444  { PPC::F8, 40U },
3445  { PPC::F9, 41U },
3446  { PPC::F10, 42U },
3447  { PPC::F11, 43U },
3448  { PPC::F12, 44U },
3449  { PPC::F13, 45U },
3450  { PPC::F14, 46U },
3451  { PPC::F15, 47U },
3452  { PPC::F16, 48U },
3453  { PPC::F17, 49U },
3454  { PPC::F18, 50U },
3455  { PPC::F19, 51U },
3456  { PPC::F20, 52U },
3457  { PPC::F21, 53U },
3458  { PPC::F22, 54U },
3459  { PPC::F23, 55U },
3460  { PPC::F24, 56U },
3461  { PPC::F25, 57U },
3462  { PPC::F26, 58U },
3463  { PPC::F27, 59U },
3464  { PPC::F28, 60U },
3465  { PPC::F29, 61U },
3466  { PPC::F30, 62U },
3467  { PPC::F31, 63U },
3468  { PPC::LR8, 65U },
3469  { PPC::R0, -2U },
3470  { PPC::R1, -2U },
3471  { PPC::R2, -2U },
3472  { PPC::R3, -2U },
3473  { PPC::R4, -2U },
3474  { PPC::R5, -2U },
3475  { PPC::R6, -2U },
3476  { PPC::R7, -2U },
3477  { PPC::R8, -2U },
3478  { PPC::R9, -2U },
3479  { PPC::R10, -2U },
3480  { PPC::R11, -2U },
3481  { PPC::R12, -2U },
3482  { PPC::R13, -2U },
3483  { PPC::R14, -2U },
3484  { PPC::R15, -2U },
3485  { PPC::R16, -2U },
3486  { PPC::R17, -2U },
3487  { PPC::R18, -2U },
3488  { PPC::R19, -2U },
3489  { PPC::R20, -2U },
3490  { PPC::R21, -2U },
3491  { PPC::R22, -2U },
3492  { PPC::R23, -2U },
3493  { PPC::R24, -2U },
3494  { PPC::R25, -2U },
3495  { PPC::R26, -2U },
3496  { PPC::R27, -2U },
3497  { PPC::R28, -2U },
3498  { PPC::R29, -2U },
3499  { PPC::R30, -2U },
3500  { PPC::R31, -2U },
3501  { PPC::S0, 1200U },
3502  { PPC::S1, 1201U },
3503  { PPC::S2, 1202U },
3504  { PPC::S3, 1203U },
3505  { PPC::S4, 1204U },
3506  { PPC::S5, 1205U },
3507  { PPC::S6, 1206U },
3508  { PPC::S7, 1207U },
3509  { PPC::S8, 1208U },
3510  { PPC::S9, 1209U },
3511  { PPC::S10, 1210U },
3512  { PPC::S11, 1211U },
3513  { PPC::S12, 1212U },
3514  { PPC::S13, 1213U },
3515  { PPC::S14, 1214U },
3516  { PPC::S15, 1215U },
3517  { PPC::S16, 1216U },
3518  { PPC::S17, 1217U },
3519  { PPC::S18, 1218U },
3520  { PPC::S19, 1219U },
3521  { PPC::S20, 1220U },
3522  { PPC::S21, 1221U },
3523  { PPC::S22, 1222U },
3524  { PPC::S23, 1223U },
3525  { PPC::S24, 1224U },
3526  { PPC::S25, 1225U },
3527  { PPC::S26, 1226U },
3528  { PPC::S27, 1227U },
3529  { PPC::S28, 1228U },
3530  { PPC::S29, 1229U },
3531  { PPC::S30, 1230U },
3532  { PPC::S31, 1231U },
3533  { PPC::V0, 77U },
3534  { PPC::V1, 78U },
3535  { PPC::V2, 79U },
3536  { PPC::V3, 80U },
3537  { PPC::V4, 81U },
3538  { PPC::V5, 82U },
3539  { PPC::V6, 83U },
3540  { PPC::V7, 84U },
3541  { PPC::V8, 85U },
3542  { PPC::V9, 86U },
3543  { PPC::V10, 87U },
3544  { PPC::V11, 88U },
3545  { PPC::V12, 89U },
3546  { PPC::V13, 90U },
3547  { PPC::V14, 91U },
3548  { PPC::V15, 92U },
3549  { PPC::V16, 93U },
3550  { PPC::V17, 94U },
3551  { PPC::V18, 95U },
3552  { PPC::V19, 96U },
3553  { PPC::V20, 97U },
3554  { PPC::V21, 98U },
3555  { PPC::V22, 99U },
3556  { PPC::V23, 100U },
3557  { PPC::V24, 101U },
3558  { PPC::V25, 102U },
3559  { PPC::V26, 103U },
3560  { PPC::V27, 104U },
3561  { PPC::V28, 105U },
3562  { PPC::V29, 106U },
3563  { PPC::V30, 107U },
3564  { PPC::V31, 108U },
3565  { PPC::VF0, 77U },
3566  { PPC::VF1, 78U },
3567  { PPC::VF2, 79U },
3568  { PPC::VF3, 80U },
3569  { PPC::VF4, 81U },
3570  { PPC::VF5, 82U },
3571  { PPC::VF6, 83U },
3572  { PPC::VF7, 84U },
3573  { PPC::VF8, 85U },
3574  { PPC::VF9, 86U },
3575  { PPC::VF10, 87U },
3576  { PPC::VF11, 88U },
3577  { PPC::VF12, 89U },
3578  { PPC::VF13, 90U },
3579  { PPC::VF14, 91U },
3580  { PPC::VF15, 92U },
3581  { PPC::VF16, 93U },
3582  { PPC::VF17, 94U },
3583  { PPC::VF18, 95U },
3584  { PPC::VF19, 96U },
3585  { PPC::VF20, 97U },
3586  { PPC::VF21, 98U },
3587  { PPC::VF22, 99U },
3588  { PPC::VF23, 100U },
3589  { PPC::VF24, 101U },
3590  { PPC::VF25, 102U },
3591  { PPC::VF26, 103U },
3592  { PPC::VF27, 104U },
3593  { PPC::VF28, 105U },
3594  { PPC::VF29, 106U },
3595  { PPC::VF30, 107U },
3596  { PPC::VF31, 108U },
3597  { PPC::VSL0, 32U },
3598  { PPC::VSL1, 33U },
3599  { PPC::VSL2, 34U },
3600  { PPC::VSL3, 35U },
3601  { PPC::VSL4, 36U },
3602  { PPC::VSL5, 37U },
3603  { PPC::VSL6, 38U },
3604  { PPC::VSL7, 39U },
3605  { PPC::VSL8, 40U },
3606  { PPC::VSL9, 41U },
3607  { PPC::VSL10, 42U },
3608  { PPC::VSL11, 43U },
3609  { PPC::VSL12, 44U },
3610  { PPC::VSL13, 45U },
3611  { PPC::VSL14, 46U },
3612  { PPC::VSL15, 47U },
3613  { PPC::VSL16, 48U },
3614  { PPC::VSL17, 49U },
3615  { PPC::VSL18, 50U },
3616  { PPC::VSL19, 51U },
3617  { PPC::VSL20, 52U },
3618  { PPC::VSL21, 53U },
3619  { PPC::VSL22, 54U },
3620  { PPC::VSL23, 55U },
3621  { PPC::VSL24, 56U },
3622  { PPC::VSL25, 57U },
3623  { PPC::VSL26, 58U },
3624  { PPC::VSL27, 59U },
3625  { PPC::VSL28, 60U },
3626  { PPC::VSL29, 61U },
3627  { PPC::VSL30, 62U },
3628  { PPC::VSL31, 63U },
3629  { PPC::X0, 0U },
3630  { PPC::X1, 1U },
3631  { PPC::X2, 2U },
3632  { PPC::X3, 3U },
3633  { PPC::X4, 4U },
3634  { PPC::X5, 5U },
3635  { PPC::X6, 6U },
3636  { PPC::X7, 7U },
3637  { PPC::X8, 8U },
3638  { PPC::X9, 9U },
3639  { PPC::X10, 10U },
3640  { PPC::X11, 11U },
3641  { PPC::X12, 12U },
3642  { PPC::X13, 13U },
3643  { PPC::X14, 14U },
3644  { PPC::X15, 15U },
3645  { PPC::X16, 16U },
3646  { PPC::X17, 17U },
3647  { PPC::X18, 18U },
3648  { PPC::X19, 19U },
3649  { PPC::X20, 20U },
3650  { PPC::X21, 21U },
3651  { PPC::X22, 22U },
3652  { PPC::X23, 23U },
3653  { PPC::X24, 24U },
3654  { PPC::X25, 25U },
3655  { PPC::X26, 26U },
3656  { PPC::X27, 27U },
3657  { PPC::X28, 28U },
3658  { PPC::X29, 29U },
3659  { PPC::X30, 30U },
3660  { PPC::X31, 31U },
3661  { PPC::ZERO8, 0U },
3662};
3663extern const unsigned PPCDwarfFlavour0L2DwarfSize = std::size(PPCDwarfFlavour0L2Dwarf);
3664
3665extern const MCRegisterInfo::DwarfLLVMRegPair PPCDwarfFlavour1L2Dwarf[] = {
3666  { PPC::CTR, 66U },
3667  { PPC::LR, 65U },
3668  { PPC::SPEFSCR, 112U },
3669  { PPC::ZERO, 0U },
3670  { PPC::CR0, 68U },
3671  { PPC::CR1, 69U },
3672  { PPC::CR2, 70U },
3673  { PPC::CR3, 71U },
3674  { PPC::CR4, 72U },
3675  { PPC::CR5, 73U },
3676  { PPC::CR6, 74U },
3677  { PPC::CR7, 75U },
3678  { PPC::CTR8, -2U },
3679  { PPC::F0, 32U },
3680  { PPC::F1, 33U },
3681  { PPC::F2, 34U },
3682  { PPC::F3, 35U },
3683  { PPC::F4, 36U },
3684  { PPC::F5, 37U },
3685  { PPC::F6, 38U },
3686  { PPC::F7, 39U },
3687  { PPC::F8, 40U },
3688  { PPC::F9, 41U },
3689  { PPC::F10, 42U },
3690  { PPC::F11, 43U },
3691  { PPC::F12, 44U },
3692  { PPC::F13, 45U },
3693  { PPC::F14, 46U },
3694  { PPC::F15, 47U },
3695  { PPC::F16, 48U },
3696  { PPC::F17, 49U },
3697  { PPC::F18, 50U },
3698  { PPC::F19, 51U },
3699  { PPC::F20, 52U },
3700  { PPC::F21, 53U },
3701  { PPC::F22, 54U },
3702  { PPC::F23, 55U },
3703  { PPC::F24, 56U },
3704  { PPC::F25, 57U },
3705  { PPC::F26, 58U },
3706  { PPC::F27, 59U },
3707  { PPC::F28, 60U },
3708  { PPC::F29, 61U },
3709  { PPC::F30, 62U },
3710  { PPC::F31, 63U },
3711  { PPC::LR8, -2U },
3712  { PPC::R0, 0U },
3713  { PPC::R1, 1U },
3714  { PPC::R2, 2U },
3715  { PPC::R3, 3U },
3716  { PPC::R4, 4U },
3717  { PPC::R5, 5U },
3718  { PPC::R6, 6U },
3719  { PPC::R7, 7U },
3720  { PPC::R8, 8U },
3721  { PPC::R9, 9U },
3722  { PPC::R10, 10U },
3723  { PPC::R11, 11U },
3724  { PPC::R12, 12U },
3725  { PPC::R13, 13U },
3726  { PPC::R14, 14U },
3727  { PPC::R15, 15U },
3728  { PPC::R16, 16U },
3729  { PPC::R17, 17U },
3730  { PPC::R18, 18U },
3731  { PPC::R19, 19U },
3732  { PPC::R20, 20U },
3733  { PPC::R21, 21U },
3734  { PPC::R22, 22U },
3735  { PPC::R23, 23U },
3736  { PPC::R24, 24U },
3737  { PPC::R25, 25U },
3738  { PPC::R26, 26U },
3739  { PPC::R27, 27U },
3740  { PPC::R28, 28U },
3741  { PPC::R29, 29U },
3742  { PPC::R30, 30U },
3743  { PPC::R31, 31U },
3744  { PPC::S0, 1200U },
3745  { PPC::S1, 1201U },
3746  { PPC::S2, 1202U },
3747  { PPC::S3, 1203U },
3748  { PPC::S4, 1204U },
3749  { PPC::S5, 1205U },
3750  { PPC::S6, 1206U },
3751  { PPC::S7, 1207U },
3752  { PPC::S8, 1208U },
3753  { PPC::S9, 1209U },
3754  { PPC::S10, 1210U },
3755  { PPC::S11, 1211U },
3756  { PPC::S12, 1212U },
3757  { PPC::S13, 1213U },
3758  { PPC::S14, 1214U },
3759  { PPC::S15, 1215U },
3760  { PPC::S16, 1216U },
3761  { PPC::S17, 1217U },
3762  { PPC::S18, 1218U },
3763  { PPC::S19, 1219U },
3764  { PPC::S20, 1220U },
3765  { PPC::S21, 1221U },
3766  { PPC::S22, 1222U },
3767  { PPC::S23, 1223U },
3768  { PPC::S24, 1224U },
3769  { PPC::S25, 1225U },
3770  { PPC::S26, 1226U },
3771  { PPC::S27, 1227U },
3772  { PPC::S28, 1228U },
3773  { PPC::S29, 1229U },
3774  { PPC::S30, 1230U },
3775  { PPC::S31, 1231U },
3776  { PPC::V0, 77U },
3777  { PPC::V1, 78U },
3778  { PPC::V2, 79U },
3779  { PPC::V3, 80U },
3780  { PPC::V4, 81U },
3781  { PPC::V5, 82U },
3782  { PPC::V6, 83U },
3783  { PPC::V7, 84U },
3784  { PPC::V8, 85U },
3785  { PPC::V9, 86U },
3786  { PPC::V10, 87U },
3787  { PPC::V11, 88U },
3788  { PPC::V12, 89U },
3789  { PPC::V13, 90U },
3790  { PPC::V14, 91U },
3791  { PPC::V15, 92U },
3792  { PPC::V16, 93U },
3793  { PPC::V17, 94U },
3794  { PPC::V18, 95U },
3795  { PPC::V19, 96U },
3796  { PPC::V20, 97U },
3797  { PPC::V21, 98U },
3798  { PPC::V22, 99U },
3799  { PPC::V23, 100U },
3800  { PPC::V24, 101U },
3801  { PPC::V25, 102U },
3802  { PPC::V26, 103U },
3803  { PPC::V27, 104U },
3804  { PPC::V28, 105U },
3805  { PPC::V29, 106U },
3806  { PPC::V30, 107U },
3807  { PPC::V31, 108U },
3808  { PPC::VF0, 77U },
3809  { PPC::VF1, 78U },
3810  { PPC::VF2, 79U },
3811  { PPC::VF3, 80U },
3812  { PPC::VF4, 81U },
3813  { PPC::VF5, 82U },
3814  { PPC::VF6, 83U },
3815  { PPC::VF7, 84U },
3816  { PPC::VF8, 85U },
3817  { PPC::VF9, 86U },
3818  { PPC::VF10, 87U },
3819  { PPC::VF11, 88U },
3820  { PPC::VF12, 89U },
3821  { PPC::VF13, 90U },
3822  { PPC::VF14, 91U },
3823  { PPC::VF15, 92U },
3824  { PPC::VF16, 93U },
3825  { PPC::VF17, 94U },
3826  { PPC::VF18, 95U },
3827  { PPC::VF19, 96U },
3828  { PPC::VF20, 97U },
3829  { PPC::VF21, 98U },
3830  { PPC::VF22, 99U },
3831  { PPC::VF23, 100U },
3832  { PPC::VF24, 101U },
3833  { PPC::VF25, 102U },
3834  { PPC::VF26, 103U },
3835  { PPC::VF27, 104U },
3836  { PPC::VF28, 105U },
3837  { PPC::VF29, 106U },
3838  { PPC::VF30, 107U },
3839  { PPC::VF31, 108U },
3840  { PPC::VSL0, 32U },
3841  { PPC::VSL1, 33U },
3842  { PPC::VSL2, 34U },
3843  { PPC::VSL3, 35U },
3844  { PPC::VSL4, 36U },
3845  { PPC::VSL5, 37U },
3846  { PPC::VSL6, 38U },
3847  { PPC::VSL7, 39U },
3848  { PPC::VSL8, 40U },
3849  { PPC::VSL9, 41U },
3850  { PPC::VSL10, 42U },
3851  { PPC::VSL11, 43U },
3852  { PPC::VSL12, 44U },
3853  { PPC::VSL13, 45U },
3854  { PPC::VSL14, 46U },
3855  { PPC::VSL15, 47U },
3856  { PPC::VSL16, 48U },
3857  { PPC::VSL17, 49U },
3858  { PPC::VSL18, 50U },
3859  { PPC::VSL19, 51U },
3860  { PPC::VSL20, 52U },
3861  { PPC::VSL21, 53U },
3862  { PPC::VSL22, 54U },
3863  { PPC::VSL23, 55U },
3864  { PPC::VSL24, 56U },
3865  { PPC::VSL25, 57U },
3866  { PPC::VSL26, 58U },
3867  { PPC::VSL27, 59U },
3868  { PPC::VSL28, 60U },
3869  { PPC::VSL29, 61U },
3870  { PPC::VSL30, 62U },
3871  { PPC::VSL31, 63U },
3872  { PPC::X0, -2U },
3873  { PPC::X1, -2U },
3874  { PPC::X2, -2U },
3875  { PPC::X3, -2U },
3876  { PPC::X4, -2U },
3877  { PPC::X5, -2U },
3878  { PPC::X6, -2U },
3879  { PPC::X7, -2U },
3880  { PPC::X8, -2U },
3881  { PPC::X9, -2U },
3882  { PPC::X10, -2U },
3883  { PPC::X11, -2U },
3884  { PPC::X12, -2U },
3885  { PPC::X13, -2U },
3886  { PPC::X14, -2U },
3887  { PPC::X15, -2U },
3888  { PPC::X16, -2U },
3889  { PPC::X17, -2U },
3890  { PPC::X18, -2U },
3891  { PPC::X19, -2U },
3892  { PPC::X20, -2U },
3893  { PPC::X21, -2U },
3894  { PPC::X22, -2U },
3895  { PPC::X23, -2U },
3896  { PPC::X24, -2U },
3897  { PPC::X25, -2U },
3898  { PPC::X26, -2U },
3899  { PPC::X27, -2U },
3900  { PPC::X28, -2U },
3901  { PPC::X29, -2U },
3902  { PPC::X30, -2U },
3903  { PPC::X31, -2U },
3904  { PPC::ZERO8, -2U },
3905};
3906extern const unsigned PPCDwarfFlavour1L2DwarfSize = std::size(PPCDwarfFlavour1L2Dwarf);
3907
3908extern const MCRegisterInfo::DwarfLLVMRegPair PPCEHFlavour0L2Dwarf[] = {
3909  { PPC::CARRY, 76U },
3910  { PPC::CTR, -2U },
3911  { PPC::LR, -2U },
3912  { PPC::SPEFSCR, 612U },
3913  { PPC::VRSAVE, 109U },
3914  { PPC::XER, 76U },
3915  { PPC::ZERO, -2U },
3916  { PPC::CR0, 68U },
3917  { PPC::CR1, 69U },
3918  { PPC::CR2, 70U },
3919  { PPC::CR3, 71U },
3920  { PPC::CR4, 72U },
3921  { PPC::CR5, 73U },
3922  { PPC::CR6, 74U },
3923  { PPC::CR7, 75U },
3924  { PPC::CTR8, 66U },
3925  { PPC::F0, 32U },
3926  { PPC::F1, 33U },
3927  { PPC::F2, 34U },
3928  { PPC::F3, 35U },
3929  { PPC::F4, 36U },
3930  { PPC::F5, 37U },
3931  { PPC::F6, 38U },
3932  { PPC::F7, 39U },
3933  { PPC::F8, 40U },
3934  { PPC::F9, 41U },
3935  { PPC::F10, 42U },
3936  { PPC::F11, 43U },
3937  { PPC::F12, 44U },
3938  { PPC::F13, 45U },
3939  { PPC::F14, 46U },
3940  { PPC::F15, 47U },
3941  { PPC::F16, 48U },
3942  { PPC::F17, 49U },
3943  { PPC::F18, 50U },
3944  { PPC::F19, 51U },
3945  { PPC::F20, 52U },
3946  { PPC::F21, 53U },
3947  { PPC::F22, 54U },
3948  { PPC::F23, 55U },
3949  { PPC::F24, 56U },
3950  { PPC::F25, 57U },
3951  { PPC::F26, 58U },
3952  { PPC::F27, 59U },
3953  { PPC::F28, 60U },
3954  { PPC::F29, 61U },
3955  { PPC::F30, 62U },
3956  { PPC::F31, 63U },
3957  { PPC::LR8, 65U },
3958  { PPC::R0, -2U },
3959  { PPC::R1, -2U },
3960  { PPC::R2, -2U },
3961  { PPC::R3, -2U },
3962  { PPC::R4, -2U },
3963  { PPC::R5, -2U },
3964  { PPC::R6, -2U },
3965  { PPC::R7, -2U },
3966  { PPC::R8, -2U },
3967  { PPC::R9, -2U },
3968  { PPC::R10, -2U },
3969  { PPC::R11, -2U },
3970  { PPC::R12, -2U },
3971  { PPC::R13, -2U },
3972  { PPC::R14, -2U },
3973  { PPC::R15, -2U },
3974  { PPC::R16, -2U },
3975  { PPC::R17, -2U },
3976  { PPC::R18, -2U },
3977  { PPC::R19, -2U },
3978  { PPC::R20, -2U },
3979  { PPC::R21, -2U },
3980  { PPC::R22, -2U },
3981  { PPC::R23, -2U },
3982  { PPC::R24, -2U },
3983  { PPC::R25, -2U },
3984  { PPC::R26, -2U },
3985  { PPC::R27, -2U },
3986  { PPC::R28, -2U },
3987  { PPC::R29, -2U },
3988  { PPC::R30, -2U },
3989  { PPC::R31, -2U },
3990  { PPC::S0, 1200U },
3991  { PPC::S1, 1201U },
3992  { PPC::S2, 1202U },
3993  { PPC::S3, 1203U },
3994  { PPC::S4, 1204U },
3995  { PPC::S5, 1205U },
3996  { PPC::S6, 1206U },
3997  { PPC::S7, 1207U },
3998  { PPC::S8, 1208U },
3999  { PPC::S9, 1209U },
4000  { PPC::S10, 1210U },
4001  { PPC::S11, 1211U },
4002  { PPC::S12, 1212U },
4003  { PPC::S13, 1213U },
4004  { PPC::S14, 1214U },
4005  { PPC::S15, 1215U },
4006  { PPC::S16, 1216U },
4007  { PPC::S17, 1217U },
4008  { PPC::S18, 1218U },
4009  { PPC::S19, 1219U },
4010  { PPC::S20, 1220U },
4011  { PPC::S21, 1221U },
4012  { PPC::S22, 1222U },
4013  { PPC::S23, 1223U },
4014  { PPC::S24, 1224U },
4015  { PPC::S25, 1225U },
4016  { PPC::S26, 1226U },
4017  { PPC::S27, 1227U },
4018  { PPC::S28, 1228U },
4019  { PPC::S29, 1229U },
4020  { PPC::S30, 1230U },
4021  { PPC::S31, 1231U },
4022  { PPC::V0, 77U },
4023  { PPC::V1, 78U },
4024  { PPC::V2, 79U },
4025  { PPC::V3, 80U },
4026  { PPC::V4, 81U },
4027  { PPC::V5, 82U },
4028  { PPC::V6, 83U },
4029  { PPC::V7, 84U },
4030  { PPC::V8, 85U },
4031  { PPC::V9, 86U },
4032  { PPC::V10, 87U },
4033  { PPC::V11, 88U },
4034  { PPC::V12, 89U },
4035  { PPC::V13, 90U },
4036  { PPC::V14, 91U },
4037  { PPC::V15, 92U },
4038  { PPC::V16, 93U },
4039  { PPC::V17, 94U },
4040  { PPC::V18, 95U },
4041  { PPC::V19, 96U },
4042  { PPC::V20, 97U },
4043  { PPC::V21, 98U },
4044  { PPC::V22, 99U },
4045  { PPC::V23, 100U },
4046  { PPC::V24, 101U },
4047  { PPC::V25, 102U },
4048  { PPC::V26, 103U },
4049  { PPC::V27, 104U },
4050  { PPC::V28, 105U },
4051  { PPC::V29, 106U },
4052  { PPC::V30, 107U },
4053  { PPC::V31, 108U },
4054  { PPC::VF0, 77U },
4055  { PPC::VF1, 78U },
4056  { PPC::VF2, 79U },
4057  { PPC::VF3, 80U },
4058  { PPC::VF4, 81U },
4059  { PPC::VF5, 82U },
4060  { PPC::VF6, 83U },
4061  { PPC::VF7, 84U },
4062  { PPC::VF8, 85U },
4063  { PPC::VF9, 86U },
4064  { PPC::VF10, 87U },
4065  { PPC::VF11, 88U },
4066  { PPC::VF12, 89U },
4067  { PPC::VF13, 90U },
4068  { PPC::VF14, 91U },
4069  { PPC::VF15, 92U },
4070  { PPC::VF16, 93U },
4071  { PPC::VF17, 94U },
4072  { PPC::VF18, 95U },
4073  { PPC::VF19, 96U },
4074  { PPC::VF20, 97U },
4075  { PPC::VF21, 98U },
4076  { PPC::VF22, 99U },
4077  { PPC::VF23, 100U },
4078  { PPC::VF24, 101U },
4079  { PPC::VF25, 102U },
4080  { PPC::VF26, 103U },
4081  { PPC::VF27, 104U },
4082  { PPC::VF28, 105U },
4083  { PPC::VF29, 106U },
4084  { PPC::VF30, 107U },
4085  { PPC::VF31, 108U },
4086  { PPC::VSL0, 32U },
4087  { PPC::VSL1, 33U },
4088  { PPC::VSL2, 34U },
4089  { PPC::VSL3, 35U },
4090  { PPC::VSL4, 36U },
4091  { PPC::VSL5, 37U },
4092  { PPC::VSL6, 38U },
4093  { PPC::VSL7, 39U },
4094  { PPC::VSL8, 40U },
4095  { PPC::VSL9, 41U },
4096  { PPC::VSL10, 42U },
4097  { PPC::VSL11, 43U },
4098  { PPC::VSL12, 44U },
4099  { PPC::VSL13, 45U },
4100  { PPC::VSL14, 46U },
4101  { PPC::VSL15, 47U },
4102  { PPC::VSL16, 48U },
4103  { PPC::VSL17, 49U },
4104  { PPC::VSL18, 50U },
4105  { PPC::VSL19, 51U },
4106  { PPC::VSL20, 52U },
4107  { PPC::VSL21, 53U },
4108  { PPC::VSL22, 54U },
4109  { PPC::VSL23, 55U },
4110  { PPC::VSL24, 56U },
4111  { PPC::VSL25, 57U },
4112  { PPC::VSL26, 58U },
4113  { PPC::VSL27, 59U },
4114  { PPC::VSL28, 60U },
4115  { PPC::VSL29, 61U },
4116  { PPC::VSL30, 62U },
4117  { PPC::VSL31, 63U },
4118  { PPC::X0, 0U },
4119  { PPC::X1, 1U },
4120  { PPC::X2, 2U },
4121  { PPC::X3, 3U },
4122  { PPC::X4, 4U },
4123  { PPC::X5, 5U },
4124  { PPC::X6, 6U },
4125  { PPC::X7, 7U },
4126  { PPC::X8, 8U },
4127  { PPC::X9, 9U },
4128  { PPC::X10, 10U },
4129  { PPC::X11, 11U },
4130  { PPC::X12, 12U },
4131  { PPC::X13, 13U },
4132  { PPC::X14, 14U },
4133  { PPC::X15, 15U },
4134  { PPC::X16, 16U },
4135  { PPC::X17, 17U },
4136  { PPC::X18, 18U },
4137  { PPC::X19, 19U },
4138  { PPC::X20, 20U },
4139  { PPC::X21, 21U },
4140  { PPC::X22, 22U },
4141  { PPC::X23, 23U },
4142  { PPC::X24, 24U },
4143  { PPC::X25, 25U },
4144  { PPC::X26, 26U },
4145  { PPC::X27, 27U },
4146  { PPC::X28, 28U },
4147  { PPC::X29, 29U },
4148  { PPC::X30, 30U },
4149  { PPC::X31, 31U },
4150  { PPC::ZERO8, 0U },
4151};
4152extern const unsigned PPCEHFlavour0L2DwarfSize = std::size(PPCEHFlavour0L2Dwarf);
4153
4154extern const MCRegisterInfo::DwarfLLVMRegPair PPCEHFlavour1L2Dwarf[] = {
4155  { PPC::CTR, 66U },
4156  { PPC::LR, 65U },
4157  { PPC::SPEFSCR, 112U },
4158  { PPC::ZERO, 0U },
4159  { PPC::CR0, 68U },
4160  { PPC::CR1, 69U },
4161  { PPC::CR2, 70U },
4162  { PPC::CR3, 71U },
4163  { PPC::CR4, 72U },
4164  { PPC::CR5, 73U },
4165  { PPC::CR6, 74U },
4166  { PPC::CR7, 75U },
4167  { PPC::CTR8, -2U },
4168  { PPC::F0, 32U },
4169  { PPC::F1, 33U },
4170  { PPC::F2, 34U },
4171  { PPC::F3, 35U },
4172  { PPC::F4, 36U },
4173  { PPC::F5, 37U },
4174  { PPC::F6, 38U },
4175  { PPC::F7, 39U },
4176  { PPC::F8, 40U },
4177  { PPC::F9, 41U },
4178  { PPC::F10, 42U },
4179  { PPC::F11, 43U },
4180  { PPC::F12, 44U },
4181  { PPC::F13, 45U },
4182  { PPC::F14, 46U },
4183  { PPC::F15, 47U },
4184  { PPC::F16, 48U },
4185  { PPC::F17, 49U },
4186  { PPC::F18, 50U },
4187  { PPC::F19, 51U },
4188  { PPC::F20, 52U },
4189  { PPC::F21, 53U },
4190  { PPC::F22, 54U },
4191  { PPC::F23, 55U },
4192  { PPC::F24, 56U },
4193  { PPC::F25, 57U },
4194  { PPC::F26, 58U },
4195  { PPC::F27, 59U },
4196  { PPC::F28, 60U },
4197  { PPC::F29, 61U },
4198  { PPC::F30, 62U },
4199  { PPC::F31, 63U },
4200  { PPC::LR8, -2U },
4201  { PPC::R0, 0U },
4202  { PPC::R1, 1U },
4203  { PPC::R2, 2U },
4204  { PPC::R3, 3U },
4205  { PPC::R4, 4U },
4206  { PPC::R5, 5U },
4207  { PPC::R6, 6U },
4208  { PPC::R7, 7U },
4209  { PPC::R8, 8U },
4210  { PPC::R9, 9U },
4211  { PPC::R10, 10U },
4212  { PPC::R11, 11U },
4213  { PPC::R12, 12U },
4214  { PPC::R13, 13U },
4215  { PPC::R14, 14U },
4216  { PPC::R15, 15U },
4217  { PPC::R16, 16U },
4218  { PPC::R17, 17U },
4219  { PPC::R18, 18U },
4220  { PPC::R19, 19U },
4221  { PPC::R20, 20U },
4222  { PPC::R21, 21U },
4223  { PPC::R22, 22U },
4224  { PPC::R23, 23U },
4225  { PPC::R24, 24U },
4226  { PPC::R25, 25U },
4227  { PPC::R26, 26U },
4228  { PPC::R27, 27U },
4229  { PPC::R28, 28U },
4230  { PPC::R29, 29U },
4231  { PPC::R30, 30U },
4232  { PPC::R31, 31U },
4233  { PPC::S0, 1200U },
4234  { PPC::S1, 1201U },
4235  { PPC::S2, 1202U },
4236  { PPC::S3, 1203U },
4237  { PPC::S4, 1204U },
4238  { PPC::S5, 1205U },
4239  { PPC::S6, 1206U },
4240  { PPC::S7, 1207U },
4241  { PPC::S8, 1208U },
4242  { PPC::S9, 1209U },
4243  { PPC::S10, 1210U },
4244  { PPC::S11, 1211U },
4245  { PPC::S12, 1212U },
4246  { PPC::S13, 1213U },
4247  { PPC::S14, 1214U },
4248  { PPC::S15, 1215U },
4249  { PPC::S16, 1216U },
4250  { PPC::S17, 1217U },
4251  { PPC::S18, 1218U },
4252  { PPC::S19, 1219U },
4253  { PPC::S20, 1220U },
4254  { PPC::S21, 1221U },
4255  { PPC::S22, 1222U },
4256  { PPC::S23, 1223U },
4257  { PPC::S24, 1224U },
4258  { PPC::S25, 1225U },
4259  { PPC::S26, 1226U },
4260  { PPC::S27, 1227U },
4261  { PPC::S28, 1228U },
4262  { PPC::S29, 1229U },
4263  { PPC::S30, 1230U },
4264  { PPC::S31, 1231U },
4265  { PPC::V0, 77U },
4266  { PPC::V1, 78U },
4267  { PPC::V2, 79U },
4268  { PPC::V3, 80U },
4269  { PPC::V4, 81U },
4270  { PPC::V5, 82U },
4271  { PPC::V6, 83U },
4272  { PPC::V7, 84U },
4273  { PPC::V8, 85U },
4274  { PPC::V9, 86U },
4275  { PPC::V10, 87U },
4276  { PPC::V11, 88U },
4277  { PPC::V12, 89U },
4278  { PPC::V13, 90U },
4279  { PPC::V14, 91U },
4280  { PPC::V15, 92U },
4281  { PPC::V16, 93U },
4282  { PPC::V17, 94U },
4283  { PPC::V18, 95U },
4284  { PPC::V19, 96U },
4285  { PPC::V20, 97U },
4286  { PPC::V21, 98U },
4287  { PPC::V22, 99U },
4288  { PPC::V23, 100U },
4289  { PPC::V24, 101U },
4290  { PPC::V25, 102U },
4291  { PPC::V26, 103U },
4292  { PPC::V27, 104U },
4293  { PPC::V28, 105U },
4294  { PPC::V29, 106U },
4295  { PPC::V30, 107U },
4296  { PPC::V31, 108U },
4297  { PPC::VF0, 77U },
4298  { PPC::VF1, 78U },
4299  { PPC::VF2, 79U },
4300  { PPC::VF3, 80U },
4301  { PPC::VF4, 81U },
4302  { PPC::VF5, 82U },
4303  { PPC::VF6, 83U },
4304  { PPC::VF7, 84U },
4305  { PPC::VF8, 85U },
4306  { PPC::VF9, 86U },
4307  { PPC::VF10, 87U },
4308  { PPC::VF11, 88U },
4309  { PPC::VF12, 89U },
4310  { PPC::VF13, 90U },
4311  { PPC::VF14, 91U },
4312  { PPC::VF15, 92U },
4313  { PPC::VF16, 93U },
4314  { PPC::VF17, 94U },
4315  { PPC::VF18, 95U },
4316  { PPC::VF19, 96U },
4317  { PPC::VF20, 97U },
4318  { PPC::VF21, 98U },
4319  { PPC::VF22, 99U },
4320  { PPC::VF23, 100U },
4321  { PPC::VF24, 101U },
4322  { PPC::VF25, 102U },
4323  { PPC::VF26, 103U },
4324  { PPC::VF27, 104U },
4325  { PPC::VF28, 105U },
4326  { PPC::VF29, 106U },
4327  { PPC::VF30, 107U },
4328  { PPC::VF31, 108U },
4329  { PPC::VSL0, 32U },
4330  { PPC::VSL1, 33U },
4331  { PPC::VSL2, 34U },
4332  { PPC::VSL3, 35U },
4333  { PPC::VSL4, 36U },
4334  { PPC::VSL5, 37U },
4335  { PPC::VSL6, 38U },
4336  { PPC::VSL7, 39U },
4337  { PPC::VSL8, 40U },
4338  { PPC::VSL9, 41U },
4339  { PPC::VSL10, 42U },
4340  { PPC::VSL11, 43U },
4341  { PPC::VSL12, 44U },
4342  { PPC::VSL13, 45U },
4343  { PPC::VSL14, 46U },
4344  { PPC::VSL15, 47U },
4345  { PPC::VSL16, 48U },
4346  { PPC::VSL17, 49U },
4347  { PPC::VSL18, 50U },
4348  { PPC::VSL19, 51U },
4349  { PPC::VSL20, 52U },
4350  { PPC::VSL21, 53U },
4351  { PPC::VSL22, 54U },
4352  { PPC::VSL23, 55U },
4353  { PPC::VSL24, 56U },
4354  { PPC::VSL25, 57U },
4355  { PPC::VSL26, 58U },
4356  { PPC::VSL27, 59U },
4357  { PPC::VSL28, 60U },
4358  { PPC::VSL29, 61U },
4359  { PPC::VSL30, 62U },
4360  { PPC::VSL31, 63U },
4361  { PPC::X0, -2U },
4362  { PPC::X1, -2U },
4363  { PPC::X2, -2U },
4364  { PPC::X3, -2U },
4365  { PPC::X4, -2U },
4366  { PPC::X5, -2U },
4367  { PPC::X6, -2U },
4368  { PPC::X7, -2U },
4369  { PPC::X8, -2U },
4370  { PPC::X9, -2U },
4371  { PPC::X10, -2U },
4372  { PPC::X11, -2U },
4373  { PPC::X12, -2U },
4374  { PPC::X13, -2U },
4375  { PPC::X14, -2U },
4376  { PPC::X15, -2U },
4377  { PPC::X16, -2U },
4378  { PPC::X17, -2U },
4379  { PPC::X18, -2U },
4380  { PPC::X19, -2U },
4381  { PPC::X20, -2U },
4382  { PPC::X21, -2U },
4383  { PPC::X22, -2U },
4384  { PPC::X23, -2U },
4385  { PPC::X24, -2U },
4386  { PPC::X25, -2U },
4387  { PPC::X26, -2U },
4388  { PPC::X27, -2U },
4389  { PPC::X28, -2U },
4390  { PPC::X29, -2U },
4391  { PPC::X30, -2U },
4392  { PPC::X31, -2U },
4393  { PPC::ZERO8, -2U },
4394};
4395extern const unsigned PPCEHFlavour1L2DwarfSize = std::size(PPCEHFlavour1L2Dwarf);
4396
4397extern const uint16_t PPCRegEncodingTable[] = {
4398  0,
4399  0,
4400  1,
4401  9,
4402  0,
4403  8,
4404  0,
4405  512,
4406  256,
4407  1,
4408  0,
4409  0,
4410  1,
4411  2,
4412  3,
4413  4,
4414  5,
4415  6,
4416  7,
4417  0,
4418  0,
4419  1,
4420  2,
4421  3,
4422  4,
4423  5,
4424  6,
4425  7,
4426  9,
4427  0,
4428  1,
4429  2,
4430  3,
4431  4,
4432  5,
4433  6,
4434  7,
4435  0,
4436  1,
4437  2,
4438  3,
4439  4,
4440  5,
4441  6,
4442  7,
4443  8,
4444  9,
4445  10,
4446  11,
4447  12,
4448  13,
4449  14,
4450  15,
4451  16,
4452  17,
4453  18,
4454  19,
4455  20,
4456  21,
4457  22,
4458  23,
4459  24,
4460  25,
4461  26,
4462  27,
4463  28,
4464  29,
4465  30,
4466  31,
4467  32,
4468  33,
4469  34,
4470  35,
4471  36,
4472  37,
4473  38,
4474  39,
4475  40,
4476  41,
4477  42,
4478  43,
4479  44,
4480  45,
4481  46,
4482  47,
4483  48,
4484  49,
4485  50,
4486  51,
4487  52,
4488  53,
4489  54,
4490  55,
4491  56,
4492  57,
4493  58,
4494  59,
4495  60,
4496  61,
4497  62,
4498  63,
4499  0,
4500  1,
4501  2,
4502  3,
4503  4,
4504  5,
4505  6,
4506  7,
4507  8,
4508  9,
4509  10,
4510  11,
4511  12,
4512  13,
4513  14,
4514  15,
4515  16,
4516  17,
4517  18,
4518  19,
4519  20,
4520  21,
4521  22,
4522  23,
4523  24,
4524  25,
4525  26,
4526  27,
4527  28,
4528  29,
4529  30,
4530  31,
4531  0,
4532  1,
4533  2,
4534  3,
4535  0,
4536  1,
4537  2,
4538  3,
4539  4,
4540  5,
4541  6,
4542  7,
4543  8,
4544  9,
4545  10,
4546  11,
4547  12,
4548  13,
4549  14,
4550  15,
4551  16,
4552  17,
4553  18,
4554  19,
4555  20,
4556  21,
4557  22,
4558  23,
4559  24,
4560  25,
4561  26,
4562  27,
4563  28,
4564  29,
4565  30,
4566  31,
4567  0,
4568  8,
4569  0,
4570  1,
4571  2,
4572  3,
4573  4,
4574  5,
4575  6,
4576  7,
4577  8,
4578  9,
4579  10,
4580  11,
4581  12,
4582  13,
4583  14,
4584  15,
4585  16,
4586  17,
4587  18,
4588  19,
4589  20,
4590  21,
4591  22,
4592  23,
4593  24,
4594  25,
4595  26,
4596  27,
4597  28,
4598  29,
4599  30,
4600  31,
4601  0,
4602  1,
4603  2,
4604  3,
4605  4,
4606  5,
4607  6,
4608  7,
4609  8,
4610  9,
4611  10,
4612  11,
4613  12,
4614  13,
4615  14,
4616  15,
4617  16,
4618  17,
4619  18,
4620  19,
4621  20,
4622  21,
4623  22,
4624  23,
4625  24,
4626  25,
4627  26,
4628  27,
4629  28,
4630  29,
4631  30,
4632  31,
4633  0,
4634  1,
4635  2,
4636  3,
4637  4,
4638  5,
4639  6,
4640  7,
4641  0,
4642  1,
4643  2,
4644  3,
4645  4,
4646  5,
4647  6,
4648  7,
4649  8,
4650  9,
4651  10,
4652  11,
4653  12,
4654  13,
4655  14,
4656  15,
4657  16,
4658  17,
4659  18,
4660  19,
4661  20,
4662  21,
4663  22,
4664  23,
4665  24,
4666  25,
4667  26,
4668  27,
4669  28,
4670  29,
4671  30,
4672  31,
4673  32,
4674  33,
4675  34,
4676  35,
4677  36,
4678  37,
4679  38,
4680  39,
4681  40,
4682  41,
4683  42,
4684  43,
4685  44,
4686  45,
4687  46,
4688  47,
4689  48,
4690  49,
4691  50,
4692  51,
4693  52,
4694  53,
4695  54,
4696  55,
4697  56,
4698  57,
4699  58,
4700  59,
4701  60,
4702  61,
4703  62,
4704  63,
4705  0,
4706  1,
4707  2,
4708  3,
4709  4,
4710  5,
4711  6,
4712  7,
4713  8,
4714  9,
4715  10,
4716  11,
4717  12,
4718  13,
4719  14,
4720  15,
4721  16,
4722  17,
4723  18,
4724  19,
4725  20,
4726  21,
4727  22,
4728  23,
4729  24,
4730  25,
4731  26,
4732  27,
4733  28,
4734  29,
4735  30,
4736  31,
4737  0,
4738  1,
4739  2,
4740  3,
4741  4,
4742  5,
4743  6,
4744  7,
4745  8,
4746  9,
4747  10,
4748  11,
4749  12,
4750  13,
4751  14,
4752  15,
4753  16,
4754  17,
4755  18,
4756  19,
4757  20,
4758  21,
4759  22,
4760  23,
4761  24,
4762  25,
4763  26,
4764  27,
4765  28,
4766  29,
4767  30,
4768  31,
4769  32,
4770  33,
4771  34,
4772  35,
4773  36,
4774  37,
4775  38,
4776  39,
4777  40,
4778  41,
4779  42,
4780  43,
4781  44,
4782  45,
4783  46,
4784  47,
4785  48,
4786  49,
4787  50,
4788  51,
4789  52,
4790  53,
4791  54,
4792  55,
4793  56,
4794  57,
4795  58,
4796  59,
4797  60,
4798  61,
4799  62,
4800  63,
4801  0,
4802  1,
4803  2,
4804  3,
4805  4,
4806  5,
4807  6,
4808  7,
4809  0,
4810  1,
4811  2,
4812  3,
4813  4,
4814  5,
4815  6,
4816  7,
4817  0,
4818  1,
4819  2,
4820  3,
4821  4,
4822  5,
4823  6,
4824  7,
4825  8,
4826  9,
4827  10,
4828  11,
4829  12,
4830  13,
4831  14,
4832  15,
4833  16,
4834  17,
4835  18,
4836  19,
4837  20,
4838  21,
4839  22,
4840  23,
4841  24,
4842  25,
4843  26,
4844  27,
4845  28,
4846  29,
4847  30,
4848  31,
4849  0,
4850  2,
4851  6,
4852  10,
4853  14,
4854  18,
4855  22,
4856  26,
4857  30,
4858  1,
4859  5,
4860  9,
4861  13,
4862  17,
4863  21,
4864  25,
4865  29,
4866  0,
4867  4,
4868  8,
4869  12,
4870  16,
4871  20,
4872  24,
4873  28,
4874  3,
4875  7,
4876  11,
4877  15,
4878  19,
4879  23,
4880  27,
4881  31,
4882  0,
4883  2,
4884  4,
4885  6,
4886  8,
4887  10,
4888  12,
4889  14,
4890  16,
4891  18,
4892  20,
4893  22,
4894  24,
4895  26,
4896  28,
4897  30,
4898};
4899static inline void InitPPCMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
4900  RI->InitMCRegisterInfo(PPCRegDesc, 500, RA, PC, PPCMCRegisterClasses, 51, PPCRegUnitRoots, 235, PPCRegDiffLists, PPCLaneMaskLists, PPCRegStrings, PPCRegClassStrings, PPCSubRegIdxLists, 49,
4901PPCSubRegIdxRanges, PPCRegEncodingTable);
4902
4903  switch (DwarfFlavour) {
4904  default:
4905    llvm_unreachable("Unknown DWARF flavour");
4906  case 0:
4907    RI->mapDwarfRegsToLLVMRegs(PPCDwarfFlavour0Dwarf2L, PPCDwarfFlavour0Dwarf2LSize, false);
4908    break;
4909  case 1:
4910    RI->mapDwarfRegsToLLVMRegs(PPCDwarfFlavour1Dwarf2L, PPCDwarfFlavour1Dwarf2LSize, false);
4911    break;
4912  }
4913  switch (EHFlavour) {
4914  default:
4915    llvm_unreachable("Unknown DWARF flavour");
4916  case 0:
4917    RI->mapDwarfRegsToLLVMRegs(PPCEHFlavour0Dwarf2L, PPCEHFlavour0Dwarf2LSize, true);
4918    break;
4919  case 1:
4920    RI->mapDwarfRegsToLLVMRegs(PPCEHFlavour1Dwarf2L, PPCEHFlavour1Dwarf2LSize, true);
4921    break;
4922  }
4923  switch (DwarfFlavour) {
4924  default:
4925    llvm_unreachable("Unknown DWARF flavour");
4926  case 0:
4927    RI->mapLLVMRegsToDwarfRegs(PPCDwarfFlavour0L2Dwarf, PPCDwarfFlavour0L2DwarfSize, false);
4928    break;
4929  case 1:
4930    RI->mapLLVMRegsToDwarfRegs(PPCDwarfFlavour1L2Dwarf, PPCDwarfFlavour1L2DwarfSize, false);
4931    break;
4932  }
4933  switch (EHFlavour) {
4934  default:
4935    llvm_unreachable("Unknown DWARF flavour");
4936  case 0:
4937    RI->mapLLVMRegsToDwarfRegs(PPCEHFlavour0L2Dwarf, PPCEHFlavour0L2DwarfSize, true);
4938    break;
4939  case 1:
4940    RI->mapLLVMRegsToDwarfRegs(PPCEHFlavour1L2Dwarf, PPCEHFlavour1L2DwarfSize, true);
4941    break;
4942  }
4943}
4944
4945} // end namespace llvm
4946
4947#endif // GET_REGINFO_MC_DESC
4948
4949/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
4950|*                                                                            *|
4951|* Register Information Header Fragment                                       *|
4952|*                                                                            *|
4953|* Automatically generated file, do not edit!                                 *|
4954|*                                                                            *|
4955\*===----------------------------------------------------------------------===*/
4956
4957
4958#ifdef GET_REGINFO_HEADER
4959#undef GET_REGINFO_HEADER
4960
4961#include "llvm/CodeGen/TargetRegisterInfo.h"
4962
4963namespace llvm {
4964
4965class PPCFrameLowering;
4966
4967struct PPCGenRegisterInfo : public TargetRegisterInfo {
4968  explicit PPCGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
4969      unsigned PC = 0, unsigned HwMode = 0);
4970  unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
4971  LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
4972  LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
4973  const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass *, unsigned) const override;
4974  const TargetRegisterClass *getSubRegisterClass(const TargetRegisterClass *, unsigned) const override;
4975  const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
4976  unsigned getRegUnitWeight(unsigned RegUnit) const override;
4977  unsigned getNumRegPressureSets() const override;
4978  const char *getRegPressureSetName(unsigned Idx) const override;
4979  unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
4980  const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
4981  const int *getRegUnitPressureSets(unsigned RegUnit) const override;
4982  ArrayRef<const char *> getRegMaskNames() const override;
4983  ArrayRef<const uint32_t *> getRegMasks() const override;
4984  bool isGeneralPurposeRegister(const MachineFunction &, MCRegister) const override;
4985  bool isFixedRegister(const MachineFunction &, MCRegister) const override;
4986  bool isArgumentRegister(const MachineFunction &, MCRegister) const override;
4987  bool isConstantPhysReg(MCRegister PhysReg) const override final;
4988  /// Devirtualized TargetFrameLowering.
4989  static const PPCFrameLowering *getFrameLowering(
4990      const MachineFunction &MF);
4991};
4992
4993namespace PPC { // Register classes
4994  extern const TargetRegisterClass VSSRCRegClass;
4995  extern const TargetRegisterClass GPRCRegClass;
4996  extern const TargetRegisterClass GPRC_NOR0RegClass;
4997  extern const TargetRegisterClass GPRC_and_GPRC_NOR0RegClass;
4998  extern const TargetRegisterClass CRBITRCRegClass;
4999  extern const TargetRegisterClass F4RCRegClass;
5000  extern const TargetRegisterClass CRRCRegClass;
5001  extern const TargetRegisterClass CARRYRCRegClass;
5002  extern const TargetRegisterClass CTRRCRegClass;
5003  extern const TargetRegisterClass LRRCRegClass;
5004  extern const TargetRegisterClass VRSAVERCRegClass;
5005  extern const TargetRegisterClass SPILLTOVSRRCRegClass;
5006  extern const TargetRegisterClass VSFRCRegClass;
5007  extern const TargetRegisterClass G8RCRegClass;
5008  extern const TargetRegisterClass G8RC_NOX0RegClass;
5009  extern const TargetRegisterClass SPILLTOVSRRC_and_VSFRCRegClass;
5010  extern const TargetRegisterClass G8RC_and_G8RC_NOX0RegClass;
5011  extern const TargetRegisterClass F8RCRegClass;
5012  extern const TargetRegisterClass SPERCRegClass;
5013  extern const TargetRegisterClass VFRCRegClass;
5014  extern const TargetRegisterClass SPERC_with_sub_32_in_GPRC_NOR0RegClass;
5015  extern const TargetRegisterClass SPILLTOVSRRC_and_VFRCRegClass;
5016  extern const TargetRegisterClass SPILLTOVSRRC_and_F4RCRegClass;
5017  extern const TargetRegisterClass CTRRC8RegClass;
5018  extern const TargetRegisterClass LR8RCRegClass;
5019  extern const TargetRegisterClass DMRROWRCRegClass;
5020  extern const TargetRegisterClass VSRCRegClass;
5021  extern const TargetRegisterClass VSRC_with_sub_64_in_SPILLTOVSRRCRegClass;
5022  extern const TargetRegisterClass VRRCRegClass;
5023  extern const TargetRegisterClass VSLRCRegClass;
5024  extern const TargetRegisterClass VRRC_with_sub_64_in_SPILLTOVSRRCRegClass;
5025  extern const TargetRegisterClass G8pRCRegClass;
5026  extern const TargetRegisterClass G8pRC_with_sub_32_in_GPRC_NOR0RegClass;
5027  extern const TargetRegisterClass VSLRC_with_sub_64_in_SPILLTOVSRRCRegClass;
5028  extern const TargetRegisterClass DMRROWpRCRegClass;
5029  extern const TargetRegisterClass VSRpRCRegClass;
5030  extern const TargetRegisterClass VSRpRC_with_sub_64_in_SPILLTOVSRRCRegClass;
5031  extern const TargetRegisterClass VSRpRC_with_sub_64_in_F4RCRegClass;
5032  extern const TargetRegisterClass VSRpRC_with_sub_64_in_VFRCRegClass;
5033  extern const TargetRegisterClass VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCRegClass;
5034  extern const TargetRegisterClass VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCRegClass;
5035  extern const TargetRegisterClass ACCRCRegClass;
5036  extern const TargetRegisterClass UACCRCRegClass;
5037  extern const TargetRegisterClass WACCRCRegClass;
5038  extern const TargetRegisterClass WACC_HIRCRegClass;
5039  extern const TargetRegisterClass ACCRC_with_sub_64_in_SPILLTOVSRRCRegClass;
5040  extern const TargetRegisterClass UACCRC_with_sub_64_in_SPILLTOVSRRCRegClass;
5041  extern const TargetRegisterClass ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCRegClass;
5042  extern const TargetRegisterClass UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCRegClass;
5043  extern const TargetRegisterClass DMRRCRegClass;
5044  extern const TargetRegisterClass DMRpRCRegClass;
5045} // end namespace PPC
5046
5047} // end namespace llvm
5048
5049#endif // GET_REGINFO_HEADER
5050
5051/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
5052|*                                                                            *|
5053|* Target Register and Register Classes Information                           *|
5054|*                                                                            *|
5055|* Automatically generated file, do not edit!                                 *|
5056|*                                                                            *|
5057\*===----------------------------------------------------------------------===*/
5058
5059
5060#ifdef GET_REGINFO_TARGET_DESC
5061#undef GET_REGINFO_TARGET_DESC
5062
5063namespace llvm {
5064
5065extern const MCRegisterClass PPCMCRegisterClasses[];
5066
5067static const MVT::SimpleValueType VTLists[] = {
5068  /* 0 */ MVT::i1, MVT::Other,
5069  /* 2 */ MVT::i32, MVT::Other,
5070  /* 4 */ MVT::i64, MVT::Other,
5071  /* 6 */ MVT::i128, MVT::Other,
5072  /* 8 */ MVT::i32, MVT::f32, MVT::Other,
5073  /* 11 */ MVT::i64, MVT::f64, MVT::Other,
5074  /* 14 */ MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::v1i128, MVT::v4f32, MVT::v2f64, MVT::f128, MVT::Other,
5075  /* 23 */ MVT::v128i1, MVT::Other,
5076  /* 25 */ MVT::v256i1, MVT::Other,
5077  /* 27 */ MVT::v512i1, MVT::Other,
5078  /* 29 */ MVT::v1024i1, MVT::Other,
5079  /* 31 */ MVT::v2048i1, MVT::Other,
5080  /* 33 */ MVT::v4i32, MVT::v4f32, MVT::v2f64, MVT::v2i64, MVT::Other,
5081};
5082
5083static const char *SubRegIndexNameTable[] = { "sub_32", "sub_64", "sub_dmr0", "sub_dmr1", "sub_dmrrow0", "sub_dmrrow1", "sub_dmrrowp0", "sub_dmrrowp1", "sub_eq", "sub_gp8_x0", "sub_gp8_x1", "sub_gt", "sub_lt", "sub_pair0", "sub_pair1", "sub_un", "sub_vsx0", "sub_vsx1", "sub_wacc_hi", "sub_wacc_lo", "sub_vsx1_then_sub_64", "sub_pair1_then_sub_64", "sub_pair1_then_sub_vsx0", "sub_pair1_then_sub_vsx1", "sub_pair1_then_sub_vsx1_then_sub_64", "sub_dmrrowp1_then_sub_dmrrow0", "sub_dmrrowp1_then_sub_dmrrow1", "sub_wacc_hi_then_sub_dmrrow0", "sub_wacc_hi_then_sub_dmrrow1", "sub_wacc_hi_then_sub_dmrrowp0", "sub_wacc_hi_then_sub_dmrrowp1", "sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0", "sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1", "sub_dmr1_then_sub_dmrrow0", "sub_dmr1_then_sub_dmrrow1", "sub_dmr1_then_sub_dmrrowp0", "sub_dmr1_then_sub_dmrrowp1", "sub_dmr1_then_sub_wacc_hi", "sub_dmr1_then_sub_wacc_lo", "sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0", "sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1", "sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0", "sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1", "sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0", "sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1", "sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0", "sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1", "sub_gp8_x1_then_sub_32", "" };
5084
5085
5086static const LaneBitmask SubRegIndexLaneMaskTable[] = {
5087  LaneBitmask::getAll(),
5088  LaneBitmask(0x0000000000000001), // sub_32
5089  LaneBitmask(0x0000000000000002), // sub_64
5090  LaneBitmask(0x000000000001F80C), // sub_dmr0
5091  LaneBitmask(0x0000000001FE0000), // sub_dmr1
5092  LaneBitmask(0x0000000000000004), // sub_dmrrow0
5093  LaneBitmask(0x0000000000000008), // sub_dmrrow1
5094  LaneBitmask(0x000000000000000C), // sub_dmrrowp0
5095  LaneBitmask(0x0000000000001800), // sub_dmrrowp1
5096  LaneBitmask(0x0000000000000010), // sub_eq
5097  LaneBitmask(0x0000000000000001), // sub_gp8_x0
5098  LaneBitmask(0x0000000002000000), // sub_gp8_x1
5099  LaneBitmask(0x0000000000000020), // sub_gt
5100  LaneBitmask(0x0000000000000040), // sub_lt
5101  LaneBitmask(0x0000000000000102), // sub_pair0
5102  LaneBitmask(0x0000000000000600), // sub_pair1
5103  LaneBitmask(0x0000000000000080), // sub_un
5104  LaneBitmask(0x0000000000000002), // sub_vsx0
5105  LaneBitmask(0x0000000000000100), // sub_vsx1
5106  LaneBitmask(0x000000000001E000), // sub_wacc_hi
5107  LaneBitmask(0x000000000000180C), // sub_wacc_lo
5108  LaneBitmask(0x0000000000000100), // sub_vsx1_then_sub_64
5109  LaneBitmask(0x0000000000000200), // sub_pair1_then_sub_64
5110  LaneBitmask(0x0000000000000200), // sub_pair1_then_sub_vsx0
5111  LaneBitmask(0x0000000000000400), // sub_pair1_then_sub_vsx1
5112  LaneBitmask(0x0000000000000400), // sub_pair1_then_sub_vsx1_then_sub_64
5113  LaneBitmask(0x0000000000000800), // sub_dmrrowp1_then_sub_dmrrow0
5114  LaneBitmask(0x0000000000001000), // sub_dmrrowp1_then_sub_dmrrow1
5115  LaneBitmask(0x0000000000002000), // sub_wacc_hi_then_sub_dmrrow0
5116  LaneBitmask(0x0000000000004000), // sub_wacc_hi_then_sub_dmrrow1
5117  LaneBitmask(0x0000000000006000), // sub_wacc_hi_then_sub_dmrrowp0
5118  LaneBitmask(0x0000000000018000), // sub_wacc_hi_then_sub_dmrrowp1
5119  LaneBitmask(0x0000000000008000), // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
5120  LaneBitmask(0x0000000000010000), // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
5121  LaneBitmask(0x0000000000020000), // sub_dmr1_then_sub_dmrrow0
5122  LaneBitmask(0x0000000000040000), // sub_dmr1_then_sub_dmrrow1
5123  LaneBitmask(0x0000000000060000), // sub_dmr1_then_sub_dmrrowp0
5124  LaneBitmask(0x0000000000180000), // sub_dmr1_then_sub_dmrrowp1
5125  LaneBitmask(0x0000000001E00000), // sub_dmr1_then_sub_wacc_hi
5126  LaneBitmask(0x00000000001E0000), // sub_dmr1_then_sub_wacc_lo
5127  LaneBitmask(0x0000000000080000), // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
5128  LaneBitmask(0x0000000000100000), // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
5129  LaneBitmask(0x0000000000200000), // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
5130  LaneBitmask(0x0000000000400000), // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
5131  LaneBitmask(0x0000000000600000), // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
5132  LaneBitmask(0x0000000001800000), // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
5133  LaneBitmask(0x0000000000800000), // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
5134  LaneBitmask(0x0000000001000000), // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
5135  LaneBitmask(0x0000000002000000), // sub_gp8_x1_then_sub_32
5136 };
5137
5138
5139
5140static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
5141  // Mode = 0 (Default)
5142  { 32, 32, 32, VTLists+9 },    // VSSRC
5143  { 32, 32, 32, VTLists+8 },    // GPRC
5144  { 32, 32, 32, VTLists+8 },    // GPRC_NOR0
5145  { 32, 32, 32, VTLists+8 },    // GPRC_and_GPRC_NOR0
5146  { 32, 32, 32, VTLists+0 },    // CRBITRC
5147  { 32, 32, 32, VTLists+9 },    // F4RC
5148  { 32, 32, 32, VTLists+2 },    // CRRC
5149  { 32, 32, 32, VTLists+2 },    // CARRYRC
5150  { 32, 32, 32, VTLists+2 },    // CTRRC
5151  { 32, 32, 32, VTLists+2 },    // LRRC
5152  { 32, 32, 32, VTLists+2 },    // VRSAVERC
5153  { 64, 64, 64, VTLists+11 },    // SPILLTOVSRRC
5154  { 64, 64, 64, VTLists+12 },    // VSFRC
5155  { 64, 64, 64, VTLists+4 },    // G8RC
5156  { 64, 64, 64, VTLists+4 },    // G8RC_NOX0
5157  { 64, 64, 64, VTLists+12 },    // SPILLTOVSRRC_and_VSFRC
5158  { 64, 64, 64, VTLists+4 },    // G8RC_and_G8RC_NOX0
5159  { 64, 64, 64, VTLists+12 },    // F8RC
5160  { 64, 64, 64, VTLists+12 },    // SPERC
5161  { 64, 64, 64, VTLists+12 },    // VFRC
5162  { 64, 64, 64, VTLists+12 },    // SPERC_with_sub_32_in_GPRC_NOR0
5163  { 64, 64, 64, VTLists+12 },    // SPILLTOVSRRC_and_VFRC
5164  { 64, 64, 64, VTLists+12 },    // SPILLTOVSRRC_and_F4RC
5165  { 64, 64, 64, VTLists+4 },    // CTRRC8
5166  { 64, 64, 64, VTLists+4 },    // LR8RC
5167  { 128, 128, 128, VTLists+23 },    // DMRROWRC
5168  { 128, 128, 128, VTLists+33 },    // VSRC
5169  { 128, 128, 128, VTLists+33 },    // VSRC_with_sub_64_in_SPILLTOVSRRC
5170  { 128, 128, 128, VTLists+14 },    // VRRC
5171  { 128, 128, 128, VTLists+33 },    // VSLRC
5172  { 128, 128, 128, VTLists+14 },    // VRRC_with_sub_64_in_SPILLTOVSRRC
5173  { 128, 128, 128, VTLists+6 },    // G8pRC
5174  { 128, 128, 128, VTLists+6 },    // G8pRC_with_sub_32_in_GPRC_NOR0
5175  { 128, 128, 128, VTLists+33 },    // VSLRC_with_sub_64_in_SPILLTOVSRRC
5176  { 256, 256, 128, VTLists+25 },    // DMRROWpRC
5177  { 256, 256, 128, VTLists+25 },    // VSRpRC
5178  { 256, 256, 128, VTLists+25 },    // VSRpRC_with_sub_64_in_SPILLTOVSRRC
5179  { 256, 256, 128, VTLists+25 },    // VSRpRC_with_sub_64_in_F4RC
5180  { 256, 256, 128, VTLists+25 },    // VSRpRC_with_sub_64_in_VFRC
5181  { 256, 256, 128, VTLists+25 },    // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC
5182  { 256, 256, 128, VTLists+25 },    // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
5183  { 512, 512, 128, VTLists+27 },    // ACCRC
5184  { 512, 512, 128, VTLists+27 },    // UACCRC
5185  { 512, 512, 128, VTLists+27 },    // WACCRC
5186  { 512, 512, 128, VTLists+27 },    // WACC_HIRC
5187  { 512, 512, 128, VTLists+27 },    // ACCRC_with_sub_64_in_SPILLTOVSRRC
5188  { 512, 512, 128, VTLists+27 },    // UACCRC_with_sub_64_in_SPILLTOVSRRC
5189  { 512, 512, 128, VTLists+27 },    // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
5190  { 512, 512, 128, VTLists+27 },    // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
5191  { 1024, 1024, 128, VTLists+29 },    // DMRRC
5192  { 2048, 2048, 128, VTLists+31 },    // DMRpRC
5193};
5194
5195static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
5196
5197static const uint32_t VSSRCSubClassMask[] = {
5198  0x006a9021, 0x00000000,
5199  0x7c000000, 0x0001e7fa, // sub_64
5200  0x00000000, 0x0001e7f8, // sub_vsx1_then_sub_64
5201  0x00000000, 0x0001e600, // sub_pair1_then_sub_64
5202  0x00000000, 0x0001e600, // sub_pair1_then_sub_vsx1_then_sub_64
5203};
5204
5205static const uint32_t GPRCSubClassMask[] = {
5206  0x0000000a, 0x00000000,
5207  0x80152000, 0x00000001, // sub_32
5208  0x80000000, 0x00000001, // sub_gp8_x1_then_sub_32
5209};
5210
5211static const uint32_t GPRC_NOR0SubClassMask[] = {
5212  0x0000000c, 0x00000000,
5213  0x00114000, 0x00000001, // sub_32
5214  0x80000000, 0x00000001, // sub_gp8_x1_then_sub_32
5215};
5216
5217static const uint32_t GPRC_and_GPRC_NOR0SubClassMask[] = {
5218  0x00000008, 0x00000000,
5219  0x00110000, 0x00000001, // sub_32
5220  0x80000000, 0x00000001, // sub_gp8_x1_then_sub_32
5221};
5222
5223static const uint32_t CRBITRCSubClassMask[] = {
5224  0x00000010, 0x00000000,
5225  0x00000040, 0x00000000, // sub_eq
5226  0x00000040, 0x00000000, // sub_gt
5227  0x00000040, 0x00000000, // sub_lt
5228  0x00000040, 0x00000000, // sub_un
5229};
5230
5231static const uint32_t F4RCSubClassMask[] = {
5232  0x00420020, 0x00000000,
5233  0x20000000, 0x0001e722, // sub_64
5234  0x00000000, 0x0001e720, // sub_vsx1_then_sub_64
5235  0x00000000, 0x0001e600, // sub_pair1_then_sub_64
5236  0x00000000, 0x0001e600, // sub_pair1_then_sub_vsx1_then_sub_64
5237};
5238
5239static const uint32_t CRRCSubClassMask[] = {
5240  0x00000040, 0x00000000,
5241};
5242
5243static const uint32_t CARRYRCSubClassMask[] = {
5244  0x00000080, 0x00000000,
5245};
5246
5247static const uint32_t CTRRCSubClassMask[] = {
5248  0x00000100, 0x00000000,
5249};
5250
5251static const uint32_t LRRCSubClassMask[] = {
5252  0x00000200, 0x00000000,
5253};
5254
5255static const uint32_t VRSAVERCSubClassMask[] = {
5256  0x00000400, 0x00000000,
5257};
5258
5259static const uint32_t SPILLTOVSRRCSubClassMask[] = {
5260  0x0061a800, 0x00000000,
5261  0x48000000, 0x0001e192, // sub_64
5262  0x80000000, 0x00000001, // sub_gp8_x0
5263  0x80000000, 0x00000001, // sub_gp8_x1
5264  0x00000000, 0x0001e190, // sub_vsx1_then_sub_64
5265  0x00000000, 0x00018000, // sub_pair1_then_sub_64
5266  0x00000000, 0x00018000, // sub_pair1_then_sub_vsx1_then_sub_64
5267};
5268
5269static const uint32_t VSFRCSubClassMask[] = {
5270  0x006a9000, 0x00000000,
5271  0x7c000000, 0x0001e7fa, // sub_64
5272  0x00000000, 0x0001e7f8, // sub_vsx1_then_sub_64
5273  0x00000000, 0x0001e600, // sub_pair1_then_sub_64
5274  0x00000000, 0x0001e600, // sub_pair1_then_sub_vsx1_then_sub_64
5275};
5276
5277static const uint32_t G8RCSubClassMask[] = {
5278  0x00012000, 0x00000000,
5279  0x80000000, 0x00000001, // sub_gp8_x0
5280  0x80000000, 0x00000001, // sub_gp8_x1
5281};
5282
5283static const uint32_t G8RC_NOX0SubClassMask[] = {
5284  0x00014000, 0x00000000,
5285  0x00000000, 0x00000001, // sub_gp8_x0
5286  0x80000000, 0x00000001, // sub_gp8_x1
5287};
5288
5289static const uint32_t SPILLTOVSRRC_and_VSFRCSubClassMask[] = {
5290  0x00608000, 0x00000000,
5291  0x48000000, 0x0001e192, // sub_64
5292  0x00000000, 0x0001e190, // sub_vsx1_then_sub_64
5293  0x00000000, 0x00018000, // sub_pair1_then_sub_64
5294  0x00000000, 0x00018000, // sub_pair1_then_sub_vsx1_then_sub_64
5295};
5296
5297static const uint32_t G8RC_and_G8RC_NOX0SubClassMask[] = {
5298  0x00010000, 0x00000000,
5299  0x00000000, 0x00000001, // sub_gp8_x0
5300  0x80000000, 0x00000001, // sub_gp8_x1
5301};
5302
5303static const uint32_t F8RCSubClassMask[] = {
5304  0x00420000, 0x00000000,
5305  0x20000000, 0x0001e722, // sub_64
5306  0x00000000, 0x0001e720, // sub_vsx1_then_sub_64
5307  0x00000000, 0x0001e600, // sub_pair1_then_sub_64
5308  0x00000000, 0x0001e600, // sub_pair1_then_sub_vsx1_then_sub_64
5309};
5310
5311static const uint32_t SPERCSubClassMask[] = {
5312  0x00140000, 0x00000000,
5313};
5314
5315static const uint32_t VFRCSubClassMask[] = {
5316  0x00280000, 0x00000000,
5317  0x50000000, 0x000000c0, // sub_64
5318  0x00000000, 0x000000c0, // sub_vsx1_then_sub_64
5319};
5320
5321static const uint32_t SPERC_with_sub_32_in_GPRC_NOR0SubClassMask[] = {
5322  0x00100000, 0x00000000,
5323};
5324
5325static const uint32_t SPILLTOVSRRC_and_VFRCSubClassMask[] = {
5326  0x00200000, 0x00000000,
5327  0x40000000, 0x00000080, // sub_64
5328  0x00000000, 0x00000080, // sub_vsx1_then_sub_64
5329};
5330
5331static const uint32_t SPILLTOVSRRC_and_F4RCSubClassMask[] = {
5332  0x00400000, 0x00000000,
5333  0x00000000, 0x0001e102, // sub_64
5334  0x00000000, 0x0001e100, // sub_vsx1_then_sub_64
5335  0x00000000, 0x00018000, // sub_pair1_then_sub_64
5336  0x00000000, 0x00018000, // sub_pair1_then_sub_vsx1_then_sub_64
5337};
5338
5339static const uint32_t CTRRC8SubClassMask[] = {
5340  0x00800000, 0x00000000,
5341};
5342
5343static const uint32_t LR8RCSubClassMask[] = {
5344  0x01000000, 0x00000000,
5345};
5346
5347static const uint32_t DMRROWRCSubClassMask[] = {
5348  0x02000000, 0x00000000,
5349  0x00000000, 0x00061804, // sub_dmrrow0
5350  0x00000000, 0x00061804, // sub_dmrrow1
5351  0x00000000, 0x00061800, // sub_dmrrowp1_then_sub_dmrrow0
5352  0x00000000, 0x00061800, // sub_dmrrowp1_then_sub_dmrrow1
5353  0x00000000, 0x00060000, // sub_wacc_hi_then_sub_dmrrow0
5354  0x00000000, 0x00060000, // sub_wacc_hi_then_sub_dmrrow1
5355  0x00000000, 0x00060000, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
5356  0x00000000, 0x00060000, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
5357  0x00000000, 0x00040000, // sub_dmr1_then_sub_dmrrow0
5358  0x00000000, 0x00040000, // sub_dmr1_then_sub_dmrrow1
5359  0x00000000, 0x00040000, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
5360  0x00000000, 0x00040000, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
5361  0x00000000, 0x00040000, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
5362  0x00000000, 0x00040000, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
5363  0x00000000, 0x00040000, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
5364  0x00000000, 0x00040000, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
5365};
5366
5367static const uint32_t VSRCSubClassMask[] = {
5368  0x7c000000, 0x00000002,
5369  0x00000000, 0x0001e7f8, // sub_vsx0
5370  0x00000000, 0x0001e7f8, // sub_vsx1
5371  0x00000000, 0x0001e600, // sub_pair1_then_sub_vsx0
5372  0x00000000, 0x0001e600, // sub_pair1_then_sub_vsx1
5373};
5374
5375static const uint32_t VSRC_with_sub_64_in_SPILLTOVSRRCSubClassMask[] = {
5376  0x48000000, 0x00000002,
5377  0x00000000, 0x0001e190, // sub_vsx0
5378  0x00000000, 0x0001e190, // sub_vsx1
5379  0x00000000, 0x00018000, // sub_pair1_then_sub_vsx0
5380  0x00000000, 0x00018000, // sub_pair1_then_sub_vsx1
5381};
5382
5383static const uint32_t VRRCSubClassMask[] = {
5384  0x50000000, 0x00000000,
5385  0x00000000, 0x000000c0, // sub_vsx0
5386  0x00000000, 0x000000c0, // sub_vsx1
5387};
5388
5389static const uint32_t VSLRCSubClassMask[] = {
5390  0x20000000, 0x00000002,
5391  0x00000000, 0x0001e720, // sub_vsx0
5392  0x00000000, 0x0001e720, // sub_vsx1
5393  0x00000000, 0x0001e600, // sub_pair1_then_sub_vsx0
5394  0x00000000, 0x0001e600, // sub_pair1_then_sub_vsx1
5395};
5396
5397static const uint32_t VRRC_with_sub_64_in_SPILLTOVSRRCSubClassMask[] = {
5398  0x40000000, 0x00000000,
5399  0x00000000, 0x00000080, // sub_vsx0
5400  0x00000000, 0x00000080, // sub_vsx1
5401};
5402
5403static const uint32_t G8pRCSubClassMask[] = {
5404  0x80000000, 0x00000001,
5405};
5406
5407static const uint32_t G8pRC_with_sub_32_in_GPRC_NOR0SubClassMask[] = {
5408  0x00000000, 0x00000001,
5409};
5410
5411static const uint32_t VSLRC_with_sub_64_in_SPILLTOVSRRCSubClassMask[] = {
5412  0x00000000, 0x00000002,
5413  0x00000000, 0x0001e100, // sub_vsx0
5414  0x00000000, 0x0001e100, // sub_vsx1
5415  0x00000000, 0x00018000, // sub_pair1_then_sub_vsx0
5416  0x00000000, 0x00018000, // sub_pair1_then_sub_vsx1
5417};
5418
5419static const uint32_t DMRROWpRCSubClassMask[] = {
5420  0x00000000, 0x00000004,
5421  0x00000000, 0x00061800, // sub_dmrrowp0
5422  0x00000000, 0x00061800, // sub_dmrrowp1
5423  0x00000000, 0x00060000, // sub_wacc_hi_then_sub_dmrrowp0
5424  0x00000000, 0x00060000, // sub_wacc_hi_then_sub_dmrrowp1
5425  0x00000000, 0x00040000, // sub_dmr1_then_sub_dmrrowp0
5426  0x00000000, 0x00040000, // sub_dmr1_then_sub_dmrrowp1
5427  0x00000000, 0x00040000, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
5428  0x00000000, 0x00040000, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
5429};
5430
5431static const uint32_t VSRpRCSubClassMask[] = {
5432  0x00000000, 0x000001f8,
5433  0x00000000, 0x0001e600, // sub_pair0
5434  0x00000000, 0x0001e600, // sub_pair1
5435};
5436
5437static const uint32_t VSRpRC_with_sub_64_in_SPILLTOVSRRCSubClassMask[] = {
5438  0x00000000, 0x00000190,
5439  0x00000000, 0x0001e000, // sub_pair0
5440  0x00000000, 0x00018000, // sub_pair1
5441};
5442
5443static const uint32_t VSRpRC_with_sub_64_in_F4RCSubClassMask[] = {
5444  0x00000000, 0x00000120,
5445  0x00000000, 0x0001e600, // sub_pair0
5446  0x00000000, 0x0001e600, // sub_pair1
5447};
5448
5449static const uint32_t VSRpRC_with_sub_64_in_VFRCSubClassMask[] = {
5450  0x00000000, 0x000000c0,
5451};
5452
5453static const uint32_t VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCSubClassMask[] = {
5454  0x00000000, 0x00000080,
5455};
5456
5457static const uint32_t VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCSubClassMask[] = {
5458  0x00000000, 0x00000100,
5459  0x00000000, 0x0001e000, // sub_pair0
5460  0x00000000, 0x00018000, // sub_pair1
5461};
5462
5463static const uint32_t ACCRCSubClassMask[] = {
5464  0x00000000, 0x0000a200,
5465};
5466
5467static const uint32_t UACCRCSubClassMask[] = {
5468  0x00000000, 0x00014400,
5469};
5470
5471static const uint32_t WACCRCSubClassMask[] = {
5472  0x00000000, 0x00000800,
5473  0x00000000, 0x00060000, // sub_wacc_lo
5474  0x00000000, 0x00040000, // sub_dmr1_then_sub_wacc_lo
5475};
5476
5477static const uint32_t WACC_HIRCSubClassMask[] = {
5478  0x00000000, 0x00001000,
5479  0x00000000, 0x00060000, // sub_wacc_hi
5480  0x00000000, 0x00040000, // sub_dmr1_then_sub_wacc_hi
5481};
5482
5483static const uint32_t ACCRC_with_sub_64_in_SPILLTOVSRRCSubClassMask[] = {
5484  0x00000000, 0x0000a000,
5485};
5486
5487static const uint32_t UACCRC_with_sub_64_in_SPILLTOVSRRCSubClassMask[] = {
5488  0x00000000, 0x00014000,
5489};
5490
5491static const uint32_t ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCSubClassMask[] = {
5492  0x00000000, 0x00008000,
5493};
5494
5495static const uint32_t UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCSubClassMask[] = {
5496  0x00000000, 0x00010000,
5497};
5498
5499static const uint32_t DMRRCSubClassMask[] = {
5500  0x00000000, 0x00020000,
5501  0x00000000, 0x00040000, // sub_dmr0
5502  0x00000000, 0x00040000, // sub_dmr1
5503};
5504
5505static const uint32_t DMRpRCSubClassMask[] = {
5506  0x00000000, 0x00040000,
5507};
5508
5509static const uint16_t SuperRegIdxSeqs[] = {
5510  /* 0 */ 3, 4, 0,
5511  /* 3 */ 10, 11, 0,
5512  /* 6 */ 14, 15, 0,
5513  /* 9 */ 9, 12, 13, 16, 0,
5514  /* 14 */ 17, 18, 0,
5515  /* 17 */ 2, 21, 0,
5516  /* 20 */ 17, 18, 23, 24, 0,
5517  /* 25 */ 2, 21, 22, 25, 0,
5518  /* 30 */ 2, 10, 11, 21, 22, 25, 0,
5519  /* 37 */ 19, 38, 0,
5520  /* 40 */ 20, 39, 0,
5521  /* 43 */ 7, 8, 30, 31, 36, 37, 44, 45, 0,
5522  /* 52 */ 5, 6, 26, 27, 28, 29, 32, 33, 34, 35, 40, 41, 42, 43, 46, 47, 0,
5523  /* 69 */ 1, 48, 0,
5524};
5525
5526static const TargetRegisterClass *const GPRC_and_GPRC_NOR0Superclasses[] = {
5527  &PPC::GPRCRegClass,
5528  &PPC::GPRC_NOR0RegClass,
5529  nullptr
5530};
5531
5532static const TargetRegisterClass *const F4RCSuperclasses[] = {
5533  &PPC::VSSRCRegClass,
5534  nullptr
5535};
5536
5537static const TargetRegisterClass *const VSFRCSuperclasses[] = {
5538  &PPC::VSSRCRegClass,
5539  nullptr
5540};
5541
5542static const TargetRegisterClass *const G8RCSuperclasses[] = {
5543  &PPC::SPILLTOVSRRCRegClass,
5544  nullptr
5545};
5546
5547static const TargetRegisterClass *const SPILLTOVSRRC_and_VSFRCSuperclasses[] = {
5548  &PPC::VSSRCRegClass,
5549  &PPC::SPILLTOVSRRCRegClass,
5550  &PPC::VSFRCRegClass,
5551  nullptr
5552};
5553
5554static const TargetRegisterClass *const G8RC_and_G8RC_NOX0Superclasses[] = {
5555  &PPC::SPILLTOVSRRCRegClass,
5556  &PPC::G8RCRegClass,
5557  &PPC::G8RC_NOX0RegClass,
5558  nullptr
5559};
5560
5561static const TargetRegisterClass *const F8RCSuperclasses[] = {
5562  &PPC::VSSRCRegClass,
5563  &PPC::F4RCRegClass,
5564  &PPC::VSFRCRegClass,
5565  nullptr
5566};
5567
5568static const TargetRegisterClass *const VFRCSuperclasses[] = {
5569  &PPC::VSSRCRegClass,
5570  &PPC::VSFRCRegClass,
5571  nullptr
5572};
5573
5574static const TargetRegisterClass *const SPERC_with_sub_32_in_GPRC_NOR0Superclasses[] = {
5575  &PPC::SPERCRegClass,
5576  nullptr
5577};
5578
5579static const TargetRegisterClass *const SPILLTOVSRRC_and_VFRCSuperclasses[] = {
5580  &PPC::VSSRCRegClass,
5581  &PPC::SPILLTOVSRRCRegClass,
5582  &PPC::VSFRCRegClass,
5583  &PPC::SPILLTOVSRRC_and_VSFRCRegClass,
5584  &PPC::VFRCRegClass,
5585  nullptr
5586};
5587
5588static const TargetRegisterClass *const SPILLTOVSRRC_and_F4RCSuperclasses[] = {
5589  &PPC::VSSRCRegClass,
5590  &PPC::F4RCRegClass,
5591  &PPC::SPILLTOVSRRCRegClass,
5592  &PPC::VSFRCRegClass,
5593  &PPC::SPILLTOVSRRC_and_VSFRCRegClass,
5594  &PPC::F8RCRegClass,
5595  nullptr
5596};
5597
5598static const TargetRegisterClass *const VSRC_with_sub_64_in_SPILLTOVSRRCSuperclasses[] = {
5599  &PPC::VSRCRegClass,
5600  nullptr
5601};
5602
5603static const TargetRegisterClass *const VRRCSuperclasses[] = {
5604  &PPC::VSRCRegClass,
5605  nullptr
5606};
5607
5608static const TargetRegisterClass *const VSLRCSuperclasses[] = {
5609  &PPC::VSRCRegClass,
5610  nullptr
5611};
5612
5613static const TargetRegisterClass *const VRRC_with_sub_64_in_SPILLTOVSRRCSuperclasses[] = {
5614  &PPC::VSRCRegClass,
5615  &PPC::VSRC_with_sub_64_in_SPILLTOVSRRCRegClass,
5616  &PPC::VRRCRegClass,
5617  nullptr
5618};
5619
5620static const TargetRegisterClass *const G8pRC_with_sub_32_in_GPRC_NOR0Superclasses[] = {
5621  &PPC::G8pRCRegClass,
5622  nullptr
5623};
5624
5625static const TargetRegisterClass *const VSLRC_with_sub_64_in_SPILLTOVSRRCSuperclasses[] = {
5626  &PPC::VSRCRegClass,
5627  &PPC::VSRC_with_sub_64_in_SPILLTOVSRRCRegClass,
5628  &PPC::VSLRCRegClass,
5629  nullptr
5630};
5631
5632static const TargetRegisterClass *const VSRpRC_with_sub_64_in_SPILLTOVSRRCSuperclasses[] = {
5633  &PPC::VSRpRCRegClass,
5634  nullptr
5635};
5636
5637static const TargetRegisterClass *const VSRpRC_with_sub_64_in_F4RCSuperclasses[] = {
5638  &PPC::VSRpRCRegClass,
5639  nullptr
5640};
5641
5642static const TargetRegisterClass *const VSRpRC_with_sub_64_in_VFRCSuperclasses[] = {
5643  &PPC::VSRpRCRegClass,
5644  nullptr
5645};
5646
5647static const TargetRegisterClass *const VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCSuperclasses[] = {
5648  &PPC::VSRpRCRegClass,
5649  &PPC::VSRpRC_with_sub_64_in_SPILLTOVSRRCRegClass,
5650  &PPC::VSRpRC_with_sub_64_in_VFRCRegClass,
5651  nullptr
5652};
5653
5654static const TargetRegisterClass *const VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCSuperclasses[] = {
5655  &PPC::VSRpRCRegClass,
5656  &PPC::VSRpRC_with_sub_64_in_SPILLTOVSRRCRegClass,
5657  &PPC::VSRpRC_with_sub_64_in_F4RCRegClass,
5658  nullptr
5659};
5660
5661static const TargetRegisterClass *const ACCRC_with_sub_64_in_SPILLTOVSRRCSuperclasses[] = {
5662  &PPC::ACCRCRegClass,
5663  nullptr
5664};
5665
5666static const TargetRegisterClass *const UACCRC_with_sub_64_in_SPILLTOVSRRCSuperclasses[] = {
5667  &PPC::UACCRCRegClass,
5668  nullptr
5669};
5670
5671static const TargetRegisterClass *const ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCSuperclasses[] = {
5672  &PPC::ACCRCRegClass,
5673  &PPC::ACCRC_with_sub_64_in_SPILLTOVSRRCRegClass,
5674  nullptr
5675};
5676
5677static const TargetRegisterClass *const UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCSuperclasses[] = {
5678  &PPC::UACCRCRegClass,
5679  &PPC::UACCRC_with_sub_64_in_SPILLTOVSRRCRegClass,
5680  nullptr
5681};
5682
5683
5684static inline unsigned GPRCAltOrderSelect(const MachineFunction &MF) {
5685    return MF.getSubtarget<PPCSubtarget>().getGPRAllocationOrderIdx();
5686  }
5687
5688static ArrayRef<MCPhysReg> GPRCGetRawAllocationOrder(const MachineFunction &MF) {
5689  static const MCPhysReg AltOrder1[] = { PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::R30, PPC::R29, PPC::R28, PPC::R27, PPC::R26, PPC::R25, PPC::R24, PPC::R23, PPC::R22, PPC::R21, PPC::R20, PPC::R19, PPC::R18, PPC::R17, PPC::R16, PPC::R15, PPC::R14, PPC::R13, PPC::R31, PPC::R0, PPC::R1, PPC::FP, PPC::BP, PPC::R2 };
5690  static const MCPhysReg AltOrder2[] = { PPC::R2, PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::R31, PPC::R30, PPC::R29, PPC::R28, PPC::R27, PPC::R26, PPC::R25, PPC::R24, PPC::R23, PPC::R22, PPC::R21, PPC::R20, PPC::R19, PPC::R18, PPC::R17, PPC::R16, PPC::R15, PPC::R14, PPC::R13, PPC::R0, PPC::R1, PPC::FP, PPC::BP };
5691  const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::GPRCRegClassID];
5692  const ArrayRef<MCPhysReg> Order[] = {
5693    ArrayRef(MCR.begin(), MCR.getNumRegs()),
5694    ArrayRef(AltOrder1),
5695    ArrayRef(AltOrder2)
5696  };
5697  const unsigned Select = GPRCAltOrderSelect(MF);
5698  assert(Select < 3);
5699  return Order[Select];
5700}
5701
5702static inline unsigned GPRC_NOR0AltOrderSelect(const MachineFunction &MF) {
5703    return MF.getSubtarget<PPCSubtarget>().getGPRAllocationOrderIdx();
5704  }
5705
5706static ArrayRef<MCPhysReg> GPRC_NOR0GetRawAllocationOrder(const MachineFunction &MF) {
5707  static const MCPhysReg AltOrder1[] = { PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::R30, PPC::R29, PPC::R28, PPC::R27, PPC::R26, PPC::R25, PPC::R24, PPC::R23, PPC::R22, PPC::R21, PPC::R20, PPC::R19, PPC::R18, PPC::R17, PPC::R16, PPC::R15, PPC::R14, PPC::R13, PPC::R31, PPC::R1, PPC::FP, PPC::BP, PPC::ZERO, PPC::R2 };
5708  static const MCPhysReg AltOrder2[] = { PPC::R2, PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::R31, PPC::R30, PPC::R29, PPC::R28, PPC::R27, PPC::R26, PPC::R25, PPC::R24, PPC::R23, PPC::R22, PPC::R21, PPC::R20, PPC::R19, PPC::R18, PPC::R17, PPC::R16, PPC::R15, PPC::R14, PPC::R13, PPC::R1, PPC::FP, PPC::BP, PPC::ZERO };
5709  const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::GPRC_NOR0RegClassID];
5710  const ArrayRef<MCPhysReg> Order[] = {
5711    ArrayRef(MCR.begin(), MCR.getNumRegs()),
5712    ArrayRef(AltOrder1),
5713    ArrayRef(AltOrder2)
5714  };
5715  const unsigned Select = GPRC_NOR0AltOrderSelect(MF);
5716  assert(Select < 3);
5717  return Order[Select];
5718}
5719
5720static inline unsigned GPRC_and_GPRC_NOR0AltOrderSelect(const MachineFunction &MF) {
5721    return MF.getSubtarget<PPCSubtarget>().getGPRAllocationOrderIdx();
5722  }
5723
5724static ArrayRef<MCPhysReg> GPRC_and_GPRC_NOR0GetRawAllocationOrder(const MachineFunction &MF) {
5725  static const MCPhysReg AltOrder1[] = { PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::R30, PPC::R29, PPC::R28, PPC::R27, PPC::R26, PPC::R25, PPC::R24, PPC::R23, PPC::R22, PPC::R21, PPC::R20, PPC::R19, PPC::R18, PPC::R17, PPC::R16, PPC::R15, PPC::R14, PPC::R13, PPC::R31, PPC::R1, PPC::FP, PPC::BP, PPC::R2 };
5726  static const MCPhysReg AltOrder2[] = { PPC::R2, PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::R31, PPC::R30, PPC::R29, PPC::R28, PPC::R27, PPC::R26, PPC::R25, PPC::R24, PPC::R23, PPC::R22, PPC::R21, PPC::R20, PPC::R19, PPC::R18, PPC::R17, PPC::R16, PPC::R15, PPC::R14, PPC::R13, PPC::R1, PPC::FP, PPC::BP };
5727  const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::GPRC_and_GPRC_NOR0RegClassID];
5728  const ArrayRef<MCPhysReg> Order[] = {
5729    ArrayRef(MCR.begin(), MCR.getNumRegs()),
5730    ArrayRef(AltOrder1),
5731    ArrayRef(AltOrder2)
5732  };
5733  const unsigned Select = GPRC_and_GPRC_NOR0AltOrderSelect(MF);
5734  assert(Select < 3);
5735  return Order[Select];
5736}
5737
5738static inline unsigned CRBITRCAltOrderSelect(const MachineFunction &MF) {
5739    return MF.getSubtarget<PPCSubtarget>().isELFv2ABI() &&
5740           MF.getInfo<PPCFunctionInfo>()->isNonVolatileCRDisabled();
5741  }
5742
5743static ArrayRef<MCPhysReg> CRBITRCGetRawAllocationOrder(const MachineFunction &MF) {
5744  static const MCPhysReg AltOrder1[] = { PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN, PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN, PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN, PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN, PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN };
5745  const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::CRBITRCRegClassID];
5746  const ArrayRef<MCPhysReg> Order[] = {
5747    ArrayRef(MCR.begin(), MCR.getNumRegs()),
5748    ArrayRef(AltOrder1)
5749  };
5750  const unsigned Select = CRBITRCAltOrderSelect(MF);
5751  assert(Select < 2);
5752  return Order[Select];
5753}
5754
5755static inline unsigned CRRCAltOrderSelect(const MachineFunction &MF) {
5756    return MF.getSubtarget<PPCSubtarget>().isELFv2ABI() &&
5757           MF.getInfo<PPCFunctionInfo>()->isNonVolatileCRDisabled();
5758  }
5759
5760static ArrayRef<MCPhysReg> CRRCGetRawAllocationOrder(const MachineFunction &MF) {
5761  static const MCPhysReg AltOrder1[] = { PPC::CR0, PPC::CR1, PPC::CR5, PPC::CR6, PPC::CR7 };
5762  const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::CRRCRegClassID];
5763  const ArrayRef<MCPhysReg> Order[] = {
5764    ArrayRef(MCR.begin(), MCR.getNumRegs()),
5765    ArrayRef(AltOrder1)
5766  };
5767  const unsigned Select = CRRCAltOrderSelect(MF);
5768  assert(Select < 2);
5769  return Order[Select];
5770}
5771
5772static inline unsigned G8RCAltOrderSelect(const MachineFunction &MF) {
5773    return MF.getSubtarget<PPCSubtarget>().getGPRAllocationOrderIdx();
5774  }
5775
5776static ArrayRef<MCPhysReg> G8RCGetRawAllocationOrder(const MachineFunction &MF) {
5777  static const MCPhysReg AltOrder1[] = { PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::X30, PPC::X29, PPC::X28, PPC::X27, PPC::X26, PPC::X25, PPC::X24, PPC::X23, PPC::X22, PPC::X21, PPC::X20, PPC::X19, PPC::X18, PPC::X17, PPC::X16, PPC::X15, PPC::X14, PPC::X31, PPC::X13, PPC::X0, PPC::X1, PPC::FP8, PPC::BP8, PPC::X2 };
5778  static const MCPhysReg AltOrder2[] = { PPC::X2, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::X31, PPC::X30, PPC::X29, PPC::X28, PPC::X27, PPC::X26, PPC::X25, PPC::X24, PPC::X23, PPC::X22, PPC::X21, PPC::X20, PPC::X19, PPC::X18, PPC::X17, PPC::X16, PPC::X15, PPC::X14, PPC::X13, PPC::X0, PPC::X1, PPC::FP8, PPC::BP8 };
5779  const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::G8RCRegClassID];
5780  const ArrayRef<MCPhysReg> Order[] = {
5781    ArrayRef(MCR.begin(), MCR.getNumRegs()),
5782    ArrayRef(AltOrder1),
5783    ArrayRef(AltOrder2)
5784  };
5785  const unsigned Select = G8RCAltOrderSelect(MF);
5786  assert(Select < 3);
5787  return Order[Select];
5788}
5789
5790static inline unsigned G8RC_NOX0AltOrderSelect(const MachineFunction &MF) {
5791    return MF.getSubtarget<PPCSubtarget>().getGPRAllocationOrderIdx();
5792  }
5793
5794static ArrayRef<MCPhysReg> G8RC_NOX0GetRawAllocationOrder(const MachineFunction &MF) {
5795  static const MCPhysReg AltOrder1[] = { PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::X30, PPC::X29, PPC::X28, PPC::X27, PPC::X26, PPC::X25, PPC::X24, PPC::X23, PPC::X22, PPC::X21, PPC::X20, PPC::X19, PPC::X18, PPC::X17, PPC::X16, PPC::X15, PPC::X14, PPC::X31, PPC::X13, PPC::X1, PPC::FP8, PPC::BP8, PPC::ZERO8, PPC::X2 };
5796  static const MCPhysReg AltOrder2[] = { PPC::X2, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::X31, PPC::X30, PPC::X29, PPC::X28, PPC::X27, PPC::X26, PPC::X25, PPC::X24, PPC::X23, PPC::X22, PPC::X21, PPC::X20, PPC::X19, PPC::X18, PPC::X17, PPC::X16, PPC::X15, PPC::X14, PPC::X13, PPC::X1, PPC::FP8, PPC::BP8, PPC::ZERO8 };
5797  const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::G8RC_NOX0RegClassID];
5798  const ArrayRef<MCPhysReg> Order[] = {
5799    ArrayRef(MCR.begin(), MCR.getNumRegs()),
5800    ArrayRef(AltOrder1),
5801    ArrayRef(AltOrder2)
5802  };
5803  const unsigned Select = G8RC_NOX0AltOrderSelect(MF);
5804  assert(Select < 3);
5805  return Order[Select];
5806}
5807
5808static inline unsigned G8RC_and_G8RC_NOX0AltOrderSelect(const MachineFunction &MF) {
5809    return MF.getSubtarget<PPCSubtarget>().getGPRAllocationOrderIdx();
5810  }
5811
5812static ArrayRef<MCPhysReg> G8RC_and_G8RC_NOX0GetRawAllocationOrder(const MachineFunction &MF) {
5813  static const MCPhysReg AltOrder1[] = { PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::X30, PPC::X29, PPC::X28, PPC::X27, PPC::X26, PPC::X25, PPC::X24, PPC::X23, PPC::X22, PPC::X21, PPC::X20, PPC::X19, PPC::X18, PPC::X17, PPC::X16, PPC::X15, PPC::X14, PPC::X31, PPC::X13, PPC::X1, PPC::FP8, PPC::BP8, PPC::X2 };
5814  static const MCPhysReg AltOrder2[] = { PPC::X2, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::X31, PPC::X30, PPC::X29, PPC::X28, PPC::X27, PPC::X26, PPC::X25, PPC::X24, PPC::X23, PPC::X22, PPC::X21, PPC::X20, PPC::X19, PPC::X18, PPC::X17, PPC::X16, PPC::X15, PPC::X14, PPC::X13, PPC::X1, PPC::FP8, PPC::BP8 };
5815  const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::G8RC_and_G8RC_NOX0RegClassID];
5816  const ArrayRef<MCPhysReg> Order[] = {
5817    ArrayRef(MCR.begin(), MCR.getNumRegs()),
5818    ArrayRef(AltOrder1),
5819    ArrayRef(AltOrder2)
5820  };
5821  const unsigned Select = G8RC_and_G8RC_NOX0AltOrderSelect(MF);
5822  assert(Select < 3);
5823  return Order[Select];
5824}
5825
5826static inline unsigned G8pRCAltOrderSelect(const MachineFunction &MF) {
5827    return MF.getSubtarget<PPCSubtarget>().is64BitELFABI();
5828  }
5829
5830static ArrayRef<MCPhysReg> G8pRCGetRawAllocationOrder(const MachineFunction &MF) {
5831  static const MCPhysReg AltOrder1[] = { PPC::G8p2, PPC::G8p3, PPC::G8p4, PPC::G8p5, PPC::G8p14, PPC::G8p13, PPC::G8p12, PPC::G8p11, PPC::G8p10, PPC::G8p9, PPC::G8p8, PPC::G8p7, PPC::G8p15, PPC::G8p6, PPC::G8p0, PPC::G8p1 };
5832  const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::G8pRCRegClassID];
5833  const ArrayRef<MCPhysReg> Order[] = {
5834    ArrayRef(MCR.begin(), MCR.getNumRegs()),
5835    ArrayRef(AltOrder1)
5836  };
5837  const unsigned Select = G8pRCAltOrderSelect(MF);
5838  assert(Select < 2);
5839  return Order[Select];
5840}
5841
5842static inline unsigned G8pRC_with_sub_32_in_GPRC_NOR0AltOrderSelect(const MachineFunction &MF) {
5843    return MF.getSubtarget<PPCSubtarget>().is64BitELFABI();
5844  }
5845
5846static ArrayRef<MCPhysReg> G8pRC_with_sub_32_in_GPRC_NOR0GetRawAllocationOrder(const MachineFunction &MF) {
5847  static const MCPhysReg AltOrder1[] = { PPC::G8p2, PPC::G8p3, PPC::G8p4, PPC::G8p5, PPC::G8p14, PPC::G8p13, PPC::G8p12, PPC::G8p11, PPC::G8p10, PPC::G8p9, PPC::G8p8, PPC::G8p7, PPC::G8p15, PPC::G8p6, PPC::G8p1 };
5848  const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::G8pRC_with_sub_32_in_GPRC_NOR0RegClassID];
5849  const ArrayRef<MCPhysReg> Order[] = {
5850    ArrayRef(MCR.begin(), MCR.getNumRegs()),
5851    ArrayRef(AltOrder1)
5852  };
5853  const unsigned Select = G8pRC_with_sub_32_in_GPRC_NOR0AltOrderSelect(MF);
5854  assert(Select < 2);
5855  return Order[Select];
5856}
5857
5858namespace PPC {   // Register class instances
5859  extern const TargetRegisterClass VSSRCRegClass = {
5860    &PPCMCRegisterClasses[VSSRCRegClassID],
5861    VSSRCSubClassMask,
5862    SuperRegIdxSeqs + 25,
5863    LaneBitmask(0x0000000000000001),
5864    0,
5865    false,
5866    0x00, /* TSFlags */
5867    false, /* HasDisjunctSubRegs */
5868    false, /* CoveredBySubRegs */
5869    NullRegClasses,
5870    nullptr
5871  };
5872
5873  extern const TargetRegisterClass GPRCRegClass = {
5874    &PPCMCRegisterClasses[GPRCRegClassID],
5875    GPRCSubClassMask,
5876    SuperRegIdxSeqs + 69,
5877    LaneBitmask(0x0000000000000001),
5878    0,
5879    false,
5880    0x00, /* TSFlags */
5881    false, /* HasDisjunctSubRegs */
5882    false, /* CoveredBySubRegs */
5883    NullRegClasses,
5884    GPRCGetRawAllocationOrder
5885  };
5886
5887  extern const TargetRegisterClass GPRC_NOR0RegClass = {
5888    &PPCMCRegisterClasses[GPRC_NOR0RegClassID],
5889    GPRC_NOR0SubClassMask,
5890    SuperRegIdxSeqs + 69,
5891    LaneBitmask(0x0000000000000001),
5892    0,
5893    false,
5894    0x00, /* TSFlags */
5895    false, /* HasDisjunctSubRegs */
5896    false, /* CoveredBySubRegs */
5897    NullRegClasses,
5898    GPRC_NOR0GetRawAllocationOrder
5899  };
5900
5901  extern const TargetRegisterClass GPRC_and_GPRC_NOR0RegClass = {
5902    &PPCMCRegisterClasses[GPRC_and_GPRC_NOR0RegClassID],
5903    GPRC_and_GPRC_NOR0SubClassMask,
5904    SuperRegIdxSeqs + 69,
5905    LaneBitmask(0x0000000000000001),
5906    0,
5907    false,
5908    0x00, /* TSFlags */
5909    false, /* HasDisjunctSubRegs */
5910    false, /* CoveredBySubRegs */
5911    GPRC_and_GPRC_NOR0Superclasses,
5912    GPRC_and_GPRC_NOR0GetRawAllocationOrder
5913  };
5914
5915  extern const TargetRegisterClass CRBITRCRegClass = {
5916    &PPCMCRegisterClasses[CRBITRCRegClassID],
5917    CRBITRCSubClassMask,
5918    SuperRegIdxSeqs + 9,
5919    LaneBitmask(0x0000000000000001),
5920    0,
5921    false,
5922    0x00, /* TSFlags */
5923    false, /* HasDisjunctSubRegs */
5924    false, /* CoveredBySubRegs */
5925    NullRegClasses,
5926    CRBITRCGetRawAllocationOrder
5927  };
5928
5929  extern const TargetRegisterClass F4RCRegClass = {
5930    &PPCMCRegisterClasses[F4RCRegClassID],
5931    F4RCSubClassMask,
5932    SuperRegIdxSeqs + 25,
5933    LaneBitmask(0x0000000000000001),
5934    0,
5935    false,
5936    0x00, /* TSFlags */
5937    false, /* HasDisjunctSubRegs */
5938    false, /* CoveredBySubRegs */
5939    F4RCSuperclasses,
5940    nullptr
5941  };
5942
5943  extern const TargetRegisterClass CRRCRegClass = {
5944    &PPCMCRegisterClasses[CRRCRegClassID],
5945    CRRCSubClassMask,
5946    SuperRegIdxSeqs + 2,
5947    LaneBitmask(0x00000000000000F0),
5948    0,
5949    false,
5950    0x00, /* TSFlags */
5951    true, /* HasDisjunctSubRegs */
5952    false, /* CoveredBySubRegs */
5953    NullRegClasses,
5954    CRRCGetRawAllocationOrder
5955  };
5956
5957  extern const TargetRegisterClass CARRYRCRegClass = {
5958    &PPCMCRegisterClasses[CARRYRCRegClassID],
5959    CARRYRCSubClassMask,
5960    SuperRegIdxSeqs + 2,
5961    LaneBitmask(0x0000000000000001),
5962    0,
5963    false,
5964    0x00, /* TSFlags */
5965    false, /* HasDisjunctSubRegs */
5966    false, /* CoveredBySubRegs */
5967    NullRegClasses,
5968    nullptr
5969  };
5970
5971  extern const TargetRegisterClass CTRRCRegClass = {
5972    &PPCMCRegisterClasses[CTRRCRegClassID],
5973    CTRRCSubClassMask,
5974    SuperRegIdxSeqs + 2,
5975    LaneBitmask(0x0000000000000001),
5976    0,
5977    false,
5978    0x00, /* TSFlags */
5979    false, /* HasDisjunctSubRegs */
5980    false, /* CoveredBySubRegs */
5981    NullRegClasses,
5982    nullptr
5983  };
5984
5985  extern const TargetRegisterClass LRRCRegClass = {
5986    &PPCMCRegisterClasses[LRRCRegClassID],
5987    LRRCSubClassMask,
5988    SuperRegIdxSeqs + 2,
5989    LaneBitmask(0x0000000000000001),
5990    0,
5991    false,
5992    0x00, /* TSFlags */
5993    false, /* HasDisjunctSubRegs */
5994    false, /* CoveredBySubRegs */
5995    NullRegClasses,
5996    nullptr
5997  };
5998
5999  extern const TargetRegisterClass VRSAVERCRegClass = {
6000    &PPCMCRegisterClasses[VRSAVERCRegClassID],
6001    VRSAVERCSubClassMask,
6002    SuperRegIdxSeqs + 2,
6003    LaneBitmask(0x0000000000000001),
6004    0,
6005    false,
6006    0x00, /* TSFlags */
6007    false, /* HasDisjunctSubRegs */
6008    false, /* CoveredBySubRegs */
6009    NullRegClasses,
6010    nullptr
6011  };
6012
6013  extern const TargetRegisterClass SPILLTOVSRRCRegClass = {
6014    &PPCMCRegisterClasses[SPILLTOVSRRCRegClassID],
6015    SPILLTOVSRRCSubClassMask,
6016    SuperRegIdxSeqs + 30,
6017    LaneBitmask(0x0000000000000001),
6018    0,
6019    false,
6020    0x00, /* TSFlags */
6021    false, /* HasDisjunctSubRegs */
6022    false, /* CoveredBySubRegs */
6023    NullRegClasses,
6024    nullptr
6025  };
6026
6027  extern const TargetRegisterClass VSFRCRegClass = {
6028    &PPCMCRegisterClasses[VSFRCRegClassID],
6029    VSFRCSubClassMask,
6030    SuperRegIdxSeqs + 25,
6031    LaneBitmask(0x0000000000000001),
6032    0,
6033    false,
6034    0x00, /* TSFlags */
6035    false, /* HasDisjunctSubRegs */
6036    false, /* CoveredBySubRegs */
6037    VSFRCSuperclasses,
6038    nullptr
6039  };
6040
6041  extern const TargetRegisterClass G8RCRegClass = {
6042    &PPCMCRegisterClasses[G8RCRegClassID],
6043    G8RCSubClassMask,
6044    SuperRegIdxSeqs + 3,
6045    LaneBitmask(0x0000000000000001),
6046    0,
6047    false,
6048    0x00, /* TSFlags */
6049    false, /* HasDisjunctSubRegs */
6050    false, /* CoveredBySubRegs */
6051    G8RCSuperclasses,
6052    G8RCGetRawAllocationOrder
6053  };
6054
6055  extern const TargetRegisterClass G8RC_NOX0RegClass = {
6056    &PPCMCRegisterClasses[G8RC_NOX0RegClassID],
6057    G8RC_NOX0SubClassMask,
6058    SuperRegIdxSeqs + 3,
6059    LaneBitmask(0x0000000000000001),
6060    0,
6061    false,
6062    0x00, /* TSFlags */
6063    false, /* HasDisjunctSubRegs */
6064    false, /* CoveredBySubRegs */
6065    NullRegClasses,
6066    G8RC_NOX0GetRawAllocationOrder
6067  };
6068
6069  extern const TargetRegisterClass SPILLTOVSRRC_and_VSFRCRegClass = {
6070    &PPCMCRegisterClasses[SPILLTOVSRRC_and_VSFRCRegClassID],
6071    SPILLTOVSRRC_and_VSFRCSubClassMask,
6072    SuperRegIdxSeqs + 25,
6073    LaneBitmask(0x0000000000000001),
6074    0,
6075    false,
6076    0x00, /* TSFlags */
6077    false, /* HasDisjunctSubRegs */
6078    false, /* CoveredBySubRegs */
6079    SPILLTOVSRRC_and_VSFRCSuperclasses,
6080    nullptr
6081  };
6082
6083  extern const TargetRegisterClass G8RC_and_G8RC_NOX0RegClass = {
6084    &PPCMCRegisterClasses[G8RC_and_G8RC_NOX0RegClassID],
6085    G8RC_and_G8RC_NOX0SubClassMask,
6086    SuperRegIdxSeqs + 3,
6087    LaneBitmask(0x0000000000000001),
6088    0,
6089    false,
6090    0x00, /* TSFlags */
6091    false, /* HasDisjunctSubRegs */
6092    false, /* CoveredBySubRegs */
6093    G8RC_and_G8RC_NOX0Superclasses,
6094    G8RC_and_G8RC_NOX0GetRawAllocationOrder
6095  };
6096
6097  extern const TargetRegisterClass F8RCRegClass = {
6098    &PPCMCRegisterClasses[F8RCRegClassID],
6099    F8RCSubClassMask,
6100    SuperRegIdxSeqs + 25,
6101    LaneBitmask(0x0000000000000001),
6102    0,
6103    false,
6104    0x00, /* TSFlags */
6105    false, /* HasDisjunctSubRegs */
6106    false, /* CoveredBySubRegs */
6107    F8RCSuperclasses,
6108    nullptr
6109  };
6110
6111  extern const TargetRegisterClass SPERCRegClass = {
6112    &PPCMCRegisterClasses[SPERCRegClassID],
6113    SPERCSubClassMask,
6114    SuperRegIdxSeqs + 2,
6115    LaneBitmask(0x0000000000000001),
6116    0,
6117    false,
6118    0x00, /* TSFlags */
6119    false, /* HasDisjunctSubRegs */
6120    false, /* CoveredBySubRegs */
6121    NullRegClasses,
6122    nullptr
6123  };
6124
6125  extern const TargetRegisterClass VFRCRegClass = {
6126    &PPCMCRegisterClasses[VFRCRegClassID],
6127    VFRCSubClassMask,
6128    SuperRegIdxSeqs + 17,
6129    LaneBitmask(0x0000000000000001),
6130    0,
6131    false,
6132    0x00, /* TSFlags */
6133    false, /* HasDisjunctSubRegs */
6134    false, /* CoveredBySubRegs */
6135    VFRCSuperclasses,
6136    nullptr
6137  };
6138
6139  extern const TargetRegisterClass SPERC_with_sub_32_in_GPRC_NOR0RegClass = {
6140    &PPCMCRegisterClasses[SPERC_with_sub_32_in_GPRC_NOR0RegClassID],
6141    SPERC_with_sub_32_in_GPRC_NOR0SubClassMask,
6142    SuperRegIdxSeqs + 2,
6143    LaneBitmask(0x0000000000000001),
6144    0,
6145    false,
6146    0x00, /* TSFlags */
6147    false, /* HasDisjunctSubRegs */
6148    false, /* CoveredBySubRegs */
6149    SPERC_with_sub_32_in_GPRC_NOR0Superclasses,
6150    nullptr
6151  };
6152
6153  extern const TargetRegisterClass SPILLTOVSRRC_and_VFRCRegClass = {
6154    &PPCMCRegisterClasses[SPILLTOVSRRC_and_VFRCRegClassID],
6155    SPILLTOVSRRC_and_VFRCSubClassMask,
6156    SuperRegIdxSeqs + 17,
6157    LaneBitmask(0x0000000000000001),
6158    0,
6159    false,
6160    0x00, /* TSFlags */
6161    false, /* HasDisjunctSubRegs */
6162    false, /* CoveredBySubRegs */
6163    SPILLTOVSRRC_and_VFRCSuperclasses,
6164    nullptr
6165  };
6166
6167  extern const TargetRegisterClass SPILLTOVSRRC_and_F4RCRegClass = {
6168    &PPCMCRegisterClasses[SPILLTOVSRRC_and_F4RCRegClassID],
6169    SPILLTOVSRRC_and_F4RCSubClassMask,
6170    SuperRegIdxSeqs + 25,
6171    LaneBitmask(0x0000000000000001),
6172    0,
6173    false,
6174    0x00, /* TSFlags */
6175    false, /* HasDisjunctSubRegs */
6176    false, /* CoveredBySubRegs */
6177    SPILLTOVSRRC_and_F4RCSuperclasses,
6178    nullptr
6179  };
6180
6181  extern const TargetRegisterClass CTRRC8RegClass = {
6182    &PPCMCRegisterClasses[CTRRC8RegClassID],
6183    CTRRC8SubClassMask,
6184    SuperRegIdxSeqs + 2,
6185    LaneBitmask(0x0000000000000001),
6186    0,
6187    false,
6188    0x00, /* TSFlags */
6189    false, /* HasDisjunctSubRegs */
6190    false, /* CoveredBySubRegs */
6191    NullRegClasses,
6192    nullptr
6193  };
6194
6195  extern const TargetRegisterClass LR8RCRegClass = {
6196    &PPCMCRegisterClasses[LR8RCRegClassID],
6197    LR8RCSubClassMask,
6198    SuperRegIdxSeqs + 2,
6199    LaneBitmask(0x0000000000000001),
6200    0,
6201    false,
6202    0x00, /* TSFlags */
6203    false, /* HasDisjunctSubRegs */
6204    false, /* CoveredBySubRegs */
6205    NullRegClasses,
6206    nullptr
6207  };
6208
6209  extern const TargetRegisterClass DMRROWRCRegClass = {
6210    &PPCMCRegisterClasses[DMRROWRCRegClassID],
6211    DMRROWRCSubClassMask,
6212    SuperRegIdxSeqs + 52,
6213    LaneBitmask(0x0000000000000001),
6214    0,
6215    false,
6216    0x00, /* TSFlags */
6217    false, /* HasDisjunctSubRegs */
6218    false, /* CoveredBySubRegs */
6219    NullRegClasses,
6220    nullptr
6221  };
6222
6223  extern const TargetRegisterClass VSRCRegClass = {
6224    &PPCMCRegisterClasses[VSRCRegClassID],
6225    VSRCSubClassMask,
6226    SuperRegIdxSeqs + 20,
6227    LaneBitmask(0x0000000000000002),
6228    0,
6229    false,
6230    0x00, /* TSFlags */
6231    false, /* HasDisjunctSubRegs */
6232    false, /* CoveredBySubRegs */
6233    NullRegClasses,
6234    nullptr
6235  };
6236
6237  extern const TargetRegisterClass VSRC_with_sub_64_in_SPILLTOVSRRCRegClass = {
6238    &PPCMCRegisterClasses[VSRC_with_sub_64_in_SPILLTOVSRRCRegClassID],
6239    VSRC_with_sub_64_in_SPILLTOVSRRCSubClassMask,
6240    SuperRegIdxSeqs + 20,
6241    LaneBitmask(0x0000000000000002),
6242    0,
6243    false,
6244    0x00, /* TSFlags */
6245    false, /* HasDisjunctSubRegs */
6246    false, /* CoveredBySubRegs */
6247    VSRC_with_sub_64_in_SPILLTOVSRRCSuperclasses,
6248    nullptr
6249  };
6250
6251  extern const TargetRegisterClass VRRCRegClass = {
6252    &PPCMCRegisterClasses[VRRCRegClassID],
6253    VRRCSubClassMask,
6254    SuperRegIdxSeqs + 14,
6255    LaneBitmask(0x0000000000000002),
6256    0,
6257    false,
6258    0x00, /* TSFlags */
6259    false, /* HasDisjunctSubRegs */
6260    false, /* CoveredBySubRegs */
6261    VRRCSuperclasses,
6262    nullptr
6263  };
6264
6265  extern const TargetRegisterClass VSLRCRegClass = {
6266    &PPCMCRegisterClasses[VSLRCRegClassID],
6267    VSLRCSubClassMask,
6268    SuperRegIdxSeqs + 20,
6269    LaneBitmask(0x0000000000000002),
6270    0,
6271    false,
6272    0x00, /* TSFlags */
6273    false, /* HasDisjunctSubRegs */
6274    false, /* CoveredBySubRegs */
6275    VSLRCSuperclasses,
6276    nullptr
6277  };
6278
6279  extern const TargetRegisterClass VRRC_with_sub_64_in_SPILLTOVSRRCRegClass = {
6280    &PPCMCRegisterClasses[VRRC_with_sub_64_in_SPILLTOVSRRCRegClassID],
6281    VRRC_with_sub_64_in_SPILLTOVSRRCSubClassMask,
6282    SuperRegIdxSeqs + 14,
6283    LaneBitmask(0x0000000000000002),
6284    0,
6285    false,
6286    0x00, /* TSFlags */
6287    false, /* HasDisjunctSubRegs */
6288    false, /* CoveredBySubRegs */
6289    VRRC_with_sub_64_in_SPILLTOVSRRCSuperclasses,
6290    nullptr
6291  };
6292
6293  extern const TargetRegisterClass G8pRCRegClass = {
6294    &PPCMCRegisterClasses[G8pRCRegClassID],
6295    G8pRCSubClassMask,
6296    SuperRegIdxSeqs + 2,
6297    LaneBitmask(0x0000000002000001),
6298    0,
6299    false,
6300    0x00, /* TSFlags */
6301    true, /* HasDisjunctSubRegs */
6302    false, /* CoveredBySubRegs */
6303    NullRegClasses,
6304    G8pRCGetRawAllocationOrder
6305  };
6306
6307  extern const TargetRegisterClass G8pRC_with_sub_32_in_GPRC_NOR0RegClass = {
6308    &PPCMCRegisterClasses[G8pRC_with_sub_32_in_GPRC_NOR0RegClassID],
6309    G8pRC_with_sub_32_in_GPRC_NOR0SubClassMask,
6310    SuperRegIdxSeqs + 2,
6311    LaneBitmask(0x0000000002000001),
6312    0,
6313    false,
6314    0x00, /* TSFlags */
6315    true, /* HasDisjunctSubRegs */
6316    false, /* CoveredBySubRegs */
6317    G8pRC_with_sub_32_in_GPRC_NOR0Superclasses,
6318    G8pRC_with_sub_32_in_GPRC_NOR0GetRawAllocationOrder
6319  };
6320
6321  extern const TargetRegisterClass VSLRC_with_sub_64_in_SPILLTOVSRRCRegClass = {
6322    &PPCMCRegisterClasses[VSLRC_with_sub_64_in_SPILLTOVSRRCRegClassID],
6323    VSLRC_with_sub_64_in_SPILLTOVSRRCSubClassMask,
6324    SuperRegIdxSeqs + 20,
6325    LaneBitmask(0x0000000000000002),
6326    0,
6327    false,
6328    0x00, /* TSFlags */
6329    false, /* HasDisjunctSubRegs */
6330    false, /* CoveredBySubRegs */
6331    VSLRC_with_sub_64_in_SPILLTOVSRRCSuperclasses,
6332    nullptr
6333  };
6334
6335  extern const TargetRegisterClass DMRROWpRCRegClass = {
6336    &PPCMCRegisterClasses[DMRROWpRCRegClassID],
6337    DMRROWpRCSubClassMask,
6338    SuperRegIdxSeqs + 43,
6339    LaneBitmask(0x000000000000000C),
6340    0,
6341    false,
6342    0x00, /* TSFlags */
6343    true, /* HasDisjunctSubRegs */
6344    false, /* CoveredBySubRegs */
6345    NullRegClasses,
6346    nullptr
6347  };
6348
6349  extern const TargetRegisterClass VSRpRCRegClass = {
6350    &PPCMCRegisterClasses[VSRpRCRegClassID],
6351    VSRpRCSubClassMask,
6352    SuperRegIdxSeqs + 6,
6353    LaneBitmask(0x0000000000000102),
6354    2,
6355    false,
6356    0x00, /* TSFlags */
6357    true, /* HasDisjunctSubRegs */
6358    false, /* CoveredBySubRegs */
6359    NullRegClasses,
6360    nullptr
6361  };
6362
6363  extern const TargetRegisterClass VSRpRC_with_sub_64_in_SPILLTOVSRRCRegClass = {
6364    &PPCMCRegisterClasses[VSRpRC_with_sub_64_in_SPILLTOVSRRCRegClassID],
6365    VSRpRC_with_sub_64_in_SPILLTOVSRRCSubClassMask,
6366    SuperRegIdxSeqs + 6,
6367    LaneBitmask(0x0000000000000102),
6368    2,
6369    false,
6370    0x00, /* TSFlags */
6371    true, /* HasDisjunctSubRegs */
6372    false, /* CoveredBySubRegs */
6373    VSRpRC_with_sub_64_in_SPILLTOVSRRCSuperclasses,
6374    nullptr
6375  };
6376
6377  extern const TargetRegisterClass VSRpRC_with_sub_64_in_F4RCRegClass = {
6378    &PPCMCRegisterClasses[VSRpRC_with_sub_64_in_F4RCRegClassID],
6379    VSRpRC_with_sub_64_in_F4RCSubClassMask,
6380    SuperRegIdxSeqs + 6,
6381    LaneBitmask(0x0000000000000102),
6382    2,
6383    false,
6384    0x00, /* TSFlags */
6385    true, /* HasDisjunctSubRegs */
6386    false, /* CoveredBySubRegs */
6387    VSRpRC_with_sub_64_in_F4RCSuperclasses,
6388    nullptr
6389  };
6390
6391  extern const TargetRegisterClass VSRpRC_with_sub_64_in_VFRCRegClass = {
6392    &PPCMCRegisterClasses[VSRpRC_with_sub_64_in_VFRCRegClassID],
6393    VSRpRC_with_sub_64_in_VFRCSubClassMask,
6394    SuperRegIdxSeqs + 2,
6395    LaneBitmask(0x0000000000000102),
6396    2,
6397    false,
6398    0x00, /* TSFlags */
6399    true, /* HasDisjunctSubRegs */
6400    false, /* CoveredBySubRegs */
6401    VSRpRC_with_sub_64_in_VFRCSuperclasses,
6402    nullptr
6403  };
6404
6405  extern const TargetRegisterClass VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCRegClass = {
6406    &PPCMCRegisterClasses[VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCRegClassID],
6407    VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCSubClassMask,
6408    SuperRegIdxSeqs + 2,
6409    LaneBitmask(0x0000000000000102),
6410    2,
6411    false,
6412    0x00, /* TSFlags */
6413    true, /* HasDisjunctSubRegs */
6414    false, /* CoveredBySubRegs */
6415    VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCSuperclasses,
6416    nullptr
6417  };
6418
6419  extern const TargetRegisterClass VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCRegClass = {
6420    &PPCMCRegisterClasses[VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCRegClassID],
6421    VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCSubClassMask,
6422    SuperRegIdxSeqs + 6,
6423    LaneBitmask(0x0000000000000102),
6424    2,
6425    false,
6426    0x00, /* TSFlags */
6427    true, /* HasDisjunctSubRegs */
6428    false, /* CoveredBySubRegs */
6429    VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCSuperclasses,
6430    nullptr
6431  };
6432
6433  extern const TargetRegisterClass ACCRCRegClass = {
6434    &PPCMCRegisterClasses[ACCRCRegClassID],
6435    ACCRCSubClassMask,
6436    SuperRegIdxSeqs + 2,
6437    LaneBitmask(0x0000000000000702),
6438    31,
6439    true,
6440    0x00, /* TSFlags */
6441    true, /* HasDisjunctSubRegs */
6442    false, /* CoveredBySubRegs */
6443    NullRegClasses,
6444    nullptr
6445  };
6446
6447  extern const TargetRegisterClass UACCRCRegClass = {
6448    &PPCMCRegisterClasses[UACCRCRegClassID],
6449    UACCRCSubClassMask,
6450    SuperRegIdxSeqs + 2,
6451    LaneBitmask(0x0000000000000702),
6452    4,
6453    true,
6454    0x00, /* TSFlags */
6455    true, /* HasDisjunctSubRegs */
6456    false, /* CoveredBySubRegs */
6457    NullRegClasses,
6458    nullptr
6459  };
6460
6461  extern const TargetRegisterClass WACCRCRegClass = {
6462    &PPCMCRegisterClasses[WACCRCRegClassID],
6463    WACCRCSubClassMask,
6464    SuperRegIdxSeqs + 40,
6465    LaneBitmask(0x000000000000180C),
6466    0,
6467    false,
6468    0x00, /* TSFlags */
6469    true, /* HasDisjunctSubRegs */
6470    false, /* CoveredBySubRegs */
6471    NullRegClasses,
6472    nullptr
6473  };
6474
6475  extern const TargetRegisterClass WACC_HIRCRegClass = {
6476    &PPCMCRegisterClasses[WACC_HIRCRegClassID],
6477    WACC_HIRCSubClassMask,
6478    SuperRegIdxSeqs + 37,
6479    LaneBitmask(0x000000000000180C),
6480    0,
6481    false,
6482    0x00, /* TSFlags */
6483    true, /* HasDisjunctSubRegs */
6484    false, /* CoveredBySubRegs */
6485    NullRegClasses,
6486    nullptr
6487  };
6488
6489  extern const TargetRegisterClass ACCRC_with_sub_64_in_SPILLTOVSRRCRegClass = {
6490    &PPCMCRegisterClasses[ACCRC_with_sub_64_in_SPILLTOVSRRCRegClassID],
6491    ACCRC_with_sub_64_in_SPILLTOVSRRCSubClassMask,
6492    SuperRegIdxSeqs + 2,
6493    LaneBitmask(0x0000000000000702),
6494    31,
6495    true,
6496    0x00, /* TSFlags */
6497    true, /* HasDisjunctSubRegs */
6498    false, /* CoveredBySubRegs */
6499    ACCRC_with_sub_64_in_SPILLTOVSRRCSuperclasses,
6500    nullptr
6501  };
6502
6503  extern const TargetRegisterClass UACCRC_with_sub_64_in_SPILLTOVSRRCRegClass = {
6504    &PPCMCRegisterClasses[UACCRC_with_sub_64_in_SPILLTOVSRRCRegClassID],
6505    UACCRC_with_sub_64_in_SPILLTOVSRRCSubClassMask,
6506    SuperRegIdxSeqs + 2,
6507    LaneBitmask(0x0000000000000702),
6508    4,
6509    true,
6510    0x00, /* TSFlags */
6511    true, /* HasDisjunctSubRegs */
6512    false, /* CoveredBySubRegs */
6513    UACCRC_with_sub_64_in_SPILLTOVSRRCSuperclasses,
6514    nullptr
6515  };
6516
6517  extern const TargetRegisterClass ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCRegClass = {
6518    &PPCMCRegisterClasses[ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCRegClassID],
6519    ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCSubClassMask,
6520    SuperRegIdxSeqs + 2,
6521    LaneBitmask(0x0000000000000702),
6522    31,
6523    true,
6524    0x00, /* TSFlags */
6525    true, /* HasDisjunctSubRegs */
6526    false, /* CoveredBySubRegs */
6527    ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCSuperclasses,
6528    nullptr
6529  };
6530
6531  extern const TargetRegisterClass UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCRegClass = {
6532    &PPCMCRegisterClasses[UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCRegClassID],
6533    UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCSubClassMask,
6534    SuperRegIdxSeqs + 2,
6535    LaneBitmask(0x0000000000000702),
6536    4,
6537    true,
6538    0x00, /* TSFlags */
6539    true, /* HasDisjunctSubRegs */
6540    false, /* CoveredBySubRegs */
6541    UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCSuperclasses,
6542    nullptr
6543  };
6544
6545  extern const TargetRegisterClass DMRRCRegClass = {
6546    &PPCMCRegisterClasses[DMRRCRegClassID],
6547    DMRRCSubClassMask,
6548    SuperRegIdxSeqs + 0,
6549    LaneBitmask(0x000000000001F80C),
6550    0,
6551    false,
6552    0x00, /* TSFlags */
6553    true, /* HasDisjunctSubRegs */
6554    false, /* CoveredBySubRegs */
6555    NullRegClasses,
6556    nullptr
6557  };
6558
6559  extern const TargetRegisterClass DMRpRCRegClass = {
6560    &PPCMCRegisterClasses[DMRpRCRegClassID],
6561    DMRpRCSubClassMask,
6562    SuperRegIdxSeqs + 2,
6563    LaneBitmask(0x0000000001FFF80C),
6564    0,
6565    false,
6566    0x00, /* TSFlags */
6567    true, /* HasDisjunctSubRegs */
6568    false, /* CoveredBySubRegs */
6569    NullRegClasses,
6570    nullptr
6571  };
6572
6573} // end namespace PPC
6574
6575namespace {
6576  const TargetRegisterClass *const RegisterClasses[] = {
6577    &PPC::VSSRCRegClass,
6578    &PPC::GPRCRegClass,
6579    &PPC::GPRC_NOR0RegClass,
6580    &PPC::GPRC_and_GPRC_NOR0RegClass,
6581    &PPC::CRBITRCRegClass,
6582    &PPC::F4RCRegClass,
6583    &PPC::CRRCRegClass,
6584    &PPC::CARRYRCRegClass,
6585    &PPC::CTRRCRegClass,
6586    &PPC::LRRCRegClass,
6587    &PPC::VRSAVERCRegClass,
6588    &PPC::SPILLTOVSRRCRegClass,
6589    &PPC::VSFRCRegClass,
6590    &PPC::G8RCRegClass,
6591    &PPC::G8RC_NOX0RegClass,
6592    &PPC::SPILLTOVSRRC_and_VSFRCRegClass,
6593    &PPC::G8RC_and_G8RC_NOX0RegClass,
6594    &PPC::F8RCRegClass,
6595    &PPC::SPERCRegClass,
6596    &PPC::VFRCRegClass,
6597    &PPC::SPERC_with_sub_32_in_GPRC_NOR0RegClass,
6598    &PPC::SPILLTOVSRRC_and_VFRCRegClass,
6599    &PPC::SPILLTOVSRRC_and_F4RCRegClass,
6600    &PPC::CTRRC8RegClass,
6601    &PPC::LR8RCRegClass,
6602    &PPC::DMRROWRCRegClass,
6603    &PPC::VSRCRegClass,
6604    &PPC::VSRC_with_sub_64_in_SPILLTOVSRRCRegClass,
6605    &PPC::VRRCRegClass,
6606    &PPC::VSLRCRegClass,
6607    &PPC::VRRC_with_sub_64_in_SPILLTOVSRRCRegClass,
6608    &PPC::G8pRCRegClass,
6609    &PPC::G8pRC_with_sub_32_in_GPRC_NOR0RegClass,
6610    &PPC::VSLRC_with_sub_64_in_SPILLTOVSRRCRegClass,
6611    &PPC::DMRROWpRCRegClass,
6612    &PPC::VSRpRCRegClass,
6613    &PPC::VSRpRC_with_sub_64_in_SPILLTOVSRRCRegClass,
6614    &PPC::VSRpRC_with_sub_64_in_F4RCRegClass,
6615    &PPC::VSRpRC_with_sub_64_in_VFRCRegClass,
6616    &PPC::VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCRegClass,
6617    &PPC::VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCRegClass,
6618    &PPC::ACCRCRegClass,
6619    &PPC::UACCRCRegClass,
6620    &PPC::WACCRCRegClass,
6621    &PPC::WACC_HIRCRegClass,
6622    &PPC::ACCRC_with_sub_64_in_SPILLTOVSRRCRegClass,
6623    &PPC::UACCRC_with_sub_64_in_SPILLTOVSRRCRegClass,
6624    &PPC::ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCRegClass,
6625    &PPC::UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCRegClass,
6626    &PPC::DMRRCRegClass,
6627    &PPC::DMRpRCRegClass,
6628  };
6629} // end anonymous namespace
6630
6631static const uint8_t CostPerUseTable[] = {
66320, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
6633
6634
6635static const bool InAllocatableClassTable[] = {
6636false, true, true, false, true, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
6637
6638
6639static const TargetRegisterInfoDesc PPCRegInfoDesc = { // Extra Descriptors
6640CostPerUseTable, 1, InAllocatableClassTable};
6641
6642unsigned PPCGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
6643  static const uint8_t RowMap[48] = {
6644    0, 0, 0, 1, 0, 0, 0, 2, 0, 0, 1, 0, 0, 0, 1, 0, 0, 2, 3, 0, 0, 0, 1, 3, 0, 0, 0, 0, 0, 3, 4, 0, 0, 0, 0, 1, 5, 6, 1, 0, 0, 0, 0, 6, 7, 0, 0, 0,
6645  };
6646  static const uint8_t Rows[8][48] = {
6647    { PPC::sub_32, PPC::sub_64, 0, 0, PPC::sub_dmrrow0, PPC::sub_dmrrow1, PPC::sub_dmrrowp0, PPC::sub_dmrrowp1, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_vsx0, PPC::sub_vsx1, PPC::sub_wacc_hi, PPC::sub_wacc_lo, PPC::sub_vsx1_then_sub_64, 0, 0, 0, 0, PPC::sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmrrowp1_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrowp0, PPC::sub_wacc_hi_then_sub_dmrrowp1, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
6648    { PPC::sub_gp8_x1_then_sub_32, PPC::sub_pair1_then_sub_64, 0, 0, PPC::sub_dmr1_then_sub_dmrrow0, PPC::sub_dmr1_then_sub_dmrrow1, PPC::sub_dmr1_then_sub_dmrrowp0, PPC::sub_dmr1_then_sub_dmrrowp1, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_pair1_then_sub_vsx0, PPC::sub_pair1_then_sub_vsx1, PPC::sub_dmr1_then_sub_wacc_hi, PPC::sub_dmr1_then_sub_wacc_lo, PPC::sub_pair1_then_sub_vsx1_then_sub_64, 0, 0, 0, 0, PPC::sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
6649    { 0, PPC::sub_vsx1_then_sub_64, 0, 0, PPC::sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
6650    { 0, PPC::sub_pair1_then_sub_vsx1_then_sub_64, 0, 0, PPC::sub_wacc_hi_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrowp0, PPC::sub_wacc_hi_then_sub_dmrrowp1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
6651    { 0, 0, 0, 0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
6652    { 0, 0, 0, 0, PPC::sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
6653    { 0, 0, 0, 0, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
6654    { 0, 0, 0, 0, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
6655  };
6656
6657  --IdxA; assert(IdxA < 48); (void) IdxA;
6658  --IdxB; assert(IdxB < 48);
6659  return Rows[RowMap[IdxA]][IdxB];
6660}
6661
6662  struct MaskRolOp {
6663    LaneBitmask Mask;
6664    uint8_t  RotateLeft;
6665  };
6666  static const MaskRolOp LaneMaskComposeSequences[] = {
6667    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  0 }, { LaneBitmask::getNone(), 0 },   // Sequence 0
6668    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  1 }, { LaneBitmask::getNone(), 0 },   // Sequence 2
6669    { LaneBitmask(0x000000000000000C), 15 }, { LaneBitmask(0x000000000001F800),  8 }, { LaneBitmask::getNone(), 0 },   // Sequence 4
6670    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  2 }, { LaneBitmask::getNone(), 0 },   // Sequence 7
6671    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  3 }, { LaneBitmask::getNone(), 0 },   // Sequence 9
6672    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  9 }, { LaneBitmask::getNone(), 0 },   // Sequence 11
6673    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  4 }, { LaneBitmask::getNone(), 0 },   // Sequence 13
6674    { LaneBitmask(0xFFFFFFFFFFFFFFFF), 25 }, { LaneBitmask::getNone(), 0 },   // Sequence 15
6675    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  5 }, { LaneBitmask::getNone(), 0 },   // Sequence 17
6676    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  6 }, { LaneBitmask::getNone(), 0 },   // Sequence 19
6677    { LaneBitmask(0x0000000000000002),  8 }, { LaneBitmask(0x0000000000000100),  2 }, { LaneBitmask::getNone(), 0 },   // Sequence 21
6678    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  7 }, { LaneBitmask::getNone(), 0 },   // Sequence 24
6679    { LaneBitmask(0x000000000000000C), 11 }, { LaneBitmask(0x0000000000001800),  4 }, { LaneBitmask::getNone(), 0 },   // Sequence 26
6680    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  8 }, { LaneBitmask::getNone(), 0 },   // Sequence 29
6681    { LaneBitmask(0xFFFFFFFFFFFFFFFF), 10 }, { LaneBitmask::getNone(), 0 },   // Sequence 31
6682    { LaneBitmask(0xFFFFFFFFFFFFFFFF), 11 }, { LaneBitmask::getNone(), 0 },   // Sequence 33
6683    { LaneBitmask(0xFFFFFFFFFFFFFFFF), 12 }, { LaneBitmask::getNone(), 0 },   // Sequence 35
6684    { LaneBitmask(0xFFFFFFFFFFFFFFFF), 13 }, { LaneBitmask::getNone(), 0 },   // Sequence 37
6685    { LaneBitmask(0xFFFFFFFFFFFFFFFF), 14 }, { LaneBitmask::getNone(), 0 },   // Sequence 39
6686    { LaneBitmask(0xFFFFFFFFFFFFFFFF), 15 }, { LaneBitmask::getNone(), 0 },   // Sequence 41
6687    { LaneBitmask(0xFFFFFFFFFFFFFFFF), 16 }, { LaneBitmask::getNone(), 0 },   // Sequence 43
6688    { LaneBitmask(0xFFFFFFFFFFFFFFFF), 17 }, { LaneBitmask::getNone(), 0 },   // Sequence 45
6689    { LaneBitmask(0xFFFFFFFFFFFFFFFF), 18 }, { LaneBitmask::getNone(), 0 },   // Sequence 47
6690    { LaneBitmask(0x000000000000000C), 19 }, { LaneBitmask(0x0000000000001800), 12 }, { LaneBitmask::getNone(), 0 },   // Sequence 49
6691    { LaneBitmask(0x000000000000000C), 15 }, { LaneBitmask(0x0000000000001800),  8 }, { LaneBitmask::getNone(), 0 },   // Sequence 52
6692    { LaneBitmask(0xFFFFFFFFFFFFFFFF), 19 }, { LaneBitmask::getNone(), 0 },   // Sequence 55
6693    { LaneBitmask(0xFFFFFFFFFFFFFFFF), 20 }, { LaneBitmask::getNone(), 0 },   // Sequence 57
6694    { LaneBitmask(0xFFFFFFFFFFFFFFFF), 21 }, { LaneBitmask::getNone(), 0 },   // Sequence 59
6695    { LaneBitmask(0xFFFFFFFFFFFFFFFF), 22 }, { LaneBitmask::getNone(), 0 },   // Sequence 61
6696    { LaneBitmask(0xFFFFFFFFFFFFFFFF), 23 }, { LaneBitmask::getNone(), 0 },   // Sequence 63
6697    { LaneBitmask(0xFFFFFFFFFFFFFFFF), 24 }, { LaneBitmask::getNone(), 0 }  // Sequence 65
6698  };
6699  static const uint8_t CompositeSequences[] = {
6700    0, // to sub_32
6701    2, // to sub_64
6702    0, // to sub_dmr0
6703    4, // to sub_dmr1
6704    7, // to sub_dmrrow0
6705    9, // to sub_dmrrow1
6706    0, // to sub_dmrrowp0
6707    11, // to sub_dmrrowp1
6708    13, // to sub_eq
6709    0, // to sub_gp8_x0
6710    15, // to sub_gp8_x1
6711    17, // to sub_gt
6712    19, // to sub_lt
6713    0, // to sub_pair0
6714    21, // to sub_pair1
6715    24, // to sub_un
6716    0, // to sub_vsx0
6717    24, // to sub_vsx1
6718    26, // to sub_wacc_hi
6719    0, // to sub_wacc_lo
6720    29, // to sub_vsx1_then_sub_64
6721    11, // to sub_pair1_then_sub_64
6722    29, // to sub_pair1_then_sub_vsx0
6723    11, // to sub_pair1_then_sub_vsx1
6724    31, // to sub_pair1_then_sub_vsx1_then_sub_64
6725    33, // to sub_dmrrowp1_then_sub_dmrrow0
6726    35, // to sub_dmrrowp1_then_sub_dmrrow1
6727    37, // to sub_wacc_hi_then_sub_dmrrow0
6728    39, // to sub_wacc_hi_then_sub_dmrrow1
6729    33, // to sub_wacc_hi_then_sub_dmrrowp0
6730    37, // to sub_wacc_hi_then_sub_dmrrowp1
6731    41, // to sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
6732    43, // to sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
6733    45, // to sub_dmr1_then_sub_dmrrow0
6734    47, // to sub_dmr1_then_sub_dmrrow1
6735    41, // to sub_dmr1_then_sub_dmrrowp0
6736    45, // to sub_dmr1_then_sub_dmrrowp1
6737    49, // to sub_dmr1_then_sub_wacc_hi
6738    52, // to sub_dmr1_then_sub_wacc_lo
6739    55, // to sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
6740    57, // to sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
6741    59, // to sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
6742    61, // to sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
6743    55, // to sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
6744    59, // to sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
6745    63, // to sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
6746    65, // to sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
6747    15 // to sub_gp8_x1_then_sub_32
6748  };
6749
6750LaneBitmask PPCGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
6751  --IdxA; assert(IdxA < 48 && "Subregister index out of bounds");
6752  LaneBitmask Result;
6753  for (const MaskRolOp *Ops =
6754       &LaneMaskComposeSequences[CompositeSequences[IdxA]];
6755       Ops->Mask.any(); ++Ops) {
6756    LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
6757    if (unsigned S = Ops->RotateLeft)
6758      Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
6759    else
6760      Result |= LaneBitmask(M);
6761  }
6762  return Result;
6763}
6764
6765LaneBitmask PPCGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA,  LaneBitmask LaneMask) const {
6766  LaneMask &= getSubRegIndexLaneMask(IdxA);
6767  --IdxA; assert(IdxA < 48 && "Subregister index out of bounds");
6768  LaneBitmask Result;
6769  for (const MaskRolOp *Ops =
6770       &LaneMaskComposeSequences[CompositeSequences[IdxA]];
6771       Ops->Mask.any(); ++Ops) {
6772    LaneBitmask::Type M = LaneMask.getAsInteger();
6773    if (unsigned S = Ops->RotateLeft)
6774      Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
6775    else
6776      Result |= LaneBitmask(M);
6777  }
6778  return Result;
6779}
6780
6781const TargetRegisterClass *PPCGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
6782  static const uint8_t Table[51][48] = {
6783    {	// VSSRC
6784      0,	// sub_32
6785      0,	// sub_64
6786      0,	// sub_dmr0
6787      0,	// sub_dmr1
6788      0,	// sub_dmrrow0
6789      0,	// sub_dmrrow1
6790      0,	// sub_dmrrowp0
6791      0,	// sub_dmrrowp1
6792      0,	// sub_eq
6793      0,	// sub_gp8_x0
6794      0,	// sub_gp8_x1
6795      0,	// sub_gt
6796      0,	// sub_lt
6797      0,	// sub_pair0
6798      0,	// sub_pair1
6799      0,	// sub_un
6800      0,	// sub_vsx0
6801      0,	// sub_vsx1
6802      0,	// sub_wacc_hi
6803      0,	// sub_wacc_lo
6804      0,	// sub_vsx1_then_sub_64
6805      0,	// sub_pair1_then_sub_64
6806      0,	// sub_pair1_then_sub_vsx0
6807      0,	// sub_pair1_then_sub_vsx1
6808      0,	// sub_pair1_then_sub_vsx1_then_sub_64
6809      0,	// sub_dmrrowp1_then_sub_dmrrow0
6810      0,	// sub_dmrrowp1_then_sub_dmrrow1
6811      0,	// sub_wacc_hi_then_sub_dmrrow0
6812      0,	// sub_wacc_hi_then_sub_dmrrow1
6813      0,	// sub_wacc_hi_then_sub_dmrrowp0
6814      0,	// sub_wacc_hi_then_sub_dmrrowp1
6815      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
6816      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
6817      0,	// sub_dmr1_then_sub_dmrrow0
6818      0,	// sub_dmr1_then_sub_dmrrow1
6819      0,	// sub_dmr1_then_sub_dmrrowp0
6820      0,	// sub_dmr1_then_sub_dmrrowp1
6821      0,	// sub_dmr1_then_sub_wacc_hi
6822      0,	// sub_dmr1_then_sub_wacc_lo
6823      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
6824      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
6825      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
6826      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
6827      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
6828      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
6829      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
6830      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
6831      0,	// sub_gp8_x1_then_sub_32
6832    },
6833    {	// GPRC
6834      0,	// sub_32
6835      0,	// sub_64
6836      0,	// sub_dmr0
6837      0,	// sub_dmr1
6838      0,	// sub_dmrrow0
6839      0,	// sub_dmrrow1
6840      0,	// sub_dmrrowp0
6841      0,	// sub_dmrrowp1
6842      0,	// sub_eq
6843      0,	// sub_gp8_x0
6844      0,	// sub_gp8_x1
6845      0,	// sub_gt
6846      0,	// sub_lt
6847      0,	// sub_pair0
6848      0,	// sub_pair1
6849      0,	// sub_un
6850      0,	// sub_vsx0
6851      0,	// sub_vsx1
6852      0,	// sub_wacc_hi
6853      0,	// sub_wacc_lo
6854      0,	// sub_vsx1_then_sub_64
6855      0,	// sub_pair1_then_sub_64
6856      0,	// sub_pair1_then_sub_vsx0
6857      0,	// sub_pair1_then_sub_vsx1
6858      0,	// sub_pair1_then_sub_vsx1_then_sub_64
6859      0,	// sub_dmrrowp1_then_sub_dmrrow0
6860      0,	// sub_dmrrowp1_then_sub_dmrrow1
6861      0,	// sub_wacc_hi_then_sub_dmrrow0
6862      0,	// sub_wacc_hi_then_sub_dmrrow1
6863      0,	// sub_wacc_hi_then_sub_dmrrowp0
6864      0,	// sub_wacc_hi_then_sub_dmrrowp1
6865      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
6866      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
6867      0,	// sub_dmr1_then_sub_dmrrow0
6868      0,	// sub_dmr1_then_sub_dmrrow1
6869      0,	// sub_dmr1_then_sub_dmrrowp0
6870      0,	// sub_dmr1_then_sub_dmrrowp1
6871      0,	// sub_dmr1_then_sub_wacc_hi
6872      0,	// sub_dmr1_then_sub_wacc_lo
6873      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
6874      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
6875      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
6876      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
6877      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
6878      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
6879      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
6880      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
6881      0,	// sub_gp8_x1_then_sub_32
6882    },
6883    {	// GPRC_NOR0
6884      0,	// sub_32
6885      0,	// sub_64
6886      0,	// sub_dmr0
6887      0,	// sub_dmr1
6888      0,	// sub_dmrrow0
6889      0,	// sub_dmrrow1
6890      0,	// sub_dmrrowp0
6891      0,	// sub_dmrrowp1
6892      0,	// sub_eq
6893      0,	// sub_gp8_x0
6894      0,	// sub_gp8_x1
6895      0,	// sub_gt
6896      0,	// sub_lt
6897      0,	// sub_pair0
6898      0,	// sub_pair1
6899      0,	// sub_un
6900      0,	// sub_vsx0
6901      0,	// sub_vsx1
6902      0,	// sub_wacc_hi
6903      0,	// sub_wacc_lo
6904      0,	// sub_vsx1_then_sub_64
6905      0,	// sub_pair1_then_sub_64
6906      0,	// sub_pair1_then_sub_vsx0
6907      0,	// sub_pair1_then_sub_vsx1
6908      0,	// sub_pair1_then_sub_vsx1_then_sub_64
6909      0,	// sub_dmrrowp1_then_sub_dmrrow0
6910      0,	// sub_dmrrowp1_then_sub_dmrrow1
6911      0,	// sub_wacc_hi_then_sub_dmrrow0
6912      0,	// sub_wacc_hi_then_sub_dmrrow1
6913      0,	// sub_wacc_hi_then_sub_dmrrowp0
6914      0,	// sub_wacc_hi_then_sub_dmrrowp1
6915      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
6916      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
6917      0,	// sub_dmr1_then_sub_dmrrow0
6918      0,	// sub_dmr1_then_sub_dmrrow1
6919      0,	// sub_dmr1_then_sub_dmrrowp0
6920      0,	// sub_dmr1_then_sub_dmrrowp1
6921      0,	// sub_dmr1_then_sub_wacc_hi
6922      0,	// sub_dmr1_then_sub_wacc_lo
6923      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
6924      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
6925      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
6926      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
6927      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
6928      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
6929      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
6930      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
6931      0,	// sub_gp8_x1_then_sub_32
6932    },
6933    {	// GPRC_and_GPRC_NOR0
6934      0,	// sub_32
6935      0,	// sub_64
6936      0,	// sub_dmr0
6937      0,	// sub_dmr1
6938      0,	// sub_dmrrow0
6939      0,	// sub_dmrrow1
6940      0,	// sub_dmrrowp0
6941      0,	// sub_dmrrowp1
6942      0,	// sub_eq
6943      0,	// sub_gp8_x0
6944      0,	// sub_gp8_x1
6945      0,	// sub_gt
6946      0,	// sub_lt
6947      0,	// sub_pair0
6948      0,	// sub_pair1
6949      0,	// sub_un
6950      0,	// sub_vsx0
6951      0,	// sub_vsx1
6952      0,	// sub_wacc_hi
6953      0,	// sub_wacc_lo
6954      0,	// sub_vsx1_then_sub_64
6955      0,	// sub_pair1_then_sub_64
6956      0,	// sub_pair1_then_sub_vsx0
6957      0,	// sub_pair1_then_sub_vsx1
6958      0,	// sub_pair1_then_sub_vsx1_then_sub_64
6959      0,	// sub_dmrrowp1_then_sub_dmrrow0
6960      0,	// sub_dmrrowp1_then_sub_dmrrow1
6961      0,	// sub_wacc_hi_then_sub_dmrrow0
6962      0,	// sub_wacc_hi_then_sub_dmrrow1
6963      0,	// sub_wacc_hi_then_sub_dmrrowp0
6964      0,	// sub_wacc_hi_then_sub_dmrrowp1
6965      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
6966      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
6967      0,	// sub_dmr1_then_sub_dmrrow0
6968      0,	// sub_dmr1_then_sub_dmrrow1
6969      0,	// sub_dmr1_then_sub_dmrrowp0
6970      0,	// sub_dmr1_then_sub_dmrrowp1
6971      0,	// sub_dmr1_then_sub_wacc_hi
6972      0,	// sub_dmr1_then_sub_wacc_lo
6973      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
6974      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
6975      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
6976      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
6977      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
6978      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
6979      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
6980      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
6981      0,	// sub_gp8_x1_then_sub_32
6982    },
6983    {	// CRBITRC
6984      0,	// sub_32
6985      0,	// sub_64
6986      0,	// sub_dmr0
6987      0,	// sub_dmr1
6988      0,	// sub_dmrrow0
6989      0,	// sub_dmrrow1
6990      0,	// sub_dmrrowp0
6991      0,	// sub_dmrrowp1
6992      0,	// sub_eq
6993      0,	// sub_gp8_x0
6994      0,	// sub_gp8_x1
6995      0,	// sub_gt
6996      0,	// sub_lt
6997      0,	// sub_pair0
6998      0,	// sub_pair1
6999      0,	// sub_un
7000      0,	// sub_vsx0
7001      0,	// sub_vsx1
7002      0,	// sub_wacc_hi
7003      0,	// sub_wacc_lo
7004      0,	// sub_vsx1_then_sub_64
7005      0,	// sub_pair1_then_sub_64
7006      0,	// sub_pair1_then_sub_vsx0
7007      0,	// sub_pair1_then_sub_vsx1
7008      0,	// sub_pair1_then_sub_vsx1_then_sub_64
7009      0,	// sub_dmrrowp1_then_sub_dmrrow0
7010      0,	// sub_dmrrowp1_then_sub_dmrrow1
7011      0,	// sub_wacc_hi_then_sub_dmrrow0
7012      0,	// sub_wacc_hi_then_sub_dmrrow1
7013      0,	// sub_wacc_hi_then_sub_dmrrowp0
7014      0,	// sub_wacc_hi_then_sub_dmrrowp1
7015      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7016      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7017      0,	// sub_dmr1_then_sub_dmrrow0
7018      0,	// sub_dmr1_then_sub_dmrrow1
7019      0,	// sub_dmr1_then_sub_dmrrowp0
7020      0,	// sub_dmr1_then_sub_dmrrowp1
7021      0,	// sub_dmr1_then_sub_wacc_hi
7022      0,	// sub_dmr1_then_sub_wacc_lo
7023      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
7024      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
7025      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
7026      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
7027      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
7028      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
7029      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7030      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7031      0,	// sub_gp8_x1_then_sub_32
7032    },
7033    {	// F4RC
7034      0,	// sub_32
7035      0,	// sub_64
7036      0,	// sub_dmr0
7037      0,	// sub_dmr1
7038      0,	// sub_dmrrow0
7039      0,	// sub_dmrrow1
7040      0,	// sub_dmrrowp0
7041      0,	// sub_dmrrowp1
7042      0,	// sub_eq
7043      0,	// sub_gp8_x0
7044      0,	// sub_gp8_x1
7045      0,	// sub_gt
7046      0,	// sub_lt
7047      0,	// sub_pair0
7048      0,	// sub_pair1
7049      0,	// sub_un
7050      0,	// sub_vsx0
7051      0,	// sub_vsx1
7052      0,	// sub_wacc_hi
7053      0,	// sub_wacc_lo
7054      0,	// sub_vsx1_then_sub_64
7055      0,	// sub_pair1_then_sub_64
7056      0,	// sub_pair1_then_sub_vsx0
7057      0,	// sub_pair1_then_sub_vsx1
7058      0,	// sub_pair1_then_sub_vsx1_then_sub_64
7059      0,	// sub_dmrrowp1_then_sub_dmrrow0
7060      0,	// sub_dmrrowp1_then_sub_dmrrow1
7061      0,	// sub_wacc_hi_then_sub_dmrrow0
7062      0,	// sub_wacc_hi_then_sub_dmrrow1
7063      0,	// sub_wacc_hi_then_sub_dmrrowp0
7064      0,	// sub_wacc_hi_then_sub_dmrrowp1
7065      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7066      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7067      0,	// sub_dmr1_then_sub_dmrrow0
7068      0,	// sub_dmr1_then_sub_dmrrow1
7069      0,	// sub_dmr1_then_sub_dmrrowp0
7070      0,	// sub_dmr1_then_sub_dmrrowp1
7071      0,	// sub_dmr1_then_sub_wacc_hi
7072      0,	// sub_dmr1_then_sub_wacc_lo
7073      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
7074      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
7075      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
7076      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
7077      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
7078      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
7079      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7080      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7081      0,	// sub_gp8_x1_then_sub_32
7082    },
7083    {	// CRRC
7084      0,	// sub_32
7085      0,	// sub_64
7086      0,	// sub_dmr0
7087      0,	// sub_dmr1
7088      0,	// sub_dmrrow0
7089      0,	// sub_dmrrow1
7090      0,	// sub_dmrrowp0
7091      0,	// sub_dmrrowp1
7092      7,	// sub_eq -> CRRC
7093      0,	// sub_gp8_x0
7094      0,	// sub_gp8_x1
7095      7,	// sub_gt -> CRRC
7096      7,	// sub_lt -> CRRC
7097      0,	// sub_pair0
7098      0,	// sub_pair1
7099      7,	// sub_un -> CRRC
7100      0,	// sub_vsx0
7101      0,	// sub_vsx1
7102      0,	// sub_wacc_hi
7103      0,	// sub_wacc_lo
7104      0,	// sub_vsx1_then_sub_64
7105      0,	// sub_pair1_then_sub_64
7106      0,	// sub_pair1_then_sub_vsx0
7107      0,	// sub_pair1_then_sub_vsx1
7108      0,	// sub_pair1_then_sub_vsx1_then_sub_64
7109      0,	// sub_dmrrowp1_then_sub_dmrrow0
7110      0,	// sub_dmrrowp1_then_sub_dmrrow1
7111      0,	// sub_wacc_hi_then_sub_dmrrow0
7112      0,	// sub_wacc_hi_then_sub_dmrrow1
7113      0,	// sub_wacc_hi_then_sub_dmrrowp0
7114      0,	// sub_wacc_hi_then_sub_dmrrowp1
7115      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7116      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7117      0,	// sub_dmr1_then_sub_dmrrow0
7118      0,	// sub_dmr1_then_sub_dmrrow1
7119      0,	// sub_dmr1_then_sub_dmrrowp0
7120      0,	// sub_dmr1_then_sub_dmrrowp1
7121      0,	// sub_dmr1_then_sub_wacc_hi
7122      0,	// sub_dmr1_then_sub_wacc_lo
7123      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
7124      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
7125      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
7126      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
7127      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
7128      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
7129      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7130      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7131      0,	// sub_gp8_x1_then_sub_32
7132    },
7133    {	// CARRYRC
7134      0,	// sub_32
7135      0,	// sub_64
7136      0,	// sub_dmr0
7137      0,	// sub_dmr1
7138      0,	// sub_dmrrow0
7139      0,	// sub_dmrrow1
7140      0,	// sub_dmrrowp0
7141      0,	// sub_dmrrowp1
7142      0,	// sub_eq
7143      0,	// sub_gp8_x0
7144      0,	// sub_gp8_x1
7145      0,	// sub_gt
7146      0,	// sub_lt
7147      0,	// sub_pair0
7148      0,	// sub_pair1
7149      0,	// sub_un
7150      0,	// sub_vsx0
7151      0,	// sub_vsx1
7152      0,	// sub_wacc_hi
7153      0,	// sub_wacc_lo
7154      0,	// sub_vsx1_then_sub_64
7155      0,	// sub_pair1_then_sub_64
7156      0,	// sub_pair1_then_sub_vsx0
7157      0,	// sub_pair1_then_sub_vsx1
7158      0,	// sub_pair1_then_sub_vsx1_then_sub_64
7159      0,	// sub_dmrrowp1_then_sub_dmrrow0
7160      0,	// sub_dmrrowp1_then_sub_dmrrow1
7161      0,	// sub_wacc_hi_then_sub_dmrrow0
7162      0,	// sub_wacc_hi_then_sub_dmrrow1
7163      0,	// sub_wacc_hi_then_sub_dmrrowp0
7164      0,	// sub_wacc_hi_then_sub_dmrrowp1
7165      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7166      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7167      0,	// sub_dmr1_then_sub_dmrrow0
7168      0,	// sub_dmr1_then_sub_dmrrow1
7169      0,	// sub_dmr1_then_sub_dmrrowp0
7170      0,	// sub_dmr1_then_sub_dmrrowp1
7171      0,	// sub_dmr1_then_sub_wacc_hi
7172      0,	// sub_dmr1_then_sub_wacc_lo
7173      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
7174      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
7175      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
7176      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
7177      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
7178      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
7179      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7180      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7181      0,	// sub_gp8_x1_then_sub_32
7182    },
7183    {	// CTRRC
7184      0,	// sub_32
7185      0,	// sub_64
7186      0,	// sub_dmr0
7187      0,	// sub_dmr1
7188      0,	// sub_dmrrow0
7189      0,	// sub_dmrrow1
7190      0,	// sub_dmrrowp0
7191      0,	// sub_dmrrowp1
7192      0,	// sub_eq
7193      0,	// sub_gp8_x0
7194      0,	// sub_gp8_x1
7195      0,	// sub_gt
7196      0,	// sub_lt
7197      0,	// sub_pair0
7198      0,	// sub_pair1
7199      0,	// sub_un
7200      0,	// sub_vsx0
7201      0,	// sub_vsx1
7202      0,	// sub_wacc_hi
7203      0,	// sub_wacc_lo
7204      0,	// sub_vsx1_then_sub_64
7205      0,	// sub_pair1_then_sub_64
7206      0,	// sub_pair1_then_sub_vsx0
7207      0,	// sub_pair1_then_sub_vsx1
7208      0,	// sub_pair1_then_sub_vsx1_then_sub_64
7209      0,	// sub_dmrrowp1_then_sub_dmrrow0
7210      0,	// sub_dmrrowp1_then_sub_dmrrow1
7211      0,	// sub_wacc_hi_then_sub_dmrrow0
7212      0,	// sub_wacc_hi_then_sub_dmrrow1
7213      0,	// sub_wacc_hi_then_sub_dmrrowp0
7214      0,	// sub_wacc_hi_then_sub_dmrrowp1
7215      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7216      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7217      0,	// sub_dmr1_then_sub_dmrrow0
7218      0,	// sub_dmr1_then_sub_dmrrow1
7219      0,	// sub_dmr1_then_sub_dmrrowp0
7220      0,	// sub_dmr1_then_sub_dmrrowp1
7221      0,	// sub_dmr1_then_sub_wacc_hi
7222      0,	// sub_dmr1_then_sub_wacc_lo
7223      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
7224      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
7225      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
7226      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
7227      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
7228      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
7229      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7230      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7231      0,	// sub_gp8_x1_then_sub_32
7232    },
7233    {	// LRRC
7234      0,	// sub_32
7235      0,	// sub_64
7236      0,	// sub_dmr0
7237      0,	// sub_dmr1
7238      0,	// sub_dmrrow0
7239      0,	// sub_dmrrow1
7240      0,	// sub_dmrrowp0
7241      0,	// sub_dmrrowp1
7242      0,	// sub_eq
7243      0,	// sub_gp8_x0
7244      0,	// sub_gp8_x1
7245      0,	// sub_gt
7246      0,	// sub_lt
7247      0,	// sub_pair0
7248      0,	// sub_pair1
7249      0,	// sub_un
7250      0,	// sub_vsx0
7251      0,	// sub_vsx1
7252      0,	// sub_wacc_hi
7253      0,	// sub_wacc_lo
7254      0,	// sub_vsx1_then_sub_64
7255      0,	// sub_pair1_then_sub_64
7256      0,	// sub_pair1_then_sub_vsx0
7257      0,	// sub_pair1_then_sub_vsx1
7258      0,	// sub_pair1_then_sub_vsx1_then_sub_64
7259      0,	// sub_dmrrowp1_then_sub_dmrrow0
7260      0,	// sub_dmrrowp1_then_sub_dmrrow1
7261      0,	// sub_wacc_hi_then_sub_dmrrow0
7262      0,	// sub_wacc_hi_then_sub_dmrrow1
7263      0,	// sub_wacc_hi_then_sub_dmrrowp0
7264      0,	// sub_wacc_hi_then_sub_dmrrowp1
7265      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7266      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7267      0,	// sub_dmr1_then_sub_dmrrow0
7268      0,	// sub_dmr1_then_sub_dmrrow1
7269      0,	// sub_dmr1_then_sub_dmrrowp0
7270      0,	// sub_dmr1_then_sub_dmrrowp1
7271      0,	// sub_dmr1_then_sub_wacc_hi
7272      0,	// sub_dmr1_then_sub_wacc_lo
7273      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
7274      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
7275      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
7276      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
7277      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
7278      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
7279      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7280      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7281      0,	// sub_gp8_x1_then_sub_32
7282    },
7283    {	// VRSAVERC
7284      0,	// sub_32
7285      0,	// sub_64
7286      0,	// sub_dmr0
7287      0,	// sub_dmr1
7288      0,	// sub_dmrrow0
7289      0,	// sub_dmrrow1
7290      0,	// sub_dmrrowp0
7291      0,	// sub_dmrrowp1
7292      0,	// sub_eq
7293      0,	// sub_gp8_x0
7294      0,	// sub_gp8_x1
7295      0,	// sub_gt
7296      0,	// sub_lt
7297      0,	// sub_pair0
7298      0,	// sub_pair1
7299      0,	// sub_un
7300      0,	// sub_vsx0
7301      0,	// sub_vsx1
7302      0,	// sub_wacc_hi
7303      0,	// sub_wacc_lo
7304      0,	// sub_vsx1_then_sub_64
7305      0,	// sub_pair1_then_sub_64
7306      0,	// sub_pair1_then_sub_vsx0
7307      0,	// sub_pair1_then_sub_vsx1
7308      0,	// sub_pair1_then_sub_vsx1_then_sub_64
7309      0,	// sub_dmrrowp1_then_sub_dmrrow0
7310      0,	// sub_dmrrowp1_then_sub_dmrrow1
7311      0,	// sub_wacc_hi_then_sub_dmrrow0
7312      0,	// sub_wacc_hi_then_sub_dmrrow1
7313      0,	// sub_wacc_hi_then_sub_dmrrowp0
7314      0,	// sub_wacc_hi_then_sub_dmrrowp1
7315      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7316      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7317      0,	// sub_dmr1_then_sub_dmrrow0
7318      0,	// sub_dmr1_then_sub_dmrrow1
7319      0,	// sub_dmr1_then_sub_dmrrowp0
7320      0,	// sub_dmr1_then_sub_dmrrowp1
7321      0,	// sub_dmr1_then_sub_wacc_hi
7322      0,	// sub_dmr1_then_sub_wacc_lo
7323      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
7324      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
7325      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
7326      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
7327      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
7328      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
7329      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7330      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7331      0,	// sub_gp8_x1_then_sub_32
7332    },
7333    {	// SPILLTOVSRRC
7334      14,	// sub_32 -> G8RC
7335      0,	// sub_64
7336      0,	// sub_dmr0
7337      0,	// sub_dmr1
7338      0,	// sub_dmrrow0
7339      0,	// sub_dmrrow1
7340      0,	// sub_dmrrowp0
7341      0,	// sub_dmrrowp1
7342      0,	// sub_eq
7343      0,	// sub_gp8_x0
7344      0,	// sub_gp8_x1
7345      0,	// sub_gt
7346      0,	// sub_lt
7347      0,	// sub_pair0
7348      0,	// sub_pair1
7349      0,	// sub_un
7350      0,	// sub_vsx0
7351      0,	// sub_vsx1
7352      0,	// sub_wacc_hi
7353      0,	// sub_wacc_lo
7354      0,	// sub_vsx1_then_sub_64
7355      0,	// sub_pair1_then_sub_64
7356      0,	// sub_pair1_then_sub_vsx0
7357      0,	// sub_pair1_then_sub_vsx1
7358      0,	// sub_pair1_then_sub_vsx1_then_sub_64
7359      0,	// sub_dmrrowp1_then_sub_dmrrow0
7360      0,	// sub_dmrrowp1_then_sub_dmrrow1
7361      0,	// sub_wacc_hi_then_sub_dmrrow0
7362      0,	// sub_wacc_hi_then_sub_dmrrow1
7363      0,	// sub_wacc_hi_then_sub_dmrrowp0
7364      0,	// sub_wacc_hi_then_sub_dmrrowp1
7365      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7366      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7367      0,	// sub_dmr1_then_sub_dmrrow0
7368      0,	// sub_dmr1_then_sub_dmrrow1
7369      0,	// sub_dmr1_then_sub_dmrrowp0
7370      0,	// sub_dmr1_then_sub_dmrrowp1
7371      0,	// sub_dmr1_then_sub_wacc_hi
7372      0,	// sub_dmr1_then_sub_wacc_lo
7373      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
7374      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
7375      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
7376      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
7377      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
7378      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
7379      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7380      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7381      0,	// sub_gp8_x1_then_sub_32
7382    },
7383    {	// VSFRC
7384      0,	// sub_32
7385      0,	// sub_64
7386      0,	// sub_dmr0
7387      0,	// sub_dmr1
7388      0,	// sub_dmrrow0
7389      0,	// sub_dmrrow1
7390      0,	// sub_dmrrowp0
7391      0,	// sub_dmrrowp1
7392      0,	// sub_eq
7393      0,	// sub_gp8_x0
7394      0,	// sub_gp8_x1
7395      0,	// sub_gt
7396      0,	// sub_lt
7397      0,	// sub_pair0
7398      0,	// sub_pair1
7399      0,	// sub_un
7400      0,	// sub_vsx0
7401      0,	// sub_vsx1
7402      0,	// sub_wacc_hi
7403      0,	// sub_wacc_lo
7404      0,	// sub_vsx1_then_sub_64
7405      0,	// sub_pair1_then_sub_64
7406      0,	// sub_pair1_then_sub_vsx0
7407      0,	// sub_pair1_then_sub_vsx1
7408      0,	// sub_pair1_then_sub_vsx1_then_sub_64
7409      0,	// sub_dmrrowp1_then_sub_dmrrow0
7410      0,	// sub_dmrrowp1_then_sub_dmrrow1
7411      0,	// sub_wacc_hi_then_sub_dmrrow0
7412      0,	// sub_wacc_hi_then_sub_dmrrow1
7413      0,	// sub_wacc_hi_then_sub_dmrrowp0
7414      0,	// sub_wacc_hi_then_sub_dmrrowp1
7415      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7416      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7417      0,	// sub_dmr1_then_sub_dmrrow0
7418      0,	// sub_dmr1_then_sub_dmrrow1
7419      0,	// sub_dmr1_then_sub_dmrrowp0
7420      0,	// sub_dmr1_then_sub_dmrrowp1
7421      0,	// sub_dmr1_then_sub_wacc_hi
7422      0,	// sub_dmr1_then_sub_wacc_lo
7423      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
7424      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
7425      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
7426      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
7427      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
7428      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
7429      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7430      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7431      0,	// sub_gp8_x1_then_sub_32
7432    },
7433    {	// G8RC
7434      14,	// sub_32 -> G8RC
7435      0,	// sub_64
7436      0,	// sub_dmr0
7437      0,	// sub_dmr1
7438      0,	// sub_dmrrow0
7439      0,	// sub_dmrrow1
7440      0,	// sub_dmrrowp0
7441      0,	// sub_dmrrowp1
7442      0,	// sub_eq
7443      0,	// sub_gp8_x0
7444      0,	// sub_gp8_x1
7445      0,	// sub_gt
7446      0,	// sub_lt
7447      0,	// sub_pair0
7448      0,	// sub_pair1
7449      0,	// sub_un
7450      0,	// sub_vsx0
7451      0,	// sub_vsx1
7452      0,	// sub_wacc_hi
7453      0,	// sub_wacc_lo
7454      0,	// sub_vsx1_then_sub_64
7455      0,	// sub_pair1_then_sub_64
7456      0,	// sub_pair1_then_sub_vsx0
7457      0,	// sub_pair1_then_sub_vsx1
7458      0,	// sub_pair1_then_sub_vsx1_then_sub_64
7459      0,	// sub_dmrrowp1_then_sub_dmrrow0
7460      0,	// sub_dmrrowp1_then_sub_dmrrow1
7461      0,	// sub_wacc_hi_then_sub_dmrrow0
7462      0,	// sub_wacc_hi_then_sub_dmrrow1
7463      0,	// sub_wacc_hi_then_sub_dmrrowp0
7464      0,	// sub_wacc_hi_then_sub_dmrrowp1
7465      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7466      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7467      0,	// sub_dmr1_then_sub_dmrrow0
7468      0,	// sub_dmr1_then_sub_dmrrow1
7469      0,	// sub_dmr1_then_sub_dmrrowp0
7470      0,	// sub_dmr1_then_sub_dmrrowp1
7471      0,	// sub_dmr1_then_sub_wacc_hi
7472      0,	// sub_dmr1_then_sub_wacc_lo
7473      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
7474      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
7475      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
7476      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
7477      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
7478      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
7479      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7480      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7481      0,	// sub_gp8_x1_then_sub_32
7482    },
7483    {	// G8RC_NOX0
7484      15,	// sub_32 -> G8RC_NOX0
7485      0,	// sub_64
7486      0,	// sub_dmr0
7487      0,	// sub_dmr1
7488      0,	// sub_dmrrow0
7489      0,	// sub_dmrrow1
7490      0,	// sub_dmrrowp0
7491      0,	// sub_dmrrowp1
7492      0,	// sub_eq
7493      0,	// sub_gp8_x0
7494      0,	// sub_gp8_x1
7495      0,	// sub_gt
7496      0,	// sub_lt
7497      0,	// sub_pair0
7498      0,	// sub_pair1
7499      0,	// sub_un
7500      0,	// sub_vsx0
7501      0,	// sub_vsx1
7502      0,	// sub_wacc_hi
7503      0,	// sub_wacc_lo
7504      0,	// sub_vsx1_then_sub_64
7505      0,	// sub_pair1_then_sub_64
7506      0,	// sub_pair1_then_sub_vsx0
7507      0,	// sub_pair1_then_sub_vsx1
7508      0,	// sub_pair1_then_sub_vsx1_then_sub_64
7509      0,	// sub_dmrrowp1_then_sub_dmrrow0
7510      0,	// sub_dmrrowp1_then_sub_dmrrow1
7511      0,	// sub_wacc_hi_then_sub_dmrrow0
7512      0,	// sub_wacc_hi_then_sub_dmrrow1
7513      0,	// sub_wacc_hi_then_sub_dmrrowp0
7514      0,	// sub_wacc_hi_then_sub_dmrrowp1
7515      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7516      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7517      0,	// sub_dmr1_then_sub_dmrrow0
7518      0,	// sub_dmr1_then_sub_dmrrow1
7519      0,	// sub_dmr1_then_sub_dmrrowp0
7520      0,	// sub_dmr1_then_sub_dmrrowp1
7521      0,	// sub_dmr1_then_sub_wacc_hi
7522      0,	// sub_dmr1_then_sub_wacc_lo
7523      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
7524      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
7525      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
7526      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
7527      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
7528      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
7529      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7530      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7531      0,	// sub_gp8_x1_then_sub_32
7532    },
7533    {	// SPILLTOVSRRC_and_VSFRC
7534      0,	// sub_32
7535      0,	// sub_64
7536      0,	// sub_dmr0
7537      0,	// sub_dmr1
7538      0,	// sub_dmrrow0
7539      0,	// sub_dmrrow1
7540      0,	// sub_dmrrowp0
7541      0,	// sub_dmrrowp1
7542      0,	// sub_eq
7543      0,	// sub_gp8_x0
7544      0,	// sub_gp8_x1
7545      0,	// sub_gt
7546      0,	// sub_lt
7547      0,	// sub_pair0
7548      0,	// sub_pair1
7549      0,	// sub_un
7550      0,	// sub_vsx0
7551      0,	// sub_vsx1
7552      0,	// sub_wacc_hi
7553      0,	// sub_wacc_lo
7554      0,	// sub_vsx1_then_sub_64
7555      0,	// sub_pair1_then_sub_64
7556      0,	// sub_pair1_then_sub_vsx0
7557      0,	// sub_pair1_then_sub_vsx1
7558      0,	// sub_pair1_then_sub_vsx1_then_sub_64
7559      0,	// sub_dmrrowp1_then_sub_dmrrow0
7560      0,	// sub_dmrrowp1_then_sub_dmrrow1
7561      0,	// sub_wacc_hi_then_sub_dmrrow0
7562      0,	// sub_wacc_hi_then_sub_dmrrow1
7563      0,	// sub_wacc_hi_then_sub_dmrrowp0
7564      0,	// sub_wacc_hi_then_sub_dmrrowp1
7565      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7566      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7567      0,	// sub_dmr1_then_sub_dmrrow0
7568      0,	// sub_dmr1_then_sub_dmrrow1
7569      0,	// sub_dmr1_then_sub_dmrrowp0
7570      0,	// sub_dmr1_then_sub_dmrrowp1
7571      0,	// sub_dmr1_then_sub_wacc_hi
7572      0,	// sub_dmr1_then_sub_wacc_lo
7573      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
7574      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
7575      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
7576      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
7577      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
7578      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
7579      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7580      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7581      0,	// sub_gp8_x1_then_sub_32
7582    },
7583    {	// G8RC_and_G8RC_NOX0
7584      17,	// sub_32 -> G8RC_and_G8RC_NOX0
7585      0,	// sub_64
7586      0,	// sub_dmr0
7587      0,	// sub_dmr1
7588      0,	// sub_dmrrow0
7589      0,	// sub_dmrrow1
7590      0,	// sub_dmrrowp0
7591      0,	// sub_dmrrowp1
7592      0,	// sub_eq
7593      0,	// sub_gp8_x0
7594      0,	// sub_gp8_x1
7595      0,	// sub_gt
7596      0,	// sub_lt
7597      0,	// sub_pair0
7598      0,	// sub_pair1
7599      0,	// sub_un
7600      0,	// sub_vsx0
7601      0,	// sub_vsx1
7602      0,	// sub_wacc_hi
7603      0,	// sub_wacc_lo
7604      0,	// sub_vsx1_then_sub_64
7605      0,	// sub_pair1_then_sub_64
7606      0,	// sub_pair1_then_sub_vsx0
7607      0,	// sub_pair1_then_sub_vsx1
7608      0,	// sub_pair1_then_sub_vsx1_then_sub_64
7609      0,	// sub_dmrrowp1_then_sub_dmrrow0
7610      0,	// sub_dmrrowp1_then_sub_dmrrow1
7611      0,	// sub_wacc_hi_then_sub_dmrrow0
7612      0,	// sub_wacc_hi_then_sub_dmrrow1
7613      0,	// sub_wacc_hi_then_sub_dmrrowp0
7614      0,	// sub_wacc_hi_then_sub_dmrrowp1
7615      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7616      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7617      0,	// sub_dmr1_then_sub_dmrrow0
7618      0,	// sub_dmr1_then_sub_dmrrow1
7619      0,	// sub_dmr1_then_sub_dmrrowp0
7620      0,	// sub_dmr1_then_sub_dmrrowp1
7621      0,	// sub_dmr1_then_sub_wacc_hi
7622      0,	// sub_dmr1_then_sub_wacc_lo
7623      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
7624      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
7625      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
7626      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
7627      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
7628      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
7629      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7630      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7631      0,	// sub_gp8_x1_then_sub_32
7632    },
7633    {	// F8RC
7634      0,	// sub_32
7635      0,	// sub_64
7636      0,	// sub_dmr0
7637      0,	// sub_dmr1
7638      0,	// sub_dmrrow0
7639      0,	// sub_dmrrow1
7640      0,	// sub_dmrrowp0
7641      0,	// sub_dmrrowp1
7642      0,	// sub_eq
7643      0,	// sub_gp8_x0
7644      0,	// sub_gp8_x1
7645      0,	// sub_gt
7646      0,	// sub_lt
7647      0,	// sub_pair0
7648      0,	// sub_pair1
7649      0,	// sub_un
7650      0,	// sub_vsx0
7651      0,	// sub_vsx1
7652      0,	// sub_wacc_hi
7653      0,	// sub_wacc_lo
7654      0,	// sub_vsx1_then_sub_64
7655      0,	// sub_pair1_then_sub_64
7656      0,	// sub_pair1_then_sub_vsx0
7657      0,	// sub_pair1_then_sub_vsx1
7658      0,	// sub_pair1_then_sub_vsx1_then_sub_64
7659      0,	// sub_dmrrowp1_then_sub_dmrrow0
7660      0,	// sub_dmrrowp1_then_sub_dmrrow1
7661      0,	// sub_wacc_hi_then_sub_dmrrow0
7662      0,	// sub_wacc_hi_then_sub_dmrrow1
7663      0,	// sub_wacc_hi_then_sub_dmrrowp0
7664      0,	// sub_wacc_hi_then_sub_dmrrowp1
7665      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7666      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7667      0,	// sub_dmr1_then_sub_dmrrow0
7668      0,	// sub_dmr1_then_sub_dmrrow1
7669      0,	// sub_dmr1_then_sub_dmrrowp0
7670      0,	// sub_dmr1_then_sub_dmrrowp1
7671      0,	// sub_dmr1_then_sub_wacc_hi
7672      0,	// sub_dmr1_then_sub_wacc_lo
7673      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
7674      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
7675      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
7676      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
7677      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
7678      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
7679      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7680      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7681      0,	// sub_gp8_x1_then_sub_32
7682    },
7683    {	// SPERC
7684      19,	// sub_32 -> SPERC
7685      0,	// sub_64
7686      0,	// sub_dmr0
7687      0,	// sub_dmr1
7688      0,	// sub_dmrrow0
7689      0,	// sub_dmrrow1
7690      0,	// sub_dmrrowp0
7691      0,	// sub_dmrrowp1
7692      0,	// sub_eq
7693      0,	// sub_gp8_x0
7694      0,	// sub_gp8_x1
7695      0,	// sub_gt
7696      0,	// sub_lt
7697      0,	// sub_pair0
7698      0,	// sub_pair1
7699      0,	// sub_un
7700      0,	// sub_vsx0
7701      0,	// sub_vsx1
7702      0,	// sub_wacc_hi
7703      0,	// sub_wacc_lo
7704      0,	// sub_vsx1_then_sub_64
7705      0,	// sub_pair1_then_sub_64
7706      0,	// sub_pair1_then_sub_vsx0
7707      0,	// sub_pair1_then_sub_vsx1
7708      0,	// sub_pair1_then_sub_vsx1_then_sub_64
7709      0,	// sub_dmrrowp1_then_sub_dmrrow0
7710      0,	// sub_dmrrowp1_then_sub_dmrrow1
7711      0,	// sub_wacc_hi_then_sub_dmrrow0
7712      0,	// sub_wacc_hi_then_sub_dmrrow1
7713      0,	// sub_wacc_hi_then_sub_dmrrowp0
7714      0,	// sub_wacc_hi_then_sub_dmrrowp1
7715      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7716      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7717      0,	// sub_dmr1_then_sub_dmrrow0
7718      0,	// sub_dmr1_then_sub_dmrrow1
7719      0,	// sub_dmr1_then_sub_dmrrowp0
7720      0,	// sub_dmr1_then_sub_dmrrowp1
7721      0,	// sub_dmr1_then_sub_wacc_hi
7722      0,	// sub_dmr1_then_sub_wacc_lo
7723      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
7724      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
7725      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
7726      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
7727      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
7728      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
7729      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7730      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7731      0,	// sub_gp8_x1_then_sub_32
7732    },
7733    {	// VFRC
7734      0,	// sub_32
7735      0,	// sub_64
7736      0,	// sub_dmr0
7737      0,	// sub_dmr1
7738      0,	// sub_dmrrow0
7739      0,	// sub_dmrrow1
7740      0,	// sub_dmrrowp0
7741      0,	// sub_dmrrowp1
7742      0,	// sub_eq
7743      0,	// sub_gp8_x0
7744      0,	// sub_gp8_x1
7745      0,	// sub_gt
7746      0,	// sub_lt
7747      0,	// sub_pair0
7748      0,	// sub_pair1
7749      0,	// sub_un
7750      0,	// sub_vsx0
7751      0,	// sub_vsx1
7752      0,	// sub_wacc_hi
7753      0,	// sub_wacc_lo
7754      0,	// sub_vsx1_then_sub_64
7755      0,	// sub_pair1_then_sub_64
7756      0,	// sub_pair1_then_sub_vsx0
7757      0,	// sub_pair1_then_sub_vsx1
7758      0,	// sub_pair1_then_sub_vsx1_then_sub_64
7759      0,	// sub_dmrrowp1_then_sub_dmrrow0
7760      0,	// sub_dmrrowp1_then_sub_dmrrow1
7761      0,	// sub_wacc_hi_then_sub_dmrrow0
7762      0,	// sub_wacc_hi_then_sub_dmrrow1
7763      0,	// sub_wacc_hi_then_sub_dmrrowp0
7764      0,	// sub_wacc_hi_then_sub_dmrrowp1
7765      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7766      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7767      0,	// sub_dmr1_then_sub_dmrrow0
7768      0,	// sub_dmr1_then_sub_dmrrow1
7769      0,	// sub_dmr1_then_sub_dmrrowp0
7770      0,	// sub_dmr1_then_sub_dmrrowp1
7771      0,	// sub_dmr1_then_sub_wacc_hi
7772      0,	// sub_dmr1_then_sub_wacc_lo
7773      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
7774      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
7775      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
7776      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
7777      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
7778      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
7779      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7780      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7781      0,	// sub_gp8_x1_then_sub_32
7782    },
7783    {	// SPERC_with_sub_32_in_GPRC_NOR0
7784      21,	// sub_32 -> SPERC_with_sub_32_in_GPRC_NOR0
7785      0,	// sub_64
7786      0,	// sub_dmr0
7787      0,	// sub_dmr1
7788      0,	// sub_dmrrow0
7789      0,	// sub_dmrrow1
7790      0,	// sub_dmrrowp0
7791      0,	// sub_dmrrowp1
7792      0,	// sub_eq
7793      0,	// sub_gp8_x0
7794      0,	// sub_gp8_x1
7795      0,	// sub_gt
7796      0,	// sub_lt
7797      0,	// sub_pair0
7798      0,	// sub_pair1
7799      0,	// sub_un
7800      0,	// sub_vsx0
7801      0,	// sub_vsx1
7802      0,	// sub_wacc_hi
7803      0,	// sub_wacc_lo
7804      0,	// sub_vsx1_then_sub_64
7805      0,	// sub_pair1_then_sub_64
7806      0,	// sub_pair1_then_sub_vsx0
7807      0,	// sub_pair1_then_sub_vsx1
7808      0,	// sub_pair1_then_sub_vsx1_then_sub_64
7809      0,	// sub_dmrrowp1_then_sub_dmrrow0
7810      0,	// sub_dmrrowp1_then_sub_dmrrow1
7811      0,	// sub_wacc_hi_then_sub_dmrrow0
7812      0,	// sub_wacc_hi_then_sub_dmrrow1
7813      0,	// sub_wacc_hi_then_sub_dmrrowp0
7814      0,	// sub_wacc_hi_then_sub_dmrrowp1
7815      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7816      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7817      0,	// sub_dmr1_then_sub_dmrrow0
7818      0,	// sub_dmr1_then_sub_dmrrow1
7819      0,	// sub_dmr1_then_sub_dmrrowp0
7820      0,	// sub_dmr1_then_sub_dmrrowp1
7821      0,	// sub_dmr1_then_sub_wacc_hi
7822      0,	// sub_dmr1_then_sub_wacc_lo
7823      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
7824      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
7825      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
7826      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
7827      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
7828      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
7829      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7830      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7831      0,	// sub_gp8_x1_then_sub_32
7832    },
7833    {	// SPILLTOVSRRC_and_VFRC
7834      0,	// sub_32
7835      0,	// sub_64
7836      0,	// sub_dmr0
7837      0,	// sub_dmr1
7838      0,	// sub_dmrrow0
7839      0,	// sub_dmrrow1
7840      0,	// sub_dmrrowp0
7841      0,	// sub_dmrrowp1
7842      0,	// sub_eq
7843      0,	// sub_gp8_x0
7844      0,	// sub_gp8_x1
7845      0,	// sub_gt
7846      0,	// sub_lt
7847      0,	// sub_pair0
7848      0,	// sub_pair1
7849      0,	// sub_un
7850      0,	// sub_vsx0
7851      0,	// sub_vsx1
7852      0,	// sub_wacc_hi
7853      0,	// sub_wacc_lo
7854      0,	// sub_vsx1_then_sub_64
7855      0,	// sub_pair1_then_sub_64
7856      0,	// sub_pair1_then_sub_vsx0
7857      0,	// sub_pair1_then_sub_vsx1
7858      0,	// sub_pair1_then_sub_vsx1_then_sub_64
7859      0,	// sub_dmrrowp1_then_sub_dmrrow0
7860      0,	// sub_dmrrowp1_then_sub_dmrrow1
7861      0,	// sub_wacc_hi_then_sub_dmrrow0
7862      0,	// sub_wacc_hi_then_sub_dmrrow1
7863      0,	// sub_wacc_hi_then_sub_dmrrowp0
7864      0,	// sub_wacc_hi_then_sub_dmrrowp1
7865      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7866      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7867      0,	// sub_dmr1_then_sub_dmrrow0
7868      0,	// sub_dmr1_then_sub_dmrrow1
7869      0,	// sub_dmr1_then_sub_dmrrowp0
7870      0,	// sub_dmr1_then_sub_dmrrowp1
7871      0,	// sub_dmr1_then_sub_wacc_hi
7872      0,	// sub_dmr1_then_sub_wacc_lo
7873      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
7874      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
7875      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
7876      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
7877      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
7878      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
7879      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7880      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7881      0,	// sub_gp8_x1_then_sub_32
7882    },
7883    {	// SPILLTOVSRRC_and_F4RC
7884      0,	// sub_32
7885      0,	// sub_64
7886      0,	// sub_dmr0
7887      0,	// sub_dmr1
7888      0,	// sub_dmrrow0
7889      0,	// sub_dmrrow1
7890      0,	// sub_dmrrowp0
7891      0,	// sub_dmrrowp1
7892      0,	// sub_eq
7893      0,	// sub_gp8_x0
7894      0,	// sub_gp8_x1
7895      0,	// sub_gt
7896      0,	// sub_lt
7897      0,	// sub_pair0
7898      0,	// sub_pair1
7899      0,	// sub_un
7900      0,	// sub_vsx0
7901      0,	// sub_vsx1
7902      0,	// sub_wacc_hi
7903      0,	// sub_wacc_lo
7904      0,	// sub_vsx1_then_sub_64
7905      0,	// sub_pair1_then_sub_64
7906      0,	// sub_pair1_then_sub_vsx0
7907      0,	// sub_pair1_then_sub_vsx1
7908      0,	// sub_pair1_then_sub_vsx1_then_sub_64
7909      0,	// sub_dmrrowp1_then_sub_dmrrow0
7910      0,	// sub_dmrrowp1_then_sub_dmrrow1
7911      0,	// sub_wacc_hi_then_sub_dmrrow0
7912      0,	// sub_wacc_hi_then_sub_dmrrow1
7913      0,	// sub_wacc_hi_then_sub_dmrrowp0
7914      0,	// sub_wacc_hi_then_sub_dmrrowp1
7915      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7916      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7917      0,	// sub_dmr1_then_sub_dmrrow0
7918      0,	// sub_dmr1_then_sub_dmrrow1
7919      0,	// sub_dmr1_then_sub_dmrrowp0
7920      0,	// sub_dmr1_then_sub_dmrrowp1
7921      0,	// sub_dmr1_then_sub_wacc_hi
7922      0,	// sub_dmr1_then_sub_wacc_lo
7923      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
7924      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
7925      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
7926      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
7927      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
7928      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
7929      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7930      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7931      0,	// sub_gp8_x1_then_sub_32
7932    },
7933    {	// CTRRC8
7934      0,	// sub_32
7935      0,	// sub_64
7936      0,	// sub_dmr0
7937      0,	// sub_dmr1
7938      0,	// sub_dmrrow0
7939      0,	// sub_dmrrow1
7940      0,	// sub_dmrrowp0
7941      0,	// sub_dmrrowp1
7942      0,	// sub_eq
7943      0,	// sub_gp8_x0
7944      0,	// sub_gp8_x1
7945      0,	// sub_gt
7946      0,	// sub_lt
7947      0,	// sub_pair0
7948      0,	// sub_pair1
7949      0,	// sub_un
7950      0,	// sub_vsx0
7951      0,	// sub_vsx1
7952      0,	// sub_wacc_hi
7953      0,	// sub_wacc_lo
7954      0,	// sub_vsx1_then_sub_64
7955      0,	// sub_pair1_then_sub_64
7956      0,	// sub_pair1_then_sub_vsx0
7957      0,	// sub_pair1_then_sub_vsx1
7958      0,	// sub_pair1_then_sub_vsx1_then_sub_64
7959      0,	// sub_dmrrowp1_then_sub_dmrrow0
7960      0,	// sub_dmrrowp1_then_sub_dmrrow1
7961      0,	// sub_wacc_hi_then_sub_dmrrow0
7962      0,	// sub_wacc_hi_then_sub_dmrrow1
7963      0,	// sub_wacc_hi_then_sub_dmrrowp0
7964      0,	// sub_wacc_hi_then_sub_dmrrowp1
7965      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7966      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7967      0,	// sub_dmr1_then_sub_dmrrow0
7968      0,	// sub_dmr1_then_sub_dmrrow1
7969      0,	// sub_dmr1_then_sub_dmrrowp0
7970      0,	// sub_dmr1_then_sub_dmrrowp1
7971      0,	// sub_dmr1_then_sub_wacc_hi
7972      0,	// sub_dmr1_then_sub_wacc_lo
7973      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
7974      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
7975      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
7976      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
7977      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
7978      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
7979      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7980      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7981      0,	// sub_gp8_x1_then_sub_32
7982    },
7983    {	// LR8RC
7984      0,	// sub_32
7985      0,	// sub_64
7986      0,	// sub_dmr0
7987      0,	// sub_dmr1
7988      0,	// sub_dmrrow0
7989      0,	// sub_dmrrow1
7990      0,	// sub_dmrrowp0
7991      0,	// sub_dmrrowp1
7992      0,	// sub_eq
7993      0,	// sub_gp8_x0
7994      0,	// sub_gp8_x1
7995      0,	// sub_gt
7996      0,	// sub_lt
7997      0,	// sub_pair0
7998      0,	// sub_pair1
7999      0,	// sub_un
8000      0,	// sub_vsx0
8001      0,	// sub_vsx1
8002      0,	// sub_wacc_hi
8003      0,	// sub_wacc_lo
8004      0,	// sub_vsx1_then_sub_64
8005      0,	// sub_pair1_then_sub_64
8006      0,	// sub_pair1_then_sub_vsx0
8007      0,	// sub_pair1_then_sub_vsx1
8008      0,	// sub_pair1_then_sub_vsx1_then_sub_64
8009      0,	// sub_dmrrowp1_then_sub_dmrrow0
8010      0,	// sub_dmrrowp1_then_sub_dmrrow1
8011      0,	// sub_wacc_hi_then_sub_dmrrow0
8012      0,	// sub_wacc_hi_then_sub_dmrrow1
8013      0,	// sub_wacc_hi_then_sub_dmrrowp0
8014      0,	// sub_wacc_hi_then_sub_dmrrowp1
8015      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8016      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8017      0,	// sub_dmr1_then_sub_dmrrow0
8018      0,	// sub_dmr1_then_sub_dmrrow1
8019      0,	// sub_dmr1_then_sub_dmrrowp0
8020      0,	// sub_dmr1_then_sub_dmrrowp1
8021      0,	// sub_dmr1_then_sub_wacc_hi
8022      0,	// sub_dmr1_then_sub_wacc_lo
8023      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
8024      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
8025      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
8026      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
8027      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
8028      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
8029      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8030      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8031      0,	// sub_gp8_x1_then_sub_32
8032    },
8033    {	// DMRROWRC
8034      0,	// sub_32
8035      0,	// sub_64
8036      0,	// sub_dmr0
8037      0,	// sub_dmr1
8038      0,	// sub_dmrrow0
8039      0,	// sub_dmrrow1
8040      0,	// sub_dmrrowp0
8041      0,	// sub_dmrrowp1
8042      0,	// sub_eq
8043      0,	// sub_gp8_x0
8044      0,	// sub_gp8_x1
8045      0,	// sub_gt
8046      0,	// sub_lt
8047      0,	// sub_pair0
8048      0,	// sub_pair1
8049      0,	// sub_un
8050      0,	// sub_vsx0
8051      0,	// sub_vsx1
8052      0,	// sub_wacc_hi
8053      0,	// sub_wacc_lo
8054      0,	// sub_vsx1_then_sub_64
8055      0,	// sub_pair1_then_sub_64
8056      0,	// sub_pair1_then_sub_vsx0
8057      0,	// sub_pair1_then_sub_vsx1
8058      0,	// sub_pair1_then_sub_vsx1_then_sub_64
8059      0,	// sub_dmrrowp1_then_sub_dmrrow0
8060      0,	// sub_dmrrowp1_then_sub_dmrrow1
8061      0,	// sub_wacc_hi_then_sub_dmrrow0
8062      0,	// sub_wacc_hi_then_sub_dmrrow1
8063      0,	// sub_wacc_hi_then_sub_dmrrowp0
8064      0,	// sub_wacc_hi_then_sub_dmrrowp1
8065      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8066      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8067      0,	// sub_dmr1_then_sub_dmrrow0
8068      0,	// sub_dmr1_then_sub_dmrrow1
8069      0,	// sub_dmr1_then_sub_dmrrowp0
8070      0,	// sub_dmr1_then_sub_dmrrowp1
8071      0,	// sub_dmr1_then_sub_wacc_hi
8072      0,	// sub_dmr1_then_sub_wacc_lo
8073      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
8074      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
8075      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
8076      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
8077      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
8078      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
8079      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8080      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8081      0,	// sub_gp8_x1_then_sub_32
8082    },
8083    {	// VSRC
8084      0,	// sub_32
8085      27,	// sub_64 -> VSRC
8086      0,	// sub_dmr0
8087      0,	// sub_dmr1
8088      0,	// sub_dmrrow0
8089      0,	// sub_dmrrow1
8090      0,	// sub_dmrrowp0
8091      0,	// sub_dmrrowp1
8092      0,	// sub_eq
8093      0,	// sub_gp8_x0
8094      0,	// sub_gp8_x1
8095      0,	// sub_gt
8096      0,	// sub_lt
8097      0,	// sub_pair0
8098      0,	// sub_pair1
8099      0,	// sub_un
8100      0,	// sub_vsx0
8101      0,	// sub_vsx1
8102      0,	// sub_wacc_hi
8103      0,	// sub_wacc_lo
8104      0,	// sub_vsx1_then_sub_64
8105      0,	// sub_pair1_then_sub_64
8106      0,	// sub_pair1_then_sub_vsx0
8107      0,	// sub_pair1_then_sub_vsx1
8108      0,	// sub_pair1_then_sub_vsx1_then_sub_64
8109      0,	// sub_dmrrowp1_then_sub_dmrrow0
8110      0,	// sub_dmrrowp1_then_sub_dmrrow1
8111      0,	// sub_wacc_hi_then_sub_dmrrow0
8112      0,	// sub_wacc_hi_then_sub_dmrrow1
8113      0,	// sub_wacc_hi_then_sub_dmrrowp0
8114      0,	// sub_wacc_hi_then_sub_dmrrowp1
8115      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8116      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8117      0,	// sub_dmr1_then_sub_dmrrow0
8118      0,	// sub_dmr1_then_sub_dmrrow1
8119      0,	// sub_dmr1_then_sub_dmrrowp0
8120      0,	// sub_dmr1_then_sub_dmrrowp1
8121      0,	// sub_dmr1_then_sub_wacc_hi
8122      0,	// sub_dmr1_then_sub_wacc_lo
8123      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
8124      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
8125      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
8126      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
8127      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
8128      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
8129      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8130      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8131      0,	// sub_gp8_x1_then_sub_32
8132    },
8133    {	// VSRC_with_sub_64_in_SPILLTOVSRRC
8134      0,	// sub_32
8135      28,	// sub_64 -> VSRC_with_sub_64_in_SPILLTOVSRRC
8136      0,	// sub_dmr0
8137      0,	// sub_dmr1
8138      0,	// sub_dmrrow0
8139      0,	// sub_dmrrow1
8140      0,	// sub_dmrrowp0
8141      0,	// sub_dmrrowp1
8142      0,	// sub_eq
8143      0,	// sub_gp8_x0
8144      0,	// sub_gp8_x1
8145      0,	// sub_gt
8146      0,	// sub_lt
8147      0,	// sub_pair0
8148      0,	// sub_pair1
8149      0,	// sub_un
8150      0,	// sub_vsx0
8151      0,	// sub_vsx1
8152      0,	// sub_wacc_hi
8153      0,	// sub_wacc_lo
8154      0,	// sub_vsx1_then_sub_64
8155      0,	// sub_pair1_then_sub_64
8156      0,	// sub_pair1_then_sub_vsx0
8157      0,	// sub_pair1_then_sub_vsx1
8158      0,	// sub_pair1_then_sub_vsx1_then_sub_64
8159      0,	// sub_dmrrowp1_then_sub_dmrrow0
8160      0,	// sub_dmrrowp1_then_sub_dmrrow1
8161      0,	// sub_wacc_hi_then_sub_dmrrow0
8162      0,	// sub_wacc_hi_then_sub_dmrrow1
8163      0,	// sub_wacc_hi_then_sub_dmrrowp0
8164      0,	// sub_wacc_hi_then_sub_dmrrowp1
8165      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8166      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8167      0,	// sub_dmr1_then_sub_dmrrow0
8168      0,	// sub_dmr1_then_sub_dmrrow1
8169      0,	// sub_dmr1_then_sub_dmrrowp0
8170      0,	// sub_dmr1_then_sub_dmrrowp1
8171      0,	// sub_dmr1_then_sub_wacc_hi
8172      0,	// sub_dmr1_then_sub_wacc_lo
8173      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
8174      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
8175      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
8176      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
8177      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
8178      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
8179      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8180      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8181      0,	// sub_gp8_x1_then_sub_32
8182    },
8183    {	// VRRC
8184      0,	// sub_32
8185      29,	// sub_64 -> VRRC
8186      0,	// sub_dmr0
8187      0,	// sub_dmr1
8188      0,	// sub_dmrrow0
8189      0,	// sub_dmrrow1
8190      0,	// sub_dmrrowp0
8191      0,	// sub_dmrrowp1
8192      0,	// sub_eq
8193      0,	// sub_gp8_x0
8194      0,	// sub_gp8_x1
8195      0,	// sub_gt
8196      0,	// sub_lt
8197      0,	// sub_pair0
8198      0,	// sub_pair1
8199      0,	// sub_un
8200      0,	// sub_vsx0
8201      0,	// sub_vsx1
8202      0,	// sub_wacc_hi
8203      0,	// sub_wacc_lo
8204      0,	// sub_vsx1_then_sub_64
8205      0,	// sub_pair1_then_sub_64
8206      0,	// sub_pair1_then_sub_vsx0
8207      0,	// sub_pair1_then_sub_vsx1
8208      0,	// sub_pair1_then_sub_vsx1_then_sub_64
8209      0,	// sub_dmrrowp1_then_sub_dmrrow0
8210      0,	// sub_dmrrowp1_then_sub_dmrrow1
8211      0,	// sub_wacc_hi_then_sub_dmrrow0
8212      0,	// sub_wacc_hi_then_sub_dmrrow1
8213      0,	// sub_wacc_hi_then_sub_dmrrowp0
8214      0,	// sub_wacc_hi_then_sub_dmrrowp1
8215      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8216      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8217      0,	// sub_dmr1_then_sub_dmrrow0
8218      0,	// sub_dmr1_then_sub_dmrrow1
8219      0,	// sub_dmr1_then_sub_dmrrowp0
8220      0,	// sub_dmr1_then_sub_dmrrowp1
8221      0,	// sub_dmr1_then_sub_wacc_hi
8222      0,	// sub_dmr1_then_sub_wacc_lo
8223      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
8224      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
8225      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
8226      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
8227      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
8228      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
8229      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8230      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8231      0,	// sub_gp8_x1_then_sub_32
8232    },
8233    {	// VSLRC
8234      0,	// sub_32
8235      30,	// sub_64 -> VSLRC
8236      0,	// sub_dmr0
8237      0,	// sub_dmr1
8238      0,	// sub_dmrrow0
8239      0,	// sub_dmrrow1
8240      0,	// sub_dmrrowp0
8241      0,	// sub_dmrrowp1
8242      0,	// sub_eq
8243      0,	// sub_gp8_x0
8244      0,	// sub_gp8_x1
8245      0,	// sub_gt
8246      0,	// sub_lt
8247      0,	// sub_pair0
8248      0,	// sub_pair1
8249      0,	// sub_un
8250      0,	// sub_vsx0
8251      0,	// sub_vsx1
8252      0,	// sub_wacc_hi
8253      0,	// sub_wacc_lo
8254      0,	// sub_vsx1_then_sub_64
8255      0,	// sub_pair1_then_sub_64
8256      0,	// sub_pair1_then_sub_vsx0
8257      0,	// sub_pair1_then_sub_vsx1
8258      0,	// sub_pair1_then_sub_vsx1_then_sub_64
8259      0,	// sub_dmrrowp1_then_sub_dmrrow0
8260      0,	// sub_dmrrowp1_then_sub_dmrrow1
8261      0,	// sub_wacc_hi_then_sub_dmrrow0
8262      0,	// sub_wacc_hi_then_sub_dmrrow1
8263      0,	// sub_wacc_hi_then_sub_dmrrowp0
8264      0,	// sub_wacc_hi_then_sub_dmrrowp1
8265      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8266      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8267      0,	// sub_dmr1_then_sub_dmrrow0
8268      0,	// sub_dmr1_then_sub_dmrrow1
8269      0,	// sub_dmr1_then_sub_dmrrowp0
8270      0,	// sub_dmr1_then_sub_dmrrowp1
8271      0,	// sub_dmr1_then_sub_wacc_hi
8272      0,	// sub_dmr1_then_sub_wacc_lo
8273      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
8274      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
8275      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
8276      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
8277      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
8278      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
8279      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8280      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8281      0,	// sub_gp8_x1_then_sub_32
8282    },
8283    {	// VRRC_with_sub_64_in_SPILLTOVSRRC
8284      0,	// sub_32
8285      31,	// sub_64 -> VRRC_with_sub_64_in_SPILLTOVSRRC
8286      0,	// sub_dmr0
8287      0,	// sub_dmr1
8288      0,	// sub_dmrrow0
8289      0,	// sub_dmrrow1
8290      0,	// sub_dmrrowp0
8291      0,	// sub_dmrrowp1
8292      0,	// sub_eq
8293      0,	// sub_gp8_x0
8294      0,	// sub_gp8_x1
8295      0,	// sub_gt
8296      0,	// sub_lt
8297      0,	// sub_pair0
8298      0,	// sub_pair1
8299      0,	// sub_un
8300      0,	// sub_vsx0
8301      0,	// sub_vsx1
8302      0,	// sub_wacc_hi
8303      0,	// sub_wacc_lo
8304      0,	// sub_vsx1_then_sub_64
8305      0,	// sub_pair1_then_sub_64
8306      0,	// sub_pair1_then_sub_vsx0
8307      0,	// sub_pair1_then_sub_vsx1
8308      0,	// sub_pair1_then_sub_vsx1_then_sub_64
8309      0,	// sub_dmrrowp1_then_sub_dmrrow0
8310      0,	// sub_dmrrowp1_then_sub_dmrrow1
8311      0,	// sub_wacc_hi_then_sub_dmrrow0
8312      0,	// sub_wacc_hi_then_sub_dmrrow1
8313      0,	// sub_wacc_hi_then_sub_dmrrowp0
8314      0,	// sub_wacc_hi_then_sub_dmrrowp1
8315      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8316      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8317      0,	// sub_dmr1_then_sub_dmrrow0
8318      0,	// sub_dmr1_then_sub_dmrrow1
8319      0,	// sub_dmr1_then_sub_dmrrowp0
8320      0,	// sub_dmr1_then_sub_dmrrowp1
8321      0,	// sub_dmr1_then_sub_wacc_hi
8322      0,	// sub_dmr1_then_sub_wacc_lo
8323      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
8324      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
8325      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
8326      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
8327      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
8328      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
8329      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8330      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8331      0,	// sub_gp8_x1_then_sub_32
8332    },
8333    {	// G8pRC
8334      32,	// sub_32 -> G8pRC
8335      0,	// sub_64
8336      0,	// sub_dmr0
8337      0,	// sub_dmr1
8338      0,	// sub_dmrrow0
8339      0,	// sub_dmrrow1
8340      0,	// sub_dmrrowp0
8341      0,	// sub_dmrrowp1
8342      0,	// sub_eq
8343      32,	// sub_gp8_x0 -> G8pRC
8344      32,	// sub_gp8_x1 -> G8pRC
8345      0,	// sub_gt
8346      0,	// sub_lt
8347      0,	// sub_pair0
8348      0,	// sub_pair1
8349      0,	// sub_un
8350      0,	// sub_vsx0
8351      0,	// sub_vsx1
8352      0,	// sub_wacc_hi
8353      0,	// sub_wacc_lo
8354      0,	// sub_vsx1_then_sub_64
8355      0,	// sub_pair1_then_sub_64
8356      0,	// sub_pair1_then_sub_vsx0
8357      0,	// sub_pair1_then_sub_vsx1
8358      0,	// sub_pair1_then_sub_vsx1_then_sub_64
8359      0,	// sub_dmrrowp1_then_sub_dmrrow0
8360      0,	// sub_dmrrowp1_then_sub_dmrrow1
8361      0,	// sub_wacc_hi_then_sub_dmrrow0
8362      0,	// sub_wacc_hi_then_sub_dmrrow1
8363      0,	// sub_wacc_hi_then_sub_dmrrowp0
8364      0,	// sub_wacc_hi_then_sub_dmrrowp1
8365      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8366      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8367      0,	// sub_dmr1_then_sub_dmrrow0
8368      0,	// sub_dmr1_then_sub_dmrrow1
8369      0,	// sub_dmr1_then_sub_dmrrowp0
8370      0,	// sub_dmr1_then_sub_dmrrowp1
8371      0,	// sub_dmr1_then_sub_wacc_hi
8372      0,	// sub_dmr1_then_sub_wacc_lo
8373      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
8374      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
8375      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
8376      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
8377      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
8378      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
8379      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8380      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8381      32,	// sub_gp8_x1_then_sub_32 -> G8pRC
8382    },
8383    {	// G8pRC_with_sub_32_in_GPRC_NOR0
8384      33,	// sub_32 -> G8pRC_with_sub_32_in_GPRC_NOR0
8385      0,	// sub_64
8386      0,	// sub_dmr0
8387      0,	// sub_dmr1
8388      0,	// sub_dmrrow0
8389      0,	// sub_dmrrow1
8390      0,	// sub_dmrrowp0
8391      0,	// sub_dmrrowp1
8392      0,	// sub_eq
8393      33,	// sub_gp8_x0 -> G8pRC_with_sub_32_in_GPRC_NOR0
8394      33,	// sub_gp8_x1 -> G8pRC_with_sub_32_in_GPRC_NOR0
8395      0,	// sub_gt
8396      0,	// sub_lt
8397      0,	// sub_pair0
8398      0,	// sub_pair1
8399      0,	// sub_un
8400      0,	// sub_vsx0
8401      0,	// sub_vsx1
8402      0,	// sub_wacc_hi
8403      0,	// sub_wacc_lo
8404      0,	// sub_vsx1_then_sub_64
8405      0,	// sub_pair1_then_sub_64
8406      0,	// sub_pair1_then_sub_vsx0
8407      0,	// sub_pair1_then_sub_vsx1
8408      0,	// sub_pair1_then_sub_vsx1_then_sub_64
8409      0,	// sub_dmrrowp1_then_sub_dmrrow0
8410      0,	// sub_dmrrowp1_then_sub_dmrrow1
8411      0,	// sub_wacc_hi_then_sub_dmrrow0
8412      0,	// sub_wacc_hi_then_sub_dmrrow1
8413      0,	// sub_wacc_hi_then_sub_dmrrowp0
8414      0,	// sub_wacc_hi_then_sub_dmrrowp1
8415      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8416      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8417      0,	// sub_dmr1_then_sub_dmrrow0
8418      0,	// sub_dmr1_then_sub_dmrrow1
8419      0,	// sub_dmr1_then_sub_dmrrowp0
8420      0,	// sub_dmr1_then_sub_dmrrowp1
8421      0,	// sub_dmr1_then_sub_wacc_hi
8422      0,	// sub_dmr1_then_sub_wacc_lo
8423      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
8424      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
8425      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
8426      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
8427      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
8428      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
8429      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8430      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8431      33,	// sub_gp8_x1_then_sub_32 -> G8pRC_with_sub_32_in_GPRC_NOR0
8432    },
8433    {	// VSLRC_with_sub_64_in_SPILLTOVSRRC
8434      0,	// sub_32
8435      34,	// sub_64 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
8436      0,	// sub_dmr0
8437      0,	// sub_dmr1
8438      0,	// sub_dmrrow0
8439      0,	// sub_dmrrow1
8440      0,	// sub_dmrrowp0
8441      0,	// sub_dmrrowp1
8442      0,	// sub_eq
8443      0,	// sub_gp8_x0
8444      0,	// sub_gp8_x1
8445      0,	// sub_gt
8446      0,	// sub_lt
8447      0,	// sub_pair0
8448      0,	// sub_pair1
8449      0,	// sub_un
8450      0,	// sub_vsx0
8451      0,	// sub_vsx1
8452      0,	// sub_wacc_hi
8453      0,	// sub_wacc_lo
8454      0,	// sub_vsx1_then_sub_64
8455      0,	// sub_pair1_then_sub_64
8456      0,	// sub_pair1_then_sub_vsx0
8457      0,	// sub_pair1_then_sub_vsx1
8458      0,	// sub_pair1_then_sub_vsx1_then_sub_64
8459      0,	// sub_dmrrowp1_then_sub_dmrrow0
8460      0,	// sub_dmrrowp1_then_sub_dmrrow1
8461      0,	// sub_wacc_hi_then_sub_dmrrow0
8462      0,	// sub_wacc_hi_then_sub_dmrrow1
8463      0,	// sub_wacc_hi_then_sub_dmrrowp0
8464      0,	// sub_wacc_hi_then_sub_dmrrowp1
8465      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8466      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8467      0,	// sub_dmr1_then_sub_dmrrow0
8468      0,	// sub_dmr1_then_sub_dmrrow1
8469      0,	// sub_dmr1_then_sub_dmrrowp0
8470      0,	// sub_dmr1_then_sub_dmrrowp1
8471      0,	// sub_dmr1_then_sub_wacc_hi
8472      0,	// sub_dmr1_then_sub_wacc_lo
8473      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
8474      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
8475      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
8476      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
8477      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
8478      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
8479      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8480      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8481      0,	// sub_gp8_x1_then_sub_32
8482    },
8483    {	// DMRROWpRC
8484      0,	// sub_32
8485      0,	// sub_64
8486      0,	// sub_dmr0
8487      0,	// sub_dmr1
8488      35,	// sub_dmrrow0 -> DMRROWpRC
8489      35,	// sub_dmrrow1 -> DMRROWpRC
8490      0,	// sub_dmrrowp0
8491      0,	// sub_dmrrowp1
8492      0,	// sub_eq
8493      0,	// sub_gp8_x0
8494      0,	// sub_gp8_x1
8495      0,	// sub_gt
8496      0,	// sub_lt
8497      0,	// sub_pair0
8498      0,	// sub_pair1
8499      0,	// sub_un
8500      0,	// sub_vsx0
8501      0,	// sub_vsx1
8502      0,	// sub_wacc_hi
8503      0,	// sub_wacc_lo
8504      0,	// sub_vsx1_then_sub_64
8505      0,	// sub_pair1_then_sub_64
8506      0,	// sub_pair1_then_sub_vsx0
8507      0,	// sub_pair1_then_sub_vsx1
8508      0,	// sub_pair1_then_sub_vsx1_then_sub_64
8509      0,	// sub_dmrrowp1_then_sub_dmrrow0
8510      0,	// sub_dmrrowp1_then_sub_dmrrow1
8511      0,	// sub_wacc_hi_then_sub_dmrrow0
8512      0,	// sub_wacc_hi_then_sub_dmrrow1
8513      0,	// sub_wacc_hi_then_sub_dmrrowp0
8514      0,	// sub_wacc_hi_then_sub_dmrrowp1
8515      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8516      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8517      0,	// sub_dmr1_then_sub_dmrrow0
8518      0,	// sub_dmr1_then_sub_dmrrow1
8519      0,	// sub_dmr1_then_sub_dmrrowp0
8520      0,	// sub_dmr1_then_sub_dmrrowp1
8521      0,	// sub_dmr1_then_sub_wacc_hi
8522      0,	// sub_dmr1_then_sub_wacc_lo
8523      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
8524      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
8525      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
8526      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
8527      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
8528      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
8529      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8530      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8531      0,	// sub_gp8_x1_then_sub_32
8532    },
8533    {	// VSRpRC
8534      0,	// sub_32
8535      36,	// sub_64 -> VSRpRC
8536      0,	// sub_dmr0
8537      0,	// sub_dmr1
8538      0,	// sub_dmrrow0
8539      0,	// sub_dmrrow1
8540      0,	// sub_dmrrowp0
8541      0,	// sub_dmrrowp1
8542      0,	// sub_eq
8543      0,	// sub_gp8_x0
8544      0,	// sub_gp8_x1
8545      0,	// sub_gt
8546      0,	// sub_lt
8547      0,	// sub_pair0
8548      0,	// sub_pair1
8549      0,	// sub_un
8550      36,	// sub_vsx0 -> VSRpRC
8551      36,	// sub_vsx1 -> VSRpRC
8552      0,	// sub_wacc_hi
8553      0,	// sub_wacc_lo
8554      36,	// sub_vsx1_then_sub_64 -> VSRpRC
8555      0,	// sub_pair1_then_sub_64
8556      0,	// sub_pair1_then_sub_vsx0
8557      0,	// sub_pair1_then_sub_vsx1
8558      0,	// sub_pair1_then_sub_vsx1_then_sub_64
8559      0,	// sub_dmrrowp1_then_sub_dmrrow0
8560      0,	// sub_dmrrowp1_then_sub_dmrrow1
8561      0,	// sub_wacc_hi_then_sub_dmrrow0
8562      0,	// sub_wacc_hi_then_sub_dmrrow1
8563      0,	// sub_wacc_hi_then_sub_dmrrowp0
8564      0,	// sub_wacc_hi_then_sub_dmrrowp1
8565      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8566      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8567      0,	// sub_dmr1_then_sub_dmrrow0
8568      0,	// sub_dmr1_then_sub_dmrrow1
8569      0,	// sub_dmr1_then_sub_dmrrowp0
8570      0,	// sub_dmr1_then_sub_dmrrowp1
8571      0,	// sub_dmr1_then_sub_wacc_hi
8572      0,	// sub_dmr1_then_sub_wacc_lo
8573      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
8574      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
8575      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
8576      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
8577      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
8578      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
8579      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8580      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8581      0,	// sub_gp8_x1_then_sub_32
8582    },
8583    {	// VSRpRC_with_sub_64_in_SPILLTOVSRRC
8584      0,	// sub_32
8585      37,	// sub_64 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC
8586      0,	// sub_dmr0
8587      0,	// sub_dmr1
8588      0,	// sub_dmrrow0
8589      0,	// sub_dmrrow1
8590      0,	// sub_dmrrowp0
8591      0,	// sub_dmrrowp1
8592      0,	// sub_eq
8593      0,	// sub_gp8_x0
8594      0,	// sub_gp8_x1
8595      0,	// sub_gt
8596      0,	// sub_lt
8597      0,	// sub_pair0
8598      0,	// sub_pair1
8599      0,	// sub_un
8600      37,	// sub_vsx0 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC
8601      37,	// sub_vsx1 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC
8602      0,	// sub_wacc_hi
8603      0,	// sub_wacc_lo
8604      37,	// sub_vsx1_then_sub_64 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC
8605      0,	// sub_pair1_then_sub_64
8606      0,	// sub_pair1_then_sub_vsx0
8607      0,	// sub_pair1_then_sub_vsx1
8608      0,	// sub_pair1_then_sub_vsx1_then_sub_64
8609      0,	// sub_dmrrowp1_then_sub_dmrrow0
8610      0,	// sub_dmrrowp1_then_sub_dmrrow1
8611      0,	// sub_wacc_hi_then_sub_dmrrow0
8612      0,	// sub_wacc_hi_then_sub_dmrrow1
8613      0,	// sub_wacc_hi_then_sub_dmrrowp0
8614      0,	// sub_wacc_hi_then_sub_dmrrowp1
8615      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8616      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8617      0,	// sub_dmr1_then_sub_dmrrow0
8618      0,	// sub_dmr1_then_sub_dmrrow1
8619      0,	// sub_dmr1_then_sub_dmrrowp0
8620      0,	// sub_dmr1_then_sub_dmrrowp1
8621      0,	// sub_dmr1_then_sub_wacc_hi
8622      0,	// sub_dmr1_then_sub_wacc_lo
8623      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
8624      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
8625      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
8626      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
8627      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
8628      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
8629      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8630      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8631      0,	// sub_gp8_x1_then_sub_32
8632    },
8633    {	// VSRpRC_with_sub_64_in_F4RC
8634      0,	// sub_32
8635      38,	// sub_64 -> VSRpRC_with_sub_64_in_F4RC
8636      0,	// sub_dmr0
8637      0,	// sub_dmr1
8638      0,	// sub_dmrrow0
8639      0,	// sub_dmrrow1
8640      0,	// sub_dmrrowp0
8641      0,	// sub_dmrrowp1
8642      0,	// sub_eq
8643      0,	// sub_gp8_x0
8644      0,	// sub_gp8_x1
8645      0,	// sub_gt
8646      0,	// sub_lt
8647      0,	// sub_pair0
8648      0,	// sub_pair1
8649      0,	// sub_un
8650      38,	// sub_vsx0 -> VSRpRC_with_sub_64_in_F4RC
8651      38,	// sub_vsx1 -> VSRpRC_with_sub_64_in_F4RC
8652      0,	// sub_wacc_hi
8653      0,	// sub_wacc_lo
8654      38,	// sub_vsx1_then_sub_64 -> VSRpRC_with_sub_64_in_F4RC
8655      0,	// sub_pair1_then_sub_64
8656      0,	// sub_pair1_then_sub_vsx0
8657      0,	// sub_pair1_then_sub_vsx1
8658      0,	// sub_pair1_then_sub_vsx1_then_sub_64
8659      0,	// sub_dmrrowp1_then_sub_dmrrow0
8660      0,	// sub_dmrrowp1_then_sub_dmrrow1
8661      0,	// sub_wacc_hi_then_sub_dmrrow0
8662      0,	// sub_wacc_hi_then_sub_dmrrow1
8663      0,	// sub_wacc_hi_then_sub_dmrrowp0
8664      0,	// sub_wacc_hi_then_sub_dmrrowp1
8665      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8666      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8667      0,	// sub_dmr1_then_sub_dmrrow0
8668      0,	// sub_dmr1_then_sub_dmrrow1
8669      0,	// sub_dmr1_then_sub_dmrrowp0
8670      0,	// sub_dmr1_then_sub_dmrrowp1
8671      0,	// sub_dmr1_then_sub_wacc_hi
8672      0,	// sub_dmr1_then_sub_wacc_lo
8673      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
8674      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
8675      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
8676      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
8677      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
8678      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
8679      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8680      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8681      0,	// sub_gp8_x1_then_sub_32
8682    },
8683    {	// VSRpRC_with_sub_64_in_VFRC
8684      0,	// sub_32
8685      39,	// sub_64 -> VSRpRC_with_sub_64_in_VFRC
8686      0,	// sub_dmr0
8687      0,	// sub_dmr1
8688      0,	// sub_dmrrow0
8689      0,	// sub_dmrrow1
8690      0,	// sub_dmrrowp0
8691      0,	// sub_dmrrowp1
8692      0,	// sub_eq
8693      0,	// sub_gp8_x0
8694      0,	// sub_gp8_x1
8695      0,	// sub_gt
8696      0,	// sub_lt
8697      0,	// sub_pair0
8698      0,	// sub_pair1
8699      0,	// sub_un
8700      39,	// sub_vsx0 -> VSRpRC_with_sub_64_in_VFRC
8701      39,	// sub_vsx1 -> VSRpRC_with_sub_64_in_VFRC
8702      0,	// sub_wacc_hi
8703      0,	// sub_wacc_lo
8704      39,	// sub_vsx1_then_sub_64 -> VSRpRC_with_sub_64_in_VFRC
8705      0,	// sub_pair1_then_sub_64
8706      0,	// sub_pair1_then_sub_vsx0
8707      0,	// sub_pair1_then_sub_vsx1
8708      0,	// sub_pair1_then_sub_vsx1_then_sub_64
8709      0,	// sub_dmrrowp1_then_sub_dmrrow0
8710      0,	// sub_dmrrowp1_then_sub_dmrrow1
8711      0,	// sub_wacc_hi_then_sub_dmrrow0
8712      0,	// sub_wacc_hi_then_sub_dmrrow1
8713      0,	// sub_wacc_hi_then_sub_dmrrowp0
8714      0,	// sub_wacc_hi_then_sub_dmrrowp1
8715      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8716      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8717      0,	// sub_dmr1_then_sub_dmrrow0
8718      0,	// sub_dmr1_then_sub_dmrrow1
8719      0,	// sub_dmr1_then_sub_dmrrowp0
8720      0,	// sub_dmr1_then_sub_dmrrowp1
8721      0,	// sub_dmr1_then_sub_wacc_hi
8722      0,	// sub_dmr1_then_sub_wacc_lo
8723      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
8724      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
8725      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
8726      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
8727      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
8728      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
8729      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8730      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8731      0,	// sub_gp8_x1_then_sub_32
8732    },
8733    {	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC
8734      0,	// sub_32
8735      40,	// sub_64 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC
8736      0,	// sub_dmr0
8737      0,	// sub_dmr1
8738      0,	// sub_dmrrow0
8739      0,	// sub_dmrrow1
8740      0,	// sub_dmrrowp0
8741      0,	// sub_dmrrowp1
8742      0,	// sub_eq
8743      0,	// sub_gp8_x0
8744      0,	// sub_gp8_x1
8745      0,	// sub_gt
8746      0,	// sub_lt
8747      0,	// sub_pair0
8748      0,	// sub_pair1
8749      0,	// sub_un
8750      40,	// sub_vsx0 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC
8751      40,	// sub_vsx1 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC
8752      0,	// sub_wacc_hi
8753      0,	// sub_wacc_lo
8754      40,	// sub_vsx1_then_sub_64 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC
8755      0,	// sub_pair1_then_sub_64
8756      0,	// sub_pair1_then_sub_vsx0
8757      0,	// sub_pair1_then_sub_vsx1
8758      0,	// sub_pair1_then_sub_vsx1_then_sub_64
8759      0,	// sub_dmrrowp1_then_sub_dmrrow0
8760      0,	// sub_dmrrowp1_then_sub_dmrrow1
8761      0,	// sub_wacc_hi_then_sub_dmrrow0
8762      0,	// sub_wacc_hi_then_sub_dmrrow1
8763      0,	// sub_wacc_hi_then_sub_dmrrowp0
8764      0,	// sub_wacc_hi_then_sub_dmrrowp1
8765      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8766      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8767      0,	// sub_dmr1_then_sub_dmrrow0
8768      0,	// sub_dmr1_then_sub_dmrrow1
8769      0,	// sub_dmr1_then_sub_dmrrowp0
8770      0,	// sub_dmr1_then_sub_dmrrowp1
8771      0,	// sub_dmr1_then_sub_wacc_hi
8772      0,	// sub_dmr1_then_sub_wacc_lo
8773      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
8774      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
8775      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
8776      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
8777      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
8778      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
8779      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8780      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8781      0,	// sub_gp8_x1_then_sub_32
8782    },
8783    {	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
8784      0,	// sub_32
8785      41,	// sub_64 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
8786      0,	// sub_dmr0
8787      0,	// sub_dmr1
8788      0,	// sub_dmrrow0
8789      0,	// sub_dmrrow1
8790      0,	// sub_dmrrowp0
8791      0,	// sub_dmrrowp1
8792      0,	// sub_eq
8793      0,	// sub_gp8_x0
8794      0,	// sub_gp8_x1
8795      0,	// sub_gt
8796      0,	// sub_lt
8797      0,	// sub_pair0
8798      0,	// sub_pair1
8799      0,	// sub_un
8800      41,	// sub_vsx0 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
8801      41,	// sub_vsx1 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
8802      0,	// sub_wacc_hi
8803      0,	// sub_wacc_lo
8804      41,	// sub_vsx1_then_sub_64 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
8805      0,	// sub_pair1_then_sub_64
8806      0,	// sub_pair1_then_sub_vsx0
8807      0,	// sub_pair1_then_sub_vsx1
8808      0,	// sub_pair1_then_sub_vsx1_then_sub_64
8809      0,	// sub_dmrrowp1_then_sub_dmrrow0
8810      0,	// sub_dmrrowp1_then_sub_dmrrow1
8811      0,	// sub_wacc_hi_then_sub_dmrrow0
8812      0,	// sub_wacc_hi_then_sub_dmrrow1
8813      0,	// sub_wacc_hi_then_sub_dmrrowp0
8814      0,	// sub_wacc_hi_then_sub_dmrrowp1
8815      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8816      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8817      0,	// sub_dmr1_then_sub_dmrrow0
8818      0,	// sub_dmr1_then_sub_dmrrow1
8819      0,	// sub_dmr1_then_sub_dmrrowp0
8820      0,	// sub_dmr1_then_sub_dmrrowp1
8821      0,	// sub_dmr1_then_sub_wacc_hi
8822      0,	// sub_dmr1_then_sub_wacc_lo
8823      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
8824      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
8825      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
8826      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
8827      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
8828      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
8829      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8830      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8831      0,	// sub_gp8_x1_then_sub_32
8832    },
8833    {	// ACCRC
8834      0,	// sub_32
8835      42,	// sub_64 -> ACCRC
8836      0,	// sub_dmr0
8837      0,	// sub_dmr1
8838      0,	// sub_dmrrow0
8839      0,	// sub_dmrrow1
8840      0,	// sub_dmrrowp0
8841      0,	// sub_dmrrowp1
8842      0,	// sub_eq
8843      0,	// sub_gp8_x0
8844      0,	// sub_gp8_x1
8845      0,	// sub_gt
8846      0,	// sub_lt
8847      42,	// sub_pair0 -> ACCRC
8848      42,	// sub_pair1 -> ACCRC
8849      0,	// sub_un
8850      42,	// sub_vsx0 -> ACCRC
8851      42,	// sub_vsx1 -> ACCRC
8852      0,	// sub_wacc_hi
8853      0,	// sub_wacc_lo
8854      42,	// sub_vsx1_then_sub_64 -> ACCRC
8855      42,	// sub_pair1_then_sub_64 -> ACCRC
8856      42,	// sub_pair1_then_sub_vsx0 -> ACCRC
8857      42,	// sub_pair1_then_sub_vsx1 -> ACCRC
8858      42,	// sub_pair1_then_sub_vsx1_then_sub_64 -> ACCRC
8859      0,	// sub_dmrrowp1_then_sub_dmrrow0
8860      0,	// sub_dmrrowp1_then_sub_dmrrow1
8861      0,	// sub_wacc_hi_then_sub_dmrrow0
8862      0,	// sub_wacc_hi_then_sub_dmrrow1
8863      0,	// sub_wacc_hi_then_sub_dmrrowp0
8864      0,	// sub_wacc_hi_then_sub_dmrrowp1
8865      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8866      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8867      0,	// sub_dmr1_then_sub_dmrrow0
8868      0,	// sub_dmr1_then_sub_dmrrow1
8869      0,	// sub_dmr1_then_sub_dmrrowp0
8870      0,	// sub_dmr1_then_sub_dmrrowp1
8871      0,	// sub_dmr1_then_sub_wacc_hi
8872      0,	// sub_dmr1_then_sub_wacc_lo
8873      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
8874      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
8875      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
8876      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
8877      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
8878      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
8879      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8880      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8881      0,	// sub_gp8_x1_then_sub_32
8882    },
8883    {	// UACCRC
8884      0,	// sub_32
8885      43,	// sub_64 -> UACCRC
8886      0,	// sub_dmr0
8887      0,	// sub_dmr1
8888      0,	// sub_dmrrow0
8889      0,	// sub_dmrrow1
8890      0,	// sub_dmrrowp0
8891      0,	// sub_dmrrowp1
8892      0,	// sub_eq
8893      0,	// sub_gp8_x0
8894      0,	// sub_gp8_x1
8895      0,	// sub_gt
8896      0,	// sub_lt
8897      43,	// sub_pair0 -> UACCRC
8898      43,	// sub_pair1 -> UACCRC
8899      0,	// sub_un
8900      43,	// sub_vsx0 -> UACCRC
8901      43,	// sub_vsx1 -> UACCRC
8902      0,	// sub_wacc_hi
8903      0,	// sub_wacc_lo
8904      43,	// sub_vsx1_then_sub_64 -> UACCRC
8905      43,	// sub_pair1_then_sub_64 -> UACCRC
8906      43,	// sub_pair1_then_sub_vsx0 -> UACCRC
8907      43,	// sub_pair1_then_sub_vsx1 -> UACCRC
8908      43,	// sub_pair1_then_sub_vsx1_then_sub_64 -> UACCRC
8909      0,	// sub_dmrrowp1_then_sub_dmrrow0
8910      0,	// sub_dmrrowp1_then_sub_dmrrow1
8911      0,	// sub_wacc_hi_then_sub_dmrrow0
8912      0,	// sub_wacc_hi_then_sub_dmrrow1
8913      0,	// sub_wacc_hi_then_sub_dmrrowp0
8914      0,	// sub_wacc_hi_then_sub_dmrrowp1
8915      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8916      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8917      0,	// sub_dmr1_then_sub_dmrrow0
8918      0,	// sub_dmr1_then_sub_dmrrow1
8919      0,	// sub_dmr1_then_sub_dmrrowp0
8920      0,	// sub_dmr1_then_sub_dmrrowp1
8921      0,	// sub_dmr1_then_sub_wacc_hi
8922      0,	// sub_dmr1_then_sub_wacc_lo
8923      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
8924      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
8925      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
8926      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
8927      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
8928      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
8929      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8930      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8931      0,	// sub_gp8_x1_then_sub_32
8932    },
8933    {	// WACCRC
8934      0,	// sub_32
8935      0,	// sub_64
8936      0,	// sub_dmr0
8937      0,	// sub_dmr1
8938      44,	// sub_dmrrow0 -> WACCRC
8939      44,	// sub_dmrrow1 -> WACCRC
8940      44,	// sub_dmrrowp0 -> WACCRC
8941      44,	// sub_dmrrowp1 -> WACCRC
8942      0,	// sub_eq
8943      0,	// sub_gp8_x0
8944      0,	// sub_gp8_x1
8945      0,	// sub_gt
8946      0,	// sub_lt
8947      0,	// sub_pair0
8948      0,	// sub_pair1
8949      0,	// sub_un
8950      0,	// sub_vsx0
8951      0,	// sub_vsx1
8952      0,	// sub_wacc_hi
8953      0,	// sub_wacc_lo
8954      0,	// sub_vsx1_then_sub_64
8955      0,	// sub_pair1_then_sub_64
8956      0,	// sub_pair1_then_sub_vsx0
8957      0,	// sub_pair1_then_sub_vsx1
8958      0,	// sub_pair1_then_sub_vsx1_then_sub_64
8959      44,	// sub_dmrrowp1_then_sub_dmrrow0 -> WACCRC
8960      44,	// sub_dmrrowp1_then_sub_dmrrow1 -> WACCRC
8961      0,	// sub_wacc_hi_then_sub_dmrrow0
8962      0,	// sub_wacc_hi_then_sub_dmrrow1
8963      0,	// sub_wacc_hi_then_sub_dmrrowp0
8964      0,	// sub_wacc_hi_then_sub_dmrrowp1
8965      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8966      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8967      0,	// sub_dmr1_then_sub_dmrrow0
8968      0,	// sub_dmr1_then_sub_dmrrow1
8969      0,	// sub_dmr1_then_sub_dmrrowp0
8970      0,	// sub_dmr1_then_sub_dmrrowp1
8971      0,	// sub_dmr1_then_sub_wacc_hi
8972      0,	// sub_dmr1_then_sub_wacc_lo
8973      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
8974      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
8975      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
8976      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
8977      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
8978      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
8979      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8980      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8981      0,	// sub_gp8_x1_then_sub_32
8982    },
8983    {	// WACC_HIRC
8984      0,	// sub_32
8985      0,	// sub_64
8986      0,	// sub_dmr0
8987      0,	// sub_dmr1
8988      45,	// sub_dmrrow0 -> WACC_HIRC
8989      45,	// sub_dmrrow1 -> WACC_HIRC
8990      45,	// sub_dmrrowp0 -> WACC_HIRC
8991      45,	// sub_dmrrowp1 -> WACC_HIRC
8992      0,	// sub_eq
8993      0,	// sub_gp8_x0
8994      0,	// sub_gp8_x1
8995      0,	// sub_gt
8996      0,	// sub_lt
8997      0,	// sub_pair0
8998      0,	// sub_pair1
8999      0,	// sub_un
9000      0,	// sub_vsx0
9001      0,	// sub_vsx1
9002      0,	// sub_wacc_hi
9003      0,	// sub_wacc_lo
9004      0,	// sub_vsx1_then_sub_64
9005      0,	// sub_pair1_then_sub_64
9006      0,	// sub_pair1_then_sub_vsx0
9007      0,	// sub_pair1_then_sub_vsx1
9008      0,	// sub_pair1_then_sub_vsx1_then_sub_64
9009      45,	// sub_dmrrowp1_then_sub_dmrrow0 -> WACC_HIRC
9010      45,	// sub_dmrrowp1_then_sub_dmrrow1 -> WACC_HIRC
9011      0,	// sub_wacc_hi_then_sub_dmrrow0
9012      0,	// sub_wacc_hi_then_sub_dmrrow1
9013      0,	// sub_wacc_hi_then_sub_dmrrowp0
9014      0,	// sub_wacc_hi_then_sub_dmrrowp1
9015      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9016      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9017      0,	// sub_dmr1_then_sub_dmrrow0
9018      0,	// sub_dmr1_then_sub_dmrrow1
9019      0,	// sub_dmr1_then_sub_dmrrowp0
9020      0,	// sub_dmr1_then_sub_dmrrowp1
9021      0,	// sub_dmr1_then_sub_wacc_hi
9022      0,	// sub_dmr1_then_sub_wacc_lo
9023      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
9024      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
9025      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
9026      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
9027      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
9028      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
9029      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9030      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9031      0,	// sub_gp8_x1_then_sub_32
9032    },
9033    {	// ACCRC_with_sub_64_in_SPILLTOVSRRC
9034      0,	// sub_32
9035      46,	// sub_64 -> ACCRC_with_sub_64_in_SPILLTOVSRRC
9036      0,	// sub_dmr0
9037      0,	// sub_dmr1
9038      0,	// sub_dmrrow0
9039      0,	// sub_dmrrow1
9040      0,	// sub_dmrrowp0
9041      0,	// sub_dmrrowp1
9042      0,	// sub_eq
9043      0,	// sub_gp8_x0
9044      0,	// sub_gp8_x1
9045      0,	// sub_gt
9046      0,	// sub_lt
9047      46,	// sub_pair0 -> ACCRC_with_sub_64_in_SPILLTOVSRRC
9048      46,	// sub_pair1 -> ACCRC_with_sub_64_in_SPILLTOVSRRC
9049      0,	// sub_un
9050      46,	// sub_vsx0 -> ACCRC_with_sub_64_in_SPILLTOVSRRC
9051      46,	// sub_vsx1 -> ACCRC_with_sub_64_in_SPILLTOVSRRC
9052      0,	// sub_wacc_hi
9053      0,	// sub_wacc_lo
9054      46,	// sub_vsx1_then_sub_64 -> ACCRC_with_sub_64_in_SPILLTOVSRRC
9055      46,	// sub_pair1_then_sub_64 -> ACCRC_with_sub_64_in_SPILLTOVSRRC
9056      46,	// sub_pair1_then_sub_vsx0 -> ACCRC_with_sub_64_in_SPILLTOVSRRC
9057      46,	// sub_pair1_then_sub_vsx1 -> ACCRC_with_sub_64_in_SPILLTOVSRRC
9058      46,	// sub_pair1_then_sub_vsx1_then_sub_64 -> ACCRC_with_sub_64_in_SPILLTOVSRRC
9059      0,	// sub_dmrrowp1_then_sub_dmrrow0
9060      0,	// sub_dmrrowp1_then_sub_dmrrow1
9061      0,	// sub_wacc_hi_then_sub_dmrrow0
9062      0,	// sub_wacc_hi_then_sub_dmrrow1
9063      0,	// sub_wacc_hi_then_sub_dmrrowp0
9064      0,	// sub_wacc_hi_then_sub_dmrrowp1
9065      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9066      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9067      0,	// sub_dmr1_then_sub_dmrrow0
9068      0,	// sub_dmr1_then_sub_dmrrow1
9069      0,	// sub_dmr1_then_sub_dmrrowp0
9070      0,	// sub_dmr1_then_sub_dmrrowp1
9071      0,	// sub_dmr1_then_sub_wacc_hi
9072      0,	// sub_dmr1_then_sub_wacc_lo
9073      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
9074      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
9075      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
9076      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
9077      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
9078      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
9079      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9080      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9081      0,	// sub_gp8_x1_then_sub_32
9082    },
9083    {	// UACCRC_with_sub_64_in_SPILLTOVSRRC
9084      0,	// sub_32
9085      47,	// sub_64 -> UACCRC_with_sub_64_in_SPILLTOVSRRC
9086      0,	// sub_dmr0
9087      0,	// sub_dmr1
9088      0,	// sub_dmrrow0
9089      0,	// sub_dmrrow1
9090      0,	// sub_dmrrowp0
9091      0,	// sub_dmrrowp1
9092      0,	// sub_eq
9093      0,	// sub_gp8_x0
9094      0,	// sub_gp8_x1
9095      0,	// sub_gt
9096      0,	// sub_lt
9097      47,	// sub_pair0 -> UACCRC_with_sub_64_in_SPILLTOVSRRC
9098      47,	// sub_pair1 -> UACCRC_with_sub_64_in_SPILLTOVSRRC
9099      0,	// sub_un
9100      47,	// sub_vsx0 -> UACCRC_with_sub_64_in_SPILLTOVSRRC
9101      47,	// sub_vsx1 -> UACCRC_with_sub_64_in_SPILLTOVSRRC
9102      0,	// sub_wacc_hi
9103      0,	// sub_wacc_lo
9104      47,	// sub_vsx1_then_sub_64 -> UACCRC_with_sub_64_in_SPILLTOVSRRC
9105      47,	// sub_pair1_then_sub_64 -> UACCRC_with_sub_64_in_SPILLTOVSRRC
9106      47,	// sub_pair1_then_sub_vsx0 -> UACCRC_with_sub_64_in_SPILLTOVSRRC
9107      47,	// sub_pair1_then_sub_vsx1 -> UACCRC_with_sub_64_in_SPILLTOVSRRC
9108      47,	// sub_pair1_then_sub_vsx1_then_sub_64 -> UACCRC_with_sub_64_in_SPILLTOVSRRC
9109      0,	// sub_dmrrowp1_then_sub_dmrrow0
9110      0,	// sub_dmrrowp1_then_sub_dmrrow1
9111      0,	// sub_wacc_hi_then_sub_dmrrow0
9112      0,	// sub_wacc_hi_then_sub_dmrrow1
9113      0,	// sub_wacc_hi_then_sub_dmrrowp0
9114      0,	// sub_wacc_hi_then_sub_dmrrowp1
9115      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9116      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9117      0,	// sub_dmr1_then_sub_dmrrow0
9118      0,	// sub_dmr1_then_sub_dmrrow1
9119      0,	// sub_dmr1_then_sub_dmrrowp0
9120      0,	// sub_dmr1_then_sub_dmrrowp1
9121      0,	// sub_dmr1_then_sub_wacc_hi
9122      0,	// sub_dmr1_then_sub_wacc_lo
9123      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
9124      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
9125      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
9126      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
9127      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
9128      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
9129      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9130      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9131      0,	// sub_gp8_x1_then_sub_32
9132    },
9133    {	// ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
9134      0,	// sub_32
9135      48,	// sub_64 -> ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
9136      0,	// sub_dmr0
9137      0,	// sub_dmr1
9138      0,	// sub_dmrrow0
9139      0,	// sub_dmrrow1
9140      0,	// sub_dmrrowp0
9141      0,	// sub_dmrrowp1
9142      0,	// sub_eq
9143      0,	// sub_gp8_x0
9144      0,	// sub_gp8_x1
9145      0,	// sub_gt
9146      0,	// sub_lt
9147      48,	// sub_pair0 -> ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
9148      48,	// sub_pair1 -> ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
9149      0,	// sub_un
9150      48,	// sub_vsx0 -> ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
9151      48,	// sub_vsx1 -> ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
9152      0,	// sub_wacc_hi
9153      0,	// sub_wacc_lo
9154      48,	// sub_vsx1_then_sub_64 -> ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
9155      48,	// sub_pair1_then_sub_64 -> ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
9156      48,	// sub_pair1_then_sub_vsx0 -> ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
9157      48,	// sub_pair1_then_sub_vsx1 -> ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
9158      48,	// sub_pair1_then_sub_vsx1_then_sub_64 -> ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
9159      0,	// sub_dmrrowp1_then_sub_dmrrow0
9160      0,	// sub_dmrrowp1_then_sub_dmrrow1
9161      0,	// sub_wacc_hi_then_sub_dmrrow0
9162      0,	// sub_wacc_hi_then_sub_dmrrow1
9163      0,	// sub_wacc_hi_then_sub_dmrrowp0
9164      0,	// sub_wacc_hi_then_sub_dmrrowp1
9165      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9166      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9167      0,	// sub_dmr1_then_sub_dmrrow0
9168      0,	// sub_dmr1_then_sub_dmrrow1
9169      0,	// sub_dmr1_then_sub_dmrrowp0
9170      0,	// sub_dmr1_then_sub_dmrrowp1
9171      0,	// sub_dmr1_then_sub_wacc_hi
9172      0,	// sub_dmr1_then_sub_wacc_lo
9173      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
9174      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
9175      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
9176      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
9177      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
9178      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
9179      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9180      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9181      0,	// sub_gp8_x1_then_sub_32
9182    },
9183    {	// UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
9184      0,	// sub_32
9185      49,	// sub_64 -> UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
9186      0,	// sub_dmr0
9187      0,	// sub_dmr1
9188      0,	// sub_dmrrow0
9189      0,	// sub_dmrrow1
9190      0,	// sub_dmrrowp0
9191      0,	// sub_dmrrowp1
9192      0,	// sub_eq
9193      0,	// sub_gp8_x0
9194      0,	// sub_gp8_x1
9195      0,	// sub_gt
9196      0,	// sub_lt
9197      49,	// sub_pair0 -> UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
9198      49,	// sub_pair1 -> UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
9199      0,	// sub_un
9200      49,	// sub_vsx0 -> UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
9201      49,	// sub_vsx1 -> UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
9202      0,	// sub_wacc_hi
9203      0,	// sub_wacc_lo
9204      49,	// sub_vsx1_then_sub_64 -> UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
9205      49,	// sub_pair1_then_sub_64 -> UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
9206      49,	// sub_pair1_then_sub_vsx0 -> UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
9207      49,	// sub_pair1_then_sub_vsx1 -> UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
9208      49,	// sub_pair1_then_sub_vsx1_then_sub_64 -> UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
9209      0,	// sub_dmrrowp1_then_sub_dmrrow0
9210      0,	// sub_dmrrowp1_then_sub_dmrrow1
9211      0,	// sub_wacc_hi_then_sub_dmrrow0
9212      0,	// sub_wacc_hi_then_sub_dmrrow1
9213      0,	// sub_wacc_hi_then_sub_dmrrowp0
9214      0,	// sub_wacc_hi_then_sub_dmrrowp1
9215      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9216      0,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9217      0,	// sub_dmr1_then_sub_dmrrow0
9218      0,	// sub_dmr1_then_sub_dmrrow1
9219      0,	// sub_dmr1_then_sub_dmrrowp0
9220      0,	// sub_dmr1_then_sub_dmrrowp1
9221      0,	// sub_dmr1_then_sub_wacc_hi
9222      0,	// sub_dmr1_then_sub_wacc_lo
9223      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
9224      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
9225      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
9226      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
9227      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
9228      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
9229      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9230      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9231      0,	// sub_gp8_x1_then_sub_32
9232    },
9233    {	// DMRRC
9234      0,	// sub_32
9235      0,	// sub_64
9236      0,	// sub_dmr0
9237      0,	// sub_dmr1
9238      50,	// sub_dmrrow0 -> DMRRC
9239      50,	// sub_dmrrow1 -> DMRRC
9240      50,	// sub_dmrrowp0 -> DMRRC
9241      50,	// sub_dmrrowp1 -> DMRRC
9242      0,	// sub_eq
9243      0,	// sub_gp8_x0
9244      0,	// sub_gp8_x1
9245      0,	// sub_gt
9246      0,	// sub_lt
9247      0,	// sub_pair0
9248      0,	// sub_pair1
9249      0,	// sub_un
9250      0,	// sub_vsx0
9251      0,	// sub_vsx1
9252      50,	// sub_wacc_hi -> DMRRC
9253      50,	// sub_wacc_lo -> DMRRC
9254      0,	// sub_vsx1_then_sub_64
9255      0,	// sub_pair1_then_sub_64
9256      0,	// sub_pair1_then_sub_vsx0
9257      0,	// sub_pair1_then_sub_vsx1
9258      0,	// sub_pair1_then_sub_vsx1_then_sub_64
9259      50,	// sub_dmrrowp1_then_sub_dmrrow0 -> DMRRC
9260      50,	// sub_dmrrowp1_then_sub_dmrrow1 -> DMRRC
9261      50,	// sub_wacc_hi_then_sub_dmrrow0 -> DMRRC
9262      50,	// sub_wacc_hi_then_sub_dmrrow1 -> DMRRC
9263      50,	// sub_wacc_hi_then_sub_dmrrowp0 -> DMRRC
9264      50,	// sub_wacc_hi_then_sub_dmrrowp1 -> DMRRC
9265      50,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0 -> DMRRC
9266      50,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1 -> DMRRC
9267      0,	// sub_dmr1_then_sub_dmrrow0
9268      0,	// sub_dmr1_then_sub_dmrrow1
9269      0,	// sub_dmr1_then_sub_dmrrowp0
9270      0,	// sub_dmr1_then_sub_dmrrowp1
9271      0,	// sub_dmr1_then_sub_wacc_hi
9272      0,	// sub_dmr1_then_sub_wacc_lo
9273      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
9274      0,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
9275      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
9276      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
9277      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
9278      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
9279      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9280      0,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9281      0,	// sub_gp8_x1_then_sub_32
9282    },
9283    {	// DMRpRC
9284      0,	// sub_32
9285      0,	// sub_64
9286      51,	// sub_dmr0 -> DMRpRC
9287      51,	// sub_dmr1 -> DMRpRC
9288      51,	// sub_dmrrow0 -> DMRpRC
9289      51,	// sub_dmrrow1 -> DMRpRC
9290      51,	// sub_dmrrowp0 -> DMRpRC
9291      51,	// sub_dmrrowp1 -> DMRpRC
9292      0,	// sub_eq
9293      0,	// sub_gp8_x0
9294      0,	// sub_gp8_x1
9295      0,	// sub_gt
9296      0,	// sub_lt
9297      0,	// sub_pair0
9298      0,	// sub_pair1
9299      0,	// sub_un
9300      0,	// sub_vsx0
9301      0,	// sub_vsx1
9302      51,	// sub_wacc_hi -> DMRpRC
9303      51,	// sub_wacc_lo -> DMRpRC
9304      0,	// sub_vsx1_then_sub_64
9305      0,	// sub_pair1_then_sub_64
9306      0,	// sub_pair1_then_sub_vsx0
9307      0,	// sub_pair1_then_sub_vsx1
9308      0,	// sub_pair1_then_sub_vsx1_then_sub_64
9309      51,	// sub_dmrrowp1_then_sub_dmrrow0 -> DMRpRC
9310      51,	// sub_dmrrowp1_then_sub_dmrrow1 -> DMRpRC
9311      51,	// sub_wacc_hi_then_sub_dmrrow0 -> DMRpRC
9312      51,	// sub_wacc_hi_then_sub_dmrrow1 -> DMRpRC
9313      51,	// sub_wacc_hi_then_sub_dmrrowp0 -> DMRpRC
9314      51,	// sub_wacc_hi_then_sub_dmrrowp1 -> DMRpRC
9315      51,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0 -> DMRpRC
9316      51,	// sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1 -> DMRpRC
9317      51,	// sub_dmr1_then_sub_dmrrow0 -> DMRpRC
9318      51,	// sub_dmr1_then_sub_dmrrow1 -> DMRpRC
9319      51,	// sub_dmr1_then_sub_dmrrowp0 -> DMRpRC
9320      51,	// sub_dmr1_then_sub_dmrrowp1 -> DMRpRC
9321      51,	// sub_dmr1_then_sub_wacc_hi -> DMRpRC
9322      51,	// sub_dmr1_then_sub_wacc_lo -> DMRpRC
9323      51,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0 -> DMRpRC
9324      51,	// sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1 -> DMRpRC
9325      51,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0 -> DMRpRC
9326      51,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1 -> DMRpRC
9327      51,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0 -> DMRpRC
9328      51,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1 -> DMRpRC
9329      51,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0 -> DMRpRC
9330      51,	// sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1 -> DMRpRC
9331      0,	// sub_gp8_x1_then_sub_32
9332    },
9333  };
9334  assert(RC && "Missing regclass");
9335  if (!Idx) return RC;
9336  --Idx;
9337  assert(Idx < 48 && "Bad subreg");
9338  unsigned TV = Table[RC->getID()][Idx];
9339  return TV ? getRegClass(TV - 1) : nullptr;
9340}
9341
9342const TargetRegisterClass *PPCGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
9343  static const uint8_t Table[51][48] = {
9344    {	// VSSRC
9345      0,	// VSSRC:sub_32
9346      0,	// VSSRC:sub_64
9347      0,	// VSSRC:sub_dmr0
9348      0,	// VSSRC:sub_dmr1
9349      0,	// VSSRC:sub_dmrrow0
9350      0,	// VSSRC:sub_dmrrow1
9351      0,	// VSSRC:sub_dmrrowp0
9352      0,	// VSSRC:sub_dmrrowp1
9353      0,	// VSSRC:sub_eq
9354      0,	// VSSRC:sub_gp8_x0
9355      0,	// VSSRC:sub_gp8_x1
9356      0,	// VSSRC:sub_gt
9357      0,	// VSSRC:sub_lt
9358      0,	// VSSRC:sub_pair0
9359      0,	// VSSRC:sub_pair1
9360      0,	// VSSRC:sub_un
9361      0,	// VSSRC:sub_vsx0
9362      0,	// VSSRC:sub_vsx1
9363      0,	// VSSRC:sub_wacc_hi
9364      0,	// VSSRC:sub_wacc_lo
9365      0,	// VSSRC:sub_vsx1_then_sub_64
9366      0,	// VSSRC:sub_pair1_then_sub_64
9367      0,	// VSSRC:sub_pair1_then_sub_vsx0
9368      0,	// VSSRC:sub_pair1_then_sub_vsx1
9369      0,	// VSSRC:sub_pair1_then_sub_vsx1_then_sub_64
9370      0,	// VSSRC:sub_dmrrowp1_then_sub_dmrrow0
9371      0,	// VSSRC:sub_dmrrowp1_then_sub_dmrrow1
9372      0,	// VSSRC:sub_wacc_hi_then_sub_dmrrow0
9373      0,	// VSSRC:sub_wacc_hi_then_sub_dmrrow1
9374      0,	// VSSRC:sub_wacc_hi_then_sub_dmrrowp0
9375      0,	// VSSRC:sub_wacc_hi_then_sub_dmrrowp1
9376      0,	// VSSRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9377      0,	// VSSRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9378      0,	// VSSRC:sub_dmr1_then_sub_dmrrow0
9379      0,	// VSSRC:sub_dmr1_then_sub_dmrrow1
9380      0,	// VSSRC:sub_dmr1_then_sub_dmrrowp0
9381      0,	// VSSRC:sub_dmr1_then_sub_dmrrowp1
9382      0,	// VSSRC:sub_dmr1_then_sub_wacc_hi
9383      0,	// VSSRC:sub_dmr1_then_sub_wacc_lo
9384      0,	// VSSRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
9385      0,	// VSSRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
9386      0,	// VSSRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
9387      0,	// VSSRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
9388      0,	// VSSRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
9389      0,	// VSSRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
9390      0,	// VSSRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9391      0,	// VSSRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9392      0,	// VSSRC:sub_gp8_x1_then_sub_32
9393    },
9394    {	// GPRC
9395      0,	// GPRC:sub_32
9396      0,	// GPRC:sub_64
9397      0,	// GPRC:sub_dmr0
9398      0,	// GPRC:sub_dmr1
9399      0,	// GPRC:sub_dmrrow0
9400      0,	// GPRC:sub_dmrrow1
9401      0,	// GPRC:sub_dmrrowp0
9402      0,	// GPRC:sub_dmrrowp1
9403      0,	// GPRC:sub_eq
9404      0,	// GPRC:sub_gp8_x0
9405      0,	// GPRC:sub_gp8_x1
9406      0,	// GPRC:sub_gt
9407      0,	// GPRC:sub_lt
9408      0,	// GPRC:sub_pair0
9409      0,	// GPRC:sub_pair1
9410      0,	// GPRC:sub_un
9411      0,	// GPRC:sub_vsx0
9412      0,	// GPRC:sub_vsx1
9413      0,	// GPRC:sub_wacc_hi
9414      0,	// GPRC:sub_wacc_lo
9415      0,	// GPRC:sub_vsx1_then_sub_64
9416      0,	// GPRC:sub_pair1_then_sub_64
9417      0,	// GPRC:sub_pair1_then_sub_vsx0
9418      0,	// GPRC:sub_pair1_then_sub_vsx1
9419      0,	// GPRC:sub_pair1_then_sub_vsx1_then_sub_64
9420      0,	// GPRC:sub_dmrrowp1_then_sub_dmrrow0
9421      0,	// GPRC:sub_dmrrowp1_then_sub_dmrrow1
9422      0,	// GPRC:sub_wacc_hi_then_sub_dmrrow0
9423      0,	// GPRC:sub_wacc_hi_then_sub_dmrrow1
9424      0,	// GPRC:sub_wacc_hi_then_sub_dmrrowp0
9425      0,	// GPRC:sub_wacc_hi_then_sub_dmrrowp1
9426      0,	// GPRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9427      0,	// GPRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9428      0,	// GPRC:sub_dmr1_then_sub_dmrrow0
9429      0,	// GPRC:sub_dmr1_then_sub_dmrrow1
9430      0,	// GPRC:sub_dmr1_then_sub_dmrrowp0
9431      0,	// GPRC:sub_dmr1_then_sub_dmrrowp1
9432      0,	// GPRC:sub_dmr1_then_sub_wacc_hi
9433      0,	// GPRC:sub_dmr1_then_sub_wacc_lo
9434      0,	// GPRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
9435      0,	// GPRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
9436      0,	// GPRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
9437      0,	// GPRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
9438      0,	// GPRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
9439      0,	// GPRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
9440      0,	// GPRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9441      0,	// GPRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9442      0,	// GPRC:sub_gp8_x1_then_sub_32
9443    },
9444    {	// GPRC_NOR0
9445      0,	// GPRC_NOR0:sub_32
9446      0,	// GPRC_NOR0:sub_64
9447      0,	// GPRC_NOR0:sub_dmr0
9448      0,	// GPRC_NOR0:sub_dmr1
9449      0,	// GPRC_NOR0:sub_dmrrow0
9450      0,	// GPRC_NOR0:sub_dmrrow1
9451      0,	// GPRC_NOR0:sub_dmrrowp0
9452      0,	// GPRC_NOR0:sub_dmrrowp1
9453      0,	// GPRC_NOR0:sub_eq
9454      0,	// GPRC_NOR0:sub_gp8_x0
9455      0,	// GPRC_NOR0:sub_gp8_x1
9456      0,	// GPRC_NOR0:sub_gt
9457      0,	// GPRC_NOR0:sub_lt
9458      0,	// GPRC_NOR0:sub_pair0
9459      0,	// GPRC_NOR0:sub_pair1
9460      0,	// GPRC_NOR0:sub_un
9461      0,	// GPRC_NOR0:sub_vsx0
9462      0,	// GPRC_NOR0:sub_vsx1
9463      0,	// GPRC_NOR0:sub_wacc_hi
9464      0,	// GPRC_NOR0:sub_wacc_lo
9465      0,	// GPRC_NOR0:sub_vsx1_then_sub_64
9466      0,	// GPRC_NOR0:sub_pair1_then_sub_64
9467      0,	// GPRC_NOR0:sub_pair1_then_sub_vsx0
9468      0,	// GPRC_NOR0:sub_pair1_then_sub_vsx1
9469      0,	// GPRC_NOR0:sub_pair1_then_sub_vsx1_then_sub_64
9470      0,	// GPRC_NOR0:sub_dmrrowp1_then_sub_dmrrow0
9471      0,	// GPRC_NOR0:sub_dmrrowp1_then_sub_dmrrow1
9472      0,	// GPRC_NOR0:sub_wacc_hi_then_sub_dmrrow0
9473      0,	// GPRC_NOR0:sub_wacc_hi_then_sub_dmrrow1
9474      0,	// GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp0
9475      0,	// GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp1
9476      0,	// GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9477      0,	// GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9478      0,	// GPRC_NOR0:sub_dmr1_then_sub_dmrrow0
9479      0,	// GPRC_NOR0:sub_dmr1_then_sub_dmrrow1
9480      0,	// GPRC_NOR0:sub_dmr1_then_sub_dmrrowp0
9481      0,	// GPRC_NOR0:sub_dmr1_then_sub_dmrrowp1
9482      0,	// GPRC_NOR0:sub_dmr1_then_sub_wacc_hi
9483      0,	// GPRC_NOR0:sub_dmr1_then_sub_wacc_lo
9484      0,	// GPRC_NOR0:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
9485      0,	// GPRC_NOR0:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
9486      0,	// GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
9487      0,	// GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
9488      0,	// GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
9489      0,	// GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
9490      0,	// GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9491      0,	// GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9492      0,	// GPRC_NOR0:sub_gp8_x1_then_sub_32
9493    },
9494    {	// GPRC_and_GPRC_NOR0
9495      0,	// GPRC_and_GPRC_NOR0:sub_32
9496      0,	// GPRC_and_GPRC_NOR0:sub_64
9497      0,	// GPRC_and_GPRC_NOR0:sub_dmr0
9498      0,	// GPRC_and_GPRC_NOR0:sub_dmr1
9499      0,	// GPRC_and_GPRC_NOR0:sub_dmrrow0
9500      0,	// GPRC_and_GPRC_NOR0:sub_dmrrow1
9501      0,	// GPRC_and_GPRC_NOR0:sub_dmrrowp0
9502      0,	// GPRC_and_GPRC_NOR0:sub_dmrrowp1
9503      0,	// GPRC_and_GPRC_NOR0:sub_eq
9504      0,	// GPRC_and_GPRC_NOR0:sub_gp8_x0
9505      0,	// GPRC_and_GPRC_NOR0:sub_gp8_x1
9506      0,	// GPRC_and_GPRC_NOR0:sub_gt
9507      0,	// GPRC_and_GPRC_NOR0:sub_lt
9508      0,	// GPRC_and_GPRC_NOR0:sub_pair0
9509      0,	// GPRC_and_GPRC_NOR0:sub_pair1
9510      0,	// GPRC_and_GPRC_NOR0:sub_un
9511      0,	// GPRC_and_GPRC_NOR0:sub_vsx0
9512      0,	// GPRC_and_GPRC_NOR0:sub_vsx1
9513      0,	// GPRC_and_GPRC_NOR0:sub_wacc_hi
9514      0,	// GPRC_and_GPRC_NOR0:sub_wacc_lo
9515      0,	// GPRC_and_GPRC_NOR0:sub_vsx1_then_sub_64
9516      0,	// GPRC_and_GPRC_NOR0:sub_pair1_then_sub_64
9517      0,	// GPRC_and_GPRC_NOR0:sub_pair1_then_sub_vsx0
9518      0,	// GPRC_and_GPRC_NOR0:sub_pair1_then_sub_vsx1
9519      0,	// GPRC_and_GPRC_NOR0:sub_pair1_then_sub_vsx1_then_sub_64
9520      0,	// GPRC_and_GPRC_NOR0:sub_dmrrowp1_then_sub_dmrrow0
9521      0,	// GPRC_and_GPRC_NOR0:sub_dmrrowp1_then_sub_dmrrow1
9522      0,	// GPRC_and_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrow0
9523      0,	// GPRC_and_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrow1
9524      0,	// GPRC_and_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp0
9525      0,	// GPRC_and_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp1
9526      0,	// GPRC_and_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9527      0,	// GPRC_and_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9528      0,	// GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_dmrrow0
9529      0,	// GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_dmrrow1
9530      0,	// GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_dmrrowp0
9531      0,	// GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_dmrrowp1
9532      0,	// GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi
9533      0,	// GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_wacc_lo
9534      0,	// GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
9535      0,	// GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
9536      0,	// GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
9537      0,	// GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
9538      0,	// GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
9539      0,	// GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
9540      0,	// GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9541      0,	// GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9542      0,	// GPRC_and_GPRC_NOR0:sub_gp8_x1_then_sub_32
9543    },
9544    {	// CRBITRC
9545      0,	// CRBITRC:sub_32
9546      0,	// CRBITRC:sub_64
9547      0,	// CRBITRC:sub_dmr0
9548      0,	// CRBITRC:sub_dmr1
9549      0,	// CRBITRC:sub_dmrrow0
9550      0,	// CRBITRC:sub_dmrrow1
9551      0,	// CRBITRC:sub_dmrrowp0
9552      0,	// CRBITRC:sub_dmrrowp1
9553      0,	// CRBITRC:sub_eq
9554      0,	// CRBITRC:sub_gp8_x0
9555      0,	// CRBITRC:sub_gp8_x1
9556      0,	// CRBITRC:sub_gt
9557      0,	// CRBITRC:sub_lt
9558      0,	// CRBITRC:sub_pair0
9559      0,	// CRBITRC:sub_pair1
9560      0,	// CRBITRC:sub_un
9561      0,	// CRBITRC:sub_vsx0
9562      0,	// CRBITRC:sub_vsx1
9563      0,	// CRBITRC:sub_wacc_hi
9564      0,	// CRBITRC:sub_wacc_lo
9565      0,	// CRBITRC:sub_vsx1_then_sub_64
9566      0,	// CRBITRC:sub_pair1_then_sub_64
9567      0,	// CRBITRC:sub_pair1_then_sub_vsx0
9568      0,	// CRBITRC:sub_pair1_then_sub_vsx1
9569      0,	// CRBITRC:sub_pair1_then_sub_vsx1_then_sub_64
9570      0,	// CRBITRC:sub_dmrrowp1_then_sub_dmrrow0
9571      0,	// CRBITRC:sub_dmrrowp1_then_sub_dmrrow1
9572      0,	// CRBITRC:sub_wacc_hi_then_sub_dmrrow0
9573      0,	// CRBITRC:sub_wacc_hi_then_sub_dmrrow1
9574      0,	// CRBITRC:sub_wacc_hi_then_sub_dmrrowp0
9575      0,	// CRBITRC:sub_wacc_hi_then_sub_dmrrowp1
9576      0,	// CRBITRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9577      0,	// CRBITRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9578      0,	// CRBITRC:sub_dmr1_then_sub_dmrrow0
9579      0,	// CRBITRC:sub_dmr1_then_sub_dmrrow1
9580      0,	// CRBITRC:sub_dmr1_then_sub_dmrrowp0
9581      0,	// CRBITRC:sub_dmr1_then_sub_dmrrowp1
9582      0,	// CRBITRC:sub_dmr1_then_sub_wacc_hi
9583      0,	// CRBITRC:sub_dmr1_then_sub_wacc_lo
9584      0,	// CRBITRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
9585      0,	// CRBITRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
9586      0,	// CRBITRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
9587      0,	// CRBITRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
9588      0,	// CRBITRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
9589      0,	// CRBITRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
9590      0,	// CRBITRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9591      0,	// CRBITRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9592      0,	// CRBITRC:sub_gp8_x1_then_sub_32
9593    },
9594    {	// F4RC
9595      0,	// F4RC:sub_32
9596      0,	// F4RC:sub_64
9597      0,	// F4RC:sub_dmr0
9598      0,	// F4RC:sub_dmr1
9599      0,	// F4RC:sub_dmrrow0
9600      0,	// F4RC:sub_dmrrow1
9601      0,	// F4RC:sub_dmrrowp0
9602      0,	// F4RC:sub_dmrrowp1
9603      0,	// F4RC:sub_eq
9604      0,	// F4RC:sub_gp8_x0
9605      0,	// F4RC:sub_gp8_x1
9606      0,	// F4RC:sub_gt
9607      0,	// F4RC:sub_lt
9608      0,	// F4RC:sub_pair0
9609      0,	// F4RC:sub_pair1
9610      0,	// F4RC:sub_un
9611      0,	// F4RC:sub_vsx0
9612      0,	// F4RC:sub_vsx1
9613      0,	// F4RC:sub_wacc_hi
9614      0,	// F4RC:sub_wacc_lo
9615      0,	// F4RC:sub_vsx1_then_sub_64
9616      0,	// F4RC:sub_pair1_then_sub_64
9617      0,	// F4RC:sub_pair1_then_sub_vsx0
9618      0,	// F4RC:sub_pair1_then_sub_vsx1
9619      0,	// F4RC:sub_pair1_then_sub_vsx1_then_sub_64
9620      0,	// F4RC:sub_dmrrowp1_then_sub_dmrrow0
9621      0,	// F4RC:sub_dmrrowp1_then_sub_dmrrow1
9622      0,	// F4RC:sub_wacc_hi_then_sub_dmrrow0
9623      0,	// F4RC:sub_wacc_hi_then_sub_dmrrow1
9624      0,	// F4RC:sub_wacc_hi_then_sub_dmrrowp0
9625      0,	// F4RC:sub_wacc_hi_then_sub_dmrrowp1
9626      0,	// F4RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9627      0,	// F4RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9628      0,	// F4RC:sub_dmr1_then_sub_dmrrow0
9629      0,	// F4RC:sub_dmr1_then_sub_dmrrow1
9630      0,	// F4RC:sub_dmr1_then_sub_dmrrowp0
9631      0,	// F4RC:sub_dmr1_then_sub_dmrrowp1
9632      0,	// F4RC:sub_dmr1_then_sub_wacc_hi
9633      0,	// F4RC:sub_dmr1_then_sub_wacc_lo
9634      0,	// F4RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
9635      0,	// F4RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
9636      0,	// F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
9637      0,	// F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
9638      0,	// F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
9639      0,	// F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
9640      0,	// F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9641      0,	// F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9642      0,	// F4RC:sub_gp8_x1_then_sub_32
9643    },
9644    {	// CRRC
9645      0,	// CRRC:sub_32
9646      0,	// CRRC:sub_64
9647      0,	// CRRC:sub_dmr0
9648      0,	// CRRC:sub_dmr1
9649      0,	// CRRC:sub_dmrrow0
9650      0,	// CRRC:sub_dmrrow1
9651      0,	// CRRC:sub_dmrrowp0
9652      0,	// CRRC:sub_dmrrowp1
9653      5,	// CRRC:sub_eq -> CRBITRC
9654      0,	// CRRC:sub_gp8_x0
9655      0,	// CRRC:sub_gp8_x1
9656      5,	// CRRC:sub_gt -> CRBITRC
9657      5,	// CRRC:sub_lt -> CRBITRC
9658      0,	// CRRC:sub_pair0
9659      0,	// CRRC:sub_pair1
9660      5,	// CRRC:sub_un -> CRBITRC
9661      0,	// CRRC:sub_vsx0
9662      0,	// CRRC:sub_vsx1
9663      0,	// CRRC:sub_wacc_hi
9664      0,	// CRRC:sub_wacc_lo
9665      0,	// CRRC:sub_vsx1_then_sub_64
9666      0,	// CRRC:sub_pair1_then_sub_64
9667      0,	// CRRC:sub_pair1_then_sub_vsx0
9668      0,	// CRRC:sub_pair1_then_sub_vsx1
9669      0,	// CRRC:sub_pair1_then_sub_vsx1_then_sub_64
9670      0,	// CRRC:sub_dmrrowp1_then_sub_dmrrow0
9671      0,	// CRRC:sub_dmrrowp1_then_sub_dmrrow1
9672      0,	// CRRC:sub_wacc_hi_then_sub_dmrrow0
9673      0,	// CRRC:sub_wacc_hi_then_sub_dmrrow1
9674      0,	// CRRC:sub_wacc_hi_then_sub_dmrrowp0
9675      0,	// CRRC:sub_wacc_hi_then_sub_dmrrowp1
9676      0,	// CRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9677      0,	// CRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9678      0,	// CRRC:sub_dmr1_then_sub_dmrrow0
9679      0,	// CRRC:sub_dmr1_then_sub_dmrrow1
9680      0,	// CRRC:sub_dmr1_then_sub_dmrrowp0
9681      0,	// CRRC:sub_dmr1_then_sub_dmrrowp1
9682      0,	// CRRC:sub_dmr1_then_sub_wacc_hi
9683      0,	// CRRC:sub_dmr1_then_sub_wacc_lo
9684      0,	// CRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
9685      0,	// CRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
9686      0,	// CRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
9687      0,	// CRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
9688      0,	// CRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
9689      0,	// CRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
9690      0,	// CRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9691      0,	// CRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9692      0,	// CRRC:sub_gp8_x1_then_sub_32
9693    },
9694    {	// CARRYRC
9695      0,	// CARRYRC:sub_32
9696      0,	// CARRYRC:sub_64
9697      0,	// CARRYRC:sub_dmr0
9698      0,	// CARRYRC:sub_dmr1
9699      0,	// CARRYRC:sub_dmrrow0
9700      0,	// CARRYRC:sub_dmrrow1
9701      0,	// CARRYRC:sub_dmrrowp0
9702      0,	// CARRYRC:sub_dmrrowp1
9703      0,	// CARRYRC:sub_eq
9704      0,	// CARRYRC:sub_gp8_x0
9705      0,	// CARRYRC:sub_gp8_x1
9706      0,	// CARRYRC:sub_gt
9707      0,	// CARRYRC:sub_lt
9708      0,	// CARRYRC:sub_pair0
9709      0,	// CARRYRC:sub_pair1
9710      0,	// CARRYRC:sub_un
9711      0,	// CARRYRC:sub_vsx0
9712      0,	// CARRYRC:sub_vsx1
9713      0,	// CARRYRC:sub_wacc_hi
9714      0,	// CARRYRC:sub_wacc_lo
9715      0,	// CARRYRC:sub_vsx1_then_sub_64
9716      0,	// CARRYRC:sub_pair1_then_sub_64
9717      0,	// CARRYRC:sub_pair1_then_sub_vsx0
9718      0,	// CARRYRC:sub_pair1_then_sub_vsx1
9719      0,	// CARRYRC:sub_pair1_then_sub_vsx1_then_sub_64
9720      0,	// CARRYRC:sub_dmrrowp1_then_sub_dmrrow0
9721      0,	// CARRYRC:sub_dmrrowp1_then_sub_dmrrow1
9722      0,	// CARRYRC:sub_wacc_hi_then_sub_dmrrow0
9723      0,	// CARRYRC:sub_wacc_hi_then_sub_dmrrow1
9724      0,	// CARRYRC:sub_wacc_hi_then_sub_dmrrowp0
9725      0,	// CARRYRC:sub_wacc_hi_then_sub_dmrrowp1
9726      0,	// CARRYRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9727      0,	// CARRYRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9728      0,	// CARRYRC:sub_dmr1_then_sub_dmrrow0
9729      0,	// CARRYRC:sub_dmr1_then_sub_dmrrow1
9730      0,	// CARRYRC:sub_dmr1_then_sub_dmrrowp0
9731      0,	// CARRYRC:sub_dmr1_then_sub_dmrrowp1
9732      0,	// CARRYRC:sub_dmr1_then_sub_wacc_hi
9733      0,	// CARRYRC:sub_dmr1_then_sub_wacc_lo
9734      0,	// CARRYRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
9735      0,	// CARRYRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
9736      0,	// CARRYRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
9737      0,	// CARRYRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
9738      0,	// CARRYRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
9739      0,	// CARRYRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
9740      0,	// CARRYRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9741      0,	// CARRYRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9742      0,	// CARRYRC:sub_gp8_x1_then_sub_32
9743    },
9744    {	// CTRRC
9745      0,	// CTRRC:sub_32
9746      0,	// CTRRC:sub_64
9747      0,	// CTRRC:sub_dmr0
9748      0,	// CTRRC:sub_dmr1
9749      0,	// CTRRC:sub_dmrrow0
9750      0,	// CTRRC:sub_dmrrow1
9751      0,	// CTRRC:sub_dmrrowp0
9752      0,	// CTRRC:sub_dmrrowp1
9753      0,	// CTRRC:sub_eq
9754      0,	// CTRRC:sub_gp8_x0
9755      0,	// CTRRC:sub_gp8_x1
9756      0,	// CTRRC:sub_gt
9757      0,	// CTRRC:sub_lt
9758      0,	// CTRRC:sub_pair0
9759      0,	// CTRRC:sub_pair1
9760      0,	// CTRRC:sub_un
9761      0,	// CTRRC:sub_vsx0
9762      0,	// CTRRC:sub_vsx1
9763      0,	// CTRRC:sub_wacc_hi
9764      0,	// CTRRC:sub_wacc_lo
9765      0,	// CTRRC:sub_vsx1_then_sub_64
9766      0,	// CTRRC:sub_pair1_then_sub_64
9767      0,	// CTRRC:sub_pair1_then_sub_vsx0
9768      0,	// CTRRC:sub_pair1_then_sub_vsx1
9769      0,	// CTRRC:sub_pair1_then_sub_vsx1_then_sub_64
9770      0,	// CTRRC:sub_dmrrowp1_then_sub_dmrrow0
9771      0,	// CTRRC:sub_dmrrowp1_then_sub_dmrrow1
9772      0,	// CTRRC:sub_wacc_hi_then_sub_dmrrow0
9773      0,	// CTRRC:sub_wacc_hi_then_sub_dmrrow1
9774      0,	// CTRRC:sub_wacc_hi_then_sub_dmrrowp0
9775      0,	// CTRRC:sub_wacc_hi_then_sub_dmrrowp1
9776      0,	// CTRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9777      0,	// CTRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9778      0,	// CTRRC:sub_dmr1_then_sub_dmrrow0
9779      0,	// CTRRC:sub_dmr1_then_sub_dmrrow1
9780      0,	// CTRRC:sub_dmr1_then_sub_dmrrowp0
9781      0,	// CTRRC:sub_dmr1_then_sub_dmrrowp1
9782      0,	// CTRRC:sub_dmr1_then_sub_wacc_hi
9783      0,	// CTRRC:sub_dmr1_then_sub_wacc_lo
9784      0,	// CTRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
9785      0,	// CTRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
9786      0,	// CTRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
9787      0,	// CTRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
9788      0,	// CTRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
9789      0,	// CTRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
9790      0,	// CTRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9791      0,	// CTRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9792      0,	// CTRRC:sub_gp8_x1_then_sub_32
9793    },
9794    {	// LRRC
9795      0,	// LRRC:sub_32
9796      0,	// LRRC:sub_64
9797      0,	// LRRC:sub_dmr0
9798      0,	// LRRC:sub_dmr1
9799      0,	// LRRC:sub_dmrrow0
9800      0,	// LRRC:sub_dmrrow1
9801      0,	// LRRC:sub_dmrrowp0
9802      0,	// LRRC:sub_dmrrowp1
9803      0,	// LRRC:sub_eq
9804      0,	// LRRC:sub_gp8_x0
9805      0,	// LRRC:sub_gp8_x1
9806      0,	// LRRC:sub_gt
9807      0,	// LRRC:sub_lt
9808      0,	// LRRC:sub_pair0
9809      0,	// LRRC:sub_pair1
9810      0,	// LRRC:sub_un
9811      0,	// LRRC:sub_vsx0
9812      0,	// LRRC:sub_vsx1
9813      0,	// LRRC:sub_wacc_hi
9814      0,	// LRRC:sub_wacc_lo
9815      0,	// LRRC:sub_vsx1_then_sub_64
9816      0,	// LRRC:sub_pair1_then_sub_64
9817      0,	// LRRC:sub_pair1_then_sub_vsx0
9818      0,	// LRRC:sub_pair1_then_sub_vsx1
9819      0,	// LRRC:sub_pair1_then_sub_vsx1_then_sub_64
9820      0,	// LRRC:sub_dmrrowp1_then_sub_dmrrow0
9821      0,	// LRRC:sub_dmrrowp1_then_sub_dmrrow1
9822      0,	// LRRC:sub_wacc_hi_then_sub_dmrrow0
9823      0,	// LRRC:sub_wacc_hi_then_sub_dmrrow1
9824      0,	// LRRC:sub_wacc_hi_then_sub_dmrrowp0
9825      0,	// LRRC:sub_wacc_hi_then_sub_dmrrowp1
9826      0,	// LRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9827      0,	// LRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9828      0,	// LRRC:sub_dmr1_then_sub_dmrrow0
9829      0,	// LRRC:sub_dmr1_then_sub_dmrrow1
9830      0,	// LRRC:sub_dmr1_then_sub_dmrrowp0
9831      0,	// LRRC:sub_dmr1_then_sub_dmrrowp1
9832      0,	// LRRC:sub_dmr1_then_sub_wacc_hi
9833      0,	// LRRC:sub_dmr1_then_sub_wacc_lo
9834      0,	// LRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
9835      0,	// LRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
9836      0,	// LRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
9837      0,	// LRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
9838      0,	// LRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
9839      0,	// LRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
9840      0,	// LRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9841      0,	// LRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9842      0,	// LRRC:sub_gp8_x1_then_sub_32
9843    },
9844    {	// VRSAVERC
9845      0,	// VRSAVERC:sub_32
9846      0,	// VRSAVERC:sub_64
9847      0,	// VRSAVERC:sub_dmr0
9848      0,	// VRSAVERC:sub_dmr1
9849      0,	// VRSAVERC:sub_dmrrow0
9850      0,	// VRSAVERC:sub_dmrrow1
9851      0,	// VRSAVERC:sub_dmrrowp0
9852      0,	// VRSAVERC:sub_dmrrowp1
9853      0,	// VRSAVERC:sub_eq
9854      0,	// VRSAVERC:sub_gp8_x0
9855      0,	// VRSAVERC:sub_gp8_x1
9856      0,	// VRSAVERC:sub_gt
9857      0,	// VRSAVERC:sub_lt
9858      0,	// VRSAVERC:sub_pair0
9859      0,	// VRSAVERC:sub_pair1
9860      0,	// VRSAVERC:sub_un
9861      0,	// VRSAVERC:sub_vsx0
9862      0,	// VRSAVERC:sub_vsx1
9863      0,	// VRSAVERC:sub_wacc_hi
9864      0,	// VRSAVERC:sub_wacc_lo
9865      0,	// VRSAVERC:sub_vsx1_then_sub_64
9866      0,	// VRSAVERC:sub_pair1_then_sub_64
9867      0,	// VRSAVERC:sub_pair1_then_sub_vsx0
9868      0,	// VRSAVERC:sub_pair1_then_sub_vsx1
9869      0,	// VRSAVERC:sub_pair1_then_sub_vsx1_then_sub_64
9870      0,	// VRSAVERC:sub_dmrrowp1_then_sub_dmrrow0
9871      0,	// VRSAVERC:sub_dmrrowp1_then_sub_dmrrow1
9872      0,	// VRSAVERC:sub_wacc_hi_then_sub_dmrrow0
9873      0,	// VRSAVERC:sub_wacc_hi_then_sub_dmrrow1
9874      0,	// VRSAVERC:sub_wacc_hi_then_sub_dmrrowp0
9875      0,	// VRSAVERC:sub_wacc_hi_then_sub_dmrrowp1
9876      0,	// VRSAVERC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9877      0,	// VRSAVERC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9878      0,	// VRSAVERC:sub_dmr1_then_sub_dmrrow0
9879      0,	// VRSAVERC:sub_dmr1_then_sub_dmrrow1
9880      0,	// VRSAVERC:sub_dmr1_then_sub_dmrrowp0
9881      0,	// VRSAVERC:sub_dmr1_then_sub_dmrrowp1
9882      0,	// VRSAVERC:sub_dmr1_then_sub_wacc_hi
9883      0,	// VRSAVERC:sub_dmr1_then_sub_wacc_lo
9884      0,	// VRSAVERC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
9885      0,	// VRSAVERC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
9886      0,	// VRSAVERC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
9887      0,	// VRSAVERC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
9888      0,	// VRSAVERC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
9889      0,	// VRSAVERC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
9890      0,	// VRSAVERC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9891      0,	// VRSAVERC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9892      0,	// VRSAVERC:sub_gp8_x1_then_sub_32
9893    },
9894    {	// SPILLTOVSRRC
9895      2,	// SPILLTOVSRRC:sub_32 -> GPRC
9896      0,	// SPILLTOVSRRC:sub_64
9897      0,	// SPILLTOVSRRC:sub_dmr0
9898      0,	// SPILLTOVSRRC:sub_dmr1
9899      0,	// SPILLTOVSRRC:sub_dmrrow0
9900      0,	// SPILLTOVSRRC:sub_dmrrow1
9901      0,	// SPILLTOVSRRC:sub_dmrrowp0
9902      0,	// SPILLTOVSRRC:sub_dmrrowp1
9903      0,	// SPILLTOVSRRC:sub_eq
9904      0,	// SPILLTOVSRRC:sub_gp8_x0
9905      0,	// SPILLTOVSRRC:sub_gp8_x1
9906      0,	// SPILLTOVSRRC:sub_gt
9907      0,	// SPILLTOVSRRC:sub_lt
9908      0,	// SPILLTOVSRRC:sub_pair0
9909      0,	// SPILLTOVSRRC:sub_pair1
9910      0,	// SPILLTOVSRRC:sub_un
9911      0,	// SPILLTOVSRRC:sub_vsx0
9912      0,	// SPILLTOVSRRC:sub_vsx1
9913      0,	// SPILLTOVSRRC:sub_wacc_hi
9914      0,	// SPILLTOVSRRC:sub_wacc_lo
9915      0,	// SPILLTOVSRRC:sub_vsx1_then_sub_64
9916      0,	// SPILLTOVSRRC:sub_pair1_then_sub_64
9917      0,	// SPILLTOVSRRC:sub_pair1_then_sub_vsx0
9918      0,	// SPILLTOVSRRC:sub_pair1_then_sub_vsx1
9919      0,	// SPILLTOVSRRC:sub_pair1_then_sub_vsx1_then_sub_64
9920      0,	// SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow0
9921      0,	// SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow1
9922      0,	// SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow0
9923      0,	// SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow1
9924      0,	// SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp0
9925      0,	// SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1
9926      0,	// SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9927      0,	// SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9928      0,	// SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow0
9929      0,	// SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow1
9930      0,	// SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp0
9931      0,	// SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1
9932      0,	// SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi
9933      0,	// SPILLTOVSRRC:sub_dmr1_then_sub_wacc_lo
9934      0,	// SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
9935      0,	// SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
9936      0,	// SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
9937      0,	// SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
9938      0,	// SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
9939      0,	// SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
9940      0,	// SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9941      0,	// SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9942      0,	// SPILLTOVSRRC:sub_gp8_x1_then_sub_32
9943    },
9944    {	// VSFRC
9945      0,	// VSFRC:sub_32
9946      0,	// VSFRC:sub_64
9947      0,	// VSFRC:sub_dmr0
9948      0,	// VSFRC:sub_dmr1
9949      0,	// VSFRC:sub_dmrrow0
9950      0,	// VSFRC:sub_dmrrow1
9951      0,	// VSFRC:sub_dmrrowp0
9952      0,	// VSFRC:sub_dmrrowp1
9953      0,	// VSFRC:sub_eq
9954      0,	// VSFRC:sub_gp8_x0
9955      0,	// VSFRC:sub_gp8_x1
9956      0,	// VSFRC:sub_gt
9957      0,	// VSFRC:sub_lt
9958      0,	// VSFRC:sub_pair0
9959      0,	// VSFRC:sub_pair1
9960      0,	// VSFRC:sub_un
9961      0,	// VSFRC:sub_vsx0
9962      0,	// VSFRC:sub_vsx1
9963      0,	// VSFRC:sub_wacc_hi
9964      0,	// VSFRC:sub_wacc_lo
9965      0,	// VSFRC:sub_vsx1_then_sub_64
9966      0,	// VSFRC:sub_pair1_then_sub_64
9967      0,	// VSFRC:sub_pair1_then_sub_vsx0
9968      0,	// VSFRC:sub_pair1_then_sub_vsx1
9969      0,	// VSFRC:sub_pair1_then_sub_vsx1_then_sub_64
9970      0,	// VSFRC:sub_dmrrowp1_then_sub_dmrrow0
9971      0,	// VSFRC:sub_dmrrowp1_then_sub_dmrrow1
9972      0,	// VSFRC:sub_wacc_hi_then_sub_dmrrow0
9973      0,	// VSFRC:sub_wacc_hi_then_sub_dmrrow1
9974      0,	// VSFRC:sub_wacc_hi_then_sub_dmrrowp0
9975      0,	// VSFRC:sub_wacc_hi_then_sub_dmrrowp1
9976      0,	// VSFRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9977      0,	// VSFRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9978      0,	// VSFRC:sub_dmr1_then_sub_dmrrow0
9979      0,	// VSFRC:sub_dmr1_then_sub_dmrrow1
9980      0,	// VSFRC:sub_dmr1_then_sub_dmrrowp0
9981      0,	// VSFRC:sub_dmr1_then_sub_dmrrowp1
9982      0,	// VSFRC:sub_dmr1_then_sub_wacc_hi
9983      0,	// VSFRC:sub_dmr1_then_sub_wacc_lo
9984      0,	// VSFRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
9985      0,	// VSFRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
9986      0,	// VSFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
9987      0,	// VSFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
9988      0,	// VSFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
9989      0,	// VSFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
9990      0,	// VSFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9991      0,	// VSFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9992      0,	// VSFRC:sub_gp8_x1_then_sub_32
9993    },
9994    {	// G8RC
9995      2,	// G8RC:sub_32 -> GPRC
9996      0,	// G8RC:sub_64
9997      0,	// G8RC:sub_dmr0
9998      0,	// G8RC:sub_dmr1
9999      0,	// G8RC:sub_dmrrow0
10000      0,	// G8RC:sub_dmrrow1
10001      0,	// G8RC:sub_dmrrowp0
10002      0,	// G8RC:sub_dmrrowp1
10003      0,	// G8RC:sub_eq
10004      0,	// G8RC:sub_gp8_x0
10005      0,	// G8RC:sub_gp8_x1
10006      0,	// G8RC:sub_gt
10007      0,	// G8RC:sub_lt
10008      0,	// G8RC:sub_pair0
10009      0,	// G8RC:sub_pair1
10010      0,	// G8RC:sub_un
10011      0,	// G8RC:sub_vsx0
10012      0,	// G8RC:sub_vsx1
10013      0,	// G8RC:sub_wacc_hi
10014      0,	// G8RC:sub_wacc_lo
10015      0,	// G8RC:sub_vsx1_then_sub_64
10016      0,	// G8RC:sub_pair1_then_sub_64
10017      0,	// G8RC:sub_pair1_then_sub_vsx0
10018      0,	// G8RC:sub_pair1_then_sub_vsx1
10019      0,	// G8RC:sub_pair1_then_sub_vsx1_then_sub_64
10020      0,	// G8RC:sub_dmrrowp1_then_sub_dmrrow0
10021      0,	// G8RC:sub_dmrrowp1_then_sub_dmrrow1
10022      0,	// G8RC:sub_wacc_hi_then_sub_dmrrow0
10023      0,	// G8RC:sub_wacc_hi_then_sub_dmrrow1
10024      0,	// G8RC:sub_wacc_hi_then_sub_dmrrowp0
10025      0,	// G8RC:sub_wacc_hi_then_sub_dmrrowp1
10026      0,	// G8RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10027      0,	// G8RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10028      0,	// G8RC:sub_dmr1_then_sub_dmrrow0
10029      0,	// G8RC:sub_dmr1_then_sub_dmrrow1
10030      0,	// G8RC:sub_dmr1_then_sub_dmrrowp0
10031      0,	// G8RC:sub_dmr1_then_sub_dmrrowp1
10032      0,	// G8RC:sub_dmr1_then_sub_wacc_hi
10033      0,	// G8RC:sub_dmr1_then_sub_wacc_lo
10034      0,	// G8RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
10035      0,	// G8RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
10036      0,	// G8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
10037      0,	// G8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
10038      0,	// G8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
10039      0,	// G8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
10040      0,	// G8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10041      0,	// G8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10042      0,	// G8RC:sub_gp8_x1_then_sub_32
10043    },
10044    {	// G8RC_NOX0
10045      3,	// G8RC_NOX0:sub_32 -> GPRC_NOR0
10046      0,	// G8RC_NOX0:sub_64
10047      0,	// G8RC_NOX0:sub_dmr0
10048      0,	// G8RC_NOX0:sub_dmr1
10049      0,	// G8RC_NOX0:sub_dmrrow0
10050      0,	// G8RC_NOX0:sub_dmrrow1
10051      0,	// G8RC_NOX0:sub_dmrrowp0
10052      0,	// G8RC_NOX0:sub_dmrrowp1
10053      0,	// G8RC_NOX0:sub_eq
10054      0,	// G8RC_NOX0:sub_gp8_x0
10055      0,	// G8RC_NOX0:sub_gp8_x1
10056      0,	// G8RC_NOX0:sub_gt
10057      0,	// G8RC_NOX0:sub_lt
10058      0,	// G8RC_NOX0:sub_pair0
10059      0,	// G8RC_NOX0:sub_pair1
10060      0,	// G8RC_NOX0:sub_un
10061      0,	// G8RC_NOX0:sub_vsx0
10062      0,	// G8RC_NOX0:sub_vsx1
10063      0,	// G8RC_NOX0:sub_wacc_hi
10064      0,	// G8RC_NOX0:sub_wacc_lo
10065      0,	// G8RC_NOX0:sub_vsx1_then_sub_64
10066      0,	// G8RC_NOX0:sub_pair1_then_sub_64
10067      0,	// G8RC_NOX0:sub_pair1_then_sub_vsx0
10068      0,	// G8RC_NOX0:sub_pair1_then_sub_vsx1
10069      0,	// G8RC_NOX0:sub_pair1_then_sub_vsx1_then_sub_64
10070      0,	// G8RC_NOX0:sub_dmrrowp1_then_sub_dmrrow0
10071      0,	// G8RC_NOX0:sub_dmrrowp1_then_sub_dmrrow1
10072      0,	// G8RC_NOX0:sub_wacc_hi_then_sub_dmrrow0
10073      0,	// G8RC_NOX0:sub_wacc_hi_then_sub_dmrrow1
10074      0,	// G8RC_NOX0:sub_wacc_hi_then_sub_dmrrowp0
10075      0,	// G8RC_NOX0:sub_wacc_hi_then_sub_dmrrowp1
10076      0,	// G8RC_NOX0:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10077      0,	// G8RC_NOX0:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10078      0,	// G8RC_NOX0:sub_dmr1_then_sub_dmrrow0
10079      0,	// G8RC_NOX0:sub_dmr1_then_sub_dmrrow1
10080      0,	// G8RC_NOX0:sub_dmr1_then_sub_dmrrowp0
10081      0,	// G8RC_NOX0:sub_dmr1_then_sub_dmrrowp1
10082      0,	// G8RC_NOX0:sub_dmr1_then_sub_wacc_hi
10083      0,	// G8RC_NOX0:sub_dmr1_then_sub_wacc_lo
10084      0,	// G8RC_NOX0:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
10085      0,	// G8RC_NOX0:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
10086      0,	// G8RC_NOX0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
10087      0,	// G8RC_NOX0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
10088      0,	// G8RC_NOX0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
10089      0,	// G8RC_NOX0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
10090      0,	// G8RC_NOX0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10091      0,	// G8RC_NOX0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10092      0,	// G8RC_NOX0:sub_gp8_x1_then_sub_32
10093    },
10094    {	// SPILLTOVSRRC_and_VSFRC
10095      0,	// SPILLTOVSRRC_and_VSFRC:sub_32
10096      0,	// SPILLTOVSRRC_and_VSFRC:sub_64
10097      0,	// SPILLTOVSRRC_and_VSFRC:sub_dmr0
10098      0,	// SPILLTOVSRRC_and_VSFRC:sub_dmr1
10099      0,	// SPILLTOVSRRC_and_VSFRC:sub_dmrrow0
10100      0,	// SPILLTOVSRRC_and_VSFRC:sub_dmrrow1
10101      0,	// SPILLTOVSRRC_and_VSFRC:sub_dmrrowp0
10102      0,	// SPILLTOVSRRC_and_VSFRC:sub_dmrrowp1
10103      0,	// SPILLTOVSRRC_and_VSFRC:sub_eq
10104      0,	// SPILLTOVSRRC_and_VSFRC:sub_gp8_x0
10105      0,	// SPILLTOVSRRC_and_VSFRC:sub_gp8_x1
10106      0,	// SPILLTOVSRRC_and_VSFRC:sub_gt
10107      0,	// SPILLTOVSRRC_and_VSFRC:sub_lt
10108      0,	// SPILLTOVSRRC_and_VSFRC:sub_pair0
10109      0,	// SPILLTOVSRRC_and_VSFRC:sub_pair1
10110      0,	// SPILLTOVSRRC_and_VSFRC:sub_un
10111      0,	// SPILLTOVSRRC_and_VSFRC:sub_vsx0
10112      0,	// SPILLTOVSRRC_and_VSFRC:sub_vsx1
10113      0,	// SPILLTOVSRRC_and_VSFRC:sub_wacc_hi
10114      0,	// SPILLTOVSRRC_and_VSFRC:sub_wacc_lo
10115      0,	// SPILLTOVSRRC_and_VSFRC:sub_vsx1_then_sub_64
10116      0,	// SPILLTOVSRRC_and_VSFRC:sub_pair1_then_sub_64
10117      0,	// SPILLTOVSRRC_and_VSFRC:sub_pair1_then_sub_vsx0
10118      0,	// SPILLTOVSRRC_and_VSFRC:sub_pair1_then_sub_vsx1
10119      0,	// SPILLTOVSRRC_and_VSFRC:sub_pair1_then_sub_vsx1_then_sub_64
10120      0,	// SPILLTOVSRRC_and_VSFRC:sub_dmrrowp1_then_sub_dmrrow0
10121      0,	// SPILLTOVSRRC_and_VSFRC:sub_dmrrowp1_then_sub_dmrrow1
10122      0,	// SPILLTOVSRRC_and_VSFRC:sub_wacc_hi_then_sub_dmrrow0
10123      0,	// SPILLTOVSRRC_and_VSFRC:sub_wacc_hi_then_sub_dmrrow1
10124      0,	// SPILLTOVSRRC_and_VSFRC:sub_wacc_hi_then_sub_dmrrowp0
10125      0,	// SPILLTOVSRRC_and_VSFRC:sub_wacc_hi_then_sub_dmrrowp1
10126      0,	// SPILLTOVSRRC_and_VSFRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10127      0,	// SPILLTOVSRRC_and_VSFRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10128      0,	// SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_dmrrow0
10129      0,	// SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_dmrrow1
10130      0,	// SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_dmrrowp0
10131      0,	// SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_dmrrowp1
10132      0,	// SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_wacc_hi
10133      0,	// SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_wacc_lo
10134      0,	// SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
10135      0,	// SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
10136      0,	// SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
10137      0,	// SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
10138      0,	// SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
10139      0,	// SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
10140      0,	// SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10141      0,	// SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10142      0,	// SPILLTOVSRRC_and_VSFRC:sub_gp8_x1_then_sub_32
10143    },
10144    {	// G8RC_and_G8RC_NOX0
10145      4,	// G8RC_and_G8RC_NOX0:sub_32 -> GPRC_and_GPRC_NOR0
10146      0,	// G8RC_and_G8RC_NOX0:sub_64
10147      0,	// G8RC_and_G8RC_NOX0:sub_dmr0
10148      0,	// G8RC_and_G8RC_NOX0:sub_dmr1
10149      0,	// G8RC_and_G8RC_NOX0:sub_dmrrow0
10150      0,	// G8RC_and_G8RC_NOX0:sub_dmrrow1
10151      0,	// G8RC_and_G8RC_NOX0:sub_dmrrowp0
10152      0,	// G8RC_and_G8RC_NOX0:sub_dmrrowp1
10153      0,	// G8RC_and_G8RC_NOX0:sub_eq
10154      0,	// G8RC_and_G8RC_NOX0:sub_gp8_x0
10155      0,	// G8RC_and_G8RC_NOX0:sub_gp8_x1
10156      0,	// G8RC_and_G8RC_NOX0:sub_gt
10157      0,	// G8RC_and_G8RC_NOX0:sub_lt
10158      0,	// G8RC_and_G8RC_NOX0:sub_pair0
10159      0,	// G8RC_and_G8RC_NOX0:sub_pair1
10160      0,	// G8RC_and_G8RC_NOX0:sub_un
10161      0,	// G8RC_and_G8RC_NOX0:sub_vsx0
10162      0,	// G8RC_and_G8RC_NOX0:sub_vsx1
10163      0,	// G8RC_and_G8RC_NOX0:sub_wacc_hi
10164      0,	// G8RC_and_G8RC_NOX0:sub_wacc_lo
10165      0,	// G8RC_and_G8RC_NOX0:sub_vsx1_then_sub_64
10166      0,	// G8RC_and_G8RC_NOX0:sub_pair1_then_sub_64
10167      0,	// G8RC_and_G8RC_NOX0:sub_pair1_then_sub_vsx0
10168      0,	// G8RC_and_G8RC_NOX0:sub_pair1_then_sub_vsx1
10169      0,	// G8RC_and_G8RC_NOX0:sub_pair1_then_sub_vsx1_then_sub_64
10170      0,	// G8RC_and_G8RC_NOX0:sub_dmrrowp1_then_sub_dmrrow0
10171      0,	// G8RC_and_G8RC_NOX0:sub_dmrrowp1_then_sub_dmrrow1
10172      0,	// G8RC_and_G8RC_NOX0:sub_wacc_hi_then_sub_dmrrow0
10173      0,	// G8RC_and_G8RC_NOX0:sub_wacc_hi_then_sub_dmrrow1
10174      0,	// G8RC_and_G8RC_NOX0:sub_wacc_hi_then_sub_dmrrowp0
10175      0,	// G8RC_and_G8RC_NOX0:sub_wacc_hi_then_sub_dmrrowp1
10176      0,	// G8RC_and_G8RC_NOX0:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10177      0,	// G8RC_and_G8RC_NOX0:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10178      0,	// G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_dmrrow0
10179      0,	// G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_dmrrow1
10180      0,	// G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_dmrrowp0
10181      0,	// G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_dmrrowp1
10182      0,	// G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_wacc_hi
10183      0,	// G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_wacc_lo
10184      0,	// G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
10185      0,	// G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
10186      0,	// G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
10187      0,	// G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
10188      0,	// G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
10189      0,	// G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
10190      0,	// G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10191      0,	// G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10192      0,	// G8RC_and_G8RC_NOX0:sub_gp8_x1_then_sub_32
10193    },
10194    {	// F8RC
10195      0,	// F8RC:sub_32
10196      0,	// F8RC:sub_64
10197      0,	// F8RC:sub_dmr0
10198      0,	// F8RC:sub_dmr1
10199      0,	// F8RC:sub_dmrrow0
10200      0,	// F8RC:sub_dmrrow1
10201      0,	// F8RC:sub_dmrrowp0
10202      0,	// F8RC:sub_dmrrowp1
10203      0,	// F8RC:sub_eq
10204      0,	// F8RC:sub_gp8_x0
10205      0,	// F8RC:sub_gp8_x1
10206      0,	// F8RC:sub_gt
10207      0,	// F8RC:sub_lt
10208      0,	// F8RC:sub_pair0
10209      0,	// F8RC:sub_pair1
10210      0,	// F8RC:sub_un
10211      0,	// F8RC:sub_vsx0
10212      0,	// F8RC:sub_vsx1
10213      0,	// F8RC:sub_wacc_hi
10214      0,	// F8RC:sub_wacc_lo
10215      0,	// F8RC:sub_vsx1_then_sub_64
10216      0,	// F8RC:sub_pair1_then_sub_64
10217      0,	// F8RC:sub_pair1_then_sub_vsx0
10218      0,	// F8RC:sub_pair1_then_sub_vsx1
10219      0,	// F8RC:sub_pair1_then_sub_vsx1_then_sub_64
10220      0,	// F8RC:sub_dmrrowp1_then_sub_dmrrow0
10221      0,	// F8RC:sub_dmrrowp1_then_sub_dmrrow1
10222      0,	// F8RC:sub_wacc_hi_then_sub_dmrrow0
10223      0,	// F8RC:sub_wacc_hi_then_sub_dmrrow1
10224      0,	// F8RC:sub_wacc_hi_then_sub_dmrrowp0
10225      0,	// F8RC:sub_wacc_hi_then_sub_dmrrowp1
10226      0,	// F8RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10227      0,	// F8RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10228      0,	// F8RC:sub_dmr1_then_sub_dmrrow0
10229      0,	// F8RC:sub_dmr1_then_sub_dmrrow1
10230      0,	// F8RC:sub_dmr1_then_sub_dmrrowp0
10231      0,	// F8RC:sub_dmr1_then_sub_dmrrowp1
10232      0,	// F8RC:sub_dmr1_then_sub_wacc_hi
10233      0,	// F8RC:sub_dmr1_then_sub_wacc_lo
10234      0,	// F8RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
10235      0,	// F8RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
10236      0,	// F8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
10237      0,	// F8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
10238      0,	// F8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
10239      0,	// F8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
10240      0,	// F8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10241      0,	// F8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10242      0,	// F8RC:sub_gp8_x1_then_sub_32
10243    },
10244    {	// SPERC
10245      2,	// SPERC:sub_32 -> GPRC
10246      0,	// SPERC:sub_64
10247      0,	// SPERC:sub_dmr0
10248      0,	// SPERC:sub_dmr1
10249      0,	// SPERC:sub_dmrrow0
10250      0,	// SPERC:sub_dmrrow1
10251      0,	// SPERC:sub_dmrrowp0
10252      0,	// SPERC:sub_dmrrowp1
10253      0,	// SPERC:sub_eq
10254      0,	// SPERC:sub_gp8_x0
10255      0,	// SPERC:sub_gp8_x1
10256      0,	// SPERC:sub_gt
10257      0,	// SPERC:sub_lt
10258      0,	// SPERC:sub_pair0
10259      0,	// SPERC:sub_pair1
10260      0,	// SPERC:sub_un
10261      0,	// SPERC:sub_vsx0
10262      0,	// SPERC:sub_vsx1
10263      0,	// SPERC:sub_wacc_hi
10264      0,	// SPERC:sub_wacc_lo
10265      0,	// SPERC:sub_vsx1_then_sub_64
10266      0,	// SPERC:sub_pair1_then_sub_64
10267      0,	// SPERC:sub_pair1_then_sub_vsx0
10268      0,	// SPERC:sub_pair1_then_sub_vsx1
10269      0,	// SPERC:sub_pair1_then_sub_vsx1_then_sub_64
10270      0,	// SPERC:sub_dmrrowp1_then_sub_dmrrow0
10271      0,	// SPERC:sub_dmrrowp1_then_sub_dmrrow1
10272      0,	// SPERC:sub_wacc_hi_then_sub_dmrrow0
10273      0,	// SPERC:sub_wacc_hi_then_sub_dmrrow1
10274      0,	// SPERC:sub_wacc_hi_then_sub_dmrrowp0
10275      0,	// SPERC:sub_wacc_hi_then_sub_dmrrowp1
10276      0,	// SPERC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10277      0,	// SPERC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10278      0,	// SPERC:sub_dmr1_then_sub_dmrrow0
10279      0,	// SPERC:sub_dmr1_then_sub_dmrrow1
10280      0,	// SPERC:sub_dmr1_then_sub_dmrrowp0
10281      0,	// SPERC:sub_dmr1_then_sub_dmrrowp1
10282      0,	// SPERC:sub_dmr1_then_sub_wacc_hi
10283      0,	// SPERC:sub_dmr1_then_sub_wacc_lo
10284      0,	// SPERC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
10285      0,	// SPERC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
10286      0,	// SPERC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
10287      0,	// SPERC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
10288      0,	// SPERC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
10289      0,	// SPERC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
10290      0,	// SPERC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10291      0,	// SPERC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10292      0,	// SPERC:sub_gp8_x1_then_sub_32
10293    },
10294    {	// VFRC
10295      0,	// VFRC:sub_32
10296      0,	// VFRC:sub_64
10297      0,	// VFRC:sub_dmr0
10298      0,	// VFRC:sub_dmr1
10299      0,	// VFRC:sub_dmrrow0
10300      0,	// VFRC:sub_dmrrow1
10301      0,	// VFRC:sub_dmrrowp0
10302      0,	// VFRC:sub_dmrrowp1
10303      0,	// VFRC:sub_eq
10304      0,	// VFRC:sub_gp8_x0
10305      0,	// VFRC:sub_gp8_x1
10306      0,	// VFRC:sub_gt
10307      0,	// VFRC:sub_lt
10308      0,	// VFRC:sub_pair0
10309      0,	// VFRC:sub_pair1
10310      0,	// VFRC:sub_un
10311      0,	// VFRC:sub_vsx0
10312      0,	// VFRC:sub_vsx1
10313      0,	// VFRC:sub_wacc_hi
10314      0,	// VFRC:sub_wacc_lo
10315      0,	// VFRC:sub_vsx1_then_sub_64
10316      0,	// VFRC:sub_pair1_then_sub_64
10317      0,	// VFRC:sub_pair1_then_sub_vsx0
10318      0,	// VFRC:sub_pair1_then_sub_vsx1
10319      0,	// VFRC:sub_pair1_then_sub_vsx1_then_sub_64
10320      0,	// VFRC:sub_dmrrowp1_then_sub_dmrrow0
10321      0,	// VFRC:sub_dmrrowp1_then_sub_dmrrow1
10322      0,	// VFRC:sub_wacc_hi_then_sub_dmrrow0
10323      0,	// VFRC:sub_wacc_hi_then_sub_dmrrow1
10324      0,	// VFRC:sub_wacc_hi_then_sub_dmrrowp0
10325      0,	// VFRC:sub_wacc_hi_then_sub_dmrrowp1
10326      0,	// VFRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10327      0,	// VFRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10328      0,	// VFRC:sub_dmr1_then_sub_dmrrow0
10329      0,	// VFRC:sub_dmr1_then_sub_dmrrow1
10330      0,	// VFRC:sub_dmr1_then_sub_dmrrowp0
10331      0,	// VFRC:sub_dmr1_then_sub_dmrrowp1
10332      0,	// VFRC:sub_dmr1_then_sub_wacc_hi
10333      0,	// VFRC:sub_dmr1_then_sub_wacc_lo
10334      0,	// VFRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
10335      0,	// VFRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
10336      0,	// VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
10337      0,	// VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
10338      0,	// VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
10339      0,	// VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
10340      0,	// VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10341      0,	// VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10342      0,	// VFRC:sub_gp8_x1_then_sub_32
10343    },
10344    {	// SPERC_with_sub_32_in_GPRC_NOR0
10345      4,	// SPERC_with_sub_32_in_GPRC_NOR0:sub_32 -> GPRC_and_GPRC_NOR0
10346      0,	// SPERC_with_sub_32_in_GPRC_NOR0:sub_64
10347      0,	// SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr0
10348      0,	// SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1
10349      0,	// SPERC_with_sub_32_in_GPRC_NOR0:sub_dmrrow0
10350      0,	// SPERC_with_sub_32_in_GPRC_NOR0:sub_dmrrow1
10351      0,	// SPERC_with_sub_32_in_GPRC_NOR0:sub_dmrrowp0
10352      0,	// SPERC_with_sub_32_in_GPRC_NOR0:sub_dmrrowp1
10353      0,	// SPERC_with_sub_32_in_GPRC_NOR0:sub_eq
10354      0,	// SPERC_with_sub_32_in_GPRC_NOR0:sub_gp8_x0
10355      0,	// SPERC_with_sub_32_in_GPRC_NOR0:sub_gp8_x1
10356      0,	// SPERC_with_sub_32_in_GPRC_NOR0:sub_gt
10357      0,	// SPERC_with_sub_32_in_GPRC_NOR0:sub_lt
10358      0,	// SPERC_with_sub_32_in_GPRC_NOR0:sub_pair0
10359      0,	// SPERC_with_sub_32_in_GPRC_NOR0:sub_pair1
10360      0,	// SPERC_with_sub_32_in_GPRC_NOR0:sub_un
10361      0,	// SPERC_with_sub_32_in_GPRC_NOR0:sub_vsx0
10362      0,	// SPERC_with_sub_32_in_GPRC_NOR0:sub_vsx1
10363      0,	// SPERC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi
10364      0,	// SPERC_with_sub_32_in_GPRC_NOR0:sub_wacc_lo
10365      0,	// SPERC_with_sub_32_in_GPRC_NOR0:sub_vsx1_then_sub_64
10366      0,	// SPERC_with_sub_32_in_GPRC_NOR0:sub_pair1_then_sub_64
10367      0,	// SPERC_with_sub_32_in_GPRC_NOR0:sub_pair1_then_sub_vsx0
10368      0,	// SPERC_with_sub_32_in_GPRC_NOR0:sub_pair1_then_sub_vsx1
10369      0,	// SPERC_with_sub_32_in_GPRC_NOR0:sub_pair1_then_sub_vsx1_then_sub_64
10370      0,	// SPERC_with_sub_32_in_GPRC_NOR0:sub_dmrrowp1_then_sub_dmrrow0
10371      0,	// SPERC_with_sub_32_in_GPRC_NOR0:sub_dmrrowp1_then_sub_dmrrow1
10372      0,	// SPERC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrow0
10373      0,	// SPERC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrow1
10374      0,	// SPERC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp0
10375      0,	// SPERC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp1
10376      0,	// SPERC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10377      0,	// SPERC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10378      0,	// SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_dmrrow0
10379      0,	// SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_dmrrow1
10380      0,	// SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_dmrrowp0
10381      0,	// SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_dmrrowp1
10382      0,	// SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi
10383      0,	// SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_lo
10384      0,	// SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
10385      0,	// SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
10386      0,	// SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
10387      0,	// SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
10388      0,	// SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
10389      0,	// SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
10390      0,	// SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10391      0,	// SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10392      0,	// SPERC_with_sub_32_in_GPRC_NOR0:sub_gp8_x1_then_sub_32
10393    },
10394    {	// SPILLTOVSRRC_and_VFRC
10395      0,	// SPILLTOVSRRC_and_VFRC:sub_32
10396      0,	// SPILLTOVSRRC_and_VFRC:sub_64
10397      0,	// SPILLTOVSRRC_and_VFRC:sub_dmr0
10398      0,	// SPILLTOVSRRC_and_VFRC:sub_dmr1
10399      0,	// SPILLTOVSRRC_and_VFRC:sub_dmrrow0
10400      0,	// SPILLTOVSRRC_and_VFRC:sub_dmrrow1
10401      0,	// SPILLTOVSRRC_and_VFRC:sub_dmrrowp0
10402      0,	// SPILLTOVSRRC_and_VFRC:sub_dmrrowp1
10403      0,	// SPILLTOVSRRC_and_VFRC:sub_eq
10404      0,	// SPILLTOVSRRC_and_VFRC:sub_gp8_x0
10405      0,	// SPILLTOVSRRC_and_VFRC:sub_gp8_x1
10406      0,	// SPILLTOVSRRC_and_VFRC:sub_gt
10407      0,	// SPILLTOVSRRC_and_VFRC:sub_lt
10408      0,	// SPILLTOVSRRC_and_VFRC:sub_pair0
10409      0,	// SPILLTOVSRRC_and_VFRC:sub_pair1
10410      0,	// SPILLTOVSRRC_and_VFRC:sub_un
10411      0,	// SPILLTOVSRRC_and_VFRC:sub_vsx0
10412      0,	// SPILLTOVSRRC_and_VFRC:sub_vsx1
10413      0,	// SPILLTOVSRRC_and_VFRC:sub_wacc_hi
10414      0,	// SPILLTOVSRRC_and_VFRC:sub_wacc_lo
10415      0,	// SPILLTOVSRRC_and_VFRC:sub_vsx1_then_sub_64
10416      0,	// SPILLTOVSRRC_and_VFRC:sub_pair1_then_sub_64
10417      0,	// SPILLTOVSRRC_and_VFRC:sub_pair1_then_sub_vsx0
10418      0,	// SPILLTOVSRRC_and_VFRC:sub_pair1_then_sub_vsx1
10419      0,	// SPILLTOVSRRC_and_VFRC:sub_pair1_then_sub_vsx1_then_sub_64
10420      0,	// SPILLTOVSRRC_and_VFRC:sub_dmrrowp1_then_sub_dmrrow0
10421      0,	// SPILLTOVSRRC_and_VFRC:sub_dmrrowp1_then_sub_dmrrow1
10422      0,	// SPILLTOVSRRC_and_VFRC:sub_wacc_hi_then_sub_dmrrow0
10423      0,	// SPILLTOVSRRC_and_VFRC:sub_wacc_hi_then_sub_dmrrow1
10424      0,	// SPILLTOVSRRC_and_VFRC:sub_wacc_hi_then_sub_dmrrowp0
10425      0,	// SPILLTOVSRRC_and_VFRC:sub_wacc_hi_then_sub_dmrrowp1
10426      0,	// SPILLTOVSRRC_and_VFRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10427      0,	// SPILLTOVSRRC_and_VFRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10428      0,	// SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_dmrrow0
10429      0,	// SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_dmrrow1
10430      0,	// SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_dmrrowp0
10431      0,	// SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_dmrrowp1
10432      0,	// SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi
10433      0,	// SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_lo
10434      0,	// SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
10435      0,	// SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
10436      0,	// SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
10437      0,	// SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
10438      0,	// SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
10439      0,	// SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
10440      0,	// SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10441      0,	// SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10442      0,	// SPILLTOVSRRC_and_VFRC:sub_gp8_x1_then_sub_32
10443    },
10444    {	// SPILLTOVSRRC_and_F4RC
10445      0,	// SPILLTOVSRRC_and_F4RC:sub_32
10446      0,	// SPILLTOVSRRC_and_F4RC:sub_64
10447      0,	// SPILLTOVSRRC_and_F4RC:sub_dmr0
10448      0,	// SPILLTOVSRRC_and_F4RC:sub_dmr1
10449      0,	// SPILLTOVSRRC_and_F4RC:sub_dmrrow0
10450      0,	// SPILLTOVSRRC_and_F4RC:sub_dmrrow1
10451      0,	// SPILLTOVSRRC_and_F4RC:sub_dmrrowp0
10452      0,	// SPILLTOVSRRC_and_F4RC:sub_dmrrowp1
10453      0,	// SPILLTOVSRRC_and_F4RC:sub_eq
10454      0,	// SPILLTOVSRRC_and_F4RC:sub_gp8_x0
10455      0,	// SPILLTOVSRRC_and_F4RC:sub_gp8_x1
10456      0,	// SPILLTOVSRRC_and_F4RC:sub_gt
10457      0,	// SPILLTOVSRRC_and_F4RC:sub_lt
10458      0,	// SPILLTOVSRRC_and_F4RC:sub_pair0
10459      0,	// SPILLTOVSRRC_and_F4RC:sub_pair1
10460      0,	// SPILLTOVSRRC_and_F4RC:sub_un
10461      0,	// SPILLTOVSRRC_and_F4RC:sub_vsx0
10462      0,	// SPILLTOVSRRC_and_F4RC:sub_vsx1
10463      0,	// SPILLTOVSRRC_and_F4RC:sub_wacc_hi
10464      0,	// SPILLTOVSRRC_and_F4RC:sub_wacc_lo
10465      0,	// SPILLTOVSRRC_and_F4RC:sub_vsx1_then_sub_64
10466      0,	// SPILLTOVSRRC_and_F4RC:sub_pair1_then_sub_64
10467      0,	// SPILLTOVSRRC_and_F4RC:sub_pair1_then_sub_vsx0
10468      0,	// SPILLTOVSRRC_and_F4RC:sub_pair1_then_sub_vsx1
10469      0,	// SPILLTOVSRRC_and_F4RC:sub_pair1_then_sub_vsx1_then_sub_64
10470      0,	// SPILLTOVSRRC_and_F4RC:sub_dmrrowp1_then_sub_dmrrow0
10471      0,	// SPILLTOVSRRC_and_F4RC:sub_dmrrowp1_then_sub_dmrrow1
10472      0,	// SPILLTOVSRRC_and_F4RC:sub_wacc_hi_then_sub_dmrrow0
10473      0,	// SPILLTOVSRRC_and_F4RC:sub_wacc_hi_then_sub_dmrrow1
10474      0,	// SPILLTOVSRRC_and_F4RC:sub_wacc_hi_then_sub_dmrrowp0
10475      0,	// SPILLTOVSRRC_and_F4RC:sub_wacc_hi_then_sub_dmrrowp1
10476      0,	// SPILLTOVSRRC_and_F4RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10477      0,	// SPILLTOVSRRC_and_F4RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10478      0,	// SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_dmrrow0
10479      0,	// SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_dmrrow1
10480      0,	// SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_dmrrowp0
10481      0,	// SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_dmrrowp1
10482      0,	// SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi
10483      0,	// SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_lo
10484      0,	// SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
10485      0,	// SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
10486      0,	// SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
10487      0,	// SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
10488      0,	// SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
10489      0,	// SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
10490      0,	// SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10491      0,	// SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10492      0,	// SPILLTOVSRRC_and_F4RC:sub_gp8_x1_then_sub_32
10493    },
10494    {	// CTRRC8
10495      0,	// CTRRC8:sub_32
10496      0,	// CTRRC8:sub_64
10497      0,	// CTRRC8:sub_dmr0
10498      0,	// CTRRC8:sub_dmr1
10499      0,	// CTRRC8:sub_dmrrow0
10500      0,	// CTRRC8:sub_dmrrow1
10501      0,	// CTRRC8:sub_dmrrowp0
10502      0,	// CTRRC8:sub_dmrrowp1
10503      0,	// CTRRC8:sub_eq
10504      0,	// CTRRC8:sub_gp8_x0
10505      0,	// CTRRC8:sub_gp8_x1
10506      0,	// CTRRC8:sub_gt
10507      0,	// CTRRC8:sub_lt
10508      0,	// CTRRC8:sub_pair0
10509      0,	// CTRRC8:sub_pair1
10510      0,	// CTRRC8:sub_un
10511      0,	// CTRRC8:sub_vsx0
10512      0,	// CTRRC8:sub_vsx1
10513      0,	// CTRRC8:sub_wacc_hi
10514      0,	// CTRRC8:sub_wacc_lo
10515      0,	// CTRRC8:sub_vsx1_then_sub_64
10516      0,	// CTRRC8:sub_pair1_then_sub_64
10517      0,	// CTRRC8:sub_pair1_then_sub_vsx0
10518      0,	// CTRRC8:sub_pair1_then_sub_vsx1
10519      0,	// CTRRC8:sub_pair1_then_sub_vsx1_then_sub_64
10520      0,	// CTRRC8:sub_dmrrowp1_then_sub_dmrrow0
10521      0,	// CTRRC8:sub_dmrrowp1_then_sub_dmrrow1
10522      0,	// CTRRC8:sub_wacc_hi_then_sub_dmrrow0
10523      0,	// CTRRC8:sub_wacc_hi_then_sub_dmrrow1
10524      0,	// CTRRC8:sub_wacc_hi_then_sub_dmrrowp0
10525      0,	// CTRRC8:sub_wacc_hi_then_sub_dmrrowp1
10526      0,	// CTRRC8:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10527      0,	// CTRRC8:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10528      0,	// CTRRC8:sub_dmr1_then_sub_dmrrow0
10529      0,	// CTRRC8:sub_dmr1_then_sub_dmrrow1
10530      0,	// CTRRC8:sub_dmr1_then_sub_dmrrowp0
10531      0,	// CTRRC8:sub_dmr1_then_sub_dmrrowp1
10532      0,	// CTRRC8:sub_dmr1_then_sub_wacc_hi
10533      0,	// CTRRC8:sub_dmr1_then_sub_wacc_lo
10534      0,	// CTRRC8:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
10535      0,	// CTRRC8:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
10536      0,	// CTRRC8:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
10537      0,	// CTRRC8:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
10538      0,	// CTRRC8:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
10539      0,	// CTRRC8:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
10540      0,	// CTRRC8:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10541      0,	// CTRRC8:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10542      0,	// CTRRC8:sub_gp8_x1_then_sub_32
10543    },
10544    {	// LR8RC
10545      0,	// LR8RC:sub_32
10546      0,	// LR8RC:sub_64
10547      0,	// LR8RC:sub_dmr0
10548      0,	// LR8RC:sub_dmr1
10549      0,	// LR8RC:sub_dmrrow0
10550      0,	// LR8RC:sub_dmrrow1
10551      0,	// LR8RC:sub_dmrrowp0
10552      0,	// LR8RC:sub_dmrrowp1
10553      0,	// LR8RC:sub_eq
10554      0,	// LR8RC:sub_gp8_x0
10555      0,	// LR8RC:sub_gp8_x1
10556      0,	// LR8RC:sub_gt
10557      0,	// LR8RC:sub_lt
10558      0,	// LR8RC:sub_pair0
10559      0,	// LR8RC:sub_pair1
10560      0,	// LR8RC:sub_un
10561      0,	// LR8RC:sub_vsx0
10562      0,	// LR8RC:sub_vsx1
10563      0,	// LR8RC:sub_wacc_hi
10564      0,	// LR8RC:sub_wacc_lo
10565      0,	// LR8RC:sub_vsx1_then_sub_64
10566      0,	// LR8RC:sub_pair1_then_sub_64
10567      0,	// LR8RC:sub_pair1_then_sub_vsx0
10568      0,	// LR8RC:sub_pair1_then_sub_vsx1
10569      0,	// LR8RC:sub_pair1_then_sub_vsx1_then_sub_64
10570      0,	// LR8RC:sub_dmrrowp1_then_sub_dmrrow0
10571      0,	// LR8RC:sub_dmrrowp1_then_sub_dmrrow1
10572      0,	// LR8RC:sub_wacc_hi_then_sub_dmrrow0
10573      0,	// LR8RC:sub_wacc_hi_then_sub_dmrrow1
10574      0,	// LR8RC:sub_wacc_hi_then_sub_dmrrowp0
10575      0,	// LR8RC:sub_wacc_hi_then_sub_dmrrowp1
10576      0,	// LR8RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10577      0,	// LR8RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10578      0,	// LR8RC:sub_dmr1_then_sub_dmrrow0
10579      0,	// LR8RC:sub_dmr1_then_sub_dmrrow1
10580      0,	// LR8RC:sub_dmr1_then_sub_dmrrowp0
10581      0,	// LR8RC:sub_dmr1_then_sub_dmrrowp1
10582      0,	// LR8RC:sub_dmr1_then_sub_wacc_hi
10583      0,	// LR8RC:sub_dmr1_then_sub_wacc_lo
10584      0,	// LR8RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
10585      0,	// LR8RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
10586      0,	// LR8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
10587      0,	// LR8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
10588      0,	// LR8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
10589      0,	// LR8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
10590      0,	// LR8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10591      0,	// LR8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10592      0,	// LR8RC:sub_gp8_x1_then_sub_32
10593    },
10594    {	// DMRROWRC
10595      0,	// DMRROWRC:sub_32
10596      0,	// DMRROWRC:sub_64
10597      0,	// DMRROWRC:sub_dmr0
10598      0,	// DMRROWRC:sub_dmr1
10599      0,	// DMRROWRC:sub_dmrrow0
10600      0,	// DMRROWRC:sub_dmrrow1
10601      0,	// DMRROWRC:sub_dmrrowp0
10602      0,	// DMRROWRC:sub_dmrrowp1
10603      0,	// DMRROWRC:sub_eq
10604      0,	// DMRROWRC:sub_gp8_x0
10605      0,	// DMRROWRC:sub_gp8_x1
10606      0,	// DMRROWRC:sub_gt
10607      0,	// DMRROWRC:sub_lt
10608      0,	// DMRROWRC:sub_pair0
10609      0,	// DMRROWRC:sub_pair1
10610      0,	// DMRROWRC:sub_un
10611      0,	// DMRROWRC:sub_vsx0
10612      0,	// DMRROWRC:sub_vsx1
10613      0,	// DMRROWRC:sub_wacc_hi
10614      0,	// DMRROWRC:sub_wacc_lo
10615      0,	// DMRROWRC:sub_vsx1_then_sub_64
10616      0,	// DMRROWRC:sub_pair1_then_sub_64
10617      0,	// DMRROWRC:sub_pair1_then_sub_vsx0
10618      0,	// DMRROWRC:sub_pair1_then_sub_vsx1
10619      0,	// DMRROWRC:sub_pair1_then_sub_vsx1_then_sub_64
10620      0,	// DMRROWRC:sub_dmrrowp1_then_sub_dmrrow0
10621      0,	// DMRROWRC:sub_dmrrowp1_then_sub_dmrrow1
10622      0,	// DMRROWRC:sub_wacc_hi_then_sub_dmrrow0
10623      0,	// DMRROWRC:sub_wacc_hi_then_sub_dmrrow1
10624      0,	// DMRROWRC:sub_wacc_hi_then_sub_dmrrowp0
10625      0,	// DMRROWRC:sub_wacc_hi_then_sub_dmrrowp1
10626      0,	// DMRROWRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10627      0,	// DMRROWRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10628      0,	// DMRROWRC:sub_dmr1_then_sub_dmrrow0
10629      0,	// DMRROWRC:sub_dmr1_then_sub_dmrrow1
10630      0,	// DMRROWRC:sub_dmr1_then_sub_dmrrowp0
10631      0,	// DMRROWRC:sub_dmr1_then_sub_dmrrowp1
10632      0,	// DMRROWRC:sub_dmr1_then_sub_wacc_hi
10633      0,	// DMRROWRC:sub_dmr1_then_sub_wacc_lo
10634      0,	// DMRROWRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
10635      0,	// DMRROWRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
10636      0,	// DMRROWRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
10637      0,	// DMRROWRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
10638      0,	// DMRROWRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
10639      0,	// DMRROWRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
10640      0,	// DMRROWRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10641      0,	// DMRROWRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10642      0,	// DMRROWRC:sub_gp8_x1_then_sub_32
10643    },
10644    {	// VSRC
10645      0,	// VSRC:sub_32
10646      1,	// VSRC:sub_64 -> VSSRC
10647      0,	// VSRC:sub_dmr0
10648      0,	// VSRC:sub_dmr1
10649      0,	// VSRC:sub_dmrrow0
10650      0,	// VSRC:sub_dmrrow1
10651      0,	// VSRC:sub_dmrrowp0
10652      0,	// VSRC:sub_dmrrowp1
10653      0,	// VSRC:sub_eq
10654      0,	// VSRC:sub_gp8_x0
10655      0,	// VSRC:sub_gp8_x1
10656      0,	// VSRC:sub_gt
10657      0,	// VSRC:sub_lt
10658      0,	// VSRC:sub_pair0
10659      0,	// VSRC:sub_pair1
10660      0,	// VSRC:sub_un
10661      0,	// VSRC:sub_vsx0
10662      0,	// VSRC:sub_vsx1
10663      0,	// VSRC:sub_wacc_hi
10664      0,	// VSRC:sub_wacc_lo
10665      0,	// VSRC:sub_vsx1_then_sub_64
10666      0,	// VSRC:sub_pair1_then_sub_64
10667      0,	// VSRC:sub_pair1_then_sub_vsx0
10668      0,	// VSRC:sub_pair1_then_sub_vsx1
10669      0,	// VSRC:sub_pair1_then_sub_vsx1_then_sub_64
10670      0,	// VSRC:sub_dmrrowp1_then_sub_dmrrow0
10671      0,	// VSRC:sub_dmrrowp1_then_sub_dmrrow1
10672      0,	// VSRC:sub_wacc_hi_then_sub_dmrrow0
10673      0,	// VSRC:sub_wacc_hi_then_sub_dmrrow1
10674      0,	// VSRC:sub_wacc_hi_then_sub_dmrrowp0
10675      0,	// VSRC:sub_wacc_hi_then_sub_dmrrowp1
10676      0,	// VSRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10677      0,	// VSRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10678      0,	// VSRC:sub_dmr1_then_sub_dmrrow0
10679      0,	// VSRC:sub_dmr1_then_sub_dmrrow1
10680      0,	// VSRC:sub_dmr1_then_sub_dmrrowp0
10681      0,	// VSRC:sub_dmr1_then_sub_dmrrowp1
10682      0,	// VSRC:sub_dmr1_then_sub_wacc_hi
10683      0,	// VSRC:sub_dmr1_then_sub_wacc_lo
10684      0,	// VSRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
10685      0,	// VSRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
10686      0,	// VSRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
10687      0,	// VSRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
10688      0,	// VSRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
10689      0,	// VSRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
10690      0,	// VSRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10691      0,	// VSRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10692      0,	// VSRC:sub_gp8_x1_then_sub_32
10693    },
10694    {	// VSRC_with_sub_64_in_SPILLTOVSRRC
10695      0,	// VSRC_with_sub_64_in_SPILLTOVSRRC:sub_32
10696      16,	// VSRC_with_sub_64_in_SPILLTOVSRRC:sub_64 -> SPILLTOVSRRC_and_VSFRC
10697      0,	// VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr0
10698      0,	// VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1
10699      0,	// VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrow0
10700      0,	// VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrow1
10701      0,	// VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp0
10702      0,	// VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1
10703      0,	// VSRC_with_sub_64_in_SPILLTOVSRRC:sub_eq
10704      0,	// VSRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x0
10705      0,	// VSRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x1
10706      0,	// VSRC_with_sub_64_in_SPILLTOVSRRC:sub_gt
10707      0,	// VSRC_with_sub_64_in_SPILLTOVSRRC:sub_lt
10708      0,	// VSRC_with_sub_64_in_SPILLTOVSRRC:sub_pair0
10709      0,	// VSRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1
10710      0,	// VSRC_with_sub_64_in_SPILLTOVSRRC:sub_un
10711      0,	// VSRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx0
10712      0,	// VSRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1
10713      0,	// VSRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi
10714      0,	// VSRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_lo
10715      0,	// VSRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1_then_sub_64
10716      0,	// VSRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_64
10717      0,	// VSRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx0
10718      0,	// VSRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1
10719      0,	// VSRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1_then_sub_64
10720      0,	// VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow0
10721      0,	// VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow1
10722      0,	// VSRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow0
10723      0,	// VSRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow1
10724      0,	// VSRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp0
10725      0,	// VSRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1
10726      0,	// VSRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10727      0,	// VSRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10728      0,	// VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow0
10729      0,	// VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow1
10730      0,	// VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp0
10731      0,	// VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1
10732      0,	// VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi
10733      0,	// VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_lo
10734      0,	// VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
10735      0,	// VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
10736      0,	// VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
10737      0,	// VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
10738      0,	// VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
10739      0,	// VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
10740      0,	// VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10741      0,	// VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10742      0,	// VSRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x1_then_sub_32
10743    },
10744    {	// VRRC
10745      0,	// VRRC:sub_32
10746      20,	// VRRC:sub_64 -> VFRC
10747      0,	// VRRC:sub_dmr0
10748      0,	// VRRC:sub_dmr1
10749      0,	// VRRC:sub_dmrrow0
10750      0,	// VRRC:sub_dmrrow1
10751      0,	// VRRC:sub_dmrrowp0
10752      0,	// VRRC:sub_dmrrowp1
10753      0,	// VRRC:sub_eq
10754      0,	// VRRC:sub_gp8_x0
10755      0,	// VRRC:sub_gp8_x1
10756      0,	// VRRC:sub_gt
10757      0,	// VRRC:sub_lt
10758      0,	// VRRC:sub_pair0
10759      0,	// VRRC:sub_pair1
10760      0,	// VRRC:sub_un
10761      0,	// VRRC:sub_vsx0
10762      0,	// VRRC:sub_vsx1
10763      0,	// VRRC:sub_wacc_hi
10764      0,	// VRRC:sub_wacc_lo
10765      0,	// VRRC:sub_vsx1_then_sub_64
10766      0,	// VRRC:sub_pair1_then_sub_64
10767      0,	// VRRC:sub_pair1_then_sub_vsx0
10768      0,	// VRRC:sub_pair1_then_sub_vsx1
10769      0,	// VRRC:sub_pair1_then_sub_vsx1_then_sub_64
10770      0,	// VRRC:sub_dmrrowp1_then_sub_dmrrow0
10771      0,	// VRRC:sub_dmrrowp1_then_sub_dmrrow1
10772      0,	// VRRC:sub_wacc_hi_then_sub_dmrrow0
10773      0,	// VRRC:sub_wacc_hi_then_sub_dmrrow1
10774      0,	// VRRC:sub_wacc_hi_then_sub_dmrrowp0
10775      0,	// VRRC:sub_wacc_hi_then_sub_dmrrowp1
10776      0,	// VRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10777      0,	// VRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10778      0,	// VRRC:sub_dmr1_then_sub_dmrrow0
10779      0,	// VRRC:sub_dmr1_then_sub_dmrrow1
10780      0,	// VRRC:sub_dmr1_then_sub_dmrrowp0
10781      0,	// VRRC:sub_dmr1_then_sub_dmrrowp1
10782      0,	// VRRC:sub_dmr1_then_sub_wacc_hi
10783      0,	// VRRC:sub_dmr1_then_sub_wacc_lo
10784      0,	// VRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
10785      0,	// VRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
10786      0,	// VRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
10787      0,	// VRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
10788      0,	// VRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
10789      0,	// VRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
10790      0,	// VRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10791      0,	// VRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10792      0,	// VRRC:sub_gp8_x1_then_sub_32
10793    },
10794    {	// VSLRC
10795      0,	// VSLRC:sub_32
10796      6,	// VSLRC:sub_64 -> F4RC
10797      0,	// VSLRC:sub_dmr0
10798      0,	// VSLRC:sub_dmr1
10799      0,	// VSLRC:sub_dmrrow0
10800      0,	// VSLRC:sub_dmrrow1
10801      0,	// VSLRC:sub_dmrrowp0
10802      0,	// VSLRC:sub_dmrrowp1
10803      0,	// VSLRC:sub_eq
10804      0,	// VSLRC:sub_gp8_x0
10805      0,	// VSLRC:sub_gp8_x1
10806      0,	// VSLRC:sub_gt
10807      0,	// VSLRC:sub_lt
10808      0,	// VSLRC:sub_pair0
10809      0,	// VSLRC:sub_pair1
10810      0,	// VSLRC:sub_un
10811      0,	// VSLRC:sub_vsx0
10812      0,	// VSLRC:sub_vsx1
10813      0,	// VSLRC:sub_wacc_hi
10814      0,	// VSLRC:sub_wacc_lo
10815      0,	// VSLRC:sub_vsx1_then_sub_64
10816      0,	// VSLRC:sub_pair1_then_sub_64
10817      0,	// VSLRC:sub_pair1_then_sub_vsx0
10818      0,	// VSLRC:sub_pair1_then_sub_vsx1
10819      0,	// VSLRC:sub_pair1_then_sub_vsx1_then_sub_64
10820      0,	// VSLRC:sub_dmrrowp1_then_sub_dmrrow0
10821      0,	// VSLRC:sub_dmrrowp1_then_sub_dmrrow1
10822      0,	// VSLRC:sub_wacc_hi_then_sub_dmrrow0
10823      0,	// VSLRC:sub_wacc_hi_then_sub_dmrrow1
10824      0,	// VSLRC:sub_wacc_hi_then_sub_dmrrowp0
10825      0,	// VSLRC:sub_wacc_hi_then_sub_dmrrowp1
10826      0,	// VSLRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10827      0,	// VSLRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10828      0,	// VSLRC:sub_dmr1_then_sub_dmrrow0
10829      0,	// VSLRC:sub_dmr1_then_sub_dmrrow1
10830      0,	// VSLRC:sub_dmr1_then_sub_dmrrowp0
10831      0,	// VSLRC:sub_dmr1_then_sub_dmrrowp1
10832      0,	// VSLRC:sub_dmr1_then_sub_wacc_hi
10833      0,	// VSLRC:sub_dmr1_then_sub_wacc_lo
10834      0,	// VSLRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
10835      0,	// VSLRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
10836      0,	// VSLRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
10837      0,	// VSLRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
10838      0,	// VSLRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
10839      0,	// VSLRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
10840      0,	// VSLRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10841      0,	// VSLRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10842      0,	// VSLRC:sub_gp8_x1_then_sub_32
10843    },
10844    {	// VRRC_with_sub_64_in_SPILLTOVSRRC
10845      0,	// VRRC_with_sub_64_in_SPILLTOVSRRC:sub_32
10846      22,	// VRRC_with_sub_64_in_SPILLTOVSRRC:sub_64 -> SPILLTOVSRRC_and_VFRC
10847      0,	// VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr0
10848      0,	// VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1
10849      0,	// VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrow0
10850      0,	// VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrow1
10851      0,	// VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp0
10852      0,	// VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1
10853      0,	// VRRC_with_sub_64_in_SPILLTOVSRRC:sub_eq
10854      0,	// VRRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x0
10855      0,	// VRRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x1
10856      0,	// VRRC_with_sub_64_in_SPILLTOVSRRC:sub_gt
10857      0,	// VRRC_with_sub_64_in_SPILLTOVSRRC:sub_lt
10858      0,	// VRRC_with_sub_64_in_SPILLTOVSRRC:sub_pair0
10859      0,	// VRRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1
10860      0,	// VRRC_with_sub_64_in_SPILLTOVSRRC:sub_un
10861      0,	// VRRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx0
10862      0,	// VRRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1
10863      0,	// VRRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi
10864      0,	// VRRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_lo
10865      0,	// VRRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1_then_sub_64
10866      0,	// VRRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_64
10867      0,	// VRRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx0
10868      0,	// VRRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1
10869      0,	// VRRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1_then_sub_64
10870      0,	// VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow0
10871      0,	// VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow1
10872      0,	// VRRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow0
10873      0,	// VRRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow1
10874      0,	// VRRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp0
10875      0,	// VRRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1
10876      0,	// VRRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10877      0,	// VRRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10878      0,	// VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow0
10879      0,	// VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow1
10880      0,	// VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp0
10881      0,	// VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1
10882      0,	// VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi
10883      0,	// VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_lo
10884      0,	// VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
10885      0,	// VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
10886      0,	// VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
10887      0,	// VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
10888      0,	// VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
10889      0,	// VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
10890      0,	// VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10891      0,	// VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10892      0,	// VRRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x1_then_sub_32
10893    },
10894    {	// G8pRC
10895      2,	// G8pRC:sub_32 -> GPRC
10896      0,	// G8pRC:sub_64
10897      0,	// G8pRC:sub_dmr0
10898      0,	// G8pRC:sub_dmr1
10899      0,	// G8pRC:sub_dmrrow0
10900      0,	// G8pRC:sub_dmrrow1
10901      0,	// G8pRC:sub_dmrrowp0
10902      0,	// G8pRC:sub_dmrrowp1
10903      0,	// G8pRC:sub_eq
10904      14,	// G8pRC:sub_gp8_x0 -> G8RC
10905      17,	// G8pRC:sub_gp8_x1 -> G8RC_and_G8RC_NOX0
10906      0,	// G8pRC:sub_gt
10907      0,	// G8pRC:sub_lt
10908      0,	// G8pRC:sub_pair0
10909      0,	// G8pRC:sub_pair1
10910      0,	// G8pRC:sub_un
10911      0,	// G8pRC:sub_vsx0
10912      0,	// G8pRC:sub_vsx1
10913      0,	// G8pRC:sub_wacc_hi
10914      0,	// G8pRC:sub_wacc_lo
10915      0,	// G8pRC:sub_vsx1_then_sub_64
10916      0,	// G8pRC:sub_pair1_then_sub_64
10917      0,	// G8pRC:sub_pair1_then_sub_vsx0
10918      0,	// G8pRC:sub_pair1_then_sub_vsx1
10919      0,	// G8pRC:sub_pair1_then_sub_vsx1_then_sub_64
10920      0,	// G8pRC:sub_dmrrowp1_then_sub_dmrrow0
10921      0,	// G8pRC:sub_dmrrowp1_then_sub_dmrrow1
10922      0,	// G8pRC:sub_wacc_hi_then_sub_dmrrow0
10923      0,	// G8pRC:sub_wacc_hi_then_sub_dmrrow1
10924      0,	// G8pRC:sub_wacc_hi_then_sub_dmrrowp0
10925      0,	// G8pRC:sub_wacc_hi_then_sub_dmrrowp1
10926      0,	// G8pRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10927      0,	// G8pRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10928      0,	// G8pRC:sub_dmr1_then_sub_dmrrow0
10929      0,	// G8pRC:sub_dmr1_then_sub_dmrrow1
10930      0,	// G8pRC:sub_dmr1_then_sub_dmrrowp0
10931      0,	// G8pRC:sub_dmr1_then_sub_dmrrowp1
10932      0,	// G8pRC:sub_dmr1_then_sub_wacc_hi
10933      0,	// G8pRC:sub_dmr1_then_sub_wacc_lo
10934      0,	// G8pRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
10935      0,	// G8pRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
10936      0,	// G8pRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
10937      0,	// G8pRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
10938      0,	// G8pRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
10939      0,	// G8pRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
10940      0,	// G8pRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10941      0,	// G8pRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10942      4,	// G8pRC:sub_gp8_x1_then_sub_32 -> GPRC_and_GPRC_NOR0
10943    },
10944    {	// G8pRC_with_sub_32_in_GPRC_NOR0
10945      4,	// G8pRC_with_sub_32_in_GPRC_NOR0:sub_32 -> GPRC_and_GPRC_NOR0
10946      0,	// G8pRC_with_sub_32_in_GPRC_NOR0:sub_64
10947      0,	// G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr0
10948      0,	// G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1
10949      0,	// G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmrrow0
10950      0,	// G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmrrow1
10951      0,	// G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmrrowp0
10952      0,	// G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmrrowp1
10953      0,	// G8pRC_with_sub_32_in_GPRC_NOR0:sub_eq
10954      17,	// G8pRC_with_sub_32_in_GPRC_NOR0:sub_gp8_x0 -> G8RC_and_G8RC_NOX0
10955      17,	// G8pRC_with_sub_32_in_GPRC_NOR0:sub_gp8_x1 -> G8RC_and_G8RC_NOX0
10956      0,	// G8pRC_with_sub_32_in_GPRC_NOR0:sub_gt
10957      0,	// G8pRC_with_sub_32_in_GPRC_NOR0:sub_lt
10958      0,	// G8pRC_with_sub_32_in_GPRC_NOR0:sub_pair0
10959      0,	// G8pRC_with_sub_32_in_GPRC_NOR0:sub_pair1
10960      0,	// G8pRC_with_sub_32_in_GPRC_NOR0:sub_un
10961      0,	// G8pRC_with_sub_32_in_GPRC_NOR0:sub_vsx0
10962      0,	// G8pRC_with_sub_32_in_GPRC_NOR0:sub_vsx1
10963      0,	// G8pRC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi
10964      0,	// G8pRC_with_sub_32_in_GPRC_NOR0:sub_wacc_lo
10965      0,	// G8pRC_with_sub_32_in_GPRC_NOR0:sub_vsx1_then_sub_64
10966      0,	// G8pRC_with_sub_32_in_GPRC_NOR0:sub_pair1_then_sub_64
10967      0,	// G8pRC_with_sub_32_in_GPRC_NOR0:sub_pair1_then_sub_vsx0
10968      0,	// G8pRC_with_sub_32_in_GPRC_NOR0:sub_pair1_then_sub_vsx1
10969      0,	// G8pRC_with_sub_32_in_GPRC_NOR0:sub_pair1_then_sub_vsx1_then_sub_64
10970      0,	// G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmrrowp1_then_sub_dmrrow0
10971      0,	// G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmrrowp1_then_sub_dmrrow1
10972      0,	// G8pRC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrow0
10973      0,	// G8pRC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrow1
10974      0,	// G8pRC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp0
10975      0,	// G8pRC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp1
10976      0,	// G8pRC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10977      0,	// G8pRC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10978      0,	// G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_dmrrow0
10979      0,	// G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_dmrrow1
10980      0,	// G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_dmrrowp0
10981      0,	// G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_dmrrowp1
10982      0,	// G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi
10983      0,	// G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_lo
10984      0,	// G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
10985      0,	// G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
10986      0,	// G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
10987      0,	// G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
10988      0,	// G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
10989      0,	// G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
10990      0,	// G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10991      0,	// G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10992      4,	// G8pRC_with_sub_32_in_GPRC_NOR0:sub_gp8_x1_then_sub_32 -> GPRC_and_GPRC_NOR0
10993    },
10994    {	// VSLRC_with_sub_64_in_SPILLTOVSRRC
10995      0,	// VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_32
10996      23,	// VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_64 -> SPILLTOVSRRC_and_F4RC
10997      0,	// VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr0
10998      0,	// VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1
10999      0,	// VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrow0
11000      0,	// VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrow1
11001      0,	// VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp0
11002      0,	// VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1
11003      0,	// VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_eq
11004      0,	// VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x0
11005      0,	// VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x1
11006      0,	// VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_gt
11007      0,	// VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_lt
11008      0,	// VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_pair0
11009      0,	// VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1
11010      0,	// VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_un
11011      0,	// VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx0
11012      0,	// VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1
11013      0,	// VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi
11014      0,	// VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_lo
11015      0,	// VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1_then_sub_64
11016      0,	// VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_64
11017      0,	// VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx0
11018      0,	// VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1
11019      0,	// VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1_then_sub_64
11020      0,	// VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow0
11021      0,	// VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow1
11022      0,	// VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow0
11023      0,	// VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow1
11024      0,	// VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp0
11025      0,	// VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1
11026      0,	// VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11027      0,	// VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11028      0,	// VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow0
11029      0,	// VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow1
11030      0,	// VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp0
11031      0,	// VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1
11032      0,	// VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi
11033      0,	// VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_lo
11034      0,	// VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
11035      0,	// VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
11036      0,	// VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
11037      0,	// VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
11038      0,	// VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
11039      0,	// VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
11040      0,	// VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11041      0,	// VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11042      0,	// VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x1_then_sub_32
11043    },
11044    {	// DMRROWpRC
11045      0,	// DMRROWpRC:sub_32
11046      0,	// DMRROWpRC:sub_64
11047      0,	// DMRROWpRC:sub_dmr0
11048      0,	// DMRROWpRC:sub_dmr1
11049      26,	// DMRROWpRC:sub_dmrrow0 -> DMRROWRC
11050      26,	// DMRROWpRC:sub_dmrrow1 -> DMRROWRC
11051      0,	// DMRROWpRC:sub_dmrrowp0
11052      0,	// DMRROWpRC:sub_dmrrowp1
11053      0,	// DMRROWpRC:sub_eq
11054      0,	// DMRROWpRC:sub_gp8_x0
11055      0,	// DMRROWpRC:sub_gp8_x1
11056      0,	// DMRROWpRC:sub_gt
11057      0,	// DMRROWpRC:sub_lt
11058      0,	// DMRROWpRC:sub_pair0
11059      0,	// DMRROWpRC:sub_pair1
11060      0,	// DMRROWpRC:sub_un
11061      0,	// DMRROWpRC:sub_vsx0
11062      0,	// DMRROWpRC:sub_vsx1
11063      0,	// DMRROWpRC:sub_wacc_hi
11064      0,	// DMRROWpRC:sub_wacc_lo
11065      0,	// DMRROWpRC:sub_vsx1_then_sub_64
11066      0,	// DMRROWpRC:sub_pair1_then_sub_64
11067      0,	// DMRROWpRC:sub_pair1_then_sub_vsx0
11068      0,	// DMRROWpRC:sub_pair1_then_sub_vsx1
11069      0,	// DMRROWpRC:sub_pair1_then_sub_vsx1_then_sub_64
11070      0,	// DMRROWpRC:sub_dmrrowp1_then_sub_dmrrow0
11071      0,	// DMRROWpRC:sub_dmrrowp1_then_sub_dmrrow1
11072      0,	// DMRROWpRC:sub_wacc_hi_then_sub_dmrrow0
11073      0,	// DMRROWpRC:sub_wacc_hi_then_sub_dmrrow1
11074      0,	// DMRROWpRC:sub_wacc_hi_then_sub_dmrrowp0
11075      0,	// DMRROWpRC:sub_wacc_hi_then_sub_dmrrowp1
11076      0,	// DMRROWpRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11077      0,	// DMRROWpRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11078      0,	// DMRROWpRC:sub_dmr1_then_sub_dmrrow0
11079      0,	// DMRROWpRC:sub_dmr1_then_sub_dmrrow1
11080      0,	// DMRROWpRC:sub_dmr1_then_sub_dmrrowp0
11081      0,	// DMRROWpRC:sub_dmr1_then_sub_dmrrowp1
11082      0,	// DMRROWpRC:sub_dmr1_then_sub_wacc_hi
11083      0,	// DMRROWpRC:sub_dmr1_then_sub_wacc_lo
11084      0,	// DMRROWpRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
11085      0,	// DMRROWpRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
11086      0,	// DMRROWpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
11087      0,	// DMRROWpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
11088      0,	// DMRROWpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
11089      0,	// DMRROWpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
11090      0,	// DMRROWpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11091      0,	// DMRROWpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11092      0,	// DMRROWpRC:sub_gp8_x1_then_sub_32
11093    },
11094    {	// VSRpRC
11095      0,	// VSRpRC:sub_32
11096      13,	// VSRpRC:sub_64 -> VSFRC
11097      0,	// VSRpRC:sub_dmr0
11098      0,	// VSRpRC:sub_dmr1
11099      0,	// VSRpRC:sub_dmrrow0
11100      0,	// VSRpRC:sub_dmrrow1
11101      0,	// VSRpRC:sub_dmrrowp0
11102      0,	// VSRpRC:sub_dmrrowp1
11103      0,	// VSRpRC:sub_eq
11104      0,	// VSRpRC:sub_gp8_x0
11105      0,	// VSRpRC:sub_gp8_x1
11106      0,	// VSRpRC:sub_gt
11107      0,	// VSRpRC:sub_lt
11108      0,	// VSRpRC:sub_pair0
11109      0,	// VSRpRC:sub_pair1
11110      0,	// VSRpRC:sub_un
11111      27,	// VSRpRC:sub_vsx0 -> VSRC
11112      27,	// VSRpRC:sub_vsx1 -> VSRC
11113      0,	// VSRpRC:sub_wacc_hi
11114      0,	// VSRpRC:sub_wacc_lo
11115      13,	// VSRpRC:sub_vsx1_then_sub_64 -> VSFRC
11116      0,	// VSRpRC:sub_pair1_then_sub_64
11117      0,	// VSRpRC:sub_pair1_then_sub_vsx0
11118      0,	// VSRpRC:sub_pair1_then_sub_vsx1
11119      0,	// VSRpRC:sub_pair1_then_sub_vsx1_then_sub_64
11120      0,	// VSRpRC:sub_dmrrowp1_then_sub_dmrrow0
11121      0,	// VSRpRC:sub_dmrrowp1_then_sub_dmrrow1
11122      0,	// VSRpRC:sub_wacc_hi_then_sub_dmrrow0
11123      0,	// VSRpRC:sub_wacc_hi_then_sub_dmrrow1
11124      0,	// VSRpRC:sub_wacc_hi_then_sub_dmrrowp0
11125      0,	// VSRpRC:sub_wacc_hi_then_sub_dmrrowp1
11126      0,	// VSRpRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11127      0,	// VSRpRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11128      0,	// VSRpRC:sub_dmr1_then_sub_dmrrow0
11129      0,	// VSRpRC:sub_dmr1_then_sub_dmrrow1
11130      0,	// VSRpRC:sub_dmr1_then_sub_dmrrowp0
11131      0,	// VSRpRC:sub_dmr1_then_sub_dmrrowp1
11132      0,	// VSRpRC:sub_dmr1_then_sub_wacc_hi
11133      0,	// VSRpRC:sub_dmr1_then_sub_wacc_lo
11134      0,	// VSRpRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
11135      0,	// VSRpRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
11136      0,	// VSRpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
11137      0,	// VSRpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
11138      0,	// VSRpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
11139      0,	// VSRpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
11140      0,	// VSRpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11141      0,	// VSRpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11142      0,	// VSRpRC:sub_gp8_x1_then_sub_32
11143    },
11144    {	// VSRpRC_with_sub_64_in_SPILLTOVSRRC
11145      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_32
11146      16,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_64 -> SPILLTOVSRRC_and_VSFRC
11147      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr0
11148      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1
11149      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrow0
11150      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrow1
11151      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp0
11152      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1
11153      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_eq
11154      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x0
11155      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x1
11156      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_gt
11157      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_lt
11158      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_pair0
11159      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1
11160      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_un
11161      28,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx0 -> VSRC_with_sub_64_in_SPILLTOVSRRC
11162      28,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1 -> VSRC_with_sub_64_in_SPILLTOVSRRC
11163      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi
11164      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_lo
11165      16,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1_then_sub_64 -> SPILLTOVSRRC_and_VSFRC
11166      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_64
11167      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx0
11168      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1
11169      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1_then_sub_64
11170      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow0
11171      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow1
11172      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow0
11173      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow1
11174      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp0
11175      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1
11176      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11177      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11178      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow0
11179      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow1
11180      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp0
11181      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1
11182      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi
11183      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_lo
11184      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
11185      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
11186      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
11187      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
11188      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
11189      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
11190      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11191      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11192      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x1_then_sub_32
11193    },
11194    {	// VSRpRC_with_sub_64_in_F4RC
11195      0,	// VSRpRC_with_sub_64_in_F4RC:sub_32
11196      18,	// VSRpRC_with_sub_64_in_F4RC:sub_64 -> F8RC
11197      0,	// VSRpRC_with_sub_64_in_F4RC:sub_dmr0
11198      0,	// VSRpRC_with_sub_64_in_F4RC:sub_dmr1
11199      0,	// VSRpRC_with_sub_64_in_F4RC:sub_dmrrow0
11200      0,	// VSRpRC_with_sub_64_in_F4RC:sub_dmrrow1
11201      0,	// VSRpRC_with_sub_64_in_F4RC:sub_dmrrowp0
11202      0,	// VSRpRC_with_sub_64_in_F4RC:sub_dmrrowp1
11203      0,	// VSRpRC_with_sub_64_in_F4RC:sub_eq
11204      0,	// VSRpRC_with_sub_64_in_F4RC:sub_gp8_x0
11205      0,	// VSRpRC_with_sub_64_in_F4RC:sub_gp8_x1
11206      0,	// VSRpRC_with_sub_64_in_F4RC:sub_gt
11207      0,	// VSRpRC_with_sub_64_in_F4RC:sub_lt
11208      0,	// VSRpRC_with_sub_64_in_F4RC:sub_pair0
11209      0,	// VSRpRC_with_sub_64_in_F4RC:sub_pair1
11210      0,	// VSRpRC_with_sub_64_in_F4RC:sub_un
11211      30,	// VSRpRC_with_sub_64_in_F4RC:sub_vsx0 -> VSLRC
11212      30,	// VSRpRC_with_sub_64_in_F4RC:sub_vsx1 -> VSLRC
11213      0,	// VSRpRC_with_sub_64_in_F4RC:sub_wacc_hi
11214      0,	// VSRpRC_with_sub_64_in_F4RC:sub_wacc_lo
11215      18,	// VSRpRC_with_sub_64_in_F4RC:sub_vsx1_then_sub_64 -> F8RC
11216      0,	// VSRpRC_with_sub_64_in_F4RC:sub_pair1_then_sub_64
11217      0,	// VSRpRC_with_sub_64_in_F4RC:sub_pair1_then_sub_vsx0
11218      0,	// VSRpRC_with_sub_64_in_F4RC:sub_pair1_then_sub_vsx1
11219      0,	// VSRpRC_with_sub_64_in_F4RC:sub_pair1_then_sub_vsx1_then_sub_64
11220      0,	// VSRpRC_with_sub_64_in_F4RC:sub_dmrrowp1_then_sub_dmrrow0
11221      0,	// VSRpRC_with_sub_64_in_F4RC:sub_dmrrowp1_then_sub_dmrrow1
11222      0,	// VSRpRC_with_sub_64_in_F4RC:sub_wacc_hi_then_sub_dmrrow0
11223      0,	// VSRpRC_with_sub_64_in_F4RC:sub_wacc_hi_then_sub_dmrrow1
11224      0,	// VSRpRC_with_sub_64_in_F4RC:sub_wacc_hi_then_sub_dmrrowp0
11225      0,	// VSRpRC_with_sub_64_in_F4RC:sub_wacc_hi_then_sub_dmrrowp1
11226      0,	// VSRpRC_with_sub_64_in_F4RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11227      0,	// VSRpRC_with_sub_64_in_F4RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11228      0,	// VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_dmrrow0
11229      0,	// VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_dmrrow1
11230      0,	// VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_dmrrowp0
11231      0,	// VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_dmrrowp1
11232      0,	// VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_wacc_hi
11233      0,	// VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_wacc_lo
11234      0,	// VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
11235      0,	// VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
11236      0,	// VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
11237      0,	// VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
11238      0,	// VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
11239      0,	// VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
11240      0,	// VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11241      0,	// VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11242      0,	// VSRpRC_with_sub_64_in_F4RC:sub_gp8_x1_then_sub_32
11243    },
11244    {	// VSRpRC_with_sub_64_in_VFRC
11245      0,	// VSRpRC_with_sub_64_in_VFRC:sub_32
11246      20,	// VSRpRC_with_sub_64_in_VFRC:sub_64 -> VFRC
11247      0,	// VSRpRC_with_sub_64_in_VFRC:sub_dmr0
11248      0,	// VSRpRC_with_sub_64_in_VFRC:sub_dmr1
11249      0,	// VSRpRC_with_sub_64_in_VFRC:sub_dmrrow0
11250      0,	// VSRpRC_with_sub_64_in_VFRC:sub_dmrrow1
11251      0,	// VSRpRC_with_sub_64_in_VFRC:sub_dmrrowp0
11252      0,	// VSRpRC_with_sub_64_in_VFRC:sub_dmrrowp1
11253      0,	// VSRpRC_with_sub_64_in_VFRC:sub_eq
11254      0,	// VSRpRC_with_sub_64_in_VFRC:sub_gp8_x0
11255      0,	// VSRpRC_with_sub_64_in_VFRC:sub_gp8_x1
11256      0,	// VSRpRC_with_sub_64_in_VFRC:sub_gt
11257      0,	// VSRpRC_with_sub_64_in_VFRC:sub_lt
11258      0,	// VSRpRC_with_sub_64_in_VFRC:sub_pair0
11259      0,	// VSRpRC_with_sub_64_in_VFRC:sub_pair1
11260      0,	// VSRpRC_with_sub_64_in_VFRC:sub_un
11261      29,	// VSRpRC_with_sub_64_in_VFRC:sub_vsx0 -> VRRC
11262      29,	// VSRpRC_with_sub_64_in_VFRC:sub_vsx1 -> VRRC
11263      0,	// VSRpRC_with_sub_64_in_VFRC:sub_wacc_hi
11264      0,	// VSRpRC_with_sub_64_in_VFRC:sub_wacc_lo
11265      20,	// VSRpRC_with_sub_64_in_VFRC:sub_vsx1_then_sub_64 -> VFRC
11266      0,	// VSRpRC_with_sub_64_in_VFRC:sub_pair1_then_sub_64
11267      0,	// VSRpRC_with_sub_64_in_VFRC:sub_pair1_then_sub_vsx0
11268      0,	// VSRpRC_with_sub_64_in_VFRC:sub_pair1_then_sub_vsx1
11269      0,	// VSRpRC_with_sub_64_in_VFRC:sub_pair1_then_sub_vsx1_then_sub_64
11270      0,	// VSRpRC_with_sub_64_in_VFRC:sub_dmrrowp1_then_sub_dmrrow0
11271      0,	// VSRpRC_with_sub_64_in_VFRC:sub_dmrrowp1_then_sub_dmrrow1
11272      0,	// VSRpRC_with_sub_64_in_VFRC:sub_wacc_hi_then_sub_dmrrow0
11273      0,	// VSRpRC_with_sub_64_in_VFRC:sub_wacc_hi_then_sub_dmrrow1
11274      0,	// VSRpRC_with_sub_64_in_VFRC:sub_wacc_hi_then_sub_dmrrowp0
11275      0,	// VSRpRC_with_sub_64_in_VFRC:sub_wacc_hi_then_sub_dmrrowp1
11276      0,	// VSRpRC_with_sub_64_in_VFRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11277      0,	// VSRpRC_with_sub_64_in_VFRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11278      0,	// VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_dmrrow0
11279      0,	// VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_dmrrow1
11280      0,	// VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_dmrrowp0
11281      0,	// VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_dmrrowp1
11282      0,	// VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_wacc_hi
11283      0,	// VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_wacc_lo
11284      0,	// VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
11285      0,	// VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
11286      0,	// VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
11287      0,	// VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
11288      0,	// VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
11289      0,	// VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
11290      0,	// VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11291      0,	// VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11292      0,	// VSRpRC_with_sub_64_in_VFRC:sub_gp8_x1_then_sub_32
11293    },
11294    {	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC
11295      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_32
11296      22,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_64 -> SPILLTOVSRRC_and_VFRC
11297      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr0
11298      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1
11299      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmrrow0
11300      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmrrow1
11301      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmrrowp0
11302      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmrrowp1
11303      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_eq
11304      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_gp8_x0
11305      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_gp8_x1
11306      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_gt
11307      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_lt
11308      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_pair0
11309      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_pair1
11310      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_un
11311      31,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_vsx0 -> VRRC_with_sub_64_in_SPILLTOVSRRC
11312      31,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_vsx1 -> VRRC_with_sub_64_in_SPILLTOVSRRC
11313      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_wacc_hi
11314      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_wacc_lo
11315      22,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_vsx1_then_sub_64 -> SPILLTOVSRRC_and_VFRC
11316      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_pair1_then_sub_64
11317      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_pair1_then_sub_vsx0
11318      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_pair1_then_sub_vsx1
11319      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_pair1_then_sub_vsx1_then_sub_64
11320      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmrrowp1_then_sub_dmrrow0
11321      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmrrowp1_then_sub_dmrrow1
11322      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_wacc_hi_then_sub_dmrrow0
11323      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_wacc_hi_then_sub_dmrrow1
11324      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_wacc_hi_then_sub_dmrrowp0
11325      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_wacc_hi_then_sub_dmrrowp1
11326      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11327      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11328      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_dmrrow0
11329      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_dmrrow1
11330      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_dmrrowp0
11331      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_dmrrowp1
11332      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi
11333      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_lo
11334      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
11335      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
11336      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
11337      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
11338      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
11339      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
11340      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11341      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11342      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_gp8_x1_then_sub_32
11343    },
11344    {	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
11345      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_32
11346      23,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_64 -> SPILLTOVSRRC_and_F4RC
11347      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr0
11348      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1
11349      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmrrow0
11350      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmrrow1
11351      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmrrowp0
11352      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmrrowp1
11353      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_eq
11354      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_gp8_x0
11355      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_gp8_x1
11356      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_gt
11357      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_lt
11358      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_pair0
11359      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_pair1
11360      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_un
11361      34,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_vsx0 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
11362      34,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_vsx1 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
11363      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_wacc_hi
11364      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_wacc_lo
11365      23,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_vsx1_then_sub_64 -> SPILLTOVSRRC_and_F4RC
11366      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_pair1_then_sub_64
11367      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_pair1_then_sub_vsx0
11368      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_pair1_then_sub_vsx1
11369      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_pair1_then_sub_vsx1_then_sub_64
11370      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmrrowp1_then_sub_dmrrow0
11371      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmrrowp1_then_sub_dmrrow1
11372      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_wacc_hi_then_sub_dmrrow0
11373      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_wacc_hi_then_sub_dmrrow1
11374      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_wacc_hi_then_sub_dmrrowp0
11375      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_wacc_hi_then_sub_dmrrowp1
11376      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11377      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11378      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_dmrrow0
11379      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_dmrrow1
11380      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_dmrrowp0
11381      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_dmrrowp1
11382      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi
11383      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_lo
11384      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
11385      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
11386      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
11387      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
11388      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
11389      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
11390      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11391      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11392      0,	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_gp8_x1_then_sub_32
11393    },
11394    {	// ACCRC
11395      0,	// ACCRC:sub_32
11396      18,	// ACCRC:sub_64 -> F8RC
11397      0,	// ACCRC:sub_dmr0
11398      0,	// ACCRC:sub_dmr1
11399      0,	// ACCRC:sub_dmrrow0
11400      0,	// ACCRC:sub_dmrrow1
11401      0,	// ACCRC:sub_dmrrowp0
11402      0,	// ACCRC:sub_dmrrowp1
11403      0,	// ACCRC:sub_eq
11404      0,	// ACCRC:sub_gp8_x0
11405      0,	// ACCRC:sub_gp8_x1
11406      0,	// ACCRC:sub_gt
11407      0,	// ACCRC:sub_lt
11408      38,	// ACCRC:sub_pair0 -> VSRpRC_with_sub_64_in_F4RC
11409      38,	// ACCRC:sub_pair1 -> VSRpRC_with_sub_64_in_F4RC
11410      0,	// ACCRC:sub_un
11411      30,	// ACCRC:sub_vsx0 -> VSLRC
11412      30,	// ACCRC:sub_vsx1 -> VSLRC
11413      0,	// ACCRC:sub_wacc_hi
11414      0,	// ACCRC:sub_wacc_lo
11415      18,	// ACCRC:sub_vsx1_then_sub_64 -> F8RC
11416      18,	// ACCRC:sub_pair1_then_sub_64 -> F8RC
11417      30,	// ACCRC:sub_pair1_then_sub_vsx0 -> VSLRC
11418      30,	// ACCRC:sub_pair1_then_sub_vsx1 -> VSLRC
11419      18,	// ACCRC:sub_pair1_then_sub_vsx1_then_sub_64 -> F8RC
11420      0,	// ACCRC:sub_dmrrowp1_then_sub_dmrrow0
11421      0,	// ACCRC:sub_dmrrowp1_then_sub_dmrrow1
11422      0,	// ACCRC:sub_wacc_hi_then_sub_dmrrow0
11423      0,	// ACCRC:sub_wacc_hi_then_sub_dmrrow1
11424      0,	// ACCRC:sub_wacc_hi_then_sub_dmrrowp0
11425      0,	// ACCRC:sub_wacc_hi_then_sub_dmrrowp1
11426      0,	// ACCRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11427      0,	// ACCRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11428      0,	// ACCRC:sub_dmr1_then_sub_dmrrow0
11429      0,	// ACCRC:sub_dmr1_then_sub_dmrrow1
11430      0,	// ACCRC:sub_dmr1_then_sub_dmrrowp0
11431      0,	// ACCRC:sub_dmr1_then_sub_dmrrowp1
11432      0,	// ACCRC:sub_dmr1_then_sub_wacc_hi
11433      0,	// ACCRC:sub_dmr1_then_sub_wacc_lo
11434      0,	// ACCRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
11435      0,	// ACCRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
11436      0,	// ACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
11437      0,	// ACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
11438      0,	// ACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
11439      0,	// ACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
11440      0,	// ACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11441      0,	// ACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11442      0,	// ACCRC:sub_gp8_x1_then_sub_32
11443    },
11444    {	// UACCRC
11445      0,	// UACCRC:sub_32
11446      18,	// UACCRC:sub_64 -> F8RC
11447      0,	// UACCRC:sub_dmr0
11448      0,	// UACCRC:sub_dmr1
11449      0,	// UACCRC:sub_dmrrow0
11450      0,	// UACCRC:sub_dmrrow1
11451      0,	// UACCRC:sub_dmrrowp0
11452      0,	// UACCRC:sub_dmrrowp1
11453      0,	// UACCRC:sub_eq
11454      0,	// UACCRC:sub_gp8_x0
11455      0,	// UACCRC:sub_gp8_x1
11456      0,	// UACCRC:sub_gt
11457      0,	// UACCRC:sub_lt
11458      38,	// UACCRC:sub_pair0 -> VSRpRC_with_sub_64_in_F4RC
11459      38,	// UACCRC:sub_pair1 -> VSRpRC_with_sub_64_in_F4RC
11460      0,	// UACCRC:sub_un
11461      30,	// UACCRC:sub_vsx0 -> VSLRC
11462      30,	// UACCRC:sub_vsx1 -> VSLRC
11463      0,	// UACCRC:sub_wacc_hi
11464      0,	// UACCRC:sub_wacc_lo
11465      18,	// UACCRC:sub_vsx1_then_sub_64 -> F8RC
11466      18,	// UACCRC:sub_pair1_then_sub_64 -> F8RC
11467      30,	// UACCRC:sub_pair1_then_sub_vsx0 -> VSLRC
11468      30,	// UACCRC:sub_pair1_then_sub_vsx1 -> VSLRC
11469      18,	// UACCRC:sub_pair1_then_sub_vsx1_then_sub_64 -> F8RC
11470      0,	// UACCRC:sub_dmrrowp1_then_sub_dmrrow0
11471      0,	// UACCRC:sub_dmrrowp1_then_sub_dmrrow1
11472      0,	// UACCRC:sub_wacc_hi_then_sub_dmrrow0
11473      0,	// UACCRC:sub_wacc_hi_then_sub_dmrrow1
11474      0,	// UACCRC:sub_wacc_hi_then_sub_dmrrowp0
11475      0,	// UACCRC:sub_wacc_hi_then_sub_dmrrowp1
11476      0,	// UACCRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11477      0,	// UACCRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11478      0,	// UACCRC:sub_dmr1_then_sub_dmrrow0
11479      0,	// UACCRC:sub_dmr1_then_sub_dmrrow1
11480      0,	// UACCRC:sub_dmr1_then_sub_dmrrowp0
11481      0,	// UACCRC:sub_dmr1_then_sub_dmrrowp1
11482      0,	// UACCRC:sub_dmr1_then_sub_wacc_hi
11483      0,	// UACCRC:sub_dmr1_then_sub_wacc_lo
11484      0,	// UACCRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
11485      0,	// UACCRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
11486      0,	// UACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
11487      0,	// UACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
11488      0,	// UACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
11489      0,	// UACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
11490      0,	// UACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11491      0,	// UACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11492      0,	// UACCRC:sub_gp8_x1_then_sub_32
11493    },
11494    {	// WACCRC
11495      0,	// WACCRC:sub_32
11496      0,	// WACCRC:sub_64
11497      0,	// WACCRC:sub_dmr0
11498      0,	// WACCRC:sub_dmr1
11499      26,	// WACCRC:sub_dmrrow0 -> DMRROWRC
11500      26,	// WACCRC:sub_dmrrow1 -> DMRROWRC
11501      35,	// WACCRC:sub_dmrrowp0 -> DMRROWpRC
11502      35,	// WACCRC:sub_dmrrowp1 -> DMRROWpRC
11503      0,	// WACCRC:sub_eq
11504      0,	// WACCRC:sub_gp8_x0
11505      0,	// WACCRC:sub_gp8_x1
11506      0,	// WACCRC:sub_gt
11507      0,	// WACCRC:sub_lt
11508      0,	// WACCRC:sub_pair0
11509      0,	// WACCRC:sub_pair1
11510      0,	// WACCRC:sub_un
11511      0,	// WACCRC:sub_vsx0
11512      0,	// WACCRC:sub_vsx1
11513      0,	// WACCRC:sub_wacc_hi
11514      0,	// WACCRC:sub_wacc_lo
11515      0,	// WACCRC:sub_vsx1_then_sub_64
11516      0,	// WACCRC:sub_pair1_then_sub_64
11517      0,	// WACCRC:sub_pair1_then_sub_vsx0
11518      0,	// WACCRC:sub_pair1_then_sub_vsx1
11519      0,	// WACCRC:sub_pair1_then_sub_vsx1_then_sub_64
11520      26,	// WACCRC:sub_dmrrowp1_then_sub_dmrrow0 -> DMRROWRC
11521      26,	// WACCRC:sub_dmrrowp1_then_sub_dmrrow1 -> DMRROWRC
11522      0,	// WACCRC:sub_wacc_hi_then_sub_dmrrow0
11523      0,	// WACCRC:sub_wacc_hi_then_sub_dmrrow1
11524      0,	// WACCRC:sub_wacc_hi_then_sub_dmrrowp0
11525      0,	// WACCRC:sub_wacc_hi_then_sub_dmrrowp1
11526      0,	// WACCRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11527      0,	// WACCRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11528      0,	// WACCRC:sub_dmr1_then_sub_dmrrow0
11529      0,	// WACCRC:sub_dmr1_then_sub_dmrrow1
11530      0,	// WACCRC:sub_dmr1_then_sub_dmrrowp0
11531      0,	// WACCRC:sub_dmr1_then_sub_dmrrowp1
11532      0,	// WACCRC:sub_dmr1_then_sub_wacc_hi
11533      0,	// WACCRC:sub_dmr1_then_sub_wacc_lo
11534      0,	// WACCRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
11535      0,	// WACCRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
11536      0,	// WACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
11537      0,	// WACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
11538      0,	// WACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
11539      0,	// WACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
11540      0,	// WACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11541      0,	// WACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11542      0,	// WACCRC:sub_gp8_x1_then_sub_32
11543    },
11544    {	// WACC_HIRC
11545      0,	// WACC_HIRC:sub_32
11546      0,	// WACC_HIRC:sub_64
11547      0,	// WACC_HIRC:sub_dmr0
11548      0,	// WACC_HIRC:sub_dmr1
11549      26,	// WACC_HIRC:sub_dmrrow0 -> DMRROWRC
11550      26,	// WACC_HIRC:sub_dmrrow1 -> DMRROWRC
11551      35,	// WACC_HIRC:sub_dmrrowp0 -> DMRROWpRC
11552      35,	// WACC_HIRC:sub_dmrrowp1 -> DMRROWpRC
11553      0,	// WACC_HIRC:sub_eq
11554      0,	// WACC_HIRC:sub_gp8_x0
11555      0,	// WACC_HIRC:sub_gp8_x1
11556      0,	// WACC_HIRC:sub_gt
11557      0,	// WACC_HIRC:sub_lt
11558      0,	// WACC_HIRC:sub_pair0
11559      0,	// WACC_HIRC:sub_pair1
11560      0,	// WACC_HIRC:sub_un
11561      0,	// WACC_HIRC:sub_vsx0
11562      0,	// WACC_HIRC:sub_vsx1
11563      0,	// WACC_HIRC:sub_wacc_hi
11564      0,	// WACC_HIRC:sub_wacc_lo
11565      0,	// WACC_HIRC:sub_vsx1_then_sub_64
11566      0,	// WACC_HIRC:sub_pair1_then_sub_64
11567      0,	// WACC_HIRC:sub_pair1_then_sub_vsx0
11568      0,	// WACC_HIRC:sub_pair1_then_sub_vsx1
11569      0,	// WACC_HIRC:sub_pair1_then_sub_vsx1_then_sub_64
11570      26,	// WACC_HIRC:sub_dmrrowp1_then_sub_dmrrow0 -> DMRROWRC
11571      26,	// WACC_HIRC:sub_dmrrowp1_then_sub_dmrrow1 -> DMRROWRC
11572      0,	// WACC_HIRC:sub_wacc_hi_then_sub_dmrrow0
11573      0,	// WACC_HIRC:sub_wacc_hi_then_sub_dmrrow1
11574      0,	// WACC_HIRC:sub_wacc_hi_then_sub_dmrrowp0
11575      0,	// WACC_HIRC:sub_wacc_hi_then_sub_dmrrowp1
11576      0,	// WACC_HIRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11577      0,	// WACC_HIRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11578      0,	// WACC_HIRC:sub_dmr1_then_sub_dmrrow0
11579      0,	// WACC_HIRC:sub_dmr1_then_sub_dmrrow1
11580      0,	// WACC_HIRC:sub_dmr1_then_sub_dmrrowp0
11581      0,	// WACC_HIRC:sub_dmr1_then_sub_dmrrowp1
11582      0,	// WACC_HIRC:sub_dmr1_then_sub_wacc_hi
11583      0,	// WACC_HIRC:sub_dmr1_then_sub_wacc_lo
11584      0,	// WACC_HIRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
11585      0,	// WACC_HIRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
11586      0,	// WACC_HIRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
11587      0,	// WACC_HIRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
11588      0,	// WACC_HIRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
11589      0,	// WACC_HIRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
11590      0,	// WACC_HIRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11591      0,	// WACC_HIRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11592      0,	// WACC_HIRC:sub_gp8_x1_then_sub_32
11593    },
11594    {	// ACCRC_with_sub_64_in_SPILLTOVSRRC
11595      0,	// ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_32
11596      23,	// ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_64 -> SPILLTOVSRRC_and_F4RC
11597      0,	// ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr0
11598      0,	// ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1
11599      0,	// ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrow0
11600      0,	// ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrow1
11601      0,	// ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp0
11602      0,	// ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1
11603      0,	// ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_eq
11604      0,	// ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x0
11605      0,	// ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x1
11606      0,	// ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_gt
11607      0,	// ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_lt
11608      41,	// ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_pair0 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
11609      38,	// ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1 -> VSRpRC_with_sub_64_in_F4RC
11610      0,	// ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_un
11611      34,	// ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx0 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
11612      34,	// ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
11613      0,	// ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi
11614      0,	// ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_lo
11615      23,	// ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1_then_sub_64 -> SPILLTOVSRRC_and_F4RC
11616      18,	// ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_64 -> F8RC
11617      30,	// ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx0 -> VSLRC
11618      30,	// ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1 -> VSLRC
11619      18,	// ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1_then_sub_64 -> F8RC
11620      0,	// ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow0
11621      0,	// ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow1
11622      0,	// ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow0
11623      0,	// ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow1
11624      0,	// ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp0
11625      0,	// ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1
11626      0,	// ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11627      0,	// ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11628      0,	// ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow0
11629      0,	// ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow1
11630      0,	// ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp0
11631      0,	// ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1
11632      0,	// ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi
11633      0,	// ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_lo
11634      0,	// ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
11635      0,	// ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
11636      0,	// ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
11637      0,	// ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
11638      0,	// ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
11639      0,	// ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
11640      0,	// ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11641      0,	// ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11642      0,	// ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x1_then_sub_32
11643    },
11644    {	// UACCRC_with_sub_64_in_SPILLTOVSRRC
11645      0,	// UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_32
11646      23,	// UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_64 -> SPILLTOVSRRC_and_F4RC
11647      0,	// UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr0
11648      0,	// UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1
11649      0,	// UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrow0
11650      0,	// UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrow1
11651      0,	// UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp0
11652      0,	// UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1
11653      0,	// UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_eq
11654      0,	// UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x0
11655      0,	// UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x1
11656      0,	// UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_gt
11657      0,	// UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_lt
11658      41,	// UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_pair0 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
11659      38,	// UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1 -> VSRpRC_with_sub_64_in_F4RC
11660      0,	// UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_un
11661      34,	// UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx0 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
11662      34,	// UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
11663      0,	// UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi
11664      0,	// UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_lo
11665      23,	// UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1_then_sub_64 -> SPILLTOVSRRC_and_F4RC
11666      18,	// UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_64 -> F8RC
11667      30,	// UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx0 -> VSLRC
11668      30,	// UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1 -> VSLRC
11669      18,	// UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1_then_sub_64 -> F8RC
11670      0,	// UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow0
11671      0,	// UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow1
11672      0,	// UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow0
11673      0,	// UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow1
11674      0,	// UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp0
11675      0,	// UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1
11676      0,	// UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11677      0,	// UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11678      0,	// UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow0
11679      0,	// UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow1
11680      0,	// UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp0
11681      0,	// UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1
11682      0,	// UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi
11683      0,	// UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_lo
11684      0,	// UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
11685      0,	// UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
11686      0,	// UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
11687      0,	// UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
11688      0,	// UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
11689      0,	// UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
11690      0,	// UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11691      0,	// UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11692      0,	// UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x1_then_sub_32
11693    },
11694    {	// ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
11695      0,	// ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_32
11696      23,	// ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_64 -> SPILLTOVSRRC_and_F4RC
11697      0,	// ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr0
11698      0,	// ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1
11699      0,	// ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmrrow0
11700      0,	// ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmrrow1
11701      0,	// ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmrrowp0
11702      0,	// ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1
11703      0,	// ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_eq
11704      0,	// ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_gp8_x0
11705      0,	// ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_gp8_x1
11706      0,	// ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_gt
11707      0,	// ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_lt
11708      41,	// ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_pair0 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
11709      41,	// ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_pair1 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
11710      0,	// ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_un
11711      34,	// ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_vsx0 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
11712      34,	// ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_vsx1 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
11713      0,	// ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi
11714      0,	// ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_lo
11715      23,	// ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_vsx1_then_sub_64 -> SPILLTOVSRRC_and_F4RC
11716      23,	// ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_64 -> SPILLTOVSRRC_and_F4RC
11717      34,	// ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx0 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
11718      34,	// ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
11719      23,	// ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1_then_sub_64 -> SPILLTOVSRRC_and_F4RC
11720      0,	// ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow0
11721      0,	// ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow1
11722      0,	// ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow0
11723      0,	// ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow1
11724      0,	// ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp0
11725      0,	// ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1
11726      0,	// ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11727      0,	// ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11728      0,	// ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow0
11729      0,	// ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow1
11730      0,	// ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp0
11731      0,	// ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1
11732      0,	// ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi
11733      0,	// ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_lo
11734      0,	// ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
11735      0,	// ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
11736      0,	// ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
11737      0,	// ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
11738      0,	// ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
11739      0,	// ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
11740      0,	// ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11741      0,	// ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11742      0,	// ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_gp8_x1_then_sub_32
11743    },
11744    {	// UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
11745      0,	// UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_32
11746      23,	// UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_64 -> SPILLTOVSRRC_and_F4RC
11747      0,	// UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr0
11748      0,	// UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1
11749      0,	// UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmrrow0
11750      0,	// UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmrrow1
11751      0,	// UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmrrowp0
11752      0,	// UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1
11753      0,	// UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_eq
11754      0,	// UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_gp8_x0
11755      0,	// UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_gp8_x1
11756      0,	// UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_gt
11757      0,	// UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_lt
11758      41,	// UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_pair0 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
11759      41,	// UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_pair1 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
11760      0,	// UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_un
11761      34,	// UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_vsx0 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
11762      34,	// UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_vsx1 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
11763      0,	// UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi
11764      0,	// UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_lo
11765      23,	// UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_vsx1_then_sub_64 -> SPILLTOVSRRC_and_F4RC
11766      23,	// UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_64 -> SPILLTOVSRRC_and_F4RC
11767      34,	// UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx0 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
11768      34,	// UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
11769      23,	// UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1_then_sub_64 -> SPILLTOVSRRC_and_F4RC
11770      0,	// UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow0
11771      0,	// UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow1
11772      0,	// UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow0
11773      0,	// UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow1
11774      0,	// UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp0
11775      0,	// UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1
11776      0,	// UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11777      0,	// UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11778      0,	// UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow0
11779      0,	// UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow1
11780      0,	// UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp0
11781      0,	// UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1
11782      0,	// UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi
11783      0,	// UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_lo
11784      0,	// UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
11785      0,	// UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
11786      0,	// UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
11787      0,	// UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
11788      0,	// UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
11789      0,	// UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
11790      0,	// UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11791      0,	// UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11792      0,	// UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_gp8_x1_then_sub_32
11793    },
11794    {	// DMRRC
11795      0,	// DMRRC:sub_32
11796      0,	// DMRRC:sub_64
11797      0,	// DMRRC:sub_dmr0
11798      0,	// DMRRC:sub_dmr1
11799      26,	// DMRRC:sub_dmrrow0 -> DMRROWRC
11800      26,	// DMRRC:sub_dmrrow1 -> DMRROWRC
11801      35,	// DMRRC:sub_dmrrowp0 -> DMRROWpRC
11802      35,	// DMRRC:sub_dmrrowp1 -> DMRROWpRC
11803      0,	// DMRRC:sub_eq
11804      0,	// DMRRC:sub_gp8_x0
11805      0,	// DMRRC:sub_gp8_x1
11806      0,	// DMRRC:sub_gt
11807      0,	// DMRRC:sub_lt
11808      0,	// DMRRC:sub_pair0
11809      0,	// DMRRC:sub_pair1
11810      0,	// DMRRC:sub_un
11811      0,	// DMRRC:sub_vsx0
11812      0,	// DMRRC:sub_vsx1
11813      45,	// DMRRC:sub_wacc_hi -> WACC_HIRC
11814      44,	// DMRRC:sub_wacc_lo -> WACCRC
11815      0,	// DMRRC:sub_vsx1_then_sub_64
11816      0,	// DMRRC:sub_pair1_then_sub_64
11817      0,	// DMRRC:sub_pair1_then_sub_vsx0
11818      0,	// DMRRC:sub_pair1_then_sub_vsx1
11819      0,	// DMRRC:sub_pair1_then_sub_vsx1_then_sub_64
11820      26,	// DMRRC:sub_dmrrowp1_then_sub_dmrrow0 -> DMRROWRC
11821      26,	// DMRRC:sub_dmrrowp1_then_sub_dmrrow1 -> DMRROWRC
11822      26,	// DMRRC:sub_wacc_hi_then_sub_dmrrow0 -> DMRROWRC
11823      26,	// DMRRC:sub_wacc_hi_then_sub_dmrrow1 -> DMRROWRC
11824      35,	// DMRRC:sub_wacc_hi_then_sub_dmrrowp0 -> DMRROWpRC
11825      35,	// DMRRC:sub_wacc_hi_then_sub_dmrrowp1 -> DMRROWpRC
11826      26,	// DMRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0 -> DMRROWRC
11827      26,	// DMRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1 -> DMRROWRC
11828      0,	// DMRRC:sub_dmr1_then_sub_dmrrow0
11829      0,	// DMRRC:sub_dmr1_then_sub_dmrrow1
11830      0,	// DMRRC:sub_dmr1_then_sub_dmrrowp0
11831      0,	// DMRRC:sub_dmr1_then_sub_dmrrowp1
11832      0,	// DMRRC:sub_dmr1_then_sub_wacc_hi
11833      0,	// DMRRC:sub_dmr1_then_sub_wacc_lo
11834      0,	// DMRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
11835      0,	// DMRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
11836      0,	// DMRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
11837      0,	// DMRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
11838      0,	// DMRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
11839      0,	// DMRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
11840      0,	// DMRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11841      0,	// DMRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11842      0,	// DMRRC:sub_gp8_x1_then_sub_32
11843    },
11844    {	// DMRpRC
11845      0,	// DMRpRC:sub_32
11846      0,	// DMRpRC:sub_64
11847      50,	// DMRpRC:sub_dmr0 -> DMRRC
11848      50,	// DMRpRC:sub_dmr1 -> DMRRC
11849      26,	// DMRpRC:sub_dmrrow0 -> DMRROWRC
11850      26,	// DMRpRC:sub_dmrrow1 -> DMRROWRC
11851      35,	// DMRpRC:sub_dmrrowp0 -> DMRROWpRC
11852      35,	// DMRpRC:sub_dmrrowp1 -> DMRROWpRC
11853      0,	// DMRpRC:sub_eq
11854      0,	// DMRpRC:sub_gp8_x0
11855      0,	// DMRpRC:sub_gp8_x1
11856      0,	// DMRpRC:sub_gt
11857      0,	// DMRpRC:sub_lt
11858      0,	// DMRpRC:sub_pair0
11859      0,	// DMRpRC:sub_pair1
11860      0,	// DMRpRC:sub_un
11861      0,	// DMRpRC:sub_vsx0
11862      0,	// DMRpRC:sub_vsx1
11863      45,	// DMRpRC:sub_wacc_hi -> WACC_HIRC
11864      44,	// DMRpRC:sub_wacc_lo -> WACCRC
11865      0,	// DMRpRC:sub_vsx1_then_sub_64
11866      0,	// DMRpRC:sub_pair1_then_sub_64
11867      0,	// DMRpRC:sub_pair1_then_sub_vsx0
11868      0,	// DMRpRC:sub_pair1_then_sub_vsx1
11869      0,	// DMRpRC:sub_pair1_then_sub_vsx1_then_sub_64
11870      26,	// DMRpRC:sub_dmrrowp1_then_sub_dmrrow0 -> DMRROWRC
11871      26,	// DMRpRC:sub_dmrrowp1_then_sub_dmrrow1 -> DMRROWRC
11872      26,	// DMRpRC:sub_wacc_hi_then_sub_dmrrow0 -> DMRROWRC
11873      26,	// DMRpRC:sub_wacc_hi_then_sub_dmrrow1 -> DMRROWRC
11874      35,	// DMRpRC:sub_wacc_hi_then_sub_dmrrowp0 -> DMRROWpRC
11875      35,	// DMRpRC:sub_wacc_hi_then_sub_dmrrowp1 -> DMRROWpRC
11876      26,	// DMRpRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0 -> DMRROWRC
11877      26,	// DMRpRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1 -> DMRROWRC
11878      26,	// DMRpRC:sub_dmr1_then_sub_dmrrow0 -> DMRROWRC
11879      26,	// DMRpRC:sub_dmr1_then_sub_dmrrow1 -> DMRROWRC
11880      35,	// DMRpRC:sub_dmr1_then_sub_dmrrowp0 -> DMRROWpRC
11881      35,	// DMRpRC:sub_dmr1_then_sub_dmrrowp1 -> DMRROWpRC
11882      45,	// DMRpRC:sub_dmr1_then_sub_wacc_hi -> WACC_HIRC
11883      44,	// DMRpRC:sub_dmr1_then_sub_wacc_lo -> WACCRC
11884      26,	// DMRpRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0 -> DMRROWRC
11885      26,	// DMRpRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1 -> DMRROWRC
11886      26,	// DMRpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0 -> DMRROWRC
11887      26,	// DMRpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1 -> DMRROWRC
11888      35,	// DMRpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0 -> DMRROWpRC
11889      35,	// DMRpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1 -> DMRROWpRC
11890      26,	// DMRpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0 -> DMRROWRC
11891      26,	// DMRpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1 -> DMRROWRC
11892      0,	// DMRpRC:sub_gp8_x1_then_sub_32
11893    },
11894  };
11895  assert(RC && "Missing regclass");
11896  if (!Idx) return RC;
11897  --Idx;
11898  assert(Idx < 48 && "Bad subreg");
11899  unsigned TV = Table[RC->getID()][Idx];
11900  return TV ? getRegClass(TV - 1) : nullptr;
11901}
11902
11903/// Get the weight in units of pressure for this register class.
11904const RegClassWeight &PPCGenRegisterInfo::
11905getRegClassWeight(const TargetRegisterClass *RC) const {
11906  static const RegClassWeight RCWeightTable[] = {
11907    {1, 64},  	// VSSRC
11908    {1, 34},  	// GPRC
11909    {1, 34},  	// GPRC_NOR0
11910    {1, 33},  	// GPRC_and_GPRC_NOR0
11911    {1, 32},  	// CRBITRC
11912    {1, 32},  	// F4RC
11913    {4, 32},  	// CRRC
11914    {1, 1},  	// CARRYRC
11915    {0, 0},  	// CTRRC
11916    {0, 0},  	// LRRC
11917    {1, 1},  	// VRSAVERC
11918    {1, 68},  	// SPILLTOVSRRC
11919    {1, 64},  	// VSFRC
11920    {1, 34},  	// G8RC
11921    {1, 34},  	// G8RC_NOX0
11922    {1, 34},  	// SPILLTOVSRRC_and_VSFRC
11923    {1, 33},  	// G8RC_and_G8RC_NOX0
11924    {1, 32},  	// F8RC
11925    {1, 32},  	// SPERC
11926    {1, 32},  	// VFRC
11927    {1, 31},  	// SPERC_with_sub_32_in_GPRC_NOR0
11928    {1, 20},  	// SPILLTOVSRRC_and_VFRC
11929    {1, 14},  	// SPILLTOVSRRC_and_F4RC
11930    {0, 0},  	// CTRRC8
11931    {0, 0},  	// LR8RC
11932    {1, 64},  	// DMRROWRC
11933    {1, 64},  	// VSRC
11934    {1, 34},  	// VSRC_with_sub_64_in_SPILLTOVSRRC
11935    {1, 32},  	// VRRC
11936    {1, 32},  	// VSLRC
11937    {1, 20},  	// VRRC_with_sub_64_in_SPILLTOVSRRC
11938    {2, 32},  	// G8pRC
11939    {2, 30},  	// G8pRC_with_sub_32_in_GPRC_NOR0
11940    {1, 14},  	// VSLRC_with_sub_64_in_SPILLTOVSRRC
11941    {2, 64},  	// DMRROWpRC
11942    {2, 64},  	// VSRpRC
11943    {2, 34},  	// VSRpRC_with_sub_64_in_SPILLTOVSRRC
11944    {2, 32},  	// VSRpRC_with_sub_64_in_F4RC
11945    {2, 32},  	// VSRpRC_with_sub_64_in_VFRC
11946    {2, 20},  	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC
11947    {2, 14},  	// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
11948    {4, 32},  	// ACCRC
11949    {4, 32},  	// UACCRC
11950    {4, 32},  	// WACCRC
11951    {4, 32},  	// WACC_HIRC
11952    {4, 16},  	// ACCRC_with_sub_64_in_SPILLTOVSRRC
11953    {4, 16},  	// UACCRC_with_sub_64_in_SPILLTOVSRRC
11954    {4, 12},  	// ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
11955    {4, 12},  	// UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
11956    {8, 64},  	// DMRRC
11957    {16, 64},  	// DMRpRC
11958  };
11959  return RCWeightTable[RC->getID()];
11960}
11961
11962/// Get the weight in units of pressure for this register unit.
11963unsigned PPCGenRegisterInfo::
11964getRegUnitWeight(unsigned RegUnit) const {
11965  assert(RegUnit < 235 && "invalid register unit");
11966  // All register units have unit weight.
11967  return 1;
11968}
11969
11970
11971// Get the number of dimensions of register pressure.
11972unsigned PPCGenRegisterInfo::getNumRegPressureSets() const {
11973  return 20;
11974}
11975
11976// Get the name of this register unit pressure set.
11977const char *PPCGenRegisterInfo::
11978getRegPressureSetName(unsigned Idx) const {
11979  static const char *PressureNameTable[] = {
11980    "CARRYRC",
11981    "VRSAVERC",
11982    "SPILLTOVSRRC_and_F4RC",
11983    "SPILLTOVSRRC_and_VFRC",
11984    "CRBITRC",
11985    "F4RC",
11986    "VFRC",
11987    "WACCRC",
11988    "WACC_HIRC",
11989    "GPRC",
11990    "SPILLTOVSRRC_and_VSFRC",
11991    "SPILLTOVSRRC_and_VSFRC_with_VFRC",
11992    "F4RC_with_SPILLTOVSRRC_and_VSFRC",
11993    "VSSRC",
11994    "DMRROWRC",
11995    "SPILLTOVSRRC",
11996    "SPILLTOVSRRC_with_SPILLTOVSRRC_and_F4RC",
11997    "SPILLTOVSRRC_with_VFRC",
11998    "F4RC_with_SPILLTOVSRRC",
11999    "VSSRC_with_SPILLTOVSRRC",
12000  };
12001  return PressureNameTable[Idx];
12002}
12003
12004// Get the register unit pressure limit for this dimension.
12005// This limit must be adjusted dynamically for reserved registers.
12006unsigned PPCGenRegisterInfo::
12007getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
12008  static const uint8_t PressureLimitTable[] = {
12009    1,  	// 0: CARRYRC
12010    1,  	// 1: VRSAVERC
12011    16,  	// 2: SPILLTOVSRRC_and_F4RC
12012    20,  	// 3: SPILLTOVSRRC_and_VFRC
12013    32,  	// 4: CRBITRC
12014    32,  	// 5: F4RC
12015    32,  	// 6: VFRC
12016    32,  	// 7: WACCRC
12017    32,  	// 8: WACC_HIRC
12018    35,  	// 9: GPRC
12019    36,  	// 10: SPILLTOVSRRC_and_VSFRC
12020    46,  	// 11: SPILLTOVSRRC_and_VSFRC_with_VFRC
12021    52,  	// 12: F4RC_with_SPILLTOVSRRC_and_VSFRC
12022    64,  	// 13: VSSRC
12023    64,  	// 14: DMRROWRC
12024    69,  	// 15: SPILLTOVSRRC
12025    70,  	// 16: SPILLTOVSRRC_with_SPILLTOVSRRC_and_F4RC
12026    80,  	// 17: SPILLTOVSRRC_with_VFRC
12027    86,  	// 18: F4RC_with_SPILLTOVSRRC
12028    98,  	// 19: VSSRC_with_SPILLTOVSRRC
12029  };
12030  return PressureLimitTable[Idx];
12031}
12032
12033/// Table of pressure sets per register class or unit.
12034static const int RCSetsTable[] = {
12035  /* 0 */ 0, -1,
12036  /* 2 */ 1, -1,
12037  /* 4 */ 4, -1,
12038  /* 6 */ 7, 14, -1,
12039  /* 9 */ 8, 14, -1,
12040  /* 12 */ 9, 15, -1,
12041  /* 15 */ 13, 19, -1,
12042  /* 18 */ 6, 11, 13, 17, 19, -1,
12043  /* 24 */ 5, 12, 13, 18, 19, -1,
12044  /* 30 */ 2, 5, 10, 12, 13, 16, 18, 19, -1,
12045  /* 39 */ 9, 15, 16, 17, 18, 19, -1,
12046  /* 46 */ 2, 5, 10, 11, 12, 13, 15, 16, 17, 18, 19, -1,
12047  /* 58 */ 3, 6, 10, 11, 12, 13, 15, 16, 17, 18, 19, -1,
12048};
12049
12050/// Get the dimensions of register pressure impacted by this register class.
12051/// Returns a -1 terminated array of pressure set IDs
12052const int *PPCGenRegisterInfo::
12053getRegClassPressureSets(const TargetRegisterClass *RC) const {
12054  static const uint8_t RCSetStartTable[] = {
12055    15,39,12,39,4,24,4,0,1,1,2,40,15,39,12,48,39,24,39,18,39,58,46,1,1,7,15,48,18,24,58,39,39,46,7,15,48,24,18,58,46,24,24,6,9,30,30,46,46,7,7,};
12056  return &RCSetsTable[RCSetStartTable[RC->getID()]];
12057}
12058
12059/// Get the dimensions of register pressure impacted by this register unit.
12060/// Returns a -1 terminated array of pressure set IDs
12061const int *PPCGenRegisterInfo::
12062getRegUnitPressureSets(unsigned RegUnit) const {
12063  assert(RegUnit < 235 && "invalid register unit");
12064  static const uint8_t RUSetStartTable[] = {
12065    39,0,1,39,1,1,1,2,12,46,46,46,46,46,46,46,46,46,46,46,46,46,46,30,30,24,24,24,24,24,24,24,24,24,24,24,24,24,24,24,24,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,1,6,6,6,6,9,9,9,9,6,6,6,6,9,9,9,9,6,6,6,6,9,9,9,9,6,6,6,6,9,9,9,9,6,6,6,6,9,9,9,9,6,6,6,6,9,9,9,9,6,6,6,6,9,9,9,9,6,6,6,6,9,9,9,9,1,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,58,58,58,58,58,58,58,58,58,58,58,58,58,58,58,58,58,58,58,58,18,18,18,18,18,18,18,18,18,18,18,18,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,};
12066  return &RCSetsTable[RUSetStartTable[RegUnit]];
12067}
12068
12069extern const MCRegisterDesc PPCRegDesc[];
12070extern const MCPhysReg PPCRegDiffLists[];
12071extern const LaneBitmask PPCLaneMaskLists[];
12072extern const char PPCRegStrings[];
12073extern const char PPCRegClassStrings[];
12074extern const MCPhysReg PPCRegUnitRoots[][2];
12075extern const uint16_t PPCSubRegIdxLists[];
12076extern const MCRegisterInfo::SubRegCoveredBits PPCSubRegIdxRanges[];
12077extern const uint16_t PPCRegEncodingTable[];
12078// PPC Dwarf<->LLVM register mappings.
12079extern const MCRegisterInfo::DwarfLLVMRegPair PPCDwarfFlavour0Dwarf2L[];
12080extern const unsigned PPCDwarfFlavour0Dwarf2LSize;
12081
12082extern const MCRegisterInfo::DwarfLLVMRegPair PPCDwarfFlavour1Dwarf2L[];
12083extern const unsigned PPCDwarfFlavour1Dwarf2LSize;
12084
12085extern const MCRegisterInfo::DwarfLLVMRegPair PPCEHFlavour0Dwarf2L[];
12086extern const unsigned PPCEHFlavour0Dwarf2LSize;
12087
12088extern const MCRegisterInfo::DwarfLLVMRegPair PPCEHFlavour1Dwarf2L[];
12089extern const unsigned PPCEHFlavour1Dwarf2LSize;
12090
12091extern const MCRegisterInfo::DwarfLLVMRegPair PPCDwarfFlavour0L2Dwarf[];
12092extern const unsigned PPCDwarfFlavour0L2DwarfSize;
12093
12094extern const MCRegisterInfo::DwarfLLVMRegPair PPCDwarfFlavour1L2Dwarf[];
12095extern const unsigned PPCDwarfFlavour1L2DwarfSize;
12096
12097extern const MCRegisterInfo::DwarfLLVMRegPair PPCEHFlavour0L2Dwarf[];
12098extern const unsigned PPCEHFlavour0L2DwarfSize;
12099
12100extern const MCRegisterInfo::DwarfLLVMRegPair PPCEHFlavour1L2Dwarf[];
12101extern const unsigned PPCEHFlavour1L2DwarfSize;
12102
12103PPCGenRegisterInfo::
12104PPCGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
12105      unsigned PC, unsigned HwMode)
12106  : TargetRegisterInfo(&PPCRegInfoDesc, RegisterClasses, RegisterClasses+51,
12107             SubRegIndexNameTable, SubRegIndexLaneMaskTable,
12108             LaneBitmask(0xFFFFFFFFFC000000), RegClassInfos, HwMode) {
12109  InitMCRegisterInfo(PPCRegDesc, 500, RA, PC,
12110                     PPCMCRegisterClasses, 51,
12111                     PPCRegUnitRoots,
12112                     235,
12113                     PPCRegDiffLists,
12114                     PPCLaneMaskLists,
12115                     PPCRegStrings,
12116                     PPCRegClassStrings,
12117                     PPCSubRegIdxLists,
12118                     49,
12119                     PPCSubRegIdxRanges,
12120                     PPCRegEncodingTable);
12121
12122  switch (DwarfFlavour) {
12123  default:
12124    llvm_unreachable("Unknown DWARF flavour");
12125  case 0:
12126    mapDwarfRegsToLLVMRegs(PPCDwarfFlavour0Dwarf2L, PPCDwarfFlavour0Dwarf2LSize, false);
12127    break;
12128  case 1:
12129    mapDwarfRegsToLLVMRegs(PPCDwarfFlavour1Dwarf2L, PPCDwarfFlavour1Dwarf2LSize, false);
12130    break;
12131  }
12132  switch (EHFlavour) {
12133  default:
12134    llvm_unreachable("Unknown DWARF flavour");
12135  case 0:
12136    mapDwarfRegsToLLVMRegs(PPCEHFlavour0Dwarf2L, PPCEHFlavour0Dwarf2LSize, true);
12137    break;
12138  case 1:
12139    mapDwarfRegsToLLVMRegs(PPCEHFlavour1Dwarf2L, PPCEHFlavour1Dwarf2LSize, true);
12140    break;
12141  }
12142  switch (DwarfFlavour) {
12143  default:
12144    llvm_unreachable("Unknown DWARF flavour");
12145  case 0:
12146    mapLLVMRegsToDwarfRegs(PPCDwarfFlavour0L2Dwarf, PPCDwarfFlavour0L2DwarfSize, false);
12147    break;
12148  case 1:
12149    mapLLVMRegsToDwarfRegs(PPCDwarfFlavour1L2Dwarf, PPCDwarfFlavour1L2DwarfSize, false);
12150    break;
12151  }
12152  switch (EHFlavour) {
12153  default:
12154    llvm_unreachable("Unknown DWARF flavour");
12155  case 0:
12156    mapLLVMRegsToDwarfRegs(PPCEHFlavour0L2Dwarf, PPCEHFlavour0L2DwarfSize, true);
12157    break;
12158  case 1:
12159    mapLLVMRegsToDwarfRegs(PPCEHFlavour1L2Dwarf, PPCEHFlavour1L2DwarfSize, true);
12160    break;
12161  }
12162}
12163
12164static const MCPhysReg CSR_64_AllRegs_SaveList[] = { PPC::X0, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, 0 };
12165static const uint32_t CSR_64_AllRegs_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffe00, 0xfe3fc9ff, 0x000007ff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfffe3fc8, 0xffffffff, 0x0000000f, };
12166static const MCPhysReg CSR_64_AllRegs_AIX_Dflt_Altivec_SaveList[] = { PPC::X0, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::V0, PPC::V1, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, 0 };
12167static const uint32_t CSR_64_AllRegs_AIX_Dflt_Altivec_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffe00, 0xfe3fc9ff, 0x000007ff, 0xfff80000, 0xfff8007f, 0x0000007f, 0x00000000, 0x00000000, 0x00000000, 0xfffe3fc8, 0xffffffff, 0x0000000f, };
12168static const MCPhysReg CSR_64_AllRegs_AIX_Dflt_VSX_SaveList[] = { PPC::X0, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::V0, PPC::V1, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3, PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7, PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11, PPC::VSL12, PPC::VSL13, PPC::VSL14, PPC::VSL15, PPC::VSL16, PPC::VSL17, PPC::VSL18, PPC::VSL19, 0 };
12169static const uint32_t CSR_64_AllRegs_AIX_Dflt_VSX_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffe00, 0xfe3fc9ff, 0x000007ff, 0xfff80000, 0xffffffff, 0xffffffff, 0x0000007f, 0x00000000, 0x00000000, 0xfffe3fc8, 0xffffffff, 0x0000000f, };
12170static const MCPhysReg CSR_64_AllRegs_Altivec_SaveList[] = { PPC::X0, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::V0, PPC::V1, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, 0 };
12171static const uint32_t CSR_64_AllRegs_Altivec_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffe00, 0xfe3fc9ff, 0x000007ff, 0xfff80000, 0xffffffff, 0x0007ffff, 0x00000000, 0x00000000, 0x00000000, 0xfffe3fc8, 0xffffffff, 0x0000000f, };
12172static const MCPhysReg CSR_64_AllRegs_VSRP_SaveList[] = { PPC::X0, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::V0, PPC::V1, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3, PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7, PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11, PPC::VSL12, PPC::VSL13, PPC::VSL14, PPC::VSL15, PPC::VSL16, PPC::VSL17, PPC::VSL18, PPC::VSL19, PPC::VSL20, PPC::VSL21, PPC::VSL22, PPC::VSL23, PPC::VSL24, PPC::VSL25, PPC::VSL26, PPC::VSL27, PPC::VSL28, PPC::VSL29, PPC::VSL30, PPC::VSL31, PPC::VSRp0, PPC::VSRp1, PPC::VSRp2, PPC::VSRp3, PPC::VSRp4, PPC::VSRp5, PPC::VSRp6, PPC::VSRp7, PPC::VSRp8, PPC::VSRp9, PPC::VSRp10, PPC::VSRp11, PPC::VSRp12, PPC::VSRp13, PPC::VSRp14, PPC::VSRp15, PPC::VSRp16, PPC::VSRp17, PPC::VSRp18, PPC::VSRp19, PPC::VSRp20, PPC::VSRp21, PPC::VSRp22, PPC::VSRp23, PPC::VSRp24, PPC::VSRp25, PPC::VSRp26, PPC::VSRp27, PPC::VSRp28, PPC::VSRp29, PPC::VSRp30, PPC::VSRp31, 0 };
12173static const uint32_t CSR_64_AllRegs_VSRP_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffe00, 0xfe3fc9ff, 0x000007ff, 0xfff80000, 0xffffffff, 0xffffffff, 0xffffffff, 0x0007ffff, 0x00000000, 0xfffe3fc8, 0xffffffff, 0x0000000f, };
12174static const MCPhysReg CSR_64_AllRegs_VSX_SaveList[] = { PPC::X0, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::V0, PPC::V1, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3, PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7, PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11, PPC::VSL12, PPC::VSL13, PPC::VSL14, PPC::VSL15, PPC::VSL16, PPC::VSL17, PPC::VSL18, PPC::VSL19, PPC::VSL20, PPC::VSL21, PPC::VSL22, PPC::VSL23, PPC::VSL24, PPC::VSL25, PPC::VSL26, PPC::VSL27, PPC::VSL28, PPC::VSL29, PPC::VSL30, PPC::VSL31, 0 };
12175static const uint32_t CSR_64_AllRegs_VSX_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffe00, 0xfe3fc9ff, 0x000007ff, 0xfff80000, 0xffffffff, 0xffffffff, 0x0007ffff, 0x00000000, 0x00000000, 0xfffe3fc8, 0xffffffff, 0x0000000f, };
12176static const MCPhysReg CSR_AIX32_SaveList[] = { PPC::R13, PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, 0 };
12177static const uint32_t CSR_AIX32_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0xff0001ff, 0x000007ff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xc1c1c1c8, 0x00000001, };
12178static const MCPhysReg CSR_AIX32_Altivec_SaveList[] = { PPC::R13, PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, 0 };
12179static const uint32_t CSR_AIX32_Altivec_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0xff0001ff, 0x000007ff, 0x00000000, 0x0007ff80, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xc1c1c1c8, 0x00000001, };
12180static const MCPhysReg CSR_AIX32_VSRP_SaveList[] = { PPC::R13, PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, PPC::VSRp26, PPC::VSRp27, PPC::VSRp28, PPC::VSRp29, PPC::VSRp30, PPC::VSRp31, 0 };
12181static const uint32_t CSR_AIX32_VSRP_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0xff0001ff, 0x000007ff, 0x00000000, 0x0007ff80, 0x0007ff80, 0x00000000, 0x0007e000, 0x00000000, 0x00000000, 0xc1c1c1c8, 0x00000001, };
12182static const MCPhysReg CSR_AIX64_R2_VSRP_SaveList[] = { PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, PPC::VSRp26, PPC::VSRp27, PPC::VSRp28, PPC::VSRp29, PPC::VSRp30, PPC::VSRp31, PPC::X2, 0 };
12183static const uint32_t CSR_AIX64_R2_VSRP_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0xfe0021ff, 0x000007ff, 0x00000000, 0x0007ff80, 0x0007ff80, 0x00000000, 0x0007e000, 0x00000000, 0xfffe0020, 0xc1c1c1cf, 0x00000001, };
12184static const MCPhysReg CSR_AIX64_VSRP_SaveList[] = { PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, PPC::VSRp26, PPC::VSRp27, PPC::VSRp28, PPC::VSRp29, PPC::VSRp30, PPC::VSRp31, 0 };
12185static const uint32_t CSR_AIX64_VSRP_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0xfe0001ff, 0x000007ff, 0x00000000, 0x0007ff80, 0x0007ff80, 0x00000000, 0x0007e000, 0x00000000, 0xfffe0000, 0xc1c1c1cf, 0x00000001, };
12186static const MCPhysReg CSR_ALL_VSRP_SaveList[] = { PPC::VSRp0, PPC::VSRp1, PPC::VSRp2, PPC::VSRp3, PPC::VSRp4, PPC::VSRp5, PPC::VSRp6, PPC::VSRp7, PPC::VSRp8, PPC::VSRp9, PPC::VSRp10, PPC::VSRp11, PPC::VSRp12, PPC::VSRp13, PPC::VSRp14, PPC::VSRp15, PPC::VSRp16, PPC::VSRp17, PPC::VSRp18, PPC::VSRp19, PPC::VSRp20, PPC::VSRp21, PPC::VSRp22, PPC::VSRp23, PPC::VSRp24, PPC::VSRp25, PPC::VSRp26, PPC::VSRp27, PPC::VSRp28, PPC::VSRp29, PPC::VSRp30, PPC::VSRp31, 0 };
12187static const uint32_t CSR_ALL_VSRP_RegMask[] = { 0x00000400, 0x00000000, 0x00000000, 0x00000000, 0xfffffe00, 0x000001ff, 0x00000000, 0xfff80000, 0xffffffff, 0xffffffff, 0xffffffff, 0x0007ffff, 0x00000000, 0x00000000, 0x00000008, 0x00000000, };
12188static const MCPhysReg CSR_Altivec_SaveList[] = { PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, 0 };
12189static const uint32_t CSR_Altivec_RegMask[] = { 0x00000400, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0007ff80, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008, 0x00000000, };
12190static const MCPhysReg CSR_NoRegs_SaveList[] = { 0 };
12191static const uint32_t CSR_NoRegs_RegMask[] = { 0x00000400, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008, 0x00000000, };
12192static const MCPhysReg CSR_PPC64_SaveList[] = { PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, 0 };
12193static const uint32_t CSR_PPC64_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0xfe0001ff, 0x000007ff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfffe0000, 0xc1c1c1cf, 0x00000001, };
12194static const MCPhysReg CSR_PPC64_Altivec_SaveList[] = { PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, 0 };
12195static const uint32_t CSR_PPC64_Altivec_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0xfe0001ff, 0x000007ff, 0x00000000, 0x0007ff80, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0xfffe0000, 0xc1c1c1cf, 0x00000001, };
12196static const MCPhysReg CSR_PPC64_R2_SaveList[] = { PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::X2, 0 };
12197static const uint32_t CSR_PPC64_R2_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0xfe0021ff, 0x000007ff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfffe0020, 0xc1c1c1cf, 0x00000001, };
12198static const MCPhysReg CSR_PPC64_R2_Altivec_SaveList[] = { PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, PPC::X2, 0 };
12199static const uint32_t CSR_PPC64_R2_Altivec_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0xfe0021ff, 0x000007ff, 0x00000000, 0x0007ff80, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0xfffe0020, 0xc1c1c1cf, 0x00000001, };
12200static const MCPhysReg CSR_SPE_SaveList[] = { PPC::S14, PPC::S15, PPC::S16, PPC::S17, PPC::S18, PPC::S19, PPC::S20, PPC::S21, PPC::S22, PPC::S23, PPC::S24, PPC::S25, PPC::S26, PPC::S27, PPC::S28, PPC::S29, PPC::S30, 0 };
12201static const uint32_t CSR_SPE_RegMask[] = { 0x00000400, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfe000000, 0xfe0003ff, 0x000003ff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008, 0x00000000, };
12202static const MCPhysReg CSR_SPE_NO_S30_31_SaveList[] = { PPC::S14, PPC::S15, PPC::S16, PPC::S17, PPC::S18, PPC::S19, PPC::S20, PPC::S21, PPC::S22, PPC::S23, PPC::S24, PPC::S25, PPC::S26, PPC::S27, PPC::S28, PPC::S29, 0 };
12203static const uint32_t CSR_SPE_NO_S30_31_RegMask[] = { 0x00000400, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfe000000, 0xfe0001ff, 0x000001ff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008, 0x00000000, };
12204static const MCPhysReg CSR_SVR32_ColdCC_SaveList[] = { PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::F0, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, 0 };
12205static const uint32_t CSR_SVR32_ColdCC_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffa00, 0xfe3f81ff, 0x000007ff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfffffff8, 0x0000000f, };
12206static const MCPhysReg CSR_SVR32_ColdCC_Altivec_SaveList[] = { PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::F0, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::V0, PPC::V1, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, 0 };
12207static const uint32_t CSR_SVR32_ColdCC_Altivec_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffa00, 0xfe3f81ff, 0x000007ff, 0xffd80000, 0xffdfffff, 0x0007ffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfffffff8, 0x0000000f, };
12208static const MCPhysReg CSR_SVR32_ColdCC_Common_SaveList[] = { PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, 0 };
12209static const uint32_t CSR_SVR32_ColdCC_Common_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfe3f8000, 0x000007ff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfffffff8, 0x0000000f, };
12210static const MCPhysReg CSR_SVR32_ColdCC_SPE_SaveList[] = { PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::S4, PPC::S5, PPC::S6, PPC::S7, PPC::S8, PPC::S9, PPC::S10, PPC::S14, PPC::S15, PPC::S16, PPC::S17, PPC::S18, PPC::S19, PPC::S20, PPC::S21, PPC::S22, PPC::S23, PPC::S24, PPC::S25, PPC::S26, PPC::S27, PPC::S28, PPC::S29, PPC::S30, PPC::S31, 0 };
12211static const uint32_t CSR_SVR32_ColdCC_SPE_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfe3f8000, 0xfe3f87ff, 0x000007ff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfffffff8, 0x0000000f, };
12212static const MCPhysReg CSR_SVR32_ColdCC_VSRP_SaveList[] = { PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::F0, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::V0, PPC::V1, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, PPC::VSRp0, PPC::VSRp1, PPC::VSRp2, PPC::VSRp3, PPC::VSRp4, PPC::VSRp5, PPC::VSRp6, PPC::VSRp7, PPC::VSRp8, PPC::VSRp9, PPC::VSRp10, PPC::VSRp11, PPC::VSRp12, PPC::VSRp13, PPC::VSRp14, PPC::VSRp15, PPC::VSRp16, PPC::VSRp18, PPC::VSRp19, PPC::VSRp20, PPC::VSRp21, PPC::VSRp22, PPC::VSRp23, PPC::VSRp24, PPC::VSRp25, PPC::VSRp26, PPC::VSRp27, PPC::VSRp28, PPC::VSRp29, PPC::VSRp30, PPC::VSRp31, 0 };
12213static const uint32_t CSR_SVR32_ColdCC_VSRP_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffe00, 0xfe3f81ff, 0x000007ff, 0xffd80000, 0xffdfffff, 0xffffffff, 0xffffffff, 0x0007ffef, 0x00000000, 0x00000000, 0xfffffff8, 0x0000000f, };
12214static const MCPhysReg CSR_SVR432_SaveList[] = { PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, 0 };
12215static const uint32_t CSR_SVR432_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0xfe0001ff, 0x000007ff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xc1c1c1c8, 0x00000001, };
12216static const MCPhysReg CSR_SVR432_Altivec_SaveList[] = { PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, 0 };
12217static const uint32_t CSR_SVR432_Altivec_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0xfe0001ff, 0x000007ff, 0x00000000, 0x0007ff80, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xc1c1c1c8, 0x00000001, };
12218static const MCPhysReg CSR_SVR432_COMM_SaveList[] = { PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::CR2, PPC::CR3, PPC::CR4, 0 };
12219static const uint32_t CSR_SVR432_COMM_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfe000000, 0x000007ff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xc1c1c1c8, 0x00000001, };
12220static const MCPhysReg CSR_SVR432_SPE_SaveList[] = { PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::S14, PPC::S15, PPC::S16, PPC::S17, PPC::S18, PPC::S19, PPC::S20, PPC::S21, PPC::S22, PPC::S23, PPC::S24, PPC::S25, PPC::S26, PPC::S27, PPC::S28, PPC::S29, PPC::S30, 0 };
12221static const uint32_t CSR_SVR432_SPE_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfe000000, 0xfe0007ff, 0x000003ff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xc1c1c1c8, 0x00000001, };
12222static const MCPhysReg CSR_SVR432_SPE_NO_S30_31_SaveList[] = { PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::S14, PPC::S15, PPC::S16, PPC::S17, PPC::S18, PPC::S19, PPC::S20, PPC::S21, PPC::S22, PPC::S23, PPC::S24, PPC::S25, PPC::S26, PPC::S27, PPC::S28, PPC::S29, 0 };
12223static const uint32_t CSR_SVR432_SPE_NO_S30_31_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfe000000, 0xfe0007ff, 0x000001ff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xc1c1c1c8, 0x00000001, };
12224static const MCPhysReg CSR_SVR432_VSRP_SaveList[] = { PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, PPC::VSRp26, PPC::VSRp27, PPC::VSRp28, PPC::VSRp29, PPC::VSRp30, PPC::VSRp31, 0 };
12225static const uint32_t CSR_SVR432_VSRP_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0xfe0001ff, 0x000007ff, 0x00000000, 0x0007ff80, 0x0007ff80, 0x00000000, 0x0007e000, 0x00000000, 0x00000000, 0xc1c1c1c8, 0x00000001, };
12226static const MCPhysReg CSR_SVR464_R2_VSRP_SaveList[] = { PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, PPC::VSRp26, PPC::VSRp27, PPC::VSRp28, PPC::VSRp29, PPC::VSRp30, PPC::VSRp31, PPC::X2, 0 };
12227static const uint32_t CSR_SVR464_R2_VSRP_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0xfe0021ff, 0x000007ff, 0x00000000, 0x0007ff80, 0x0007ff80, 0x00000000, 0x0007e000, 0x00000000, 0xfffe0020, 0xc1c1c1cf, 0x00000001, };
12228static const MCPhysReg CSR_SVR464_VSRP_SaveList[] = { PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, PPC::VSRp26, PPC::VSRp27, PPC::VSRp28, PPC::VSRp29, PPC::VSRp30, PPC::VSRp31, 0 };
12229static const uint32_t CSR_SVR464_VSRP_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0xfe0001ff, 0x000007ff, 0x00000000, 0x0007ff80, 0x0007ff80, 0x00000000, 0x0007e000, 0x00000000, 0xfffe0000, 0xc1c1c1cf, 0x00000001, };
12230static const MCPhysReg CSR_SVR64_ColdCC_SaveList[] = { PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, 0 };
12231static const uint32_t CSR_SVR64_ColdCC_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffa00, 0xfe3f81ff, 0x000007ff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfffe3f80, 0xffffffff, 0x0000000f, };
12232static const MCPhysReg CSR_SVR64_ColdCC_Altivec_SaveList[] = { PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::V0, PPC::V1, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, 0 };
12233static const uint32_t CSR_SVR64_ColdCC_Altivec_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffa00, 0xfe3f81ff, 0x000007ff, 0xffd80000, 0xffdfffff, 0x0007ffff, 0x00000000, 0x00000000, 0x00000000, 0xfffe3f80, 0xffffffff, 0x0000000f, };
12234static const MCPhysReg CSR_SVR64_ColdCC_R2_SaveList[] = { PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::X2, 0 };
12235static const uint32_t CSR_SVR64_ColdCC_R2_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffa00, 0xfe3fa1ff, 0x000007ff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfffe3fa0, 0xffffffff, 0x0000000f, };
12236static const MCPhysReg CSR_SVR64_ColdCC_R2_Altivec_SaveList[] = { PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::V0, PPC::V1, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, PPC::X2, 0 };
12237static const uint32_t CSR_SVR64_ColdCC_R2_Altivec_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffa00, 0xfe3fa1ff, 0x000007ff, 0xffd80000, 0xffdfffff, 0x0007ffff, 0x00000000, 0x00000000, 0x00000000, 0xfffe3fa0, 0xffffffff, 0x0000000f, };
12238static const MCPhysReg CSR_SVR64_ColdCC_R2_VSRP_SaveList[] = { PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::VSRp0, PPC::VSRp1, PPC::VSRp2, PPC::VSRp3, PPC::VSRp4, PPC::VSRp5, PPC::VSRp6, PPC::VSRp7, PPC::VSRp8, PPC::VSRp9, PPC::VSRp10, PPC::VSRp11, PPC::VSRp12, PPC::VSRp13, PPC::VSRp14, PPC::VSRp15, PPC::VSRp16, PPC::VSRp18, PPC::VSRp19, PPC::VSRp20, PPC::VSRp21, PPC::VSRp22, PPC::VSRp23, PPC::VSRp24, PPC::VSRp25, PPC::VSRp26, PPC::VSRp27, PPC::VSRp28, PPC::VSRp29, PPC::VSRp30, PPC::VSRp31, PPC::X2, 0 };
12239static const uint32_t CSR_SVR64_ColdCC_R2_VSRP_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffe00, 0xfe3fa1ff, 0x000007ff, 0xff980000, 0xff9fffff, 0xffffffff, 0xffffffff, 0x0007ffef, 0x00000000, 0xfffe3fa0, 0xffffffff, 0x0000000f, };
12240static const MCPhysReg CSR_SVR64_ColdCC_VSRP_SaveList[] = { PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::VSRp0, PPC::VSRp1, PPC::VSRp2, PPC::VSRp3, PPC::VSRp4, PPC::VSRp5, PPC::VSRp6, PPC::VSRp7, PPC::VSRp8, PPC::VSRp9, PPC::VSRp10, PPC::VSRp11, PPC::VSRp12, PPC::VSRp13, PPC::VSRp14, PPC::VSRp15, PPC::VSRp16, PPC::VSRp18, PPC::VSRp19, PPC::VSRp20, PPC::VSRp21, PPC::VSRp22, PPC::VSRp23, PPC::VSRp24, PPC::VSRp25, PPC::VSRp26, PPC::VSRp27, PPC::VSRp28, PPC::VSRp29, PPC::VSRp30, PPC::VSRp31, 0 };
12241static const uint32_t CSR_SVR64_ColdCC_VSRP_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffe00, 0xfe3f81ff, 0x000007ff, 0xff980000, 0xff9fffff, 0xffffffff, 0xffffffff, 0x0007ffef, 0x00000000, 0xfffe3f80, 0xffffffff, 0x0000000f, };
12242static const MCPhysReg CSR_VSRP_SaveList[] = { PPC::VSRp26, PPC::VSRp27, PPC::VSRp28, PPC::VSRp29, PPC::VSRp30, PPC::VSRp31, 0 };
12243static const uint32_t CSR_VSRP_RegMask[] = { 0x00000400, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0007ff80, 0x0007ff80, 0x00000000, 0x0007e000, 0x00000000, 0x00000000, 0x00000008, 0x00000000, };
12244
12245
12246ArrayRef<const uint32_t *> PPCGenRegisterInfo::getRegMasks() const {
12247  static const uint32_t *const Masks[] = {
12248    CSR_64_AllRegs_RegMask,
12249    CSR_64_AllRegs_AIX_Dflt_Altivec_RegMask,
12250    CSR_64_AllRegs_AIX_Dflt_VSX_RegMask,
12251    CSR_64_AllRegs_Altivec_RegMask,
12252    CSR_64_AllRegs_VSRP_RegMask,
12253    CSR_64_AllRegs_VSX_RegMask,
12254    CSR_AIX32_RegMask,
12255    CSR_AIX32_Altivec_RegMask,
12256    CSR_AIX32_VSRP_RegMask,
12257    CSR_AIX64_R2_VSRP_RegMask,
12258    CSR_AIX64_VSRP_RegMask,
12259    CSR_ALL_VSRP_RegMask,
12260    CSR_Altivec_RegMask,
12261    CSR_NoRegs_RegMask,
12262    CSR_PPC64_RegMask,
12263    CSR_PPC64_Altivec_RegMask,
12264    CSR_PPC64_R2_RegMask,
12265    CSR_PPC64_R2_Altivec_RegMask,
12266    CSR_SPE_RegMask,
12267    CSR_SPE_NO_S30_31_RegMask,
12268    CSR_SVR32_ColdCC_RegMask,
12269    CSR_SVR32_ColdCC_Altivec_RegMask,
12270    CSR_SVR32_ColdCC_Common_RegMask,
12271    CSR_SVR32_ColdCC_SPE_RegMask,
12272    CSR_SVR32_ColdCC_VSRP_RegMask,
12273    CSR_SVR432_RegMask,
12274    CSR_SVR432_Altivec_RegMask,
12275    CSR_SVR432_COMM_RegMask,
12276    CSR_SVR432_SPE_RegMask,
12277    CSR_SVR432_SPE_NO_S30_31_RegMask,
12278    CSR_SVR432_VSRP_RegMask,
12279    CSR_SVR464_R2_VSRP_RegMask,
12280    CSR_SVR464_VSRP_RegMask,
12281    CSR_SVR64_ColdCC_RegMask,
12282    CSR_SVR64_ColdCC_Altivec_RegMask,
12283    CSR_SVR64_ColdCC_R2_RegMask,
12284    CSR_SVR64_ColdCC_R2_Altivec_RegMask,
12285    CSR_SVR64_ColdCC_R2_VSRP_RegMask,
12286    CSR_SVR64_ColdCC_VSRP_RegMask,
12287    CSR_VSRP_RegMask,
12288  };
12289  return ArrayRef(Masks);
12290}
12291
12292bool PPCGenRegisterInfo::
12293isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
12294  return
12295      false;
12296}
12297
12298bool PPCGenRegisterInfo::
12299isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
12300  return
12301      false;
12302}
12303
12304bool PPCGenRegisterInfo::
12305isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
12306  return
12307      false;
12308}
12309
12310bool PPCGenRegisterInfo::
12311isConstantPhysReg(MCRegister PhysReg) const {
12312  return
12313      PhysReg == PPC::ZERO ||
12314      PhysReg == PPC::ZERO8 ||
12315      false;
12316}
12317
12318ArrayRef<const char *> PPCGenRegisterInfo::getRegMaskNames() const {
12319  static const char *Names[] = {
12320    "CSR_64_AllRegs",
12321    "CSR_64_AllRegs_AIX_Dflt_Altivec",
12322    "CSR_64_AllRegs_AIX_Dflt_VSX",
12323    "CSR_64_AllRegs_Altivec",
12324    "CSR_64_AllRegs_VSRP",
12325    "CSR_64_AllRegs_VSX",
12326    "CSR_AIX32",
12327    "CSR_AIX32_Altivec",
12328    "CSR_AIX32_VSRP",
12329    "CSR_AIX64_R2_VSRP",
12330    "CSR_AIX64_VSRP",
12331    "CSR_ALL_VSRP",
12332    "CSR_Altivec",
12333    "CSR_NoRegs",
12334    "CSR_PPC64",
12335    "CSR_PPC64_Altivec",
12336    "CSR_PPC64_R2",
12337    "CSR_PPC64_R2_Altivec",
12338    "CSR_SPE",
12339    "CSR_SPE_NO_S30_31",
12340    "CSR_SVR32_ColdCC",
12341    "CSR_SVR32_ColdCC_Altivec",
12342    "CSR_SVR32_ColdCC_Common",
12343    "CSR_SVR32_ColdCC_SPE",
12344    "CSR_SVR32_ColdCC_VSRP",
12345    "CSR_SVR432",
12346    "CSR_SVR432_Altivec",
12347    "CSR_SVR432_COMM",
12348    "CSR_SVR432_SPE",
12349    "CSR_SVR432_SPE_NO_S30_31",
12350    "CSR_SVR432_VSRP",
12351    "CSR_SVR464_R2_VSRP",
12352    "CSR_SVR464_VSRP",
12353    "CSR_SVR64_ColdCC",
12354    "CSR_SVR64_ColdCC_Altivec",
12355    "CSR_SVR64_ColdCC_R2",
12356    "CSR_SVR64_ColdCC_R2_Altivec",
12357    "CSR_SVR64_ColdCC_R2_VSRP",
12358    "CSR_SVR64_ColdCC_VSRP",
12359    "CSR_VSRP",
12360  };
12361  return ArrayRef(Names);
12362}
12363
12364const PPCFrameLowering *
12365PPCGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
12366  return static_cast<const PPCFrameLowering *>(
12367      MF.getSubtarget().getFrameLowering());
12368}
12369
12370} // end namespace llvm
12371
12372#endif // GET_REGINFO_TARGET_DESC
12373
12374