1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2|* *| 3|* Compress instruction Source Fragment *| 4|* *| 5|* Automatically generated file, do not edit! *| 6|* *| 7\*===----------------------------------------------------------------------===*/ 8 9 10#ifdef GEN_COMPRESS_INSTR 11#undef GEN_COMPRESS_INSTR 12 13static bool RISCVValidateMCOperandForCompress(const MCOperand &MCOp, 14 const MCSubtargetInfo &STI, 15 unsigned PredicateIndex) { 16 switch (PredicateIndex) { 17 default: 18 llvm_unreachable("Unknown MCOperandPredicate kind"); 19 break; 20 case 1: { 21 // uimm10_lsb00nonzero 22 23 int64_t Imm; 24 if (!MCOp.evaluateAsConstantImm(Imm)) 25 return false; 26 return isShiftedUInt<8, 2>(Imm) && (Imm != 0); 27 28 } 29 case 2: { 30 // simm6nonzero 31 32 int64_t Imm; 33 if (MCOp.evaluateAsConstantImm(Imm)) 34 return (Imm != 0) && isInt<6>(Imm); 35 return MCOp.isBareSymbolRef(); 36 37 } 38 case 3: { 39 // simm6 40 41 int64_t Imm; 42 if (MCOp.evaluateAsConstantImm(Imm)) 43 return isInt<6>(Imm); 44 return MCOp.isBareSymbolRef(); 45 46 } 47 case 4: { 48 // simm10_lsb0000nonzero 49 50 int64_t Imm; 51 if (!MCOp.evaluateAsConstantImm(Imm)) 52 return false; 53 return isShiftedInt<6, 4>(Imm) && (Imm != 0); 54 55 } 56 case 5: { 57 // simm9_lsb0 58 59 int64_t Imm; 60 if (MCOp.evaluateAsConstantImm(Imm)) 61 return isShiftedInt<8, 1>(Imm); 62 return MCOp.isBareSymbolRef(); 63 64 65 } 66 case 6: { 67 // uimm8_lsb000 68 69 int64_t Imm; 70 if (!MCOp.evaluateAsConstantImm(Imm)) 71 return false; 72 return isShiftedUInt<5, 3>(Imm); 73 74 } 75 case 7: { 76 // uimm9_lsb000 77 78 int64_t Imm; 79 if (!MCOp.evaluateAsConstantImm(Imm)) 80 return false; 81 return isShiftedUInt<6, 3>(Imm); 82 83 } 84 case 8: { 85 // uimm7_lsb00 86 87 int64_t Imm; 88 if (!MCOp.evaluateAsConstantImm(Imm)) 89 return false; 90 return isShiftedUInt<5, 2>(Imm); 91 92 } 93 case 9: { 94 // uimm8_lsb00 95 96 int64_t Imm; 97 if (!MCOp.evaluateAsConstantImm(Imm)) 98 return false; 99 return isShiftedUInt<6, 2>(Imm); 100 101 } 102 case 10: { 103 // simm12_lsb0 104 105 int64_t Imm; 106 if (MCOp.evaluateAsConstantImm(Imm)) 107 return isShiftedInt<11, 1>(Imm); 108 return MCOp.isBareSymbolRef(); 109 110 } 111 case 11: { 112 // c_lui_imm 113 114 int64_t Imm; 115 if (MCOp.evaluateAsConstantImm(Imm)) 116 return (Imm != 0) && (isUInt<5>(Imm) || 117 (Imm >= 0xfffe0 && Imm <= 0xfffff)); 118 return MCOp.isBareSymbolRef(); 119 120 } 121 case 12: { 122 // uimmlog2xlennonzero 123 124 int64_t Imm; 125 if (!MCOp.evaluateAsConstantImm(Imm)) 126 return false; 127 if (STI.getTargetTriple().isArch64Bit()) 128 return isUInt<6>(Imm) && (Imm != 0); 129 return isUInt<5>(Imm) && (Imm != 0); 130 131 } 132 } 133} 134 135static bool compressInst(MCInst &OutInst, 136 const MCInst &MI, 137 const MCSubtargetInfo &STI) { 138 switch (MI.getOpcode()) { 139 default: return false; 140 case RISCV::ADD: { 141 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 142 (MI.getOperand(1).isReg()) && 143 (MI.getOperand(1).getReg() == RISCV::X0) && 144 (MI.getOperand(0).isReg()) && 145 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(0).getReg())) && 146 (MI.getOperand(2).isReg()) && 147 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(2).getReg()))) { 148 // c.mv $rs1, $rs2 149 OutInst.setOpcode(RISCV::C_MV); 150 // Operand: rs1 151 OutInst.addOperand(MI.getOperand(0)); 152 // Operand: rs2 153 OutInst.addOperand(MI.getOperand(2)); 154 OutInst.setLoc(MI.getLoc()); 155 return true; 156 } // if 157 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 158 (MI.getOperand(2).isReg()) && 159 (MI.getOperand(2).getReg() == RISCV::X0) && 160 (MI.getOperand(0).isReg()) && 161 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(0).getReg())) && 162 (MI.getOperand(1).isReg()) && 163 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(1).getReg()))) { 164 // c.mv $rs1, $rs2 165 OutInst.setOpcode(RISCV::C_MV); 166 // Operand: rs1 167 OutInst.addOperand(MI.getOperand(0)); 168 // Operand: rs2 169 OutInst.addOperand(MI.getOperand(1)); 170 OutInst.setLoc(MI.getLoc()); 171 return true; 172 } // if 173 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 174 (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) && 175 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && 176 (MI.getOperand(1).isReg()) && 177 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(1).getReg())) && 178 (MI.getOperand(2).isReg()) && 179 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(2).getReg()))) { 180 // c.add $rs1, $rs2 181 OutInst.setOpcode(RISCV::C_ADD); 182 // Operand: rs1_wb 183 OutInst.addOperand(MI.getOperand(1)); 184 // Operand: rs1 185 OutInst.addOperand(MI.getOperand(1)); 186 // Operand: rs2 187 OutInst.addOperand(MI.getOperand(2)); 188 OutInst.setLoc(MI.getLoc()); 189 return true; 190 } // if 191 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 192 (MI.getOperand(2).isReg()) && (MI.getOperand(0).isReg()) && 193 (MI.getOperand(2).getReg() == MI.getOperand(0).getReg()) && 194 (MI.getOperand(2).isReg()) && 195 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(2).getReg())) && 196 (MI.getOperand(1).isReg()) && 197 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(1).getReg()))) { 198 // c.add $rs1, $rs2 199 OutInst.setOpcode(RISCV::C_ADD); 200 // Operand: rs1_wb 201 OutInst.addOperand(MI.getOperand(2)); 202 // Operand: rs1 203 OutInst.addOperand(MI.getOperand(2)); 204 // Operand: rs2 205 OutInst.addOperand(MI.getOperand(1)); 206 OutInst.setLoc(MI.getLoc()); 207 return true; 208 } // if 209 break; 210 } // case ADD 211 case RISCV::ADDI: { 212 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 213 (MI.getOperand(0).isReg()) && 214 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(0).getReg())) && 215 (MI.getOperand(1).isReg()) && 216 (RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(1).getReg())) && 217 RISCVValidateMCOperandForCompress(MI.getOperand(2), STI, 1)) { 218 // c.addi4spn $rd, $rs1, $imm 219 OutInst.setOpcode(RISCV::C_ADDI4SPN); 220 // Operand: rd 221 OutInst.addOperand(MI.getOperand(0)); 222 // Operand: rs1 223 OutInst.addOperand(MI.getOperand(1)); 224 // Operand: imm 225 OutInst.addOperand(MI.getOperand(2)); 226 OutInst.setLoc(MI.getLoc()); 227 return true; 228 } // if 229 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 230 (MI.getOperand(0).isReg()) && 231 (MI.getOperand(0).getReg() == RISCV::X0) && 232 (MI.getOperand(1).isReg()) && 233 (MI.getOperand(1).getReg() == RISCV::X0) && 234 (MI.getOperand(2).isImm()) && 235 (MI.getOperand(2).getImm() == 0)) { 236 // c.nop 237 OutInst.setOpcode(RISCV::C_NOP); 238 OutInst.setLoc(MI.getLoc()); 239 return true; 240 } // if 241 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 242 (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) && 243 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && 244 (MI.getOperand(1).isReg()) && 245 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(1).getReg())) && 246 RISCVValidateMCOperandForCompress(MI.getOperand(2), STI, 2)) { 247 // c.addi $rd, $imm 248 OutInst.setOpcode(RISCV::C_ADDI); 249 // Operand: rd_wb 250 OutInst.addOperand(MI.getOperand(1)); 251 // Operand: rd 252 OutInst.addOperand(MI.getOperand(1)); 253 // Operand: imm 254 OutInst.addOperand(MI.getOperand(2)); 255 OutInst.setLoc(MI.getLoc()); 256 return true; 257 } // if 258 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 259 (MI.getOperand(1).isReg()) && 260 (MI.getOperand(1).getReg() == RISCV::X0) && 261 (MI.getOperand(0).isReg()) && 262 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(0).getReg())) && 263 RISCVValidateMCOperandForCompress(MI.getOperand(2), STI, 3)) { 264 // c.li $rd, $imm 265 OutInst.setOpcode(RISCV::C_LI); 266 // Operand: rd 267 OutInst.addOperand(MI.getOperand(0)); 268 // Operand: imm 269 OutInst.addOperand(MI.getOperand(2)); 270 OutInst.setLoc(MI.getLoc()); 271 return true; 272 } // if 273 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 274 (MI.getOperand(0).isReg()) && 275 (MI.getOperand(0).getReg() == RISCV::X2) && 276 (MI.getOperand(1).isReg()) && 277 (MI.getOperand(1).getReg() == RISCV::X2) && 278 RISCVValidateMCOperandForCompress(MI.getOperand(2), STI, 4)) { 279 // c.addi16sp $rd, $imm 280 OutInst.setOpcode(RISCV::C_ADDI16SP); 281 // Operand: rd_wb 282 OutInst.addOperand(MCOperand::createReg(RISCV::X2)); 283 // Operand: rd 284 OutInst.addOperand(MCOperand::createReg(RISCV::X2)); 285 // Operand: imm 286 OutInst.addOperand(MI.getOperand(2)); 287 OutInst.setLoc(MI.getLoc()); 288 return true; 289 } // if 290 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 291 (MI.getOperand(2).isImm()) && 292 (MI.getOperand(2).getImm() == 0) && 293 (MI.getOperand(0).isReg()) && 294 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(0).getReg())) && 295 (MI.getOperand(1).isReg()) && 296 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(1).getReg()))) { 297 // c.mv $rs1, $rs2 298 OutInst.setOpcode(RISCV::C_MV); 299 // Operand: rs1 300 OutInst.addOperand(MI.getOperand(0)); 301 // Operand: rs2 302 OutInst.addOperand(MI.getOperand(1)); 303 OutInst.setLoc(MI.getLoc()); 304 return true; 305 } // if 306 break; 307 } // case ADDI 308 case RISCV::ADDIW: { 309 if (STI.getFeatureBits()[RISCV::Feature64Bit] && 310 (STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 311 (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) && 312 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && 313 (MI.getOperand(1).isReg()) && 314 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(1).getReg())) && 315 RISCVValidateMCOperandForCompress(MI.getOperand(2), STI, 3)) { 316 // c.addiw $rd, $imm 317 OutInst.setOpcode(RISCV::C_ADDIW); 318 // Operand: rd_wb 319 OutInst.addOperand(MI.getOperand(1)); 320 // Operand: rd 321 OutInst.addOperand(MI.getOperand(1)); 322 // Operand: imm 323 OutInst.addOperand(MI.getOperand(2)); 324 OutInst.setLoc(MI.getLoc()); 325 return true; 326 } // if 327 if (STI.getFeatureBits()[RISCV::Feature64Bit] && 328 (STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 329 (MI.getOperand(1).isReg()) && 330 (MI.getOperand(1).getReg() == RISCV::X0) && 331 (MI.getOperand(0).isReg()) && 332 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(0).getReg())) && 333 RISCVValidateMCOperandForCompress(MI.getOperand(2), STI, 3)) { 334 // c.li $rd, $imm 335 OutInst.setOpcode(RISCV::C_LI); 336 // Operand: rd 337 OutInst.addOperand(MI.getOperand(0)); 338 // Operand: imm 339 OutInst.addOperand(MI.getOperand(2)); 340 OutInst.setLoc(MI.getLoc()); 341 return true; 342 } // if 343 break; 344 } // case ADDIW 345 case RISCV::ADDW: { 346 if (STI.getFeatureBits()[RISCV::Feature64Bit] && 347 (STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 348 (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) && 349 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && 350 (MI.getOperand(1).isReg()) && 351 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) && 352 (MI.getOperand(2).isReg()) && 353 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(2).getReg()))) { 354 // c.addw $rd, $rs2 355 OutInst.setOpcode(RISCV::C_ADDW); 356 // Operand: rd_wb 357 OutInst.addOperand(MI.getOperand(1)); 358 // Operand: rd 359 OutInst.addOperand(MI.getOperand(1)); 360 // Operand: rs2 361 OutInst.addOperand(MI.getOperand(2)); 362 OutInst.setLoc(MI.getLoc()); 363 return true; 364 } // if 365 if (STI.getFeatureBits()[RISCV::Feature64Bit] && 366 (STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 367 (MI.getOperand(2).isReg()) && (MI.getOperand(0).isReg()) && 368 (MI.getOperand(2).getReg() == MI.getOperand(0).getReg()) && 369 (MI.getOperand(2).isReg()) && 370 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(2).getReg())) && 371 (MI.getOperand(1).isReg()) && 372 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg()))) { 373 // c.addw $rd, $rs2 374 OutInst.setOpcode(RISCV::C_ADDW); 375 // Operand: rd_wb 376 OutInst.addOperand(MI.getOperand(2)); 377 // Operand: rd 378 OutInst.addOperand(MI.getOperand(2)); 379 // Operand: rs2 380 OutInst.addOperand(MI.getOperand(1)); 381 OutInst.setLoc(MI.getLoc()); 382 return true; 383 } // if 384 break; 385 } // case ADDW 386 case RISCV::AND: { 387 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 388 (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) && 389 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && 390 (MI.getOperand(1).isReg()) && 391 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) && 392 (MI.getOperand(2).isReg()) && 393 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(2).getReg()))) { 394 // c.and $rd, $rs2 395 OutInst.setOpcode(RISCV::C_AND); 396 // Operand: rd_wb 397 OutInst.addOperand(MI.getOperand(1)); 398 // Operand: rd 399 OutInst.addOperand(MI.getOperand(1)); 400 // Operand: rs2 401 OutInst.addOperand(MI.getOperand(2)); 402 OutInst.setLoc(MI.getLoc()); 403 return true; 404 } // if 405 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 406 (MI.getOperand(2).isReg()) && (MI.getOperand(0).isReg()) && 407 (MI.getOperand(2).getReg() == MI.getOperand(0).getReg()) && 408 (MI.getOperand(2).isReg()) && 409 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(2).getReg())) && 410 (MI.getOperand(1).isReg()) && 411 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg()))) { 412 // c.and $rd, $rs2 413 OutInst.setOpcode(RISCV::C_AND); 414 // Operand: rd_wb 415 OutInst.addOperand(MI.getOperand(2)); 416 // Operand: rd 417 OutInst.addOperand(MI.getOperand(2)); 418 // Operand: rs2 419 OutInst.addOperand(MI.getOperand(1)); 420 OutInst.setLoc(MI.getLoc()); 421 return true; 422 } // if 423 break; 424 } // case AND 425 case RISCV::ANDI: { 426 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 427 (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) && 428 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && 429 (MI.getOperand(1).isReg()) && 430 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) && 431 RISCVValidateMCOperandForCompress(MI.getOperand(2), STI, 3)) { 432 // c.andi $rs1, $imm 433 OutInst.setOpcode(RISCV::C_ANDI); 434 // Operand: rs1_wb 435 OutInst.addOperand(MI.getOperand(1)); 436 // Operand: rs1 437 OutInst.addOperand(MI.getOperand(1)); 438 // Operand: imm 439 OutInst.addOperand(MI.getOperand(2)); 440 OutInst.setLoc(MI.getLoc()); 441 return true; 442 } // if 443 break; 444 } // case ANDI 445 case RISCV::BEQ: { 446 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 447 (MI.getOperand(1).isReg()) && 448 (MI.getOperand(1).getReg() == RISCV::X0) && 449 (MI.getOperand(0).isReg()) && 450 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(0).getReg())) && 451 RISCVValidateMCOperandForCompress(MI.getOperand(2), STI, 5)) { 452 // c.beqz $rs1, $imm 453 OutInst.setOpcode(RISCV::C_BEQZ); 454 // Operand: rs1 455 OutInst.addOperand(MI.getOperand(0)); 456 // Operand: imm 457 OutInst.addOperand(MI.getOperand(2)); 458 OutInst.setLoc(MI.getLoc()); 459 return true; 460 } // if 461 break; 462 } // case BEQ 463 case RISCV::BNE: { 464 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 465 (MI.getOperand(1).isReg()) && 466 (MI.getOperand(1).getReg() == RISCV::X0) && 467 (MI.getOperand(0).isReg()) && 468 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(0).getReg())) && 469 RISCVValidateMCOperandForCompress(MI.getOperand(2), STI, 5)) { 470 // c.bnez $rs1, $imm 471 OutInst.setOpcode(RISCV::C_BNEZ); 472 // Operand: rs1 473 OutInst.addOperand(MI.getOperand(0)); 474 // Operand: imm 475 OutInst.addOperand(MI.getOperand(2)); 476 OutInst.setLoc(MI.getLoc()); 477 return true; 478 } // if 479 break; 480 } // case BNE 481 case RISCV::EBREAK: { 482 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC])) { 483 // c.ebreak 484 OutInst.setOpcode(RISCV::C_EBREAK); 485 OutInst.setLoc(MI.getLoc()); 486 return true; 487 } // if 488 break; 489 } // case EBREAK 490 case RISCV::FLD: { 491 if (STI.getFeatureBits()[RISCV::FeatureStdExtD] && 492 (STI.getFeatureBits()[RISCV::FeatureExtZcd] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 493 (MI.getOperand(0).isReg()) && 494 (RISCVMCRegisterClasses[RISCV::FPR64CRegClassID].contains(MI.getOperand(0).getReg())) && 495 (MI.getOperand(1).isReg()) && 496 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) && 497 RISCVValidateMCOperandForCompress(MI.getOperand(2), STI, 6)) { 498 // c.fld $rd, ${imm}(${rs1}) 499 OutInst.setOpcode(RISCV::C_FLD); 500 // Operand: rd 501 OutInst.addOperand(MI.getOperand(0)); 502 // Operand: rs1 503 OutInst.addOperand(MI.getOperand(1)); 504 // Operand: imm 505 OutInst.addOperand(MI.getOperand(2)); 506 OutInst.setLoc(MI.getLoc()); 507 return true; 508 } // if 509 if (STI.getFeatureBits()[RISCV::FeatureStdExtD] && 510 (STI.getFeatureBits()[RISCV::FeatureExtZcd] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 511 (MI.getOperand(0).isReg()) && 512 (RISCVMCRegisterClasses[RISCV::FPR64RegClassID].contains(MI.getOperand(0).getReg())) && 513 (MI.getOperand(1).isReg()) && 514 (RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(1).getReg())) && 515 RISCVValidateMCOperandForCompress(MI.getOperand(2), STI, 7)) { 516 // c.fldsp $rd, ${imm}(${rs1}) 517 OutInst.setOpcode(RISCV::C_FLDSP); 518 // Operand: rd 519 OutInst.addOperand(MI.getOperand(0)); 520 // Operand: rs1 521 OutInst.addOperand(MI.getOperand(1)); 522 // Operand: imm 523 OutInst.addOperand(MI.getOperand(2)); 524 OutInst.setLoc(MI.getLoc()); 525 return true; 526 } // if 527 break; 528 } // case FLD 529 case RISCV::FLW: { 530 if (STI.getFeatureBits()[RISCV::FeatureStdExtF] && 531 !STI.getFeatureBits()[RISCV::Feature64Bit] && 532 (STI.getFeatureBits()[RISCV::FeatureExtZcf] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 533 (MI.getOperand(0).isReg()) && 534 (RISCVMCRegisterClasses[RISCV::FPR32CRegClassID].contains(MI.getOperand(0).getReg())) && 535 (MI.getOperand(1).isReg()) && 536 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) && 537 RISCVValidateMCOperandForCompress(MI.getOperand(2), STI, 8)) { 538 // c.flw $rd, ${imm}(${rs1}) 539 OutInst.setOpcode(RISCV::C_FLW); 540 // Operand: rd 541 OutInst.addOperand(MI.getOperand(0)); 542 // Operand: rs1 543 OutInst.addOperand(MI.getOperand(1)); 544 // Operand: imm 545 OutInst.addOperand(MI.getOperand(2)); 546 OutInst.setLoc(MI.getLoc()); 547 return true; 548 } // if 549 if (STI.getFeatureBits()[RISCV::FeatureStdExtF] && 550 !STI.getFeatureBits()[RISCV::Feature64Bit] && 551 (STI.getFeatureBits()[RISCV::FeatureExtZcf] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 552 (MI.getOperand(0).isReg()) && 553 (RISCVMCRegisterClasses[RISCV::FPR32RegClassID].contains(MI.getOperand(0).getReg())) && 554 (MI.getOperand(1).isReg()) && 555 (RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(1).getReg())) && 556 RISCVValidateMCOperandForCompress(MI.getOperand(2), STI, 9)) { 557 // c.flwsp $rd, ${imm}(${rs1}) 558 OutInst.setOpcode(RISCV::C_FLWSP); 559 // Operand: rd 560 OutInst.addOperand(MI.getOperand(0)); 561 // Operand: rs1 562 OutInst.addOperand(MI.getOperand(1)); 563 // Operand: imm 564 OutInst.addOperand(MI.getOperand(2)); 565 OutInst.setLoc(MI.getLoc()); 566 return true; 567 } // if 568 break; 569 } // case FLW 570 case RISCV::FSD: { 571 if (STI.getFeatureBits()[RISCV::FeatureStdExtD] && 572 (STI.getFeatureBits()[RISCV::FeatureExtZcd] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 573 (MI.getOperand(0).isReg()) && 574 (RISCVMCRegisterClasses[RISCV::FPR64CRegClassID].contains(MI.getOperand(0).getReg())) && 575 (MI.getOperand(1).isReg()) && 576 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) && 577 RISCVValidateMCOperandForCompress(MI.getOperand(2), STI, 6)) { 578 // c.fsd $rs2, ${imm}(${rs1}) 579 OutInst.setOpcode(RISCV::C_FSD); 580 // Operand: rs2 581 OutInst.addOperand(MI.getOperand(0)); 582 // Operand: rs1 583 OutInst.addOperand(MI.getOperand(1)); 584 // Operand: imm 585 OutInst.addOperand(MI.getOperand(2)); 586 OutInst.setLoc(MI.getLoc()); 587 return true; 588 } // if 589 if (STI.getFeatureBits()[RISCV::FeatureStdExtD] && 590 (STI.getFeatureBits()[RISCV::FeatureExtZcd] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 591 (MI.getOperand(0).isReg()) && 592 (RISCVMCRegisterClasses[RISCV::FPR64RegClassID].contains(MI.getOperand(0).getReg())) && 593 (MI.getOperand(1).isReg()) && 594 (RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(1).getReg())) && 595 RISCVValidateMCOperandForCompress(MI.getOperand(2), STI, 7)) { 596 // c.fsdsp $rs2, ${imm}(${rs1}) 597 OutInst.setOpcode(RISCV::C_FSDSP); 598 // Operand: rs2 599 OutInst.addOperand(MI.getOperand(0)); 600 // Operand: rs1 601 OutInst.addOperand(MI.getOperand(1)); 602 // Operand: imm 603 OutInst.addOperand(MI.getOperand(2)); 604 OutInst.setLoc(MI.getLoc()); 605 return true; 606 } // if 607 break; 608 } // case FSD 609 case RISCV::FSW: { 610 if (STI.getFeatureBits()[RISCV::FeatureStdExtF] && 611 !STI.getFeatureBits()[RISCV::Feature64Bit] && 612 (STI.getFeatureBits()[RISCV::FeatureExtZcf] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 613 (MI.getOperand(0).isReg()) && 614 (RISCVMCRegisterClasses[RISCV::FPR32CRegClassID].contains(MI.getOperand(0).getReg())) && 615 (MI.getOperand(1).isReg()) && 616 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) && 617 RISCVValidateMCOperandForCompress(MI.getOperand(2), STI, 8)) { 618 // c.fsw $rs2, ${imm}(${rs1}) 619 OutInst.setOpcode(RISCV::C_FSW); 620 // Operand: rs2 621 OutInst.addOperand(MI.getOperand(0)); 622 // Operand: rs1 623 OutInst.addOperand(MI.getOperand(1)); 624 // Operand: imm 625 OutInst.addOperand(MI.getOperand(2)); 626 OutInst.setLoc(MI.getLoc()); 627 return true; 628 } // if 629 if (STI.getFeatureBits()[RISCV::FeatureStdExtF] && 630 !STI.getFeatureBits()[RISCV::Feature64Bit] && 631 (STI.getFeatureBits()[RISCV::FeatureExtZcf] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 632 (MI.getOperand(0).isReg()) && 633 (RISCVMCRegisterClasses[RISCV::FPR32RegClassID].contains(MI.getOperand(0).getReg())) && 634 (MI.getOperand(1).isReg()) && 635 (RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(1).getReg())) && 636 RISCVValidateMCOperandForCompress(MI.getOperand(2), STI, 9)) { 637 // c.fswsp $rs2, ${imm}(${rs1}) 638 OutInst.setOpcode(RISCV::C_FSWSP); 639 // Operand: rs2 640 OutInst.addOperand(MI.getOperand(0)); 641 // Operand: rs1 642 OutInst.addOperand(MI.getOperand(1)); 643 // Operand: imm 644 OutInst.addOperand(MI.getOperand(2)); 645 OutInst.setLoc(MI.getLoc()); 646 return true; 647 } // if 648 break; 649 } // case FSW 650 case RISCV::JAL: { 651 if (!STI.getFeatureBits()[RISCV::Feature64Bit] && 652 (STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 653 (MI.getOperand(0).isReg()) && 654 (MI.getOperand(0).getReg() == RISCV::X1) && 655 RISCVValidateMCOperandForCompress(MI.getOperand(1), STI, 10)) { 656 // c.jal $offset 657 OutInst.setOpcode(RISCV::C_JAL); 658 // Operand: offset 659 OutInst.addOperand(MI.getOperand(1)); 660 OutInst.setLoc(MI.getLoc()); 661 return true; 662 } // if 663 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 664 (MI.getOperand(0).isReg()) && 665 (MI.getOperand(0).getReg() == RISCV::X0) && 666 RISCVValidateMCOperandForCompress(MI.getOperand(1), STI, 10)) { 667 // c.j $offset 668 OutInst.setOpcode(RISCV::C_J); 669 // Operand: offset 670 OutInst.addOperand(MI.getOperand(1)); 671 OutInst.setLoc(MI.getLoc()); 672 return true; 673 } // if 674 break; 675 } // case JAL 676 case RISCV::JALR: { 677 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 678 (MI.getOperand(0).isReg()) && 679 (MI.getOperand(0).getReg() == RISCV::X0) && 680 (MI.getOperand(2).isImm()) && 681 (MI.getOperand(2).getImm() == 0) && 682 (MI.getOperand(1).isReg()) && 683 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(1).getReg()))) { 684 // c.jr $rs1 685 OutInst.setOpcode(RISCV::C_JR); 686 // Operand: rs1 687 OutInst.addOperand(MI.getOperand(1)); 688 OutInst.setLoc(MI.getLoc()); 689 return true; 690 } // if 691 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 692 (MI.getOperand(0).isReg()) && 693 (MI.getOperand(0).getReg() == RISCV::X1) && 694 (MI.getOperand(2).isImm()) && 695 (MI.getOperand(2).getImm() == 0) && 696 (MI.getOperand(1).isReg()) && 697 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(1).getReg()))) { 698 // c.jalr $rs1 699 OutInst.setOpcode(RISCV::C_JALR); 700 // Operand: rs1 701 OutInst.addOperand(MI.getOperand(1)); 702 OutInst.setLoc(MI.getLoc()); 703 return true; 704 } // if 705 break; 706 } // case JALR 707 case RISCV::LD: { 708 if (STI.getFeatureBits()[RISCV::Feature64Bit] && 709 (STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 710 (MI.getOperand(0).isReg()) && 711 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(0).getReg())) && 712 (MI.getOperand(1).isReg()) && 713 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) && 714 RISCVValidateMCOperandForCompress(MI.getOperand(2), STI, 6)) { 715 // c.ld $rd, ${imm}(${rs1}) 716 OutInst.setOpcode(RISCV::C_LD); 717 // Operand: rd 718 OutInst.addOperand(MI.getOperand(0)); 719 // Operand: rs1 720 OutInst.addOperand(MI.getOperand(1)); 721 // Operand: imm 722 OutInst.addOperand(MI.getOperand(2)); 723 OutInst.setLoc(MI.getLoc()); 724 return true; 725 } // if 726 if (STI.getFeatureBits()[RISCV::Feature64Bit] && 727 (STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 728 (MI.getOperand(0).isReg()) && 729 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(0).getReg())) && 730 (MI.getOperand(1).isReg()) && 731 (RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(1).getReg())) && 732 RISCVValidateMCOperandForCompress(MI.getOperand(2), STI, 7)) { 733 // c.ldsp $rd, ${imm}(${rs1}) 734 OutInst.setOpcode(RISCV::C_LDSP); 735 // Operand: rd 736 OutInst.addOperand(MI.getOperand(0)); 737 // Operand: rs1 738 OutInst.addOperand(MI.getOperand(1)); 739 // Operand: imm 740 OutInst.addOperand(MI.getOperand(2)); 741 OutInst.setLoc(MI.getLoc()); 742 return true; 743 } // if 744 break; 745 } // case LD 746 case RISCV::LUI: { 747 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 748 (MI.getOperand(0).isReg()) && 749 (RISCVMCRegisterClasses[RISCV::GPRNoX0X2RegClassID].contains(MI.getOperand(0).getReg())) && 750 RISCVValidateMCOperandForCompress(MI.getOperand(1), STI, 11)) { 751 // c.lui $rd, $imm 752 OutInst.setOpcode(RISCV::C_LUI); 753 // Operand: rd 754 OutInst.addOperand(MI.getOperand(0)); 755 // Operand: imm 756 OutInst.addOperand(MI.getOperand(1)); 757 OutInst.setLoc(MI.getLoc()); 758 return true; 759 } // if 760 break; 761 } // case LUI 762 case RISCV::LW: { 763 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 764 (MI.getOperand(0).isReg()) && 765 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(0).getReg())) && 766 (MI.getOperand(1).isReg()) && 767 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) && 768 RISCVValidateMCOperandForCompress(MI.getOperand(2), STI, 8)) { 769 // c.lw $rd, ${imm}(${rs1}) 770 OutInst.setOpcode(RISCV::C_LW); 771 // Operand: rd 772 OutInst.addOperand(MI.getOperand(0)); 773 // Operand: rs1 774 OutInst.addOperand(MI.getOperand(1)); 775 // Operand: imm 776 OutInst.addOperand(MI.getOperand(2)); 777 OutInst.setLoc(MI.getLoc()); 778 return true; 779 } // if 780 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 781 (MI.getOperand(0).isReg()) && 782 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(0).getReg())) && 783 (MI.getOperand(1).isReg()) && 784 (RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(1).getReg())) && 785 RISCVValidateMCOperandForCompress(MI.getOperand(2), STI, 9)) { 786 // c.lwsp $rd, ${imm}(${rs1}) 787 OutInst.setOpcode(RISCV::C_LWSP); 788 // Operand: rd 789 OutInst.addOperand(MI.getOperand(0)); 790 // Operand: rs1 791 OutInst.addOperand(MI.getOperand(1)); 792 // Operand: imm 793 OutInst.addOperand(MI.getOperand(2)); 794 OutInst.setLoc(MI.getLoc()); 795 return true; 796 } // if 797 break; 798 } // case LW 799 case RISCV::OR: { 800 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 801 (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) && 802 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && 803 (MI.getOperand(1).isReg()) && 804 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) && 805 (MI.getOperand(2).isReg()) && 806 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(2).getReg()))) { 807 // c.or $rd, $rs2 808 OutInst.setOpcode(RISCV::C_OR); 809 // Operand: rd_wb 810 OutInst.addOperand(MI.getOperand(1)); 811 // Operand: rd 812 OutInst.addOperand(MI.getOperand(1)); 813 // Operand: rs2 814 OutInst.addOperand(MI.getOperand(2)); 815 OutInst.setLoc(MI.getLoc()); 816 return true; 817 } // if 818 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 819 (MI.getOperand(2).isReg()) && (MI.getOperand(0).isReg()) && 820 (MI.getOperand(2).getReg() == MI.getOperand(0).getReg()) && 821 (MI.getOperand(2).isReg()) && 822 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(2).getReg())) && 823 (MI.getOperand(1).isReg()) && 824 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg()))) { 825 // c.or $rd, $rs2 826 OutInst.setOpcode(RISCV::C_OR); 827 // Operand: rd_wb 828 OutInst.addOperand(MI.getOperand(2)); 829 // Operand: rd 830 OutInst.addOperand(MI.getOperand(2)); 831 // Operand: rs2 832 OutInst.addOperand(MI.getOperand(1)); 833 OutInst.setLoc(MI.getLoc()); 834 return true; 835 } // if 836 break; 837 } // case OR 838 case RISCV::SD: { 839 if (STI.getFeatureBits()[RISCV::Feature64Bit] && 840 (STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 841 (MI.getOperand(0).isReg()) && 842 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(0).getReg())) && 843 (MI.getOperand(1).isReg()) && 844 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) && 845 RISCVValidateMCOperandForCompress(MI.getOperand(2), STI, 6)) { 846 // c.sd $rs2, ${imm}(${rs1}) 847 OutInst.setOpcode(RISCV::C_SD); 848 // Operand: rs2 849 OutInst.addOperand(MI.getOperand(0)); 850 // Operand: rs1 851 OutInst.addOperand(MI.getOperand(1)); 852 // Operand: imm 853 OutInst.addOperand(MI.getOperand(2)); 854 OutInst.setLoc(MI.getLoc()); 855 return true; 856 } // if 857 if (STI.getFeatureBits()[RISCV::Feature64Bit] && 858 (STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 859 (MI.getOperand(0).isReg()) && 860 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) && 861 (MI.getOperand(1).isReg()) && 862 (RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(1).getReg())) && 863 RISCVValidateMCOperandForCompress(MI.getOperand(2), STI, 7)) { 864 // c.sdsp $rs2, ${imm}(${rs1}) 865 OutInst.setOpcode(RISCV::C_SDSP); 866 // Operand: rs2 867 OutInst.addOperand(MI.getOperand(0)); 868 // Operand: rs1 869 OutInst.addOperand(MI.getOperand(1)); 870 // Operand: imm 871 OutInst.addOperand(MI.getOperand(2)); 872 OutInst.setLoc(MI.getLoc()); 873 return true; 874 } // if 875 break; 876 } // case SD 877 case RISCV::SLLI: { 878 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 879 (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) && 880 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && 881 (MI.getOperand(1).isReg()) && 882 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(1).getReg())) && 883 RISCVValidateMCOperandForCompress(MI.getOperand(2), STI, 12)) { 884 // c.slli $rd, $imm 885 OutInst.setOpcode(RISCV::C_SLLI); 886 // Operand: rd_wb 887 OutInst.addOperand(MI.getOperand(1)); 888 // Operand: rd 889 OutInst.addOperand(MI.getOperand(1)); 890 // Operand: imm 891 OutInst.addOperand(MI.getOperand(2)); 892 OutInst.setLoc(MI.getLoc()); 893 return true; 894 } // if 895 break; 896 } // case SLLI 897 case RISCV::SRAI: { 898 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 899 (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) && 900 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && 901 (MI.getOperand(1).isReg()) && 902 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) && 903 RISCVValidateMCOperandForCompress(MI.getOperand(2), STI, 12)) { 904 // c.srai $rs1, $imm 905 OutInst.setOpcode(RISCV::C_SRAI); 906 // Operand: rs1_wb 907 OutInst.addOperand(MI.getOperand(1)); 908 // Operand: rs1 909 OutInst.addOperand(MI.getOperand(1)); 910 // Operand: imm 911 OutInst.addOperand(MI.getOperand(2)); 912 OutInst.setLoc(MI.getLoc()); 913 return true; 914 } // if 915 break; 916 } // case SRAI 917 case RISCV::SRLI: { 918 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 919 (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) && 920 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && 921 (MI.getOperand(1).isReg()) && 922 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) && 923 RISCVValidateMCOperandForCompress(MI.getOperand(2), STI, 12)) { 924 // c.srli $rs1, $imm 925 OutInst.setOpcode(RISCV::C_SRLI); 926 // Operand: rs1_wb 927 OutInst.addOperand(MI.getOperand(1)); 928 // Operand: rs1 929 OutInst.addOperand(MI.getOperand(1)); 930 // Operand: imm 931 OutInst.addOperand(MI.getOperand(2)); 932 OutInst.setLoc(MI.getLoc()); 933 return true; 934 } // if 935 break; 936 } // case SRLI 937 case RISCV::SUB: { 938 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 939 (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) && 940 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && 941 (MI.getOperand(1).isReg()) && 942 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) && 943 (MI.getOperand(2).isReg()) && 944 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(2).getReg()))) { 945 // c.sub $rd, $rs2 946 OutInst.setOpcode(RISCV::C_SUB); 947 // Operand: rd_wb 948 OutInst.addOperand(MI.getOperand(1)); 949 // Operand: rd 950 OutInst.addOperand(MI.getOperand(1)); 951 // Operand: rs2 952 OutInst.addOperand(MI.getOperand(2)); 953 OutInst.setLoc(MI.getLoc()); 954 return true; 955 } // if 956 break; 957 } // case SUB 958 case RISCV::SUBW: { 959 if (STI.getFeatureBits()[RISCV::Feature64Bit] && 960 (STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 961 (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) && 962 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && 963 (MI.getOperand(1).isReg()) && 964 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) && 965 (MI.getOperand(2).isReg()) && 966 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(2).getReg()))) { 967 // c.subw $rd, $rs2 968 OutInst.setOpcode(RISCV::C_SUBW); 969 // Operand: rd_wb 970 OutInst.addOperand(MI.getOperand(1)); 971 // Operand: rd 972 OutInst.addOperand(MI.getOperand(1)); 973 // Operand: rs2 974 OutInst.addOperand(MI.getOperand(2)); 975 OutInst.setLoc(MI.getLoc()); 976 return true; 977 } // if 978 break; 979 } // case SUBW 980 case RISCV::SW: { 981 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 982 (MI.getOperand(0).isReg()) && 983 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(0).getReg())) && 984 (MI.getOperand(1).isReg()) && 985 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) && 986 RISCVValidateMCOperandForCompress(MI.getOperand(2), STI, 8)) { 987 // c.sw $rs2, ${imm}(${rs1}) 988 OutInst.setOpcode(RISCV::C_SW); 989 // Operand: rs2 990 OutInst.addOperand(MI.getOperand(0)); 991 // Operand: rs1 992 OutInst.addOperand(MI.getOperand(1)); 993 // Operand: imm 994 OutInst.addOperand(MI.getOperand(2)); 995 OutInst.setLoc(MI.getLoc()); 996 return true; 997 } // if 998 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 999 (MI.getOperand(0).isReg()) && 1000 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) && 1001 (MI.getOperand(1).isReg()) && 1002 (RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(1).getReg())) && 1003 RISCVValidateMCOperandForCompress(MI.getOperand(2), STI, 9)) { 1004 // c.swsp $rs2, ${imm}(${rs1}) 1005 OutInst.setOpcode(RISCV::C_SWSP); 1006 // Operand: rs2 1007 OutInst.addOperand(MI.getOperand(0)); 1008 // Operand: rs1 1009 OutInst.addOperand(MI.getOperand(1)); 1010 // Operand: imm 1011 OutInst.addOperand(MI.getOperand(2)); 1012 OutInst.setLoc(MI.getLoc()); 1013 return true; 1014 } // if 1015 break; 1016 } // case SW 1017 case RISCV::UNIMP: { 1018 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC])) { 1019 // c.unimp 1020 OutInst.setOpcode(RISCV::C_UNIMP); 1021 OutInst.setLoc(MI.getLoc()); 1022 return true; 1023 } // if 1024 break; 1025 } // case UNIMP 1026 case RISCV::XOR: { 1027 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 1028 (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) && 1029 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && 1030 (MI.getOperand(1).isReg()) && 1031 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) && 1032 (MI.getOperand(2).isReg()) && 1033 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(2).getReg()))) { 1034 // c.xor $rd, $rs2 1035 OutInst.setOpcode(RISCV::C_XOR); 1036 // Operand: rd_wb 1037 OutInst.addOperand(MI.getOperand(1)); 1038 // Operand: rd 1039 OutInst.addOperand(MI.getOperand(1)); 1040 // Operand: rs2 1041 OutInst.addOperand(MI.getOperand(2)); 1042 OutInst.setLoc(MI.getLoc()); 1043 return true; 1044 } // if 1045 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 1046 (MI.getOperand(2).isReg()) && (MI.getOperand(0).isReg()) && 1047 (MI.getOperand(2).getReg() == MI.getOperand(0).getReg()) && 1048 (MI.getOperand(2).isReg()) && 1049 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(2).getReg())) && 1050 (MI.getOperand(1).isReg()) && 1051 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg()))) { 1052 // c.xor $rd, $rs2 1053 OutInst.setOpcode(RISCV::C_XOR); 1054 // Operand: rd_wb 1055 OutInst.addOperand(MI.getOperand(2)); 1056 // Operand: rd 1057 OutInst.addOperand(MI.getOperand(2)); 1058 // Operand: rs2 1059 OutInst.addOperand(MI.getOperand(1)); 1060 OutInst.setLoc(MI.getLoc()); 1061 return true; 1062 } // if 1063 1064 } // case XOR 1065 } // switch 1066 return false; 1067} 1068 1069#endif //GEN_COMPRESS_INSTR 1070 1071#ifdef GEN_UNCOMPRESS_INSTR 1072#undef GEN_UNCOMPRESS_INSTR 1073 1074static bool RISCVValidateMCOperandForUncompress(const MCOperand &MCOp, 1075 const MCSubtargetInfo &STI, 1076 unsigned PredicateIndex) { 1077 switch (PredicateIndex) { 1078 default: 1079 llvm_unreachable("Unknown MCOperandPredicate kind"); 1080 break; 1081 case 1: { 1082 // simm12 1083 1084 int64_t Imm; 1085 if (MCOp.evaluateAsConstantImm(Imm)) 1086 return isInt<12>(Imm); 1087 return MCOp.isBareSymbolRef(); 1088 1089 } 1090 case 2: { 1091 // simm13_lsb0 1092 1093 int64_t Imm; 1094 if (MCOp.evaluateAsConstantImm(Imm)) 1095 return isShiftedInt<12, 1>(Imm); 1096 return MCOp.isBareSymbolRef(); 1097 1098 } 1099 case 3: { 1100 // simm21_lsb0_jal 1101 1102 int64_t Imm; 1103 if (MCOp.evaluateAsConstantImm(Imm)) 1104 return isShiftedInt<20, 1>(Imm); 1105 return MCOp.isBareSymbolRef(); 1106 1107 } 1108 case 4: { 1109 // uimm20_lui 1110 1111 int64_t Imm; 1112 if (MCOp.evaluateAsConstantImm(Imm)) 1113 return isUInt<20>(Imm); 1114 return MCOp.isBareSymbolRef(); 1115 1116 } 1117 case 5: { 1118 // uimmlog2xlen 1119 1120 int64_t Imm; 1121 if (!MCOp.evaluateAsConstantImm(Imm)) 1122 return false; 1123 if (STI.getTargetTriple().isArch64Bit()) 1124 return isUInt<6>(Imm); 1125 return isUInt<5>(Imm); 1126 1127 } 1128 } 1129} 1130 1131static bool uncompressInst(MCInst &OutInst, 1132 const MCInst &MI, 1133 const MCSubtargetInfo &STI) { 1134 switch (MI.getOpcode()) { 1135 default: return false; 1136 case RISCV::C_ADD: { 1137 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 1138 (MI.getOperand(0).isReg()) && 1139 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) && 1140 (MI.getOperand(0).isReg()) && 1141 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) && 1142 (MI.getOperand(2).isReg()) && 1143 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(2).getReg()))) { 1144 // add $rd, $rs1, $rs2 1145 OutInst.setOpcode(RISCV::ADD); 1146 // Operand: rd 1147 OutInst.addOperand(MI.getOperand(0)); 1148 // Operand: rs1 1149 OutInst.addOperand(MI.getOperand(0)); 1150 // Operand: rs2 1151 OutInst.addOperand(MI.getOperand(2)); 1152 OutInst.setLoc(MI.getLoc()); 1153 return true; 1154 } // if 1155 break; 1156 } // case C_ADD 1157 case RISCV::C_ADDI: { 1158 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 1159 (MI.getOperand(0).isReg()) && 1160 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) && 1161 (MI.getOperand(0).isReg()) && 1162 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) && 1163 RISCVValidateMCOperandForUncompress(MI.getOperand(2), STI, 1)) { 1164 // addi $rd, $rs1, $imm12 1165 OutInst.setOpcode(RISCV::ADDI); 1166 // Operand: rd 1167 OutInst.addOperand(MI.getOperand(0)); 1168 // Operand: rs1 1169 OutInst.addOperand(MI.getOperand(0)); 1170 // Operand: imm12 1171 OutInst.addOperand(MI.getOperand(2)); 1172 OutInst.setLoc(MI.getLoc()); 1173 return true; 1174 } // if 1175 break; 1176 } // case C_ADDI 1177 case RISCV::C_ADDI16SP: { 1178 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 1179 (MI.getOperand(0).isReg()) && 1180 (MI.getOperand(0).getReg() == RISCV::X2) && 1181 (MI.getOperand(1).isReg()) && 1182 (MI.getOperand(1).getReg() == RISCV::X2) && 1183 RISCVValidateMCOperandForUncompress(MI.getOperand(2), STI, 1)) { 1184 // addi $rd, $rs1, $imm12 1185 OutInst.setOpcode(RISCV::ADDI); 1186 // Operand: rd 1187 OutInst.addOperand(MCOperand::createReg(RISCV::X2)); 1188 // Operand: rs1 1189 OutInst.addOperand(MCOperand::createReg(RISCV::X2)); 1190 // Operand: imm12 1191 OutInst.addOperand(MI.getOperand(2)); 1192 OutInst.setLoc(MI.getLoc()); 1193 return true; 1194 } // if 1195 break; 1196 } // case C_ADDI16SP 1197 case RISCV::C_ADDI4SPN: { 1198 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 1199 (MI.getOperand(0).isReg()) && 1200 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) && 1201 (MI.getOperand(1).isReg()) && 1202 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(1).getReg())) && 1203 RISCVValidateMCOperandForUncompress(MI.getOperand(2), STI, 1)) { 1204 // addi $rd, $rs1, $imm12 1205 OutInst.setOpcode(RISCV::ADDI); 1206 // Operand: rd 1207 OutInst.addOperand(MI.getOperand(0)); 1208 // Operand: rs1 1209 OutInst.addOperand(MI.getOperand(1)); 1210 // Operand: imm12 1211 OutInst.addOperand(MI.getOperand(2)); 1212 OutInst.setLoc(MI.getLoc()); 1213 return true; 1214 } // if 1215 break; 1216 } // case C_ADDI4SPN 1217 case RISCV::C_ADDIW: { 1218 if (STI.getFeatureBits()[RISCV::Feature64Bit] && 1219 (STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 1220 (MI.getOperand(0).isReg()) && 1221 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) && 1222 (MI.getOperand(0).isReg()) && 1223 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) && 1224 RISCVValidateMCOperandForUncompress(MI.getOperand(2), STI, 1)) { 1225 // addiw $rd, $rs1, $imm12 1226 OutInst.setOpcode(RISCV::ADDIW); 1227 // Operand: rd 1228 OutInst.addOperand(MI.getOperand(0)); 1229 // Operand: rs1 1230 OutInst.addOperand(MI.getOperand(0)); 1231 // Operand: imm12 1232 OutInst.addOperand(MI.getOperand(2)); 1233 OutInst.setLoc(MI.getLoc()); 1234 return true; 1235 } // if 1236 break; 1237 } // case C_ADDIW 1238 case RISCV::C_ADDW: { 1239 if (STI.getFeatureBits()[RISCV::Feature64Bit] && 1240 (STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 1241 (MI.getOperand(0).isReg()) && 1242 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) && 1243 (MI.getOperand(0).isReg()) && 1244 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) && 1245 (MI.getOperand(2).isReg()) && 1246 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(2).getReg()))) { 1247 // addw $rd, $rs1, $rs2 1248 OutInst.setOpcode(RISCV::ADDW); 1249 // Operand: rd 1250 OutInst.addOperand(MI.getOperand(0)); 1251 // Operand: rs1 1252 OutInst.addOperand(MI.getOperand(0)); 1253 // Operand: rs2 1254 OutInst.addOperand(MI.getOperand(2)); 1255 OutInst.setLoc(MI.getLoc()); 1256 return true; 1257 } // if 1258 break; 1259 } // case C_ADDW 1260 case RISCV::C_AND: { 1261 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 1262 (MI.getOperand(0).isReg()) && 1263 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) && 1264 (MI.getOperand(0).isReg()) && 1265 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) && 1266 (MI.getOperand(2).isReg()) && 1267 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(2).getReg()))) { 1268 // and $rd, $rs1, $rs2 1269 OutInst.setOpcode(RISCV::AND); 1270 // Operand: rd 1271 OutInst.addOperand(MI.getOperand(0)); 1272 // Operand: rs1 1273 OutInst.addOperand(MI.getOperand(0)); 1274 // Operand: rs2 1275 OutInst.addOperand(MI.getOperand(2)); 1276 OutInst.setLoc(MI.getLoc()); 1277 return true; 1278 } // if 1279 break; 1280 } // case C_AND 1281 case RISCV::C_ANDI: { 1282 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 1283 (MI.getOperand(0).isReg()) && 1284 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) && 1285 (MI.getOperand(0).isReg()) && 1286 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) && 1287 RISCVValidateMCOperandForUncompress(MI.getOperand(2), STI, 1)) { 1288 // andi $rd, $rs1, $imm12 1289 OutInst.setOpcode(RISCV::ANDI); 1290 // Operand: rd 1291 OutInst.addOperand(MI.getOperand(0)); 1292 // Operand: rs1 1293 OutInst.addOperand(MI.getOperand(0)); 1294 // Operand: imm12 1295 OutInst.addOperand(MI.getOperand(2)); 1296 OutInst.setLoc(MI.getLoc()); 1297 return true; 1298 } // if 1299 break; 1300 } // case C_ANDI 1301 case RISCV::C_BEQZ: { 1302 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 1303 (MI.getOperand(0).isReg()) && 1304 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) && 1305 RISCVValidateMCOperandForUncompress(MI.getOperand(1), STI, 2)) { 1306 // beq $rs1, $rs2, $imm12 1307 OutInst.setOpcode(RISCV::BEQ); 1308 // Operand: rs1 1309 OutInst.addOperand(MI.getOperand(0)); 1310 // Operand: rs2 1311 OutInst.addOperand(MCOperand::createReg(RISCV::X0)); 1312 // Operand: imm12 1313 OutInst.addOperand(MI.getOperand(1)); 1314 OutInst.setLoc(MI.getLoc()); 1315 return true; 1316 } // if 1317 break; 1318 } // case C_BEQZ 1319 case RISCV::C_BNEZ: { 1320 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 1321 (MI.getOperand(0).isReg()) && 1322 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) && 1323 RISCVValidateMCOperandForUncompress(MI.getOperand(1), STI, 2)) { 1324 // bne $rs1, $rs2, $imm12 1325 OutInst.setOpcode(RISCV::BNE); 1326 // Operand: rs1 1327 OutInst.addOperand(MI.getOperand(0)); 1328 // Operand: rs2 1329 OutInst.addOperand(MCOperand::createReg(RISCV::X0)); 1330 // Operand: imm12 1331 OutInst.addOperand(MI.getOperand(1)); 1332 OutInst.setLoc(MI.getLoc()); 1333 return true; 1334 } // if 1335 break; 1336 } // case C_BNEZ 1337 case RISCV::C_EBREAK: { 1338 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC])) { 1339 // ebreak 1340 OutInst.setOpcode(RISCV::EBREAK); 1341 OutInst.setLoc(MI.getLoc()); 1342 return true; 1343 } // if 1344 break; 1345 } // case C_EBREAK 1346 case RISCV::C_FLD: { 1347 if (STI.getFeatureBits()[RISCV::FeatureStdExtD] && 1348 (STI.getFeatureBits()[RISCV::FeatureExtZcd] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 1349 (MI.getOperand(0).isReg()) && 1350 (RISCVMCRegisterClasses[RISCV::FPR64RegClassID].contains(MI.getOperand(0).getReg())) && 1351 (MI.getOperand(1).isReg()) && 1352 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(1).getReg())) && 1353 RISCVValidateMCOperandForUncompress(MI.getOperand(2), STI, 1)) { 1354 // fld $rd, ${imm12}(${rs1}) 1355 OutInst.setOpcode(RISCV::FLD); 1356 // Operand: rd 1357 OutInst.addOperand(MI.getOperand(0)); 1358 // Operand: rs1 1359 OutInst.addOperand(MI.getOperand(1)); 1360 // Operand: imm12 1361 OutInst.addOperand(MI.getOperand(2)); 1362 OutInst.setLoc(MI.getLoc()); 1363 return true; 1364 } // if 1365 break; 1366 } // case C_FLD 1367 case RISCV::C_FLDSP: { 1368 if (STI.getFeatureBits()[RISCV::FeatureStdExtD] && 1369 (STI.getFeatureBits()[RISCV::FeatureExtZcd] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 1370 (MI.getOperand(0).isReg()) && 1371 (RISCVMCRegisterClasses[RISCV::FPR64RegClassID].contains(MI.getOperand(0).getReg())) && 1372 (MI.getOperand(1).isReg()) && 1373 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(1).getReg())) && 1374 RISCVValidateMCOperandForUncompress(MI.getOperand(2), STI, 1)) { 1375 // fld $rd, ${imm12}(${rs1}) 1376 OutInst.setOpcode(RISCV::FLD); 1377 // Operand: rd 1378 OutInst.addOperand(MI.getOperand(0)); 1379 // Operand: rs1 1380 OutInst.addOperand(MI.getOperand(1)); 1381 // Operand: imm12 1382 OutInst.addOperand(MI.getOperand(2)); 1383 OutInst.setLoc(MI.getLoc()); 1384 return true; 1385 } // if 1386 break; 1387 } // case C_FLDSP 1388 case RISCV::C_FLW: { 1389 if (STI.getFeatureBits()[RISCV::FeatureStdExtF] && 1390 !STI.getFeatureBits()[RISCV::Feature64Bit] && 1391 (STI.getFeatureBits()[RISCV::FeatureExtZcf] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 1392 (MI.getOperand(0).isReg()) && 1393 (RISCVMCRegisterClasses[RISCV::FPR32RegClassID].contains(MI.getOperand(0).getReg())) && 1394 (MI.getOperand(1).isReg()) && 1395 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(1).getReg())) && 1396 RISCVValidateMCOperandForUncompress(MI.getOperand(2), STI, 1)) { 1397 // flw $rd, ${imm12}(${rs1}) 1398 OutInst.setOpcode(RISCV::FLW); 1399 // Operand: rd 1400 OutInst.addOperand(MI.getOperand(0)); 1401 // Operand: rs1 1402 OutInst.addOperand(MI.getOperand(1)); 1403 // Operand: imm12 1404 OutInst.addOperand(MI.getOperand(2)); 1405 OutInst.setLoc(MI.getLoc()); 1406 return true; 1407 } // if 1408 break; 1409 } // case C_FLW 1410 case RISCV::C_FLWSP: { 1411 if (STI.getFeatureBits()[RISCV::FeatureStdExtF] && 1412 !STI.getFeatureBits()[RISCV::Feature64Bit] && 1413 (STI.getFeatureBits()[RISCV::FeatureExtZcf] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 1414 (MI.getOperand(0).isReg()) && 1415 (RISCVMCRegisterClasses[RISCV::FPR32RegClassID].contains(MI.getOperand(0).getReg())) && 1416 (MI.getOperand(1).isReg()) && 1417 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(1).getReg())) && 1418 RISCVValidateMCOperandForUncompress(MI.getOperand(2), STI, 1)) { 1419 // flw $rd, ${imm12}(${rs1}) 1420 OutInst.setOpcode(RISCV::FLW); 1421 // Operand: rd 1422 OutInst.addOperand(MI.getOperand(0)); 1423 // Operand: rs1 1424 OutInst.addOperand(MI.getOperand(1)); 1425 // Operand: imm12 1426 OutInst.addOperand(MI.getOperand(2)); 1427 OutInst.setLoc(MI.getLoc()); 1428 return true; 1429 } // if 1430 break; 1431 } // case C_FLWSP 1432 case RISCV::C_FSD: { 1433 if (STI.getFeatureBits()[RISCV::FeatureStdExtD] && 1434 (STI.getFeatureBits()[RISCV::FeatureExtZcd] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 1435 (MI.getOperand(0).isReg()) && 1436 (RISCVMCRegisterClasses[RISCV::FPR64RegClassID].contains(MI.getOperand(0).getReg())) && 1437 (MI.getOperand(1).isReg()) && 1438 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(1).getReg())) && 1439 RISCVValidateMCOperandForUncompress(MI.getOperand(2), STI, 1)) { 1440 // fsd $rs2, ${imm12}(${rs1}) 1441 OutInst.setOpcode(RISCV::FSD); 1442 // Operand: rs2 1443 OutInst.addOperand(MI.getOperand(0)); 1444 // Operand: rs1 1445 OutInst.addOperand(MI.getOperand(1)); 1446 // Operand: imm12 1447 OutInst.addOperand(MI.getOperand(2)); 1448 OutInst.setLoc(MI.getLoc()); 1449 return true; 1450 } // if 1451 break; 1452 } // case C_FSD 1453 case RISCV::C_FSDSP: { 1454 if (STI.getFeatureBits()[RISCV::FeatureStdExtD] && 1455 (STI.getFeatureBits()[RISCV::FeatureExtZcd] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 1456 (MI.getOperand(0).isReg()) && 1457 (RISCVMCRegisterClasses[RISCV::FPR64RegClassID].contains(MI.getOperand(0).getReg())) && 1458 (MI.getOperand(1).isReg()) && 1459 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(1).getReg())) && 1460 RISCVValidateMCOperandForUncompress(MI.getOperand(2), STI, 1)) { 1461 // fsd $rs2, ${imm12}(${rs1}) 1462 OutInst.setOpcode(RISCV::FSD); 1463 // Operand: rs2 1464 OutInst.addOperand(MI.getOperand(0)); 1465 // Operand: rs1 1466 OutInst.addOperand(MI.getOperand(1)); 1467 // Operand: imm12 1468 OutInst.addOperand(MI.getOperand(2)); 1469 OutInst.setLoc(MI.getLoc()); 1470 return true; 1471 } // if 1472 break; 1473 } // case C_FSDSP 1474 case RISCV::C_FSW: { 1475 if (STI.getFeatureBits()[RISCV::FeatureStdExtF] && 1476 !STI.getFeatureBits()[RISCV::Feature64Bit] && 1477 (STI.getFeatureBits()[RISCV::FeatureExtZcf] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 1478 (MI.getOperand(0).isReg()) && 1479 (RISCVMCRegisterClasses[RISCV::FPR32RegClassID].contains(MI.getOperand(0).getReg())) && 1480 (MI.getOperand(1).isReg()) && 1481 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(1).getReg())) && 1482 RISCVValidateMCOperandForUncompress(MI.getOperand(2), STI, 1)) { 1483 // fsw $rs2, ${imm12}(${rs1}) 1484 OutInst.setOpcode(RISCV::FSW); 1485 // Operand: rs2 1486 OutInst.addOperand(MI.getOperand(0)); 1487 // Operand: rs1 1488 OutInst.addOperand(MI.getOperand(1)); 1489 // Operand: imm12 1490 OutInst.addOperand(MI.getOperand(2)); 1491 OutInst.setLoc(MI.getLoc()); 1492 return true; 1493 } // if 1494 break; 1495 } // case C_FSW 1496 case RISCV::C_FSWSP: { 1497 if (STI.getFeatureBits()[RISCV::FeatureStdExtF] && 1498 !STI.getFeatureBits()[RISCV::Feature64Bit] && 1499 (STI.getFeatureBits()[RISCV::FeatureExtZcf] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 1500 (MI.getOperand(0).isReg()) && 1501 (RISCVMCRegisterClasses[RISCV::FPR32RegClassID].contains(MI.getOperand(0).getReg())) && 1502 (MI.getOperand(1).isReg()) && 1503 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(1).getReg())) && 1504 RISCVValidateMCOperandForUncompress(MI.getOperand(2), STI, 1)) { 1505 // fsw $rs2, ${imm12}(${rs1}) 1506 OutInst.setOpcode(RISCV::FSW); 1507 // Operand: rs2 1508 OutInst.addOperand(MI.getOperand(0)); 1509 // Operand: rs1 1510 OutInst.addOperand(MI.getOperand(1)); 1511 // Operand: imm12 1512 OutInst.addOperand(MI.getOperand(2)); 1513 OutInst.setLoc(MI.getLoc()); 1514 return true; 1515 } // if 1516 break; 1517 } // case C_FSWSP 1518 case RISCV::C_J: { 1519 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 1520 RISCVValidateMCOperandForUncompress(MI.getOperand(0), STI, 3)) { 1521 // jal $rd, $imm20 1522 OutInst.setOpcode(RISCV::JAL); 1523 // Operand: rd 1524 OutInst.addOperand(MCOperand::createReg(RISCV::X0)); 1525 // Operand: imm20 1526 OutInst.addOperand(MI.getOperand(0)); 1527 OutInst.setLoc(MI.getLoc()); 1528 return true; 1529 } // if 1530 break; 1531 } // case C_J 1532 case RISCV::C_JAL: { 1533 if (!STI.getFeatureBits()[RISCV::Feature64Bit] && 1534 (STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 1535 RISCVValidateMCOperandForUncompress(MI.getOperand(0), STI, 3)) { 1536 // jal $rd, $imm20 1537 OutInst.setOpcode(RISCV::JAL); 1538 // Operand: rd 1539 OutInst.addOperand(MCOperand::createReg(RISCV::X1)); 1540 // Operand: imm20 1541 OutInst.addOperand(MI.getOperand(0)); 1542 OutInst.setLoc(MI.getLoc()); 1543 return true; 1544 } // if 1545 break; 1546 } // case C_JAL 1547 case RISCV::C_JALR: { 1548 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 1549 (MI.getOperand(0).isReg()) && 1550 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) && 1551 RISCVValidateMCOperandForUncompress(MCOperand::createImm(0), STI, 1)) { 1552 // jalr $rd, ${imm12}(${rs1}) 1553 OutInst.setOpcode(RISCV::JALR); 1554 // Operand: rd 1555 OutInst.addOperand(MCOperand::createReg(RISCV::X1)); 1556 // Operand: rs1 1557 OutInst.addOperand(MI.getOperand(0)); 1558 // Operand: imm12 1559 OutInst.addOperand(MCOperand::createImm(0)); 1560 OutInst.setLoc(MI.getLoc()); 1561 return true; 1562 } // if 1563 break; 1564 } // case C_JALR 1565 case RISCV::C_JR: { 1566 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 1567 (MI.getOperand(0).isReg()) && 1568 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) && 1569 RISCVValidateMCOperandForUncompress(MCOperand::createImm(0), STI, 1)) { 1570 // jalr $rd, ${imm12}(${rs1}) 1571 OutInst.setOpcode(RISCV::JALR); 1572 // Operand: rd 1573 OutInst.addOperand(MCOperand::createReg(RISCV::X0)); 1574 // Operand: rs1 1575 OutInst.addOperand(MI.getOperand(0)); 1576 // Operand: imm12 1577 OutInst.addOperand(MCOperand::createImm(0)); 1578 OutInst.setLoc(MI.getLoc()); 1579 return true; 1580 } // if 1581 break; 1582 } // case C_JR 1583 case RISCV::C_LD: { 1584 if (STI.getFeatureBits()[RISCV::Feature64Bit] && 1585 (STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 1586 (MI.getOperand(0).isReg()) && 1587 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) && 1588 (MI.getOperand(1).isReg()) && 1589 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(1).getReg())) && 1590 RISCVValidateMCOperandForUncompress(MI.getOperand(2), STI, 1)) { 1591 // ld $rd, ${imm12}(${rs1}) 1592 OutInst.setOpcode(RISCV::LD); 1593 // Operand: rd 1594 OutInst.addOperand(MI.getOperand(0)); 1595 // Operand: rs1 1596 OutInst.addOperand(MI.getOperand(1)); 1597 // Operand: imm12 1598 OutInst.addOperand(MI.getOperand(2)); 1599 OutInst.setLoc(MI.getLoc()); 1600 return true; 1601 } // if 1602 break; 1603 } // case C_LD 1604 case RISCV::C_LDSP: { 1605 if (STI.getFeatureBits()[RISCV::Feature64Bit] && 1606 (STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 1607 (MI.getOperand(0).isReg()) && 1608 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) && 1609 (MI.getOperand(1).isReg()) && 1610 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(1).getReg())) && 1611 RISCVValidateMCOperandForUncompress(MI.getOperand(2), STI, 1)) { 1612 // ld $rd, ${imm12}(${rs1}) 1613 OutInst.setOpcode(RISCV::LD); 1614 // Operand: rd 1615 OutInst.addOperand(MI.getOperand(0)); 1616 // Operand: rs1 1617 OutInst.addOperand(MI.getOperand(1)); 1618 // Operand: imm12 1619 OutInst.addOperand(MI.getOperand(2)); 1620 OutInst.setLoc(MI.getLoc()); 1621 return true; 1622 } // if 1623 break; 1624 } // case C_LDSP 1625 case RISCV::C_LI: { 1626 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 1627 (MI.getOperand(0).isReg()) && 1628 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) && 1629 RISCVValidateMCOperandForUncompress(MI.getOperand(1), STI, 1)) { 1630 // addi $rd, $rs1, $imm12 1631 OutInst.setOpcode(RISCV::ADDI); 1632 // Operand: rd 1633 OutInst.addOperand(MI.getOperand(0)); 1634 // Operand: rs1 1635 OutInst.addOperand(MCOperand::createReg(RISCV::X0)); 1636 // Operand: imm12 1637 OutInst.addOperand(MI.getOperand(1)); 1638 OutInst.setLoc(MI.getLoc()); 1639 return true; 1640 } // if 1641 break; 1642 } // case C_LI 1643 case RISCV::C_LUI: { 1644 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 1645 (MI.getOperand(0).isReg()) && 1646 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) && 1647 RISCVValidateMCOperandForUncompress(MI.getOperand(1), STI, 4)) { 1648 // lui $rd, $imm20 1649 OutInst.setOpcode(RISCV::LUI); 1650 // Operand: rd 1651 OutInst.addOperand(MI.getOperand(0)); 1652 // Operand: imm20 1653 OutInst.addOperand(MI.getOperand(1)); 1654 OutInst.setLoc(MI.getLoc()); 1655 return true; 1656 } // if 1657 break; 1658 } // case C_LUI 1659 case RISCV::C_LW: { 1660 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 1661 (MI.getOperand(0).isReg()) && 1662 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) && 1663 (MI.getOperand(1).isReg()) && 1664 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(1).getReg())) && 1665 RISCVValidateMCOperandForUncompress(MI.getOperand(2), STI, 1)) { 1666 // lw $rd, ${imm12}(${rs1}) 1667 OutInst.setOpcode(RISCV::LW); 1668 // Operand: rd 1669 OutInst.addOperand(MI.getOperand(0)); 1670 // Operand: rs1 1671 OutInst.addOperand(MI.getOperand(1)); 1672 // Operand: imm12 1673 OutInst.addOperand(MI.getOperand(2)); 1674 OutInst.setLoc(MI.getLoc()); 1675 return true; 1676 } // if 1677 break; 1678 } // case C_LW 1679 case RISCV::C_LWSP: { 1680 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 1681 (MI.getOperand(0).isReg()) && 1682 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) && 1683 (MI.getOperand(1).isReg()) && 1684 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(1).getReg())) && 1685 RISCVValidateMCOperandForUncompress(MI.getOperand(2), STI, 1)) { 1686 // lw $rd, ${imm12}(${rs1}) 1687 OutInst.setOpcode(RISCV::LW); 1688 // Operand: rd 1689 OutInst.addOperand(MI.getOperand(0)); 1690 // Operand: rs1 1691 OutInst.addOperand(MI.getOperand(1)); 1692 // Operand: imm12 1693 OutInst.addOperand(MI.getOperand(2)); 1694 OutInst.setLoc(MI.getLoc()); 1695 return true; 1696 } // if 1697 break; 1698 } // case C_LWSP 1699 case RISCV::C_MV: { 1700 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 1701 (MI.getOperand(0).isReg()) && 1702 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) && 1703 (MI.getOperand(1).isReg()) && 1704 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(1).getReg())) && 1705 RISCVValidateMCOperandForUncompress(MCOperand::createImm(0), STI, 1)) { 1706 // addi $rd, $rs1, $imm12 1707 OutInst.setOpcode(RISCV::ADDI); 1708 // Operand: rd 1709 OutInst.addOperand(MI.getOperand(0)); 1710 // Operand: rs1 1711 OutInst.addOperand(MI.getOperand(1)); 1712 // Operand: imm12 1713 OutInst.addOperand(MCOperand::createImm(0)); 1714 OutInst.setLoc(MI.getLoc()); 1715 return true; 1716 } // if 1717 break; 1718 } // case C_MV 1719 case RISCV::C_NOP: { 1720 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 1721 RISCVValidateMCOperandForUncompress(MCOperand::createImm(0), STI, 1)) { 1722 // addi $rd, $rs1, $imm12 1723 OutInst.setOpcode(RISCV::ADDI); 1724 // Operand: rd 1725 OutInst.addOperand(MCOperand::createReg(RISCV::X0)); 1726 // Operand: rs1 1727 OutInst.addOperand(MCOperand::createReg(RISCV::X0)); 1728 // Operand: imm12 1729 OutInst.addOperand(MCOperand::createImm(0)); 1730 OutInst.setLoc(MI.getLoc()); 1731 return true; 1732 } // if 1733 break; 1734 } // case C_NOP 1735 case RISCV::C_OR: { 1736 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 1737 (MI.getOperand(0).isReg()) && 1738 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) && 1739 (MI.getOperand(0).isReg()) && 1740 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) && 1741 (MI.getOperand(2).isReg()) && 1742 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(2).getReg()))) { 1743 // or $rd, $rs1, $rs2 1744 OutInst.setOpcode(RISCV::OR); 1745 // Operand: rd 1746 OutInst.addOperand(MI.getOperand(0)); 1747 // Operand: rs1 1748 OutInst.addOperand(MI.getOperand(0)); 1749 // Operand: rs2 1750 OutInst.addOperand(MI.getOperand(2)); 1751 OutInst.setLoc(MI.getLoc()); 1752 return true; 1753 } // if 1754 break; 1755 } // case C_OR 1756 case RISCV::C_SD: { 1757 if (STI.getFeatureBits()[RISCV::Feature64Bit] && 1758 (STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 1759 (MI.getOperand(0).isReg()) && 1760 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) && 1761 (MI.getOperand(1).isReg()) && 1762 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(1).getReg())) && 1763 RISCVValidateMCOperandForUncompress(MI.getOperand(2), STI, 1)) { 1764 // sd $rs2, ${imm12}(${rs1}) 1765 OutInst.setOpcode(RISCV::SD); 1766 // Operand: rs2 1767 OutInst.addOperand(MI.getOperand(0)); 1768 // Operand: rs1 1769 OutInst.addOperand(MI.getOperand(1)); 1770 // Operand: imm12 1771 OutInst.addOperand(MI.getOperand(2)); 1772 OutInst.setLoc(MI.getLoc()); 1773 return true; 1774 } // if 1775 break; 1776 } // case C_SD 1777 case RISCV::C_SDSP: { 1778 if (STI.getFeatureBits()[RISCV::Feature64Bit] && 1779 (STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 1780 (MI.getOperand(0).isReg()) && 1781 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) && 1782 (MI.getOperand(1).isReg()) && 1783 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(1).getReg())) && 1784 RISCVValidateMCOperandForUncompress(MI.getOperand(2), STI, 1)) { 1785 // sd $rs2, ${imm12}(${rs1}) 1786 OutInst.setOpcode(RISCV::SD); 1787 // Operand: rs2 1788 OutInst.addOperand(MI.getOperand(0)); 1789 // Operand: rs1 1790 OutInst.addOperand(MI.getOperand(1)); 1791 // Operand: imm12 1792 OutInst.addOperand(MI.getOperand(2)); 1793 OutInst.setLoc(MI.getLoc()); 1794 return true; 1795 } // if 1796 break; 1797 } // case C_SDSP 1798 case RISCV::C_SLLI: { 1799 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 1800 (MI.getOperand(0).isReg()) && 1801 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) && 1802 (MI.getOperand(0).isReg()) && 1803 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) && 1804 RISCVValidateMCOperandForUncompress(MI.getOperand(2), STI, 5)) { 1805 // slli $rd, $rs1, $shamt 1806 OutInst.setOpcode(RISCV::SLLI); 1807 // Operand: rd 1808 OutInst.addOperand(MI.getOperand(0)); 1809 // Operand: rs1 1810 OutInst.addOperand(MI.getOperand(0)); 1811 // Operand: shamt 1812 OutInst.addOperand(MI.getOperand(2)); 1813 OutInst.setLoc(MI.getLoc()); 1814 return true; 1815 } // if 1816 break; 1817 } // case C_SLLI 1818 case RISCV::C_SRAI: { 1819 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 1820 (MI.getOperand(0).isReg()) && 1821 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) && 1822 (MI.getOperand(0).isReg()) && 1823 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) && 1824 RISCVValidateMCOperandForUncompress(MI.getOperand(2), STI, 5)) { 1825 // srai $rd, $rs1, $shamt 1826 OutInst.setOpcode(RISCV::SRAI); 1827 // Operand: rd 1828 OutInst.addOperand(MI.getOperand(0)); 1829 // Operand: rs1 1830 OutInst.addOperand(MI.getOperand(0)); 1831 // Operand: shamt 1832 OutInst.addOperand(MI.getOperand(2)); 1833 OutInst.setLoc(MI.getLoc()); 1834 return true; 1835 } // if 1836 break; 1837 } // case C_SRAI 1838 case RISCV::C_SRLI: { 1839 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 1840 (MI.getOperand(0).isReg()) && 1841 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) && 1842 (MI.getOperand(0).isReg()) && 1843 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) && 1844 RISCVValidateMCOperandForUncompress(MI.getOperand(2), STI, 5)) { 1845 // srli $rd, $rs1, $shamt 1846 OutInst.setOpcode(RISCV::SRLI); 1847 // Operand: rd 1848 OutInst.addOperand(MI.getOperand(0)); 1849 // Operand: rs1 1850 OutInst.addOperand(MI.getOperand(0)); 1851 // Operand: shamt 1852 OutInst.addOperand(MI.getOperand(2)); 1853 OutInst.setLoc(MI.getLoc()); 1854 return true; 1855 } // if 1856 break; 1857 } // case C_SRLI 1858 case RISCV::C_SUB: { 1859 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 1860 (MI.getOperand(0).isReg()) && 1861 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) && 1862 (MI.getOperand(0).isReg()) && 1863 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) && 1864 (MI.getOperand(2).isReg()) && 1865 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(2).getReg()))) { 1866 // sub $rd, $rs1, $rs2 1867 OutInst.setOpcode(RISCV::SUB); 1868 // Operand: rd 1869 OutInst.addOperand(MI.getOperand(0)); 1870 // Operand: rs1 1871 OutInst.addOperand(MI.getOperand(0)); 1872 // Operand: rs2 1873 OutInst.addOperand(MI.getOperand(2)); 1874 OutInst.setLoc(MI.getLoc()); 1875 return true; 1876 } // if 1877 break; 1878 } // case C_SUB 1879 case RISCV::C_SUBW: { 1880 if (STI.getFeatureBits()[RISCV::Feature64Bit] && 1881 (STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 1882 (MI.getOperand(0).isReg()) && 1883 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) && 1884 (MI.getOperand(0).isReg()) && 1885 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) && 1886 (MI.getOperand(2).isReg()) && 1887 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(2).getReg()))) { 1888 // subw $rd, $rs1, $rs2 1889 OutInst.setOpcode(RISCV::SUBW); 1890 // Operand: rd 1891 OutInst.addOperand(MI.getOperand(0)); 1892 // Operand: rs1 1893 OutInst.addOperand(MI.getOperand(0)); 1894 // Operand: rs2 1895 OutInst.addOperand(MI.getOperand(2)); 1896 OutInst.setLoc(MI.getLoc()); 1897 return true; 1898 } // if 1899 break; 1900 } // case C_SUBW 1901 case RISCV::C_SW: { 1902 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 1903 (MI.getOperand(0).isReg()) && 1904 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) && 1905 (MI.getOperand(1).isReg()) && 1906 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(1).getReg())) && 1907 RISCVValidateMCOperandForUncompress(MI.getOperand(2), STI, 1)) { 1908 // sw $rs2, ${imm12}(${rs1}) 1909 OutInst.setOpcode(RISCV::SW); 1910 // Operand: rs2 1911 OutInst.addOperand(MI.getOperand(0)); 1912 // Operand: rs1 1913 OutInst.addOperand(MI.getOperand(1)); 1914 // Operand: imm12 1915 OutInst.addOperand(MI.getOperand(2)); 1916 OutInst.setLoc(MI.getLoc()); 1917 return true; 1918 } // if 1919 break; 1920 } // case C_SW 1921 case RISCV::C_SWSP: { 1922 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 1923 (MI.getOperand(0).isReg()) && 1924 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) && 1925 (MI.getOperand(1).isReg()) && 1926 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(1).getReg())) && 1927 RISCVValidateMCOperandForUncompress(MI.getOperand(2), STI, 1)) { 1928 // sw $rs2, ${imm12}(${rs1}) 1929 OutInst.setOpcode(RISCV::SW); 1930 // Operand: rs2 1931 OutInst.addOperand(MI.getOperand(0)); 1932 // Operand: rs1 1933 OutInst.addOperand(MI.getOperand(1)); 1934 // Operand: imm12 1935 OutInst.addOperand(MI.getOperand(2)); 1936 OutInst.setLoc(MI.getLoc()); 1937 return true; 1938 } // if 1939 break; 1940 } // case C_SWSP 1941 case RISCV::C_UNIMP: { 1942 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC])) { 1943 // unimp 1944 OutInst.setOpcode(RISCV::UNIMP); 1945 OutInst.setLoc(MI.getLoc()); 1946 return true; 1947 } // if 1948 break; 1949 } // case C_UNIMP 1950 case RISCV::C_XOR: { 1951 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 1952 (MI.getOperand(0).isReg()) && 1953 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) && 1954 (MI.getOperand(0).isReg()) && 1955 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) && 1956 (MI.getOperand(2).isReg()) && 1957 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(2).getReg()))) { 1958 // xor $rd, $rs1, $rs2 1959 OutInst.setOpcode(RISCV::XOR); 1960 // Operand: rd 1961 OutInst.addOperand(MI.getOperand(0)); 1962 // Operand: rs1 1963 OutInst.addOperand(MI.getOperand(0)); 1964 // Operand: rs2 1965 OutInst.addOperand(MI.getOperand(2)); 1966 OutInst.setLoc(MI.getLoc()); 1967 return true; 1968 } // if 1969 1970 } // case C_XOR 1971 } // switch 1972 return false; 1973} 1974 1975#endif //GEN_UNCOMPRESS_INSTR 1976 1977 1978#ifdef GEN_CHECK_COMPRESS_INSTR 1979#undef GEN_CHECK_COMPRESS_INSTR 1980 1981static bool RISCVValidateMachineOperand(const MachineOperand &MO, 1982 const RISCVSubtarget *Subtarget, 1983 unsigned PredicateIndex) { 1984 int64_t Imm = MO.getImm(); 1985 switch (PredicateIndex) { 1986 default: 1987 llvm_unreachable("Unknown ImmLeaf Predicate kind"); 1988 break; 1989 case 1: { 1990 // simm6nonzero 1991 return (Imm != 0) && isInt<6>(Imm); 1992 } 1993 case 2: { 1994 // simm10_lsb0000nonzero 1995 return (Imm != 0) && isShiftedInt<6, 4>(Imm); 1996 } 1997 case 3: { 1998 // uimm10_lsb00nonzero 1999 return isShiftedUInt<8, 2>(Imm) && (Imm != 0); 2000 } 2001 case 4: { 2002 // simm6 2003 return isInt<6>(Imm); 2004 } 2005 case 5: { 2006 // simm9_lsb0 2007 return isShiftedInt<8, 1>(Imm); 2008 } 2009 case 6: { 2010 // uimm8_lsb000 2011 return isShiftedUInt<5, 3>(Imm); 2012 } 2013 case 7: { 2014 // uimm9_lsb000 2015 return isShiftedUInt<6, 3>(Imm); 2016 } 2017 case 8: { 2018 // uimm7_lsb00 2019 return isShiftedUInt<5, 2>(Imm); 2020 } 2021 case 9: { 2022 // uimm8_lsb00 2023 return isShiftedUInt<6, 2>(Imm); 2024 } 2025 case 10: { 2026 // simm12_lsb0 2027 return isShiftedInt<11, 1>(Imm); 2028 } 2029 case 11: { 2030 // c_lui_imm 2031 return (Imm != 0) && 2032 (isUInt<5>(Imm) || 2033 (Imm >= 0xfffe0 && Imm <= 0xfffff)); 2034 } 2035 case 12: { 2036 // uimmlog2xlennonzero 2037 2038 if (Subtarget->is64Bit()) 2039 return isUInt<6>(Imm) && (Imm != 0); 2040 return isUInt<5>(Imm) && (Imm != 0); 2041 2042 } 2043 } 2044} 2045 2046static bool isCompressibleInst(const MachineInstr &MI, 2047 const RISCVSubtarget &STI) { 2048 switch (MI.getOpcode()) { 2049 default: return false; 2050 case RISCV::ADD: { 2051 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 2052 (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) && 2053 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && 2054 (MI.getOperand(1).isReg()) && 2055 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(1).getReg())) && 2056 (MI.getOperand(2).isReg()) && 2057 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(2).getReg()))) { 2058 // c.add $rs1, $rs2 2059 // Operand: rs1_wb 2060 // Operand: rs1 2061 // Operand: rs2 2062 return true; 2063 } // if 2064 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 2065 (MI.getOperand(2).isReg()) && (MI.getOperand(0).isReg()) && 2066 (MI.getOperand(2).getReg() == MI.getOperand(0).getReg()) && 2067 (MI.getOperand(2).isReg()) && 2068 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(2).getReg())) && 2069 (MI.getOperand(1).isReg()) && 2070 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(1).getReg()))) { 2071 // c.add $rs1, $rs2 2072 // Operand: rs1_wb 2073 // Operand: rs1 2074 // Operand: rs2 2075 return true; 2076 } // if 2077 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 2078 (MI.getOperand(1).isReg()) && 2079 (MI.getOperand(1).getReg() == RISCV::X0) && 2080 (MI.getOperand(0).isReg()) && 2081 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(0).getReg())) && 2082 (MI.getOperand(2).isReg()) && 2083 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(2).getReg()))) { 2084 // c.mv $rs1, $rs2 2085 // Operand: rs1 2086 // Operand: rs2 2087 return true; 2088 } // if 2089 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 2090 (MI.getOperand(2).isReg()) && 2091 (MI.getOperand(2).getReg() == RISCV::X0) && 2092 (MI.getOperand(0).isReg()) && 2093 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(0).getReg())) && 2094 (MI.getOperand(1).isReg()) && 2095 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(1).getReg()))) { 2096 // c.mv $rs1, $rs2 2097 // Operand: rs1 2098 // Operand: rs2 2099 return true; 2100 } // if 2101 break; 2102 } // case ADD 2103 case RISCV::ADDI: { 2104 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 2105 (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) && 2106 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && 2107 (MI.getOperand(1).isReg()) && 2108 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(1).getReg())) && 2109 MI.getOperand(2).isImm() && 2110 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 1)) { 2111 // c.addi $rd, $imm 2112 // Operand: rd_wb 2113 // Operand: rd 2114 // Operand: imm 2115 return true; 2116 } // if 2117 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 2118 (MI.getOperand(0).isReg()) && 2119 (MI.getOperand(0).getReg() == RISCV::X2) && 2120 (MI.getOperand(1).isReg()) && 2121 (MI.getOperand(1).getReg() == RISCV::X2) && 2122 MI.getOperand(2).isImm() && 2123 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 2)) { 2124 // c.addi16sp $rd, $imm 2125 // Operand: rd_wb 2126 // Operand: rd 2127 // Operand: imm 2128 return true; 2129 } // if 2130 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 2131 (MI.getOperand(0).isReg()) && 2132 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(0).getReg())) && 2133 (MI.getOperand(1).isReg()) && 2134 (RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(1).getReg())) && 2135 MI.getOperand(2).isImm() && 2136 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 3)) { 2137 // c.addi4spn $rd, $rs1, $imm 2138 // Operand: rd 2139 // Operand: rs1 2140 // Operand: imm 2141 return true; 2142 } // if 2143 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 2144 (MI.getOperand(1).isReg()) && 2145 (MI.getOperand(1).getReg() == RISCV::X0) && 2146 (MI.getOperand(0).isReg()) && 2147 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(0).getReg())) && 2148 MI.getOperand(2).isImm() && 2149 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 4)) { 2150 // c.li $rd, $imm 2151 // Operand: rd 2152 // Operand: imm 2153 return true; 2154 } // if 2155 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 2156 (MI.getOperand(2).isImm()) && 2157 (MI.getOperand(2).getImm() == 0) && 2158 (MI.getOperand(0).isReg()) && 2159 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(0).getReg())) && 2160 (MI.getOperand(1).isReg()) && 2161 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(1).getReg()))) { 2162 // c.mv $rs1, $rs2 2163 // Operand: rs1 2164 // Operand: rs2 2165 return true; 2166 } // if 2167 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 2168 (MI.getOperand(0).isReg()) && 2169 (MI.getOperand(0).getReg() == RISCV::X0) && 2170 (MI.getOperand(1).isReg()) && 2171 (MI.getOperand(1).getReg() == RISCV::X0) && 2172 (MI.getOperand(2).isImm()) && 2173 (MI.getOperand(2).getImm() == 0)) { 2174 // c.nop 2175 return true; 2176 } // if 2177 break; 2178 } // case ADDI 2179 case RISCV::ADDIW: { 2180 if (STI.getFeatureBits()[RISCV::Feature64Bit] && 2181 (STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 2182 (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) && 2183 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && 2184 (MI.getOperand(1).isReg()) && 2185 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(1).getReg())) && 2186 MI.getOperand(2).isImm() && 2187 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 4)) { 2188 // c.addiw $rd, $imm 2189 // Operand: rd_wb 2190 // Operand: rd 2191 // Operand: imm 2192 return true; 2193 } // if 2194 if (STI.getFeatureBits()[RISCV::Feature64Bit] && 2195 (STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 2196 (MI.getOperand(1).isReg()) && 2197 (MI.getOperand(1).getReg() == RISCV::X0) && 2198 (MI.getOperand(0).isReg()) && 2199 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(0).getReg())) && 2200 MI.getOperand(2).isImm() && 2201 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 4)) { 2202 // c.li $rd, $imm 2203 // Operand: rd 2204 // Operand: imm 2205 return true; 2206 } // if 2207 break; 2208 } // case ADDIW 2209 case RISCV::ADDW: { 2210 if (STI.getFeatureBits()[RISCV::Feature64Bit] && 2211 (STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 2212 (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) && 2213 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && 2214 (MI.getOperand(1).isReg()) && 2215 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) && 2216 (MI.getOperand(2).isReg()) && 2217 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(2).getReg()))) { 2218 // c.addw $rd, $rs2 2219 // Operand: rd_wb 2220 // Operand: rd 2221 // Operand: rs2 2222 return true; 2223 } // if 2224 if (STI.getFeatureBits()[RISCV::Feature64Bit] && 2225 (STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 2226 (MI.getOperand(2).isReg()) && (MI.getOperand(0).isReg()) && 2227 (MI.getOperand(2).getReg() == MI.getOperand(0).getReg()) && 2228 (MI.getOperand(2).isReg()) && 2229 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(2).getReg())) && 2230 (MI.getOperand(1).isReg()) && 2231 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg()))) { 2232 // c.addw $rd, $rs2 2233 // Operand: rd_wb 2234 // Operand: rd 2235 // Operand: rs2 2236 return true; 2237 } // if 2238 break; 2239 } // case ADDW 2240 case RISCV::AND: { 2241 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 2242 (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) && 2243 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && 2244 (MI.getOperand(1).isReg()) && 2245 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) && 2246 (MI.getOperand(2).isReg()) && 2247 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(2).getReg()))) { 2248 // c.and $rd, $rs2 2249 // Operand: rd_wb 2250 // Operand: rd 2251 // Operand: rs2 2252 return true; 2253 } // if 2254 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 2255 (MI.getOperand(2).isReg()) && (MI.getOperand(0).isReg()) && 2256 (MI.getOperand(2).getReg() == MI.getOperand(0).getReg()) && 2257 (MI.getOperand(2).isReg()) && 2258 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(2).getReg())) && 2259 (MI.getOperand(1).isReg()) && 2260 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg()))) { 2261 // c.and $rd, $rs2 2262 // Operand: rd_wb 2263 // Operand: rd 2264 // Operand: rs2 2265 return true; 2266 } // if 2267 break; 2268 } // case AND 2269 case RISCV::ANDI: { 2270 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 2271 (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) && 2272 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && 2273 (MI.getOperand(1).isReg()) && 2274 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) && 2275 MI.getOperand(2).isImm() && 2276 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 4)) { 2277 // c.andi $rs1, $imm 2278 // Operand: rs1_wb 2279 // Operand: rs1 2280 // Operand: imm 2281 return true; 2282 } // if 2283 break; 2284 } // case ANDI 2285 case RISCV::BEQ: { 2286 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 2287 (MI.getOperand(1).isReg()) && 2288 (MI.getOperand(1).getReg() == RISCV::X0) && 2289 (MI.getOperand(0).isReg()) && 2290 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(0).getReg())) && 2291 MI.getOperand(2).isImm() && 2292 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 5)) { 2293 // c.beqz $rs1, $imm 2294 // Operand: rs1 2295 // Operand: imm 2296 return true; 2297 } // if 2298 break; 2299 } // case BEQ 2300 case RISCV::BNE: { 2301 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 2302 (MI.getOperand(1).isReg()) && 2303 (MI.getOperand(1).getReg() == RISCV::X0) && 2304 (MI.getOperand(0).isReg()) && 2305 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(0).getReg())) && 2306 MI.getOperand(2).isImm() && 2307 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 5)) { 2308 // c.bnez $rs1, $imm 2309 // Operand: rs1 2310 // Operand: imm 2311 return true; 2312 } // if 2313 break; 2314 } // case BNE 2315 case RISCV::EBREAK: { 2316 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC])) { 2317 // c.ebreak 2318 return true; 2319 } // if 2320 break; 2321 } // case EBREAK 2322 case RISCV::FLD: { 2323 if (STI.getFeatureBits()[RISCV::FeatureStdExtD] && 2324 (STI.getFeatureBits()[RISCV::FeatureExtZcd] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 2325 (MI.getOperand(0).isReg()) && 2326 (RISCVMCRegisterClasses[RISCV::FPR64CRegClassID].contains(MI.getOperand(0).getReg())) && 2327 (MI.getOperand(1).isReg()) && 2328 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) && 2329 MI.getOperand(2).isImm() && 2330 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 6)) { 2331 // c.fld $rd, ${imm}(${rs1}) 2332 // Operand: rd 2333 // Operand: rs1 2334 // Operand: imm 2335 return true; 2336 } // if 2337 if (STI.getFeatureBits()[RISCV::FeatureStdExtD] && 2338 (STI.getFeatureBits()[RISCV::FeatureExtZcd] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 2339 (MI.getOperand(0).isReg()) && 2340 (RISCVMCRegisterClasses[RISCV::FPR64RegClassID].contains(MI.getOperand(0).getReg())) && 2341 (MI.getOperand(1).isReg()) && 2342 (RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(1).getReg())) && 2343 MI.getOperand(2).isImm() && 2344 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 7)) { 2345 // c.fldsp $rd, ${imm}(${rs1}) 2346 // Operand: rd 2347 // Operand: rs1 2348 // Operand: imm 2349 return true; 2350 } // if 2351 break; 2352 } // case FLD 2353 case RISCV::FLW: { 2354 if (STI.getFeatureBits()[RISCV::FeatureStdExtF] && 2355 !STI.getFeatureBits()[RISCV::Feature64Bit] && 2356 (STI.getFeatureBits()[RISCV::FeatureExtZcf] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 2357 (MI.getOperand(0).isReg()) && 2358 (RISCVMCRegisterClasses[RISCV::FPR32CRegClassID].contains(MI.getOperand(0).getReg())) && 2359 (MI.getOperand(1).isReg()) && 2360 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) && 2361 MI.getOperand(2).isImm() && 2362 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 8)) { 2363 // c.flw $rd, ${imm}(${rs1}) 2364 // Operand: rd 2365 // Operand: rs1 2366 // Operand: imm 2367 return true; 2368 } // if 2369 if (STI.getFeatureBits()[RISCV::FeatureStdExtF] && 2370 !STI.getFeatureBits()[RISCV::Feature64Bit] && 2371 (STI.getFeatureBits()[RISCV::FeatureExtZcf] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 2372 (MI.getOperand(0).isReg()) && 2373 (RISCVMCRegisterClasses[RISCV::FPR32RegClassID].contains(MI.getOperand(0).getReg())) && 2374 (MI.getOperand(1).isReg()) && 2375 (RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(1).getReg())) && 2376 MI.getOperand(2).isImm() && 2377 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 9)) { 2378 // c.flwsp $rd, ${imm}(${rs1}) 2379 // Operand: rd 2380 // Operand: rs1 2381 // Operand: imm 2382 return true; 2383 } // if 2384 break; 2385 } // case FLW 2386 case RISCV::FSD: { 2387 if (STI.getFeatureBits()[RISCV::FeatureStdExtD] && 2388 (STI.getFeatureBits()[RISCV::FeatureExtZcd] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 2389 (MI.getOperand(0).isReg()) && 2390 (RISCVMCRegisterClasses[RISCV::FPR64CRegClassID].contains(MI.getOperand(0).getReg())) && 2391 (MI.getOperand(1).isReg()) && 2392 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) && 2393 MI.getOperand(2).isImm() && 2394 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 6)) { 2395 // c.fsd $rs2, ${imm}(${rs1}) 2396 // Operand: rs2 2397 // Operand: rs1 2398 // Operand: imm 2399 return true; 2400 } // if 2401 if (STI.getFeatureBits()[RISCV::FeatureStdExtD] && 2402 (STI.getFeatureBits()[RISCV::FeatureExtZcd] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 2403 (MI.getOperand(0).isReg()) && 2404 (RISCVMCRegisterClasses[RISCV::FPR64RegClassID].contains(MI.getOperand(0).getReg())) && 2405 (MI.getOperand(1).isReg()) && 2406 (RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(1).getReg())) && 2407 MI.getOperand(2).isImm() && 2408 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 7)) { 2409 // c.fsdsp $rs2, ${imm}(${rs1}) 2410 // Operand: rs2 2411 // Operand: rs1 2412 // Operand: imm 2413 return true; 2414 } // if 2415 break; 2416 } // case FSD 2417 case RISCV::FSW: { 2418 if (STI.getFeatureBits()[RISCV::FeatureStdExtF] && 2419 !STI.getFeatureBits()[RISCV::Feature64Bit] && 2420 (STI.getFeatureBits()[RISCV::FeatureExtZcf] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 2421 (MI.getOperand(0).isReg()) && 2422 (RISCVMCRegisterClasses[RISCV::FPR32CRegClassID].contains(MI.getOperand(0).getReg())) && 2423 (MI.getOperand(1).isReg()) && 2424 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) && 2425 MI.getOperand(2).isImm() && 2426 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 8)) { 2427 // c.fsw $rs2, ${imm}(${rs1}) 2428 // Operand: rs2 2429 // Operand: rs1 2430 // Operand: imm 2431 return true; 2432 } // if 2433 if (STI.getFeatureBits()[RISCV::FeatureStdExtF] && 2434 !STI.getFeatureBits()[RISCV::Feature64Bit] && 2435 (STI.getFeatureBits()[RISCV::FeatureExtZcf] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 2436 (MI.getOperand(0).isReg()) && 2437 (RISCVMCRegisterClasses[RISCV::FPR32RegClassID].contains(MI.getOperand(0).getReg())) && 2438 (MI.getOperand(1).isReg()) && 2439 (RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(1).getReg())) && 2440 MI.getOperand(2).isImm() && 2441 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 9)) { 2442 // c.fswsp $rs2, ${imm}(${rs1}) 2443 // Operand: rs2 2444 // Operand: rs1 2445 // Operand: imm 2446 return true; 2447 } // if 2448 break; 2449 } // case FSW 2450 case RISCV::JAL: { 2451 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 2452 (MI.getOperand(0).isReg()) && 2453 (MI.getOperand(0).getReg() == RISCV::X0) && 2454 MI.getOperand(1).isImm() && 2455 RISCVValidateMachineOperand(MI.getOperand(1), &STI, 10)) { 2456 // c.j $offset 2457 // Operand: offset 2458 return true; 2459 } // if 2460 if (!STI.getFeatureBits()[RISCV::Feature64Bit] && 2461 (STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 2462 (MI.getOperand(0).isReg()) && 2463 (MI.getOperand(0).getReg() == RISCV::X1) && 2464 MI.getOperand(1).isImm() && 2465 RISCVValidateMachineOperand(MI.getOperand(1), &STI, 10)) { 2466 // c.jal $offset 2467 // Operand: offset 2468 return true; 2469 } // if 2470 break; 2471 } // case JAL 2472 case RISCV::JALR: { 2473 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 2474 (MI.getOperand(0).isReg()) && 2475 (MI.getOperand(0).getReg() == RISCV::X1) && 2476 (MI.getOperand(2).isImm()) && 2477 (MI.getOperand(2).getImm() == 0) && 2478 (MI.getOperand(1).isReg()) && 2479 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(1).getReg()))) { 2480 // c.jalr $rs1 2481 // Operand: rs1 2482 return true; 2483 } // if 2484 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 2485 (MI.getOperand(0).isReg()) && 2486 (MI.getOperand(0).getReg() == RISCV::X0) && 2487 (MI.getOperand(2).isImm()) && 2488 (MI.getOperand(2).getImm() == 0) && 2489 (MI.getOperand(1).isReg()) && 2490 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(1).getReg()))) { 2491 // c.jr $rs1 2492 // Operand: rs1 2493 return true; 2494 } // if 2495 break; 2496 } // case JALR 2497 case RISCV::LD: { 2498 if (STI.getFeatureBits()[RISCV::Feature64Bit] && 2499 (STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 2500 (MI.getOperand(0).isReg()) && 2501 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(0).getReg())) && 2502 (MI.getOperand(1).isReg()) && 2503 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) && 2504 MI.getOperand(2).isImm() && 2505 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 6)) { 2506 // c.ld $rd, ${imm}(${rs1}) 2507 // Operand: rd 2508 // Operand: rs1 2509 // Operand: imm 2510 return true; 2511 } // if 2512 if (STI.getFeatureBits()[RISCV::Feature64Bit] && 2513 (STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 2514 (MI.getOperand(0).isReg()) && 2515 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(0).getReg())) && 2516 (MI.getOperand(1).isReg()) && 2517 (RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(1).getReg())) && 2518 MI.getOperand(2).isImm() && 2519 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 7)) { 2520 // c.ldsp $rd, ${imm}(${rs1}) 2521 // Operand: rd 2522 // Operand: rs1 2523 // Operand: imm 2524 return true; 2525 } // if 2526 break; 2527 } // case LD 2528 case RISCV::LUI: { 2529 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 2530 (MI.getOperand(0).isReg()) && 2531 (RISCVMCRegisterClasses[RISCV::GPRNoX0X2RegClassID].contains(MI.getOperand(0).getReg())) && 2532 MI.getOperand(1).isImm() && 2533 RISCVValidateMachineOperand(MI.getOperand(1), &STI, 11)) { 2534 // c.lui $rd, $imm 2535 // Operand: rd 2536 // Operand: imm 2537 return true; 2538 } // if 2539 break; 2540 } // case LUI 2541 case RISCV::LW: { 2542 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 2543 (MI.getOperand(0).isReg()) && 2544 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(0).getReg())) && 2545 (MI.getOperand(1).isReg()) && 2546 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) && 2547 MI.getOperand(2).isImm() && 2548 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 8)) { 2549 // c.lw $rd, ${imm}(${rs1}) 2550 // Operand: rd 2551 // Operand: rs1 2552 // Operand: imm 2553 return true; 2554 } // if 2555 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 2556 (MI.getOperand(0).isReg()) && 2557 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(0).getReg())) && 2558 (MI.getOperand(1).isReg()) && 2559 (RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(1).getReg())) && 2560 MI.getOperand(2).isImm() && 2561 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 9)) { 2562 // c.lwsp $rd, ${imm}(${rs1}) 2563 // Operand: rd 2564 // Operand: rs1 2565 // Operand: imm 2566 return true; 2567 } // if 2568 break; 2569 } // case LW 2570 case RISCV::OR: { 2571 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 2572 (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) && 2573 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && 2574 (MI.getOperand(1).isReg()) && 2575 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) && 2576 (MI.getOperand(2).isReg()) && 2577 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(2).getReg()))) { 2578 // c.or $rd, $rs2 2579 // Operand: rd_wb 2580 // Operand: rd 2581 // Operand: rs2 2582 return true; 2583 } // if 2584 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 2585 (MI.getOperand(2).isReg()) && (MI.getOperand(0).isReg()) && 2586 (MI.getOperand(2).getReg() == MI.getOperand(0).getReg()) && 2587 (MI.getOperand(2).isReg()) && 2588 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(2).getReg())) && 2589 (MI.getOperand(1).isReg()) && 2590 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg()))) { 2591 // c.or $rd, $rs2 2592 // Operand: rd_wb 2593 // Operand: rd 2594 // Operand: rs2 2595 return true; 2596 } // if 2597 break; 2598 } // case OR 2599 case RISCV::SD: { 2600 if (STI.getFeatureBits()[RISCV::Feature64Bit] && 2601 (STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 2602 (MI.getOperand(0).isReg()) && 2603 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(0).getReg())) && 2604 (MI.getOperand(1).isReg()) && 2605 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) && 2606 MI.getOperand(2).isImm() && 2607 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 6)) { 2608 // c.sd $rs2, ${imm}(${rs1}) 2609 // Operand: rs2 2610 // Operand: rs1 2611 // Operand: imm 2612 return true; 2613 } // if 2614 if (STI.getFeatureBits()[RISCV::Feature64Bit] && 2615 (STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 2616 (MI.getOperand(0).isReg()) && 2617 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) && 2618 (MI.getOperand(1).isReg()) && 2619 (RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(1).getReg())) && 2620 MI.getOperand(2).isImm() && 2621 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 7)) { 2622 // c.sdsp $rs2, ${imm}(${rs1}) 2623 // Operand: rs2 2624 // Operand: rs1 2625 // Operand: imm 2626 return true; 2627 } // if 2628 break; 2629 } // case SD 2630 case RISCV::SLLI: { 2631 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 2632 (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) && 2633 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && 2634 (MI.getOperand(1).isReg()) && 2635 (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(1).getReg())) && 2636 MI.getOperand(2).isImm() && 2637 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 12)) { 2638 // c.slli $rd, $imm 2639 // Operand: rd_wb 2640 // Operand: rd 2641 // Operand: imm 2642 return true; 2643 } // if 2644 break; 2645 } // case SLLI 2646 case RISCV::SRAI: { 2647 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 2648 (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) && 2649 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && 2650 (MI.getOperand(1).isReg()) && 2651 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) && 2652 MI.getOperand(2).isImm() && 2653 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 12)) { 2654 // c.srai $rs1, $imm 2655 // Operand: rs1_wb 2656 // Operand: rs1 2657 // Operand: imm 2658 return true; 2659 } // if 2660 break; 2661 } // case SRAI 2662 case RISCV::SRLI: { 2663 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 2664 (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) && 2665 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && 2666 (MI.getOperand(1).isReg()) && 2667 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) && 2668 MI.getOperand(2).isImm() && 2669 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 12)) { 2670 // c.srli $rs1, $imm 2671 // Operand: rs1_wb 2672 // Operand: rs1 2673 // Operand: imm 2674 return true; 2675 } // if 2676 break; 2677 } // case SRLI 2678 case RISCV::SUB: { 2679 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 2680 (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) && 2681 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && 2682 (MI.getOperand(1).isReg()) && 2683 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) && 2684 (MI.getOperand(2).isReg()) && 2685 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(2).getReg()))) { 2686 // c.sub $rd, $rs2 2687 // Operand: rd_wb 2688 // Operand: rd 2689 // Operand: rs2 2690 return true; 2691 } // if 2692 break; 2693 } // case SUB 2694 case RISCV::SUBW: { 2695 if (STI.getFeatureBits()[RISCV::Feature64Bit] && 2696 (STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 2697 (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) && 2698 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && 2699 (MI.getOperand(1).isReg()) && 2700 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) && 2701 (MI.getOperand(2).isReg()) && 2702 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(2).getReg()))) { 2703 // c.subw $rd, $rs2 2704 // Operand: rd_wb 2705 // Operand: rd 2706 // Operand: rs2 2707 return true; 2708 } // if 2709 break; 2710 } // case SUBW 2711 case RISCV::SW: { 2712 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 2713 (MI.getOperand(0).isReg()) && 2714 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(0).getReg())) && 2715 (MI.getOperand(1).isReg()) && 2716 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) && 2717 MI.getOperand(2).isImm() && 2718 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 8)) { 2719 // c.sw $rs2, ${imm}(${rs1}) 2720 // Operand: rs2 2721 // Operand: rs1 2722 // Operand: imm 2723 return true; 2724 } // if 2725 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 2726 (MI.getOperand(0).isReg()) && 2727 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) && 2728 (MI.getOperand(1).isReg()) && 2729 (RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(1).getReg())) && 2730 MI.getOperand(2).isImm() && 2731 RISCVValidateMachineOperand(MI.getOperand(2), &STI, 9)) { 2732 // c.swsp $rs2, ${imm}(${rs1}) 2733 // Operand: rs2 2734 // Operand: rs1 2735 // Operand: imm 2736 return true; 2737 } // if 2738 break; 2739 } // case SW 2740 case RISCV::UNIMP: { 2741 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC])) { 2742 // c.unimp 2743 return true; 2744 } // if 2745 break; 2746 } // case UNIMP 2747 case RISCV::XOR: { 2748 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 2749 (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) && 2750 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && 2751 (MI.getOperand(1).isReg()) && 2752 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) && 2753 (MI.getOperand(2).isReg()) && 2754 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(2).getReg()))) { 2755 // c.xor $rd, $rs2 2756 // Operand: rd_wb 2757 // Operand: rd 2758 // Operand: rs2 2759 return true; 2760 } // if 2761 if ((STI.getFeatureBits()[RISCV::FeatureExtZca] || STI.getFeatureBits()[RISCV::FeatureStdExtC]) && 2762 (MI.getOperand(2).isReg()) && (MI.getOperand(0).isReg()) && 2763 (MI.getOperand(2).getReg() == MI.getOperand(0).getReg()) && 2764 (MI.getOperand(2).isReg()) && 2765 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(2).getReg())) && 2766 (MI.getOperand(1).isReg()) && 2767 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg()))) { 2768 // c.xor $rd, $rs2 2769 // Operand: rd_wb 2770 // Operand: rd 2771 // Operand: rs2 2772 return true; 2773 } // if 2774 2775 } // case XOR 2776 } // switch 2777 return false; 2778} 2779 2780#endif //GEN_CHECK_COMPRESS_INSTR 2781 2782