1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2|* *| 3|* Pseudo-instruction MC lowering Source Fragment *| 4|* *| 5|* Automatically generated file, do not edit! *| 6|* *| 7\*===----------------------------------------------------------------------===*/ 8 9bool RISCVAsmPrinter:: 10emitPseudoExpansionLowering(MCStreamer &OutStreamer, 11 const MachineInstr *MI) { 12 switch (MI->getOpcode()) { 13 default: return false; 14 case RISCV::PseudoBR: { 15 MCInst TmpInst; 16 MCOperand MCOp; 17 TmpInst.setOpcode(RISCV::JAL); 18 // Operand: rd 19 TmpInst.addOperand(MCOperand::createReg(RISCV::X0)); 20 // Operand: imm20 21 lowerOperand(MI->getOperand(0), MCOp); 22 TmpInst.addOperand(MCOp); 23 EmitToStreamer(OutStreamer, TmpInst); 24 break; 25 } 26 case RISCV::PseudoBRIND: { 27 MCInst TmpInst; 28 MCOperand MCOp; 29 TmpInst.setOpcode(RISCV::JALR); 30 // Operand: rd 31 TmpInst.addOperand(MCOperand::createReg(RISCV::X0)); 32 // Operand: rs1 33 lowerOperand(MI->getOperand(0), MCOp); 34 TmpInst.addOperand(MCOp); 35 // Operand: imm12 36 lowerOperand(MI->getOperand(1), MCOp); 37 TmpInst.addOperand(MCOp); 38 EmitToStreamer(OutStreamer, TmpInst); 39 break; 40 } 41 case RISCV::PseudoCALLIndirect: { 42 MCInst TmpInst; 43 MCOperand MCOp; 44 TmpInst.setOpcode(RISCV::JALR); 45 // Operand: rd 46 TmpInst.addOperand(MCOperand::createReg(RISCV::X1)); 47 // Operand: rs1 48 lowerOperand(MI->getOperand(0), MCOp); 49 TmpInst.addOperand(MCOp); 50 // Operand: imm12 51 TmpInst.addOperand(MCOperand::createImm(0)); 52 EmitToStreamer(OutStreamer, TmpInst); 53 break; 54 } 55 case RISCV::PseudoRET: { 56 MCInst TmpInst; 57 MCOperand MCOp; 58 TmpInst.setOpcode(RISCV::JALR); 59 // Operand: rd 60 TmpInst.addOperand(MCOperand::createReg(RISCV::X0)); 61 // Operand: rs1 62 TmpInst.addOperand(MCOperand::createReg(RISCV::X1)); 63 // Operand: imm12 64 TmpInst.addOperand(MCOperand::createImm(0)); 65 EmitToStreamer(OutStreamer, TmpInst); 66 break; 67 } 68 case RISCV::PseudoTAILIndirect: { 69 MCInst TmpInst; 70 MCOperand MCOp; 71 TmpInst.setOpcode(RISCV::JALR); 72 // Operand: rd 73 TmpInst.addOperand(MCOperand::createReg(RISCV::X0)); 74 // Operand: rs1 75 lowerOperand(MI->getOperand(0), MCOp); 76 TmpInst.addOperand(MCOp); 77 // Operand: imm12 78 TmpInst.addOperand(MCOperand::createImm(0)); 79 EmitToStreamer(OutStreamer, TmpInst); 80 break; 81 } 82 case RISCV::ReadFFLAGS: { 83 MCInst TmpInst; 84 MCOperand MCOp; 85 TmpInst.setOpcode(RISCV::CSRRS); 86 // Operand: rd 87 lowerOperand(MI->getOperand(0), MCOp); 88 TmpInst.addOperand(MCOp); 89 // Operand: imm12 90 TmpInst.addOperand(MCOperand::createImm(1)); 91 // Operand: rs1 92 TmpInst.addOperand(MCOperand::createReg(RISCV::X0)); 93 EmitToStreamer(OutStreamer, TmpInst); 94 break; 95 } 96 case RISCV::ReadFRM: { 97 MCInst TmpInst; 98 MCOperand MCOp; 99 TmpInst.setOpcode(RISCV::CSRRS); 100 // Operand: rd 101 lowerOperand(MI->getOperand(0), MCOp); 102 TmpInst.addOperand(MCOp); 103 // Operand: imm12 104 TmpInst.addOperand(MCOperand::createImm(2)); 105 // Operand: rs1 106 TmpInst.addOperand(MCOperand::createReg(RISCV::X0)); 107 EmitToStreamer(OutStreamer, TmpInst); 108 break; 109 } 110 case RISCV::SwapFRMImm: { 111 MCInst TmpInst; 112 MCOperand MCOp; 113 TmpInst.setOpcode(RISCV::CSRRWI); 114 // Operand: rd 115 lowerOperand(MI->getOperand(0), MCOp); 116 TmpInst.addOperand(MCOp); 117 // Operand: imm12 118 TmpInst.addOperand(MCOperand::createImm(2)); 119 // Operand: rs1 120 lowerOperand(MI->getOperand(1), MCOp); 121 TmpInst.addOperand(MCOp); 122 EmitToStreamer(OutStreamer, TmpInst); 123 break; 124 } 125 case RISCV::WriteFFLAGS: { 126 MCInst TmpInst; 127 MCOperand MCOp; 128 TmpInst.setOpcode(RISCV::CSRRW); 129 // Operand: rd 130 TmpInst.addOperand(MCOperand::createReg(RISCV::X0)); 131 // Operand: imm12 132 TmpInst.addOperand(MCOperand::createImm(1)); 133 // Operand: rs1 134 lowerOperand(MI->getOperand(0), MCOp); 135 TmpInst.addOperand(MCOp); 136 EmitToStreamer(OutStreamer, TmpInst); 137 break; 138 } 139 case RISCV::WriteFRM: { 140 MCInst TmpInst; 141 MCOperand MCOp; 142 TmpInst.setOpcode(RISCV::CSRRW); 143 // Operand: rd 144 TmpInst.addOperand(MCOperand::createReg(RISCV::X0)); 145 // Operand: imm12 146 TmpInst.addOperand(MCOperand::createImm(2)); 147 // Operand: rs1 148 lowerOperand(MI->getOperand(0), MCOp); 149 TmpInst.addOperand(MCOp); 150 EmitToStreamer(OutStreamer, TmpInst); 151 break; 152 } 153 case RISCV::WriteFRMImm: { 154 MCInst TmpInst; 155 MCOperand MCOp; 156 TmpInst.setOpcode(RISCV::CSRRWI); 157 // Operand: rd 158 TmpInst.addOperand(MCOperand::createReg(RISCV::X0)); 159 // Operand: imm12 160 TmpInst.addOperand(MCOperand::createImm(2)); 161 // Operand: rs1 162 lowerOperand(MI->getOperand(0), MCOp); 163 TmpInst.addOperand(MCOp); 164 EmitToStreamer(OutStreamer, TmpInst); 165 break; 166 } 167 } 168 return true; 169} 170 171