1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2|* *| 3|* Register Bank Source Fragments *| 4|* *| 5|* Automatically generated file, do not edit! *| 6|* *| 7\*===----------------------------------------------------------------------===*/ 8 9#ifdef GET_REGBANK_DECLARATIONS 10#undef GET_REGBANK_DECLARATIONS 11namespace llvm { 12namespace RISCV { 13enum : unsigned { 14 InvalidRegBankID = ~0u, 15 GPRRegBankID = 0, 16 NumRegisterBanks, 17}; 18} // end namespace RISCV 19} // end namespace llvm 20#endif // GET_REGBANK_DECLARATIONS 21 22#ifdef GET_TARGET_REGBANK_CLASS 23#undef GET_TARGET_REGBANK_CLASS 24private: 25 static RegisterBank *RegBanks[]; 26 27protected: 28 RISCVGenRegisterBankInfo(); 29 30#endif // GET_TARGET_REGBANK_CLASS 31 32#ifdef GET_TARGET_REGBANK_IMPL 33#undef GET_TARGET_REGBANK_IMPL 34namespace llvm { 35namespace RISCV { 36const uint32_t GPRRegBankCoverageData[] = { 37 // 0-31 38 (1u << (RISCV::GPRRegClassID - 0)) | 39 (1u << (RISCV::GPRF16RegClassID - 0)) | 40 (1u << (RISCV::GPRF32RegClassID - 0)) | 41 (1u << (RISCV::GPRF64RegClassID - 0)) | 42 (1u << (RISCV::GPRNoX0RegClassID - 0)) | 43 (1u << (RISCV::GPRNoX0X2RegClassID - 0)) | 44 (1u << (RISCV::GPRJALRRegClassID - 0)) | 45 (1u << (RISCV::GPRTCRegClassID - 0)) | 46 (1u << (RISCV::GPRC_and_GPRTCRegClassID - 0)) | 47 (1u << (RISCV::GPRCRegClassID - 0)) | 48 (1u << (RISCV::SPRegClassID - 0)) | 49 (1u << (RISCV::GPRX0RegClassID - 0)) | 50 0, 51 // 32-63 52 0, 53 // 64-95 54 0, 55}; 56 57RegisterBank GPRRegBank(/* ID */ RISCV::GPRRegBankID, /* Name */ "GPRB", /* Size */ 32, /* CoveredRegClasses */ GPRRegBankCoverageData, /* NumRegClasses */ 76); 58} // end namespace RISCV 59 60RegisterBank *RISCVGenRegisterBankInfo::RegBanks[] = { 61 &RISCV::GPRRegBank, 62}; 63 64RISCVGenRegisterBankInfo::RISCVGenRegisterBankInfo() 65 : RegisterBankInfo(RegBanks, RISCV::NumRegisterBanks) { 66 // Assert that RegBank indices match their ID's 67#ifndef NDEBUG 68 for (auto RB : enumerate(RegBanks)) 69 assert(RB.index() == RB.value()->getID() && "Index != ID"); 70#endif // NDEBUG 71} 72} // end namespace llvm 73#endif // GET_TARGET_REGBANK_IMPL 74