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1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|*                                                                            *|
3|* Calling Convention Implementation Fragment                                 *|
4|*                                                                            *|
5|* Automatically generated file, do not edit!                                 *|
6|*                                                                            *|
7\*===----------------------------------------------------------------------===*/
8
9#ifndef GET_CC_REGISTER_LISTS
10
11static bool CC_Intel_OCL_BI(unsigned ValNo, MVT ValVT,
12                            MVT LocVT, CCValAssign::LocInfo LocInfo,
13                            ISD::ArgFlagsTy ArgFlags, CCState &State);
14bool llvm::CC_X86(unsigned ValNo, MVT ValVT,
15                  MVT LocVT, CCValAssign::LocInfo LocInfo,
16                  ISD::ArgFlagsTy ArgFlags, CCState &State);
17static bool CC_X86_32(unsigned ValNo, MVT ValVT,
18                      MVT LocVT, CCValAssign::LocInfo LocInfo,
19                      ISD::ArgFlagsTy ArgFlags, CCState &State);
20static bool CC_X86_32_C(unsigned ValNo, MVT ValVT,
21                        MVT LocVT, CCValAssign::LocInfo LocInfo,
22                        ISD::ArgFlagsTy ArgFlags, CCState &State);
23static bool CC_X86_32_Common(unsigned ValNo, MVT ValVT,
24                             MVT LocVT, CCValAssign::LocInfo LocInfo,
25                             ISD::ArgFlagsTy ArgFlags, CCState &State);
26static bool CC_X86_32_FastCC(unsigned ValNo, MVT ValVT,
27                             MVT LocVT, CCValAssign::LocInfo LocInfo,
28                             ISD::ArgFlagsTy ArgFlags, CCState &State);
29static bool CC_X86_32_FastCall(unsigned ValNo, MVT ValVT,
30                               MVT LocVT, CCValAssign::LocInfo LocInfo,
31                               ISD::ArgFlagsTy ArgFlags, CCState &State);
32static bool CC_X86_32_GHC(unsigned ValNo, MVT ValVT,
33                          MVT LocVT, CCValAssign::LocInfo LocInfo,
34                          ISD::ArgFlagsTy ArgFlags, CCState &State);
35static bool CC_X86_32_HiPE(unsigned ValNo, MVT ValVT,
36                           MVT LocVT, CCValAssign::LocInfo LocInfo,
37                           ISD::ArgFlagsTy ArgFlags, CCState &State);
38static bool CC_X86_32_MCU(unsigned ValNo, MVT ValVT,
39                          MVT LocVT, CCValAssign::LocInfo LocInfo,
40                          ISD::ArgFlagsTy ArgFlags, CCState &State);
41static bool CC_X86_32_RegCall(unsigned ValNo, MVT ValVT,
42                              MVT LocVT, CCValAssign::LocInfo LocInfo,
43                              ISD::ArgFlagsTy ArgFlags, CCState &State);
44static bool CC_X86_32_ThisCall(unsigned ValNo, MVT ValVT,
45                               MVT LocVT, CCValAssign::LocInfo LocInfo,
46                               ISD::ArgFlagsTy ArgFlags, CCState &State);
47static bool CC_X86_32_ThisCall_Common(unsigned ValNo, MVT ValVT,
48                                      MVT LocVT, CCValAssign::LocInfo LocInfo,
49                                      ISD::ArgFlagsTy ArgFlags, CCState &State);
50static bool CC_X86_32_ThisCall_Mingw(unsigned ValNo, MVT ValVT,
51                                     MVT LocVT, CCValAssign::LocInfo LocInfo,
52                                     ISD::ArgFlagsTy ArgFlags, CCState &State);
53static bool CC_X86_32_ThisCall_Win(unsigned ValNo, MVT ValVT,
54                                   MVT LocVT, CCValAssign::LocInfo LocInfo,
55                                   ISD::ArgFlagsTy ArgFlags, CCState &State);
56static bool CC_X86_32_Vector_Common(unsigned ValNo, MVT ValVT,
57                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
58                                    ISD::ArgFlagsTy ArgFlags, CCState &State);
59static bool CC_X86_32_Vector_Darwin(unsigned ValNo, MVT ValVT,
60                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
61                                    ISD::ArgFlagsTy ArgFlags, CCState &State);
62static bool CC_X86_32_Vector_Standard(unsigned ValNo, MVT ValVT,
63                                      MVT LocVT, CCValAssign::LocInfo LocInfo,
64                                      ISD::ArgFlagsTy ArgFlags, CCState &State);
65static bool CC_X86_64(unsigned ValNo, MVT ValVT,
66                      MVT LocVT, CCValAssign::LocInfo LocInfo,
67                      ISD::ArgFlagsTy ArgFlags, CCState &State);
68static bool CC_X86_64_AnyReg(unsigned ValNo, MVT ValVT,
69                             MVT LocVT, CCValAssign::LocInfo LocInfo,
70                             ISD::ArgFlagsTy ArgFlags, CCState &State);
71static bool CC_X86_64_C(unsigned ValNo, MVT ValVT,
72                        MVT LocVT, CCValAssign::LocInfo LocInfo,
73                        ISD::ArgFlagsTy ArgFlags, CCState &State);
74static bool CC_X86_64_GHC(unsigned ValNo, MVT ValVT,
75                          MVT LocVT, CCValAssign::LocInfo LocInfo,
76                          ISD::ArgFlagsTy ArgFlags, CCState &State);
77static bool CC_X86_64_HHVM(unsigned ValNo, MVT ValVT,
78                           MVT LocVT, CCValAssign::LocInfo LocInfo,
79                           ISD::ArgFlagsTy ArgFlags, CCState &State);
80static bool CC_X86_64_HHVM_C(unsigned ValNo, MVT ValVT,
81                             MVT LocVT, CCValAssign::LocInfo LocInfo,
82                             ISD::ArgFlagsTy ArgFlags, CCState &State);
83static bool CC_X86_64_HiPE(unsigned ValNo, MVT ValVT,
84                           MVT LocVT, CCValAssign::LocInfo LocInfo,
85                           ISD::ArgFlagsTy ArgFlags, CCState &State);
86static bool CC_X86_64_WebKit_JS(unsigned ValNo, MVT ValVT,
87                                MVT LocVT, CCValAssign::LocInfo LocInfo,
88                                ISD::ArgFlagsTy ArgFlags, CCState &State);
89static bool CC_X86_SysV64_RegCall(unsigned ValNo, MVT ValVT,
90                                  MVT LocVT, CCValAssign::LocInfo LocInfo,
91                                  ISD::ArgFlagsTy ArgFlags, CCState &State);
92static bool CC_X86_Win32_CFGuard_Check(unsigned ValNo, MVT ValVT,
93                                       MVT LocVT, CCValAssign::LocInfo LocInfo,
94                                       ISD::ArgFlagsTy ArgFlags, CCState &State);
95static bool CC_X86_Win32_Vector(unsigned ValNo, MVT ValVT,
96                                MVT LocVT, CCValAssign::LocInfo LocInfo,
97                                ISD::ArgFlagsTy ArgFlags, CCState &State);
98static bool CC_X86_Win32_VectorCall(unsigned ValNo, MVT ValVT,
99                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
100                                    ISD::ArgFlagsTy ArgFlags, CCState &State);
101static bool CC_X86_Win64_C(unsigned ValNo, MVT ValVT,
102                           MVT LocVT, CCValAssign::LocInfo LocInfo,
103                           ISD::ArgFlagsTy ArgFlags, CCState &State);
104static bool CC_X86_Win64_RegCall(unsigned ValNo, MVT ValVT,
105                                 MVT LocVT, CCValAssign::LocInfo LocInfo,
106                                 ISD::ArgFlagsTy ArgFlags, CCState &State);
107static bool CC_X86_Win64_VectorCall(unsigned ValNo, MVT ValVT,
108                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
109                                    ISD::ArgFlagsTy ArgFlags, CCState &State);
110static bool RetCC_Intel_OCL_BI(unsigned ValNo, MVT ValVT,
111                               MVT LocVT, CCValAssign::LocInfo LocInfo,
112                               ISD::ArgFlagsTy ArgFlags, CCState &State);
113bool llvm::RetCC_X86(unsigned ValNo, MVT ValVT,
114                     MVT LocVT, CCValAssign::LocInfo LocInfo,
115                     ISD::ArgFlagsTy ArgFlags, CCState &State);
116static bool RetCC_X86Common(unsigned ValNo, MVT ValVT,
117                            MVT LocVT, CCValAssign::LocInfo LocInfo,
118                            ISD::ArgFlagsTy ArgFlags, CCState &State);
119static bool RetCC_X86_32(unsigned ValNo, MVT ValVT,
120                         MVT LocVT, CCValAssign::LocInfo LocInfo,
121                         ISD::ArgFlagsTy ArgFlags, CCState &State);
122static bool RetCC_X86_32_C(unsigned ValNo, MVT ValVT,
123                           MVT LocVT, CCValAssign::LocInfo LocInfo,
124                           ISD::ArgFlagsTy ArgFlags, CCState &State);
125static bool RetCC_X86_32_Fast(unsigned ValNo, MVT ValVT,
126                              MVT LocVT, CCValAssign::LocInfo LocInfo,
127                              ISD::ArgFlagsTy ArgFlags, CCState &State);
128static bool RetCC_X86_32_HiPE(unsigned ValNo, MVT ValVT,
129                              MVT LocVT, CCValAssign::LocInfo LocInfo,
130                              ISD::ArgFlagsTy ArgFlags, CCState &State);
131static bool RetCC_X86_32_RegCall(unsigned ValNo, MVT ValVT,
132                                 MVT LocVT, CCValAssign::LocInfo LocInfo,
133                                 ISD::ArgFlagsTy ArgFlags, CCState &State);
134static bool RetCC_X86_32_VectorCall(unsigned ValNo, MVT ValVT,
135                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
136                                    ISD::ArgFlagsTy ArgFlags, CCState &State);
137static bool RetCC_X86_64(unsigned ValNo, MVT ValVT,
138                         MVT LocVT, CCValAssign::LocInfo LocInfo,
139                         ISD::ArgFlagsTy ArgFlags, CCState &State);
140static bool RetCC_X86_64_AnyReg(unsigned ValNo, MVT ValVT,
141                                MVT LocVT, CCValAssign::LocInfo LocInfo,
142                                ISD::ArgFlagsTy ArgFlags, CCState &State);
143static bool RetCC_X86_64_C(unsigned ValNo, MVT ValVT,
144                           MVT LocVT, CCValAssign::LocInfo LocInfo,
145                           ISD::ArgFlagsTy ArgFlags, CCState &State);
146static bool RetCC_X86_64_HHVM(unsigned ValNo, MVT ValVT,
147                              MVT LocVT, CCValAssign::LocInfo LocInfo,
148                              ISD::ArgFlagsTy ArgFlags, CCState &State);
149static bool RetCC_X86_64_HiPE(unsigned ValNo, MVT ValVT,
150                              MVT LocVT, CCValAssign::LocInfo LocInfo,
151                              ISD::ArgFlagsTy ArgFlags, CCState &State);
152static bool RetCC_X86_64_Swift(unsigned ValNo, MVT ValVT,
153                               MVT LocVT, CCValAssign::LocInfo LocInfo,
154                               ISD::ArgFlagsTy ArgFlags, CCState &State);
155static bool RetCC_X86_64_Vectorcall(unsigned ValNo, MVT ValVT,
156                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
157                                    ISD::ArgFlagsTy ArgFlags, CCState &State);
158static bool RetCC_X86_64_WebKit_JS(unsigned ValNo, MVT ValVT,
159                                   MVT LocVT, CCValAssign::LocInfo LocInfo,
160                                   ISD::ArgFlagsTy ArgFlags, CCState &State);
161static bool RetCC_X86_SysV64_RegCall(unsigned ValNo, MVT ValVT,
162                                     MVT LocVT, CCValAssign::LocInfo LocInfo,
163                                     ISD::ArgFlagsTy ArgFlags, CCState &State);
164static bool RetCC_X86_Win64_C(unsigned ValNo, MVT ValVT,
165                              MVT LocVT, CCValAssign::LocInfo LocInfo,
166                              ISD::ArgFlagsTy ArgFlags, CCState &State);
167static bool RetCC_X86_Win64_RegCall(unsigned ValNo, MVT ValVT,
168                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
169                                    ISD::ArgFlagsTy ArgFlags, CCState &State);
170
171
172static bool CC_Intel_OCL_BI(unsigned ValNo, MVT ValVT,
173                            MVT LocVT, CCValAssign::LocInfo LocInfo,
174                            ISD::ArgFlagsTy ArgFlags, CCState &State) {
175
176  if (LocVT == MVT::i32) {
177    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) {
178      static const MCPhysReg RegList1[] = {
179        X86::ECX, X86::EDX, X86::R8D, X86::R9D
180      };
181      if (unsigned Reg = State.AllocateReg(RegList1)) {
182        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
183        return false;
184      }
185    }
186  }
187
188  if (LocVT == MVT::i64) {
189    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) {
190      static const MCPhysReg RegList2[] = {
191        X86::RCX, X86::RDX, X86::R8, X86::R9
192      };
193      if (unsigned Reg = State.AllocateReg(RegList2)) {
194        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
195        return false;
196      }
197    }
198  }
199
200  if (LocVT == MVT::i32) {
201    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
202      static const MCPhysReg RegList3[] = {
203        X86::EDI, X86::ESI, X86::EDX, X86::ECX
204      };
205      if (unsigned Reg = State.AllocateReg(RegList3)) {
206        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
207        return false;
208      }
209    }
210  }
211
212  if (LocVT == MVT::i64) {
213    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
214      static const MCPhysReg RegList4[] = {
215        X86::RDI, X86::RSI, X86::RDX, X86::RCX
216      };
217      if (unsigned Reg = State.AllocateReg(RegList4)) {
218        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
219        return false;
220      }
221    }
222  }
223
224  if (LocVT == MVT::i32) {
225    unsigned Offset5 = State.AllocateStack(4, Align(4));
226    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset5, LocVT, LocInfo));
227    return false;
228  }
229
230  if (LocVT == MVT::f32 ||
231      LocVT == MVT::f64 ||
232      LocVT == MVT::v4i32 ||
233      LocVT == MVT::v2i64 ||
234      LocVT == MVT::v4f32 ||
235      LocVT == MVT::v2f64) {
236    static const MCPhysReg RegList6[] = {
237      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
238    };
239    if (unsigned Reg = State.AllocateReg(RegList6)) {
240      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
241      return false;
242    }
243  }
244
245  if (LocVT == MVT::v8f32 ||
246      LocVT == MVT::v4f64 ||
247      LocVT == MVT::v8i32 ||
248      LocVT == MVT::v4i64) {
249    static const MCPhysReg RegList7[] = {
250      X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3
251    };
252    if (unsigned Reg = State.AllocateReg(RegList7)) {
253      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
254      return false;
255    }
256  }
257
258  if (LocVT == MVT::v16f32 ||
259      LocVT == MVT::v8f64 ||
260      LocVT == MVT::v16i32 ||
261      LocVT == MVT::v8i64) {
262    static const MCPhysReg RegList8[] = {
263      X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3
264    };
265    if (unsigned Reg = State.AllocateReg(RegList8)) {
266      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
267      return false;
268    }
269  }
270
271  if (LocVT == MVT::v16i1 ||
272      LocVT == MVT::v8i1) {
273    if (unsigned Reg = State.AllocateReg(X86::K1)) {
274      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
275      return false;
276    }
277  }
278
279  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) {
280    if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
281      return false;
282  }
283
284  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
285    if (!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
286      return false;
287  }
288
289  if (!CC_X86_32_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
290    return false;
291
292  return true; // CC didn't match.
293}
294
295
296bool llvm::CC_X86(unsigned ValNo, MVT ValVT,
297                  MVT LocVT, CCValAssign::LocInfo LocInfo,
298                  ISD::ArgFlagsTy ArgFlags, CCState &State) {
299
300  if (State.getCallingConv() == CallingConv::Intel_OCL_BI) {
301    if (!CC_Intel_OCL_BI(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
302      return false;
303  }
304
305  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
306    if (!CC_X86_64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
307      return false;
308  }
309
310  if (!CC_X86_32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
311    return false;
312
313  return true; // CC didn't match.
314}
315
316
317static bool CC_X86_32(unsigned ValNo, MVT ValVT,
318                      MVT LocVT, CCValAssign::LocInfo LocInfo,
319                      ISD::ArgFlagsTy ArgFlags, CCState &State) {
320
321  if (State.getCallingConv() == CallingConv::X86_INTR) {
322    if (CC_X86_Intr(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
323      return false;
324  }
325
326  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetMCU()) {
327    if (!CC_X86_32_MCU(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
328      return false;
329  }
330
331  if (State.getCallingConv() == CallingConv::X86_FastCall) {
332    if (!CC_X86_32_FastCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
333      return false;
334  }
335
336  if (State.getCallingConv() == CallingConv::X86_VectorCall) {
337    if (!CC_X86_Win32_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
338      return false;
339  }
340
341  if (State.getCallingConv() == CallingConv::X86_ThisCall) {
342    if (!CC_X86_32_ThisCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
343      return false;
344  }
345
346  if (State.getCallingConv() == CallingConv::CFGuard_Check) {
347    if (!CC_X86_Win32_CFGuard_Check(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
348      return false;
349  }
350
351  if (State.getCallingConv() == CallingConv::Fast) {
352    if (!CC_X86_32_FastCC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
353      return false;
354  }
355
356  if (State.getCallingConv() == CallingConv::Tail) {
357    if (!CC_X86_32_FastCC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
358      return false;
359  }
360
361  if (State.getCallingConv() == CallingConv::GHC) {
362    if (!CC_X86_32_GHC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
363      return false;
364  }
365
366  if (State.getCallingConv() == CallingConv::HiPE) {
367    if (!CC_X86_32_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
368      return false;
369  }
370
371  if (State.getCallingConv() == CallingConv::X86_RegCall) {
372    if (!CC_X86_32_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
373      return false;
374  }
375
376  if (!CC_X86_32_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
377    return false;
378
379  return true; // CC didn't match.
380}
381
382
383static bool CC_X86_32_C(unsigned ValNo, MVT ValVT,
384                        MVT LocVT, CCValAssign::LocInfo LocInfo,
385                        ISD::ArgFlagsTy ArgFlags, CCState &State) {
386
387  if (LocVT == MVT::i1 ||
388      LocVT == MVT::i8 ||
389      LocVT == MVT::i16 ||
390      LocVT == MVT::v1i1) {
391    LocVT = MVT::i32;
392    if (ArgFlags.isSExt())
393      LocInfo = CCValAssign::SExt;
394    else if (ArgFlags.isZExt())
395      LocInfo = CCValAssign::ZExt;
396    else
397      LocInfo = CCValAssign::AExt;
398  }
399
400  if (ArgFlags.isNest()) {
401    if (unsigned Reg = State.AllocateReg(X86::ECX)) {
402      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
403      return false;
404    }
405  }
406
407  if (State.getCallingConv() == CallingConv::SwiftTail) {
408    if (ArgFlags.isSwiftSelf()) {
409      if (LocVT == MVT::i32) {
410        if (unsigned Reg = State.AllocateReg(X86::ECX)) {
411          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
412          return false;
413        }
414      }
415    }
416  }
417
418  if (!State.isVarArg()) {
419    if (ArgFlags.isInReg()) {
420      if (LocVT == MVT::i32) {
421        static const MCPhysReg RegList1[] = {
422          X86::EAX, X86::EDX, X86::ECX
423        };
424        if (unsigned Reg = State.AllocateReg(RegList1)) {
425          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
426          return false;
427        }
428      }
429    }
430  }
431
432  if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
433    return false;
434
435  return true; // CC didn't match.
436}
437
438
439static bool CC_X86_32_Common(unsigned ValNo, MVT ValVT,
440                             MVT LocVT, CCValAssign::LocInfo LocInfo,
441                             ISD::ArgFlagsTy ArgFlags, CCState &State) {
442
443  if (ArgFlags.isByVal()) {
444    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, Align(4), ArgFlags);
445    return false;
446  }
447
448  if (ArgFlags.isPreallocated()) {
449    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, Align(4), ArgFlags);
450    return false;
451  }
452
453  if (!State.isVarArg()) {
454    if (ArgFlags.isInReg()) {
455      if (LocVT == MVT::f32 ||
456          LocVT == MVT::f64) {
457        if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()) {
458          static const MCPhysReg RegList1[] = {
459            X86::XMM0, X86::XMM1, X86::XMM2
460          };
461          if (unsigned Reg = State.AllocateReg(RegList1)) {
462            State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
463            return false;
464          }
465        }
466      }
467    }
468  }
469
470  if (!State.isVarArg()) {
471    if (ArgFlags.isInReg()) {
472      if (LocVT == MVT::f16) {
473        static const MCPhysReg RegList2[] = {
474          X86::XMM0, X86::XMM1, X86::XMM2
475        };
476        if (unsigned Reg = State.AllocateReg(RegList2)) {
477          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
478          return false;
479        }
480      }
481    }
482  }
483
484  if (!State.isVarArg()) {
485    if (LocVT == MVT::x86mmx) {
486      static const MCPhysReg RegList3[] = {
487        X86::MM0, X86::MM1, X86::MM2
488      };
489      if (unsigned Reg = State.AllocateReg(RegList3)) {
490        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
491        return false;
492      }
493    }
494  }
495
496  if (LocVT == MVT::f16) {
497    unsigned Offset4 = State.AllocateStack(4, Align(4));
498    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset4, LocVT, LocInfo));
499    return false;
500  }
501
502  if (LocVT == MVT::i32 ||
503      LocVT == MVT::f32) {
504    unsigned Offset5 = State.AllocateStack(4, Align(4));
505    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset5, LocVT, LocInfo));
506    return false;
507  }
508
509  if (LocVT == MVT::f64) {
510    unsigned Offset6 = State.AllocateStack(8, Align(4));
511    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo));
512    return false;
513  }
514
515  if (LocVT == MVT::f80) {
516    unsigned Offset7 = State.AllocateStack(
517      State.getMachineFunction().getDataLayout().getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())),
518      State.getMachineFunction().getDataLayout().getABITypeAlign(EVT(LocVT).getTypeForEVT(State.getContext())));
519    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset7, LocVT, LocInfo));
520    return false;
521  }
522
523  if (LocVT == MVT::v2i1) {
524    LocVT = MVT::v2i64;
525    if (ArgFlags.isSExt())
526      LocInfo = CCValAssign::SExt;
527    else if (ArgFlags.isZExt())
528      LocInfo = CCValAssign::ZExt;
529    else
530      LocInfo = CCValAssign::AExt;
531  }
532
533  if (LocVT == MVT::v4i1) {
534    LocVT = MVT::v4i32;
535    if (ArgFlags.isSExt())
536      LocInfo = CCValAssign::SExt;
537    else if (ArgFlags.isZExt())
538      LocInfo = CCValAssign::ZExt;
539    else
540      LocInfo = CCValAssign::AExt;
541  }
542
543  if (LocVT == MVT::v8i1) {
544    LocVT = MVT::v8i16;
545    if (ArgFlags.isSExt())
546      LocInfo = CCValAssign::SExt;
547    else if (ArgFlags.isZExt())
548      LocInfo = CCValAssign::ZExt;
549    else
550      LocInfo = CCValAssign::AExt;
551  }
552
553  if (LocVT == MVT::v16i1) {
554    LocVT = MVT::v16i8;
555    if (ArgFlags.isSExt())
556      LocInfo = CCValAssign::SExt;
557    else if (ArgFlags.isZExt())
558      LocInfo = CCValAssign::ZExt;
559    else
560      LocInfo = CCValAssign::AExt;
561  }
562
563  if (LocVT == MVT::v32i1) {
564    LocVT = MVT::v32i8;
565    if (ArgFlags.isSExt())
566      LocInfo = CCValAssign::SExt;
567    else if (ArgFlags.isZExt())
568      LocInfo = CCValAssign::ZExt;
569    else
570      LocInfo = CCValAssign::AExt;
571  }
572
573  if (LocVT == MVT::v64i1) {
574    LocVT = MVT::v64i8;
575    if (ArgFlags.isSExt())
576      LocInfo = CCValAssign::SExt;
577    else if (ArgFlags.isZExt())
578      LocInfo = CCValAssign::ZExt;
579    else
580      LocInfo = CCValAssign::AExt;
581  }
582
583  if (LocVT == MVT::x86mmx) {
584    unsigned Offset8 = State.AllocateStack(8, Align(4));
585    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset8, LocVT, LocInfo));
586    return false;
587  }
588
589  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetDarwin()) {
590    if (!CC_X86_32_Vector_Darwin(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
591      return false;
592  }
593
594  if (!CC_X86_32_Vector_Standard(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
595    return false;
596
597  return true; // CC didn't match.
598}
599
600
601static bool CC_X86_32_FastCC(unsigned ValNo, MVT ValVT,
602                             MVT LocVT, CCValAssign::LocInfo LocInfo,
603                             ISD::ArgFlagsTy ArgFlags, CCState &State) {
604
605  if (ArgFlags.isByVal()) {
606    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, Align(4), ArgFlags);
607    return false;
608  }
609
610  if (LocVT == MVT::i1 ||
611      LocVT == MVT::i8 ||
612      LocVT == MVT::i16 ||
613      LocVT == MVT::v1i1) {
614    LocVT = MVT::i32;
615    if (ArgFlags.isSExt())
616      LocInfo = CCValAssign::SExt;
617    else if (ArgFlags.isZExt())
618      LocInfo = CCValAssign::ZExt;
619    else
620      LocInfo = CCValAssign::AExt;
621  }
622
623  if (ArgFlags.isNest()) {
624    if (unsigned Reg = State.AllocateReg(X86::EAX)) {
625      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
626      return false;
627    }
628  }
629
630  if (LocVT == MVT::i32) {
631    static const MCPhysReg RegList1[] = {
632      X86::ECX, X86::EDX
633    };
634    if (unsigned Reg = State.AllocateReg(RegList1)) {
635      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
636      return false;
637    }
638  }
639
640  if (!State.isVarArg()) {
641    if (LocVT == MVT::f32 ||
642        LocVT == MVT::f64) {
643      if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()) {
644        static const MCPhysReg RegList2[] = {
645          X86::XMM0, X86::XMM1, X86::XMM2
646        };
647        if (unsigned Reg = State.AllocateReg(RegList2)) {
648          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
649          return false;
650        }
651      }
652    }
653  }
654
655  if (LocVT == MVT::f64) {
656    unsigned Offset3 = State.AllocateStack(8, Align(8));
657    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo));
658    return false;
659  }
660
661  if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
662    return false;
663
664  return true; // CC didn't match.
665}
666
667
668static bool CC_X86_32_FastCall(unsigned ValNo, MVT ValVT,
669                               MVT LocVT, CCValAssign::LocInfo LocInfo,
670                               ISD::ArgFlagsTy ArgFlags, CCState &State) {
671
672  if (LocVT == MVT::i1) {
673    LocVT = MVT::i8;
674    if (ArgFlags.isSExt())
675      LocInfo = CCValAssign::SExt;
676    else if (ArgFlags.isZExt())
677      LocInfo = CCValAssign::ZExt;
678    else
679      LocInfo = CCValAssign::AExt;
680  }
681
682  if (ArgFlags.isNest()) {
683    if (unsigned Reg = State.AllocateReg(X86::EAX)) {
684      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
685      return false;
686    }
687  }
688
689  if (ArgFlags.isInReg()) {
690    if (LocVT == MVT::i8) {
691      static const MCPhysReg RegList1[] = {
692        X86::CL, X86::DL
693      };
694      if (unsigned Reg = State.AllocateReg(RegList1)) {
695        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
696        return false;
697      }
698    }
699  }
700
701  if (ArgFlags.isInReg()) {
702    if (LocVT == MVT::i16) {
703      static const MCPhysReg RegList2[] = {
704        X86::CX, X86::DX
705      };
706      if (unsigned Reg = State.AllocateReg(RegList2)) {
707        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
708        return false;
709      }
710    }
711  }
712
713  if (ArgFlags.isInReg()) {
714    if (LocVT == MVT::i32) {
715      static const MCPhysReg RegList3[] = {
716        X86::ECX, X86::EDX
717      };
718      if (unsigned Reg = State.AllocateReg(RegList3)) {
719        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
720        return false;
721      }
722    }
723  }
724
725  if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
726    return false;
727
728  return true; // CC didn't match.
729}
730
731
732static bool CC_X86_32_GHC(unsigned ValNo, MVT ValVT,
733                          MVT LocVT, CCValAssign::LocInfo LocInfo,
734                          ISD::ArgFlagsTy ArgFlags, CCState &State) {
735
736  if (LocVT == MVT::i8 ||
737      LocVT == MVT::i16) {
738    LocVT = MVT::i32;
739    if (ArgFlags.isSExt())
740      LocInfo = CCValAssign::SExt;
741    else if (ArgFlags.isZExt())
742      LocInfo = CCValAssign::ZExt;
743    else
744      LocInfo = CCValAssign::AExt;
745  }
746
747  if (LocVT == MVT::i32) {
748    static const MCPhysReg RegList1[] = {
749      X86::EBX, X86::EBP, X86::EDI, X86::ESI
750    };
751    if (unsigned Reg = State.AllocateReg(RegList1)) {
752      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
753      return false;
754    }
755  }
756
757  return true; // CC didn't match.
758}
759
760
761static bool CC_X86_32_HiPE(unsigned ValNo, MVT ValVT,
762                           MVT LocVT, CCValAssign::LocInfo LocInfo,
763                           ISD::ArgFlagsTy ArgFlags, CCState &State) {
764
765  if (LocVT == MVT::i8 ||
766      LocVT == MVT::i16) {
767    LocVT = MVT::i32;
768    if (ArgFlags.isSExt())
769      LocInfo = CCValAssign::SExt;
770    else if (ArgFlags.isZExt())
771      LocInfo = CCValAssign::ZExt;
772    else
773      LocInfo = CCValAssign::AExt;
774  }
775
776  if (LocVT == MVT::i32) {
777    static const MCPhysReg RegList1[] = {
778      X86::ESI, X86::EBP, X86::EAX, X86::EDX, X86::ECX
779    };
780    if (unsigned Reg = State.AllocateReg(RegList1)) {
781      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
782      return false;
783    }
784  }
785
786  if (LocVT == MVT::i32 ||
787      LocVT == MVT::f32) {
788    unsigned Offset2 = State.AllocateStack(4, Align(4));
789    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
790    return false;
791  }
792
793  return true; // CC didn't match.
794}
795
796
797static bool CC_X86_32_MCU(unsigned ValNo, MVT ValVT,
798                          MVT LocVT, CCValAssign::LocInfo LocInfo,
799                          ISD::ArgFlagsTy ArgFlags, CCState &State) {
800
801  if (ArgFlags.isByVal()) {
802    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, Align(4), ArgFlags);
803    return false;
804  }
805
806  if (LocVT == MVT::i1 ||
807      LocVT == MVT::i8 ||
808      LocVT == MVT::i16 ||
809      LocVT == MVT::v1i1) {
810    LocVT = MVT::i32;
811    if (ArgFlags.isSExt())
812      LocInfo = CCValAssign::SExt;
813    else if (ArgFlags.isZExt())
814      LocInfo = CCValAssign::ZExt;
815    else
816      LocInfo = CCValAssign::AExt;
817  }
818
819  if (!State.isVarArg()) {
820    if (LocVT == MVT::i32) {
821      if (CC_X86_32_MCUInReg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
822        return false;
823    }
824  }
825
826  if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
827    return false;
828
829  return true; // CC didn't match.
830}
831
832
833static bool CC_X86_32_RegCall(unsigned ValNo, MVT ValVT,
834                              MVT LocVT, CCValAssign::LocInfo LocInfo,
835                              ISD::ArgFlagsTy ArgFlags, CCState &State) {
836
837  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
838    if (ArgFlags.isByVal()) {
839      State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, Align(8), ArgFlags);
840      return false;
841    }
842  }
843
844  if (ArgFlags.isByVal()) {
845    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, Align(4), ArgFlags);
846    return false;
847  }
848
849  if (LocVT == MVT::i1 ||
850      LocVT == MVT::i8 ||
851      LocVT == MVT::i16 ||
852      LocVT == MVT::v1i1) {
853    LocVT = MVT::i32;
854    if (ArgFlags.isSExt())
855      LocInfo = CCValAssign::SExt;
856    else if (ArgFlags.isZExt())
857      LocInfo = CCValAssign::ZExt;
858    else
859      LocInfo = CCValAssign::AExt;
860  }
861
862  if (LocVT == MVT::v8i1 ||
863      LocVT == MVT::v16i1 ||
864      LocVT == MVT::v32i1) {
865    LocVT = MVT::i32;
866    if (ArgFlags.isSExt())
867      LocInfo = CCValAssign::SExt;
868    else if (ArgFlags.isZExt())
869      LocInfo = CCValAssign::ZExt;
870    else
871      LocInfo = CCValAssign::AExt;
872  }
873
874  if (LocVT == MVT::i32) {
875    static const MCPhysReg RegList1[] = {
876      X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI
877    };
878    if (unsigned Reg = State.AllocateReg(RegList1)) {
879      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
880      return false;
881    }
882  }
883
884  if (LocVT == MVT::i64) {
885    if (unsigned Reg = State.AllocateReg(X86::RAX)) {
886      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
887      return false;
888    }
889  }
890
891  if (LocVT == MVT::v64i1) {
892    LocVT = MVT::i64;
893    if (ArgFlags.isSExt())
894      LocInfo = CCValAssign::SExt;
895    else if (ArgFlags.isZExt())
896      LocInfo = CCValAssign::ZExt;
897    else
898      LocInfo = CCValAssign::AExt;
899  }
900
901  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
902    if (LocVT == MVT::i64) {
903      if (unsigned Reg = State.AllocateReg(X86::RAX)) {
904        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
905        return false;
906      }
907    }
908  }
909
910  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()) {
911    if (LocVT == MVT::i64) {
912      if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
913        return false;
914    }
915  }
916
917  if (LocVT == MVT::f32 ||
918      LocVT == MVT::f64 ||
919      LocVT == MVT::f128) {
920    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
921      static const MCPhysReg RegList2[] = {
922        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
923      };
924      if (unsigned Reg = State.AllocateReg(RegList2)) {
925        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
926        return false;
927      }
928    }
929  }
930
931  if (LocVT == MVT::f80) {
932    if (unsigned Reg = State.AllocateReg(X86::FP0)) {
933      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
934      return false;
935    }
936  }
937
938  if (LocVT == MVT::v16i8 ||
939      LocVT == MVT::v8i16 ||
940      LocVT == MVT::v4i32 ||
941      LocVT == MVT::v2i64 ||
942      LocVT == MVT::v4f32 ||
943      LocVT == MVT::v2f64) {
944    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
945      static const MCPhysReg RegList3[] = {
946        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
947      };
948      if (unsigned Reg = State.AllocateReg(RegList3)) {
949        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
950        return false;
951      }
952    }
953  }
954
955  if (LocVT == MVT::v32i8 ||
956      LocVT == MVT::v16i16 ||
957      LocVT == MVT::v8i32 ||
958      LocVT == MVT::v4i64 ||
959      LocVT == MVT::v8f32 ||
960      LocVT == MVT::v4f64) {
961    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
962      static const MCPhysReg RegList4[] = {
963        X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7
964      };
965      if (unsigned Reg = State.AllocateReg(RegList4)) {
966        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
967        return false;
968      }
969    }
970  }
971
972  if (LocVT == MVT::v64i8 ||
973      LocVT == MVT::v32i16 ||
974      LocVT == MVT::v16i32 ||
975      LocVT == MVT::v8i64 ||
976      LocVT == MVT::v16f32 ||
977      LocVT == MVT::v8f64) {
978    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) {
979      static const MCPhysReg RegList5[] = {
980        X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7
981      };
982      if (unsigned Reg = State.AllocateReg(RegList5)) {
983        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
984        return false;
985      }
986    }
987  }
988
989  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
990    if (LocVT == MVT::i32 ||
991        LocVT == MVT::i64 ||
992        LocVT == MVT::f32 ||
993        LocVT == MVT::f64) {
994      unsigned Offset6 = State.AllocateStack(8, Align(8));
995      State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo));
996      return false;
997    }
998  }
999
1000  if (LocVT == MVT::i32 ||
1001      LocVT == MVT::f32) {
1002    unsigned Offset7 = State.AllocateStack(4, Align(4));
1003    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset7, LocVT, LocInfo));
1004    return false;
1005  }
1006
1007  if (LocVT == MVT::i64 ||
1008      LocVT == MVT::f64) {
1009    unsigned Offset8 = State.AllocateStack(8, Align(4));
1010    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset8, LocVT, LocInfo));
1011    return false;
1012  }
1013
1014  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
1015    if (LocVT == MVT::x86mmx) {
1016      unsigned Offset9 = State.AllocateStack(8, Align(8));
1017      State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset9, LocVT, LocInfo));
1018      return false;
1019    }
1020  }
1021
1022  if (LocVT == MVT::x86mmx) {
1023    unsigned Offset10 = State.AllocateStack(8, Align(4));
1024    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset10, LocVT, LocInfo));
1025    return false;
1026  }
1027
1028  if (LocVT == MVT::f80 ||
1029      LocVT == MVT::f128) {
1030    unsigned Offset11 = State.AllocateStack(
1031      State.getMachineFunction().getDataLayout().getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())),
1032      State.getMachineFunction().getDataLayout().getABITypeAlign(EVT(LocVT).getTypeForEVT(State.getContext())));
1033    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset11, LocVT, LocInfo));
1034    return false;
1035  }
1036
1037  if (LocVT == MVT::v16i8 ||
1038      LocVT == MVT::v8i16 ||
1039      LocVT == MVT::v4i32 ||
1040      LocVT == MVT::v2i64 ||
1041      LocVT == MVT::v4f32 ||
1042      LocVT == MVT::v2f64) {
1043    unsigned Offset12 = State.AllocateStack(16, Align(16));
1044    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset12, LocVT, LocInfo));
1045    return false;
1046  }
1047
1048  if (LocVT == MVT::v32i8 ||
1049      LocVT == MVT::v16i16 ||
1050      LocVT == MVT::v8i32 ||
1051      LocVT == MVT::v4i64 ||
1052      LocVT == MVT::v8f32 ||
1053      LocVT == MVT::v4f64) {
1054    unsigned Offset13 = State.AllocateStack(32, Align(32));
1055    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset13, LocVT, LocInfo));
1056    return false;
1057  }
1058
1059  if (LocVT == MVT::v64i8 ||
1060      LocVT == MVT::v32i16 ||
1061      LocVT == MVT::v16i32 ||
1062      LocVT == MVT::v8i64 ||
1063      LocVT == MVT::v16f32 ||
1064      LocVT == MVT::v8f64) {
1065    unsigned Offset14 = State.AllocateStack(64, Align(64));
1066    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset14, LocVT, LocInfo));
1067    return false;
1068  }
1069
1070  return true; // CC didn't match.
1071}
1072
1073
1074static bool CC_X86_32_ThisCall(unsigned ValNo, MVT ValVT,
1075                               MVT LocVT, CCValAssign::LocInfo LocInfo,
1076                               ISD::ArgFlagsTy ArgFlags, CCState &State) {
1077
1078  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetCygMing()) {
1079    if (!CC_X86_32_ThisCall_Mingw(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1080      return false;
1081  }
1082
1083  if (!CC_X86_32_ThisCall_Win(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1084    return false;
1085
1086  return true; // CC didn't match.
1087}
1088
1089
1090static bool CC_X86_32_ThisCall_Common(unsigned ValNo, MVT ValVT,
1091                                      MVT LocVT, CCValAssign::LocInfo LocInfo,
1092                                      ISD::ArgFlagsTy ArgFlags, CCState &State) {
1093
1094  if (LocVT == MVT::i32) {
1095    if (unsigned Reg = State.AllocateReg(X86::ECX)) {
1096      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1097      return false;
1098    }
1099  }
1100
1101  if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1102    return false;
1103
1104  return true; // CC didn't match.
1105}
1106
1107
1108static bool CC_X86_32_ThisCall_Mingw(unsigned ValNo, MVT ValVT,
1109                                     MVT LocVT, CCValAssign::LocInfo LocInfo,
1110                                     ISD::ArgFlagsTy ArgFlags, CCState &State) {
1111
1112  if (LocVT == MVT::i1 ||
1113      LocVT == MVT::i8 ||
1114      LocVT == MVT::i16 ||
1115      LocVT == MVT::v1i1) {
1116    LocVT = MVT::i32;
1117    if (ArgFlags.isSExt())
1118      LocInfo = CCValAssign::SExt;
1119    else if (ArgFlags.isZExt())
1120      LocInfo = CCValAssign::ZExt;
1121    else
1122      LocInfo = CCValAssign::AExt;
1123  }
1124
1125  if (!CC_X86_32_ThisCall_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1126    return false;
1127
1128  return true; // CC didn't match.
1129}
1130
1131
1132static bool CC_X86_32_ThisCall_Win(unsigned ValNo, MVT ValVT,
1133                                   MVT LocVT, CCValAssign::LocInfo LocInfo,
1134                                   ISD::ArgFlagsTy ArgFlags, CCState &State) {
1135
1136  if (LocVT == MVT::i1 ||
1137      LocVT == MVT::i8 ||
1138      LocVT == MVT::i16 ||
1139      LocVT == MVT::v1i1) {
1140    LocVT = MVT::i32;
1141    if (ArgFlags.isSExt())
1142      LocInfo = CCValAssign::SExt;
1143    else if (ArgFlags.isZExt())
1144      LocInfo = CCValAssign::ZExt;
1145    else
1146      LocInfo = CCValAssign::AExt;
1147  }
1148
1149  if (ArgFlags.isSRet()) {
1150    unsigned Offset1 = State.AllocateStack(4, Align(4));
1151    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo));
1152    return false;
1153  }
1154
1155  if (!CC_X86_32_ThisCall_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1156    return false;
1157
1158  return true; // CC didn't match.
1159}
1160
1161
1162static bool CC_X86_32_Vector_Common(unsigned ValNo, MVT ValVT,
1163                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
1164                                    ISD::ArgFlagsTy ArgFlags, CCState &State) {
1165
1166  if (LocVT == MVT::v16i8 ||
1167      LocVT == MVT::v8i16 ||
1168      LocVT == MVT::v4i32 ||
1169      LocVT == MVT::v2i64 ||
1170      LocVT == MVT::v8f16 ||
1171      LocVT == MVT::v4f32 ||
1172      LocVT == MVT::v2f64) {
1173    unsigned Offset1 = State.AllocateStack(16, Align(16));
1174    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo));
1175    return false;
1176  }
1177
1178  if (LocVT == MVT::v32i8 ||
1179      LocVT == MVT::v16i16 ||
1180      LocVT == MVT::v8i32 ||
1181      LocVT == MVT::v4i64 ||
1182      LocVT == MVT::v16f16 ||
1183      LocVT == MVT::v8f32 ||
1184      LocVT == MVT::v4f64) {
1185    unsigned Offset2 = State.AllocateStack(32, Align(32));
1186    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
1187    return false;
1188  }
1189
1190  if (LocVT == MVT::v64i8 ||
1191      LocVT == MVT::v32i16 ||
1192      LocVT == MVT::v16i32 ||
1193      LocVT == MVT::v8i64 ||
1194      LocVT == MVT::v32f16 ||
1195      LocVT == MVT::v16f32 ||
1196      LocVT == MVT::v8f64) {
1197    unsigned Offset3 = State.AllocateStack(64, Align(64));
1198    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo));
1199    return false;
1200  }
1201
1202  return true; // CC didn't match.
1203}
1204
1205
1206static bool CC_X86_32_Vector_Darwin(unsigned ValNo, MVT ValVT,
1207                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
1208                                    ISD::ArgFlagsTy ArgFlags, CCState &State) {
1209
1210  if (!State.isVarArg()) {
1211    if (LocVT == MVT::v16i8 ||
1212        LocVT == MVT::v8i16 ||
1213        LocVT == MVT::v4i32 ||
1214        LocVT == MVT::v2i64 ||
1215        LocVT == MVT::v8f16 ||
1216        LocVT == MVT::v4f32 ||
1217        LocVT == MVT::v2f64) {
1218      static const MCPhysReg RegList1[] = {
1219        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1220      };
1221      if (unsigned Reg = State.AllocateReg(RegList1)) {
1222        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1223        return false;
1224      }
1225    }
1226  }
1227
1228  if (!State.isVarArg()) {
1229    if (LocVT == MVT::v32i8 ||
1230        LocVT == MVT::v16i16 ||
1231        LocVT == MVT::v8i32 ||
1232        LocVT == MVT::v4i64 ||
1233        LocVT == MVT::v16f16 ||
1234        LocVT == MVT::v8f32 ||
1235        LocVT == MVT::v4f64) {
1236      if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
1237        static const MCPhysReg RegList2[] = {
1238          X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3
1239        };
1240        if (unsigned Reg = State.AllocateReg(RegList2)) {
1241          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1242          return false;
1243        }
1244      }
1245    }
1246  }
1247
1248  if (!State.isVarArg()) {
1249    if (LocVT == MVT::v64i8 ||
1250        LocVT == MVT::v32i16 ||
1251        LocVT == MVT::v16i32 ||
1252        LocVT == MVT::v8i64 ||
1253        LocVT == MVT::v32f16 ||
1254        LocVT == MVT::v16f32 ||
1255        LocVT == MVT::v8f64) {
1256      static const MCPhysReg RegList3[] = {
1257        X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3
1258      };
1259      if (unsigned Reg = State.AllocateReg(RegList3)) {
1260        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1261        return false;
1262      }
1263    }
1264  }
1265
1266  if (!CC_X86_32_Vector_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1267    return false;
1268
1269  return true; // CC didn't match.
1270}
1271
1272
1273static bool CC_X86_32_Vector_Standard(unsigned ValNo, MVT ValVT,
1274                                      MVT LocVT, CCValAssign::LocInfo LocInfo,
1275                                      ISD::ArgFlagsTy ArgFlags, CCState &State) {
1276
1277  if (!State.isVarArg()) {
1278    if (LocVT == MVT::v16i8 ||
1279        LocVT == MVT::v8i16 ||
1280        LocVT == MVT::v4i32 ||
1281        LocVT == MVT::v2i64 ||
1282        LocVT == MVT::v8f16 ||
1283        LocVT == MVT::v4f32 ||
1284        LocVT == MVT::v2f64) {
1285      static const MCPhysReg RegList1[] = {
1286        X86::XMM0, X86::XMM1, X86::XMM2
1287      };
1288      if (unsigned Reg = State.AllocateReg(RegList1)) {
1289        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1290        return false;
1291      }
1292    }
1293  }
1294
1295  if (!State.isVarArg()) {
1296    if (LocVT == MVT::v32i8 ||
1297        LocVT == MVT::v16i16 ||
1298        LocVT == MVT::v8i32 ||
1299        LocVT == MVT::v4i64 ||
1300        LocVT == MVT::v16f16 ||
1301        LocVT == MVT::v8f32 ||
1302        LocVT == MVT::v4f64) {
1303      if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
1304        static const MCPhysReg RegList2[] = {
1305          X86::YMM0, X86::YMM1, X86::YMM2
1306        };
1307        if (unsigned Reg = State.AllocateReg(RegList2)) {
1308          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1309          return false;
1310        }
1311      }
1312    }
1313  }
1314
1315  if (!State.isVarArg()) {
1316    if (LocVT == MVT::v64i8 ||
1317        LocVT == MVT::v32i16 ||
1318        LocVT == MVT::v16i32 ||
1319        LocVT == MVT::v8i64 ||
1320        LocVT == MVT::v32f16 ||
1321        LocVT == MVT::v16f32 ||
1322        LocVT == MVT::v8f64) {
1323      static const MCPhysReg RegList3[] = {
1324        X86::ZMM0, X86::ZMM1, X86::ZMM2
1325      };
1326      if (unsigned Reg = State.AllocateReg(RegList3)) {
1327        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1328        return false;
1329      }
1330    }
1331  }
1332
1333  if (State.isVarArg() && State.getMachineFunction().getSubtarget().getTargetTriple().isWindowsMSVCEnvironment()) {
1334    if (!CC_X86_Win32_Vector(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1335      return false;
1336  }
1337
1338  if (!CC_X86_32_Vector_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1339    return false;
1340
1341  return true; // CC didn't match.
1342}
1343
1344
1345static bool CC_X86_64(unsigned ValNo, MVT ValVT,
1346                      MVT LocVT, CCValAssign::LocInfo LocInfo,
1347                      ISD::ArgFlagsTy ArgFlags, CCState &State) {
1348
1349  if (State.getCallingConv() == CallingConv::GHC) {
1350    if (!CC_X86_64_GHC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1351      return false;
1352  }
1353
1354  if (State.getCallingConv() == CallingConv::HiPE) {
1355    if (!CC_X86_64_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1356      return false;
1357  }
1358
1359  if (State.getCallingConv() == CallingConv::WebKit_JS) {
1360    if (!CC_X86_64_WebKit_JS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1361      return false;
1362  }
1363
1364  if (State.getCallingConv() == CallingConv::AnyReg) {
1365    if (!CC_X86_64_AnyReg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1366      return false;
1367  }
1368
1369  if (State.getCallingConv() == CallingConv::Win64) {
1370    if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1371      return false;
1372  }
1373
1374  if (State.getCallingConv() == CallingConv::X86_64_SysV) {
1375    if (!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1376      return false;
1377  }
1378
1379  if (State.getCallingConv() == CallingConv::X86_VectorCall) {
1380    if (!CC_X86_Win64_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1381      return false;
1382  }
1383
1384  if (State.getCallingConv() == CallingConv::HHVM) {
1385    if (!CC_X86_64_HHVM(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1386      return false;
1387  }
1388
1389  if (State.getCallingConv() == CallingConv::HHVM_C) {
1390    if (!CC_X86_64_HHVM_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1391      return false;
1392  }
1393
1394  if (State.getCallingConv() == CallingConv::X86_RegCall) {
1395    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) {
1396      if (!CC_X86_Win64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1397        return false;
1398    }
1399  }
1400
1401  if (State.getCallingConv() == CallingConv::X86_RegCall) {
1402    if (!CC_X86_SysV64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1403      return false;
1404  }
1405
1406  if (State.getCallingConv() == CallingConv::X86_INTR) {
1407    if (CC_X86_Intr(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1408      return false;
1409  }
1410
1411  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) {
1412    if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1413      return false;
1414  }
1415
1416  if (!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1417    return false;
1418
1419  return true; // CC didn't match.
1420}
1421
1422
1423static bool CC_X86_64_AnyReg(unsigned ValNo, MVT ValVT,
1424                             MVT LocVT, CCValAssign::LocInfo LocInfo,
1425                             ISD::ArgFlagsTy ArgFlags, CCState &State) {
1426
1427  if (CC_X86_AnyReg_Error(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1428    return false;
1429
1430  return true; // CC didn't match.
1431}
1432
1433
1434static bool CC_X86_64_C(unsigned ValNo, MVT ValVT,
1435                        MVT LocVT, CCValAssign::LocInfo LocInfo,
1436                        ISD::ArgFlagsTy ArgFlags, CCState &State) {
1437
1438  if (ArgFlags.isByVal()) {
1439    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, Align(8), ArgFlags);
1440    return false;
1441  }
1442
1443  if (LocVT == MVT::i1 ||
1444      LocVT == MVT::i8 ||
1445      LocVT == MVT::i16 ||
1446      LocVT == MVT::v1i1) {
1447    LocVT = MVT::i32;
1448    if (ArgFlags.isSExt())
1449      LocInfo = CCValAssign::SExt;
1450    else if (ArgFlags.isZExt())
1451      LocInfo = CCValAssign::ZExt;
1452    else
1453      LocInfo = CCValAssign::AExt;
1454  }
1455
1456  if (ArgFlags.isNest()) {
1457    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTarget64BitILP32()) {
1458      if (unsigned Reg = State.AllocateReg(X86::R10D)) {
1459        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1460        return false;
1461      }
1462    }
1463  }
1464
1465  if (ArgFlags.isNest()) {
1466    if (unsigned Reg = State.AllocateReg(X86::R10)) {
1467      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1468      return false;
1469    }
1470  }
1471
1472  if (ArgFlags.isSwiftSelf()) {
1473    if (LocVT == MVT::i64) {
1474      if (unsigned Reg = State.AllocateReg(X86::R13)) {
1475        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1476        return false;
1477      }
1478    }
1479  }
1480
1481  if (ArgFlags.isSwiftError()) {
1482    if (LocVT == MVT::i64) {
1483      if (unsigned Reg = State.AllocateReg(X86::R12)) {
1484        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1485        return false;
1486      }
1487    }
1488  }
1489
1490  if (ArgFlags.isSwiftAsync()) {
1491    if (LocVT == MVT::i64) {
1492      if (unsigned Reg = State.AllocateReg(X86::R14)) {
1493        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1494        return false;
1495      }
1496    }
1497  }
1498
1499  if (State.getCallingConv() == CallingConv::Swift) {
1500    if (ArgFlags.isSRet()) {
1501      if (LocVT == MVT::i64) {
1502        if (unsigned Reg = State.AllocateReg(X86::RAX)) {
1503          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1504          return false;
1505        }
1506      }
1507    }
1508  }
1509
1510  if (State.getCallingConv() == CallingConv::SwiftTail) {
1511    if (ArgFlags.isSRet()) {
1512      if (LocVT == MVT::i64) {
1513        if (unsigned Reg = State.AllocateReg(X86::RAX)) {
1514          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1515          return false;
1516        }
1517      }
1518    }
1519  }
1520
1521  if (ArgFlags.isPointer()) {
1522    if (CC_X86_64_Pointer(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1523      return false;
1524  }
1525
1526  if (LocVT == MVT::i32) {
1527    static const MCPhysReg RegList1[] = {
1528      X86::EDI, X86::ESI, X86::EDX, X86::ECX, X86::R8D, X86::R9D
1529    };
1530    if (unsigned Reg = State.AllocateReg(RegList1)) {
1531      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1532      return false;
1533    }
1534  }
1535
1536  if (LocVT == MVT::i64) {
1537    static const MCPhysReg RegList2[] = {
1538      X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1539    };
1540    if (unsigned Reg = State.AllocateReg(RegList2)) {
1541      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1542      return false;
1543    }
1544  }
1545
1546  if (LocVT == MVT::x86mmx) {
1547    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetDarwin()) {
1548      if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()) {
1549        LocVT = MVT::v2i64;
1550        if (ArgFlags.isSExt())
1551          LocInfo = CCValAssign::SExt;
1552        else if (ArgFlags.isZExt())
1553          LocInfo = CCValAssign::ZExt;
1554        else
1555          LocInfo = CCValAssign::AExt;
1556      }
1557    }
1558  }
1559
1560  if (LocVT == MVT::v2i1) {
1561    LocVT = MVT::v2i64;
1562    if (ArgFlags.isSExt())
1563      LocInfo = CCValAssign::SExt;
1564    else if (ArgFlags.isZExt())
1565      LocInfo = CCValAssign::ZExt;
1566    else
1567      LocInfo = CCValAssign::AExt;
1568  }
1569
1570  if (LocVT == MVT::v4i1) {
1571    LocVT = MVT::v4i32;
1572    if (ArgFlags.isSExt())
1573      LocInfo = CCValAssign::SExt;
1574    else if (ArgFlags.isZExt())
1575      LocInfo = CCValAssign::ZExt;
1576    else
1577      LocInfo = CCValAssign::AExt;
1578  }
1579
1580  if (LocVT == MVT::v8i1) {
1581    LocVT = MVT::v8i16;
1582    if (ArgFlags.isSExt())
1583      LocInfo = CCValAssign::SExt;
1584    else if (ArgFlags.isZExt())
1585      LocInfo = CCValAssign::ZExt;
1586    else
1587      LocInfo = CCValAssign::AExt;
1588  }
1589
1590  if (LocVT == MVT::v16i1) {
1591    LocVT = MVT::v16i8;
1592    if (ArgFlags.isSExt())
1593      LocInfo = CCValAssign::SExt;
1594    else if (ArgFlags.isZExt())
1595      LocInfo = CCValAssign::ZExt;
1596    else
1597      LocInfo = CCValAssign::AExt;
1598  }
1599
1600  if (LocVT == MVT::v32i1) {
1601    LocVT = MVT::v32i8;
1602    if (ArgFlags.isSExt())
1603      LocInfo = CCValAssign::SExt;
1604    else if (ArgFlags.isZExt())
1605      LocInfo = CCValAssign::ZExt;
1606    else
1607      LocInfo = CCValAssign::AExt;
1608  }
1609
1610  if (LocVT == MVT::v64i1) {
1611    LocVT = MVT::v64i8;
1612    if (ArgFlags.isSExt())
1613      LocInfo = CCValAssign::SExt;
1614    else if (ArgFlags.isZExt())
1615      LocInfo = CCValAssign::ZExt;
1616    else
1617      LocInfo = CCValAssign::AExt;
1618  }
1619
1620  if (LocVT == MVT::f16 ||
1621      LocVT == MVT::f32 ||
1622      LocVT == MVT::f64 ||
1623      LocVT == MVT::f128 ||
1624      LocVT == MVT::v16i8 ||
1625      LocVT == MVT::v8i16 ||
1626      LocVT == MVT::v4i32 ||
1627      LocVT == MVT::v2i64 ||
1628      LocVT == MVT::v8f16 ||
1629      LocVT == MVT::v4f32 ||
1630      LocVT == MVT::v2f64) {
1631    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
1632      static const MCPhysReg RegList3[] = {
1633        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1634      };
1635      if (unsigned Reg = State.AllocateReg(RegList3)) {
1636        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1637        return false;
1638      }
1639    }
1640  }
1641
1642  if (!State.isVarArg()) {
1643    if (LocVT == MVT::v32i8 ||
1644        LocVT == MVT::v16i16 ||
1645        LocVT == MVT::v8i32 ||
1646        LocVT == MVT::v4i64 ||
1647        LocVT == MVT::v16f16 ||
1648        LocVT == MVT::v8f32 ||
1649        LocVT == MVT::v4f64) {
1650      if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
1651        static const MCPhysReg RegList4[] = {
1652          X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7
1653        };
1654        if (unsigned Reg = State.AllocateReg(RegList4)) {
1655          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1656          return false;
1657        }
1658      }
1659    }
1660  }
1661
1662  if (!State.isVarArg()) {
1663    if (LocVT == MVT::v64i8 ||
1664        LocVT == MVT::v32i16 ||
1665        LocVT == MVT::v16i32 ||
1666        LocVT == MVT::v8i64 ||
1667        LocVT == MVT::v32f16 ||
1668        LocVT == MVT::v16f32 ||
1669        LocVT == MVT::v8f64) {
1670      if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) {
1671        static const MCPhysReg RegList5[] = {
1672          X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7
1673        };
1674        if (unsigned Reg = State.AllocateReg(RegList5)) {
1675          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1676          return false;
1677        }
1678      }
1679    }
1680  }
1681
1682  if (LocVT == MVT::i32 ||
1683      LocVT == MVT::i64 ||
1684      LocVT == MVT::f16 ||
1685      LocVT == MVT::f32 ||
1686      LocVT == MVT::f64) {
1687    unsigned Offset6 = State.AllocateStack(8, Align(8));
1688    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo));
1689    return false;
1690  }
1691
1692  if (LocVT == MVT::f80 ||
1693      LocVT == MVT::f128) {
1694    unsigned Offset7 = State.AllocateStack(
1695      State.getMachineFunction().getDataLayout().getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())),
1696      State.getMachineFunction().getDataLayout().getABITypeAlign(EVT(LocVT).getTypeForEVT(State.getContext())));
1697    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset7, LocVT, LocInfo));
1698    return false;
1699  }
1700
1701  if (LocVT == MVT::v16i8 ||
1702      LocVT == MVT::v8i16 ||
1703      LocVT == MVT::v4i32 ||
1704      LocVT == MVT::v2i64 ||
1705      LocVT == MVT::v8f16 ||
1706      LocVT == MVT::v4f32 ||
1707      LocVT == MVT::v2f64) {
1708    unsigned Offset8 = State.AllocateStack(16, Align(16));
1709    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset8, LocVT, LocInfo));
1710    return false;
1711  }
1712
1713  if (LocVT == MVT::v32i8 ||
1714      LocVT == MVT::v16i16 ||
1715      LocVT == MVT::v8i32 ||
1716      LocVT == MVT::v4i64 ||
1717      LocVT == MVT::v16f16 ||
1718      LocVT == MVT::v8f32 ||
1719      LocVT == MVT::v4f64) {
1720    unsigned Offset9 = State.AllocateStack(32, Align(32));
1721    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset9, LocVT, LocInfo));
1722    return false;
1723  }
1724
1725  if (LocVT == MVT::v64i8 ||
1726      LocVT == MVT::v32i16 ||
1727      LocVT == MVT::v16i32 ||
1728      LocVT == MVT::v8i64 ||
1729      LocVT == MVT::v32f16 ||
1730      LocVT == MVT::v16f32 ||
1731      LocVT == MVT::v8f64) {
1732    unsigned Offset10 = State.AllocateStack(64, Align(64));
1733    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset10, LocVT, LocInfo));
1734    return false;
1735  }
1736
1737  return true; // CC didn't match.
1738}
1739
1740
1741static bool CC_X86_64_GHC(unsigned ValNo, MVT ValVT,
1742                          MVT LocVT, CCValAssign::LocInfo LocInfo,
1743                          ISD::ArgFlagsTy ArgFlags, CCState &State) {
1744
1745  if (LocVT == MVT::i8 ||
1746      LocVT == MVT::i16 ||
1747      LocVT == MVT::i32) {
1748    LocVT = MVT::i64;
1749    if (ArgFlags.isSExt())
1750      LocInfo = CCValAssign::SExt;
1751    else if (ArgFlags.isZExt())
1752      LocInfo = CCValAssign::ZExt;
1753    else
1754      LocInfo = CCValAssign::AExt;
1755  }
1756
1757  if (LocVT == MVT::i64) {
1758    static const MCPhysReg RegList1[] = {
1759      X86::R13, X86::RBP, X86::R12, X86::RBX, X86::R14, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R15
1760    };
1761    if (unsigned Reg = State.AllocateReg(RegList1)) {
1762      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1763      return false;
1764    }
1765  }
1766
1767  if (LocVT == MVT::f32 ||
1768      LocVT == MVT::f64 ||
1769      LocVT == MVT::v16i8 ||
1770      LocVT == MVT::v8i16 ||
1771      LocVT == MVT::v4i32 ||
1772      LocVT == MVT::v2i64 ||
1773      LocVT == MVT::v4f32 ||
1774      LocVT == MVT::v2f64) {
1775    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
1776      static const MCPhysReg RegList2[] = {
1777        X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6
1778      };
1779      if (unsigned Reg = State.AllocateReg(RegList2)) {
1780        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1781        return false;
1782      }
1783    }
1784  }
1785
1786  if (LocVT == MVT::v32i8 ||
1787      LocVT == MVT::v16i16 ||
1788      LocVT == MVT::v8i32 ||
1789      LocVT == MVT::v4i64 ||
1790      LocVT == MVT::v8f32 ||
1791      LocVT == MVT::v4f64) {
1792    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
1793      static const MCPhysReg RegList3[] = {
1794        X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6
1795      };
1796      if (unsigned Reg = State.AllocateReg(RegList3)) {
1797        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1798        return false;
1799      }
1800    }
1801  }
1802
1803  if (LocVT == MVT::v64i8 ||
1804      LocVT == MVT::v32i16 ||
1805      LocVT == MVT::v16i32 ||
1806      LocVT == MVT::v8i64 ||
1807      LocVT == MVT::v16f32 ||
1808      LocVT == MVT::v8f64) {
1809    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) {
1810      static const MCPhysReg RegList4[] = {
1811        X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6
1812      };
1813      if (unsigned Reg = State.AllocateReg(RegList4)) {
1814        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1815        return false;
1816      }
1817    }
1818  }
1819
1820  return true; // CC didn't match.
1821}
1822
1823
1824static bool CC_X86_64_HHVM(unsigned ValNo, MVT ValVT,
1825                           MVT LocVT, CCValAssign::LocInfo LocInfo,
1826                           ISD::ArgFlagsTy ArgFlags, CCState &State) {
1827
1828  if (LocVT == MVT::i64) {
1829    static const MCPhysReg RegList1[] = {
1830      X86::RBX, X86::R12, X86::RBP, X86::R15, X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9, X86::RAX, X86::R10, X86::R11, X86::R13, X86::R14
1831    };
1832    if (unsigned Reg = State.AllocateReg(RegList1)) {
1833      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1834      return false;
1835    }
1836  }
1837
1838  return true; // CC didn't match.
1839}
1840
1841
1842static bool CC_X86_64_HHVM_C(unsigned ValNo, MVT ValVT,
1843                             MVT LocVT, CCValAssign::LocInfo LocInfo,
1844                             ISD::ArgFlagsTy ArgFlags, CCState &State) {
1845
1846  if (LocVT == MVT::i64) {
1847    if (unsigned Reg = State.AllocateReg(X86::RBP)) {
1848      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1849      return false;
1850    }
1851  }
1852
1853  if (!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1854    return false;
1855
1856  return true; // CC didn't match.
1857}
1858
1859
1860static bool CC_X86_64_HiPE(unsigned ValNo, MVT ValVT,
1861                           MVT LocVT, CCValAssign::LocInfo LocInfo,
1862                           ISD::ArgFlagsTy ArgFlags, CCState &State) {
1863
1864  if (LocVT == MVT::i8 ||
1865      LocVT == MVT::i16 ||
1866      LocVT == MVT::i32) {
1867    LocVT = MVT::i64;
1868    if (ArgFlags.isSExt())
1869      LocInfo = CCValAssign::SExt;
1870    else if (ArgFlags.isZExt())
1871      LocInfo = CCValAssign::ZExt;
1872    else
1873      LocInfo = CCValAssign::AExt;
1874  }
1875
1876  if (LocVT == MVT::i64) {
1877    static const MCPhysReg RegList1[] = {
1878      X86::R15, X86::RBP, X86::RSI, X86::RDX, X86::RCX, X86::R8
1879    };
1880    if (unsigned Reg = State.AllocateReg(RegList1)) {
1881      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1882      return false;
1883    }
1884  }
1885
1886  if (LocVT == MVT::i32 ||
1887      LocVT == MVT::i64 ||
1888      LocVT == MVT::f32 ||
1889      LocVT == MVT::f64) {
1890    unsigned Offset2 = State.AllocateStack(8, Align(8));
1891    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
1892    return false;
1893  }
1894
1895  return true; // CC didn't match.
1896}
1897
1898
1899static bool CC_X86_64_WebKit_JS(unsigned ValNo, MVT ValVT,
1900                                MVT LocVT, CCValAssign::LocInfo LocInfo,
1901                                ISD::ArgFlagsTy ArgFlags, CCState &State) {
1902
1903  if (LocVT == MVT::i8 ||
1904      LocVT == MVT::i16) {
1905    LocVT = MVT::i32;
1906    if (ArgFlags.isSExt())
1907      LocInfo = CCValAssign::SExt;
1908    else if (ArgFlags.isZExt())
1909      LocInfo = CCValAssign::ZExt;
1910    else
1911      LocInfo = CCValAssign::AExt;
1912  }
1913
1914  if (LocVT == MVT::i32) {
1915    if (unsigned Reg = State.AllocateReg(X86::EAX)) {
1916      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1917      return false;
1918    }
1919  }
1920
1921  if (LocVT == MVT::i64) {
1922    if (unsigned Reg = State.AllocateReg(X86::RAX)) {
1923      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1924      return false;
1925    }
1926  }
1927
1928  if (LocVT == MVT::i32 ||
1929      LocVT == MVT::f32) {
1930    unsigned Offset1 = State.AllocateStack(4, Align(4));
1931    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo));
1932    return false;
1933  }
1934
1935  if (LocVT == MVT::i64 ||
1936      LocVT == MVT::f64) {
1937    unsigned Offset2 = State.AllocateStack(8, Align(8));
1938    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
1939    return false;
1940  }
1941
1942  return true; // CC didn't match.
1943}
1944
1945
1946static bool CC_X86_SysV64_RegCall(unsigned ValNo, MVT ValVT,
1947                                  MVT LocVT, CCValAssign::LocInfo LocInfo,
1948                                  ISD::ArgFlagsTy ArgFlags, CCState &State) {
1949
1950  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
1951    if (ArgFlags.isByVal()) {
1952      State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, Align(8), ArgFlags);
1953      return false;
1954    }
1955  }
1956
1957  if (ArgFlags.isByVal()) {
1958    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, Align(4), ArgFlags);
1959    return false;
1960  }
1961
1962  if (LocVT == MVT::i1 ||
1963      LocVT == MVT::i8 ||
1964      LocVT == MVT::i16 ||
1965      LocVT == MVT::v1i1) {
1966    LocVT = MVT::i32;
1967    if (ArgFlags.isSExt())
1968      LocInfo = CCValAssign::SExt;
1969    else if (ArgFlags.isZExt())
1970      LocInfo = CCValAssign::ZExt;
1971    else
1972      LocInfo = CCValAssign::AExt;
1973  }
1974
1975  if (LocVT == MVT::v8i1 ||
1976      LocVT == MVT::v16i1 ||
1977      LocVT == MVT::v32i1) {
1978    LocVT = MVT::i32;
1979    if (ArgFlags.isSExt())
1980      LocInfo = CCValAssign::SExt;
1981    else if (ArgFlags.isZExt())
1982      LocInfo = CCValAssign::ZExt;
1983    else
1984      LocInfo = CCValAssign::AExt;
1985  }
1986
1987  if (LocVT == MVT::i32) {
1988    static const MCPhysReg RegList1[] = {
1989      X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R12D, X86::R13D, X86::R14D, X86::R15D
1990    };
1991    if (unsigned Reg = State.AllocateReg(RegList1)) {
1992      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1993      return false;
1994    }
1995  }
1996
1997  if (LocVT == MVT::i64) {
1998    static const MCPhysReg RegList2[] = {
1999      X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R12, X86::R13, X86::R14, X86::R15
2000    };
2001    if (unsigned Reg = State.AllocateReg(RegList2)) {
2002      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2003      return false;
2004    }
2005  }
2006
2007  if (LocVT == MVT::v64i1) {
2008    LocVT = MVT::i64;
2009    if (ArgFlags.isSExt())
2010      LocInfo = CCValAssign::SExt;
2011    else if (ArgFlags.isZExt())
2012      LocInfo = CCValAssign::ZExt;
2013    else
2014      LocInfo = CCValAssign::AExt;
2015  }
2016
2017  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
2018    if (LocVT == MVT::i64) {
2019      static const MCPhysReg RegList3[] = {
2020        X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R12, X86::R13, X86::R14, X86::R15
2021      };
2022      if (unsigned Reg = State.AllocateReg(RegList3)) {
2023        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2024        return false;
2025      }
2026    }
2027  }
2028
2029  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()) {
2030    if (LocVT == MVT::i64) {
2031      if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2032        return false;
2033    }
2034  }
2035
2036  if (LocVT == MVT::f32 ||
2037      LocVT == MVT::f64 ||
2038      LocVT == MVT::f128) {
2039    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
2040      static const MCPhysReg RegList4[] = {
2041        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
2042      };
2043      if (unsigned Reg = State.AllocateReg(RegList4)) {
2044        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2045        return false;
2046      }
2047    }
2048  }
2049
2050  if (LocVT == MVT::f80) {
2051    if (unsigned Reg = State.AllocateReg(X86::FP0)) {
2052      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2053      return false;
2054    }
2055  }
2056
2057  if (LocVT == MVT::v16i8 ||
2058      LocVT == MVT::v8i16 ||
2059      LocVT == MVT::v4i32 ||
2060      LocVT == MVT::v2i64 ||
2061      LocVT == MVT::v4f32 ||
2062      LocVT == MVT::v2f64) {
2063    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
2064      static const MCPhysReg RegList5[] = {
2065        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
2066      };
2067      if (unsigned Reg = State.AllocateReg(RegList5)) {
2068        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2069        return false;
2070      }
2071    }
2072  }
2073
2074  if (LocVT == MVT::v32i8 ||
2075      LocVT == MVT::v16i16 ||
2076      LocVT == MVT::v8i32 ||
2077      LocVT == MVT::v4i64 ||
2078      LocVT == MVT::v8f32 ||
2079      LocVT == MVT::v4f64) {
2080    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
2081      static const MCPhysReg RegList6[] = {
2082        X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15
2083      };
2084      if (unsigned Reg = State.AllocateReg(RegList6)) {
2085        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2086        return false;
2087      }
2088    }
2089  }
2090
2091  if (LocVT == MVT::v64i8 ||
2092      LocVT == MVT::v32i16 ||
2093      LocVT == MVT::v16i32 ||
2094      LocVT == MVT::v8i64 ||
2095      LocVT == MVT::v16f32 ||
2096      LocVT == MVT::v8f64) {
2097    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) {
2098      static const MCPhysReg RegList7[] = {
2099        X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15
2100      };
2101      if (unsigned Reg = State.AllocateReg(RegList7)) {
2102        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2103        return false;
2104      }
2105    }
2106  }
2107
2108  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
2109    if (LocVT == MVT::i32 ||
2110        LocVT == MVT::i64 ||
2111        LocVT == MVT::f32 ||
2112        LocVT == MVT::f64) {
2113      unsigned Offset8 = State.AllocateStack(8, Align(8));
2114      State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset8, LocVT, LocInfo));
2115      return false;
2116    }
2117  }
2118
2119  if (LocVT == MVT::i32 ||
2120      LocVT == MVT::f32) {
2121    unsigned Offset9 = State.AllocateStack(4, Align(4));
2122    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset9, LocVT, LocInfo));
2123    return false;
2124  }
2125
2126  if (LocVT == MVT::i64 ||
2127      LocVT == MVT::f64) {
2128    unsigned Offset10 = State.AllocateStack(8, Align(4));
2129    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset10, LocVT, LocInfo));
2130    return false;
2131  }
2132
2133  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
2134    if (LocVT == MVT::x86mmx) {
2135      unsigned Offset11 = State.AllocateStack(8, Align(8));
2136      State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset11, LocVT, LocInfo));
2137      return false;
2138    }
2139  }
2140
2141  if (LocVT == MVT::x86mmx) {
2142    unsigned Offset12 = State.AllocateStack(8, Align(4));
2143    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset12, LocVT, LocInfo));
2144    return false;
2145  }
2146
2147  if (LocVT == MVT::f80 ||
2148      LocVT == MVT::f128) {
2149    unsigned Offset13 = State.AllocateStack(
2150      State.getMachineFunction().getDataLayout().getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())),
2151      State.getMachineFunction().getDataLayout().getABITypeAlign(EVT(LocVT).getTypeForEVT(State.getContext())));
2152    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset13, LocVT, LocInfo));
2153    return false;
2154  }
2155
2156  if (LocVT == MVT::v16i8 ||
2157      LocVT == MVT::v8i16 ||
2158      LocVT == MVT::v4i32 ||
2159      LocVT == MVT::v2i64 ||
2160      LocVT == MVT::v4f32 ||
2161      LocVT == MVT::v2f64) {
2162    unsigned Offset14 = State.AllocateStack(16, Align(16));
2163    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset14, LocVT, LocInfo));
2164    return false;
2165  }
2166
2167  if (LocVT == MVT::v32i8 ||
2168      LocVT == MVT::v16i16 ||
2169      LocVT == MVT::v8i32 ||
2170      LocVT == MVT::v4i64 ||
2171      LocVT == MVT::v8f32 ||
2172      LocVT == MVT::v4f64) {
2173    unsigned Offset15 = State.AllocateStack(32, Align(32));
2174    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset15, LocVT, LocInfo));
2175    return false;
2176  }
2177
2178  if (LocVT == MVT::v64i8 ||
2179      LocVT == MVT::v32i16 ||
2180      LocVT == MVT::v16i32 ||
2181      LocVT == MVT::v8i64 ||
2182      LocVT == MVT::v16f32 ||
2183      LocVT == MVT::v8f64) {
2184    unsigned Offset16 = State.AllocateStack(64, Align(64));
2185    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset16, LocVT, LocInfo));
2186    return false;
2187  }
2188
2189  return true; // CC didn't match.
2190}
2191
2192
2193static bool CC_X86_Win32_CFGuard_Check(unsigned ValNo, MVT ValVT,
2194                                       MVT LocVT, CCValAssign::LocInfo LocInfo,
2195                                       ISD::ArgFlagsTy ArgFlags, CCState &State) {
2196
2197  if (LocVT == MVT::i32) {
2198    if (unsigned Reg = State.AllocateReg(X86::ECX)) {
2199      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2200      return false;
2201    }
2202  }
2203
2204  return true; // CC didn't match.
2205}
2206
2207
2208static bool CC_X86_Win32_Vector(unsigned ValNo, MVT ValVT,
2209                                MVT LocVT, CCValAssign::LocInfo LocInfo,
2210                                ISD::ArgFlagsTy ArgFlags, CCState &State) {
2211
2212  if (LocVT == MVT::v16i8 ||
2213      LocVT == MVT::v8i16 ||
2214      LocVT == MVT::v4i32 ||
2215      LocVT == MVT::v2i64 ||
2216      LocVT == MVT::v8f16 ||
2217      LocVT == MVT::v4f32 ||
2218      LocVT == MVT::v2f64) {
2219    unsigned Offset1 = State.AllocateStack(16, Align(4));
2220    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo));
2221    return false;
2222  }
2223
2224  if (LocVT == MVT::v32i8 ||
2225      LocVT == MVT::v16i16 ||
2226      LocVT == MVT::v8i32 ||
2227      LocVT == MVT::v4i64 ||
2228      LocVT == MVT::v16f16 ||
2229      LocVT == MVT::v8f32 ||
2230      LocVT == MVT::v4f64) {
2231    unsigned Offset2 = State.AllocateStack(32, Align(4));
2232    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
2233    return false;
2234  }
2235
2236  if (LocVT == MVT::v64i8 ||
2237      LocVT == MVT::v32i16 ||
2238      LocVT == MVT::v16i32 ||
2239      LocVT == MVT::v8i64 ||
2240      LocVT == MVT::v32f16 ||
2241      LocVT == MVT::v16f32 ||
2242      LocVT == MVT::v8f64) {
2243    unsigned Offset3 = State.AllocateStack(64, Align(4));
2244    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo));
2245    return false;
2246  }
2247
2248  return true; // CC didn't match.
2249}
2250
2251
2252static bool CC_X86_Win32_VectorCall(unsigned ValNo, MVT ValVT,
2253                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
2254                                    ISD::ArgFlagsTy ArgFlags, CCState &State) {
2255
2256  if (CC_X86_32_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2257    return false;
2258
2259  if (!CC_X86_32_FastCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2260    return false;
2261
2262  return true; // CC didn't match.
2263}
2264
2265
2266static bool CC_X86_Win64_C(unsigned ValNo, MVT ValVT,
2267                           MVT LocVT, CCValAssign::LocInfo LocInfo,
2268                           ISD::ArgFlagsTy ArgFlags, CCState &State) {
2269
2270  if (ArgFlags.isByVal()) {
2271    LocVT = MVT::i64;
2272    LocInfo = CCValAssign::Indirect;
2273  }
2274
2275  if (LocVT == MVT::i1 ||
2276      LocVT == MVT::v1i1) {
2277    LocVT = MVT::i8;
2278    if (ArgFlags.isSExt())
2279      LocInfo = CCValAssign::SExt;
2280    else if (ArgFlags.isZExt())
2281      LocInfo = CCValAssign::ZExt;
2282    else
2283      LocInfo = CCValAssign::AExt;
2284  }
2285
2286  if (ArgFlags.isNest()) {
2287    if (unsigned Reg = State.AllocateReg(X86::R10)) {
2288      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2289      return false;
2290    }
2291  }
2292
2293  if (ArgFlags.isSwiftError()) {
2294    if (LocVT == MVT::i64) {
2295      if (unsigned Reg = State.AllocateReg(X86::R12)) {
2296        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2297        return false;
2298      }
2299    }
2300  }
2301
2302  if (ArgFlags.isSwiftSelf()) {
2303    if (LocVT == MVT::i64) {
2304      if (unsigned Reg = State.AllocateReg(X86::R13)) {
2305        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2306        return false;
2307      }
2308    }
2309  }
2310
2311  if (ArgFlags.isSwiftAsync()) {
2312    if (LocVT == MVT::i64) {
2313      if (unsigned Reg = State.AllocateReg(X86::R14)) {
2314        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2315        return false;
2316      }
2317    }
2318  }
2319
2320  if (ArgFlags.isCFGuardTarget()) {
2321    if (unsigned Reg = State.AllocateReg(X86::RAX)) {
2322      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2323      return false;
2324    }
2325  }
2326
2327  if (LocVT == MVT::v16i8 ||
2328      LocVT == MVT::v8i16 ||
2329      LocVT == MVT::v4i32 ||
2330      LocVT == MVT::v2i64 ||
2331      LocVT == MVT::v8f16 ||
2332      LocVT == MVT::v4f32 ||
2333      LocVT == MVT::v2f64) {
2334    LocVT = MVT::i64;
2335    LocInfo = CCValAssign::Indirect;
2336  }
2337
2338  if (LocVT == MVT::v32i8 ||
2339      LocVT == MVT::v16i16 ||
2340      LocVT == MVT::v8i32 ||
2341      LocVT == MVT::v4i64 ||
2342      LocVT == MVT::v16f16 ||
2343      LocVT == MVT::v8f32 ||
2344      LocVT == MVT::v4f64) {
2345    LocVT = MVT::i64;
2346    LocInfo = CCValAssign::Indirect;
2347  }
2348
2349  if (LocVT == MVT::v64i8 ||
2350      LocVT == MVT::v32i16 ||
2351      LocVT == MVT::v16i32 ||
2352      LocVT == MVT::v32f16 ||
2353      LocVT == MVT::v16f32 ||
2354      LocVT == MVT::v8f64 ||
2355      LocVT == MVT::v8i64) {
2356    LocVT = MVT::i64;
2357    LocInfo = CCValAssign::Indirect;
2358  }
2359
2360  if (LocVT == MVT::f80) {
2361    LocVT = MVT::i64;
2362    LocInfo = CCValAssign::Indirect;
2363  }
2364
2365  if (LocVT == MVT::x86mmx) {
2366    LocVT = MVT::i64;
2367    LocInfo = CCValAssign::BCvt;
2368  }
2369
2370  if (LocVT == MVT::f32) {
2371    if (!static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
2372      LocVT = MVT::i32;
2373      LocInfo = CCValAssign::BCvt;
2374    }
2375  }
2376
2377  if (LocVT == MVT::f64) {
2378    if (!static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
2379      LocVT = MVT::i64;
2380      LocInfo = CCValAssign::BCvt;
2381    }
2382  }
2383
2384  if (LocVT == MVT::f16 ||
2385      LocVT == MVT::f32 ||
2386      LocVT == MVT::f64) {
2387    static const MCPhysReg RegList1[] = {
2388      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
2389    };
2390    static const MCPhysReg RegList2[] = {
2391      X86::RCX, X86::RDX, X86::R8, X86::R9
2392    };
2393    if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
2394      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2395      return false;
2396    }
2397  }
2398
2399  if (LocVT == MVT::i8) {
2400    static const MCPhysReg RegList3[] = {
2401      X86::CL, X86::DL, X86::R8B, X86::R9B
2402    };
2403    static const MCPhysReg RegList4[] = {
2404      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
2405    };
2406    if (unsigned Reg = State.AllocateReg(RegList3, RegList4)) {
2407      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2408      return false;
2409    }
2410  }
2411
2412  if (LocVT == MVT::i16) {
2413    static const MCPhysReg RegList5[] = {
2414      X86::CX, X86::DX, X86::R8W, X86::R9W
2415    };
2416    static const MCPhysReg RegList6[] = {
2417      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
2418    };
2419    if (unsigned Reg = State.AllocateReg(RegList5, RegList6)) {
2420      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2421      return false;
2422    }
2423  }
2424
2425  if (LocVT == MVT::i32) {
2426    static const MCPhysReg RegList7[] = {
2427      X86::ECX, X86::EDX, X86::R8D, X86::R9D
2428    };
2429    static const MCPhysReg RegList8[] = {
2430      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
2431    };
2432    if (unsigned Reg = State.AllocateReg(RegList7, RegList8)) {
2433      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2434      return false;
2435    }
2436  }
2437
2438  if (State.getCallingConv() == CallingConv::X86_ThisCall) {
2439    if (ArgFlags.isSRet()) {
2440      if (LocVT == MVT::i64) {
2441        static const MCPhysReg RegList9[] = {
2442          X86::RDX, X86::R8, X86::R9
2443        };
2444        static const MCPhysReg RegList10[] = {
2445          X86::XMM1, X86::XMM2, X86::XMM3
2446        };
2447        if (unsigned Reg = State.AllocateReg(RegList9, RegList10)) {
2448          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2449          return false;
2450        }
2451      }
2452    }
2453  }
2454
2455  if (LocVT == MVT::i64) {
2456    static const MCPhysReg RegList11[] = {
2457      X86::RCX, X86::RDX, X86::R8, X86::R9
2458    };
2459    static const MCPhysReg RegList12[] = {
2460      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
2461    };
2462    if (unsigned Reg = State.AllocateReg(RegList11, RegList12)) {
2463      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2464      return false;
2465    }
2466  }
2467
2468  if (LocVT == MVT::i8 ||
2469      LocVT == MVT::i16 ||
2470      LocVT == MVT::i32 ||
2471      LocVT == MVT::i64 ||
2472      LocVT == MVT::f16 ||
2473      LocVT == MVT::f32 ||
2474      LocVT == MVT::f64) {
2475    unsigned Offset13 = State.AllocateStack(8, Align(8));
2476    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset13, LocVT, LocInfo));
2477    return false;
2478  }
2479
2480  return true; // CC didn't match.
2481}
2482
2483
2484static bool CC_X86_Win64_RegCall(unsigned ValNo, MVT ValVT,
2485                                 MVT LocVT, CCValAssign::LocInfo LocInfo,
2486                                 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2487
2488  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
2489    if (ArgFlags.isByVal()) {
2490      State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, Align(8), ArgFlags);
2491      return false;
2492    }
2493  }
2494
2495  if (ArgFlags.isByVal()) {
2496    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, Align(4), ArgFlags);
2497    return false;
2498  }
2499
2500  if (LocVT == MVT::i1 ||
2501      LocVT == MVT::i8 ||
2502      LocVT == MVT::i16 ||
2503      LocVT == MVT::v1i1) {
2504    LocVT = MVT::i32;
2505    if (ArgFlags.isSExt())
2506      LocInfo = CCValAssign::SExt;
2507    else if (ArgFlags.isZExt())
2508      LocInfo = CCValAssign::ZExt;
2509    else
2510      LocInfo = CCValAssign::AExt;
2511  }
2512
2513  if (LocVT == MVT::v8i1 ||
2514      LocVT == MVT::v16i1 ||
2515      LocVT == MVT::v32i1) {
2516    LocVT = MVT::i32;
2517    if (ArgFlags.isSExt())
2518      LocInfo = CCValAssign::SExt;
2519    else if (ArgFlags.isZExt())
2520      LocInfo = CCValAssign::ZExt;
2521    else
2522      LocInfo = CCValAssign::AExt;
2523  }
2524
2525  if (LocVT == MVT::i32) {
2526    static const MCPhysReg RegList1[] = {
2527      X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R12D, X86::R14D, X86::R15D
2528    };
2529    if (unsigned Reg = State.AllocateReg(RegList1)) {
2530      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2531      return false;
2532    }
2533  }
2534
2535  if (LocVT == MVT::i64) {
2536    static const MCPhysReg RegList2[] = {
2537      X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R14, X86::R15
2538    };
2539    if (unsigned Reg = State.AllocateReg(RegList2)) {
2540      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2541      return false;
2542    }
2543  }
2544
2545  if (LocVT == MVT::v64i1) {
2546    LocVT = MVT::i64;
2547    if (ArgFlags.isSExt())
2548      LocInfo = CCValAssign::SExt;
2549    else if (ArgFlags.isZExt())
2550      LocInfo = CCValAssign::ZExt;
2551    else
2552      LocInfo = CCValAssign::AExt;
2553  }
2554
2555  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
2556    if (LocVT == MVT::i64) {
2557      static const MCPhysReg RegList3[] = {
2558        X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R14, X86::R15
2559      };
2560      if (unsigned Reg = State.AllocateReg(RegList3)) {
2561        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2562        return false;
2563      }
2564    }
2565  }
2566
2567  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()) {
2568    if (LocVT == MVT::i64) {
2569      if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2570        return false;
2571    }
2572  }
2573
2574  if (LocVT == MVT::f32 ||
2575      LocVT == MVT::f64 ||
2576      LocVT == MVT::f128) {
2577    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
2578      static const MCPhysReg RegList4[] = {
2579        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
2580      };
2581      if (unsigned Reg = State.AllocateReg(RegList4)) {
2582        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2583        return false;
2584      }
2585    }
2586  }
2587
2588  if (LocVT == MVT::f80) {
2589    if (unsigned Reg = State.AllocateReg(X86::FP0)) {
2590      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2591      return false;
2592    }
2593  }
2594
2595  if (LocVT == MVT::v16i8 ||
2596      LocVT == MVT::v8i16 ||
2597      LocVT == MVT::v4i32 ||
2598      LocVT == MVT::v2i64 ||
2599      LocVT == MVT::v4f32 ||
2600      LocVT == MVT::v2f64) {
2601    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
2602      static const MCPhysReg RegList5[] = {
2603        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
2604      };
2605      if (unsigned Reg = State.AllocateReg(RegList5)) {
2606        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2607        return false;
2608      }
2609    }
2610  }
2611
2612  if (LocVT == MVT::v32i8 ||
2613      LocVT == MVT::v16i16 ||
2614      LocVT == MVT::v8i32 ||
2615      LocVT == MVT::v4i64 ||
2616      LocVT == MVT::v8f32 ||
2617      LocVT == MVT::v4f64) {
2618    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
2619      static const MCPhysReg RegList6[] = {
2620        X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15
2621      };
2622      if (unsigned Reg = State.AllocateReg(RegList6)) {
2623        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2624        return false;
2625      }
2626    }
2627  }
2628
2629  if (LocVT == MVT::v64i8 ||
2630      LocVT == MVT::v32i16 ||
2631      LocVT == MVT::v16i32 ||
2632      LocVT == MVT::v8i64 ||
2633      LocVT == MVT::v16f32 ||
2634      LocVT == MVT::v8f64) {
2635    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) {
2636      static const MCPhysReg RegList7[] = {
2637        X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15
2638      };
2639      if (unsigned Reg = State.AllocateReg(RegList7)) {
2640        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2641        return false;
2642      }
2643    }
2644  }
2645
2646  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
2647    if (LocVT == MVT::i32 ||
2648        LocVT == MVT::i64 ||
2649        LocVT == MVT::f32 ||
2650        LocVT == MVT::f64) {
2651      unsigned Offset8 = State.AllocateStack(8, Align(8));
2652      State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset8, LocVT, LocInfo));
2653      return false;
2654    }
2655  }
2656
2657  if (LocVT == MVT::i32 ||
2658      LocVT == MVT::f32) {
2659    unsigned Offset9 = State.AllocateStack(4, Align(4));
2660    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset9, LocVT, LocInfo));
2661    return false;
2662  }
2663
2664  if (LocVT == MVT::i64 ||
2665      LocVT == MVT::f64) {
2666    unsigned Offset10 = State.AllocateStack(8, Align(4));
2667    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset10, LocVT, LocInfo));
2668    return false;
2669  }
2670
2671  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
2672    if (LocVT == MVT::x86mmx) {
2673      unsigned Offset11 = State.AllocateStack(8, Align(8));
2674      State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset11, LocVT, LocInfo));
2675      return false;
2676    }
2677  }
2678
2679  if (LocVT == MVT::x86mmx) {
2680    unsigned Offset12 = State.AllocateStack(8, Align(4));
2681    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset12, LocVT, LocInfo));
2682    return false;
2683  }
2684
2685  if (LocVT == MVT::f80 ||
2686      LocVT == MVT::f128) {
2687    unsigned Offset13 = State.AllocateStack(
2688      State.getMachineFunction().getDataLayout().getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())),
2689      State.getMachineFunction().getDataLayout().getABITypeAlign(EVT(LocVT).getTypeForEVT(State.getContext())));
2690    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset13, LocVT, LocInfo));
2691    return false;
2692  }
2693
2694  if (LocVT == MVT::v16i8 ||
2695      LocVT == MVT::v8i16 ||
2696      LocVT == MVT::v4i32 ||
2697      LocVT == MVT::v2i64 ||
2698      LocVT == MVT::v4f32 ||
2699      LocVT == MVT::v2f64) {
2700    unsigned Offset14 = State.AllocateStack(16, Align(16));
2701    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset14, LocVT, LocInfo));
2702    return false;
2703  }
2704
2705  if (LocVT == MVT::v32i8 ||
2706      LocVT == MVT::v16i16 ||
2707      LocVT == MVT::v8i32 ||
2708      LocVT == MVT::v4i64 ||
2709      LocVT == MVT::v8f32 ||
2710      LocVT == MVT::v4f64) {
2711    unsigned Offset15 = State.AllocateStack(32, Align(32));
2712    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset15, LocVT, LocInfo));
2713    return false;
2714  }
2715
2716  if (LocVT == MVT::v64i8 ||
2717      LocVT == MVT::v32i16 ||
2718      LocVT == MVT::v16i32 ||
2719      LocVT == MVT::v8i64 ||
2720      LocVT == MVT::v16f32 ||
2721      LocVT == MVT::v8f64) {
2722    unsigned Offset16 = State.AllocateStack(64, Align(64));
2723    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset16, LocVT, LocInfo));
2724    return false;
2725  }
2726
2727  return true; // CC didn't match.
2728}
2729
2730
2731static bool CC_X86_Win64_VectorCall(unsigned ValNo, MVT ValVT,
2732                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
2733                                    ISD::ArgFlagsTy ArgFlags, CCState &State) {
2734
2735  if (CC_X86_64_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2736    return false;
2737
2738  if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2739    return false;
2740
2741  return true; // CC didn't match.
2742}
2743
2744
2745static bool RetCC_Intel_OCL_BI(unsigned ValNo, MVT ValVT,
2746                               MVT LocVT, CCValAssign::LocInfo LocInfo,
2747                               ISD::ArgFlagsTy ArgFlags, CCState &State) {
2748
2749  if (LocVT == MVT::f32 ||
2750      LocVT == MVT::f64 ||
2751      LocVT == MVT::v4i32 ||
2752      LocVT == MVT::v2i64 ||
2753      LocVT == MVT::v4f32 ||
2754      LocVT == MVT::v2f64) {
2755    static const MCPhysReg RegList1[] = {
2756      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
2757    };
2758    if (unsigned Reg = State.AllocateReg(RegList1)) {
2759      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2760      return false;
2761    }
2762  }
2763
2764  if (LocVT == MVT::v8f32 ||
2765      LocVT == MVT::v4f64 ||
2766      LocVT == MVT::v8i32 ||
2767      LocVT == MVT::v4i64) {
2768    static const MCPhysReg RegList2[] = {
2769      X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3
2770    };
2771    if (unsigned Reg = State.AllocateReg(RegList2)) {
2772      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2773      return false;
2774    }
2775  }
2776
2777  if (LocVT == MVT::v16f32 ||
2778      LocVT == MVT::v8f64 ||
2779      LocVT == MVT::v16i32 ||
2780      LocVT == MVT::v8i64) {
2781    static const MCPhysReg RegList3[] = {
2782      X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3
2783    };
2784    if (unsigned Reg = State.AllocateReg(RegList3)) {
2785      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2786      return false;
2787    }
2788  }
2789
2790  if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2791    return false;
2792
2793  return true; // CC didn't match.
2794}
2795
2796
2797bool llvm::RetCC_X86(unsigned ValNo, MVT ValVT,
2798                     MVT LocVT, CCValAssign::LocInfo LocInfo,
2799                     ISD::ArgFlagsTy ArgFlags, CCState &State) {
2800
2801  if (State.getCallingConv() == CallingConv::Intel_OCL_BI) {
2802    if (!RetCC_Intel_OCL_BI(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2803      return false;
2804  }
2805
2806  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
2807    if (!RetCC_X86_64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2808      return false;
2809  }
2810
2811  if (!RetCC_X86_32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2812    return false;
2813
2814  return true; // CC didn't match.
2815}
2816
2817
2818static bool RetCC_X86Common(unsigned ValNo, MVT ValVT,
2819                            MVT LocVT, CCValAssign::LocInfo LocInfo,
2820                            ISD::ArgFlagsTy ArgFlags, CCState &State) {
2821
2822  if (LocVT == MVT::v1i1) {
2823    LocVT = MVT::i8;
2824    if (ArgFlags.isSExt())
2825      LocInfo = CCValAssign::SExt;
2826    else if (ArgFlags.isZExt())
2827      LocInfo = CCValAssign::ZExt;
2828    else
2829      LocInfo = CCValAssign::AExt;
2830  }
2831
2832  if (LocVT == MVT::i1) {
2833    LocVT = MVT::i8;
2834    if (ArgFlags.isSExt())
2835      LocInfo = CCValAssign::SExt;
2836    else if (ArgFlags.isZExt())
2837      LocInfo = CCValAssign::ZExt;
2838    else
2839      LocInfo = CCValAssign::AExt;
2840  }
2841
2842  if (LocVT == MVT::i8) {
2843    static const MCPhysReg RegList1[] = {
2844      X86::AL, X86::DL, X86::CL
2845    };
2846    if (unsigned Reg = State.AllocateReg(RegList1)) {
2847      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2848      return false;
2849    }
2850  }
2851
2852  if (LocVT == MVT::i16) {
2853    static const MCPhysReg RegList2[] = {
2854      X86::AX, X86::DX, X86::CX
2855    };
2856    if (unsigned Reg = State.AllocateReg(RegList2)) {
2857      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2858      return false;
2859    }
2860  }
2861
2862  if (LocVT == MVT::i32) {
2863    static const MCPhysReg RegList3[] = {
2864      X86::EAX, X86::EDX, X86::ECX
2865    };
2866    if (unsigned Reg = State.AllocateReg(RegList3)) {
2867      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2868      return false;
2869    }
2870  }
2871
2872  if (LocVT == MVT::i64) {
2873    static const MCPhysReg RegList4[] = {
2874      X86::RAX, X86::RDX, X86::RCX
2875    };
2876    if (unsigned Reg = State.AllocateReg(RegList4)) {
2877      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2878      return false;
2879    }
2880  }
2881
2882  if (LocVT == MVT::v2i1) {
2883    LocVT = MVT::v2i64;
2884    if (ArgFlags.isSExt())
2885      LocInfo = CCValAssign::SExt;
2886    else if (ArgFlags.isZExt())
2887      LocInfo = CCValAssign::ZExt;
2888    else
2889      LocInfo = CCValAssign::AExt;
2890  }
2891
2892  if (LocVT == MVT::v4i1) {
2893    LocVT = MVT::v4i32;
2894    if (ArgFlags.isSExt())
2895      LocInfo = CCValAssign::SExt;
2896    else if (ArgFlags.isZExt())
2897      LocInfo = CCValAssign::ZExt;
2898    else
2899      LocInfo = CCValAssign::AExt;
2900  }
2901
2902  if (LocVT == MVT::v8i1) {
2903    LocVT = MVT::v8i16;
2904    if (ArgFlags.isSExt())
2905      LocInfo = CCValAssign::SExt;
2906    else if (ArgFlags.isZExt())
2907      LocInfo = CCValAssign::ZExt;
2908    else
2909      LocInfo = CCValAssign::AExt;
2910  }
2911
2912  if (LocVT == MVT::v16i1) {
2913    LocVT = MVT::v16i8;
2914    if (ArgFlags.isSExt())
2915      LocInfo = CCValAssign::SExt;
2916    else if (ArgFlags.isZExt())
2917      LocInfo = CCValAssign::ZExt;
2918    else
2919      LocInfo = CCValAssign::AExt;
2920  }
2921
2922  if (LocVT == MVT::v32i1) {
2923    LocVT = MVT::v32i8;
2924    if (ArgFlags.isSExt())
2925      LocInfo = CCValAssign::SExt;
2926    else if (ArgFlags.isZExt())
2927      LocInfo = CCValAssign::ZExt;
2928    else
2929      LocInfo = CCValAssign::AExt;
2930  }
2931
2932  if (LocVT == MVT::v64i1) {
2933    LocVT = MVT::v64i8;
2934    if (ArgFlags.isSExt())
2935      LocInfo = CCValAssign::SExt;
2936    else if (ArgFlags.isZExt())
2937      LocInfo = CCValAssign::ZExt;
2938    else
2939      LocInfo = CCValAssign::AExt;
2940  }
2941
2942  if (LocVT == MVT::v16i8 ||
2943      LocVT == MVT::v8i16 ||
2944      LocVT == MVT::v4i32 ||
2945      LocVT == MVT::v2i64 ||
2946      LocVT == MVT::v8f16 ||
2947      LocVT == MVT::v4f32 ||
2948      LocVT == MVT::v2f64) {
2949    static const MCPhysReg RegList5[] = {
2950      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
2951    };
2952    if (unsigned Reg = State.AllocateReg(RegList5)) {
2953      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2954      return false;
2955    }
2956  }
2957
2958  if (LocVT == MVT::v32i8 ||
2959      LocVT == MVT::v16i16 ||
2960      LocVT == MVT::v8i32 ||
2961      LocVT == MVT::v4i64 ||
2962      LocVT == MVT::v16f16 ||
2963      LocVT == MVT::v8f32 ||
2964      LocVT == MVT::v4f64) {
2965    static const MCPhysReg RegList6[] = {
2966      X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3
2967    };
2968    if (unsigned Reg = State.AllocateReg(RegList6)) {
2969      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2970      return false;
2971    }
2972  }
2973
2974  if (LocVT == MVT::v64i8 ||
2975      LocVT == MVT::v32i16 ||
2976      LocVT == MVT::v16i32 ||
2977      LocVT == MVT::v8i64 ||
2978      LocVT == MVT::v32f16 ||
2979      LocVT == MVT::v16f32 ||
2980      LocVT == MVT::v8f64) {
2981    static const MCPhysReg RegList7[] = {
2982      X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3
2983    };
2984    if (unsigned Reg = State.AllocateReg(RegList7)) {
2985      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2986      return false;
2987    }
2988  }
2989
2990  if (LocVT == MVT::x86mmx) {
2991    if (unsigned Reg = State.AllocateReg(X86::MM0)) {
2992      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2993      return false;
2994    }
2995  }
2996
2997  if (!static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) {
2998    if (LocVT == MVT::f80) {
2999      static const MCPhysReg RegList8[] = {
3000        X86::FP0, X86::FP1
3001      };
3002      if (unsigned Reg = State.AllocateReg(RegList8)) {
3003        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3004        return false;
3005      }
3006    }
3007  }
3008
3009  return true; // CC didn't match.
3010}
3011
3012
3013static bool RetCC_X86_32(unsigned ValNo, MVT ValVT,
3014                         MVT LocVT, CCValAssign::LocInfo LocInfo,
3015                         ISD::ArgFlagsTy ArgFlags, CCState &State) {
3016
3017  if (State.getCallingConv() == CallingConv::Fast) {
3018    if (!RetCC_X86_32_Fast(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3019      return false;
3020  }
3021
3022  if (State.getCallingConv() == CallingConv::Tail) {
3023    if (!RetCC_X86_32_Fast(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3024      return false;
3025  }
3026
3027  if (State.getCallingConv() == CallingConv::HiPE) {
3028    if (!RetCC_X86_32_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3029      return false;
3030  }
3031
3032  if (State.getCallingConv() == CallingConv::X86_VectorCall) {
3033    if (!RetCC_X86_32_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3034      return false;
3035  }
3036
3037  if (State.getCallingConv() == CallingConv::X86_RegCall) {
3038    if (!RetCC_X86_32_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3039      return false;
3040  }
3041
3042  if (!RetCC_X86_32_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3043    return false;
3044
3045  return true; // CC didn't match.
3046}
3047
3048
3049static bool RetCC_X86_32_C(unsigned ValNo, MVT ValVT,
3050                           MVT LocVT, CCValAssign::LocInfo LocInfo,
3051                           ISD::ArgFlagsTy ArgFlags, CCState &State) {
3052
3053  if (ArgFlags.isInReg()) {
3054    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()) {
3055      if (LocVT == MVT::f32 ||
3056          LocVT == MVT::f64) {
3057        static const MCPhysReg RegList1[] = {
3058          X86::XMM0, X86::XMM1, X86::XMM2
3059        };
3060        if (unsigned Reg = State.AllocateReg(RegList1)) {
3061          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3062          return false;
3063        }
3064      }
3065    }
3066  }
3067
3068  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasX87()) {
3069    if (LocVT == MVT::f32 ||
3070        LocVT == MVT::f64) {
3071      static const MCPhysReg RegList2[] = {
3072        X86::FP0, X86::FP1
3073      };
3074      if (unsigned Reg = State.AllocateReg(RegList2)) {
3075        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3076        return false;
3077      }
3078    }
3079  }
3080
3081  if (!static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasX87()) {
3082    if (LocVT == MVT::f32) {
3083      static const MCPhysReg RegList3[] = {
3084        X86::EAX, X86::EDX, X86::ECX
3085      };
3086      if (unsigned Reg = State.AllocateReg(RegList3)) {
3087        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3088        return false;
3089      }
3090    }
3091  }
3092
3093  if (LocVT == MVT::f16) {
3094    static const MCPhysReg RegList4[] = {
3095      X86::XMM0, X86::XMM1, X86::XMM2
3096    };
3097    if (unsigned Reg = State.AllocateReg(RegList4)) {
3098      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3099      return false;
3100    }
3101  }
3102
3103  if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3104    return false;
3105
3106  return true; // CC didn't match.
3107}
3108
3109
3110static bool RetCC_X86_32_Fast(unsigned ValNo, MVT ValVT,
3111                              MVT LocVT, CCValAssign::LocInfo LocInfo,
3112                              ISD::ArgFlagsTy ArgFlags, CCState &State) {
3113
3114  if (LocVT == MVT::f32) {
3115    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()) {
3116      static const MCPhysReg RegList1[] = {
3117        X86::XMM0, X86::XMM1, X86::XMM2
3118      };
3119      if (unsigned Reg = State.AllocateReg(RegList1)) {
3120        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3121        return false;
3122      }
3123    }
3124  }
3125
3126  if (LocVT == MVT::f64) {
3127    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()) {
3128      static const MCPhysReg RegList2[] = {
3129        X86::XMM0, X86::XMM1, X86::XMM2
3130      };
3131      if (unsigned Reg = State.AllocateReg(RegList2)) {
3132        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3133        return false;
3134      }
3135    }
3136  }
3137
3138  if (LocVT == MVT::i8) {
3139    static const MCPhysReg RegList3[] = {
3140      X86::AL, X86::DL, X86::CL
3141    };
3142    if (unsigned Reg = State.AllocateReg(RegList3)) {
3143      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3144      return false;
3145    }
3146  }
3147
3148  if (LocVT == MVT::i16) {
3149    static const MCPhysReg RegList4[] = {
3150      X86::AX, X86::DX, X86::CX
3151    };
3152    if (unsigned Reg = State.AllocateReg(RegList4)) {
3153      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3154      return false;
3155    }
3156  }
3157
3158  if (LocVT == MVT::i32) {
3159    static const MCPhysReg RegList5[] = {
3160      X86::EAX, X86::EDX, X86::ECX
3161    };
3162    if (unsigned Reg = State.AllocateReg(RegList5)) {
3163      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3164      return false;
3165    }
3166  }
3167
3168  if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3169    return false;
3170
3171  return true; // CC didn't match.
3172}
3173
3174
3175static bool RetCC_X86_32_HiPE(unsigned ValNo, MVT ValVT,
3176                              MVT LocVT, CCValAssign::LocInfo LocInfo,
3177                              ISD::ArgFlagsTy ArgFlags, CCState &State) {
3178
3179  if (LocVT == MVT::i8 ||
3180      LocVT == MVT::i16) {
3181    LocVT = MVT::i32;
3182    if (ArgFlags.isSExt())
3183      LocInfo = CCValAssign::SExt;
3184    else if (ArgFlags.isZExt())
3185      LocInfo = CCValAssign::ZExt;
3186    else
3187      LocInfo = CCValAssign::AExt;
3188  }
3189
3190  if (LocVT == MVT::i32) {
3191    static const MCPhysReg RegList1[] = {
3192      X86::ESI, X86::EBP, X86::EAX, X86::EDX
3193    };
3194    if (unsigned Reg = State.AllocateReg(RegList1)) {
3195      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3196      return false;
3197    }
3198  }
3199
3200  return true; // CC didn't match.
3201}
3202
3203
3204static bool RetCC_X86_32_RegCall(unsigned ValNo, MVT ValVT,
3205                                 MVT LocVT, CCValAssign::LocInfo LocInfo,
3206                                 ISD::ArgFlagsTy ArgFlags, CCState &State) {
3207
3208  if (LocVT == MVT::i1 ||
3209      LocVT == MVT::v1i1 ||
3210      LocVT == MVT::v8i1) {
3211    LocVT = MVT::i8;
3212    if (ArgFlags.isSExt())
3213      LocInfo = CCValAssign::SExt;
3214    else if (ArgFlags.isZExt())
3215      LocInfo = CCValAssign::ZExt;
3216    else
3217      LocInfo = CCValAssign::AExt;
3218  }
3219
3220  if (LocVT == MVT::v16i1) {
3221    LocVT = MVT::i16;
3222    if (ArgFlags.isSExt())
3223      LocInfo = CCValAssign::SExt;
3224    else if (ArgFlags.isZExt())
3225      LocInfo = CCValAssign::ZExt;
3226    else
3227      LocInfo = CCValAssign::AExt;
3228  }
3229
3230  if (LocVT == MVT::v32i1) {
3231    LocVT = MVT::i32;
3232    if (ArgFlags.isSExt())
3233      LocInfo = CCValAssign::SExt;
3234    else if (ArgFlags.isZExt())
3235      LocInfo = CCValAssign::ZExt;
3236    else
3237      LocInfo = CCValAssign::AExt;
3238  }
3239
3240  if (LocVT == MVT::i8) {
3241    static const MCPhysReg RegList1[] = {
3242      X86::AL, X86::CL, X86::DL, X86::DIL, X86::SIL
3243    };
3244    if (unsigned Reg = State.AllocateReg(RegList1)) {
3245      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3246      return false;
3247    }
3248  }
3249
3250  if (LocVT == MVT::i16) {
3251    static const MCPhysReg RegList2[] = {
3252      X86::AX, X86::CX, X86::DX, X86::DI, X86::SI
3253    };
3254    if (unsigned Reg = State.AllocateReg(RegList2)) {
3255      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3256      return false;
3257    }
3258  }
3259
3260  if (LocVT == MVT::i32) {
3261    static const MCPhysReg RegList3[] = {
3262      X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI
3263    };
3264    if (unsigned Reg = State.AllocateReg(RegList3)) {
3265      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3266      return false;
3267    }
3268  }
3269
3270  if (LocVT == MVT::i64) {
3271    if (unsigned Reg = State.AllocateReg(X86::RAX)) {
3272      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3273      return false;
3274    }
3275  }
3276
3277  if (LocVT == MVT::v64i1) {
3278    LocVT = MVT::i64;
3279    if (ArgFlags.isSExt())
3280      LocInfo = CCValAssign::SExt;
3281    else if (ArgFlags.isZExt())
3282      LocInfo = CCValAssign::ZExt;
3283    else
3284      LocInfo = CCValAssign::AExt;
3285  }
3286
3287  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
3288    if (LocVT == MVT::i64) {
3289      if (unsigned Reg = State.AllocateReg(X86::RAX)) {
3290        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3291        return false;
3292      }
3293    }
3294  }
3295
3296  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()) {
3297    if (LocVT == MVT::i64) {
3298      if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3299        return false;
3300    }
3301  }
3302
3303  if (LocVT == MVT::f80) {
3304    static const MCPhysReg RegList4[] = {
3305      X86::FP0, X86::FP1
3306    };
3307    if (unsigned Reg = State.AllocateReg(RegList4)) {
3308      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3309      return false;
3310    }
3311  }
3312
3313  if (LocVT == MVT::f32 ||
3314      LocVT == MVT::f64 ||
3315      LocVT == MVT::f128) {
3316    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
3317      static const MCPhysReg RegList5[] = {
3318        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3319      };
3320      if (unsigned Reg = State.AllocateReg(RegList5)) {
3321        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3322        return false;
3323      }
3324    }
3325  }
3326
3327  if (LocVT == MVT::v16i8 ||
3328      LocVT == MVT::v8i16 ||
3329      LocVT == MVT::v4i32 ||
3330      LocVT == MVT::v2i64 ||
3331      LocVT == MVT::v4f32 ||
3332      LocVT == MVT::v2f64) {
3333    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
3334      static const MCPhysReg RegList6[] = {
3335        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3336      };
3337      if (unsigned Reg = State.AllocateReg(RegList6)) {
3338        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3339        return false;
3340      }
3341    }
3342  }
3343
3344  if (LocVT == MVT::v32i8 ||
3345      LocVT == MVT::v16i16 ||
3346      LocVT == MVT::v8i32 ||
3347      LocVT == MVT::v4i64 ||
3348      LocVT == MVT::v8f32 ||
3349      LocVT == MVT::v4f64) {
3350    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
3351      static const MCPhysReg RegList7[] = {
3352        X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7
3353      };
3354      if (unsigned Reg = State.AllocateReg(RegList7)) {
3355        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3356        return false;
3357      }
3358    }
3359  }
3360
3361  if (LocVT == MVT::v64i8 ||
3362      LocVT == MVT::v32i16 ||
3363      LocVT == MVT::v16i32 ||
3364      LocVT == MVT::v8i64 ||
3365      LocVT == MVT::v16f32 ||
3366      LocVT == MVT::v8f64) {
3367    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) {
3368      static const MCPhysReg RegList8[] = {
3369        X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7
3370      };
3371      if (unsigned Reg = State.AllocateReg(RegList8)) {
3372        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3373        return false;
3374      }
3375    }
3376  }
3377
3378  return true; // CC didn't match.
3379}
3380
3381
3382static bool RetCC_X86_32_VectorCall(unsigned ValNo, MVT ValVT,
3383                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
3384                                    ISD::ArgFlagsTy ArgFlags, CCState &State) {
3385
3386  if (LocVT == MVT::f32 ||
3387      LocVT == MVT::f64 ||
3388      LocVT == MVT::f128) {
3389    static const MCPhysReg RegList1[] = {
3390      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
3391    };
3392    if (unsigned Reg = State.AllocateReg(RegList1)) {
3393      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3394      return false;
3395    }
3396  }
3397
3398  if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3399    return false;
3400
3401  return true; // CC didn't match.
3402}
3403
3404
3405static bool RetCC_X86_64(unsigned ValNo, MVT ValVT,
3406                         MVT LocVT, CCValAssign::LocInfo LocInfo,
3407                         ISD::ArgFlagsTy ArgFlags, CCState &State) {
3408
3409  if (State.getCallingConv() == CallingConv::HiPE) {
3410    if (!RetCC_X86_64_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3411      return false;
3412  }
3413
3414  if (State.getCallingConv() == CallingConv::WebKit_JS) {
3415    if (!RetCC_X86_64_WebKit_JS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3416      return false;
3417  }
3418
3419  if (State.getCallingConv() == CallingConv::AnyReg) {
3420    if (!RetCC_X86_64_AnyReg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3421      return false;
3422  }
3423
3424  if (State.getCallingConv() == CallingConv::Swift) {
3425    if (!RetCC_X86_64_Swift(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3426      return false;
3427  }
3428
3429  if (State.getCallingConv() == CallingConv::SwiftTail) {
3430    if (!RetCC_X86_64_Swift(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3431      return false;
3432  }
3433
3434  if (State.getCallingConv() == CallingConv::Win64) {
3435    if (!RetCC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3436      return false;
3437  }
3438
3439  if (State.getCallingConv() == CallingConv::X86_64_SysV) {
3440    if (!RetCC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3441      return false;
3442  }
3443
3444  if (State.getCallingConv() == CallingConv::X86_VectorCall) {
3445    if (!RetCC_X86_64_Vectorcall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3446      return false;
3447  }
3448
3449  if (State.getCallingConv() == CallingConv::HHVM) {
3450    if (!RetCC_X86_64_HHVM(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3451      return false;
3452  }
3453
3454  if (State.getCallingConv() == CallingConv::X86_RegCall) {
3455    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) {
3456      if (!RetCC_X86_Win64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3457        return false;
3458    }
3459  }
3460
3461  if (State.getCallingConv() == CallingConv::X86_RegCall) {
3462    if (!RetCC_X86_SysV64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3463      return false;
3464  }
3465
3466  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) {
3467    if (!RetCC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3468      return false;
3469  }
3470
3471  if (!RetCC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3472    return false;
3473
3474  return true; // CC didn't match.
3475}
3476
3477
3478static bool RetCC_X86_64_AnyReg(unsigned ValNo, MVT ValVT,
3479                                MVT LocVT, CCValAssign::LocInfo LocInfo,
3480                                ISD::ArgFlagsTy ArgFlags, CCState &State) {
3481
3482  if (CC_X86_AnyReg_Error(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3483    return false;
3484
3485  return true; // CC didn't match.
3486}
3487
3488
3489static bool RetCC_X86_64_C(unsigned ValNo, MVT ValVT,
3490                           MVT LocVT, CCValAssign::LocInfo LocInfo,
3491                           ISD::ArgFlagsTy ArgFlags, CCState &State) {
3492
3493  if (LocVT == MVT::f16) {
3494    static const MCPhysReg RegList1[] = {
3495      X86::XMM0, X86::XMM1
3496    };
3497    if (unsigned Reg = State.AllocateReg(RegList1)) {
3498      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3499      return false;
3500    }
3501  }
3502
3503  if (LocVT == MVT::f32) {
3504    static const MCPhysReg RegList2[] = {
3505      X86::XMM0, X86::XMM1
3506    };
3507    if (unsigned Reg = State.AllocateReg(RegList2)) {
3508      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3509      return false;
3510    }
3511  }
3512
3513  if (LocVT == MVT::f64) {
3514    static const MCPhysReg RegList3[] = {
3515      X86::XMM0, X86::XMM1
3516    };
3517    if (unsigned Reg = State.AllocateReg(RegList3)) {
3518      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3519      return false;
3520    }
3521  }
3522
3523  if (LocVT == MVT::f128) {
3524    static const MCPhysReg RegList4[] = {
3525      X86::XMM0, X86::XMM1
3526    };
3527    if (unsigned Reg = State.AllocateReg(RegList4)) {
3528      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3529      return false;
3530    }
3531  }
3532
3533  if (LocVT == MVT::x86mmx) {
3534    static const MCPhysReg RegList5[] = {
3535      X86::XMM0, X86::XMM1
3536    };
3537    if (unsigned Reg = State.AllocateReg(RegList5)) {
3538      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3539      return false;
3540    }
3541  }
3542
3543  if (ArgFlags.isPointer()) {
3544    if (CC_X86_64_Pointer(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3545      return false;
3546  }
3547
3548  if (ArgFlags.isSwiftError()) {
3549    if (LocVT == MVT::i64) {
3550      if (unsigned Reg = State.AllocateReg(X86::R12)) {
3551        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3552        return false;
3553      }
3554    }
3555  }
3556
3557  if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3558    return false;
3559
3560  return true; // CC didn't match.
3561}
3562
3563
3564static bool RetCC_X86_64_HHVM(unsigned ValNo, MVT ValVT,
3565                              MVT LocVT, CCValAssign::LocInfo LocInfo,
3566                              ISD::ArgFlagsTy ArgFlags, CCState &State) {
3567
3568  if (LocVT == MVT::i8 ||
3569      LocVT == MVT::i16 ||
3570      LocVT == MVT::i32) {
3571    LocVT = MVT::i64;
3572    if (ArgFlags.isSExt())
3573      LocInfo = CCValAssign::SExt;
3574    else if (ArgFlags.isZExt())
3575      LocInfo = CCValAssign::ZExt;
3576    else
3577      LocInfo = CCValAssign::AExt;
3578  }
3579
3580  if (LocVT == MVT::i64) {
3581    static const MCPhysReg RegList1[] = {
3582      X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9, X86::RAX, X86::R10, X86::R11, X86::R13, X86::R14, X86::R15
3583    };
3584    if (unsigned Reg = State.AllocateReg(RegList1)) {
3585      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3586      return false;
3587    }
3588  }
3589
3590  return true; // CC didn't match.
3591}
3592
3593
3594static bool RetCC_X86_64_HiPE(unsigned ValNo, MVT ValVT,
3595                              MVT LocVT, CCValAssign::LocInfo LocInfo,
3596                              ISD::ArgFlagsTy ArgFlags, CCState &State) {
3597
3598  if (LocVT == MVT::i8 ||
3599      LocVT == MVT::i16 ||
3600      LocVT == MVT::i32) {
3601    LocVT = MVT::i64;
3602    if (ArgFlags.isSExt())
3603      LocInfo = CCValAssign::SExt;
3604    else if (ArgFlags.isZExt())
3605      LocInfo = CCValAssign::ZExt;
3606    else
3607      LocInfo = CCValAssign::AExt;
3608  }
3609
3610  if (LocVT == MVT::i64) {
3611    static const MCPhysReg RegList1[] = {
3612      X86::R15, X86::RBP, X86::RAX, X86::RDX
3613    };
3614    if (unsigned Reg = State.AllocateReg(RegList1)) {
3615      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3616      return false;
3617    }
3618  }
3619
3620  return true; // CC didn't match.
3621}
3622
3623
3624static bool RetCC_X86_64_Swift(unsigned ValNo, MVT ValVT,
3625                               MVT LocVT, CCValAssign::LocInfo LocInfo,
3626                               ISD::ArgFlagsTy ArgFlags, CCState &State) {
3627
3628  if (ArgFlags.isSwiftError()) {
3629    if (LocVT == MVT::i64) {
3630      if (unsigned Reg = State.AllocateReg(X86::R12)) {
3631        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3632        return false;
3633      }
3634    }
3635  }
3636
3637  if (LocVT == MVT::v1i1) {
3638    LocVT = MVT::i8;
3639    if (ArgFlags.isSExt())
3640      LocInfo = CCValAssign::SExt;
3641    else if (ArgFlags.isZExt())
3642      LocInfo = CCValAssign::ZExt;
3643    else
3644      LocInfo = CCValAssign::AExt;
3645  }
3646
3647  if (LocVT == MVT::i1) {
3648    LocVT = MVT::i8;
3649    if (ArgFlags.isSExt())
3650      LocInfo = CCValAssign::SExt;
3651    else if (ArgFlags.isZExt())
3652      LocInfo = CCValAssign::ZExt;
3653    else
3654      LocInfo = CCValAssign::AExt;
3655  }
3656
3657  if (LocVT == MVT::i8) {
3658    static const MCPhysReg RegList1[] = {
3659      X86::AL, X86::DL, X86::CL, X86::R8B
3660    };
3661    if (unsigned Reg = State.AllocateReg(RegList1)) {
3662      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3663      return false;
3664    }
3665  }
3666
3667  if (LocVT == MVT::i16) {
3668    static const MCPhysReg RegList2[] = {
3669      X86::AX, X86::DX, X86::CX, X86::R8W
3670    };
3671    if (unsigned Reg = State.AllocateReg(RegList2)) {
3672      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3673      return false;
3674    }
3675  }
3676
3677  if (LocVT == MVT::i32) {
3678    static const MCPhysReg RegList3[] = {
3679      X86::EAX, X86::EDX, X86::ECX, X86::R8D
3680    };
3681    if (unsigned Reg = State.AllocateReg(RegList3)) {
3682      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3683      return false;
3684    }
3685  }
3686
3687  if (LocVT == MVT::i64) {
3688    static const MCPhysReg RegList4[] = {
3689      X86::RAX, X86::RDX, X86::RCX, X86::R8
3690    };
3691    if (unsigned Reg = State.AllocateReg(RegList4)) {
3692      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3693      return false;
3694    }
3695  }
3696
3697  if (LocVT == MVT::f32) {
3698    static const MCPhysReg RegList5[] = {
3699      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
3700    };
3701    if (unsigned Reg = State.AllocateReg(RegList5)) {
3702      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3703      return false;
3704    }
3705  }
3706
3707  if (LocVT == MVT::f64) {
3708    static const MCPhysReg RegList6[] = {
3709      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
3710    };
3711    if (unsigned Reg = State.AllocateReg(RegList6)) {
3712      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3713      return false;
3714    }
3715  }
3716
3717  if (LocVT == MVT::f128) {
3718    static const MCPhysReg RegList7[] = {
3719      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
3720    };
3721    if (unsigned Reg = State.AllocateReg(RegList7)) {
3722      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3723      return false;
3724    }
3725  }
3726
3727  if (LocVT == MVT::x86mmx) {
3728    static const MCPhysReg RegList8[] = {
3729      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
3730    };
3731    if (unsigned Reg = State.AllocateReg(RegList8)) {
3732      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3733      return false;
3734    }
3735  }
3736
3737  if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3738    return false;
3739
3740  return true; // CC didn't match.
3741}
3742
3743
3744static bool RetCC_X86_64_Vectorcall(unsigned ValNo, MVT ValVT,
3745                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
3746                                    ISD::ArgFlagsTy ArgFlags, CCState &State) {
3747
3748  if (LocVT == MVT::f32 ||
3749      LocVT == MVT::f64 ||
3750      LocVT == MVT::f128) {
3751    static const MCPhysReg RegList1[] = {
3752      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
3753    };
3754    if (unsigned Reg = State.AllocateReg(RegList1)) {
3755      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3756      return false;
3757    }
3758  }
3759
3760  if (!RetCC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3761    return false;
3762
3763  return true; // CC didn't match.
3764}
3765
3766
3767static bool RetCC_X86_64_WebKit_JS(unsigned ValNo, MVT ValVT,
3768                                   MVT LocVT, CCValAssign::LocInfo LocInfo,
3769                                   ISD::ArgFlagsTy ArgFlags, CCState &State) {
3770
3771  if (LocVT == MVT::i8 ||
3772      LocVT == MVT::i16 ||
3773      LocVT == MVT::i32) {
3774    LocVT = MVT::i64;
3775    if (ArgFlags.isSExt())
3776      LocInfo = CCValAssign::SExt;
3777    else if (ArgFlags.isZExt())
3778      LocInfo = CCValAssign::ZExt;
3779    else
3780      LocInfo = CCValAssign::AExt;
3781  }
3782
3783  if (LocVT == MVT::i64) {
3784    if (unsigned Reg = State.AllocateReg(X86::RAX)) {
3785      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3786      return false;
3787    }
3788  }
3789
3790  return true; // CC didn't match.
3791}
3792
3793
3794static bool RetCC_X86_SysV64_RegCall(unsigned ValNo, MVT ValVT,
3795                                     MVT LocVT, CCValAssign::LocInfo LocInfo,
3796                                     ISD::ArgFlagsTy ArgFlags, CCState &State) {
3797
3798  if (LocVT == MVT::i1 ||
3799      LocVT == MVT::v1i1 ||
3800      LocVT == MVT::v8i1) {
3801    LocVT = MVT::i8;
3802    if (ArgFlags.isSExt())
3803      LocInfo = CCValAssign::SExt;
3804    else if (ArgFlags.isZExt())
3805      LocInfo = CCValAssign::ZExt;
3806    else
3807      LocInfo = CCValAssign::AExt;
3808  }
3809
3810  if (LocVT == MVT::v16i1) {
3811    LocVT = MVT::i16;
3812    if (ArgFlags.isSExt())
3813      LocInfo = CCValAssign::SExt;
3814    else if (ArgFlags.isZExt())
3815      LocInfo = CCValAssign::ZExt;
3816    else
3817      LocInfo = CCValAssign::AExt;
3818  }
3819
3820  if (LocVT == MVT::v32i1) {
3821    LocVT = MVT::i32;
3822    if (ArgFlags.isSExt())
3823      LocInfo = CCValAssign::SExt;
3824    else if (ArgFlags.isZExt())
3825      LocInfo = CCValAssign::ZExt;
3826    else
3827      LocInfo = CCValAssign::AExt;
3828  }
3829
3830  if (LocVT == MVT::i8) {
3831    static const MCPhysReg RegList1[] = {
3832      X86::AL, X86::CL, X86::DL, X86::DIL, X86::SIL, X86::R8B, X86::R9B, X86::R12B, X86::R13B, X86::R14B, X86::R15B
3833    };
3834    if (unsigned Reg = State.AllocateReg(RegList1)) {
3835      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3836      return false;
3837    }
3838  }
3839
3840  if (LocVT == MVT::i16) {
3841    static const MCPhysReg RegList2[] = {
3842      X86::AX, X86::CX, X86::DX, X86::DI, X86::SI, X86::R8W, X86::R9W, X86::R12W, X86::R13W, X86::R14W, X86::R15W
3843    };
3844    if (unsigned Reg = State.AllocateReg(RegList2)) {
3845      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3846      return false;
3847    }
3848  }
3849
3850  if (LocVT == MVT::i32) {
3851    static const MCPhysReg RegList3[] = {
3852      X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R12D, X86::R13D, X86::R14D, X86::R15D
3853    };
3854    if (unsigned Reg = State.AllocateReg(RegList3)) {
3855      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3856      return false;
3857    }
3858  }
3859
3860  if (LocVT == MVT::i64) {
3861    static const MCPhysReg RegList4[] = {
3862      X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R12, X86::R13, X86::R14, X86::R15
3863    };
3864    if (unsigned Reg = State.AllocateReg(RegList4)) {
3865      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3866      return false;
3867    }
3868  }
3869
3870  if (LocVT == MVT::v64i1) {
3871    LocVT = MVT::i64;
3872    if (ArgFlags.isSExt())
3873      LocInfo = CCValAssign::SExt;
3874    else if (ArgFlags.isZExt())
3875      LocInfo = CCValAssign::ZExt;
3876    else
3877      LocInfo = CCValAssign::AExt;
3878  }
3879
3880  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
3881    if (LocVT == MVT::i64) {
3882      static const MCPhysReg RegList5[] = {
3883        X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R12, X86::R13, X86::R14, X86::R15
3884      };
3885      if (unsigned Reg = State.AllocateReg(RegList5)) {
3886        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3887        return false;
3888      }
3889    }
3890  }
3891
3892  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()) {
3893    if (LocVT == MVT::i64) {
3894      if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3895        return false;
3896    }
3897  }
3898
3899  if (LocVT == MVT::f80) {
3900    static const MCPhysReg RegList6[] = {
3901      X86::FP0, X86::FP1
3902    };
3903    if (unsigned Reg = State.AllocateReg(RegList6)) {
3904      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3905      return false;
3906    }
3907  }
3908
3909  if (LocVT == MVT::f32 ||
3910      LocVT == MVT::f64 ||
3911      LocVT == MVT::f128) {
3912    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
3913      static const MCPhysReg RegList7[] = {
3914        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
3915      };
3916      if (unsigned Reg = State.AllocateReg(RegList7)) {
3917        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3918        return false;
3919      }
3920    }
3921  }
3922
3923  if (LocVT == MVT::v16i8 ||
3924      LocVT == MVT::v8i16 ||
3925      LocVT == MVT::v4i32 ||
3926      LocVT == MVT::v2i64 ||
3927      LocVT == MVT::v4f32 ||
3928      LocVT == MVT::v2f64) {
3929    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
3930      static const MCPhysReg RegList8[] = {
3931        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
3932      };
3933      if (unsigned Reg = State.AllocateReg(RegList8)) {
3934        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3935        return false;
3936      }
3937    }
3938  }
3939
3940  if (LocVT == MVT::v32i8 ||
3941      LocVT == MVT::v16i16 ||
3942      LocVT == MVT::v8i32 ||
3943      LocVT == MVT::v4i64 ||
3944      LocVT == MVT::v8f32 ||
3945      LocVT == MVT::v4f64) {
3946    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
3947      static const MCPhysReg RegList9[] = {
3948        X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15
3949      };
3950      if (unsigned Reg = State.AllocateReg(RegList9)) {
3951        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3952        return false;
3953      }
3954    }
3955  }
3956
3957  if (LocVT == MVT::v64i8 ||
3958      LocVT == MVT::v32i16 ||
3959      LocVT == MVT::v16i32 ||
3960      LocVT == MVT::v8i64 ||
3961      LocVT == MVT::v16f32 ||
3962      LocVT == MVT::v8f64) {
3963    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) {
3964      static const MCPhysReg RegList10[] = {
3965        X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15
3966      };
3967      if (unsigned Reg = State.AllocateReg(RegList10)) {
3968        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3969        return false;
3970      }
3971    }
3972  }
3973
3974  return true; // CC didn't match.
3975}
3976
3977
3978static bool RetCC_X86_Win64_C(unsigned ValNo, MVT ValVT,
3979                              MVT LocVT, CCValAssign::LocInfo LocInfo,
3980                              ISD::ArgFlagsTy ArgFlags, CCState &State) {
3981
3982  if (LocVT == MVT::x86mmx) {
3983    LocVT = MVT::i64;
3984    LocInfo = CCValAssign::BCvt;
3985  }
3986
3987  if (LocVT == MVT::f32) {
3988    if (!static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
3989      LocVT = MVT::i32;
3990      LocInfo = CCValAssign::BCvt;
3991    }
3992  }
3993
3994  if (LocVT == MVT::f64) {
3995    if (!static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
3996      LocVT = MVT::i64;
3997      LocInfo = CCValAssign::BCvt;
3998    }
3999  }
4000
4001  if (!RetCC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
4002    return false;
4003
4004  return true; // CC didn't match.
4005}
4006
4007
4008static bool RetCC_X86_Win64_RegCall(unsigned ValNo, MVT ValVT,
4009                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
4010                                    ISD::ArgFlagsTy ArgFlags, CCState &State) {
4011
4012  if (LocVT == MVT::i1 ||
4013      LocVT == MVT::v1i1 ||
4014      LocVT == MVT::v8i1) {
4015    LocVT = MVT::i8;
4016    if (ArgFlags.isSExt())
4017      LocInfo = CCValAssign::SExt;
4018    else if (ArgFlags.isZExt())
4019      LocInfo = CCValAssign::ZExt;
4020    else
4021      LocInfo = CCValAssign::AExt;
4022  }
4023
4024  if (LocVT == MVT::v16i1) {
4025    LocVT = MVT::i16;
4026    if (ArgFlags.isSExt())
4027      LocInfo = CCValAssign::SExt;
4028    else if (ArgFlags.isZExt())
4029      LocInfo = CCValAssign::ZExt;
4030    else
4031      LocInfo = CCValAssign::AExt;
4032  }
4033
4034  if (LocVT == MVT::v32i1) {
4035    LocVT = MVT::i32;
4036    if (ArgFlags.isSExt())
4037      LocInfo = CCValAssign::SExt;
4038    else if (ArgFlags.isZExt())
4039      LocInfo = CCValAssign::ZExt;
4040    else
4041      LocInfo = CCValAssign::AExt;
4042  }
4043
4044  if (LocVT == MVT::i8) {
4045    static const MCPhysReg RegList1[] = {
4046      X86::AL, X86::CL, X86::DL, X86::DIL, X86::SIL, X86::R8B, X86::R9B, X86::R10B, X86::R11B, X86::R12B, X86::R14B, X86::R15B
4047    };
4048    if (unsigned Reg = State.AllocateReg(RegList1)) {
4049      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
4050      return false;
4051    }
4052  }
4053
4054  if (LocVT == MVT::i16) {
4055    static const MCPhysReg RegList2[] = {
4056      X86::AX, X86::CX, X86::DX, X86::DI, X86::SI, X86::R8W, X86::R9W, X86::R10W, X86::R11W, X86::R12W, X86::R14W, X86::R15W
4057    };
4058    if (unsigned Reg = State.AllocateReg(RegList2)) {
4059      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
4060      return false;
4061    }
4062  }
4063
4064  if (LocVT == MVT::i32) {
4065    static const MCPhysReg RegList3[] = {
4066      X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R12D, X86::R14D, X86::R15D
4067    };
4068    if (unsigned Reg = State.AllocateReg(RegList3)) {
4069      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
4070      return false;
4071    }
4072  }
4073
4074  if (LocVT == MVT::i64) {
4075    static const MCPhysReg RegList4[] = {
4076      X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R14, X86::R15
4077    };
4078    if (unsigned Reg = State.AllocateReg(RegList4)) {
4079      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
4080      return false;
4081    }
4082  }
4083
4084  if (LocVT == MVT::v64i1) {
4085    LocVT = MVT::i64;
4086    if (ArgFlags.isSExt())
4087      LocInfo = CCValAssign::SExt;
4088    else if (ArgFlags.isZExt())
4089      LocInfo = CCValAssign::ZExt;
4090    else
4091      LocInfo = CCValAssign::AExt;
4092  }
4093
4094  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
4095    if (LocVT == MVT::i64) {
4096      static const MCPhysReg RegList5[] = {
4097        X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R14, X86::R15
4098      };
4099      if (unsigned Reg = State.AllocateReg(RegList5)) {
4100        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
4101        return false;
4102      }
4103    }
4104  }
4105
4106  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()) {
4107    if (LocVT == MVT::i64) {
4108      if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
4109        return false;
4110    }
4111  }
4112
4113  if (LocVT == MVT::f80) {
4114    static const MCPhysReg RegList6[] = {
4115      X86::FP0, X86::FP1
4116    };
4117    if (unsigned Reg = State.AllocateReg(RegList6)) {
4118      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
4119      return false;
4120    }
4121  }
4122
4123  if (LocVT == MVT::f32 ||
4124      LocVT == MVT::f64 ||
4125      LocVT == MVT::f128) {
4126    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
4127      static const MCPhysReg RegList7[] = {
4128        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
4129      };
4130      if (unsigned Reg = State.AllocateReg(RegList7)) {
4131        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
4132        return false;
4133      }
4134    }
4135  }
4136
4137  if (LocVT == MVT::v16i8 ||
4138      LocVT == MVT::v8i16 ||
4139      LocVT == MVT::v4i32 ||
4140      LocVT == MVT::v2i64 ||
4141      LocVT == MVT::v4f32 ||
4142      LocVT == MVT::v2f64) {
4143    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
4144      static const MCPhysReg RegList8[] = {
4145        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
4146      };
4147      if (unsigned Reg = State.AllocateReg(RegList8)) {
4148        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
4149        return false;
4150      }
4151    }
4152  }
4153
4154  if (LocVT == MVT::v32i8 ||
4155      LocVT == MVT::v16i16 ||
4156      LocVT == MVT::v8i32 ||
4157      LocVT == MVT::v4i64 ||
4158      LocVT == MVT::v8f32 ||
4159      LocVT == MVT::v4f64) {
4160    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
4161      static const MCPhysReg RegList9[] = {
4162        X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15
4163      };
4164      if (unsigned Reg = State.AllocateReg(RegList9)) {
4165        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
4166        return false;
4167      }
4168    }
4169  }
4170
4171  if (LocVT == MVT::v64i8 ||
4172      LocVT == MVT::v32i16 ||
4173      LocVT == MVT::v16i32 ||
4174      LocVT == MVT::v8i64 ||
4175      LocVT == MVT::v16f32 ||
4176      LocVT == MVT::v8f64) {
4177    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) {
4178      static const MCPhysReg RegList10[] = {
4179        X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15
4180      };
4181      if (unsigned Reg = State.AllocateReg(RegList10)) {
4182        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
4183        return false;
4184      }
4185    }
4186  }
4187
4188  return true; // CC didn't match.
4189}
4190
4191#else
4192
4193const MCRegister CC_Intel_OCL_BI_ArgRegs[] = { X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::K1, X86::R8, X86::R8D, X86::R9, X86::R9D, X86::RCX, X86::RDI, X86::RDX, X86::RSI, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3 };
4194const MCRegister CC_X86_ArgRegs[] = { 0 };
4195const MCRegister CC_X86_32_ArgRegs[] = { 0 };
4196const MCRegister CC_X86_32_C_ArgRegs[] = { X86::EAX, X86::ECX, X86::EDX };
4197const MCRegister CC_X86_32_Common_ArgRegs[] = { X86::MM0, X86::MM1, X86::MM2, X86::XMM0, X86::XMM1, X86::XMM2 };
4198const MCRegister CC_X86_32_FastCC_ArgRegs[] = { X86::EAX, X86::ECX, X86::EDX, X86::XMM0, X86::XMM1, X86::XMM2 };
4199const MCRegister CC_X86_32_FastCall_ArgRegs[] = { X86::CL, X86::CX, X86::DL, X86::DX, X86::EAX, X86::ECX, X86::EDX };
4200const MCRegister CC_X86_32_GHC_ArgRegs[] = { X86::EBP, X86::EBX, X86::EDI, X86::ESI };
4201const MCRegister CC_X86_32_HiPE_ArgRegs[] = { X86::EAX, X86::EBP, X86::ECX, X86::EDX, X86::ESI };
4202const MCRegister CC_X86_32_MCU_ArgRegs[] = { 0 };
4203const MCRegister CC_X86_32_RegCall_ArgRegs[] = { X86::EAX, X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::FP0, X86::RAX, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7 };
4204const MCRegister CC_X86_32_ThisCall_ArgRegs[] = { 0 };
4205const MCRegister CC_X86_32_ThisCall_Common_ArgRegs[] = { X86::ECX };
4206const MCRegister CC_X86_32_ThisCall_Mingw_ArgRegs[] = { 0 };
4207const MCRegister CC_X86_32_ThisCall_Win_ArgRegs[] = { 0 };
4208const MCRegister CC_X86_32_Vector_Common_ArgRegs[] = { 0 };
4209const MCRegister CC_X86_32_Vector_Darwin_ArgRegs[] = { X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3 };
4210const MCRegister CC_X86_32_Vector_Standard_ArgRegs[] = { X86::XMM0, X86::XMM1, X86::XMM2, X86::YMM0, X86::YMM1, X86::YMM2, X86::ZMM0, X86::ZMM1, X86::ZMM2 };
4211const MCRegister CC_X86_64_ArgRegs[] = { 0 };
4212const MCRegister CC_X86_64_AnyReg_ArgRegs[] = { 0 };
4213const MCRegister CC_X86_64_C_ArgRegs[] = { X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::R10, X86::R10D, X86::R8, X86::R8D, X86::R9, X86::R9D, X86::RAX, X86::RCX, X86::RDI, X86::RDX, X86::RSI, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7 };
4214const MCRegister CC_X86_64_GHC_ArgRegs[] = { X86::R12, X86::R13, X86::R14, X86::R15, X86::R8, X86::R9, X86::RBP, X86::RBX, X86::RDI, X86::RSI, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6 };
4215const MCRegister CC_X86_64_HHVM_ArgRegs[] = { X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::R8, X86::R9, X86::RAX, X86::RBP, X86::RBX, X86::RCX, X86::RDI, X86::RDX, X86::RSI };
4216const MCRegister CC_X86_64_HHVM_C_ArgRegs[] = { X86::RBP };
4217const MCRegister CC_X86_64_HiPE_ArgRegs[] = { X86::R15, X86::R8, X86::RBP, X86::RCX, X86::RDX, X86::RSI };
4218const MCRegister CC_X86_64_WebKit_JS_ArgRegs[] = { X86::EAX, X86::RAX };
4219const MCRegister CC_X86_SysV64_RegCall_ArgRegs[] = { X86::EAX, X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::FP0, X86::R12, X86::R12D, X86::R13, X86::R13D, X86::R14, X86::R14D, X86::R15, X86::R15D, X86::R8, X86::R8D, X86::R9, X86::R9D, X86::RAX, X86::RCX, X86::RDI, X86::RDX, X86::RSI, X86::XMM0, X86::XMM1, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::YMM0, X86::YMM1, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::ZMM0, X86::ZMM1, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9 };
4220const MCRegister CC_X86_Win32_CFGuard_Check_ArgRegs[] = { X86::ECX };
4221const MCRegister CC_X86_Win32_Vector_ArgRegs[] = { 0 };
4222const MCRegister CC_X86_Win32_VectorCall_ArgRegs[] = { 0 };
4223const MCRegister CC_X86_Win64_C_ArgRegs[] = { X86::R10, X86::RAX };
4224const MCRegister CC_X86_Win64_RegCall_ArgRegs[] = { X86::EAX, X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::FP0, X86::R10, X86::R10D, X86::R11, X86::R11D, X86::R12, X86::R12D, X86::R14, X86::R14D, X86::R15, X86::R15D, X86::R8, X86::R8D, X86::R9, X86::R9D, X86::RAX, X86::RCX, X86::RDI, X86::RDX, X86::RSI, X86::XMM0, X86::XMM1, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::YMM0, X86::YMM1, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::ZMM0, X86::ZMM1, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9 };
4225const MCRegister CC_X86_Win64_VectorCall_ArgRegs[] = { 0 };
4226const MCRegister RetCC_Intel_OCL_BI_ArgRegs[] = { X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3 };
4227const MCRegister RetCC_X86_ArgRegs[] = { 0 };
4228const MCRegister RetCC_X86Common_ArgRegs[] = { X86::AL, X86::AX, X86::CL, X86::CX, X86::DL, X86::DX, X86::EAX, X86::ECX, X86::EDX, X86::FP0, X86::FP1, X86::MM0, X86::RAX, X86::RCX, X86::RDX, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3 };
4229const MCRegister RetCC_X86_32_ArgRegs[] = { 0 };
4230const MCRegister RetCC_X86_32_C_ArgRegs[] = { X86::EAX, X86::ECX, X86::EDX, X86::FP0, X86::FP1, X86::XMM0, X86::XMM1, X86::XMM2 };
4231const MCRegister RetCC_X86_32_Fast_ArgRegs[] = { X86::AL, X86::AX, X86::CL, X86::CX, X86::DL, X86::DX, X86::EAX, X86::ECX, X86::EDX, X86::XMM0, X86::XMM1, X86::XMM2 };
4232const MCRegister RetCC_X86_32_HiPE_ArgRegs[] = { X86::EAX, X86::EBP, X86::EDX, X86::ESI };
4233const MCRegister RetCC_X86_32_RegCall_ArgRegs[] = { X86::AL, X86::AX, X86::CL, X86::CX, X86::DI, X86::DIL, X86::DL, X86::DX, X86::EAX, X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::FP0, X86::FP1, X86::RAX, X86::SI, X86::SIL, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7 };
4234const MCRegister RetCC_X86_32_VectorCall_ArgRegs[] = { X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 };
4235const MCRegister RetCC_X86_64_ArgRegs[] = { 0 };
4236const MCRegister RetCC_X86_64_AnyReg_ArgRegs[] = { 0 };
4237const MCRegister RetCC_X86_64_C_ArgRegs[] = { X86::XMM0, X86::XMM1 };
4238const MCRegister RetCC_X86_64_HHVM_ArgRegs[] = { X86::R10, X86::R11, X86::R13, X86::R14, X86::R15, X86::R8, X86::R9, X86::RAX, X86::RBP, X86::RBX, X86::RCX, X86::RDI, X86::RDX, X86::RSI };
4239const MCRegister RetCC_X86_64_HiPE_ArgRegs[] = { X86::R15, X86::RAX, X86::RBP, X86::RDX };
4240const MCRegister RetCC_X86_64_Swift_ArgRegs[] = { X86::AL, X86::AX, X86::CL, X86::CX, X86::DL, X86::DX, X86::EAX, X86::ECX, X86::EDX, X86::R8, X86::R8B, X86::R8D, X86::R8W, X86::RAX, X86::RCX, X86::RDX, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 };
4241const MCRegister RetCC_X86_64_Vectorcall_ArgRegs[] = { X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 };
4242const MCRegister RetCC_X86_64_WebKit_JS_ArgRegs[] = { X86::RAX };
4243const MCRegister RetCC_X86_SysV64_RegCall_ArgRegs[] = { X86::AL, X86::AX, X86::CL, X86::CX, X86::DI, X86::DIL, X86::DL, X86::DX, X86::EAX, X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::FP0, X86::FP1, X86::R12, X86::R12B, X86::R12D, X86::R12W, X86::R13, X86::R13B, X86::R13D, X86::R13W, X86::R14, X86::R14B, X86::R14D, X86::R14W, X86::R15, X86::R15B, X86::R15D, X86::R15W, X86::R8, X86::R8B, X86::R8D, X86::R8W, X86::R9, X86::R9B, X86::R9D, X86::R9W, X86::RAX, X86::RCX, X86::RDI, X86::RDX, X86::RSI, X86::SI, X86::SIL, X86::XMM0, X86::XMM1, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::YMM0, X86::YMM1, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::ZMM0, X86::ZMM1, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9 };
4244const MCRegister RetCC_X86_Win64_C_ArgRegs[] = { 0 };
4245const MCRegister RetCC_X86_Win64_RegCall_ArgRegs[] = { X86::AL, X86::AX, X86::CL, X86::CX, X86::DI, X86::DIL, X86::DL, X86::DX, X86::EAX, X86::ECX, X86::EDI, X86::EDX, X86::ESI, X86::FP0, X86::FP1, X86::R10, X86::R10B, X86::R10D, X86::R10W, X86::R11, X86::R11B, X86::R11D, X86::R11W, X86::R12, X86::R12B, X86::R12D, X86::R12W, X86::R14, X86::R14B, X86::R14D, X86::R14W, X86::R15, X86::R15B, X86::R15D, X86::R15W, X86::R8, X86::R8B, X86::R8D, X86::R8W, X86::R9, X86::R9B, X86::R9D, X86::R9W, X86::RAX, X86::RCX, X86::RDI, X86::RDX, X86::RSI, X86::SI, X86::SIL, X86::XMM0, X86::XMM1, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::YMM0, X86::YMM1, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::ZMM0, X86::ZMM1, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9 };
4246
4247// Registers used by Swift.
4248const MCRegister CC_X86_64_C_Swift_ArgRegs[] = { X86::R12, X86::R13, X86::R14 };
4249const MCRegister CC_X86_Win64_C_Swift_ArgRegs[] = { X86::R12, X86::R13, X86::R14 };
4250const MCRegister RetCC_X86_64_C_Swift_ArgRegs[] = { X86::R12 };
4251const MCRegister RetCC_X86_64_Swift_Swift_ArgRegs[] = { X86::R12 };
4252
4253#endif // CC_REGISTER_LIST
4254